3351 files changed, 422400 insertions, 0 deletions

diff --git a/roms/u-boot/board/AndesTech/adp-ae3xx/Kconfig b/roms/u-boot/board/AndesTech/adp-ae3xx/Kconfig
new file mode 100644
index 000000000..8ec69d611
--- /dev/null
+++ b/roms/u-boot/board/AndesTech/adp-ae3xx/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_ADP_AE3XX
+
+config SYS_CPU
+	default "n1213"
+
+config SYS_BOARD
+	default "adp-ae3xx"
+
+config SYS_VENDOR
+	default "AndesTech"
+
+config SYS_SOC
+	default "ae3xx"
+
+config SYS_CONFIG_NAME
+	default "adp-ae3xx"
+
+endif
diff --git a/roms/u-boot/board/AndesTech/adp-ae3xx/MAINTAINERS b/roms/u-boot/board/AndesTech/adp-ae3xx/MAINTAINERS
new file mode 100644
index 000000000..02e5a19c9
--- /dev/null
+++ b/roms/u-boot/board/AndesTech/adp-ae3xx/MAINTAINERS
@@ -0,0 +1,6 @@
+ADP-AG101P BOARD
+M:	Andes <uboot@andestech.com>
+S:	Maintained
+F:	board/AndesTech/adp-ae3xx/
+F:	include/configs/adp-ae3xx.h
+F:	configs/adp-ae3xx_defconfig
diff --git a/roms/u-boot/board/AndesTech/adp-ae3xx/Makefile b/roms/u-boot/board/AndesTech/adp-ae3xx/Makefile
new file mode 100644
index 000000000..8c889d100
--- /dev/null
+++ b/roms/u-boot/board/AndesTech/adp-ae3xx/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2016 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+
+obj-y	:= adp-ae3xx.o
diff --git a/roms/u-boot/board/AndesTech/adp-ae3xx/adp-ae3xx.c b/roms/u-boot/board/AndesTech/adp-ae3xx/adp-ae3xx.c
new file mode 100644
index 000000000..3c4a27d63
--- /dev/null
+++ b/roms/u-boot/board/AndesTech/adp-ae3xx/adp-ae3xx.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <common.h>
+#include <flash.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+#include <netdev.h>
+#endif
+#include <linux/io.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	printf("Board: %s\n" , CONFIG_SYS_BOARD);
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAE3XX;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+	unsigned long actual_size;
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+	gd->ram_size = actual_size;
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+int board_eth_init(struct bd_info *bd)
+{
+	return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
diff --git a/roms/u-boot/board/AndesTech/adp-ag101p/Kconfig b/roms/u-boot/board/AndesTech/adp-ag101p/Kconfig
new file mode 100644
index 000000000..5e8aa22c4
--- /dev/null
+++ b/roms/u-boot/board/AndesTech/adp-ag101p/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_ADP_AG101P
+
+config SYS_CPU
+	default "n1213"
+
+config SYS_BOARD
+	default "adp-ag101p"
+
+config SYS_VENDOR
+	default "AndesTech"
+
+config SYS_SOC
+	default "ag101"
+
+config SYS_CONFIG_NAME
+	default "adp-ag101p"
+
+endif
diff --git a/roms/u-boot/board/AndesTech/adp-ag101p/MAINTAINERS b/roms/u-boot/board/AndesTech/adp-ag101p/MAINTAINERS
new file mode 100644
index 000000000..9a2c7a3c1
--- /dev/null
+++ b/roms/u-boot/board/AndesTech/adp-ag101p/MAINTAINERS
@@ -0,0 +1,6 @@
+ADP-AG101P BOARD
+M:	Andes <uboot@andestech.com>
+S:	Maintained
+F:	board/AndesTech/adp-ag101p/
+F:	include/configs/adp-ag101p.h
+F:	configs/adp-ag101p_defconfig
diff --git a/roms/u-boot/board/AndesTech/adp-ag101p/Makefile b/roms/u-boot/board/AndesTech/adp-ag101p/Makefile
new file mode 100644
index 000000000..5398f7ed0
--- /dev/null
+++ b/roms/u-boot/board/AndesTech/adp-ag101p/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+
+obj-y	:= adp-ag101p.o
diff --git a/roms/u-boot/board/AndesTech/adp-ag101p/adp-ag101p.c b/roms/u-boot/board/AndesTech/adp-ag101p/adp-ag101p.c
new file mode 100644
index 000000000..8848b7f97
--- /dev/null
+++ b/roms/u-boot/board/AndesTech/adp-ag101p/adp-ag101p.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#include <common.h>
+#include <flash.h>
+#include <init.h>
+#include <net.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+#include <netdev.h>
+#endif
+#include <asm/global_data.h>
+#include <linux/io.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	printf("Board: %s\n" , CONFIG_SYS_BOARD);
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+int board_eth_init(struct bd_info *bd)
+{
+	return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
diff --git a/roms/u-boot/board/AndesTech/ax25-ae350/Kconfig b/roms/u-boot/board/AndesTech/ax25-ae350/Kconfig
new file mode 100644
index 000000000..e50f505a2
--- /dev/null
+++ b/roms/u-boot/board/AndesTech/ax25-ae350/Kconfig
@@ -0,0 +1,39 @@
+if TARGET_AX25_AE350
+
+config SYS_CPU
+	default "ax25"
+
+config SYS_BOARD
+	default "ax25-ae350"
+
+config SYS_VENDOR
+	default "AndesTech"
+
+config SYS_SOC
+	default "ae350"
+
+config SYS_CONFIG_NAME
+	default "ax25-ae350"
+
+config ENV_SIZE
+	default 0x2000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+	default 0x140000 if ENV_IS_IN_SPI_FLASH
+
+config SPL_TEXT_BASE
+	default 0x800000
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x01000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select RISCV_NDS
+	select SUPPORT_SPL
+	select BINMAN if SPL
+	imply SMP
+	imply SPL_RAM_SUPPORT
+	imply SPL_RAM_DEVICE
+
+endif
diff --git a/roms/u-boot/board/AndesTech/ax25-ae350/MAINTAINERS b/roms/u-boot/board/AndesTech/ax25-ae350/MAINTAINERS
new file mode 100644
index 000000000..eebee167c
--- /dev/null
+++ b/roms/u-boot/board/AndesTech/ax25-ae350/MAINTAINERS
@@ -0,0 +1,13 @@
+AX25-AE350 BOARD
+M:	Rick Chen <rick@andestech.com>
+S:	Maintained
+F:	board/AndesTech/ax25-ae350/
+F:	include/configs/ax25-ae350.h
+F:	configs/ae350_rv32_defconfig
+F:	configs/ae350_rv64_defconfig
+F:	configs/ae350_rv32_xip_defconfig
+F:	configs/ae350_rv64_xip_defconfig
+F:	configs/ae350_rv32_spl_defconfig
+F:	configs/ae350_rv64_spl_defconfig
+F:	configs/ae350_rv32_spl_xip_defconfig
+F:	configs/ae350_rv64_spl_xip_defconfig
diff --git a/roms/u-boot/board/AndesTech/ax25-ae350/Makefile b/roms/u-boot/board/AndesTech/ax25-ae350/Makefile
new file mode 100644
index 000000000..0e4ba8d70
--- /dev/null
+++ b/roms/u-boot/board/AndesTech/ax25-ae350/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Andes Technology Corporation.
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+
+obj-y	:= ax25-ae350.o
diff --git a/roms/u-boot/board/AndesTech/ax25-ae350/ax25-ae350.c b/roms/u-boot/board/AndesTech/ax25-ae350/ax25-ae350.c
new file mode 100644
index 000000000..81b0ee992
--- /dev/null
+++ b/roms/u-boot/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <common.h>
+#include <flash.h>
+#include <image.h>
+#include <init.h>
+#include <net.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+#include <netdev.h>
+#endif
+#include <asm/global_data.h>
+#include <linux/io.h>
+#include <faraday/ftsmc020.h>
+#include <fdtdec.h>
+#include <dm.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern phys_addr_t prior_stage_fdt_address;
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+int board_eth_init(struct bd_info *bd)
+{
+	return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	return 0;
+}
+
+void *board_fdt_blob_setup(void)
+{
+	return (void *)CONFIG_SYS_FDT_BASE;
+}
+
+int smc_init(void)
+{
+	int node = -1;
+	const char *compat = "andestech,atfsmc020";
+	void *blob = (void *)gd->fdt_blob;
+	fdt_addr_t addr;
+	struct ftsmc020_bank *regs;
+
+	node = fdt_node_offset_by_compatible(blob, -1, compat);
+	if (node < 0)
+		return -FDT_ERR_NOTFOUND;
+
+	addr = fdtdec_get_addr_size_auto_noparent(blob, node,
+		"reg", 0, NULL, false);
+
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	regs = (struct ftsmc020_bank *)(uintptr_t)addr;
+	regs->cr &= ~FTSMC020_BANK_WPROT;
+
+	return 0;
+}
+
+static void v5l2_init(void)
+{
+	struct udevice *dev;
+
+	uclass_get_device(UCLASS_CACHE, 0, &dev);
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	smc_init();
+	v5l2_init();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list)
+{
+	u8 i;
+	u32 boot_devices[] = {
+#ifdef CONFIG_SPL_RAM_SUPPORT
+		BOOT_DEVICE_RAM,
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+		BOOT_DEVICE_MMC1,
+#endif
+	};
+
+	for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+		spl_boot_list[i] = boot_devices[i];
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/Arcturus/ucp1020/Kconfig b/roms/u-boot/board/Arcturus/ucp1020/Kconfig
new file mode 100644
index 000000000..fe2c3be1b
--- /dev/null
+++ b/roms/u-boot/board/Arcturus/ucp1020/Kconfig
@@ -0,0 +1,36 @@
+if TARGET_UCP1020
+
+config SYS_BOARD
+	string
+	default "ucp1020"
+
+config SYS_VENDOR
+	string
+	default "Arcturus"
+
+config SYS_CONFIG_NAME
+	string
+	default "UCP1020"
+
+choice
+	prompt "Target image select"
+
+config TARGET_UCP1020_NOR
+	bool "NOR flash u-boot image"
+
+config TARGET_UCP1020_SPIFLASH
+	bool "SPI flash u-boot image"
+
+endchoice
+
+if TARGET_UCP1020_SPIFLASH
+config UCBOOT
+	bool
+	default y
+
+config SPIFLASH
+	bool
+	default y
+endif
+
+endif
diff --git a/roms/u-boot/board/Arcturus/ucp1020/MAINTAINERS b/roms/u-boot/board/Arcturus/ucp1020/MAINTAINERS
new file mode 100644
index 000000000..e4a471818
--- /dev/null
+++ b/roms/u-boot/board/Arcturus/ucp1020/MAINTAINERS
@@ -0,0 +1,7 @@
+UCP1020 BOARD
+M:	Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
+S:	Maintained
+F:	board/Arcturus/ucp1020/
+F:	include/configs/UCP1020.h
+F:	configs/UCP1020_defconfig
+F:	configs/UCP1020_SPIFLASH_defconfig
diff --git a/roms/u-boot/board/Arcturus/ucp1020/Makefile b/roms/u-boot/board/Arcturus/ucp1020/Makefile
new file mode 100644
index 000000000..46d04fb78
--- /dev/null
+++ b/roms/u-boot/board/Arcturus/ucp1020/Makefile
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2013-2015 Arcturus Networks, Inc.
+# based on board/freescale/p1_p2_rdb_pc/Makefile
+# original copyright follows:
+# Copyright 2010-2011 Freescale Semiconductor, Inc.
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y	+= spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
+obj-y        += ucp1020.o
+obj-y        += ddr.o
+obj-y        += law.o
+obj-y        += tlb.o
+obj-y        += cmd_arc.o
+
+endif
diff --git a/roms/u-boot/board/Arcturus/ucp1020/README b/roms/u-boot/board/Arcturus/ucp1020/README
new file mode 100644
index 000000000..555c4ef79
--- /dev/null
+++ b/roms/u-boot/board/Arcturus/ucp1020/README
@@ -0,0 +1,54 @@
+The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules
+product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs,
+DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
+
+Information on the generic product family can be found here:
+	http://www.arcturusnetworks.com/products/ucp1020
+
+The UCP1020 several configurable options
+========================================
+
+- the selection of populated phy(s):
+	KSZ9031 (current default for eTSEC 1 and 3)
+
+- the selection of boot location:
+	SPI Flash or NOR flash
+
+The UCP1020 includes 2 default configurations
+=============================================
+NOR boot image:
+	configs/UCP1020_defconfig
+SPI boot image:
+	configs/UCP1020_SPIFLASH_defconfig
+
+The UCP1020 adds an additional command in cmd_arc.c to access and program
+SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet
+HW Addresses.
+
+
+Build example
+=============
+
+make distclean
+make UCP1020_defconfig
+make
+
+Default Scripts
+===============
+A default upgrade scripts is included in the default environment variable example:
+
+B$ run tftpflash
+
+Dual Environment
+================
+
+This build enables dual / failover environment environment.
+
+NOR Flash Partition declarations and scripts
+============================================
+Several scripts are available to allow TFTP of images and programming directly
+into defined NOR flash partitions. Examples:
+
+B$ run program0
+B$ run program1
+B$ run program2
diff --git a/roms/u-boot/board/Arcturus/ucp1020/cmd_arc.c b/roms/u-boot/board/Arcturus/ucp1020/cmd_arc.c
new file mode 100644
index 000000000..4b30b66e2
--- /dev/null
+++ b/roms/u-boot/board/Arcturus/ucp1020/cmd_arc.c
@@ -0,0 +1,408 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Command for accessing Arcturus factory environment.
+ *
+ * Copyright 2013-2019 Arcturus Networks Inc.
+ *           https://www.arcturusnetworks.com/products/
+ *           by Oleksandr G Zhadan et al.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <div64.h>
+#include <env.h>
+#include <flash.h>
+#include <malloc.h>
+#include <spi_flash.h>
+#include <mmc.h>
+#include <version.h>
+#include <asm/io.h>
+#include <linux/stringify.h>
+
+static ulong fwenv_addr[MAX_FWENV_ADDR];
+const char mystrerr[] = "ERROR: Failed to save factory info";
+
+static int ishwaddr(char *hwaddr)
+{
+	if (strlen(hwaddr) == MAX_HWADDR_SIZE)
+		if (hwaddr[2] == ':' &&
+		    hwaddr[5] == ':' &&
+		    hwaddr[8] == ':' &&
+		    hwaddr[11] == ':' &&
+		    hwaddr[14] == ':')
+			return 0;
+	return -1;
+}
+
+#if (FWENV_TYPE == FWENV_MMC)
+
+static char smac[29][18] __attribute__ ((aligned(0x200)));	/* 1 MMC block is 512 bytes */
+
+int set_mmc_arc_product(int argc, char *const argv[])
+{
+	struct mmc *mmc;
+	u32 blk, cnt, n;
+	int i, err = 1;
+	void *addr;
+	const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
+
+	mmc = find_mmc_device(mmc_dev_num);
+	if (!mmc) {
+		printf("No SD/MMC/eMMC card found\n");
+		return 0;
+	}
+	if (mmc_init(mmc)) {
+		printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
+		       mmc_dev_num);
+		return 0;
+	}
+	if (mmc_getwp(mmc) == 1) {
+		printf("Error: card is write protected!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	/* Save factory defaults */
+	addr = (void *)smac;
+	cnt = 1;		/* One 512 bytes block */
+
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1) {
+			blk = fwenv_addr[i] / 512;
+			n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
+			if (n != cnt)
+				printf("%s: %s [%d]\n", __func__, mystrerr, i);
+			else
+				err = 0;
+		}
+	if (err)
+		return -2;
+
+	return err;
+}
+
+static int read_mmc_arc_info(void)
+{
+	struct mmc *mmc;
+	u32 blk, cnt, n;
+	int i;
+	void *addr;
+	const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
+
+	mmc = find_mmc_device(mmc_dev_num);
+	if (!mmc) {
+		printf("No SD/MMC/eMMC card found\n");
+		return 0;
+	}
+	if (mmc_init(mmc)) {
+		printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
+		       mmc_dev_num);
+		return 0;
+	}
+
+	addr = (void *)smac;
+	cnt = 1;		/* One 512 bytes block */
+
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1) {
+			blk = fwenv_addr[i] / 512;
+			n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
+			flush_cache((ulong) addr, 512);
+			if (n == cnt)
+				return (i + 1);
+		}
+	return 0;
+}
+#endif
+
+#if (FWENV_TYPE == FWENV_SPI_FLASH)
+
+static struct spi_flash *flash;
+static char smac[4][18];
+
+int set_spi_arc_product(int argc, char *const argv[])
+{
+	int i, err = 1;
+
+	flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+				CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+	if (!flash) {
+		printf("Failed to initialize SPI flash at %u:%u\n",
+		       CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS);
+		return -1;
+	}
+
+	/* Save factory defaults */
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1)
+			if (spi_flash_write
+			    (flash, fwenv_addr[i], sizeof(smac), smac))
+				printf("%s: %s [%d]\n", __func__, mystrerr, i);
+			else
+				err = 0;
+	if (err)
+		return -2;
+
+	return err;
+}
+
+static int read_spi_arc_info(void)
+{
+	int i;
+
+	flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+				CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+	if (!flash) {
+		printf("Failed to initialize SPI flash at %u:%u\n",
+		       CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS);
+		return 0;
+	}
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1)
+			if (!spi_flash_read
+			    (flash, fwenv_addr[i], sizeof(smac), smac))
+				return (i + 1);
+	return 0;
+}
+#endif
+
+#if (FWENV_TYPE == FWENV_NOR_FLASH)
+
+static char smac[4][18];
+
+int set_nor_arc_product(int argc, char *const argv[])
+{
+	int i, err = 1;
+
+	/* Save factory defaults */
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1) {
+			ulong fwenv_end = fwenv_addr[i] + 4;
+
+			flash_sect_roundb(&fwenv_end);
+			flash_sect_protect(0, fwenv_addr[i], fwenv_end);
+			if (flash_write
+			    ((char *)smac, fwenv_addr[i], sizeof(smac)))
+				printf("%s: %s [%d]\n", __func__, mystrerr, i);
+			else
+				err = 0;
+			flash_sect_protect(1, fwenv_addr[i], fwenv_end);
+		}
+	if (err)
+		return -2;
+
+	return err;
+}
+
+static int read_nor_arc_info(void)
+{
+	int i;
+
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1) {
+			memcpy(smac, (void *)fwenv_addr[i], sizeof(smac));
+			return (i + 1);
+		}
+
+	return 0;
+}
+#endif
+
+int set_arc_product(int argc, char *const argv[])
+{
+	if (argc != 5)
+		return -1;
+
+	/* Check serial number */
+	if (strlen(argv[1]) != MAX_SERIAL_SIZE)
+		return -1;
+
+	/* Check HWaddrs */
+	if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4]))
+		return -1;
+
+	strcpy(smac[0], argv[1]);
+	strcpy(smac[1], argv[2]);
+	strcpy(smac[2], argv[3]);
+	strcpy(smac[3], argv[4]);
+
+#if (FWENV_TYPE == FWENV_NOR_FLASH)
+	return set_nor_arc_product(argc, argv);
+#endif
+#if (FWENV_TYPE == FWENV_SPI_FLASH)
+	return set_spi_arc_product(argc, argv);
+#endif
+#if (FWENV_TYPE == FWENV_MMC)
+	return set_mmc_arc_product(argc, argv);
+#endif
+	return -2;
+}
+
+static int read_arc_info(void)
+{
+#if (FWENV_TYPE == FWENV_NOR_FLASH)
+	return read_nor_arc_info();
+#endif
+#if (FWENV_TYPE == FWENV_SPI_FLASH)
+	return read_spi_arc_info();
+#endif
+#if (FWENV_TYPE == FWENV_MMC)
+	return read_mmc_arc_info();
+#endif
+	return 0;
+}
+
+static int do_get_arc_info(void)
+{
+	int l = read_arc_info();
+	char *oldserial = env_get("SERIAL");
+	char *oldversion = env_get("VERSION");
+
+	if (oldversion != NULL)
+		if (strcmp(oldversion, U_BOOT_VERSION) != 0)
+			oldversion = NULL;
+
+	if (l == 0) {
+		printf("%s: failed to read factory info\n", __func__);
+		return -2;
+	}
+
+	printf("\rSERIAL:  ");
+	if (smac[0][0] == EMPY_CHAR) {
+		printf("<not found>\n");
+	} else {
+		printf("%s\n", smac[0]);
+		env_set("SERIAL", smac[0]);
+	}
+
+	if (strcmp(smac[1], "00:00:00:00:00:00") == 0) {
+		env_set("ethaddr", NULL);
+		env_set("eth1addr", NULL);
+		env_set("eth2addr", NULL);
+		goto done;
+	}
+
+	printf("HWADDR0: ");
+	if (smac[1][0] == EMPY_CHAR) {
+		printf("<not found>\n");
+	} else {
+		char *ret = env_get("ethaddr");
+
+		if (ret == NULL) {
+			env_set("ethaddr", smac[1]);
+			printf("%s\n", smac[1]);
+		} else if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) {
+			env_set("ethaddr", smac[1]);
+			printf("%s (factory)\n", smac[1]);
+		} else {
+			printf("%s\n", ret);
+		}
+	}
+
+	if (strcmp(smac[2], "00:00:00:00:00:00") == 0) {
+		env_set("eth1addr", NULL);
+		env_set("eth2addr", NULL);
+		goto done;
+	}
+
+	printf("HWADDR1: ");
+	if (smac[2][0] == EMPY_CHAR) {
+		printf("<not found>\n");
+	} else {
+		char *ret = env_get("eth1addr");
+
+		if (ret == NULL) {
+			env_set("ethaddr", smac[2]);
+			printf("%s\n", smac[2]);
+		} else if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) {
+			env_set("eth1addr", smac[2]);
+			printf("%s (factory)\n", smac[2]);
+		} else {
+			printf("%s\n", ret);
+		}
+	}
+
+	if (strcmp(smac[3], "00:00:00:00:00:00") == 0) {
+		env_set("eth2addr", NULL);
+		goto done;
+	}
+
+	printf("HWADDR2: ");
+	if (smac[3][0] == EMPY_CHAR) {
+		printf("<not found>\n");
+	} else {
+		char *ret = env_get("eth2addr");
+
+		if (ret == NULL) {
+			env_set("ethaddr", smac[3]);
+			printf("%s\n", smac[3]);
+		} else if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) {
+			env_set("eth2addr", smac[3]);
+			printf("%s (factory)\n", smac[3]);
+		} else {
+			printf("%s\n", ret);
+		}
+	}
+done:
+	if (oldserial == NULL || oldversion == NULL) {
+		if (oldversion == NULL)
+			env_set("VERSION", U_BOOT_VERSION);
+		env_save();
+	}
+
+	return 0;
+}
+
+static int init_fwenv(void)
+{
+	int i, ret = -1;
+
+	fwenv_addr[0] = FWENV_ADDR1;
+	fwenv_addr[1] = FWENV_ADDR2;
+	fwenv_addr[2] = FWENV_ADDR3;
+	fwenv_addr[3] = FWENV_ADDR4;
+
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1)
+			ret = 0;
+	if (ret)
+		printf("%s: No firmfare info storage address is defined\n",
+		       __func__);
+	return ret;
+}
+
+void get_arc_info(void)
+{
+	if (!init_fwenv())
+		do_get_arc_info();
+}
+
+static int do_arc_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+		      char *const argv[])
+{
+	const char *cmd;
+	int ret = -1;
+
+	cmd = argv[1];
+	--argc;
+	++argv;
+
+	if (init_fwenv())
+		return ret;
+
+	if (strcmp(cmd, "product") == 0)
+		ret = set_arc_product(argc, argv);
+	else if (strcmp(cmd, "info") == 0)
+		ret = do_get_arc_info();
+
+	if (ret == -1)
+		return CMD_RET_USAGE;
+
+	return ret;
+}
+
+U_BOOT_CMD(arc, 6, 1, do_arc_cmd,
+	   "Arcturus product command sub-system",
+	   "product serial hwaddr0 hwaddr1 hwaddr2    - save Arcturus factory env\n"
+	   "info                                      - show Arcturus factory env\n\n");
diff --git a/roms/u-boot/board/Arcturus/ucp1020/ddr.c b/roms/u-boot/board/Arcturus/ucp1020/ddr.c
new file mode 100644
index 000000000..a3285ebe5
--- /dev/null
+++ b/roms/u-boot/board/Arcturus/ucp1020/ddr.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
+/*
+ * Micron MT41J128M16HA-15E
+ * */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 536870912u,
+	.capacity = 536870912u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 14,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 2,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 1650,
+	.caslat_x = 0x7e << 4,	/* 5,6,7,8,9,10 */
+	.taa_ps = 14050,
+	.twr_ps = 15000,
+	.trcd_ps = 13500,
+	.trrd_ps = 75000,
+	.trp_ps = 13500,
+	.tras_ps = 40000,
+	.trc_ps = 49500,
+	.trfc_ps = 160000,
+	.twtr_ps = 75000,
+	.trtp_ps = 75000,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 30000,
+};
+
+#else
+#error Missing raw timing data for this board
+#endif
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			    unsigned int controller_number,
+			    unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR on board";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
+
+#ifdef CONFIG_SYS_DDR_CS0_BNDS
+/* Fixed sdram init -- doesn't use serial presence detect. */
+phys_size_t fixed_sdram(void)
+{
+	sys_info_t sysinfo;
+	char buf[32];
+	size_t ddr_size;
+	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
+		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+#endif
+		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
+		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
+		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
+		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
+		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
+		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
+		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+		.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
+		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
+		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+	};
+
+	get_sys_info(&sysinfo);
+	printf("Configuring DDR for %s MT/s data rate\n",
+	       strmhz(buf, sysinfo.freq_ddrbus));
+
+	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+			 ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
+		printf("ERROR setting Local Access Windows for DDR\n");
+		return 0;
+	};
+
+	return ddr_size;
+}
+#endif
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	int i;
+
+	popts->clk_adjust = 6;
+	popts->cpo_override = 0x1f;
+	popts->write_data_delay = 2;
+	popts->half_strength_driver_enable = 1;
+	/* Write leveling override */
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x8;
+	popts->trwt_override = 1;
+	popts->trwt = 0;
+
+	if (pdimm->primary_sdram_width == 64)
+		popts->data_bus_width = 0;
+	else if (pdimm->primary_sdram_width == 32)
+		popts->data_bus_width = 1;
+	else
+		printf("Error in DDR bus width configuration!\n");
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+	}
+}
diff --git a/roms/u-boot/board/Arcturus/ucp1020/law.c b/roms/u-boot/board/Arcturus/ucp1020/law.c
new file mode 100644
index 000000000..cb53692a3
--- /dev/null
+++ b/roms/u-boot/board/Arcturus/ucp1020/law.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_VSC7385_ENET
+	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/Arcturus/ucp1020/spl.c b/roms/u-boot/board/Arcturus/ucp1020/spl.c
new file mode 100644
index 000000000..437e975fd
--- /dev/null
+++ b/roms/u-boot/board/Arcturus/ucp1020/spl.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <console.h>
+#include <env.h>
+#include <env_internal.h>
+#include <init.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 sysclk_tbl[] = {
+	66666000, 7499900, 83332500, 8999900,
+	99999000, 11111000, 12499800, 13333200
+};
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, bus_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+	setbits_be32(&gur->pmuxcr,
+		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+	/* Read back the register to synchronize the write. */
+	in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	gd->bus_clk = bus_clk;
+
+	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+		     bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
+#endif
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	struct bd_info *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(struct bd_info));
+	gd->bd = bd;
+
+	arch_cpu_init();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+	env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+	gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = ENV_VALID;
+#else
+	env_relocate();
+#endif
+
+#ifdef CONFIG_SYS_I2C
+	i2c_init_all();
+#else
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	dram_init();
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("Tertiary program loader running in sram...");
+#else
+	puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/roms/u-boot/board/Arcturus/ucp1020/spl_minimal.c b/roms/u-boot/board/Arcturus/ucp1020/spl_minimal.c
new file mode 100644
index 000000000..90abec9cc
--- /dev/null
+++ b/roms/u-boot/board/Arcturus/ucp1020/spl_minimal.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
+ * original copyright follows:
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	puts("\nSecond program loader running in sram...");
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r');
+
+	ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
diff --git a/roms/u-boot/board/Arcturus/ucp1020/tlb.c b/roms/u-boot/board/Arcturus/ucp1020/tlb.c
new file mode 100644
index 000000000..2c07df63e
--- /dev/null
+++ b/roms/u-boot/board/Arcturus/ucp1020/tlb.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/tlb.c
+ * original copyright follows:
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
+		      0, 2, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_PCI
+	/* *I*G* - PCI memory 1.5G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O effective: 192K  */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#ifdef CONFIG_VSC7385_ENET
+	/* *I*G - VSC7385 Switch */
+	SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 5, BOOKE_PAGESZ_1M, 1),
+#endif
+#endif /* not SPL */
+
+#ifdef CONFIG_SYS_NAND_BASE
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+	/* *I*G - eSDHC/eSPI/NAND boot */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
+		      0, 8, BOOKE_PAGESZ_1G, 1),
+
+#endif /* RAMBOOT/SPL */
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/Arcturus/ucp1020/ucp1020.c b/roms/u-boot/board/Arcturus/ucp1020/ucp1020.c
new file mode 100644
index 000000000..24d1d57ec
--- /dev/null
+++ b/roms/u-boot/board/Arcturus/ucp1020/ucp1020.c
@@ -0,0 +1,372 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2019 Arcturus Networks, Inc.
+ *           https://www.arcturusnetworks.com/products/ucp1020/
+ *           by Oleksandr G Zhadan et al.
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <hwconfig.h>
+#include <image.h>
+#include <init.h>
+#include <net.h>
+#include <pci.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <ioports.h>
+#include <netdev.h>
+#include <micrel.h>
+#include <spi_flash.h>
+#include <mmc.h>
+#include <linux/ctype.h>
+#include <asm/fsl_serdes.h>
+#include <asm/gpio.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_lbc.h>
+#include <asm/mp.h>
+#include "ucp1020.h"
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+	/* TO DO: It's actially have to be in spi/ */
+}
+
+/*
+ * To be compatible with cmd_gpio
+ */
+int name_to_gpio(const char *name)
+{
+	int gpio = 31 - simple_strtoul(name, NULL, 10);
+
+	if (gpio < 16)
+		gpio = -1;
+
+	return gpio;
+}
+
+void board_gpio_init(void)
+{
+	int i;
+	char envname[8], *val;
+
+	for (i = 0; i < GPIO_MAX_NUM; i++) {
+		sprintf(envname, "GPIO%d", i);
+		val = env_get(envname);
+		if (val) {
+			char direction = toupper(val[0]);
+			char level = toupper(val[1]);
+
+			if (direction == 'I') {
+				gpio_direction_input(i);
+			} else {
+				if (direction == 'O') {
+					if (level == '1')
+						gpio_direction_output(i, 1);
+					else
+						gpio_direction_output(i, 0);
+				}
+			}
+		}
+	}
+
+	val = env_get("PCIE_OFF");
+	if (val) {
+		gpio_direction_input(GPIO_PCIE1_EN);
+		gpio_direction_input(GPIO_PCIE2_EN);
+	} else {
+		gpio_direction_output(GPIO_PCIE1_EN, 1);
+		gpio_direction_output(GPIO_PCIE2_EN, 1);
+	}
+
+	val = env_get("SDHC_CDWP_OFF");
+	if (!val) {
+		ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+		setbits_be32(&gur->pmuxcr,
+			     (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+	}
+}
+
+int board_early_init_f(void)
+{
+	return 0;	/* Just in case. Could be disable in config file */
+}
+
+int checkboard(void)
+{
+	printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
+	board_gpio_init();
+#ifdef CONFIG_MMC
+	printf("SD/MMC: 4-bit Mode\n");
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+		MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
+		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+#if defined(CONFIG_PHY_MICREL_KSZ9021)
+	int regval;
+	static int cnt;
+
+	if (cnt++ == 0)
+		printf("PHYs address [");
+
+	if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
+		regval =
+		    ksz9021_phy_extended_read(phydev,
+					      MII_KSZ9021_EXT_STRAP_STATUS);
+		/*
+		 * min rx data delay
+		 */
+		ksz9021_phy_extended_write(phydev,
+					   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+					   0x6666);
+		/*
+		 * max rx/tx clock delay, min rx/tx control
+		 */
+		ksz9021_phy_extended_write(phydev,
+					   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+					   0xf6f6);
+		printf("0x%x", (regval & 0x1f));
+	} else {
+		printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
+	}
+	if (cnt == 3)
+		printf("] ");
+	else
+		printf(",");
+#endif
+
+#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
+	regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
+	if (regval >= 0)
+		printf(" (ADDR 0x%x) ", regval & 0x1f);
+#endif
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	static char newkernelargs[256];
+	static u8 id1[16];
+	static u8 id2;
+#ifdef CONFIG_MMC
+	struct mmc *mmc;
+#endif
+	char *sval, *kval;
+
+	if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
+		printf("Error reading i2c IDT6V49205B information!\n");
+	} else {
+		printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
+		i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
+		if (!(id1[1] & 0x02)) {
+			id1[1] |= 0x02;
+			i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
+			asm("nop; nop");
+		}
+	}
+
+	if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
+		printf("Error reading i2c NCT72 information!\n");
+	else
+		printf("NCT72(0x%x): ready\n", id2);
+
+	kval = env_get("kernelargs");
+
+#ifdef CONFIG_MMC
+	mmc = find_mmc_device(0);
+	if (mmc)
+		if (!mmc_init(mmc)) {
+			printf("MMC/SD card detected\n");
+			if (kval) {
+				int n = strlen(defkargs);
+				char *tmp = strstr(kval, defkargs);
+
+				*tmp = 0;
+				strcpy(newkernelargs, kval);
+				strcat(newkernelargs, " ");
+				strcat(newkernelargs, mmckargs);
+				strcat(newkernelargs, " ");
+				strcat(newkernelargs, &tmp[n]);
+				env_set("kernelargs", newkernelargs);
+			} else {
+				env_set("kernelargs", mmckargs);
+			}
+		}
+#endif
+	get_arc_info();
+
+	if (kval) {
+		sval = env_get("SERIAL");
+		if (sval) {
+			strcpy(newkernelargs, "SN=");
+			strcat(newkernelargs, sval);
+			strcat(newkernelargs, " ");
+			strcat(newkernelargs, kval);
+			env_set("kernelargs", newkernelargs);
+		}
+	} else {
+		printf("Error reading kernelargs env variable!\n");
+	}
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+#ifdef CONFIG_TSEC2
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (is_serdes_configured(SGMII_TSEC2)) {
+		if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
+			puts("eTSEC2 is in sgmii mode.\n");
+			tsec_info[num].flags |= TSEC_SGMII;
+			tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
+		}
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+	const char *soc_usb_compat = "fsl-usb2-dr";
+	int err, usb1_off, usb2_off;
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	FT_FSL_PCI_SETUP;
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+	fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+	/* Delete eLBC node as it is muxed with USB2 controller */
+	if (hwconfig("usb2")) {
+		const char *soc_elbc_compat = "fsl,p1020-elbc";
+		int off = fdt_node_offset_by_compatible(blob, -1,
+							soc_elbc_compat);
+		if (off < 0) {
+			printf
+			    ("WARNING: could not find compatible node %s: %s\n",
+			     soc_elbc_compat, fdt_strerror(off));
+			return off;
+		}
+		err = fdt_del_node(blob, off);
+		if (err < 0) {
+			printf("WARNING: could not remove %s: %s\n",
+			       soc_elbc_compat, fdt_strerror(err));
+		}
+		return err;
+	}
+#endif
+
+/* Delete USB2 node as it is muxed with eLBC */
+	usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
+	if (usb1_off < 0) {
+		printf("WARNING: could not find compatible node %s: %s.\n",
+		       soc_usb_compat, fdt_strerror(usb1_off));
+		return usb1_off;
+	}
+	usb2_off =
+	    fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
+	if (usb2_off < 0) {
+		printf("WARNING: could not find compatible node %s: %s.\n",
+		       soc_usb_compat, fdt_strerror(usb2_off));
+		return usb2_off;
+	}
+	err = fdt_del_node(blob, usb2_off);
+	if (err < 0) {
+		printf("WARNING: could not remove %s: %s.\n",
+		       soc_usb_compat, fdt_strerror(err));
+	}
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/Arcturus/ucp1020/ucp1020.h b/roms/u-boot/board/Arcturus/ucp1020/ucp1020.h
new file mode 100644
index 000000000..1b527cdb1
--- /dev/null
+++ b/roms/u-boot/board/Arcturus/ucp1020/ucp1020.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013-2019 Arcturus Networks, Inc.
+ *           https://www.arcturusnetworks.com/products/ucp1020/
+ *           by Oleksandr G Zhadan et al.
+ */
+
+#ifndef __UCP1020_H__
+#define __UCP1020_H__
+
+#define GPIO0		31
+#define GPIO1		30
+#define GPIO2		29
+#define GPIO3		28
+#define GPIO4		27
+#define GPIO5		26
+#define GPIO6		25
+#define GPIO7		24
+#define GPIO8		23
+#define GPIO9		22
+#define GPIO10		21
+#define GPIO11		20
+#define GPIO12		19
+#define GPIO13		18
+#define GPIO14		17
+#define GPIO15		16
+#define GPIO_MAX_NUM	16
+
+#define GPIO_SDHC_CD	GPIO8
+#define GPIO_SDHC_WP	GPIO9
+#define GPIO_USB_PCTL0	GPIO10
+#define GPIO_PCIE1_EN	GPIO11
+#define GPIO_PCIE2_EN	GPIO10
+#define GPIO_USB_PCTL1	GPIO11
+
+#define GPIO_WD		GPIO15
+
+#ifdef CONFIG_MMC
+static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro";
+static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw";
+#endif
+
+int get_arc_info(void);
+
+#endif
diff --git a/roms/u-boot/board/BuR/brppt1/Kconfig b/roms/u-boot/board/BuR/brppt1/Kconfig
new file mode 100644
index 000000000..e006c80e6
--- /dev/null
+++ b/roms/u-boot/board/BuR/brppt1/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BRPPT1
+
+config SYS_BOARD
+	default "brppt1"
+
+config SYS_VENDOR
+	default "BuR"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "brppt1"
+
+endif
diff --git a/roms/u-boot/board/BuR/brppt1/MAINTAINERS b/roms/u-boot/board/BuR/brppt1/MAINTAINERS
new file mode 100644
index 000000000..9eddab420
--- /dev/null
+++ b/roms/u-boot/board/BuR/brppt1/MAINTAINERS
@@ -0,0 +1,8 @@
+BRPPT1 BOARD
+M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S:	Maintained
+F:	board/BuR/brppt1/
+F:	include/configs/brppt1.h
+F:	configs/brppt1_mmc_defconfig
+F:	configs/brppt1_nand_defconfig
+F:	configs/brppt1_spi_defconfig
diff --git a/roms/u-boot/board/BuR/brppt1/Makefile b/roms/u-boot/board/BuR/brppt1/Makefile
new file mode 100644
index 000000000..3dec0e652
--- /dev/null
+++ b/roms/u-boot/board/BuR/brppt1/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y	:= mux.o
+endif
+obj-y	+= ../common/common.o
+obj-y	+= board.o
diff --git a/roms/u-boot/board/BuR/brppt1/board.c b/roms/u-boot/board/BuR/brppt1/board.c
new file mode 100644
index 000000000..7df37e4e6
--- /dev/null
+++ b/roms/u-boot/board/BuR/brppt1/board.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for B&R BRPPT1
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ */
+
+#include <common.h>
+#include <bootcount.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* --------------------------------------------------------------------------*/
+/* -- defines for GPIO -- */
+#define	REPSWITCH	(0+20)	/* GPIO0_20 */
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC	(V_OSCK/1000000)
+static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	int rc;
+
+	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+	/*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
+	struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+
+	/*
+	 * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
+	 * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
+	 * the source of timer6 clk to CLK_M_OSC
+	 */
+	writel(0x01, &cmdpll->clktimer6clk);
+
+	/* enable additional clocks of modules which are accessed later */
+	u32 *const clk_domains[] = {
+		&cmper->lcdcclkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_tsspecific[] = {
+		&cmper->lcdclkctrl,
+		&cmper->timer5clkctrl,
+		&cmper->timer6clkctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
+
+	/* setup I2C */
+	enable_i2c_pin_mux();
+
+	pmicsetup(0, 0);
+
+	/* peripheral reset */
+	rc = gpio_request(64 + 29, "GPMC_WAIT1");
+	if (rc != 0)
+		printf("cannot request GPMC_WAIT1 GPIO!\n");
+	rc = gpio_direction_output(64 + 29, 1);
+	if (rc != 0)
+		printf("cannot set GPMC_WAIT1 GPIO!\n");
+
+	rc = gpio_request(64 + 28, "GPMC_WAIT0");
+	if (rc != 0)
+		printf("cannot request GPMC_WAIT0 GPIO!\n");
+	rc = gpio_direction_output(64 + 28, 1);
+	if (rc != 0)
+		printf("cannot set GPMC_WAIT0 GPIO!\n");
+
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+	config_ddr(400, &ddr3_ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/* Basic board specific setup.  Pinmux has been handled already. */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#ifdef CONFIG_MTD_RAW_NAND
+	gpmc_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+static char *bootmodeascii[16] = {
+	"BOOT",		"reserved",	"reserved",	"reserved",
+	"RUN",		"reserved",	"reserved",	"reserved",
+	"reserved",	"reserved",	"reserved",	"reserved",
+	"PME",		"reserved",	"reserved",	"DIAG",
+};
+
+int board_late_init(void)
+{
+	unsigned char bmode = 0;
+	ulong bootcount = 0;
+	int rc;
+
+	bootcount = bootcount_load() & 0xF;
+
+	rc = gpio_request(REPSWITCH, "REPSWITCH");
+
+	if (rc != 0 || gpio_get_value(REPSWITCH) == 0 || bootcount == 12)
+		bmode = 12;
+	else if (bootcount > 0)
+		bmode = 0;
+	else
+		bmode = 4;
+
+	printf("Mode:  %s\n", bootmodeascii[bmode & 0x0F]);
+	env_set_ulong("b_mode", bmode);
+
+	/* get sure that bootcmd isn't affected by any bootcount value */
+	env_set_ulong("bootlimit", 0);
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/roms/u-boot/board/BuR/brppt1/config.mk b/roms/u-boot/board/BuR/brppt1/config.mk
new file mode 100644
index 000000000..6853135f8
--- /dev/null
+++ b/roms/u-boot/board/BuR/brppt1/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (C) 2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/am335x-//')
+
+payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
+
+quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
+cmd_prodbin =								\
+	dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
+	dd conv=notrunc bs=1 if=MLO.byteswap of=$@ seek=0 2>/dev/null && \
+	dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
+
+quiet_cmd_prodzip = SAPZIP  $@
+cmd_prodzip =					\
+	test -d misc && rm -r misc;		\
+	mkdir misc &&				\
+	cp MLO.byteswap misc/ &&		\
+	cp spl/u-boot-spl.bin misc/ &&		\
+	cp u-boot-dtb.img misc/ &&		\
+	zip -9 -r $@ misc/* >/dev/null $<
+
+ifeq ($(hw-platform-y),brppt1-spi)
+INPUTS-y += $(hw-platform-y)_prog.bin
+INPUTS-y += $(hw-platform-y)_prod.zip
+endif
+
+$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/u-boot-spl.bin
+	$(call if_changed,prodbin)
+
+$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
+	$(call if_changed,prodzip)
diff --git a/roms/u-boot/board/BuR/brppt1/mux.c b/roms/u-boot/board/BuR/brppt1/mux.c
new file mode 100644
index 000000000..b863d3733
--- /dev/null
+++ b/roms/u-boot/board/BuR/brppt1/mux.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R BRPPT1 Board(s)
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	/* UART0_RTS */
+	{OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
+	/* UART0_CTS */
+	{OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_RXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_TXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+static struct module_pin_mux uart1_pin_mux[] = {
+	/* UART1_RTS as I2C2-SCL */
+	{OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART1_CTS as I2C2-SDA */
+	{OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART1_RXD */
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART1_TXD */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
+
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+	{-1},
+};
+#endif
+static struct module_pin_mux i2c0_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	/* SPI0_SCLK */
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	/* SPI0_D0 */
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |	PULLUDEN | PULLUP_EN)},
+	/* SPI0_D1 */
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	/* SPI0_CS0 */
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_col), MODE(0) | RXACTIVE},		/* MII1_COL */
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux mii2_pin_mux[] = {
+	{OFFSET(gpmc_a0), MODE(1)},		/* MII2_TXEN */
+	{OFFSET(gpmc_a1), MODE(1) | RXACTIVE},	/* MII2_RXDV */
+	{OFFSET(gpmc_a2), MODE(1)},		/* MII2_TXD3 */
+	{OFFSET(gpmc_a3), MODE(1)},		/* MII2_TXD2 */
+	{OFFSET(gpmc_a4), MODE(1)},		/* MII2_TXD1 */
+	{OFFSET(gpmc_a5), MODE(1)},		/* MII2_TXD0 */
+	{OFFSET(gpmc_a6), MODE(1) | RXACTIVE},	/* MII2_TXCLK */
+	{OFFSET(gpmc_a7), MODE(1) | RXACTIVE},	/* MII2_RXCLK */
+	{OFFSET(gpmc_a8), MODE(1) | RXACTIVE},	/* MII2_RXD3 */
+	{OFFSET(gpmc_a9), MODE(1) | RXACTIVE},	/* MII2_RXD2 */
+	{OFFSET(gpmc_a10), MODE(1) | RXACTIVE},	/* MII2_RXD1 */
+	{OFFSET(gpmc_a11), MODE(1) | RXACTIVE},	/* MII2_RXD0 */
+	{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
+	{OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
+						/*
+						 * MII2_CRS is shared with
+						 * NAND_WAIT0
+						 */
+	{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
+	{-1},
+};
+#ifdef CONFIG_MTD_RAW_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+#endif
+static struct module_pin_mux gpIOs[] = {
+	/* GPIO0_6  (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
+	{OFFSET(spi0_cs1),  (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* TIMER5   (MMC0_DAT3) - TIMER5 (Buzzer) */
+	{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
+	/* TIMER6   (MMC0_DAT2) - PWM_BACK_3V3 */
+	{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_28 (MMC0_DAT1)	 - MII_nNAND */
+	{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_29 (MMC0_DAT0)	 - NAND_1n0 */
+	{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
+	{OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
+	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN  | RXACTIVE)},
+	/* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
+	{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
+	{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO2_0  (GPMC_nCS3) - DCOK */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/*
+	 * GPIO0_7 (PWW0 OUT)
+	 * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
+	 */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
+	{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO0_20 (DMA_INTR1) - REP-Switch */
+	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
+	{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+	/* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
+	{OFFSET(mcasp0_fsx),   (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+	/* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
+	{OFFSET(mcasp0_axr0),  (MODE(7) | PULLUDDIS) },
+	/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
+#ifndef CONFIG_MTD_RAW_NAND
+	/* GPIO2_3 - NAND_OE */
+	{OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+	/* GPIO2_4 - NAND_WEN */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+	/* GPIO2_5 - NAND_BE_CLE */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+#endif
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
+
+	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
+	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
+	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
+	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
+	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
+	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
+	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
+	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
+
+	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
+	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
+	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
+
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(mii2_pin_mux);
+#ifdef CONFIG_MTD_RAW_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_MMC)
+	configure_module_pin_mux(mmc1_pin_mux);
+#endif
+	configure_module_pin_mux(spi0_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(uart1_pin_mux);
+	configure_module_pin_mux(gpIOs);
+}
diff --git a/roms/u-boot/board/BuR/brppt2/Kconfig b/roms/u-boot/board/BuR/brppt2/Kconfig
new file mode 100644
index 000000000..aa39d66fb
--- /dev/null
+++ b/roms/u-boot/board/BuR/brppt2/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_BRPPT2
+
+config SYS_BOARD
+	default "brppt2"
+
+config SYS_VENDOR
+	default "BuR"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "brppt2"
+
+config SPL_DM_SPI
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/BuR/brppt2/MAINTAINERS b/roms/u-boot/board/BuR/brppt2/MAINTAINERS
new file mode 100644
index 000000000..a1b5bd49b
--- /dev/null
+++ b/roms/u-boot/board/BuR/brppt2/MAINTAINERS
@@ -0,0 +1,6 @@
+BUR_PPT2 BOARD
+M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S:	Maintained
+F:	board/BuR/brppt2/
+F:	include/configs/brppt2.h
+F:	configs/brppt2_defconfig
diff --git a/roms/u-boot/board/BuR/brppt2/Makefile b/roms/u-boot/board/BuR/brppt2/Makefile
new file mode 100644
index 000000000..7f3c7cd95
--- /dev/null
+++ b/roms/u-boot/board/BuR/brppt2/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+# Copyright (C) 2019
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+
+obj-y := ../common/common.o
+obj-y += board.o
diff --git a/roms/u-boot/board/BuR/brppt2/board.c b/roms/u-boot/board/BuR/brppt2/board.c
new file mode 100644
index 000000000..ee006f019
--- /dev/null
+++ b/roms/u-boot/board/BuR/brppt2/board.c
@@ -0,0 +1,546 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for BuR BRPPT2 board
+ *
+ * Copyright (C) 2019
+ * B&R Industrial Automation GmbH - http://www.br-automation.com/
+ *
+ */
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <spl.h>
+#include <dm.h>
+#include <miiphy.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#ifdef CONFIG_SPL_BUILD
+# include <asm/arch/mx6-ddr.h>
+#endif
+#include <asm/arch/clock.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define USBHUB_RSTN	IMX_GPIO_NR(1, 16)
+#define BKLT_EN		IMX_GPIO_NR(1, 15)
+#define CAPT_INT	IMX_GPIO_NR(4, 9)
+#define CAPT_RESETN	IMX_GPIO_NR(4, 11)
+#define SW_INTN		IMX_GPIO_NR(3, 26)
+#define VCCDISP_EN	IMX_GPIO_NR(5, 18)
+#define EMMC_RSTN	IMX_GPIO_NR(6, 8)
+#define PMIC_IRQN	IMX_GPIO_NR(5, 22)
+#define TASTER		IMX_GPIO_NR(5, 23)
+
+#define ETH0_LINK	IMX_GPIO_NR(1, 27)
+#define ETH1_LINK	IMX_GPIO_NR(1, 28)
+
+#define UART_PAD_CTRL		(PAD_CTL_PUS_47K_UP |			\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL		(PAD_CTL_PUS_47K_UP |			\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define ECSPI_PAD_CTRL		(PAD_CTL_PUS_100K_DOWN |		\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL		(PAD_CTL_PUS_47K_UP |			\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP |			\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL1		(PAD_CTL_PUS_100K_UP |			\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PU	(PAD_CTL_PUS_100K_UP |		\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK	((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) |	\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm |	\
+				PAD_CTL_SRE_FAST)
+
+#define GPIO_PAD_CTRL_PU	(PAD_CTL_PUS_100K_UP |			\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define GPIO_PAD_CTRL_PD	(PAD_CTL_PUS_100K_DOWN |		\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define LCDCMOS_PAD_CTRL	(PAD_CTL_PUS_100K_DOWN |		\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm |\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define MUXDESC(pad, ctrl)	IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl))
+
+#if !defined(CONFIG_SPL_BUILD)
+static iomux_v3_cfg_t const eth_pads[] = {
+	/*
+	 * Gigabit Ethernet
+	 */
+	/* CLKs */
+	MUXDESC(PAD_GPIO_16__ENET_REF_CLK,	ENET_PAD_CTRL_CLK),
+	MUXDESC(PAD_ENET_REF_CLK__ENET_TX_CLK,	ENET_PAD_CTRL_CLK),
+	/* MDIO */
+	MUXDESC(PAD_ENET_MDIO__ENET_MDIO,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_ENET_MDC__ENET_MDC,		ENET_PAD_CTRL_PU),
+	/* RGMII */
+	MUXDESC(PAD_RGMII_TXC__RGMII_TXC,	ENET_PAD_CTRL1),
+	MUXDESC(PAD_RGMII_TD0__RGMII_TD0,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_TD1__RGMII_TD1,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_TD2__RGMII_TD2,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_TD3__RGMII_TD3,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_TX_CTL__RGMII_TX_CTL,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_RXC__RGMII_RXC,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RD0__RGMII_RD0,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RD1__RGMII_RD1,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RD2__RGMII_RD2,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RD3__RGMII_RD3,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RX_CTL__RGMII_RX_CTL,	ENET_PAD_CTRL_PU),
+	/* ETH0_LINK */
+	MUXDESC(PAD_ENET_RXD0__GPIO1_IO27,	GPIO_PAD_CTRL_PD),
+	/* ETH1_LINK */
+	MUXDESC(PAD_ENET_TX_EN__GPIO1_IO28,	GPIO_PAD_CTRL_PD),
+};
+
+static iomux_v3_cfg_t const board_pads[] = {
+	/*
+	 * I2C #3, #4
+	 */
+	MUXDESC(PAD_GPIO_3__I2C3_SCL,		I2C_PAD_CTRL),
+	MUXDESC(PAD_GPIO_6__I2C3_SDA,		I2C_PAD_CTRL),
+
+	/*
+	 * UART#4 PADS
+	 * UART_Tasten
+	 */
+	MUXDESC(PAD_CSI0_DAT12__UART4_TX_DATA,	UART_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT13__UART4_RX_DATA,	UART_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT17__UART4_CTS_B,	UART_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT16__UART4_RTS_B,	UART_PAD_CTRL),
+	/*
+	 * ESCPI#1
+	 * M25P32 NOR-Flash
+	 */
+	MUXDESC(PAD_EIM_D16__ECSPI1_SCLK,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D17__ECSPI1_MISO,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D18__ECSPI1_MOSI,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D19__GPIO3_IO19,	ECSPI_PAD_CTRL),
+	/*
+	 * ESCPI#2
+	 * resTouch SPI ADC
+	 */
+	MUXDESC(PAD_CSI0_DAT8__ECSPI2_SCLK,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_OE__ECSPI2_MISO,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT9__ECSPI2_MOSI,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D24__GPIO3_IO24,	ECSPI_PAD_CTRL),
+	/*
+	 * USDHC#4
+	 */
+	MUXDESC(PAD_SD4_CLK__SD4_CLK,		USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_CMD__SD4_CMD,		USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT0__SD4_DATA0,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT1__SD4_DATA1,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT2__SD4_DATA2,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT3__SD4_DATA3,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT4__SD4_DATA4,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT5__SD4_DATA5,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT6__SD4_DATA6,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT7__SD4_DATA7,	USDHC_PAD_CTRL),
+	/*
+	 * USB OTG power & ID
+	 */
+	/* USB_OTG_5V_EN */
+	MUXDESC(PAD_EIM_D22__GPIO3_IO22,	GPIO_PAD_CTRL_PD),
+	MUXDESC(PAD_EIM_D31__GPIO3_IO31,	GPIO_PAD_CTRL_PD),
+	/* USB_OTG_JUMPER */
+	MUXDESC(PAD_ENET_RX_ER__USB_OTG_ID,	GPIO_PAD_CTRL_PD),
+	/*
+	 * PWM-Pins
+	 */
+	/* BKLT_CTL */
+	MUXDESC(PAD_SD1_CMD__PWM4_OUT,		GPIO_PAD_CTRL_PD),
+	/* SPEAKER */
+	MUXDESC(PAD_SD1_DAT1__PWM3_OUT,		GPIO_PAD_CTRL_PD),
+	/*
+	 * GPIOs
+	 */
+	/* USB_HUB_nRESET */
+	MUXDESC(PAD_SD1_DAT0__GPIO1_IO16,	GPIO_PAD_CTRL_PD),
+	/* BKLT_EN */
+	MUXDESC(PAD_SD2_DAT0__GPIO1_IO15,	GPIO_PAD_CTRL_PD),
+	/* capTouch_INT */
+	MUXDESC(PAD_KEY_ROW1__GPIO4_IO09,	GPIO_PAD_CTRL_PD),
+	/* capTouch_nRESET */
+	MUXDESC(PAD_KEY_ROW2__GPIO4_IO11,	GPIO_PAD_CTRL_PD),
+	/* SW_nINT */
+	MUXDESC(PAD_EIM_D26__GPIO3_IO26,	GPIO_PAD_CTRL_PU),
+	/* VCC_DISP_EN */
+	MUXDESC(PAD_CSI0_PIXCLK__GPIO5_IO18,	GPIO_PAD_CTRL_PD),
+	/* eMMC_nRESET */
+	MUXDESC(PAD_NANDF_ALE__GPIO6_IO08,	GPIO_PAD_CTRL_PD),
+	/* HWID*/
+	MUXDESC(PAD_NANDF_D0__GPIO2_IO00,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D1__GPIO2_IO01,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D2__GPIO2_IO02,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D3__GPIO2_IO03,	GPIO_PAD_CTRL_PU),
+	/* PMIC_nIRQ */
+	MUXDESC(PAD_CSI0_DAT4__GPIO5_IO22,	GPIO_PAD_CTRL_PU),
+	/* nTASTER */
+	MUXDESC(PAD_CSI0_DAT5__GPIO5_IO23,	GPIO_PAD_CTRL_PU),
+	/* RGB LCD Display */
+	MUXDESC(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DI0_PIN2__IPU1_DI0_PIN02,		LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DI0_PIN3__IPU1_DI0_PIN03,		LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DI0_PIN4__IPU1_DI0_PIN04,		LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DI0_PIN15__IPU1_DI0_PIN15,		LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT0__IPU1_DISP0_DATA00,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT1__IPU1_DISP0_DATA01,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT2__IPU1_DISP0_DATA02,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT3__IPU1_DISP0_DATA03,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT4__IPU1_DISP0_DATA04,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT5__IPU1_DISP0_DATA05,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT6__IPU1_DISP0_DATA06,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT7__IPU1_DISP0_DATA07,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT8__IPU1_DISP0_DATA08,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT9__IPU1_DISP0_DATA09,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT10__IPU1_DISP0_DATA10,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT11__IPU1_DISP0_DATA11,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT12__IPU1_DISP0_DATA12,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT13__IPU1_DISP0_DATA13,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT14__IPU1_DISP0_DATA14,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT15__IPU1_DISP0_DATA15,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT16__IPU1_DISP0_DATA16,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT17__IPU1_DISP0_DATA17,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT18__IPU1_DISP0_DATA18,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT19__IPU1_DISP0_DATA19,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT20__IPU1_DISP0_DATA20,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT21__IPU1_DISP0_DATA21,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT22__IPU1_DISP0_DATA22,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT23__IPU1_DISP0_DATA23,	LCDCMOS_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+	gpio_direction_output(USBHUB_RSTN, 1);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	ulong b_mode = 4;
+
+	if (gpio_get_value(TASTER) == 0)
+		b_mode = 12;
+
+	env_set_ulong("b_mode", b_mode);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	if (gpio_request(BKLT_EN, "BKLT_EN"))
+		printf("Warning: BKLT_EN setup failed\n");
+	gpio_direction_output(BKLT_EN, 0);
+
+	if (gpio_request(USBHUB_RSTN, "USBHUB_nRST"))
+		printf("Warning: USBHUB_nRST setup failed\n");
+	gpio_direction_output(USBHUB_RSTN, 0);
+
+	if (gpio_request(TASTER, "TASTER"))
+		printf("Warning: TASTER setup failed\n");
+	gpio_direction_input(TASTER);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	SETUP_IOMUX_PADS(board_pads);
+	SETUP_IOMUX_PADS(eth_pads);
+
+	/* set GPIO_16 as ENET_REF_CLK_OUT running at 25 MHz */
+	setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+	enable_fec_anatop_clock(0, ENET_25MHZ);
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+#else
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+	.dram_sdclk_0		= 0x00020030,
+	.dram_sdclk_1		= 0x00020030,
+	.dram_cas		= 0x00020030,
+	.dram_ras		= 0x00020030,
+	.dram_reset		= 0x00020030,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0		= 0x00003000,
+	.dram_sdcke1		= 0x00003000,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2		= 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 40 ohm */
+	.dram_sdodt0		= 0x00003030,
+	.dram_sdodt1		= 0x00003030,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.dram_sdqs0		= 0x00000030,
+	.dram_sdqs1		= 0x00000030,
+	.dram_sdqs2		= 0x00000030,
+	.dram_sdqs3		= 0x00000030,
+	.dram_sdqs4		= 0x00000030,
+	.dram_sdqs5		= 0x00000030,
+	.dram_sdqs6		= 0x00000030,
+	.dram_sdqs7		= 0x00000030,
+	/* DQM[0:7]: Differential input, 40 ohm */
+	.dram_dqm0		= 0x00020030,
+	.dram_dqm1		= 0x00020030,
+	.dram_dqm2		= 0x00020030,
+	.dram_dqm3		= 0x00020030,
+	.dram_dqm4		= 0x00020030,
+	.dram_dqm5		= 0x00020030,
+	.dram_dqm6		= 0x00020030,
+	.dram_dqm7		= 0x00020030,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+static struct mx6sdl_iomux_grp_regs grp_iomux_s = {
+	/* DDR3 */
+	.grp_ddr_type		= 0x000c0000,
+	.grp_ddrmode_ctl	= 0x00020000,
+	/* disable DDR pullups */
+	.grp_ddrpke		= 0x00000000,
+	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
+	.grp_addds		= 0x00000030,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+	.grp_ctlds		= 0x00000030,
+	/* DATA[00:63]: Differential input, 40 ohm */
+	.grp_ddrmode		= 0x00020000,
+	.grp_b0ds		= 0x00000030,
+	.grp_b1ds		= 0x00000030,
+	.grp_b2ds		= 0x00000030,
+	.grp_b3ds		= 0x00000030,
+	.grp_b4ds		= 0x00000030,
+	.grp_b5ds		= 0x00000030,
+	.grp_b6ds		= 0x00000030,
+	.grp_b7ds		= 0x00000030,
+};
+
+/*
+ * DDR3 desriptions - these are the memory chips we support
+ */
+
+/* NT5CC128M16FP-DII */
+static struct mx6_ddr3_cfg cfg_nt5cc128m16fp_dii = {
+	.mem_speed      = 1600,
+	.density        = 2,
+	.width          = 16,
+	.banks          = 8,
+	.rowaddr        = 14,
+	.coladdr        = 10,
+	.pagesz         = 2,
+	.trcd           = 1375,
+	.trcmin         = 4875,
+	.trasmin        = 3500,
+};
+
+/* measured on board TSERIES_ARM/1 V_LVDS_DL64 */
+static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x64_s = {
+	/* write leveling calibration determine, MR1-value = 0x0002 */
+	.p0_mpwldectrl0 = 0x003F003E,
+	.p0_mpwldectrl1 = 0x003A003A,
+	.p1_mpwldectrl0 = 0x001B001C,
+	.p1_mpwldectrl1 = 0x00190031,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0   = 0x02640264,
+	.p0_mpdgctrl1   = 0x02440250,
+	.p1_mpdgctrl0   = 0x02400250,
+	.p1_mpdgctrl1   = 0x0238023C,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl   = 0x40464644,
+	.p1_mprddlctl   = 0x464A4842,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl   = 0x38343034,
+	.p1_mpwrdlctl   = 0x36323830,
+};
+
+/* measured on board TSERIES_ARM/1 V_LVDS_S32 */
+static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x32_s = {
+	/* write leveling calibration determine, MR1-value = 0x0002 */
+	.p0_mpwldectrl0 = 0x00410043,
+	.p0_mpwldectrl1 = 0x003A003C,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0   = 0x023C0244,
+	.p0_mpdgctrl1   = 0x02240230,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl   = 0x484C4A48,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl   = 0x3C363434,
+};
+
+static void spl_dram_init(void)
+{
+	struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR;
+	u32 val, dram_strap = 0;
+	struct mx6_ddr3_cfg *mem = NULL;
+	struct mx6_mmdc_calibration *calib = NULL;
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize		= -1,	/* CPU type specific (overwritten) */
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density	= 32,	/* 32Gb per CS */
+		.ncs		= 1,	/* single chip select */
+		.cs1_mirror	= 0,
+		.rtt_wr		= 1,	/* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
+		.rtt_nom	= 1,	/* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
+		.walat		= 1,	/* Write additional latency */
+		.ralat		= 5,	/* Read additional latency */
+		.mif3_mode	= 3,	/* Command prediction working mode */
+		.bi_on		= 1,	/* Bank interleaving enabled */
+		.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.ddr_type	= 0,	/* DDR3 */
+	};
+
+	/*
+	 * MMDC Calibration requires the following data:
+	 *  mx6_mmdc_calibration - board-specific calibration (routing delays)
+	 *     these calibration values depend on board routing, SoC, and DDR
+	 *  mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
+	 *  mx6_ddr_cfg - chip specific timing/layout details
+	 */
+
+	/* setup HWID3-2 to input */
+	val = readl(&gpio->gpio_dir);
+	val &= ~(0x1 << 0 | 0x1 << 1);
+	writel(val, &gpio->gpio_dir);
+
+	/* read DRAM strapping from HWID3/2 (bit 1 and bit 0) */
+	dram_strap = readl(&gpio->gpio_psr) & 0x3;
+
+	switch (dram_strap) {
+	/* 1 GiB, 64 bit, 4 NT5CC128M16FP chips */
+	case 0:
+		puts("DRAM strap 00\n");
+		mem = &cfg_nt5cc128m16fp_dii;
+		sysinfo.dsize = 2;
+		calib = &cal_nt5cc128m16fp_dii_128x64_s;
+		break;
+	/* 512 MiB, 32 bit, 2 NT5CC128M16FP chips */
+	case 1:
+		puts("DRAM strap 01\n");
+		mem = &cfg_nt5cc128m16fp_dii;
+		sysinfo.dsize = 1;
+		calib = &cal_nt5cc128m16fp_dii_128x32_s;
+		break;
+	default:
+		printf("DRAM strap 0x%x (invalid)\n", dram_strap);
+		break;
+	}
+
+	if (!mem) {
+		puts("Error: Invalid Memory Configuration\n");
+		hang();
+	}
+	if (!calib) {
+		puts("Error: Invalid Board Calibration Configuration\n");
+		hang();
+	}
+
+	mx6sdl_dram_iocfg(16 << sysinfo.dsize,
+			  &ddr_iomux_s,
+			  &grp_iomux_s);
+
+	mx6_dram_cfg(&sysinfo, calib, mem);
+}
+
+static iomux_v3_cfg_t const board_pads_spl[] = {
+	/* UART#1 PADS */
+	MUXDESC(PAD_CSI0_DAT10__UART1_TX_DATA,	UART_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT11__UART1_RX_DATA,	UART_PAD_CTRL),
+	/* ESCPI#1 PADS */
+	MUXDESC(PAD_EIM_D16__ECSPI1_SCLK,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D17__ECSPI1_MISO,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D18__ECSPI1_MOSI,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D19__GPIO3_IO19,	ECSPI_PAD_CTRL),
+	/* USDHC#4 PADS */
+	MUXDESC(PAD_SD4_CLK__SD4_CLK,		USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_CMD__SD4_CMD,		USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT0__SD4_DATA0,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT1__SD4_DATA1,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT2__SD4_DATA2,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT3__SD4_DATA3,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT4__SD4_DATA4,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT5__SD4_DATA5,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT6__SD4_DATA6,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT7__SD4_DATA7,	USDHC_PAD_CTRL),
+	/* HWID*/
+	MUXDESC(PAD_NANDF_D0__GPIO2_IO00,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D1__GPIO2_IO01,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D2__GPIO2_IO02,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D3__GPIO2_IO03,	GPIO_PAD_CTRL_PU),
+};
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+}
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/*
+	 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
+	 * initializes DMA very early (before all board code), so the only
+	 * opportunity we have to initialize APBHDMA clocks is in SPL.
+	 * setbits_le32(&ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+	 */
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x00F0FC03, &ccm->CCGR1);
+	writel(0x0FFFF000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0030C3, &ccm->CCGR5);
+	writel(0x000003F0, &ccm->CCGR6);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+	arch_cpu_init();
+	timer_init();
+	gpr_init();
+
+	SETUP_IOMUX_PADS(board_pads_spl);
+	spl_dram_init();
+}
+
+void reset_cpu(void)
+{
+}
+#endif /* CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/BuR/brppt2/config.mk b/roms/u-boot/board/BuR/brppt2/config.mk
new file mode 100644
index 000000000..0d1638a97
--- /dev/null
+++ b/roms/u-boot/board/BuR/brppt2/config.mk
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/imx6dl-//')
+
+payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
+
+quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
+cmd_prodbin =								\
+	dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
+	dd conv=notrunc bs=1 if=SPL of=$@ seek=1024 2>/dev/null && \
+	dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
+
+quiet_cmd_prodzip = SAPZIP  $@
+cmd_prodzip =					\
+	test -d misc && rm -r misc;		\
+	mkdir misc &&				\
+	cp SPL misc/ &&				\
+	cp u-boot-dtb.img misc/ &&		\
+	zip -9 -r $@ misc/* >/dev/null $<
+
+ifeq ($(hw-platform-y),brppt2)
+ifneq ($(CONFIG_SPL_BUILD),y)
+INPUTS-y += $(hw-platform-y)_prog.bin
+INPUTS-y += $(hw-platform-y)_prod.zip
+endif
+endif
+
+$(hw-platform-y)_prog.bin: u-boot-dtb.img spl SPL
+	$(call if_changed,prodbin)
+
+$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
+	$(call if_changed,prodzip)
diff --git a/roms/u-boot/board/BuR/brsmarc1/Kconfig b/roms/u-boot/board/BuR/brsmarc1/Kconfig
new file mode 100644
index 000000000..6d3d7a2a2
--- /dev/null
+++ b/roms/u-boot/board/BuR/brsmarc1/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BRSMARC1
+
+config SYS_BOARD
+	default "brsmarc1"
+
+config SYS_VENDOR
+	default "BuR"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "brsmarc1"
+
+endif
diff --git a/roms/u-boot/board/BuR/brsmarc1/MAINTAINERS b/roms/u-boot/board/BuR/brsmarc1/MAINTAINERS
new file mode 100644
index 000000000..c6dfc20f4
--- /dev/null
+++ b/roms/u-boot/board/BuR/brsmarc1/MAINTAINERS
@@ -0,0 +1,6 @@
+BRSMARC1 BOARD
+M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S:	Maintained
+F:	board/BuR/brsmarc1/
+F:	include/configs/brsmarc1.h
+F:	configs/brsmarc1_defconfig
diff --git a/roms/u-boot/board/BuR/brsmarc1/Makefile b/roms/u-boot/board/BuR/brsmarc1/Makefile
new file mode 100644
index 000000000..1c3f64dea
--- /dev/null
+++ b/roms/u-boot/board/BuR/brsmarc1/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com/
+#
+
+obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-y	+= ../common/br_resetc.o
+obj-y	+= ../common/common.o
+obj-y	+= board.o
diff --git a/roms/u-boot/board/BuR/brsmarc1/board.c b/roms/u-boot/board/BuR/brsmarc1/board.c
new file mode 100644
index 000000000..738a5d2ff
--- /dev/null
+++ b/roms/u-boot/board/BuR/brsmarc1/board.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for B&R BRSMARC1 Board
+ *
+ * Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/emif.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+#include "../common/br_resetc.h"
+
+/* -------------------------------------------------------------------------*/
+/* -- defines for used GPIO Hardware -- */
+#define PER_RESET		(2 * 32 + 0)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC	(V_OSCK / 1000000)
+const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+	struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+
+	int rc;
+	/*
+	 * enable additional clocks of modules which are accessed later from
+	 * VxWorks OS
+	 */
+	u32 *const clk_domains[] = { 0 };
+	u32 *const clk_modules_specific[] = {
+		&cmwkup->wkup_adctscctrl,
+		&cmper->spi1clkctrl,
+		&cmper->dcan0clkctrl,
+		&cmper->dcan1clkctrl,
+		&cmper->timer4clkctrl,
+		&cmper->timer5clkctrl,
+		&cmper->lcdclkctrl,
+		&cmper->lcdcclkstctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_specific, 1);
+
+	/* setup I2C */
+	enable_i2c_pin_mux();
+
+	/* peripheral reset */
+	rc = gpio_request(PER_RESET, "PER_RESET");
+	if (rc != 0)
+		printf("cannot request PER_RESET GPIO!\n");
+
+	rc = gpio_direction_output(PER_RESET, 0);
+	if (rc != 0)
+		printf("cannot set PER_RESET GPIO!\n");
+
+	/* setup pmic */
+	pmicsetup(0, 0);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+	config_ddr(400, &ddr3_ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+#if !defined(CONFIG_SPL_BUILD)
+
+/* decision if backlight is switched on or not on powerup */
+int board_backlightstate(void)
+{
+	u8 bklmask, rstcause;
+	int rc = 0;
+
+	rc |= br_resetc_regget(RSTCTRL_SCRATCHREG1, &bklmask);
+	rc |= br_resetc_regget(RSTCTRL_ERSTCAUSE, &rstcause);
+
+	if (rc != 0) {
+		printf("%s: read rstctrl failed!\n", __func__);
+		return 1;
+	}
+
+	if ((rstcause & bklmask) != 0)
+		return 0;
+
+	return 1;
+}
+
+/* Basic board specific setup. run quite after relocation */
+int board_init(void)
+{
+	if (power_tps65217_init(0))
+		printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_BOARD_LATE_INIT)
+
+int board_late_init(void)
+{
+	br_resetc_bmode();
+
+	return 0;
+}
+
+#endif /* CONFIG_BOARD_LATE_INIT */
+#endif /* !CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/BuR/brsmarc1/config.mk b/roms/u-boot/board/BuR/brsmarc1/config.mk
new file mode 100644
index 000000000..1de971876
--- /dev/null
+++ b/roms/u-boot/board/BuR/brsmarc1/config.mk
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/am335x-//')
+
+payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
+
+quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
+cmd_prodbin =								\
+	dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
+	dd conv=notrunc bs=1 if=MLO.byteswap of=$@ seek=0 2>/dev/null && \
+	dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
+
+quiet_cmd_prodzip = SAPZIP  $@
+cmd_prodzip =					\
+	test -d misc && rm -r misc;		\
+	mkdir misc &&				\
+	cp MLO.byteswap misc/ &&		\
+	cp spl/u-boot-spl.bin misc/ &&		\
+	cp u-boot-dtb.img misc/ &&		\
+	zip -9 -r $@ misc/* >/dev/null $<
+
+INPUTS-y += $(hw-platform-y)_prog.bin
+INPUTS-y += $(hw-platform-y)_prod.zip
+
+$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/u-boot-spl.bin
+	$(call if_changed,prodbin)
+
+$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
+	$(call if_changed,prodzip)
diff --git a/roms/u-boot/board/BuR/brsmarc1/mux.c b/roms/u-boot/board/BuR/brsmarc1/mux.c
new file mode 100644
index 000000000..33c214d6b
--- /dev/null
+++ b/roms/u-boot/board/BuR/brsmarc1/mux.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1)
+ *
+ * Copyright (C) 2017 Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	/* SPI0_SCLK */
+	{OFFSET(spi0_sclk),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI0_D0 */
+	{OFFSET(spi0_d0),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI0_D1 */
+	{OFFSET(spi0_d1),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI0_CS0 */
+	{OFFSET(spi0_cs0),	MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	/* SPI0_CS1 */
+	{OFFSET(spi0_cs1),	MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux spi1_pin_mux[] = {
+	/* SPI1_SCLK */
+	{OFFSET(mcasp0_aclkx),	MODE(3) | PULLUDEN | RXACTIVE},
+	/* SPI1_D0 */
+	{OFFSET(mcasp0_fsx),	MODE(3) | PULLUDEN | RXACTIVE},
+	/* SPI1_D1 */
+	{OFFSET(mcasp0_axr0),	MODE(3) | PULLUDEN | RXACTIVE},
+	/* SPI1_CS0 */
+	{OFFSET(mcasp0_ahclkr),	MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	/* SPI1_CS1 */
+	{OFFSET(xdma_event_intr0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan0_pin_mux[] = {
+	/* DCAN0 TX */
+	{OFFSET(uart1_ctsn),	MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN0 RX */
+	{OFFSET(uart1_rtsn),	MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan1_pin_mux[] = {
+	/* DCAN1 TX */
+	{OFFSET(uart0_ctsn),	MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN1 RX */
+	{OFFSET(uart0_rtsn),	MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux gpios[] = {
+	/* GPIO0_7 - LVDS_EN */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+	/* GPIO0_20 - BKLT_PWM (timer7) */
+	{OFFSET(xdma_event_intr1), (MODE(4) | PULLUDDIS | PULLDOWN_EN)},
+	/* GPIO2_4 - DISON */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+	/* GPIO1_24 - RGB_EN */
+	{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+	/* GPIO1_28 - nPD */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUDEN | PULLUP_EN)},
+	/* GPIO2_5 - Watchdog */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+	/* GPIO2_0 - ResetOut */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},
+	/* GPIO2_2 - BKLT_EN */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+	/* GPIO1_17 - GPIO0 */
+	{OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_18 - GPIO1 */
+	{OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_19 - GPIO2 */
+	{OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_22 - GPIO3 */
+	{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_23 - GPIO4 */
+	{OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_25 - GPIO5 */
+	{OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_7 - GPIO6 */
+	{OFFSET(emu0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_8 - GPIO7 */
+	{OFFSET(emu1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_18 - GPIO8 */
+	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_19 - GPIO9 */
+	{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_20 - GPIO10 */
+	{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_21 - GPIO11 */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO2_28 - DRAM-strapping */
+	{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN)},
+	/* GPIO2_4 - not routed (Pin U6) */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO2_5 - not routed (Pin T6) */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO2_28 - not routed (Pin G15) */
+	{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_18 - not routed (Pin B12) */
+	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	{-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	/* UART0_RXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_TXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux uart234_pin_mux[] = {
+	/* UART2_RXD */
+	{OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART2_TXD */
+	{OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},
+
+	/* UART3_RXD */
+	{OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART3_TXD */
+	{OFFSET(mmc0_dat0), (MODE(3) | PULLUDEN)},
+	/* UART3_RTS */
+	{OFFSET(mmc0_cmd), (MODE(2) | PULLUDEN)},
+	/* UART3_CTS */
+	{OFFSET(mmc0_clk), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+
+	/* UART4_RXD */
+	{OFFSET(mii1_txd3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART4_TXD */
+	{OFFSET(mii1_txd2), (MODE(3) | PULLUDEN)},
+	/* UART4_RTS */
+	{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN)},
+	/* UART4_CTS */
+	{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+
+	{-1},
+};
+
+static struct module_pin_mux i2c_pin_mux[] = {
+	/* I2C0_DATA */
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C0_SCLK */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C1_DATA */
+	{OFFSET(uart1_rxd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C1_SCLK */
+	{OFFSET(uart1_txd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux eth_pin_mux[] = {
+	/* ETH1 */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* ETH1_REFCLK */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRSDV */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXER */
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TXD0 */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TXD1 */
+
+	/* ETH2 */
+	{OFFSET(mii1_col), MODE(1) | RXACTIVE},		/* ETH2_REFCLK */
+	{OFFSET(gpmc_wait0), MODE(3) | RXACTIVE},	/* RMII2_CRSDV */
+	{OFFSET(gpmc_wpn), MODE(3) | RXACTIVE},		/* RMII2_RXER */
+	{OFFSET(gpmc_a0), MODE(3)},			/* RMII2_TXEN */
+	{OFFSET(gpmc_a11), MODE(3) | RXACTIVE},		/* RMII2_RXD0 */
+	{OFFSET(gpmc_a10), MODE(3) | RXACTIVE},		/* RMII2_RXD1 */
+	{OFFSET(gpmc_a5), MODE(3)},			/* RMII2_TXD0 */
+	{OFFSET(gpmc_a4), MODE(3)},			/* RMII2_TXD1 */
+
+	/* gpio2_19, gpio 3_4, not connected on board */
+	{OFFSET(mii1_rxd2), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	{OFFSET(mii1_rxdv), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+
+	/* ETH Management */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},	/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},		/* MDIO_CLK */
+
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
+
+	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
+	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
+	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
+	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
+	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
+	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
+	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
+	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
+
+	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
+	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
+	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
+
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c_pin_mux(void)
+{
+	configure_module_pin_mux(i2c_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(eth_pin_mux);
+	configure_module_pin_mux(spi0_pin_mux);
+	configure_module_pin_mux(spi1_pin_mux);
+	configure_module_pin_mux(dcan0_pin_mux);
+	configure_module_pin_mux(dcan1_pin_mux);
+	configure_module_pin_mux(uart234_pin_mux);
+	configure_module_pin_mux(mmc1_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(gpios);
+}
diff --git a/roms/u-boot/board/BuR/brxre1/Kconfig b/roms/u-boot/board/BuR/brxre1/Kconfig
new file mode 100644
index 000000000..389e523f6
--- /dev/null
+++ b/roms/u-boot/board/BuR/brxre1/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BRXRE1
+
+config SYS_BOARD
+	default "brxre1"
+
+config SYS_VENDOR
+	default "BuR"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "brxre1"
+
+endif
diff --git a/roms/u-boot/board/BuR/brxre1/MAINTAINERS b/roms/u-boot/board/BuR/brxre1/MAINTAINERS
new file mode 100644
index 000000000..eb0fe8b28
--- /dev/null
+++ b/roms/u-boot/board/BuR/brxre1/MAINTAINERS
@@ -0,0 +1,7 @@
+BRXRE1 BOARD
+M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S:	Maintained
+F:	board/BuR/brxre1/
+F:	include/configs/brxre1.h
+F:	configs/brxre1_defconfig
+F:	arch/arm/dts/am335x-brxre1.dts
diff --git a/roms/u-boot/board/BuR/brxre1/Makefile b/roms/u-boot/board/BuR/brxre1/Makefile
new file mode 100644
index 000000000..1d224e9e7
--- /dev/null
+++ b/roms/u-boot/board/BuR/brxre1/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2014 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
+
+obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-y	+= ../common/br_resetc.o
+obj-y	+= ../common/common.o
+obj-y	+= board.o
diff --git a/roms/u-boot/board/BuR/brxre1/board.c b/roms/u-boot/board/BuR/brxre1/board.c
new file mode 100644
index 000000000..544e09f44
--- /dev/null
+++ b/roms/u-boot/board/BuR/brxre1/board.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for B&R BRXRE1 Board
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ */
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <dm.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+#include "../common/br_resetc.h"
+
+/* -------------------------------------------------------------------------*/
+/* -- defines for used GPIO Hardware -- */
+#define ESC_KEY					(0 + 19)
+#define LCD_PWR					(0 + 5)
+
+#define	RSTCTRL_FORCE_PWR_NEN			0x04
+#define	RSTCTRL_CAN_STB				0x40
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC	(V_OSCK / 1000000)
+const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	int rc;
+
+	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+	struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+	/*
+	 * enable additional clocks of modules which are accessed later from
+	 * VxWorks OS
+	 */
+	u32 *const clk_domains[] = { 0 };
+
+	u32 *const clk_modules_xre1specific[] = {
+		&cmwkup->wkup_adctscctrl,
+		&cmper->spi1clkctrl,
+		&cmper->dcan0clkctrl,
+		&cmper->dcan1clkctrl,
+		&cmper->epwmss0clkctrl,
+		&cmper->epwmss1clkctrl,
+		&cmper->epwmss2clkctrl,
+		&cmper->lcdclkctrl,
+		&cmper->lcdcclkstctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
+	/* power-OFF LCD-Display */
+	if (gpio_request(LCD_PWR, "LCD_PWR") != 0)
+		printf("cannot request gpio for LCD_PWR!\n");
+	else if (gpio_direction_output(LCD_PWR, 0) != 0)
+		printf("cannot set direction output on LCD_PWR!\n");
+
+	/* setup I2C */
+	enable_i2c_pin_mux();
+
+	/* power-ON 3V3 via Resetcontroller */
+	rc = br_resetc_regset(RSTCTRL_CTRLREG,
+			      RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB);
+	if (rc != 0)
+		printf("ERROR: cannot write to resetc (turn on PWR_nEN)!\n");
+
+	pmicsetup(0, 0);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+	config_ddr(400, &ddr3_ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	/* request common used gpios */
+	gpio_request(ESC_KEY, "boot-key");
+
+	if (power_tps65217_init(0))
+		printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+
+int board_boot_key(void)
+{
+	return gpio_get_value(ESC_KEY);
+}
+
+int board_late_init(void)
+{
+	char othbootargs[128];
+
+	br_resetc_bmode();
+
+	/* setup othbootargs for bootvx-command (vxWorks bootline) */
+#ifdef CONFIG_LCD
+	snprintf(othbootargs, sizeof(othbootargs),
+		 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
+		 (u32)gd->fb_base - 0x20,
+		 (u32)env_get_ulong("vx_memtop", 16, gd->fb_base - 0x20),
+		 (u32)env_get_ulong("vx_romfsbase", 16, 0),
+		 (u32)env_get_ulong("vx_romfssize", 16, 0));
+#else
+	snprintf(othbootargs, sizeof(othbootargs),
+		 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
+		 (u32)gd->relocaddr,
+		 (u32)env_get_ulong("vx_memtop", 16, gd->relocaddr),
+		 (u32)env_get_ulong("vx_romfsbase", 16, 0),
+		 (u32)env_get_ulong("vx_romfssize", 16, 0));
+#endif
+	env_set("othbootargs", othbootargs);
+	/*
+	 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
+	 * expect that vectors are there, original u-boot moves them to _start
+	 */
+	__asm__("ldr r0,=0x20000");
+	__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/roms/u-boot/board/BuR/brxre1/mux.c b/roms/u-boot/board/BuR/brxre1/mux.c
new file mode 100644
index 000000000..6c5ad891b
--- /dev/null
+++ b/roms/u-boot/board/BuR/brxre1/mux.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	/* SPI1_SCLK */
+	{OFFSET(spi0_sclk),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI1_D0 */
+	{OFFSET(spi0_d0),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI1_D1 */
+	{OFFSET(spi0_d1),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI1_CS0 */
+	{OFFSET(spi0_cs0),	MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	/* SPI1_CS1 */
+	{OFFSET(spi0_cs1),	MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan0_pin_mux[] = {
+	/* DCAN0 TX */
+	{OFFSET(uart1_ctsn),   MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN0 RX */
+	{OFFSET(uart1_rtsn),   MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan1_pin_mux[] = {
+	/* DCAN1 TX */
+	{OFFSET(uart1_rxd),   MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN1 RX */
+	{OFFSET(uart1_txd),   MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux gpios[] = {
+	/* GPIO0_7  (PWW0 OUT) - CAN TERM */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_19 (DMA_INTR0) - TA602 */
+	{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */
+	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
+	/* GPIO0_30 (GPMC_WAIT0) - TA601 */
+	{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
+	/* GPIO1_29 (gpmc_csn0) - MMC nRST */
+	{OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
+	/* GPIO2_0  (GPMC_nCS3)	- VBAT_OK */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/* GPIO2_2  (GPMC_nADV_ALE) - DCOK */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO2_4  (GPMC_nWE) - TST_BAST */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
+	/* GPIO2_5  (gpmc_be0n_cle) - DISPLAY_ON_OFF */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
+	/* GPIO3_16 (mcasp0_axr0) - ETH-LED green */
+	{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
+	{OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
+	{OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
+	{OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	{-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	/* UART0_CTS */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_RXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_TXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_col), MODE(0) | RXACTIVE},		/* MII1_COL */
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
+
+	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
+	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
+	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
+	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
+	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
+	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
+	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
+	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
+
+	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
+	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
+	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
+
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(spi0_pin_mux);
+	configure_module_pin_mux(dcan0_pin_mux);
+	configure_module_pin_mux(dcan1_pin_mux);
+	configure_module_pin_mux(mmc1_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(gpios);
+}
diff --git a/roms/u-boot/board/BuR/common/br_resetc.c b/roms/u-boot/board/BuR/common/br_resetc.c
new file mode 100644
index 000000000..5006687fb
--- /dev/null
+++ b/roms/u-boot/board/BuR/common/br_resetc.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * common reset-controller functions for B&R boards
+ *
+ * Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com/ *
+ */
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <i2c.h>
+#include <dm/uclass.h>
+#include <linux/delay.h>
+#include "br_resetc.h"
+
+/* I2C Address of controller */
+#define	RSTCTRL_ADDR_PSOC	0x75
+#define	RSTCTRL_ADDR_STM32	0x60
+
+#define BMODE_DEFAULTAR		0
+#define BMODE_SERVICE		2
+#define BMODE_RUN		4
+#define BMODE_PME		12
+#define BMODE_DIAG		15
+
+#if CONFIG_IS_ENABLED(LCD) && !CONFIG_IS_ENABLED(DM_VIDEO)
+#include <lcd.h>
+#define LCD_SETCURSOR(x, y)	lcd_position_cursor(x, y)
+#define LCD_PUTS(x)		lcd_puts(x)
+#else
+#define LCD_SETCURSOR(x, y)
+#define LCD_PUTS(x)
+#endif /* CONFIG_LCD */
+
+static const char *bootmodeascii[16] = {
+	"BOOT",		"reserved",	"reserved",	"reserved",
+	"RUN",		"reserved",	"reserved",	"reserved",
+	"reserved",	"reserved",	"reserved",	"reserved",
+	"PME",		"reserved",	"reserved",	"DIAG",
+};
+
+struct br_reset_t {
+	struct udevice *i2cdev;
+	u8 is_psoc;
+};
+
+static struct br_reset_t resetc;
+
+__weak int board_boot_key(void)
+{
+	return 0;
+}
+
+__weak void board_boot_led(unsigned int on)
+{
+}
+
+static int resetc_init(void)
+{
+	struct udevice *i2cbus;
+	int rc;
+
+	rc = uclass_get_device_by_seq(UCLASS_I2C, 0, &i2cbus);
+	if (rc) {
+		printf("Cannot find I2C bus #0!\n");
+		return -1;
+	}
+
+	resetc.is_psoc = 1;
+	rc = dm_i2c_probe(i2cbus,
+			  RSTCTRL_ADDR_PSOC, 0, &resetc.i2cdev);
+	if (rc) {
+		resetc.is_psoc = 0;
+		rc = dm_i2c_probe(i2cbus,
+				  RSTCTRL_ADDR_STM32, 0, &resetc.i2cdev);
+	}
+
+	if (rc)
+		printf("Warning: cannot probe BuR resetcontroller!\n");
+
+	return rc;
+}
+
+int br_resetc_regget(u8 reg, u8 *dst)
+{
+	int rc = 0;
+
+	if (!resetc.i2cdev)
+		rc = resetc_init();
+
+	if (rc != 0)
+		return rc;
+
+	return dm_i2c_read(resetc.i2cdev, reg, dst, 1);
+}
+
+int br_resetc_regset(u8 reg, u8 val)
+{
+	int rc = 0;
+	u16 regw = (val << 8) | val;
+
+	if (!resetc.i2cdev)
+		rc = resetc_init();
+
+	if (rc != 0)
+		return rc;
+
+	if (resetc.is_psoc)
+		return dm_i2c_write(resetc.i2cdev, reg, (u8 *)&regw, 2);
+
+	return dm_i2c_write(resetc.i2cdev, reg, (u8 *)&regw, 1);
+}
+
+int br_resetc_bmode(void)
+{
+	int rc = 0;
+	u16 regw;
+	u8 regb, scr;
+	int cnt;
+	unsigned int bmode = 0;
+
+	if (!resetc.i2cdev)
+		rc = resetc_init();
+
+	if (rc != 0)
+		return rc;
+
+	rc = dm_i2c_read(resetc.i2cdev, RSTCTRL_ENHSTATUS, &regb, 1);
+	if (rc != 0) {
+		printf("WARN: cannot read ENHSTATUS from resetcontroller!\n");
+		return -1;
+	}
+
+	rc = dm_i2c_read(resetc.i2cdev, RSTCTRL_SCRATCHREG0, &scr, 1);
+	if (rc != 0) {
+		printf("WARN: cannot read SCRATCHREG from resetcontroller!\n");
+		return -1;
+	}
+
+	board_boot_led(1);
+
+	/* special bootmode from resetcontroller */
+	if (regb & 0x4) {
+		bmode = BMODE_DIAG;
+	} else if (regb & 0x8) {
+		bmode = BMODE_DEFAULTAR;
+	} else if (board_boot_key() != 0) {
+		cnt = 4;
+		do {
+			LCD_SETCURSOR(1, 8);
+			switch (cnt) {
+			case 4:
+				LCD_PUTS
+				("release KEY to enter SERVICE-mode.     ");
+				break;
+			case 3:
+				LCD_PUTS
+				("release KEY to enter DIAGNOSE-mode.    ");
+				break;
+			case 2:
+				LCD_PUTS
+				("release KEY to enter BOOT-mode.        ");
+				break;
+			}
+			mdelay(1000);
+			cnt--;
+			if (board_boot_key() == 0)
+				break;
+		} while (cnt);
+
+		switch (cnt) {
+		case 0:
+			bmode = BMODE_PME;
+			break;
+		case 1:
+			bmode = BMODE_DEFAULTAR;
+			break;
+		case 2:
+			bmode = BMODE_DIAG;
+			break;
+		case 3:
+			bmode = BMODE_SERVICE;
+			break;
+		}
+	} else if ((regb & 0x1) || scr == 0xCC) {
+		bmode = BMODE_PME;
+	} else {
+		bmode = BMODE_RUN;
+	}
+
+	LCD_SETCURSOR(1, 8);
+
+	switch (bmode) {
+	case BMODE_PME:
+		LCD_PUTS("entering PME-Mode (netscript).         ");
+		regw = 0x0C0C;
+		break;
+	case BMODE_DEFAULTAR:
+		LCD_PUTS("entering BOOT-mode.                    ");
+		regw = 0x0000;
+		break;
+	case BMODE_DIAG:
+		LCD_PUTS("entering DIAGNOSE-mode.                ");
+		regw = 0x0F0F;
+		break;
+	case BMODE_SERVICE:
+		LCD_PUTS("entering SERVICE mode.                 ");
+		regw = 0xB4B4;
+		break;
+	case BMODE_RUN:
+		LCD_PUTS("loading OS...                          ");
+		regw = 0x0404;
+		break;
+	}
+
+	board_boot_led(0);
+
+	if (resetc.is_psoc)
+		rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
+				  (u8 *)&regw, 2);
+	else
+		rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
+				  (u8 *)&regw, 1);
+
+	if (rc != 0)
+		printf("WARN: cannot write into resetcontroller!\n");
+
+	if (resetc.is_psoc)
+		printf("Reset: PSOC controller\n");
+	else
+		printf("Reset: STM32 controller\n");
+
+	printf("Mode:  %s\n", bootmodeascii[regw & 0x0F]);
+	env_set_ulong("b_mode", regw & 0x0F);
+
+	return rc;
+}
diff --git a/roms/u-boot/board/BuR/common/br_resetc.h b/roms/u-boot/board/BuR/common/br_resetc.h
new file mode 100644
index 000000000..ba0689bf2
--- /dev/null
+++ b/roms/u-boot/board/BuR/common/br_resetc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * common reset-controller functions for B&R boards
+ *
+ * Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com/ *
+ */
+#ifndef __CONFIG_BRRESETC_H__
+#define __CONFIG_BRRESETC_H__
+#include <common.h>
+
+int br_resetc_regget(u8 reg, u8 *dst);
+int br_resetc_regset(u8 reg, u8 val);
+int br_resetc_bmode(void);
+
+/* reset controller register defines */
+#define RSTCTRL_CTRLREG		0x01
+#define RSTCTRL_SCRATCHREG0	0x04
+#define RSTCTRL_ENHSTATUS	0x07
+#define RSTCTRL_SCRATCHREG1	0x08
+#define RSTCTRL_RSTCAUSE	0x00
+#define RSTCTRL_ERSTCAUSE	0x09
+#define RSTCTRL_SPECGPIO_I	0x0A
+#define RSTCTRL_SPECGPIO_O	0x0B
+
+#endif /* __CONFIG_BRRESETC_H__ */
diff --git a/roms/u-boot/board/BuR/common/bur_common.h b/roms/u-boot/board/BuR/common/bur_common.h
new file mode 100644
index 000000000..79c9af146
--- /dev/null
+++ b/roms/u-boot/board/BuR/common/bur_common.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * bur_comon.h
+ *
+ * common board information header for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ */
+
+#ifndef _BUR_COMMON_H_
+#define _BUR_COMMON_H_
+
+#if !CONFIG_IS_ENABLED(DM_VIDEO)
+#include <../../../drivers/video/ti/am335x-fb.h>
+
+int load_lcdtiming(struct am335x_lcdpanel *panel);
+#endif
+
+void br_summaryscreen(void);
+void pmicsetup(u32 mpupll, unsigned int bus);
+void enable_uart0_pin_mux(void);
+void enable_i2c_pin_mux(void);
+void enable_board_pin_mux(void);
+int board_eth_init(struct bd_info *bis);
+
+int brdefaultip_setup(int bus, int chip);
+
+#endif
diff --git a/roms/u-boot/board/BuR/common/common.c b/roms/u-boot/board/BuR/common/common.c
new file mode 100644
index 000000000..78bf7d622
--- /dev/null
+++ b/roms/u-boot/board/BuR/common/common.c
@@ -0,0 +1,404 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * common.c
+ *
+ * common board functions for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ */
+#include <log.h>
+#include <version.h>
+#include <common.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <lcd.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include "bur_common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* --------------------------------------------------------------------------*/
+#if defined(CONFIG_LCD) && defined(CONFIG_AM335X_LCD) && \
+	!defined(CONFIG_DM_VIDEO) && !defined(CONFIG_SPL_BUILD)
+#include <asm/arch/hardware.h>
+#include <asm/arch/cpu.h>
+#include <asm/gpio.h>
+#include <power/tps65217.h>
+#include "../../../drivers/video/ti/am335x-fb.h"
+
+void lcdbacklight(int on)
+{
+	unsigned int driver = env_get_ulong("ds1_bright_drv", 16, 0UL);
+	unsigned int bright = env_get_ulong("ds1_bright_def", 10, 50);
+	unsigned int pwmfrq = env_get_ulong("ds1_pwmfreq", 10, ~0UL);
+	unsigned int tmp;
+	struct gptimer *timerhw;
+
+	if (on)
+		bright = bright != ~0UL ? bright : 50;
+	else
+		bright = 0;
+
+	switch (driver) {
+	case 2:
+		timerhw = (struct gptimer *)DM_TIMER5_BASE;
+		break;
+	default:
+		timerhw = (struct gptimer *)DM_TIMER6_BASE;
+	}
+
+	switch (driver) {
+	case 0:	/* PMIC LED-Driver */
+		/* brightness level */
+		tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+				   TPS65217_WLEDCTRL2, bright, 0xFF);
+		/* current sink */
+		tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+				   TPS65217_WLEDCTRL1,
+				   bright != 0 ? 0x0A : 0x02,
+				   0xFF);
+		break;
+	case 1:
+	case 2: /* PWM using timer */
+		if (pwmfrq != ~0UL) {
+			timerhw->tiocp_cfg = TCFG_RESET;
+			udelay(10);
+			while (timerhw->tiocp_cfg & TCFG_RESET)
+				;
+			tmp = ~0UL-(V_OSCK/pwmfrq);	/* bottom value */
+			timerhw->tldr = tmp;
+			timerhw->tcrr = tmp;
+			tmp = tmp + ((V_OSCK/pwmfrq)/100) * bright;
+			timerhw->tmar = tmp;
+			timerhw->tclr = (TCLR_PT | (2 << TCLR_TRG_SHIFT) |
+					TCLR_CE | TCLR_AR | TCLR_ST);
+		} else {
+			puts("invalid pwmfrq in env/dtb! skip PWM-setup.\n");
+		}
+		break;
+	default:
+		puts("no suitable backlightdriver in env/dtb!\n");
+		break;
+	}
+}
+
+int load_lcdtiming(struct am335x_lcdpanel *panel)
+{
+	struct am335x_lcdpanel pnltmp;
+
+	pnltmp.hactive = env_get_ulong("ds1_hactive", 10, ~0UL);
+	pnltmp.vactive = env_get_ulong("ds1_vactive", 10, ~0UL);
+	pnltmp.bpp = env_get_ulong("ds1_bpp", 10, ~0UL);
+	pnltmp.hfp = env_get_ulong("ds1_hfp", 10, ~0UL);
+	pnltmp.hbp = env_get_ulong("ds1_hbp", 10, ~0UL);
+	pnltmp.hsw = env_get_ulong("ds1_hsw", 10, ~0UL);
+	pnltmp.vfp = env_get_ulong("ds1_vfp", 10, ~0UL);
+	pnltmp.vbp = env_get_ulong("ds1_vbp", 10, ~0UL);
+	pnltmp.vsw = env_get_ulong("ds1_vsw", 10, ~0UL);
+	pnltmp.pxl_clk = env_get_ulong("ds1_pxlclk", 10, ~0UL);
+	pnltmp.pol = env_get_ulong("ds1_pol", 16, ~0UL);
+	pnltmp.pup_delay = env_get_ulong("ds1_pupdelay", 10, ~0UL);
+	pnltmp.pon_delay = env_get_ulong("ds1_tondelay", 10, ~0UL);
+	panel_info.vl_rot = env_get_ulong("ds1_rotation", 10, 0);
+
+	if (
+	   ~0UL == (pnltmp.hactive) ||
+	   ~0UL == (pnltmp.vactive) ||
+	   ~0UL == (pnltmp.bpp) ||
+	   ~0UL == (pnltmp.hfp) ||
+	   ~0UL == (pnltmp.hbp) ||
+	   ~0UL == (pnltmp.hsw) ||
+	   ~0UL == (pnltmp.vfp) ||
+	   ~0UL == (pnltmp.vbp) ||
+	   ~0UL == (pnltmp.vsw) ||
+	   ~0UL == (pnltmp.pxl_clk) ||
+	   ~0UL == (pnltmp.pol) ||
+	   ~0UL == (pnltmp.pup_delay) ||
+	   ~0UL == (pnltmp.pon_delay)
+	   ) {
+		puts("lcd-settings in env/dtb incomplete!\n");
+		printf("display-timings:\n"
+			"================\n"
+			"hactive: %d\n"
+			"vactive: %d\n"
+			"bpp    : %d\n"
+			"hfp    : %d\n"
+			"hbp    : %d\n"
+			"hsw    : %d\n"
+			"vfp    : %d\n"
+			"vbp    : %d\n"
+			"vsw    : %d\n"
+			"pxlclk : %d\n"
+			"pol    : 0x%08x\n"
+			"pondly : %d\n",
+			pnltmp.hactive, pnltmp.vactive, pnltmp.bpp,
+			pnltmp.hfp, pnltmp.hbp, pnltmp.hsw,
+			pnltmp.vfp, pnltmp.vbp, pnltmp.vsw,
+			pnltmp.pxl_clk, pnltmp.pol, pnltmp.pon_delay);
+
+		return -1;
+	}
+	debug("lcd-settings in env complete, taking over.\n");
+	memcpy((void *)panel,
+	       (void *)&pnltmp,
+	       sizeof(struct am335x_lcdpanel));
+
+	return 0;
+}
+
+static void br_summaryscreen_printenv(char *prefix,
+				       char *name, char *altname,
+				       char *suffix)
+{
+	char *envval = env_get(name);
+	if (0 != envval) {
+		lcd_printf("%s %s %s", prefix, envval, suffix);
+	} else if (0 != altname) {
+		envval = env_get(altname);
+		if (0 != envval)
+			lcd_printf("%s %s %s", prefix, envval, suffix);
+	} else {
+		lcd_printf("\n");
+	}
+}
+
+void br_summaryscreen(void)
+{
+	br_summaryscreen_printenv(" - B&R -", "br_orderno", 0, "-\n");
+	br_summaryscreen_printenv(" Serial/Rev :", "br_serial", 0, "\n");
+	br_summaryscreen_printenv(" MAC1       :", "br_mac1", "ethaddr", "\n");
+	br_summaryscreen_printenv(" MAC2       :", "br_mac2", 0, "\n");
+	lcd_puts(" Bootloader : " PLAIN_VERSION "\n");
+	lcd_puts("\n");
+}
+
+void lcdpower(int on)
+{
+	u32 pin, swval, i;
+	char buf[16] = { 0 };
+
+	pin = env_get_ulong("ds1_pwr", 16, ~0UL);
+
+	if (pin == ~0UL) {
+		puts("no pwrpin in dtb/env, cannot powerup display!\n");
+		return;
+	}
+
+	for (i = 0; i < 3; i++) {
+		if (pin != 0) {
+			snprintf(buf, sizeof(buf), "ds1_pwr#%d", i);
+			if (gpio_request(pin & 0x7F, buf) != 0) {
+				printf("%s: not able to request gpio %s",
+				       __func__, buf);
+				continue;
+			}
+			swval = pin & 0x80 ? 0 : 1;
+			if (on)
+				gpio_direction_output(pin & 0x7F, swval);
+			else
+				gpio_direction_output(pin & 0x7F, !swval);
+
+			debug("switched pin %d to %d\n", pin & 0x7F, swval);
+		}
+		pin >>= 8;
+	}
+}
+
+vidinfo_t	panel_info = {
+		.vl_col = 1366,	/*
+				 * give full resolution for allocating enough
+				 * memory
+				 */
+		.vl_row = 768,
+		.vl_bpix = 5,
+		.priv = 0
+};
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	struct am335x_lcdpanel lcd_panel;
+
+	memset(&lcd_panel, 0, sizeof(struct am335x_lcdpanel));
+	if (load_lcdtiming(&lcd_panel) != 0)
+		return;
+
+	lcd_panel.panel_power_ctrl = &lcdpower;
+
+	if (0 != am335xfb_init(&lcd_panel))
+		printf("ERROR: failed to initialize video!");
+	/*
+	 * modifiy panel info to 'real' resolution, to operate correct with
+	 * lcd-framework.
+	 */
+	panel_info.vl_col = lcd_panel.hactive;
+	panel_info.vl_row = lcd_panel.vactive;
+
+	lcd_set_flush_dcache(1);
+}
+
+void lcd_enable(void)
+{
+	br_summaryscreen();
+	lcdbacklight(1);
+}
+#endif /* CONFIG_LCD */
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int nodeoffset;
+
+	nodeoffset = fdt_path_offset(blob, "/factory-settings");
+	if (nodeoffset < 0) {
+		printf("%s: cannot find /factory-settings, trying /fset\n",
+		       __func__);
+		nodeoffset = fdt_path_offset(blob, "/fset");
+		if (nodeoffset < 0) {
+			printf("%s: cannot find /fset.\n", __func__);
+			return 0;
+		}
+	}
+
+	if (fdt_setprop(blob, nodeoffset, "bl-version",
+			PLAIN_VERSION, strlen(PLAIN_VERSION)) != 0) {
+		printf("%s: no 'bl-version' prop in fdt!\n", __func__);
+		return 0;
+	}
+	return 0;
+}
+
+int brdefaultip_setup(int bus, int chip)
+{
+	int rc;
+	struct udevice *i2cdev;
+	u8 u8buf = 0;
+	char defip[256] = { 0 };
+
+	rc = i2c_get_chip_for_busnum(bus, chip, 2, &i2cdev);
+	if (rc != 0) {
+		printf("WARN: cannot probe baseboard EEPROM!\n");
+		return -1;
+	}
+
+	rc = dm_i2c_read(i2cdev, 0, &u8buf, 1);
+	if (rc != 0) {
+		printf("WARN: cannot read baseboard EEPROM!\n");
+		return -1;
+	}
+
+	if (u8buf != 0xFF)
+		snprintf(defip, sizeof(defip),
+			 "if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.%d; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;",
+			 u8buf);
+	else
+		strncpy(defip,
+			"if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;",
+			sizeof(defip));
+
+	env_set("brdefaultip", defip);
+	env_set_hex("board_id", u8buf);
+
+	return 0;
+}
+
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_AM33XX)
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <power/tps65217.h>
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+void pmicsetup(u32 mpupll, unsigned int bus)
+{
+	int mpu_vdd;
+	int usb_cur_lim;
+
+	if (power_tps65217_init(bus)) {
+		printf("WARN: cannot setup PMIC 0x24 @ bus #%d, not found!.\n",
+		       bus);
+		return;
+	}
+
+	/* Get the frequency which is defined by device fuses */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+	printf("detected max. frequency: %d - ", dpll_mpu_opp100.m);
+
+	if (0 != mpupll) {
+		dpll_mpu_opp100.m = mpupll;
+		printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m);
+	} else {
+		puts("ok.\n");
+	}
+	/*
+	 * Increase USB current limit to 1300mA or 1800mA and set
+	 * the MPU voltage controller as needed.
+	 */
+	if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+	} else {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+	}
+
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
+			       usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set DCDC3 (CORE) voltage to 1.125V */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+				    TPS65217_DCDC_VOLT_SEL_1125MV)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set LDO3 to 1.8V */
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS1,
+			       TPS65217_LDO_VOLTAGE_OUT_1_8,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+	/* Set LDO4 to 3.3V */
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS2,
+			       TPS65217_LDO_VOLTAGE_OUT_3_3,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+	/* Set PWR_EN bit in Status Register */
+	tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+			   TPS65217_STATUS, TPS65217_PWR_OFF, TPS65217_PWR_OFF);
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+#endif /* CONFIG_SPL_BUILD && CONFIG_AM33XX */
diff --git a/roms/u-boot/board/BuS/eb_cpu5282/Kconfig b/roms/u-boot/board/BuS/eb_cpu5282/Kconfig
new file mode 100644
index 000000000..237dc1b5c
--- /dev/null
+++ b/roms/u-boot/board/BuS/eb_cpu5282/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EB_CPU5282
+
+config SYS_CPU
+	default "mcf52x2"
+
+config SYS_BOARD
+	default "eb_cpu5282"
+
+config SYS_VENDOR
+	default "BuS"
+
+config SYS_CONFIG_NAME
+	default "eb_cpu5282"
+
+endif
diff --git a/roms/u-boot/board/BuS/eb_cpu5282/MAINTAINERS b/roms/u-boot/board/BuS/eb_cpu5282/MAINTAINERS
new file mode 100644
index 000000000..87298ad9f
--- /dev/null
+++ b/roms/u-boot/board/BuS/eb_cpu5282/MAINTAINERS
@@ -0,0 +1,7 @@
+EB_CPU5282 BOARD
+M:	Jens Scharsig <esw@bus-elektronik.de>
+S:	Maintained
+F:	board/BuS/eb_cpu5282/
+F:	include/configs/eb_cpu5282.h
+F:	configs/eb_cpu5282_defconfig
+F:	configs/eb_cpu5282_internal_defconfig
diff --git a/roms/u-boot/board/BuS/eb_cpu5282/Makefile b/roms/u-boot/board/BuS/eb_cpu5282/Makefile
new file mode 100644
index 000000000..10026ee0e
--- /dev/null
+++ b/roms/u-boot/board/BuS/eb_cpu5282/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= eb_cpu5282.o
diff --git a/roms/u-boot/board/BuS/eb_cpu5282/eb_cpu5282.c b/roms/u-boot/board/BuS/eb_cpu5282/eb_cpu5282.c
new file mode 100644
index 000000000..153ed0e96
--- /dev/null
+++ b/roms/u-boot/board/BuS/eb_cpu5282/eb_cpu5282.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2005-2009
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/global_data.h>
+#include "asm/m5282.h"
+#include <bmp_layout.h>
+#include <env.h>
+#include <init.h>
+#include <status_led.h>
+#include <bus_vcxk.h>
+
+/*---------------------------------------------------------------------------*/
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if IS_ENABLED(CONFIG_VIDEO_VCXK)
+unsigned long display_width;
+unsigned long display_height;
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+int checkboard (void)
+{
+	puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n");
+#if (CONFIG_SYS_TEXT_BASE ==  CONFIG_SYS_INT_FLASH_BASE)
+	puts("       Boot from Internal FLASH\n");
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	int size, i;
+
+	size = 0;
+	MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 |
+			MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4);
+	asm (" nop");
+#ifdef CONFIG_SYS_SDRAM_BASE0
+	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)|
+		MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) |
+		MCFSDRAMC_DACR_PS_32;
+	asm (" nop");
+
+	MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
+	asm (" nop");
+
+	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
+	asm (" nop");
+	for (i = 0; i < 10; i++)
+		asm (" nop");
+
+	*(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
+	asm (" nop");
+	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
+	asm (" nop");
+
+	for (i = 0; i < 2000; i++)
+		asm (" nop");
+
+	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
+	asm (" nop");
+	/* write SDRAM mode register */
+	*(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
+	asm (" nop");
+	size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024;
+#endif
+#ifdef CONFIG_SYS_SDRAM_BASE1xx
+	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
+			| MCFSDRAMC_DACR_CASL (1)
+			| MCFSDRAMC_DACR_CBM (3)
+			| MCFSDRAMC_DACR_PS_16;
+
+	MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
+
+	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
+
+	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
+	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
+
+	for (i = 0; i < 2000; i++)
+		asm (" nop");
+
+	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
+	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
+	size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
+#endif
+	gd->ram_size = size;
+
+	return 0;
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram(void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_HW_WATCHDOG)
+
+void hw_watchdog_init(void)
+{
+	char *s;
+	int enable;
+
+	enable = 1;
+	s = env_get("watchdog");
+	if (s != NULL)
+		if ((strncmp(s, "off", 3) == 0) || (strncmp(s, "0", 1) == 0))
+			enable = 0;
+	if (enable)
+		MCFGPTA_GPTDDR  |= (1<<2);
+	else
+		MCFGPTA_GPTDDR  &= ~(1<<2);
+}
+
+void hw_watchdog_reset(void)
+{
+	MCFGPTA_GPTPORT  ^= (1<<2);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef	CONFIG_HW_WATCHDOG
+	hw_watchdog_init();
+#endif
+	return 1;
+}
+
+void __led_toggle(led_id_t mask)
+{
+	MCFGPTA_GPTPORT ^= (1 << 3);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+	__led_set(mask, state);
+	MCFGPTA_GPTDDR  |= (1 << 3);
+}
+
+void __led_set(led_id_t mask, int state)
+{
+	if (state == CONFIG_LED_STATUS_ON)
+		MCFGPTA_GPTPORT |= (1 << 3);
+	else
+		MCFGPTA_GPTPORT &= ~(1 << 3);
+}
+
+#if IS_ENABLED(CONFIG_VIDEO_VCXK)
+int drv_video_init(void)
+{
+	char *s;
+#ifdef CONFIG_SPLASH_SCREEN
+	unsigned long splash;
+#endif
+	printf("Init Video as ");
+	s = env_get("displaywidth");
+	if (s != NULL)
+		display_width = simple_strtoul(s, NULL, 10);
+	else
+		display_width = 256;
+
+	s = env_get("displayheight");
+	if (s != NULL)
+		display_height = simple_strtoul(s, NULL, 10);
+	else
+		display_height = 256;
+
+	printf("%lu x %lu pixel matrix\n", display_width, display_height);
+
+	MCFCCM_CCR &= ~MCFCCM_CCR_SZEN;
+	MCFGPIO_PEPAR &= ~MCFGPIO_PEPAR_PEPA2;
+
+	vcxk_init(display_width, display_height);
+
+#ifdef CONFIG_SPLASH_SCREEN
+	s = env_get("splashimage");
+	if (s != NULL) {
+		splash = simple_strtoul(s, NULL, 16);
+		vcxk_acknowledge_wait();
+		video_display_bitmap(splash, 0, 0);
+	}
+#endif
+	return 0;
+}
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#if IS_ENABLED(CONFIG_VIDEO_VCXK)
+int do_brightness(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int rcode = 0;
+	ulong side;
+	ulong bright;
+
+	switch (argc) {
+	case 3:
+		side = simple_strtoul(argv[1], NULL, 10);
+		bright = simple_strtoul(argv[2], NULL, 10);
+		if ((side >= 0) && (side <= 3) &&
+			(bright >= 0) && (bright <= 1000)) {
+			vcxk_setbrightness(side, bright);
+			rcode = 0;
+		} else {
+			printf("parameters out of range\n");
+			printf("Usage:\n%s\n", cmdtp->usage);
+			rcode = 1;
+		}
+		break;
+	default:
+		printf("Usage:\n%s\n", cmdtp->usage);
+		rcode = 1;
+		break;
+	}
+	return rcode;
+}
+
+/*---------------------------------------------------------------------------*/
+
+U_BOOT_CMD(
+	bright,	3,	0,	do_brightness,
+	"sets the display brightness\n",
+	" <side> <0..1000>\n        side: 0/3=both; 1=first; 2=second\n"
+);
+
+#endif
+
+/* EOF EB+MCF-EV123.c */
diff --git a/roms/u-boot/board/CZ.NIC/turris_mox/MAINTAINERS b/roms/u-boot/board/CZ.NIC/turris_mox/MAINTAINERS
new file mode 100644
index 000000000..2b9c1132f
--- /dev/null
+++ b/roms/u-boot/board/CZ.NIC/turris_mox/MAINTAINERS
@@ -0,0 +1,6 @@
+TURRIS OMNIA BOARD
+M:	Marek Behún <marek.behun@nic.cz>
+S:	Maintained
+F:	board/CZ.NIC/turris_mox/
+F:	include/configs/turris_mox.h
+F:	configs/turris_mox_defconfig
diff --git a/roms/u-boot/board/CZ.NIC/turris_mox/Makefile b/roms/u-boot/board/CZ.NIC/turris_mox/Makefile
new file mode 100644
index 000000000..33a52b63d
--- /dev/null
+++ b/roms/u-boot/board/CZ.NIC/turris_mox/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+
+obj-y	:= turris_mox.o mox_sp.o
diff --git a/roms/u-boot/board/CZ.NIC/turris_mox/mox_sp.c b/roms/u-boot/board/CZ.NIC/turris_mox/mox_sp.c
new file mode 100644
index 000000000..cc57b9f09
--- /dev/null
+++ b/roms/u-boot/board/CZ.NIC/turris_mox/mox_sp.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+ */
+
+#include <common.h>
+#include <asm/arch/soc.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+#define RWTM_BASE		(MVEBU_REGISTER(0xb0000))
+#define RWTM_CMD_PARAM(i)	(size_t)(RWTM_BASE + (i) * 4)
+#define RWTM_CMD		(RWTM_BASE + 0x40)
+#define RWTM_CMD_RETSTATUS	(RWTM_BASE + 0x80)
+#define RWTM_CMD_STATUS(i)	(size_t)(RWTM_BASE + 0x84 + (i) * 4)
+
+#define RWTM_HOST_INT_RESET	(RWTM_BASE + 0xc8)
+#define RWTM_HOST_INT_MASK	(RWTM_BASE + 0xcc)
+#define SP_CMD_COMPLETE		BIT(0)
+
+#define MBOX_STS_SUCCESS		(0x0 << 30)
+#define MBOX_STS_FAIL			(0x1 << 30)
+#define MBOX_STS_BADCMD			(0x2 << 30)
+#define MBOX_STS_LATER			(0x3 << 30)
+#define MBOX_STS_ERROR(s)		((s) & (3 << 30))
+#define MBOX_STS_VALUE(s)		(((s) >> 10) & 0xfffff)
+#define MBOX_STS_CMD(s)			((s) & 0x3ff)
+
+enum mbox_cmd {
+	MBOX_CMD_GET_RANDOM	= 1,
+	MBOX_CMD_BOARD_INFO,
+	MBOX_CMD_ECDSA_PUB_KEY,
+	MBOX_CMD_HASH,
+	MBOX_CMD_SIGN,
+	MBOX_CMD_VERIFY,
+
+	MBOX_CMD_OTP_READ,
+	MBOX_CMD_OTP_WRITE
+};
+
+static int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout)
+{
+	const int tries = 50;
+	int i;
+	u32 status;
+
+	clrbits_le32(RWTM_HOST_INT_MASK, SP_CMD_COMPLETE);
+
+	writel(cmd, RWTM_CMD);
+
+	for (i = 0; i < tries; ++i) {
+		mdelay(10);
+		if (readl(RWTM_HOST_INT_RESET) & SP_CMD_COMPLETE)
+			break;
+	}
+
+	if (i == tries) {
+		/* if timed out, don't read status */
+		setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE);
+		return -ETIMEDOUT;
+	}
+
+	for (i = 0; i < nout; ++i)
+		out[i] = readl(RWTM_CMD_STATUS(i));
+	status = readl(RWTM_CMD_RETSTATUS);
+
+	setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE);
+
+	if (MBOX_STS_CMD(status) != cmd)
+		return -EIO;
+	else if (MBOX_STS_ERROR(status) == MBOX_STS_FAIL)
+		return -(int)MBOX_STS_VALUE(status);
+	else if (MBOX_STS_ERROR(status) != MBOX_STS_SUCCESS)
+		return -EIO;
+	else
+		return MBOX_STS_VALUE(status);
+}
+
+const char *mox_sp_get_ecdsa_public_key(void)
+{
+	static char public_key[135];
+	u32 out[16];
+	int res;
+
+	if (public_key[0])
+		return public_key;
+
+	res = mbox_do_cmd(MBOX_CMD_ECDSA_PUB_KEY, out, 16);
+	if (res < 0)
+		return NULL;
+
+	sprintf(public_key,
+		"%06x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x",
+		(u32)res, out[0], out[1], out[2], out[3], out[4], out[5],
+		out[6], out[7], out[8], out[9], out[10], out[11], out[12],
+		out[13], out[14], out[15]);
+
+	return public_key;
+}
+
+static inline void res_to_mac(u8 *mac, u32 t1, u32 t2)
+{
+	mac[0] = t1 >> 8;
+	mac[1] = t1;
+	mac[2] = t2 >> 24;
+	mac[3] = t2 >> 16;
+	mac[4] = t2 >> 8;
+	mac[5] = t2;
+}
+
+int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, int *ram)
+{
+	u32 out[8];
+	int res;
+
+	res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, out, 8);
+	if (res < 0)
+		return res;
+
+	if (sn) {
+		*sn = out[1];
+		*sn <<= 32;
+		*sn |= out[0];
+	}
+
+	if (bv)
+		*bv = out[2];
+
+	if (ram)
+		*ram = out[3];
+
+	if (mac1)
+		res_to_mac(mac1, out[4], out[5]);
+
+	if (mac2)
+		res_to_mac(mac2, out[6], out[7]);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/CZ.NIC/turris_mox/mox_sp.h b/roms/u-boot/board/CZ.NIC/turris_mox/mox_sp.h
new file mode 100644
index 000000000..49a4ed80e
--- /dev/null
+++ b/roms/u-boot/board/CZ.NIC/turris_mox/mox_sp.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+ */
+
+#ifndef _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_
+#define _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_
+
+#include <common.h>
+
+const char *mox_sp_get_ecdsa_public_key(void);
+int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv,
+			   int *ram);
+
+#endif /* _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_ */
diff --git a/roms/u-boot/board/CZ.NIC/turris_mox/turris_mox.c b/roms/u-boot/board/CZ.NIC/turris_mox/turris_mox.c
new file mode 100644
index 000000000..428cd23a1
--- /dev/null
+++ b/roms/u-boot/board/CZ.NIC/turris_mox/turris_mox.c
@@ -0,0 +1,925 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <button.h>
+#include <clk.h>
+#include <dm.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <led.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <linux/string.h>
+#include <miiphy.h>
+#include <mvebu/comphy.h>
+#include <spi.h>
+
+#include "mox_sp.h"
+
+#define MAX_MOX_MODULES		10
+
+#define MOX_MODULE_SFP		0x1
+#define MOX_MODULE_PCI		0x2
+#define MOX_MODULE_TOPAZ	0x3
+#define MOX_MODULE_PERIDOT	0x4
+#define MOX_MODULE_USB3		0x5
+#define MOX_MODULE_PASSPCI	0x6
+
+#define ARMADA_37XX_NB_GPIO_SEL	(MVEBU_REGISTER(0x13830))
+#define ARMADA_37XX_SPI_CTRL	(MVEBU_REGISTER(0x10600))
+#define ARMADA_37XX_SPI_CFG	(MVEBU_REGISTER(0x10604))
+#define ARMADA_37XX_SPI_DOUT	(MVEBU_REGISTER(0x10608))
+#define ARMADA_37XX_SPI_DIN	(MVEBU_REGISTER(0x1060c))
+
+#define ETH1_PATH	"/soc/internal-regs@d0000000/ethernet@40000"
+#define MDIO_PATH	"/soc/internal-regs@d0000000/mdio@32004"
+#define SFP_GPIO_PATH	"/soc/internal-regs@d0000000/spi@10600/moxtet@1/gpio@0"
+#define PCIE_PATH	"/soc/pcie@d0070000"
+#define SFP_PATH	"/sfp"
+#define LED_PATH	"/leds/led"
+#define BUTTON_PATH	"/gpio-keys/reset"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *blob)
+{
+	u8 topology[MAX_MOX_MODULES];
+	int i, size, node;
+	bool enable;
+
+	/*
+	 * SPI driver is not loaded in driver model yet, but we have to find out
+	 * if pcie should be enabled in U-Boot's device tree. Therefore we have
+	 * to read SPI by reading/writing SPI registers directly
+	 */
+
+	writel(0x10df, ARMADA_37XX_SPI_CFG);
+	/* put pin from GPIO to SPI mode */
+	clrbits_le32(ARMADA_37XX_NB_GPIO_SEL, BIT(12));
+	/* enable SPI CS1 */
+	setbits_le32(ARMADA_37XX_SPI_CTRL, BIT(17));
+
+	while (!(readl(ARMADA_37XX_SPI_CTRL) & 0x2))
+		udelay(1);
+
+	for (i = 0; i < MAX_MOX_MODULES; ++i) {
+		writel(0x0, ARMADA_37XX_SPI_DOUT);
+
+		while (!(readl(ARMADA_37XX_SPI_CTRL) & 0x2))
+			udelay(1);
+
+		topology[i] = readl(ARMADA_37XX_SPI_DIN) & 0xff;
+		if (topology[i] == 0xff)
+			break;
+
+		topology[i] &= 0xf;
+	}
+
+	size = i;
+
+	/* disable SPI CS1 */
+	clrbits_le32(ARMADA_37XX_SPI_CTRL, BIT(17));
+
+	if (size > 1 && (topology[1] == MOX_MODULE_PCI ||
+			 topology[1] == MOX_MODULE_USB3 ||
+			 topology[1] == MOX_MODULE_PASSPCI))
+		enable = true;
+	else
+		enable = false;
+
+	node = fdt_path_offset(blob, PCIE_PATH);
+
+	if (node < 0) {
+		printf("Cannot find PCIe node in U-Boot's device tree!\n");
+		return 0;
+	}
+
+	if (fdt_setprop_string(blob, node, "status",
+			       enable ? "okay" : "disabled") < 0) {
+		printf("Cannot %s PCIe in U-Boot's device tree!\n",
+		       enable ? "enable" : "disable");
+		return 0;
+	}
+
+	if (a3700_fdt_fix_pcie_regions(blob) < 0) {
+		printf("Cannot fix PCIe regions in U-Boot's device tree!\n");
+		return 0;
+	}
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+static int mox_do_spi(u8 *in, u8 *out, size_t size)
+{
+	struct spi_slave *slave;
+	struct udevice *dev;
+	int ret;
+
+	ret = spi_get_bus_and_cs(0, 1, 1000000, SPI_CPHA | SPI_CPOL,
+				 "spi_generic_drv", "moxtet@1", &dev,
+				 &slave);
+	if (ret)
+		goto fail;
+
+	ret = spi_claim_bus(slave);
+	if (ret)
+		goto fail_free;
+
+	ret = spi_xfer(slave, size * 8, out, in, SPI_XFER_ONCE);
+
+	spi_release_bus(slave);
+fail_free:
+	spi_free_slave(slave);
+fail:
+	return ret;
+}
+
+static int mox_get_topology(const u8 **ptopology, int *psize, int *pis_sd)
+{
+	static int is_sd;
+	static u8 topology[MAX_MOX_MODULES - 1];
+	static int size;
+	u8 din[MAX_MOX_MODULES], dout[MAX_MOX_MODULES];
+	int ret, i;
+
+	if (size) {
+		if (ptopology)
+			*ptopology = topology;
+		if (psize)
+			*psize = size;
+		if (pis_sd)
+			*pis_sd = is_sd;
+		return 0;
+	}
+
+	memset(din, 0, MAX_MOX_MODULES);
+	memset(dout, 0, MAX_MOX_MODULES);
+
+	ret = mox_do_spi(din, dout, MAX_MOX_MODULES);
+	if (ret)
+		return ret;
+
+	if (din[0] == 0x10)
+		is_sd = 1;
+	else if (din[0] == 0x00)
+		is_sd = 0;
+	else
+		return -ENODEV;
+
+	for (i = 1; i < MAX_MOX_MODULES && din[i] != 0xff; ++i)
+		topology[i - 1] = din[i] & 0xf;
+	size = i - 1;
+
+	if (ptopology)
+		*ptopology = topology;
+	if (psize)
+		*psize = size;
+	if (pis_sd)
+		*pis_sd = is_sd;
+
+	return 0;
+}
+
+int comphy_update_map(struct comphy_map *serdes_map, int count)
+{
+	int ret, i, size, sfpindex = -1, swindex = -1;
+	const u8 *topology;
+
+	ret = mox_get_topology(&topology, &size, NULL);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < size; ++i) {
+		if (topology[i] == MOX_MODULE_SFP && sfpindex == -1)
+			sfpindex = i;
+		else if ((topology[i] == MOX_MODULE_TOPAZ ||
+			  topology[i] == MOX_MODULE_PERIDOT) &&
+			 swindex == -1)
+			swindex = i;
+	}
+
+	if (sfpindex >= 0 && swindex >= 0) {
+		if (sfpindex < swindex)
+			serdes_map[0].speed = COMPHY_SPEED_1_25G;
+		else
+			serdes_map[0].speed = COMPHY_SPEED_3_125G;
+	} else if (sfpindex >= 0) {
+		serdes_map[0].speed = COMPHY_SPEED_1_25G;
+	} else if (swindex >= 0) {
+		serdes_map[0].speed = COMPHY_SPEED_3_125G;
+	}
+
+	return 0;
+}
+
+#define SW_SMI_CMD_R(d, r)	(0x9800 | (((d) & 0x1f) << 5) | ((r) & 0x1f))
+#define SW_SMI_CMD_W(d, r)	(0x9400 | (((d) & 0x1f) << 5) | ((r) & 0x1f))
+
+static int sw_multi_read(struct mii_dev *bus, int sw, int dev, int reg)
+{
+	bus->write(bus, sw, 0, 0, SW_SMI_CMD_R(dev, reg));
+	mdelay(5);
+	return bus->read(bus, sw, 0, 1);
+}
+
+static void sw_multi_write(struct mii_dev *bus, int sw, int dev, int reg,
+			   u16 val)
+{
+	bus->write(bus, sw, 0, 1, val);
+	bus->write(bus, sw, 0, 0, SW_SMI_CMD_W(dev, reg));
+	mdelay(5);
+}
+
+static int sw_scratch_read(struct mii_dev *bus, int sw, int reg)
+{
+	sw_multi_write(bus, sw, 0x1c, 0x1a, (reg & 0x7f) << 8);
+	return sw_multi_read(bus, sw, 0x1c, 0x1a) & 0xff;
+}
+
+static void sw_led_write(struct mii_dev *bus, int sw, int port, int reg,
+			 u16 val)
+{
+	sw_multi_write(bus, sw, port, 0x16, 0x8000 | ((reg & 7) << 12)
+					    | (val & 0x7ff));
+}
+
+static void sw_blink_leds(struct mii_dev *bus, int peridot, int topaz)
+{
+	int i, p;
+	struct {
+		int port;
+		u16 val;
+		int wait;
+	} regs[] = {
+		{ 2, 0xef, 1 }, { 2, 0xfe, 1 }, { 2, 0x33, 0 },
+		{ 4, 0xef, 1 }, { 4, 0xfe, 1 }, { 4, 0x33, 0 },
+		{ 3, 0xfe, 1 }, { 3, 0xef, 1 }, { 3, 0x33, 0 },
+		{ 1, 0xfe, 1 }, { 1, 0xef, 1 }, { 1, 0x33, 0 }
+	};
+
+	for (i = 0; i < 12; ++i) {
+		for (p = 0; p < peridot; ++p) {
+			sw_led_write(bus, 0x10 + p, regs[i].port, 0,
+				     regs[i].val);
+			sw_led_write(bus, 0x10 + p, regs[i].port + 4, 0,
+				     regs[i].val);
+		}
+		if (topaz) {
+			sw_led_write(bus, 0x2, 0x10 + regs[i].port, 0,
+				     regs[i].val);
+		}
+
+		if (regs[i].wait)
+			mdelay(75);
+	}
+}
+
+static void check_switch_address(struct mii_dev *bus, int addr)
+{
+	if (sw_scratch_read(bus, addr, 0x70) >> 3 != addr)
+		printf("Check of switch MDIO address failed for 0x%02x\n",
+		       addr);
+}
+
+static int sfp, pci, topaz, peridot, usb, passpci;
+static int sfp_pos, peridot_pos[3];
+static int module_count;
+
+static int configure_peridots(struct gpio_desc *reset_gpio)
+{
+	int i, ret;
+	u8 dout[MAX_MOX_MODULES];
+
+	memset(dout, 0, MAX_MOX_MODULES);
+
+	/* set addresses of Peridot modules */
+	for (i = 0; i < peridot; ++i)
+		dout[module_count - peridot_pos[i]] = (~i) & 3;
+
+	/*
+	 * if there is a SFP module connected to the last Peridot module, set
+	 * the P10_SMODE to 1 for the Peridot module
+	 */
+	if (sfp)
+		dout[module_count - peridot_pos[i - 1]] |= 1 << 3;
+
+	dm_gpio_set_value(reset_gpio, 1);
+	mdelay(10);
+
+	ret = mox_do_spi(NULL, dout, module_count + 1);
+
+	mdelay(10);
+	dm_gpio_set_value(reset_gpio, 0);
+
+	mdelay(50);
+
+	return ret;
+}
+
+static int get_reset_gpio(struct gpio_desc *reset_gpio)
+{
+	int node;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "cznic,moxtet");
+	if (node < 0) {
+		printf("Cannot find Moxtet bus device node!\n");
+		return -1;
+	}
+
+	gpio_request_by_name_nodev(offset_to_ofnode(node), "reset-gpios", 0,
+				   reset_gpio, GPIOD_IS_OUT);
+
+	if (!dm_gpio_is_valid(reset_gpio)) {
+		printf("Cannot find reset GPIO for Moxtet bus!\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	int ret;
+	u8 mac1[6], mac2[6];
+
+	ret = mbox_sp_get_board_info(NULL, mac1, mac2, NULL, NULL);
+	if (ret < 0) {
+		printf("Cannot read data from OTP!\n");
+		return 0;
+	}
+
+	if (is_valid_ethaddr(mac1) && !env_get("ethaddr"))
+		eth_env_set_enetaddr("ethaddr", mac1);
+
+	if (is_valid_ethaddr(mac2) && !env_get("eth1addr"))
+		eth_env_set_enetaddr("eth1addr", mac2);
+
+	return 0;
+}
+
+static void mox_phy_modify(struct phy_device *phydev, int page, int reg,
+			   u16 mask, u16 set)
+{
+	int val;
+
+	val = phydev->drv->readext(phydev, MDIO_DEVAD_NONE, page, reg);
+	val &= ~mask;
+	val |= set;
+	phydev->drv->writeext(phydev, MDIO_DEVAD_NONE, page, reg, val);
+}
+
+static void mox_phy_leds_start_blinking(void)
+{
+	struct phy_device *phydev;
+	struct mii_dev *bus;
+
+	bus = miiphy_get_dev_by_name("neta@30000");
+	if (!bus) {
+		printf("Cannot get MDIO bus device!\n");
+		return;
+	}
+
+	phydev = phy_find_by_mask(bus, BIT(1), PHY_INTERFACE_MODE_RGMII);
+	if (!phydev) {
+		printf("Cannot get ethernet PHY!\n");
+		return;
+	}
+
+	mox_phy_modify(phydev, 3, 0x12, 0x700, 0x400);
+	mox_phy_modify(phydev, 3, 0x10, 0xff, 0xbb);
+}
+
+static bool read_reset_button(void)
+{
+	struct udevice *button, *led;
+	int i;
+
+	if (device_get_global_by_ofnode(ofnode_path(BUTTON_PATH), &button)) {
+		printf("Cannot find reset button!\n");
+		return false;
+	}
+
+	if (device_get_global_by_ofnode(ofnode_path(LED_PATH), &led)) {
+		printf("Cannot find status LED!\n");
+		return false;
+	}
+
+	led_set_state(led, LEDST_ON);
+
+	for (i = 0; i < 21; ++i) {
+		if (button_get_state(button) != BUTTON_ON)
+			return false;
+		if (i < 20)
+			mdelay(50);
+	}
+
+	led_set_state(led, LEDST_OFF);
+
+	return true;
+}
+
+static void handle_reset_button(void)
+{
+	const char * const vars[1] = { "bootcmd_rescue", };
+
+	/*
+	 * Ensure that bootcmd_rescue has always stock value, so that running
+	 *   run bootcmd_rescue
+	 * always works correctly.
+	 */
+	env_set_default_vars(1, (char * const *)vars, 0);
+
+	if (read_reset_button()) {
+		const char * const vars[2] = {
+			"bootcmd",
+			"distro_bootcmd",
+		};
+
+		/*
+		 * Set the above envs to their default values, in case the user
+		 * managed to break them.
+		 */
+		env_set_default_vars(2, (char * const *)vars, 0);
+
+		/* Ensure bootcmd_rescue is used by distroboot */
+		env_set("boot_targets", "rescue");
+
+		/* start blinking PHY LEDs */
+		mox_phy_leds_start_blinking();
+
+		printf("RESET button was pressed, overwriting boot_targets!\n");
+	} else {
+		/*
+		 * In case the user somehow managed to save environment with
+		 * boot_targets=rescue, reset boot_targets to default value.
+		 * This could happen in subsequent commands if bootcmd_rescue
+		 * failed.
+		 */
+		if (!strcmp(env_get("boot_targets"), "rescue")) {
+			const char * const vars[1] = {
+				"boot_targets",
+			};
+
+			env_set_default_vars(1, (char * const *)vars, 0);
+		}
+	}
+}
+
+static void mox_print_info(void)
+{
+	int ret, board_version, ram_size;
+	u64 serial_number;
+	const char *pub_key;
+
+	ret = mbox_sp_get_board_info(&serial_number, NULL, NULL, &board_version,
+				     &ram_size);
+	if (ret < 0)
+		return;
+
+	printf("Turris Mox:\n");
+	printf("  Board version: %i\n", board_version);
+	printf("  RAM size: %i MiB\n", ram_size);
+	printf("  Serial Number: %016llX\n", serial_number);
+
+	pub_key = mox_sp_get_ecdsa_public_key();
+	if (pub_key)
+		printf("  ECDSA Public Key: %s\n", pub_key);
+	else
+		printf("Cannot read ECDSA Public Key\n");
+}
+
+int last_stage_init(void)
+{
+	int ret, i;
+	const u8 *topology;
+	int is_sd;
+	struct mii_dev *bus;
+	struct gpio_desc reset_gpio = {};
+
+	mox_print_info();
+
+	ret = mox_get_topology(&topology, &module_count, &is_sd);
+	if (ret) {
+		printf("Cannot read module topology!\n");
+		return 0;
+	}
+
+	printf("  SD/eMMC version: %s\n", is_sd ? "SD" : "eMMC");
+
+	if (module_count)
+		printf("Module Topology:\n");
+
+	for (i = 0; i < module_count; ++i) {
+		switch (topology[i]) {
+		case MOX_MODULE_SFP:
+			printf("% 4i: SFP Module\n", i + 1);
+			break;
+		case MOX_MODULE_PCI:
+			printf("% 4i: Mini-PCIe Module\n", i + 1);
+			break;
+		case MOX_MODULE_TOPAZ:
+			printf("% 4i: Topaz Switch Module (4-port)\n", i + 1);
+			break;
+		case MOX_MODULE_PERIDOT:
+			printf("% 4i: Peridot Switch Module (8-port)\n", i + 1);
+			break;
+		case MOX_MODULE_USB3:
+			printf("% 4i: USB 3.0 Module (4 ports)\n", i + 1);
+			break;
+		case MOX_MODULE_PASSPCI:
+			printf("% 4i: Passthrough Mini-PCIe Module\n", i + 1);
+			break;
+		default:
+			printf("% 4i: unknown (ID %i)\n", i + 1, topology[i]);
+		}
+	}
+
+	/* now check if modules are connected in supported mode */
+
+	for (i = 0; i < module_count; ++i) {
+		switch (topology[i]) {
+		case MOX_MODULE_SFP:
+			if (sfp) {
+				printf("Error: Only one SFP module is supported!\n");
+			} else if (topaz) {
+				printf("Error: SFP module cannot be connected after Topaz Switch module!\n");
+			} else {
+				sfp_pos = i;
+				++sfp;
+			}
+			break;
+		case MOX_MODULE_PCI:
+			if (pci)
+				printf("Error: Only one Mini-PCIe module is supported!\n");
+			else if (usb)
+				printf("Error: Mini-PCIe module cannot come after USB 3.0 module!\n");
+			else if (i && (i != 1 || !passpci))
+				printf("Error: Mini-PCIe module should be the first connected module or come right after Passthrough Mini-PCIe module!\n");
+			else
+				++pci;
+			break;
+		case MOX_MODULE_TOPAZ:
+			if (topaz)
+				printf("Error: Only one Topaz module is supported!\n");
+			else if (peridot >= 3)
+				printf("Error: At most two Peridot modules can come before Topaz module!\n");
+			else
+				++topaz;
+			break;
+		case MOX_MODULE_PERIDOT:
+			if (sfp || topaz) {
+				printf("Error: Peridot module must come before SFP or Topaz module!\n");
+			} else if (peridot >= 3) {
+				printf("Error: At most three Peridot modules are supported!\n");
+			} else {
+				peridot_pos[peridot] = i;
+				++peridot;
+			}
+			break;
+		case MOX_MODULE_USB3:
+			if (pci)
+				printf("Error: USB 3.0 module cannot come after Mini-PCIe module!\n");
+			else if (usb)
+				printf("Error: Only one USB 3.0 module is supported!\n");
+			else if (i && (i != 1 || !passpci))
+				printf("Error: USB 3.0 module should be the first connected module or come right after Passthrough Mini-PCIe module!\n");
+			else
+				++usb;
+			break;
+		case MOX_MODULE_PASSPCI:
+			if (passpci)
+				printf("Error: Only one Passthrough Mini-PCIe module is supported!\n");
+			else if (i != 0)
+				printf("Error: Passthrough Mini-PCIe module should be the first connected module!\n");
+			else
+				++passpci;
+		}
+	}
+
+	/* now configure modules */
+
+	if (get_reset_gpio(&reset_gpio) < 0)
+		return 0;
+
+	if (peridot > 0) {
+		if (configure_peridots(&reset_gpio) < 0) {
+			printf("Cannot configure Peridot modules!\n");
+			peridot = 0;
+		}
+	} else {
+		dm_gpio_set_value(&reset_gpio, 1);
+		mdelay(50);
+		dm_gpio_set_value(&reset_gpio, 0);
+		mdelay(50);
+	}
+
+	if (peridot || topaz) {
+		/*
+		 * now check if the addresses are set by reading Scratch & Misc
+		 * register 0x70 of Peridot (and potentially Topaz) modules
+		 */
+
+		bus = miiphy_get_dev_by_name("neta@30000");
+		if (!bus) {
+			printf("Cannot get MDIO bus device!\n");
+		} else {
+			for (i = 0; i < peridot; ++i)
+				check_switch_address(bus, 0x10 + i);
+
+			if (topaz)
+				check_switch_address(bus, 0x2);
+
+			sw_blink_leds(bus, peridot, topaz);
+		}
+	}
+
+	printf("\n");
+
+	handle_reset_button();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+static int vnode_by_path(void *blob, const char *fmt, va_list ap)
+{
+	char path[128];
+
+	vsnprintf(path, 128, fmt, ap);
+	return fdt_path_offset(blob, path);
+}
+
+static int node_by_path(void *blob, const char *fmt, ...)
+{
+	va_list ap;
+	int res;
+
+	va_start(ap, fmt);
+	res = vnode_by_path(blob, fmt, ap);
+	va_end(ap);
+
+	return res;
+}
+
+static int phandle_by_path(void *blob, const char *fmt, ...)
+{
+	va_list ap;
+	int node, phandle, res;
+
+	va_start(ap, fmt);
+	node = vnode_by_path(blob, fmt, ap);
+	va_end(ap);
+
+	if (node < 0)
+		return node;
+
+	phandle = fdt_get_phandle(blob, node);
+	if (phandle > 0)
+		return phandle;
+
+	phandle = fdt_get_max_phandle(blob);
+	if (phandle < 0)
+		return phandle;
+
+	phandle += 1;
+
+	res = fdt_setprop_u32(blob, node, "linux,phandle", phandle);
+	if (res < 0)
+		return res;
+
+	res = fdt_setprop_u32(blob, node, "phandle", phandle);
+	if (res < 0)
+		return res;
+
+	return phandle;
+}
+
+static int enable_by_path(void *blob, const char *fmt, ...)
+{
+	va_list ap;
+	int node;
+
+	va_start(ap, fmt);
+	node = vnode_by_path(blob, fmt, ap);
+	va_end(ap);
+
+	if (node < 0)
+		return node;
+
+	return fdt_setprop_string(blob, node, "status", "okay");
+}
+
+static bool is_topaz(int id)
+{
+	return topaz && id == peridot + topaz - 1;
+}
+
+static int switch_addr(int id)
+{
+	return is_topaz(id) ? 0x2 : 0x10 + id;
+}
+
+static int setup_switch(void *blob, int id)
+{
+	int res, addr, i, node, phandle;
+
+	addr = switch_addr(id);
+
+	/* first enable the switch by setting status = "okay" */
+	res = enable_by_path(blob, MDIO_PATH "/switch%i@%x", id, addr);
+	if (res < 0)
+		return res;
+
+	/*
+	 * now if there are more switches or a SFP module coming after,
+	 * enable corresponding ports
+	 */
+	if (id < peridot + topaz - 1) {
+		res = enable_by_path(blob,
+				     MDIO_PATH "/switch%i@%x/ports/port@a",
+				     id, addr);
+	} else if (id == peridot - 1 && !topaz && sfp) {
+		res = enable_by_path(blob,
+				     MDIO_PATH "/switch%i@%x/ports/port-sfp@a",
+				     id, addr);
+	} else {
+		res = 0;
+	}
+	if (res < 0)
+		return res;
+
+	if (id >= peridot + topaz - 1)
+		return 0;
+
+	/* finally change link property if needed */
+	node = node_by_path(blob, MDIO_PATH "/switch%i@%x/ports/port@a", id,
+			    addr);
+	if (node < 0)
+		return node;
+
+	for (i = id + 1; i < peridot + topaz; ++i) {
+		phandle = phandle_by_path(blob,
+					  MDIO_PATH "/switch%i@%x/ports/port@%x",
+					  i, switch_addr(i),
+					  is_topaz(i) ? 5 : 9);
+		if (phandle < 0)
+			return phandle;
+
+		if (i == id + 1)
+			res = fdt_setprop_u32(blob, node, "link", phandle);
+		else
+			res = fdt_appendprop_u32(blob, node, "link", phandle);
+		if (res < 0)
+			return res;
+	}
+
+	return 0;
+}
+
+static int remove_disabled_nodes(void *blob)
+{
+	while (1) {
+		int res, offset;
+
+		offset = fdt_node_offset_by_prop_value(blob, -1, "status",
+						       "disabled", 9);
+		if (offset < 0)
+			break;
+
+		res = fdt_del_node(blob, offset);
+		if (res < 0)
+			return res;
+	}
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int node, phandle, res;
+
+	/*
+	 * If MOX B (PCI), MOX F (USB) or MOX G (Passthrough PCI) modules are
+	 * connected, enable the PCIe node.
+	 */
+	if (pci || usb || passpci) {
+		node = fdt_path_offset(blob, PCIE_PATH);
+		if (node < 0)
+			return node;
+
+		res = fdt_setprop_string(blob, node, "status", "okay");
+		if (res < 0)
+			return res;
+
+		/* Fix PCIe regions for devices with 4 GB RAM */
+		res = a3700_fdt_fix_pcie_regions(blob);
+		if (res < 0)
+			return res;
+	}
+
+	/*
+	 * If MOX C (Topaz switch) and/or MOX E (Peridot switch) are connected,
+	 * enable the eth1 node and setup the switches.
+	 */
+	if (peridot || topaz) {
+		int i;
+
+		res = enable_by_path(blob, ETH1_PATH);
+		if (res < 0)
+			return res;
+
+		for (i = 0; i < peridot + topaz; ++i) {
+			res = setup_switch(blob, i);
+			if (res < 0)
+				return res;
+		}
+	}
+
+	/*
+	 * If MOX D (SFP cage module) is connected, enable the SFP node and eth1
+	 * node. If there is no Peridot switch between MOX A and MOX D, add link
+	 * to the SFP node to eth1 node.
+	 * Also enable and configure SFP GPIO controller node.
+	 */
+	if (sfp) {
+		res = enable_by_path(blob, SFP_PATH);
+		if (res < 0)
+			return res;
+
+		res = enable_by_path(blob, ETH1_PATH);
+		if (res < 0)
+			return res;
+
+		if (!peridot) {
+			phandle = phandle_by_path(blob, SFP_PATH);
+			if (phandle < 0)
+				return res;
+
+			node = node_by_path(blob, ETH1_PATH);
+			if (node < 0)
+				return node;
+
+			res = fdt_setprop_u32(blob, node, "sfp", phandle);
+			if (res < 0)
+				return res;
+
+			res = fdt_setprop_string(blob, node, "phy-mode",
+						 "sgmii");
+			if (res < 0)
+				return res;
+		}
+
+		res = enable_by_path(blob, SFP_GPIO_PATH);
+		if (res < 0)
+			return res;
+
+		if (sfp_pos) {
+			char newname[16];
+
+			/* moxtet-sfp is on non-zero position, change default */
+			node = node_by_path(blob, SFP_GPIO_PATH);
+			if (node < 0)
+				return node;
+
+			res = fdt_setprop_u32(blob, node, "reg", sfp_pos);
+			if (res < 0)
+				return res;
+
+			sprintf(newname, "gpio@%x", sfp_pos);
+
+			res = fdt_set_name(blob, node, newname);
+			if (res < 0)
+				return res;
+		}
+	}
+
+	fdt_fixup_ethernet(blob);
+
+	/* Finally remove disabled nodes, as per Rob Herring's request. */
+	remove_disabled_nodes(blob);
+
+	return 0;
+}
+
+#endif
diff --git a/roms/u-boot/board/CZ.NIC/turris_omnia/MAINTAINERS b/roms/u-boot/board/CZ.NIC/turris_omnia/MAINTAINERS
new file mode 100644
index 000000000..ed15e11d3
--- /dev/null
+++ b/roms/u-boot/board/CZ.NIC/turris_omnia/MAINTAINERS
@@ -0,0 +1,6 @@
+TURRIS OMNIA BOARD
+M:	Marek Behún <marek.behun@nic.cz>
+S:	Maintained
+F:	board/CZ.NIC/turris_omnia/
+F:	include/configs/turris_omnia.h
+F:	configs/turris_omnia_defconfig
diff --git a/roms/u-boot/board/CZ.NIC/turris_omnia/Makefile b/roms/u-boot/board/CZ.NIC/turris_omnia/Makefile
new file mode 100644
index 000000000..ccdf6c352
--- /dev/null
+++ b/roms/u-boot/board/CZ.NIC/turris_omnia/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
+
+obj-y	:= turris_omnia.o
diff --git a/roms/u-boot/board/CZ.NIC/turris_omnia/turris_omnia.c b/roms/u-boot/board/CZ.NIC/turris_omnia/turris_omnia.c
new file mode 100644
index 000000000..8b2f94f95
--- /dev/null
+++ b/roms/u-boot/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -0,0 +1,559 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
+ * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
+ *
+ * Derived from the code for
+ *   Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <log.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <dm/uclass.h>
+#include <fdt_support.h>
+#include <time.h>
+#include <linux/bitops.h>
+#include <u-boot/crc.h>
+# include <atsha204a-i2c.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OMNIA_I2C_BUS_NAME		"i2c@11000->i2cmux@70->i2c@0"
+
+#define OMNIA_I2C_MCU_CHIP_ADDR		0x2a
+#define OMNIA_I2C_MCU_CHIP_LEN		1
+
+#define OMNIA_I2C_EEPROM_CHIP_ADDR	0x54
+#define OMNIA_I2C_EEPROM_CHIP_LEN	2
+#define OMNIA_I2C_EEPROM_MAGIC		0x0341a034
+
+enum mcu_commands {
+	CMD_GET_STATUS_WORD	= 0x01,
+	CMD_GET_RESET		= 0x09,
+	CMD_WATCHDOG_STATE	= 0x0b,
+};
+
+enum status_word_bits {
+	CARD_DET_STSBIT		= 0x0010,
+	MSATA_IND_STSBIT	= 0x0020,
+};
+
+#define OMNIA_ATSHA204_OTP_VERSION	0
+#define OMNIA_ATSHA204_OTP_SERIAL	1
+#define OMNIA_ATSHA204_OTP_MAC0		3
+#define OMNIA_ATSHA204_OTP_MAC1		4
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2014_T3.0"
+ */
+#define OMNIA_GPP_OUT_ENA_LOW					\
+	(~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |	\
+	   BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |	\
+	   BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
+#define OMNIA_GPP_OUT_ENA_MID					\
+	(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |	\
+	   BIT(16) | BIT(17) | BIT(18)))
+
+#define OMNIA_GPP_OUT_VAL_LOW	0x0
+#define OMNIA_GPP_OUT_VAL_MID	0x0
+#define OMNIA_GPP_POL_LOW	0x0
+#define OMNIA_GPP_POL_MID	0x0
+
+static struct serdes_map board_serdes_map_pex[] = {
+	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+static struct serdes_map board_serdes_map_sata[] = {
+	{SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
+					  uint offset_len)
+{
+	struct udevice *bus, *dev;
+	int ret;
+
+	ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
+	if (ret) {
+		printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
+		       OMNIA_I2C_BUS_NAME, ret);
+		return NULL;
+	}
+
+	ret = i2c_get_chip(bus, addr, offset_len, &dev);
+	if (ret) {
+		printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
+		       name, ret);
+		return NULL;
+	}
+
+	return dev;
+}
+
+static int omnia_mcu_read(u8 cmd, void *buf, int len)
+{
+	struct udevice *chip;
+
+	chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
+				  OMNIA_I2C_MCU_CHIP_LEN);
+	if (!chip)
+		return -ENODEV;
+
+	return dm_i2c_read(chip, cmd, buf, len);
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int omnia_mcu_write(u8 cmd, const void *buf, int len)
+{
+	struct udevice *chip;
+
+	chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
+				  OMNIA_I2C_MCU_CHIP_LEN);
+	if (!chip)
+		return -ENODEV;
+
+	return dm_i2c_write(chip, cmd, buf, len);
+}
+
+static bool disable_mcu_watchdog(void)
+{
+	int ret;
+
+	puts("Disabling MCU watchdog... ");
+
+	ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
+	if (ret) {
+		printf("omnia_mcu_write failed: %i\n", ret);
+		return false;
+	}
+
+	puts("disabled\n");
+
+	return true;
+}
+#endif
+
+static bool omnia_detect_sata(void)
+{
+	int ret;
+	u16 stsword;
+
+	puts("MiniPCIe/mSATA card detection... ");
+
+	ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
+	if (ret) {
+		printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
+		       ret);
+		return false;
+	}
+
+	if (!(stsword & CARD_DET_STSBIT)) {
+		puts("none\n");
+		return false;
+	}
+
+	if (stsword & MSATA_IND_STSBIT)
+		puts("mSATA\n");
+	else
+		puts("MiniPCIe\n");
+
+	return stsword & MSATA_IND_STSBIT ? true : false;
+}
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	if (omnia_detect_sata()) {
+		*serdes_map_array = board_serdes_map_sata;
+		*count = ARRAY_SIZE(board_serdes_map_sata);
+	} else {
+		*serdes_map_array = board_serdes_map_pex;
+		*count = ARRAY_SIZE(board_serdes_map_pex);
+	}
+
+	return 0;
+}
+
+struct omnia_eeprom {
+	u32 magic;
+	u32 ramsize;
+	char region[4];
+	u32 crc;
+};
+
+static bool omnia_read_eeprom(struct omnia_eeprom *oep)
+{
+	struct udevice *chip;
+	u32 crc;
+	int ret;
+
+	chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
+				  OMNIA_I2C_EEPROM_CHIP_LEN);
+
+	if (!chip)
+		return false;
+
+	ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
+	if (ret) {
+		printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
+		return false;
+	}
+
+	if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
+		printf("bad EEPROM magic number (%08x, should be %08x)\n",
+		       oep->magic, OMNIA_I2C_EEPROM_MAGIC);
+		return false;
+	}
+
+	crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
+	if (crc != oep->crc) {
+		printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
+		       oep->crc, crc);
+		return false;
+	}
+
+	return true;
+}
+
+static int omnia_get_ram_size_gb(void)
+{
+	static int ram_size;
+	struct omnia_eeprom oep;
+
+	if (!ram_size) {
+		/* Get the board config from EEPROM */
+		if (omnia_read_eeprom(&oep)) {
+			debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
+
+			if (oep.ramsize == 0x2)
+				ram_size = 2;
+			else
+				ram_size = 1;
+		} else {
+			/* Hardcoded fallback */
+			puts("Memory config from EEPROM read failed!\n");
+			puts("Falling back to default 1 GiB!\n");
+			ram_size = 1;
+		}
+	}
+
+	return ram_size;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct mv_ddr_topology_map board_topology_map_1g = {
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1600K,	/* speed_bin */
+	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
+	    MV_DDR_DIE_CAP_4GBIT,			/* mem_size */
+	    MV_DDR_FREQ_800,		/* frequency */
+	    0, 0,			/* cas_wl cas_l */
+	    MV_DDR_TEMP_NORMAL,		/* temperature */
+	    MV_DDR_TIM_2T} },		/* timing */
+	BUS_MASK_32BIT,			/* Busses mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+static struct mv_ddr_topology_map board_topology_map_2g = {
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1600K,	/* speed_bin */
+	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
+	    MV_DDR_DIE_CAP_8GBIT,			/* mem_size */
+	    MV_DDR_FREQ_800,		/* frequency */
+	    0, 0,			/* cas_wl cas_l */
+	    MV_DDR_TEMP_NORMAL,		/* temperature */
+	    MV_DDR_TIM_2T} },		/* timing */
+	BUS_MASK_32BIT,			/* Busses mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	if (omnia_get_ram_size_gb() == 2)
+		return &board_topology_map_2g;
+	else
+		return &board_topology_map_1g;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int set_regdomain(void)
+{
+	struct omnia_eeprom oep;
+	char rd[3] = {' ', ' ', 0};
+
+	if (omnia_read_eeprom(&oep))
+		memcpy(rd, &oep.region, 2);
+	else
+		puts("EEPROM regdomain read failed.\n");
+
+	printf("Regdomain set to %s\n", rd);
+	return env_set("regdomain", rd);
+}
+
+static void handle_reset_button(void)
+{
+	const char * const vars[1] = { "bootcmd_rescue", };
+	int ret;
+	u8 reset_status;
+
+	/*
+	 * Ensure that bootcmd_rescue has always stock value, so that running
+	 *   run bootcmd_rescue
+	 * always works correctly.
+	 */
+	env_set_default_vars(1, (char * const *)vars, 0);
+
+	ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
+	if (ret) {
+		printf("omnia_mcu_read failed: %i, reset status unknown!\n",
+		       ret);
+		return;
+	}
+
+	env_set_ulong("omnia_reset", reset_status);
+
+	if (reset_status) {
+		const char * const vars[2] = {
+			"bootcmd",
+			"distro_bootcmd",
+		};
+
+		/*
+		 * Set the above envs to their default values, in case the user
+		 * managed to break them.
+		 */
+		env_set_default_vars(2, (char * const *)vars, 0);
+
+		/* Ensure bootcmd_rescue is used by distroboot */
+		env_set("boot_targets", "rescue");
+
+		printf("RESET button was pressed, overwriting bootcmd!\n");
+	} else {
+		/*
+		 * In case the user somehow managed to save environment with
+		 * boot_targets=rescue, reset boot_targets to default value.
+		 * This could happen in subsequent commands if bootcmd_rescue
+		 * failed.
+		 */
+		if (!strcmp(env_get("boot_targets"), "rescue")) {
+			const char * const vars[1] = {
+				"boot_targets",
+			};
+
+			env_set_default_vars(1, (char * const *)vars, 0);
+		}
+	}
+}
+#endif
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+	writel(0x11244011, MVEBU_MPP_BASE + 0x08);
+	writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
+	writel(0x22200002, MVEBU_MPP_BASE + 0x10);
+	writel(0x30042022, MVEBU_MPP_BASE + 0x14);
+	writel(0x55550555, MVEBU_MPP_BASE + 0x18);
+	writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+#ifndef CONFIG_SPL_BUILD
+	disable_mcu_watchdog();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifndef CONFIG_SPL_BUILD
+	set_regdomain();
+	handle_reset_button();
+#endif
+	pci_init();
+
+	return 0;
+}
+
+static struct udevice *get_atsha204a_dev(void)
+{
+	static struct udevice *dev;
+
+	if (dev)
+		return dev;
+
+	if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
+		puts("Cannot find ATSHA204A on I2C bus!\n");
+		dev = NULL;
+	}
+
+	return dev;
+}
+
+int checkboard(void)
+{
+	u32 version_num, serial_num;
+	int err = 1;
+
+	struct udevice *dev = get_atsha204a_dev();
+
+	if (dev) {
+		err = atsha204a_wakeup(dev);
+		if (err)
+			goto out;
+
+		err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+				     OMNIA_ATSHA204_OTP_VERSION,
+				     (u8 *)&version_num);
+		if (err)
+			goto out;
+
+		err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+				     OMNIA_ATSHA204_OTP_SERIAL,
+				     (u8 *)&serial_num);
+		if (err)
+			goto out;
+
+		atsha204a_sleep(dev);
+	}
+
+out:
+	printf("Turris Omnia:\n");
+	printf("  RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
+	if (err)
+		printf("  Serial Number: unknown\n");
+	else
+		printf("  Serial Number: %08X%08X\n", be32_to_cpu(version_num),
+		       be32_to_cpu(serial_num));
+
+	return 0;
+}
+
+static void increment_mac(u8 *mac)
+{
+	int i;
+
+	for (i = 5; i >= 3; i--) {
+		mac[i] += 1;
+		if (mac[i])
+			break;
+	}
+}
+
+int misc_init_r(void)
+{
+	int err;
+	struct udevice *dev = get_atsha204a_dev();
+	u8 mac0[4], mac1[4], mac[6];
+
+	if (!dev)
+		goto out;
+
+	err = atsha204a_wakeup(dev);
+	if (err)
+		goto out;
+
+	err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+			     OMNIA_ATSHA204_OTP_MAC0, mac0);
+	if (err)
+		goto out;
+
+	err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+			     OMNIA_ATSHA204_OTP_MAC1, mac1);
+	if (err)
+		goto out;
+
+	atsha204a_sleep(dev);
+
+	mac[0] = mac0[1];
+	mac[1] = mac0[2];
+	mac[2] = mac0[3];
+	mac[3] = mac1[1];
+	mac[4] = mac1[2];
+	mac[5] = mac1[3];
+
+	if (is_valid_ethaddr(mac))
+		eth_env_set_enetaddr("eth1addr", mac);
+
+	increment_mac(mac);
+
+	if (is_valid_ethaddr(mac))
+		eth_env_set_enetaddr("eth2addr", mac);
+
+	increment_mac(mac);
+
+	if (is_valid_ethaddr(mac))
+		eth_env_set_enetaddr("ethaddr", mac);
+
+out:
+	return 0;
+}
+
diff --git a/roms/u-boot/board/CarMediaLab/flea3/Kconfig b/roms/u-boot/board/CarMediaLab/flea3/Kconfig
new file mode 100644
index 000000000..7113f2b51
--- /dev/null
+++ b/roms/u-boot/board/CarMediaLab/flea3/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_FLEA3
+
+config SYS_BOARD
+	default "flea3"
+
+config SYS_VENDOR
+	default "CarMediaLab"
+
+config SYS_SOC
+	default "mx35"
+
+config SYS_CONFIG_NAME
+	default "flea3"
+
+endif
diff --git a/roms/u-boot/board/CarMediaLab/flea3/MAINTAINERS b/roms/u-boot/board/CarMediaLab/flea3/MAINTAINERS
new file mode 100644
index 000000000..c7b0df7bc
--- /dev/null
+++ b/roms/u-boot/board/CarMediaLab/flea3/MAINTAINERS
@@ -0,0 +1,6 @@
+FLEA3 BOARD
+M:	Stefano Babic <sbabic@denx.de>
+S:	Maintained
+F:	board/CarMediaLab/flea3/
+F:	include/configs/flea3.h
+F:	configs/flea3_defconfig
diff --git a/roms/u-boot/board/CarMediaLab/flea3/Makefile b/roms/u-boot/board/CarMediaLab/flea3/Makefile
new file mode 100644
index 000000000..edaac8683
--- /dev/null
+++ b/roms/u-boot/board/CarMediaLab/flea3/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+
+obj-y	:= flea3.o
+obj-y	+= lowlevel_init.o
diff --git a/roms/u-boot/board/CarMediaLab/flea3/flea3.c b/roms/u-boot/board/CarMediaLab/flea3/flea3.c
new file mode 100644
index 000000000..12c5ac331
--- /dev/null
+++ b/roms/u-boot/board/CarMediaLab/flea3/flea3.c
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <env.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux-mx35.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+#include <fdt_support.h>
+#include <mtd_node.h>
+#include <jffs2/load_kernel.h>
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define CCM_CCMR_CONFIG		0x003F4208
+
+#define ESDCTL_DDR2_CONFIG	0x007FFC3F
+
+static inline void dram_wait(unsigned int count)
+{
+	volatile unsigned int wait = count;
+
+	while (wait--)
+		;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+		PHYS_SDRAM_1_SIZE);
+
+	return 0;
+}
+
+static void board_setup_sdram(void)
+{
+	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+	/* Initialize with default values both CSD0/1 */
+	writel(0x2000, &esdc->esdctl0);
+	writel(0x2000, &esdc->esdctl1);
+
+
+	mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+			     13, 10, 2, 0x8080);
+}
+
+static void setup_iomux_uart3(void)
+{
+	static const iomux_v3_cfg_t uart3_pads[] = {
+		MX35_PAD_RTS2__UART3_RXD_MUX,
+		MX35_PAD_CTS2__UART3_TXD_MUX,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+	static const iomux_v3_cfg_t i2c_pads[] = {
+		NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
+
+		NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
+}
+
+
+static void setup_iomux_spi(void)
+{
+	static const iomux_v3_cfg_t spi_pads[] = {
+		MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
+		MX35_PAD_CSPI1_MISO__CSPI1_MISO,
+		MX35_PAD_CSPI1_SS0__CSPI1_SS0,
+		MX35_PAD_CSPI1_SS1__CSPI1_SS1,
+		MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+}
+
+static void setup_iomux_fec(void)
+{
+	static const iomux_v3_cfg_t fec_pads[] = {
+		MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+		MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+		MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+		MX35_PAD_FEC_COL__FEC_COL,
+		MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+		MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+		MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+		MX35_PAD_FEC_MDC__FEC_MDC,
+		MX35_PAD_FEC_MDIO__FEC_MDIO,
+		MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+		MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+		MX35_PAD_FEC_CRS__FEC_CRS,
+		MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+		MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+		MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+		MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+		MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+		MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+		/* GPIO used to power off ethernet */
+		MX35_PAD_STXFS4__GPIO2_31,
+	};
+
+	/* setup pins for FEC */
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+int board_early_init_f(void)
+{
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	/* setup GPIO3_1 to set HighVCore signal */
+	imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
+	gpio_direction_output(65, 1);
+
+	/* initialize PLL and clock configuration */
+	writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+	writel(CCM_MPLL_532_HZ, &ccm->mpctl);
+	writel(CCM_PPLL_300_HZ, &ccm->ppctl);
+
+	/* Set the core to run at 532 Mhz */
+	writel(0x00001000, &ccm->pdr0);
+
+	/* Set-up RAM */
+	board_setup_sdram();
+
+	/* enable clocks */
+	writel(readl(&ccm->cgr0) |
+		MXC_CCM_CGR0_EMI_MASK |
+		MXC_CCM_CGR0_EDIO_MASK |
+		MXC_CCM_CGR0_EPIT1_MASK,
+		&ccm->cgr0);
+
+	writel(readl(&ccm->cgr1) |
+		MXC_CCM_CGR1_FEC_MASK |
+		MXC_CCM_CGR1_GPIO1_MASK |
+		MXC_CCM_CGR1_GPIO2_MASK |
+		MXC_CCM_CGR1_GPIO3_MASK |
+		MXC_CCM_CGR1_I2C1_MASK |
+		MXC_CCM_CGR1_I2C2_MASK |
+		MXC_CCM_CGR1_I2C3_MASK,
+		&ccm->cgr1);
+
+	/* Set-up NAND */
+	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+	/* Set pinmux for the required peripherals */
+	setup_iomux_uart3();
+	setup_iomux_i2c();
+	setup_iomux_fec();
+	setup_iomux_spi();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	/* Enable power for ethernet */
+	gpio_direction_output(63, 0);
+
+	udelay(2000);
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	int rev = 0;
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+/*
+ * called prior to booting kernel or by 'fdt boardsetup' command
+ *
+ */
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	static const struct node_info nodes[] = {
+		{ "physmap-flash.0", MTD_DEV_TYPE_NOR, },  /* NOR flash */
+		{ "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+	};
+
+	if (env_get("fdt_noauto")) {
+		puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
+		return 0;
+	}
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+	return 0;
+}
diff --git a/roms/u-boot/board/CarMediaLab/flea3/lowlevel_init.S b/roms/u-boot/board/CarMediaLab/flea3/lowlevel_init.S
new file mode 100644
index 000000000..8186b3922
--- /dev/null
+++ b/roms/u-boot/board/CarMediaLab/flea3/lowlevel_init.S
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ */
+
+#include <config.h>
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+	core_init
+
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	mov pc, lr
diff --git a/roms/u-boot/board/LaCie/common/common.c b/roms/u-boot/board/LaCie/common/common.c
new file mode 100644
index 000000000..52880a16f
--- /dev/null
+++ b/roms/u-boot/board/LaCie/common/common.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+
+#define MII_MARVELL_PHY_PAGE		22
+
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+void mv_phy_88e1116_init(const char *name, u16 phyaddr)
+{
+	u16 reg;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+	miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
+
+	if (miiphy_reset(name, phyaddr) == 0)
+		printf("88E1116 Initialized on %s\n", name);
+}
+
+void mv_phy_88e1318_init(const char *name, u16 phyaddr)
+{
+	u16 reg;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/*
+	 * Set control mode 4 for LED[0].
+	 */
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
+	miiphy_read(name, phyaddr, 16, &reg);
+	reg |= 0xf;
+	miiphy_write(name, phyaddr, 16, reg);
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+	miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
+	miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
+
+	if (miiphy_reset(name, phyaddr) == 0)
+		printf("88E1318 Initialized on %s\n", name);
+}
+#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
+
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+int lacie_read_mac_address(uchar *mac_addr)
+{
+	int ret;
+	ushort version;
+
+	/* I2C-0 for on-board EEPROM */
+	i2c_set_bus_num(0);
+
+	/* Check layout version for EEPROM data */
+	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+			CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+			(uchar *) &version, 2);
+	if (ret != 0) {
+		printf("Error: failed to read I2C EEPROM @%02x\n",
+			CONFIG_SYS_I2C_EEPROM_ADDR);
+		return ret;
+	}
+	version = be16_to_cpu(version);
+	if (version < 1 || version > 3) {
+		printf("Error: unknown version %d for EEPROM data\n",
+			version);
+		return -1;
+	}
+
+	/* Read Ethernet MAC address from EEPROM */
+	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2,
+			CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6);
+	if (ret != 0)
+		printf("Error: failed to read I2C EEPROM @%02x\n",
+			CONFIG_SYS_I2C_EEPROM_ADDR);
+	return ret;
+}
+#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */
diff --git a/roms/u-boot/board/LaCie/common/common.h b/roms/u-boot/board/LaCie/common/common.h
new file mode 100644
index 000000000..bf75d0a09
--- /dev/null
+++ b/roms/u-boot/board/LaCie/common/common.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ */
+
+#ifndef _LACIE_COMMON_H
+#define _LACIE_COMMON_H
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+void mv_phy_88e1116_init(const char *name, u16 phyaddr);
+void mv_phy_88e1318_init(const char *name, u16 phyaddr);
+#endif
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+int lacie_read_mac_address(uchar *mac);
+#endif
+
+#endif /* _LACIE_COMMON_H */
diff --git a/roms/u-boot/board/LaCie/common/cpld-gpio-bus.c b/roms/u-boot/board/LaCie/common/cpld-gpio-bus.c
new file mode 100644
index 000000000..b95fcfa42
--- /dev/null
+++ b/roms/u-boot/board/LaCie/common/cpld-gpio-bus.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * cpld-gpio-bus.c: provides support for the CPLD GPIO bus found on some LaCie
+ * boards (as the 2Big/5Big Network v2 and the 2Big NAS). This parallel GPIO
+ * bus exposes two registers (address and data). Each of this register is made
+ * up of several dedicated GPIOs. An extra GPIO is used to notify the CPLD that
+ * the registers have been updated.
+ *
+ * Mostly this bus is used to configure the LEDs on LaCie boards.
+ *
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ */
+
+#include <asm/arch/gpio.h>
+#include "cpld-gpio-bus.h"
+
+static void cpld_gpio_bus_set_addr(struct cpld_gpio_bus *bus, unsigned addr)
+{
+	int pin;
+
+	for (pin = 0; pin < bus->num_addr; pin++)
+		kw_gpio_set_value(bus->addr[pin], (addr >> pin) & 1);
+}
+
+static void cpld_gpio_bus_set_data(struct cpld_gpio_bus *bus, unsigned data)
+{
+	int pin;
+
+	for (pin = 0; pin < bus->num_data; pin++)
+		kw_gpio_set_value(bus->data[pin], (data >> pin) & 1);
+}
+
+static void cpld_gpio_bus_enable_select(struct cpld_gpio_bus *bus)
+{
+	/* The transfer is enabled on the raising edge. */
+	kw_gpio_set_value(bus->enable, 0);
+	kw_gpio_set_value(bus->enable, 1);
+}
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *bus,
+			 unsigned addr, unsigned value)
+{
+	cpld_gpio_bus_set_addr(bus, addr);
+	cpld_gpio_bus_set_data(bus, value);
+	cpld_gpio_bus_enable_select(bus);
+}
diff --git a/roms/u-boot/board/LaCie/common/cpld-gpio-bus.h b/roms/u-boot/board/LaCie/common/cpld-gpio-bus.h
new file mode 100644
index 000000000..8db832356
--- /dev/null
+++ b/roms/u-boot/board/LaCie/common/cpld-gpio-bus.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ */
+
+#ifndef _LACIE_CPLD_GPI0_BUS_H
+#define _LACIE_CPLD_GPI0_BUS_H
+
+struct cpld_gpio_bus {
+	unsigned *addr;
+	unsigned num_addr;
+	unsigned *data;
+	unsigned num_data;
+	unsigned enable;
+};
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *cpld_gpio_bus,
+			 unsigned addr, unsigned value);
+
+#endif /* _LACIE_CPLD_GPI0_BUS_H */
diff --git a/roms/u-boot/board/LaCie/edminiv2/Kconfig b/roms/u-boot/board/LaCie/edminiv2/Kconfig
new file mode 100644
index 000000000..ac3fe3fbc
--- /dev/null
+++ b/roms/u-boot/board/LaCie/edminiv2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_EDMINIV2
+
+config SYS_BOARD
+	default "edminiv2"
+
+config SYS_VENDOR
+	default "LaCie"
+
+config SYS_CONFIG_NAME
+	default "edminiv2"
+
+endif
diff --git a/roms/u-boot/board/LaCie/edminiv2/MAINTAINERS b/roms/u-boot/board/LaCie/edminiv2/MAINTAINERS
new file mode 100644
index 000000000..e0591f4b8
--- /dev/null
+++ b/roms/u-boot/board/LaCie/edminiv2/MAINTAINERS
@@ -0,0 +1,6 @@
+EDMINIV2 BOARD
+M:	Albert ARIBAUD <albert.u.boot@aribaud.net>
+S:	Maintained
+F:	board/LaCie/edminiv2/
+F:	include/configs/edminiv2.h
+F:	configs/edminiv2_defconfig
diff --git a/roms/u-boot/board/LaCie/edminiv2/Makefile b/roms/u-boot/board/LaCie/edminiv2/Makefile
new file mode 100644
index 000000000..5252c2b0e
--- /dev/null
+++ b/roms/u-boot/board/LaCie/edminiv2/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= edminiv2.o ../common/common.o
diff --git a/roms/u-boot/board/LaCie/edminiv2/edminiv2.c b/roms/u-boot/board/LaCie/edminiv2/edminiv2.c
new file mode 100644
index 000000000..9c066a283
--- /dev/null
+++ b/roms/u-boot/board/LaCie/edminiv2/edminiv2.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/arch/orion5x.h>
+#include <asm/global_data.h>
+#include "../common/common.h"
+#include <spl.h>
+#include <ns16550.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* arch number of board */
+	gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
+
+	/* boot parameter start at 256th byte of RAM base */
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+	return 0;
+}
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	mv_phy_88e1116_init("egiga0", 8);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+/*
+ * SPL serial setup and NOR boot device selection
+ */
+
+#ifdef CONFIG_SPL_BUILD
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NOR;
+}
+
+#endif /* CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/LaCie/net2big_v2/Kconfig b/roms/u-boot/board/LaCie/net2big_v2/Kconfig
new file mode 100644
index 000000000..ba460dba4
--- /dev/null
+++ b/roms/u-boot/board/LaCie/net2big_v2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NET2BIG_V2
+
+config SYS_BOARD
+	default "net2big_v2"
+
+config SYS_VENDOR
+	default "LaCie"
+
+config SYS_CONFIG_NAME
+	default "lacie_kw"
+
+endif
diff --git a/roms/u-boot/board/LaCie/net2big_v2/MAINTAINERS b/roms/u-boot/board/LaCie/net2big_v2/MAINTAINERS
new file mode 100644
index 000000000..7046e1b2c
--- /dev/null
+++ b/roms/u-boot/board/LaCie/net2big_v2/MAINTAINERS
@@ -0,0 +1,13 @@
+NET2BIG_V2 BOARD
+M:	Simon Guinot <simon.guinot@sequanux.org>
+S:	Maintained
+F:	arch/arm/dts/kirkwood-d2net.dts
+F:	arch/arm/dts/kirkwood-d2net-u-boot.dtsi
+F:	arch/arm/dts/kirkwood-d2net.dtsi
+F:	arch/arm/dts/kirkwood-net2big.dts
+F:	arch/arm/dts/kirkwood-net2big-u-boot.dtsi
+F:	arch/arm/dts/kirkwood-netxbig.dtsi
+F:	board/LaCie/net2big_v2/
+F:	include/configs/lacie_kw.h
+F:	configs/d2net_v2_defconfig
+F:	configs/net2big_v2_defconfig
diff --git a/roms/u-boot/board/LaCie/net2big_v2/Makefile b/roms/u-boot/board/LaCie/net2big_v2/Makefile
new file mode 100644
index 000000000..3d12b7281
--- /dev/null
+++ b/roms/u-boot/board/LaCie/net2big_v2/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= net2big_v2.o ../common/common.o
+ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
+obj-y	+= ../common/cpld-gpio-bus.o
+endif
diff --git a/roms/u-boot/board/LaCie/net2big_v2/kwbimage.cfg b/roms/u-boot/board/LaCie/net2big_v2/kwbimage.cfg
new file mode 100644
index 000000000..3897a1197
--- /dev/null
+++ b/roms/u-boot/board/LaCie/net2big_v2/kwbimage.cfg
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000C30	# DDR Configuration register
+# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x38743000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A32	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000CCCC	#  DDR Address Control
+# bit1-0:   01, Cs0width=x16
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000662	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000044	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd enabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  1  , D2P Latency enabled
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00096630	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00009663	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit3-0:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/LaCie/net2big_v2/net2big_v2.c b/roms/u-boot/board/LaCie/net2big_v2/net2big_v2.c
new file mode 100644
index 000000000..695d6f6ed
--- /dev/null
+++ b/roms/u-boot/board/LaCie/net2big_v2/net2big_v2.c
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#include "net2big_v2.h"
+#include "../common/common.h"
+#include "../common/cpld-gpio-bus.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/* GPIO configuration */
+	mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
+			  NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,		/* Request power-off */
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP13_GPIO,		/* Rear power switch (on|auto) */
+		MPP14_GPIO,		/* USB fuse alarm */
+		MPP15_GPIO,		/* Rear power switch (auto|off) */
+		MPP16_GPIO,		/* SATA HDD1 power */
+		MPP17_GPIO,		/* SATA HDD2 power */
+		MPP20_SATA1_ACTn,
+		MPP21_SATA0_ACTn,
+		MPP24_GPIO,		/* USB mode select */
+		MPP26_GPIO,		/* USB device vbus */
+		MPP28_GPIO,		/* USB enable host vbus */
+		MPP29_GPIO,		/* CPLD GPIO bus ALE */
+		MPP34_GPIO,		/* Rear Push button 0=on 1=off */
+		MPP35_GPIO,		/* Inhibit switch power-off */
+		MPP36_GPIO,		/* SATA HDD1 presence */
+		MPP37_GPIO,		/* SATA HDD2 presence */
+		MPP40_GPIO,		/* eSATA presence */
+		MPP44_GPIO,		/* CPLD GPIO bus (data 0) */
+		MPP45_GPIO,		/* CPLD GPIO bus (data 1) */
+		MPP46_GPIO,		/* CPLD GPIO bus (data 2) */
+		MPP47_GPIO,		/* CPLD GPIO bus (addr 0) */
+		MPP48_GPIO,		/* CPLD GPIO bus (addr 1) */
+		MPP49_GPIO,		/* CPLD GPIO bus (addr 2) */
+		0
+	};
+
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Machine number */
+	gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
+
+	/* Boot parameters address */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR)
+/*
+ * Start I2C fan (GMT G762 controller)
+ */
+static void init_fan(void)
+{
+	u8 data;
+
+	i2c_set_bus_num(0);
+
+	/* Enable open-loop and PWM modes */
+	data = 0x20;
+	if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+		      G762_REG_FAN_CMD1, 1, &data, 1) != 0)
+		goto err;
+	data = 0;
+	if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+		      G762_REG_SET_CNT, 1, &data, 1) != 0)
+		goto err;
+	/*
+	 * RPM to PWM (set_out register) fan speed conversion array:
+	 * 0    0x00
+	 * 1500	0x04
+	 * 2800	0x08
+	 * 3400	0x0C
+	 * 3700	0x10
+	 * 4400	0x20
+	 * 4700	0x30
+	 * 4800	0x50
+	 * 5200	0x80
+	 * 5400	0xC0
+	 * 5500	0xFF
+	 *
+	 * Start fan at low speed (2800 RPM):
+	 */
+	data = 0x08;
+	if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+		      G762_REG_SET_OUT, 1, &data, 1) != 0)
+		goto err;
+
+	return;
+err:
+	printf("Error: failed to start I2C fan @%02x\n",
+	       CONFIG_SYS_I2C_G762_ADDR);
+}
+#else
+static void init_fan(void) {}
+#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */
+
+#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
+/*
+ * CPLD GPIO bus:
+ *
+ * - address register : bit [0-2] -> GPIO [47-49]
+ * - data register    : bit [0-2] -> GPIO [44-46]
+ * - enable register  : GPIO 29
+ */
+static unsigned cpld_gpio_bus_addr[] = { 47, 48, 49 };
+static unsigned cpld_gpio_bus_data[] = { 44, 45, 46 };
+
+static struct cpld_gpio_bus cpld_gpio_bus = {
+	.addr		= cpld_gpio_bus_addr,
+	.num_addr	= ARRAY_SIZE(cpld_gpio_bus_addr),
+	.data		= cpld_gpio_bus_data,
+	.num_data	= ARRAY_SIZE(cpld_gpio_bus_data),
+	.enable		= 29,
+};
+
+/*
+ * LEDs configuration:
+ *
+ * The LEDs are controlled by a CPLD and can be configured through
+ * the CPLD GPIO bus.
+ *
+ * Address register selection:
+ *
+ * addr | register
+ * ----------------------------
+ *   0  | front LED
+ *   1  | front LED brightness
+ *   2  | SATA LED brightness
+ *   3  | SATA0 LED
+ *   4  | SATA1 LED
+ *   5  | SATA2 LED
+ *   6  | SATA3 LED
+ *   7  | SATA4 LED
+ *
+ * Data register configuration:
+ *
+ * data | LED brightness
+ * -------------------------------------------------
+ *   0  | min (off)
+ *   -  | -
+ *   7  | max
+ *
+ * data | front LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | fix blue on
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | blink blue on=0.5 sec and blue off=2.5 sec
+ *
+ * data | SATA LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | SATA activity blink
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | fix blue on
+ */
+static void init_leds(void)
+{
+	/* Enable the front blue LED */
+	cpld_gpio_bus_write(&cpld_gpio_bus, 0, 1);
+	cpld_gpio_bus_write(&cpld_gpio_bus, 1, 3);
+
+	/* Configure SATA LEDs to blink in relation with the SATA activity */
+	cpld_gpio_bus_write(&cpld_gpio_bus, 3, 1);
+	cpld_gpio_bus_write(&cpld_gpio_bus, 4, 1);
+	cpld_gpio_bus_write(&cpld_gpio_bus, 2, 3);
+}
+#else
+static void init_leds(void) {}
+#endif /* CONFIG_NET2BIG_V2 && CONFIG_KIRKWOOD_GPIO */
+
+int misc_init_r(void)
+{
+	init_fan();
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+	if (!env_get("ethaddr")) {
+		uchar mac[6];
+		if (lacie_read_mac_address(mac) == 0)
+			eth_env_set_enetaddr("ethaddr", mac);
+	}
+#endif
+	init_leds();
+
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+	mv_phy_88e1116_init("ethernet-controller@72000", 8);
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO)
+/* Return GPIO push button status */
+static int
+do_read_push_button(struct cmd_tbl *cmdtp, int flag, int argc,
+		    char *const argv[])
+{
+	return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON);
+}
+
+U_BOOT_CMD(button, 1, 1, do_read_push_button,
+	   "Return GPIO push button status 0=off 1=on", "");
+#endif
diff --git a/roms/u-boot/board/LaCie/net2big_v2/net2big_v2.h b/roms/u-boot/board/LaCie/net2big_v2/net2big_v2.h
new file mode 100644
index 000000000..d61dd0e99
--- /dev/null
+++ b/roms/u-boot/board/LaCie/net2big_v2/net2big_v2.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef NET2BIG_V2_H
+#define NET2BIG_V2_H
+
+/* GPIO configuration */
+#define NET2BIG_V2_OE_LOW		0x0600E000
+#define NET2BIG_V2_OE_HIGH		0x00000134
+#define NET2BIG_V2_OE_VAL_LOW		0x10030000
+#define NET2BIG_V2_OE_VAL_HIGH		0x00000000
+
+/* Buttons */
+#define NET2BIG_V2_GPIO_PUSH_BUTTON	34
+
+/* GMT G762 registers (I2C fan controller) */
+#define G762_REG_SET_CNT		0x00
+#define G762_REG_SET_OUT		0x03
+#define G762_REG_FAN_CMD1		0x04
+
+#endif /* NET2BIG_V2_H */
diff --git a/roms/u-boot/board/LaCie/netspace_v2/Kconfig b/roms/u-boot/board/LaCie/netspace_v2/Kconfig
new file mode 100644
index 000000000..930b822df
--- /dev/null
+++ b/roms/u-boot/board/LaCie/netspace_v2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NETSPACE_V2
+
+config SYS_BOARD
+	default "netspace_v2"
+
+config SYS_VENDOR
+	default "LaCie"
+
+config SYS_CONFIG_NAME
+	default "lacie_kw"
+
+endif
diff --git a/roms/u-boot/board/LaCie/netspace_v2/MAINTAINERS b/roms/u-boot/board/LaCie/netspace_v2/MAINTAINERS
new file mode 100644
index 000000000..1cc4f7108
--- /dev/null
+++ b/roms/u-boot/board/LaCie/netspace_v2/MAINTAINERS
@@ -0,0 +1,21 @@
+NETSPACE_V2 BOARDS
+M:	Simon Guinot <simon.guinot@sequanux.org>
+S:	Maintained
+F:	arch/arm/dts/kirkwood-is2.dts
+F:	arch/arm/dts/kirkwood-is2-u-boot.dtsi
+F:	arch/arm/dts/kirkwood-ns2-common.dtsi
+F:	arch/arm/dts/kirkwood-ns2.dts
+F:	arch/arm/dts/kirkwood-ns2lite.dts
+F:	arch/arm/dts/kirkwood-ns2lite-u-boot.dtsi
+F:	arch/arm/dts/kirkwood-ns2max.dts
+F:	arch/arm/dts/kirkwood-ns2max-u-boot.dtsi
+F:	arch/arm/dts/kirkwood-ns2mini.dts
+F:	arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi
+F:	arch/arm/dts/kirkwood-ns2-u-boot.dtsi
+F:	board/LaCie/netspace_v2/
+F:	include/configs/lacie_kw.h
+F:	configs/inetspace_v2_defconfig
+F:	configs/netspace_lite_v2_defconfig
+F:	configs/netspace_max_v2_defconfig
+F:	configs/netspace_mini_v2_defconfig
+F:	configs/netspace_v2_defconfig
diff --git a/roms/u-boot/board/LaCie/netspace_v2/Makefile b/roms/u-boot/board/LaCie/netspace_v2/Makefile
new file mode 100644
index 000000000..a6270bdd4
--- /dev/null
+++ b/roms/u-boot/board/LaCie/netspace_v2/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= netspace_v2.o ../common/common.o
diff --git a/roms/u-boot/board/LaCie/netspace_v2/kwbimage-is2.cfg b/roms/u-boot/board/LaCie/netspace_v2/kwbimage-is2.cfg
new file mode 100644
index 000000000..50f584ae7
--- /dev/null
+++ b/roms/u-boot/board/LaCie/netspace_v2/kwbimage-is2.cfg
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618	# DDR Configuration register
+# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x35143000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228	# DDR Timing (Low) (active cycles value +1)
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000008	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   10, Cs0size=512Mb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000632	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd enabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  1  , D2P Latency enabled
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit3-0:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/roms/u-boot/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
new file mode 100644
index 000000000..092353a06
--- /dev/null
+++ b/roms/u-boot/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618	# DDR Configuration register
+# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x34143000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228	# DDR Timing (Low) (active cycles value +1)
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000DDDD	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   10, Cs0size=512Mb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000632	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd enabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  1  , D2P Latency enabled
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit3-0:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/LaCie/netspace_v2/kwbimage.cfg b/roms/u-boot/board/LaCie/netspace_v2/kwbimage.cfg
new file mode 100644
index 000000000..1ed03fa9a
--- /dev/null
+++ b/roms/u-boot/board/LaCie/netspace_v2/kwbimage.cfg
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618	# DDR Configuration register
+# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x35143000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228	# DDR Timing (Low) (active cycles value +1)
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000C	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000632	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd enabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  1  , D2P Latency enabled
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit3-0:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/LaCie/netspace_v2/netspace_v2.c b/roms/u-boot/board/LaCie/netspace_v2/netspace_v2.c
new file mode 100644
index 000000000..730eab7e7
--- /dev/null
+++ b/roms/u-boot/board/LaCie/netspace_v2/netspace_v2.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#include "netspace_v2.h"
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/* Gpio configuration */
+	mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
+			  NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,		/* Fan speed (bit 1) */
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_GPO,		/* Red led */
+		MPP14_GPIO,		/* USB fuse */
+		MPP16_GPIO,		/* SATA 0 power */
+		MPP17_GPIO,		/* SATA 1 power */
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_SATA1_ACTn,
+		MPP21_SATA0_ACTn,
+		MPP22_GPIO,		/* Fan speed (bit 0) */
+		MPP23_GPIO,		/* Fan power */
+		MPP24_GPIO,		/* USB mode select */
+		MPP25_GPIO,		/* Fan rotation fail */
+		MPP26_GPIO,		/* USB vbus-in detection */
+		MPP28_GPIO,		/* USB enable vbus-out */
+		MPP29_GPIO,		/* Blue led (slow register) */
+		MPP30_GPIO,		/* Blue led (command register) */
+		MPP31_GPIO,		/* Board power off */
+		MPP32_GPIO,		/* Button (0 = Released, 1 = Pushed) */
+		MPP33_GPIO,		/* Fan speed (bit 2) */
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Machine number */
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+	/* Boot parameters address */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+	if (!env_get("ethaddr")) {
+		uchar mac[6];
+		if (lacie_read_mac_address(mac) == 0)
+			eth_env_set_enetaddr("ethaddr", mac);
+	}
+#endif
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+	mv_phy_88e1318_init("ethernet-controller@72000", 0);
+#else
+	mv_phy_88e1116_init("ethernet-controller@72000", 8);
+#endif
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO)
+/* Return GPIO button status */
+static int
+do_read_button(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
+}
+
+U_BOOT_CMD(button, 1, 1, do_read_button,
+	   "Return GPIO button status 0=off 1=on", "");
+#endif
diff --git a/roms/u-boot/board/LaCie/netspace_v2/netspace_v2.h b/roms/u-boot/board/LaCie/netspace_v2/netspace_v2.h
new file mode 100644
index 000000000..2c930171e
--- /dev/null
+++ b/roms/u-boot/board/LaCie/netspace_v2/netspace_v2.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef NETSPACE_V2_H
+#define NETSPACE_V2_H
+
+/* GPIO configuration */
+#define NETSPACE_V2_OE_LOW		0x06004000
+#define NETSPACE_V2_OE_HIGH		0x00000031
+#define NETSPACE_V2_OE_VAL_LOW		0x10030000
+#define NETSPACE_V2_OE_VAL_HIGH		0x00000000
+
+#define NETSPACE_V2_GPIO_BUTTON         32
+
+#endif /* NETSPACE_V2_H */
diff --git a/roms/u-boot/board/Marvell/aspenite/Kconfig b/roms/u-boot/board/Marvell/aspenite/Kconfig
new file mode 100644
index 000000000..4dd49c445
--- /dev/null
+++ b/roms/u-boot/board/Marvell/aspenite/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ASPENITE
+
+config SYS_BOARD
+	default "aspenite"
+
+config SYS_VENDOR
+	default "Marvell"
+
+config SYS_SOC
+	default "armada100"
+
+config SYS_CONFIG_NAME
+	default "aspenite"
+
+endif
diff --git a/roms/u-boot/board/Marvell/aspenite/MAINTAINERS b/roms/u-boot/board/Marvell/aspenite/MAINTAINERS
new file mode 100644
index 000000000..a77d30eb7
--- /dev/null
+++ b/roms/u-boot/board/Marvell/aspenite/MAINTAINERS
@@ -0,0 +1,6 @@
+ASPENITE BOARD
+M:	Prafulla Wadaskar <prafulla@marvell.com>
+S:	Maintained
+F:	board/Marvell/aspenite/
+F:	include/configs/aspenite.h
+F:	configs/aspenite_defconfig
diff --git a/roms/u-boot/board/Marvell/aspenite/Makefile b/roms/u-boot/board/Marvell/aspenite/Makefile
new file mode 100644
index 000000000..f67a978a1
--- /dev/null
+++ b/roms/u-boot/board/Marvell/aspenite/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Contributor: Mahavir Jain <mjain@marvell.com>
+
+obj-y	:= aspenite.o
diff --git a/roms/u-boot/board/Marvell/aspenite/aspenite.c b/roms/u-boot/board/Marvell/aspenite/aspenite.c
new file mode 100644
index 000000000..1f9389c0a
--- /dev/null
+++ b/roms/u-boot/board/Marvell/aspenite/aspenite.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mvmfp.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* I2C */
+		MFP105_CI2C_SDA,
+		MFP106_CI2C_SCL,
+
+		/* Enable Console on UART1 */
+		MFP107_UART1_RXD,
+		MFP108_UART1_TXD,
+
+		MFP_EOC		/*End of configureation*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of Board */
+	gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+	return 0;
+}
diff --git a/roms/u-boot/board/Marvell/db-88f6720/MAINTAINERS b/roms/u-boot/board/Marvell/db-88f6720/MAINTAINERS
new file mode 100644
index 000000000..a27d1c2d6
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-88f6720/MAINTAINERS
@@ -0,0 +1,6 @@
+DB_88F6720 BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/Marvell/db-88f6720/
+F:	include/configs/db-88f6720.h
+F:	configs/db-88f6720_defconfig
diff --git a/roms/u-boot/board/Marvell/db-88f6720/Makefile b/roms/u-boot/board/Marvell/db-88f6720/Makefile
new file mode 100644
index 000000000..6c633132d
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-88f6720/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+
+obj-y	:= db-88f6720.o
diff --git a/roms/u-boot/board/Marvell/db-88f6720/db-88f6720.c b/roms/u-boot/board/Marvell/db-88f6720/db-88f6720.c
new file mode 100644
index 000000000..26c30647f
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-88f6720/db-88f6720.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720
+ */
+#define DB_88F6720_MPP0_7		0x00020020 /* SPI */
+#define DB_88F6720_MPP8_15		0x22000022 /* SPI , I2C */
+#define DB_88F6720_MPP16_23		0x22222222 /* UART, TDM*/
+#define DB_88F6720_MPP24_31		0x33333333 /* SDIO, SPI1*/
+#define DB_88F6720_MPP32_39		0x04403330 /* SPI1, External SMI */
+#define DB_88F6720_MPP40_47		0x22002044 /* UART1, GE0, SATA0 LED */
+#define DB_88F6720_MPP48_55		0x22222222 /* GE0 */
+#define DB_88F6720_MPP56_63		0x04444422 /* GE0 , LED_MATRIX, GPIO */
+#define DB_88F6720_MPP64_67		0x014	/* LED_MATRIX, SATA1 LED*/
+
+#define DB_88F6720_GPP_OUT_ENA_LOW	0xFFFFFFFF
+#define DB_88F6720_GPP_OUT_ENA_MID	0x7FFFFFFF
+#define DB_88F6720_GPP_OUT_ENA_HIGH	0xFFFFFFFF
+#define DB_88F6720_GPP_OUT_VAL_LOW	0x0
+#define DB_88F6720_GPP_OUT_VAL_MID	BIT(31)	/* SATA Power output enable */
+#define DB_88F6720_GPP_OUT_VAL_HIGH	0x0
+#define DB_88F6720_GPP_POL_LOW		0x0
+#define DB_88F6720_GPP_POL_MID		0x0
+#define DB_88F6720_GPP_POL_HIGH		0x0
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00);
+	writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04);
+	writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08);
+	writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c);
+	writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10);
+	writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14);
+	writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18);
+	writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c);
+	writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20);
+
+	/* Configure GPIO */
+	/* Set GPP Out value */
+	writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+	writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+	writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+	writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Marvell DB-88F6720\n");
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	cpu_eth_init(bis); /* Built in controller(s) come first */
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/Marvell/db-88f6820-amc/MAINTAINERS b/roms/u-boot/board/Marvell/db-88f6820-amc/MAINTAINERS
new file mode 100644
index 000000000..abf5b7efd
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-88f6820-amc/MAINTAINERS
@@ -0,0 +1,6 @@
+DB_88F6820_AMC BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/Marvell/db-88f6820-amc/
+F:	include/configs/db-88f6820-amc.h
+F:	configs/db-88f6820-amc_defconfig
diff --git a/roms/u-boot/board/Marvell/db-88f6820-amc/Makefile b/roms/u-boot/board/Marvell/db-88f6820-amc/Makefile
new file mode 100644
index 000000000..99bdf1a2c
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-88f6820-amc/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+
+obj-y	:= db-88f6820-amc.o
diff --git a/roms/u-boot/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/roms/u-boot/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
new file mode 100644
index 000000000..122c63d11
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/bitops.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2016_T1.0.eng_drop_v10"
+ */
+#define DB_AMC_88F68XX_GPP_OUT_ENA_LOW					\
+	(~(BIT(29)))
+#define DB_AMC_88F68XX_GPP_OUT_ENA_MID					\
+	(~(BIT(12) | BIT(17) | BIT(18) | BIT(20) | BIT(21)))
+#define DB_AMC_88F68XX_GPP_OUT_VAL_LOW	(BIT(29))
+#define DB_AMC_88F68XX_GPP_OUT_VAL_MID	0x0
+#define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH	0x0
+#define DB_AMC_88F68XX_GPP_POL_LOW	0x0
+#define DB_AMC_88F68XX_GPP_POL_MID	0x0
+
+static struct serdes_map board_serdes_map[] = {
+	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	*serdes_map_array = board_serdes_map;
+	*count = ARRAY_SIZE(board_serdes_map);
+	return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1866L,	/* speed_bin */
+	    MV_DDR_DEV_WIDTH_8BIT,	/* memory_width */
+	    MV_DDR_DIE_CAP_2GBIT,	/* mem_size */
+	    MV_DDR_FREQ_800,		/* frequency */
+	    0, 0,			/* cas_wl cas_l */
+	    MV_DDR_TEMP_LOW,		/* temperature */
+	    MV_DDR_TIM_DEFAULT} },	/* timing */
+	BUS_MASK_32BIT,			/* Busses mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+	writel(0x55066011, MVEBU_MPP_BASE + 0x08);
+	writel(0x05055550, MVEBU_MPP_BASE + 0x0c);
+	writel(0x05055555, MVEBU_MPP_BASE + 0x10);
+	writel(0x01106565, MVEBU_MPP_BASE + 0x14);
+	writel(0x40000000, MVEBU_MPP_BASE + 0x18);
+	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(DB_AMC_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(DB_AMC_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(DB_AMC_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(DB_AMC_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(DB_AMC_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(DB_AMC_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Marvell DB-88F6820-AMC\n");
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	cpu_eth_init(bis); /* Built in controller(s) come first */
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/Marvell/db-88f6820-gp/MAINTAINERS b/roms/u-boot/board/Marvell/db-88f6820-gp/MAINTAINERS
new file mode 100644
index 000000000..f5649400e
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-88f6820-gp/MAINTAINERS
@@ -0,0 +1,6 @@
+DB_88F6820_GP BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/Marvell/db-88f6820-gp/
+F:	include/configs/db-88f6820-gp.h
+F:	configs/db-88f6820-gp_defconfig
diff --git a/roms/u-boot/board/Marvell/db-88f6820-gp/Makefile b/roms/u-boot/board/Marvell/db-88f6820-gp/Makefile
new file mode 100644
index 000000000..afc964851
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-88f6820-gp/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+
+obj-y	:= db-88f6820-gp.o
diff --git a/roms/u-boot/board/Marvell/db-88f6820-gp/README b/roms/u-boot/board/Marvell/db-88f6820-gp/README
new file mode 100644
index 000000000..9bea5b35c
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-88f6820-gp/README
@@ -0,0 +1,18 @@
+Update from original Marvell U-Boot to mainline U-Boot:
+-------------------------------------------------------
+
+The resulting image including the SPL binary with the
+full DDR setup is "u-boot-spl.kwb".
+
+To update the SPI NOR flash, please use the following
+command:
+
+=> sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\
+sf update 2000000 0 60000
+
+Note that the original Marvell U-Boot seems to have
+problems with the "sf update" command. This does not
+work reliable. So here this command should be used:
+
+=> sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\
+sf erase 0 60000;sf write 2000000 0 60000
diff --git a/roms/u-boot/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/roms/u-boot/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
new file mode 100644
index 000000000..1edc1cb65
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/bitops.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2014_T3.0"
+ */
+#define DB_GP_88F68XX_GPP_OUT_ENA_LOW					\
+	(~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |	\
+	   BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |	\
+	   BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
+#define DB_GP_88F68XX_GPP_OUT_ENA_MID					\
+	(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |	\
+	   BIT(16) | BIT(17) | BIT(18)))
+
+#define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
+#define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x0
+#define DB_GP_88F68XX_GPP_POL_LOW	0x0
+#define DB_GP_88F68XX_GPP_POL_MID	0x0
+
+/* IO expander on Marvell GP board includes e.g. fan enabling */
+struct marvell_io_exp {
+	u8 chip;
+	u8 addr;
+	u8 val;
+};
+
+static struct marvell_io_exp io_exp[] = {
+	{ 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
+	{ 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
+	{ 0x20, 2, 0x1D }, /* Output Data, register#0 */
+	{ 0x20, 3, 0x18 }, /* Output Data, register#1 */
+	{ 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits  */
+	{ 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits  */
+	{ 0x21, 2, 0x08 }, /* Output Data, register#0 */
+	{ 0x21, 3, 0xC0 }  /* Output Data, register#1 */
+};
+
+static struct serdes_map board_serdes_map[] = {
+	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	*serdes_map_array = board_serdes_map;
+	*count = ARRAY_SIZE(board_serdes_map);
+	return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1866L,	/* speed_bin */
+	    MV_DDR_DEV_WIDTH_8BIT,	/* memory_width */
+	    MV_DDR_DIE_CAP_4GBIT,	/* mem_size */
+	    MV_DDR_FREQ_800,		/* frequency */
+	    0, 0,			/* cas_wl cas_l */
+	    MV_DDR_TEMP_LOW,		/* temperature */
+	    MV_DDR_TIM_DEFAULT} },	/* timing */
+	BUS_MASK_32BIT,			/* Busses mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+	writel(0x11244011, MVEBU_MPP_BASE + 0x08);
+	writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
+	writel(0x22200002, MVEBU_MPP_BASE + 0x10);
+	writel(0x30042022, MVEBU_MPP_BASE + 0x14);
+	writel(0x55550555, MVEBU_MPP_BASE + 0x18);
+	writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	int i;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/* Init I2C IO expanders */
+	for (i = 0; i < ARRAY_SIZE(io_exp); i++)
+		i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Marvell DB-88F6820-GP\n");
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	cpu_eth_init(bis); /* Built in controller(s) come first */
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/Marvell/db-mv784mp-gp/MAINTAINERS b/roms/u-boot/board/Marvell/db-mv784mp-gp/MAINTAINERS
new file mode 100644
index 000000000..a095f898d
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-mv784mp-gp/MAINTAINERS
@@ -0,0 +1,6 @@
+DB_MV784MP_GP BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/Marvell/db-mv784mp-gp/
+F:	include/configs/db-mv784mp-gp.h
+F:	configs/db-mv784mp-gp_defconfig
diff --git a/roms/u-boot/board/Marvell/db-mv784mp-gp/Makefile b/roms/u-boot/board/Marvell/db-mv784mp-gp/Makefile
new file mode 100644
index 000000000..1bd2388af
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-mv784mp-gp/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+
+obj-y	:= db-mv784mp-gp.o
diff --git a/roms/u-boot/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/roms/u-boot/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
new file mode 100644
index 000000000..9e1fdecfc
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ETH_PHY_CTRL_REG		0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT	11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
+ * "RD-AXP-GP rev 1.0".
+ *
+ * GPPs
+ * MPP#		NAME			IN/OUT
+ * ----------------------------------------------
+ * 21		SW_Reset_		OUT
+ * 25		Phy_Int#		IN
+ * 28		SDI_WP			IN
+ * 29		SDI_Status		IN
+ * 54-61	On GPP Connector	?
+ * 62		Switch Interrupt	IN
+ * 63-65	Reserved from SW Board	?
+ * 66		SW_BRD connected	IN
+ */
+#define RD_78460_GP_GPP_OUT_ENA_LOW	(~(BIT(21) | BIT(20)))
+#define RD_78460_GP_GPP_OUT_ENA_MID	(~(BIT(26) | BIT(27)))
+#define RD_78460_GP_GPP_OUT_ENA_HIGH	(~(0x0))
+
+#define RD_78460_GP_GPP_OUT_VAL_LOW	(BIT(21) | BIT(20))
+#define RD_78460_GP_GPP_OUT_VAL_MID	(BIT(26) | BIT(27))
+#define RD_78460_GP_GPP_OUT_VAL_HIGH	0x0
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x00000000, MVEBU_MPP_BASE + 0x00);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x04);
+	writel(0x33000000, MVEBU_MPP_BASE + 0x08);
+	writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x10);
+	writel(0x00221100, MVEBU_MPP_BASE + 0x14);
+	writel(0x00000003, MVEBU_MPP_BASE + 0x18);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x20);
+
+	/* Configure GPIO */
+	writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+	writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+	writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
+	writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Marvell DB-MV784MP-GP\n");
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	cpu_eth_init(bis); /* Built in controller(s) come first */
+	return pci_eth_init(bis);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	u16 reg;
+
+	/* Enable QSGMII AN */
+	/* Set page to 4 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
+	/* Enable AN */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
+	/* Set page to 0 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
+
+	/* Phy C_ANEG */
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
+	reg |= 0x1E0;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
+
+	/* Soft-Reset */
+	phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
+
+	/* Power up the phy */
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
+	reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
+	phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
+
+	printf("88E1545 Initialized\n");
+	return 0;
+}
diff --git a/roms/u-boot/board/Marvell/db-xc3-24g4xg/.gitignore b/roms/u-boot/board/Marvell/db-xc3-24g4xg/.gitignore
new file mode 100644
index 000000000..775b9346b
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-xc3-24g4xg/.gitignore
@@ -0,0 +1 @@
+kwbimage.cfg
diff --git a/roms/u-boot/board/Marvell/db-xc3-24g4xg/MAINTAINERS b/roms/u-boot/board/Marvell/db-xc3-24g4xg/MAINTAINERS
new file mode 100644
index 000000000..2b27e4818
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-xc3-24g4xg/MAINTAINERS
@@ -0,0 +1,7 @@
+DB-XC3-24G4XG BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/Marvell/db-xc3-24g4xg/
+F:	include/configs/db-xc3-24g4xg.h
+F:	configs/db-xc3-24g4xg_defconfig
+F:	arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
diff --git a/roms/u-boot/board/Marvell/db-xc3-24g4xg/Makefile b/roms/u-boot/board/Marvell/db-xc3-24g4xg/Makefile
new file mode 100644
index 000000000..24e820000
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-xc3-24g4xg/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+
+obj-y	:= db-xc3-24g4xg.o
+extra-y	:= kwbimage.cfg
+
+quiet_cmd_sed = SED     $@
+      cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F)
+
+SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|"
+$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
+		include/config/auto.conf
+	  $(call if_changed,sed)
diff --git a/roms/u-boot/board/Marvell/db-xc3-24g4xg/README b/roms/u-boot/board/Marvell/db-xc3-24g4xg/README
new file mode 100644
index 000000000..5e479b433
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-xc3-24g4xg/README
@@ -0,0 +1,4 @@
+To generate binary.0 from Marvell's bin_hdr.elf use the following command
+
+    arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \
+       board/Marvell/db-xc3-24g4xg/binary.0
diff --git a/roms/u-boot/board/Marvell/db-xc3-24g4xg/binary.0 b/roms/u-boot/board/Marvell/db-xc3-24g4xg/binary.0
new file mode 100644
index 000000000..8dd687286
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-xc3-24g4xg/binary.0
@@ -0,0 +1,11 @@
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
diff --git a/roms/u-boot/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c b/roms/u-boot/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
new file mode 100644
index 000000000..0abdca1cd
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <linux/bitops.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * These values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2016_T1.0.eng_drop_v6"
+ */
+#define DB_DX_AC3_GPP_OUT_ENA_LOW	(~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
+					| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29)  | BIT(30)))
+#define DB_DX_AC3_GPP_OUT_ENA_MID	(~(0))
+#define DB_DX_AC3_GPP_OUT_VAL_LOW	(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
+					| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29)  | BIT(30))
+#define DB_DX_AC3_GPP_OUT_VAL_MID	0x0
+#define DB_DX_AC3_GPP_POL_LOW		0x0
+#define DB_DX_AC3_GPP_POL_MID		0x0
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x00142222, MVEBU_MPP_BASE + 0x00);
+	writel(0x11122000, MVEBU_MPP_BASE + 0x04);
+	writel(0x44444004, MVEBU_MPP_BASE + 0x08);
+	writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
+	writel(0x00000001, MVEBU_MPP_BASE + 0x10);
+
+	/* Set GPP Out value */
+	writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	puts("Board: " CONFIG_SYS_BOARD "\n");
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in b/roms/u-boot/board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in
new file mode 100644
index 000000000..b8bb7a6eb
--- /dev/null
+++ b/roms/u-boot/board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068
diff --git a/roms/u-boot/board/Marvell/dreamplug/Kconfig b/roms/u-boot/board/Marvell/dreamplug/Kconfig
new file mode 100644
index 000000000..f65ff7371
--- /dev/null
+++ b/roms/u-boot/board/Marvell/dreamplug/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DREAMPLUG
+
+config SYS_BOARD
+	default "dreamplug"
+
+config SYS_VENDOR
+	default "Marvell"
+
+config SYS_CONFIG_NAME
+	default "dreamplug"
+
+endif
diff --git a/roms/u-boot/board/Marvell/dreamplug/MAINTAINERS b/roms/u-boot/board/Marvell/dreamplug/MAINTAINERS
new file mode 100644
index 000000000..2561ba813
--- /dev/null
+++ b/roms/u-boot/board/Marvell/dreamplug/MAINTAINERS
@@ -0,0 +1,6 @@
+DREAMPLUG BOARD
+M:	Jason Cooper <u-boot@lakedaemon.net>
+S:	Maintained
+F:	board/Marvell/dreamplug/
+F:	include/configs/dreamplug.h
+F:	configs/dreamplug_defconfig
diff --git a/roms/u-boot/board/Marvell/dreamplug/Makefile b/roms/u-boot/board/Marvell/dreamplug/Makefile
new file mode 100644
index 000000000..e239d591b
--- /dev/null
+++ b/roms/u-boot/board/Marvell/dreamplug/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2011
+# Jason Cooper <u-boot@lakedaemon.net>
+#
+# Based on work by:
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+
+obj-y	:= dreamplug.o
diff --git a/roms/u-boot/board/Marvell/dreamplug/dreamplug.c b/roms/u-boot/board/Marvell/dreamplug/dreamplug.c
new file mode 100644
index 000000000..e1c64b522
--- /dev/null
+++ b/roms/u-boot/board/Marvell/dreamplug/dreamplug.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/global_data.h>
+#include "dreamplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
+			  DREAMPLUG_OE_VAL_HIGH,
+			  DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,		/* SPI Flash */
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,	/* Serial */
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,		/* SDIO Slot */
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,		/* Gigabit Ethernet */
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GE1_8,
+		MPP29_GE1_9,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GE1_14,
+		MPP35_GE1_15,
+		MPP36_GPIO,		/* 7 external GPIO pins (36 - 45) */
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_TDM_SPI_SCK,
+		MPP41_TDM_SPI_MISO,
+		MPP42_TDM_SPI_MOSI,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,		/* Bluetooth LED */
+		MPP48_GPIO,		/* Wifi LED */
+		MPP49_GPIO,		/* Wifi AP LED */
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void mv_phy_88e1116_init(char *name)
+{
+	u16 reg;
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__func__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+	/* configure and initialize both PHY's */
+	mv_phy_88e1116_init("egiga0");
+	mv_phy_88e1116_init("egiga1");
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/roms/u-boot/board/Marvell/dreamplug/dreamplug.h b/roms/u-boot/board/Marvell/dreamplug/dreamplug.h
new file mode 100644
index 000000000..6f6223898
--- /dev/null
+++ b/roms/u-boot/board/Marvell/dreamplug/dreamplug.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ */
+
+#ifndef __DREAMPLUG_H
+#define __DREAMPLUG_H
+
+#define DREAMPLUG_OE_LOW	(~(0))
+#define DREAMPLUG_OE_HIGH	(~(0))
+#define DREAMPLUG_OE_VAL_LOW	0
+#define DREAMPLUG_OE_VAL_HIGH	(0xf << 16) /* 4 LED Pins high */
+
+/* PHY related */
+#define MV88E1116_MAC_CTRL2_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __DREAMPLUG_H */
diff --git a/roms/u-boot/board/Marvell/dreamplug/kwbimage.cfg b/roms/u-boot/board/Marvell/dreamplug/kwbimage.cfg
new file mode 100644
index 000000000..f916208c1
--- /dev/null
+++ b/roms/u-boot/board/Marvell/dreamplug/kwbimage.cfg
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2011
+# Jason Cooper <u-boot@lakedaemon.net>
+#
+# Based on work by:
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b9b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc	#  DDR Address Control
+# bit1-0:   01, Cs0width=x8
+# bit3-2:   10, Cs0size=1Gb
+# bit5-4:   01, Cs1width=x8
+# bit7-6:   10, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/Marvell/gplugd/Kconfig b/roms/u-boot/board/Marvell/gplugd/Kconfig
new file mode 100644
index 000000000..d94481650
--- /dev/null
+++ b/roms/u-boot/board/Marvell/gplugd/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_GPLUGD
+
+config SYS_BOARD
+	default "gplugd"
+
+config SYS_VENDOR
+	default "Marvell"
+
+config SYS_SOC
+	default "armada100"
+
+config SYS_CONFIG_NAME
+	default "gplugd"
+
+endif
diff --git a/roms/u-boot/board/Marvell/gplugd/MAINTAINERS b/roms/u-boot/board/Marvell/gplugd/MAINTAINERS
new file mode 100644
index 000000000..197c6a01d
--- /dev/null
+++ b/roms/u-boot/board/Marvell/gplugd/MAINTAINERS
@@ -0,0 +1,6 @@
+GPLUGD BOARD
+M:	Ajay Bhargav <contact@8051projects.net>
+S:	Maintained
+F:	board/Marvell/gplugd/
+F:	include/configs/gplugd.h
+F:	configs/gplugd_defconfig
diff --git a/roms/u-boot/board/Marvell/gplugd/Makefile b/roms/u-boot/board/Marvell/gplugd/Makefile
new file mode 100644
index 000000000..6161bf1c8
--- /dev/null
+++ b/roms/u-boot/board/Marvell/gplugd/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2011
+# eInfochips Ltd. <www.einfochips.com>
+# Written-by: Ajay Bhargav <contact@8051projects.net>
+#
+# Based on Aspenite:
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Contributor: Mahavir Jain <mjain@marvell.com>
+
+obj-y	:= gplugd.o
diff --git a/roms/u-boot/board/Marvell/gplugd/gplugd.c b/roms/u-boot/board/Marvell/gplugd/gplugd.c
new file mode 100644
index 000000000..c6376cdf6
--- /dev/null
+++ b/roms/u-boot/board/Marvell/gplugd/gplugd.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
+ *
+ * Based on Aspenite:
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <mvmfp.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/armada100.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <miiphy.h>
+#include <asm/mach-types.h>
+#include <linux/delay.h>
+
+#ifdef CONFIG_ARMADA100_FEC
+#include <net.h>
+#include <netdev.h>
+#endif /* CONFIG_ARMADA100_FEC */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* I2C */
+		MFP105_CI2C_SDA,
+		MFP106_CI2C_SCL,
+
+		/* Enable Console on UART3 */
+		MFPO8_UART3_TXD,
+		MFPO9_UART3_RXD,
+
+		/* Ethernet PHY Interface */
+		MFP086_ETH_TXCLK,
+		MFP087_ETH_TXEN,
+		MFP088_ETH_TXDQ3,
+		MFP089_ETH_TXDQ2,
+		MFP090_ETH_TXDQ1,
+		MFP091_ETH_TXDQ0,
+		MFP092_ETH_CRS,
+		MFP093_ETH_COL,
+		MFP094_ETH_RXCLK,
+		MFP095_ETH_RXER,
+		MFP096_ETH_RXDQ3,
+		MFP097_ETH_RXDQ2,
+		MFP098_ETH_RXDQ1,
+		MFP099_ETH_RXDQ0,
+		MFP100_ETH_MDC,
+		MFP101_ETH_MDIO,
+		MFP103_ETH_RXDV,
+
+		/* SSP2 */
+		MFP107_SSP2_RXD,
+		MFP108_SSP2_TXD,
+		MFP110_SSP2_CS,
+		MFP111_SSP2_CLK,
+
+		MFP_EOC		/*End of configuration*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+	return 0;
+}
+
+int board_init(void)
+{
+	struct armd1apb2_registers *apb2_regs =
+		(struct armd1apb2_registers *)ARMD1_APBC2_BASE;
+
+	/* arch number of Board */
+	gd->bd->bi_arch_number = MACH_TYPE_GPLUGD;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+	/* Assert PHY_RST# */
+	gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
+	udelay(10);
+	/* Deassert PHY_RST# */
+	gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
+
+	/* Enable SSP2 clock */
+	writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
+	return 0;
+}
+
+#ifdef CONFIG_ARMADA100_FEC
+int board_eth_init(struct bd_info *bis)
+{
+	struct armd1apmu_registers *apmu_regs =
+		(struct armd1apmu_registers *)ARMD1_APMU_BASE;
+
+	/* Enable clock of ethernet controller */
+	writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
+
+	return armada100_fec_register(ARMD1_FEC_BASE);
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY chip 88E3015 */
+void reset_phy(void)
+{
+	u16 phy_adr;
+	const char *name = "armd-fec0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xff, 0xff, &phy_adr)) {
+		printf("Err..%s could not read PHY dev address\n", __func__);
+		return;
+	}
+
+	/* Set Ethernet LED in TX blink mode */
+	miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
+	miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
+
+	/* reset the phy */
+	miiphy_reset(name, phy_adr);
+	debug("88E3015 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+#endif /* CONFIG_ARMADA100_FEC */
diff --git a/roms/u-boot/board/Marvell/guruplug/Kconfig b/roms/u-boot/board/Marvell/guruplug/Kconfig
new file mode 100644
index 000000000..529e6e3b4
--- /dev/null
+++ b/roms/u-boot/board/Marvell/guruplug/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GURUPLUG
+
+config SYS_BOARD
+	default "guruplug"
+
+config SYS_VENDOR
+	default "Marvell"
+
+config SYS_CONFIG_NAME
+	default "guruplug"
+
+endif
diff --git a/roms/u-boot/board/Marvell/guruplug/MAINTAINERS b/roms/u-boot/board/Marvell/guruplug/MAINTAINERS
new file mode 100644
index 000000000..b5d073483
--- /dev/null
+++ b/roms/u-boot/board/Marvell/guruplug/MAINTAINERS
@@ -0,0 +1,6 @@
+GURUPLUG BOARD
+M:	Siddarth Gore <gores@marvell.com>
+S:	Maintained
+F:	board/Marvell/guruplug/
+F:	include/configs/guruplug.h
+F:	configs/guruplug_defconfig
diff --git a/roms/u-boot/board/Marvell/guruplug/Makefile b/roms/u-boot/board/Marvell/guruplug/Makefile
new file mode 100644
index 000000000..b0dfc0cd6
--- /dev/null
+++ b/roms/u-boot/board/Marvell/guruplug/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+
+obj-y	:= guruplug.o
diff --git a/roms/u-boot/board/Marvell/guruplug/guruplug.c b/roms/u-boot/board/Marvell/guruplug/guruplug.c
new file mode 100644
index 000000000..8e7dbb3f3
--- /dev/null
+++ b/roms/u-boot/board/Marvell/guruplug/guruplug.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "guruplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
+			  GURUPLUG_OE_VAL_HIGH,
+			  GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,	/* GPIO_RST */
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GE1_8,
+		MPP29_GE1_9,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GE1_14,
+		MPP35_GE1_15,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_TDM_SPI_SCK,
+		MPP41_TDM_SPI_MISO,
+		MPP42_TDM_SPI_MOSI,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO, 	/* M_RLED */
+		MPP47_GPIO,	/* M_GLED */
+		MPP48_GPIO,	/* B_RLED */
+		MPP49_GPIO,	/* B_GLED */
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void mv_phy_88e1121_init(char *name)
+{
+	u16 reg;
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__FUNCTION__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, &reg);
+	reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
+	miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1121 Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+	/* configure and initialize both PHY's */
+	mv_phy_88e1121_init("egiga0");
+	mv_phy_88e1121_init("egiga1");
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/roms/u-boot/board/Marvell/guruplug/guruplug.h b/roms/u-boot/board/Marvell/guruplug/guruplug.h
new file mode 100644
index 000000000..a70236681
--- /dev/null
+++ b/roms/u-boot/board/Marvell/guruplug/guruplug.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ */
+
+#ifndef __GURUPLUG_H
+#define __GURUPLUG_H
+
+#define GURUPLUG_OE_LOW		(~(0))
+#define GURUPLUG_OE_HIGH	(~(0))
+#define GURUPLUG_OE_VAL_LOW	0
+#define GURUPLUG_OE_VAL_HIGH	(0xf << 16) /* 4 LED Pins high */
+
+/* PHY related */
+#define MV88E1121_MAC_CTRL2_REG		21
+#define MV88E1121_PGADR_REG		22
+#define MV88E1121_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1121_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __GURUPLUG_H */
diff --git a/roms/u-boot/board/Marvell/guruplug/kwbimage.cfg b/roms/u-boot/board/Marvell/guruplug/kwbimage.cfg
new file mode 100644
index 000000000..8a0d752c9
--- /dev/null
+++ b/roms/u-boot/board/Marvell/guruplug/kwbimage.cfg
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b9b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc	#  DDR Address Control
+# bit1-0:   01, Cs0width=x8
+# bit3-2:   10, Cs0size=1Gb
+# bit5-4:   01, Cs1width=x8
+# bit7-6:   10, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/Marvell/mvebu_armada-37xx/MAINTAINERS b/roms/u-boot/board/Marvell/mvebu_armada-37xx/MAINTAINERS
new file mode 100644
index 000000000..f2c0a582d
--- /dev/null
+++ b/roms/u-boot/board/Marvell/mvebu_armada-37xx/MAINTAINERS
@@ -0,0 +1,16 @@
+MVEBU_DB_88F3720 BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/Marvell/mvebu_armada-37xx/
+F:	include/configs/mvebu_armada-37xx.h
+F:	configs/mvebu_db-88f3720_defconfig
+
+ESPRESSOBin BOARD
+M:	Konstantin Porotchkin <kostap@marvell.com>
+S:	Maintained
+F:	configs/mvebu_espressobin-88f3720_defconfig
+
+uDPU BOARD
+M:	Vladimir Vid <vladimir.vid@sartura.hr>
+S:	Maintained
+F:	configs/uDPU_defconfig
diff --git a/roms/u-boot/board/Marvell/mvebu_armada-37xx/Makefile b/roms/u-boot/board/Marvell/mvebu_armada-37xx/Makefile
new file mode 100644
index 000000000..27221557c
--- /dev/null
+++ b/roms/u-boot/board/Marvell/mvebu_armada-37xx/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+
+obj-y	:= board.o
diff --git a/roms/u-boot/board/Marvell/mvebu_armada-37xx/board.c b/roms/u-boot/board/Marvell/mvebu_armada-37xx/board.c
new file mode 100644
index 000000000..c630437c0
--- /dev/null
+++ b/roms/u-boot/board/Marvell/mvebu_armada-37xx/board.c
@@ -0,0 +1,436 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <env.h>
+#include <env_internal.h>
+#include <i2c.h>
+#include <init.h>
+#include <mmc.h>
+#include <phy.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO expander I2C device */
+#define I2C_IO_EXP_ADDR		0x22
+#define I2C_IO_CFG_REG_0	0x6
+#define I2C_IO_DATA_OUT_REG_0	0x2
+#define I2C_IO_REG_0_SATA_OFF	2
+#define I2C_IO_REG_0_USB_H_OFF	1
+
+/* The pin control values are the same for DB and Espressobin */
+#define PINCTRL_NB_REG_VALUE	0x000173fa
+#define PINCTRL_SB_REG_VALUE	0x00007a23
+
+/* Ethernet switch registers */
+/* SMI addresses for multi-chip mode */
+#define MVEBU_PORT_CTRL_SMI_ADDR(p)	(16 + (p))
+#define MVEBU_SW_G2_SMI_ADDR		(28)
+
+/* Multi-chip mode */
+#define MVEBU_SW_SMI_DATA_REG		(1)
+#define MVEBU_SW_SMI_CMD_REG		(0)
+ #define SW_SMI_CMD_REG_ADDR_OFF	0
+ #define SW_SMI_CMD_DEV_ADDR_OFF	5
+ #define SW_SMI_CMD_SMI_OP_OFF		10
+ #define SW_SMI_CMD_SMI_MODE_OFF	12
+ #define SW_SMI_CMD_SMI_BUSY_OFF	15
+
+/* Single-chip mode */
+/* Switch Port Registers */
+#define MVEBU_SW_LINK_CTRL_REG		(1)
+#define MVEBU_SW_PORT_CTRL_REG		(4)
+#define MVEBU_SW_PORT_BASE_VLAN		(6)
+
+/* Global 2 Registers */
+#define MVEBU_G2_SMI_PHY_CMD_REG	(24)
+#define MVEBU_G2_SMI_PHY_DATA_REG	(25)
+
+/*
+ * Memory Controller Registers
+ *
+ * Assembled based on public information:
+ * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336
+ * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
+ *
+ * And checked against the written register values for the various topologies:
+ * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h
+ */
+#define A3700_CH0_MC_CTRL2_REG		MVEBU_REGISTER(0x002c4)
+#define A3700_MC_CTRL2_SDRAM_TYPE_MASK	0xf
+#define A3700_MC_CTRL2_SDRAM_TYPE_OFFS	4
+#define A3700_MC_CTRL2_SDRAM_TYPE_DDR3	2
+#define A3700_MC_CTRL2_SDRAM_TYPE_DDR4	3
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	char *ptr = (char *)&default_environment[0];
+	struct udevice *dev;
+	struct mmc *mmc_dev;
+	bool ddr4, emmc;
+	const char *mac;
+	char eth[10];
+	int i;
+
+	if (!of_machine_is_compatible("globalscale,espressobin"))
+		return 0;
+
+	/* Find free buffer in default_environment[] for new variables */
+	while (*ptr != '\0' && *(ptr+1) != '\0') ptr++;
+	ptr += 2;
+
+	/*
+	 * Ensure that 'env default -a' does not erase permanent MAC addresses
+	 * stored in env variables: $ethaddr, $eth1addr, $eth2addr and $eth3addr
+	 */
+
+	mac = env_get("ethaddr");
+	if (mac && strlen(mac) <= 17)
+		ptr += sprintf(ptr, "ethaddr=%s", mac) + 1;
+
+	for (i = 1; i <= 3; i++) {
+		sprintf(eth, "eth%daddr", i);
+		mac = env_get(eth);
+		if (mac && strlen(mac) <= 17)
+			ptr += sprintf(ptr, "%s=%s", eth, mac) + 1;
+	}
+
+	/* If the memory controller has been configured for DDR4, we're running on v7 */
+	ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
+		& A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
+
+	/* eMMC is mmc dev num 1 */
+	mmc_dev = find_mmc_device(1);
+	emmc = (mmc_dev && mmc_init(mmc_dev) == 0);
+
+	/* if eMMC is not present then remove it from DM */
+	if (!emmc && mmc_dev) {
+		dev = mmc_dev->dev;
+		device_remove(dev, DM_REMOVE_NORMAL);
+		device_unbind(dev);
+	}
+
+	if (env_get("fdtfile"))
+		return 0;
+
+	/* Ensure that 'env default -a' set correct value to $fdtfile */
+	if (ddr4 && emmc)
+		strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7-emmc.dtb");
+	else if (ddr4)
+		strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7.dtb");
+	else if (emmc)
+		strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-emmc.dtb");
+	else
+		strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin.dtb");
+
+	/* If $fdtfile was not set explicitly by user then set default value */
+	if (!env_get("fdtfile"))
+		env_set("fdtfile", ptr + sizeof("fdtfile="));
+
+	return 0;
+}
+#endif
+
+/* Board specific AHCI / SATA enable code */
+int board_ahci_enable(void)
+{
+	struct udevice *dev;
+	int ret;
+	u8 buf[8];
+
+	/* Only DB requres this configuration */
+	if (!of_machine_is_compatible("marvell,armada-3720-db"))
+		return 0;
+
+	/* Configure IO exander PCA9555: 7bit address 0x22 */
+	ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+	if (ret) {
+		printf("Cannot find PCA9555: %d\n", ret);
+		return 0;
+	}
+
+	ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to read IO expander value via I2C\n");
+		return -EIO;
+	}
+
+	/*
+	 * Enable SATA power via IO expander connected via I2C by setting
+	 * the corresponding bit to output mode to enable power for SATA
+	 */
+	buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
+	ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to set IO expander via I2C\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/* Board specific xHCI enable code */
+int board_xhci_enable(fdt_addr_t base)
+{
+	struct udevice *dev;
+	int ret;
+	u8 buf[8];
+
+	/* Only DB requres this configuration */
+	if (!of_machine_is_compatible("marvell,armada-3720-db"))
+		return 0;
+
+	/* Configure IO exander PCA9555: 7bit address 0x22 */
+	ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+	if (ret) {
+		printf("Cannot find PCA9555: %d\n", ret);
+		return 0;
+	}
+
+	printf("Enable USB VBUS\n");
+
+	/*
+	 * Read configuration (direction) and set VBUS pin as output
+	 * (reset pin = output)
+	 */
+	ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to read IO expander value via I2C\n");
+		return -EIO;
+	}
+	buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
+	ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to set IO expander via I2C\n");
+		return -EIO;
+	}
+
+	/* Read VBUS output value and disable it */
+	ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to read IO expander value via I2C\n");
+		return -EIO;
+	}
+	buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
+	ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to set IO expander via I2C\n");
+		return -EIO;
+	}
+
+	/*
+	 * Required delay for configuration to settle - must wait for
+	 * power on port is disabled in case VBUS signal was high,
+	 * required 3 seconds delay to let VBUS signal fully settle down
+	 */
+	mdelay(3000);
+
+	/* Enable VBUS power: Set output value of VBUS pin as enabled */
+	buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
+	ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to set IO expander via I2C\n");
+		return -EIO;
+	}
+
+	mdelay(500); /* required delay to let output value settle */
+
+	return 0;
+}
+
+/* Helper function for accessing switch devices in multi-chip connection mode */
+static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
+				     int smi_addr, int reg, u16 value)
+{
+	u16 smi_cmd = 0;
+
+	if (bus->write(bus, dev_smi_addr, 0,
+		       MVEBU_SW_SMI_DATA_REG, value) != 0) {
+		printf("Error writing to the PHY addr=%02x reg=%02x\n",
+		       smi_addr, reg);
+		return -EFAULT;
+	}
+
+	smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
+		  (1 << SW_SMI_CMD_SMI_MODE_OFF) |
+		  (1 << SW_SMI_CMD_SMI_OP_OFF) |
+		  (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
+		  (reg << SW_SMI_CMD_REG_ADDR_OFF);
+	if (bus->write(bus, dev_smi_addr, 0,
+		       MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
+		printf("Error writing to the PHY addr=%02x reg=%02x\n",
+		       smi_addr, reg);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/* Bring-up board-specific network stuff */
+int board_network_enable(struct mii_dev *bus)
+{
+	if (!of_machine_is_compatible("globalscale,espressobin"))
+		return 0;
+
+	/*
+	 * FIXME: remove this code once Topaz driver gets available
+	 * A3720 Community Board Only
+	 * Configure Topaz switch (88E6341)
+	 * Restrict output to ports 1,2,3 only from port 0 (CPU)
+	 * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
+	 */
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
+				  MVEBU_SW_PORT_BASE_VLAN, BIT(0));
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
+				  MVEBU_SW_PORT_BASE_VLAN, BIT(0));
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
+				  MVEBU_SW_PORT_BASE_VLAN, BIT(0));
+
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
+				  MVEBU_SW_PORT_CTRL_REG, 0x7f);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
+				  MVEBU_SW_PORT_CTRL_REG, 0x7f);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
+				  MVEBU_SW_PORT_CTRL_REG, 0x7f);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
+				  MVEBU_SW_PORT_CTRL_REG, 0x7f);
+
+	/* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
+				  MVEBU_SW_LINK_CTRL_REG, 0xe002);
+
+	/* Power up PHY 1, 2, 3 (through Global 2 registers) */
+	mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
+				  MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
+				  MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
+				  MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
+				  MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int ret;
+	int spi_off;
+	int parts_off;
+	int part_off;
+
+	/* Fill SPI MTD partitions for Linux kernel on Espressobin */
+	if (!of_machine_is_compatible("globalscale,espressobin"))
+		return 0;
+
+	spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
+	if (spi_off < 0)
+		return 0;
+
+	/* Do not touch partitions if they are already defined */
+	if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
+		return 0;
+
+	parts_off = fdt_add_subnode(blob, spi_off, "partitions");
+	if (parts_off < 0) {
+		printf("Can't add partitions node: %s\n", fdt_strerror(parts_off));
+		return 0;
+	}
+
+	ret = fdt_setprop_string(blob, parts_off, "compatible", "fixed-partitions");
+	if (ret < 0) {
+		printf("Can't set compatible property: %s\n", fdt_strerror(ret));
+		return 0;
+	}
+
+	ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
+	if (ret < 0) {
+		printf("Can't set #address-cells property: %s\n", fdt_strerror(ret));
+		return 0;
+	}
+
+	ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
+	if (ret < 0) {
+		printf("Can't set #size-cells property: %s\n", fdt_strerror(ret));
+		return 0;
+	}
+
+	/* Add u-boot-env partition */
+
+	part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-env");
+	if (part_off < 0) {
+		printf("Can't add partition@u-boot-env node: %s\n", fdt_strerror(part_off));
+		return 0;
+	}
+
+	ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
+	if (ret < 0) {
+		printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
+		return 0;
+	}
+
+	ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_SIZE);
+	if (ret < 0) {
+		printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
+		return 0;
+	}
+
+	ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
+	if (ret < 0) {
+		printf("Can't set partition@u-boot-env label property: %s\n", fdt_strerror(ret));
+		return 0;
+	}
+
+	/* Add firmware partition */
+
+	part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
+	if (part_off < 0) {
+		printf("Can't add partition@firmware node: %s\n", fdt_strerror(part_off));
+		return 0;
+	}
+
+	ret = fdt_setprop_u32(blob, part_off, "reg", 0);
+	if (ret < 0) {
+		printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
+		return 0;
+	}
+
+	ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
+	if (ret < 0) {
+		printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
+		return 0;
+	}
+
+	ret = fdt_setprop_string(blob, part_off, "label", "firmware");
+	if (ret < 0) {
+		printf("Can't set partition@firmware label property: %s\n", fdt_strerror(ret));
+		return 0;
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/Marvell/mvebu_armada-8k/MAINTAINERS b/roms/u-boot/board/Marvell/mvebu_armada-8k/MAINTAINERS
new file mode 100644
index 000000000..55e485faa
--- /dev/null
+++ b/roms/u-boot/board/Marvell/mvebu_armada-8k/MAINTAINERS
@@ -0,0 +1,19 @@
+MVEBU_ARMADA_8K BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/Marvell/mvebu_armada-8k/
+F:	include/configs/mvebu_armada-8k.h
+F:	configs/mvebu_db_armada8k_defconfig
+
+
+MACCHIATOBin BOARD
+M:	Konstantin Porotchkin <kostap@marvell.com>
+S:	Maintained
+F:	configs/mvebu_mcbin-88f8040_defconfig
+
+Puzzle-M801 BOARD
+M:	Luka Kovacic <luka.kovacic@sartura.hr>
+M:	Luka Perkov <luka.perkov@sartura.hr>
+S:	Maintained
+F:	configs/mvebu_puzzle-m801-88f8040_defconfig
+F:	arch/arm/dts/armada-8040-puzzle-m801.dts
diff --git a/roms/u-boot/board/Marvell/mvebu_armada-8k/Makefile b/roms/u-boot/board/Marvell/mvebu_armada-8k/Makefile
new file mode 100644
index 000000000..27221557c
--- /dev/null
+++ b/roms/u-boot/board/Marvell/mvebu_armada-8k/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+
+obj-y	:= board.o
diff --git a/roms/u-boot/board/Marvell/mvebu_armada-8k/board.c b/roms/u-boot/board/Marvell/mvebu_armada-8k/board.c
new file mode 100644
index 000000000..7da5d9f96
--- /dev/null
+++ b/roms/u-boot/board/Marvell/mvebu_armada-8k/board.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Information specific to the DB-88F7040 eval board. We strive to use
+ * DT for such platform specfic configurations. At some point, this
+ * might be removed here and implemented via DT.
+ */
+/* IO expander I2C device */
+#define I2C_IO_EXP_ADDR		0x21
+#define I2C_IO_CFG_REG_0	0x6
+#define I2C_IO_DATA_OUT_REG_0	0x2
+/* VBus enable */
+#define I2C_IO_REG_0_USB_H0_OFF	0
+#define I2C_IO_REG_0_USB_H1_OFF	1
+#define I2C_IO_REG_VBUS		((1 << I2C_IO_REG_0_USB_H0_OFF) | \
+				 (1 << I2C_IO_REG_0_USB_H1_OFF))
+/* Current limit */
+#define I2C_IO_REG_0_USB_H0_CL	4
+#define I2C_IO_REG_0_USB_H1_CL	5
+#define I2C_IO_REG_CL		((1 << I2C_IO_REG_0_USB_H0_CL) | \
+				 (1 << I2C_IO_REG_0_USB_H1_CL))
+
+/*
+ * Information specific to the iEi Puzzle-M801 board.
+ */
+
+/* Internal configuration registers */
+#define CP1_CONF_REG_BASE 0xf4440000
+#define CONF_REG_MPP0 0x0
+#define CONF_REG_MPP1 0x4
+#define CONF_REG_MPP2 0x8
+#define CONF_REG_MPP3 0xC
+
+static int usb_enabled = 0;
+
+/* Board specific xHCI dis-/enable code */
+
+/*
+ * Set USB VBUS signals (via I2C IO expander/GPIO) as output and set
+ * output value as disabled
+ *
+ * Set USB Current Limit signals (via I2C IO expander/GPIO) as output
+ * and set output value as enabled
+ */
+int board_xhci_config(void)
+{
+	struct udevice *dev;
+	int ret;
+	u8 buf[8];
+
+	if (of_machine_is_compatible("marvell,armada7040-db")) {
+		/* Configure IO exander PCA9555: 7bit address 0x21 */
+		ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+		if (ret) {
+			printf("Cannot find PCA9555: %d\n", ret);
+			return 0;
+		}
+
+		/*
+		 * Read configuration (direction) and set VBUS pin as output
+		 * (reset pin = output)
+		 */
+		ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
+		if (ret) {
+			printf("Failed to read IO expander value via I2C\n");
+			return -EIO;
+		}
+		buf[0] &= ~I2C_IO_REG_VBUS;
+		buf[0] &= ~I2C_IO_REG_CL;
+		ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
+		if (ret) {
+			printf("Failed to set IO expander via I2C\n");
+			return -EIO;
+		}
+
+		/* Read output value and configure it */
+		ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+		if (ret) {
+			printf("Failed to read IO expander value via I2C\n");
+			return -EIO;
+		}
+		buf[0] &= ~I2C_IO_REG_VBUS;
+		buf[0] |= I2C_IO_REG_CL;
+		ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+		if (ret) {
+			printf("Failed to set IO expander via I2C\n");
+			return -EIO;
+		}
+
+		mdelay(500); /* required delay to let output value settle */
+	}
+
+	return 0;
+}
+
+int board_xhci_enable(fdt_addr_t base)
+{
+	struct udevice *dev;
+	int ret;
+	u8 buf[8];
+
+	if (of_machine_is_compatible("marvell,armada7040-db")) {
+		/*
+		 * This function enables all USB ports simultaniously,
+		 * it only needs to get called once
+		 */
+		if (usb_enabled)
+			return 0;
+
+		/* Configure IO exander PCA9555: 7bit address 0x21 */
+		ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+		if (ret) {
+			printf("Cannot find PCA9555: %d\n", ret);
+			return 0;
+		}
+
+		/* Read VBUS output value */
+		ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+		if (ret) {
+			printf("Failed to read IO expander value via I2C\n");
+			return -EIO;
+		}
+
+		/* Enable VBUS power: Set output value of VBUS pin as enabled */
+		buf[0] |= I2C_IO_REG_VBUS;
+		ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+		if (ret) {
+			printf("Failed to set IO expander via I2C\n");
+			return -EIO;
+		}
+
+		mdelay(500); /* required delay to let output value settle */
+		usb_enabled = 1;
+	}
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	/* Initialize some platform specific memory locations */
+	if (of_machine_is_compatible("marvell,armada8040-puzzle-m801")) {
+		/* MPP setup */
+		writel(0x00444444, CP1_CONF_REG_BASE + CONF_REG_MPP0);
+		writel(0x00000000, CP1_CONF_REG_BASE + CONF_REG_MPP1);
+		writel(0x00000000, CP1_CONF_REG_BASE + CONF_REG_MPP2);
+		writel(0x08888000, CP1_CONF_REG_BASE + CONF_REG_MPP3);
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	/* Pre-configure the USB ports (overcurrent, VBus) */
+	board_xhci_config();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/Marvell/octeon_ebb7304/Kconfig b/roms/u-boot/board/Marvell/octeon_ebb7304/Kconfig
new file mode 100644
index 000000000..ab54e6dbb
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeon_ebb7304/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_OCTEON_EBB7304
+
+config SYS_BOARD
+	string
+	default "octeon_ebb7304"
+
+config SYS_VENDOR
+	string
+	default "Marvell"
+
+config SYS_CONFIG_NAME
+	string
+	default "octeon_ebb7304"
+
+config DEFAULT_DEVICE_TREE
+	string
+	default "mrvl,octeon-ebb7304"
+
+endif
diff --git a/roms/u-boot/board/Marvell/octeon_ebb7304/MAINTAINERS b/roms/u-boot/board/Marvell/octeon_ebb7304/MAINTAINERS
new file mode 100644
index 000000000..7256f8356
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeon_ebb7304/MAINTAINERS
@@ -0,0 +1,7 @@
+OCTEON_EBB7304 BOARD
+M:	Aaron Williams <awilliams@marvell.com>
+S:	Maintained
+F:	board/Marvell/octeon_ebb7304/*
+F:	configs/octeon_ebb7304_defconfig
+F:	include/configs/octeon_ebb7304.h
+F:	arch/mips/dts/mrvl,octeon-ebb7304.dts
diff --git a/roms/u-boot/board/Marvell/octeon_ebb7304/Makefile b/roms/u-boot/board/Marvell/octeon_ebb7304/Makefile
new file mode 100644
index 000000000..a3ed0c887
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeon_ebb7304/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2020 Stefan Roese <sr@denx.de>
+# Copyright (C) 2019-2020 Marvell International Ltd.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= board.o
diff --git a/roms/u-boot/board/Marvell/octeon_ebb7304/board.c b/roms/u-boot/board/Marvell/octeon_ebb7304/board.c
new file mode 100644
index 000000000..9aac5f0b0
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeon_ebb7304/board.c
@@ -0,0 +1,754 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <dm.h>
+#include <fdt_support.h>
+#include <ram.h>
+#include <asm/gpio.h>
+
+#include <mach/octeon_ddr.h>
+#include <mach/cvmx-qlm.h>
+#include <mach/octeon_qlm.h>
+#include <mach/octeon_fdt.h>
+#include <mach/cvmx-helper.h>
+#include <mach/cvmx-helper-cfg.h>
+#include <mach/cvmx-helper-util.h>
+#include <mach/cvmx-bgxx-defs.h>
+
+#include "board_ddr.h"
+
+#define MAX_MIX_ENV_VARS	4
+
+#define EBB7304_DEF_DRAM_FREQ	800
+
+static struct ddr_conf board_ddr_conf[] = {
+	OCTEON_EBB7304_DDR_CONFIGURATION
+};
+
+static int no_phy[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+
+struct ddr_conf *octeon_ddr_conf_table_get(int *count, int *def_ddr_freq)
+{
+	*count = ARRAY_SIZE(board_ddr_conf);
+	*def_ddr_freq = EBB7304_DEF_DRAM_FREQ;
+
+	return board_ddr_conf;
+}
+
+/*
+ * parse_env_var:	Parse the environment variable ("bgx_for_mix%d") to
+ *			extract the lmac it is set to.
+ *
+ *  index:		Index of environment variable to parse.
+ *			environment variable.
+ *  env_bgx:		Updated with the bgx of the lmac in the environment
+ *			variable.
+ *  env_lmac:		Updated with the index of lmac in the environment
+ *			variable.
+ *
+ *  returns:		Zero on success, error otherwise.
+ */
+static int parse_env_var(int index, int *env_bgx, int *env_lmac)
+{
+	char env_var[20];
+	ulong xipd_port;
+
+	sprintf(env_var, "bgx_for_mix%d", index);
+	xipd_port = env_get_ulong(env_var, 0, 0xffff);
+	if (xipd_port != 0xffff) {
+		int xiface;
+		struct cvmx_xiface xi;
+		struct cvmx_xport xp;
+
+		/*
+		 * The environemt variable is set to the xipd port. Convert the
+		 * xipd port to numa node, bgx, and lmac.
+		 */
+		xiface = cvmx_helper_get_interface_num(xipd_port);
+		xi = cvmx_helper_xiface_to_node_interface(xiface);
+		xp = cvmx_helper_ipd_port_to_xport(xipd_port);
+		*env_bgx = xi.interface;
+		*env_lmac = cvmx_helper_get_interface_index_num(xp.port);
+		return 0;
+	}
+
+	return -1;
+}
+
+/*
+ * get_lmac_fdt_node:	Search the device tree for the node corresponding to
+ *			a given bgx lmac.
+ *
+ *  fdt:		Pointer to flat device tree
+ *  search_node:	Numa node of the lmac to search for.
+ *  search_bgx:		Bgx of the lmac to search for.
+ *  search_lmac:	Lmac index to search for.
+ *  compat:		Compatible string to search for.
+
+ *  returns:		The device tree node of the lmac if found,
+ *			or -1 otherwise.
+ */
+static int get_lmac_fdt_node(const void *fdt, int search_node, int search_bgx, int search_lmac,
+			     const char *compat)
+{
+	int node;
+	const fdt32_t *reg;
+	u64 addr;
+	int fdt_node = -1;
+	int fdt_bgx = -1;
+	int fdt_lmac = -1;
+	int len;
+	int parent;
+
+	/* Iterate through all bgx ports */
+	node = -1;
+	while ((node = fdt_node_offset_by_compatible((void *)fdt, node,
+						     compat)) >= 0) {
+		/* Get the node and bgx from the physical address */
+		parent = fdt_parent_offset(fdt, node);
+		reg = fdt_getprop(fdt, parent, "reg", &len);
+		if (parent < 0 || !reg)
+			continue;
+
+		addr = fdt_translate_address((void *)fdt, parent, reg);
+		fdt_node = (addr >> 36) & 0x7;
+		fdt_bgx = (addr >> 24) & 0xf;
+
+		/* Get the lmac index from the reg property */
+		reg = fdt_getprop(fdt, node, "reg", &len);
+		if (reg)
+			fdt_lmac = *reg;
+
+		/* Check for a match */
+		if (search_node == fdt_node && search_bgx == fdt_bgx &&
+		    search_lmac == fdt_lmac)
+			return node;
+	}
+
+	return -1;
+}
+
+/*
+ * get_mix_fdt_node:	Search the device tree for the node corresponding to
+ *			a given mix.
+ *
+ *  fdt:		Pointer to flat device tree
+ *  search_node:	Mix numa node to search for.
+ *  search_index:	Mix index to search for.
+ *
+ *  returns:		The device tree node of the lmac if found,
+ *			or -1 otherwise.
+ */
+static int get_mix_fdt_node(const void *fdt, int search_node, int search_index)
+{
+	int node;
+
+	/* Iterate through all the mix fdt nodes */
+	node = -1;
+	while ((node = fdt_node_offset_by_compatible((void *)fdt, node,
+						     "cavium,octeon-7890-mix")) >= 0) {
+		int parent;
+		int len;
+		const char *name;
+		int mix_numa_node;
+		const fdt32_t *reg;
+		int mix_index = -1;
+		u64 addr;
+
+		/* Get the numa node of the mix from the parent node name */
+		parent = fdt_parent_offset(fdt, node);
+		if (parent < 0 ||
+		    ((name = fdt_get_name(fdt, parent, &len)) == NULL) ||
+		    ((name = strchr(name, '@')) == NULL))
+			continue;
+
+		name++;
+		mix_numa_node = simple_strtol(name, NULL, 0) ? 1 : 0;
+
+		/* Get the mix index from the reg property */
+		reg = fdt_getprop(fdt, node, "reg", &len);
+		if (reg) {
+			addr = fdt_translate_address((void *)fdt, parent, reg);
+			mix_index = (addr >> 11) & 1;
+		}
+
+		/* Check for a match */
+		if (mix_numa_node == search_node && mix_index == search_index)
+			return node;
+	}
+
+	return -1;
+}
+
+/*
+ * fdt_fix_mix:		Fix the mix nodes in the device tree. Only the mix nodes
+ *			configured by the user will be preserved. All other mix
+ *			nodes will be trimmed.
+ *
+ *  fdt:		Pointer to flat device tree
+ *
+ *  returns:		Zero on success, error otherwise.
+ */
+static int fdt_fix_mix(const void *fdt)
+{
+	int node;
+	int next_node;
+	int len;
+	int i;
+
+	/* Parse all the mix port environment variables */
+	for (i = 0; i < MAX_MIX_ENV_VARS; i++) {
+		int env_node = 0;
+		int env_bgx = -1;
+		int env_lmac = -1;
+		int lmac_fdt_node = -1;
+		int mix_fdt_node = -1;
+		int lmac_phandle;
+		char *compat;
+
+		/* Get the lmac for this environment variable */
+		if (parse_env_var(i, &env_bgx, &env_lmac))
+			continue;
+
+		/* Get the fdt node for this lmac and add a phandle to it */
+		compat = "cavium,octeon-7890-bgx-port";
+		lmac_fdt_node = get_lmac_fdt_node(fdt, env_node, env_bgx,
+						  env_lmac, compat);
+		if (lmac_fdt_node < 0) {
+			/* Must check for the xcv compatible string too */
+			compat = "cavium,octeon-7360-xcv";
+			lmac_fdt_node = get_lmac_fdt_node(fdt, env_node,
+							  env_bgx, env_lmac,
+							  compat);
+			if (lmac_fdt_node < 0) {
+				printf("WARNING: Failed to get lmac fdt node for %d%d%d\n",
+				       env_node, env_bgx, env_lmac);
+				continue;
+			}
+		}
+
+		lmac_phandle = fdt_alloc_phandle((void *)fdt);
+		fdt_set_phandle((void *)fdt, lmac_fdt_node, lmac_phandle);
+
+		/* Get the fdt mix node corresponding to this lmac */
+		mix_fdt_node = get_mix_fdt_node(fdt, env_node, env_lmac);
+		if (mix_fdt_node < 0)
+			continue;
+
+		/* Point the mix to the lmac */
+		fdt_getprop(fdt, mix_fdt_node, "cavium,mac-handle", &len);
+		fdt_setprop_inplace((void *)fdt, mix_fdt_node,
+				    "cavium,mac-handle", &lmac_phandle, len);
+	}
+
+	/* Trim unused mix'es from the device tree */
+	for (node = fdt_next_node(fdt, -1, NULL); node >= 0; node = next_node) {
+		const char *compat;
+		const fdt32_t *reg;
+
+		next_node = fdt_next_node(fdt, node, NULL);
+
+		compat = fdt_getprop(fdt, node, "compatible", &len);
+		if (compat) {
+			if (strcmp(compat, "cavium,octeon-7890-mix"))
+				continue;
+
+			reg = fdt_getprop(fdt, node, "cavium,mac-handle", &len);
+			if (reg) {
+				if (*reg == 0xffff)
+					fdt_nop_node((void *)fdt, node);
+			}
+		}
+	}
+
+	return 0;
+}
+
+static void kill_fdt_phy(void *fdt, int offset, void *arg)
+{
+	int len, phy_offset;
+	const fdt32_t *php;
+	u32 phandle;
+
+	php = fdt_getprop(fdt, offset, "phy-handle", &len);
+	if (php && len == sizeof(*php)) {
+		phandle = fdt32_to_cpu(*php);
+		fdt_nop_property(fdt, offset, "phy-handle");
+		phy_offset = fdt_node_offset_by_phandle(fdt, phandle);
+		if (phy_offset > 0)
+			fdt_nop_node(fdt, phy_offset);
+	}
+}
+
+void __fixup_xcv(void)
+{
+	unsigned long bgx = env_get_ulong("bgx_for_rgmii", 10,
+					  (unsigned long)-1);
+	char fdt_key[16];
+	int i;
+
+	debug("%s: BGX %d\n", __func__, (int)bgx);
+
+	for (i = 0; i < 3; i++) {
+		snprintf(fdt_key, sizeof(fdt_key),
+			 bgx == i ? "%d,xcv" : "%d,not-xcv", i);
+		debug("%s: trimming bgx %lu with key %s\n",
+		      __func__, bgx, fdt_key);
+
+		octeon_fdt_patch_rename((void *)gd->fdt_blob, fdt_key,
+					"cavium,xcv-trim", true, NULL, NULL);
+	}
+}
+
+/* QLM0 - QLM6 */
+void __fixup_fdt(void)
+{
+	int qlm;
+	int speed = 0;
+
+	for (qlm = 0; qlm < 7; qlm++) {
+		enum cvmx_qlm_mode mode;
+		char fdt_key[16];
+		const char *type_str = "none";
+
+		mode = cvmx_qlm_get_mode(qlm);
+		switch (mode) {
+		case CVMX_QLM_MODE_SGMII:
+		case CVMX_QLM_MODE_RGMII_SGMII:
+		case CVMX_QLM_MODE_RGMII_SGMII_1X1:
+			type_str = "sgmii";
+			break;
+		case CVMX_QLM_MODE_XAUI:
+		case CVMX_QLM_MODE_RGMII_XAUI:
+			speed = (cvmx_qlm_get_gbaud_mhz(qlm) * 8 / 10) * 4;
+			if (speed == 10000)
+				type_str = "xaui";
+			else
+				type_str = "dxaui";
+			break;
+		case CVMX_QLM_MODE_RXAUI:
+		case CVMX_QLM_MODE_RGMII_RXAUI:
+			type_str = "rxaui";
+			break;
+		case CVMX_QLM_MODE_XLAUI:
+		case CVMX_QLM_MODE_RGMII_XLAUI:
+			type_str = "xlaui";
+			break;
+		case CVMX_QLM_MODE_XFI:
+		case CVMX_QLM_MODE_RGMII_XFI:
+		case CVMX_QLM_MODE_RGMII_XFI_1X1:
+			type_str = "xfi";
+			break;
+		case CVMX_QLM_MODE_10G_KR:
+		case CVMX_QLM_MODE_RGMII_10G_KR:
+			type_str = "10G_KR";
+			break;
+		case CVMX_QLM_MODE_40G_KR4:
+		case CVMX_QLM_MODE_RGMII_40G_KR4:
+			type_str = "40G_KR4";
+			break;
+		case CVMX_QLM_MODE_SATA_2X1:
+			type_str = "sata";
+			break;
+		case CVMX_QLM_MODE_SGMII_2X1:
+		case CVMX_QLM_MODE_XFI_1X2:
+		case CVMX_QLM_MODE_10G_KR_1X2:
+		case CVMX_QLM_MODE_RXAUI_1X2:
+		case CVMX_QLM_MODE_MIXED: // special for DLM5 & DLM6
+		{
+			cvmx_bgxx_cmrx_config_t cmr_config;
+			cvmx_bgxx_spux_br_pmd_control_t pmd_control;
+			int mux = cvmx_qlm_mux_interface(2);
+
+			if (mux == 2) { // only dlm6
+				cmr_config.u64 = csr_rd(CVMX_BGXX_CMRX_CONFIG(2, 2));
+				pmd_control.u64 =
+					csr_rd(CVMX_BGXX_SPUX_BR_PMD_CONTROL(2, 2));
+			} else {
+				if (qlm == 5) {
+					cmr_config.u64 =
+						csr_rd(CVMX_BGXX_CMRX_CONFIG(0, 2));
+					pmd_control.u64 =
+						csr_rd(CVMX_BGXX_SPUX_BR_PMD_CONTROL(0, 2));
+				} else {
+					cmr_config.u64 =
+						csr_rd(CVMX_BGXX_CMRX_CONFIG(2, 2));
+					pmd_control.u64 =
+						csr_rd(CVMX_BGXX_SPUX_BR_PMD_CONTROL(2, 2));
+				}
+			}
+			switch (cmr_config.s.lmac_type) {
+			case 0:
+				type_str = "sgmii";
+				break;
+			case 1:
+				type_str = "xaui";
+				break;
+			case 2:
+				type_str = "rxaui";
+				break;
+			case 3:
+				if (pmd_control.s.train_en)
+					type_str = "10G_KR";
+				else
+					type_str = "xfi";
+				break;
+			case 4:
+				if (pmd_control.s.train_en)
+					type_str = "40G_KR4";
+				else
+					type_str = "xlaui";
+				break;
+			default:
+				type_str = "none";
+				break;
+			}
+			break;
+		}
+		default:
+			type_str = "none";
+			break;
+		}
+		sprintf(fdt_key, "%d,%s", qlm, type_str);
+		debug("Patching qlm %d for %s for mode %d%s\n", qlm, fdt_key, mode,
+		      no_phy[qlm] ? ", removing PHY" : "");
+		octeon_fdt_patch_rename((void *)gd->fdt_blob, fdt_key, NULL, true,
+					no_phy[qlm] ? kill_fdt_phy : NULL, NULL);
+	}
+}
+
+int board_fix_fdt(void)
+{
+	__fixup_fdt();
+	__fixup_xcv();
+
+	/* Fix the mix ports */
+	fdt_fix_mix(gd->fdt_blob);
+
+	return 0;
+}
+
+/*
+ * Here is the description of the parameters that are passed to QLM
+ * configuration:
+ *
+ *	param0 : The QLM to configure
+ *	param1 : Speed to configure the QLM at
+ *	param2 : Mode the QLM to configure
+ *	param3 : 1 = RC, 0 = EP
+ *	param4 : 0 = GEN1, 1 = GEN2, 2 = GEN3
+ *	param5 : ref clock select, 0 = 100Mhz, 1 = 125MHz, 2 = 156MHz
+ *	param6 : ref clock input to use:
+ *		 0 - external reference (QLMx_REF_CLK)
+ *		 1 = common clock 0 (QLMC_REF_CLK0)
+ *		 2 = common_clock 1 (QLMC_REF_CLK1)
+ */
+static void board_configure_qlms(void)
+{
+	int speed[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+	int mode[8] = { -1, -1, -1, -1, -1, -1, -1, -1 };
+	int pcie_rc[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+	int pcie_gen[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+	int ref_clock_sel[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+	int ref_clock_input[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+	struct gpio_desc desc;
+	int rbgx, rqlm;
+	char env_var[16];
+	int qlm;
+	int ret;
+
+	/* RGMII PHY reset GPIO */
+	ret = dm_gpio_lookup_name("gpio-controllerA27", &desc);
+	if (ret)
+		debug("gpio ret=%d\n", ret);
+	ret = dm_gpio_request(&desc, "rgmii_phy_reset");
+	if (ret)
+		debug("gpio_request ret=%d\n", ret);
+	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	if (ret)
+		debug("gpio dir ret=%d\n", ret);
+
+	/* Put RGMII PHY in reset */
+	dm_gpio_set_value(&desc, 0);
+
+	octeon_init_qlm(0);
+
+	rbgx = env_get_ulong("bgx_for_rgmii", 10, (unsigned long)-1);
+	switch (rbgx) {
+	case 0:
+		rqlm = 2;
+		break;
+	case 1:
+		rqlm = 3;
+		break;
+	case 2:
+		rqlm = 5;
+		break;
+	default:
+		rqlm = -1;
+		break;
+	}
+
+	for (qlm = 0; qlm < 7; qlm++) {
+		const char *mode_str;
+		char spd_env[16];
+
+		mode[qlm] = CVMX_QLM_MODE_DISABLED;
+		sprintf(env_var, "qlm%d_mode", qlm);
+		mode_str = env_get(env_var);
+		if (!mode_str)
+			continue;
+
+		if (qlm == 4 && mode[4] != -1 &&
+		    mode[4] != CVMX_QLM_MODE_SATA_2X1) {
+			printf("Error: DLM 4 can only be configured for SATA\n");
+			continue;
+		}
+
+		if (strstr(mode_str, ",no_phy"))
+			no_phy[qlm] = 1;
+
+		if (!strncmp(mode_str, "sgmii", 5)) {
+			bool rgmii = false;
+
+			speed[qlm] = 1250;
+			if (rqlm == qlm && qlm < 5) {
+				mode[qlm] = CVMX_QLM_MODE_RGMII_SGMII;
+				rgmii = true;
+			} else if (qlm == 6 || qlm == 5) {
+				if (rqlm == qlm && qlm == 5) {
+					mode[qlm] = CVMX_QLM_MODE_RGMII_SGMII_1X1;
+					rgmii = true;
+				} else if (rqlm == 5 && qlm == 6 &&
+					   mode[5] != CVMX_QLM_MODE_RGMII_SGMII_1X1) {
+					mode[qlm] = CVMX_QLM_MODE_RGMII_SGMII_2X1;
+					rgmii = true;
+				} else {
+					mode[qlm] = CVMX_QLM_MODE_SGMII_2X1;
+				}
+			} else {
+				mode[qlm] = CVMX_QLM_MODE_SGMII;
+			}
+			ref_clock_sel[qlm] = 2;
+
+			if (qlm == 5 || qlm == 6)
+				ref_clock_input[qlm] = 2; // use QLMC_REF_CLK1
+
+			if (no_phy[qlm]) {
+				int i;
+				int start = 0, stop = 2;
+
+				rbgx = 0;
+				switch (qlm) {
+				case 3:
+					rbgx = 1;
+				case 2:
+					for (i = 0; i < 4; i++) {
+						printf("Ignoring PHY for interface: %d, port: %d\n",
+						       rbgx, i);
+						cvmx_helper_set_port_force_link_up(rbgx, i, true);
+					}
+					break;
+				case 6:
+					start = 2;
+					stop = 4;
+				case 5:
+					for (i = start; i < stop; i++) {
+						printf("Ignoring PHY for interface: %d, port: %d\n",
+						       2, i);
+						cvmx_helper_set_port_force_link_up(2, i, true);
+					}
+					break;
+				default:
+					printf("SGMII not supported for QLM/DLM %d\n",
+					       qlm);
+					break;
+				}
+			}
+			printf("QLM %d: SGMII%s\n",
+			       qlm, rgmii ? ", RGMII" : "");
+		} else if (!strncmp(mode_str, "xaui", 4)) {
+			speed[qlm] = 3125;
+			mode[qlm] = CVMX_QLM_MODE_XAUI;
+			ref_clock_sel[qlm] = 2;
+			if (qlm == 5 || qlm == 6)
+				ref_clock_input[qlm] = 2; // use QLMC_REF_CLK1
+			printf("QLM %d: XAUI\n", qlm);
+		} else if (!strncmp(mode_str, "dxaui", 5)) {
+			speed[qlm] = 6250;
+			mode[qlm] = CVMX_QLM_MODE_XAUI;
+			ref_clock_sel[qlm] = 2;
+			if (qlm == 5 || qlm == 6)
+				ref_clock_input[qlm] = 2; // use QLMC_REF_CLK1
+			printf("QLM %d: DXAUI\n", qlm);
+		} else if (!strncmp(mode_str, "rxaui", 5)) {
+			bool rgmii = false;
+
+			speed[qlm] = 6250;
+			if (qlm == 5 || qlm == 6) {
+				if (rqlm == qlm && qlm == 5) {
+					mode[qlm] = CVMX_QLM_MODE_RGMII_RXAUI;
+					rgmii = true;
+				} else {
+					mode[qlm] = CVMX_QLM_MODE_RXAUI_1X2;
+				}
+			} else {
+				mode[qlm] = CVMX_QLM_MODE_RXAUI;
+			}
+			ref_clock_sel[qlm] = 2;
+			if (qlm == 5 || qlm == 6)
+				ref_clock_input[qlm] = 2; // use QLMC_REF_CLK1
+			printf("QLM %d: RXAUI%s\n",
+			       qlm, rgmii ? ", rgmii" : "");
+		} else if (!strncmp(mode_str, "xlaui", 5)) {
+			speed[qlm] = 103125;
+			mode[qlm] = CVMX_QLM_MODE_XLAUI;
+			ref_clock_sel[qlm] = 2;
+			if (qlm == 5 || qlm == 6)
+				ref_clock_input[qlm] = 2; // use QLMC_REF_CLK1
+			sprintf(spd_env, "qlm%d_speed", qlm);
+			if (env_get(spd_env)) {
+				int spd = env_get_ulong(spd_env, 0, 8);
+
+				if (spd)
+					speed[qlm] = spd;
+				else
+					speed[qlm] = 103125;
+			}
+			printf("QLM %d: XLAUI\n", qlm);
+		} else if (!strncmp(mode_str, "xfi", 3)) {
+			bool rgmii = false;
+
+			speed[qlm] = 103125;
+			if (rqlm == qlm) {
+				mode[qlm] = CVMX_QLM_MODE_RGMII_XFI;
+				rgmii = true;
+			} else if (qlm == 5 || qlm == 6) {
+				mode[qlm] = CVMX_QLM_MODE_XFI_1X2;
+			} else {
+				mode[qlm] = CVMX_QLM_MODE_XFI;
+			}
+			ref_clock_sel[qlm] = 2;
+			if (qlm == 5 || qlm == 6)
+				ref_clock_input[qlm] = 2; // use QLMC_REF_CLK1
+			printf("QLM %d: XFI%s\n", qlm, rgmii ? ", RGMII" : "");
+		} else if (!strncmp(mode_str, "10G_KR", 6)) {
+			speed[qlm] = 103125;
+			if (rqlm == qlm && qlm == 5)
+				mode[qlm] = CVMX_QLM_MODE_RGMII_10G_KR;
+			else if (qlm == 5 || qlm == 6)
+				mode[qlm] = CVMX_QLM_MODE_10G_KR_1X2;
+			else
+				mode[qlm] = CVMX_QLM_MODE_10G_KR;
+			ref_clock_sel[qlm] = 2;
+			if (qlm == 5 || qlm == 6)
+				ref_clock_input[qlm] = 2; // use QLMC_REF_CLK1
+			printf("QLM %d: 10G_KR\n", qlm);
+		} else if (!strncmp(mode_str, "40G_KR4", 7)) {
+			speed[qlm] = 103125;
+			mode[qlm] = CVMX_QLM_MODE_40G_KR4;
+			ref_clock_sel[qlm] = 2;
+			if (qlm == 5 || qlm == 6)
+				ref_clock_input[qlm] = 2; // use QLMC_REF_CLK1
+			printf("QLM %d: 40G_KR4\n", qlm);
+		} else if (!strcmp(mode_str, "pcie")) {
+			char *pmode;
+			int lanes = 0;
+
+			sprintf(env_var, "pcie%d_mode", qlm);
+			pmode = env_get(env_var);
+			if (pmode && !strcmp(pmode, "ep"))
+				pcie_rc[qlm] = 0;
+			else
+				pcie_rc[qlm] = 1;
+			sprintf(env_var, "pcie%d_gen", qlm);
+			pcie_gen[qlm] = env_get_ulong(env_var, 0, 3);
+			sprintf(env_var, "pcie%d_lanes", qlm);
+			lanes = env_get_ulong(env_var, 0, 8);
+			if (lanes == 8) {
+				mode[qlm] = CVMX_QLM_MODE_PCIE_1X8;
+			} else if (qlm == 5 || qlm == 6) {
+				if (lanes != 2) {
+					printf("QLM%d: Invalid lanes selected, defaulting to 2 lanes\n",
+					       qlm);
+				}
+				mode[qlm] = CVMX_QLM_MODE_PCIE_1X2;
+				ref_clock_input[qlm] = 1; // use QLMC_REF_CLK0
+			} else {
+				mode[qlm] = CVMX_QLM_MODE_PCIE;
+			}
+			ref_clock_sel[qlm] = 0;
+			printf("QLM %d: PCIe gen%d %s, x%d lanes\n",
+			       qlm, pcie_gen[qlm] + 1,
+			       pcie_rc[qlm] ? "root complex" : "endpoint",
+			       lanes);
+		} else if (!strcmp(mode_str, "sata")) {
+			mode[qlm] = CVMX_QLM_MODE_SATA_2X1;
+			ref_clock_sel[qlm] = 0;
+			ref_clock_input[qlm] = 1;
+			sprintf(spd_env, "qlm%d_speed", qlm);
+			if (env_get(spd_env)) {
+				int spd = env_get_ulong(spd_env, 0, 8);
+
+				if (spd == 1500 || spd == 3000 || spd == 3000)
+					speed[qlm] = spd;
+				else
+					speed[qlm] = 6000;
+			} else {
+				speed[qlm] = 6000;
+			}
+		} else {
+			printf("QLM %d: disabled\n", qlm);
+		}
+	}
+
+	for (qlm = 0; qlm < 7; qlm++) {
+		int rc;
+
+		if (mode[qlm] == -1)
+			continue;
+
+		debug("Configuring qlm%d with speed(%d), mode(%d), RC(%d), Gen(%d), REF_CLK(%d), CLK_SOURCE(%d)\n",
+		      qlm, speed[qlm], mode[qlm], pcie_rc[qlm],
+		      pcie_gen[qlm] + 1,
+		      ref_clock_sel[qlm], ref_clock_input[qlm]);
+		rc = octeon_configure_qlm(qlm, speed[qlm], mode[qlm],
+					  pcie_rc[qlm], pcie_gen[qlm],
+					  ref_clock_sel[qlm],
+					  ref_clock_input[qlm]);
+
+		if (speed[qlm] == 6250) {
+			if (mode[qlm] == CVMX_QLM_MODE_RXAUI) {
+				octeon_qlm_tune_v3(0, qlm, speed[qlm], 0x12,
+						   0xa0, -1, -1);
+			} else {
+				octeon_qlm_tune_v3(0, qlm, speed[qlm], 0xa,
+						   0xa0, -1, -1);
+			}
+		} else if (speed[qlm] == 103125) {
+			octeon_qlm_tune_v3(0, qlm, speed[qlm], 0xd, 0xd0,
+					   -1, -1);
+		}
+
+		if (qlm == 4 && rc != 0)
+			/*
+			 * There is a bug with SATA with 73xx.  Until it's
+			 * fixed we need to strip it from the device tree.
+			 */
+			octeon_fdt_patch_rename((void *)gd->fdt_blob, "4,none",
+						NULL, true, NULL, NULL);
+	}
+
+	dm_gpio_set_value(&desc, 0); /* Put RGMII PHY in reset */
+	mdelay(10);
+	dm_gpio_set_value(&desc, 1); /* Take RGMII PHY out of reset */
+}
+
+int board_late_init(void)
+{
+	board_configure_qlms();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/Marvell/octeon_ebb7304/board_ddr.h b/roms/u-boot/board/Marvell/octeon_ebb7304/board_ddr.h
new file mode 100644
index 000000000..f2f3419e5
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeon_ebb7304/board_ddr.h
@@ -0,0 +1,447 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __BOARD_DDR_H__
+#define __BOARD_DDR_H__
+
+#define OCTEON_EBB7304_DRAM_SOCKET_CONFIGURATION0			\
+	{ {0x1050, 0x0}, {NULL, NULL} }, { {0x1051, 0x0}, {NULL, NULL} }
+#define OCTEON_EBB7304_DRAM_SOCKET_CONFIGURATION1			\
+	{ {0x1052, 0x0}, {NULL, NULL} }, { {0x1053, 0x0}, {NULL, NULL} }
+
+#define OCTEON_EBB7304_BOARD_EEPROM_TWSI_ADDR	0x56
+
+/*
+ * Local copy of these parameters to allow for customization for this
+ * board design.  The generic version resides in lib_octeon_shared.h.
+ */
+
+/* LMC0_MODEREG_PARAMS1 */
+#define OCTEON_EBB7304_MODEREG_PARAMS1_1RANK_1SLOT		\
+	{							\
+		.cn78xx = {					\
+			.pasr_00	= 0,			\
+			.asr_00		= 0,			\
+			.srt_00		= 0,			\
+			.rtt_wr_00	= ddr4_rttwr_80ohm & 3,	\
+			.rtt_wr_00_ext	= (ddr4_rttwr_80ohm >> 2) & 1,	\
+			.dic_00		= ddr4_dic_34ohm,	\
+			.rtt_nom_00	= 0,                    \
+			.pasr_01	= 0,			\
+			.asr_01		= 0,			\
+			.srt_01		= 0,			\
+			.rtt_wr_01	= 0,			\
+			.dic_01		= ddr4_dic_34ohm,	\
+			.rtt_nom_01	= 0,			\
+			.pasr_10	= 0,			\
+			.asr_10		= 0,			\
+			.srt_10		= 0,			\
+			.rtt_wr_10	= 0,			\
+			.dic_10		= ddr4_dic_34ohm,	\
+			.rtt_nom_10	= 0,			\
+			.pasr_11	= 0,			\
+			.asr_11		= 0,			\
+			.srt_11		= 0,			\
+			.rtt_wr_11	= 0,			\
+			.dic_11		= ddr4_dic_34ohm,	\
+			.rtt_nom_11	= 0,			\
+		}						\
+	}
+
+#define OCTEON_EBB7304_MODEREG_PARAMS1_1RANK_2SLOT	\
+	{							\
+		.cn78xx = {					\
+			.pasr_00	= 0,			\
+			.asr_00		= 0,			\
+			.srt_00		= 0,			\
+			.rtt_wr_00	= ddr4_rttwr_80ohm & 3,	\
+			.rtt_wr_00_ext	= (ddr4_rttwr_80ohm >> 2) & 1,	\
+			.dic_00		= ddr4_dic_34ohm,	\
+			.rtt_nom_00	= 0,			\
+			.pasr_01	= 0,			\
+			.asr_01		= 0,			\
+			.srt_01		= 0,			\
+			.rtt_wr_01	= 0,			\
+			.dic_01		= ddr4_dic_34ohm,	\
+			.rtt_nom_01	= 0,			\
+			.pasr_10	= 0,			\
+			.asr_10		= 0,			\
+			.srt_10		= 0,                    \
+			.rtt_wr_10	= ddr4_rttwr_80ohm & 3,	\
+			.rtt_wr_10_ext	= (ddr4_rttwr_80ohm >> 2) & 1,	\
+			.dic_10		= ddr4_dic_34ohm,	\
+			.rtt_nom_10	= 0,			\
+			.pasr_11	= 0,			\
+			.asr_11		= 0,			\
+			.srt_11		= 0,			\
+			.rtt_wr_11	= 0,			\
+			.dic_11		= ddr4_dic_34ohm,	\
+			.rtt_nom_11	= 0			\
+		}                                               \
+	}
+
+#define OCTEON_EBB7304_MODEREG_PARAMS1_2RANK_1SLOT		\
+	{							\
+		.cn78xx = {					\
+			.pasr_00	= 0,			\
+			.asr_00		= 0,			\
+			.srt_00		= 0,			\
+			.rtt_wr_00	= ddr4_rttwr_240ohm,	\
+			.dic_00		= ddr4_dic_34ohm,	\
+			.rtt_nom_00	= 0,			\
+			.pasr_01	= 0,			\
+			.asr_01		= 0,			\
+			.srt_01		= 0,			\
+			.rtt_wr_01	= ddr4_rttwr_240ohm,	\
+			.dic_01		= ddr4_dic_34ohm,	\
+			.rtt_nom_01	= 0,			\
+			.pasr_10	= 0,			\
+			.asr_10		= 0,			\
+			.srt_10		= 0,			\
+			.dic_10		= ddr4_dic_34ohm,	\
+			.rtt_nom_10	= 0,			\
+			.pasr_11	= 0,			\
+			.asr_11		= 0,			\
+			.srt_11		= 0,			\
+			.rtt_wr_11	= 0,			\
+			.dic_11		= ddr4_dic_34ohm,	\
+			.rtt_nom_11	= 0,			\
+		}						\
+	}
+
+#define OCTEON_EBB7304_MODEREG_PARAMS1_2RANK_2SLOT		\
+	{							\
+		.cn78xx = {					\
+			.pasr_00	= 0,			\
+			.asr_00		= 0,			\
+			.srt_00		= 0,			\
+			.rtt_wr_00	= ddr4_rttwr_240ohm,	\
+			.dic_00		= ddr4_dic_34ohm,	\
+			.rtt_nom_00	= ddr4_rttnom_120ohm,	\
+			.pasr_01	= 0,			\
+			.asr_01		= 0,			\
+			.srt_01		= 0,			\
+			.rtt_wr_01	= ddr4_rttwr_240ohm,	\
+			.dic_01		= ddr4_dic_34ohm,	\
+			.rtt_nom_01	= ddr4_rttnom_120ohm,	\
+			.pasr_10	= 0,			\
+			.asr_10		= 0,			\
+			.srt_10		= 0,			\
+			.rtt_wr_10	= ddr4_rttwr_240ohm,	\
+			.dic_10		= ddr4_dic_34ohm,	\
+			.rtt_nom_10	= ddr4_rttnom_120ohm,	\
+			.pasr_11	= 0,			\
+			.asr_11		= 0,			\
+			.srt_11		= 0,			\
+			.rtt_wr_11	= ddr4_rttwr_240ohm,	\
+			.dic_11		= ddr4_dic_34ohm,	\
+			.rtt_nom_11	= ddr4_rttnom_120ohm,	\
+		}						\
+	}
+
+#define OCTEON_EBB7304_MODEREG_PARAMS1_4RANK_1SLOT		\
+	{							\
+		.cn78xx = {					\
+			.pasr_00	= 0,			\
+			.asr_00		= 0,			\
+			.srt_00		= 0,			\
+			.rtt_wr_00	= rttwr_60ohm,		\
+			.dic_00		= dic_34ohm,		\
+			.rtt_nom_00	= rttnom_20ohm,		\
+			.pasr_01	= 0,			\
+			.asr_01		= 0,			\
+			.srt_01		= 0,			\
+			.rtt_wr_01	= rttwr_60ohm,		\
+			.dic_01		= dic_34ohm,		\
+			.rtt_nom_01	= rttnom_none,		\
+			.pasr_10	= 0,			\
+			.asr_10		= 0,			\
+			.srt_10		= 0,			\
+			.rtt_wr_10	= rttwr_60ohm,		\
+			.dic_10		= dic_34ohm,		\
+			.rtt_nom_10	= rttnom_20ohm,		\
+			.pasr_11	= 0,			\
+			.asr_11		= 0,			\
+			.srt_11		= 0,			\
+			.rtt_wr_11	= rttwr_60ohm,		\
+			.dic_11		= dic_34ohm,		\
+			.rtt_nom_11	= rttnom_none,		\
+		}						\
+	}
+
+#define OCTEON_EBB7304_MODEREG_PARAMS2_1RANK_1SLOT	\
+{							\
+	.cn78xx = {					\
+		.rtt_park_00    = ddr4_rttpark_60ohm,	\
+		.vref_value_00  = 0x22,			\
+		.vref_range_00  = 0,			\
+		.rtt_park_01    = 0,			\
+		.vref_value_01  = 0,			\
+		.vref_range_01  = 0,			\
+		.rtt_park_10    = 0,			\
+		.vref_value_10  = 0,			\
+		.vref_range_10  = 0,			\
+		.rtt_park_11    = 0,			\
+		.vref_value_11  = 0,			\
+		.vref_range_11  = 0			\
+	}						\
+}
+
+/* FIX */
+#define OCTEON_EBB7304_MODEREG_PARAMS2_1RANK_2SLOT	\
+{							\
+	.cn78xx = {					\
+		.rtt_park_00    = ddr4_rttpark_48ohm,	\
+		.vref_value_00  = 0x1f,			\
+		.vref_range_00  = 0,			\
+		.rtt_park_01    = 0,			\
+		.vref_value_01  = 0,			\
+		.vref_range_01  = 0,			\
+		.rtt_park_10    = ddr4_rttpark_48ohm,	\
+		.vref_value_10  = 0x1f,			\
+		.vref_range_10  = 0,			\
+		.rtt_park_11    = 0,			\
+		.vref_value_11  = 0,			\
+		.vref_range_11  = 0			\
+	}						\
+}
+
+#define OCTEON_EBB7304_MODEREG_PARAMS2_2RANK_1SLOT	\
+{							\
+	.cn78xx = {					\
+		.rtt_park_00    = ddr4_rttpark_120ohm,	\
+		.vref_value_00  = 0x19,			\
+		.vref_range_00  = 0,			\
+		.rtt_park_01    = ddr4_rttpark_120ohm,	\
+		.vref_value_01  = 0x19,			\
+		.vref_range_01  = 0,			\
+		.rtt_park_10    = 0,			\
+		.vref_value_10  = 0,			\
+		.vref_range_10  = 0,			\
+		.rtt_park_11    = 0,			\
+		.vref_value_11  = 0,			\
+		.vref_range_11  = 0			\
+	}						\
+}
+
+#define OCTEON_EBB7304_MODEREG_PARAMS2_2RANK_2SLOT	\
+{							\
+	.cn78xx = {					\
+		.rtt_park_00    = ddr4_rttpark_60ohm,	\
+		.vref_value_00  = 0x19,			\
+		.vref_range_00  = 0,			\
+		.rtt_park_01    = ddr4_rttpark_60ohm,	\
+		.vref_value_01  = 0x19,			\
+		.vref_range_01  = 0,			\
+		.rtt_park_10    = ddr4_rttpark_60ohm,	\
+		.vref_value_10  = 0x19,			\
+		.vref_range_10  = 0,			\
+		.rtt_park_11    = ddr4_rttpark_60ohm,	\
+		.vref_value_11  = 0x19,			\
+		.vref_range_11  = 0			\
+	}						\
+}
+
+#define OCTEON_EBB7304_MODEREG_PARAMS2_4RANK_1SLOT	\
+{							\
+	.cn78xx = {					\
+		.rtt_park_00    = ddr4_rttpark_80ohm,	\
+		.vref_value_00  = 0x1f,			\
+		.vref_range_00  = 0,			\
+		.rtt_park_01    = ddr4_rttpark_80ohm,	\
+		.vref_value_01  = 0x1f,			\
+		.vref_range_01  = 0,			\
+		.rtt_park_10    = 0,			\
+		.vref_value_10  = 0,			\
+		.vref_range_10  = 0,			\
+		.rtt_park_11    = 0,			\
+		.vref_value_11  = 0,			\
+		.vref_range_11  = 0			\
+	}						\
+}
+
+#define OCTEON_EBB7304_CN78XX_DRAM_ODT_1RANK_CONFIGURATION		\
+	/*   1 */							\
+	{								\
+		ddr4_dqx_driver_34_ohm,					\
+		0x00000000ULL,						\
+		OCTEON_EBB7304_MODEREG_PARAMS1_1RANK_1SLOT,		\
+		OCTEON_EBB7304_MODEREG_PARAMS2_1RANK_1SLOT,		\
+		ddr4_rodt_ctl_48_ohm,					\
+		0x00000000ULL,						\
+		0							\
+	},								\
+	/*   2 */							\
+	{								\
+		ddr4_dqx_driver_34_ohm,					\
+		0x00000000ULL,						\
+		OCTEON_EBB7304_MODEREG_PARAMS1_1RANK_2SLOT,		\
+		OCTEON_EBB7304_MODEREG_PARAMS2_1RANK_2SLOT,		\
+		ddr4_rodt_ctl_80_ohm,					\
+		0x00000000ULL,						\
+		0							\
+	}
+
+#define OCTEON_EBB7304_CN78XX_DRAM_ODT_2RANK_CONFIGURATION		\
+	/*   1 */							\
+	{								\
+		ddr4_dqx_driver_34_ohm,					\
+		0x00000000ULL,						\
+		OCTEON_EBB7304_MODEREG_PARAMS1_2RANK_1SLOT,		\
+		OCTEON_EBB7304_MODEREG_PARAMS2_2RANK_1SLOT,		\
+		ddr4_rodt_ctl_80_ohm,					\
+		0x00000000ULL,						\
+		0							\
+	},								\
+	/*   2 */							\
+	{								\
+		ddr4_dqx_driver_34_ohm,					\
+		0x0c0c0303ULL,						\
+		OCTEON_EBB7304_MODEREG_PARAMS1_2RANK_2SLOT,		\
+		OCTEON_EBB7304_MODEREG_PARAMS2_2RANK_2SLOT,		\
+		ddr4_rodt_ctl_48_ohm,					\
+		0x04080102ULL,						\
+		0							\
+	}
+
+#define OCTEON_EBB7304_CN78XX_DRAM_ODT_4RANK_CONFIGURATION		\
+	/*   1 */							\
+	{								\
+		ddr4_dqx_driver_34_ohm,					\
+		0x01030203ULL,						\
+		OCTEON_EBB7304_MODEREG_PARAMS1_4RANK_1SLOT,		\
+		OCTEON_EBB7304_MODEREG_PARAMS2_4RANK_1SLOT,		\
+		ddr4_rodt_ctl_48_ohm,					\
+		0x01010202ULL,						\
+		0							\
+	}
+
+/*
+ * Construct a static initializer for the ddr_configuration_t variable that
+ * holds (almost) all of the information required for DDR initialization.
+ */
+
+/*
+ * The parameters below make up the custom_lmc_config data structure.
+ * This structure is used to customize the way that the LMC DRAM
+ * Controller is configured for a particular board design.
+ *
+ * Refer to the file lib_octeon_board_table_entry.h for a description
+ * of the custom board settings.  It is usually kept in the following
+ * location... arch/mips/include/asm/arch-octeon/
+ *
+ */
+
+#define OCTEON_EBB7304_DDR_CONFIGURATION				\
+/* Interface 0 */							\
+{									\
+	.custom_lmc_config = {						\
+		.min_rtt_nom_idx		= 1,			\
+		.max_rtt_nom_idx		= 7,			\
+		.min_rodt_ctl			= 1,			\
+		.max_rodt_ctl			= 7,			\
+		.ck_ctl				= ddr4_driver_34_ohm,	\
+		.cmd_ctl			= ddr4_driver_34_ohm,	\
+		.ctl_ctl			= ddr4_driver_34_ohm,	\
+		.min_cas_latency		= 0,			\
+		.offset_en			= 1,			\
+		.offset_udimm			= 2,			\
+		.offset_rdimm			= 2,			\
+		.ddr_rtt_nom_auto		= 0,			\
+		.ddr_rodt_ctl_auto		= 0,			\
+		.rlevel_comp_offset_udimm	= 0,			\
+		.rlevel_comp_offset_rdimm	= 0,			\
+		.rlevel_compute			= 0,			\
+		.ddr2t_udimm			= 1,			\
+		.ddr2t_rdimm			= 1,			\
+		.maximum_adjacent_rlevel_delay_increment = 2,		\
+		.fprch2				= 2,			\
+		.dll_write_offset		= NULL,			\
+		.dll_read_offset		= NULL,			\
+		.parity				= 0			\
+	},								\
+	.dimm_config_table = {						\
+		OCTEON_EBB7304_DRAM_SOCKET_CONFIGURATION0,		\
+		DIMM_CONFIG_TERMINATOR					\
+	},								\
+	.unbuffered = {							\
+		.ddr_board_delay		= 0,			\
+		.lmc_delay_clk			= 0,			\
+		.lmc_delay_cmd			= 0,			\
+		.lmc_delay_dq			= 0			\
+	},								\
+	.registered = {							\
+		.ddr_board_delay		= 0,			\
+		.lmc_delay_clk			= 0,			\
+		.lmc_delay_cmd			= 0,			\
+		.lmc_delay_dq			= 0			\
+	},								\
+	.odt_1rank_config = {						\
+		OCTEON_EBB7304_CN78XX_DRAM_ODT_1RANK_CONFIGURATION	\
+	},								\
+	.odt_2rank_config = {						\
+		OCTEON_EBB7304_CN78XX_DRAM_ODT_2RANK_CONFIGURATION	\
+	},								\
+	.odt_4rank_config = {						\
+		OCTEON_EBB7304_CN78XX_DRAM_ODT_4RANK_CONFIGURATION	\
+	}								\
+},									\
+/* Interface 1 */							\
+{									\
+	.custom_lmc_config = {						\
+		.min_rtt_nom_idx		= 1,			\
+		.max_rtt_nom_idx		= 7,			\
+		.min_rodt_ctl			= 1,			\
+		.max_rodt_ctl			= 7,			\
+		.ck_ctl				= ddr4_driver_34_ohm,	\
+		.cmd_ctl			= ddr4_driver_34_ohm,	\
+		.ctl_ctl			= ddr4_driver_34_ohm,	\
+		.min_cas_latency		= 0,			\
+		.offset_en			= 1,			\
+		.offset_udimm			= 2,			\
+		.offset_rdimm			= 2,			\
+		.ddr_rtt_nom_auto		= 0,			\
+		.ddr_rodt_ctl_auto		= 0,			\
+		.rlevel_comp_offset_udimm	= 0,			\
+		.rlevel_comp_offset_rdimm	= 0,			\
+		.rlevel_compute			= 0,			\
+		.ddr2t_udimm			= 1,			\
+		.ddr2t_rdimm			= 1,			\
+		.maximum_adjacent_rlevel_delay_increment = 2,		\
+		.fprch2				= 2,			\
+		.dll_write_offset		= NULL,			\
+		.dll_read_offset		= NULL,			\
+		.parity				= 0			\
+	},								\
+	.dimm_config_table = {						\
+		OCTEON_EBB7304_DRAM_SOCKET_CONFIGURATION1,		\
+		DIMM_CONFIG_TERMINATOR					\
+	},								\
+	.unbuffered = {							\
+		.ddr_board_delay		= 0,			\
+		.lmc_delay_clk			= 0,			\
+		.lmc_delay_cmd			= 0,			\
+		.lmc_delay_dq			= 0			\
+	},								\
+	.registered = {							\
+		.ddr_board_delay		= 0,			\
+		.lmc_delay_clk			= 0,			\
+		.lmc_delay_cmd			= 0,			\
+		.lmc_delay_dq			= 0			\
+	},								\
+	.odt_1rank_config = {						\
+		OCTEON_EBB7304_CN78XX_DRAM_ODT_1RANK_CONFIGURATION	\
+	},								\
+	.odt_2rank_config = {						\
+		OCTEON_EBB7304_CN78XX_DRAM_ODT_2RANK_CONFIGURATION	\
+	},								\
+	.odt_4rank_config = {						\
+		OCTEON_EBB7304_CN78XX_DRAM_ODT_4RANK_CONFIGURATION	\
+	}								\
+},
+
+#endif /* __BOARD_DDR_H__ */
diff --git a/roms/u-boot/board/Marvell/octeon_nic23/Kconfig b/roms/u-boot/board/Marvell/octeon_nic23/Kconfig
new file mode 100644
index 000000000..3c42e8acd
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeon_nic23/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_OCTEON_NIC23
+
+config SYS_BOARD
+	string
+	default "octeon_nic23"
+
+config SYS_VENDOR
+	string
+	default "Marvell"
+
+config SYS_CONFIG_NAME
+	string
+	default "octeon_nic23"
+
+config DEFAULT_DEVICE_TREE
+	string
+	default "mrvl,octeon-nic23"
+
+endif
diff --git a/roms/u-boot/board/Marvell/octeon_nic23/MAINTAINERS b/roms/u-boot/board/Marvell/octeon_nic23/MAINTAINERS
new file mode 100644
index 000000000..cd5148dcf
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeon_nic23/MAINTAINERS
@@ -0,0 +1,7 @@
+OCTEON_NIC23 BOARD
+M:	Aaron Williams <awilliams@marvell.com>
+S:	Maintained
+F:	board/Marvell/octeon_nic23/*
+F:	configs/octeon_nic23_defconfig
+F:	include/configs/octeon_nic23.h
+F:	arch/mips/dts/mrvl,octeon-nic23.dts
diff --git a/roms/u-boot/board/Marvell/octeon_nic23/Makefile b/roms/u-boot/board/Marvell/octeon_nic23/Makefile
new file mode 100644
index 000000000..a79b94ec6
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeon_nic23/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2021 Stefan Roese <sr@denx.de>
+# Copyright (C) 2019-2020 Marvell International Ltd.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= board.o
diff --git a/roms/u-boot/board/Marvell/octeon_nic23/board.c b/roms/u-boot/board/Marvell/octeon_nic23/board.c
new file mode 100644
index 000000000..9f5eb2e2a
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeon_nic23/board.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Stefan Roese <sr@denx.de>
+ */
+
+#include <dm.h>
+#include <ram.h>
+
+#include <mach/octeon_ddr.h>
+#include <mach/cvmx-qlm.h>
+#include <mach/octeon_qlm.h>
+#include <mach/octeon_fdt.h>
+#include <mach/cvmx-helper.h>
+#include <mach/cvmx-helper-cfg.h>
+#include <mach/cvmx-helper-util.h>
+#include <mach/cvmx-bgxx-defs.h>
+
+#include "board_ddr.h"
+
+#define NIC23_DEF_DRAM_FREQ		800
+
+static u8 octeon_nic23_cfg0_spd_values[512] = {
+	OCTEON_NIC23_CFG0_SPD_VALUES
+};
+
+static struct ddr_conf board_ddr_conf[] = {
+	 OCTEON_NIC23_DDR_CONFIGURATION
+};
+
+struct ddr_conf *octeon_ddr_conf_table_get(int *count, int *def_ddr_freq)
+{
+	*count = ARRAY_SIZE(board_ddr_conf);
+	*def_ddr_freq = NIC23_DEF_DRAM_FREQ;
+
+	return board_ddr_conf;
+}
+
+int board_fix_fdt(void *fdt)
+{
+	u32 range_data[5 * 8];
+	bool rev4;
+	int node;
+	int rc;
+
+	/*
+	 * ToDo:
+	 * Read rev4 info from EEPROM or where the original U-Boot does
+	 * and don't hard-code it here.
+	 */
+	rev4 = true;
+
+	debug("%s() rev4: %s\n", __func__, rev4 ? "true" : "false");
+	/* Patch the PHY configuration based on board revision */
+	rc = octeon_fdt_patch_rename(fdt,
+				     rev4 ? "4,nor-flash" : "4,no-nor-flash",
+				     "cavium,board-trim", false, NULL, NULL);
+	if (!rev4) {
+		/* Modify the ranges for CS 0 */
+		node = fdt_node_offset_by_compatible(fdt, -1,
+						     "cavium,octeon-3860-bootbus");
+		if (node < 0) {
+			printf("%s: Error: cannot find boot bus in device tree!\n",
+			       __func__);
+			return -1;
+		}
+
+		rc = fdtdec_get_int_array(fdt, node, "ranges",
+					  range_data, 5 * 8);
+		if (rc) {
+			printf("%s: Error reading ranges from boot bus FDT\n",
+			       __func__);
+			return -1;
+		}
+		range_data[2] = cpu_to_fdt32(0x10000);
+		range_data[3] = 0;
+		range_data[4] = 0;
+		rc = fdt_setprop(fdt, node, "ranges", range_data,
+				 sizeof(range_data));
+		if (rc) {
+			printf("%s: Error updating boot bus ranges in fdt\n",
+			       __func__);
+		}
+	}
+	return rc;
+}
+
+void board_configure_qlms(void)
+{
+	octeon_configure_qlm(4, 3000, CVMX_QLM_MODE_SATA_2X1, 0, 0, 0, 0);
+	octeon_configure_qlm(5, 103125, CVMX_QLM_MODE_XFI_1X2, 0, 0, 2, 0);
+	/* Apply amplitude tuning to 10G interface */
+	octeon_qlm_tune_v3(0, 4, 3000, -1, -1, 7, -1);
+	octeon_qlm_tune_v3(0, 5, 103125, 0x19, 0x0, -1, -1);
+	octeon_qlm_set_channel_v3(0, 5, 0);
+	octeon_qlm_dfe_disable(0, 5, -1, 103125, CVMX_QLM_MODE_XFI_1X2);
+	debug("QLM 4 reference clock: %d\n"
+	      "DLM 5 reference clock: %d\n",
+	      cvmx_qlm_measure_clock(4), cvmx_qlm_measure_clock(5));
+}
+
+int board_late_init(void)
+{
+	board_configure_qlms();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/Marvell/octeon_nic23/board_ddr.h b/roms/u-boot/board/Marvell/octeon_nic23/board_ddr.h
new file mode 100644
index 000000000..eac877faf
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeon_nic23/board_ddr.h
@@ -0,0 +1,269 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __BOARD_DDR_H__
+#define __BOARD_DDR_H__
+
+#define OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0			\
+	{ {0x0, 0x0}, {octeon_nic23_cfg0_spd_values, NULL} }
+
+#define NIC23_MTA8ATF51264AZ2G3_SPD_VALUES			\
+	0x23, 0x10, 0x0c, 0x02, 0x84, 0x19, 0x00, 0x08,		\
+	0x00, 0x00, 0x00, 0x03, 0x01, 0x0b, 0x80, 0x00,		\
+	0x00, 0x00, 0x08, 0x0c, 0xf4, 0x1b, 0x00, 0x00,		\
+	0x6c, 0x6c, 0x6c, 0x11, 0x08, 0x74, 0x20, 0x08,		\
+	0x00, 0x05, 0x70, 0x03, 0x00, 0xa8, 0x1e, 0x2b,		\
+	0x2b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x0c, 0x2c, 0x15, 0x35,		\
+	0x15, 0x35, 0x0b, 0x2c, 0x15, 0x35, 0x0b, 0x35,		\
+	0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0xec, 0xb5, 0xce,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x30, 0x0e,		\
+	0x11, 0x11, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x2e,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x80, 0x2c, 0x0f, 0x14, 0x50, 0x0e, 0x08, 0x18,		\
+	0xc8, 0x31, 0x38, 0x41, 0x53, 0x46, 0x31, 0x47,		\
+	0x37, 0x32, 0x41, 0x5a, 0x2d, 0x32, 0x47, 0x31,		\
+	0x41, 0x31, 0x20, 0x20, 0x20, 0x31, 0x80, 0x2c,		\
+	0x41, 0x44, 0x50, 0x41, 0x45, 0x4e, 0x43, 0x39,		\
+	0x30, 0x30, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,		\
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+#define OCTEON_NIC23_CFG0_SPD_VALUES	NIC23_MTA8ATF51264AZ2G3_SPD_VALUES
+
+#define OCTEON_NIC23_BOARD_EEPROM_TWSI_ADDR	0x56
+
+#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT		\
+{								\
+		.cn78xx = {					\
+			.pasr_00	= 0,			\
+			.asr_00		= 0,			\
+			.srt_00		= 0,			\
+			.rtt_wr_00	= ddr4_rttwr_80ohm & 3,	\
+			.rtt_wr_00_ext	= (ddr4_rttwr_80ohm >> 2) & 1, \
+			.dic_00		= ddr4_dic_34ohm,	\
+			.rtt_nom_00	= 0,                    \
+			.pasr_01	= 0,			\
+			.asr_01		= 0,			\
+			.srt_01		= 0,			\
+			.rtt_wr_01	= 0,			\
+			.dic_01		= ddr4_dic_34ohm,	\
+			.rtt_nom_01	= 0,			\
+			.pasr_10	= 0,			\
+			.asr_10		= 0,			\
+			.srt_10		= 0,			\
+			.rtt_wr_10	= 0,			\
+			.dic_10		= ddr4_dic_34ohm,	\
+			.rtt_nom_10	= 0,			\
+			.pasr_11	= 0,			\
+			.asr_11		= 0,			\
+			.srt_11		= 0,			\
+			.rtt_wr_11	= 0,			\
+			.dic_11		= ddr4_dic_34ohm,	\
+			.rtt_nom_11	= 0,			\
+		}						\
+	}
+
+#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT		\
+{								\
+		.cn78xx = {					\
+			.pasr_00	= 0,			\
+			.asr_00		= 0,			\
+			.srt_00		= 0,			\
+			.rtt_wr_00	= ddr4_rttwr_80ohm & 3,	\
+			.rtt_wr_00_ext	= (ddr4_rttwr_80ohm >> 2) & 1, \
+			.dic_00		= ddr4_dic_34ohm,	\
+			.rtt_nom_00	= 0,			\
+			.pasr_01	= 0,			\
+			.asr_01		= 0,			\
+			.srt_01		= 0,			\
+			.rtt_wr_01	= 0,			\
+			.dic_01		= ddr4_dic_34ohm,	\
+			.rtt_nom_01	= 0,			\
+			.pasr_10	= 0,			\
+			.asr_10		= 0,			\
+			.srt_10		= 0,                    \
+			.rtt_wr_10	= ddr4_rttwr_80ohm & 3,	\
+			.rtt_wr_10_ext	= (ddr4_rttwr_80ohm >> 2) & 1, \
+			.dic_10		= ddr4_dic_34ohm,	\
+			.rtt_nom_10	= 0,			\
+			.pasr_11	= 0,			\
+			.asr_11		= 0,			\
+			.srt_11		= 0,			\
+			.rtt_wr_11	= 0,			\
+			.dic_11		= ddr4_dic_34ohm,	\
+			.rtt_nom_11	= 0			\
+		}                                               \
+}
+
+#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT	\
+{							\
+	.cn78xx = {					\
+		.rtt_park_00    = ddr4_rttpark_60ohm,	\
+		.vref_value_00  = 0x22,			\
+		.vref_range_00  = 0,			\
+		.rtt_park_01    = 0,			\
+		.vref_value_01  = 0,			\
+		.vref_range_01  = 0,			\
+		.rtt_park_10    = 0,			\
+		.vref_value_10  = 0,			\
+		.vref_range_10  = 0,			\
+		.rtt_park_11    = 0,			\
+		.vref_value_11  = 0,			\
+		.vref_range_11  = 0			\
+	}						\
+}
+
+#define  OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT	\
+{							\
+	.cn78xx = {					\
+		.rtt_park_00    = ddr4_rttpark_48ohm,	\
+		.vref_value_00  = 0x1f,			\
+		.vref_range_00  = 0,			\
+		.rtt_park_01    = 0,			\
+		.vref_value_01  = 0,			\
+		.vref_range_01  = 0,			\
+		.rtt_park_10    = ddr4_rttpark_48ohm,	\
+		.vref_value_10  = 0x1f,			\
+		.vref_range_10  = 0,			\
+		.rtt_park_11    = 0,			\
+		.vref_value_11  = 0,			\
+		.vref_range_11  = 0			\
+	}						\
+}
+
+#define OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION		\
+	/*   1 */							\
+	{								\
+		ddr4_dqx_driver_34_ohm,					\
+		0x00000000ULL,						\
+		OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT,		\
+		OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT,		\
+		ddr4_rodt_ctl_48_ohm,					\
+		0x00000000ULL,						\
+		0							\
+	},								\
+	/*   2 */							\
+	{								\
+		ddr4_dqx_driver_34_ohm,					\
+		0x00000000ULL,						\
+		OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT,		\
+		OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT,		\
+		ddr4_rodt_ctl_80_ohm,					\
+		0x00000000ULL,						\
+		0							\
+	}
+
+/*
+ * Construct a static initializer for the ddr_configuration_t variable that
+ * holds (almost) all of the information required for DDR initialization.
+ */
+
+/*
+ * The parameters below make up the custom_lmc_config data structure.
+ * This structure is used to customize the way that the LMC DRAM
+ * Controller is configured for a particular board design.
+ *
+ * Refer to the file lib_octeon_board_table_entry.h for a description
+ * of the custom board settings.  It is usually kept in the following
+ * location... arch/mips/include/asm/arch-octeon/
+ *
+ */
+
+#define OCTEON_NIC23_DDR_CONFIGURATION					\
+/* Interface 0 */							\
+{									\
+	.custom_lmc_config = {						\
+		.min_rtt_nom_idx	= 2,				\
+		.max_rtt_nom_idx	= 5,				\
+		.min_rodt_ctl		= 2,				\
+		.max_rodt_ctl		= 4,				\
+		.ck_ctl                 = ddr4_driver_34_ohm,           \
+		.cmd_ctl                = ddr4_driver_34_ohm,           \
+		.ctl_ctl                = ddr4_driver_34_ohm,           \
+		.min_cas_latency	= 7,				\
+		.offset_en		= 1,				\
+		.offset_udimm		= 2,				\
+		.offset_rdimm		= 2,				\
+		.ddr_rtt_nom_auto	= 0,				\
+		.ddr_rodt_ctl_auto	= 0,				\
+		.rlevel_compute		= 0,				\
+		.ddr2t_udimm		= 1,				\
+		.ddr2t_rdimm		= 1,				\
+		.maximum_adjacent_rlevel_delay_increment = 2,           \
+		.fprch2			= 2,				\
+		.dll_write_offset       = NULL,                         \
+		.dll_read_offset        = NULL,                         \
+		.disable_sequential_delay_check = 1,                    \
+		.parity			= 0				\
+	},								\
+	.dimm_config_table = {						\
+		OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0,		\
+		DIMM_CONFIG_TERMINATOR					\
+	},								\
+	.unbuffered = {							\
+		.ddr_board_delay = 0,					\
+		.lmc_delay_clk = 0,					\
+		.lmc_delay_cmd = 0,					\
+		.lmc_delay_dq = 0					\
+	},								\
+	.registered = {							\
+		.ddr_board_delay = 0,					\
+		.lmc_delay_clk = 0,					\
+		.lmc_delay_cmd = 0,					\
+		.lmc_delay_dq = 0					\
+	},								\
+	.odt_1rank_config = {						\
+		OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION	\
+	},								\
+},
+
+#endif /* __BOARD_DDR_H__ */
diff --git a/roms/u-boot/board/Marvell/octeontx/Kconfig b/roms/u-boot/board/Marvell/octeontx/Kconfig
new file mode 100644
index 000000000..45d115916
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_OCTEONTX_81XX || TARGET_OCTEONTX_83XX
+
+config SYS_VENDOR
+	string
+	default	"Marvell"
+
+config SYS_BOARD
+	string
+	default "octeontx"
+
+config SYS_CONFIG_NAME
+	default "octeontx_common"
+
+endif
diff --git a/roms/u-boot/board/Marvell/octeontx/MAINTAINERS b/roms/u-boot/board/Marvell/octeontx/MAINTAINERS
new file mode 100644
index 000000000..1f3b12b1a
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx/MAINTAINERS
@@ -0,0 +1,8 @@
+OCTEONTX BOARD
+M:	Aaron Williams <awilliams@marvell.com>
+S:	Maintained
+F:	board/Marvell/octeontx/
+F:	include/configs/octeontx_81xx.h
+F:	include/configs/octeontx_83xx.h
+F:	configs/octeontx_81xx_defconfig
+F:	configs/octeontx_83xx_defconfig
diff --git a/roms/u-boot/board/Marvell/octeontx/Makefile b/roms/u-boot/board/Marvell/octeontx/Makefile
new file mode 100644
index 000000000..fbe32ae00
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx/Makefile
@@ -0,0 +1,9 @@
+#/*
+# * Copyright (C) 2018 Marvell International Ltd.
+# *
+# * SPDX-License-Identifier:    GPL-2.0
+# * https://spdx.org/licenses
+# */
+
+obj-y	:= board.o smc.o soc-utils.o
+obj-$(CONFIG_OF_LIBFDT) += board-fdt.o
diff --git a/roms/u-boot/board/Marvell/octeontx/board-fdt.c b/roms/u-boot/board/Marvell/octeontx/board-fdt.c
new file mode 100644
index 000000000..0b05ef11e
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx/board-fdt.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier:    GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <errno.h>
+#include <env.h>
+#include <log.h>
+#include <net.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <linux/libfdt.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <asm/arch/board.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int fdt_get_mdio_bus(const void *fdt, int phy_offset)
+{
+	int node, bus = -1;
+	const u64 *reg;
+	u64 addr;
+
+	if (phy_offset < 0)
+		return -1;
+	/* obtain mdio node and get the reg prop */
+	node = fdt_parent_offset(fdt, phy_offset);
+	if (node < 0)
+		return -1;
+
+	reg = fdt_getprop(fdt, node, "reg", NULL);
+	addr = fdt64_to_cpu(*reg);
+	bus = (addr & (1 << 7)) ? 1 : 0;
+	return bus;
+}
+
+static int fdt_get_phy_addr(const void *fdt, int phy_offset)
+{
+	const u32 *reg;
+	int addr = -1;
+
+	if (phy_offset < 0)
+		return -1;
+	reg = fdt_getprop(fdt, phy_offset, "reg", NULL);
+	addr = fdt32_to_cpu(*reg);
+	return addr;
+}
+
+void fdt_parse_phy_info(void)
+{
+	const void *fdt = gd->fdt_blob;
+	int offset = 0, node, bgx_id = 0, lmacid = 0;
+	const u32 *val;
+	char bgxname[24];
+	int len, rgx_id = 0, eth_id = 0;
+	int phandle, phy_offset;
+	int subnode, i;
+	int bdknode;
+
+	bdknode = fdt_path_offset(fdt, "/cavium,bdk");
+	if (bdknode < 0) {
+		printf("%s: bdk node is missing from device tree: %s\n",
+		       __func__, fdt_strerror(bdknode));
+	}
+
+	offset = fdt_node_offset_by_compatible(fdt, -1, "pci-bridge");
+	if (offset < 1)
+		return;
+
+	for (bgx_id = 0; bgx_id < MAX_BGX_PER_NODE; bgx_id++) {
+		int phy_addr[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = -1};
+		bool autoneg_dis[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = 0};
+		int mdio_bus[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = -1};
+		bool lmac_reg[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = 0};
+		bool lmac_enable[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = 0};
+
+		snprintf(bgxname, sizeof(bgxname), "bgx%d", bgx_id);
+		node = fdt_subnode_offset(fdt, offset, bgxname);
+		if (node < 0) {
+			/* check if it is rgx node */
+			snprintf(bgxname, sizeof(bgxname), "rgx%d", rgx_id);
+			node = fdt_subnode_offset(fdt, offset, bgxname);
+			if (node < 0) {
+				debug("bgx%d/rgx0 node not found\n", bgx_id);
+				return;
+			}
+		}
+		debug("bgx%d node found\n", bgx_id);
+
+		/*
+		 * loop through each of the bgx/rgx nodes
+		 * to find PHY nodes
+		 */
+		fdt_for_each_subnode(subnode, fdt, node) {
+			/* Check for reg property */
+			val = fdt_getprop(fdt, subnode, "reg", &len);
+			if (val) {
+				debug("lmacid = %d\n", lmacid);
+				lmac_reg[lmacid] = 1;
+			}
+			/* check for phy-handle property */
+			val = fdt_getprop(fdt, subnode, "phy-handle", &len);
+			if (val) {
+				phandle = fdt32_to_cpu(*val);
+				if (!phandle) {
+					debug("phandle not valid %d\n", lmacid);
+				} else {
+					phy_offset = fdt_node_offset_by_phandle
+							(fdt, phandle);
+					phy_addr[lmacid] = fdt_get_phy_addr
+							(fdt, phy_offset);
+					mdio_bus[lmacid] = fdt_get_mdio_bus
+							(fdt, phy_offset);
+					}
+				} else {
+					debug("phy-handle prop not found %d\n",
+					      lmacid);
+				}
+				/* check for autonegotiation property */
+				val = fdt_getprop(fdt, subnode,
+						  "cavium,disable-autonegotiation",
+						  &len);
+				if (val)
+					autoneg_dis[lmacid] = 1;
+
+				eth_id++;
+				lmacid++;
+			}
+
+			for (i = 0; i < MAX_LMAC_PER_BGX; i++) {
+				const char *str;
+
+				snprintf(bgxname, sizeof(bgxname),
+					 "BGX-ENABLE.N0.BGX%d.P%d", bgx_id, i);
+				if (bdknode >= 0) {
+					str = fdt_getprop(fdt, bdknode,
+							  bgxname, &len);
+					if (str)
+						lmac_enable[i] =
+							simple_strtol(str, NULL,
+								      10);
+				}
+			}
+
+			lmacid = 0;
+			bgx_set_board_info(bgx_id, mdio_bus, phy_addr,
+					   autoneg_dis, lmac_reg, lmac_enable);
+		}
+}
+
+static int fdt_get_bdk_node(void)
+{
+	int node, ret;
+	const void *fdt = gd->fdt_blob;
+
+	if (!fdt) {
+		printf("ERROR: %s: no valid device tree found\n", __func__);
+		return 0;
+	}
+
+	ret = fdt_check_header(fdt);
+	if (ret < 0) {
+		printf("fdt: %s\n", fdt_strerror(ret));
+		return 0;
+	}
+
+	node = fdt_path_offset(fdt, "/cavium,bdk");
+	if (node < 0) {
+		printf("%s: /cavium,bdk is missing from device tree: %s\n",
+		       __func__, fdt_strerror(node));
+		return 0;
+	}
+	return node;
+}
+
+const char *fdt_get_board_serial(void)
+{
+	const void *fdt = gd->fdt_blob;
+	int node, len = 64;
+	const char *str = NULL;
+
+	node = fdt_get_bdk_node();
+	if (!node)
+		return NULL;
+
+	str = fdt_getprop(fdt, node, "BOARD-SERIAL", &len);
+	if (!str)
+		printf("Error: cannot retrieve board serial from fdt\n");
+	return str;
+}
+
+const char *fdt_get_board_revision(void)
+{
+	const void *fdt = gd->fdt_blob;
+	int node, len = 64;
+	const char *str = NULL;
+
+	node = fdt_get_bdk_node();
+	if (!node)
+		return NULL;
+
+	str = fdt_getprop(fdt, node, "BOARD-REVISION", &len);
+	if (!str)
+		printf("Error: cannot retrieve board revision from fdt\n");
+	return str;
+}
+
+const char *fdt_get_board_model(void)
+{
+	const void *fdt = gd->fdt_blob;
+	int node, len = 16;
+	const char *str = NULL;
+
+	node = fdt_get_bdk_node();
+	if (!node)
+		return NULL;
+
+	str = fdt_getprop(fdt, node, "BOARD-MODEL", &len);
+	if (!str)
+		printf("Error: cannot retrieve board model from fdt\n");
+	return str;
+}
+
+void fdt_board_get_ethaddr(int bgx, int lmac, unsigned char *eth)
+{
+	const void *fdt = gd->fdt_blob;
+	const char *mac = NULL;
+	int offset = 0, node, len;
+	int subnode, i = 0;
+	char bgxname[24];
+
+	offset = fdt_node_offset_by_compatible(fdt, -1, "pci-bridge");
+	if (offset < 0) {
+		printf("%s couldn't find mrml bridge node in fdt\n",
+		       __func__);
+		return;
+	}
+	if (bgx == 2 && otx_is_soc(CN81XX)) {
+		snprintf(bgxname, sizeof(bgxname), "rgx%d", 0);
+		lmac = 0;
+	} else {
+		snprintf(bgxname, sizeof(bgxname), "bgx%d", bgx);
+	}
+
+	node = fdt_subnode_offset(fdt, offset, bgxname);
+
+	fdt_for_each_subnode(subnode, fdt, node) {
+		if (i++ != lmac)
+			continue;
+		/* check for local-mac-address */
+		mac = fdt_getprop(fdt, subnode, "local-mac-address", &len);
+		if (mac) {
+			debug("%s mac %pM\n", __func__, mac);
+			memcpy(eth, mac, ARP_HLEN);
+		} else {
+			memset(eth, 0, ARP_HLEN);
+		}
+		debug("%s eth %pM\n", __func__, eth);
+		return;
+	}
+}
+
+int arch_fixup_memory_node(void *blob)
+{
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	/* remove "cavium, bdk" node from DT */
+	int ret = 0, offset;
+
+	ret = fdt_check_header(blob);
+	if (ret < 0) {
+		printf("ERROR: %s\n", fdt_strerror(ret));
+		return ret;
+	}
+
+	if (blob) {
+		offset = fdt_path_offset(blob, "/cavium,bdk");
+		if (offset < 0) {
+			printf("ERROR: FDT BDK node not found\n");
+			return offset;
+		}
+
+		/* delete node */
+		ret = fdt_del_node(blob, offset);
+		if (ret < 0) {
+			printf("WARNING : could not remove bdk node\n");
+			return ret;
+		}
+
+		debug("%s deleted bdk node\n", __func__);
+	}
+
+	return 0;
+}
+
+/**
+ * Return the FDT base address that was passed by ATF
+ *
+ * @return	FDT base address received from ATF in x1 register
+ */
+void *board_fdt_blob_setup(void)
+{
+	return (void *)fdt_base_addr;
+}
diff --git a/roms/u-boot/board/Marvell/octeontx/board.c b/roms/u-boot/board/Marvell/octeontx/board.c
new file mode 100644
index 000000000..059ebf8f1
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx/board.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier:    GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <dm.h>
+#include <malloc.h>
+#include <errno.h>
+#include <env.h>
+#include <init.h>
+#include <log.h>
+#include <netdev.h>
+#include <pci_ids.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/arch/smc.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/board.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void octeontx_cleanup_ethaddr(void)
+{
+	char ename[32];
+
+	for (int i = 0; i < 20; i++) {
+		sprintf(ename, i ? "eth%daddr" : "ethaddr", i);
+		if (env_get(ename))
+			env_set(ename, NULL);
+	}
+}
+
+int octeontx_board_has_pmp(void)
+{
+	return (otx_is_board("sff8104") || otx_is_board("nas8104"));
+}
+
+int board_early_init_r(void)
+{
+	pci_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_NET_OCTEONTX))
+		fdt_parse_phy_info();
+
+	return 0;
+}
+
+int timer_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = smc_dram_size(0);
+	gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
+	mem_map_fill();
+
+	return 0;
+}
+
+void board_late_probe_devices(void)
+{
+	struct udevice *dev;
+	int err, bgx_cnt, i;
+
+	/* Probe MAC(BGX) and NIC PF devices before Network stack init */
+	bgx_cnt = otx_is_soc(CN81XX) ? 2 : 4;
+	for (i = 0; i < bgx_cnt; i++) {
+		err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
+					 PCI_DEVICE_ID_CAVIUM_BGX, i, &dev);
+		if (err)
+			debug("%s BGX%d device not found\n", __func__, i);
+	}
+	if (otx_is_soc(CN81XX)) {
+		err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
+					 PCI_DEVICE_ID_CAVIUM_RGX, 0, &dev);
+		if (err)
+			debug("%s RGX device not found\n", __func__);
+	}
+	err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
+				 PCI_DEVICE_ID_CAVIUM_NIC, 0, &dev);
+	if (err)
+		debug("NIC PF device not found\n");
+}
+
+/**
+ * Board late initialization routine.
+ */
+int board_late_init(void)
+{
+	char boardname[32];
+	char boardserial[150], boardrev[150];
+	bool save_env = false;
+	const char *str;
+
+	/*
+	 * Try to cleanup ethaddr env variables, this is needed
+	 * as with each boot, configuration of network interfaces can change.
+	 */
+	octeontx_cleanup_ethaddr();
+
+	snprintf(boardname, sizeof(boardname), "%s> ", fdt_get_board_model());
+	env_set("prompt", boardname);
+
+	set_working_fdt_addr(env_get_hex("fdtcontroladdr", fdt_base_addr));
+
+	str = fdt_get_board_revision();
+	if (str) {
+		snprintf(boardrev, sizeof(boardrev), "%s", str);
+		if (env_get("boardrev") &&
+		    strcmp(boardrev, env_get("boardrev")))
+			save_env = true;
+		env_set("boardrev", boardrev);
+	}
+
+	str = fdt_get_board_serial();
+	if (str) {
+		snprintf(boardserial, sizeof(boardserial), "%s", str);
+		if (env_get("serial#") &&
+		    strcmp(boardserial, env_get("serial#")))
+			save_env = true;
+		env_set("serial#", boardserial);
+	}
+
+	if (IS_ENABLED(CONFIG_NET_OCTEONTX))
+		board_late_probe_devices();
+
+	if (save_env)
+		env_save();
+
+	return 0;
+}
+
+/*
+ * Invoked before relocation, so limit to stack variables.
+ */
+int checkboard(void)
+{
+	printf("Board: %s\n", fdt_get_board_model());
+
+	return 0;
+}
diff --git a/roms/u-boot/board/Marvell/octeontx/smc.c b/roms/u-boot/board/Marvell/octeontx/smc.c
new file mode 100644
index 000000000..5eeba2358
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx/smc.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier:    GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <asm/global_data.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <asm/arch/smc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ssize_t smc_dram_size(unsigned int node)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = OCTEONTX_DRAM_SIZE;
+	regs.regs[1] = node;
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
diff --git a/roms/u-boot/board/Marvell/octeontx/soc-utils.c b/roms/u-boot/board/Marvell/octeontx/soc-utils.c
new file mode 100644
index 000000000..5fd5afd48
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx/soc-utils.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier:    GPL-2.0
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <dm.h>
+#include <dm/util.h>
+#include <errno.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/board.h>
+
+int read_platform(void)
+{
+	int plat = PLATFORM_HW;
+
+	const char *model = fdt_get_board_model();
+
+	if (model && !strncmp(model, "ASIM-", 5))
+		plat = PLATFORM_ASIM;
+	if (model && !strncmp(model, "EMUL-", 5))
+		plat = PLATFORM_EMULATOR;
+	return plat;
+}
+
+static inline u64 read_midr(void)
+{
+	u64 result;
+
+	asm ("mrs %[rd],MIDR_EL1" : [rd] "=r" (result));
+	return result;
+}
+
+u8 read_partnum(void)
+{
+	return ((read_midr() >> 4) & 0xFF);
+}
+
+const char *read_board_name(void)
+{
+	return fdt_get_board_model();
+}
+
+bool read_alt_pkg(void)
+{
+	return false;
+}
diff --git a/roms/u-boot/board/Marvell/octeontx2/Kconfig b/roms/u-boot/board/Marvell/octeontx2/Kconfig
new file mode 100644
index 000000000..99291d795
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx2/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_OCTEONTX2_95XX || TARGET_OCTEONTX2_96XX
+
+config SYS_VENDOR
+	string
+	default	"Marvell"
+
+config SYS_BOARD
+	string
+	default "octeontx2"
+
+config SYS_CONFIG_NAME
+	default "octeontx2_common"
+
+endif
diff --git a/roms/u-boot/board/Marvell/octeontx2/MAINTAINERS b/roms/u-boot/board/Marvell/octeontx2/MAINTAINERS
new file mode 100644
index 000000000..eec1d77dd
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx2/MAINTAINERS
@@ -0,0 +1,8 @@
+OCTEONTX2 BOARD
+M:	Aaron Williams <awilliams@marvell.com>
+S:	Maintained
+F:	board/Marvell/octeontx2/
+F:	include/configs/octeontx2_96xx.h
+F:	include/configs/octeontx2_95xx.h
+F:	configs/octeontx2_96xx_defconfig
+F:	configs/octeontx2_95xx_defconfig
diff --git a/roms/u-boot/board/Marvell/octeontx2/Makefile b/roms/u-boot/board/Marvell/octeontx2/Makefile
new file mode 100644
index 000000000..1f763b197
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx2/Makefile
@@ -0,0 +1,9 @@
+#/* SPDX-License-Identifier:    GPL-2.0
+# *
+# * Copyright (C) 2018 Marvell International Ltd.
+# *
+# * https://spdx.org/licenses
+# */
+
+obj-y	:= board.o smc.o soc-utils.o
+obj-$(CONFIG_OF_LIBFDT) += board-fdt.o
diff --git a/roms/u-boot/board/Marvell/octeontx2/board-fdt.c b/roms/u-boot/board/Marvell/octeontx2/board-fdt.c
new file mode 100644
index 000000000..a4771af4c
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx2/board-fdt.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier:    GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <errno.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <log.h>
+
+#include <linux/compiler.h>
+#include <linux/libfdt.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/smc.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int fdt_get_bdk_node(void)
+{
+	int node, ret;
+	const void *fdt = gd->fdt_blob;
+
+	if (!fdt) {
+		printf("ERROR: %s: no valid device tree found\n", __func__);
+		return 0;
+	}
+
+	ret = fdt_check_header(fdt);
+	if (ret < 0) {
+		printf("fdt: %s\n", fdt_strerror(ret));
+		return 0;
+	}
+
+	node = fdt_path_offset(fdt, "/cavium,bdk");
+	if (node < 0) {
+		printf("%s: /cavium,bdk is missing from device tree: %s\n",
+		       __func__, fdt_strerror(node));
+		return 0;
+	}
+	return node;
+}
+
+u64 fdt_get_board_mac_addr(void)
+{
+	int node, len = 16;
+	const char *str = NULL;
+	const void *fdt = gd->fdt_blob;
+	u64 mac_addr = 0;
+
+	node = fdt_get_bdk_node();
+	if (!node)
+		return mac_addr;
+	str = fdt_getprop(fdt, node, "BOARD-MAC-ADDRESS", &len);
+	if (str)
+		mac_addr = simple_strtol(str, NULL, 16);
+	return mac_addr;
+}
+
+int fdt_get_board_mac_cnt(void)
+{
+	int node, len = 16;
+	const char *str = NULL;
+	const void *fdt = gd->fdt_blob;
+	int mac_count = 0;
+
+	node = fdt_get_bdk_node();
+	if (!node)
+		return mac_count;
+	str = fdt_getprop(fdt, node, "BOARD-MAC-ADDRESS-NUM", &len);
+	if (str) {
+		mac_count = simple_strtol(str, NULL, 10);
+		if (!mac_count)
+			mac_count = simple_strtol(str, NULL, 16);
+		debug("fdt: MAC_NUM %d\n", mac_count);
+	} else {
+		printf("Error: cannot retrieve mac count prop from fdt\n");
+	}
+	str = fdt_getprop(gd->fdt_blob, node, "BOARD-MAC-ADDRESS-NUM-OVERRIDE",
+			  &len);
+	if (str) {
+		if (simple_strtol(str, NULL, 10) >= 0)
+			mac_count = simple_strtol(str, NULL, 10);
+		debug("fdt: MAC_NUM %d\n", mac_count);
+	} else {
+		printf("Error: cannot retrieve mac num override prop\n");
+	}
+	return mac_count;
+}
+
+const char *fdt_get_board_serial(void)
+{
+	const void *fdt = gd->fdt_blob;
+	int node, len = 64;
+	const char *str = NULL;
+
+	node = fdt_get_bdk_node();
+	if (!node)
+		return NULL;
+
+	str = fdt_getprop(fdt, node, "BOARD-SERIAL", &len);
+	if (!str)
+		printf("Error: cannot retrieve board serial from fdt\n");
+	return str;
+}
+
+const char *fdt_get_board_revision(void)
+{
+	const void *fdt = gd->fdt_blob;
+	int node, len = 64;
+	const char *str = NULL;
+
+	node = fdt_get_bdk_node();
+	if (!node)
+		return NULL;
+
+	str = fdt_getprop(fdt, node, "BOARD-REVISION", &len);
+	if (!str)
+		printf("Error: cannot retrieve board revision from fdt\n");
+	return str;
+}
+
+const char *fdt_get_board_model(void)
+{
+	int node, len = 16;
+	const char *str = NULL;
+	const void *fdt = gd->fdt_blob;
+
+	node = fdt_get_bdk_node();
+	if (!node)
+		return NULL;
+	str = fdt_getprop(fdt, node, "BOARD-MODEL", &len);
+	if (!str)
+		printf("Error: cannot retrieve board model from fdt\n");
+	return str;
+}
+
+int arch_fixup_memory_node(void *blob)
+{
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int nodeoff, node, ret, i;
+	const char *temp;
+
+	static const char * const
+		octeontx_brd_nodes[] = {"BOARD-MODEL",
+					"BOARD-SERIAL",
+					"BOARD-MAC-ADDRESS",
+					"BOARD-REVISION",
+					"BOARD-MAC-ADDRESS-NUM"
+					};
+	char nodes[ARRAY_SIZE(octeontx_brd_nodes)][32];
+
+	ret = fdt_check_header(blob);
+	if (ret < 0) {
+		printf("ERROR: %s\n", fdt_strerror(ret));
+		return ret;
+	}
+
+	if (blob) {
+		nodeoff = fdt_path_offset(blob, "/cavium,bdk");
+		if (nodeoff < 0) {
+			printf("ERROR: FDT BDK node not found\n");
+			return nodeoff;
+		}
+
+		/* Read properties in temporary variables */
+		for (i = 0; i < ARRAY_SIZE(octeontx_brd_nodes); i++) {
+			temp = fdt_getprop(blob, nodeoff,
+					   octeontx_brd_nodes[i], NULL);
+			strncpy(nodes[i], temp, sizeof(nodes[i]));
+		}
+
+		/* Delete cavium,bdk node */
+		ret = fdt_del_node(blob, nodeoff);
+		if (ret < 0) {
+			printf("WARNING : could not remove cavium, bdk node\n");
+			return ret;
+		}
+		debug("%s deleted 'cavium,bdk' node\n", __func__);
+		/*
+		 * Add a new node at root level which would have
+		 * necessary info
+		 */
+		node = fdt_add_subnode(blob, 0, "octeontx_brd");
+		if (node < 0) {
+			printf("Cannot create node octeontx_brd: %s\n",
+			       fdt_strerror(node));
+			return -EIO;
+		}
+
+		/* Populate properties in node */
+		for (i = 0; i < ARRAY_SIZE(octeontx_brd_nodes); i++) {
+			if (fdt_setprop_string(blob, node,
+					       octeontx_brd_nodes[i],
+					       nodes[i])) {
+				printf("Can't set %s\n", nodes[i]);
+				return -EIO;
+			}
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * Return the FDT base address that was passed by ATF
+ *
+ * @return	FDT base address received from ATF in x1 register
+ */
+void *board_fdt_blob_setup(void)
+{
+	return (void *)fdt_base_addr;
+}
diff --git a/roms/u-boot/board/Marvell/octeontx2/board.c b/roms/u-boot/board/Marvell/octeontx2/board.c
new file mode 100644
index 000000000..9b973a4ac
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx2/board.c
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier:    GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <command.h>
+#include <console.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/uclass-internal.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <net.h>
+#include <pci_ids.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/arch/smc.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/board.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void cleanup_env_ethaddr(void)
+{
+	char ename[32];
+
+	for (int i = 0; i < 20; i++) {
+		sprintf(ename, i ? "eth%daddr" : "ethaddr", i);
+		if (env_get(ename))
+			env_set(ename, NULL);
+	}
+}
+
+void octeontx2_board_get_mac_addr(u8 index, u8 *mac_addr)
+{
+	u64 tmp_mac, board_mac_addr = fdt_get_board_mac_addr();
+	static int board_mac_num;
+
+	board_mac_num = fdt_get_board_mac_cnt();
+	if ((!is_zero_ethaddr((u8 *)&board_mac_addr)) && board_mac_num) {
+		tmp_mac = board_mac_addr;
+		tmp_mac += index;
+		tmp_mac = swab64(tmp_mac) >> 16;
+		memcpy(mac_addr, (u8 *)&tmp_mac, ARP_HLEN);
+		board_mac_num--;
+	} else {
+		memset(mac_addr, 0, ARP_HLEN);
+	}
+	debug("%s mac %pM\n", __func__, mac_addr);
+}
+
+void board_quiesce_devices(void)
+{
+	struct uclass *uc_dev;
+	int ret;
+
+	/* Removes all RVU PF devices */
+	ret = uclass_get(UCLASS_ETH, &uc_dev);
+	if (uc_dev)
+		ret = uclass_destroy(uc_dev);
+	if (ret)
+		printf("couldn't remove rvu pf devices\n");
+
+	if (IS_ENABLED(CONFIG_OCTEONTX2_CGX_INTF)) {
+		/* Bring down all cgx lmac links */
+		cgx_intf_shutdown();
+	}
+
+	/* Removes all CGX and RVU AF devices */
+	ret = uclass_get(UCLASS_MISC, &uc_dev);
+	if (uc_dev)
+		ret = uclass_destroy(uc_dev);
+	if (ret)
+		printf("couldn't remove misc (cgx/rvu_af) devices\n");
+
+	/* SMC call - removes all LF<->PF mappings */
+	smc_disable_rvu_lfs(0);
+}
+
+int board_early_init_r(void)
+{
+	pci_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int timer_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = smc_dram_size(0);
+	gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
+
+	mem_map_fill();
+
+	return 0;
+}
+
+void board_late_probe_devices(void)
+{
+	struct udevice *dev;
+	int err, cgx_cnt = 3, i;
+
+	/* Probe MAC(CGX) and NIC AF devices before Network stack init */
+	for (i = 0; i < cgx_cnt; i++) {
+		err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
+					 PCI_DEVICE_ID_CAVIUM_CGX, i, &dev);
+		if (err)
+			debug("%s CGX%d device not found\n", __func__, i);
+	}
+	err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
+				 PCI_DEVICE_ID_CAVIUM_RVU_AF, 0, &dev);
+	if (err)
+		debug("NIC AF device not found\n");
+}
+
+/**
+ * Board late initialization routine.
+ */
+int board_late_init(void)
+{
+	char boardname[32];
+	char boardserial[150], boardrev[150];
+	long val;
+	bool save_env = false;
+	const char *str;
+
+	debug("%s()\n", __func__);
+
+	/*
+	 * Now that pci_init initializes env device.
+	 * Try to cleanup ethaddr env variables, this is needed
+	 * as with each boot, configuration of QLM can change.
+	 */
+	cleanup_env_ethaddr();
+
+	snprintf(boardname, sizeof(boardname), "%s> ", fdt_get_board_model());
+	env_set("prompt", boardname);
+	set_working_fdt_addr(env_get_hex("fdtcontroladdr", fdt_base_addr));
+
+	str = fdt_get_board_revision();
+	if (str) {
+		snprintf(boardrev, sizeof(boardrev), "%s", str);
+		if (env_get("boardrev") &&
+		    strcmp(boardrev, env_get("boardrev")))
+			save_env = true;
+		env_set("boardrev", boardrev);
+	}
+
+	str = fdt_get_board_serial();
+	if (str) {
+		snprintf(boardserial, sizeof(boardserial), "%s", str);
+		if (env_get("serial#") &&
+		    strcmp(boardserial, env_get("serial#")))
+			save_env = true;
+		env_set("serial#", boardserial);
+	}
+
+	val = env_get_hex("disable_ooo", 0);
+	smc_configure_ooo(val);
+
+	if (IS_ENABLED(CONFIG_NET_OCTEONTX2))
+		board_late_probe_devices();
+
+	if (save_env)
+		env_save();
+
+	return 0;
+}
+
+/*
+ * Invoked before relocation, so limit to stack variables.
+ */
+int checkboard(void)
+{
+	printf("Board: %s\n", fdt_get_board_model());
+
+	return 0;
+}
+
+void board_acquire_flash_arb(bool acquire)
+{
+	union cpc_boot_ownerx ownerx;
+
+	if (!acquire) {
+		ownerx.u = readl(CPC_BOOT_OWNERX(3));
+		ownerx.s.boot_req = 0;
+		writel(ownerx.u, CPC_BOOT_OWNERX(3));
+	} else {
+		ownerx.u = 0;
+		ownerx.s.boot_req = 1;
+		writel(ownerx.u, CPC_BOOT_OWNERX(3));
+		udelay(1);
+		do {
+			ownerx.u = readl(CPC_BOOT_OWNERX(3));
+		} while (ownerx.s.boot_wait);
+	}
+}
+
+int last_stage_init(void)
+{
+	(void)smc_flsf_fw_booted();
+	return 0;
+}
+
+static int do_go_uboot(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	typedef void __noreturn (*uboot_entry_t)(ulong, void *);
+	uboot_entry_t entry;
+	ulong addr;
+	void *fdt;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+	fdt = board_fdt_blob_setup();
+	entry = (uboot_entry_t)addr;
+	flush_cache((ulong)addr, 1 << 20);	/* 1MiB should be enough */
+	dcache_disable();
+
+	printf("## Starting U-Boot at %p (FDT at %p)...\n", entry, fdt);
+
+	entry(0, fdt);
+
+	return 0;
+}
+
+U_BOOT_CMD(go_uboot, 2, 0, do_go_uboot,
+	   "Start U-Boot from RAM (pass FDT via x1 register)",
+	   "");
diff --git a/roms/u-boot/board/Marvell/octeontx2/smc.c b/roms/u-boot/board/Marvell/octeontx2/smc.c
new file mode 100644
index 000000000..9e3169576
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx2/smc.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier:    GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <asm/arch/smc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ssize_t smc_dram_size(unsigned int node)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = OCTEONTX2_DRAM_SIZE;
+	regs.regs[1] = node;
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t smc_disable_rvu_lfs(unsigned int node)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = OCTEONTX2_DISABLE_RVU_LFS;
+	regs.regs[1] = node;
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t smc_configure_ooo(unsigned int val)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = OCTEONTX2_CONFIG_OOO;
+	regs.regs[1] = val;
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t smc_flsf_fw_booted(void)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = OCTEONTX2_FSAFE_PR_BOOT_SUCCESS;
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
diff --git a/roms/u-boot/board/Marvell/octeontx2/soc-utils.c b/roms/u-boot/board/Marvell/octeontx2/soc-utils.c
new file mode 100644
index 000000000..1cba7fb59
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx2/soc-utils.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier:    GPL-2.0
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/board.h>
+#include <dm/util.h>
+
+int read_platform(void)
+{
+	int plat = PLATFORM_HW;
+
+	const char *model = fdt_get_board_model();
+
+	if (model && !strncmp(model, "ASIM-", 5))
+		plat = PLATFORM_ASIM;
+	if (model && !strncmp(model, "EMUL-", 5))
+		plat = PLATFORM_EMULATOR;
+
+	return plat;
+}
+
+static inline u64 read_midr(void)
+{
+	u64 result;
+
+	asm ("mrs %[rd],MIDR_EL1" : [rd] "=r" (result));
+	return result;
+}
+
+u8 read_partnum(void)
+{
+	return ((read_midr() >> 4) & 0xFF);
+}
+
+const char *read_board_name(void)
+{
+	return fdt_get_board_model();
+}
+
diff --git a/roms/u-boot/board/Marvell/octeontx2_cn913x/MAINTAINERS b/roms/u-boot/board/Marvell/octeontx2_cn913x/MAINTAINERS
new file mode 100644
index 000000000..74c5fd16e
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx2_cn913x/MAINTAINERS
@@ -0,0 +1,6 @@
+OCTEONTX2_CN913x BOARD
+M:	Kostya Porotchkin <kostap@marvell.com>
+S:	Maintained
+F:	board/Marvell/octeontx2_cn913x/
+F:	configs/mvebu_crb_cn9130_defconfig
+F:	configs/mvebu_db_cn9130_defconfig
diff --git a/roms/u-boot/board/Marvell/octeontx2_cn913x/Makefile b/roms/u-boot/board/Marvell/octeontx2_cn913x/Makefile
new file mode 100644
index 000000000..8c6ffb932
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx2_cn913x/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+# Copyright (C) 2019 Marvell International Ltd.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= board.o
diff --git a/roms/u-boot/board/Marvell/octeontx2_cn913x/README b/roms/u-boot/board/Marvell/octeontx2_cn913x/README
new file mode 100644
index 000000000..3d0c8b31e
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx2_cn913x/README
@@ -0,0 +1,24 @@
+Not all board variants are represented with a specific defconfig in
+mainline U-Boot. Here a small documentation on how to generate U-Boot
+images for all other board variants, available via different dts
+files and defconfigs.
+
+Use a different dts than in the defconfig:
+
+make DEVICE_TREE=cn9131-db-B
+
+Use a different boot device (e.g. MMC or NAND instead of SPI NOR):
+
+For MMC, please make the following changes to the defconfig via
+e.g. "make menuconfig":
+Remove CONFIG_MVEBU_SPI_BOOT
+Select CONFIG_MVEBU_MMC_BOOT
+Remove CONFIG_ENV_IS_IN_SPI_FLASH
+Select CONFIG_ENV_IS_IN_MMC
+
+For NAND, please make the following changes to the defconfig via
+e.g. "make menuconfig":
+Remove CONFIG_MVEBU_SPI_BOOT
+Select CONFIG_MVEBU_NAND_BOOT
+Remove CONFIG_ENV_IS_IN_SPI_FLASH
+Select CONFIG_ENV_IS_IN_NAND
diff --git a/roms/u-boot/board/Marvell/octeontx2_cn913x/board.c b/roms/u-boot/board/Marvell/octeontx2_cn913x/board.c
new file mode 100644
index 000000000..953e9db9c
--- /dev/null
+++ b/roms/u-boot/board/Marvell/octeontx2_cn913x/board.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier:    GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <dm.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int soc_early_init_f(void)
+{
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	soc_early_init_f();
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
+		/* Check if any existing regulator should be turned down */
+		regulators_enable_boot_off(false);
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/board/Marvell/openrd/Kconfig b/roms/u-boot/board/Marvell/openrd/Kconfig
new file mode 100644
index 000000000..124b66da0
--- /dev/null
+++ b/roms/u-boot/board/Marvell/openrd/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OPENRD
+
+config SYS_BOARD
+	default "openrd"
+
+config SYS_VENDOR
+	default "Marvell"
+
+config SYS_CONFIG_NAME
+	default "openrd"
+
+endif
diff --git a/roms/u-boot/board/Marvell/openrd/MAINTAINERS b/roms/u-boot/board/Marvell/openrd/MAINTAINERS
new file mode 100644
index 000000000..8170452b4
--- /dev/null
+++ b/roms/u-boot/board/Marvell/openrd/MAINTAINERS
@@ -0,0 +1,8 @@
+OPENRD / OPENRD_CLIENT BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/Marvell/openrd/
+F:	include/configs/openrd.h
+F:	configs/openrd_base_defconfig
+F:	configs/openrd_client_defconfig
+F:	configs/openrd_ultimate_defconfig
diff --git a/roms/u-boot/board/Marvell/openrd/Makefile b/roms/u-boot/board/Marvell/openrd/Makefile
new file mode 100644
index 000000000..ecebb421f
--- /dev/null
+++ b/roms/u-boot/board/Marvell/openrd/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2009
+# Net Insight <www.netinsight.net>
+# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+#
+# Based on sheevaplug:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= openrd.o
diff --git a/roms/u-boot/board/Marvell/openrd/kwbimage.cfg b/roms/u-boot/board/Marvell/openrd/kwbimage.cfg
new file mode 100644
index 000000000..356fd46f9
--- /dev/null
+++ b/roms/u-boot/board/Marvell/openrd/kwbimage.cfg
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=x8
+# bit7-6:   11, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000042	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strength reduced
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00120012	#  DDR ODT Control (Low)
+# bit3-0:   0010, (read) M_ODT[0] is asserted during read from DRAM CS1
+# bit7-4:   0001, (read) M_ODT[1] is asserted during read from DRAM CS0
+# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
+# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+
+DATA 0xFFD0149C 0x0000E40f	# CPU ODT Control
+# bit3-0:    1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit11-10:    01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
+# bit13-12:    10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
+# bit14:        1, M_STARTBURST_IN ODT: Enabled
+# bit15:        1, DDR IO ODT Unit: Use ODT block
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/Marvell/openrd/openrd.c b/roms/u-boot/board/Marvell/openrd/openrd.c
new file mode 100644
index 000000000..f44ac3315
--- /dev/null
+++ b/roms/u-boot/board/Marvell/openrd/openrd.c
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.c:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "openrd.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(OPENRD_OE_VAL_LOW,
+			  OPENRD_OE_VAL_HIGH,
+			  OPENRD_OE_LOW, OPENRD_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD, /* Alt UART1_TXD */
+		MPP14_SD_D0,  /* Alt UART1_RXD */
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GPIO,
+		MPP29_TSMP9,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GPIO,   /* UART1 / SD sel */
+		MPP35_TDM_CH0_TX_QL,
+		MPP36_TDM_SPI_CS1,
+		MPP37_TDM_CH2_TX_QL,
+		MPP38_TDM_CH2_RX_QL,
+		MPP39_AUDIO_I2SBCLK,
+		MPP40_AUDIO_I2SDO,
+		MPP41_AUDIO_I2SLRC,
+		MPP42_AUDIO_I2SMCLK,
+		MPP43_AUDIO_I2SDI,
+		MPP44_AUDIO_EXTCLK,
+		MPP45_TDM_PCLK,
+		MPP46_TDM_FS,
+		MPP47_TDM_DRX,
+		MPP48_TDM_DTX,
+		MPP49_TDM_CH0_RX_QL,
+		0
+	};
+
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
+	gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
+#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
+	gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
+#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
+	gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
+#endif
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116/88E1121 PHY */
+void mv_phy_init(char *name)
+{
+	u16 reg;
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+		printf("Err..%s could not read PHY dev address\n", __func__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf(PHY_NO" Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+	mv_phy_init("egiga0");
+
+#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
+	/* Kirkwood ethernet driver is written with the assumption that in case
+	 * of multiple PHYs, their addresses are consecutive. But unfortunately
+	 * in case of OpenRD-Client, PHY addresses are not consecutive.*/
+	miiphy_write("egiga1", 0xEE, 0xEE, 24);
+#endif
+
+#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
+	defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
+	/* configure and initialize both PHY's */
+	mv_phy_init("egiga1");
+#endif
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/roms/u-boot/board/Marvell/openrd/openrd.h b/roms/u-boot/board/Marvell/openrd/openrd.h
new file mode 100644
index 000000000..ade8d2739
--- /dev/null
+++ b/roms/u-boot/board/Marvell/openrd/openrd.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef __OPENRD_BASE_H
+#define __OPENRD_BASE_H
+
+#define OPENRD_OE_LOW		(~(1<<28))        /* RS232 / RS485 */
+#define OPENRD_OE_HIGH		(~(1<<2))         /* SD / UART1 */
+#define OPENRD_OE_VAL_LOW		(0)       /* Sel RS232 */
+#define OPENRD_OE_VAL_HIGH		(1 << 2)  /* Sel SD */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __OPENRD_BASE_H */
diff --git a/roms/u-boot/board/Marvell/sheevaplug/Kconfig b/roms/u-boot/board/Marvell/sheevaplug/Kconfig
new file mode 100644
index 000000000..e5f928472
--- /dev/null
+++ b/roms/u-boot/board/Marvell/sheevaplug/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SHEEVAPLUG
+
+config SYS_BOARD
+	default "sheevaplug"
+
+config SYS_VENDOR
+	default "Marvell"
+
+config SYS_CONFIG_NAME
+	default "sheevaplug"
+
+endif
diff --git a/roms/u-boot/board/Marvell/sheevaplug/MAINTAINERS b/roms/u-boot/board/Marvell/sheevaplug/MAINTAINERS
new file mode 100644
index 000000000..2b0103d07
--- /dev/null
+++ b/roms/u-boot/board/Marvell/sheevaplug/MAINTAINERS
@@ -0,0 +1,6 @@
+SHEEVAPLUG BOARD
+M:	Prafulla Wadaskar <prafulla@marvell.com>
+S:	Maintained
+F:	board/Marvell/sheevaplug/
+F:	include/configs/sheevaplug.h
+F:	configs/sheevaplug_defconfig
diff --git a/roms/u-boot/board/Marvell/sheevaplug/Makefile b/roms/u-boot/board/Marvell/sheevaplug/Makefile
new file mode 100644
index 000000000..c39dd03e2
--- /dev/null
+++ b/roms/u-boot/board/Marvell/sheevaplug/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= sheevaplug.o
diff --git a/roms/u-boot/board/Marvell/sheevaplug/kwbimage.cfg b/roms/u-boot/board/Marvell/sheevaplug/kwbimage.cfg
new file mode 100644
index 000000000..f5206451d
--- /dev/null
+++ b/roms/u-boot/board/Marvell/sheevaplug/kwbimage.cfg
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Refer to doc/README.kwbimage for more details about how-to
+# configure and create kirkwood boot images.
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=x8
+# bit7-6:   11, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/Marvell/sheevaplug/sheevaplug.c b/roms/u-boot/board/Marvell/sheevaplug/sheevaplug.c
new file mode 100644
index 000000000..0cc7f2b39
--- /dev/null
+++ b/roms/u-boot/board/Marvell/sheevaplug/sheevaplug.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "sheevaplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
+			  SHEEVAPLUG_OE_VAL_HIGH,
+			  SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_UART0_RTS,
+		MPP9_UART0_CTS,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GPIO,
+		MPP21_GPIO,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_TSMP9,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__FUNCTION__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/roms/u-boot/board/Marvell/sheevaplug/sheevaplug.h b/roms/u-boot/board/Marvell/sheevaplug/sheevaplug.h
new file mode 100644
index 000000000..e026c1b53
--- /dev/null
+++ b/roms/u-boot/board/Marvell/sheevaplug/sheevaplug.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef __SHEEVAPLUG_H
+#define __SHEEVAPLUG_H
+
+#define SHEEVAPLUG_OE_LOW		(~(0))
+#define SHEEVAPLUG_OE_HIGH		(~(0))
+#define SHEEVAPLUG_OE_VAL_LOW		(1 << 29)	/* USB_PWEN low */
+#define SHEEVAPLUG_OE_VAL_HIGH		(1 << 17)	/* LED pin high */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __SHEEVAPLUG_H */
diff --git a/roms/u-boot/board/Seagate/dockstar/Kconfig b/roms/u-boot/board/Seagate/dockstar/Kconfig
new file mode 100644
index 000000000..b50cd3b7f
--- /dev/null
+++ b/roms/u-boot/board/Seagate/dockstar/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DOCKSTAR
+
+config SYS_BOARD
+	default "dockstar"
+
+config SYS_VENDOR
+	default "Seagate"
+
+config SYS_CONFIG_NAME
+	default "dockstar"
+
+endif
diff --git a/roms/u-boot/board/Seagate/dockstar/MAINTAINERS b/roms/u-boot/board/Seagate/dockstar/MAINTAINERS
new file mode 100644
index 000000000..f259e58ae
--- /dev/null
+++ b/roms/u-boot/board/Seagate/dockstar/MAINTAINERS
@@ -0,0 +1,6 @@
+DOCKSTAR BOARD
+M:	Eric Cooper <ecc@cmu.edu>
+S:	Maintained
+F:	board/Seagate/dockstar/
+F:	include/configs/dockstar.h
+F:	configs/dockstar_defconfig
diff --git a/roms/u-boot/board/Seagate/dockstar/Makefile b/roms/u-boot/board/Seagate/dockstar/Makefile
new file mode 100644
index 000000000..7fda3f42c
--- /dev/null
+++ b/roms/u-boot/board/Seagate/dockstar/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/Makefile originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+
+obj-y	:= dockstar.o
diff --git a/roms/u-boot/board/Seagate/dockstar/dockstar.c b/roms/u-boot/board/Seagate/dockstar/dockstar.c
new file mode 100644
index 000000000..380e37be5
--- /dev/null
+++ b/roms/u-boot/board/Seagate/dockstar/dockstar.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.c originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/cpu.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include "dockstar.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW,
+			  DOCKSTAR_OE_VAL_HIGH,
+			  DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_UART0_RTS,
+		MPP9_UART0_CTS,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GPIO,
+		MPP21_GPIO,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_TSMP9,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__FUNCTION__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#define GREEN_LED	(1 << 14)
+#define ORANGE_LED	(1 << 15)
+#define BOTH_LEDS	(GREEN_LED | ORANGE_LED)
+#define NEITHER_LED	0
+
+static void set_leds(u32 leds, u32 blinking)
+{
+	struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+	u32 oe = readl(&r->oe) | BOTH_LEDS;
+	writel(oe & ~leds, &r->oe);	/* active low */
+	u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
+	writel(bl | blinking, &r->blink_en);
+}
+
+void show_boot_progress(int val)
+{
+	switch (val) {
+	case BOOTSTAGE_ID_RUN_OS:		/* booting Linux */
+		set_leds(BOTH_LEDS, NEITHER_LED);
+		break;
+	case BOOTSTAGE_ID_NET_ETH_START:	/* Ethernet initialization */
+		set_leds(GREEN_LED, GREEN_LED);
+		break;
+	default:
+		if (val < 0)	/* error */
+			set_leds(ORANGE_LED, ORANGE_LED);
+		break;
+	}
+}
diff --git a/roms/u-boot/board/Seagate/dockstar/dockstar.h b/roms/u-boot/board/Seagate/dockstar/dockstar.h
new file mode 100644
index 000000000..cbb164447
--- /dev/null
+++ b/roms/u-boot/board/Seagate/dockstar/dockstar.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.h originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ */
+
+#ifndef __DOCKSTAR_H
+#define __DOCKSTAR_H
+
+#define DOCKSTAR_OE_LOW		(~(0))
+#define DOCKSTAR_OE_HIGH		(~(0))
+#define DOCKSTAR_OE_VAL_LOW		(1 << 29)	/* USB_PWEN low */
+#define DOCKSTAR_OE_VAL_HIGH		(1 << 17)	/* LED pin high */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __DOCKSTAR_H */
diff --git a/roms/u-boot/board/Seagate/dockstar/kwbimage.cfg b/roms/u-boot/board/Seagate/dockstar/kwbimage.cfg
new file mode 100644
index 000000000..65183d4ef
--- /dev/null
+++ b/roms/u-boot/board/Seagate/dockstar/kwbimage.cfg
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/kwbimage.cfg originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000d	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/Seagate/goflexhome/Kconfig b/roms/u-boot/board/Seagate/goflexhome/Kconfig
new file mode 100644
index 000000000..0cbeaf7ca
--- /dev/null
+++ b/roms/u-boot/board/Seagate/goflexhome/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GOFLEXHOME
+
+config SYS_BOARD
+	default "goflexhome"
+
+config SYS_VENDOR
+	default "Seagate"
+
+config SYS_CONFIG_NAME
+	default "goflexhome"
+
+endif
diff --git a/roms/u-boot/board/Seagate/goflexhome/MAINTAINERS b/roms/u-boot/board/Seagate/goflexhome/MAINTAINERS
new file mode 100644
index 000000000..6d6a1ff4e
--- /dev/null
+++ b/roms/u-boot/board/Seagate/goflexhome/MAINTAINERS
@@ -0,0 +1,6 @@
+GOFLEXHOME BOARD
+M:	Suriyan Ramasami <suriyan.r@gmail.com>
+S:	Maintained
+F:	board/Seagate/goflexhome/
+F:	include/configs/goflexhome.h
+F:	configs/goflexhome_defconfig
diff --git a/roms/u-boot/board/Seagate/goflexhome/Makefile b/roms/u-boot/board/Seagate/goflexhome/Makefile
new file mode 100644
index 000000000..d6e6b976a
--- /dev/null
+++ b/roms/u-boot/board/Seagate/goflexhome/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+#
+# Based on dockstar/Makefile originally written by
+# Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/Makefile originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+
+obj-y	:= goflexhome.o
diff --git a/roms/u-boot/board/Seagate/goflexhome/goflexhome.c b/roms/u-boot/board/Seagate/goflexhome/goflexhome.c
new file mode 100644
index 000000000..4c19fa719
--- /dev/null
+++ b/roms/u-boot/board/Seagate/goflexhome/goflexhome.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+ *
+ * Based on dockstar.c originally written by
+ * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.c originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_UART0_RTS,
+		MPP9_UART0_CTS,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GPIO,
+		MPP21_GPIO,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_TSMP9,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW,
+			  GOFLEXHOME_OE_VAL_HIGH,
+			  GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+		       __func__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#define GREEN_LED	(1 << 14)
+#define ORANGE_LED	(1 << 15)
+#define BOTH_LEDS	(GREEN_LED | ORANGE_LED)
+#define NEITHER_LED	0
+
+static void set_leds(u32 leds, u32 blinking)
+{
+	struct kwgpio_registers *r;
+	u32 oe;
+	u32 bl;
+
+	r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+	oe = readl(&r->oe) | BOTH_LEDS;
+	writel(oe & ~leds, &r->oe);	/* active low */
+	bl = readl(&r->blink_en) & ~BOTH_LEDS;
+	writel(bl | blinking, &r->blink_en);
+}
+
+void show_boot_progress(int val)
+{
+	switch (val) {
+	case BOOTSTAGE_ID_RUN_OS:		/* booting Linux */
+		set_leds(BOTH_LEDS, NEITHER_LED);
+		break;
+	case BOOTSTAGE_ID_NET_ETH_START:	/* Ethernet initialization */
+		set_leds(GREEN_LED, GREEN_LED);
+		break;
+	default:
+		if (val < 0)	/* error */
+			set_leds(ORANGE_LED, ORANGE_LED);
+		break;
+	}
+}
diff --git a/roms/u-boot/board/Seagate/goflexhome/kwbimage.cfg b/roms/u-boot/board/Seagate/goflexhome/kwbimage.cfg
new file mode 100644
index 000000000..8c8193147
--- /dev/null
+++ b/roms/u-boot/board/Seagate/goflexhome/kwbimage.cfg
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+#
+# Based on dockstar/kwbimage.cfg originally written by
+# Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/kwbimage.cfg originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000d	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/Seagate/nas220/Kconfig b/roms/u-boot/board/Seagate/nas220/Kconfig
new file mode 100644
index 000000000..0fa529cde
--- /dev/null
+++ b/roms/u-boot/board/Seagate/nas220/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NAS220
+
+config SYS_BOARD
+	default "nas220"
+
+config SYS_VENDOR
+	default "Seagate"
+
+config SYS_CONFIG_NAME
+	default "nas220"
+
+endif
diff --git a/roms/u-boot/board/Seagate/nas220/MAINTAINERS b/roms/u-boot/board/Seagate/nas220/MAINTAINERS
new file mode 100644
index 000000000..f2df7ea64
--- /dev/null
+++ b/roms/u-boot/board/Seagate/nas220/MAINTAINERS
@@ -0,0 +1,6 @@
+NAS220 BOARD
+M:	Evgeni Dobrev <evgeni@studio-punkt.com>
+S:	Maintained
+F:	board/Seagate/nas220/
+F:	include/configs/nas220.h
+F:	configs/nas220_defconfig
diff --git a/roms/u-boot/board/Seagate/nas220/Makefile b/roms/u-boot/board/Seagate/nas220/Makefile
new file mode 100644
index 000000000..9de73e6f5
--- /dev/null
+++ b/roms/u-boot/board/Seagate/nas220/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014  Evgeni Dobrev <evgeni@studio-punkt.com>
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y	:= nas220.o
diff --git a/roms/u-boot/board/Seagate/nas220/kwbimage.cfg b/roms/u-boot/board/Seagate/nas220/kwbimage.cfg
new file mode 100644
index 000000000..dbbfb9c02
--- /dev/null
+++ b/roms/u-boot/board/Seagate/nas220/kwbimage.cfg
@@ -0,0 +1,151 @@
+#
+# Copyright (C) 2014  Evgeni Dobrev <evgeni@studio-punkt.com>
+#
+# Based on sheevaplug/kwbimage.cfg originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0200
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618	# DDR Configuration register
+# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x35143000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012227	# DDR Timing (Low) (active cycles value +1)
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000819	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+
+DATA 0xFFD01410 0x0000000d	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000632	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  0
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x00000000      # CS[1]n Base address to 0x0
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+DATA 0xffd01620 0x00465000
+
+# End of Header extension
+DATA 0x0 0x0
+
diff --git a/roms/u-boot/board/Seagate/nas220/nas220.c b/roms/u-boot/board/Seagate/nas220/nas220.c
new file mode 100644
index 000000000..cd2bbdad1
--- /dev/null
+++ b/roms/u-boot/board/Seagate/nas220/nas220.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014  Evgeni Dobrev <evgeni@studio-punkt.com>
+ *
+ * Based on sheevaplug.c originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 */
+	mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH,
+			  NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_SPI_SCn,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_GPO,
+		MPP13_GPIO,
+		MPP14_GPIO,
+		MPP15_SATA0_ACTn,
+		MPP16_SATA1_ACTn,
+		MPP17_SATA0_PRESENTn,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GPIO,
+		MPP21_GPIO,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_RD88F6192_NAS;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+		printf("Err..%s could not read PHY dev address\n", __func__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/roms/u-boot/board/Synology/common/Makefile b/roms/u-boot/board/Synology/common/Makefile
new file mode 100644
index 000000000..62354cc2e
--- /dev/null
+++ b/roms/u-boot/board/Synology/common/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 Phil Sutter <phil@nwl.cc>
+
+obj-y	+= legacy.o
diff --git a/roms/u-boot/board/Synology/common/legacy.c b/roms/u-boot/board/Synology/common/legacy.c
new file mode 100644
index 000000000..3c89e92ae
--- /dev/null
+++ b/roms/u-boot/board/Synology/common/legacy.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021
+ * Walter Schweizer <swwa@users.sourceforge.net>
+ * Phil Sutter <phil@nwl.cc>
+ */
+
+#include <config.h>
+#include <vsprintf.h>
+#include <env.h>
+#include <net.h>
+#include <asm/setup.h>
+
+#include "legacy.h"
+
+static unsigned int syno_board_id(void)
+{
+	switch (CONFIG_MACH_TYPE) {
+	case 527:
+		return SYNO_DS109_ID;
+	case 3036:
+		return SYNO_AXP_4BAY_2BAY;
+	default:
+		return 0;
+	}
+}
+
+static unsigned int usb_port_modes(void)
+{
+	unsigned int i, ret = 0;
+	char var[32], *val;
+
+	for (i = 0; i < USBPORT_MAX; i++) {
+		snprintf(var, 32, "usb%dMode", i);
+		val = env_get(var);
+
+		if (!val || strcasecmp(val, "host"))
+			continue;
+
+		ret |= 1 << i;
+	}
+	return ret;
+}
+
+/* Support old kernels */
+void setup_board_tags(struct tag **in_params)
+{
+	struct tag_mv_uboot *t;
+	struct tag *params;
+	int i;
+
+	debug("Synology board tags...\n");
+
+	params = *in_params;
+	t = (struct tag_mv_uboot *)&params->u;
+
+	t->uboot_version = VER_NUM | syno_board_id();
+	t->tclk = CONFIG_SYS_TCLK;
+	t->sysclk = CONFIG_SYS_TCLK * 2;
+	t->isusbhost = usb_port_modes();
+
+	for (i = 0; i < ETHADDR_MAX; i++) {
+		char addrvar[16], mtuvar[16];
+
+		sprintf(addrvar, i ? "eth%daddr" : "ethaddr", i);
+		sprintf(mtuvar, i ? "eth%dmtu" : "ethmtu", i);
+
+		eth_env_get_enetaddr(addrvar, t->macaddr[i]);
+		t->mtu[i] = env_get_ulong(mtuvar, 10, 0);
+	}
+
+	params->hdr.tag = ATAG_MV_UBOOT;
+	params->hdr.size = tag_size(tag_mv_uboot);
+	params = tag_next(params);
+	*in_params = params;
+}
diff --git a/roms/u-boot/board/Synology/common/legacy.h b/roms/u-boot/board/Synology/common/legacy.h
new file mode 100644
index 000000000..0a814324d
--- /dev/null
+++ b/roms/u-boot/board/Synology/common/legacy.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2021
+ * Walter Schweizer <swwa@users.sourceforge.net>
+ * Phil Sutter <phil@nwl.cc>
+ */
+
+#ifndef __SYNO_LEGACY_H
+#define __SYNO_LEGACY_H
+
+/* Marvell uboot parameters */
+#define ATAG_MV_UBOOT 0x41000403
+#define VER_NUM       0x03040400 /* 3.4.4 */
+
+#define BOARD_ID_BASE 0x0
+#define SYNO_DS109_ID (BOARD_ID_BASE + 0x15)
+#define SYNO_AXP_4BAY_2BAY (0xf + 1)
+
+#define ETHADDR_MAX	4
+#define USBPORT_MAX	3
+
+struct tag_mv_uboot {
+	u32 uboot_version;
+	u32 tclk;
+	u32 sysclk;
+	u32 isusbhost;
+	u8 macaddr[ETHADDR_MAX][ETH_ALEN];
+	u16 mtu[ETHADDR_MAX];
+	u32 fw_image_base;
+	u32 fw_image_size;
+};
+
+#endif /* __SYNO_LEGACY_H */
diff --git a/roms/u-boot/board/Synology/ds109/Kconfig b/roms/u-boot/board/Synology/ds109/Kconfig
new file mode 100644
index 000000000..a7c75ae36
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds109/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DS109
+
+config SYS_BOARD
+	default "ds109"
+
+config SYS_VENDOR
+	default "Synology"
+
+config SYS_CONFIG_NAME
+	default "ds109"
+
+endif
diff --git a/roms/u-boot/board/Synology/ds109/MAINTAINERS b/roms/u-boot/board/Synology/ds109/MAINTAINERS
new file mode 100644
index 000000000..8783fdb1f
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds109/MAINTAINERS
@@ -0,0 +1,6 @@
+DS109 BOARD
+M:	Walter Schweizer <swwa@users.sourceforge.net>
+S:	Maintained
+F:	board/Synology/ds109
+F:	configs/ds109_defconfig
+F:	include/configs/ds109.h
diff --git a/roms/u-boot/board/Synology/ds109/Makefile b/roms/u-boot/board/Synology/ds109/Makefile
new file mode 100644
index 000000000..9d103a61b
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds109/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= ds109.o
diff --git a/roms/u-boot/board/Synology/ds109/ds109.c b/roms/u-boot/board/Synology/ds109/ds109.c
new file mode 100644
index 000000000..3914faaf3
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds109/ds109.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/setup.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <linux/delay.h>
+#include "ds109.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(DS109_OE_VAL_LOW,
+			  DS109_OE_VAL_HIGH,
+			  DS109_OE_LOW, DS109_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,		/* SPI Flash */
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP4_GPIO,
+		MPP5_GPO,
+		MPP6_SYSRST_OUTn,	/* Reset signal */
+		MPP7_GPO,
+		MPP8_TW_SDA,		/* I2C */
+		MPP9_TW_SCK,		/* I2C */
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_GPO,
+		MPP13_UART1_TXD,
+		MPP14_UART1_RXD,
+		MPP15_GPIO,
+		MPP16_GPIO,
+		MPP17_GPIO,
+		MPP18_GPO,
+		MPP19_GPO,
+		MPP20_SATA1_ACTn,
+		MPP21_SATA0_ACTn,
+		MPP22_GPIO,		/* HDD2 FAIL LED */
+		MPP23_GPIO,		/* HDD1 FAIL LED */
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GPIO,
+		MPP31_GPIO,		/* HDD2 */
+		MPP32_GPIO,		/* FAN A */
+		MPP33_GPIO,		/* FAN B */
+		MPP34_GPIO,		/* FAN C */
+		MPP35_GPIO,		/* FAN SENSE */
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+/* Synology reset uses UART */
+#include <ns16550.h>
+#define SOFTWARE_SHUTDOWN   0x31
+#define SOFTWARE_REBOOT     0x43
+#define CONFIG_SYS_NS16550_COM2		KW_UART1_BASE
+void reset_misc(void)
+{
+	int b_d;
+	printf("Synology reset...");
+	udelay(50000);
+
+	b_d = ns16550_calc_divisor((struct ns16550 *)CONFIG_SYS_NS16550_COM2,
+				   CONFIG_SYS_NS16550_CLK, 9600);
+	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM2, b_d);
+	ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM2,
+		     SOFTWARE_REBOOT);
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+		printf("Error: 88E1116 could not read PHY dev address\n");
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/roms/u-boot/board/Synology/ds109/ds109.h b/roms/u-boot/board/Synology/ds109/ds109.h
new file mode 100644
index 000000000..0cf05257c
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds109/ds109.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ */
+
+#ifndef __DS109_H
+#define __DS109_H
+
+#define DS109_OE_LOW			(0)
+#define DS109_OE_HIGH			(0)
+#define DS109_OE_VAL_LOW		((1 << 22)|(1 << 23))
+#define DS109_OE_VAL_HIGH		((1 << 1)|1)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_MAC_CTRL2_REG		21
+
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __DS109_H */
diff --git a/roms/u-boot/board/Synology/ds109/kwbimage.cfg b/roms/u-boot/board/Synology/ds109/kwbimage.cfg
new file mode 100644
index 000000000..8f6e70513
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds109/kwbimage.cfg
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2011
+# Jason Cooper <u-boot@lakedaemon.net>
+#
+# Based on work by:
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+DATA 0xFFD20134 0xbbbbbbbb
+DATA 0xFFD20138 0x00bbbbbb
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x39543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000833	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000d	#  DDR Address Control
+# bit1-0:   01, Cs0width=x8
+# bit3-2:   10, Cs0size=1Gb
+# bit5-4:   01, Cs1width=x8
+# bit7-6:   10, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000042	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F1FF	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+
+DATA 0xFFD01510 0x20000000	# CS[2]n Base address to 256Mb
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD01518 0x30000000	# CS[3]n Base address to 256Mb
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x003C0000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000F80F	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/Synology/ds109/openocd.cfg b/roms/u-boot/board/Synology/ds109/openocd.cfg
new file mode 100644
index 000000000..baa512aef
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds109/openocd.cfg
@@ -0,0 +1,115 @@
+# Synology DS109
+
+interface ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x000b
+ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
+
+adapter_khz 2000
+
+# length of reset signal: [ms]
+adapter_nsrst_assert_width 1000
+
+# don't talk to JTAG after reset for: [ms]
+adapter_nsrst_delay 200
+
+source [find target/feroceon.cfg]
+
+reset_config trst_and_srst srst_nogate
+
+proc ds109_init { } {
+
+	# We need to assert DBGRQ while holding nSRST down.
+	# However DBGACK will be set only when nSRST is released.
+	# Furthermore, the JTAG interface doesn't respond at all when
+	# the CPU is in the WFI (wait for interrupts) state, so it is
+	# possible that initial tap examination failed.  So let's
+	# re-examine the target again here when nSRST is asserted which
+	# should then succeed.
+	jtag_reset 0 1
+	feroceon.cpu arp_examine
+	halt 0
+	jtag_reset 0 0
+	wait_halt
+	#reset run
+	#soft_reset_halt
+
+	arm mcr 15 0 0 1 0 0x00052078
+
+	mww 0xD00100e0 0x1b1b1b9b ;#
+	mww 0xD0020134 0xbbbbbbbb ;#
+	mww 0xD0020138 0x00bbbbbb ;#
+	mww 0xD0001400 0x43000C30 ;#  DDR SDRAM Configuration Register
+	mww 0xD0001404 0x39743000 ;#  Dunit Control Low Register
+	mww 0xD0001408 0x22125551 ;#  DDR SDRAM Timing (Low) Register
+	mww 0xD000140C 0x00000833 ;#  DDR SDRAM Timing (High) Register
+	mww 0xD0001410 0x0000000d ;#  DDR SDRAM Address Control Register
+	mww 0xD0001414 0x00000000 ;#  DDR SDRAM Open Pages Control Register
+	mww 0xD0001418 0x00000000 ;#  DDR SDRAM Operation Register
+	mww 0xD000141C 0x00000C62 ;#  DDR SDRAM Mode Register
+	mww 0xD0001420 0x00000042 ;#  DDR SDRAM Extended Mode Register
+	mww 0xD0001424 0x0000F1FF ;#  Dunit Control High Register
+	mww 0xD0001428 0x00085520 ;#  Dunit Control High Register
+	mww 0xD000147c 0x00008552 ;#  Dunit Control High Register
+	mww 0xD0001500 0x00000000 ;#
+	mww 0xD0001504 0x07FFFFF1 ;#  CS0n Size Register
+	mww 0xD0001508 0x10000000 ;#  CS1n Base Register
+	mww 0xD000150C 0x00000000 ;#  CS1n Size Register
+	mww 0xD0001510 0x20000000 ;#
+	mww 0xD0001514 0x00000000 ;#  CS2n Size Register
+	mww 0xD000151C 0x00000000 ;#  CS3n Size Register
+	mww 0xD0001494 0x003C0000 ;#  DDR2 SDRAM ODT Control (Low) Register
+	mww 0xD0001498 0x00000000 ;#  DDR2 SDRAM ODT Control (High) REgister
+	mww 0xD000149C 0x0000F80F ;#  DDR2 Dunit ODT Control Register
+	mww 0xD0001480 0x00000001 ;#  DDR SDRAM Initialization Control Register
+	mww 0xD0020204 0x00000000 ;#  Main IRQ Interrupt Mask Register
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+
+	mww 0xD0010000 0x01111111 ;#  MPP  0 to 7
+	mww 0xD0010004 0x11113322 ;#  MPP  8 to 15
+	mww 0xD0010008 0x00001111 ;#  MPP 16 to 23
+}
+
+proc ds109_load { } {
+	# load u-Boot into RAM and execute it
+	ds109_init
+	load_image u-boot.bin 0x00600000 bin
+	resume 0x00600000
+}
diff --git a/roms/u-boot/board/Synology/ds414/Kconfig b/roms/u-boot/board/Synology/ds414/Kconfig
new file mode 100644
index 000000000..4d3085255
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds414/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DS414
+
+config SYS_BOARD
+	default "ds414"
+
+config SYS_VENDOR
+	default "Synology"
+
+config SYS_CONFIG_NAME
+	default "ds414"
+
+endif
diff --git a/roms/u-boot/board/Synology/ds414/MAINTAINERS b/roms/u-boot/board/Synology/ds414/MAINTAINERS
new file mode 100644
index 000000000..502cbd775
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds414/MAINTAINERS
@@ -0,0 +1,6 @@
+DS414 BOARD
+M:	Phil Sutter <phil@nwl.cc>
+S:	Maintained
+F:	board/Synology/ds414/
+F:	include/configs/ds414.h
+F:	configs/ds414_defconfig
diff --git a/roms/u-boot/board/Synology/ds414/Makefile b/roms/u-boot/board/Synology/ds414/Makefile
new file mode 100644
index 000000000..b1d018eff
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds414/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+
+obj-y	+= ds414.o
+ifndef CONFIG_SPL_BUILD
+obj-y	+= cmd_syno.o
+endif
diff --git a/roms/u-boot/board/Synology/ds414/cmd_syno.c b/roms/u-boot/board/Synology/ds414/cmd_syno.c
new file mode 100644
index 000000000..a62658a2e
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds414/cmd_syno.c
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Commands to deal with Synology specifics.
+ *
+ * Copyright (C) 2015  Phil Sutter <phil@nwl.cc>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <div64.h>
+#include <env.h>
+#include <net.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <linux/mtd/mtd.h>
+
+#include <asm/io.h>
+#include "../drivers/ddr/marvell/axp/ddr3_init.h"
+
+#include "cmd_syno.h"
+
+int do_syno_populate(int argc, char *const argv[])
+{
+	unsigned int bus = CONFIG_SF_DEFAULT_BUS;
+	unsigned int cs = CONFIG_SF_DEFAULT_CS;
+	unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
+	unsigned int mode = CONFIG_SF_DEFAULT_MODE;
+	struct spi_flash *flash;
+	unsigned long addr = 0x80000; /* XXX: parameterize this? */
+	loff_t offset = 0x007d0000;
+	loff_t len = 0x00010000;
+	char *buf, *bufp;
+	char var[128];
+	char val[128];
+	int ret, n;
+
+	/* XXX: arg parsing to select flash here? */
+
+	flash = spi_flash_probe(bus, cs, speed, mode);
+	if (!flash) {
+		printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
+		return 1;
+	}
+
+	buf = map_physmem(addr, len, MAP_WRBACK);
+	if (!buf) {
+		puts("Failed to map physical memory\n");
+		return 1;
+	}
+
+	ret = spi_flash_read(flash, offset, len, buf);
+	if (ret) {
+		puts("Failed to read from SPI flash\n");
+		goto out_unmap;
+	}
+
+	for (n = 0; n < SYNO_ETHADDR_MAX; n++) {
+		char ethaddr[ETH_ALEN];
+		int i, sum = 0;
+		unsigned char csum = 0;
+
+		for (i = 0, bufp = buf + n * 7; i < ETH_ALEN; i++) {
+			sum += bufp[i];
+			csum += bufp[i];
+			ethaddr[i] = bufp[i];
+		}
+		if (!sum)		/* MAC address empty */
+			continue;
+		if (csum != bufp[i]) {	/* seventh byte is checksum value */
+			printf("Invalid MAC address for interface %d!\n", n);
+			continue;
+		}
+		if (n == 0)
+			sprintf(var, "ethaddr");
+		else
+			sprintf(var, "eth%daddr", n);
+		snprintf(val, sizeof(val) - 1,
+		         "%02x:%02x:%02x:%02x:%02x:%02x",
+		         ethaddr[0], ethaddr[1], ethaddr[2],
+			 ethaddr[3], ethaddr[4], ethaddr[5]);
+		printf("parsed %s = %s\n", var, val);
+		env_set(var, val);
+	}
+	if (!strncmp(buf + 32, SYNO_SN_TAG, strlen(SYNO_SN_TAG))) {
+		char *snp, *csump;
+		int csum = 0;
+		unsigned long c;
+
+		snp = bufp = buf + 32 + strlen(SYNO_SN_TAG);
+		for (n = 0; bufp[n] && bufp[n] != ','; n++)
+			csum += bufp[n];
+		bufp[n] = '\0';
+
+		/* should come right after, but you never know */
+		bufp = strstr(bufp + n + 1, SYNO_CHKSUM_TAG);
+		if (!bufp) {
+			printf("Serial number checksum tag missing!\n");
+			goto out_unmap;
+		}
+
+		csump = bufp += strlen(SYNO_CHKSUM_TAG);
+		for (n = 0; bufp[n] && bufp[n] != ','; n++)
+			;
+		bufp[n] = '\0';
+
+		if (strict_strtoul(csump, 10, &c) || c != csum) {
+			puts("Invalid serial number found!\n");
+			ret = 1;
+			goto out_unmap;
+		}
+		printf("parsed SN = %s\n", snp);
+		env_set("SN", snp);
+	} else {	/* old style format */
+		unsigned char csum = 0;
+
+		for (n = 0, bufp = buf + 32; n < 10; n++)
+			csum += bufp[n];
+
+		if (csum != bufp[n]) {
+			puts("Invalid serial number found!\n");
+			ret = 1;
+			goto out_unmap;
+		}
+		bufp[n] = '\0';
+		printf("parsed SN = %s\n", buf + 32);
+		env_set("SN", buf + 32);
+	}
+out_unmap:
+	unmap_physmem(buf, len);
+	return ret;
+}
+
+/* map bit position to function in POWER_MNG_CTRL_REG */
+static const char * const pwr_mng_bit_func[] = {
+	"audio",
+	"ge3", "ge2", "ge1", "ge0",
+	"pcie00", "pcie01", "pcie02", "pcie03",
+	"pcie10", "pcie11", "pcie12", "pcie13",
+	"bp",
+	"sata0_link", "sata0_core",
+	"lcd",
+	"sdio",
+	"usb0", "usb1", "usb2",
+	"idma", "xor0", "crypto",
+	NULL,
+	"tdm",
+	"pcie20", "pcie30",
+	"xor1",
+	"sata1_link", "sata1_core",
+	NULL,
+};
+
+static int do_syno_clk_gate(int argc, char *const argv[])
+{
+	u32 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
+	const char *func, *state;
+	int i, val;
+
+	if (argc < 2)
+		return -1;
+
+	if (!strcmp(argv[1], "get")) {
+		puts("Clock Gating:\n");
+		for (i = 0; i < 32; i++) {
+			func = pwr_mng_bit_func[i];
+			if (!func)
+				continue;
+			state = pwr_mng_ctrl_reg & (1 << i) ?  "ON" : "OFF";
+			printf("%s:\t\t%s\n", func, state);
+		}
+		return 0;
+	}
+	if (argc < 4)
+		return -1;
+	if (!strcmp(argv[1], "set")) {
+		func = argv[2];
+		state = argv[3];
+		for (i = 0; i < 32; i++) {
+			if (!pwr_mng_bit_func[i])
+				continue;
+			if (!strcmp(func, pwr_mng_bit_func[i]))
+				break;
+		}
+		if (i == 32) {
+			printf("Error: name '%s' not known\n", func);
+			return -1;
+		}
+		val = state[0] != '0';
+		pwr_mng_ctrl_reg |= (val << i);
+		pwr_mng_ctrl_reg &= ~(!val << i);
+		reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
+	}
+	return 0;
+}
+
+static int do_syno(struct cmd_tbl *cmdtp, int flag, int argc,
+		   char *const argv[])
+{
+	const char *cmd;
+	int ret = 0;
+
+	if (argc < 2)
+		goto usage;
+
+	cmd = argv[1];
+	--argc;
+	++argv;
+
+	if (!strcmp(cmd, "populate_env"))
+		ret = do_syno_populate(argc, argv);
+	else if (!strcmp(cmd, "clk_gate"))
+		ret = do_syno_clk_gate(argc, argv);
+
+	if (ret != -1)
+		return ret;
+usage:
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+	syno, 5, 1, do_syno,
+	"Synology specific commands",
+	"populate_env                 - Read vendor data from SPI flash into environment\n"
+	"clk_gate (get|set name 1|0)  - Manage clock gating\n"
+);
diff --git a/roms/u-boot/board/Synology/ds414/cmd_syno.h b/roms/u-boot/board/Synology/ds414/cmd_syno.h
new file mode 100644
index 000000000..42e435c80
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds414/cmd_syno.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Commands to deal with Synology specifics.
+ *
+ * Copyright (C) 2021  Phil Sutter <phil@nwl.cc>
+ */
+
+#ifndef _CMD_SYNO_H
+#define _CMD_SYNO_H
+
+#define SYNO_ETHADDR_MAX	4
+#define SYNO_SN_TAG		"SN="
+#define SYNO_CHKSUM_TAG		"CHK="
+
+int do_syno_populate(int argc, char *const argv[]);
+
+#endif /* _CMD_SYNO_H */
diff --git a/roms/u-boot/board/Synology/ds414/ds414.c b/roms/u-boot/board/Synology/ds414/ds414.c
new file mode 100644
index 000000000..abe6f9eb5
--- /dev/null
+++ b/roms/u-boot/board/Synology/ds414/ds414.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/bitops.h>
+#include <linux/mbus.h>
+
+#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
+
+#include "cmd_syno.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */
+
+#define DS414_GPP_OUT_VAL_LOW		(BIT(25) | BIT(30))
+#define DS414_GPP_OUT_VAL_MID		(BIT(10) | BIT(15))
+#define DS414_GPP_OUT_VAL_HIGH		(0)
+
+#define DS414_GPP_OUT_POL_LOW		(0)
+#define DS414_GPP_OUT_POL_MID		(0)
+#define DS414_GPP_OUT_POL_HIGH		(0)
+
+#define DS414_GPP_OUT_ENA_LOW		(~(BIT(25) | BIT(30)))
+#define DS414_GPP_OUT_ENA_MID		(~(BIT(10) | BIT(12) | \
+					   BIT(13) | BIT(14) | BIT(15)))
+#define DS414_GPP_OUT_ENA_HIGH		(~0)
+
+static const u32 ds414_mpp_control[] = {
+	0x11111111,
+	0x22221111,
+	0x22222222,
+	0x00000000,
+	0x11110000,
+	0x00004000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+
+/* DDR3 static MC configuration */
+
+/* 1G_v1 (4x2Gbits) adapted by DS414 */
+MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
+	{0x00001400, 0x73014A28},	/*DDR SDRAM Configuration Register */
+	{0x00001404, 0x30000800},	/*Dunit Control Low Register */
+	{0x00001408, 0x44148887},	/*DDR SDRAM Timing (Low) Register */
+	{0x0000140C, 0x3AD83FEA},	/*DDR SDRAM Timing (High) Register */
+
+	{0x00001410, 0x14000000},	/*DDR SDRAM Address Control Register */
+
+	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
+	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
+	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
+	{0x00001424, 0x0000F3FF},	/*Dunit Control High Register */
+	{0x00001428, 0x000F8830},	/*Dunit Control High Register */
+	{0x0000142C, 0x054C36F4},	/*Dunit Control High Register */
+	{0x0000147C, 0x0000C671},
+
+	{0x000014a0, 0x00000001},
+	{0x000014a8, 0x00000100},	/*2:1 */
+	{0x00020220, 0x00000006},
+
+	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
+	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
+	{0x0000149C, 0x00000001},	/*DDR Dunit ODT Control Register */
+
+	{0x000014C0, 0x192424C9},	/* DRAM address and Control Driving Strenght  */
+	{0x000014C4, 0x0AAA24C9},	/* DRAM Data and DQS Driving Strenght  */
+
+	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/
+	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
+
+	{0x0001504, 0x3FFFFFE1},	/* CS0 Size */
+	{0x000150C, 0x00000000},	/* CS1 Size */
+	{0x0001514, 0x00000000},	/* CS2 Size */
+	{0x000151C, 0x00000000},	/* CS3 Size */
+
+	{0x00001538, 0x00000009},	/*Read Data Sample Delays Register */
+	{0x0000153C, 0x00000009},	/*Read Data Ready Delay Register */
+
+	{0x000015D0, 0x00000650},	/*MR0 */
+	{0x000015D4, 0x00000044},	/*MR1 */
+	{0x000015D8, 0x00000010},	/*MR2 */
+	{0x000015DC, 0x00000000},	/*MR3 */
+
+	{0x000015E4, 0x00203c18},	/*ZQC Configuration Register */
+	{0x000015EC, 0xF800A225},	/*DDR PHY */
+
+	{0x0, 0x0}
+};
+
+MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = {
+	{"ds414_1333-667",   0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1,  NULL},
+};
+
+extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
+
+MV_BIN_SERDES_CFG ds414_serdes_cfg[] = {
+	{ MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
+	  { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
+	    PEX_BUS_DISABLED },
+	  0x0040, serdes_change_m_phy
+	}
+};
+
+MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
+{
+	return &ds414_ddr_modes[0];
+}
+
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
+{
+	return &ds414_serdes_cfg[0];
+}
+
+u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+	return 0xf;	/* All PEX ports support PCIe Gen2 */
+}
+
+int board_early_init_f(void)
+{
+	int i;
+
+	/* Set GPP Out value */
+	reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW);
+	reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID);
+	reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH);
+
+	/* set GPP polarity */
+	reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW);
+	reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID);
+	reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH);
+
+	/* Set GPP Out Enable */
+	reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW);
+	reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID);
+	reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH);
+
+	for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++)
+		reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	u32 pwr_mng_ctrl_reg;
+
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/* Gate unused clocks
+	 *
+	 * Note: Disabling unused PCIe lanes will hang PCI bus scan.
+	 *       Once this is resolved, bits 10-12, 26 and 27 can be
+	 *       unset here as well.
+	 */
+	pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
+	pwr_mng_ctrl_reg &= ~(BIT(0));				/* Audio */
+	pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2));			/* GE3, GE2 */
+	pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15));		/* SATA0 link and core */
+	pwr_mng_ctrl_reg &= ~(BIT(16));				/* LCD */
+	pwr_mng_ctrl_reg &= ~(BIT(17));				/* SDIO */
+	pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20));		/* USB1 and USB2 */
+	pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30));		/* SATA1 link and core */
+	reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	if (!env_get("ethaddr")) {
+		puts("Incomplete environment, populating from SPI flash\n");
+		do_syno_populate(0, NULL);
+	}
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: DS414\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/abilis/tb100/Kconfig b/roms/u-boot/board/abilis/tb100/Kconfig
new file mode 100644
index 000000000..904a92c7a
--- /dev/null
+++ b/roms/u-boot/board/abilis/tb100/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TB100
+
+config SYS_CPU
+	default "arc700"
+
+config SYS_BOARD
+	default "tb100"
+
+config SYS_VENDOR
+	default "abilis"
+
+config SYS_CONFIG_NAME
+	default "tb100"
+
+endif
diff --git a/roms/u-boot/board/abilis/tb100/MAINTAINERS b/roms/u-boot/board/abilis/tb100/MAINTAINERS
new file mode 100644
index 000000000..f08c3fe35
--- /dev/null
+++ b/roms/u-boot/board/abilis/tb100/MAINTAINERS
@@ -0,0 +1,6 @@
+TB100 BOARD
+M:	Alexey Brodkin <abrodkin@synopsys.com>
+S:	Maintained
+F:	board/abilis/tb100/
+F:	include/configs/tb100.h
+F:	configs/tb100_defconfig
diff --git a/roms/u-boot/board/abilis/tb100/Makefile b/roms/u-boot/board/abilis/tb100/Makefile
new file mode 100644
index 000000000..43cc777be
--- /dev/null
+++ b/roms/u-boot/board/abilis/tb100/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2014 Pierrick Hascoet, Abilis Systems
+
+obj-y	+= tb100.o
diff --git a/roms/u-boot/board/abilis/tb100/config.mk b/roms/u-boot/board/abilis/tb100/config.mk
new file mode 100644
index 000000000..9e8dee49b
--- /dev/null
+++ b/roms/u-boot/board/abilis/tb100/config.mk
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Synopsys, Inc. All rights reserved.
+
+PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape
diff --git a/roms/u-boot/board/abilis/tb100/tb100.c b/roms/u-boot/board/abilis/tb100/tb100.c
new file mode 100644
index 000000000..89e73225a
--- /dev/null
+++ b/roms/u-boot/board/abilis/tb100/tb100.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 Pierrick Hascoet, Abilis Systems
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+void reset_cpu(void)
+{
+#define CRM_SWRESET	0xff101044
+	writel(0x1, (void *)CRM_SWRESET);
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	if (designware_initialize(ETH0_BASE_ADDRESS, 0) >= 0)
+		return 1;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/advantech/Kconfig b/roms/u-boot/board/advantech/Kconfig
new file mode 100644
index 000000000..a8d49691f
--- /dev/null
+++ b/roms/u-boot/board/advantech/Kconfig
@@ -0,0 +1,28 @@
+if VENDOR_ADVANTECH
+
+choice
+	prompt "Mainboard model"
+	optional
+
+config TARGET_SOM_DB5800_SOM_6867
+	bool "Advantech SOM-DB5800 & SOM-6867"
+	help
+	  Advantech SOM-DB5800 COM Express development board with SOM-6867
+	  installed.
+
+	  SOM-6867 is a COM Express Type 6 Compact Module with either an Intel
+	  Atom E3845 or Celeron N2920 processor.
+
+	  SOM-DB5800 is a COM Express Development board with:
+	    10/100/1000 Ethernet
+	    PCIe slots
+	    4x USB ports
+	    HDMI/DisplayPort/DVI, LVDS, VGA
+	    SATA ports
+	    ALC892 HD Audio Codec
+
+endchoice
+
+source "board/advantech/som-db5800-som-6867/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/advantech/imx8qm_rom7720_a1/Kconfig b/roms/u-boot/board/advantech/imx8qm_rom7720_a1/Kconfig
new file mode 100644
index 000000000..cf3869ed9
--- /dev/null
+++ b/roms/u-boot/board/advantech/imx8qm_rom7720_a1/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_IMX8QM_ROM7720_A1
+
+config SYS_BOARD
+	default "imx8qm_rom7720_a1"
+
+config SYS_VENDOR
+	default "advantech"
+
+config SYS_CONFIG_NAME
+	default "imx8qm_rom7720"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/advantech/imx8qm_rom7720_a1/MAINTAINERS b/roms/u-boot/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
new file mode 100644
index 000000000..58a4d253c
--- /dev/null
+++ b/roms/u-boot/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX8QM ROM 7720 a1 BOARD
+M:	Oliver Graute <oliver.graute@kococonnector.com>
+S:	Maintained
+F:	board/advantech/imx8qm_rom7720_a1/
+F:	arch/arm/dts/imx8qm-rom7720-a1.dts
+F:	include/configs/imx8qm_rom7720.h
+F:	configs/imx8qm_rom7720_a1_4G_defconfig
diff --git a/roms/u-boot/board/advantech/imx8qm_rom7720_a1/Makefile b/roms/u-boot/board/advantech/imx8qm_rom7720_a1/Makefile
new file mode 100644
index 000000000..51c5de251
--- /dev/null
+++ b/roms/u-boot/board/advantech/imx8qm_rom7720_a1/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += imx8qm_rom7720_a1.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/roms/u-boot/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/roms/u-boot/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c
new file mode 100644
index 000000000..ace18b2d6
--- /dev/null
+++ b/roms/u-boot/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier:	GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	int ret;
+
+	/* Set UART0 clock root to 80 MHz */
+	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+	/* This is needed to because Kernel do not Power Up DC_0 */
+	sc_pm_set_resource_power_mode(-1, SC_R_DC_0, SC_PM_PW_MODE_ON);
+	sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+#ifdef CONFIG_FEC_ENABLE_MAX7322
+	u8 value;
+
+	/* This is needed to drive the pads to 1.8V instead of 1.5V */
+	i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS);
+
+	if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) {
+		/* Write 0x1 to enable O0 output, this device has no addr */
+		/* hence addr length is 0 */
+		value = 0x1;
+		if (dm_i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1))
+			printf("MAX7322 write failed\n");
+	} else {
+		printf("MAX7322 Not found\n");
+	}
+	mdelay(1);
+#endif
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: ROM-7720-A1 4GB\n");
+
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Power up base board */
+	sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
+
+	return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+	/* TODO */
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "ROM-7720-A1");
+	env_set("board_rev", "iMX8QM");
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/advantech/imx8qm_rom7720_a1/imximage.cfg b/roms/u-boot/board/advantech/imx8qm_rom7720_a1/imximage.cfg
new file mode 100644
index 000000000..e324c7ca3
--- /dev/null
+++ b/roms/u-boot/board/advantech/imx8qm_rom7720_a1/imximage.cfg
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier:	GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QM */
+SOC_TYPE IMX8QM
+/* Append seco container image */
+APPEND mx8qm-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qm-val-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/roms/u-boot/board/advantech/imx8qm_rom7720_a1/spl.c b/roms/u-boot/board/advantech/imx8qm_rom7720_a1/spl.c
new file mode 100644
index 000000000..8493bb015
--- /dev/null
+++ b/roms/u-boot/board/advantech/imx8qm_rom7720_a1/spl.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier:	GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ */
+#include <common.h>
+#include <dm.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <fsl_esdhc.h>
+#include <asm/global_data.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ESDHC_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ESDHC_CLK_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define FSPI_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define I2C_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 22)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 12)
+
+static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR, 0, 4},
+};
+
+static iomux_cfg_t emmc0[] = {
+	SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+static iomux_cfg_t usdhc2_sd[] = {
+	SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_WP   | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 * mmc2                    USDHC3
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
+			if (ret != SC_ERR_NONE)
+				return ret;
+
+			imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
+			init_clk_usdhc(0);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
+			if (ret != SC_ERR_NONE)
+				return ret;
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
+			if (ret != SC_ERR_NONE)
+				return ret;
+
+			imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
+			init_clk_usdhc(2);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			gpio_request(USDHC2_CD_GPIO, "sd2_cd");
+			gpio_direction_input(USDHC2_CD_GPIO);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return 0;
+		}
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+#endif /* CONFIG_FSL_ESDHC */
+
+void spl_board_init(void)
+{
+#if defined(CONFIG_SPL_SPI_SUPPORT)
+	if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
+		if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
+			puts("Warning: failed to initialize FSPI0\n");
+		}
+	}
+#endif
+
+	puts("Normal Boot\n");
+}
+
+void spl_board_prepare_for_boot(void)
+{
+#if defined(CONFIG_SPL_SPI_SUPPORT)
+	if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
+		if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
+			puts("Warning: failed to turn off FSPI0\n");
+		}
+	}
+#endif
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/advantech/som-db5800-som-6867/.gitignore b/roms/u-boot/board/advantech/som-db5800-som-6867/.gitignore
new file mode 100644
index 000000000..6eb8a5481
--- /dev/null
+++ b/roms/u-boot/board/advantech/som-db5800-som-6867/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/roms/u-boot/board/advantech/som-db5800-som-6867/Kconfig b/roms/u-boot/board/advantech/som-db5800-som-6867/Kconfig
new file mode 100644
index 000000000..35d58fcd0
--- /dev/null
+++ b/roms/u-boot/board/advantech/som-db5800-som-6867/Kconfig
@@ -0,0 +1,29 @@
+if TARGET_SOM_DB5800_SOM_6867
+
+config SYS_BOARD
+	default "som-db5800-som-6867"
+
+config SYS_VENDOR
+	default "advantech"
+
+config SYS_SOC
+	default "baytrail"
+
+config SYS_CONFIG_NAME
+	default "som-db5800-som-6867"
+
+config SYS_TEXT_BASE
+	default 0xfff00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
+	select SPI_FLASH_MACRONIX
+
+config PCIE_ECAM_BASE
+	default 0xe0000000
+
+endif
diff --git a/roms/u-boot/board/advantech/som-db5800-som-6867/MAINTAINERS b/roms/u-boot/board/advantech/som-db5800-som-6867/MAINTAINERS
new file mode 100644
index 000000000..92989bfba
--- /dev/null
+++ b/roms/u-boot/board/advantech/som-db5800-som-6867/MAINTAINERS
@@ -0,0 +1,7 @@
+Advantech SOM-DB5800-SOM-6867
+M:	George McCollister <george.mccollister@gmail.com>
+S:	Maintained
+F:	board/advantech/som-db5800-som-6867
+F:	include/configs/som-db5800-som-6867.h
+F:	configs/som-db5800-som-6867_defconfig
+F:	arch/x86/dts/baytrail_som-db5800-som-6867.dts
diff --git a/roms/u-boot/board/advantech/som-db5800-som-6867/Makefile b/roms/u-boot/board/advantech/som-db5800-som-6867/Makefile
new file mode 100644
index 000000000..7975547f4
--- /dev/null
+++ b/roms/u-boot/board/advantech/som-db5800-som-6867/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Google, Inc
+
+obj-y	+= som-db5800-som-6867.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/roms/u-boot/board/advantech/som-db5800-som-6867/acpi/mainboard.asl b/roms/u-boot/board/advantech/som-db5800-som-6867/acpi/mainboard.asl
new file mode 100644
index 000000000..beb9d93ec
--- /dev/null
+++ b/roms/u-boot/board/advantech/som-db5800-som-6867/acpi/mainboard.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/roms/u-boot/board/advantech/som-db5800-som-6867/dsdt.asl b/roms/u-boot/board/advantech/som-db5800-som-6867/dsdt.asl
new file mode 100644
index 000000000..d2297ef59
--- /dev/null
+++ b/roms/u-boot/board/advantech/som-db5800-som-6867/dsdt.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/roms/u-boot/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/roms/u-boot/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
new file mode 100644
index 000000000..8499fc541
--- /dev/null
+++ b/roms/u-boot/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2016 George McCollister <george.mccollister@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/fsp1/fsp_support.h>
+
+/* ALC262 Verb Table - 10EC0262 */
+static const u32 verb_table_data13[] = {
+	/* Pin Complex (NID 0x11) */
+	0x01171cf0,
+	0x01171d11,
+	0x01171e11,
+	0x01171f41,
+	/* Pin Complex (NID 0x12) */
+	0x01271cf0,
+	0x01271d11,
+	0x01271e11,
+	0x01271f41,
+	/* Pin Complex (NID 0x14) */
+	0x01471c10,
+	0x01471d40,
+	0x01471e01,
+	0x01471f01,
+	/* Pin Complex (NID 0x15) */
+	0x01571cf0,
+	0x01571d11,
+	0x01571e11,
+	0x01571f41,
+	/* Pin Complex (NID 0x16) */
+	0x01671cf0,
+	0x01671d11,
+	0x01671e11,
+	0x01671f41,
+	/* Pin Complex (NID 0x18) */
+	0x01871c20,
+	0x01871d98,
+	0x01871ea1,
+	0x01871f01,
+	/* Pin Complex (NID 0x19) */
+	0x01971c21,
+	0x01971d98,
+	0x01971ea1,
+	0x01971f02,
+	/* Pin Complex (NID 0x1A) */
+	0x01a71c2f,
+	0x01a71d30,
+	0x01a71e81,
+	0x01a71f01,
+	/* Pin Complex */
+	0x01b71c1f,
+	0x01b71d40,
+	0x01b71e21,
+	0x01b71f02,
+	/* Pin Complex */
+	0x01c71cf0,
+	0x01c71d11,
+	0x01c71e11,
+	0x01c71f41,
+	/* Pin Complex */
+	0x01d71c01,
+	0x01d71dc6,
+	0x01d71e14,
+	0x01d71f40,
+	/* Pin Complex */
+	0x01e71cf0,
+	0x01e71d11,
+	0x01e71e11,
+	0x01e71f41,
+	/* Pin Complex */
+	0x01f71cf0,
+	0x01f71d11,
+	0x01f71e11,
+	0x01f71f41,
+};
+
+/*
+ * This needs to be in ROM since if we put it in CAR, FSP init loses it when
+ * it drops CAR.
+ *
+ * VerbTable: (RealTek ALC262)
+ * Revision ID = 0xFF, support all steps
+ * Codec Verb Table For AZALIA
+ * Codec Address: CAd value (0/1/2)
+ * Codec Vendor: 0x10EC0262
+ */
+static const struct azalia_verb_table azalia_verb_table[] = {
+	{
+		{
+			0x10ec0262,
+			0x0000,
+			0xff,
+			0x01,
+			0x000b,
+			0x0002,
+		},
+		verb_table_data13
+	}
+};
+
+static const struct azalia_config azalia_config = {
+	.pme_enable = 1,
+	.docking_supported = 1,
+	.docking_attached = 0,
+	.hdmi_codec_enable = 1,
+	.azalia_v_ci_enable = 1,
+	.rsvdbits = 0,
+	.verb_table_num = 1,
+	.verb_table = azalia_verb_table,
+	.reset_wait_timer_ms = 300
+};
+
+void update_fsp_azalia_configs(const struct azalia_config **azalia)
+{
+	*azalia = &azalia_config;
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * The FSP enables the BayTrail internal legacy UART (again).
+	 * Disable it again, so that the one on the EC can be used.
+	 */
+	setup_internal_uart(0);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFKW/Kconfig b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/Kconfig
new file mode 100644
index 000000000..5c2609b7f
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SBx81LIFKW
+
+config SYS_BOARD
+       default "SBx81LIFKW"
+
+config SYS_VENDOR
+       default "alliedtelesis"
+
+config SYS_CONFIG_NAME
+       default "SBx81LIFKW"
+
+endif
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFKW/MAINTAINERS b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/MAINTAINERS
new file mode 100644
index 000000000..31ccec0e9
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/MAINTAINERS
@@ -0,0 +1,7 @@
+SBx81LIFKW BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/alliedtelesis/SBx81LIFKW/
+F:	include/configs/SBx81LIFKW
+F:	configs/SBx81LIFKW_defconfig
+F:	arch/arm/dts/kirkwood-atl-sbx81lifkw.dts
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFKW/Makefile b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/Makefile
new file mode 100644
index 000000000..806020ed8
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010, 2018
+# Allied Telesis <www.alliedtelesis.com>
+#
+
+obj-y	+= sbx81lifkw.o
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg
new file mode 100644
index 000000000..9726f15e2
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2018 Allied Telesis
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+DATA 0xffd100e0 0x1b1b1b1b
+DATA 0xffd20134 0xffffffff
+DATA 0xffd20138 0x009fffff
+DATA 0xffd20154 0x00000000
+DATA 0xffd2014c 0x00000000
+DATA 0xffd20148 0x00000001
+
+# Dram initalization for 1 x x16
+#  DDR II Micron part number MT47H64M16HR-3
+#  MClk 333MHz, Size 128MB, ECC disable
+#
+DATA 0xffd01400 0x43000618
+DATA 0xffd01404 0x35143000
+DATA 0xffd01408 0x11012227
+DATA 0xffd0140c 0x00000819
+DATA 0xffd01410 0x0000000d
+DATA 0xffd01414 0x00000000
+DATA 0xffd01418 0x00000000
+DATA 0xffd0141c 0x00000632
+DATA 0xffd01420 0x00000040
+DATA 0xffd01424 0x0000f07f
+DATA 0xffd01500 0x00000000	# SDRAM CS[0] Base address at 0x00000000
+DATA 0xffd01504 0x07FFFFF1	# SDRAM CS[0] Size 128MiB
+DATA 0xffd01508 0x10000000
+DATA 0xffd0150c 0x00FFFFF4	# SDRAM CS[1] Size, window disabled
+DATA 0xffd01514 0x00FFFFF8	# SDRAM CS[2] Size, window disabled
+DATA 0xffd0151c 0x00FFFFFC	# SDRAM CS[3] Size, window disabled
+DATA 0xffd01494 0x00030000
+DATA 0xffd01498 0x00000000
+DATA 0xffd0149c 0x0000e803
+DATA 0xffd01480 0x00000001
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c
new file mode 100644
index 000000000..d8b9fdfe3
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010, 2018
+ * Allied Telesis <www.alliedtelesis.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <status_led.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+/* Note: GPIO differences between specific boards
+ *
+ * We're trying to avoid having multiple build targets for all the Kirkwood
+ * based boards one area where things tend to differ is GPIO usage. For the
+ * most part the GPIOs driven by the bootloader are similar enough in function
+ * that there is no harm in driving them.
+ *
+ *         XZ4  XS6     XS16  GS24A         GT40   GP24A         GT24A
+ * GPIO39  -    INT(<)  NC    MUX_RST_N(>)  NC     POE_DIS_N(>)  NC
+ */
+
+#define SBX81LIFKW_OE_LOW	~(BIT(31) | BIT(30) | BIT(28) | BIT(27) | \
+				  BIT(18) | BIT(17) | BIT(13) | BIT(12) | \
+				  BIT(10))
+#define SBX81LIFKW_OE_HIGH	~(BIT(0) | BIT(1) | BIT(7))
+#define SBX81LIFKW_OE_VAL_LOW	 (BIT(31) | BIT(30) | BIT(28) | BIT(27))
+#define SBX81LIFKW_OE_VAL_HIGH	 (BIT(0) | BIT(1))
+
+#define MV88E6097_RESET		27
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct led {
+	u32 reg;
+	u32 value;
+	u32 mask;
+};
+
+struct led amber_solid = {
+	MVEBU_GPIO0_BASE,
+	BIT(10),
+	BIT(18) | BIT(10)
+};
+
+struct led green_solid = {
+	MVEBU_GPIO0_BASE,
+	BIT(18) | BIT(10),
+	BIT(18) | BIT(10)
+};
+
+struct led amber_flash = {
+	MVEBU_GPIO0_BASE,
+	0,
+	BIT(18) | BIT(10)
+};
+
+struct led green_flash = {
+	MVEBU_GPIO0_BASE,
+	BIT(18),
+	BIT(18) | BIT(10)
+};
+
+static void status_led_set(struct led *led)
+{
+	clrsetbits_le32(led->reg, led->mask, led->value);
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(SBX81LIFKW_OE_VAL_LOW,
+			  SBX81LIFKW_OE_VAL_HIGH,
+			  SBX81LIFKW_OE_LOW, SBX81LIFKW_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP4_UART0_RXD,
+		MPP5_UART0_TXD,
+		MPP6_SYSRST_OUTn,
+		MPP7_PEX_RST_OUTn,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_GPO,
+		MPP11_GPIO,
+		MPP12_GPO,
+		MPP13_GPIO,
+		MPP14_GPIO,
+		MPP15_UART0_RTS,
+		MPP16_UART0_CTS,
+		MPP17_GPIO,
+		MPP18_GPO,
+		MPP19_GPO,
+		MPP20_GPIO,
+		MPP21_GPIO,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Power-down unused subsystems. The required
+	 * subsystems are:
+	 *
+	 *  GE0         b0
+	 *  PEX0 PHY    b1
+	 *  PEX0.0      b2
+	 *  TSU         b5
+	 *  SDRAM       b6
+	 *  RUNIT       b7
+	 */
+	writel((BIT(0) | BIT(1) | BIT(2) |
+		BIT(5) | BIT(6) | BIT(7)),
+		KW_CPU_REG_BASE + 0x1c);
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	status_led_set(&amber_solid);
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* automatically defined by kirkwood config.h */
+void reset_phy(void)
+{
+}
+#endif
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+	/* Ensure the 88e6097 gets at least 10ms Reset
+	 */
+	kw_gpio_set_value(MV88E6097_RESET, 0);
+	mdelay(20);
+	kw_gpio_set_value(MV88E6097_RESET, 1);
+	mdelay(20);
+
+	phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	status_led_set(&green_flash);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/Kconfig b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/Kconfig
new file mode 100644
index 000000000..524c29008
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SBx81LIFXCAT
+
+config SYS_BOARD
+       default "SBx81LIFXCAT"
+
+config SYS_VENDOR
+       default "alliedtelesis"
+
+config SYS_CONFIG_NAME
+       default "SBx81LIFXCAT"
+
+endif
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS
new file mode 100644
index 000000000..6b722ded2
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS
@@ -0,0 +1,7 @@
+SBx81LIFXCAT BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/alliedtelesis/SBx81LIFXCAT/
+F:	include/configs/SBx81LIFXCAT
+F:	configs/SBx81LIFXCAT_defconfig
+F:	arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/Makefile b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/Makefile
new file mode 100644
index 000000000..f21c8ef9d
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010, 2018
+# Allied Telesis <www.alliedtelesis.com>
+#
+
+obj-y	+= sbx81lifxcat.o
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg
new file mode 100644
index 000000000..53d4812f3
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2018 Allied Telesis
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+DATA 0xffd100e0 0x1b1b1b1b
+DATA 0xffd20134 0xffffffff
+DATA 0xffd20138 0x009fffff
+DATA 0xffd20154 0x00000000
+DATA 0xffd2014c 0x00000000
+DATA 0xffd20148 0x00000001
+
+# Dram initalization for 1 x x16
+#  DDR II Micron part number MT47H64M16HR-3
+#  MClk 333MHz, Size 128MB, ECC disable
+#
+DATA 0xffd01400 0x43000618
+DATA 0xffd01404 0x38543000
+DATA 0xffd01408 0x23125441
+DATA 0xffd0140c 0x00000832
+DATA 0xffd01410 0x0000000D
+DATA 0xffd01414 0x00000000
+DATA 0xffd01418 0x00000000
+DATA 0xffd0141c 0x00000652
+DATA 0xffd01420 0x00000042
+DATA 0xffd01424 0x0000F0FF
+DATA 0xffd01428 0x00074410
+DATA 0xffd0147C 0x00007441
+DATA 0xffd01500 0x00000000	# SDRAM CS[0] Base address at 0x00000000
+DATA 0xffd01504 0x07FFFFF1	# SDRAM CS[0] Size 128MiB
+DATA 0xffd01508 0x10000000
+DATA 0xffd0150c 0x00FFFFF4	# SDRAM CS[1] Size, window disabled
+DATA 0xffd01514 0x00FFFFF8	# SDRAM CS[2] Size, window disabled
+DATA 0xffd0151c 0x00FFFFFC	# SDRAM CS[3] Size, window disabled
+DATA 0xffd01494 0x84210000
+DATA 0xffd01498 0x00000000
+DATA 0xffd0149c 0x0000F80F
+DATA 0xffd01480 0x00000001
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c
new file mode 100644
index 000000000..52b8eba92
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010, 2018
+ * Allied Telesis <www.alliedtelesis.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <led.h>
+#include <asm/global_data.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#define SBX81LIFXCAT_OE_LOW		(~0)
+#define SBX81LIFXCAT_OE_HIGH		(~BIT(11))
+#define SBX81LIFXCAT_OE_VAL_LOW		(0)
+#define SBX81LIFXCAT_OE_VAL_HIGH	(BIT(11))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(SBX81LIFXCAT_OE_VAL_LOW,
+			  SBX81LIFXCAT_OE_VAL_HIGH,
+			  SBX81LIFXCAT_OE_LOW, SBX81LIFXCAT_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_GPO,
+		MPP13_UART1_TXD,
+		MPP14_UART1_RXD,
+		MPP15_GPIO,
+		MPP16_GPIO,
+		MPP17_GPIO,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GE1_8,
+		MPP29_GE1_9,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* automatically defined by kirkwood config.h */
+void reset_phy(void)
+{
+}
+#endif
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+	phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = led_get_by_label("status:ledp", &dev);
+	if (!ret)
+		led_set_state(dev, LEDST_ON);
+
+	ret = led_get_by_label("status:ledn", &dev);
+	if (!ret)
+		led_set_state(dev, LEDST_OFF);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/alliedtelesis/common/gpio_hog.c b/roms/u-boot/board/alliedtelesis/common/gpio_hog.c
new file mode 100644
index 000000000..4aecf7e2c
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/common/gpio_hog.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Allied Telesis Labs
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int gpio_hog_list(struct gpio_desc *gpiod, int max_count,
+		  const char *node_name, const char *gpio_name, int value)
+{
+	int node;
+	int count;
+	int i;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, node_name);
+	if (node < 0)
+		return -ENODEV;
+
+	if (!dm_gpio_is_valid(gpiod)) {
+		count =
+		    gpio_request_list_by_name_nodev(offset_to_ofnode(node),
+						    gpio_name, gpiod, max_count,
+						    GPIOD_IS_OUT);
+		if (count < 0)
+			return count;
+
+		for (i = 0; i < count; i++)
+			dm_gpio_set_value(&gpiod[i], value);
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/alliedtelesis/common/gpio_hog.h b/roms/u-boot/board/alliedtelesis/common/gpio_hog.h
new file mode 100644
index 000000000..edb744313
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/common/gpio_hog.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Allied Telesis Labs
+ */
+
+int gpio_hog_list(struct gpio_desc *gpiod, int max_count, const char *node_name,
+		  const char *gpio_name, int value);
+
+static inline int gpio_hog(struct gpio_desc *gpiod, const char *node_name,
+			   const char *gpio_name, int value)
+{
+	return gpio_hog_list(gpiod, 1, node_name, gpio_name, value);
+}
diff --git a/roms/u-boot/board/alliedtelesis/x530/MAINTAINERS b/roms/u-boot/board/alliedtelesis/x530/MAINTAINERS
new file mode 100644
index 000000000..8d2d7271b
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/x530/MAINTAINERS
@@ -0,0 +1,12 @@
+x530 BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/alliedtelesis/x530/
+F:	board/alliedtelesis/common/gpio_hog.c
+F:	board/alliedtelesis/common/gpio_hog.h
+F:	arch/arm/dts/armada-385-atl-x530.dts
+F:	arch/arm/dts/armada-385-atl-x530.dtsi
+F:	arch/arm/dts/armada-385-atl-x530DP.dts
+F:	arch/arm/dts/armada-385-atl-x530DP.dtsi
+F:	include/configs/x530.h
+F:	configs/x530_defconfig
diff --git a/roms/u-boot/board/alliedtelesis/x530/Makefile b/roms/u-boot/board/alliedtelesis/x530/Makefile
new file mode 100644
index 000000000..97de1d463
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/x530/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2017 Allied Telesis Labs
+#
+
+obj-y	:= $(BOARD).o
+ifndef CONFIG_SPL_BUILD
+obj-y	+= ../common/gpio_hog.o
+endif
diff --git a/roms/u-boot/board/alliedtelesis/x530/kwbimage.cfg b/roms/u-boot/board/alliedtelesis/x530/kwbimage.cfg
new file mode 100644
index 000000000..f58d38882
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/x530/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2017 Allied Telesis Labs
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/roms/u-boot/board/alliedtelesis/x530/x530.c b/roms/u-boot/board/alliedtelesis/x530/x530.c
new file mode 100644
index 000000000..7bcfa828d
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/x530/x530.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Allied Telesis Labs
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <wdt.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <linux/bitops.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include "../common/gpio_hog.h"
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MVEBU_DEV_BUS_BASE		(MVEBU_REGISTER(0x10400))
+
+#define CONFIG_NVS_LOCATION		0xf4800000
+#define CONFIG_NVS_SIZE			(512 << 10)
+
+static struct serdes_map board_serdes_map[] = {
+	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	*serdes_map_array = board_serdes_map;
+	*count = ARRAY_SIZE(board_serdes_map);
+	return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1866M,	/* speed_bin */
+	    MV_DDR_DEV_WIDTH_16BIT,	/* sdram device width */
+	    MV_DDR_DIE_CAP_4GBIT,	/* die capacity */
+	    MV_DDR_FREQ_SAR,		/* frequency */
+	    0, 0,			/* cas_l cas_wl */
+	    MV_DDR_TEMP_LOW,		/* temperature */
+	    MV_DDR_TIM_2T} },		/* timing */
+	BUS_MASK_32BIT_ECC,		/* subphys mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
+	{ {0} },			/* raw spd data */
+	{0},				/* timing parameters */
+	{ {0} },			/* electrical configuration */
+	{0},				/* electrical parameters */
+	0,				/* Clock enable mask */
+	160				/* Clock delay */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x00001111, MVEBU_MPP_BASE + 0x00);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x04);
+	writel(0x55000000, MVEBU_MPP_BASE + 0x08);
+	writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
+	writel(0x55555555, MVEBU_MPP_BASE + 0x10);
+	writel(0x00100565, MVEBU_MPP_BASE + 0x14);
+	writel(0x40000000, MVEBU_MPP_BASE + 0x18);
+	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/* window for NVS */
+	mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
+
+	/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
+	writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
+
+	spl_board_init();
+
+	return 0;
+}
+
+void arch_preboot_os(void)
+{
+#ifdef CONFIG_WATCHDOG
+	wdt_stop(gd->watchdog_dev);
+#endif
+}
+
+static int led_7seg_init(unsigned int segments)
+{
+	int node;
+	int ret;
+	int i;
+	struct gpio_desc desc[8];
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
+					     "atl,of-led-7seg");
+	if (node < 0)
+		return -ENODEV;
+
+	ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
+					      "segment-gpios", desc,
+					      ARRAY_SIZE(desc), GPIOD_IS_OUT);
+	if (ret < 0)
+		return ret;
+
+	for (i = 0; i < ARRAY_SIZE(desc); i++) {
+		ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
+				led_en = {};
+
+	gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
+	gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
+	gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
+	gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
+
+#ifdef MTDPARTS_MTDOOPS
+	env_set("mtdoops", MTDPARTS_MTDOOPS);
+#endif
+
+	led_7seg_init(0xff);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	puts("Board: " CONFIG_SYS_BOARD "\n");
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/altera/arria10-socdk/Kconfig b/roms/u-boot/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 000000000..621dc9702
--- /dev/null
+++ b/roms/u-boot/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10_SOCDK
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "socfpga_arria10"
+
+config SYS_VENDOR
+	default "altera"
+
+config SYS_SOC
+	default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+	default "socfpga_arria10"
+
+endif
diff --git a/roms/u-boot/board/altera/arria10-socdk/MAINTAINERS b/roms/u-boot/board/altera/arria10-socdk/MAINTAINERS
new file mode 100644
index 000000000..5a76efb54
--- /dev/null
+++ b/roms/u-boot/board/altera/arria10-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M:	Dinh Nguyen <dinguyen@kernel.org>
+M:	Chin-Liang See <clsee@altera.com>
+S:	Maintained
+F:	board/altera/arria10-socdk/
+F:	include/configs/socfpga_arria10_socdk.h
+F:	configs/socfpga_arria10_defconfig
diff --git a/roms/u-boot/board/altera/arria10-socdk/Makefile b/roms/u-boot/board/altera/arria10-socdk/Makefile
new file mode 100644
index 000000000..80d000434
--- /dev/null
+++ b/roms/u-boot/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2015 Altera Corporation <www.altera.com>
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/altera/arria10-socdk/fit_spl_fpga.its b/roms/u-boot/board/altera/arria10-socdk/fit_spl_fpga.its
new file mode 100644
index 000000000..adae99721
--- /dev/null
+++ b/roms/u-boot/board/altera/arria10-socdk/fit_spl_fpga.its
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+ /*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	description = "FIT image with FPGA bistream";
+	#address-cells = <1>;
+
+	images {
+		fpga-periph-1 {
+			description = "FPGA peripheral bitstream";
+			data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+
+		fpga-core-1 {
+			description = "FPGA core bitstream";
+			data = /incbin/("../../../ghrd_10as066n2.core.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "config-1";
+		config-1 {
+			description = "Boot with FPGA early IO release config";
+			fpga = "fpga-periph-1", "fpga-core-1";
+		};
+	};
+};
diff --git a/roms/u-boot/board/altera/arria10-socdk/socfpga.c b/roms/u-boot/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 000000000..4c466cb94
--- /dev/null
+++ b/roms/u-boot/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/altera/arria5-socdk/MAINTAINERS b/roms/u-boot/board/altera/arria5-socdk/MAINTAINERS
new file mode 100644
index 000000000..873ec2be2
--- /dev/null
+++ b/roms/u-boot/board/altera/arria5-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M:	Dinh Nguyen <dinguyen@kernel.org>
+M:	Chin-Liang See <clsee@altera.com>
+S:	Maintained
+F:	board/altera/arria5-socdk/
+F:	include/configs/socfpga_arria5_socdk.h
+F:	configs/socfpga_arria5_defconfig
diff --git a/roms/u-boot/board/altera/arria5-socdk/Makefile b/roms/u-boot/board/altera/arria5-socdk/Makefile
new file mode 100644
index 000000000..e1c8a6b3c
--- /dev/null
+++ b/roms/u-boot/board/altera/arria5-socdk/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/altera/arria5-socdk/qts/iocsr_config.h b/roms/u-boot/board/altera/arria5-socdk/qts/iocsr_config.h
new file mode 100644
index 000000000..69a92de63
--- /dev/null
+++ b/roms/u-boot/board/altera/arria5-socdk/qts/iocsr_config.h
@@ -0,0 +1,695 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	1337
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	1528
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000060,
+	0x00018060,
+	0x06018060,
+	0x00004000,
+	0x0C0300C0,
+	0x0C030000,
+	0x00000030,
+	0x00000000,
+	0x00000000,
+	0x00002000,
+	0x00000000,
+	0x00000000,
+	0x06000000,
+	0x00006018,
+	0x01806018,
+	0x00001000,
+	0x0000C030,
+	0x04000000,
+	0x03000000,
+	0x0000300C,
+	0x00000000,
+	0x00000800,
+	0x00006018,
+	0x01806000,
+	0x01800000,
+	0x00000006,
+	0x00001806,
+	0x00000400,
+	0x0000300C,
+	0x00C03000,
+	0x00C00000,
+	0x00000003,
+	0x00000C03,
+	0x00000200,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00100000,
+	0x300C0000,
+	0x300000C0,
+	0x000000C0,
+	0x000300C0,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00000060,
+	0x00018060,
+	0x00004000,
+	0x000300C0,
+	0x10000000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00006018,
+	0x01806000,
+	0x01800000,
+	0x00000006,
+	0x00002000,
+	0x00000400,
+	0x0000300C,
+	0x01000000,
+	0x00000000,
+	0x00000004,
+	0x00000C03,
+	0x00000200,
+	0x00001806,
+	0x00800000,
+	0x00000000,
+	0x00000002,
+	0x00000800,
+	0x00000100,
+	0x00001000,
+	0x00400000,
+	0xC0300000,
+	0x00000000,
+	0x00000400,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x00100000,
+	0x40000000,
+	0x00000000,
+	0x00000100,
+	0x00040000,
+	0x00008000,
+	0x18060180,
+	0x20000000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000000,
+	0x00010000,
+	0x00002000,
+	0x10038060,
+	0x00000000,
+	0x00000000,
+	0x00000020,
+	0x01806018,
+	0x00001000,
+	0x00010000,
+	0x04000000,
+	0x03000000,
+	0x0000801C,
+	0x00004000,
+	0x00000800,
+	0x01806018,
+	0x02000000,
+	0x00000000,
+	0x00000008,
+	0x00002000,
+	0x00000400,
+	0x00C0300C,
+	0x00C03000,
+	0x00C00003,
+	0x00000C03,
+	0x00300C03,
+	0x00000200,
+	0x00601806,
+	0x80601800,
+	0x80600001,
+	0x80000601,
+	0x00180601,
+	0x00000100,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x2C820D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000050,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x906808A2,
+	0xA2834024,
+	0x05141A00,
+	0x808A20D0,
+	0x34024906,
+	0x01A00A28,
+	0xA20D0000,
+	0x24906808,
+	0x00A28340,
+	0xD000001A,
+	0x06808A20,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000050,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x906808A2,
+	0xA2834024,
+	0x05141A00,
+	0x808A20D0,
+	0x34024906,
+	0x01A00040,
+	0xA20D0002,
+	0x24906808,
+	0x00A28340,
+	0xD005141A,
+	0x06808A20,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A810,
+	0xAA0D4000,
+	0x01C3A808,
+	0xAA0D4000,
+	0x01C3A810,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D404,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA04,
+	0x2A835000,
+	0x0070EA02,
+	0x2A835000,
+	0x0070EA04,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC055F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xBA28A3D8,
+	0xF511451E,
+	0x0341D348,
+	0x821A0000,
+	0x0000D000,
+	0x04510680,
+	0xD859647A,
+	0x1EBA28A3,
+	0x48F51145,
+	0x000341D3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875011,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A810,
+	0xAA0D4000,
+	0x01C3A808,
+	0xAA0D4000,
+	0x01C3A810,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D404,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA04,
+	0x2A835000,
+	0x0070EA02,
+	0x2A835000,
+	0x0070EA04,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC055F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xBA28A3D8,
+	0xF511451E,
+	0x8341D348,
+	0x821A0124,
+	0x0000D000,
+	0x00000680,
+	0xD859647A,
+	0x1EBA28A3,
+	0x48F51145,
+	0x000341D3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875011,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A810,
+	0xAA0D4000,
+	0x01C3A808,
+	0xAA0D4000,
+	0x01C3A810,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D404,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA04,
+	0x2A835000,
+	0x0070EA02,
+	0x2A835000,
+	0x0070EA04,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC055F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xBA28A3D8,
+	0xF511451E,
+	0x0341D348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD859647A,
+	0x1EBA28A3,
+	0x48F51145,
+	0x000341D3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875011,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A810,
+	0xAA0D4000,
+	0x01C3A808,
+	0xAA0D4000,
+	0x01C3A810,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D404,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA04,
+	0x2A835000,
+	0x0070EA02,
+	0x2A835000,
+	0x0070EA04,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC055F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xBA28A3D8,
+	0xF511451E,
+	0x0341D348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD859647A,
+	0x1EBA28A3,
+	0x48F51145,
+	0x000341D3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875011,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00481800,
+	0x001A1A1A,
+	0x085506A0,
+	0x0000E1D4,
+	0x045506A0,
+	0x0000E1D4,
+	0x085506A0,
+	0x8000E1D4,
+	0x00000200,
+	0x00000004,
+	0x04000000,
+	0x00000009,
+	0x00002410,
+	0x00000040,
+	0x41000000,
+	0x00002082,
+	0x00000350,
+	0x000000DA,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x022A8350,
+	0x000070EA,
+	0x86000000,
+	0x08000004,
+	0x00000000,
+	0x00482000,
+	0x21800000,
+	0x00101061,
+	0x021541A8,
+	0x00003875,
+	0x011541A8,
+	0x00003875,
+	0x021541A8,
+	0x20003875,
+	0x00000080,
+	0x00000001,
+	0x41000000,
+	0x00000002,
+	0x00FF0904,
+	0x00000000,
+	0x90400000,
+	0x00000820,
+	0xC0000001,
+	0xFFD602AF,
+	0x86FFFFFF,
+	0x0A0A78B4,
+	0x000D020A,
+	0x00006800,
+	0x028A4320,
+	0xEC2CB23D,
+	0x8F5D1451,
+	0xA47A88A2,
+	0x0001A0E9,
+	0x00410D00,
+	0x40000068,
+	0x3D000003,
+	0x51EC2CB2,
+	0xA28F5D14,
+	0xE9A47A88,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000540,
+	0x000003A8,
+	0x08AA0D40,
+	0x8001C3A8,
+	0x0000007F,
+	0x00000000,
+	0x00004060,
+	0xE1208000,
+	0x0000001F,
+	0x00004100,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/altera/arria5-socdk/qts/pinmux_config.h b/roms/u-boot/board/altera/arria5-socdk/qts/pinmux_config.h
new file mode 100644
index 000000000..78a032582
--- /dev/null
+++ b/roms/u-boot/board/altera/arria5-socdk/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	3, /* EMACIO14 */
+	3, /* EMACIO15 */
+	3, /* EMACIO16 */
+	3, /* EMACIO17 */
+	3, /* EMACIO18 */
+	3, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	3, /* GENERALIO0 */
+	3, /* GENERALIO1 */
+	3, /* GENERALIO2 */
+	3, /* GENERALIO3 */
+	3, /* GENERALIO4 */
+	3, /* GENERALIO5 */
+	3, /* GENERALIO6 */
+	3, /* GENERALIO7 */
+	3, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	3, /* GENERALIO15 */
+	3, /* GENERALIO16 */
+	2, /* GENERALIO17 */
+	2, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	3, /* GENERALIO23 */
+	3, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	0, /* MIXED1IO0 */
+	0, /* MIXED1IO1 */
+	0, /* MIXED1IO2 */
+	0, /* MIXED1IO3 */
+	0, /* MIXED1IO4 */
+	0, /* MIXED1IO5 */
+	0, /* MIXED1IO6 */
+	0, /* MIXED1IO7 */
+	0, /* MIXED1IO8 */
+	0, /* MIXED1IO9 */
+	0, /* MIXED1IO10 */
+	0, /* MIXED1IO11 */
+	0, /* MIXED1IO12 */
+	0, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	3, /* MIXED2IO0 */
+	3, /* MIXED2IO1 */
+	3, /* MIXED2IO2 */
+	3, /* MIXED2IO3 */
+	3, /* MIXED2IO4 */
+	3, /* MIXED2IO5 */
+	3, /* MIXED2IO6 */
+	3, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/altera/arria5-socdk/qts/pll_config.h b/roms/u-boot/board/altera/arria5-socdk/qts/pll_config.h
new file mode 100644
index 000000000..6c8325434
--- /dev/null
+++ b/roms/u-boot/board/altera/arria5-socdk/qts/pll_config.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 41
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 127
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1050000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 1066000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 350000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 100000000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 0
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 2
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/roms/u-boot/board/altera/arria5-socdk/qts/sdram_config.h b/roms/u-boot/board/altera/arria5-socdk/qts/sdram_config.h
new file mode 100644
index 000000000..927a7a4f8
--- /dev/null
+++ b/roms/u-boot/board/altera/arria5-socdk/qts/sdram_config.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		40
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			19
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			139
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		4160
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			19
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			26
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x48
+#define RW_MGR_GUARANTEED_READ	0x4B
+#define RW_MGR_GUARANTEED_READ_CONT	0x53
+#define RW_MGR_GUARANTEED_WRITE	0x17
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1A
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1E
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1C
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7A
+#define RW_MGR_IDLE_LOOP2	0x79
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6E
+#define RW_MGR_INIT_RESET_1_CKE_0	0x73
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x21
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x31
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x20
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x35
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x45
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x34
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x58
+#define RW_MGR_READ_B2B_WAIT1	0x60
+#define RW_MGR_READ_B2B_WAIT2	0x6A
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7C
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	8
+#define CALIB_VFIFO_OFFSET	6
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	234
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	15
+#define IO_DQS_EN_DELAY_OFFSET	16
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	6
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x5555048c
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	5
+#define RW_MGR_MEM_DATA_WIDTH	40
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	5
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	5
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	5
+#define TINIT_CNTR0_VAL	132
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	132
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] ={
+	0x20700000,
+	0x20780000,
+	0x10080831,
+	0x10080930,
+	0x10090004,
+	0x100a0008,
+	0x100b0000,
+	0x10380400,
+	0x10080849,
+	0x100808c8,
+	0x100a0004,
+	0x10090010,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] ={
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/roms/u-boot/board/altera/arria5-socdk/socfpga.c b/roms/u-boot/board/altera/arria5-socdk/socfpga.c
new file mode 100644
index 000000000..48bfe3295
--- /dev/null
+++ b/roms/u-boot/board/altera/arria5-socdk/socfpga.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+#include <common.h>
diff --git a/roms/u-boot/board/altera/cyclone5-socdk/MAINTAINERS b/roms/u-boot/board/altera/cyclone5-socdk/MAINTAINERS
new file mode 100644
index 000000000..ecf1d04f7
--- /dev/null
+++ b/roms/u-boot/board/altera/cyclone5-socdk/MAINTAINERS
@@ -0,0 +1,12 @@
+SOCFPGA BOARD
+M:	Dinh Nguyen <dinguyen@kernel.org>
+M:	Chin-Liang See <clsee@altera.com>
+S:	Maintained
+F:	board/altera/cyclone5-socdk/
+F:	include/configs/socfpga_cyclone5_socdk.h
+F:	configs/socfpga_cyclone5_defconfig
+
+SOCRATES BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	configs/socfpga_socrates_defconfig
diff --git a/roms/u-boot/board/altera/cyclone5-socdk/Makefile b/roms/u-boot/board/altera/cyclone5-socdk/Makefile
new file mode 100644
index 000000000..e1c8a6b3c
--- /dev/null
+++ b/roms/u-boot/board/altera/cyclone5-socdk/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/altera/cyclone5-socdk/qts/iocsr_config.h b/roms/u-boot/board/altera/cyclone5-socdk/qts/iocsr_config.h
new file mode 100644
index 000000000..81c507b84
--- /dev/null
+++ b/roms/u-boot/board/altera/cyclone5-socdk/qts/iocsr_config.h
@@ -0,0 +1,659 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00020080,
+	0x08020000,
+	0x08000000,
+	0x00018020,
+	0x00000000,
+	0x00004000,
+	0x00010040,
+	0x04010000,
+	0x04000000,
+	0x00000010,
+	0x00004010,
+	0x00002000,
+	0x00020000,
+	0x02008000,
+	0x02000000,
+	0x00000008,
+	0x00002008,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x000C0300,
+	0x10040000,
+	0x100000C0,
+	0x00000040,
+	0x00010040,
+	0x00008000,
+	0x00080000,
+	0x18060000,
+	0x18000000,
+	0x00000060,
+	0x00018060,
+	0x00004000,
+	0x00010040,
+	0x10000000,
+	0x04000000,
+	0x00000010,
+	0x00004010,
+	0x00002000,
+	0x06008020,
+	0x02008000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x00004010,
+	0x01004000,
+	0x01000000,
+	0x00003004,
+	0x00001004,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x00800000,
+	0x00000002,
+	0x00002000,
+	0x00000400,
+	0x00000000,
+	0x00401000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00600802,
+	0x00000000,
+	0x80200000,
+	0x80000600,
+	0x00000200,
+	0x00000100,
+	0x00300401,
+	0xC0100400,
+	0x40100000,
+	0x40000300,
+	0x000C0100,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x80040100,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x0C010040,
+	0x00008000,
+	0x18020080,
+	0x00000000,
+	0x08000000,
+	0x00040020,
+	0x06018060,
+	0x00004000,
+	0x0C010040,
+	0x04010000,
+	0x00000030,
+	0x00000000,
+	0x03004010,
+	0x00002000,
+	0x06008020,
+	0x02008000,
+	0x02000018,
+	0x00006008,
+	0x01802008,
+	0x00001000,
+	0x03004010,
+	0x01004000,
+	0x0100000C,
+	0x00003004,
+	0x00C01004,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x2C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000070,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x906808A2,
+	0xA2834024,
+	0x05141A00,
+	0x808A20D0,
+	0x34024906,
+	0x01A00A28,
+	0xA20D0000,
+	0x24906808,
+	0x00A28340,
+	0xD000001A,
+	0x06808A20,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000070,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x906808A2,
+	0xA2834024,
+	0x05141A00,
+	0x808A20D0,
+	0x34024906,
+	0x01A00040,
+	0xA20D0002,
+	0x24906808,
+	0x00A28340,
+	0xD005141A,
+	0x06808A20,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A810,
+	0xAA0D4000,
+	0x01C3A808,
+	0xAA0D4000,
+	0x01C3A810,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x000001C1,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D404,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA04,
+	0x2A835000,
+	0x0070EA02,
+	0x2A835000,
+	0x0070EA04,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC255F80,
+	0xF1C71C71,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xBA28A3D8,
+	0xF511451E,
+	0x0341D348,
+	0x821A0000,
+	0x0000D000,
+	0x04510680,
+	0xD859647A,
+	0x1EBA28A3,
+	0x48F51145,
+	0x000341D3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875011,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A810,
+	0xAA0D4000,
+	0x01C3A808,
+	0xAA0D4000,
+	0x01C3A810,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D404,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA04,
+	0x2A835000,
+	0x0070EA02,
+	0x2A835000,
+	0x0070EA04,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC255F80,
+	0xF1C71C71,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xBA28A3D8,
+	0xF511451E,
+	0x8341D348,
+	0x821A0124,
+	0x0000D000,
+	0x00000680,
+	0xD859647A,
+	0x1EBA28A3,
+	0x48F51145,
+	0x000341D3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875011,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A810,
+	0xAA0D4000,
+	0x01C3A808,
+	0xAA0D4000,
+	0x01C3A810,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D404,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA04,
+	0x2A835000,
+	0x0070EA02,
+	0x2A835000,
+	0x0070EA04,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC255F80,
+	0xF1C71C71,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xBA28A3D8,
+	0xF511451E,
+	0x0341D348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD859647A,
+	0x1EBA28A3,
+	0x48F51145,
+	0x000341D3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875011,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A810,
+	0xAA0D4000,
+	0x01C3A808,
+	0xAA0D4000,
+	0x01C3A810,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D404,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA04,
+	0x2A835000,
+	0x0070EA02,
+	0x2A835000,
+	0x0070EA04,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x40120800,
+	0x00000070,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC255F80,
+	0xF1C71C71,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xBA28A3D8,
+	0xF511451E,
+	0x0341D348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD859647A,
+	0x1EBA28A3,
+	0x48F51145,
+	0x000341D3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875011,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x001A1A1A,
+	0x085506A0,
+	0x0000E1D4,
+	0x045506A0,
+	0x0000E1D4,
+	0x085506A0,
+	0x8000E1D4,
+	0x00000200,
+	0x00000004,
+	0x04000000,
+	0x00000009,
+	0x00002410,
+	0x00000040,
+	0x41000000,
+	0x00002082,
+	0x00000350,
+	0x000000DA,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x022A8350,
+	0x000070EA,
+	0x86000000,
+	0x08000004,
+	0x00000000,
+	0x00482000,
+	0x21800000,
+	0x00101061,
+	0x021541A8,
+	0x00003875,
+	0x011541A8,
+	0x00003875,
+	0x021541A8,
+	0x20003875,
+	0x00000080,
+	0x00000001,
+	0x41000000,
+	0x00000002,
+	0x00FF0904,
+	0x00000000,
+	0x90400000,
+	0x00000820,
+	0xC0000001,
+	0x38D612AF,
+	0x86F8E38E,
+	0x0A0A78B4,
+	0x000D020A,
+	0x00006800,
+	0x028A4320,
+	0xEC2CB23D,
+	0x8F5D1451,
+	0xA47A88A2,
+	0x0001A0E9,
+	0x00410D00,
+	0x40000068,
+	0x3D000003,
+	0x51EC2CB2,
+	0xA28F5D14,
+	0xE9A47A88,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000540,
+	0x000003A8,
+	0x08AA0D40,
+	0x8001C3A8,
+	0x0000007F,
+	0x00000000,
+	0x00004060,
+	0xE1208000,
+	0x0000001F,
+	0x00004100,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/altera/cyclone5-socdk/qts/pinmux_config.h b/roms/u-boot/board/altera/cyclone5-socdk/qts/pinmux_config.h
new file mode 100644
index 000000000..ec64ae17a
--- /dev/null
+++ b/roms/u-boot/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	3, /* GENERALIO0 */
+	3, /* GENERALIO1 */
+	3, /* GENERALIO2 */
+	3, /* GENERALIO3 */
+	3, /* GENERALIO4 */
+	3, /* GENERALIO5 */
+	3, /* GENERALIO6 */
+	3, /* GENERALIO7 */
+	3, /* GENERALIO8 */
+	3, /* GENERALIO9 */
+	3, /* GENERALIO10 */
+	3, /* GENERALIO11 */
+	3, /* GENERALIO12 */
+	2, /* GENERALIO13 */
+	2, /* GENERALIO14 */
+	3, /* GENERALIO15 */
+	3, /* GENERALIO16 */
+	2, /* GENERALIO17 */
+	2, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/altera/cyclone5-socdk/qts/pll_config.h b/roms/u-boot/board/altera/cyclone5-socdk/qts/pll_config.h
new file mode 100644
index 000000000..ae5cfab0c
--- /dev/null
+++ b/roms/u-boot/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 370000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/roms/u-boot/board/altera/cyclone5-socdk/qts/sdram_config.h b/roms/u-boot/board/altera/cyclone5-socdk/qts/sdram_config.h
new file mode 100644
index 000000000..8adbfec11
--- /dev/null
+++ b/roms/u-boot/board/altera/cyclone5-socdk/qts/sdram_config.h
@@ -0,0 +1,344 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		40
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			104
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x48
+#define RW_MGR_GUARANTEED_READ	0x4B
+#define RW_MGR_GUARANTEED_READ_CONT	0x53
+#define RW_MGR_GUARANTEED_WRITE	0x17
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1A
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1E
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1C
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7C
+#define RW_MGR_IDLE_LOOP2	0x7B
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6E
+#define RW_MGR_INIT_RESET_1_CKE_0	0x73
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x21
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x31
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x20
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x35
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x45
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x34
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x58
+#define RW_MGR_READ_B2B_WAIT1	0x60
+#define RW_MGR_READ_B2B_WAIT2	0x6A
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7E
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	7
+#define CALIB_VFIFO_OFFSET	5
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	6
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x55550483
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	5
+#define RW_MGR_MEM_DATA_WIDTH	40
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	5
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	5
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	5
+#define TINIT_CNTR0_VAL	132
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	132
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] ={
+	0x20700000,
+	0x20780000,
+	0x10080431,
+	0x10080530,
+	0x10090004,
+	0x100a0008,
+	0x100b0000,
+	0x10380400,
+	0x10080449,
+	0x100804c8,
+	0x100a0004,
+	0x10090010,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] ={
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x0,
+	0xa000,
+	0x8000,
+	0x80000,
+	0x80,
+	0x80,
+	0x80,
+	0x80,
+	0xa080,
+	0x8080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/roms/u-boot/board/altera/cyclone5-socdk/socfpga.c b/roms/u-boot/board/altera/cyclone5-socdk/socfpga.c
new file mode 100644
index 000000000..48bfe3295
--- /dev/null
+++ b/roms/u-boot/board/altera/cyclone5-socdk/socfpga.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+#include <common.h>
diff --git a/roms/u-boot/board/altera/nios2/MAINTAINERS b/roms/u-boot/board/altera/nios2/MAINTAINERS
new file mode 100644
index 000000000..aff618b52
--- /dev/null
+++ b/roms/u-boot/board/altera/nios2/MAINTAINERS
@@ -0,0 +1,13 @@
+3C120 DEVBOARD
+M:	Thomas Chou <thomas@wytron.com.tw>
+S:	Maintained
+F:	arch/nios2/dts/3c120_devboard.dts
+F:	configs/3c120_defconfig
+F:	include/configs/3c120_devboard.h
+
+10M50 DEVBOARD
+M:	Thomas Chou <thomas@wytron.com.tw>
+S:	Maintained
+F:	arch/nios2/dts/10m50_devboard.dts
+F:	configs/10m50_defconfig
+F:	include/configs/10m50_devboard.h
diff --git a/roms/u-boot/board/altera/stratix10-socdk/MAINTAINERS b/roms/u-boot/board/altera/stratix10-socdk/MAINTAINERS
new file mode 100644
index 000000000..6efd0cfc0
--- /dev/null
+++ b/roms/u-boot/board/altera/stratix10-socdk/MAINTAINERS
@@ -0,0 +1,8 @@
+SOCFPGA BOARD
+M:	Chin-Liang See <chin.liang.see@intel.com>
+M:	Dinh Nguyen <dinh.nguyen@intel.com>
+S:	Maintained
+F:	board/altera/stratix10-socdk/
+F:	include/configs/socfpga_stratix10_socdk.h
+F:	configs/socfpga_stratix10_atf_defconfig
+F:	configs/socfpga_stratix10_defconfig
diff --git a/roms/u-boot/board/altera/stratix10-socdk/Makefile b/roms/u-boot/board/altera/stratix10-socdk/Makefile
new file mode 100644
index 000000000..02a9cadf7
--- /dev/null
+++ b/roms/u-boot/board/altera/stratix10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0
+#
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/altera/stratix10-socdk/socfpga.c b/roms/u-boot/board/altera/stratix10-socdk/socfpga.c
new file mode 100644
index 000000000..043fc543f
--- /dev/null
+++ b/roms/u-boot/board/altera/stratix10-socdk/socfpga.c
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/amarula/vyasa-rk3288/Kconfig b/roms/u-boot/board/amarula/vyasa-rk3288/Kconfig
new file mode 100644
index 000000000..8b8c30835
--- /dev/null
+++ b/roms/u-boot/board/amarula/vyasa-rk3288/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VYASA_RK3288
+
+config SYS_BOARD
+	default "vyasa-rk3288"
+
+config SYS_VENDOR
+	default "amarula"
+
+config SYS_CONFIG_NAME
+	default "vyasa-rk3288"
+
+endif
diff --git a/roms/u-boot/board/amarula/vyasa-rk3288/MAINTAINERS b/roms/u-boot/board/amarula/vyasa-rk3288/MAINTAINERS
new file mode 100644
index 000000000..08ea20800
--- /dev/null
+++ b/roms/u-boot/board/amarula/vyasa-rk3288/MAINTAINERS
@@ -0,0 +1,8 @@
+VYASA RK3288
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	board/amarula/vyasa-rk3288
+F:	include/configs/vyasa-rk3288.h
+F:	configs/vyasa-rk3288_defconfig
+F:	arch/arm/dts/rk3288-vyasa.dts
+F:	arch/arm/dts/rk3288-vyasa-u-boot.dtsi
diff --git a/roms/u-boot/board/amarula/vyasa-rk3288/Makefile b/roms/u-boot/board/amarula/vyasa-rk3288/Makefile
new file mode 100644
index 000000000..7c0d5c031
--- /dev/null
+++ b/roms/u-boot/board/amarula/vyasa-rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2017 Amarula Solutions
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= vyasa-rk3288.o
diff --git a/roms/u-boot/board/amarula/vyasa-rk3288/vyasa-rk3288.c b/roms/u-boot/board/amarula/vyasa-rk3288/vyasa-rk3288.c
new file mode 100644
index 000000000..92e0698c5
--- /dev/null
+++ b/roms/u-boot/board/amarula/vyasa-rk3288/vyasa-rk3288.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Amarula Solutions
+ */
+
+#include <common.h>
+#include <serial.h>
+
+#ifndef CONFIG_TPL_BUILD
+
+int spl_start_uboot(void)
+{
+        /* break into full u-boot on 'c' */
+        if (serial_tstc() && serial_getc() == 'c')
+                return 1;
+
+        return 0;
+}
+#endif
diff --git a/roms/u-boot/board/amlogic/beelink-s922x/MAINTAINERS b/roms/u-boot/board/amlogic/beelink-s922x/MAINTAINERS
new file mode 100644
index 000000000..7f223df4a
--- /dev/null
+++ b/roms/u-boot/board/amlogic/beelink-s922x/MAINTAINERS
@@ -0,0 +1,9 @@
+BEELINK-S922X
+M:	Christian Hewitt <christianshewitt@gmail.com>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/beelink-s922x/
+F:	configs/beelink-gtking_defconfig
+F:	configs/beelink-gtkingpro_defconfig
+F:	doc/board/amlogic/beelink-gtking.rst
+F:	doc/board/amlogic/beelink-gtkingpro.rst
diff --git a/roms/u-boot/board/amlogic/beelink-s922x/Makefile b/roms/u-boot/board/amlogic/beelink-s922x/Makefile
new file mode 100644
index 000000000..27b1a7410
--- /dev/null
+++ b/roms/u-boot/board/amlogic/beelink-s922x/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2020 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y	:= beelink-s922x.o
diff --git a/roms/u-boot/board/amlogic/beelink-s922x/beelink-s922x.c b/roms/u-boot/board/amlogic/beelink-s922x/beelink-s922x.c
new file mode 100644
index 000000000..bb7442626
--- /dev/null
+++ b/roms/u-boot/board/amlogic/beelink-s922x/beelink-s922x.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/boot.h>
+
+#define EFUSE_MAC_OFFSET	20
+#define EFUSE_MAC_SIZE		12
+#define MAC_ADDR_LEN		6
+
+int misc_init_r(void)
+{
+	u8 mac_addr[MAC_ADDR_LEN];
+	char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
+	ssize_t len;
+
+	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) &&
+	    meson_get_soc_rev(tmp, sizeof(tmp)) > 0)
+		env_set("soc_rev", tmp);
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+					  efuse_mac_addr, EFUSE_MAC_SIZE);
+		if (len != EFUSE_MAC_SIZE)
+			return 0;
+
+		/* MAC is stored in ASCII format, 1bytes = 2characters */
+		for (int i = 0; i < 6; i++) {
+			tmp[0] = efuse_mac_addr[i * 2];
+			tmp[1] = efuse_mac_addr[i * 2 + 1];
+			tmp[2] = '\0';
+			mac_addr[i] = simple_strtoul(tmp, NULL, 16);
+		}
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+		else
+			meson_generate_serial_ethaddr();
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/amlogic/odroid-n2/MAINTAINERS b/roms/u-boot/board/amlogic/odroid-n2/MAINTAINERS
new file mode 100644
index 000000000..77f774634
--- /dev/null
+++ b/roms/u-boot/board/amlogic/odroid-n2/MAINTAINERS
@@ -0,0 +1,9 @@
+ODROID-N2
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/odroid-n2/
+F:	configs/odroid-n2_defconfig
+F:	configs/odroid-c4_defconfig
+F:	doc/board/amlogic/odroid-n2.rst
+F:	doc/board/amlogic/odroid-c4.rst
diff --git a/roms/u-boot/board/amlogic/odroid-n2/Makefile b/roms/u-boot/board/amlogic/odroid-n2/Makefile
new file mode 100644
index 000000000..68e4e2a82
--- /dev/null
+++ b/roms/u-boot/board/amlogic/odroid-n2/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2020 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y	:= odroid-n2.o
diff --git a/roms/u-boot/board/amlogic/odroid-n2/odroid-n2.c b/roms/u-boot/board/amlogic/odroid-n2/odroid-n2.c
new file mode 100644
index 000000000..88a60f34f
--- /dev/null
+++ b/roms/u-boot/board/amlogic/odroid-n2/odroid-n2.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <adc.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/boot.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/boot.h>
+
+#define EFUSE_MAC_OFFSET	20
+#define EFUSE_MAC_SIZE		12
+#define MAC_ADDR_LEN		6
+
+#define ODROID_HW_VS_ADC_CHANNEL	1
+
+#define MESON_SOC_ID_G12B	0x29
+#define MESON_SOC_ID_SM1	0x2b
+
+int mmc_get_env_dev(void)
+{
+	if (meson_get_boot_device() == BOOT_DEVICE_EMMC)
+		return 1;
+	return 0;
+}
+
+/* Variant detection is based on the ADC RAW values for the channel #1 */
+static struct meson_odroid_boards {
+	unsigned int soc_id;
+	unsigned int adc_min;
+	unsigned int adc_max;
+	char *variant;
+} boards[] = {
+	/* OdroidN2 rev 2018,7,23 */
+	{ MESON_SOC_ID_G12B, 80 * 4,  90 * 4, "n2" },
+	/* OdroidN2 rev 2018,12,6 */
+	{ MESON_SOC_ID_G12B, 160 * 4, 170 * 4, "n2" },
+	/* OdroidN2 rev 2019,1,17 */
+	{ MESON_SOC_ID_G12B, 245 * 4, 255 * 4, "n2" },
+	/* OdroidN2 rev 2019,2,7 */
+	{ MESON_SOC_ID_G12B, 330 * 4, 350 * 4, "n2" },
+	/* OdroidN2plus rev 2019,11,20 */
+	{ MESON_SOC_ID_G12B, 410 * 4, 430 * 4, "n2_plus" },
+	/* OdroidC4 rev 2020,01,29 */
+	{ MESON_SOC_ID_SM1,   80 * 4, 100 * 4, "c4" },
+	/* OdroidHC4 rev 2019,12,10 */
+	{ MESON_SOC_ID_SM1,  300 * 4, 320 * 4, "hc4" },
+	/* OdroidC4 rev 2019,11,29 */
+	{ MESON_SOC_ID_SM1,  335 * 4, 345 * 4, "c4" },
+	/* OdroidHC4 rev 2020,8,7 */
+	{ MESON_SOC_ID_SM1,  590 * 4, 610 * 4, "hc4" },
+};
+
+static void odroid_set_fdtfile(char *soc, char *variant)
+{
+	char s[128];
+
+	snprintf(s, sizeof(s), "amlogic/meson-%s-odroid-%s.dtb", soc, variant);
+	env_set("fdtfile", s);
+}
+
+static int odroid_detect_variant(void)
+{
+	char *variant = "", *soc = "";
+	unsigned int adcval = 0;
+	int ret, i, soc_id = 0;
+
+	if (of_machine_is_compatible("amlogic,sm1")) {
+		soc_id = MESON_SOC_ID_SM1;
+		soc = "sm1";
+	} else if (of_machine_is_compatible("amlogic,g12b")) {
+		soc_id = MESON_SOC_ID_G12B;
+		soc = "g12b";
+	} else {
+		return -1;
+	}
+
+	ret = adc_channel_single_shot("adc@9000", ODROID_HW_VS_ADC_CHANNEL,
+				      &adcval);
+	if (ret)
+		return ret;
+
+	for (i = 0 ; i < ARRAY_SIZE(boards) ; ++i) {
+		if (soc_id == boards[i].soc_id &&
+		    adcval >= boards[i].adc_min &&
+		    adcval < boards[i].adc_max) {
+			variant = boards[i].variant;
+			break;
+		}
+	}
+
+	printf("Board variant: %s\n", variant);
+	env_set("variant", variant);
+
+	odroid_set_fdtfile(soc, variant);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u8 mac_addr[MAC_ADDR_LEN];
+	char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
+	ssize_t len;
+
+	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) &&
+	    meson_get_soc_rev(tmp, sizeof(tmp)) > 0)
+		env_set("soc_rev", tmp);
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+					  efuse_mac_addr, EFUSE_MAC_SIZE);
+		if (len != EFUSE_MAC_SIZE)
+			return 0;
+
+		/* MAC is stored in ASCII format, 1bytes = 2characters */
+		for (int i = 0; i < 6; i++) {
+			tmp[0] = efuse_mac_addr[i * 2];
+			tmp[1] = efuse_mac_addr[i * 2 + 1];
+			tmp[2] = '\0';
+			mac_addr[i] = simple_strtoul(tmp, NULL, 16);
+		}
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+		else
+			meson_generate_serial_ethaddr();
+	}
+
+	odroid_detect_variant();
+	return 0;
+}
diff --git a/roms/u-boot/board/amlogic/p200/MAINTAINERS b/roms/u-boot/board/amlogic/p200/MAINTAINERS
new file mode 100644
index 000000000..1df9b8b24
--- /dev/null
+++ b/roms/u-boot/board/amlogic/p200/MAINTAINERS
@@ -0,0 +1,12 @@
+P200
+M:	Beniamino Galvani <b.galvani@gmail.com>
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/p200/
+F:	configs/nanopi-k2_defconfig
+F:	configs/odroid-c2_defconfig
+F:	configs/p200_defconfig
+F:	doc/board/amlogic/p200.rst
+F:	doc/board/amlogic/nanopi-k2.rst
+F:	doc/board/amlogic/odroid-c2.rst
diff --git a/roms/u-boot/board/amlogic/p200/Makefile b/roms/u-boot/board/amlogic/p200/Makefile
new file mode 100644
index 000000000..f82a7ea9c
--- /dev/null
+++ b/roms/u-boot/board/amlogic/p200/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+
+obj-y	:= p200.o
diff --git a/roms/u-boot/board/amlogic/p200/p200.c b/roms/u-boot/board/amlogic/p200/p200.c
new file mode 100644
index 000000000..7c432f9d2
--- /dev/null
+++ b/roms/u-boot/board/amlogic/p200/p200.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/gx.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+#define EFUSE_SN_OFFSET		20
+#define EFUSE_SN_SIZE		16
+#define EFUSE_MAC_OFFSET	52
+#define EFUSE_MAC_SIZE		6
+
+int misc_init_r(void)
+{
+	u8 mac_addr[EFUSE_MAC_SIZE];
+	char serial[EFUSE_SN_SIZE];
+	ssize_t len;
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+					  mac_addr, EFUSE_MAC_SIZE);
+		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+	}
+
+	if (!env_get("serial#")) {
+		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+			EFUSE_SN_SIZE);
+		if (len == EFUSE_SN_SIZE)
+			env_set("serial#", serial);
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/amlogic/p201/MAINTAINERS b/roms/u-boot/board/amlogic/p201/MAINTAINERS
new file mode 100644
index 000000000..1501b6280
--- /dev/null
+++ b/roms/u-boot/board/amlogic/p201/MAINTAINERS
@@ -0,0 +1,7 @@
+P201
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/p201/
+F:	configs/p201_defconfig
+F:	doc/board/amlogic/p201.rst
diff --git a/roms/u-boot/board/amlogic/p201/Makefile b/roms/u-boot/board/amlogic/p201/Makefile
new file mode 100644
index 000000000..11de5396a
--- /dev/null
+++ b/roms/u-boot/board/amlogic/p201/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+
+obj-y	:= p201.o
diff --git a/roms/u-boot/board/amlogic/p201/p201.c b/roms/u-boot/board/amlogic/p201/p201.c
new file mode 100644
index 000000000..7c432f9d2
--- /dev/null
+++ b/roms/u-boot/board/amlogic/p201/p201.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/gx.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+#define EFUSE_SN_OFFSET		20
+#define EFUSE_SN_SIZE		16
+#define EFUSE_MAC_OFFSET	52
+#define EFUSE_MAC_SIZE		6
+
+int misc_init_r(void)
+{
+	u8 mac_addr[EFUSE_MAC_SIZE];
+	char serial[EFUSE_SN_SIZE];
+	ssize_t len;
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+					  mac_addr, EFUSE_MAC_SIZE);
+		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+	}
+
+	if (!env_get("serial#")) {
+		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+			EFUSE_SN_SIZE);
+		if (len == EFUSE_SN_SIZE)
+			env_set("serial#", serial);
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/amlogic/p212/MAINTAINERS b/roms/u-boot/board/amlogic/p212/MAINTAINERS
new file mode 100644
index 000000000..3d622af29
--- /dev/null
+++ b/roms/u-boot/board/amlogic/p212/MAINTAINERS
@@ -0,0 +1,15 @@
+P212
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/p212/
+F:	include/configs/p212.h
+F:	configs/khadas-vim_defconfig
+F:	configs/libretech-ac_defconfig
+F:	configs/libretech-cc_defconfig
+F:	configs/libretech-cc_v2_defconfig
+F:	configs/p212_defconfig
+F:	doc/board/amlogic/p212.rst
+F:	doc/board/amlogic/libretech-ac.rst
+F:	doc/board/amlogic/libretech-cc.rst
+F:	doc/board/amlogic/khadas-vim.rst
diff --git a/roms/u-boot/board/amlogic/p212/Makefile b/roms/u-boot/board/amlogic/p212/Makefile
new file mode 100644
index 000000000..d98cc11a4
--- /dev/null
+++ b/roms/u-boot/board/amlogic/p212/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y	:= p212.o
diff --git a/roms/u-boot/board/amlogic/p212/p212.c b/roms/u-boot/board/amlogic/p212/p212.c
new file mode 100644
index 000000000..fcef90bce
--- /dev/null
+++ b/roms/u-boot/board/amlogic/p212/p212.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/gx.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+#define EFUSE_SN_OFFSET		20
+#define EFUSE_SN_SIZE		16
+#define EFUSE_MAC_OFFSET	52
+#define EFUSE_MAC_SIZE		6
+
+int misc_init_r(void)
+{
+	u8 mac_addr[EFUSE_MAC_SIZE];
+	char serial[EFUSE_SN_SIZE];
+	ssize_t len;
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+					  mac_addr, EFUSE_MAC_SIZE);
+		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+		else
+			meson_generate_serial_ethaddr();
+	}
+
+	if (!env_get("serial#")) {
+		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+			EFUSE_SN_SIZE);
+		if (len == EFUSE_SN_SIZE)
+			env_set("serial#", serial);
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/amlogic/q200/MAINTAINERS b/roms/u-boot/board/amlogic/q200/MAINTAINERS
new file mode 100644
index 000000000..ba7c12b2c
--- /dev/null
+++ b/roms/u-boot/board/amlogic/q200/MAINTAINERS
@@ -0,0 +1,12 @@
+Q200
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/q200/
+F:	include/configs/q200.h
+F:	configs/khadas-vim2_defconfig
+F:	configs/libretech-s905d-pc_defconfig
+F:	configs/libretech-s912-pc_defconfig
+F:	configs/wetek-core2_defconfig
+F:	doc/board/amlogic/khadas-vim2.rst
+F:	doc/board/amlogic/wetek-core2.rst
diff --git a/roms/u-boot/board/amlogic/q200/Makefile b/roms/u-boot/board/amlogic/q200/Makefile
new file mode 100644
index 000000000..fd78fd068
--- /dev/null
+++ b/roms/u-boot/board/amlogic/q200/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y	:= q200.o
diff --git a/roms/u-boot/board/amlogic/q200/q200.c b/roms/u-boot/board/amlogic/q200/q200.c
new file mode 100644
index 000000000..3aa6d8f20
--- /dev/null
+++ b/roms/u-boot/board/amlogic/q200/q200.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/gx.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+
+#define EFUSE_SN_OFFSET		20
+#define EFUSE_SN_SIZE		16
+#define EFUSE_MAC_OFFSET	52
+#define EFUSE_MAC_SIZE		6
+
+int misc_init_r(void)
+{
+	u8 mac_addr[EFUSE_MAC_SIZE];
+	char serial[EFUSE_SN_SIZE];
+	ssize_t len;
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+					  mac_addr, EFUSE_MAC_SIZE);
+		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+		else
+			meson_generate_serial_ethaddr();
+	}
+
+	if (!env_get("serial#")) {
+		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+					  EFUSE_SN_SIZE);
+		if (len == EFUSE_SN_SIZE)
+			env_set("serial#", serial);
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/amlogic/s400/MAINTAINERS b/roms/u-boot/board/amlogic/s400/MAINTAINERS
new file mode 100644
index 000000000..fb46b1bbb
--- /dev/null
+++ b/roms/u-boot/board/amlogic/s400/MAINTAINERS
@@ -0,0 +1,8 @@
+S400
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/s400/
+F:	include/configs/s400.h
+F:	configs/s400_defconfig
+F:	doc/board/amlogic/s400.rst
diff --git a/roms/u-boot/board/amlogic/s400/Makefile b/roms/u-boot/board/amlogic/s400/Makefile
new file mode 100644
index 000000000..bf03862b9
--- /dev/null
+++ b/roms/u-boot/board/amlogic/s400/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y	:= s400.o
diff --git a/roms/u-boot/board/amlogic/s400/s400.c b/roms/u-boot/board/amlogic/s400/s400.c
new file mode 100644
index 000000000..06a9044fd
--- /dev/null
+++ b/roms/u-boot/board/amlogic/s400/s400.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/axg.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+int misc_init_r(void)
+{
+	meson_generate_serial_ethaddr();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/amlogic/sei510/MAINTAINERS b/roms/u-boot/board/amlogic/sei510/MAINTAINERS
new file mode 100644
index 000000000..c01c1d60d
--- /dev/null
+++ b/roms/u-boot/board/amlogic/sei510/MAINTAINERS
@@ -0,0 +1,8 @@
+SEI510
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/sei510/
+F:	configs/sei510_defconfig
+F:	include/configs/sei510.h
+F:	doc/board/amlogic/sei510.rst
diff --git a/roms/u-boot/board/amlogic/sei510/Makefile b/roms/u-boot/board/amlogic/sei510/Makefile
new file mode 100644
index 000000000..03399a384
--- /dev/null
+++ b/roms/u-boot/board/amlogic/sei510/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y	:= sei510.o
diff --git a/roms/u-boot/board/amlogic/sei510/sei510.c b/roms/u-boot/board/amlogic/sei510/sei510.c
new file mode 100644
index 000000000..bb188c21f
--- /dev/null
+++ b/roms/u-boot/board/amlogic/sei510/sei510.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <env_internal.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/axg.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+int misc_init_r(void)
+{
+	meson_generate_serial_ethaddr();
+
+	env_set("serial#", "AMLG12ASEI510");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/amlogic/sei610/MAINTAINERS b/roms/u-boot/board/amlogic/sei610/MAINTAINERS
new file mode 100644
index 000000000..092178b2c
--- /dev/null
+++ b/roms/u-boot/board/amlogic/sei610/MAINTAINERS
@@ -0,0 +1,8 @@
+SEI610
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/sei610/
+F:	configs/sei610_defconfig
+F:	include/configs/sei610.h
+F:	doc/board/amlogic/sei610.rst
diff --git a/roms/u-boot/board/amlogic/sei610/Makefile b/roms/u-boot/board/amlogic/sei610/Makefile
new file mode 100644
index 000000000..428792afe
--- /dev/null
+++ b/roms/u-boot/board/amlogic/sei610/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y	:= sei610.o
diff --git a/roms/u-boot/board/amlogic/sei610/sei610.c b/roms/u-boot/board/amlogic/sei610/sei610.c
new file mode 100644
index 000000000..6490bac9e
--- /dev/null
+++ b/roms/u-boot/board/amlogic/sei610/sei610.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <env_internal.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/axg.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+int misc_init_r(void)
+{
+	meson_generate_serial_ethaddr();
+
+	env_set("serial#", "AMLG12ASEI610");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/amlogic/u200/MAINTAINERS b/roms/u-boot/board/amlogic/u200/MAINTAINERS
new file mode 100644
index 000000000..8c23f9a7d
--- /dev/null
+++ b/roms/u-boot/board/amlogic/u200/MAINTAINERS
@@ -0,0 +1,7 @@
+U200
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/u200/
+F:	configs/u200_defconfig
+F:	doc/board/amlogic/u200.rst
diff --git a/roms/u-boot/board/amlogic/u200/Makefile b/roms/u-boot/board/amlogic/u200/Makefile
new file mode 100644
index 000000000..485791bbb
--- /dev/null
+++ b/roms/u-boot/board/amlogic/u200/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y	:= u200.o
diff --git a/roms/u-boot/board/amlogic/u200/u200.c b/roms/u-boot/board/amlogic/u200/u200.c
new file mode 100644
index 000000000..06a9044fd
--- /dev/null
+++ b/roms/u-boot/board/amlogic/u200/u200.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/axg.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+int misc_init_r(void)
+{
+	meson_generate_serial_ethaddr();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/amlogic/vim3/MAINTAINERS b/roms/u-boot/board/amlogic/vim3/MAINTAINERS
new file mode 100644
index 000000000..92b426f66
--- /dev/null
+++ b/roms/u-boot/board/amlogic/vim3/MAINTAINERS
@@ -0,0 +1,9 @@
+VIM3
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/vim3/
+F:	configs/khadas-vim3_defconfig
+F:	configs/khadas-vim3l_defconfig
+F:	doc/board/amlogic/khadas-vim3.rst
+F:	doc/board/amlogic/khadas-vim3l.rst
diff --git a/roms/u-boot/board/amlogic/vim3/Makefile b/roms/u-boot/board/amlogic/vim3/Makefile
new file mode 100644
index 000000000..c51507730
--- /dev/null
+++ b/roms/u-boot/board/amlogic/vim3/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2020 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y	:= vim3.o
diff --git a/roms/u-boot/board/amlogic/vim3/khadas-mcu.h b/roms/u-boot/board/amlogic/vim3/khadas-mcu.h
new file mode 100644
index 000000000..de3758caf
--- /dev/null
+++ b/roms/u-boot/board/amlogic/vim3/khadas-mcu.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Khadas System control Microcontroller Register map
+ *
+ * Copyright (C) 2020 BayLibre SAS
+ *
+ * Author(s): Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef MFD_KHADAS_MCU_H
+#define MFD_KHADAS_MCU_H
+
+#define KHADAS_MCU_PASSWD_VEN_0_REG		0x00 /* RO */
+#define KHADAS_MCU_PASSWD_VEN_1_REG		0x01 /* RO */
+#define KHADAS_MCU_PASSWD_VEN_2_REG		0x02 /* RO */
+#define KHADAS_MCU_PASSWD_VEN_3_REG		0x03 /* RO */
+#define KHADAS_MCU_PASSWD_VEN_4_REG		0x04 /* RO */
+#define KHADAS_MCU_PASSWD_VEN_5_REG		0x05 /* RO */
+#define KHADAS_MCU_MAC_0_REG			0x06 /* RO */
+#define KHADAS_MCU_MAC_1_REG			0x07 /* RO */
+#define KHADAS_MCU_MAC_2_REG			0x08 /* RO */
+#define KHADAS_MCU_MAC_3_REG			0x09 /* RO */
+#define KHADAS_MCU_MAC_4_REG			0x0a /* RO */
+#define KHADAS_MCU_MAC_5_REG			0x0b /* RO */
+#define KHADAS_MCU_USID_0_REG			0x0c /* RO */
+#define KHADAS_MCU_USID_1_REG			0x0d /* RO */
+#define KHADAS_MCU_USID_2_REG			0x0e /* RO */
+#define KHADAS_MCU_USID_3_REG			0x0f /* RO */
+#define KHADAS_MCU_USID_4_REG			0x10 /* RO */
+#define KHADAS_MCU_USID_5_REG			0x11 /* RO */
+#define KHADAS_MCU_VERSION_0_REG		0x12 /* RO */
+#define KHADAS_MCU_VERSION_1_REG		0x13 /* RO */
+#define KHADAS_MCU_DEVICE_NO_0_REG		0x14 /* RO */
+#define KHADAS_MCU_DEVICE_NO_1_REG		0x15 /* RO */
+#define KHADAS_MCU_FACTORY_TEST_REG		0x16 /* R */
+#define KHADAS_MCU_BOOT_MODE_REG		0x20 /* RW */
+#define KHADAS_MCU_BOOT_EN_WOL_REG		0x21 /* RW */
+#define KHADAS_MCU_BOOT_EN_RTC_REG		0x22 /* RW */
+#define KHADAS_MCU_BOOT_EN_EXP_REG		0x23 /* RW */
+#define KHADAS_MCU_BOOT_EN_IR_REG		0x24 /* RW */
+#define KHADAS_MCU_BOOT_EN_DCIN_REG		0x25 /* RW */
+#define KHADAS_MCU_BOOT_EN_KEY_REG		0x26 /* RW */
+#define KHADAS_MCU_KEY_MODE_REG			0x27 /* RW */
+#define KHADAS_MCU_LED_MODE_ON_REG		0x28 /* RW */
+#define KHADAS_MCU_LED_MODE_OFF_REG		0x29 /* RW */
+#define KHADAS_MCU_SHUTDOWN_NORMAL_REG		0x2c /* RW */
+#define KHADAS_MCU_MAC_SWITCH_REG		0x2d /* RW */
+#define KHADAS_MCU_MCU_SLEEP_MODE_REG		0x2e /* RW */
+#define KHADAS_MCU_IR_CODE1_0_REG		0x2f /* RW */
+#define KHADAS_MCU_IR_CODE1_1_REG		0x30 /* RW */
+#define KHADAS_MCU_IR_CODE1_2_REG		0x31 /* RW */
+#define KHADAS_MCU_IR_CODE1_3_REG		0x32 /* RW */
+#define KHADAS_MCU_USB_PCIE_SWITCH_REG		0x33 /* RW */
+#define KHADAS_MCU_IR_CODE2_0_REG		0x34 /* RW */
+#define KHADAS_MCU_IR_CODE2_1_REG		0x35 /* RW */
+#define KHADAS_MCU_IR_CODE2_2_REG		0x36 /* RW */
+#define KHADAS_MCU_IR_CODE2_3_REG		0x37 /* RW */
+#define KHADAS_MCU_PASSWD_USER_0_REG		0x40 /* RW */
+#define KHADAS_MCU_PASSWD_USER_1_REG		0x41 /* RW */
+#define KHADAS_MCU_PASSWD_USER_2_REG		0x42 /* RW */
+#define KHADAS_MCU_PASSWD_USER_3_REG		0x43 /* RW */
+#define KHADAS_MCU_PASSWD_USER_4_REG		0x44 /* RW */
+#define KHADAS_MCU_PASSWD_USER_5_REG		0x45 /* RW */
+#define KHADAS_MCU_USER_DATA_0_REG		0x46 /* RW 56 bytes */
+#define KHADAS_MCU_PWR_OFF_CMD_REG		0x80 /* WO */
+#define KHADAS_MCU_PASSWD_START_REG		0x81 /* WO */
+#define KHADAS_MCU_CHECK_VEN_PASSWD_REG		0x82 /* WO */
+#define KHADAS_MCU_CHECK_USER_PASSWD_REG	0x83 /* WO */
+#define KHADAS_MCU_SHUTDOWN_NORMAL_STATUS_REG	0x86 /* RO */
+#define KHADAS_MCU_WOL_INIT_START_REG		0x87 /* WO */
+#define KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG	0x88 /* WO */
+
+enum {
+	KHADAS_BOARD_VIM1 = 0x1,
+	KHADAS_BOARD_VIM2,
+	KHADAS_BOARD_VIM3,
+	KHADAS_BOARD_EDGE = 0x11,
+	KHADAS_BOARD_EDGE_V,
+};
+
+#endif /* MFD_KHADAS_MCU_H */
diff --git a/roms/u-boot/board/amlogic/vim3/vim3.c b/roms/u-boot/board/amlogic/vim3/vim3.c
new file mode 100644
index 000000000..6cd5f2e11
--- /dev/null
+++ b/roms/u-boot/board/amlogic/vim3/vim3.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env_internal.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/boot.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/sm.h>
+#include <asm/global_data.h>
+#include <i2c.h>
+#include "khadas-mcu.h"
+
+int mmc_get_env_dev(void)
+{
+	if (meson_get_boot_device() == BOOT_DEVICE_EMMC)
+		return 2;
+	return 1;
+}
+
+/*
+ * The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
+ * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
+ * an USB3.0 Type A connector and a M.2 Key M slot.
+ * The PHY driving these differential lines is shared between
+ * the USB3.0 controller and the PCIe Controller, thus only
+ * a single controller can use it.
+ */
+int meson_ft_board_setup(void *blob, struct bd_info *bd)
+{
+	struct udevice *bus, *dev;
+	int node, i2c_node, ret;
+	unsigned int i2c_addr;
+	u32 *val;
+
+	/* Find I2C device */
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "khadas,mcu");
+	if (node < 0) {
+		printf("vim3: cannot find khadas,mcu node\n");
+		return 0;
+	}
+
+	/* Get addr */
+	val = (u32 *)fdt_getprop(gd->fdt_blob, node, "reg", NULL);
+	if (!val) {
+		printf("vim3: cannot find khadas,mcu node i2c addr\n");
+		return 0;
+	}
+	i2c_addr = fdt32_to_cpu(*val);
+
+	/* Get i2c device */
+	i2c_node = fdt_parent_offset(gd->fdt_blob, node);
+	if (node < 0) {
+		printf("vim3: cannot find khadas,mcu i2c node\n");
+		return 0;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_I2C, i2c_node, &bus);
+	if (ret < 0) {
+		printf("vim3: cannot find i2c bus (%d)\n", ret);
+		return 0;
+	}
+
+	ret = i2c_get_chip(bus, i2c_addr, 1, &dev);
+	if (ret < 0) {
+		printf("vim3: cannot find i2c chip (%d)\n", ret);
+		return 0;
+	}
+
+	/* Read USB_PCIE_SWITCH_REG */
+	ret = dm_i2c_reg_read(dev, KHADAS_MCU_USB_PCIE_SWITCH_REG);
+	if (ret < 0) {
+		printf("vim3: failed to read i2c reg (%d)\n", ret);
+		return 0;
+	}
+	debug("MCU_USB_PCIE_SWITCH_REG: %d\n", ret);
+
+	/*
+	 * If in PCIe mode, alter DT
+	 * 0：Enable USB3.0，Disable PCIE, 1：Disable USB3.0, Enable PCIE
+	 */
+	if (ret > 0) {
+		static char data[32] __aligned(4);
+		const void *ptmp;
+		int len;
+
+		/* Find USB node */
+		node = fdt_node_offset_by_compatible(blob, -1, "amlogic,meson-g12a-usb-ctrl");
+		if (node < 0) {
+			printf("vim3: cannot find amlogic,meson-g12a-usb-ctrl node\n");
+			return 0;
+		}
+
+		/* Update PHY names (mandatory to disable USB3.0) */
+		len = strlcpy(data, "usb2-phy0", 32) + 1;
+		len += strlcpy(&data[len], "usb2-phy1", 32 - len) + 1;
+		ret = fdt_setprop(blob, node, "phy-names", data, len);
+		if (ret < 0) {
+			printf("vim3: failed to update usb phy names property (%d)\n", ret);
+			return 0;
+		}
+
+		/* Update PHY list, by keeping the 2 first entries (optional) */
+		ptmp = fdt_getprop(blob, node, "phys", &len);
+		if (ptmp) {
+			memcpy(data, ptmp, min_t(unsigned int, 2 * sizeof(u32), len));
+
+			ret = fdt_setprop(blob, node, "phys", data,
+					  min_t(unsigned int, 2 * sizeof(u32), len));
+			if (ret < 0)
+				printf("vim3: failed to update usb phys property (%d)\n", ret);
+		} else
+			printf("vim3: cannot find usb node phys property\n");
+
+		/* Find PCIe node */
+		node = fdt_node_offset_by_compatible(blob, -1, "amlogic,g12a-pcie");
+		if (node < 0) {
+			printf("vim3: cannot find amlogic,g12a-pcie node\n");
+			return 0;
+		}
+
+		/* Enable PCIe */
+		len = strlcpy(data, "okay", 32);
+		ret = fdt_setprop(blob, node, "status", data, len);
+		if (ret < 0) {
+			printf("vim3: failed to enable pcie node (%d)\n", ret);
+			return 0;
+		}
+
+		printf("vim3: successfully enabled PCIe\n");
+	}
+
+	return 0;
+}
+
+#define EFUSE_MAC_OFFSET	0
+#define EFUSE_MAC_SIZE		12
+#define MAC_ADDR_LEN		6
+
+int misc_init_r(void)
+{
+	u8 mac_addr[MAC_ADDR_LEN];
+	char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
+	ssize_t len;
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+					  efuse_mac_addr, EFUSE_MAC_SIZE);
+		if (len != EFUSE_MAC_SIZE)
+			return 0;
+
+		/* MAC is stored in ASCII format, 1bytes = 2characters */
+		for (int i = 0; i < 6; i++) {
+			tmp[0] = efuse_mac_addr[i * 2];
+			tmp[1] = efuse_mac_addr[i * 2 + 1];
+			tmp[2] = '\0';
+			mac_addr[i] = simple_strtoul(tmp, NULL, 16);
+		}
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+		else
+			meson_generate_serial_ethaddr();
+
+		eth_env_get_enetaddr("ethaddr", mac_addr);
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/amlogic/w400/MAINTAINERS b/roms/u-boot/board/amlogic/w400/MAINTAINERS
new file mode 100644
index 000000000..991590d9f
--- /dev/null
+++ b/roms/u-boot/board/amlogic/w400/MAINTAINERS
@@ -0,0 +1,6 @@
+W400
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+L:	u-boot-amlogic@groups.io
+F:	board/amlogic/w400/
+F:	doc/board/amlogic/w400.rst
diff --git a/roms/u-boot/board/amlogic/w400/Makefile b/roms/u-boot/board/amlogic/w400/Makefile
new file mode 100644
index 000000000..fac4a73af
--- /dev/null
+++ b/roms/u-boot/board/amlogic/w400/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y	:= w400.o
diff --git a/roms/u-boot/board/amlogic/w400/w400.c b/roms/u-boot/board/amlogic/w400/w400.c
new file mode 100644
index 000000000..419919849
--- /dev/null
+++ b/roms/u-boot/board/amlogic/w400/w400.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env_internal.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/eth.h>
+
+int misc_init_r(void)
+{
+	meson_generate_serial_ethaddr();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/aries/mcvevk/MAINTAINERS b/roms/u-boot/board/aries/mcvevk/MAINTAINERS
new file mode 100644
index 000000000..8646eafde
--- /dev/null
+++ b/roms/u-boot/board/aries/mcvevk/MAINTAINERS
@@ -0,0 +1,9 @@
+Aries MCVEVK BOARD
+M:	Wolfgang Grandegger <wg@aries-embedded.de>
+S:	Maintained
+F:	board/aries/mcvevk/
+F:	include/configs/socfpga_mcvevk.h
+F:	configs/socfpga_mcvevk_defconfig
+F:	arch/arm/dts/socfpga_cyclone5_mcv.dtsi
+F:	arch/arm/dts/socfpga_cyclone5_mcvevk.dts
+F:	arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi
diff --git a/roms/u-boot/board/aries/mcvevk/Makefile b/roms/u-boot/board/aries/mcvevk/Makefile
new file mode 100644
index 000000000..e1c8a6b3c
--- /dev/null
+++ b/roms/u-boot/board/aries/mcvevk/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/aries/mcvevk/qts/iocsr_config.h b/roms/u-boot/board/aries/mcvevk/qts/iocsr_config.h
new file mode 100644
index 000000000..e233d02b9
--- /dev/null
+++ b/roms/u-boot/board/aries/mcvevk/qts/iocsr_config.h
@@ -0,0 +1,659 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00000000,
+	0x18060000,
+	0x00000060,
+	0x00000000,
+	0x00000000,
+	0x00004000,
+	0x0C0300C0,
+	0x00000000,
+	0x0C000000,
+	0x0000C030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x06000018,
+	0x00006018,
+	0x01806018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x000C0300,
+	0x300C0000,
+	0x300000C0,
+	0x000000C0,
+	0x000300C0,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00000060,
+	0x00018060,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00018060,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0300C030,
+	0x00000000,
+	0x03000000,
+	0x0000000C,
+	0x00000000,
+	0x00000800,
+	0x00006018,
+	0x01806000,
+	0x00000000,
+	0x00000000,
+	0x00001806,
+	0x00000400,
+	0x0000300C,
+	0x00C03000,
+	0x00C00000,
+	0x00000003,
+	0x00000C03,
+	0x00000200,
+	0x00001806,
+	0x00601800,
+	0x80600000,
+	0x80000001,
+	0x00000601,
+	0x00000100,
+	0x00001000,
+	0x00300C00,
+	0xC0300000,
+	0xC0000000,
+	0x00000300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x300C0300,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x0C0300C0,
+	0x00008000,
+	0x00060180,
+	0x00000000,
+	0x18000000,
+	0x00018060,
+	0x06018060,
+	0x00004000,
+	0x200300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00018060,
+	0x00000000,
+	0x06000000,
+	0x00010018,
+	0x01806018,
+	0x00001000,
+	0x0000C030,
+	0x00000000,
+	0x03000000,
+	0x0000000C,
+	0x00C0300C,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x0C3000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x20430000,
+	0x0C003001,
+	0x00C00481,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x90218000,
+	0x86001800,
+	0x00600240,
+	0x80090218,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x4810C000,
+	0x43000C00,
+	0x00300120,
+	0xC004810C,
+	0x12043000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680A28,
+	0x45034030,
+	0x12481A01,
+	0x80A280D0,
+	0x34030C06,
+	0x01A01450,
+	0x280D0000,
+	0x30C0680A,
+	0x02490340,
+	0xD000001A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x18000000,
+	0x01800902,
+	0x00240860,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x20430000,
+	0x0C003001,
+	0x00C00481,
+	0x00000FF0,
+	0x4810C000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x90218000,
+	0x86001800,
+	0x00600240,
+	0x80090218,
+	0x24086001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x4810C000,
+	0x43000C00,
+	0x00300120,
+	0xC004810C,
+	0x12043000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680A28,
+	0x49034030,
+	0x12481A02,
+	0x80A280D0,
+	0x34030C06,
+	0x01A00040,
+	0x280D0002,
+	0x30C0680A,
+	0x02490340,
+	0xD00A281A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x18000000,
+	0x01800902,
+	0x00240860,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A890,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x2043090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA24,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0x9A28A3D7,
+	0xF511451E,
+	0x0356E388,
+	0x821A0000,
+	0x0000D000,
+	0x05140680,
+	0xD749247A,
+	0x1E9A28A3,
+	0x88F51145,
+	0x00034EE3,
+	0x00080000,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x00000000,
+	0x00000010,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A890,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040000,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00800000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA24,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x86120800,
+	0x00600240,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xEBCF23D7,
+	0xF611451E,
+	0x034E9248,
+	0x821A038E,
+	0x0000D000,
+	0x00000680,
+	0xD749247A,
+	0x1E9BCF23,
+	0x88F61145,
+	0x00034EE3,
+	0x00080000,
+	0x00001000,
+	0x00080000,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x00000000,
+	0x00000010,
+	0x0080C000,
+	0x41000000,
+	0x00000002,
+	0x00820004,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A890,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040000,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00800000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x2043090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010000,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00200000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0x9A28A3D7,
+	0xF431451E,
+	0x034E9248,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD749247A,
+	0x1E9A28A3,
+	0x88F61145,
+	0x000356E3,
+	0x00080000,
+	0x00001000,
+	0x00080000,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x00000000,
+	0x00000010,
+	0x0080C000,
+	0x41000000,
+	0x00000002,
+	0x00820004,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040000,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00800000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020000,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00001000,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x08864000,
+	0x49247A02,
+	0xEBCF23DB,
+	0xF431451E,
+	0x0356E388,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD749247A,
+	0x1EEBCF23,
+	0x88F43E79,
+	0x000356A2,
+	0x00080000,
+	0x00001000,
+	0x00080000,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x00000000,
+	0x00000010,
+	0x0080C000,
+	0x41000000,
+	0x00000002,
+	0x00820004,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00004000,
+	0x00010000,
+	0x40002080,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x00000000,
+	0x00000008,
+	0x00000020,
+	0x00008000,
+	0x20001040,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/aries/mcvevk/qts/pinmux_config.h b/roms/u-boot/board/aries/mcvevk/qts/pinmux_config.h
new file mode 100644
index 000000000..85f892ae4
--- /dev/null
+++ b/roms/u-boot/board/aries/mcvevk/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	3, /* EMACIO0 */
+	3, /* EMACIO1 */
+	3, /* EMACIO2 */
+	3, /* EMACIO3 */
+	3, /* EMACIO4 */
+	3, /* EMACIO5 */
+	3, /* EMACIO6 */
+	3, /* EMACIO7 */
+	3, /* EMACIO8 */
+	3, /* EMACIO9 */
+	3, /* EMACIO10 */
+	3, /* EMACIO11 */
+	3, /* EMACIO12 */
+	3, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	3, /* FLASHIO4 */
+	3, /* FLASHIO5 */
+	3, /* FLASHIO6 */
+	3, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	0, /* GENERALIO3 */
+	0, /* GENERALIO4 */
+	1, /* GENERALIO5 */
+	1, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	2, /* GENERALIO13 */
+	2, /* GENERALIO14 */
+	1, /* GENERALIO15 */
+	1, /* GENERALIO16 */
+	1, /* GENERALIO17 */
+	1, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	0, /* MIXED1IO0 */
+	1, /* MIXED1IO1 */
+	1, /* MIXED1IO2 */
+	1, /* MIXED1IO3 */
+	1, /* MIXED1IO4 */
+	0, /* MIXED1IO5 */
+	0, /* MIXED1IO6 */
+	0, /* MIXED1IO7 */
+	1, /* MIXED1IO8 */
+	1, /* MIXED1IO9 */
+	1, /* MIXED1IO10 */
+	1, /* MIXED1IO11 */
+	0, /* MIXED1IO12 */
+	0, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	1, /* MIXED1IO15 */
+	1, /* MIXED1IO16 */
+	1, /* MIXED1IO17 */
+	1, /* MIXED1IO18 */
+	0, /* MIXED1IO19 */
+	0, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	1, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/aries/mcvevk/qts/pll_config.h b/roms/u-boot/board/aries/mcvevk/qts/pll_config.h
new file mode 100644
index 000000000..4fa868e45
--- /dev/null
+++ b/roms/u-boot/board/aries/mcvevk/qts/pll_config.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 3125000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 100000000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/roms/u-boot/board/aries/mcvevk/qts/sdram_config.h b/roms/u-boot/board/aries/mcvevk/qts/sdram_config.h
new file mode 100644
index 000000000..fd72926a8
--- /dev/null
+++ b/roms/u-boot/board/aries/mcvevk/qts/sdram_config.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			140
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	7
+#define CALIB_VFIFO_OFFSET	5
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x55550496
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080421,
+	0x10080520,
+	0x10090044,
+	0x100a0008,
+	0x100b0000,
+	0x10380400,
+	0x10080441,
+	0x100804c0,
+	0x100a0024,
+	0x10090010,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/roms/u-boot/board/aries/mcvevk/socfpga.c b/roms/u-boot/board/aries/mcvevk/socfpga.c
new file mode 100644
index 000000000..f173bf84a
--- /dev/null
+++ b/roms/u-boot/board/aries/mcvevk/socfpga.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+#include <common.h>
diff --git a/roms/u-boot/board/aristainetos/Kconfig b/roms/u-boot/board/aristainetos/Kconfig
new file mode 100644
index 000000000..cc603c1bc
--- /dev/null
+++ b/roms/u-boot/board/aristainetos/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_ARISTAINETOS2C
+
+source "board/aristainetos/common/Kconfig"
+
+config SYS_BOARD
+	default "aristainetos"
+
+config SYS_BOARD_VERSION
+	default 5
+
+endif
+
+if TARGET_ARISTAINETOS2CCSLB
+
+source "board/aristainetos/common/Kconfig"
+
+config SYS_BOARD
+	default "aristainetos"
+
+config SYS_BOARD_VERSION
+	default 6
+
+endif
diff --git a/roms/u-boot/board/aristainetos/MAINTAINERS b/roms/u-boot/board/aristainetos/MAINTAINERS
new file mode 100644
index 000000000..c81bef9cb
--- /dev/null
+++ b/roms/u-boot/board/aristainetos/MAINTAINERS
@@ -0,0 +1,18 @@
+ARISTAINETOS BOARD
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	board/aristainetos/
+F:	include/configs/aristainetos2.h
+F:	configs/aristainetos2c_defconfig
+F:	configs/aristainetos2ccslb_defconfig
+F:	arch/arm/dts/imx6dl-aristainetos2c_7.dts
+F:	arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts
+F:	arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2_7.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2c.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi
diff --git a/roms/u-boot/board/aristainetos/Makefile b/roms/u-boot/board/aristainetos/Makefile
new file mode 100644
index 000000000..222542efe
--- /dev/null
+++ b/roms/u-boot/board/aristainetos/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+
+obj-y  := aristainetos.o
diff --git a/roms/u-boot/board/aristainetos/aristainetos.c b/roms/u-boot/board/aristainetos/aristainetos.c
new file mode 100644
index 000000000..f13fa1163
--- /dev/null
+++ b/roms/u-boot/board/aristainetos/aristainetos.c
@@ -0,0 +1,550 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <command.h>
+#include <image.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <bmp_logo.h>
+#include <dm/root.h>
+#include <env.h>
+#include <env_internal.h>
+#include <i2c_eeprom.h>
+#include <i2c.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <lcd.h>
+#include <led.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/da9063_pmic.h>
+#include <splash.h>
+#include <video_fb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	BOARD_TYPE_4 = 4,
+	BOARD_TYPE_7 = 7,
+};
+
+#define ARI_BT_4 "aristainetos2_4@2"
+#define ARI_BT_7 "aristainetos2_7@1"
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* control data pad skew - devaddr = 0x02, register = 0x04 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* tx data pad skew - devaddr = 0x02, register = 0x06 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+static int rotate_logo_one(unsigned char *out, unsigned char *in)
+{
+	int   i, j;
+
+	for (i = 0; i < BMP_LOGO_WIDTH; i++)
+		for (j = 0; j < BMP_LOGO_HEIGHT; j++)
+			out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
+			in[i * BMP_LOGO_WIDTH + j];
+	return 0;
+}
+
+/*
+ * Rotate the BMP_LOGO (only)
+ * Will only work, if the logo is square, as
+ * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
+ */
+void rotate_logo(int rotations)
+{
+	unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
+	struct bmp_header *header;
+	unsigned char *in_logo;
+	int   i, j;
+
+	if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
+		return;
+
+	header = (struct bmp_header *)bmp_logo_bitmap;
+	in_logo = bmp_logo_bitmap + header->data_offset;
+
+	/* one 90 degree rotation */
+	if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
+		rotate_logo_one(out_logo, in_logo);
+
+	/* second 90 degree rotation */
+	if (rotations == 2  ||  rotations == 3)
+		rotate_logo_one(in_logo, out_logo);
+
+	/* third 90 degree rotation */
+	if (rotations == 3)
+		rotate_logo_one(out_logo, in_logo);
+
+	/* copy result back to original array */
+	if (rotations == 1  ||  rotations == 3)
+		for (i = 0; i < BMP_LOGO_WIDTH; i++)
+			for (j = 0; j < BMP_LOGO_HEIGHT; j++)
+				in_logo[i * BMP_LOGO_WIDTH + j] =
+				out_logo[i * BMP_LOGO_WIDTH + j];
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+	s32 timeout = 100000;
+
+	/* set PLL5 clock */
+	reg = readl(&ccm->analog_pll_video);
+	reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
+	writel(reg, &ccm->analog_pll_video);
+
+	/* set PLL5 to 232720000Hz */
+	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
+	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
+	writel(reg, &ccm->analog_pll_video);
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
+	       &ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
+	       &ccm->analog_pll_video_denom);
+
+	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
+	writel(reg, &ccm->analog_pll_video);
+
+	while (timeout--)
+		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+			break;
+	if (timeout < 0)
+		printf("Warning: video pll lock timeout!\n");
+
+	reg = readl(&ccm->analog_pll_video);
+	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
+	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
+	writel(reg, &ccm->analog_pll_video);
+
+	/* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
+	reg = readl(&ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+		| (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &ccm->cs2cdr);
+
+	reg = readl(&ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &ccm->cscmr2);
+
+	reg = readl(&ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	      | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	      | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
+	      | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	      | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+	      | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+	      | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
+	       | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+		  << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+}
+
+static void setup_display(void)
+{
+	enable_ipu_clock();
+}
+
+static void set_gpr_register(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
+	       IOMUXC_GPR1_EXC_MON_SLVE |
+	       (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
+	       IOMUXC_GPR1_ACT_CS0,
+	       &iomuxc_regs->gpr[1]);
+	writel(0x0, &iomuxc_regs->gpr[8]);
+	writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
+	       IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
+	       &iomuxc_regs->gpr[12]);
+}
+
+extern char __bss_start[], __bss_end[];
+int board_early_init_f(void)
+{
+	select_ldb_di_clock_source(MXC_PLL5_CLK);
+	set_gpr_register();
+
+	/*
+	 * clear bss here, so we can use spi driver
+	 * before relocation and read Environment
+	 * from spi flash.
+	 */
+	memset(__bss_start, 0x00, __bss_end - __bss_start);
+
+	return 0;
+}
+
+static void setup_one_led(char *label, int state)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = led_get_by_label(label, &dev);
+	if (ret == 0)
+		led_set_state(dev, state);
+}
+
+static void setup_board_gpio(void)
+{
+	setup_one_led("led_ena", LEDST_ON);
+	/* switch off Status LEDs */
+	setup_one_led("led_yellow", LEDST_OFF);
+	setup_one_led("led_red", LEDST_OFF);
+	setup_one_led("led_green", LEDST_OFF);
+	setup_one_led("led_blue", LEDST_OFF);
+}
+
+static void aristainetos_run_rescue_command(int reason)
+{
+	char rescue_reason_command[20];
+
+	sprintf(rescue_reason_command, "setenv rreason %d", reason);
+	run_command(rescue_reason_command, 0);
+}
+
+static int aristainetos_bootmode_settings(void)
+{
+	struct gpio_desc *desc;
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned int sbmr1 = readl(&psrc->sbmr1);
+	char *my_bootdelay;
+	char bootmode = 0;
+	int ret;
+	struct udevice *dev;
+	int off;
+	u8 data[0x10];
+	u8 rescue_reason;
+
+	/* jumper controlled reset of the environment */
+	ret = gpio_hog_lookup_name("env_reset", &desc);
+	if (!ret) {
+		if (dm_gpio_get_value(desc)) {
+			printf("\nReset u-boot environment (jumper)\n");
+			run_command("run default_env; saveenv; saveenv", 0);
+		}
+	}
+
+	off = fdt_path_offset(gd->fdt_blob, "eeprom0");
+	if (off < 0) {
+		printf("%s: No eeprom0 path offset\n", __func__);
+		return off;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+	if (ret) {
+		printf("%s: Could not find EEPROM\n", __func__);
+		return ret;
+	}
+
+	ret = i2c_set_chip_offset_len(dev, 2);
+	if (ret)
+		return ret;
+
+	ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, sizeof(data));
+	if (ret) {
+		printf("%s: Could not read EEPROM\n", __func__);
+		return ret;
+	}
+
+	/* software controlled reset of the environment (EEPROM magic) */
+	if (strncmp((char *)data, "DeF", 3) == 0) {
+		memset(data, 0xff, 3);
+		i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
+		printf("\nReset u-boot environment (EEPROM)\n");
+		run_command("run default_env; saveenv; saveenv", 0);
+	}
+
+	if (sbmr1 & 0x40) {
+		env_set("bootmode", "1");
+		printf("SD bootmode jumper set!\n");
+	} else {
+		env_set("bootmode", "0");
+	}
+
+	/*
+	 * Check the boot-source. If booting from NOR Flash,
+	 * disable bootdelay
+	 */
+	ret = gpio_hog_lookup_name("bootsel0", &desc);
+	if (!ret)
+		bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
+	ret = gpio_hog_lookup_name("bootsel1", &desc);
+	if (!ret)
+		bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
+	ret = gpio_hog_lookup_name("bootsel2", &desc);
+	if (!ret)
+		bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
+
+	if (bootmode == 7) {
+		my_bootdelay = env_get("nor_bootdelay");
+		if (my_bootdelay)
+			env_set("bootdelay", my_bootdelay);
+		else
+			env_set("bootdelay", "-2");
+	}
+
+	/* jumper controlled boot of the rescue system */
+	ret = gpio_hog_lookup_name("boot_rescue", &desc);
+	if (!ret) {
+		if (dm_gpio_get_value(desc)) {
+			printf("\nBooting into Rescue System (jumper)\n");
+			aristainetos_run_rescue_command(16);
+			run_command("run rescue_xload_boot", 0);
+		}
+	}
+
+	/* software controlled boot of the rescue system (EEPROM magic) */
+	if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
+		rescue_reason = *(uint8_t *)&data[9];
+		memset(&data[3], 0xff, 7);
+		i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
+		printf("\nBooting into Rescue System (EEPROM)\n");
+		aristainetos_run_rescue_command(rescue_reason);
+		run_command("run rescue_xload_boot", 0);
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_DM_PMIC_DA9063)
+/*
+ * On the aristainetos2c boards the PMIC needs to be initialized,
+ * because the Ethernet PHY uses a different regulator that is not
+ * setup per hardware default. This does not influence the other versions
+ * as this regulator isn't used there at all.
+ *
+ * Unfortunately we have not yet a interface to setup all
+ * values we need.
+ */
+static int setup_pmic_voltages(void)
+{
+	struct udevice *dev;
+	int off;
+	int ret;
+
+	off = fdt_path_offset(gd->fdt_blob, "pmic0");
+	if (off < 0) {
+		printf("%s: No pmic path offset\n", __func__);
+		return off;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
+	if (ret) {
+		printf("%s: Could not find PMIC\n", __func__);
+		return ret;
+	}
+
+	pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
+	pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
+	ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
+	if (ret < 0) {
+		printf("%s: error %d get register\n", __func__, ret);
+		return ret;
+	}
+	ret &= 0xf0;
+	ret |= 0x09;
+	pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
+	pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
+	pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
+
+	return 0;
+}
+#else
+static int setup_pmic_voltages(void)
+{
+	return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+	int x, y;
+	int ret;
+
+	led_default_state();
+	splash_get_pos(&x, &y);
+	bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
+
+	ret = aristainetos_bootmode_settings();
+	if (ret)
+		return ret;
+
+	/* set board_type */
+	if (gd->board_type == BOARD_TYPE_4)
+		env_set("board_type", ARI_BT_4);
+	else
+		env_set("board_type", ARI_BT_7);
+
+	if (setup_pmic_voltages())
+		printf("Error setup PMIC\n");
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+struct display_info_t const displays[] = {
+	{
+		.bus	= -1,
+		.addr	= 0,
+		.pixfmt	= IPU_PIX_FMT_RGB24,
+		.detect	= NULL,
+		.enable	= enable_lvds,
+		.mode	= {
+			.name           = "lb07wv8",
+			.refresh        = 60,
+			.xres           = 800,
+			.yres           = 480,
+			.pixclock       = 30066,
+			.left_margin    = 88,
+			.right_margin   = 88,
+			.upper_margin   = 20,
+			.lower_margin   = 20,
+			.hsync_len      = 80,
+			.vsync_len      = 5,
+			.sync           = FB_SYNC_EXT,
+			.vmode          = FB_VMODE_NONINTERLACED
+		}
+	}
+};
+size_t display_count = ARRAY_SIZE(displays);
+
+int board_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_board_gpio();
+	setup_display();
+
+	/* GPIO_1 for USB_OTG_ID */
+	clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
+	return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	if (gd->board_type == BOARD_TYPE_4 &&
+	    strchr(name, 0x34))
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_7 &&
+	    strchr(name, 0x37))
+		return 0;
+
+	return -1;
+}
+
+static void do_board_detect(void)
+{
+	int ret;
+	char s[30];
+
+	/* default use board type 7 */
+	gd->board_type = BOARD_TYPE_7;
+	if (env_init())
+		return;
+
+	ret = env_get_f("panel", s, sizeof(s));
+	if (ret < 0)
+		return;
+
+	if (!strncmp("lg4573", s, 6))
+		gd->board_type = BOARD_TYPE_4;
+}
+
+#ifdef CONFIG_DTB_RESELECT
+int embedded_dtb_select(void)
+{
+	int rescan;
+
+	do_board_detect();
+	fdtdec_resetup(&rescan);
+
+	return 0;
+}
+#endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	if (op == ENVOP_SAVE || op == ENVOP_ERASE)
+		return ENVL_SPI_FLASH;
+
+	switch (prio) {
+	case 0:
+		return ENVL_NOWHERE;
+
+	case 1:
+		return ENVL_SPI_FLASH;
+
+	default:
+		return ENVL_UNKNOWN;
+	}
+
+	return ENVL_UNKNOWN;
+}
diff --git a/roms/u-boot/board/aristainetos/aristainetos2.cfg b/roms/u-boot/board/aristainetos/aristainetos2.cfg
new file mode 100644
index 000000000..d088cc83a
--- /dev/null
+++ b/roms/u-boot/board/aristainetos/aristainetos2.cfg
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd
+ */
+BOOT_FROM      spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup2.cfg"
+#include "nt5cc256m16cp.cfg"
+#include "clocks2.cfg"
+#include "axi.cfg"
diff --git a/roms/u-boot/board/aristainetos/axi.cfg b/roms/u-boot/board/aristainetos/axi.cfg
new file mode 100644
index 000000000..c8ec094b6
--- /dev/null
+++ b/roms/u-boot/board/aristainetos/axi.cfg
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
diff --git a/roms/u-boot/board/aristainetos/clocks2.cfg b/roms/u-boot/board/aristainetos/clocks2.cfg
new file mode 100644
index 000000000..b3146a95d
--- /dev/null
+++ b/roms/u-boot/board/aristainetos/clocks2.cfg
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00c03f3f
+DATA 4, CCM_CCGR1, 0x0030fcff
+DATA 4, CCM_CCGR2, 0x0fffcfc0
+DATA 4, CCM_CCGR3, 0x3ff0300f
+DATA 4, CCM_CCGR4, 0xfffff300
+DATA 4, CCM_CCGR5, 0x0f0000c3
+DATA 4, CCM_CCGR6, 0x00000fff
diff --git a/roms/u-boot/board/aristainetos/common/Kconfig b/roms/u-boot/board/aristainetos/common/Kconfig
new file mode 100644
index 000000000..328243c2f
--- /dev/null
+++ b/roms/u-boot/board/aristainetos/common/Kconfig
@@ -0,0 +1,33 @@
+config SYS_BOARD_VERSION
+	int "select version of aristainetos board"
+	help
+	  version of aristainetos board version
+	  5 version 2c and 2d
+	  6 version 2c-cslb
+
+config SYS_I2C_MXC_I2C1
+	default y
+
+config SYS_I2C_MXC_I2C2
+	default y
+
+config SYS_I2C_MXC_I2C3
+	default y
+
+config SYS_I2C_MXC_I2C4
+	default y
+
+config SYS_MALLOC_LEN
+	default 0x4000000
+
+config ENV_SIZE
+	default 0x3000
+
+config ENV_SECT_SIZE
+	default 0x10000
+
+config ENV_OFFSET
+	default 0xd0000
+
+config SYS_CONFIG_NAME
+	default "aristainetos2"
diff --git a/roms/u-boot/board/aristainetos/ddr-setup2.cfg b/roms/u-boot/board/aristainetos/ddr-setup2.cfg
new file mode 100644
index 000000000..5810446f1
--- /dev/null
+++ b/roms/u-boot/board/aristainetos/ddr-setup2.cfg
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/* DDR IO TYPE */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* Clock */
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
+/* Address */
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* Control */
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+/* Data Strobe */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028
diff --git a/roms/u-boot/board/aristainetos/nt5cc256m16cp.cfg b/roms/u-boot/board/aristainetos/nt5cc256m16cp.cfg
new file mode 100644
index 000000000..2f63d1ff8
--- /dev/null
+++ b/roms/u-boot/board/aristainetos/nt5cc256m16cp.cfg
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ */
+/* ZQ Calibration */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
+/*
+ * DQS gating, read delay, write delay calibration values
+ */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42190217
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x017B017B
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4176017B
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015F016C
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4C4C4D4C
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4D4C48
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3F40
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3538382E
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+/* Complete calibration by forced measurment */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020025
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x676B5313
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8B63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR, 0x006B1023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+
+/* final ddr setup */
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025565
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/roms/u-boot/board/armadeus/opos6uldev/Kconfig b/roms/u-boot/board/armadeus/opos6uldev/Kconfig
new file mode 100644
index 000000000..e66f060d1
--- /dev/null
+++ b/roms/u-boot/board/armadeus/opos6uldev/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_OPOS6ULDEV
+
+config SYS_BOARD
+	default "opos6uldev"
+
+config SYS_VENDOR
+	default "armadeus"
+
+config SYS_CONFIG_NAME
+	default "opos6uldev"
+
+config IMX_CONFIG
+	default "arch/arm/mach-imx/spl_sd.cfg"
+
+endif
diff --git a/roms/u-boot/board/armadeus/opos6uldev/MAINTAINERS b/roms/u-boot/board/armadeus/opos6uldev/MAINTAINERS
new file mode 100644
index 000000000..e46c66942
--- /dev/null
+++ b/roms/u-boot/board/armadeus/opos6uldev/MAINTAINERS
@@ -0,0 +1,6 @@
+OPOS6ULDev BOARD
+M:	Sébastien Szymanski <sebastien.szymanski@armadeus.com>
+S:	Maintained
+F:	board/armadeus/opos6uldev/
+F:	include/configs/opos6uldev.h
+F:	configs/opos6uldev_defconfig
diff --git a/roms/u-boot/board/armadeus/opos6uldev/Makefile b/roms/u-boot/board/armadeus/opos6uldev/Makefile
new file mode 100644
index 000000000..cff8eb267
--- /dev/null
+++ b/roms/u-boot/board/armadeus/opos6uldev/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2017 Armadeus Systems
+
+obj-y  := board.o
diff --git a/roms/u-boot/board/armadeus/opos6uldev/board.c b/roms/u-boot/board/armadeus/opos6uldev/board.c
new file mode 100644
index 000000000..365fdca1b
--- /dev/null
+++ b/roms/u-boot/board/armadeus/opos6uldev/board.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Armadeus Systems
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_VIDEO_MXS
+int setup_lcd(void)
+{
+	struct gpio_desc backlight;
+	int ret;
+
+	/* Set Brightness to high */
+	ret = dm_gpio_lookup_name("GPIO4_10", &backlight);
+	if (ret) {
+		printf("Cannot get GPIO4_10\n");
+		return ret;
+	}
+
+	ret = dm_gpio_request(&backlight, "backlight");
+	if (ret) {
+		printf("Cannot request GPIO4_10\n");
+		return ret;
+	}
+
+	dm_gpio_set_dir_flags(&backlight, GPIOD_IS_OUT);
+	dm_gpio_set_value(&backlight, 1);
+
+	return 0;
+}
+#endif
+
+int opos6ul_board_late_init(void)
+{
+#ifdef CONFIG_VIDEO_MXS
+	setup_lcd();
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/armltd/integrator/MAINTAINERS b/roms/u-boot/board/armltd/integrator/MAINTAINERS
new file mode 100644
index 000000000..8af765eae
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/MAINTAINERS
@@ -0,0 +1,14 @@
+INTEGRATOR BOARD
+M:	Linus Walleij <linus.walleij@linaro.org>
+S:	Maintained
+F:	board/armltd/integrator/
+F:	include/configs/integratorcp.h
+F:	configs/integratorcp_cm1136_defconfig
+F:	include/configs/integratorap.h
+F:	configs/integratorap_cm720t_defconfig
+F:	configs/integratorap_cm920t_defconfig
+F:	configs/integratorcp_cm920t_defconfig
+F:	configs/integratorap_cm926ejs_defconfig
+F:	configs/integratorcp_cm926ejs_defconfig
+F:	configs/integratorap_cm946es_defconfig
+F:	configs/integratorcp_cm946es_defconfig
diff --git a/roms/u-boot/board/armltd/integrator/Makefile b/roms/u-boot/board/armltd/integrator/Makefile
new file mode 100644
index 000000000..8c906e3f0
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# ARM Ltd.
+# Philippe Robin, <philippe.robin@arm.com>
+
+obj-y	:= lowlevel_init.o
+
+obj-y	+= integrator.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += timer.o
diff --git a/roms/u-boot/board/armltd/integrator/README b/roms/u-boot/board/armltd/integrator/README
new file mode 100644
index 000000000..af9dcc1f4
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/README
@@ -0,0 +1,108 @@
+
+		U-Boot for ARM Integrator Development Platforms
+
+			Peter Pearse, ARM Ltd.
+			peter.pearse@arm.com
+			     www.arm.com
+
+Manuals available from :-
+http://www.arm.com/products/DevTools/Hardware_Platforms.html
+
+Overview :
+--------
+There are two Integrator variants - Integrator/AP and Integrator/CP.
+Each may be fitted with a variety of core modules (CMs).
+Each CM consists of a ARM processor core and associated hardware e.g
+	FPGA implementing various controllers and/or register
+	SSRAM
+	SDRAM
+	RAM controllers
+	clock generators etc.
+CMs may be fitted with varying amounts of SDRAM using a DIMM socket.
+
+Boot Methods :
+------------
+Integrator platforms can be configured to use U-Boot in at least three ways :-
+a) Run ARM boot monitor, manually run U-Boot image from flash
+b) Run ARM boot monitor, automatically run U-Boot image from flash
+c) Run U-Boot image direct from flash.
+
+In cases a) and b) the ARM boot monitor will have configured the CM and mapped
+writeable memory to 0x00000000 in the Integrator address space.
+U-Boot has to carry out minimal configration before standard code is run.
+
+In case c) it may be necessary for U-Boot to perform CM dependent initialization.
+
+Configuring U-Boot :
+------------------
+	The makefile contains targets for Integrator platforms of both types
+fitted with all current variants of CM.
+
+	There are also targets independent of CM. These may not be suitable for
+boot process c) above. They have been preserved for backward compatibility with
+existing build processes.
+
+Code Hierarchy Applied :
+----------------------
+Code specific to initialization of a particular ARM processor has been placed in
+cpu/arm<>/start.S so that it may be used by other boards.
+
+However, to avoid duplicating code through all processor files, a generic core
+for ARM Integrator CMs has been added
+
+	arch/arm/cpu/arm_intcm
+
+Otherwise. for example,  the standard CM reset via the CM control register would
+need placing in each CM processor file......
+
+Code specific to the initialization of the CM, rather than the cpu, and initialization
+of the Integrator board itself, has been placed in
+
+	board/integrator<>/platform.S
+	board/integrator<>/integrator<>.c
+
+Targets
+=======
+The U-Boot make targets map to the available core modules as below.
+
+Integrator/AP is no longer available from ARM.
+Core modules marked ** are also no longer available.
+
+ap720t_config		** CM720T
+ap920t_config		** CM920T
+ap926ejs_config	Integrator Core Module for ARM926EJ-STM
+ap946es_config		Integrator Core Module for ARM946E-STM
+cp920t_config		** CM920T
+cp926ejs_config	Integrator Core Module for ARM926EJ-STM
+cp946es_config		Integrator Core Module for ARM946E-STM
+cp1136_config		Integrator Core Module ARM1136JF-S  TM
+
+The final groups of targets are for core modules where no explicit cpu
+code has yet been added to U-Boot i.e. they all use the same U-Boot binary
+using the generic "arm_intcm" core:
+
+ap966_config			Integrator Core Module for ARM966E-S TM
+ap922_config			Integrator Core Module for ARM922T TM with ETM
+ap922_XA10_config		Integrator Core Module for ARM922T using Altera Excalibur
+ap7_config			** CM7TDMI
+integratorap_config
+ap_config
+
+
+cp966_config			Integrator Core Module for ARM966E-S TM
+cp922_config			Integrator Core Module for ARM922T TM with ETM
+cp922_XA10_config		Integrator Core Module for ARM922T using Altera Excalibur
+cp1026_config			Integrator Core Module ARM1026EJ-S TM
+integratorcp_config
+cp_config
+
+The Makefile targets call board/integrator<>/split_by_variant.sh
+to configure various defines in include/configs/integrator<>.h
+to indicate the core module & core configuration and ensure that
+board/integrator<>/u-boot.lds loads the cpu object first in the U-Boot image.
+
+*********************************
+Because of this mechanism
+> make clean
+must be run before each change in configuration
+*********************************
diff --git a/roms/u-boot/board/armltd/integrator/arm-ebi.h b/roms/u-boot/board/armltd/integrator/arm-ebi.h
new file mode 100644
index 000000000..6b1a96d8a
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/arm-ebi.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the External Bus Interface (EBI)
+ * found in the ARM Integrator AP and CP reference designs
+ */
+
+#ifndef __ARM_EBI_H
+#define __ARM_EBI_H
+
+#define EBI_BASE		0x12000000
+
+#define EBI_CSR0_REG		0x00 /* CS0 = Boot ROM */
+#define EBI_CSR1_REG		0x04 /* CS1 = Flash */
+#define EBI_CSR2_REG		0x08 /* CS2 = SSRAM */
+#define EBI_CSR3_REG		0x0C /* CS3 = Expansion memory */
+/*
+ * The four upper bits are the waitstates for each chip select
+ * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
+ */
+#define EBI_CSR_WAIT_MASK	0xF0
+/* Whether memory is synchronous or asynchronous */
+#define EBI_CSR_SYNC_MASK	0xF7
+#define EBI_CSR_ASYNC		0x00
+#define EBI_CSR_SYNC		0x08
+/* Whether memory is write enabled or not */
+#define EBI_CSR_WREN_MASK	0xFB
+#define EBI_CSR_WREN_DISABLE	0x00
+#define EBI_CSR_WREN_ENABLE	0x04
+/* Memory bit width for each chip select */
+#define EBI_CSR_MEMSIZE_MASK	0xFC
+#define EBI_CSR_MEMSIZE_8BIT	0x00
+#define EBI_CSR_MEMSIZE_16BIT	0x01
+#define EBI_CSR_MEMSIZE_32BIT	0x02
+
+/*
+ * The lock register need to be written with 0xa05f before anything in the
+ * EBI can be changed.
+ */
+#define EBI_LOCK_REG		0x20
+#define EBI_UNLOCK_MAGIC	0xA05F
+
+#endif
diff --git a/roms/u-boot/board/armltd/integrator/integrator-sc.h b/roms/u-boot/board/armltd/integrator/integrator-sc.h
new file mode 100644
index 000000000..42d90b118
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/integrator-sc.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the System Controller (SC) and
+ * the similar "CP Controller" found in the ARM Integrator/AP and
+ * Integrator/CP reference designs
+ */
+
+#ifndef __ARM_SC_H
+#define __ARM_SC_H
+
+#define SC_BASE			0x11000000
+
+/*
+ * The system controller registers
+ */
+#define SC_ID_OFFSET		0x00
+#define SC_OSC_OFFSET		0x04
+/* Setting this bit switches to 25 MHz mode, clear means 33 MHz */
+#define SC_OSC_DIVXY		(1 << 8)
+#define SC_CTRLS_OFFSET		0x08
+#define SC_CTRLC_OFFSET		0x0C
+/* Set bits by writing CTRLS, clear bits by writing CTRLC */
+#define SC_CTRL_SOFTRESET	(1 << 0)
+#define SC_CTRL_FLASHVPP	(1 << 1)
+#define SC_CTRL_FLASHWP		(1 << 2)
+#define SC_CTRL_UART1DTR	(1 << 4)
+#define SC_CTRL_UART1RTS	(1 << 5)
+#define SC_CTRL_UART0DTR	(1 << 6)
+#define SC_CTRL_UART0RTS	(1 << 7)
+#define SC_DEC_OFFSET		0x10
+#define SC_ARB_OFFSET		0x14
+#define SC_PCI_OFFSET		0x18
+#define SC_PCI_PCIEN		(1 << 0)
+#define SC_PCI_PCIBINT_CLR	(1 << 1)
+#define SC_LOCK_OFFSET		0x1C
+#define SC_LBFADDR_OFFSET	0x20
+#define SC_LBFCODE_OFFSET	0x24
+
+#define SC_ID (SC_BASE + SC_ID_OFFSET)
+#define SC_OSC (SC_BASE + SC_OSC_OFFSET)
+#define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET)
+#define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET)
+#define SC_DEC (SC_BASE + SC_DEC_OFFSET)
+#define SC_ARB (SC_BASE + SC_ARB_OFFSET)
+#define SC_PCI (SC_BASE + SC_PCI_OFFSET)
+#define SC_LOCK (SC_BASE + SC_LOCK_OFFSET)
+#define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET)
+#define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET)
+
+/*
+ * The Integrator/CP as a smaller set of registers, at a different
+ * offset - probably not to disturb old software.
+ */
+
+#define CP_BASE			0xCB000000
+
+#define CP_IDFIELD_OFFSET	0x00
+#define CP_FLASHPROG_OFFSET	0x04
+#define CP_FLASHPROG_FLVPPEN	(1 << 0)
+#define CP_FLASHPROG_FLWREN	(1 << 1)
+#define CP_FLASHPROG_FLASHSIZE	(1 << 2)
+#define CP_FLASHPROG_EXTRABANK	(1 << 3)
+#define CP_INTREG_OFFSET	0x08
+#define CP_DECODE_OFFSET	0x0C
+
+#define CP_IDFIELD (CP_BASE + CP_ID_OFFSET)
+#define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET)
+#define CP_INTREG (CP_BASE + CP_INTREG_OFFSET)
+#define CP_DECODE (CP_BASE + CP_DECODE_OFFSET)
+
+#endif
diff --git a/roms/u-boot/board/armltd/integrator/integrator.c b/roms/u-boot/board/armltd/integrator/integrator.c
new file mode 100644
index 000000000..3e864e8e7
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/integrator.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include "arm-ebi.h"
+#include "integrator-sc.h"
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pl01x_serial_plat serial_plat = {
+	.base = 0x16000000,
+#ifdef CONFIG_ARCH_CINTEGRATOR
+	.type = TYPE_PL011,
+	.clock = 14745600,
+#else
+	.type = TYPE_PL010,
+	.clock = 0, /* Not used for PL010 */
+#endif
+};
+
+U_BOOT_DRVINFO(integrator_serials) = {
+	.name = "serial_pl01x",
+	.plat = &serial_plat,
+};
+
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	u32 val;
+
+	/* arch number of Integrator Board */
+#ifdef CONFIG_ARCH_CINTEGRATOR
+	gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
+#else
+	gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
+#endif
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+#ifdef CONFIG_CM_REMAP
+extern void cm_remap(void);
+	cm_remap();	/* remaps writeable memory to 0x00000000 */
+#endif
+
+#ifdef CONFIG_ARCH_CINTEGRATOR
+	/*
+	 * Flash protection on the Integrator/CP is in a simple register
+	 */
+	val = readl(CP_FLASHPROG);
+	val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
+	writel(val, CP_FLASHPROG);
+#else
+	/*
+	 * The Integrator/AP has some special protection mechanisms
+	 * for the external memories, first the External Bus Interface (EBI)
+	 * then the system controller (SC).
+	 *
+	 * The system comes up with the flash memory non-writable and
+	 * configuration locked. If we want U-Boot to be used for flash
+	 * access we cannot have the flash memory locked.
+	 */
+	writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
+	val = readl(EBI_BASE + EBI_CSR1_REG);
+	val &= EBI_CSR_WREN_MASK;
+	val |= EBI_CSR_WREN_ENABLE;
+	writel(val, EBI_BASE + EBI_CSR1_REG);
+	writel(0, EBI_BASE + EBI_LOCK_REG);
+
+	/*
+	 * Set up the system controller to remove write protection from
+	 * the flash memory and enable Vpp
+	 */
+	writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
+#endif
+
+	icache_enable();
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	env_set("verify", "n");
+	return (0);
+}
+
+/*
+ * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
+ * from there, which means we cannot test the RAM underneath the ROM at this
+ * point. It will be unmapped later on, when we are executing from the
+ * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
+ * RAM on higher addresses works fine.
+ */
+#define REMAPPED_FLASH_SZ 0x40000
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+#ifdef CONFIG_CM_SPD_DETECT
+	{
+extern void dram_query(void);
+	u32 cm_reg_sdram;
+	u32 sdram_shift;
+
+	dram_query();	/* Assembler accesses to CM registers */
+			/* Queries the SPD values	      */
+
+	/* Obtain the SDRAM size from the CM SDRAM register */
+
+	cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
+	/*   Register	      SDRAM size
+	 *
+	 *   0xXXXXXXbbb000bb	 16 MB
+	 *   0xXXXXXXbbb001bb	 32 MB
+	 *   0xXXXXXXbbb010bb	 64 MB
+	 *   0xXXXXXXbbb011bb	128 MB
+	 *   0xXXXXXXbbb100bb	256 MB
+	 *
+	 */
+	sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
+	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+				    REMAPPED_FLASH_SZ,
+				    0x01000000 << sdram_shift);
+	}
+#else
+	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+				    REMAPPED_FLASH_SZ,
+				    PHYS_SDRAM_1_SIZE);
+#endif /* CM_SPD_DETECT */
+	/* We only have one bank of RAM, set it to whatever was detected */
+	gd->bd->bi_dram[0].size	 = gd->ram_size;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	rc += pci_eth_init(bis);
+	return rc;
+}
+#endif
diff --git a/roms/u-boot/board/armltd/integrator/lowlevel_init.S b/roms/u-boot/board/armltd/integrator/lowlevel_init.S
new file mode 100644
index 000000000..1a1cb580b
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/lowlevel_init.S
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ */
+
+#include <config.h>
+
+	/* Reset using CM control register */
+.global reset_cpu
+reset_cpu:
+	mov	r0, #CM_BASE
+	ldr	r1,[r0,#OS_CTRL]
+	orr	r1,r1,#CMMASK_RESET
+	str	r1,[r0,#OS_CTRL]
+
+reset_failed:
+	b	reset_failed
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+	/* If U-Boot has been run after the ARM boot monitor
+	 * then all the necessary actions have been done
+	 * otherwise we are running from user flash mapped to 0x00000000
+	 * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
+	 * Changes to the (possibly soft) reset defaults of the processor
+	 * itself should be performed in cpu/arm<>/start.S
+	 * This function affects only the core module or board settings
+	 */
+
+#ifdef CONFIG_CM_INIT
+	/* CM has an initialization register
+	 * - bits in it are wired into test-chip pins to force
+	 *   reset defaults
+	 * - may need to change its contents for U-Boot
+	 */
+
+	/* set the desired CM specific value */
+	mov	r2,#CMMASK_LOWVEC	/* Vectors at 0x00000000 for all */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+	orr	r2,r2,#CMMASK_INIT_102
+#else
+
+#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
+     !defined (CONFIG_CM940T)
+
+#ifdef	CONFIG_CM_MULTIPLE_SSRAM
+	/* set simple mapping			*/
+	and	r2,r2,#CMMASK_MAP_SIMPLE
+#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM	*/
+
+#ifdef	CONFIG_CM_TCRAM
+	/* disable TCRAM			*/
+	and	r2,r2,#CMMASK_TCRAM_DISABLE
+#endif /* #ifdef CONFIG_CM_TCRAM		*/
+
+#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
+     defined (CONFIG_CM1136JF_S)
+
+	and	r2,r2,#CMMASK_LE
+
+#endif /* cpu with little endian initialization */
+
+	orr	r2,r2,#CMMASK_CMxx6_COMMON
+
+#endif /* CMxx6 code */
+
+#endif /* ARM102xxE value */
+
+	/* read CM_INIT		 */
+	mov	r0, #CM_BASE
+	ldr	r1, [r0, #OS_INIT]
+	/* check against desired bit setting */
+	and	r3,r1,r2
+	cmp	r3,r2
+	beq	init_reg_OK
+
+	/* lock for change */
+	mov	r3, #CMVAL_LOCK1
+	add	r3,r3,#CMVAL_LOCK2
+	str	r3, [r0, #OS_LOCK]
+	/* set desired value */
+	orr	r1,r1,r2
+	/* write & relock CM_INIT */
+	str	r1, [r0, #OS_INIT]
+	mov	r1, #CMVAL_UNLOCK
+	str	r1, [r0, #OS_LOCK]
+
+	/* soft reset so new values used */
+	b	reset_cpu
+
+init_reg_OK:
+
+#endif /* CONFIG_CM_INIT */
+
+	mov	pc, lr
+
+#ifdef	CONFIG_CM_SPD_DETECT
+	/* Fast memory is available for the DRAM data
+	 * - ensure it has been transferred, then summarize the data
+	 *   into a CM register
+	 */
+.globl dram_query
+dram_query:
+	stmfd	r13!,{r4-r6,lr}
+	/* set up SDRAM info					*/
+	/* - based on example code from the CM User Guide */
+	mov	r0, #CM_BASE
+
+readspdbit:
+	ldr	r1, [r0, #OS_SDRAM]	/* read the SDRAM register	*/
+	and	r1, r1, #0x20		/* mask SPD bit (5)		*/
+	cmp	r1, #0x20		/* test if set			*/
+	bne	readspdbit
+
+setupsdram:
+	add	r0, r0, #OS_SPD		/* address the copy of the SDP data	*/
+	ldrb	r1, [r0, #3]		/* number of row address lines		*/
+	ldrb	r2, [r0, #4]		/* number of column address lines	*/
+	ldrb	r3, [r0, #5]		/* number of banks			*/
+	ldrb	r4, [r0, #31]		/* module bank density			*/
+	mul	r5, r4, r3		/* size of SDRAM (MB divided by 4)	*/
+	mov	r5, r5, ASL#2		/* size in MB				*/
+	mov	r0, #CM_BASE		/* reload for later code		*/
+	cmp	r5, #0x10		/* is it 16MB?				*/
+	bne	not16
+	mov	r6, #0x2		/* store size and CAS latency of 2	*/
+	b	writesize
+
+not16:
+	cmp	r5, #0x20		/* is it  32MB? */
+	bne	not32
+	mov	r6, #0x6
+	b	writesize
+
+not32:
+	cmp	r5, #0x40		/* is it  64MB? */
+	bne	not64
+	mov	r6, #0xa
+	b	writesize
+
+not64:
+	cmp	r5, #0x80		/* is it 128MB? */
+	bne	not128
+	mov	r6, #0xe
+	b	writesize
+
+not128:
+	/* if it is none of these sizes then it is either 256MB, or
+	 * there is no SDRAM fitted so default to 256MB
+	 */
+	mov	r6, #0x12
+
+writesize:
+	mov	r1, r1, ASL#8		/* row addr lines from SDRAM reg */
+	orr	r2, r1, r2, ASL#12	/* OR in column address lines	 */
+	orr	r3, r2, r3, ASL#16	/* OR in number of banks	 */
+	orr	r6, r6, r3		/* OR in size and CAS latency	 */
+	str	r6, [r0, #OS_SDRAM]	/* store SDRAM parameters	 */
+
+#endif /* #ifdef CONFIG_CM_SPD_DETECT */
+
+	ldmfd	r13!,{r4-r6,pc}			/* back to caller */
+
+#ifdef	CONFIG_CM_REMAP
+	/* CM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 */
+.globl cm_remap
+cm_remap:
+	stmfd	r13!,{r4-r10,lr}
+
+	mov	r0, #CM_BASE
+	ldr	r1, [r0, #OS_CTRL]
+	orr	r1, r1, #CMMASK_REMAP	/* set remap and led bits */
+	str	r1, [r0, #OS_CTRL]
+
+	/* Now 0x00000000 is writeable, replace the vectors	*/
+	ldr	r0, =_start	/* r0 <- start of vectors	*/
+	add	r2, r0, #64	/* r2 <- past vectors	*/
+	sub	r1,r1,r1		/* destination 0x00000000	*/
+
+copy_vec:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]	*/
+	stmia	r1!, {r3-r10}		/* copy to	 target address [r1]	*/
+	cmp	r0, r2			/* until source end address [r2]	*/
+	ble	copy_vec
+
+	ldmfd	r13!,{r4-r10,pc}	/* back to caller			*/
+
+#endif /* #ifdef CONFIG_CM_REMAP */
diff --git a/roms/u-boot/board/armltd/integrator/pci.c b/roms/u-boot/board/armltd/integrator/pci.c
new file mode 100644
index 000000000..28efc33f1
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/pci.c
@@ -0,0 +1,462 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ */
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include "integrator-sc.h"
+#include "pci_v3.h"
+
+#define INTEGRATOR_BOOT_ROM_BASE	0x20000000
+#define INTEGRATOR_HDR0_SDRAM_BASE	0x80000000
+
+/*
+ * These are in the physical addresses on the CPU side, i.e.
+ * where we read and write stuff - you don't want to try to
+ * move these around
+ */
+#define PHYS_PCI_MEM_BASE	0x40000000
+#define PHYS_PCI_IO_BASE	0x60000000	/* PCI I/O space base */
+#define PHYS_PCI_CONFIG_BASE	0x61000000
+#define PHYS_PCI_V3_BASE	0x62000000	/* V360EPC registers */
+#define SZ_256M			0x10000000
+
+/*
+ * These are in the PCI BUS address space
+ * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor
+ * we follow the example of the kernel, because that is the address
+ * range that devices actually use - what would they be doing at
+ * 0x40000000?
+ */
+#define PCI_BUS_NONMEM_START	0x00000000
+#define PCI_BUS_NONMEM_SIZE	SZ_256M
+
+#define PCI_BUS_PREMEM_START	(PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE)
+#define PCI_BUS_PREMEM_SIZE	SZ_256M
+
+#if PCI_BUS_NONMEM_START & 0x000fffff
+#error PCI_BUS_NONMEM_START must be megabyte aligned
+#endif
+#if PCI_BUS_PREMEM_START & 0x000fffff
+#error PCI_BUS_PREMEM_START must be megabyte aligned
+#endif
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+#define PCI_ENET0_IOADDR	0x60000000 /* First card in PCI I/O space */
+#define PCI_ENET0_MEMADDR	0x40000000 /* First card in PCI memory space */
+static struct pci_config_table pci_integrator_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif /* CONFIG_PCI_PNP */
+
+/* V3 access routines */
+#define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
+#define v3_readb(o)    (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o)))
+
+#define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
+#define v3_readw(o)    (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o)))
+
+#define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
+#define v3_readl(o)    (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o)))
+
+static unsigned long v3_open_config_window(pci_dev_t bdf, int offset)
+{
+	unsigned int address, mapaddress;
+	unsigned int busnr = PCI_BUS(bdf);
+	unsigned int devfn = PCI_FUNC(bdf);
+
+	/*
+	 * Trap out illegal values
+	 */
+	if (offset > 255)
+		BUG();
+	if (busnr > 255)
+		BUG();
+	if (devfn > 255)
+		BUG();
+
+	if (busnr == 0) {
+		/*
+		 * Linux calls the thing U-Boot calls "DEV" "SLOT"
+		 * instead, but it's the same 5 bits
+		 */
+		int slot = PCI_DEV(bdf);
+
+		/*
+		 * local bus segment so need a type 0 config cycle
+		 *
+		 * build the PCI configuration "address" with one-hot in
+		 * A31-A11
+		 *
+		 * mapaddress:
+		 *  3:1 = config cycle (101)
+		 *  0   = PCI A1 & A0 are 0 (0)
+		 */
+		address = PCI_FUNC(bdf) << 8;
+		mapaddress = V3_LB_MAP_TYPE_CONFIG;
+
+		if (slot > 12)
+			/*
+			 * high order bits are handled by the MAP register
+			 */
+			mapaddress |= 1 << (slot - 5);
+		else
+			/*
+			 * low order bits handled directly in the address
+			 */
+			address |= 1 << (slot + 11);
+	} else {
+		/*
+		 * not the local bus segment so need a type 1 config cycle
+		 *
+		 * address:
+		 *  23:16 = bus number
+		 *  15:11 = slot number (7:3 of devfn)
+		 *  10:8  = func number (2:0 of devfn)
+		 *
+		 * mapaddress:
+		 *  3:1 = config cycle (101)
+		 *  0   = PCI A1 & A0 from host bus (1)
+		 */
+		mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
+		address = (busnr << 16) | (devfn << 8);
+	}
+
+	/*
+	 * Set up base0 to see all 512Mbytes of memory space (not
+	 * prefetchable), this frees up base1 for re-use by
+	 * configuration memory
+	 */
+	v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+			V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
+
+	/*
+	 * Set up base1/map1 to point into configuration space.
+	 */
+	v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
+			V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
+	v3_writew(V3_LB_MAP1, mapaddress);
+
+	return PHYS_PCI_CONFIG_BASE + address + offset;
+}
+
+static void v3_close_config_window(void)
+{
+	/*
+	 * Reassign base1 for use by prefetchable PCI memory
+	 */
+	v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
+			V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
+			V3_LB_BASE_ENABLE);
+	v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
+			V3_LB_MAP_TYPE_MEM_MULTIPLE);
+
+	/*
+	 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
+	 */
+	v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+			V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
+}
+
+static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf,
+				    int offset, unsigned char *val)
+{
+	unsigned long addr;
+
+	addr = v3_open_config_window(bdf, offset);
+	*val = __raw_readb(addr);
+	v3_close_config_window();
+	return 0;
+}
+
+static int pci_integrator_read__word(struct pci_controller *hose,
+				     pci_dev_t bdf, int offset,
+				     unsigned short *val)
+{
+	unsigned long addr;
+
+	addr = v3_open_config_window(bdf, offset);
+	*val = __raw_readw(addr);
+	v3_close_config_window();
+	return 0;
+}
+
+static int pci_integrator_read_dword(struct pci_controller *hose,
+				     pci_dev_t bdf, int offset,
+				     unsigned int *val)
+{
+	unsigned long addr;
+
+	addr = v3_open_config_window(bdf, offset);
+	*val = __raw_readl(addr);
+	v3_close_config_window();
+	return 0;
+}
+
+static int pci_integrator_write_byte(struct pci_controller *hose,
+				     pci_dev_t bdf, int offset,
+				     unsigned char val)
+{
+	unsigned long addr;
+
+	addr = v3_open_config_window(bdf, offset);
+	__raw_writeb((u8)val, addr);
+	__raw_readb(addr);
+	v3_close_config_window();
+	return 0;
+}
+
+static int pci_integrator_write_word(struct pci_controller *hose,
+				     pci_dev_t bdf, int offset,
+				     unsigned short val)
+{
+	unsigned long addr;
+
+	addr = v3_open_config_window(bdf, offset);
+	__raw_writew((u8)val, addr);
+	__raw_readw(addr);
+	v3_close_config_window();
+	return 0;
+}
+
+static int pci_integrator_write_dword(struct pci_controller *hose,
+				      pci_dev_t bdf, int offset,
+				      unsigned int val)
+{
+	unsigned long addr;
+
+	addr = v3_open_config_window(bdf, offset);
+	__raw_writel((u8)val, addr);
+	__raw_readl(addr);
+	v3_close_config_window();
+	return 0;
+}
+
+struct pci_controller integrator_hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_integrator_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	struct pci_controller *hose = &integrator_hose;
+	u16 val;
+
+	/* setting this register will take the V3 out of reset */
+	__raw_writel(SC_PCI_PCIEN, SC_PCI);
+
+	/* Wait for 230 ms (from spec) before accessing any V3 registers */
+	mdelay(230);
+
+	/* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */
+	v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16));
+
+	/* Wait for the mailbox to settle */
+	do {
+		v3_writeb(V3_MAIL_DATA, 0xAA);
+		v3_writeb(V3_MAIL_DATA + 4, 0x55);
+	} while (v3_readb(V3_MAIL_DATA) != 0xAA ||
+		 v3_readb(V3_MAIL_DATA + 4) != 0x55);
+
+	/* Make sure that V3 register access is not locked, if it is, unlock it */
+	if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
+		v3_writew(V3_SYSTEM, 0xA05F);
+
+	/*
+	 * Ensure that the slave accesses from PCI are disabled while we
+	 * setup memory windows
+	 */
+	val = v3_readw(V3_PCI_CMD);
+	val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
+	v3_writew(V3_PCI_CMD, val);
+
+	/* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
+	val = v3_readw(V3_SYSTEM);
+	val &= ~V3_SYSTEM_M_RST_OUT;
+	v3_writew(V3_SYSTEM, val);
+
+	/* Make all accesses from PCI space retry until we're ready for them */
+	val = v3_readw(V3_PCI_CFG);
+	val |= V3_PCI_CFG_M_RETRY_EN;
+	v3_writew(V3_PCI_CFG, val);
+
+	/*
+	 * Set up any V3 PCI Configuration Registers that we absolutely have to.
+	 * LB_CFG controls Local Bus protocol.
+	 * Enable LocalBus byte strobes for READ accesses too.
+	 * set bit 7 BE_IMODE and bit 6 BE_OMODE
+	 */
+	val = v3_readw(V3_LB_CFG);
+	val |= 0x0C0;
+	v3_writew(V3_LB_CFG, val);
+
+	/* PCI_CMD controls overall PCI operation. Enable PCI bus master. */
+	val = v3_readw(V3_PCI_CMD);
+	val |= V3_COMMAND_M_MASTER_EN;
+	v3_writew(V3_PCI_CMD, val);
+
+	/*
+	 * PCI_MAP0 controls where the PCI to CPU memory window is on
+	 * Local Bus
+	 */
+	v3_writel(V3_PCI_MAP0,
+		  (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB |
+						V3_PCI_MAP_M_REG_EN |
+						V3_PCI_MAP_M_ENABLE));
+
+	/* PCI_BASE0 is the PCI address of the start of the window */
+	v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE);
+
+	/* PCI_MAP1 is LOCAL address of the start of the window */
+	v3_writel(V3_PCI_MAP1,
+		  (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB |
+						  V3_PCI_MAP_M_REG_EN |
+						  V3_PCI_MAP_M_ENABLE));
+
+	/* PCI_BASE1 is the PCI address of the start of the window */
+	v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE);
+
+	/*
+	 * Set up memory the windows from local bus memory into PCI
+	 * configuration, I/O and Memory regions.
+	 * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this.
+	 */
+	v3_writew(V3_LB_BASE2,
+		  v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE);
+	v3_writew(V3_LB_MAP2, 0);
+
+	/* PCI Configuration, use LB_BASE1/LB_MAP1. */
+
+	/*
+	 * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1
+	 * Map first 256Mbytes as non-prefetchable via BASE0/MAP0
+	 */
+	v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+			V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
+	v3_writew(V3_LB_MAP0,
+		  v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM);
+
+	/* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
+	v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
+			V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
+			V3_LB_BASE_ENABLE);
+	v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
+			V3_LB_MAP_TYPE_MEM_MULTIPLE);
+
+	/* Dump PCI to local address space mappings */
+	debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0));
+	debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0));
+	debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1));
+	debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1));
+	debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2));
+	debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2));
+	debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE));
+
+	/*
+	 * Allow accesses to PCI Configuration space and set up A1, A0 for
+	 * type 1 config cycles
+	 */
+	val = v3_readw(V3_PCI_CFG);
+	val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1);
+	val |= V3_PCI_CFG_M_AD_LOW0;
+	v3_writew(V3_PCI_CFG, val);
+
+	/* now we can allow incoming PCI MEMORY accesses */
+	val = v3_readw(V3_PCI_CMD);
+	val |= V3_COMMAND_M_MEM_EN;
+	v3_writew(V3_PCI_CMD, val);
+
+	/*
+	 * Set RST_OUT to take the PCI bus is out of reset, PCI devices can
+	 * now initialise.
+	 */
+	val = v3_readw(V3_SYSTEM);
+	val |= V3_SYSTEM_M_RST_OUT;
+	v3_writew(V3_SYSTEM, val);
+
+	/*  Lock the V3 system register so that no one else can play with it */
+	val = v3_readw(V3_SYSTEM);
+	val |= V3_SYSTEM_M_LOCK;
+	v3_writew(V3_SYSTEM, val);
+
+	/*
+	 * Configure and register the PCI hose
+	 */
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* System memory space, window 0 256 MB non-prefetchable */
+	pci_set_region(hose->regions + 0,
+		       PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE,
+		       SZ_256M,
+		       PCI_REGION_MEM);
+
+	/* System memory space, window 1 256 MB prefetchable */
+	pci_set_region(hose->regions + 1,
+		       PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M,
+		       SZ_256M,
+		       PCI_REGION_MEM |
+		       PCI_REGION_PREFETCH);
+
+	/* PCI I/O space */
+	pci_set_region(hose->regions + 2,
+		       0x00000000, PHYS_PCI_IO_BASE, 0x01000000,
+		       PCI_REGION_IO);
+
+	/* PCI Memory - config space */
+	pci_set_region(hose->regions + 3,
+		       0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000,
+		       PCI_REGION_MEM);
+	/* PCI V3 regs */
+	pci_set_region(hose->regions + 4,
+		       0x00000000, PHYS_PCI_V3_BASE, 0x01000000,
+		       PCI_REGION_MEM);
+
+	hose->region_count = 5;
+
+	pci_set_ops(hose,
+		    pci_integrator_read_byte,
+		    pci_integrator_read__word,
+		    pci_integrator_read_dword,
+		    pci_integrator_write_byte,
+		    pci_integrator_write_word,
+		    pci_integrator_write_dword);
+
+	pci_register_hose(hose);
+
+	pciauto_config_init(hose);
+	pciauto_config_device(hose, 0);
+
+	hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/roms/u-boot/board/armltd/integrator/pci_v3.h b/roms/u-boot/board/armltd/integrator/pci_v3.h
new file mode 100644
index 000000000..8d09e6966
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/pci_v3.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  arch/arm/include/asm/hardware/pci_v3.h
+ *
+ *  Internal header file PCI V3 chip
+ *
+ *  Copyright (C) ARM Limited
+ *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
+ */
+#ifndef ASM_ARM_HARDWARE_PCI_V3_H
+#define ASM_ARM_HARDWARE_PCI_V3_H
+
+/* -------------------------------------------------------------------------------
+ *  V3 Local Bus to PCI Bridge definitions
+ * -------------------------------------------------------------------------------
+ *  Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
+ *  All V3 register names are prefaced by V3_ to avoid clashing with any other
+ *  PCI definitions.  Their names match the user's manual.
+ *
+ *  I'm assuming that I20 is disabled.
+ *
+ */
+#define V3_PCI_VENDOR                   0x00000000
+#define V3_PCI_DEVICE                   0x00000002
+#define V3_PCI_CMD                      0x00000004
+#define V3_PCI_STAT                     0x00000006
+#define V3_PCI_CC_REV                   0x00000008
+#define V3_PCI_HDR_CFG                  0x0000000C
+#define V3_PCI_IO_BASE                  0x00000010
+#define V3_PCI_BASE0                    0x00000014
+#define V3_PCI_BASE1                    0x00000018
+#define V3_PCI_SUB_VENDOR               0x0000002C
+#define V3_PCI_SUB_ID                   0x0000002E
+#define V3_PCI_ROM                      0x00000030
+#define V3_PCI_BPARAM                   0x0000003C
+#define V3_PCI_MAP0                     0x00000040
+#define V3_PCI_MAP1                     0x00000044
+#define V3_PCI_INT_STAT                 0x00000048
+#define V3_PCI_INT_CFG                  0x0000004C
+#define V3_LB_BASE0                     0x00000054
+#define V3_LB_BASE1                     0x00000058
+#define V3_LB_MAP0                      0x0000005E
+#define V3_LB_MAP1                      0x00000062
+#define V3_LB_BASE2                     0x00000064
+#define V3_LB_MAP2                      0x00000066
+#define V3_LB_SIZE                      0x00000068
+#define V3_LB_IO_BASE                   0x0000006E
+#define V3_FIFO_CFG                     0x00000070
+#define V3_FIFO_PRIORITY                0x00000072
+#define V3_FIFO_STAT                    0x00000074
+#define V3_LB_ISTAT                     0x00000076
+#define V3_LB_IMASK                     0x00000077
+#define V3_SYSTEM                       0x00000078
+#define V3_LB_CFG                       0x0000007A
+#define V3_PCI_CFG                      0x0000007C
+#define V3_DMA_PCI_ADR0                 0x00000080
+#define V3_DMA_PCI_ADR1                 0x00000090
+#define V3_DMA_LOCAL_ADR0               0x00000084
+#define V3_DMA_LOCAL_ADR1               0x00000094
+#define V3_DMA_LENGTH0                  0x00000088
+#define V3_DMA_LENGTH1                  0x00000098
+#define V3_DMA_CSR0                     0x0000008B
+#define V3_DMA_CSR1                     0x0000009B
+#define V3_DMA_CTLB_ADR0                0x0000008C
+#define V3_DMA_CTLB_ADR1                0x0000009C
+#define V3_DMA_DELAY                    0x000000E0
+#define V3_MAIL_DATA                    0x000000C0
+#define V3_PCI_MAIL_IEWR                0x000000D0
+#define V3_PCI_MAIL_IERD                0x000000D2
+#define V3_LB_MAIL_IEWR                 0x000000D4
+#define V3_LB_MAIL_IERD                 0x000000D6
+#define V3_MAIL_WR_STAT                 0x000000D8
+#define V3_MAIL_RD_STAT                 0x000000DA
+#define V3_QBA_MAP                      0x000000DC
+
+/*  PCI COMMAND REGISTER bits
+ */
+#define V3_COMMAND_M_FBB_EN             (1 << 9)
+#define V3_COMMAND_M_SERR_EN            (1 << 8)
+#define V3_COMMAND_M_PAR_EN             (1 << 6)
+#define V3_COMMAND_M_MASTER_EN          (1 << 2)
+#define V3_COMMAND_M_MEM_EN             (1 << 1)
+#define V3_COMMAND_M_IO_EN              (1 << 0)
+
+/*  SYSTEM REGISTER bits
+ */
+#define V3_SYSTEM_M_RST_OUT             (1 << 15)
+#define V3_SYSTEM_M_LOCK                (1 << 14)
+
+/*  PCI_CFG bits
+ */
+#define V3_PCI_CFG_M_I2O_EN		(1 << 15)
+#define V3_PCI_CFG_M_IO_REG_DIS		(1 << 14)
+#define V3_PCI_CFG_M_IO_DIS		(1 << 13)
+#define V3_PCI_CFG_M_EN3V		(1 << 12)
+#define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
+#define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
+#define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
+
+/*  PCI_BASE register bits (PCI -> Local Bus)
+ */
+#define V3_PCI_BASE_M_ADR_BASE          0xFFF00000
+#define V3_PCI_BASE_M_ADR_BASEL         0x000FFF00
+#define V3_PCI_BASE_M_PREFETCH          (1 << 3)
+#define V3_PCI_BASE_M_TYPE              (3 << 1)
+#define V3_PCI_BASE_M_IO                (1 << 0)
+
+/*  PCI MAP register bits (PCI -> Local bus)
+ */
+#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
+#define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
+#define V3_PCI_MAP_M_ROM_SIZE           (3 << 10)
+#define V3_PCI_MAP_M_SWAP               (3 << 8)
+#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
+#define V3_PCI_MAP_M_REG_EN             (1 << 1)
+#define V3_PCI_MAP_M_ENABLE             (1 << 0)
+
+#define V3_PCI_MAP_M_ADR_SIZE_1MB	(0 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_2MB	(1 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_4MB	(2 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_8MB	(3 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_16MB	(4 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_32MB	(5 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_64MB	(6 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_128MB	(7 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_256MB	(8 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_512MB	(9 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_1GB	(10 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_2GB	(11 << 4)
+
+/*
+ *  LB_BASE0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_BASE_ADR_BASE		0xfff00000
+#define V3_LB_BASE_SWAP			(3 << 8)
+#define V3_LB_BASE_ADR_SIZE		(15 << 4)
+#define V3_LB_BASE_PREFETCH		(1 << 3)
+#define V3_LB_BASE_ENABLE		(1 << 0)
+
+#define V3_LB_BASE_ADR_SIZE_1MB		(0 << 4)
+#define V3_LB_BASE_ADR_SIZE_2MB		(1 << 4)
+#define V3_LB_BASE_ADR_SIZE_4MB		(2 << 4)
+#define V3_LB_BASE_ADR_SIZE_8MB		(3 << 4)
+#define V3_LB_BASE_ADR_SIZE_16MB	(4 << 4)
+#define V3_LB_BASE_ADR_SIZE_32MB	(5 << 4)
+#define V3_LB_BASE_ADR_SIZE_64MB	(6 << 4)
+#define V3_LB_BASE_ADR_SIZE_128MB	(7 << 4)
+#define V3_LB_BASE_ADR_SIZE_256MB	(8 << 4)
+#define V3_LB_BASE_ADR_SIZE_512MB	(9 << 4)
+#define V3_LB_BASE_ADR_SIZE_1GB		(10 << 4)
+#define V3_LB_BASE_ADR_SIZE_2GB		(11 << 4)
+
+#define v3_addr_to_lb_base(a)	((a) & V3_LB_BASE_ADR_BASE)
+
+/*
+ *  LB_MAP0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_MAP_MAP_ADR		0xfff0
+#define V3_LB_MAP_TYPE			(7 << 1)
+#define V3_LB_MAP_AD_LOW_EN		(1 << 0)
+
+#define V3_LB_MAP_TYPE_IACK		(0 << 1)
+#define V3_LB_MAP_TYPE_IO		(1 << 1)
+#define V3_LB_MAP_TYPE_MEM		(3 << 1)
+#define V3_LB_MAP_TYPE_CONFIG		(5 << 1)
+#define V3_LB_MAP_TYPE_MEM_MULTIPLE	(6 << 1)
+
+/* PCI MAP register bits (PCI -> Local bus) */
+#define v3_addr_to_lb_map(a)	(((a) >> 16) & V3_LB_MAP_MAP_ADR)
+
+/*
+ *  LB_BASE2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_BASE2_ADR_BASE		0xff00
+#define V3_LB_BASE2_SWAP		(3 << 6)
+#define V3_LB_BASE2_ENABLE		(1 << 0)
+
+#define v3_addr_to_lb_base2(a)	(((a) >> 16) & V3_LB_BASE2_ADR_BASE)
+
+/*
+ *  LB_MAP2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_MAP2_MAP_ADR		0xff00
+
+#define v3_addr_to_lb_map2(a)	(((a) >> 16) & V3_LB_MAP2_MAP_ADR)
+
+#endif
diff --git a/roms/u-boot/board/armltd/integrator/timer.c b/roms/u-boot/board/armltd/integrator/timer.c
new file mode 100644
index 000000000..d220b877d
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/timer.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <time.h>
+#include <linux/delay.h>
+
+#ifdef CONFIG_ARCH_CINTEGRATOR
+#define DIV_CLOCK_INIT	1
+#define TIMER_LOAD_VAL	0xFFFFFFFFL
+#else
+#define DIV_CLOCK_INIT	256
+#define TIMER_LOAD_VAL	0x0000FFFFL
+#endif
+/* The Integrator/CP timer1 is clocked at 1MHz
+ * can be divided by 16 or 256
+ * and can be set up as a 32-bit timer
+ */
+/* U-Boot expects a 32 bit timer, running at CONFIG_SYS_HZ */
+/* Keep total timer count to avoid losing decrements < div_timer */
+static unsigned long long total_count = 0;
+static unsigned long long lastdec;	 /* Timer reading at last call	   */
+/* Divisor applied to timer clock */
+static unsigned long long div_clock = DIV_CLOCK_INIT;
+static unsigned long long div_timer = 1; /* Divisor to convert timer reading
+					  * change to U-Boot ticks
+					  */
+/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
+static ulong timestamp;		/* U-Boot ticks since startup */
+
+#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
+
+/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
+ *  - unless otherwise stated
+ */
+
+/* starts up a counter
+ * - the Integrator/CP timer can be set up to issue an interrupt */
+int timer_init (void)
+{
+	/* Load timer with initial value */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
+#ifdef CONFIG_ARCH_CINTEGRATOR
+	/* Set timer to be
+	 *	enabled		 1
+	 *	periodic	 1
+	 *	no interrupts	 0
+	 *	X		 0
+	 *	divider 1	00 == less rounding error
+	 *	32 bit		 1
+	 *	wrapping	 0
+	 */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
+#else
+	/* Set timer to be
+	 *	enabled		 1
+	 *	free-running	 0
+	 *	XX		00
+	 *	divider 256	10
+	 *	XX		00
+	 */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
+#endif
+
+	/* init the timestamp */
+	total_count = 0ULL;
+	/* capure current decrementer value    */
+	lastdec	  = READ_TIMER;
+	/* start "advancing" time stamp from 0 */
+	timestamp = 0L;
+
+	div_timer = CONFIG_SYS_HZ_CLOCK;
+	do_div(div_timer, CONFIG_SYS_HZ);
+	do_div(div_timer, div_clock);
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+/* converts the timer reading to U-Boot ticks	       */
+/* the timestamp is the number of ticks since reset    */
+static ulong get_timer_masked (void)
+{
+	/* get current count */
+	unsigned long long now = READ_TIMER;
+
+	if(now > lastdec) {
+		/* Must have wrapped */
+		total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
+	} else {
+		total_count += lastdec - now;
+	}
+	lastdec	= now;
+
+	/* Reuse "now" */
+	now = total_count;
+	do_div(now, div_timer);
+	timestamp = now;
+
+	return timestamp;
+}
+
+ulong get_timer (ulong base_ticks)
+{
+	return get_timer_masked () - base_ticks;
+}
+
+/* delay usec useconds */
+void __udelay(unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	/* Convert to U-Boot ticks */
+	tmo  = usec * CONFIG_SYS_HZ;
+	tmo /= (1000000L);
+
+	tmp  = get_timer_masked();	/* get current timestamp */
+	tmo += tmp;			/* form target timestamp */
+
+	while (get_timer_masked () < tmo) {/* loop till event */
+		/*NOP*/;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * Return the timebase clock frequency
+ * i.e. how often the timer decrements
+ */
+ulong get_tbclk(void)
+{
+	unsigned long long tmp = CONFIG_SYS_HZ_CLOCK;
+
+	do_div(tmp, div_clock);
+
+	return tmp;
+}
diff --git a/roms/u-boot/board/armltd/total_compute/Kconfig b/roms/u-boot/board/armltd/total_compute/Kconfig
new file mode 100644
index 000000000..62e6e6f4a
--- /dev/null
+++ b/roms/u-boot/board/armltd/total_compute/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TOTAL_COMPUTE
+
+config SYS_BOARD
+	default "total_compute"
+
+config SYS_VENDOR
+	default "armltd"
+
+config SYS_CONFIG_NAME
+	default "total_compute"
+
+endif
diff --git a/roms/u-boot/board/armltd/total_compute/MAINTAINERS b/roms/u-boot/board/armltd/total_compute/MAINTAINERS
new file mode 100644
index 000000000..3dc1cd188
--- /dev/null
+++ b/roms/u-boot/board/armltd/total_compute/MAINTAINERS
@@ -0,0 +1,7 @@
+TOTAL_COMPUTE BOARD
+M:	Usama Arif <usama.arif@arm.com>
+S:	Maintained
+F:	board/armltd/total_compute/
+F:	include/configs/total_compute.h
+F:	configs/total_compute_defconfig
+F:	arch/arm/dts/total_compute.dts
diff --git a/roms/u-boot/board/armltd/total_compute/Makefile b/roms/u-boot/board/armltd/total_compute/Makefile
new file mode 100644
index 000000000..8b1045843
--- /dev/null
+++ b/roms/u-boot/board/armltd/total_compute/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2020 Arm Limited
+# Usama Arif <usama.arif@arm.com>
+
+obj-y	:= total_compute.o
diff --git a/roms/u-boot/board/armltd/total_compute/total_compute.c b/roms/u-boot/board/armltd/total_compute/total_compute.c
new file mode 100644
index 000000000..b7eaab085
--- /dev/null
+++ b/roms/u-boot/board/armltd/total_compute/total_compute.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Arm Limited
+ * Usama Arif <usama.arif@arm.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+
+static const struct pl01x_serial_plat serial_plat = {
+	.base = UART0_BASE,
+	.type = TYPE_PL011,
+	.clock = CONFIG_PL011_CLOCK,
+};
+
+U_BOOT_DRVINFO(total_compute_serials) = {
+	.name = "serial_pl01x",
+	.plat = &serial_plat,
+};
+
+static struct mm_region total_compute_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = total_compute_mem_map;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/* Nothing to be done here as handled by PSCI interface */
+void reset_cpu(void)
+{
+}
diff --git a/roms/u-boot/board/armltd/vexpress64/Kconfig b/roms/u-boot/board/armltd/vexpress64/Kconfig
new file mode 100644
index 000000000..1d13f542e
--- /dev/null
+++ b/roms/u-boot/board/armltd/vexpress64/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO
+
+config SYS_BOARD
+	default "vexpress64"
+
+config SYS_VENDOR
+	default "armltd"
+
+config SYS_CONFIG_NAME
+	default "vexpress_aemv8a"
+
+config JUNO_DTB_PART
+	string "NOR flash partition holding DTB"
+	default "board.dtb"
+	help
+	  The ARM partition name in the NOR flash memory holding the
+	  device tree blob to configure U-Boot.
+
+endif
diff --git a/roms/u-boot/board/armltd/vexpress64/MAINTAINERS b/roms/u-boot/board/armltd/vexpress64/MAINTAINERS
new file mode 100644
index 000000000..0ba044d7f
--- /dev/null
+++ b/roms/u-boot/board/armltd/vexpress64/MAINTAINERS
@@ -0,0 +1,16 @@
+VEXPRESS64 BOARD
+M:	David Feng <fenghua@phytium.com.cn>
+S:	Maintained
+F:	board/armltd/vexpress64/
+F:	include/configs/vexpress_aemv8a.h
+F:	configs/vexpress_aemv8a_defconfig
+
+VEXPRESS_AEMV8A_SEMI BOARD
+M:	Linus Walleij <linus.walleij@linaro.org>
+S:	Maintained
+F:	configs/vexpress_aemv8a_semi_defconfig
+
+JUNO DEVELOPMENT PLATFORM BOARD
+M:	Linus Walleij <linus.walleij@linaro.org>
+S:	Maintained
+F:	configs/vexpress_aemv8a_juno_defconfig
diff --git a/roms/u-boot/board/armltd/vexpress64/Makefile b/roms/u-boot/board/armltd/vexpress64/Makefile
new file mode 100644
index 000000000..868dc4f62
--- /dev/null
+++ b/roms/u-boot/board/armltd/vexpress64/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= vexpress64.o
+obj-$(CONFIG_TARGET_VEXPRESS64_JUNO)	+= pcie.o
diff --git a/roms/u-boot/board/armltd/vexpress64/pcie.c b/roms/u-boot/board/armltd/vexpress64/pcie.c
new file mode 100644
index 000000000..733b190e5
--- /dev/null
+++ b/roms/u-boot/board/armltd/vexpress64/pcie.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) ARM Ltd 2015
+ *
+ * Author: Liviu Dudau <Liviu.Dudau@arm.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <pci_ids.h>
+#include <linux/delay.h>
+#include "pcie.h"
+
+/* XpressRICH3 support */
+#define XR3_CONFIG_BASE			0x7ff30000
+#define XR3_RESET_BASE			0x7ff20000
+
+#define XR3_PCI_ECAM_START		0x40000000
+#define XR3_PCI_ECAM_SIZE		28	/* as power of 2 = 0x10000000 */
+#define XR3_PCI_IOSPACE_START		0x5f800000
+#define XR3_PCI_IOSPACE_SIZE		23	/* as power of 2 = 0x800000 */
+#define XR3_PCI_MEMSPACE_START		0x50000000
+#define XR3_PCI_MEMSPACE_SIZE		27	/* as power of 2 = 0x8000000 */
+#define XR3_PCI_MEMSPACE64_START	0x4000000000
+#define XR3_PCI_MEMSPACE64_SIZE		33	/* as power of 2 = 0x200000000 */
+
+#define JUNO_V2M_MSI_START		0x2c1c0000
+#define JUNO_V2M_MSI_SIZE		12	/* as power of 2 = 4096 */
+
+#define XR3PCI_BASIC_STATUS		0x18
+#define XR3PCI_BS_GEN_MASK		(0xf << 8)
+#define XR3PCI_BS_LINK_MASK		0xff
+
+#define XR3PCI_VIRTCHAN_CREDITS		0x90
+#define XR3PCI_BRIDGE_PCI_IDS		0x9c
+#define XR3PCI_PEX_SPC2			0xd8
+
+#define XR3PCI_ATR_PCIE_WIN0		0x600
+#define XR3PCI_ATR_PCIE_WIN1		0x700
+#define XR3PCI_ATR_AXI4_SLV0		0x800
+
+#define XR3PCI_ATR_TABLE_SIZE		0x20
+#define XR3PCI_ATR_SRC_ADDR_LOW		0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH	0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW	0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH	0xc
+#define XR3PCI_ATR_TRSL_PARAM		0x10
+
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_AXIDEVICE	(0x420004)
+#define XR3PCI_ATR_TRSLID_AXIMEMORY	(0x4e0004)  /* Write-through, read/write allocate */
+#define XR3PCI_ATR_TRSLID_PCIE_CONF	(0x000001)
+#define XR3PCI_ATR_TRSLID_PCIE_IO	(0x020000)
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY	(0x000000)
+
+#define XR3PCI_ECAM_OFFSET(b, d, o)	(((b) << 20) | \
+					(PCI_SLOT(d) << 15) | \
+					(PCI_FUNC(d) << 12) | o)
+
+#define JUNO_RESET_CTRL			0x1004
+#define JUNO_RESET_CTRL_PHY		BIT(0)
+#define JUNO_RESET_CTRL_RC		BIT(1)
+
+#define JUNO_RESET_STATUS		0x1008
+#define JUNO_RESET_STATUS_PLL		BIT(0)
+#define JUNO_RESET_STATUS_PHY		BIT(1)
+#define JUNO_RESET_STATUS_RC		BIT(2)
+#define JUNO_RESET_STATUS_MASK		(JUNO_RESET_STATUS_PLL | \
+					 JUNO_RESET_STATUS_PHY | \
+					 JUNO_RESET_STATUS_RC)
+
+static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
+				 unsigned long trsl_addr, int window_size,
+				 int trsl_param)
+{
+	/* X3PCI_ATR_SRC_ADDR_LOW:
+	     - bit 0: enable entry,
+	     - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
+	     - bits 7-11: reserved
+	     - bits 12-31: start of source address
+	*/
+	writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1,
+	       base + XR3PCI_ATR_SRC_ADDR_LOW);
+	writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
+	writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
+	writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
+	writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
+
+	debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
+	       src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr,
+	       ((u64)1) << window_size, trsl_param);
+}
+
+static void xr3pci_setup_atr(void)
+{
+	/* setup PCIe to CPU address translation tables */
+	unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
+
+	/* forward all writes from PCIe to GIC V2M (used for MSI) */
+	xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START,
+			     JUNO_V2M_MSI_SIZE, XR3PCI_ATR_TRSLID_AXIDEVICE);
+
+	base += XR3PCI_ATR_TABLE_SIZE;
+
+	/* PCIe devices can write anywhere in memory */
+	xr3pci_set_atr_entry(base, PHYS_SDRAM_1, PHYS_SDRAM_1,
+			     31 /* grant access to all RAM under 4GB */,
+			     XR3PCI_ATR_TRSLID_AXIMEMORY);
+	base += XR3PCI_ATR_TABLE_SIZE;
+	xr3pci_set_atr_entry(base, PHYS_SDRAM_2, PHYS_SDRAM_2,
+			     XR3_PCI_MEMSPACE64_SIZE,
+			     XR3PCI_ATR_TRSLID_AXIMEMORY);
+
+
+	/* setup CPU to PCIe address translation table */
+	base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0;
+
+	/* setup ECAM space to bus configuration interface */
+	xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE,
+			     XR3PCI_ATR_TRSLID_PCIE_CONF);
+
+	base += XR3PCI_ATR_TABLE_SIZE;
+
+	/* setup IO space translation */
+	xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,
+			     XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
+
+	base += XR3PCI_ATR_TABLE_SIZE;
+
+	/* setup 32bit MEM space translation */
+	xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE_START, XR3_PCI_MEMSPACE_START,
+			     XR3_PCI_MEMSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
+
+	base += XR3PCI_ATR_TABLE_SIZE;
+
+	/* setup 64bit MEM space translation */
+	xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE64_START, XR3_PCI_MEMSPACE64_START,
+			     XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
+}
+
+static void xr3pci_init(void)
+{
+	u32 val;
+	int timeout = 200;
+
+	/* Initialise the XpressRICH3 PCIe host bridge */
+
+	/* add credits */
+	writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS);
+	writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS + 4);
+	/* allow ECRC */
+	writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);
+	/* setup the correct class code for the host bridge */
+	writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
+
+	/* reset phy and root complex */
+	writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC,
+	       XR3_RESET_BASE + JUNO_RESET_CTRL);
+
+	do {
+		mdelay(1);
+		val = readl(XR3_RESET_BASE + JUNO_RESET_STATUS);
+	} while (--timeout &&
+		(val & JUNO_RESET_STATUS_MASK) != JUNO_RESET_STATUS_MASK);
+
+	if (!timeout) {
+		printf("PCI XR3 Root complex reset timed out\n");
+		return;
+	}
+
+	/* Wait for the link to train */
+	mdelay(20);
+	timeout = 20;
+
+	do {
+		mdelay(1);
+		val = readl(XR3_CONFIG_BASE + XR3PCI_BASIC_STATUS);
+	} while (--timeout && !(val & XR3PCI_BS_LINK_MASK));
+
+	if (!(val & XR3PCI_BS_LINK_MASK)) {
+		printf("Failed to negotiate a link!\n");
+		return;
+	}
+
+	printf("PCIe XR3 Host Bridge enabled: x%d link (Gen %d)\n",
+	       val & XR3PCI_BS_LINK_MASK, (val & XR3PCI_BS_GEN_MASK) >> 8);
+
+	xr3pci_setup_atr();
+}
+
+void vexpress64_pcie_init(void)
+{
+	/* Initialise and configure the PCIe host bridge. */
+	xr3pci_init();
+
+	/* Register the now ECAM complaint PCIe host controller with U-Boot. */
+	pci_init();
+}
diff --git a/roms/u-boot/board/armltd/vexpress64/pcie.h b/roms/u-boot/board/armltd/vexpress64/pcie.h
new file mode 100644
index 000000000..14642f4f5
--- /dev/null
+++ b/roms/u-boot/board/armltd/vexpress64/pcie.h
@@ -0,0 +1,6 @@
+#ifndef __VEXPRESS64_PCIE_H__
+#define __VEXPRESS64_PCIE_H__
+
+void vexpress64_pcie_init(void);
+
+#endif /* __VEXPRESS64_PCIE_H__ */
diff --git a/roms/u-boot/board/armltd/vexpress64/vexpress64.c b/roms/u-boot/board/armltd/vexpress64/vexpress64.c
new file mode 100644
index 000000000..2e4260286
--- /dev/null
+++ b/roms/u-boot/board/armltd/vexpress64/vexpress64.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ * Sharma Bhupesh <bhupesh.sharma@freescale.com>
+ */
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include "pcie.h"
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pl01x_serial_plat serial_plat = {
+	.base = V2M_UART0,
+	.type = TYPE_PL011,
+	.clock = CONFIG_PL011_CLOCK,
+};
+
+U_BOOT_DRVINFO(vexpress_serials) = {
+	.name = "serial_pl01x",
+	.plat = &serial_plat,
+};
+
+static struct mm_region vexpress64_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = vexpress64_mem_map;
+
+/* This function gets replaced by platforms supporting PCIe.
+ * The replacement function, eg. on Juno, initialises the PCIe bus.
+ */
+__weak void vexpress64_pcie_init(void)
+{
+}
+
+int board_init(void)
+{
+	vexpress64_pcie_init();
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#ifdef PHYS_SDRAM_2
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD
+#define JUNO_FLASH_SEC_SIZE	(256 * 1024)
+static phys_addr_t find_dtb_in_nor_flash(const char *partname)
+{
+	phys_addr_t sector = CONFIG_SYS_FLASH_BASE;
+	int i;
+
+	for (i = 0;
+	     i < CONFIG_SYS_MAX_FLASH_SECT;
+	     i++, sector += JUNO_FLASH_SEC_SIZE) {
+		int len = strlen(partname) + 1;
+		int offs;
+		phys_addr_t imginfo;
+		u32 reg;
+
+		reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04);
+                /* This makes up the string "HSLFTOOF" flash footer */
+		if (reg != 0x464F4F54U)
+			continue;
+		reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08);
+                if (reg != 0x464C5348U)
+			continue;
+
+		for (offs = 0; offs < 32; offs += 4, len -= 4) {
+			reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs);
+			if (strncmp(partname + offs, (char *)&reg,
+			            len > 4 ? 4 : len))
+				break;
+
+			if (len > 4)
+				continue;
+
+			reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10);
+			imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
+			reg = readl(imginfo + 0x54);
+
+			return CONFIG_SYS_FLASH_BASE +
+			       reg * JUNO_FLASH_SEC_SIZE;
+		}
+	}
+
+	printf("No DTB found\n");
+
+	return ~0;
+}
+
+void *board_fdt_blob_setup(void)
+{
+	phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
+
+	if (fdt_rom_addr == ~0UL)
+		return NULL;
+
+	return (void *)fdt_rom_addr;
+}
+#endif
+
+/* Actual reset is done via PSCI. */
+void reset_cpu(void)
+{
+}
+
+/*
+ * Board specific ethernet initialization routine.
+ */
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+#ifndef CONFIG_DM_ETH
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+#endif
+	return rc;
+}
diff --git a/roms/u-boot/board/aspeed/evb_ast2500/Kconfig b/roms/u-boot/board/aspeed/evb_ast2500/Kconfig
new file mode 100644
index 000000000..73a8ae85f
--- /dev/null
+++ b/roms/u-boot/board/aspeed/evb_ast2500/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_EVB_AST2500
+
+config SYS_BOARD
+	default "evb_ast2500"
+
+config SYS_VENDOR
+	default "aspeed"
+
+config SYS_CONFIG_NAME
+	default "evb_ast2500"
+
+endif
diff --git a/roms/u-boot/board/aspeed/evb_ast2500/MAINTAINERS b/roms/u-boot/board/aspeed/evb_ast2500/MAINTAINERS
new file mode 100644
index 000000000..7c3c2b5e0
--- /dev/null
+++ b/roms/u-boot/board/aspeed/evb_ast2500/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB AST2500 BOARD
+M:	Maxim Sloyko <maxims@google.com>
+S:	Maintained
+F:	board/aspeed/evb_ast2500/
+F:	include/configs/evb_ast2500.h
+F:	configs/evb-ast2500_defconfig
diff --git a/roms/u-boot/board/aspeed/evb_ast2500/Makefile b/roms/u-boot/board/aspeed/evb_ast2500/Makefile
new file mode 100644
index 000000000..456409829
--- /dev/null
+++ b/roms/u-boot/board/aspeed/evb_ast2500/Makefile
@@ -0,0 +1 @@
+obj-y += evb_ast2500.o
diff --git a/roms/u-boot/board/aspeed/evb_ast2500/evb_ast2500.c b/roms/u-boot/board/aspeed/evb_ast2500/evb_ast2500.c
new file mode 100644
index 000000000..ed162c409
--- /dev/null
+++ b/roms/u-boot/board/aspeed/evb_ast2500/evb_ast2500.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+#include <common.h>
diff --git a/roms/u-boot/board/aspeed/evb_ast2600/Kconfig b/roms/u-boot/board/aspeed/evb_ast2600/Kconfig
new file mode 100644
index 000000000..42008cd03
--- /dev/null
+++ b/roms/u-boot/board/aspeed/evb_ast2600/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_EVB_AST2600
+
+config SYS_BOARD
+	default "evb_ast2600"
+
+config SYS_VENDOR
+	default "aspeed"
+
+config SYS_CONFIG_NAME
+	default "evb_ast2600"
+
+endif
diff --git a/roms/u-boot/board/aspeed/evb_ast2600/MAINTAINERS b/roms/u-boot/board/aspeed/evb_ast2600/MAINTAINERS
new file mode 100644
index 000000000..e83aae5d6
--- /dev/null
+++ b/roms/u-boot/board/aspeed/evb_ast2600/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB AST2600 BOARD
+M:	Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
+S:	Maintained
+F:	board/aspeed/evb_ast2600/
+F:	include/configs/evb_ast2600.h
+F:	configs/evb-ast2600_defconfig
diff --git a/roms/u-boot/board/aspeed/evb_ast2600/Makefile b/roms/u-boot/board/aspeed/evb_ast2600/Makefile
new file mode 100644
index 000000000..9291db6ee
--- /dev/null
+++ b/roms/u-boot/board/aspeed/evb_ast2600/Makefile
@@ -0,0 +1 @@
+obj-y += evb_ast2600.o
diff --git a/roms/u-boot/board/aspeed/evb_ast2600/evb_ast2600.c b/roms/u-boot/board/aspeed/evb_ast2600/evb_ast2600.c
new file mode 100644
index 000000000..e6dc8c795
--- /dev/null
+++ b/roms/u-boot/board/aspeed/evb_ast2600/evb_ast2600.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#include <common.h>
diff --git a/roms/u-boot/board/astro/mcf5373l/Kconfig b/roms/u-boot/board/astro/mcf5373l/Kconfig
new file mode 100644
index 000000000..a7c04cef8
--- /dev/null
+++ b/roms/u-boot/board/astro/mcf5373l/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ASTRO_MCF5373L
+
+config SYS_CPU
+	default "mcf532x"
+
+config SYS_BOARD
+	default "mcf5373l"
+
+config SYS_VENDOR
+	default "astro"
+
+config SYS_CONFIG_NAME
+	default "astro_mcf5373l"
+
+endif
diff --git a/roms/u-boot/board/astro/mcf5373l/MAINTAINERS b/roms/u-boot/board/astro/mcf5373l/MAINTAINERS
new file mode 100644
index 000000000..6c23da719
--- /dev/null
+++ b/roms/u-boot/board/astro/mcf5373l/MAINTAINERS
@@ -0,0 +1,6 @@
+MCF5373L BOARD
+M:	Wolfgang Wegner <w.wegner@astro-kom.de>
+S:	Maintained
+F:	board/astro/mcf5373l/
+F:	include/configs/astro_mcf5373l.h
+F:	configs/astro_mcf5373l_defconfig
diff --git a/roms/u-boot/board/astro/mcf5373l/Makefile b/roms/u-boot/board/astro/mcf5373l/Makefile
new file mode 100644
index 000000000..d3ea0d06a
--- /dev/null
+++ b/roms/u-boot/board/astro/mcf5373l/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= mcf5373l.o fpga.o
diff --git a/roms/u-boot/board/astro/mcf5373l/astro.h b/roms/u-boot/board/astro/mcf5373l/astro.h
new file mode 100644
index 000000000..b55a6f785
--- /dev/null
+++ b/roms/u-boot/board/astro/mcf5373l/astro.h
@@ -0,0 +1,44 @@
+#ifndef __ASTRO_H__
+#define __ASTRO_H__
+
+/* in mcf5373l.c */
+int rs_serial_init(int port, int baud);
+void astro_put_char(char ch);
+int astro_is_char(void);
+int astro_get_char(void);
+
+/* in fpga.c */
+int astro5373l_altera_load(void);
+int astro5373l_xilinx_load(void);
+
+/* data structures used for communication (update.c) */
+typedef struct card_id {
+	char card_type;
+	char hardware_version;
+	char software_version;
+	char software_subversion;	/* " ","a".."z" */
+	char fpga_version_altera;
+	char fpga_version_xilinx;
+} card_id_t;
+
+typedef struct {
+	unsigned char mode;
+	unsigned char deviation;
+	unsigned short freq;
+} __attribute__ ((packed)) output_params_t;
+
+typedef struct {
+	unsigned short satfreq;
+	unsigned char satdatallg;
+	unsigned short symbolrate;
+	unsigned char viterbirate;
+	unsigned char symbolrate_l;
+	output_params_t output_params;
+	unsigned char reserve;
+	unsigned char card_error;
+	unsigned short dummy_ts_id;
+	unsigned char dummy_pat_ver;
+	unsigned char dummy_sdt_ver;
+} __attribute__ ((packed)) parameters_t;
+
+#endif /* __ASTRO_H__ */
diff --git a/roms/u-boot/board/astro/mcf5373l/fpga.c b/roms/u-boot/board/astro/mcf5373l/fpga.c
new file mode 100644
index 000000000..ef82f0660
--- /dev/null
+++ b/roms/u-boot/board/astro/mcf5373l/fpga.c
@@ -0,0 +1,407 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2006
+ * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH,
+ * w.wegner@astro-kom.de
+ *
+ * based on the files by
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ * and
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ */
+
+/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
+
+#include <common.h>
+#include <console.h>
+#include <watchdog.h>
+#include <altera.h>
+#include <ACEX1K.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/immap_5329.h>
+#include <asm/io.h>
+#include "fpga.h"
+
+int altera_pre_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char tmp_char;
+	unsigned short tmp_short;
+
+	/* first, set the required pins to GPIO function */
+	/* PAR_T0IN -> GPIO */
+	tmp_char = readb(&gpiop->par_timer);
+	tmp_char &= 0xfc;
+	writeb(tmp_char, &gpiop->par_timer);
+	/* all QSPI pins -> GPIO */
+	writew(0x0000, &gpiop->par_qspi);
+	/* U0RTS, U0CTS -> GPIO */
+	tmp_short = __raw_readw(&gpiop->par_uart);
+	tmp_short &= 0xfff3;
+	__raw_writew(tmp_short, &gpiop->par_uart);
+	/* all PWM pins -> GPIO */
+	writeb(0x00, &gpiop->par_pwm);
+	/* next, set data direction registers */
+	writeb(0x01, &gpiop->pddr_timer);
+	writeb(0x25, &gpiop->pddr_qspi);
+	writeb(0x0c, &gpiop->pddr_uart);
+	writeb(0x04, &gpiop->pddr_pwm);
+
+	/* ensure other SPI peripherals are deselected */
+	writeb(0x08, &gpiop->ppd_uart);
+	writeb(0x38, &gpiop->ppd_qspi);
+
+	/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
+	writeb(0xFB, &gpiop->pclrr_uart);
+	/* enable Altera configuration by clearing QSPI_CS2 and DT0IN */
+	writeb(0xFE, &gpiop->pclrr_timer);
+	writeb(0xDF, &gpiop->pclrr_qspi);
+	return FPGA_SUCCESS;
+}
+
+/* Set the state of CONFIG Pin */
+int altera_config_fn(int assert_config, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert_config)
+		writeb(0x04, &gpiop->ppd_uart);
+	else
+		writeb(0xFB, &gpiop->pclrr_uart);
+	return FPGA_SUCCESS;
+}
+
+/* Returns the state of STATUS Pin */
+int altera_status_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (readb(&gpiop->ppd_pwm) & 0x08)
+		return FPGA_FAIL;
+	return FPGA_SUCCESS;
+}
+
+/* Returns the state of CONF_DONE Pin */
+int altera_done_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (readb(&gpiop->ppd_pwm) & 0x20)
+		return FPGA_FAIL;
+	return FPGA_SUCCESS;
+}
+
+/*
+ * writes the complete buffer to the FPGA
+ * writing the complete buffer in one function is much faster,
+ * then calling it for every bit
+ */
+int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
+{
+	size_t bytecount = 0;
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char *data = (unsigned char *)buf;
+	unsigned char val = 0;
+	int i;
+	int len_40 = len / 40;
+
+	while (bytecount < len) {
+		val = data[bytecount++];
+		i = 8;
+		do {
+			writeb(0xFB, &gpiop->pclrr_qspi);
+			if (val & 0x01)
+				writeb(0x01, &gpiop->ppd_qspi);
+			else
+				writeb(0xFE, &gpiop->pclrr_qspi);
+			writeb(0x04, &gpiop->ppd_qspi);
+			val >>= 1;
+			i--;
+		} while (i > 0);
+
+		if (bytecount % len_40 == 0) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+			WATCHDOG_RESET();
+#endif
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+			putc('.');	/* let them know we are alive */
+#endif
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+			if (ctrlc())
+				return FPGA_FAIL;
+#endif
+		}
+	}
+	return FPGA_SUCCESS;
+}
+
+/* called, when programming is aborted */
+int altera_abort_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	writeb(0x20, &gpiop->ppd_qspi);
+	writeb(0x08, &gpiop->ppd_uart);
+	return FPGA_SUCCESS;
+}
+
+/* called, when programming was succesful */
+int altera_post_fn(int cookie)
+{
+	return altera_abort_fn(cookie);
+}
+
+/*
+ * Note that these are pointers to code that is in Flash. They will be
+ * relocated at runtime.
+ * FIXME: relocation not yet working for coldfire, see below!
+ */
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+	altera_pre_fn,
+	altera_config_fn,
+	altera_status_fn,
+	altera_done_fn,
+	altera_write_fn,
+	altera_abort_fn,
+	altera_post_fn
+};
+
+Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
+	{Altera_CYC2,
+	 passive_serial,
+	 85903,
+	 (void *)&altera_fns,
+	 NULL,
+	 0}
+};
+
+/* Initialize the fpga.  Return 1 on success, 0 on failure. */
+int astro5373l_altera_load(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		/*
+		 * I did not yet manage to get relocation work properly,
+		 * so set stuff here instead of static initialisation:
+		 */
+		altera_fns.pre = altera_pre_fn;
+		altera_fns.config = altera_config_fn;
+		altera_fns.status = altera_status_fn;
+		altera_fns.done = altera_done_fn;
+		altera_fns.write = altera_write_fn;
+		altera_fns.abort = altera_abort_fn;
+		altera_fns.post = altera_post_fn;
+		altera_fpga[i].iface_fns = (void *)&altera_fns;
+		fpga_add(fpga_altera, &altera_fpga[i]);
+	}
+	return 1;
+}
+
+/* Set the FPGA's PROG_B line to the specified level */
+int xilinx_pgm_config_fn(int assert, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert)
+		writeb(0xFB, &gpiop->pclrr_uart);
+	else
+		writeb(0x04, &gpiop->ppd_uart);
+	return assert;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+int xilinx_init_config_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	return (readb(&gpiop->ppd_pwm) & 0x08) == 0;
+}
+
+/* Test the state of the active-high FPGA DONE pin */
+int xilinx_done_config_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	return (readb(&gpiop->ppd_pwm) & 0x20) >> 5;
+}
+
+/* Abort an FPGA operation */
+int xilinx_abort_config_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	/* ensure all SPI peripherals and FPGAs are deselected */
+	writeb(0x08, &gpiop->ppd_uart);
+	writeb(0x01, &gpiop->ppd_timer);
+	writeb(0x38, &gpiop->ppd_qspi);
+	return FPGA_FAIL;
+}
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int xilinx_pre_config_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char tmp_char;
+	unsigned short tmp_short;
+
+	/* first, set the required pins to GPIO function */
+	/* PAR_T0IN -> GPIO */
+	tmp_char = readb(&gpiop->par_timer);
+	tmp_char &= 0xfc;
+	writeb(tmp_char, &gpiop->par_timer);
+	/* all QSPI pins -> GPIO */
+	writew(0x0000, &gpiop->par_qspi);
+	/* U0RTS, U0CTS -> GPIO */
+	tmp_short = __raw_readw(&gpiop->par_uart);
+	tmp_short &= 0xfff3;
+	__raw_writew(tmp_short, &gpiop->par_uart);
+	/* all PWM pins -> GPIO */
+	writeb(0x00, &gpiop->par_pwm);
+	/* next, set data direction registers */
+	writeb(0x01, &gpiop->pddr_timer);
+	writeb(0x25, &gpiop->pddr_qspi);
+	writeb(0x0c, &gpiop->pddr_uart);
+	writeb(0x04, &gpiop->pddr_pwm);
+
+	/* ensure other SPI peripherals are deselected */
+	writeb(0x08, &gpiop->ppd_uart);
+	writeb(0x38, &gpiop->ppd_qspi);
+	writeb(0x01, &gpiop->ppd_timer);
+
+	/* CONFIG = 0, STATUS = 0 -> FPGA in reset state */
+	writeb(0xFB, &gpiop->pclrr_uart);
+	/* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */
+	writeb(0xF7, &gpiop->pclrr_uart);
+	writeb(0xDF, &gpiop->pclrr_qspi);
+	return 0;
+}
+
+/*
+ * FPGA post configuration function. Should perform a test if FPGA is running.
+ */
+int xilinx_post_config_fn(int cookie)
+{
+	int rc = 0;
+
+	/*
+	 * no test yet
+	 */
+	return rc;
+}
+
+int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert_clk)
+		writeb(0x04, &gpiop->ppd_qspi);
+	else
+		writeb(0xFB, &gpiop->pclrr_qspi);
+	return assert_clk;
+}
+
+int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert_write)
+		writeb(0x01, &gpiop->ppd_qspi);
+	else
+		writeb(0xFE, &gpiop->pclrr_qspi);
+	return assert_write;
+}
+
+int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
+{
+	size_t bytecount = 0;
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char *data = (unsigned char *)buf;
+	unsigned char val = 0;
+	int i;
+	int len_40 = len / 40;
+
+	for (bytecount = 0; bytecount < len; bytecount++) {
+		val = *(data++);
+		for (i = 8; i > 0; i--) {
+			writeb(0xFB, &gpiop->pclrr_qspi);
+			if (val & 0x80)
+				writeb(0x01, &gpiop->ppd_qspi);
+			else
+				writeb(0xFE, &gpiop->pclrr_qspi);
+			writeb(0x04, &gpiop->ppd_qspi);
+			val <<= 1;
+		}
+		if (bytecount % len_40 == 0) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+			WATCHDOG_RESET();
+#endif
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+			putc('.');	/* let them know we are alive */
+#endif
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+			if (ctrlc())
+				return FPGA_FAIL;
+#endif
+		}
+	}
+	return FPGA_SUCCESS;
+}
+
+/*
+ * Note that these are pointers to code that is in Flash.  They will be
+ * relocated at runtime.
+ * FIXME: relocation not yet working for coldfire, see below!
+ */
+xilinx_spartan3_slave_serial_fns xilinx_fns = {
+	xilinx_pre_config_fn,
+	xilinx_pgm_config_fn,
+	xilinx_clk_config_fn,
+	xilinx_init_config_fn,
+	xilinx_done_config_fn,
+	xilinx_wr_config_fn,
+	0,
+	xilinx_fastwr_config_fn
+};
+
+xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+	{xilinx_spartan3,
+	 slave_serial,
+	 XILINX_XC3S4000_SIZE,
+	 (void *)&xilinx_fns,
+	 0,
+	 &spartan3_op}
+};
+
+/* Initialize the fpga.  Return 1 on success, 0 on failure. */
+int astro5373l_xilinx_load(void)
+{
+	int i;
+
+	fpga_init();
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		/*
+		 * I did not yet manage to get relocation work properly,
+		 * so set stuff here instead of static initialisation:
+		 */
+		xilinx_fns.pre = xilinx_pre_config_fn;
+		xilinx_fns.pgm = xilinx_pgm_config_fn;
+		xilinx_fns.clk = xilinx_clk_config_fn;
+		xilinx_fns.init = xilinx_init_config_fn;
+		xilinx_fns.done = xilinx_done_config_fn;
+		xilinx_fns.wr = xilinx_wr_config_fn;
+		xilinx_fns.bwr = xilinx_fastwr_config_fn;
+		xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
+		fpga_add(fpga_xilinx, &xilinx_fpga[i]);
+	}
+	return 1;
+}
diff --git a/roms/u-boot/board/astro/mcf5373l/mcf5373l.c b/roms/u-boot/board/astro/mcf5373l/mcf5373l.c
new file mode 100644
index 000000000..3e2f79a1c
--- /dev/null
+++ b/roms/u-boot/board/astro/mcf5373l/mcf5373l.c
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
+ */
+
+#include <common.h>
+#include <init.h>
+#include <serial.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/global_data.h>
+#include <asm/m5329.h>
+#include <asm/immap_5329.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+/* needed for astro bus: */
+#include <asm/uart.h>
+#include "astro.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+extern void uart_port_conf(void);
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("ASTRO MCF5373L (Urmel) Board\n");
+	return 0;
+}
+
+int dram_init(void)
+{
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+	sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
+
+	/*
+	 * GPIO configuration for bus should be set correctly from reset,
+	 * so we do not care! First, set up address space: at this point,
+	 * we should be running from internal SRAM;
+	 * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
+	 * and do not care where it is
+	 */
+	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
+			&sdp->cs0);
+	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
+			&sdp->cs1);
+	/*
+	 * I am not sure from the data sheet, but it seems burst length
+	 * has to be 8 for the 16 bit data bus we use;
+	 * so these values are for BL = 8
+	 */
+	__raw_writel(0x33211530, &sdp->cfg1);
+	__raw_writel(0x56570000, &sdp->cfg2);
+	/* send PrechargeALL, REF and IREF remain cleared! */
+	__raw_writel(0xE1462C02, &sdp->ctrl);
+	udelay(1);
+	/* refresh SDRAM twice */
+	__raw_writel(0xE1462C04, &sdp->ctrl);
+	udelay(1);
+	__raw_writel(0xE1462C04, &sdp->ctrl);
+	/* init MR  */
+	__raw_writel(0x008D0000, &sdp->mode);
+	/* initialize EMR */
+	__raw_writel(0x80010000, &sdp->mode);
+	/* wait until DLL is locked */
+	udelay(1);
+	/*
+	 * enable automatic refresh, lock mode register,
+	 * clear iref and ipall
+	 */
+	__raw_writel(0x71462C00, &sdp->ctrl);
+	/* Dummy write to start SDRAM */
+	writel(0, CONFIG_SYS_SDRAM_BASE);
+#endif
+
+	/*
+	 * for get_ram_size() to work, both CS areas have to be
+	 * configured, i.e. CS1 has to be explicitely disabled, else
+	 * probing for memory will cause the SDRAM bus to hang!
+	 * (Do not rely on the SDCS register(s) being set to 0x00000000
+	 * during reset as stated in the data sheet.)
+	 */
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				0x80000000 - CONFIG_SYS_SDRAM_BASE);
+
+	return 0;
+}
+
+#define UART_BASE MMAP_UART0
+int rs_serial_init(int port, int baud)
+{
+	uart_t *uart;
+	u32 counter;
+
+	switch (port) {
+	case 0:
+		uart = (uart_t *)(MMAP_UART0);
+		break;
+	case 1:
+		uart = (uart_t *)(MMAP_UART1);
+		break;
+	case 2:
+		uart = (uart_t *)(MMAP_UART2);
+		break;
+	default:
+		uart = (uart_t *)(MMAP_UART0);
+	}
+
+	uart_port_conf();
+
+	/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
+	writeb(UART_UCR_RESET_RX, &uart->ucr);
+	writeb(UART_UCR_RESET_TX, &uart->ucr);
+	writeb(UART_UCR_RESET_ERROR, &uart->ucr);
+	writeb(UART_UCR_RESET_MR, &uart->ucr);
+	__asm__ ("nop");
+
+	writeb(0, &uart->uimr);
+
+	/* write to CSR: RX/TX baud rate from timers */
+	writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
+
+	writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
+	writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
+
+	/* Setting up BaudRate */
+	counter = (u32) (gd->bus_clk / (baud));
+	counter >>= 5;
+
+	/* write to CTUR: divide counter upper byte */
+	writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
+	/* write to CTLR: divide counter lower byte */
+	writeb((u8) (counter & 0x00ff), &uart->ubg2);
+
+	writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
+
+	return 0;
+}
+
+void astro_put_char(char ch)
+{
+	uart_t *uart;
+	unsigned long timer;
+
+	uart = (uart_t *)(MMAP_UART0);
+	/*
+	 * Wait for last character to go. Timeout of 6ms should
+	 * be enough for our lowest baud rate of 2400.
+	 */
+	timer = get_timer(0);
+	while (get_timer(timer) < 6) {
+		if (readb(&uart->usr) & UART_USR_TXRDY)
+			break;
+	}
+	writeb(ch, &uart->utb);
+
+	return;
+}
+
+int astro_is_char(void)
+{
+	uart_t *uart;
+
+	uart = (uart_t *)(MMAP_UART0);
+	return readb(&uart->usr) & UART_USR_RXRDY;
+}
+
+int astro_get_char(void)
+{
+	uart_t *uart;
+
+	uart = (uart_t *)(MMAP_UART0);
+	while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
+	return readb(&uart->urb);
+}
+
+int misc_init_r(void)
+{
+	int retval = 0;
+
+	puts("Configure Xilinx FPGA...");
+	retval = astro5373l_xilinx_load();
+	if (!retval) {
+		puts("failed!\n");
+		return retval;
+	}
+	puts("done\n");
+
+	puts("Configure Altera FPGA...");
+	retval = astro5373l_altera_load();
+	if (!retval) {
+		puts("failed!\n");
+		return retval;
+	}
+	puts("done\n");
+
+	return retval;
+}
diff --git a/roms/u-boot/board/atmark-techno/armadillo-800eva/Kconfig b/roms/u-boot/board/atmark-techno/armadillo-800eva/Kconfig
new file mode 100644
index 000000000..cd37dd486
--- /dev/null
+++ b/roms/u-boot/board/atmark-techno/armadillo-800eva/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ARMADILLO_800EVA
+
+config SYS_BOARD
+	default "armadillo-800eva"
+
+config SYS_VENDOR
+	default "atmark-techno"
+
+config SYS_CONFIG_NAME
+	default "armadillo-800eva"
+
+endif
diff --git a/roms/u-boot/board/atmark-techno/armadillo-800eva/MAINTAINERS b/roms/u-boot/board/atmark-techno/armadillo-800eva/MAINTAINERS
new file mode 100644
index 000000000..6f547d82e
--- /dev/null
+++ b/roms/u-boot/board/atmark-techno/armadillo-800eva/MAINTAINERS
@@ -0,0 +1,6 @@
+ARMADILLO-800EVA BOARD
+M:	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+S:	Maintained
+F:	board/atmark-techno/armadillo-800eva/
+F:	include/configs/armadillo-800eva.h
+F:	configs/armadillo-800eva_defconfig
diff --git a/roms/u-boot/board/atmark-techno/armadillo-800eva/Makefile b/roms/u-boot/board/atmark-techno/armadillo-800eva/Makefile
new file mode 100644
index 000000000..87e8ca5e6
--- /dev/null
+++ b/roms/u-boot/board/atmark-techno/armadillo-800eva/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2012  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+
+obj-y	+= armadillo-800eva.o
+
diff --git a/roms/u-boot/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/roms/u-boot/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
new file mode 100644
index 000000000..c1c3dfd3d
--- /dev/null
+++ b/roms/u-boot/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+
+#define s_init_wait(cnt) \
+		({	\
+			volatile u32 i = 0x10000 * cnt;	\
+			while (i > 0)	\
+				i--;	\
+		})
+
+#define USBCR1 0xE605810A
+
+void s_init(void)
+{
+	struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
+	struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
+	struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
+	struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
+	struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
+	struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
+
+	/* Watchdog init */
+	writew(0xA500, &rwdt0->rwtcsra0);
+	writew(0xA500, &rwdt1->rwtcsra0);
+
+	/* CPG */
+	writel(0xFF800080, &cpg->rmstpcr4);
+	writel(0xFF800080, &cpg->smstpcr4);
+
+	/* USB clock */
+	writel(0x00000080, &cpg->usbckcr);
+	s_init_wait(1);
+
+	/* USBCR1 */
+	writew(0x0710, USBCR1);
+
+	/* FRQCR */
+	writel(0x00000000, &cpg->frqcrb);
+	writel(0x62030533, &cpg->frqcra);
+	writel(0x208A354E, &cpg->frqcrc);
+	writel(0x80331050, &cpg->frqcrb);
+	s_init_wait(1);
+
+	writel(0x00000000, &cpg->frqcrd);
+	s_init_wait(1);
+
+	/* SUBClk */
+	writel(0x0000010B, &cpg->subckcr);
+
+	/* PLL */
+	writel(0x00004004, &cpg->pllc01cr);
+	s_init_wait(1);
+
+	writel(0xa0000000, &cpg->pllc2cr);
+	s_init_wait(2);
+
+	/* BSC */
+	writel(0x0000001B, &bsc->cmncr);
+
+	writel(0x20000000, &dbsc->dbcmd);
+	writel(0x10009C40, &dbsc->dbcmd);
+	s_init_wait(1);
+
+	writel(0x00000007, &dbsc->dbkind);
+	writel(0x0E030A02, &dbsc->dbconf0);
+	writel(0x00000001, &dbsc->dbphytype);
+	writel(0x00000000, &dbsc->dbbl);
+	writel(0x00000006, &dbsc->dbtr0);
+	writel(0x00000005, &dbsc->dbtr1);
+	writel(0x00000000, &dbsc->dbtr2);
+	writel(0x00000006, &dbsc->dbtr3);
+	writel(0x00080006, &dbsc->dbtr4);
+	writel(0x00000015, &dbsc->dbtr5);
+	writel(0x0000000f, &dbsc->dbtr6);
+	writel(0x00000004, &dbsc->dbtr7);
+	writel(0x00000018, &dbsc->dbtr8);
+	writel(0x00000006, &dbsc->dbtr9);
+	writel(0x00000006, &dbsc->dbtr10);
+	writel(0x0000000F, &dbsc->dbtr11);
+	writel(0x0000000D, &dbsc->dbtr12);
+	writel(0x000000A0, &dbsc->dbtr13);
+	writel(0x000A0003, &dbsc->dbtr14);
+	writel(0x00000003, &dbsc->dbtr15);
+	writel(0x40005005, &dbsc->dbtr16);
+	writel(0x0C0C0000, &dbsc->dbtr17);
+	writel(0x00000200, &dbsc->dbtr18);
+	writel(0x00000040, &dbsc->dbtr19);
+	writel(0x00000001, &dbsc->dbrnk0);
+	writel(0x00000110, &dbsc->dbdficnt);
+	writel(0x00000101, &ddrp->funcctrl);
+	writel(0x00000001, &ddrp->dllctrl);
+	writel(0x00000186, &ddrp->zqcalctrl);
+	writel(0xB3440051, &ddrp->zqodtctrl);
+	writel(0x94449443, &ddrp->rdctrl);
+	writel(0x000000C0, &ddrp->rdtmg);
+	writel(0x00000101, &ddrp->fifoinit);
+	writel(0x02060506, &ddrp->outctrl);
+	writel(0x00004646, &ddrp->dqcalofs1);
+	writel(0x00004646, &ddrp->dqcalofs2);
+	writel(0x800000aa, &ddrp->dqcalexp);
+	writel(0x00000000, &ddrp->dllctrl);
+	writel(0x00000000, DDRPNCNT);
+
+	writel(0x0000000C, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00000002, DDRPNCNT);
+
+	writel(0x0000000C, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00000187, &ddrp->zqcalctrl);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00000010, &dbsc->dbdficnt);
+	writel(0x02060507, &ddrp->outctrl);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x21009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x11000044, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x2A000000, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x2B000000, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+
+	writel(0x29000004, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+
+	writel(0x28001520, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x03000200, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x000001FF, &dbsc->dbrfcnf0);
+	writel(0x00010C30, &dbsc->dbrfcnf1);
+	writel(0x00000000, &dbsc->dbrfcnf2);
+
+	writel(0x00000001, &dbsc->dbrfen);
+	writel(0x00000001, &dbsc->dbacen);
+
+	/* BSC */
+	writel(0x00410400, &bsc->cs0bcr);
+	writel(0x00410400, &bsc->cs2bcr);
+	writel(0x00410400, &bsc->cs5bbcr);
+	writel(0x02CB0400, &bsc->cs6abcr);
+
+	writel(0x00000440, &bsc->cs0wcr);
+	writel(0x00000440, &bsc->cs2wcr);
+	writel(0x00000240, &bsc->cs5bwcr);
+	writel(0x00000240, &bsc->cs6awcr);
+
+	writel(0x00000005, &bsc->rbwtcnt);
+	writel(0x00000002, &bsc->cs0wcr2);
+	writel(0x00000002, &bsc->cs2wcr2);
+	writel(0x00000002, &bsc->cs4wcr2);
+}
+
+#define GPIO_ICCR (0xE60581A0)
+#define ICCR_15BIT (1 << 15) /* any time 1 */
+#define IIC0_CONTA (1 << 7)
+#define IIC0_CONTB (1 << 6)
+#define IIC1_CONTA (1 << 5)
+#define IIC1_CONTB (1 << 4)
+#define IIC0_PS33E (1 << 1)
+#define IIC1_PS33E (1 << 0)
+#define GPIO_ICCR_DATA	\
+		(ICCR_15BIT |	\
+		IIC0_CONTA | IIC0_CONTB | IIC1_CONTA |	\
+		IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
+
+#define MSTPCR1         0xE6150134
+#define TMU0_MSTP125    (1 << 25)
+#define I2C0_MSTP116    (1 << 16)
+
+#define MSTPCR3         0xE615013C
+#define I2C1_MSTP323    (1 << 23)
+#define GETHER_MSTP309	(1 << 9)
+
+#define GPIO_SCIFA1_TXD (0xE60520C4)
+#define GPIO_SCIFA1_RXD (0xE60520C3)
+
+int board_early_init_f(void)
+{
+	/* TMU */
+	clrbits_le32(MSTPCR1, TMU0_MSTP125);
+
+	/* GETHER */
+	clrbits_le32(MSTPCR3, GETHER_MSTP309);
+
+	/* I2C 0/1 */
+	clrbits_le32(MSTPCR1, I2C0_MSTP116);
+	clrbits_le32(MSTPCR3, I2C1_MSTP323);
+
+	/* SCIFA1 */
+	writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */
+	writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */
+
+	/* IICCR */
+	writew(GPIO_ICCR_DATA, GPIO_ICCR);
+
+	return 0;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+	/* board id for linux */
+	gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO800EVA;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7740_pinmux_init();
+
+	/* GETHER Enable */
+	gpio_request(GPIO_FN_ET_CRS, NULL);
+	gpio_request(GPIO_FN_ET_MDC, NULL);
+	gpio_request(GPIO_FN_ET_MDIO, NULL);
+	gpio_request(GPIO_FN_ET_TX_ER, NULL);
+	gpio_request(GPIO_FN_ET_RX_ER, NULL);
+	gpio_request(GPIO_FN_ET_ERXD0, NULL);
+	gpio_request(GPIO_FN_ET_ERXD1, NULL);
+	gpio_request(GPIO_FN_ET_ERXD2, NULL);
+	gpio_request(GPIO_FN_ET_ERXD3, NULL);
+	gpio_request(GPIO_FN_ET_TX_CLK, NULL);
+	gpio_request(GPIO_FN_ET_TX_EN, NULL);
+	gpio_request(GPIO_FN_ET_ETXD0, NULL);
+	gpio_request(GPIO_FN_ET_ETXD1, NULL);
+	gpio_request(GPIO_FN_ET_ETXD2, NULL);
+	gpio_request(GPIO_FN_ET_ETXD3, NULL);
+	gpio_request(GPIO_FN_ET_PHY_INT, NULL);
+	gpio_request(GPIO_FN_ET_COL, NULL);
+	gpio_request(GPIO_FN_ET_RX_DV, NULL);
+	gpio_request(GPIO_FN_ET_RX_CLK, NULL);
+
+	gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
+	gpio_direction_output(GPIO_PORT18, 1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/roms/u-boot/board/atmel/at91rm9200ek/Kconfig b/roms/u-boot/board/atmel/at91rm9200ek/Kconfig
new file mode 100644
index 000000000..952351dcd
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91rm9200ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AT91RM9200EK
+
+config SYS_BOARD
+	default "at91rm9200ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91rm9200ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/at91rm9200ek/MAINTAINERS b/roms/u-boot/board/atmel/at91rm9200ek/MAINTAINERS
new file mode 100644
index 000000000..b25bc5802
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91rm9200ek/MAINTAINERS
@@ -0,0 +1,7 @@
+AT91RM9200EK BOARD
+M:	Andreas Bießmann <andreas@biessmann.org>
+S:	Maintained
+F:	board/atmel/at91rm9200ek/
+F:	include/configs/at91rm9200ek.h
+F:	configs/at91rm9200ek_defconfig
+F:	configs/at91rm9200ek_ram_defconfig
diff --git a/roms/u-boot/board/atmel/at91rm9200ek/Makefile b/roms/u-boot/board/atmel/at91rm9200ek/Makefile
new file mode 100644
index 000000000..2d5c28082
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91rm9200ek/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y += at91rm9200ek.o
+obj-y += led.o
diff --git a/roms/u-boot/board/atmel/at91rm9200ek/at91rm9200ek.c b/roms/u-boot/board/atmel/at91rm9200ek/at91rm9200ek.c
new file mode 100644
index 000000000..a314ced5e
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91rm9200ek/at91rm9200ek.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010 Andreas Bießmann <andreas@biessmann.org>
+ *
+ * derived from previous work
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_common.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+int board_init(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+
+	/*
+	 * Correct IRDA resistor problem
+	 * Set PA23_TXD in Output
+	 */
+	writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
+
+	/* arch number of AT91RM9200EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+	return 0;
+}
+
+int dram_init (void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(struct bd_info *bis)
+{
+	return at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
+}
+#endif
diff --git a/roms/u-boot/board/atmel/at91rm9200ek/led.c b/roms/u-boot/board/atmel/at91rm9200ek/led.c
new file mode 100644
index 000000000..a6b4d1fb6
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91rm9200ek/led.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2006
+ * Atmel Nordic AB <www.atmel.com>
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * (C) Copyright 2010
+ * Andreas Bießmann <andreas@biessmann.org>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/at91_pio.h>
+#include <status_led.h>
+
+/* bit mask in PIO port B */
+#define	GREEN_LED	(1<<0)
+#define	YELLOW_LED	(1<<1)
+#define	RED_LED		(1<<2)
+
+void	green_led_on(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+	writel(GREEN_LED, &pio->piob.codr);
+}
+
+void	 yellow_led_on(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+	writel(YELLOW_LED, &pio->piob.codr);
+}
+
+void	 red_led_on(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+	writel(RED_LED, &pio->piob.codr);
+}
+
+void	green_led_off(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+	writel(GREEN_LED, &pio->piob.sodr);
+}
+
+void	yellow_led_off(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+	writel(YELLOW_LED, &pio->piob.sodr);
+}
+
+void	red_led_off(void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+	writel(RED_LED, &pio->piob.sodr);
+}
+
+void coloured_LED_init (void)
+{
+	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+
+	/* Disable peripherals on LEDs */
+	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
+	/* Enable pins as outputs */
+	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
+	/* Turn all LEDs OFF */
+	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
+}
diff --git a/roms/u-boot/board/atmel/at91sam9260ek/Kconfig b/roms/u-boot/board/atmel/at91sam9260ek/Kconfig
new file mode 100644
index 000000000..3844f086b
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9260ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9260EK
+
+config SYS_BOARD
+	default "at91sam9260ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9260ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/at91sam9260ek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9260ek/MAINTAINERS
new file mode 100644
index 000000000..aa7898ef7
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9260ek/MAINTAINERS
@@ -0,0 +1,17 @@
+AT91SAM9260EK BOARD
+M:	Stelian Pop <stelian@popies.net>
+S:	Maintained
+F:	board/atmel/at91sam9260ek/
+F:	include/configs/at91sam9260ek.h
+F:	configs/at91sam9260ek_dataflash_cs0_defconfig
+F:	configs/at91sam9260ek_dataflash_cs1_defconfig
+F:	configs/at91sam9260ek_nandflash_defconfig
+F:	configs/at91sam9g20ek_2mmc_nandflash_defconfig
+F:	configs/at91sam9g20ek_dataflash_cs0_defconfig
+F:	configs/at91sam9g20ek_dataflash_cs1_defconfig
+F:	configs/at91sam9g20ek_mmc_defconfig
+F:	configs/at91sam9g20ek_2mmc_defconfig
+F:	configs/at91sam9g20ek_nandflash_defconfig
+F:	configs/at91sam9xeek_dataflash_cs0_defconfig
+F:	configs/at91sam9xeek_dataflash_cs1_defconfig
+F:	configs/at91sam9xeek_nandflash_defconfig
diff --git a/roms/u-boot/board/atmel/at91sam9260ek/Makefile b/roms/u-boot/board/atmel/at91sam9260ek/Makefile
new file mode 100644
index 000000000..56cac9750
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9260ek/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+
+obj-y	+= at91sam9260ek.o
+obj-$(CONFIG_AT91_LED) += led.o
diff --git a/roms/u-boot/board/atmel/at91sam9260ek/at91sam9260ek.c b/roms/u-boot/board/atmel/at91sam9260ek/at91sam9260ek.c
new file mode 100644
index 000000000..38f97bce2
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9260ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	at91sam9260ek_nand_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(
+		(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
diff --git a/roms/u-boot/board/atmel/at91sam9260ek/led.c b/roms/u-boot/board/atmel/at91sam9260ek/led.c
new file mode 100644
index 000000000..cc6d5d7a0
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9260ek/led.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <status_led.h>
+
+void coloured_LED_init(void)
+{
+	/* Clock is enabled in board_early_init_f() */
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/roms/u-boot/board/atmel/at91sam9261ek/Kconfig b/roms/u-boot/board/atmel/at91sam9261ek/Kconfig
new file mode 100644
index 000000000..2971b3cf9
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9261ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9261EK
+
+config SYS_BOARD
+	default "at91sam9261ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9261ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/at91sam9261ek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9261ek/MAINTAINERS
new file mode 100644
index 000000000..682dfdfbf
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9261ek/MAINTAINERS
@@ -0,0 +1,11 @@
+AT91SAM9261EK BOARD
+M:	Stelian Pop <stelian@popies.net>
+S:	Maintained
+F:	board/atmel/at91sam9261ek/
+F:	include/configs/at91sam9261ek.h
+F:	configs/at91sam9261ek_dataflash_cs0_defconfig
+F:	configs/at91sam9261ek_dataflash_cs3_defconfig
+F:	configs/at91sam9261ek_nandflash_defconfig
+F:	configs/at91sam9g10ek_dataflash_cs0_defconfig
+F:	configs/at91sam9g10ek_dataflash_cs3_defconfig
+F:	configs/at91sam9g10ek_nandflash_defconfig
diff --git a/roms/u-boot/board/atmel/at91sam9261ek/Makefile b/roms/u-boot/board/atmel/at91sam9261ek/Makefile
new file mode 100644
index 000000000..7f5369f43
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9261ek/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+
+obj-y += at91sam9261ek.o
+obj-$(CONFIG_AT91_LED) += led.o
diff --git a/roms/u-boot/board/atmel/at91sam9261ek/at91sam9261ek.c b/roms/u-boot/board/atmel/at91sam9261ek/at91sam9261ek.c
new file mode 100644
index 000000000..0318eeaa9
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -0,0 +1,294 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91sam9261_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
+#include <net.h>
+#include <netdev.h>
+#endif
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9261ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+#ifdef CONFIG_AT91SAM9G10EK
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+		&smc->cs[3].cycle);
+#else
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+#endif
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_MODE_DBW_8 |
+#endif
+		       AT91_SMC_MODE_TDF_CYCLE(2),
+		       &smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
+	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+static void at91sam9261ek_dm9000_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	/* Configure SMC CS2 for DM9000 */
+#ifdef CONFIG_AT91SAM9G10EK
+	writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[2].setup);
+	writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
+		AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
+		&smc->cs[2].pulse);
+	writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
+		&smc->cs[2].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		       AT91_SMC_MODE_EXNW_DISABLE |
+		       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+		       AT91_SMC_MODE_TDF_CYCLE(1),
+		       &smc->cs[2].mode);
+#else
+	writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[2].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
+		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
+		&smc->cs[2].pulse);
+	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
+		&smc->cs[2].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		       AT91_SMC_MODE_EXNW_DISABLE |
+		       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+		       AT91_SMC_MODE_TDF_CYCLE(1),
+		       &smc->cs[2].mode);
+#endif
+
+	/* Configure Reset signal as output */
+	at91_set_gpio_output(AT91_PIN_PC10, 0);
+
+	/* Configure Interrupt pin as input, no pull-up */
+	at91_set_gpio_input(AT91_PIN_PC11, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
+}
+
+static void at91sam9261ek_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
+	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PB9, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PB10, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PB11, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PB12, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PB15, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PB16, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PB17, 0);	/* LCDD12 */
+	at91_set_A_periph(AT91_PIN_PB18, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PB19, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PB20, 0);	/* LCDD15 */
+	at91_set_B_periph(AT91_PIN_PB23, 0);	/* LCDD18 */
+	at91_set_B_periph(AT91_PIN_PB24, 0);	/* LCDD19 */
+	at91_set_B_periph(AT91_PIN_PB25, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PB26, 0);	/* LCDD21 */
+	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
+	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */
+
+	at91_system_clk_enable(AT91_PMC_HCK1);
+
+	/* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
+#ifdef CONFIG_AT91SAM9261EK
+	gd->fb_base = ATMEL_BASE_SRAM;
+#endif
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		ATMEL_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += get_nand_dev_by_index(i)->size;
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_AT91SAM9G10EK
+	/* arch number of AT91SAM9G10EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
+#else
+	/* arch number of AT91SAM9261EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
+#endif
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	at91sam9261ek_nand_hw_init();
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+	at91sam9261ek_dm9000_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	at91sam9261ek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(struct bd_info *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_DRIVER_DM9000
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init();
+#endif
+}
+#endif
diff --git a/roms/u-boot/board/atmel/at91sam9261ek/led.c b/roms/u-boot/board/atmel/at91sam9261ek/led.c
new file mode 100644
index 000000000..a1aab98d5
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9261ek/led.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/io.h>
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/roms/u-boot/board/atmel/at91sam9263ek/Kconfig b/roms/u-boot/board/atmel/at91sam9263ek/Kconfig
new file mode 100644
index 000000000..3f0873fe5
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9263ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9263EK
+
+config SYS_BOARD
+	default "at91sam9263ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9263ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/at91sam9263ek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9263ek/MAINTAINERS
new file mode 100644
index 000000000..3b4b654bf
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9263ek/MAINTAINERS
@@ -0,0 +1,10 @@
+AT91SAM9263EK BOARD
+M:	Stelian Pop <stelian@popies.net>
+S:	Maintained
+F:	board/atmel/at91sam9263ek/
+F:	include/configs/at91sam9263ek.h
+F:	configs/at91sam9263ek_dataflash_defconfig
+F:	configs/at91sam9263ek_dataflash_cs0_defconfig
+F:	configs/at91sam9263ek_nandflash_defconfig
+F:	configs/at91sam9263ek_norflash_defconfig
+F:	configs/at91sam9263ek_norflash_boot_defconfig
diff --git a/roms/u-boot/board/atmel/at91sam9263ek/Makefile b/roms/u-boot/board/atmel/at91sam9263ek/Makefile
new file mode 100644
index 000000000..44c8d95a0
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9263ek/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+
+obj-y += at91sam9263ek.o
+obj-$(CONFIG_AT91_LED) += led.o
diff --git a/roms/u-boot/board/atmel/at91sam9263ek/at91sam9263ek.c b/roms/u-boot/board/atmel/at91sam9263ek/at91sam9263ek.c
new file mode 100644
index 000000000..3218e14e8
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <flash.h>
+#include <init.h>
+#include <net.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9263ek_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
+	at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Enable CS3 */
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_MODE_DBW_8 |
+#endif
+		       AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
+}
+
+static void at91sam9263ek_lcd_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
+	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
+	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
+
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+	gd->fb_base = ATMEL_BASE_SRAM0;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+#ifdef CONFIG_MTD_NOR_FLASH
+extern flash_info_t flash_info[];
+#endif
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+#ifdef CONFIG_MTD_NOR_FLASH
+	ulong flash_size;
+#endif
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		ATMEL_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += get_nand_dev_by_index(i)->size;
+#ifdef CONFIG_MTD_NOR_FLASH
+	flash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+		flash_size += flash_info[i].size;
+#endif
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
+		dram_size >> 20,
+		nand_size >> 20 );
+#ifdef CONFIG_MTD_NOR_FLASH
+	lcd_printf (",\n  %ld MB NOR",
+		flash_size >> 20);
+#endif
+	lcd_puts ("\n");
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* arch number of AT91SAM9263EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	at91sam9263ek_nand_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	at91sam9263ek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
diff --git a/roms/u-boot/board/atmel/at91sam9263ek/led.c b/roms/u-boot/board/atmel/at91sam9263ek/led.c
new file mode 100644
index 000000000..849501ec3
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9263ek/led.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/clk.h>
+
+void coloured_LED_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/roms/u-boot/board/atmel/at91sam9m10g45ek/Kconfig b/roms/u-boot/board/atmel/at91sam9m10g45ek/Kconfig
new file mode 100644
index 000000000..211c411ef
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9m10g45ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9M10G45EK
+
+config SYS_BOARD
+	default "at91sam9m10g45ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9m10g45ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/at91sam9m10g45ek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9m10g45ek/MAINTAINERS
new file mode 100644
index 000000000..54632c36d
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9m10g45ek/MAINTAINERS
@@ -0,0 +1,7 @@
+AT91SAM9M10G45EK BOARD
+M:	Eugen Hristev <eugen.hristev@microchip.com>
+S:	Maintained
+F:	board/atmel/at91sam9m10g45ek/
+F:	include/configs/at91sam9m10g45ek.h
+F:	configs/at91sam9m10g45ek_mmc_defconfig
+F:	configs/at91sam9m10g45ek_nandflash_defconfig
diff --git a/roms/u-boot/board/atmel/at91sam9m10g45ek/Makefile b/roms/u-boot/board/atmel/at91sam9m10g45ek/Makefile
new file mode 100644
index 000000000..b05b81bac
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9m10g45ek/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+
+obj-y += at91sam9m10g45ek.o
+obj-(CONFIG_AT91_LED) += led.o
diff --git a/roms/u-boot/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/roms/u-boot/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
new file mode 100644
index 000000000..8cb2808e0
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <net.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <linux/mtd/rawnand.h>
+#include <atmel_lcdc.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+void at91sam9m10g45ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+	/*
+	 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
+	 * test mode, so it needs do some action to exit test mode.
+	 */
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+	at91_set_gpio_output(AT91_PIN_PD7, 0);
+	at91_set_gpio_output(AT91_PIN_PD8, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
+
+#ifdef CONFIG_SD_BOOT
+	at91_mci_hw_init();
+#elif CONFIG_NAND_BOOT
+	at91sam9m10g45ek_nand_hw_init();
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_DQMS_SHARED |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+
+	ddr2->rtr = 0x24b;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddrc_config ddr2;
+
+	ddr2_conf(&ddr2);
+
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void at91sam9m10g45ek_usb_hw_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+
+	at91_set_gpio_output(AT91_PIN_PD1, 0);
+	at91_set_gpio_output(AT91_PIN_PD3, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+
+vidinfo_t panel_info = {
+	.vl_col =		480,
+	.vl_row =		272,
+	.vl_clk =		9000000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_NORMAL |
+				ATMEL_LCDC_INVFRAME_NORMAL,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		45,
+	.vl_left_margin =	1,
+	.vl_right_margin =	1,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	40,
+	.vl_lower_margin =	1,
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+
+void lcd_enable(void)
+{
+	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_A_periph(AT91_PIN_PE6, 0);	/* power down */
+}
+
+static void at91sam9m10g45ek_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
+	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
+
+	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
+	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
+	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
+	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
+	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
+	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
+	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
+
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+
+	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		ATMEL_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += get_nand_dev_by_index(i)->size;
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* arch number of AT91SAM9M10G45EK-Board */
+#ifdef CONFIG_AT91SAM9M10G45EK
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
+#elif defined CONFIG_AT91SAM9G45EKES
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
+#endif
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	at91sam9m10g45ek_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	at91sam9m10g45ek_usb_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	at91sam9m10g45ek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
diff --git a/roms/u-boot/board/atmel/at91sam9m10g45ek/led.c b/roms/u-boot/board/atmel/at91sam9m10g45ek/led.c
new file mode 100644
index 000000000..f44a09623
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9m10g45ek/led.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+
+void coloured_LED_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/roms/u-boot/board/atmel/at91sam9n12ek/Kconfig b/roms/u-boot/board/atmel/at91sam9n12ek/Kconfig
new file mode 100644
index 000000000..816003a5d
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9n12ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9N12EK
+
+config SYS_BOARD
+	default "at91sam9n12ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9n12ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/at91sam9n12ek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9n12ek/MAINTAINERS
new file mode 100644
index 000000000..0d33340d8
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9n12ek/MAINTAINERS
@@ -0,0 +1,8 @@
+AT91SAM9N12EK BOARD
+M:	Eugen Hristev <eugen.hristev@microchip.com>
+S:	Maintained
+F:	board/atmel/at91sam9n12ek/
+F:	include/configs/at91sam9n12ek.h
+F:	configs/at91sam9n12ek_mmc_defconfig
+F:	configs/at91sam9n12ek_nandflash_defconfig
+F:	configs/at91sam9n12ek_spiflash_defconfig
diff --git a/roms/u-boot/board/atmel/at91sam9n12ek/Makefile b/roms/u-boot/board/atmel/at91sam9n12ek/Makefile
new file mode 100644
index 000000000..2ca5459a1
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9n12ek/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Josh Wu <josh.wu@atmel.com>
+# Atmel corporation <www.atmel.com>
+
+obj-y	+= at91sam9n12ek.o
diff --git a/roms/u-boot/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/roms/u-boot/board/atmel/at91sam9n12ek/at91sam9n12ek.c
new file mode 100644
index 000000000..a3fc55bbc
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013 Atmel Corporation
+ * Josh Wu <josh.wu@atmel.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <debug_uart.h>
+#include <lcd.h>
+#include <atmel_hlcdc.h>
+#include <netdev.h>
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+#ifdef CONFIG_NAND_ATMEL
+static void at91sam9n12ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+	/* Configure databus */
+	csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
+	/* Configure IO drive */
+	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(1),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY pin */
+	at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
+
+	/* Configure ENABLE pin for NandFlash */
+	at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);    /* NAND OE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);    /* NAND WE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);    /* ALE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);    /* CLE */
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col = 480,
+	.vl_row = 272,
+	.vl_clk = 9000000,
+	.vl_bpix = LCD_BPP,
+	.vl_sync = 0,
+	.vl_tft = 1,
+	.vl_hsync_len = 5,
+	.vl_left_margin = 8,
+	.vl_right_margin = 43,
+	.vl_vsync_len = 10,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 12,
+	.mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 25, 0);	/* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 25, 1);	/* power down */
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_printf("ATMEL Corp\n");
+	lcd_printf("at91@atmel.com\n");
+	lcd_printf("%s CPU at %s MHz\n",
+		ATMEL_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += get_nand_dev_by_index(i)->size;
+	lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+#ifdef CONFIG_KS8851_MLL
+void at91sam9n12ek_ks8851_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[2].setup);
+	writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
+	       AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
+	       &smc->cs[2].pulse);
+	writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
+	       &smc->cs[2].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+	       AT91_SMC_MODE_TDF_CYCLE(1),
+	       &smc->cs[2].mode);
+
+	/* Configure NCS2 PIN */
+	at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0);
+}
+#endif
+
+#ifdef CONFIG_USB_ATMEL
+void at91sam9n12ek_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	at91sam9n12ek_nand_hw_init();
+#endif
+
+#ifdef CONFIG_LCD
+	at91_lcd_hw_init();
+#endif
+
+#ifdef CONFIG_KS8851_MLL
+	at91sam9n12ek_ks8851_hw_init();
+#endif
+
+#ifdef CONFIG_USB_ATMEL
+	at91sam9n12ek_usb_hw_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_KS8851_MLL
+int board_eth_init(struct bd_info *bis)
+{
+	return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+					CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SD_BOOT
+	at91_mci_hw_init();
+#elif CONFIG_NAND_BOOT
+	at91sam9n12ek_nand_hw_init();
+#elif CONFIG_SPI_BOOT
+	at91_spi0_hw_init(1 << 4);
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_13 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddrc_config ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* enable DDR2 clock */
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+	csa |= AT91_MATRIX_EBI_DBPD_OFF;
+	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+	writel(csa, &matrix->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
+}
+#endif
diff --git a/roms/u-boot/board/atmel/at91sam9rlek/Kconfig b/roms/u-boot/board/atmel/at91sam9rlek/Kconfig
new file mode 100644
index 000000000..81a839ac0
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9rlek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9RLEK
+
+config SYS_BOARD
+	default "at91sam9rlek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9rlek"
+
+endif
diff --git a/roms/u-boot/board/atmel/at91sam9rlek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9rlek/MAINTAINERS
new file mode 100644
index 000000000..ca8c0b158
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9rlek/MAINTAINERS
@@ -0,0 +1,8 @@
+AT91SAM9RLEK BOARD
+M:	Stelian Pop <stelian@popies.net>
+S:	Maintained
+F:	board/atmel/at91sam9rlek/
+F:	include/configs/at91sam9rlek.h
+F:	configs/at91sam9rlek_dataflash_defconfig
+F:	configs/at91sam9rlek_nandflash_defconfig
+F:	configs/at91sam9rlek_mmc_defconfig
diff --git a/roms/u-boot/board/atmel/at91sam9rlek/Makefile b/roms/u-boot/board/atmel/at91sam9rlek/Makefile
new file mode 100644
index 000000000..30dcb4913
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9rlek/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+
+obj-y += at91sam9rlek.o
+obj-$(CONFIG_AT91_LED) += led.o
diff --git a/roms/u-boot/board/atmel/at91sam9rlek/at91sam9rlek.c b/roms/u-boot/board/atmel/at91sam9rlek/at91sam9rlek.c
new file mode 100644
index 000000000..f427ee658
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/at91sam9rl.h>
+#include <asm/arch/at91sam9rl_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+
+#include <lcd.h>
+#include <atmel_lcdc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9rlek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	at91_set_A_periph(AT91_PIN_PB4, 0);		/* NANDOE */
+	at91_set_A_periph(AT91_PIN_PB5, 0);		/* NANDWE */
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
+}
+static void at91sam9rlek_lcd_hw_init(void)
+{
+	at91_set_B_periph(AT91_PIN_PC1, 0);	/* LCDPWR */
+	at91_set_A_periph(AT91_PIN_PC5, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDDEN */
+	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDCC */
+	at91_set_B_periph(AT91_PIN_PC9, 0);	/* LCDD3 */
+	at91_set_B_periph(AT91_PIN_PC10, 0);	/* LCDD4 */
+	at91_set_B_periph(AT91_PIN_PC11, 0);	/* LCDD5 */
+	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD6 */
+	at91_set_B_periph(AT91_PIN_PC13, 0);	/* LCDD7 */
+	at91_set_B_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
+	at91_set_B_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD13 */
+	at91_set_B_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
+	at91_set_B_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
+	at91_set_B_periph(AT91_PIN_PC20, 0);	/* LCDD18 */
+	at91_set_B_periph(AT91_PIN_PC21, 0);	/* LCDD19 */
+	at91_set_B_periph(AT91_PIN_PC22, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PC23, 0);	/* LCDD21 */
+	at91_set_B_periph(AT91_PIN_PC24, 0);	/* LCDD22 */
+	at91_set_B_periph(AT91_PIN_PC25, 0);	/* LCDD23 */
+
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2008 ATMEL Corp\n");
+	lcd_printf ("at91support@atmel.com\n");
+	lcd_printf ("%s CPU at %s MHz\n",
+		ATMEL_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += get_nand_dev_by_index(i)->size;
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* arch number of AT91SAM9RLEK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	at91sam9rlek_nand_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	at91sam9rlek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(
+		(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
diff --git a/roms/u-boot/board/atmel/at91sam9rlek/led.c b/roms/u-boot/board/atmel/at91sam9rlek/led.c
new file mode 100644
index 000000000..6dd19aea1
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9rlek/led.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/at91sam9rl.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+void coloured_LED_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/roms/u-boot/board/atmel/at91sam9x5ek/Kconfig b/roms/u-boot/board/atmel/at91sam9x5ek/Kconfig
new file mode 100644
index 000000000..3f92754fb
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9x5ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AT91SAM9X5EK
+
+config SYS_BOARD
+	default "at91sam9x5ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "at91sam9x5ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/at91sam9x5ek/MAINTAINERS b/roms/u-boot/board/atmel/at91sam9x5ek/MAINTAINERS
new file mode 100644
index 000000000..51d2237ee
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9x5ek/MAINTAINERS
@@ -0,0 +1,9 @@
+AT91SAM9X5EK BOARD
+M:	Eugen Hristev <eugen.hristev@microchip.com>
+S:	Maintained
+F:	board/atmel/at91sam9x5ek/
+F:	include/configs/at91sam9x5ek.h
+F:	configs/at91sam9x5ek_dataflash_defconfig
+F:	configs/at91sam9x5ek_mmc_defconfig
+F:	configs/at91sam9x5ek_nandflash_defconfig
+F:	configs/at91sam9x5ek_spiflash_defconfig
diff --git a/roms/u-boot/board/atmel/at91sam9x5ek/Makefile b/roms/u-boot/board/atmel/at91sam9x5ek/Makefile
new file mode 100644
index 000000000..e50948a5b
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9x5ek/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2012
+# Bo Shen <voice.shen@atmel.com>
+# Atmel corporation <www.atmel.com>
+
+obj-y += at91sam9x5ek.o
diff --git a/roms/u-boot/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/roms/u-boot/board/atmel/at91sam9x5ek/at91sam9x5ek.c
new file mode 100644
index 000000000..e0abe4aeb
--- /dev/null
+++ b/roms/u-boot/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <debug_uart.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+void at91_prepare_cpu_var(void);
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9x5ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+	/* NAND flash on D16 */
+	csa |= AT91_MATRIX_NFD0_ON_D16;
+
+	/* Configure IO drive */
+	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(1),
+		&smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOCD);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* NAND ALE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);	/* NAND CLE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_DM_VIDEO
+	at91_video_show_board_info();
+#endif
+	at91_prepare_cpu_var();
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* arch number of AT91SAM9X5EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	at91sam9x5ek_nand_hw_init();
+#endif
+
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
+	at91_uhp_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+					CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SD_BOOT
+	at91_mci_hw_init();
+#elif CONFIG_NAND_BOOT
+	at91sam9x5ek_nand_hw_init();
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_13 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddrc_config ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* enable DDR2 clock */
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+	csa |= AT91_MATRIX_EBI_DBPD_OFF;
+	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+	writel(csa, &matrix->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
+}
+#endif
diff --git a/roms/u-boot/board/atmel/common/Makefile b/roms/u-boot/board/atmel/common/Makefile
new file mode 100644
index 000000000..6bc8cabb8
--- /dev/null
+++ b/roms/u-boot/board/atmel/common/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Microchip
+#		      Wenyou Yang <wenyou.yang@microchip.com>
+
+obj-y += board.o
+obj-$(CONFIG_I2C_EEPROM) += mac_eeprom.o
+obj-$(CONFIG_SPI_FLASH_SFDP_SUPPORT) += mac-spi-nor.o
+obj-$(CONFIG_DM_VIDEO) += video_display.o
diff --git a/roms/u-boot/board/atmel/common/board.c b/roms/u-boot/board/atmel/common/board.c
new file mode 100644
index 000000000..eee5c357b
--- /dev/null
+++ b/roms/u-boot/board/atmel/common/board.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Microchip
+ *		      Wenyou Yang <wenyou.yang@microchip.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <w1.h>
+#include <w1-eeprom.h>
+#include <dm/device-internal.h>
+
+#define AT91_PDA_EEPROM_ID_OFFSET		15
+#define AT91_PDA_EEPROM_ID_LENGTH		5
+#define AT91_PDA_EEPROM_DEFAULT_BUS		0
+
+char *get_cpu_name(void);
+
+void dummy(void)
+{
+}
+
+#if defined CONFIG_W1
+void at91_pda_detect(void)
+{
+	struct udevice *bus, *dev;
+	u8 buf[AT91_PDA_EEPROM_ID_LENGTH + 1] = {0};
+	int ret;
+	int pda = 0;
+
+	ret = w1_get_bus(AT91_PDA_EEPROM_DEFAULT_BUS, &bus);
+	if (ret)
+		goto pda_detect_err;
+
+	for (device_find_first_child(bus, &dev);
+	     dev;
+	     device_find_next_child(&dev)) {
+		ret = device_probe(dev);
+		if (ret) {
+			continue;
+		} else {
+			ret = w1_eeprom_read_buf(dev, AT91_PDA_EEPROM_ID_OFFSET,
+						 (u8 *)buf, AT91_PDA_EEPROM_ID_LENGTH);
+			if (ret)
+				goto pda_detect_err;
+			break;
+		}
+	}
+	pda = simple_strtoul((const char *)buf, NULL, 10);
+
+	switch (pda) {
+	case 7000:
+		if (buf[4] == 'B')
+			printf("PDA TM7000B detected\n");
+		else
+			printf("PDA TM7000 detected\n");
+		break;
+	case 4300:
+		printf("PDA TM4300 detected\n");
+		break;
+	case 5000:
+		printf("PDA TM5000 detected\n");
+		break;
+	}
+
+pda_detect_err:
+	env_set("pda", (const char *)buf);
+}
+#else
+void at91_pda_detect(void)
+{
+}
+#endif
+
+void at91_prepare_cpu_var(void)
+{
+	env_set("cpu", get_cpu_name());
+}
diff --git a/roms/u-boot/board/atmel/common/mac-spi-nor.c b/roms/u-boot/board/atmel/common/mac-spi-nor.c
new file mode 100644
index 000000000..ced27b65e
--- /dev/null
+++ b/roms/u-boot/board/atmel/common/mac-spi-nor.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Tudor Ambarus <tudor.ambarus@microchip.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <net.h>
+#include <linux/mtd/spi-nor.h>
+#include <netdev.h>
+
+#define ETH_ADDR_SIZE			6
+
+#ifdef CONFIG_SPI_FLASH_SST
+#define SFDP_MICROCHIP_MANUF_ID		0xbf
+#define SFDP_MICROCHIP_MEM_TYPE		0x26
+#define SFDP_MICROCHIP_DEV_ID		0x43
+
+#define SFDP_MICROCHIP_EUI_OFFSET	0x60
+#define SFDP_MICROCHIP_EUI48		0x30
+
+struct sst26vf064beui {
+	u8 manufacturer_id;
+	u8 memory_type;
+	u8 device_id;
+	u8 reserved;
+};
+
+/**
+ * sst26vf064beui_check() - Check the validity of the EUI-48 information from
+ * the sst26vf064beui SPI NOR Microchip SFDP table.
+ * @manufacturer_sfdp:	pointer to the Microchip manufacturer specific SFDP
+ *			table.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int sst26vf064beui_check(const u8 *manufacturer_sfdp)
+{
+	struct sst26vf064beui *sst26vf064beui =
+		(struct sst26vf064beui *)manufacturer_sfdp;
+
+	if (sst26vf064beui->manufacturer_id != SFDP_MICROCHIP_MANUF_ID)
+		return -EINVAL;
+
+	if (sst26vf064beui->memory_type != SFDP_MICROCHIP_MEM_TYPE)
+		return -EINVAL;
+
+	if (sst26vf064beui->device_id != SFDP_MICROCHIP_DEV_ID)
+		return -EINVAL;
+
+	/*
+	 * Check if the EUI-48 MAC address is programmed in the next six address
+	 * locations.
+	 */
+	if (manufacturer_sfdp[SFDP_MICROCHIP_EUI_OFFSET] !=
+	    SFDP_MICROCHIP_EUI48)
+		return -EINVAL;
+
+	return 0;
+}
+
+/**
+ * sst26vf064beui_get_ethaddr() - Get the ethernet address from the
+ * sst26vf064beui SPI NOR Microchip SFDP table.
+ * @manufacturer_sfdp:	pointer to the Microchip manufacturer specific SFDP
+ *			table.
+ * @ethaddr:		pointer where to fill the ethernet address
+ * @size:		size of the ethernet address.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int sst26vf064beui_get_ethaddr(const u8 *manufacturer_sfdp,
+				      u8 *ethaddr, size_t size)
+{
+	u64 eui_table[2];
+	u64 *p = (u64 *)&manufacturer_sfdp[SFDP_MICROCHIP_EUI_OFFSET];
+	int i, ret;
+
+	ret = sst26vf064beui_check(manufacturer_sfdp);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < 2; i++)
+		eui_table[i] = le64_to_cpu(p[i]);
+
+	/* Ethaddr starts at offset one. */
+	memcpy(ethaddr, &((u8 *)eui_table)[1], size);
+
+	return 0;
+}
+#endif
+
+/**
+ * at91_spi_nor_set_ethaddr() - Retrieve and set the ethernet address from the
+ * SPI NOR manufacturer specific SFDP table.
+ */
+void at91_spi_nor_set_ethaddr(void)
+{
+	struct udevice *dev;
+	struct spi_nor *nor;
+	const char *ethaddr_name = "ethaddr";
+	u8 ethaddr[ETH_ADDR_SIZE] = {0};
+
+	if (env_get(ethaddr_name))
+		return;
+
+	if (uclass_first_device_err(UCLASS_SPI_FLASH, &dev))
+		return;
+
+	nor = dev_get_uclass_priv(dev);
+	if (!nor)
+		return;
+
+	if (!nor->manufacturer_sfdp)
+		return;
+
+#ifdef CONFIG_SPI_FLASH_SST
+	if (sst26vf064beui_get_ethaddr(nor->manufacturer_sfdp, ethaddr,
+				       ETH_ADDR_SIZE))
+		return;
+#endif
+
+	if (is_valid_ethaddr(ethaddr))
+		eth_env_set_enetaddr(ethaddr_name, ethaddr);
+}
diff --git a/roms/u-boot/board/atmel/common/mac_eeprom.c b/roms/u-boot/board/atmel/common/mac_eeprom.c
new file mode 100644
index 000000000..a723ba723
--- /dev/null
+++ b/roms/u-boot/board/atmel/common/mac_eeprom.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Microchip
+ *		      Wenyou Yang <wenyou.yang@microchip.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <eeprom.h>
+#include <env.h>
+#include <i2c_eeprom.h>
+#include <net.h>
+#include <netdev.h>
+
+int at91_set_ethaddr(int offset)
+{
+	const int ETH_ADDR_LEN = 6;
+	unsigned char ethaddr[ETH_ADDR_LEN];
+	const char *ETHADDR_NAME = "ethaddr";
+	struct udevice *dev;
+	int ret;
+
+	if (env_get(ETHADDR_NAME))
+		return 0;
+
+	ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev);
+	if (ret)
+		return ret;
+
+	ret = i2c_eeprom_read(dev, offset, ethaddr, 6);
+	if (ret)
+		return ret;
+
+	if (is_valid_ethaddr(ethaddr))
+		eth_env_set_enetaddr(ETHADDR_NAME, ethaddr);
+
+	return 0;
+}
+
+/* this function will set eth1addr from a second eeprom, if available */
+int at91_set_eth1addr(int offset)
+{
+	const int ETH_ADDR_LEN = 6;
+	unsigned char ethaddr[ETH_ADDR_LEN];
+	/* configure eth1addr for second interface */
+	const char *ETHADDR_NAME = "eth1addr";
+	struct udevice *dev;
+	int ret;
+
+	if (env_get(ETHADDR_NAME))
+		return 0;
+
+	/* first eeprom is retrieved, this is for the first interface */
+	ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev);
+	if (ret)
+		return ret;
+
+	/* attempt to obtain a second eeprom device */
+	ret = uclass_next_device(&dev);
+	if (ret)
+		return ret;
+
+	ret = i2c_eeprom_read(dev, offset, ethaddr, 6);
+	if (ret)
+		return ret;
+
+	if (is_valid_ethaddr(ethaddr))
+		eth_env_set_enetaddr(ETHADDR_NAME, ethaddr);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/atmel/common/video_display.c b/roms/u-boot/board/atmel/common/video_display.c
new file mode 100644
index 000000000..a5049f4aa
--- /dev/null
+++ b/roms/u-boot/board/atmel/common/video_display.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Microchip
+ *		      Wenyou Yang <wenyou.yang@microchip.com>
+ */
+
+#include <common.h>
+#include <atmel_lcd.h>
+#include <dm.h>
+#include <init.h>
+#include <nand.h>
+#include <version.h>
+#include <video.h>
+#include <video_console.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int at91_video_show_board_info(void)
+{
+	struct vidconsole_priv *priv;
+	ulong dram_size, nand_size;
+	int i;
+	u32 len = 0;
+	char buf[255];
+	char *corp = "Microchip Technology Inc.\n";
+	char temp[32];
+	struct udevice *dev, *con;
+	const char *s;
+	vidinfo_t logo_info;
+	int ret;
+
+	len += sprintf(&buf[len], "%s\n", U_BOOT_VERSION);
+	memcpy(&buf[len], corp, strlen(corp));
+	len += strlen(corp);
+	len += sprintf(&buf[len], "%s CPU at %s MHz\n", get_cpu_name(),
+			strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+
+	nand_size = 0;
+#ifdef CONFIG_NAND_ATMEL
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += get_nand_dev_by_index(i)->size;
+#endif
+
+	len += sprintf(&buf[len], "%ld MB SDRAM, %ld MB NAND\n",
+		       dram_size >> 20, nand_size >> 20);
+
+	ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
+	if (ret)
+		return ret;
+
+	microchip_logo_info(&logo_info);
+	ret = video_bmp_display(dev, logo_info.logo_addr,
+				logo_info.logo_x_offset,
+				logo_info.logo_y_offset, false);
+	if (ret)
+		return ret;
+
+	ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con);
+	if (ret)
+		return ret;
+
+	priv = dev_get_uclass_priv(con);
+	vidconsole_position_cursor(con, 0, (logo_info.logo_height +
+				   priv->y_charsize - 1) / priv->y_charsize);
+	for (s = buf, i = 0; i < len; s++, i++)
+		vidconsole_put_char(con, *s);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/atmel/sam9x60ek/Kconfig b/roms/u-boot/board/atmel/sam9x60ek/Kconfig
new file mode 100644
index 000000000..32fae2108
--- /dev/null
+++ b/roms/u-boot/board/atmel/sam9x60ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SAM9X60EK
+
+config SYS_BOARD
+	default "sam9x60ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "sam9x60ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/sam9x60ek/MAINTAINERS b/roms/u-boot/board/atmel/sam9x60ek/MAINTAINERS
new file mode 100644
index 000000000..d209249c2
--- /dev/null
+++ b/roms/u-boot/board/atmel/sam9x60ek/MAINTAINERS
@@ -0,0 +1,9 @@
+SAM9X60EK BOARD
+M:	Sandeep Sheriker M <sandeep.sheriker@microchip.com>
+M:	Eugen Hristev <eugen.hristev@microchip.com>
+S:	Maintained
+F:	board/atmel/sam9x60ek/
+F:	include/configs/sam9x60ek.h
+F:	configs/sam9x60ek_mmc_defconfig
+F:	configs/sam9x60ek_nandflash_defconfig
+F:	configs/sam9x60ek_qspiflash_defconfig
diff --git a/roms/u-boot/board/atmel/sam9x60ek/Makefile b/roms/u-boot/board/atmel/sam9x60ek/Makefile
new file mode 100644
index 000000000..12a406a3b
--- /dev/null
+++ b/roms/u-boot/board/atmel/sam9x60ek/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+#
+# Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
+
+obj-y += sam9x60ek.o
diff --git a/roms/u-boot/board/atmel/sam9x60ek/sam9x60ek.c b/roms/u-boot/board/atmel/sam9x60ek/sam9x60ek.c
new file mode 100644
index 000000000..32e5a2bf2
--- /dev/null
+++ b/roms/u-boot/board/atmel/sam9x60ek/sam9x60ek.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_sfr.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <debug_uart.h>
+#include <asm/mach-types.h>
+
+extern void at91_pda_detect(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void at91_prepare_cpu_var(void);
+
+#ifdef CONFIG_CMD_NAND
+static void sam9x60ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+	unsigned int csa;
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0);	/* NAND ALE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0);	/* NAND CLE */
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+	/* Enable CS3 */
+	csa = readl(&sfr->ebicsa);
+	csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16;
+
+	/* Configure IO drive */
+	csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60;
+
+	writel(csa, &sfr->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) |
+	       AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20),
+	       &smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
+	       &smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15),
+	       &smc->cs[3].mode);
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	at91_prepare_cpu_var();
+
+	at91_pda_detect();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+#define MAC24AA_MAC_OFFSET     0xfa
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_I2C_EEPROM
+	at91_set_ethaddr(MAC24AA_MAC_OFFSET);
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	sam9x60ek_nand_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
diff --git a/roms/u-boot/board/atmel/sama5d27_som1_ek/Kconfig b/roms/u-boot/board/atmel/sama5d27_som1_ek/Kconfig
new file mode 100644
index 000000000..3276214d8
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d27_som1_ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D27_SOM1_EK
+
+config SYS_BOARD
+	default "sama5d27_som1_ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at91"
+
+config SYS_CONFIG_NAME
+	default "sama5d27_som1_ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/sama5d27_som1_ek/MAINTAINERS b/roms/u-boot/board/atmel/sama5d27_som1_ek/MAINTAINERS
new file mode 100644
index 000000000..ba2f31e6c
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d27_som1_ek/MAINTAINERS
@@ -0,0 +1,14 @@
+SAMA5D27 SOM1 EK BOARD
+M:	Eugen Hristev <eugen.hristev@microchip.com>
+S:	Maintained
+F:	board/atmel/sama5d27_som1_ek/
+F:	include/configs/sama5d27_som1_ek.h
+F:	configs/sama5d27_som1_ek_mmc_defconfig
+F:	configs/sama5d27_som1_ek_mmc1_defconfig
+F:	configs/sama5d27_som1_ek_qspiflash_defconfig
+
+SAMA5D27 GIANT BOARD
+M:	Greg Gallagher <greg@embeddedgreg.com>
+S:	Maintained
+F:	configs/sama5d27_giantboard_defconfig
+F:	arch/arm/dts/at91-sama5d27_giantboard.dts
diff --git a/roms/u-boot/board/atmel/sama5d27_som1_ek/Makefile b/roms/u-boot/board/atmel/sama5d27_som1_ek/Makefile
new file mode 100644
index 000000000..72d320b1a
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d27_som1_ek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Microchip Corporation
+#		     Wenyou Yang <wenyou.yang@microchip.com>
+
+obj-y += sama5d27_som1_ek.o
diff --git a/roms/u-boot/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/roms/u-boot/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c
new file mode 100644
index 000000000..1b7d946b5
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Microchip Corporation
+ *		      Wenyou.Yang <wenyou.yang@microchip.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+extern void at91_pda_detect(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_USB
+static void board_usb_hw_init(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 27, 1);
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_DM_VIDEO
+	at91_video_show_board_info();
+#endif
+	at91_pda_detect();
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart1_hw_init(void)
+{
+	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK);	/* URXD1 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);	/* UTXD1 */
+
+	at91_periph_clk_enable(ATMEL_ID_UART1);
+}
+
+void board_debug_uart_init(void)
+{
+	board_uart1_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_USB
+	board_usb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#define MAC24AA_MAC_OFFSET	0xfa
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_I2C_EEPROM
+	at91_set_ethaddr(MAC24AA_MAC_OFFSET);
+#endif
+	return 0;
+}
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+	ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_13 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_DIC_DS |
+		    ATMEL_MPDDRC_CR_ZQ_LONG |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddrc->rtr = 0x511;
+
+	ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+		      (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+		      (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+	ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+		      (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+		      (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+	ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+		      (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+		      (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	struct atmel_mpddrc_config ddrc_config;
+	u32 reg;
+
+	ddrc_conf(&ddrc_config);
+
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	reg = readl(&mpddrc->io_calibr);
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
+	writel(reg, &mpddrc->io_calibr);
+
+	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
+	       &mpddrc->rd_data_path);
+
+	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+	writel(0x3, &mpddrc->cal_mr4);
+	writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+	u32 tmp;
+
+	/*
+	 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
+	 * so we need to slow down and configure MCKR accordingly.
+	 * This is why we have a special flavor of the switching function.
+	 */
+	tmp = AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_MAIN;
+	at91_mck_init_down(tmp);
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(40) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	tmp = AT91_PMC_MCKR_H32MXDIV |
+	      AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif
diff --git a/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/Kconfig b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/Kconfig
new file mode 100644
index 000000000..4b192b084
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D27_WLSOM1_EK
+
+config SYS_BOARD
+	default "sama5d27_wlsom1_ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at91"
+
+config SYS_CONFIG_NAME
+	default "sama5d27_wlsom1_ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS
new file mode 100644
index 000000000..ff68cf01a
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS
@@ -0,0 +1,8 @@
+SAMA5D27 WLSOM1 EK BOARD
+M:	Nicolas Ferre <nicolas.ferre@microchip.com>
+M:	Eugen Hristev <eugen.hristev@microchip.com>
+S:	Maintained
+F:	board/atmel/sama5d27_wlsom1_ek/
+F:	include/configs/sama5d27_wlsom1_ek.h
+F:	configs/sama5d27_wlsom1_ek_mmc_defconfig
+F:	configs/sama5d27_wlsom1_ek_qspiflash_defconfig
diff --git a/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/Makefile b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/Makefile
new file mode 100644
index 000000000..cf827ae5e
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+#
+# Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
+
+obj-y += sama5d27_wlsom1_ek.o
diff --git a/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
new file mode 100644
index 000000000..32d51bba7
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+extern void at91_pda_detect(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_DM_VIDEO
+	at91_video_show_board_info();
+#endif
+	at91_pda_detect();
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart0_hw_init(void)
+{
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK);	/* URXD0 */
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0);				/* UTXD0 */
+
+	at91_periph_clk_enable(ATMEL_ID_UART0);
+}
+
+void board_debug_uart_init(void)
+{
+	board_uart0_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_SPI_FLASH_SFDP_SUPPORT
+	at91_spi_nor_set_ethaddr();
+#endif
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+
+static void board_leds_init(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 6, 0); /* RED */
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 7, 1); /* GREEN */
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 8, 0); /* BLUE */
+}
+
+#ifdef CONFIG_SD_BOOT
+void spl_mmc_init(void)
+{
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* CMD */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* DAT0 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0);	/* DAT1 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0);	/* DAT2 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0);	/* DAT3 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* CK */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* CD */
+
+	at91_periph_clk_enable(ATMEL_ID_SDMMC0);
+}
+#endif
+
+#ifdef CONFIG_QSPI_BOOT
+void spl_qspi_init(void)
+{
+	atmel_pio4_set_d_periph(AT91_PIO_PORTB, 5, 0);	/* SCK */
+	atmel_pio4_set_d_periph(AT91_PIO_PORTB, 6, 0);	/* CS */
+	atmel_pio4_set_d_periph(AT91_PIO_PORTB, 7, 0);	/* IO0 */
+	atmel_pio4_set_d_periph(AT91_PIO_PORTB, 8, 0);	/* IO1 */
+	atmel_pio4_set_d_periph(AT91_PIO_PORTB, 9, 0);	/* IO2 */
+	atmel_pio4_set_d_periph(AT91_PIO_PORTB, 10, 0);	/* IO3 */
+
+	at91_periph_clk_enable(ATMEL_ID_QSPI1);
+}
+#endif
+
+void spl_board_init(void)
+{
+	board_leds_init();
+#ifdef CONFIG_SD_BOOT
+	spl_mmc_init();
+#endif
+#ifdef CONFIG_QSPI_BOOT
+	spl_qspi_init();
+#endif
+}
+
+void spl_display_print(void)
+{
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR2_SDRAM);
+
+	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_ZQ_SHORT |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddrc->lpddr23_lpr = ATMEL_MPDDRC_LPDDR23_LPR_DS(0x3);
+
+	/*
+	 * The AD220032D average time between REFRESH commands (Trefi): 3.9us
+	 * 3.9us * 164MHz = 639.6 = 0x27F.
+	 */
+	ddrc->rtr = 0x27f;
+	/* Enable Adjust Refresh Rate */
+	ddrc->rtr |= ATMEL_MPDDRC_RTR_ADJ_REF;
+
+	ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+		      (11 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+		      (2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+		      (2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+		      (5 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+	ddrc->tpr1 = ((21 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+		      (23 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+		      (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+	ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+		      (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+		      (10 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+
+	ddrc->tim_cal = ATMEL_MPDDRC_CALR_ZQCS(15);
+
+	/*
+	 * According to the sama5d2 datasheet and the following values:
+	 * T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s
+	 * Warning: note that the values T driftrate and V driftrate are dependent on
+	 * the application environment.
+	 * ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s
+	 * If Trefi is 3.9us, we have: 400000 / 3.9 = 102564: we can maximize
+	 * this timer to 0xFFFE.
+	 */
+	ddrc->cal_mr4 = ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(0xFFFE);
+
+	/*
+	 * MR4 Read interval is dependent on the application environment.
+	 * Here, we want to maximize this value as temperature is supposed
+	 * to vary slowly in the application chosen.
+	 * If Trefi is 3.9us, we have:
+	 * (0xFFFE) 65534 x 3.9 = 0.25s between MR4 reads.
+	 */
+	ddrc->cal_mr4 |= ATMEL_MPDDRC_CAL_MR4_MR4R(0xFFFE);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	struct atmel_mpddrc_config ddrc_config;
+	u32 reg;
+
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	ddrc_conf(&ddrc_config);
+
+	reg = readl(&mpddrc->io_calibr);
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48;
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+	writel(reg, &mpddrc->io_calibr);
+
+	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
+	       &mpddrc->rd_data_path);
+
+	lpddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+}
+
+void at91_pmc_init(void)
+{
+	u32 tmp;
+
+	/*
+	 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
+	 * so we need to slow down and configure MCKR accordingly.
+	 * This is why we have a special flavor of the switching function.
+	 */
+	tmp = AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_MAIN;
+	at91_mck_init_down(tmp);
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(40) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	tmp = AT91_PMC_MCKR_H32MXDIV |
+	      AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif
diff --git a/roms/u-boot/board/atmel/sama5d2_icp/Kconfig b/roms/u-boot/board/atmel/sama5d2_icp/Kconfig
new file mode 100644
index 000000000..385984551
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d2_icp/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D2_ICP
+
+config SYS_BOARD
+	default "sama5d2_icp"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at91"
+
+config SYS_CONFIG_NAME
+	default "sama5d2_icp"
+
+endif
diff --git a/roms/u-boot/board/atmel/sama5d2_icp/MAINTAINERS b/roms/u-boot/board/atmel/sama5d2_icp/MAINTAINERS
new file mode 100644
index 000000000..db984b6ae
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d2_icp/MAINTAINERS
@@ -0,0 +1,7 @@
+SAMA5D2 ICP BOARD
+M:     Eugen Hristev <eugen.hristev@microchip.com>
+S:     Maintained
+F:     board/atmel/sama5d2_icp/
+F:     include/configs/sama5d2_icp.h
+F:     configs/sama5d2_icp_mmc_defconfig
+
diff --git a/roms/u-boot/board/atmel/sama5d2_icp/Makefile b/roms/u-boot/board/atmel/sama5d2_icp/Makefile
new file mode 100644
index 000000000..fd7e87059
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d2_icp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier:     GPL-2.0+
+#
+# Copyright (C) 2018 Microchip Technology Inc.
+#                   Eugen Hristev <eugen.hristev@microchip.com>
+#
+
+obj-y += sama5d2_icp.o
diff --git a/roms/u-boot/board/atmel/sama5d2_icp/sama5d2_icp.c b/roms/u-boot/board/atmel/sama5d2_icp/sama5d2_icp.c
new file mode 100644
index 000000000..3f33fcfc4
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d2_icp/sama5d2_icp.c
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Microchip Technology, Inc.
+ *		      Eugen Hristev <eugen.hristev@microchip.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart0_hw_init(void)
+{
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0);	/* UTXD0 */
+
+	at91_periph_clk_enable(ATMEL_ID_UART0);
+}
+
+void board_debug_uart_init(void)
+{
+	board_uart0_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#define MAC24AA_MAC_OFFSET	0xfa
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_I2C_EEPROM
+	at91_set_ethaddr(MAC24AA_MAC_OFFSET);
+#endif
+	return 0;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+
+/* must set PB25 low to enable the CAN transceivers */
+static void board_can_stdby_dis(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 25, 0);
+}
+
+static void board_leds_init(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* RED */
+	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 1); /* GREEN */
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 0); /* BLUE */
+}
+
+/* deassert reset lines for external periph in case of warm reboot */
+static void board_reset_additional_periph(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 0); /* LAN9252_RST */
+	atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 0); /* HSIC_RST */
+	atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 0); /* USB2534_RST */
+	atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 0); /* KSZ8563_RST */
+}
+
+static void board_start_additional_periph(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 1); /* LAN9252_RST */
+	atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 1); /* HSIC_RST */
+	atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 1); /* USB2534_RST */
+	atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 1); /* KSZ8563_RST */
+}
+
+#ifdef CONFIG_SD_BOOT
+void spl_mmc_init(void)
+{
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* CMD */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* DAT0 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0);	/* DAT1 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0);	/* DAT2 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0);	/* DAT3 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* CK */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* CD */
+
+	at91_periph_clk_enable(ATMEL_ID_SDMMC0);
+}
+#endif
+
+void spl_board_init(void)
+{
+#ifdef CONFIG_SD_BOOT
+	spl_mmc_init();
+#endif
+	board_reset_additional_periph();
+	board_can_stdby_dis();
+	board_leds_init();
+}
+
+void spl_display_print(void)
+{
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	board_start_additional_periph();
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
+
+	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
+		    ATMEL_MPDDRC_CR_DIC_DS |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddrc->rtr = 0x298;
+
+	ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+		      (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+	ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+		      (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+		      (10 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+	ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+		      (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	struct atmel_mpddrc_config ddrc_config;
+	u32 reg;
+
+	ddrc_conf(&ddrc_config);
+
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	reg = readl(&mpddrc->io_calibr);
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+	writel(reg, &mpddrc->io_calibr);
+
+	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
+	       &mpddrc->rd_data_path);
+
+	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+	writel(0x5355, &mpddrc->cal_mr4);
+	writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+	u32 tmp;
+
+	/*
+	 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
+	 * so we need to slow down and configure MCKR accordingly.
+	 * This is why we have a special flavor of the switching function.
+	 */
+	tmp = AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_MAIN;
+	at91_mck_init_down(tmp);
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(82) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	tmp = AT91_PMC_MCKR_H32MXDIV |
+	      AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif
diff --git a/roms/u-boot/board/atmel/sama5d2_ptc_ek/Kconfig b/roms/u-boot/board/atmel/sama5d2_ptc_ek/Kconfig
new file mode 100644
index 000000000..8b202d6cc
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d2_ptc_ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D2_PTC_EK
+
+config SYS_BOARD
+	default "sama5d2_ptc_ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at91"
+
+config SYS_CONFIG_NAME
+	default "sama5d2_ptc_ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/sama5d2_ptc_ek/MAINTAINERS b/roms/u-boot/board/atmel/sama5d2_ptc_ek/MAINTAINERS
new file mode 100644
index 000000000..9f82d9a3d
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d2_ptc_ek/MAINTAINERS
@@ -0,0 +1,8 @@
+SAMA5D2 PTC EK BOARD
+M:	Eugen Hristev <eugen.hristev@microchip.com>
+M:	Ludovic Desroches <ludovic.desroches@microchip.com>
+S:	Maintained
+F:	board/atmel/sama5d2_ptc_ek/
+F:	include/configs/sama5d2_ptc_ek.h
+F:	configs/sama5d2_ptc_ek_mmc_defconfig
+F:	configs/sama5d2_ptc_ek_nandflash_defconfig
diff --git a/roms/u-boot/board/atmel/sama5d2_ptc_ek/Makefile b/roms/u-boot/board/atmel/sama5d2_ptc_ek/Makefile
new file mode 100644
index 000000000..22f466439
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d2_ptc_ek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Microchip Corporation
+#		     Wenyou Yang <wenyou.yang@microchip.com>
+
+obj-y += sama5d2_ptc_ek.o
diff --git a/roms/u-boot/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/roms/u-boot/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
new file mode 100644
index 000000000..a6937e7d5
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Microchip Corporation
+ *		      Wenyou Yang <wenyou.yang@microchip.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <i2c.h>
+#include <init.h>
+#include <nand.h>
+#include <version.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+#include <asm/arch/sama5d2_smc.h>
+
+extern void at91_pda_detect(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NAND_ATMEL
+static void board_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_HSMC);
+
+	/* Configure SMC CS3 for NAND */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(4) |
+	       AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+	       AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
+	       AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3) |
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, ATMEL_PIO_DRVSTR_ME);	/* D0 */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, ATMEL_PIO_DRVSTR_ME);	/* D1 */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, ATMEL_PIO_DRVSTR_ME);	/* D2 */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, ATMEL_PIO_DRVSTR_ME);	/* D3 */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, ATMEL_PIO_DRVSTR_ME);	/* D4 */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, ATMEL_PIO_DRVSTR_ME);	/* D5 */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, ATMEL_PIO_DRVSTR_ME);	/* D6 */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, ATMEL_PIO_DRVSTR_ME);	/* D7 */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0);	/* RE */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0);	/* WE */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, ATMEL_PIO_PUEN_MASK);	/* NCS */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, ATMEL_PIO_PUEN_MASK);	/* RDY */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, ATMEL_PIO_PUEN_MASK);	/* ALE */
+	atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, ATMEL_PIO_PUEN_MASK);	/* CLE */
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	at91_pda_detect();
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void board_usb_hw_init(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, ATMEL_PIO_PUEN_MASK);
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart0_hw_init(void)
+{
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK);	/* URXD0 */
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0);	/* UTXD0 */
+
+	at91_periph_clk_enable(ATMEL_ID_UART0);
+}
+
+void board_debug_uart_init(void)
+{
+	board_uart0_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	board_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	board_usb_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#define AT24MAC_MAC_OFFSET	0xfa
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_I2C_EEPROM
+	at91_set_ethaddr(AT24MAC_MAC_OFFSET);
+#endif
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/atmel/sama5d2_xplained/Kconfig b/roms/u-boot/board/atmel/sama5d2_xplained/Kconfig
new file mode 100644
index 000000000..55712e974
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d2_xplained/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D2_XPLAINED
+
+config SYS_BOARD
+	default "sama5d2_xplained"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at91"
+
+config SYS_CONFIG_NAME
+	default "sama5d2_xplained"
+
+endif
diff --git a/roms/u-boot/board/atmel/sama5d2_xplained/MAINTAINERS b/roms/u-boot/board/atmel/sama5d2_xplained/MAINTAINERS
new file mode 100644
index 000000000..88e327f81
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d2_xplained/MAINTAINERS
@@ -0,0 +1,9 @@
+SAMA5D2 XPLAINED BOARD
+M:	Eugen Hristev <eugen.hristev@microchip.com>
+S:	Maintained
+F:	board/atmel/sama5d2_xplained/
+F:	include/configs/sama5d2_xplained.h
+F:	configs/sama5d2_xplained_mmc_defconfig
+F:	configs/sama5d2_xplained_spiflash_defconfig
+F:	configs/sama5d2_xplained_emmc_defconfig
+F:	configs/sama5d2_xplained_qspiflash_defconfig
diff --git a/roms/u-boot/board/atmel/sama5d2_xplained/Makefile b/roms/u-boot/board/atmel/sama5d2_xplained/Makefile
new file mode 100644
index 000000000..39ba24d5f
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d2_xplained/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Atmel Corporation
+#		     Wenyou Yang <wenyou.yang@atmel.com>
+
+obj-y += sama5d2_xplained.o
diff --git a/roms/u-boot/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/roms/u-boot/board/atmel/sama5d2_xplained/sama5d2_xplained.c
new file mode 100644
index 000000000..5110ec896
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ *		      Wenyou.Yang <wenyou.yang@atmel.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+extern void at91_pda_detect(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_USB
+static void board_usb_hw_init(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_DM_VIDEO
+	at91_video_show_board_info();
+#endif
+	at91_pda_detect();
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart1_hw_init(void)
+{
+	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK);	/* URXD1 */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);	/* UTXD1 */
+
+	at91_periph_clk_enable(ATMEL_ID_UART1);
+}
+
+void board_debug_uart_init(void)
+{
+	board_uart1_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_USB
+	board_usb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#define AT24MAC_MAC_OFFSET	0x9a
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_I2C_EEPROM
+	at91_set_ethaddr(AT24MAC_MAC_OFFSET);
+#endif
+
+	return 0;
+}
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
+
+	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
+		    ATMEL_MPDDRC_CR_DIC_DS |
+		    ATMEL_MPDDRC_CR_DIS_DLL |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddrc->rtr = 0x511;
+
+	ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET |
+		      29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);
+
+	ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	struct atmel_mpddrc_config ddrc_config;
+	u32 reg;
+
+	ddrc_conf(&ddrc_config);
+
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	reg = readl(&mpddrc->io_calibr);
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+	writel(reg, &mpddrc->io_calibr);
+
+	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
+	       &mpddrc->rd_data_path);
+
+	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+	writel(0x3, &mpddrc->cal_mr4);
+	writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 tmp;
+
+	/*
+	 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
+	 * so we need to slow down and configure MCKR accordingly.
+	 * This is why we have a special flavor of the switching function.
+	 */
+	tmp = AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_MAIN;
+	at91_mck_init_down(tmp);
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(82) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	writel(0x0 << 8, &pmc->pllicpr);
+
+	tmp = AT91_PMC_MCKR_H32MXDIV |
+	      AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif
diff --git a/roms/u-boot/board/atmel/sama5d3_xplained/Kconfig b/roms/u-boot/board/atmel/sama5d3_xplained/Kconfig
new file mode 100644
index 000000000..2df751a26
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d3_xplained/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SAMA5D3_XPLAINED
+
+config SYS_BOARD
+	default "sama5d3_xplained"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "sama5d3_xplained"
+
+endif
diff --git a/roms/u-boot/board/atmel/sama5d3_xplained/MAINTAINERS b/roms/u-boot/board/atmel/sama5d3_xplained/MAINTAINERS
new file mode 100644
index 000000000..69b4ee8a3
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d3_xplained/MAINTAINERS
@@ -0,0 +1,7 @@
+SAMA5D3_XPLAINED BOARD
+M:	Eugen Hristev <eugen.hristev@microchip.com>
+S:	Maintained
+F:	board/atmel/sama5d3_xplained/
+F:	include/configs/sama5d3_xplained.h
+F:	configs/sama5d3_xplained_mmc_defconfig
+F:	configs/sama5d3_xplained_nandflash_defconfig
diff --git a/roms/u-boot/board/atmel/sama5d3_xplained/Makefile b/roms/u-boot/board/atmel/sama5d3_xplained/Makefile
new file mode 100644
index 000000000..b6bcd3c0a
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d3_xplained/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2014
+# Bo Shen <voice.shen@atmel.com>
+
+obj-y += sama5d3_xplained.o
diff --git a/roms/u-boot/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/roms/u-boot/board/atmel/sama5d3_xplained/sama5d3_xplained.c
new file mode 100644
index 000000000..db9603f58
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <debug_uart.h>
+#include <spl.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/at91_wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void at91_pda_detect(void);
+
+#ifdef CONFIG_NAND_ATMEL
+void sama5d3_xplained_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+	       AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
+	       AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d3_xplained_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+static void sama5d3_xplained_mci0_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 2, 0);	/* MCI0 Power */
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	at91_pda_detect();
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	sama5d3_xplained_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	sama5d3_xplained_usb_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	sama5d3_xplained_mci0_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SD_BOOT
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	sama5d3_xplained_mci0_hw_init();
+#endif
+#elif CONFIG_NAND_BOOT
+	sama5d3_xplained_nand_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_ENRDM_ON |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+	/*
+	 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
+	 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
+	 */
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddrc_config ddr2;
+
+	ddr2_conf(&ddr2);
+
+	/* Enable MPDDR clock */
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(43) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
+
+	tmp = AT91_PMC_MCKR_MDIV_4 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif
diff --git a/roms/u-boot/board/atmel/sama5d3xek/Kconfig b/roms/u-boot/board/atmel/sama5d3xek/Kconfig
new file mode 100644
index 000000000..abd1ad81f
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d3xek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SAMA5D3XEK
+
+config SYS_BOARD
+	default "sama5d3xek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "sama5d3xek"
+
+endif
diff --git a/roms/u-boot/board/atmel/sama5d3xek/MAINTAINERS b/roms/u-boot/board/atmel/sama5d3xek/MAINTAINERS
new file mode 100644
index 000000000..e8ec275d7
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d3xek/MAINTAINERS
@@ -0,0 +1,11 @@
+SAMA5D3XEK BOARD
+M:	Eugen Hristev <eugen.hristev@microchip.com>
+S:	Maintained
+F:	board/atmel/sama5d3xek/
+F:	include/configs/sama5d3xek.h
+F:	configs/sama5d3xek_mmc_defconfig
+F:	configs/sama5d3xek_nandflash_defconfig
+F:	configs/sama5d3xek_spiflash_defconfig
+F:	configs/sama5d36ek_cmp_mmc_defconfig
+F:	configs/sama5d36ek_cmp_nandflash_defconfig
+F:	configs/sama5d36ek_cmp_spiflash_defconfig
diff --git a/roms/u-boot/board/atmel/sama5d3xek/Makefile b/roms/u-boot/board/atmel/sama5d3xek/Makefile
new file mode 100644
index 000000000..6fe1b13b0
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d3xek/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Bo Shen <voice.shen@atmel.com>
+
+obj-y += sama5d3xek.o
diff --git a/roms/u-boot/board/atmel/sama5d3xek/sama5d3xek.c b/roms/u-boot/board/atmel/sama5d3xek/sama5d3xek.c
new file mode 100644
index 000000000..b6f8dcd91
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d3xek/sama5d3xek.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 - 2013 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <debug_uart.h>
+#include <env.h>
+#include <linux/ctype.h>
+#include <spl.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/at91_wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_NAND_ATMEL
+void sama5d3xek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+	       AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
+	       AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+}
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+static void sama5d3xek_nor_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS0 for NOR flash */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[0].setup);
+	writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
+	       AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
+	       &smc->cs[0].pulse);
+	writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
+	       &smc->cs[0].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0)  |
+	       AT91_SMC_TIMINGS_TAR(0)  | AT91_SMC_TIMINGS_TRR(0)   |
+	       AT91_SMC_TIMINGS_TWB(0)  | AT91_SMC_TIMINGS_RBNSEL(0)|
+	       AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_16 |
+	       AT91_SMC_MODE_TDF_CYCLE(1),
+	       &smc->cs[0].mode);
+
+	/* Address pin (A1 ~ A23) configuration */
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0);
+	/* CS0 pin configuration */
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d3xek_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
+	at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
+	at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+static void sama5d3xek_mci_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTB, 10, 0);	/* MCI0 Power */
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	sama5d3xek_nand_hw_init();
+#endif
+#ifdef CONFIG_MTD_NOR_FLASH
+	sama5d3xek_nor_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	sama5d3xek_usb_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	sama5d3xek_mci_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	const int MAX_STR_LEN = 32;
+	char name[MAX_STR_LEN], *p;
+	int i;
+
+	strncpy(name, get_cpu_name(), MAX_STR_LEN);
+	for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++)
+		*p = tolower(*p);
+
+	strcat(name, "ek.dtb");
+	env_set("dtb_name", name);
+#endif
+#ifdef CONFIG_DM_VIDEO
+	at91_video_show_board_info();
+#endif
+	return 0;
+}
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#if CONFIG_NAND_BOOT
+	sama5d3xek_nand_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_ENRDM_ON |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+	/*
+	 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
+	 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
+	 */
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddrc_config ddr2;
+
+	ddr2_conf(&ddr2);
+
+	/* Enable MPDDR clock */
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(43) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
+
+	tmp = AT91_PMC_MCKR_MDIV_4 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif
diff --git a/roms/u-boot/board/atmel/sama5d4_xplained/Kconfig b/roms/u-boot/board/atmel/sama5d4_xplained/Kconfig
new file mode 100644
index 000000000..2cb03cb17
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d4_xplained/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SAMA5D4_XPLAINED
+
+config SYS_BOARD
+	default "sama5d4_xplained"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "sama5d4_xplained"
+
+endif
diff --git a/roms/u-boot/board/atmel/sama5d4_xplained/MAINTAINERS b/roms/u-boot/board/atmel/sama5d4_xplained/MAINTAINERS
new file mode 100644
index 000000000..9fd0ad7bc
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d4_xplained/MAINTAINERS
@@ -0,0 +1,8 @@
+SAMA5D4 XPLAINED ULTRA BOARD
+M:	Eugen Hristev <eugen.hristev@microchip.com>
+S:	Maintained
+F:	board/atmel/sama5d4_xplained/
+F:	include/configs/sama5d4_xplained.h
+F:	configs/sama5d4_xplained_mmc_defconfig
+F:	configs/sama5d4_xplained_nandflash_defconfig
+F:	configs/sama5d4_xplained_spiflash_defconfig
diff --git a/roms/u-boot/board/atmel/sama5d4_xplained/Makefile b/roms/u-boot/board/atmel/sama5d4_xplained/Makefile
new file mode 100644
index 000000000..a79a97420
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d4_xplained/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014 Atmel
+#		     Bo Shen <voice.shen@atmel.com>
+
+obj-y += sama5d4_xplained.o
diff --git a/roms/u-boot/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/roms/u-boot/board/atmel/sama5d4_xplained/sama5d4_xplained.c
new file mode 100644
index 000000000..2088b48b7
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Atmel
+ *		      Bo Shen <voice.shen@atmel.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/sama5d4.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void at91_pda_detect(void);
+
+#ifdef CONFIG_NAND_ATMEL
+static void sama5d4_xplained_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS3 for NAND */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+	       AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
+	       AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3)|
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* D0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* D1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* D2 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* D3 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* D4 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* D5 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* D6 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* D7 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* RE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* WE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1);	/* NCS */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1);	/* RDY */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1);	/* ALE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1);	/* CLE */
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d4_xplained_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
+	at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	at91_pda_detect();
+#ifdef CONFIG_DM_VIDEO
+	at91_video_show_board_info();
+#endif
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void sama5d4_xplained_serial3_hw_init(void)
+{
+	at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_USART3);
+}
+
+void board_debug_uart_init(void)
+{
+	sama5d4_xplained_serial3_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+#define AT24MAC_MAC_OFFSET	0x9a
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_I2C_EEPROM
+	at91_set_ethaddr(AT24MAC_MAC_OFFSET);
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	sama5d4_xplained_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	sama5d4_xplained_usb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#if CONFIG_NAND_BOOT
+	sama5d4_xplained_nand_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddr2->rtr = 0x2b0;
+
+	ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddrc_config ddr2;
+
+	ddr2_conf(&ddr2);
+
+	/* Enable MPDDR clock */
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(87) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
+
+	tmp = AT91_PMC_MCKR_H32MXDIV |
+	      AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif
diff --git a/roms/u-boot/board/atmel/sama5d4ek/Kconfig b/roms/u-boot/board/atmel/sama5d4ek/Kconfig
new file mode 100644
index 000000000..1a634032a
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d4ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SAMA5D4EK
+
+config SYS_BOARD
+	default "sama5d4ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_CONFIG_NAME
+	default "sama5d4ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/sama5d4ek/MAINTAINERS b/roms/u-boot/board/atmel/sama5d4ek/MAINTAINERS
new file mode 100644
index 000000000..f715af640
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d4ek/MAINTAINERS
@@ -0,0 +1,8 @@
+SAMA5D4EK BOARD
+M:	Eugen Hristev <eugen.hristev@microchip.com>
+S:	Maintained
+F:	board/atmel/sama5d4ek/
+F:	include/configs/sama5d4ek.h
+F:	configs/sama5d4ek_mmc_defconfig
+F:	configs/sama5d4ek_nandflash_defconfig
+F:	configs/sama5d4ek_spiflash_defconfig
diff --git a/roms/u-boot/board/atmel/sama5d4ek/Makefile b/roms/u-boot/board/atmel/sama5d4ek/Makefile
new file mode 100644
index 000000000..b5696c8c0
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d4ek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014 Atmel
+#		     Bo Shen <voice.shen@atmel.com>
+
+obj-y += sama5d4ek.o
diff --git a/roms/u-boot/board/atmel/sama5d4ek/sama5d4ek.c b/roms/u-boot/board/atmel/sama5d4ek/sama5d4ek.c
new file mode 100644
index 000000000..46ec1eb32
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama5d4ek/sama5d4ek.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Atmel
+ *		      Bo Shen <voice.shen@atmel.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/sama5d4.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NAND_ATMEL
+static void sama5d4ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS3 for NAND */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+	       AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
+	       AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3)|
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* D0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* D1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* D2 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* D3 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* D4 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* D5 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* D6 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* D7 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* RE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* WE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1);	/* NCS */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1);	/* RDY */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1);	/* ALE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1);	/* CLE */
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d4ek_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_DM_VIDEO
+	at91_video_show_board_info();
+#endif
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void sama5d4ek_serial3_hw_init(void)
+{
+	at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_USART3);
+}
+
+void board_debug_uart_init(void)
+{
+	sama5d4ek_serial3_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	sama5d4ek_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	sama5d4ek_usb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#if CONFIG_NAND_BOOT
+	sama5d4ek_nand_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddr2->rtr = 0x2b0;
+
+	ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddrc_config ddr2;
+	const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	u32 tmp;
+
+	ddr2_conf(&ddr2);
+
+	/* Enable MPDDR clock */
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE;
+	writel(tmp, &mpddr->rd_data_path);
+
+	tmp = readl(&mpddr->io_calibr);
+	tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV |
+	       ATMEL_MPDDRC_IO_CALIBR_TZQIO |
+	       ATMEL_MPDDRC_IO_CALIBR_CALCODEP |
+	       ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) |
+	       ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 |
+	       ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) |
+	       ATMEL_MPDDRC_IO_CALIBR_EN_CALIB;
+	writel(tmp, &mpddr->io_calibr);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(87) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
+
+	tmp = AT91_PMC_MCKR_H32MXDIV |
+	      AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif
diff --git a/roms/u-boot/board/atmel/sama7g5ek/Kconfig b/roms/u-boot/board/atmel/sama7g5ek/Kconfig
new file mode 100644
index 000000000..a89db8d8a
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama7g5ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA7G5EK
+
+config SYS_BOARD
+	default "sama7g5ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at91"
+
+config SYS_CONFIG_NAME
+	default "sama7g5ek"
+
+endif
diff --git a/roms/u-boot/board/atmel/sama7g5ek/MAINTAINERS b/roms/u-boot/board/atmel/sama7g5ek/MAINTAINERS
new file mode 100644
index 000000000..eac972968
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama7g5ek/MAINTAINERS
@@ -0,0 +1,8 @@
+SAMA7G5 EK BOARD
+M:     Eugen Hristev <eugen.hristev@microchip.com>
+S:     Maintained
+F:     board/atmel/sama7g5ek.c
+F:     include/configs/sama7g5ek.h
+F:     configs/sama7g5ek_mmc1_defconfig
+F:     configs/sama7g5ek_mmc_defconfig
+
diff --git a/roms/u-boot/board/atmel/sama7g5ek/Makefile b/roms/u-boot/board/atmel/sama7g5ek/Makefile
new file mode 100644
index 000000000..a6eedd10f
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama7g5ek/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier:     GPL-2.0+
+#
+# Copyright (C) 2020 Microchip Technology Inc.
+#                   Eugen Hristev <eugen.hristev@microchip.com>
+#
+
+obj-y += sama7g5ek.o
diff --git a/roms/u-boot/board/atmel/sama7g5ek/sama7g5ek.c b/roms/u-boot/board/atmel/sama7g5ek/sama7g5ek.c
new file mode 100644
index 000000000..4df43d81f
--- /dev/null
+++ b/roms/u-boot/board/atmel/sama7g5ek/sama7g5ek.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Microchip Technology, Inc.
+ *		      Eugen Hristev <eugen.hristev@microchip.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama7g5.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT))
+static void board_uart0_hw_init(void)
+{
+	/* FLEXCOM3 IO0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTD, 17, ATMEL_PIO_PUEN_MASK);
+	/* FLEXCOM3 IO1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTD, 16, 0);
+
+	at91_periph_clk_enable(ATMEL_ID_FLEXCOM3);
+}
+
+void board_debug_uart_init(void)
+{
+	board_uart0_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+#if (IS_ENABLED(CONFIG_DEBUG_UART))
+	debug_uart_init();
+#endif
+	return 0;
+}
+
+#define MAC24AA_MAC_OFFSET     0xfa
+
+#if (IS_ENABLED(CONFIG_MISC_INIT_R))
+int misc_init_r(void)
+{
+#if (IS_ENABLED(CONFIG_I2C_EEPROM))
+	at91_set_ethaddr(MAC24AA_MAC_OFFSET);
+	at91_set_eth1addr(MAC24AA_MAC_OFFSET);
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
diff --git a/roms/u-boot/board/avionic-design/common/pinmux-config-tamonten-ng.h b/roms/u-boot/board/avionic-design/common/pinmux-config-tamonten-ng.h
new file mode 100644
index 000000000..e7215b190
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/common/pinmux-config-tamonten-ng.h
@@ -0,0 +1,384 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ */
+
+#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_
+#define _PINMUX_CONFIG_TAMONTEN_NG_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io)		\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{							\
+		.drvgrp		= PMUX_DRVGRP_##_drvgrp,	\
+		.slwf		= _slwf,			\
+		.slwr		= _slwr,			\
+		.drvup		= _drvup,			\
+		.drvdn		= _drvdn,			\
+		.lpmd		= PMUX_LPMD_##_lpmd,		\
+		.schmt		= PMUX_SCHMT_##_schmt,		\
+		.hsm		= PMUX_HSM_##_hsm,		\
+	}
+
+static struct pmux_pingrp_config tamonten_ng_pinmux_common[] = {
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK_PZ0,  SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD_PZ1,  SDMMC1, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP,     NORMAL, INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK_PA6,  SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD_PA7,  SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_IORDY_PI5,   RSVD1,  UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_CS6_N_PI3,   RSVD1,  UP,     NORMAL, INPUT),
+
+	/* SDMMC4 pinmux */
+	LV_PINMUX(SDMMC4_CLK_PCC4,   SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_CMD_PT7,    SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT0_PAA0,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT1_PAA1,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT2_PAA2,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT3_PAA3,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT4_PAA4,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT5_PAA5,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT6_PAA6,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT7_PAA7,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1,  DOWN,   NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* UART1 */
+	DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
+
+	/* UART2 */
+	DEFAULT_PINMUX(UART2_RXD_PC3,   UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_TXD_PC2,   UARTB, NORMAL, NORMAL, OUTPUT),
+
+	/* UART3 */
+	DEFAULT_PINMUX(UART3_TXD_PW6,   UARTC, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD_PW7,   UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+
+	/* UART4 */
+	DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
+
+	/* DAP */
+	DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+
+	/* I2S1 */
+	DEFAULT_PINMUX(DAP2_FS_PA2,   I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DIN_PA4,  I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
+
+	/* SPDIF */
+	DEFAULT_PINMUX(SPDIF_IN_PK6,  SPDIF, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
+
+	/* I2S2 */
+	DEFAULT_PINMUX(DAP3_FS_PP0,   I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN_PP1,  I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+
+	/* DAP4 */
+	DEFAULT_PINMUX(DAP4_FS_PP4,   I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DIN_PP5,  I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
+
+	/* Tamonten GPIO */
+	DEFAULT_PINMUX(PV2,            RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PV3,            RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI2_CS1_N_PW2, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* LCD */
+	DEFAULT_PINMUX(LCD_PWR1_PC1,  DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR2_PC6,  DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDIN_PZ2,  DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_WR_N_PZ3,  DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC0_PN6,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SCK_PZ4,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR0_PB2,  DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PCLK_PB3,  DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DE_PJ1,    DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D0_PE0,    DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D1_PE1,    DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D2_PE2,    DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D3_PE3,    DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D4_PE4,    DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D5_PE5,    DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D6_PE6,    DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D7_PE7,    DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D8_PF0,    DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D9_PF1,    DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D10_PF2,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D11_PF3,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D12_PF4,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D13_PF5,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D14_PF6,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D15_PF7,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D16_PM0,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D17_PM1,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D18_PM2,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D19_PM3,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D20_PM4,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D21_PM5,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D22_PM6,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D23_PM7,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_M1_PW1,    DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC1_PD2,   DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT,   NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT,   NORMAL, NORMAL, OUTPUT),
+
+	/* BT656 */
+	LV_PINMUX(VI_MCLK_PT1,  VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_PCLK_PT0,  VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_HSYNC_PD7, VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_VSYNC_PD6, VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D2_PL0,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D3_PL1,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D4_PL2,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D5_PL3,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D6_PL4,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D7_PL5,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D8_PL6,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D9_PL7,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D11_PT3,   RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* GPIOs */
+	DEFAULT_PINMUX(PU5,          RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PU6,          RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* LCD BL */
+	DEFAULT_PINMUX(GMI_AD8_PH0,  PWM0,  NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD10_PH2, RSVD4, NORMAL, NORMAL, OUTPUT),
+
+	/* SPI4 */
+	DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
+
+	/* Video input GPIO */
+	DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* Sensor GPIO */
+	DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* JTAG */
+	DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
+
+	/* Power controls */
+	DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* SPI1 */
+	DEFAULT_PINMUX(SPI1_MOSI_PX4,  SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_SCK_PX5,   SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MISO_PX7,  SPI1, NORMAL, NORMAL, INPUT),
+
+	/* PMU */
+	DEFAULT_PINMUX(PV0,             RSVD1,  UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK_32K_IN,      SYSCLK, NORMAL, NORMAL, INPUT),
+
+	/* PCI */
+	DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0,  PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_RST_N_PDD1,    PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_WAKE_N_PDD3,      PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4,  PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_RST_N_PDD5,    PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7,  PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_RST_N_PCC6,    PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+
+	/* HDMI */
+	DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC,   NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_INT_PN7,  RSVD1, NORMAL, TRISTATE, INPUT),
+};
+
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+	/* UART1 - NC */
+	DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3_PO4, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, INPUT),
+
+	/* UART2 - NC */
+	DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
+
+	/* DAP - NC */
+	DEFAULT_PINMUX(CLK1_REQ_PEE2,  RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK3_OUT_PEE0,  RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK3_REQ_PEE1,  RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* DAP4 - NC */
+	DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+
+	/* Tamonten GPIO - NC */
+	DEFAULT_PINMUX(CLK2_OUT_PW5,  EXTPERIPH2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP,        NORMAL, NORMAL, INPUT),
+
+	/* BT656 - NC */
+	LV_PINMUX(VI_D0_PT4,  RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D1_PD5,  RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* GPIO - NC */
+	DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PU4, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* Video input - NC */
+	DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB3,          RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB5,          RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB6,          RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW11_PS3,  RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* KBC keys - NC */
+	DEFAULT_PINMUX(KB_ROW0_PR0,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW1_PR1,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW2_PR2,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW3_PR3,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW4_PR4,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW5_PR5,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW6_PR6,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW7_PR7,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8_PS0,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW9_PS1,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL0_PQ0,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL1_PQ1,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL2_PQ2,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL3_PQ3,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL4_PQ4,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL5_PQ5,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL6_PQ6,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL7_PQ7,  KBC, UP, NORMAL, INPUT),
+
+	/* PMU - NC */
+	DEFAULT_PINMUX(CLK_32K_OUT_PA0, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* Power rails GPIO - NC */
+	DEFAULT_PINMUX(SPI2_SCK_PX2, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB4,         RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* Others - NC */
+	DEFAULT_PINMUX(GMI_WP_N_PC7,   RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PV1,            RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WAIT_PI7,   NAND, UP,     TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_ADV_N_PK0,  NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CLK_PK1,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS3_N_PK4,  NAND, NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_CS7_N_PI6,  NAND, UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_AD0_PG0,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD1_PG1,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD2_PG2,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD3_PG3,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD4_PG4,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD5_PG5,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD6_PG6,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD7_PG7,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD9_PH1,    PWM1, NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11_PH3,   NAND, NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_AD13_PH5,   NAND, UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_WR_N_PI0,   NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_OE_N_PI1,   NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_DQS_PI2,    NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+static struct pmux_drvgrp_config tamonten_ng_padctrl[] = {
+	/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+	DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
+		SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif	/* _PINMUX_CONFIG_TAMONTEN_NG_H_ */
diff --git a/roms/u-boot/board/avionic-design/common/tamonten-ng.c b/roms/u-boot/board/avionic-design/common/tamonten-ng.c
new file mode 100644
index 000000000..29bde6022
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/common/tamonten-ng.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include "pinmux-config-tamonten-ng.h"
+#include <i2c.h>
+
+#define PMU_I2C_ADDRESS		0x2D
+
+#define PMU_REG_LDO5		0x32
+
+#define PMU_REG_LDO_HIGH_POWER	1
+
+/* Voltage selection for the LDOs with 100mV resolution */
+#define PMU_REG_LDO_SEL_100(mV)	((((mV - 1000) / 100) + 2) << 2)
+
+#define PMU_REG_LDO_100(st, mV)	(PMU_REG_LDO_##st | PMU_REG_LDO_SEL_100(mV))
+
+#define PMU_LDO5(st, mV)	PMU_REG_LDO_100(st, mV)
+
+void pinmux_init(void)
+{
+	pinmux_config_pingrp_table(tamonten_ng_pinmux_common,
+		ARRAY_SIZE(tamonten_ng_pinmux_common));
+	pinmux_config_pingrp_table(unused_pins_lowpower,
+		ARRAY_SIZE(unused_pins_lowpower));
+
+	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
+	pinmux_config_drvgrp_table(tamonten_ng_padctrl,
+		ARRAY_SIZE(tamonten_ng_padctrl));
+}
+
+void gpio_early_init(void)
+{
+	/* Turn on the alive signal */
+	gpio_request(TEGRA_GPIO(V, 2), "ALIVE");
+	gpio_direction_output(TEGRA_GPIO(V, 2), 1);
+
+	/* Remove the reset on the external periph */
+	gpio_request(TEGRA_GPIO(I, 4), "nRST_PERIPH");
+	gpio_direction_output(TEGRA_GPIO(I, 4), 1);
+}
+
+void pmu_write(uchar reg, uchar data)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(4, PMU_I2C_ADDRESS, 1, &dev);
+	if (ret) {
+		debug("%s: Cannot find PMIC I2C chip\n", __func__);
+		return;
+	}
+	dm_i2c_write(dev, reg, &data, 1);
+}
+
+/*
+ * Do I2C/PMU writes to bring up SD card bus power
+ *
+ */
+void board_sdmmc_voltage_init(void)
+{
+	/* Enable LDO5 with 3.3v for SDMMC3 */
+	pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
+
+	/* Switch the power on */
+	gpio_request(TEGRA_GPIO(J, 2), "EN_3V3_EMMC");
+	gpio_direction_output(TEGRA_GPIO(J, 2), 1);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+	/*
+	 * NOTE: We don't do mmc-specific pin muxes here.
+	 * They were done globally in pinmux_init().
+	 */
+
+	/* Bring up the SDIO1 power rail */
+	board_sdmmc_voltage_init();
+}
diff --git a/roms/u-boot/board/avionic-design/common/tamonten.c b/roms/u-boot/board/avionic-design/common/tamonten.c
new file mode 100644
index 000000000..988f057a2
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/common/tamonten.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011-2012
+ *  Avionic Design GmbH <www.avionic-design.de>
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/uart.h>
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+void gpio_early_init(void)
+{
+	gpio_request(TEGRA_GPIO(I, 4), NULL);
+	gpio_direction_output(TEGRA_GPIO(I, 4), 1);
+}
+#endif
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
+	/* for write-protect GPIO PI6 */
+	pinmux_tristate_disable(PMUX_PINGRP_ATA);
+	/* for CD GPIO PH2 */
+	pinmux_tristate_disable(PMUX_PINGRP_ATD);
+}
+#endif
diff --git a/roms/u-boot/board/avionic-design/medcom-wide/Kconfig b/roms/u-boot/board/avionic-design/medcom-wide/Kconfig
new file mode 100644
index 000000000..267647cb4
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/medcom-wide/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MEDCOM_WIDE
+
+config SYS_BOARD
+	default "medcom-wide"
+
+config SYS_VENDOR
+	default "avionic-design"
+
+config SYS_CONFIG_NAME
+	default "medcom-wide"
+
+endif
diff --git a/roms/u-boot/board/avionic-design/medcom-wide/MAINTAINERS b/roms/u-boot/board/avionic-design/medcom-wide/MAINTAINERS
new file mode 100644
index 000000000..0a00fcf71
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/medcom-wide/MAINTAINERS
@@ -0,0 +1,6 @@
+MEDCOM-WIDE BOARD
+M:	Alban Bedel <alban.bedel@avionic-design.de>
+S:	Maintained
+F:	board/avionic-design/medcom-wide/
+F:	include/configs/medcom-wide.h
+F:	configs/medcom-wide_defconfig
diff --git a/roms/u-boot/board/avionic-design/medcom-wide/Makefile b/roms/u-boot/board/avionic-design/medcom-wide/Makefile
new file mode 100644
index 000000000..fb5fd384d
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/medcom-wide/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2010,2011
+#  NVIDIA Corporation <www.nvidia.com>
+#  (C) Copyright 2011,2012
+#  Avionic Design GmbH <www.avionic-design.de>
+
+obj-y	:= ../common/tamonten.o
diff --git a/roms/u-boot/board/avionic-design/plutux/Kconfig b/roms/u-boot/board/avionic-design/plutux/Kconfig
new file mode 100644
index 000000000..09a3ac940
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/plutux/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PLUTUX
+
+config SYS_BOARD
+	default "plutux"
+
+config SYS_VENDOR
+	default "avionic-design"
+
+config SYS_CONFIG_NAME
+	default "plutux"
+
+endif
diff --git a/roms/u-boot/board/avionic-design/plutux/MAINTAINERS b/roms/u-boot/board/avionic-design/plutux/MAINTAINERS
new file mode 100644
index 000000000..e8ef5096e
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/plutux/MAINTAINERS
@@ -0,0 +1,6 @@
+PLUTUX BOARD
+M:	Alban Bedel <alban.bedel@avionic-design.de>
+S:	Maintained
+F:	board/avionic-design/plutux/
+F:	include/configs/plutux.h
+F:	configs/plutux_defconfig
diff --git a/roms/u-boot/board/avionic-design/plutux/Makefile b/roms/u-boot/board/avionic-design/plutux/Makefile
new file mode 100644
index 000000000..fb5fd384d
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/plutux/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2010,2011
+#  NVIDIA Corporation <www.nvidia.com>
+#  (C) Copyright 2011,2012
+#  Avionic Design GmbH <www.avionic-design.de>
+
+obj-y	:= ../common/tamonten.o
diff --git a/roms/u-boot/board/avionic-design/tec-ng/Kconfig b/roms/u-boot/board/avionic-design/tec-ng/Kconfig
new file mode 100644
index 000000000..36a0cec1b
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/tec-ng/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TEC_NG
+
+config SYS_BOARD
+	default "tec-ng"
+
+config SYS_VENDOR
+	default "avionic-design"
+
+config SYS_CONFIG_NAME
+	default "tec-ng"
+
+endif
diff --git a/roms/u-boot/board/avionic-design/tec-ng/MAINTAINERS b/roms/u-boot/board/avionic-design/tec-ng/MAINTAINERS
new file mode 100644
index 000000000..5cbdf8e7e
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/tec-ng/MAINTAINERS
@@ -0,0 +1,6 @@
+TEC-NG BOARD
+M:	Alban Bedel <alban.bedel@avionic-design.de>
+S:	Maintained
+F:	board/avionic-design/tec-ng/
+F:	include/configs/tec-ng.h
+F:	configs/tec-ng_defconfig
diff --git a/roms/u-boot/board/avionic-design/tec-ng/Makefile b/roms/u-boot/board/avionic-design/tec-ng/Makefile
new file mode 100644
index 000000000..46df14d99
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/tec-ng/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2013
+# Avionic Design GmbH <www.avionic-design.de>
+
+obj-y	:= ../common/tamonten-ng.o
diff --git a/roms/u-boot/board/avionic-design/tec/Kconfig b/roms/u-boot/board/avionic-design/tec/Kconfig
new file mode 100644
index 000000000..bc9751b10
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/tec/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TEC
+
+config SYS_BOARD
+	default "tec"
+
+config SYS_VENDOR
+	default "avionic-design"
+
+config SYS_CONFIG_NAME
+	default "tec"
+
+endif
diff --git a/roms/u-boot/board/avionic-design/tec/MAINTAINERS b/roms/u-boot/board/avionic-design/tec/MAINTAINERS
new file mode 100644
index 000000000..10f1aac7a
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/tec/MAINTAINERS
@@ -0,0 +1,6 @@
+TEC BOARD
+M:	Alban Bedel <alban.bedel@avionic-design.de>
+S:	Maintained
+F:	board/avionic-design/tec/
+F:	include/configs/tec.h
+F:	configs/tec_defconfig
diff --git a/roms/u-boot/board/avionic-design/tec/Makefile b/roms/u-boot/board/avionic-design/tec/Makefile
new file mode 100644
index 000000000..fb5fd384d
--- /dev/null
+++ b/roms/u-boot/board/avionic-design/tec/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2010,2011
+#  NVIDIA Corporation <www.nvidia.com>
+#  (C) Copyright 2011,2012
+#  Avionic Design GmbH <www.avionic-design.de>
+
+obj-y	:= ../common/tamonten.o
diff --git a/roms/u-boot/board/beacon/beacon-rzg2m/Kconfig b/roms/u-boot/board/beacon/beacon-rzg2m/Kconfig
new file mode 100644
index 000000000..99c23a3d1
--- /dev/null
+++ b/roms/u-boot/board/beacon/beacon-rzg2m/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BEACON_RZG2H || TARGET_BEACON_RZG2M || TARGET_BEACON_RZG2N
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "beacon-rzg2m"
+
+config SYS_VENDOR
+	default "beacon"
+
+config SYS_CONFIG_NAME
+	default "beacon-rzg2m"
+
+endif
diff --git a/roms/u-boot/board/beacon/beacon-rzg2m/MAINTAINERS b/roms/u-boot/board/beacon/beacon-rzg2m/MAINTAINERS
new file mode 100644
index 000000000..45c269da7
--- /dev/null
+++ b/roms/u-boot/board/beacon/beacon-rzg2m/MAINTAINERS
@@ -0,0 +1,8 @@
+BEACON_RZG2M BOARD
+M:	Adam Ford <aford173@gmail.com>
+S:	Maintained
+F:	board/beacon/beacon-rzg2m/
+F:	include/configs/beacon-rzg2m.h
+F:	configs/r8a774a1_beacon_defconfig
+F:	configs/r8a774b1_beacon_defconfig
+F:	configs/r8a774e1_beacon_defconfig
diff --git a/roms/u-boot/board/beacon/beacon-rzg2m/Makefile b/roms/u-boot/board/beacon/beacon-rzg2m/Makefile
new file mode 100644
index 000000000..9131a92ef
--- /dev/null
+++ b/roms/u-boot/board/beacon/beacon-rzg2m/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/hihope-rzg2m/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y	:= beacon-rzg2m.o ../../renesas/rcar-common/common.o
diff --git a/roms/u-boot/board/beacon/beacon-rzg2m/beacon-rzg2m.c b/roms/u-boot/board/beacon/beacon-rzg2m/beacon-rzg2m.c
new file mode 100644
index 000000000..c12ff77fb
--- /dev/null
+++ b/roms/u-boot/board/beacon/beacon-rzg2m/beacon-rzg2m.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/rcar-mstp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+/* Kconfig forces this on, so just return 0 */
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	return 0;
+}
+
+#define RST_BASE	0xE6160000
+#define RST_CA57RESCNT	(RST_BASE + 0x40)
+#define RST_CODE	0xA5A5000F
+
+void reset_cpu(void)
+{
+	writel(RST_CODE, RST_CA57RESCNT);
+}
diff --git a/roms/u-boot/board/beacon/imx8mm/Kconfig b/roms/u-boot/board/beacon/imx8mm/Kconfig
new file mode 100644
index 000000000..df3125eae
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mm/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_IMX8MM_BEACON
+
+config SYS_BOARD
+	default "imx8mm"
+
+config SYS_VENDOR
+	default "beacon"
+
+config SYS_CONFIG_NAME
+	default "imx8mm_beacon"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/beacon/imx8mm/MAINTAINERS b/roms/u-boot/board/beacon/imx8mm/MAINTAINERS
new file mode 100644
index 000000000..e887db20a
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mm/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX8MM Beacon EmbeddedWorks Devkit
+
+M:	Adam Ford <aford173@gmail.com>
+S:	Maintained
+F:	board/beacon/imx8mm/
+F:	include/configs/imx8mm_beacon.h
+F:	configs/imx8mm_beacon_defconfig
diff --git a/roms/u-boot/board/beacon/imx8mm/Makefile b/roms/u-boot/board/beacon/imx8mm/Makefile
new file mode 100644
index 000000000..7d3bd3112
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mm/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2020 Compass Electronics Group, LLC
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mm_beacon.o
+obj-y += ../../freescale/common/
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += lpddr4_timing.o
+endif
diff --git a/roms/u-boot/board/beacon/imx8mm/README b/roms/u-boot/board/beacon/imx8mm/README
new file mode 100644
index 000000000..dce176fa0
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mm/README
@@ -0,0 +1,37 @@
+U-Boot for the Beacon EmbeddedWorks Devkit
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+Note: $(srctree) is U-Boot source directory
+
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ git checkout imx_4.19.35_1.0.0
+$ make PLAT=imx8mm bl31 ARCH=arm CROSS_COMPILE=aarch64-linux-gnu-
+$ cp build/imx8mm/release/bl31.bin $(srctree)
+
+Get the DDR firmware
+====================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.5.bin
+$ chmod +x firmware-imx-8.5.bin
+$ ./firmware-imx-8.5
+$ cp firmware-imx-8.5/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+
+Build U-Boot
+============
+$ make imx8mm_beacon_defconfig
+$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x920000
+
+Burn U-Boot to microSD Card
+===========================
+$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
+
+Boot
+====
+Set Boot switch to SD boot
diff --git a/roms/u-boot/board/beacon/imx8mm/imx8mm_beacon.c b/roms/u-boot/board/beacon/imx8mm/imx8mm_beacon.c
new file mode 100644
index 000000000..87ffebb57
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mm/imx8mm_beacon.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_FEC_MXC))
+		setup_fec();
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
diff --git a/roms/u-boot/board/beacon/imx8mm/lpddr4_timing.c b/roms/u-boot/board/beacon/imx8mm/lpddr4_timing.c
new file mode 100644
index 000000000..8e48b9d81
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mm/lpddr4_timing.c
@@ -0,0 +1,1980 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/* Start to config, default 3200mbps */
+	{ DDRC_DBG1(0),	0x00000001 },
+	{ DDRC_PWRCTL(0), 0x00000001 },
+	{ DDRC_MSTR(0),	0xa1080020 },
+	{ DDRC_RFSHTMG(0), 0x005b00d2 },
+	{ DDRC_INIT0(0), 0xC003061B },
+	{ DDRC_INIT1(0), 0x009D0000 },
+	{ DDRC_INIT3(0), 0x00D4002D },
+	{ DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0006004a },
+
+	{ DDRC_DRAMTMG0(0), 0x1A201B22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00C0C000 },
+	{ DDRC_DRAMTMG4(0), 0x0F04080F },
+	{ DDRC_DRAMTMG5(0), 0x02040C0C },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x00000401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0C100002 },
+	{ DDRC_DRAMTMG14(0), 0x000000E6 },
+	{ DDRC_DRAMTMG17(0), 0x00A00050 },
+
+	{ DDRC_ZQCTL0(0), 0x03200018 },
+	{ DDRC_ZQCTL1(0), 0x028061A8 },
+	{ DDRC_ZQCTL2(0), 0x00000000 },
+
+	{ DDRC_DFITMG0(0), 0x0497820A },
+	{ DDRC_DFITMG2(0), 0x0000170A },
+	{ DDRC_DRAMTMG2(0), 0x070E171a },
+	{ DDRC_DBICTL(0), 0x00000001 },
+
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xE0400018 },
+	{ DDRC_DFIUPD1(0), 0x00DF00E4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x00000011 },
+
+	{ DDRC_DFIPHYMSTR(0), 0x00000000 },
+	{ DDRC_RANKCTL(0), 0x00000c99 },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), 0x0000001f },
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	{ DDRC_ADDRMAP2(0), 0x00000000 },
+	{ DDRC_ADDRMAP3(0), 0x00000000 },
+	{ DDRC_ADDRMAP4(0), 0x00001f1f },
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	{ DDRC_ADDRMAP6(0), 0x07070707 },
+	{ DDRC_ADDRMAP7(0), 0x00000f0f },
+
+	/* performance setting */
+	{ DDRC_SCHED(0), 0x29001701 },
+	{ DDRC_SCHED1(0), 0x0000002c },
+	{ DDRC_PERFHPR1(0), 0x04000030 },
+	{ DDRC_PERFLPR1(0), 0x900093e7 },
+	{ DDRC_PERFWR1(0), 0x20005574 },
+	{ DDRC_PCCFG(0), 0x00000111 },
+	{ DDRC_PCFGW_0(0), 0x000072ff },
+	{ DDRC_PCFGQOS0_0(0), 0x02100e07 },
+	{ DDRC_PCFGQOS1_0(0), 0x00620096 },
+	{ DDRC_PCFGWQOS0_0(0), 0x01100e07 },
+	{ DDRC_PCFGWQOS1_0(0), 0x00c8012c },
+
+	/* frequency P1&P2 */
+	/* Frequency 1: 400mbps */
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
+	{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
+	{ DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03818200 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x00000000 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
+	{ DDRC_FREQ1_INIT3(0), 0x00840000 },
+	{ DDRC_FREQ1_INIT4(0), 0x00310000 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0006004a },
+
+	/* Frequency 2: 100mbps */
+	{ DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
+	{ DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
+	{ DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
+	{ DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
+	{ DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
+	{ DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
+	{ DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
+	{ DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
+	{ DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
+	{ DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
+	{ DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
+	{ DDRC_FREQ2_DFITMG0(0), 0x03818200 },
+	{ DDRC_FREQ2_DFITMG2(0), 0x00000000 },
+	{ DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
+	{ DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
+	{ DDRC_FREQ2_INIT3(0), 0x00840000 },
+	{ DDRC_FREQ2_INIT4(0), 0x00310008 },
+	{ DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+	{ DDRC_FREQ2_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ2_INIT7(0), 0x0006004a },
+
+	/* boot start point */
+	{ DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+
+	{ 0x20024, 0xab },
+	{ 0x2003a, 0x0 },
+
+	{ 0x120024, 0xab },
+	{ 0x2003a, 0x0 },
+
+	{ 0x220024, 0xab },
+	{ 0x2003a, 0x0 },
+
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0xa },
+	{ 0x220056, 0xa },
+
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+
+	{ 0x10049, 0xfbe },
+	{ 0x10149, 0xfbe },
+	{ 0x11049, 0xfbe },
+	{ 0x11149, 0xfbe },
+	{ 0x12049, 0xfbe },
+	{ 0x12149, 0xfbe },
+	{ 0x13049, 0xfbe },
+	{ 0x13149, 0xfbe },
+
+	{ 0x110049, 0xfbe },
+	{ 0x110149, 0xfbe },
+	{ 0x111049, 0xfbe },
+	{ 0x111149, 0xfbe },
+	{ 0x112049, 0xfbe },
+	{ 0x112149, 0xfbe },
+	{ 0x113049, 0xfbe },
+	{ 0x113149, 0xfbe },
+
+	{ 0x210049, 0xfbe },
+	{ 0x210149, 0xfbe },
+	{ 0x211049, 0xfbe },
+	{ 0x211149, 0xfbe },
+	{ 0x212049, 0xfbe },
+	{ 0x212149, 0xfbe },
+	{ 0x213049, 0xfbe },
+	{ 0x213149, 0xfbe },
+
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x2ee },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+
+	{ 0x200b2, 0x1d4 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+
+	{ 0x20025, 0x0 },
+	{ 0x2002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x12002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x22002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x2200c7, 0x21 },
+	{ 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xf },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a7, 0x0 },
+	{ 0x900a8, 0x790 },
+	{ 0x900a9, 0x11a },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x7b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x0 },
+	{ 0x900b1, 0x7c8 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xc },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x0 },
+	{ 0x90169, 0x8 },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x448 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
+	{ 0x9016e, 0x7c0 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x7c8 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x5d },
+	{ 0x2000c, 0xbb },
+	{ 0x2000d, 0x753 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x2003a, 0x2 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P1 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+	},
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+};
diff --git a/roms/u-boot/board/beacon/imx8mm/spl.c b/roms/u-boot/board/beacon/imx8mm/spl.c
new file mode 100644
index 000000000..12266b22a
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mm/spl.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/pmic.h>
+#include <power/bd71837.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+static void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+	debug("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+static int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pmic@4b", &dev);
+	if (ret == -ENODEV) {
+		puts("No pmic\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
+
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+
+	/* unlock the PMIC regs */
+	pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+
+	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
+	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+	pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+
+	/* lock the PMIC regs */
+	pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+
+	arch_cpu_init();
+
+	init_uart_clk(1);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0) {
+		printf("Failed to find clock node. Check device tree\n");
+		hang();
+	}
+
+	enable_tzc380();
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/beacon/imx8mn/Kconfig b/roms/u-boot/board/beacon/imx8mn/Kconfig
new file mode 100644
index 000000000..2bcfb25cf
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mn/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_IMX8MN_BEACON
+
+config SYS_BOARD
+	default "imx8mn"
+
+config SYS_VENDOR
+	default "beacon"
+
+config SYS_CONFIG_NAME
+	default "imx8mn_beacon"
+
+config IMX8MN_FORCE_NOM_SOC
+	bool "Force to use nominal mode for SOC and ARM"
+	default n
+
+config IMX8MN_BEACON_2GB_LPDDR
+	bool "Enable 2GB LPDDR"
+	default n
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/beacon/imx8mn/MAINTAINERS b/roms/u-boot/board/beacon/imx8mn/MAINTAINERS
new file mode 100644
index 000000000..4805cb255
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mn/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX8MN BEACON BOARD
+M:	Adam Ford <aford173@gmail.com>
+S:	Maintained
+F:	board/beacon/imx8mn/
+F:	include/configs/imx8mn_beacon.h
+F:	configs/imx8mn_beacon_defconfig
+F:	configs/imx8mn_beacon_2g_defconfig
diff --git a/roms/u-boot/board/beacon/imx8mn/Makefile b/roms/u-boot/board/beacon/imx8mn/Makefile
new file mode 100644
index 000000000..d620ccb77
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mn/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright 2020 Compass Electronics Group, LLC
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mn_beacon.o
+obj-y += ../../freescale/common/
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+ifdef CONFIG_IMX8MN_BEACON_2GB_LPDDR
+obj-y += lpddr4_2g_timing.o
+else
+obj-y += lpddr4_timing.o
+endif
+endif
diff --git a/roms/u-boot/board/beacon/imx8mn/README b/roms/u-boot/board/beacon/imx8mn/README
new file mode 100644
index 000000000..d3c90d31d
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mn/README
@@ -0,0 +1,39 @@
+U-Boot for the Beacon EmbeddedWorks i.MX8M Nano Devkit
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+Note: $(srctree) is U-Boot source directory
+
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ git checkout imx_5.4.47_2.2.0
+$ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu-
+$ cp build/imx8mm/release/bl31.bin $(srctree)
+
+Get the DDR firmware
+====================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+$ chmod +x firmware-imx-8.9.bin
+$ ./firmware-imx-8.9
+$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+
+Build U-Boot
+============
+$ make imx8mn_beacon_defconfig
+$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x960000
+
+Burn U-Boot to microSD Card
+===========================
+$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
+
+Boot
+====
+Set baseboard DIP switch:
+S17: 1100XXXX
+
diff --git a/roms/u-boot/board/beacon/imx8mn/imx8mn_beacon.c b/roms/u-boot/board/beacon/imx8mn/imx8mn_beacon.c
new file mode 100644
index 000000000..7fe252b26
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mn/imx8mn_beacon.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_FEC_MXC))
+		setup_fec();
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return CONFIG_SYS_MMC_ENV_DEV;
+}
diff --git a/roms/u-boot/board/beacon/imx8mn/lpddr4_2g_timing.c b/roms/u-boot/board/beacon/imx8mn/lpddr4_2g_timing.c
new file mode 100644
index 000000000..3c32d804a
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mn/lpddr4_2g_timing.c
@@ -0,0 +1,1440 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa3080020 },
+	{ 0x3d400020, 0x202 },
+	{ 0x3d400024, 0x3e800 },
+	{ 0x3d400064, 0x3000e0 },
+	{ 0x3d4000d0, 0xc003061c },
+	{ 0x3d4000d4, 0x9e0000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000ec, 0x16004d },
+	{ 0x3d400100, 0x1a200d22 },
+	{ 0x3d400104, 0x60633 },
+	{ 0x3d40010c, 0xc0c000 },
+	{ 0x3d400110, 0xf04080f },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x401 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0xe6 },
+	{ 0x3d400144, 0xa00050 },
+	{ 0x3d400180, 0x3200018 },
+	{ 0x3d400184, 0x28061a8 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x17 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d400250, 0x29001701 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x0 },
+	{ 0x3d402024, 0x7d00 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0x6001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020ec, 0x16004d },
+	{ 0x3d402100, 0xa040105 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x0 },
+	{ 0x3d403024, 0x1f40 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x310000 },
+	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030ec, 0x16004d },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x3 },
+	{ 0x100a3, 0x2 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x7 },
+	{ 0x100a7, 0x6 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x2 },
+	{ 0x110a3, 0x3 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x4 },
+	{ 0x110a6, 0x6 },
+	{ 0x110a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x320 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2005b, 0x7529 },
+	{ 0x2005c, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x200cc, 0x1f7 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x1200cc, 0x1f7 },
+	{ 0x2200c7, 0x21 },
+	{ 0x2200ca, 0x24 },
+	{ 0x2200cc, 0x1f7 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2, 0x0},
+	{0x1200b2, 0x0},
+	{0x2200b2, 0x0},
+	{0x0200cb, 0x0},
+	{0x010043, 0x0},
+	{0x110043, 0x0},
+	{0x210043, 0x0},
+	{0x010143, 0x0},
+	{0x110143, 0x0},
+	{0x210143, 0x0},
+	{0x011043, 0x0},
+	{0x111043, 0x0},
+	{0x211043, 0x0},
+	{0x011143, 0x0},
+	{0x111143, 0x0},
+	{0x211143, 0x0},
+	{0x000080, 0x0},
+	{0x100080, 0x0},
+	{0x200080, 0x0},
+	{0x001080, 0x0},
+	{0x101080, 0x0},
+	{0x201080, 0x0},
+	{0x002080, 0x0},
+	{0x102080, 0x0},
+	{0x202080, 0x0},
+	{0x003080, 0x0},
+	{0x103080, 0x0},
+	{0x203080, 0x0},
+	{0x004080, 0x0},
+	{0x104080, 0x0},
+	{0x204080, 0x0},
+	{0x005080, 0x0},
+	{0x105080, 0x0},
+	{0x205080, 0x0},
+	{0x006080, 0x0},
+	{0x106080, 0x0},
+	{0x206080, 0x0},
+	{0x007080, 0x0},
+	{0x107080, 0x0},
+	{0x207080, 0x0},
+	{0x008080, 0x0},
+	{0x108080, 0x0},
+	{0x208080, 0x0},
+	{0x009080, 0x0},
+	{0x109080, 0x0},
+	{0x209080, 0x0},
+	{0x010080, 0x0},
+	{0x110080, 0x0},
+	{0x210080, 0x0},
+	{0x010180, 0x0},
+	{0x110180, 0x0},
+	{0x210180, 0x0},
+	{0x011080, 0x0},
+	{0x111080, 0x0},
+	{0x211080, 0x0},
+	{0x011180, 0x0},
+	{0x111180, 0x0},
+	{0x211180, 0x0},
+	{0x010081, 0x0},
+	{0x110081, 0x0},
+	{0x210081, 0x0},
+	{0x010181, 0x0},
+	{0x110181, 0x0},
+	{0x210181, 0x0},
+	{0x011081, 0x0},
+	{0x111081, 0x0},
+	{0x211081, 0x0},
+	{0x011181, 0x0},
+	{0x111181, 0x0},
+	{0x211181, 0x0},
+	{0x0100d0, 0x0},
+	{0x1100d0, 0x0},
+	{0x2100d0, 0x0},
+	{0x0101d0, 0x0},
+	{0x1101d0, 0x0},
+	{0x2101d0, 0x0},
+	{0x0110d0, 0x0},
+	{0x1110d0, 0x0},
+	{0x2110d0, 0x0},
+	{0x0111d0, 0x0},
+	{0x1111d0, 0x0},
+	{0x2111d0, 0x0},
+	{0x0100d1, 0x0},
+	{0x1100d1, 0x0},
+	{0x2100d1, 0x0},
+	{0x0101d1, 0x0},
+	{0x1101d1, 0x0},
+	{0x2101d1, 0x0},
+	{0x0110d1, 0x0},
+	{0x1110d1, 0x0},
+	{0x2110d1, 0x0},
+	{0x0111d1, 0x0},
+	{0x1111d1, 0x0},
+	{0x2111d1, 0x0},
+	{0x010068, 0x0},
+	{0x010168, 0x0},
+	{0x010268, 0x0},
+	{0x010368, 0x0},
+	{0x010468, 0x0},
+	{0x010568, 0x0},
+	{0x010668, 0x0},
+	{0x010768, 0x0},
+	{0x010868, 0x0},
+	{0x011068, 0x0},
+	{0x011168, 0x0},
+	{0x011268, 0x0},
+	{0x011368, 0x0},
+	{0x011468, 0x0},
+	{0x011568, 0x0},
+	{0x011668, 0x0},
+	{0x011768, 0x0},
+	{0x011868, 0x0},
+	{0x010069, 0x0},
+	{0x010169, 0x0},
+	{0x010269, 0x0},
+	{0x010369, 0x0},
+	{0x010469, 0x0},
+	{0x010569, 0x0},
+	{0x010669, 0x0},
+	{0x010769, 0x0},
+	{0x010869, 0x0},
+	{0x011069, 0x0},
+	{0x011169, 0x0},
+	{0x011269, 0x0},
+	{0x011369, 0x0},
+	{0x011469, 0x0},
+	{0x011569, 0x0},
+	{0x011669, 0x0},
+	{0x011769, 0x0},
+	{0x011869, 0x0},
+	{0x01008c, 0x0},
+	{0x11008c, 0x0},
+	{0x21008c, 0x0},
+	{0x01018c, 0x0},
+	{0x11018c, 0x0},
+	{0x21018c, 0x0},
+	{0x01108c, 0x0},
+	{0x11108c, 0x0},
+	{0x21108c, 0x0},
+	{0x01118c, 0x0},
+	{0x11118c, 0x0},
+	{0x21118c, 0x0},
+	{0x01008d, 0x0},
+	{0x11008d, 0x0},
+	{0x21008d, 0x0},
+	{0x01018d, 0x0},
+	{0x11018d, 0x0},
+	{0x21018d, 0x0},
+	{0x01108d, 0x0},
+	{0x11108d, 0x0},
+	{0x21108d, 0x0},
+	{0x01118d, 0x0},
+	{0x11118d, 0x0},
+	{0x21118d, 0x0},
+	{0x0100c0, 0x0},
+	{0x1100c0, 0x0},
+	{0x2100c0, 0x0},
+	{0x0101c0, 0x0},
+	{0x1101c0, 0x0},
+	{0x2101c0, 0x0},
+	{0x0102c0, 0x0},
+	{0x1102c0, 0x0},
+	{0x2102c0, 0x0},
+	{0x0103c0, 0x0},
+	{0x1103c0, 0x0},
+	{0x2103c0, 0x0},
+	{0x0104c0, 0x0},
+	{0x1104c0, 0x0},
+	{0x2104c0, 0x0},
+	{0x0105c0, 0x0},
+	{0x1105c0, 0x0},
+	{0x2105c0, 0x0},
+	{0x0106c0, 0x0},
+	{0x1106c0, 0x0},
+	{0x2106c0, 0x0},
+	{0x0107c0, 0x0},
+	{0x1107c0, 0x0},
+	{0x2107c0, 0x0},
+	{0x0108c0, 0x0},
+	{0x1108c0, 0x0},
+	{0x2108c0, 0x0},
+	{0x0110c0, 0x0},
+	{0x1110c0, 0x0},
+	{0x2110c0, 0x0},
+	{0x0111c0, 0x0},
+	{0x1111c0, 0x0},
+	{0x2111c0, 0x0},
+	{0x0112c0, 0x0},
+	{0x1112c0, 0x0},
+	{0x2112c0, 0x0},
+	{0x0113c0, 0x0},
+	{0x1113c0, 0x0},
+	{0x2113c0, 0x0},
+	{0x0114c0, 0x0},
+	{0x1114c0, 0x0},
+	{0x2114c0, 0x0},
+	{0x0115c0, 0x0},
+	{0x1115c0, 0x0},
+	{0x2115c0, 0x0},
+	{0x0116c0, 0x0},
+	{0x1116c0, 0x0},
+	{0x2116c0, 0x0},
+	{0x0117c0, 0x0},
+	{0x1117c0, 0x0},
+	{0x2117c0, 0x0},
+	{0x0118c0, 0x0},
+	{0x1118c0, 0x0},
+	{0x2118c0, 0x0},
+	{0x0100c1, 0x0},
+	{0x1100c1, 0x0},
+	{0x2100c1, 0x0},
+	{0x0101c1, 0x0},
+	{0x1101c1, 0x0},
+	{0x2101c1, 0x0},
+	{0x0102c1, 0x0},
+	{0x1102c1, 0x0},
+	{0x2102c1, 0x0},
+	{0x0103c1, 0x0},
+	{0x1103c1, 0x0},
+	{0x2103c1, 0x0},
+	{0x0104c1, 0x0},
+	{0x1104c1, 0x0},
+	{0x2104c1, 0x0},
+	{0x0105c1, 0x0},
+	{0x1105c1, 0x0},
+	{0x2105c1, 0x0},
+	{0x0106c1, 0x0},
+	{0x1106c1, 0x0},
+	{0x2106c1, 0x0},
+	{0x0107c1, 0x0},
+	{0x1107c1, 0x0},
+	{0x2107c1, 0x0},
+	{0x0108c1, 0x0},
+	{0x1108c1, 0x0},
+	{0x2108c1, 0x0},
+	{0x0110c1, 0x0},
+	{0x1110c1, 0x0},
+	{0x2110c1, 0x0},
+	{0x0111c1, 0x0},
+	{0x1111c1, 0x0},
+	{0x2111c1, 0x0},
+	{0x0112c1, 0x0},
+	{0x1112c1, 0x0},
+	{0x2112c1, 0x0},
+	{0x0113c1, 0x0},
+	{0x1113c1, 0x0},
+	{0x2113c1, 0x0},
+	{0x0114c1, 0x0},
+	{0x1114c1, 0x0},
+	{0x2114c1, 0x0},
+	{0x0115c1, 0x0},
+	{0x1115c1, 0x0},
+	{0x2115c1, 0x0},
+	{0x0116c1, 0x0},
+	{0x1116c1, 0x0},
+	{0x2116c1, 0x0},
+	{0x0117c1, 0x0},
+	{0x1117c1, 0x0},
+	{0x2117c1, 0x0},
+	{0x0118c1, 0x0},
+	{0x1118c1, 0x0},
+	{0x2118c1, 0x0},
+	{0x010020, 0x0},
+	{0x110020, 0x0},
+	{0x210020, 0x0},
+	{0x011020, 0x0},
+	{0x111020, 0x0},
+	{0x211020, 0x0},
+	{0x020072, 0x0},
+	{0x020073, 0x0},
+	{0x020074, 0x0},
+	{0x0100aa, 0x0},
+	{0x0110aa, 0x0},
+	{0x020010, 0x0},
+	{0x120010, 0x0},
+	{0x220010, 0x0},
+	{0x020011, 0x0},
+	{0x120011, 0x0},
+	{0x220011, 0x0},
+	{0x0100ae, 0x0},
+	{0x1100ae, 0x0},
+	{0x2100ae, 0x0},
+	{0x0100af, 0x0},
+	{0x1100af, 0x0},
+	{0x2100af, 0x0},
+	{0x0110ae, 0x0},
+	{0x1110ae, 0x0},
+	{0x2110ae, 0x0},
+	{0x0110af, 0x0},
+	{0x1110af, 0x0},
+	{0x2110af, 0x0},
+	{0x020020, 0x0},
+	{0x120020, 0x0},
+	{0x220020, 0x0},
+	{0x0100a0, 0x0},
+	{0x0100a1, 0x0},
+	{0x0100a2, 0x0},
+	{0x0100a3, 0x0},
+	{0x0100a4, 0x0},
+	{0x0100a5, 0x0},
+	{0x0100a6, 0x0},
+	{0x0100a7, 0x0},
+	{0x0110a0, 0x0},
+	{0x0110a1, 0x0},
+	{0x0110a2, 0x0},
+	{0x0110a3, 0x0},
+	{0x0110a4, 0x0},
+	{0x0110a5, 0x0},
+	{0x0110a6, 0x0},
+	{0x0110a7, 0x0},
+	{0x02007c, 0x0},
+	{0x12007c, 0x0},
+	{0x22007c, 0x0},
+	{0x02007d, 0x0},
+	{0x12007d, 0x0},
+	{0x22007d, 0x0},
+	{0x0400fd, 0x0},
+	{0x0400c0, 0x0},
+	{0x090201, 0x0},
+	{0x190201, 0x0},
+	{0x290201, 0x0},
+	{0x090202, 0x0},
+	{0x190202, 0x0},
+	{0x290202, 0x0},
+	{0x090203, 0x0},
+	{0x190203, 0x0},
+	{0x290203, 0x0},
+	{0x090204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x090205, 0x0},
+	{0x190205, 0x0},
+	{0x290205, 0x0},
+	{0x090206, 0x0},
+	{0x190206, 0x0},
+	{0x290206, 0x0},
+	{0x090207, 0x0},
+	{0x190207, 0x0},
+	{0x290207, 0x0},
+	{0x090208, 0x0},
+	{0x190208, 0x0},
+	{0x290208, 0x0},
+	{0x010062, 0x0},
+	{0x010162, 0x0},
+	{0x010262, 0x0},
+	{0x010362, 0x0},
+	{0x010462, 0x0},
+	{0x010562, 0x0},
+	{0x010662, 0x0},
+	{0x010762, 0x0},
+	{0x010862, 0x0},
+	{0x011062, 0x0},
+	{0x011162, 0x0},
+	{0x011262, 0x0},
+	{0x011362, 0x0},
+	{0x011462, 0x0},
+	{0x011562, 0x0},
+	{0x011662, 0x0},
+	{0x011762, 0x0},
+	{0x011862, 0x0},
+	{0x020077, 0x0},
+	{0x010001, 0x0},
+	{0x011001, 0x0},
+	{0x010040, 0x0},
+	{0x010140, 0x0},
+	{0x010240, 0x0},
+	{0x010340, 0x0},
+	{0x010440, 0x0},
+	{0x010540, 0x0},
+	{0x010640, 0x0},
+	{0x010740, 0x0},
+	{0x010840, 0x0},
+	{0x010030, 0x0},
+	{0x010130, 0x0},
+	{0x010230, 0x0},
+	{0x010330, 0x0},
+	{0x010430, 0x0},
+	{0x010530, 0x0},
+	{0x010630, 0x0},
+	{0x010730, 0x0},
+	{0x010830, 0x0},
+	{0x011040, 0x0},
+	{0x011140, 0x0},
+	{0x011240, 0x0},
+	{0x011340, 0x0},
+	{0x011440, 0x0},
+	{0x011540, 0x0},
+	{0x011640, 0x0},
+	{0x011740, 0x0},
+	{0x011840, 0x0},
+	{0x011030, 0x0},
+	{0x011130, 0x0},
+	{0x011230, 0x0},
+	{0x011330, 0x0},
+	{0x011430, 0x0},
+	{0x011530, 0x0},
+	{0x011630, 0x0},
+	{0x011730, 0x0},
+	{0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x448 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0xf },
+	{ 0x9016b, 0x7c0 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x0 },
+	{ 0x9016e, 0xe8 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x47 },
+	{ 0x90171, 0x630 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x8 },
+	{ 0x90174, 0x618 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0xe0 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x7c8 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x8 },
+	{ 0x9017d, 0x8140 },
+	{ 0x9017e, 0x10c },
+	{ 0x9017f, 0x0 },
+	{ 0x90180, 0x1 },
+	{ 0x90181, 0x8 },
+	{ 0x90182, 0x8 },
+	{ 0x90183, 0x4 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x7c8 },
+	{ 0x90187, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x7d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 400, 100, },
+};
diff --git a/roms/u-boot/board/beacon/imx8mn/lpddr4_timing.c b/roms/u-boot/board/beacon/imx8mn/lpddr4_timing.c
new file mode 100644
index 000000000..3c1ad392f
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mn/lpddr4_timing.c
@@ -0,0 +1,1434 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400020, 0x202 },
+	{ 0x3d400024, 0x3e800 },
+	{ 0x3d400064, 0x3000e0 },
+	{ 0x3d4000d0, 0xc003061c },
+	{ 0x3d4000d4, 0x9e0000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000ec, 0x16004d },
+	{ 0x3d400100, 0x1a200d22 },
+	{ 0x3d400104, 0x60633 },
+	{ 0x3d40010c, 0xc0c000 },
+	{ 0x3d400110, 0xf04080f },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x401 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0xe6 },
+	{ 0x3d400144, 0xa00050 },
+	{ 0x3d400180, 0x3200018 },
+	{ 0x3d400184, 0x28061a8 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d400250, 0x29001701 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x0 },
+	{ 0x3d402024, 0x7d00 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0x6001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020ec, 0x16004d },
+	{ 0x3d402100, 0xa040105 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x0 },
+	{ 0x3d403024, 0x1f40 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x310000 },
+	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030ec, 0x16004d },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x3 },
+	{ 0x100a3, 0x2 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x7 },
+	{ 0x100a7, 0x6 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x2 },
+	{ 0x110a3, 0x3 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x4 },
+	{ 0x110a6, 0x6 },
+	{ 0x110a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x320 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2005b, 0x7529 },
+	{ 0x2005c, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x200cc, 0x1f7 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x1200cc, 0x1f7 },
+	{ 0x2200c7, 0x21 },
+	{ 0x2200ca, 0x24 },
+	{ 0x2200cc, 0x1f7 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2, 0x0},
+	{0x1200b2, 0x0},
+	{0x2200b2, 0x0},
+	{0x0200cb, 0x0},
+	{0x010043, 0x0},
+	{0x110043, 0x0},
+	{0x210043, 0x0},
+	{0x010143, 0x0},
+	{0x110143, 0x0},
+	{0x210143, 0x0},
+	{0x011043, 0x0},
+	{0x111043, 0x0},
+	{0x211043, 0x0},
+	{0x011143, 0x0},
+	{0x111143, 0x0},
+	{0x211143, 0x0},
+	{0x000080, 0x0},
+	{0x100080, 0x0},
+	{0x200080, 0x0},
+	{0x001080, 0x0},
+	{0x101080, 0x0},
+	{0x201080, 0x0},
+	{0x002080, 0x0},
+	{0x102080, 0x0},
+	{0x202080, 0x0},
+	{0x003080, 0x0},
+	{0x103080, 0x0},
+	{0x203080, 0x0},
+	{0x004080, 0x0},
+	{0x104080, 0x0},
+	{0x204080, 0x0},
+	{0x005080, 0x0},
+	{0x105080, 0x0},
+	{0x205080, 0x0},
+	{0x006080, 0x0},
+	{0x106080, 0x0},
+	{0x206080, 0x0},
+	{0x007080, 0x0},
+	{0x107080, 0x0},
+	{0x207080, 0x0},
+	{0x008080, 0x0},
+	{0x108080, 0x0},
+	{0x208080, 0x0},
+	{0x009080, 0x0},
+	{0x109080, 0x0},
+	{0x209080, 0x0},
+	{0x010080, 0x0},
+	{0x110080, 0x0},
+	{0x210080, 0x0},
+	{0x010180, 0x0},
+	{0x110180, 0x0},
+	{0x210180, 0x0},
+	{0x011080, 0x0},
+	{0x111080, 0x0},
+	{0x211080, 0x0},
+	{0x011180, 0x0},
+	{0x111180, 0x0},
+	{0x211180, 0x0},
+	{0x010081, 0x0},
+	{0x110081, 0x0},
+	{0x210081, 0x0},
+	{0x010181, 0x0},
+	{0x110181, 0x0},
+	{0x210181, 0x0},
+	{0x011081, 0x0},
+	{0x111081, 0x0},
+	{0x211081, 0x0},
+	{0x011181, 0x0},
+	{0x111181, 0x0},
+	{0x211181, 0x0},
+	{0x0100d0, 0x0},
+	{0x1100d0, 0x0},
+	{0x2100d0, 0x0},
+	{0x0101d0, 0x0},
+	{0x1101d0, 0x0},
+	{0x2101d0, 0x0},
+	{0x0110d0, 0x0},
+	{0x1110d0, 0x0},
+	{0x2110d0, 0x0},
+	{0x0111d0, 0x0},
+	{0x1111d0, 0x0},
+	{0x2111d0, 0x0},
+	{0x0100d1, 0x0},
+	{0x1100d1, 0x0},
+	{0x2100d1, 0x0},
+	{0x0101d1, 0x0},
+	{0x1101d1, 0x0},
+	{0x2101d1, 0x0},
+	{0x0110d1, 0x0},
+	{0x1110d1, 0x0},
+	{0x2110d1, 0x0},
+	{0x0111d1, 0x0},
+	{0x1111d1, 0x0},
+	{0x2111d1, 0x0},
+	{0x010068, 0x0},
+	{0x010168, 0x0},
+	{0x010268, 0x0},
+	{0x010368, 0x0},
+	{0x010468, 0x0},
+	{0x010568, 0x0},
+	{0x010668, 0x0},
+	{0x010768, 0x0},
+	{0x010868, 0x0},
+	{0x011068, 0x0},
+	{0x011168, 0x0},
+	{0x011268, 0x0},
+	{0x011368, 0x0},
+	{0x011468, 0x0},
+	{0x011568, 0x0},
+	{0x011668, 0x0},
+	{0x011768, 0x0},
+	{0x011868, 0x0},
+	{0x010069, 0x0},
+	{0x010169, 0x0},
+	{0x010269, 0x0},
+	{0x010369, 0x0},
+	{0x010469, 0x0},
+	{0x010569, 0x0},
+	{0x010669, 0x0},
+	{0x010769, 0x0},
+	{0x010869, 0x0},
+	{0x011069, 0x0},
+	{0x011169, 0x0},
+	{0x011269, 0x0},
+	{0x011369, 0x0},
+	{0x011469, 0x0},
+	{0x011569, 0x0},
+	{0x011669, 0x0},
+	{0x011769, 0x0},
+	{0x011869, 0x0},
+	{0x01008c, 0x0},
+	{0x11008c, 0x0},
+	{0x21008c, 0x0},
+	{0x01018c, 0x0},
+	{0x11018c, 0x0},
+	{0x21018c, 0x0},
+	{0x01108c, 0x0},
+	{0x11108c, 0x0},
+	{0x21108c, 0x0},
+	{0x01118c, 0x0},
+	{0x11118c, 0x0},
+	{0x21118c, 0x0},
+	{0x01008d, 0x0},
+	{0x11008d, 0x0},
+	{0x21008d, 0x0},
+	{0x01018d, 0x0},
+	{0x11018d, 0x0},
+	{0x21018d, 0x0},
+	{0x01108d, 0x0},
+	{0x11108d, 0x0},
+	{0x21108d, 0x0},
+	{0x01118d, 0x0},
+	{0x11118d, 0x0},
+	{0x21118d, 0x0},
+	{0x0100c0, 0x0},
+	{0x1100c0, 0x0},
+	{0x2100c0, 0x0},
+	{0x0101c0, 0x0},
+	{0x1101c0, 0x0},
+	{0x2101c0, 0x0},
+	{0x0102c0, 0x0},
+	{0x1102c0, 0x0},
+	{0x2102c0, 0x0},
+	{0x0103c0, 0x0},
+	{0x1103c0, 0x0},
+	{0x2103c0, 0x0},
+	{0x0104c0, 0x0},
+	{0x1104c0, 0x0},
+	{0x2104c0, 0x0},
+	{0x0105c0, 0x0},
+	{0x1105c0, 0x0},
+	{0x2105c0, 0x0},
+	{0x0106c0, 0x0},
+	{0x1106c0, 0x0},
+	{0x2106c0, 0x0},
+	{0x0107c0, 0x0},
+	{0x1107c0, 0x0},
+	{0x2107c0, 0x0},
+	{0x0108c0, 0x0},
+	{0x1108c0, 0x0},
+	{0x2108c0, 0x0},
+	{0x0110c0, 0x0},
+	{0x1110c0, 0x0},
+	{0x2110c0, 0x0},
+	{0x0111c0, 0x0},
+	{0x1111c0, 0x0},
+	{0x2111c0, 0x0},
+	{0x0112c0, 0x0},
+	{0x1112c0, 0x0},
+	{0x2112c0, 0x0},
+	{0x0113c0, 0x0},
+	{0x1113c0, 0x0},
+	{0x2113c0, 0x0},
+	{0x0114c0, 0x0},
+	{0x1114c0, 0x0},
+	{0x2114c0, 0x0},
+	{0x0115c0, 0x0},
+	{0x1115c0, 0x0},
+	{0x2115c0, 0x0},
+	{0x0116c0, 0x0},
+	{0x1116c0, 0x0},
+	{0x2116c0, 0x0},
+	{0x0117c0, 0x0},
+	{0x1117c0, 0x0},
+	{0x2117c0, 0x0},
+	{0x0118c0, 0x0},
+	{0x1118c0, 0x0},
+	{0x2118c0, 0x0},
+	{0x0100c1, 0x0},
+	{0x1100c1, 0x0},
+	{0x2100c1, 0x0},
+	{0x0101c1, 0x0},
+	{0x1101c1, 0x0},
+	{0x2101c1, 0x0},
+	{0x0102c1, 0x0},
+	{0x1102c1, 0x0},
+	{0x2102c1, 0x0},
+	{0x0103c1, 0x0},
+	{0x1103c1, 0x0},
+	{0x2103c1, 0x0},
+	{0x0104c1, 0x0},
+	{0x1104c1, 0x0},
+	{0x2104c1, 0x0},
+	{0x0105c1, 0x0},
+	{0x1105c1, 0x0},
+	{0x2105c1, 0x0},
+	{0x0106c1, 0x0},
+	{0x1106c1, 0x0},
+	{0x2106c1, 0x0},
+	{0x0107c1, 0x0},
+	{0x1107c1, 0x0},
+	{0x2107c1, 0x0},
+	{0x0108c1, 0x0},
+	{0x1108c1, 0x0},
+	{0x2108c1, 0x0},
+	{0x0110c1, 0x0},
+	{0x1110c1, 0x0},
+	{0x2110c1, 0x0},
+	{0x0111c1, 0x0},
+	{0x1111c1, 0x0},
+	{0x2111c1, 0x0},
+	{0x0112c1, 0x0},
+	{0x1112c1, 0x0},
+	{0x2112c1, 0x0},
+	{0x0113c1, 0x0},
+	{0x1113c1, 0x0},
+	{0x2113c1, 0x0},
+	{0x0114c1, 0x0},
+	{0x1114c1, 0x0},
+	{0x2114c1, 0x0},
+	{0x0115c1, 0x0},
+	{0x1115c1, 0x0},
+	{0x2115c1, 0x0},
+	{0x0116c1, 0x0},
+	{0x1116c1, 0x0},
+	{0x2116c1, 0x0},
+	{0x0117c1, 0x0},
+	{0x1117c1, 0x0},
+	{0x2117c1, 0x0},
+	{0x0118c1, 0x0},
+	{0x1118c1, 0x0},
+	{0x2118c1, 0x0},
+	{0x010020, 0x0},
+	{0x110020, 0x0},
+	{0x210020, 0x0},
+	{0x011020, 0x0},
+	{0x111020, 0x0},
+	{0x211020, 0x0},
+	{0x020072, 0x0},
+	{0x020073, 0x0},
+	{0x020074, 0x0},
+	{0x0100aa, 0x0},
+	{0x0110aa, 0x0},
+	{0x020010, 0x0},
+	{0x120010, 0x0},
+	{0x220010, 0x0},
+	{0x020011, 0x0},
+	{0x120011, 0x0},
+	{0x220011, 0x0},
+	{0x0100ae, 0x0},
+	{0x1100ae, 0x0},
+	{0x2100ae, 0x0},
+	{0x0100af, 0x0},
+	{0x1100af, 0x0},
+	{0x2100af, 0x0},
+	{0x0110ae, 0x0},
+	{0x1110ae, 0x0},
+	{0x2110ae, 0x0},
+	{0x0110af, 0x0},
+	{0x1110af, 0x0},
+	{0x2110af, 0x0},
+	{0x020020, 0x0},
+	{0x120020, 0x0},
+	{0x220020, 0x0},
+	{0x0100a0, 0x0},
+	{0x0100a1, 0x0},
+	{0x0100a2, 0x0},
+	{0x0100a3, 0x0},
+	{0x0100a4, 0x0},
+	{0x0100a5, 0x0},
+	{0x0100a6, 0x0},
+	{0x0100a7, 0x0},
+	{0x0110a0, 0x0},
+	{0x0110a1, 0x0},
+	{0x0110a2, 0x0},
+	{0x0110a3, 0x0},
+	{0x0110a4, 0x0},
+	{0x0110a5, 0x0},
+	{0x0110a6, 0x0},
+	{0x0110a7, 0x0},
+	{0x02007c, 0x0},
+	{0x12007c, 0x0},
+	{0x22007c, 0x0},
+	{0x02007d, 0x0},
+	{0x12007d, 0x0},
+	{0x22007d, 0x0},
+	{0x0400fd, 0x0},
+	{0x0400c0, 0x0},
+	{0x090201, 0x0},
+	{0x190201, 0x0},
+	{0x290201, 0x0},
+	{0x090202, 0x0},
+	{0x190202, 0x0},
+	{0x290202, 0x0},
+	{0x090203, 0x0},
+	{0x190203, 0x0},
+	{0x290203, 0x0},
+	{0x090204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x090205, 0x0},
+	{0x190205, 0x0},
+	{0x290205, 0x0},
+	{0x090206, 0x0},
+	{0x190206, 0x0},
+	{0x290206, 0x0},
+	{0x090207, 0x0},
+	{0x190207, 0x0},
+	{0x290207, 0x0},
+	{0x090208, 0x0},
+	{0x190208, 0x0},
+	{0x290208, 0x0},
+	{0x010062, 0x0},
+	{0x010162, 0x0},
+	{0x010262, 0x0},
+	{0x010362, 0x0},
+	{0x010462, 0x0},
+	{0x010562, 0x0},
+	{0x010662, 0x0},
+	{0x010762, 0x0},
+	{0x010862, 0x0},
+	{0x011062, 0x0},
+	{0x011162, 0x0},
+	{0x011262, 0x0},
+	{0x011362, 0x0},
+	{0x011462, 0x0},
+	{0x011562, 0x0},
+	{0x011662, 0x0},
+	{0x011762, 0x0},
+	{0x011862, 0x0},
+	{0x020077, 0x0},
+	{0x010001, 0x0},
+	{0x011001, 0x0},
+	{0x010040, 0x0},
+	{0x010140, 0x0},
+	{0x010240, 0x0},
+	{0x010340, 0x0},
+	{0x010440, 0x0},
+	{0x010540, 0x0},
+	{0x010640, 0x0},
+	{0x010740, 0x0},
+	{0x010840, 0x0},
+	{0x010030, 0x0},
+	{0x010130, 0x0},
+	{0x010230, 0x0},
+	{0x010330, 0x0},
+	{0x010430, 0x0},
+	{0x010530, 0x0},
+	{0x010630, 0x0},
+	{0x010730, 0x0},
+	{0x010830, 0x0},
+	{0x011040, 0x0},
+	{0x011140, 0x0},
+	{0x011240, 0x0},
+	{0x011340, 0x0},
+	{0x011440, 0x0},
+	{0x011540, 0x0},
+	{0x011640, 0x0},
+	{0x011740, 0x0},
+	{0x011840, 0x0},
+	{0x011030, 0x0},
+	{0x011130, 0x0},
+	{0x011230, 0x0},
+	{0x011330, 0x0},
+	{0x011430, 0x0},
+	{0x011530, 0x0},
+	{0x011630, 0x0},
+	{0x011730, 0x0},
+	{0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x448 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0xf },
+	{ 0x9016b, 0x7c0 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x0 },
+	{ 0x9016e, 0xe8 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x47 },
+	{ 0x90171, 0x630 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x8 },
+	{ 0x90174, 0x618 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0xe0 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x7c8 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x8 },
+	{ 0x9017d, 0x8140 },
+	{ 0x9017e, 0x10c },
+	{ 0x9017f, 0x0 },
+	{ 0x90180, 0x1 },
+	{ 0x90181, 0x8 },
+	{ 0x90182, 0x8 },
+	{ 0x90183, 0x4 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x7c8 },
+	{ 0x90187, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x7d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 400, 100, },
+};
+
diff --git a/roms/u-boot/board/beacon/imx8mn/spl.c b/roms/u-boot/board/beacon/imx8mn/spl.c
new file mode 100644
index 000000000..b5263ccfd
--- /dev/null
+++ b/roms/u-boot/board/beacon/imx8mn/spl.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mn_pins.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/bd71837.h>
+#include <spl.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	debug("Normal Boot\n");
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0)
+		puts("Failed to find clock node. Check device tree\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+#define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
+
+static iomux_v3_cfg_t const pwm_pads[] = {
+	IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	/* Claiming pwm pins prevents LCD flicker during startup*/
+	imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+	init_uart_clk(1);
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/beckhoff/mx53cx9020/Kconfig b/roms/u-boot/board/beckhoff/mx53cx9020/Kconfig
new file mode 100644
index 000000000..dcdafb68e
--- /dev/null
+++ b/roms/u-boot/board/beckhoff/mx53cx9020/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX53CX9020
+
+config SYS_BOARD
+	default "mx53cx9020"
+
+config SYS_VENDOR
+	default "beckhoff"
+
+config SYS_CONFIG_NAME
+	default "mx53cx9020"
+
+endif
diff --git a/roms/u-boot/board/beckhoff/mx53cx9020/MAINTAINERS b/roms/u-boot/board/beckhoff/mx53cx9020/MAINTAINERS
new file mode 100644
index 000000000..f84413e66
--- /dev/null
+++ b/roms/u-boot/board/beckhoff/mx53cx9020/MAINTAINERS
@@ -0,0 +1,6 @@
+MX53 CX9020
+M:	Patrick Bruenn <p.bruenn@beckhoff.com>
+S:	Maintained
+F:	board/beckhoff/mx53cx9020/
+F:	include/configs/mx53cx9020.h
+F:	configs/mx53cx9020_defconfig
diff --git a/roms/u-boot/board/beckhoff/mx53cx9020/Makefile b/roms/u-boot/board/beckhoff/mx53cx9020/Makefile
new file mode 100644
index 000000000..7f15fc574
--- /dev/null
+++ b/roms/u-boot/board/beckhoff/mx53cx9020/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015  Beckhoff Automation GmbH & Co. KG
+# Patrick Bruenn <p.bruenn@beckhoff.com>
+
+obj-y               += mx53cx9020.o
+obj-$(CONFIG_DM_VIDEO) += mx53cx9020_video.o
diff --git a/roms/u-boot/board/beckhoff/mx53cx9020/imximage.cfg b/roms/u-boot/board/beckhoff/mx53cx9020/imximage.cfg
new file mode 100644
index 000000000..159f50e2a
--- /dev/null
+++ b/roms/u-boot/board/beckhoff/mx53cx9020/imximage.cfg
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015  Beckhoff Automation GmbH
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * Based on <u-boot>/board/freescale/mx53loco/imximage.cfg
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8724 0x00000000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0x83190000
+DATA 4 0x63fd900c 0x40425333
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9040 0x05380003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
diff --git a/roms/u-boot/board/beckhoff/mx53cx9020/mx53cx9020.c b/roms/u-boot/board/beckhoff/mx53cx9020/mx53cx9020.c
new file mode 100644
index 000000000..a3657db82
--- /dev/null
+++ b/roms/u-boot/board/beckhoff/mx53cx9020/mx53cx9020.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015  Beckhoff Automation GmbH & Co. KG
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/mx5_video.h>
+#include <ACEX1K.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+
+enum LED_GPIOS {
+	GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
+	GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
+	GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
+	GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
+	GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
+	GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
+	GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
+	GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
+	GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
+	GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
+	GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
+	GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
+	GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
+	GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
+	GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
+};
+
+#define CCAT_BASE_ADDR ((void *)0xf0000000)
+#define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
+#define CCAT_SIZE 1191788
+#define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
+static const char CCAT_SIGNATURE[] = "CCAT";
+
+static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
+static const u32 CCAT_MODE_RUN = 0x0033DC8F;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_board_rev(void)
+{
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+	    (struct fuse_bank0_regs *)bank->fuse_regs;
+
+	int rev = readl(&fuse->gp[6]);
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+/*
+ * Set CCAT mode
+ * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
+ */
+void weim_cs0_settings(u32 mode)
+{
+	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+	writel(0x0, &weim_regs->cs0gcr1);
+	writel(mode, &weim_regs->cs0gcr1);
+	writel(0x00001002, &weim_regs->cs0gcr2);
+
+	writel(0x04000000, &weim_regs->cs0rcr1);
+	writel(0x00000000, &weim_regs->cs0rcr2);
+
+	writel(0x04000000, &weim_regs->cs0wcr1);
+	writel(0x00000000, &weim_regs->cs0wcr2);
+}
+
+static void setup_gpio_eim(void)
+{
+	gpio_request(GPIO_C3_STATUS, "GPIO_C3_STATUS");
+	gpio_request(GPIO_C3_DONE, "GPIO_C3_DONE");
+	gpio_request(GPIO_C3_CONFIG, "GPIO_C3_CONFIG");
+	gpio_direction_input(GPIO_C3_STATUS);
+	gpio_direction_input(GPIO_C3_DONE);
+	gpio_direction_output(GPIO_C3_CONFIG, 1);
+
+	weim_cs0_settings(CCAT_MODE_RUN);
+}
+
+static void setup_gpio_sups(void)
+{
+	gpio_request(GPIO_SUPS_INT, "GPIO_SUPS_INT");
+	gpio_direction_input(GPIO_SUPS_INT);
+
+	static const int BLINK_INTERVALL = 50000;
+	int status = 1;
+	while (gpio_get_value(GPIO_SUPS_INT)) {
+		/* signal "CX SUPS power fail" */
+		gpio_set_value(GPIO_LED_PWR_R,
+			       (++status / BLINK_INTERVALL) % 2);
+	}
+
+	/* signal "CX power up" */
+	gpio_set_value(GPIO_LED_PWR_R, 1);
+}
+
+static void setup_gpio_leds(void)
+{
+	gpio_request(GPIO_LED_SD2_R, "GPIO_LED_SD2_R");
+	gpio_request(GPIO_LED_SD2_B, "GPIO_LED_SD2_B");
+	gpio_request(GPIO_LED_SD2_G, "GPIO_LED_SD2_G");
+	gpio_request(GPIO_LED_SD1_R, "GPIO_LED_SD1_R");
+	gpio_request(GPIO_LED_SD1_B, "GPIO_LED_SD1_B");
+	gpio_request(GPIO_LED_SD1_G, "GPIO_LED_SD1_G");
+	gpio_request(GPIO_LED_PWR_R, "GPIO_LED_PWR_R");
+	gpio_request(GPIO_LED_PWR_B, "GPIO_LED_PWR_B");
+	gpio_request(GPIO_LED_PWR_G, "GPIO_LED_PWR_G");
+
+	gpio_direction_output(GPIO_LED_SD2_R, 0);
+	gpio_direction_output(GPIO_LED_SD2_B, 0);
+	gpio_direction_output(GPIO_LED_SD2_G, 0);
+	gpio_direction_output(GPIO_LED_SD1_R, 0);
+	gpio_direction_output(GPIO_LED_SD1_B, 0);
+	gpio_direction_output(GPIO_LED_SD1_G, 0);
+	gpio_direction_output(GPIO_LED_PWR_R, 0);
+	gpio_direction_output(GPIO_LED_PWR_B, 0);
+	gpio_direction_output(GPIO_LED_PWR_G, 0);
+}
+
+static int power_init(void)
+{
+	/* nothing to do on CX9020 */
+	return 0;
+}
+
+static void clock_1GHz(void)
+{
+	int ret;
+	u32 ref_clk = MXC_HCLK;
+	/*
+	 * After increasing voltage to 1.25V, we can switch
+	 * CPU clock to 1GHz and DDR to 400MHz safely
+	 */
+	ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to 1GHZ failed\n");
+
+	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to 400MHz failed\n");
+}
+
+int board_early_init_f(void)
+{
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	mxc_set_sata_internal_clock();
+
+	setup_gpio_leds();
+	setup_gpio_sups();
+	setup_gpio_eim();
+	setup_iomux_lcd();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Beckhoff CX9020\n");
+
+	return 0;
+}
+
+static int ccat_config_fn(int assert_config, int flush, int cookie)
+{
+	/* prepare FPGA for programming */
+	weim_cs0_settings(CCAT_MODE_CONFIG);
+	gpio_set_value(GPIO_C3_CONFIG, 0);
+	udelay(1);
+	gpio_set_value(GPIO_C3_CONFIG, 1);
+	udelay(230);
+
+	return FPGA_SUCCESS;
+}
+
+static int ccat_status_fn(int cookie)
+{
+	return FPGA_FAIL;
+}
+
+static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
+{
+	const uint8_t *const buffer = buf;
+
+	/* program CCAT */
+	int i;
+	for (i = 0; i < buf_len; ++i)
+		writeb(buffer[i], CCAT_BASE_ADDR);
+
+	writeb(0xff, CCAT_BASE_ADDR);
+	writeb(0xff, CCAT_BASE_ADDR);
+
+	return FPGA_SUCCESS;
+}
+
+static int ccat_done_fn(int cookie)
+{
+	/* programming complete? */
+	return gpio_get_value(GPIO_C3_DONE);
+}
+
+static int ccat_post_fn(int cookie)
+{
+	/* switch to FPGA run mode */
+	weim_cs0_settings(CCAT_MODE_RUN);
+	invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
+
+	if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
+		printf("Verifing CCAT firmware failed, signature not found\n");
+		return FPGA_FAIL;
+	}
+
+	/* signal "CX booting OS" */
+	gpio_set_value(GPIO_LED_PWR_R, 1);
+	gpio_set_value(GPIO_LED_PWR_G, 1);
+	gpio_set_value(GPIO_LED_PWR_B, 0);
+	return FPGA_SUCCESS;
+}
+
+static Altera_CYC2_Passive_Serial_fns ccat_fns = {
+	.config = ccat_config_fn,
+	.status = ccat_status_fn,
+	.done = ccat_done_fn,
+	.write = ccat_write_fn,
+	.abort = ccat_post_fn,
+	.post = ccat_post_fn,
+};
+
+static Altera_desc ccat_fpga = {
+	.family = Altera_CYC2,
+	.iface = passive_serial,
+	.size = CCAT_SIZE,
+	.iface_fns = &ccat_fns,
+	.base = CCAT_BASE_ADDR,
+};
+
+int board_late_init(void)
+{
+	if (!power_init())
+		clock_1GHz();
+
+	fpga_init();
+	fpga_add(fpga_altera, &ccat_fpga);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/beckhoff/mx53cx9020/mx53cx9020_video.c b/roms/u-boot/board/beckhoff/mx53cx9020/mx53cx9020_video.c
new file mode 100644
index 000000000..bf4729025
--- /dev/null
+++ b/roms/u-boot/board/beckhoff/mx53cx9020/mx53cx9020_video.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015  Beckhoff Automation GmbH & Co. KG
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * Based on <u-boot>/board/freescale/mx53loco/mx53loco_video.c
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/video.h>
+
+#define CX9020_DVI_PWD	IMX_GPIO_NR(6, 1)
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= NULL,
+	.enable	= NULL,
+	.mode	= {
+		.name           = "DVI",
+		.refresh = 60,
+		.xres = 640,
+		.yres = 480,
+		.pixclock = 39721,	/* picosecond (25.175 MHz) */
+		.left_margin = 40,
+		.right_margin = 60,
+		.upper_margin = 10,
+		.lower_margin = 10,
+		.hsync_len = 20,
+		.vsync_len = 10,
+		.sync = 0,
+		.vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+void setup_iomux_lcd(void)
+{
+	/* Turn on DVI_PWD */
+	imx_iomux_v3_setup_pad(MX53_PAD_CSI0_DAT15__GPIO6_1);
+	gpio_request(CX9020_DVI_PWD, "CX9020_DVI_PWD");
+	gpio_direction_output(CX9020_DVI_PWD, 1);
+}
diff --git a/roms/u-boot/board/birdland/bav335x/MAINTAINERS b/roms/u-boot/board/birdland/bav335x/MAINTAINERS
new file mode 100644
index 000000000..45dcfcb1e
--- /dev/null
+++ b/roms/u-boot/board/birdland/bav335x/MAINTAINERS
@@ -0,0 +1,13 @@
+BAV335x BOARD
+M:	Gilles Gameiro <gilles@gigadevices.com>
+S:	Maintained
+F:	include/configs/bav335x.h
+F:	board/birdland/bav335x/Kconfig
+F:	board/birdland/bav335x/Makefile
+F:	board/birdland/bav335x/README
+F:	board/birdland/bav335x/board.c
+F:	board/birdland/bav335x/board.h
+F:	board/birdland/bav335x/mux.c
+F:	board/birdland/bav335x/u-boot.lds
+F:	configs/birdland_bav335a_defconfig
+F:	configs/birdland_bav335b_defconfig
diff --git a/roms/u-boot/board/bitmain/antminer_s9/MAINTAINERS b/roms/u-boot/board/bitmain/antminer_s9/MAINTAINERS
new file mode 100644
index 000000000..302dd4807
--- /dev/null
+++ b/roms/u-boot/board/bitmain/antminer_s9/MAINTAINERS
@@ -0,0 +1,6 @@
+Bitmain Antminer S9
+M:	Michal Simek <monstr@monstr.eu>
+S:	Maintained
+F:	board/bitmain/antminer_s9
+F:	include/configs/bitmain_antminer_s9.h
+F:	configs/bitmain_antminer_s9_defconfig
diff --git a/roms/u-boot/board/bitmain/antminer_s9/Makefile b/roms/u-boot/board/bitmain/antminer_s9/Makefile
new file mode 100644
index 000000000..1af01d6d8
--- /dev/null
+++ b/roms/u-boot/board/bitmain/antminer_s9/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y	:= board.o
+obj-y	+= ../../xilinx/common/board.o
+
+# Remove quotes
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
diff --git a/roms/u-boot/board/bitmain/antminer_s9/bitmain-antminer-s9/ps7_init_gpl.c b/roms/u-boot/board/bitmain/antminer_s9/bitmain-antminer-s9/ps7_init_gpl.c
new file mode 100644
index 000000000..aee202996
--- /dev/null
+++ b/roms/u-boot/board/bitmain/antminer_s9/bitmain-antminer-s9/ps7_init_gpl.c
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2018 Michal Simek
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d),
+	EMIT_MASKWRITE(0xf8000110, 0x003ffff0, 0x000fa220),
+	EMIT_MASKWRITE(0xf8000100, 0x0007f000, 0x00028000),
+	EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000010),
+	EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000001),
+	EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000000),
+	EMIT_MASKPOLL(0xf800010c, 0x00000001),
+	EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000000),
+	EMIT_MASKWRITE(0xf8000120, 0x1f003f30, 0x1f000200),
+	EMIT_MASKWRITE(0xf8000114, 0x003ffff0, 0x0012c220),
+	EMIT_MASKWRITE(0xf8000104, 0x0007f000, 0x00020000),
+	EMIT_MASKWRITE(0xf8000104, 0x00000010, 0x00000010),
+	EMIT_MASKWRITE(0xf8000104, 0x00000001, 0x000000),
+	EMIT_MASKWRITE(0xf8000104, 0x00000001, 0x00000000),
+	EMIT_MASKPOLL(0xf800010c, 0x00000002),
+	EMIT_MASKWRITE(0xf8000104, 0x00000010, 0x00000000),
+	EMIT_MASKWRITE(0xf8000124, 0xfff00003, 0x0c200003),
+	EMIT_MASKWRITE(0xf8000118, 0x003ffff0, 0x001452c0),
+	EMIT_MASKWRITE(0xf8000108, 0x0007f000, 0x0001e000),
+	EMIT_MASKWRITE(0xf8000108, 0x00000010, 0x00000010),
+	EMIT_MASKWRITE(0xf8000108, 0x00000001, 0x00000001),
+	EMIT_MASKWRITE(0xf8000108, 0x00000001, 0x00000000),
+	EMIT_MASKPOLL(0xf800010c, 0x00000004),
+	EMIT_MASKWRITE(0xf8000108, 0x00000010, 0x00000000),
+	EMIT_MASKWRITE(0xf8000004, 0x0000ffff, 0x0000767b),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d),
+	EMIT_MASKWRITE(0xf8000128, 0x03f03f01, 0x00302301),
+	EMIT_MASKWRITE(0xf8000138, 0x00000011, 0x00000001),
+	EMIT_MASKWRITE(0xf8000140, 0x03f03f71, 0x00100801),
+	EMIT_MASKWRITE(0xf8000148, 0x00003f31, 0x00000a01),
+	EMIT_MASKWRITE(0xf8000150, 0x00003f33, 0x00002801),
+	EMIT_MASKWRITE(0xf8000154, 0x00003f33, 0x00001402),
+	EMIT_MASKWRITE(0xf8000168, 0x00003f31, 0x00000501),
+	EMIT_MASKWRITE(0xf8000170, 0x03f03f30, 0x00101400),
+	EMIT_MASKWRITE(0xf8000180, 0x03f03f30, 0x00100a00),
+	EMIT_MASKWRITE(0xf8000190, 0x03f03f30, 0x00101e00),
+	EMIT_MASKWRITE(0xf80001a0, 0x03f03f30, 0x00101400),
+	EMIT_MASKWRITE(0xf80001c4, 0x00000001, 0x00000001),
+	EMIT_MASKWRITE(0xf800012c, 0x01ffcccd, 0x016c044d),
+	EMIT_MASKWRITE(0xf8000004, 0x0000ffff, 0x0000767b),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xf8006000, 0x0001ffff, 0x00000080),
+	EMIT_MASKWRITE(0xf8006004, 0x0007ffff, 0x00001081),
+	EMIT_MASKWRITE(0xf8006008, 0x03ffffff, 0x03c0780f),
+	EMIT_MASKWRITE(0xf800600c, 0x03ffffff, 0x02001001),
+	EMIT_MASKWRITE(0xf8006010, 0x03ffffff, 0x00014001),
+	EMIT_MASKWRITE(0xf8006014, 0x001fffff, 0x0004281b),
+	EMIT_MASKWRITE(0xf8006018, 0xf7ffffff, 0x44e458d1),
+	EMIT_MASKWRITE(0xf800601c, 0xffffffff, 0xb2023584),
+	EMIT_MASKWRITE(0xf8006020, 0x7fdffffc, 0x2b08b2d0),
+	EMIT_MASKWRITE(0xf8006024, 0x0fffffc3, 0x00000000),
+	EMIT_MASKWRITE(0xf8006028, 0x00003fff, 0x00002007),
+	EMIT_MASKWRITE(0xf800602c, 0xffffffff, 0x00000000),
+	EMIT_MASKWRITE(0xf8006030, 0xffffffff, 0x00040970),
+	EMIT_MASKWRITE(0xf8006034, 0x13ff3fff, 0x000116d4),
+	EMIT_MASKWRITE(0xf8006038, 0x00000003, 0x00000000),
+	EMIT_MASKWRITE(0xf800603c, 0x000fffff, 0x00000777),
+	EMIT_MASKWRITE(0xf8006040, 0xffffffff, 0xfff00000),
+	EMIT_MASKWRITE(0xf8006044, 0x0fffffff, 0x0f666666),
+	EMIT_MASKWRITE(0xf8006048, 0x0003f03f, 0x0003c008),
+	EMIT_MASKWRITE(0xf8006050, 0xff0f8fff, 0x77010800),
+	EMIT_MASKWRITE(0xf8006058, 0x00010000, 0x00000000),
+	EMIT_MASKWRITE(0xf800605c, 0x0000ffff, 0x00005003),
+	EMIT_MASKWRITE(0xf8006060, 0x000017ff, 0x0000003e),
+	EMIT_MASKWRITE(0xf8006064, 0x00021fe0, 0x00020000),
+	EMIT_MASKWRITE(0xf8006068, 0x03ffffff, 0x00284545),
+	EMIT_MASKWRITE(0xf800606c, 0x0000ffff, 0x00001610),
+	EMIT_MASKWRITE(0xf8006078, 0x03ffffff, 0x00466111),
+	EMIT_MASKWRITE(0xf800607c, 0x000fffff, 0x00032222),
+	EMIT_MASKWRITE(0xf80060a4, 0xffffffff, 0x10200802),
+	EMIT_MASKWRITE(0xf80060a8, 0x0fffffff, 0x0690cb73),
+	EMIT_MASKWRITE(0xf80060ac, 0x000001ff, 0x000001fe),
+	EMIT_MASKWRITE(0xf80060b0, 0x1fffffff, 0x1cffffff),
+	EMIT_MASKWRITE(0xf80060b4, 0x00000200, 0x00000200),
+	EMIT_MASKWRITE(0xf80060b8, 0x01ffffff, 0x0020006a),
+	EMIT_MASKWRITE(0xf80060c4, 0x00000003, 0x00000003),
+	EMIT_MASKWRITE(0xf80060c4, 0x00000003, 0x00000000),
+	EMIT_MASKWRITE(0xf80060c8, 0x000000ff, 0x00000000),
+	EMIT_MASKWRITE(0xf80060dc, 0x00000001, 0x00000000),
+	EMIT_MASKWRITE(0xf80060f0, 0x0000ffff, 0x00000000),
+	EMIT_MASKWRITE(0xf80060f4, 0x0000000f, 0x00000008),
+	EMIT_MASKWRITE(0xf8006114, 0x000000ff, 0x00000000),
+	EMIT_MASKWRITE(0xf8006118, 0x7fffffcf, 0x40000001),
+	EMIT_MASKWRITE(0xf800611c, 0x7fffffcf, 0x40000001),
+	EMIT_MASKWRITE(0xf8006120, 0x7fffffcf, 0x40000001),
+	EMIT_MASKWRITE(0xf8006124, 0x7fffffcf, 0x40000001),
+	EMIT_MASKWRITE(0xf800612c, 0x000fffff, 0x0002c000),
+	EMIT_MASKWRITE(0xf8006130, 0x000fffff, 0x0002c400),
+	EMIT_MASKWRITE(0xf8006134, 0x000fffff, 0x0002f003),
+	EMIT_MASKWRITE(0xf8006138, 0x000fffff, 0x0002ec03),
+	EMIT_MASKWRITE(0xf8006140, 0x000fffff, 0x00000035),
+	EMIT_MASKWRITE(0xf8006144, 0x000fffff, 0x00000035),
+	EMIT_MASKWRITE(0xf8006148, 0x000fffff, 0x00000035),
+	EMIT_MASKWRITE(0xf800614c, 0x000fffff, 0x00000035),
+	EMIT_MASKWRITE(0xf8006154, 0x000fffff, 0x00000077),
+	EMIT_MASKWRITE(0xf8006158, 0x000fffff, 0x00000077),
+	EMIT_MASKWRITE(0xf800615c, 0x000fffff, 0x00000083),
+	EMIT_MASKWRITE(0xf8006160, 0x000fffff, 0x00000083),
+	EMIT_MASKWRITE(0xf8006168, 0x001fffff, 0x00000105),
+	EMIT_MASKWRITE(0xf800616c, 0x001fffff, 0x00000106),
+	EMIT_MASKWRITE(0xf8006170, 0x001fffff, 0x00000111),
+	EMIT_MASKWRITE(0xf8006174, 0x001fffff, 0x00000110),
+	EMIT_MASKWRITE(0xf800617c, 0x000fffff, 0x000000b7),
+	EMIT_MASKWRITE(0xf8006180, 0x000fffff, 0x000000b7),
+	EMIT_MASKWRITE(0xf8006184, 0x000fffff, 0x000000c3),
+	EMIT_MASKWRITE(0xf8006188, 0x000fffff, 0x000000c3),
+	EMIT_MASKWRITE(0xf8006190, 0x6ffffefe, 0x00040080),
+	EMIT_MASKWRITE(0xf8006194, 0x000fffff, 0x0001fd01),
+	EMIT_MASKWRITE(0xf8006204, 0xffffffff, 0x00000000),
+	EMIT_MASKWRITE(0xf8006208, 0x000703ff, 0x000003ff),
+	EMIT_MASKWRITE(0xf800620c, 0x000703ff, 0x000003ff),
+	EMIT_MASKWRITE(0xf8006210, 0x000703ff, 0x000003ff),
+	EMIT_MASKWRITE(0xf8006214, 0x000703ff, 0x000003ff),
+	EMIT_MASKWRITE(0xf8006218, 0x000f03ff, 0x000003ff),
+	EMIT_MASKWRITE(0xf800621c, 0x000f03ff, 0x000003ff),
+	EMIT_MASKWRITE(0xf8006220, 0x000f03ff, 0x000003ff),
+	EMIT_MASKWRITE(0xf8006224, 0x000f03ff, 0x000003ff),
+	EMIT_MASKWRITE(0xf80062a8, 0x00000ff5, 0x00000000),
+	EMIT_MASKWRITE(0xf80062ac, 0xffffffff, 0x00000000),
+	EMIT_MASKWRITE(0xf80062b0, 0x003fffff, 0x00005125),
+	EMIT_MASKWRITE(0xf80062b4, 0x0003ffff, 0x000012a8),
+	EMIT_MASKPOLL(0xf8000b74, 0x00002000),
+	EMIT_MASKWRITE(0xf8006000, 0x0001ffff, 0x00000081),
+	EMIT_MASKPOLL(0xf8006054, 0x00000007),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d),
+	EMIT_MASKWRITE(0xf8000b40, 0x00000fff, 0x00000600),
+	EMIT_MASKWRITE(0xf8000b44, 0x00000fff, 0x00000600),
+	EMIT_MASKWRITE(0xf8000b48, 0x00000fff, 0x00000672),
+	EMIT_MASKWRITE(0xf8000b4c, 0x00000fff, 0x00000672),
+	EMIT_MASKWRITE(0xf8000b50, 0x00000fff, 0x00000674),
+	EMIT_MASKWRITE(0xf8000b54, 0x00000fff, 0x00000674),
+	EMIT_MASKWRITE(0xf8000b58, 0x00000fff, 0x00000600),
+	EMIT_MASKWRITE(0xf8000b5c, 0xffffffff, 0x0018c068),
+	EMIT_MASKWRITE(0xf8000b60, 0xffffffff, 0x00f98068),
+	EMIT_MASKWRITE(0xf8000b64, 0xffffffff, 0x00f98068),
+	EMIT_MASKWRITE(0xf8000b68, 0xffffffff, 0x00f98068),
+	EMIT_MASKWRITE(0xf8000b6c, 0x00007fff, 0x00000205),
+	EMIT_MASKWRITE(0xf8000b70, 0x00000001, 0x00000001),
+	EMIT_MASKWRITE(0xf8000b70, 0x00000021, 0x00000020),
+	EMIT_MASKWRITE(0xf8000b70, 0x07feffff, 0x00000823),
+	EMIT_MASKWRITE(0xf8000700, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf8000704, 0x00003fff, 0x00000600),
+	EMIT_MASKWRITE(0xf8000708, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf800070c, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf8000710, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf8000714, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf8000718, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf800071c, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf8000720, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf8000724, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf8000728, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf800072c, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf8000730, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf8000734, 0x00003fff, 0x00000610),
+	EMIT_MASKWRITE(0xf8000738, 0x00003fff, 0x00000611),
+	EMIT_MASKWRITE(0xf800073c, 0x00003fff, 0x00000600),
+	EMIT_MASKWRITE(0xf8000740, 0x00003fff, 0x00000202),
+	EMIT_MASKWRITE(0xf8000744, 0x00003fff, 0x00000202),
+	EMIT_MASKWRITE(0xf8000748, 0x00003fff, 0x00000202),
+	EMIT_MASKWRITE(0xf800074c, 0x00003fff, 0x00000202),
+	EMIT_MASKWRITE(0xf8000750, 0x00003fff, 0x00000202),
+	EMIT_MASKWRITE(0xf8000754, 0x00003fff, 0x00000202),
+	EMIT_MASKWRITE(0xf8000758, 0x00003fff, 0x00000203),
+	EMIT_MASKWRITE(0xf800075c, 0x00003fff, 0x00000203),
+	EMIT_MASKWRITE(0xf8000760, 0x00003fff, 0x00000203),
+	EMIT_MASKWRITE(0xf8000764, 0x00003fff, 0x00000203),
+	EMIT_MASKWRITE(0xf8000768, 0x00003fff, 0x00000203),
+	EMIT_MASKWRITE(0xf800076c, 0x00003fff, 0x00000203),
+	EMIT_MASKWRITE(0xf8000770, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf8000774, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf8000778, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf800077c, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf8000780, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf8000784, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf8000788, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf800078c, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf8000790, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf8000794, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf8000798, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf800079c, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf80007a0, 0x00003fff, 0x00000280),
+	EMIT_MASKWRITE(0xf80007a4, 0x00003fff, 0x00000280),
+	EMIT_MASKWRITE(0xf80007a8, 0x00003fff, 0x00000280),
+	EMIT_MASKWRITE(0xf80007ac, 0x00003fff, 0x00000280),
+	EMIT_MASKWRITE(0xf80007b0, 0x00003fff, 0x00000280),
+	EMIT_MASKWRITE(0xf80007b4, 0x00003fff, 0x00000280),
+	EMIT_MASKWRITE(0xf80007b8, 0x00003f01, 0x00000201),
+	EMIT_MASKWRITE(0xf80007bc, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf80007c0, 0x00003fff, 0x000002e0),
+	EMIT_MASKWRITE(0xf80007c4, 0x00003fff, 0x000002e1),
+	EMIT_MASKWRITE(0xf80007c8, 0x00003f01, 0x00000201),
+	EMIT_MASKWRITE(0xf80007cc, 0x00003fff, 0x00000200),
+	EMIT_MASKWRITE(0xf80007d0, 0x00003fff, 0x00000280),
+	EMIT_MASKWRITE(0xf80007d4, 0x00003fff, 0x00000280),
+	EMIT_MASKWRITE(0xf8000830, 0x003f003f, 0x002e0032),
+	EMIT_MASKWRITE(0xf8000004, 0x0000ffff, 0x0000767b),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d),
+	EMIT_MASKWRITE(0xf8000b48, 0x00000180, 0x00000180),
+	EMIT_MASKWRITE(0xf8000b4c, 0x00000180, 0x00000180),
+	EMIT_MASKWRITE(0xf8000b50, 0x00000180, 0x00000180),
+	EMIT_MASKWRITE(0xf8000b54, 0x00000180, 0x00000180),
+	EMIT_MASKWRITE(0xf8000004, 0x0000ffff, 0x0000767b),
+	EMIT_MASKWRITE(0xe0001034, 0x000000ff, 0x00000006),
+	EMIT_MASKWRITE(0xe0001018, 0x0000ffff, 0x0000003e),
+	EMIT_MASKWRITE(0xe0001000, 0x000001ff, 0x00000017),
+	EMIT_MASKWRITE(0xe0001004, 0x000003ff, 0x00000020),
+	EMIT_MASKWRITE(0xe000d000, 0x00080000, 0x00080000),
+	EMIT_MASKWRITE(0xf8007000, 0x20000000, 0x00000000),
+	EMIT_MASKWRITE(0xe000e014, 0x00ffffff, 0x00449144),
+	EMIT_MASKWRITE(0xe000e018, 0x00000003, 0x00000000),
+	EMIT_MASKWRITE(0xe000e010, 0x03e00000, 0x02400000),
+	EMIT_MASKDELAY(0xf8f00200, 0x00000001),
+	EMIT_MASKDELAY(0xf8f00200, 0x00000001),
+	EMIT_MASKDELAY(0xf8f00200, 0x00000001),
+	EMIT_MASKDELAY(0xf8f00200, 0x00000001),
+	EMIT_MASKDELAY(0xf8f00200, 0x00000001),
+	EMIT_MASKDELAY(0xf8f00200, 0x00000001),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d),
+	EMIT_MASKWRITE(0xf8000900, 0x0000000f, 0x0000000f),
+	EMIT_MASKWRITE(0xf8000240, 0xffffffff, 0x00000000),
+	EMIT_MASKWRITE(0xf8008000, 0x00000001, 0x00000001),
+	EMIT_MASKWRITE(0xf8008014, 0x00000001, 0x00000001),
+	EMIT_MASKWRITE(0xf8000004, 0x0000ffff, 0x0000767b),
+	EMIT_EXIT(),
+};
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
diff --git a/roms/u-boot/board/bitmain/antminer_s9/board.c b/roms/u-boot/board/bitmain/antminer_s9/board.c
new file mode 100644
index 000000000..bb7cef318
--- /dev/null
+++ b/roms/u-boot/board/bitmain/antminer_s9/board.c
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "../../xilinx/zynq/board.c"
diff --git a/roms/u-boot/board/bluewater/gurnard/Kconfig b/roms/u-boot/board/bluewater/gurnard/Kconfig
new file mode 100644
index 000000000..e2cd9f00d
--- /dev/null
+++ b/roms/u-boot/board/bluewater/gurnard/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GURNARD
+
+config SYS_BOARD
+	default "gurnard"
+
+config SYS_VENDOR
+	default "bluewater"
+
+config SYS_CONFIG_NAME
+	default "snapper9g45"
+
+endif
diff --git a/roms/u-boot/board/bluewater/gurnard/MAINTAINERS b/roms/u-boot/board/bluewater/gurnard/MAINTAINERS
new file mode 100644
index 000000000..5e546d43f
--- /dev/null
+++ b/roms/u-boot/board/bluewater/gurnard/MAINTAINERS
@@ -0,0 +1,6 @@
+GURNARD BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/bluewater/gurnard/
+F:	include/configs/snapper9g45.h
+F:	configs/gurnard_defconfig
diff --git a/roms/u-boot/board/bluewater/gurnard/Makefile b/roms/u-boot/board/bluewater/gurnard/Makefile
new file mode 100644
index 000000000..8218e2cd5
--- /dev/null
+++ b/roms/u-boot/board/bluewater/gurnard/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011 Bluewater Systems
+# Ryan Mallon <ryan@bluewatersys.com>
+
+obj-y	+= gurnard.o
diff --git a/roms/u-boot/board/bluewater/gurnard/gurnard.c b/roms/u-boot/board/bluewater/gurnard/gurnard.c
new file mode 100644
index 000000000..e217b95b4
--- /dev/null
+++ b/roms/u-boot/board/bluewater/gurnard/gurnard.c
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Bluewater Systems Snapper 9260/9G20 modules
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ *   Author: Andre Renaud <andre@bluewatersys.com>
+ *   Author: Ryan Mallon <ryan@bluewatersys.com>
+ */
+
+#include <common.h>
+#include <atmel_lcd.h>
+#include <atmel_lcdc.h>
+#include <atmel_mci.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <lcd.h>
+#include <net.h>
+#ifndef CONFIG_DM_ETH
+#include <netdev.h>
+#endif
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_emac.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_rtc.h>
+#include <asm/arch/at91_sck.h>
+#include <asm/arch/atmel_serial.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <dm/uclass-internal.h>
+#include <linux/delay.h>
+
+#ifdef CONFIG_GURNARD_SPLASH
+#include "splash_logo.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO Expander pins */
+#define IO_EXP_ETH_RESET	(0 << 1)
+#define IO_EXP_ETH_POWER	(1 << 1)
+
+#ifdef CONFIG_MACB
+static void gurnard_macb_hw_init(void)
+{
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+
+	/*
+	 * Enable pull-up on:
+	 *	RXDV (PA12) => MODE0 - PHY also has pull-up
+	 *	ERX0 (PA13) => MODE1 - PHY also has pull-up
+	 *	ERX1 (PA15) => MODE2 - PHY also has pull-up
+	 */
+	writel(pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA12) |
+	       pin_to_mask(AT91_PIN_PA13),
+	       &pioa->puer);
+
+	at91_phy_reset();
+
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_CMD_NAND
+static int gurnard_nand_hw_init(void)
+{
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	ulong flags;
+	int ret;
+
+	/* Enable CS3 as NAND/SmartMedia */
+	setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+	       &smc->cs[3].cycle);
+#ifdef CONFIG_SYS_NAND_DBW_16
+	flags = AT91_SMC_MODE_DBW_16;
+#else
+	flags = AT91_SMC_MODE_DBW_8;
+#endif
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       flags |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
+	if (ret)
+		return ret;
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+	/* Enable NandFlash */
+	ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
+	if (ret)
+		return ret;
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_GURNARD_SPLASH
+static void lcd_splash(int width, int height)
+{
+	u16 colour;
+	int x, y;
+	u16 *base_addr = (u16 *)gd->video_bottom;
+
+	memset(base_addr, 0xff, width * height * 2);
+	/*
+	 * Blit the logo to the center of the screen
+	 */
+	for (y = 0; y < BMP_LOGO_HEIGHT; y++) {
+		for (x = 0; x < BMP_LOGO_WIDTH; x++) {
+			int posx, posy;
+			colour = bmp_logo_palette[bmp_logo_bitmap[
+			    y * BMP_LOGO_WIDTH + x]];
+			posx = x + (width - BMP_LOGO_WIDTH) / 2;
+			posy = y;
+			base_addr[posy * width + posx] = colour;
+		}
+	}
+}
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+static void at91sam9g45_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
+	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
+
+	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
+	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
+	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
+	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
+	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
+	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
+	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
+
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+#endif
+
+#ifdef CONFIG_GURNARD_FPGA
+/**
+ * Initialise the memory bus settings so that we can talk to the
+ * memory mapped FPGA
+ */
+static int fpga_hw_init(void)
+{
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	int i;
+
+	setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC);
+
+	at91_set_a_periph(2, 4, 0); /* EBIA21 */
+	at91_set_a_periph(2, 5, 0); /* EBIA22 */
+	at91_set_a_periph(2, 6, 0); /* EBIA23 */
+	at91_set_a_periph(2, 7, 0); /* EBIA24 */
+	at91_set_a_periph(2, 12, 0); /* EBIA25 */
+	for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */
+		at91_set_a_periph(2, i, 0);
+
+	/* configure SMC cs0 for FPGA access timing */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) |
+	       AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2),
+	       &smc->cs[0].setup);
+	writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) |
+	       AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4),
+	       &smc->cs[0].pulse);
+	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
+	       &smc->cs[0].cycle);
+	writel(AT91_SMC_MODE_BAT |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_32 |
+	       AT91_SMC_MODE_TDF |
+	       AT91_SMC_MODE_TDF_CYCLE(2),
+	       &smc->cs[0].mode);
+
+	/* Do a write to within EBI_CS1 to enable the SDCK */
+	writel(0, ATMEL_BASE_CS1);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+
+#define USB0_ENABLE_PIN		AT91_PIN_PB22
+#define USB1_ENABLE_PIN		AT91_PIN_PB23
+
+void gurnard_usb_init(void)
+{
+	at91_set_gpio_output(USB0_ENABLE_PIN, 1);
+	at91_set_gpio_value(USB0_ENABLE_PIN, 0);
+	at91_set_gpio_output(USB1_ENABLE_PIN, 1);
+	at91_set_gpio_value(USB1_ENABLE_PIN, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int cpu_mmc_init(struct bd_info *bis)
+{
+	return atmel_mci_init((void *)ATMEL_BASE_MCI0);
+}
+#endif
+
+static void gurnard_enable_console(int enable)
+{
+	at91_set_gpio_output(AT91_PIN_PB14, 1);
+	at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1);
+}
+
+void at91sam9g45_slowclock_init(void)
+{
+	/*
+	 * On AT91SAM9G45 revC CPUs, the slow clock can be based on an
+	 * internal impreciseRC oscillator or an external 32kHz oscillator.
+	 * Switch to the latter.
+	 */
+	unsigned i, tmp;
+	ulong *reg = (ulong *)ATMEL_BASE_SCKCR;
+
+	tmp = readl(reg);
+	if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) {
+		timer_init();
+		tmp |= AT91SAM9G45_SCKCR_OSC32EN;
+		writel(tmp, reg);
+		for (i = 0; i < 1200; i++)
+			udelay(1000);
+		tmp |= AT91SAM9G45_SCKCR_OSCSEL_32;
+		writel(tmp, reg);
+		udelay(200);
+		tmp &= ~AT91SAM9G45_SCKCR_RCEN;
+		writel(tmp, reg);
+	}
+}
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+	gurnard_enable_console(1);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	const char *rev_str;
+#ifdef CONFIG_CMD_NAND
+	int ret;
+#endif
+
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+
+	at91sam9g45_slowclock_init();
+
+	/*
+	 * Clear the RTC IDR to disable all IRQs. Avoid issues when Linux
+	 * boots with spurious IRQs.
+	 */
+	writel(0xffffffff, AT91_RTC_IDR);
+
+	/* Make sure that the reset signal is attached properly */
+	setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN);
+
+	gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	ret = gurnard_nand_hw_init();
+	if (ret)
+		return ret;
+#endif
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 4);
+#endif
+
+#ifdef CONFIG_MACB
+	gurnard_macb_hw_init();
+#endif
+
+#ifdef CONFIG_GURNARD_FPGA
+	fpga_hw_init();
+#endif
+
+#ifdef CONFIG_CMD_USB
+	gurnard_usb_init();
+#endif
+
+#ifdef CONFIG_CMD_MMC
+	at91_set_A_periph(AT91_PIN_PA12, 0);
+	at91_set_gpio_output(AT91_PIN_PA8, 1);
+	at91_set_gpio_value(AT91_PIN_PA8, 0);
+	at91_mci_hw_init();
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+	at91sam9g45_lcd_hw_init();
+	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
+
+	/* Select the second timing index for board rev 2 */
+	rev_str = env_get("board_rev");
+	if (rev_str && !strncmp(rev_str, "2", 1)) {
+		struct udevice *dev;
+
+		uclass_find_first_device(UCLASS_VIDEO, &dev);
+		if (dev) {
+			struct atmel_lcd_plat *plat = dev_get_plat(dev);
+
+			plat->timing_index = 1;
+		}
+	}
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	u_int8_t env_enetaddr[8];
+	char *env_str;
+	char *end;
+	int i;
+
+	/*
+	 * Set MAC address so we do not need to init Ethernet before Linux
+	 * boot
+	 */
+	env_str = env_get("ethaddr");
+	if (env_str) {
+		struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC;
+		/* Parse MAC address */
+		for (i = 0; i < 6; i++) {
+			env_enetaddr[i] = env_str ?
+				simple_strtoul(env_str, &end, 16) : 0;
+			if (env_str)
+				env_str = (*end) ? end+1 : end;
+		}
+
+		/* Set hardware address */
+		writel(env_enetaddr[0] | env_enetaddr[1] << 8 |
+		       env_enetaddr[2] << 16 | env_enetaddr[3] << 24,
+		       &emac->sa2l);
+		writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h);
+
+		printf("MAC:   %s\n", env_get("ethaddr"));
+	} else {
+		/* Not set in environment */
+		printf("MAC:   not set\n");
+	}
+#ifdef CONFIG_GURNARD_SPLASH
+	lcd_splash(480, 272);
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_DM_ETH
+int board_eth_init(struct bd_info *bis)
+{
+	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0);
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+void reset_phy(void)
+{
+}
+
+static struct atmel_serial_plat at91sam9260_serial_plat = {
+	.base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DRVINFO(at91sam9260_serial) = {
+	.name	= "serial_atmel",
+	.plat = &at91sam9260_serial_plat,
+};
diff --git a/roms/u-boot/board/bluewater/gurnard/splash_logo.h b/roms/u-boot/board/bluewater/gurnard/splash_logo.h
new file mode 100644
index 000000000..fb87dea86
--- /dev/null
+++ b/roms/u-boot/board/bluewater/gurnard/splash_logo.h
@@ -0,0 +1,2619 @@
+/* generated by ppm_logo (c) 2004 by Andre Renaud from logo_gurnard_small.ppm*/
+#ifndef __BMP_LOGO_H__
+#define __BMP_LOGO_H__
+#define BMP_LOGO_WIDTH 187
+#define BMP_LOGO_HEIGHT 139
+#define BMP_LOGO_COLORS 255
+#define BMP_LOGO_OFFSET 50
+
+unsigned short bmp_logo_palette[] = {
+	0xb61a, 0x9d78, 0xdefc, 0xffff, 0x7455, 0x32b1, 0xb5fa, 0xe75e,
+	0xffdf, 0xc65b, 0x9538, 0xd6dc, 0xce9b, 0xf7df, 0xadb9, 0x84d7,
+	0xffff, 0xffff, 0xffdf, 0x5bb4, 0x4b11, 0x3ad1, 0xf7bf, 0xf7bf,
+	0xffff, 0xffff, 0xf79e, 0xef9e, 0x6c35, 0xef7e, 0xe75d, 0xdf1d,
+	0xdf1c, 0xf7df, 0xde9a, 0xed96, 0xe6fb, 0xdb4d, 0xc945, 0xe410,
+	0xffdf, 0xc965, 0xc986, 0xd2aa, 0xe451, 0xed14, 0xef5d, 0xffbe,
+	0xffff, 0xef3c, };
+
+unsigned char bmp_logo_bitmap[] = {
+	0x0000, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001,
+	0x0001, 0x0001, 0x0001, 0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005,
+	0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+	0x0006, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+	0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0006, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
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+	0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+	0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+	0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+	0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+	0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+	0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+	0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+	0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+	0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+	0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+	0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d,
+	0x002d, 0x0022, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x001f,
+	0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
+	0x000e, 0x000e, 0x0009, };
+#endif
diff --git a/roms/u-boot/board/bluewater/snapper9260/Kconfig b/roms/u-boot/board/bluewater/snapper9260/Kconfig
new file mode 100644
index 000000000..b8e9cbc58
--- /dev/null
+++ b/roms/u-boot/board/bluewater/snapper9260/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SNAPPER9260
+
+config SYS_BOARD
+	default "snapper9260"
+
+config SYS_VENDOR
+	default "bluewater"
+
+config SYS_CONFIG_NAME
+	default "snapper9260"
+
+endif
diff --git a/roms/u-boot/board/bluewater/snapper9260/MAINTAINERS b/roms/u-boot/board/bluewater/snapper9260/MAINTAINERS
new file mode 100644
index 000000000..1f8f4d698
--- /dev/null
+++ b/roms/u-boot/board/bluewater/snapper9260/MAINTAINERS
@@ -0,0 +1,7 @@
+SNAPPER9260 BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/bluewater/snapper9260/
+F:	include/configs/snapper9260.h
+F:	configs/snapper9260_defconfig
+F:	configs/snapper9g20_defconfig
diff --git a/roms/u-boot/board/bluewater/snapper9260/Makefile b/roms/u-boot/board/bluewater/snapper9260/Makefile
new file mode 100644
index 000000000..842abf4ee
--- /dev/null
+++ b/roms/u-boot/board/bluewater/snapper9260/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011 Bluewater Systems
+# Ryan Mallon <ryan@bluewatersys.com>
+
+obj-y	+= snapper9260.o
diff --git a/roms/u-boot/board/bluewater/snapper9260/snapper9260.c b/roms/u-boot/board/bluewater/snapper9260/snapper9260.c
new file mode 100644
index 000000000..df53a651c
--- /dev/null
+++ b/roms/u-boot/board/bluewater/snapper9260/snapper9260.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Bluewater Systems Snapper 9260/9G20 modules
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ *   Author: Andre Renaud <andre@bluewatersys.com>
+ *   Author: Ryan Mallon <ryan@bluewatersys.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/atmel_serial.h>
+#include <net.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <pca953x.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO Expander pins */
+#define IO_EXP_ETH_RESET	(0 << 1)
+#define IO_EXP_ETH_POWER	(1 << 1)
+
+static void macb_hw_init(void)
+{
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+	at91_periph_clk_enable(ATMEL_ID_EMAC0);
+
+	/* Disable pull-ups to prevent PHY going into test mode */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA18),
+	       &pioa->pudr);
+
+	/* Power down ethernet */
+	pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
+	pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
+
+	/* Hold ethernet in reset */
+	pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
+	pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
+
+	/* Enable ethernet power */
+	pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
+
+	at91_phy_reset();
+
+	/* Bring the ethernet out of reset */
+	pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
+
+	/* The phy internal reset take 21ms */
+	udelay(21 * 1000);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA18),
+	       &pioa->puer);
+
+	at91_macb_hw_init();
+}
+
+static void nand_hw_init(void)
+{
+	struct at91_smc *smc       = (struct at91_smc    *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 as NAND/SmartMedia */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+	/* Enable NandFlash */
+	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+int board_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+	/* The mach-type is the same for both Snapper 9260 and 9G20 */
+	gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Initialise peripherals */
+	at91_seriald_hw_init();
+	i2c_set_bus_num(0);
+	nand_hw_init();
+	macb_hw_init();
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+void reset_phy(void)
+{
+}
+
+static struct atmel_serial_plat at91sam9260_serial_plat = {
+	.base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DRVINFO(at91sam9260_serial) = {
+	.name	= "serial_atmel",
+	.plat = &at91sam9260_serial_plat,
+};
diff --git a/roms/u-boot/board/bosch/guardian/Kconfig b/roms/u-boot/board/bosch/guardian/Kconfig
new file mode 100644
index 000000000..1417da61f
--- /dev/null
+++ b/roms/u-boot/board/bosch/guardian/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AM335X_GUARDIAN
+
+config SYS_BOARD
+	default "guardian"
+
+config SYS_VENDOR
+	default "bosch"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "am335x_guardian"
+
+endif
diff --git a/roms/u-boot/board/bosch/guardian/MAINTAINERS b/roms/u-boot/board/bosch/guardian/MAINTAINERS
new file mode 100644
index 000000000..fd216a96c
--- /dev/null
+++ b/roms/u-boot/board/bosch/guardian/MAINTAINERS
@@ -0,0 +1,8 @@
+Guardian BOARD
+M:	Sjoerd Simons <sjoerd.simons@collabora.co.uk>
+M:	Govindaraji Sivanantham <Govindaraji.Sivanantham@in.bosch.com>
+M:	Hiremath Gireesh <Gireesh.Hiremath@in.bosch.com>
+S:	Maintained
+F:	board/bosch/guardian/
+F:	include/configs/am335x_guardian.h
+F:	configs/am335x_guardian_defconfig
diff --git a/roms/u-boot/board/bosch/guardian/Makefile b/roms/u-boot/board/bosch/guardian/Makefile
new file mode 100644
index 000000000..11625c9dd
--- /dev/null
+++ b/roms/u-boot/board/bosch/guardian/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2018 Robert Bosch Power Tools GmbH
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/roms/u-boot/board/bosch/guardian/board.c b/roms/u-boot/board/bosch/guardian/board.c
new file mode 100644
index 000000000..113838f8b
--- /dev/null
+++ b/roms/u-boot/board/bosch/guardian/board.c
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for Bosch Guardian
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Robert Bosch Power Tools GmbH
+ */
+
+#include <common.h>
+#include <cpsw.h>
+#include <dm.h>
+#include <env.h>
+#include <env_internal.h>
+#include <errno.h>
+#include <i2c.h>
+#include <init.h>
+#include <led.h>
+#include <miiphy.h>
+#include <panel.h>
+#include <asm/global_data.h>
+#include <power/tps65217.h>
+#include <power/tps65910.h>
+#include <spl.h>
+#include <watchdog.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K128M16JT125K_RD_DQS,
+	.datawdsratio0 = MT41K128M16JT125K_WR_DQS,
+	.datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K128M16JT125K_RATIO,
+	.cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K128M16JT125K_RATIO,
+	.cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K128M16JT125K_RATIO,
+	.cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K128M16JT125K_EMIF_SDCFG,
+	.ref_ctrl = MT41K128M16JT125K_EMIF_SDREF,
+	.sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
+	.sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2,
+	.sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3,
+	.zq_config = MT41K128M16JT125K_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY,
+};
+
+#define OSC	(V_OSCK / 1000000)
+const struct dpll_params dpll_ddr = {
+		400, OSC - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	int mpu_vdd;
+	int usb_cur_lim;
+
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	if (i2c_probe(TPS65217_CHIP_PM))
+		return;
+
+	/*
+	 * Increase USB current limit to 1300mA or 1800mA and set
+	 * the MPU voltage controller as needed.
+	 */
+	if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+	} else {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+	}
+
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+			       TPS65217_POWER_PATH,
+			       usb_cur_lim,
+			       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set DCDC3 (CORE) voltage to 1.125V */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+				    TPS65217_DCDC_VOLT_SEL_1125MV)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/*
+	 * Set LDO3 to 1.8V and LDO4 to 3.3V
+	 */
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS1,
+			       TPS65217_LDO_VOLTAGE_OUT_1_8,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS2,
+			       TPS65217_LDO_VOLTAGE_OUT_3_3,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+	return &dpll_ddr;
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT41K128M16JT125K_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K128M16JT125K_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K128M16JT125K_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K128M16JT125K_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K128M16JT125K_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+	config_ddr(400, &ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif
+
+int board_init(void)
+{
+	save_omap_boot_params();
+
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_MTD_RAW_NAND
+	gpmc_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+static void set_bootmode_env(void)
+{
+	char *boot_device_name = NULL;
+	char *boot_mode_gpio = "gpio@44e07000_14";
+	int   ret;
+	int   value;
+
+	struct gpio_desc boot_mode_desc;
+
+	switch (gd->arch.omap_boot_device) {
+	case BOOT_DEVICE_NAND:
+		boot_device_name = "nand";
+		break;
+	case BOOT_DEVICE_USBETH:
+		boot_device_name = "usbeth";
+		break;
+	default:
+		break;
+	}
+
+	if (boot_device_name)
+		env_set("boot_device", boot_device_name);
+
+	ret = dm_gpio_lookup_name(boot_mode_gpio, &boot_mode_desc);
+	if (ret) {
+		printf("%s is not found\n", boot_mode_gpio);
+		goto err;
+	}
+
+	ret = dm_gpio_request(&boot_mode_desc, "setup_bootmode_env");
+	if (ret && ret != -EBUSY) {
+		printf("requesting gpio: %s failed\n", boot_mode_gpio);
+		goto err;
+	}
+
+	value = dm_gpio_get_value(&boot_mode_desc);
+	value ? env_set("swi_status", "0") : env_set("swi_status", "1");
+	return;
+
+err:
+	env_set("swi_status", "err");
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_LED_GPIO
+	led_default_state();
+#endif
+	set_bootmode_env();
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/roms/u-boot/board/bosch/guardian/board.h b/roms/u-boot/board/bosch/guardian/board.h
new file mode 100644
index 000000000..b301caf47
--- /dev/null
+++ b/roms/u-boot/board/bosch/guardian/board.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * Board header for Bosch Guardian
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Robert Bosch Power Tools GmbH
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/roms/u-boot/board/bosch/guardian/mux.c b/roms/u-boot/board/bosch/guardian/mux.c
new file mode 100644
index 000000000..9c81f29f9
--- /dev/null
+++ b/roms/u-boot/board/bosch/guardian/mux.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Robert Bosch Power Tools GmbH
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux guardian_interfaces_pin_mux[] = {
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLDOWN_EN)},
+	{OFFSET(mcasp0_aclkx),  (MODE(7) | PULLUP_EN)},
+	{OFFSET(mii1_txd0),     (MODE(7) | PULLUP_EN)},
+	{OFFSET(uart1_rxd),     (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(uart1_txd),     (MODE(7) | PULLUDDIS)},
+	{OFFSET(mii1_crs),      (MODE(7) | PULLDOWN_EN)},
+	{OFFSET(rmii1_refclk),  (MODE(7) | PULLDOWN_EN)},
+	{OFFSET(mii1_txd3),     (MODE(7) | PULLUDDIS)},
+	{OFFSET(mii1_rxdv),     (MODE(7) | PULLDOWN_EN)},
+	{-1},
+};
+
+#ifdef CONFIG_MTD_RAW_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0),      (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad1),      (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad2),      (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad3),      (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad4),      (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad5),      (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad6),      (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad7),      (MODE(0) | PULLUDDIS | RXACTIVE)},
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+	{OFFSET(gpmc_ad8),      (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad9),      (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad10),     (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad11),     (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad12),     (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad13),     (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad14),     (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad15),     (MODE(0) | PULLUDDIS | RXACTIVE)},
+#endif
+	{OFFSET(gpmc_wait0),    (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(gpmc_wpn),      (MODE(7) | PULLUP_EN)},
+	{OFFSET(gpmc_csn0),     (MODE(0) | PULLUP_EN)},
+	{OFFSET(gpmc_wen),      (MODE(0) | PULLDOWN_EN)},
+	{OFFSET(gpmc_oen_ren),  (MODE(0) | PULLDOWN_EN)},
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},
+	{-1},
+};
+#endif
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+#ifdef CONFIG_MTD_RAW_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#endif
+	configure_module_pin_mux(guardian_interfaces_pin_mux);
+}
diff --git a/roms/u-boot/board/bosch/shc/Kconfig b/roms/u-boot/board/bosch/shc/Kconfig
new file mode 100644
index 000000000..e0e56e6bf
--- /dev/null
+++ b/roms/u-boot/board/bosch/shc/Kconfig
@@ -0,0 +1,87 @@
+if TARGET_AM335X_SHC
+
+config SYS_BOARD
+	default "shc"
+
+config SYS_VENDOR
+	default "bosch"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "am335x_shc"
+
+choice
+	prompt "enable different boot versions for the shc board"
+	default SHC_EMMC
+	help
+	  Select the boot version of the shc board.
+
+config SHC_EMMC
+	bool "enable eMMC"
+	help
+	  enable here the eMMC functionality on the bosch shc board.
+
+config SHC_ICT
+	bool "enable ICT"
+	help
+	  enable here the ICT functionality on the bosch shc board
+
+config SHC_NETBOOT
+	bool "enable NETBOOT"
+	help
+	  enable here the NETBOOT functionality on the bosch shc board
+
+config SHC_SDBOOT
+	bool "enable SDBOOT"
+	help
+	  enable here the SDBOOT functionality on the bosch shc board
+
+endchoice
+
+choice
+	prompt "enable different board versions for the shc board"
+	default C3_SAMPLE
+	help
+	  Select the board version of the shc board.
+
+config B_SAMPLE
+	bool "B Sample board version"
+	help
+	  activate, if you want to build for the B sample version
+	  of the bosch shc board
+
+config B2_SAMPLE
+	bool "B2 Sample board version"
+	help
+	  activate, if you want to build for the B2 sample version
+	  of the bosch shc board
+
+config C_SAMPLE
+	bool "C Sample board version"
+	help
+	  activate, if you want to build for the C sample version
+	  of the bosch shc board
+
+config C2_SAMPLE
+	bool "C2 Sample board version"
+	help
+	  activate, if you want to build for the C2 sample version
+	  of the bosch shc board
+
+config C3_SAMPLE
+	bool "C3 Sample board version"
+	help
+	  activate, if you want to build for the C3 sample version
+	  of the bosch shc board
+
+config SERIES
+	bool "Series board version"
+	help
+	  activate, if you want to build for the Series version
+	  of the bosch shc board
+
+endchoice
+
+endif
diff --git a/roms/u-boot/board/bosch/shc/MAINTAINERS b/roms/u-boot/board/bosch/shc/MAINTAINERS
new file mode 100644
index 000000000..58104cc13
--- /dev/null
+++ b/roms/u-boot/board/bosch/shc/MAINTAINERS
@@ -0,0 +1,11 @@
+SHC BOARD
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	board/bosch/shc
+F:	include/configs/am335x_shc.h
+F:	configs/am335x_shc_defconfig
+F:	configs/am335x_shc_ict_defconfig
+F:	configs/am335x_shc_netboot_defconfig
+F:	configs/am335x_shc_sdboot_defconfig
+F:	arch/arm/dts/am335x-shc.dts
+F:	arch/arm/dts/am335x-shc-u-boot.dtsi
diff --git a/roms/u-boot/board/bosch/shc/Makefile b/roms/u-boot/board/bosch/shc/Makefile
new file mode 100644
index 000000000..93f2df377
--- /dev/null
+++ b/roms/u-boot/board/bosch/shc/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+
+obj-y	:= mux.o
+obj-y	+= board.o
diff --git a/roms/u-boot/board/bosch/shc/README b/roms/u-boot/board/bosch/shc/README
new file mode 100644
index 000000000..2f206e0d5
--- /dev/null
+++ b/roms/u-boot/board/bosch/shc/README
@@ -0,0 +1,114 @@
+Summary
+=======
+
+This document covers various features of the 'am335x_shc' build.
+
+Hardware
+========
+
+AM335X based board:
+
+I2C:   ready
+DRAM:  512 MiB
+Enabling the D-Cache
+MMC:   OMAP SD/MMC: 0 @ 26 MHz, OMAP SD/MMC: 1 @ 26 MHz
+Net:   cpsw
+
+Following boot options are possible:
+
+2 Jumpers:
+
+Jumper 1 Jumper 2 Bootmode
+off      off    eMMC boot
+on       off    SD boot
+off      on     Net boot
+
+Compiling
+=========
+
+$ make am335x_shc_defconfig
+  HOSTCC  scripts/basic/fixdep
+  HOSTCC  scripts/kconfig/conf.o
+  SHIPPED scripts/kconfig/zconf.tab.c
+  SHIPPED scripts/kconfig/zconf.lex.c
+  SHIPPED scripts/kconfig/zconf.hash.c
+  HOSTCC  scripts/kconfig/zconf.tab.o
+  HOSTLD  scripts/kconfig/conf
+#
+# configuration written to .config
+#
+$ make -s all
+
+-> now you have the MLO and the u-boot.img file, you can put
+on your SD card or eMMC.
+
+Configuring
+===========
+
+There are a lot of board versions and boot configurations, which
+can be selected through "make menuconfig"
+
+ARM architecture  --->
+  enable different boot versions for the shc board (enable eMMC)  --->
+   (X) enable eMMC
+   ( ) enable ICT
+   ( ) enable NETBOOT
+   ( ) enable SDBOOT
+
+  enable different board versions for the shc board (C3 Sample board version)  --->
+   ( ) B Sample board version
+   ( ) B2 Sample board version
+   ( ) C Sample board version
+   ( ) C2 Sample board version
+   (X) C3 Sample board version
+   ( ) Series board version
+
+Netboot
+=======
+- see also doc/SPL/README.am335x-network
+
+- set the jumper into netboot mode
+- compile the U-boot sources with:
+  make am335x_shc_netboot_defconfig
+  make all
+- copy the images into your tftp boot directory
+  cp spl/u-boot-spl.bin /tftpboot/.../u-boot-spl-restore.bin
+  cp u-boot.img /tftpboot/.../u-boot-restore.img
+- power on the board, and you should get something like this:
+
+U-Boot SPL 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18)
+#### NETBOOT ####
+SHC
+MPU reference clock runs at 6 MHz
+Setting MPU clock to 594 MHz
+Enabling Spread Spectrum of 18 permille for MPU
+Trying to boot from net
+Using default environment
+
+<ethaddr> not set. Validating first E-fuse MAC
+cpsw
+cpsw Waiting for PHY auto negotiation to complete... done
+link up on port 0, speed 100, full duplex
+BOOTP broadcast 1
+BOOTP broadcast 2
+DHCP client bound to address 192.168.20.91 (258 ms)
+Using cpsw device
+TFTP from server 192.168.1.1; our IP address is 192.168.20.91
+Filename 'shc/u-boot-restore.img'.
+Load address: 0x807fffc0
+Loading: ##################
+         1.2 MiB/s
+done
+Bytes transferred = 262480 (40150 hex)
+
+
+U-Boot 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18 +0200)
+
+       Watchdog enabled
+I2C:   ready
+DRAM:  512 MiB
+MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
+*** Warning - bad CRC, using default environment
+
+Net:   cpsw
+switch to partitions #0, OK
diff --git a/roms/u-boot/board/bosch/shc/board.c b/roms/u-boot/board/bosch/shc/board.c
new file mode 100644
index 000000000..86356e387
--- /dev/null
+++ b/roms/u-boot/board/bosch/shc/board.c
@@ -0,0 +1,533 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <irq_func.h>
+#include <net.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <linux/delay.h>
+#include <power/tps65217.h>
+#include <env_internal.h>
+#include <watchdog.h>
+#include "mmc.h"
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct shc_eeprom __section(".data") header;
+static int shc_eeprom_valid;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+	/* Check if baseboard eeprom is available */
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
+		return -ENODEV;
+	}
+
+	/* read the eeprom using i2c */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
+		     sizeof(header))) {
+		puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
+		return -EIO;
+	}
+
+	if (header.magic != HDR_MAGIC) {
+		printf("Incorrect magic number (0x%x) in EEPROM\n",
+		       header.magic);
+		return -EIO;
+	}
+
+	shc_eeprom_valid = 1;
+
+	return 0;
+}
+
+static void shc_request_gpio(void)
+{
+	gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
+	gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
+	gpio_request(RESET_GPIO, "reset");
+	gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
+	gpio_request(WIFI_RST_GPIO, "WIFI rst");
+	gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
+	gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
+	gpio_request(ENOC_RST_GPIO, "ENOC rst");
+#if defined CONFIG_B_SAMPLE
+	gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
+	gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
+	gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
+	gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
+#else
+	gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
+	gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
+	gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
+	gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
+	gpio_request(LED_PWM_GPIO, "LED PWM");
+	gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
+#endif
+	gpio_request(BACK_BUTTON_GPIO, "Back button");
+	gpio_request(FRONT_BUTTON_GPIO, "Front button");
+}
+
+/*
+ * Function which forces all installed modules into running state for ICT
+ * testing. Called by SPL.
+ */
+static void __maybe_unused force_modules_running(void)
+{
+	/* Wi-Fi power regulator enable - high = enabled */
+	gpio_direction_output(WIFI_REGEN_GPIO, 1);
+	/*
+	 * Wait for Wi-Fi power regulator to reach a stable voltage
+	 * (soft-start time, max. 350 µs)
+	 */
+	__udelay(350);
+
+	/* Wi-Fi module reset - high = running */
+	gpio_direction_output(WIFI_RST_GPIO, 1);
+
+	/* ZigBee reset - high = running */
+	gpio_direction_output(ZIGBEE_RST_GPIO, 1);
+
+	/* BidCos reset - high = running */
+	gpio_direction_output(BIDCOS_RST_GPIO, 1);
+
+#if !defined(CONFIG_B_SAMPLE)
+	/* Z-Wave reset - high = running */
+	gpio_direction_output(Z_WAVE_RST_GPIO, 1);
+#endif
+
+	/* EnOcean reset - low = running */
+	gpio_direction_output(ENOC_RST_GPIO, 0);
+}
+
+/*
+ * Function which forces all installed modules into reset - to be released by
+ * the OS, called by SPL
+ */
+static void __maybe_unused force_modules_reset(void)
+{
+	/* Wi-Fi module reset - low = reset */
+	gpio_direction_output(WIFI_RST_GPIO, 0);
+
+	/* Wi-Fi power regulator enable - low = disabled */
+	gpio_direction_output(WIFI_REGEN_GPIO, 0);
+
+	/* ZigBee reset - low = reset */
+	gpio_direction_output(ZIGBEE_RST_GPIO, 0);
+
+	/* BidCos reset - low = reset */
+	/*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
+
+#if !defined(CONFIG_B_SAMPLE)
+	/* Z-Wave reset - low = reset */
+	gpio_direction_output(Z_WAVE_RST_GPIO, 0);
+#endif
+
+	/* EnOcean reset - high = reset*/
+	gpio_direction_output(ENOC_RST_GPIO, 1);
+}
+
+/*
+ * Function to set the LEDs in the state "Bootloader booting"
+ */
+static void __maybe_unused leds_set_booting(void)
+{
+#if defined(CONFIG_B_SAMPLE)
+
+	/* Turn all red LEDs on */
+	gpio_direction_output(LED_PWR_RD_GPIO, 1);
+	gpio_direction_output(LED_CONN_RD_GPIO, 1);
+
+#else /* All other SHCs starting with B2-Sample */
+	/* Set the PWM GPIO */
+	gpio_direction_output(LED_PWM_GPIO, 1);
+	/* Turn all red LEDs on */
+	gpio_direction_output(LED_PWR_RD_GPIO, 1);
+	gpio_direction_output(LED_LAN_RD_GPIO, 1);
+	gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
+
+#endif
+}
+
+/*
+ * Function to set the LEDs in the state "Bootloader error"
+ */
+static void leds_set_failure(int state)
+{
+#if defined(CONFIG_B_SAMPLE)
+	/* Turn all blue and green LEDs off */
+	gpio_set_value(LED_PWR_BL_GPIO, 0);
+	gpio_set_value(LED_PWR_GN_GPIO, 0);
+	gpio_set_value(LED_CONN_BL_GPIO, 0);
+	gpio_set_value(LED_CONN_GN_GPIO, 0);
+
+	/* Turn all red LEDs to 'state' */
+	gpio_set_value(LED_PWR_RD_GPIO, state);
+	gpio_set_value(LED_CONN_RD_GPIO, state);
+
+#else /* All other SHCs starting with B2-Sample */
+	/* Set the PWM GPIO */
+	gpio_direction_output(LED_PWM_GPIO, 1);
+
+	/* Turn all blue LEDs off */
+	gpio_set_value(LED_PWR_BL_GPIO, 0);
+	gpio_set_value(LED_LAN_BL_GPIO, 0);
+	gpio_set_value(LED_CLOUD_BL_GPIO, 0);
+
+	/* Turn all red LEDs to 'state' */
+	gpio_set_value(LED_PWR_RD_GPIO, state);
+	gpio_set_value(LED_LAN_RD_GPIO, state);
+	gpio_set_value(LED_CLOUD_RD_GPIO, state);
+#endif
+}
+
+/*
+ * Function to set the LEDs in the state "Bootloader finished"
+ */
+static void leds_set_finish(void)
+{
+#if defined(CONFIG_B_SAMPLE)
+	/* Turn all LEDs off */
+	gpio_set_value(LED_PWR_BL_GPIO, 0);
+	gpio_set_value(LED_PWR_RD_GPIO, 0);
+	gpio_set_value(LED_PWR_GN_GPIO, 0);
+	gpio_set_value(LED_CONN_BL_GPIO, 0);
+	gpio_set_value(LED_CONN_RD_GPIO, 0);
+	gpio_set_value(LED_CONN_GN_GPIO, 0);
+#else /* All other SHCs starting with B2-Sample */
+	/* Turn all LEDs off */
+	gpio_set_value(LED_PWR_BL_GPIO, 0);
+	gpio_set_value(LED_PWR_RD_GPIO, 0);
+	gpio_set_value(LED_LAN_BL_GPIO, 0);
+	gpio_set_value(LED_LAN_RD_GPIO, 0);
+	gpio_set_value(LED_CLOUD_BL_GPIO, 0);
+	gpio_set_value(LED_CLOUD_RD_GPIO, 0);
+
+	/* Turn off the PWM GPIO and mux it to EHRPWM */
+	gpio_set_value(LED_PWM_GPIO, 0);
+	enable_shc_board_pwm_pin_mux();
+#endif
+}
+
+static void check_button_status(void)
+{
+	ulong value;
+	gpio_direction_input(FRONT_BUTTON_GPIO);
+	value = gpio_get_value(FRONT_BUTTON_GPIO);
+
+	if (value == 0) {
+		printf("front button activated !\n");
+		env_set("harakiri", "1");
+	}
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	return 1;
+}
+#endif
+
+static void shc_board_early_init(void)
+{
+	shc_request_gpio();
+# ifdef CONFIG_SHC_ICT
+	/* Force all modules into enabled state for ICT testing */
+	force_modules_running();
+# else
+	/* Force all modules to enter Reset state until released by the OS */
+	force_modules_reset();
+# endif
+	leds_set_booting();
+}
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
+#define OSC	(V_OSCK/1000000)
+/* Bosch: Predivider must be fixed to 4, so N = 4-1 */
+#define MPUPLL_N        (4-1)
+/* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
+#define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
+
+const struct dpll_params dpll_ddr_shc = {
+		400, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr_shc;
+}
+
+/*
+ * As we enabled downspread SSC with 1.8%, the values needed to be corrected
+ * such that the 20% overshoot will not lead to too high frequencies.
+ * In all cases, this is achieved by subtracting one from M (6 MHz less).
+ * Example: 600 MHz CPU
+ *   Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
+ *   600 MHz - 6 MHz (1x Fref) = 594 MHz
+ *   SSC: 594 MHz * 1.8% = 10.7 MHz SSC
+ *   Overshoot: 10.7 MHz * 20 % = 2.2 MHz
+ *   --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
+ */
+const struct dpll_params dpll_mpu_shc_opp100 = {
+		99, MPUPLL_N, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	int sil_rev;
+	int mpu_vdd;
+
+	puts(BOARD_ID_STR);
+
+	/*
+	 * Set CORE Frequency to OPP100
+	 * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
+	 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	if (sil_rev < 2) {
+		puts("We do not support Silicon Revisions below 2.0!\n");
+		return;
+	}
+
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+	if (i2c_probe(TPS65217_CHIP_PM))
+		return;
+
+	/*
+	 * Retrieve the CPU max frequency by reading the efuse
+	 * SHC-Default: 600 MHz
+	 */
+	switch (dpll_mpu_opp100.m) {
+	case MPUPLL_M_1000:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+		break;
+	case MPUPLL_M_800:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+		break;
+	case MPUPLL_M_720:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
+		break;
+	case MPUPLL_M_600:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
+		break;
+	case MPUPLL_M_300:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
+		break;
+	default:
+		puts("Cannot determine the frequency, failing!\n");
+		return;
+	}
+
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set MPU Frequency to what we detected */
+	printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
+	printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
+	       dpll_mpu_shc_opp100.m);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
+
+	/* Enable Spread Spectrum for this freq to be clean on EMI side */
+	set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
+
+	/*
+	 * Using the default voltages for the PMIC (TPS65217D)
+	 * LS1 = 1.8V (VDD_1V8)
+	 * LS2 = 3.3V (VDD_3V3A)
+	 * LDO1 = 1.8V (VIO and VRTC)
+	 * LDO2 = 3.3V (VDD_3V3AUX)
+	 */
+	shc_board_early_init();
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_shc_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs_evmsk = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_shc_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_shc_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
+};
+
+void sdram_init(void)
+{
+	/* Configure the DDR3 RAM */
+	config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
+		   &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	if (read_eeprom() < 0)
+		puts("EEPROM Content Invalid.\n");
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
+	gpmc_init();
+#endif
+	shc_request_gpio();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	check_button_status();
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (shc_eeprom_valid)
+		if (is_valid_ethaddr(header.mac_addr))
+			eth_env_set_enetaddr("ethaddr", header.mac_addr);
+#endif
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
+int board_eth_init(struct bd_info *bis)
+{
+	return usb_eth_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+static void bosch_check_reset_pin(void)
+{
+	if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
+		printf("Resetting ...\n");
+		writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
+		disable_interrupts();
+		reset_cpu();
+		/*NOTREACHED*/
+	}
+}
+
+static void hang_bosch(const char *cause, int code)
+{
+	int lv;
+
+	gpio_direction_input(RESET_GPIO);
+
+	/* Enable reset pin interrupt on falling edge */
+	writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
+	writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
+	enable_interrupts();
+
+	puts(cause);
+	for (;;) {
+		for (lv = 0; lv < code; lv++) {
+			bosch_check_reset_pin();
+			leds_set_failure(1);
+			__udelay(150 * 1000);
+			leds_set_failure(0);
+			__udelay(150 * 1000);
+		}
+#if defined(BLINK_CODE)
+		__udelay(300 * 1000);
+#endif
+	}
+}
+
+void show_boot_progress(int val)
+{
+	switch (val) {
+	case BOOTSTAGE_ID_NEED_RESET:
+		hang_bosch("need reset", 4);
+		break;
+	}
+}
+
+void arch_preboot_os(void)
+{
+	leds_set_finish();
+}
+#endif
diff --git a/roms/u-boot/board/bosch/shc/board.h b/roms/u-boot/board/bosch/shc/board.h
new file mode 100644
index 000000000..997595bf4
--- /dev/null
+++ b/roms/u-boot/board/bosch/shc/board.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/* Definition to control the GPIOs (for LEDs and Reset) */
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+
+static inline int board_is_b_sample(void)
+{
+#if defined CONFIG_B_SAMPLE
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+static inline int board_is_c_sample(void)
+{
+#if defined CONFIG_C_SAMPLE
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+static inline int board_is_c3_sample(void)
+{
+#if defined CONFIG_C3_SAMPLE
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+static inline int board_is_series(void)
+{
+#if defined CONFIG_SERIES
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+/*
+ * Definitions for pinmuxing header and Board ID strings
+ */
+#if defined CONFIG_B_SAMPLE
+# define BOARD_ID_STR "SHC B-Sample\n"
+#elif defined CONFIG_B2_SAMPLE
+# define BOARD_ID_STR "SHC B2-Sample\n"
+#elif defined CONFIG_C_SAMPLE
+# if defined(CONFIG_SHC_NETBOOT)
+#  define BOARD_ID_STR "#### NETBOOT ####\nSHC C-Sample\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+#  define BOARD_ID_STR "#### SDBOOT ####\nSHC C-Sample\n"
+# else
+#  define BOARD_ID_STR "SHC C-Sample\n"
+# endif
+#elif defined CONFIG_C2_SAMPLE
+# if defined(CONFIG_SHC_ICT)
+#  define BOARD_ID_STR "#### ICT ####\nSHC C2-Sample\n"
+# elif defined(CONFIG_SHC_NETBOOT)
+#  define BOARD_ID_STR "#### NETBOOT ####\nSHC C2-Sample\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+#  define BOARD_ID_STR "#### SDBOOT ####\nSHC C2-Sample\n"
+# else
+#  define BOARD_ID_STR "SHC C2-Sample\n"
+# endif
+#elif defined CONFIG_C3_SAMPLE
+# if defined(CONFIG_SHC_ICT)
+#  define BOARD_ID_STR "#### ICT ####\nSHC C3-Sample\n"
+# elif defined(CONFIG_SHC_NETBOOT)
+#  define BOARD_ID_STR "#### NETBOOT ####\nSHC C3-Sample\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+#  define BOARD_ID_STR "#### SDBOOT ####\nSHC C3-Sample\n"
+# else
+#  define BOARD_ID_STR "SHC C3-Sample\n"
+# endif
+#elif defined CONFIG_SERIES
+# if defined(CONFIG_SHC_ICT)
+#  define BOARD_ID_STR "#### ICT ####\nSHC\n"
+# elif defined(CONFIG_SHC_NETBOOT)
+#  define BOARD_ID_STR "#### NETBOOT ####\nSHC\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+#  define BOARD_ID_STR "#### SDBOOT ####\nSHC\n"
+# else
+#  define BOARD_ID_STR "SHC\n"
+# endif
+#else
+# define BOARD_ID_STR "Unknown device!\n"
+#endif
+
+/*
+ * Definitions for GPIO pin assignments
+ */
+#if defined CONFIG_B_SAMPLE
+
+# define LED_PWR_BL_GPIO   GPIO_TO_PIN(1, 17)
+# define LED_PWR_RD_GPIO   GPIO_TO_PIN(1, 18)
+# define LED_PWR_GN_GPIO   GPIO_TO_PIN(1, 19)
+# define LED_CONN_BL_GPIO  GPIO_TO_PIN(0, 26)
+# define LED_CONN_RD_GPIO  GPIO_TO_PIN(0, 22)
+# define LED_CONN_GN_GPIO  GPIO_TO_PIN(0, 23)
+# define RESET_GPIO        GPIO_TO_PIN(1, 29)
+# define WIFI_REGEN_GPIO   GPIO_TO_PIN(1, 16)
+# define WIFI_RST_GPIO     GPIO_TO_PIN(0, 27)
+# define ZIGBEE_RST_GPIO   GPIO_TO_PIN(3, 18)
+# define BIDCOS_RST_GPIO   GPIO_TO_PIN(0, 12)
+# define ENOC_RST_GPIO     GPIO_TO_PIN(1, 22)
+
+#else
+
+# define LED_PWR_BL_GPIO   GPIO_TO_PIN(0, 22)
+# define LED_PWR_RD_GPIO   GPIO_TO_PIN(0, 23)
+# define LED_LAN_BL_GPIO   GPIO_TO_PIN(1, 17)
+# define LED_LAN_RD_GPIO   GPIO_TO_PIN(0, 26)
+# define LED_CLOUD_BL_GPIO GPIO_TO_PIN(1, 18)
+# define LED_CLOUD_RD_GPIO GPIO_TO_PIN(2, 2)
+# define LED_PWM_GPIO      GPIO_TO_PIN(1, 19)
+# define RESET_GPIO        GPIO_TO_PIN(1, 29)
+# define WIFI_REGEN_GPIO   GPIO_TO_PIN(1, 16)
+# define WIFI_RST_GPIO     GPIO_TO_PIN(0, 27)
+# define ZIGBEE_RST_GPIO   GPIO_TO_PIN(3, 18)
+# define BIDCOS_RST_GPIO   GPIO_TO_PIN(1, 24)
+# define Z_WAVE_RST_GPIO   GPIO_TO_PIN(1, 21)
+# define ENOC_RST_GPIO     GPIO_TO_PIN(1, 22)
+
+#endif
+
+#define BACK_BUTTON_GPIO    GPIO_TO_PIN(1, 29)
+#define FRONT_BUTTON_GPIO   GPIO_TO_PIN(1, 25)
+
+/* Reset is on GPIO pin 29 of GPIO bank 1 */
+#define RESET_MASK	(0x1 << 29)
+
+#define HDR_MAGIC	0x43485342
+#define HDR_ETH_ALEN	6
+#define HDR_NAME_LEN	8
+#define HDR_REV_LEN	8
+#define HDR_SER_LEN	16
+#define HDR_ROOT_LEN	12
+#define HDR_FATC_LEN	12
+
+/*
+* SHC parameters held in On-Board I²C EEPROM device.
+*
+* Header Format
+*
+*  Name     Size   Contents
+*-------------------------------------------------------------
+*  Magic     4     0x42 0x53 0x48 0x43  [BSHC]
+*
+*  Version   2     0x0100 for v1.0
+*
+*  Lenght    2     The length of the complete structure, not only this header
+*
+*  Eth-MAC   6     Ethernet MAC Address
+*                  SHC Pool: 7C:AC:B2:00:10:01 - TBD
+*
+*  --- Further values follow, not important for Bootloader ---
+*/
+
+struct  shc_eeprom {
+	u32  magic;
+	u16  version;
+	u16  lenght;
+	uint8_t mac_addr[HDR_ETH_ALEN];
+};
+
+void enable_uart0_pin_mux(void);
+void enable_shc_board_pin_mux(void);
+void enable_shc_board_pwm_pin_mux(void);
+
+#endif
diff --git a/roms/u-boot/board/bosch/shc/mux.c b/roms/u-boot/board/bosch/shc/mux.c
new file mode 100644
index 000000000..0a97eafea
--- /dev/null
+++ b/roms/u-boot/board/bosch/shc/mux.c
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)},		/* UART0_TXD */
+	{OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)},	/* UART0_CTS */
+	{OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)},		/* UART0_RTS */
+	{-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)},	/* UART1_RXD */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)},		/* UART1_TXD */
+	{OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)},	/* UART1_CTS */
+	{OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)},		/* UART1_RTS */
+	{-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)},	/* UART2_RXD */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)},		/* UART2_TXD */
+	{-1},
+};
+
+static struct module_pin_mux spi1_pin_mux[] = {
+	{OFFSET(mcasp0_aclkx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_SCLK */
+	{OFFSET(mcasp0_fsx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D0 */
+	{OFFSET(mcasp0_axr0), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D1 */
+	{OFFSET(mcasp0_ahclkr), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_CS0 */
+	{-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUP_EN)},		/* UART4_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDDIS)},	/* MMC0_CD */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUDDIS)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{-1},
+};
+
+static struct module_pin_mux mmc2_pin_mux[] = {
+	{OFFSET(gpmc_ad12), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT0 */
+	{OFFSET(gpmc_ad13), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT1 */
+	{OFFSET(gpmc_ad14), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT2 */
+	{OFFSET(gpmc_ad15), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT3 */
+	{OFFSET(gpmc_csn3), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CMD */
+	{OFFSET(gpmc_clk), (MODE(3) | RXACTIVE | PULLUDDIS)},  /* MMC2_CLK */
+	{-1},
+};
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux gpio0_7_pin_mux[] = {
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUP_EN)},	/* GPIO0_7 */
+	{-1},
+};
+
+static struct module_pin_mux jtag_pin_mux[] = {
+	{OFFSET(xdma_event_intr0), (MODE(6) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(xdma_event_intr1), (MODE(6) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(nresetin_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(tdo), (MODE(0) | PULLUP_EN)},
+	{OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(ntrst), (MODE(0) | RXACTIVE)},
+	{OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)},
+	{OFFSET(rsvd2), (MODE(0) | PULLUP_EN)},
+	{OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)},
+	{OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)},
+	{OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	{OFFSET(gpmc_ad8), (MODE(7) | PULLUDDIS)},	/* gpio0[22] - LED_PWR_BL (external pull-down) */
+	{OFFSET(gpmc_ad9), (MODE(7) | PULLUDDIS)},	/* gpio0[23] - LED_PWR_RD (external pull-down) */
+	{OFFSET(gpmc_ad10), (MODE(7) | PULLUDDIS)},	/* gpio0[26] - LED_LAN_RD (external pull-down) */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},	/* gpio0[27] - #WIFI_RST (external pull-down) */
+	{OFFSET(gpmc_a0), (MODE(7) | PULLUDDIS)},	/* gpio1[16] - WIFI_REGEN */
+	{OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS)},	/* gpio1[17] - LED_LAN_BL */
+	{OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS)},	/* gpio1[18] - LED_Cloud_BL */
+	{OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS)},	/* gpio1[19] -  LED_PWM as GPIO */
+	{OFFSET(gpmc_a4), (MODE(7))},			/* gpio1[20] -  #eMMC_RST */
+	{OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)},	/* gpio1[21] -  #Z-Wave_RST */
+	{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)},	/* gpio1[22] -  ENOC_RST */
+	{OFFSET(gpmc_a7), (MODE(7) | PULLUP_EN)},	/* gpio1[23] -  WIFI_MODE */
+	{OFFSET(gpmc_a8), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[24] -  #BIDCOS_RST */
+	{OFFSET(gpmc_a9), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[25] -  USR_BUTTON */
+	{OFFSET(gpmc_a10), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[26] -  #USB1_OC */
+	{OFFSET(gpmc_a11), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[27] -  BIDCOS_PROG */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUP_EN)},	/* gpio1[28] -  ZIGBEE_PC7 */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[29] -  RESET_BUTTON */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS)},	/* gpio2[2] -  LED_Cloud_RD */
+	{OFFSET(gpmc_oen_ren), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* gpio2[3] -  #WIFI_POR */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},	/* gpio2[4] -  N/C */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},	/* gpio2[5] -  EEPROM_WP */
+	{OFFSET(lcd_data0), (MODE(7) | PULLUDDIS)},	/* gpio2[6] */
+	{OFFSET(lcd_data1), (MODE(7) | PULLUDDIS)},	/* gpio2[7] */
+	{OFFSET(lcd_data2), (MODE(7) | PULLUDDIS)},	/* gpio2[8] */
+	{OFFSET(lcd_data3), (MODE(7) | PULLUDDIS)},	/* gpio2[9] */
+	{OFFSET(lcd_data4), (MODE(7) | PULLUDDIS)},	/* gpio2[10] */
+	{OFFSET(lcd_data5), (MODE(7) | PULLUDDIS)},	/* gpio2[11] */
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDDIS)},	/* gpio2[12] */
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDDIS)},	/* gpio2[13] */
+	{OFFSET(lcd_data8), (MODE(7) | PULLUDDIS)},	/* gpio2[14] */
+	{OFFSET(lcd_data9), (MODE(7) | PULLUDDIS)},	/* gpio2[15] */
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDDIS)},	/* gpio2[16] */
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDDIS)},	/* gpio2[17] */
+	{OFFSET(lcd_data12), (MODE(7) | PULLUDDIS)},	/* gpio0[8] */
+	{OFFSET(lcd_data13), (MODE(7) | PULLUDDIS)},	/* gpio0[9] */
+	{OFFSET(lcd_data14), (MODE(7) | PULLUDDIS)},	/* gpio0[10] */
+	{OFFSET(lcd_data15), (MODE(7) | PULLUDDIS)},	/* gpio0[11] */
+	{OFFSET(lcd_vsync), (MODE(7) | PULLUDDIS)},	/* gpio2[22] */
+	{OFFSET(lcd_hsync), (MODE(7) | PULLUDDIS)},	/* gpio2[23] */
+	{OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)},	/* gpio2[24] */
+	{OFFSET(lcd_ac_bias_en), (MODE(7) | PULLUDDIS)},/* gpio2[25] */
+	{OFFSET(spi0_d1), (MODE(7) | PULLUDDIS)},	/* gpio0[4] */
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},	/* gpio0[5] */
+	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS)},	/* gpio3[18] - #ZIGBEE_RST */
+	{OFFSET(mcasp0_fsr), (MODE(7)) | PULLUDDIS},	/* gpio3[19] - ZIGBEE_BOOT */
+	{OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)},	/* gpio3[19] - ZIGBEE_BOOT */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE | PULLUP_EN)},/* gpio3[21] - ZIGBEE_PC5 */
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_col), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_txen), MODE(0)},
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_txd3), MODE(0)},
+	{OFFSET(mii1_txd2), MODE(0)},
+	{OFFSET(mii1_txd1), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_txd0), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},
+	{OFFSET(rmii1_refclk), MODE(7) | RXACTIVE},
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},
+	{-1},
+};
+
+static struct module_pin_mux pwm_pin_mux[] = {
+	{OFFSET(gpmc_a3), (MODE(6) | PULLUDDIS)},
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_shc_board_pwm_pin_mux(void)
+{
+	configure_module_pin_mux(pwm_pin_mux);
+}
+
+void enable_shc_board_pin_mux(void)
+{
+	/* Do board-specific muxes. */
+	if (board_is_c3_sample() || board_is_series()) {
+		configure_module_pin_mux(mii1_pin_mux);
+		configure_module_pin_mux(mmc0_pin_mux);
+		configure_module_pin_mux(mmc1_pin_mux);
+		configure_module_pin_mux(mmc2_pin_mux);
+		configure_module_pin_mux(i2c0_pin_mux);
+		configure_module_pin_mux(gpio0_7_pin_mux);
+		configure_module_pin_mux(gpio_pin_mux);
+		configure_module_pin_mux(uart1_pin_mux);
+		configure_module_pin_mux(uart2_pin_mux);
+		configure_module_pin_mux(uart4_pin_mux);
+		configure_module_pin_mux(spi1_pin_mux);
+		configure_module_pin_mux(jtag_pin_mux);
+	} else {
+		puts("Unknown board, cannot configure pinmux.");
+		hang();
+	}
+}
diff --git a/roms/u-boot/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg b/roms/u-boot/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
new file mode 100644
index 000000000..c38c15147
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7974
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42720306
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026F0266
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4273030A
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02740240
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45393B3E
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x403A3747
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40434541
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x473E4A3B
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0011000E
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x000E001B
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00190015
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00070018
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/roms/u-boot/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg b/roms/u-boot/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
new file mode 100644
index 000000000..f81d49106
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42740304
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026e0265
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x02750306
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02720244
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x463d4041
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c47
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x37414441
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4633473b
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0025001f
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00290027
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f002b
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000f0029
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/roms/u-boot/board/boundary/nitrogen6x/6x_bootscript.txt b/roms/u-boot/board/boundary/nitrogen6x/6x_bootscript.txt
new file mode 100644
index 000000000..061b3a44b
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/6x_bootscript.txt
@@ -0,0 +1,63 @@
+setenv bootargs enable_wait_mode=off
+setenv nextcon 0;
+
+if hdmidet ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
+	setenv fbmem "fbmem=28M";
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no HDMI monitor";
+fi
+
+i2c dev 2
+if i2c probe 0x04 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbmem "fbmem=10M";
+	else
+		setenv fbmem ${fbmem},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no Freescale display";
+fi
+
+if i2c probe 0x38 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbmem "fbmem=10M";
+	else
+		setenv fbmem ${fbmem},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no 1024x600 display";
+fi
+
+if i2c probe 0x48 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbmem "fbmem=10M";
+	else
+		setenv fbmem ${fbmem},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no 800x480 display";
+fi
+
+while test "3" -ne $nextcon ; do
+	setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
+	setexpr nextcon $nextcon + 1 ;
+done
+
+setenv bootargs $bootargs $fbmem
+setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait"
+
+if test "sata" = "${dtype}" ; then
+	setenv bootargs "$bootargs root=/dev/sda1" ;
+else
+	setenv "bootargs $bootargs root=/dev/mmcblk0p1" ;
+fi
+${fs}load ${dtype} ${disk}:1 10800000 /boot/uImage && bootm 10800000 ;
+echo "Error loading kernel image"
diff --git a/roms/u-boot/board/boundary/nitrogen6x/6x_bootscript_android.txt b/roms/u-boot/board/boundary/nitrogen6x/6x_bootscript_android.txt
new file mode 100644
index 000000000..0982cf805
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/6x_bootscript_android.txt
@@ -0,0 +1,64 @@
+${dtype} dev ${disk}
+
+setenv bootargs enable_wait_mode=off
+setenv nextcon 0;
+setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ;
+
+i2c dev 2
+
+if i2c probe 0x04 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=10M";
+	else
+		setenv fbcon ${fbcon},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no Freescale display";
+fi
+
+if i2c probe 0x38 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=10M";
+	else
+		setenv fbcon ${fbcon},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no 1024x600 display";
+fi
+
+if i2c probe 0x48 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=10M";
+	else
+		setenv fbcon ${fbcon},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no 800x480 display";
+fi
+
+if hdmidet ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=28M";
+	else
+		setenv fbcon ${fbcon},28M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no HDMI monitor";
+fi
+
+while test "3" -ne $nextcon ; do
+	setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
+	setexpr nextcon $nextcon + 1 ;
+done
+
+setenv bootargs $bootargs fbcon=$fbcon
+${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000
+echo "Error loading kernel image"
diff --git a/roms/u-boot/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt b/roms/u-boot/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt
new file mode 100644
index 000000000..0982cf805
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt
@@ -0,0 +1,64 @@
+${dtype} dev ${disk}
+
+setenv bootargs enable_wait_mode=off
+setenv nextcon 0;
+setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ;
+
+i2c dev 2
+
+if i2c probe 0x04 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=10M";
+	else
+		setenv fbcon ${fbcon},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no Freescale display";
+fi
+
+if i2c probe 0x38 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=10M";
+	else
+		setenv fbcon ${fbcon},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no 1024x600 display";
+fi
+
+if i2c probe 0x48 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=10M";
+	else
+		setenv fbcon ${fbcon},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no 800x480 display";
+fi
+
+if hdmidet ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=28M";
+	else
+		setenv fbcon ${fbcon},28M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no HDMI monitor";
+fi
+
+while test "3" -ne $nextcon ; do
+	setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
+	setexpr nextcon $nextcon + 1 ;
+done
+
+setenv bootargs $bootargs fbcon=$fbcon
+${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000
+echo "Error loading kernel image"
diff --git a/roms/u-boot/board/boundary/nitrogen6x/6x_upgrade.txt b/roms/u-boot/board/boundary/nitrogen6x/6x_upgrade.txt
new file mode 100644
index 000000000..cd3c33e40
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/6x_upgrade.txt
@@ -0,0 +1,45 @@
+setenv stdout serial,vidconsole
+echo "check U-Boot" ;
+setenv offset 0x400
+if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then
+      echo "read $filesize bytes from SD card" ;
+      if sf probe || sf probe || \
+	 sf probe 1 27000000 || sf probe 1 27000000 ; then
+	   echo "probed SPI ROM" ;
+	   if sf read 0x12400000 $offset $filesize ; then
+	       if cmp.b 0x12000000 0x12400000 $filesize ; then
+		   echo "------- U-Boot versions match" ;
+	       else
+		   echo "Need U-Boot upgrade" ;
+		   echo "Program in 5 seconds" ;
+		   for n in 5 4 3 2 1 ; do
+			echo $n ;
+			sleep 1 ;
+		   done
+		   echo "erasing" ;
+		   sf erase 0 0xC0000 ;
+		   # two steps to prevent bricking
+		   echo "programming" ;
+		   sf write 0x12000000 $offset $filesize ;
+		   echo "verifying" ;
+		   if sf read 0x12400000 $offset $filesize ; then
+		       if cmp.b 0x12000000 0x12400000 $filesize ; then
+			   while echo "---- U-Boot upgraded. reset" ; do
+				sleep 120
+			   done
+		       else
+			   echo "Read verification error" ;
+		       fi
+		   else
+			echo "Error re-reading EEPROM" ;
+		   fi
+	       fi
+	   else
+	       echo "Error reading boot loader from EEPROM" ;
+	   fi
+      else
+	   echo "Error initializing EEPROM" ;
+      fi ;
+else
+     echo "No U-Boot image found on SD card" ;
+fi
diff --git a/roms/u-boot/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg b/roms/u-boot/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg
new file mode 100644
index 000000000..cb04832c5
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/roms/u-boot/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg b/roms/u-boot/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg
new file mode 100644
index 000000000..d85466f2f
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/roms/u-boot/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg b/roms/u-boot/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg
new file mode 100644
index 000000000..417af6450
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420F020F
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01760175
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x41640171
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015E0160
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45464B4A
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x49484A46
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40402E32
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3A3A3231
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x003A003A
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0030002F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x002F0038
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00270039
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/roms/u-boot/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg b/roms/u-boot/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg
new file mode 100644
index 000000000..6f75ea277
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/roms/u-boot/board/boundary/nitrogen6x/Kconfig b/roms/u-boot/board/boundary/nitrogen6x/Kconfig
new file mode 100644
index 000000000..f4db56d49
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NITROGEN6X
+
+config SYS_BOARD
+	default "nitrogen6x"
+
+config SYS_VENDOR
+	default "boundary"
+
+config SYS_CONFIG_NAME
+	default "nitrogen6x"
+
+endif
diff --git a/roms/u-boot/board/boundary/nitrogen6x/MAINTAINERS b/roms/u-boot/board/boundary/nitrogen6x/MAINTAINERS
new file mode 100644
index 000000000..17018d69f
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/MAINTAINERS
@@ -0,0 +1,17 @@
+NITROGEN6X BOARD
+M:	Troy Kisky <troy.kisky@boundarydevices.com>
+S:	Maintained
+F:	arch/arm/dts/imx6dl-nitrogen6x.dts
+F:	arch/arm/dts/imx6q-nitrogen6x.dts
+F:	arch/arm/dts/imx6q-sabrelite.dts
+F:	arch/arm/dts/imx6qdl-nitrogen6x.dtsi
+F:	arch/arm/dts/imx6qdl-sabrelite.dtsi
+F:	board/boundary/nitrogen6x/
+F:	include/configs/nitrogen6x.h
+F:	configs/mx6qsabrelite_defconfig
+F:	configs/nitrogen6dl_defconfig
+F:	configs/nitrogen6dl2g_defconfig
+F:	configs/nitrogen6q_defconfig
+F:	configs/nitrogen6q2g_defconfig
+F:	configs/nitrogen6s_defconfig
+F:	configs/nitrogen6s1g_defconfig
diff --git a/roms/u-boot/board/boundary/nitrogen6x/Makefile b/roms/u-boot/board/boundary/nitrogen6x/Makefile
new file mode 100644
index 000000000..c8433bd74
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+
+obj-y  := nitrogen6x.o
diff --git a/roms/u-boot/board/boundary/nitrogen6x/README b/roms/u-boot/board/boundary/nitrogen6x/README
new file mode 100644
index 000000000..9d8426502
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/README
@@ -0,0 +1,92 @@
+U-Boot for the Boundary Devices Nitrogen6X and
+Freescale i.MX6Q SabreLite boards
+
+This file contains information for the port of
+U-Boot to the Boundary Devices Nitrogen6X and
+Freescale i.MX6Q SabreLite boards.
+
+1. Boot source, boot from SPI NOR
+---------------------------------
+The configuration in this directory supports both the
+Nitrogen6X and Freescale SabreLite board, but in a
+different fashion from Freescale's implementation in
+board/freescale/mx6qsabrelite.
+
+In particular, this image supports booting from SPI NOR
+and saving the environment to SPI NOR.
+
+It does not support 'boot from SD' at offset 0x400
+except through the 'bmode' command.
+	http://lists.denx.de/pipermail/u-boot/2012-August/131151.html
+
+2. Boots using 6x_bootscript on SATA or SD card
+-----------------------------------------------
+The default bootcmd for these boards is configured
+to look for and source a boot script named '6x_bootscript'
+in the root of the first partition of the following
+devices:
+
+	sata 0
+	mmc 0
+	mmc 1
+
+They're searched in the order listed above, trying both the
+ext2 and fat filesystems.
+
+2. Maintaining the SPI NOR
+--------------------------
+A couple of convenience commands
+
+	clearenv - clear environment to factory default
+	upgradeu - look and source a boot script named
+		'6x_upgrade' to upgrade the U-Boot version
+		in SPI NOR. The search is the same as for
+		6x_bootscript described above.
+
+3. Display support
+------------------
+U-Boot support for the following displays is configured by
+default:
+
+    HDMI           - 1024 x 768 for maximum compatibility
+    Hannstar-XGA   - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1)
+    wsvga-lvds     - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600)
+    wvga-rgb       - 800 x 480 RGB (Boundary p/n Nit6X_800x480)
+
+Since the ipuv3_fb display driver currently supports only a single display,
+this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect
+or the I2C touch controller of the LVDS and RGB displays in the priority
+listed above.
+
+Setting 'panel' environment variable to one of the names above will
+override auto-detection and force activation of the specified panel.
+
+4. Building
+------------
+
+To build U-Boot for one of the Nitrogen6x or SabreLite board:
+
+	make nitrogen6x_config
+	make
+
+Note that 'nitrogen6x' is a placeholder. The complete list of supported
+board configurations is shown in the boards.cfg file:
+	nitrogen6q		i.MX6Q/6D	1GB
+	nitrogen6dl		i.MX6DL		1GB
+	nitrogen6s		i.MX6S		512MB
+	nitrogen6q2g    	i.MX6Q/6D	2GB
+	nitrogen6dl2g		i.MX6DL		2GB
+	nitrogen6s1g		i.MX6S		1GB
+
+The -6q variants support either the i.MX6Quad or i.MX6Dual processors
+and are configured for a 64-bit memory bus at 1066 MHz.
+
+The -6dl variants also use a 64-bit memory bus, operated at 800MHz.
+
+The -6s variants use a 32-bit memory bus at 800MHz.
+
+If you place the u-boot.imx into a single-partition SD card
+along with a binary version of the boot script 6x_upgrade.txt,
+you can program it using 'upgradeu':
+
+	U-Boot> run upgradeu
diff --git a/roms/u-boot/board/boundary/nitrogen6x/README.mx6qsabrelite b/roms/u-boot/board/boundary/nitrogen6x/README.mx6qsabrelite
new file mode 100644
index 000000000..6283c9575
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/README.mx6qsabrelite
@@ -0,0 +1,119 @@
+U-Boot for the Freescale i.MX6q SabreLite board
+===============================================
+
+This file contains information for the port of U-Boot to the Freescale
+i.MX6q SabreLite board.
+
+
+1. Build
+--------
+
+To build U-Boot for the SabreLite board:
+
+ make mx6qsabrelite_config
+ make
+
+
+2. Boot from SD card
+--------------------
+
+The SabreLite boards boot from the SPI NOR flash. These boards need their SPI
+to be reflashed with a small SD card loader to support boot from SD card. The
+board will still boot from SPI NOR, but the loader will in turn request the
+BootROM to load the U-Boot from SD card.
+
+The SD card loader is available from
+
+https://wiki.linaro.org/Boards/MX6QSabreLite
+
+This is provided under a open-source 3-clause BSD license.
+
+To following procedure can be used to update the SPI-NOR on the SabreLite
+board:
+
+1. Write this SD card loader onto a large SD card using:
+
+      sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx
+
+   Note: Replace sXx with the device representing the SD card in your system.
+
+   Note: This writes SD card loader at address 0
+
+2. Put this SD card into the slot for the large SD card (SD3 on the bottom of
+   the board). Make sure SW1 switch is at position "00", so that it can boot
+   from the fuses.
+
+3. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot
+   (the default one the board is shipped with, starting from the SPI NOR) and
+   enter the following commands:
+
+      MX6Q SABRELITE U-Boot > mmc dev 0
+      MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200
+      MX6Q SABRELITE U-Boot > sf probe
+      MX6Q SABRELITE U-Boot > sf erase 0 0x40000
+      MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000
+
+4. Write the u-boot.imx produced during the U-Boot build to the SD card:
+
+      sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2 && sudo sync
+
+   Note: Replace sXx with the device representing the SD card in your system.
+
+5. Re-insert the SD card back in the slot for the large SD card and power-cycle
+   the board.
+
+Note: The board now boots from full size SD3 on the bottom of the board. NOT
+      the micro SD4/BOOT slot on the top of the board. I.e. you have to use
+      full size SD cards.
+
+This information originally taken from:
+
+   https://wiki.linaro.org/Boards/MX6QSabreLite
+
+
+3. Boot from SPI NOR
+--------------------
+
+The SabreLite board can also boot U-Boot directly from the SPI NOR flash:
+
+1. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot
+   and enter the following commands:
+
+      => mmc dev 0
+      => mmc read 0x10800000 0x400 0x80000
+      => sf probe 0
+      => sf erase 0 0xc0000
+      => sf write 0x10800000 0x400 0x80000
+
+Note: This procedure assumes you have booted using the desired U-Boot from an
+      SD card as prepared in the previous section. Alternative mechanisms, such
+      as using tftpboot to copy an alternative U-Boot image into memory can
+      also be used.
+
+
+4. Recovering SPI-NOR
+---------------------
+
+In case you somehow do not succeed with this procedure you can upload U-Boot
+via USB:
+
+1. Download and install the imx_loader following the instructions provided:
+
+      https://github.com/boundarydevices/imx_usb_loader
+
+2. Connect the board to USB via the USB OTG port.
+
+3. Make sure SW1 switch is at position "01", so that it can boot from USB OTG.
+
+4. Power-up the SabreLite and run the imx_loader to upload the U-Boot image:
+
+      sudo imx_usb u-boot.imx
+
+Note: This will upload and run the U-Boot image in memory, the SPI will not be
+      reprogrammed and this procedure will need to be repeated if the board is
+      reset.
+
+5. Use one of previous descriptions to re-flash the SPI-NOR as required.
+
+6. Ensure SW1 is returned to "00" to boot from the fuses once done.
+
diff --git a/roms/u-boot/board/boundary/nitrogen6x/clocks.cfg b/roms/u-boot/board/boundary/nitrogen6x/clocks.cfg
new file mode 100644
index 000000000..d78e0fdbb
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/clocks.cfg
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/roms/u-boot/board/boundary/nitrogen6x/ddr-setup.cfg b/roms/u-boot/board/boundary/nitrogen6x/ddr-setup.cfg
new file mode 100644
index 000000000..99b449c29
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/ddr-setup.cfg
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 32 bits	x16/x32
+ */
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+
+/*
+ * MDSCR	con_req
+ */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/roms/u-boot/board/boundary/nitrogen6x/nitrogen6dl.cfg b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6dl.cfg
new file mode 100644
index 000000000..9558e26a2
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6dl.cfg
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "800mhz_4x128mx16.cfg"
+#include "clocks.cfg"
diff --git a/roms/u-boot/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
new file mode 100644
index 000000000..f5a107c22
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "800mhz_4x256mx16.cfg"
+#include "clocks.cfg"
diff --git a/roms/u-boot/board/boundary/nitrogen6x/nitrogen6q.cfg b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6q.cfg
new file mode 100644
index 000000000..b0bbf0d79
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6q.cfg
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "1066mhz_4x128mx16.cfg"
+#include "clocks.cfg"
diff --git a/roms/u-boot/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6q2g.cfg
new file mode 100644
index 000000000..499925432
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6q2g.cfg
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "1066mhz_4x256mx16.cfg"
+#include "clocks.cfg"
diff --git a/roms/u-boot/board/boundary/nitrogen6x/nitrogen6s.cfg b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6s.cfg
new file mode 100644
index 000000000..16d778491
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6s.cfg
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "800mhz_2x128mx16.cfg"
+#include "clocks.cfg"
diff --git a/roms/u-boot/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6s1g.cfg
new file mode 100644
index 000000000..0320078a9
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6s1g.cfg
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "800mhz_2x256mx16.cfg"
+#include "clocks.cfg"
diff --git a/roms/u-boot/board/boundary/nitrogen6x/nitrogen6x.c b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6x.c
new file mode 100644
index 000000000..84e14d112
--- /dev/null
+++ b/roms/u-boot/board/boundary/nitrogen6x/nitrogen6x.c
@@ -0,0 +1,1005 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <fsl_esdhc_imx.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <i2c.h>
+#include <input.h>
+#include <netdev.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#define GP_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define RGB_PAD_CTRL	PAD_CTL_DSE_120ohm
+
+#define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_SRE_SLOW)
+
+#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
+
+/* Prevent compiler error if gpio number 08 or 09 is used */
+#define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf)))
+
+#define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,	       \
+		sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) {		       \
+	.scl = {							       \
+		.i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\
+					 pad_ctrl),			       \
+		.gpio_mode = NEW_PAD_CTRL(				       \
+			cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\
+			pad_ctrl),					       \
+		.gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp))		       \
+	},								       \
+	.sda = {							       \
+		.i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\
+					 pad_ctrl),			       \
+		.gpio_mode = NEW_PAD_CTRL(				       \
+			cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\
+			pad_ctrl),					       \
+			.gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp))	       \
+	}								       \
+}
+
+#define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,	       \
+		sda_pad, sda_bank, sda_gp, pad_ctrl)			       \
+		_I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,     \
+				sda_pad, sda_bank, sda_gp, pad_ctrl, _IO)
+
+#if defined(CONFIG_MX6QDL)
+#define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,		\
+		sda_pad, sda_bank, sda_gp, pad_ctrl)			\
+	I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp,	\
+		sda_pad, sda_bank, sda_gp, pad_ctrl),			\
+	I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp,	\
+		sda_pad, sda_bank, sda_gp, pad_ctrl)
+#define I2C_PADS_INFO_ENTRY_SPACING 2
+
+#define IOMUX_PAD_CTRL(name, pad_ctrl) \
+		NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl),	\
+		NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl)
+#else
+#define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,		\
+		sda_pad, sda_bank, sda_gp, pad_ctrl)			\
+	I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp,	\
+		sda_pad, sda_bank, sda_gp, pad_ctrl)
+#define I2C_PADS_INFO_ENTRY_SPACING 1
+
+#define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl)
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+	IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
+};
+
+static struct i2c_pads_info i2c_pads[] = {
+	/* I2C1, SGTL5000 */
+	I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
+	/* I2C2 Camera, MIPI */
+	I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13,
+			    I2C_PAD_CTRL),
+	/* I2C3, J15 - RGB connector */
+	I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
+};
+
+#define I2C_BUS_CNT    3
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads1[] = {
+	IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
+	/* pin 35 - 1 (PHY_AD2) on reset */
+	IOMUX_PAD_CTRL(RGMII_RXC__GPIO6_IO30, NO_PAD_CTRL),
+	/* pin 32 - 1 - (MODE0) all */
+	IOMUX_PAD_CTRL(RGMII_RD0__GPIO6_IO25, NO_PAD_CTRL),
+	/* pin 31 - 1 - (MODE1) all */
+	IOMUX_PAD_CTRL(RGMII_RD1__GPIO6_IO27, NO_PAD_CTRL),
+	/* pin 28 - 1 - (MODE2) all */
+	IOMUX_PAD_CTRL(RGMII_RD2__GPIO6_IO28, NO_PAD_CTRL),
+	/* pin 27 - 1 - (MODE3) all */
+	IOMUX_PAD_CTRL(RGMII_RD3__GPIO6_IO29, NO_PAD_CTRL),
+	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+	IOMUX_PAD_CTRL(RGMII_RX_CTL__GPIO6_IO24, NO_PAD_CTRL),
+	/* pin 42 PHY nRST */
+	IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, NO_PAD_CTRL),
+	IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads2[] = {
+	IOMUX_PAD_CTRL(RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL),
+	IOMUX_PAD_CTRL(RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const misc_pads[] = {
+	IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
+	/* OTG Power enable */
+	IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
+};
+
+/* wl1271 pads on nitrogen6x */
+static iomux_v3_cfg_t const wl12xx_pads[] = {
+	IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
+	IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
+	IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
+};
+#define WL12XX_WL_IRQ_GP	IMX_GPIO_NR(6, 14)
+#define WL12XX_WL_ENABLE_GP	IMX_GPIO_NR(6, 15)
+#define WL12XX_BT_ENABLE_GP	IMX_GPIO_NR(6, 16)
+
+/* Button assignments for J14 */
+static iomux_v3_cfg_t const button_pads[] = {
+	/* Menu */
+	IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
+	/* Back */
+	IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
+	/* Labelled Search (mapped to Power under Android) */
+	IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
+	/* Home */
+	IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
+	/* Volume Down */
+	IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
+	/* Volume Up */
+	IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+	gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
+	gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
+	gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+	SETUP_IOMUX_PADS(enet_pads1);
+	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+
+	/* Need delay 10ms according to KSZ9021 spec */
+	udelay(1000 * 10);
+	gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
+	gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
+
+	SETUP_IOMUX_PADS(enet_pads2);
+	udelay(100);	/* Wait 100 us before using mii interface */
+}
+
+static iomux_v3_cfg_t const usb_pads[] = {
+	IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+	SETUP_IOMUX_PADS(uart2_pads);
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	SETUP_IOMUX_PADS(usb_pads);
+
+	/* Reset USB hub */
+	gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
+	mdelay(2);
+	gpio_set_value(IMX_GPIO_NR(7, 12), 1);
+
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	if (port)
+		return 0;
+	gpio_set_value(GP_USB_OTG_PWR, on);
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
+}
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	/* SS1 */
+	IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, NO_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* min rx data delay */
+	ksz9021_phy_extended_write(phydev,
+			MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
+	/* min tx data delay */
+	ksz9021_phy_extended_write(phydev,
+			MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
+	/* max rx/tx clock delay, min rx/tx control */
+	ksz9021_phy_extended_write(phydev,
+			MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	uint32_t base = IMX_FEC_BASE;
+	struct mii_dev *bus = NULL;
+	struct phy_device *phydev = NULL;
+	int ret;
+
+	gpio_request(WL12XX_WL_IRQ_GP, "wifi_irq");
+	gpio_request(IMX_GPIO_NR(6, 30), "rgmii_rxc");
+	gpio_request(IMX_GPIO_NR(6, 25), "rgmii_rd0");
+	gpio_request(IMX_GPIO_NR(6, 27), "rgmii_rd1");
+	gpio_request(IMX_GPIO_NR(6, 28), "rgmii_rd2");
+	gpio_request(IMX_GPIO_NR(6, 29), "rgmii_rd3");
+	gpio_request(IMX_GPIO_NR(6, 24), "rgmii_rx_ctl");
+	gpio_request(IMX_GPIO_NR(3, 23), "rgmii_reset_sabrelite");
+	gpio_request(IMX_GPIO_NR(1, 27), "rgmii_reset_nitrogen6x");
+	setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+	bus = fec_get_miibus(base, -1);
+	if (!bus)
+		return -EINVAL;
+	/* scan phy 4,5,6,7 */
+	phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+	if (!phydev) {
+		ret = -EINVAL;
+		goto free_bus;
+	}
+	printf("using phy at %d\n", phydev->addr);
+	ret  = fec_probe(bis, -1, base, bus, phydev);
+	if (ret)
+		goto free_phydev;
+#endif
+
+#ifdef CONFIG_CI_UDC
+	/* For otg ethernet*/
+	usb_eth_initialize(bis);
+#endif
+	return 0;
+
+free_phydev:
+	free(phydev);
+free_bus:
+	free(bus);
+	return ret;
+}
+
+static void setup_buttons(void)
+{
+	SETUP_IOMUX_PADS(button_pads);
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+	/* Backlight on RGB connector: J15 */
+	IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, NO_PAD_CTRL),
+#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
+
+	/* Backlight on LVDS connector: J6 */
+	IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, NO_PAD_CTRL),
+#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+	IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+	return ((0 == i2c_set_bus_num(dev->bus))
+		&&
+		(0 == i2c_probe(dev->addr)));
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)
+				IOMUXC_BASE_ADDR;
+	u32 reg = readl(&iomux->gpr[2]);
+	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+	writel(reg, &iomux->gpr[2]);
+	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+}
+
+static void enable_lvds_jeida(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)
+				IOMUXC_BASE_ADDR;
+	u32 reg = readl(&iomux->gpr[2]);
+	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+	     |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
+	writel(reg, &iomux->gpr[2]);
+	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+}
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+	SETUP_IOMUX_PADS(rgb_pads);
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= 1,
+	.addr	= 0x50,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_i2c,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 0,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= NULL,
+	.enable	= enable_lvds_jeida,
+	.mode	= {
+		.name           = "LDB-WXGA",
+		.refresh        = 60,
+		.xres           = 1280,
+		.yres           = 800,
+		.pixclock       = 14065,
+		.left_margin    = 40,
+		.right_margin   = 40,
+		.upper_margin   = 3,
+		.lower_margin   = 80,
+		.hsync_len      = 10,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 0,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= NULL,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "LDB-WXGA-S",
+		.refresh        = 60,
+		.xres           = 1280,
+		.yres           = 800,
+		.pixclock       = 14065,
+		.left_margin    = 40,
+		.right_margin   = 40,
+		.upper_margin   = 3,
+		.lower_margin   = 80,
+		.hsync_len      = 10,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 2,
+	.addr	= 0x4,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.detect	= detect_i2c,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "Hannstar-XGA",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 0,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.detect	= NULL,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "LG-9.7",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385, /* ~65MHz */
+		.left_margin    = 480,
+		.right_margin   = 260,
+		.upper_margin   = 16,
+		.lower_margin   = 6,
+		.hsync_len      = 250,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 2,
+	.addr	= 0x38,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.detect	= detect_i2c,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "wsvga-lvds",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 600,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 2,
+	.addr	= 0x10,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= detect_i2c,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "fusion7",
+		.refresh        = 60,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 33898,
+		.left_margin    = 96,
+		.right_margin   = 24,
+		.upper_margin   = 3,
+		.lower_margin   = 10,
+		.hsync_len      = 72,
+		.vsync_len      = 7,
+		.sync           = 0x40000002,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 0,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= NULL,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "svga",
+		.refresh        = 60,
+		.xres           = 800,
+		.yres           = 600,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 2,
+	.addr	= 0x41,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.detect	= detect_i2c,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "amp1024x600",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 600,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 0,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.detect	= 0,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "wvga-lvds",
+		.refresh        = 57,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 2,
+	.addr	= 0x48,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= detect_i2c,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "wvga-rgb",
+		.refresh        = 57,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 37037,
+		.left_margin    = 40,
+		.right_margin   = 60,
+		.upper_margin   = 10,
+		.lower_margin   = 10,
+		.hsync_len      = 20,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 0,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= NULL,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "qvga",
+		.refresh        = 60,
+		.xres           = 320,
+		.yres           = 240,
+		.pixclock       = 37037,
+		.left_margin    = 38,
+		.right_margin   = 37,
+		.upper_margin   = 16,
+		.lower_margin   = 15,
+		.hsync_len      = 30,
+		.vsync_len      = 3,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+int board_cfb_skip(void)
+{
+	return NULL != env_get("novideo");
+}
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+	/* Turn on LDB0,IPU,IPU DI0 clocks */
+	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+	      |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	     |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+	     |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+	     |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+	     |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+			|IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+
+	/* backlights off until needed */
+	SETUP_IOMUX_PADS(backlight_pads);
+	gpio_direction_input(LVDS_BACKLIGHT_GP);
+	gpio_direction_input(RGB_BACKLIGHT_GP);
+}
+#endif
+
+static iomux_v3_cfg_t const init_pads[] = {
+	/* SGTL5000 sys_mclk */
+	IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
+
+	/* J5 - Camera MCLK */
+	IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
+
+	/* wl1271 pads on nitrogen6x */
+	/* WL12XX_WL_IRQ_GP */
+	IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
+	/* WL12XX_WL_ENABLE_GP */
+	IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
+	/* WL12XX_BT_ENABLE_GP */
+	IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
+	/* USB otg power */
+	IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
+	IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
+	IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
+	IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
+	IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
+};
+
+#define WL12XX_WL_IRQ_GP	IMX_GPIO_NR(6, 14)
+
+static unsigned gpios_out_low[] = {
+	/* Disable wl1271 */
+	IMX_GPIO_NR(6, 15),	/* disable wireless */
+	IMX_GPIO_NR(6, 16),	/* disable bluetooth */
+	IMX_GPIO_NR(3, 22),	/* disable USB otg power */
+	IMX_GPIO_NR(2, 5),	/* ov5640 mipi camera reset */
+	IMX_GPIO_NR(1, 8),	/* ov5642 reset */
+};
+
+static unsigned gpios_out_high[] = {
+	IMX_GPIO_NR(1, 6),	/* ov5642 powerdown */
+	IMX_GPIO_NR(6, 9),	/* ov5640 mipi camera power down */
+};
+
+static void set_gpios(unsigned *p, int cnt, int val)
+{
+	int i;
+
+	for (i = 0; i < cnt; i++)
+		gpio_direction_output(*p++, val);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
+	set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
+	gpio_direction_input(WL12XX_WL_IRQ_GP);
+
+	SETUP_IOMUX_PADS(wl12xx_pads);
+	SETUP_IOMUX_PADS(init_pads);
+	setup_buttons();
+
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	struct i2c_pads_info *p = i2c_pads;
+	int i;
+	int stride = 1;
+
+#if defined(CONFIG_MX6QDL)
+	stride = 2;
+	if (!is_mx6dq() && !is_mx6dqp())
+		p += 1;
+#endif
+	clrsetbits_le32(&iomuxc_regs->gpr[1],
+			IOMUXC_GPR1_OTG_ID_MASK,
+			IOMUXC_GPR1_OTG_ID_GPIO1);
+
+	SETUP_IOMUX_PADS(misc_pads);
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
+	SETUP_IOMUX_PADS(usdhc2_pads);
+	for (i = 0; i < I2C_BUS_CNT; i++) {
+		setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p);
+		p += stride;
+	}
+
+#ifdef CONFIG_SATA
+	setup_sata();
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	int ret = gpio_get_value(WL12XX_WL_IRQ_GP);
+
+	if (ret < 0) {
+		/* The gpios have not been probed yet. Read it myself */
+		struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR;
+		int gpio = WL12XX_WL_IRQ_GP & 0x1f;
+
+		ret = (readl(&regs->gpio_psr) >> gpio) & 0x01;
+	}
+	if (ret)
+		puts("Board: Nitrogen6X\n");
+	else
+		puts("Board: SABRE Lite\n");
+
+	return 0;
+}
+
+struct button_key {
+	char const	*name;
+	unsigned	gpnum;
+	char		ident;
+};
+
+static struct button_key const buttons[] = {
+	{"back",	IMX_GPIO_NR(2, 2),	'B'},
+	{"home",	IMX_GPIO_NR(2, 4),	'H'},
+	{"menu",	IMX_GPIO_NR(2, 1),	'M'},
+	{"search",	IMX_GPIO_NR(2, 3),	'S'},
+	{"volup",	IMX_GPIO_NR(7, 13),	'V'},
+	{"voldown",	IMX_GPIO_NR(4, 5),	'v'},
+};
+
+/*
+ * generate a null-terminated string containing the buttons pressed
+ * returns number of keys pressed
+ */
+static int read_keys(char *buf)
+{
+	int i, numpressed = 0;
+	for (i = 0; i < ARRAY_SIZE(buttons); i++) {
+		if (!gpio_get_value(buttons[i].gpnum))
+			buf[numpressed++] = buttons[i].ident;
+	}
+	buf[numpressed] = '\0';
+	return numpressed;
+}
+
+static int do_kbd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	char envvalue[ARRAY_SIZE(buttons)+1];
+	int numpressed = read_keys(envvalue);
+	env_set("keybd", envvalue);
+	return numpressed == 0;
+}
+
+U_BOOT_CMD(
+	kbd, 1, 1, do_kbd,
+	"Tests for keypresses, sets 'keybd' environment variable",
+	"Returns 0 (true) to shell if key is pressed."
+);
+
+#ifdef CONFIG_PREBOOT
+static char const kbd_magic_prefix[] = "key_magic";
+static char const kbd_command_prefix[] = "key_cmd";
+
+static void preboot_keys(void)
+{
+	int numpressed;
+	char keypress[ARRAY_SIZE(buttons)+1];
+	numpressed = read_keys(keypress);
+	if (numpressed) {
+		char *kbd_magic_keys = env_get("magic_keys");
+		char *suffix;
+		/*
+		 * loop over all magic keys
+		 */
+		for (suffix = kbd_magic_keys; *suffix; ++suffix) {
+			char *keys;
+			char magic[sizeof(kbd_magic_prefix) + 1];
+			sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
+			keys = env_get(magic);
+			if (keys) {
+				if (!strcmp(keys, keypress))
+					break;
+			}
+		}
+		if (*suffix) {
+			char cmd_name[sizeof(kbd_command_prefix) + 1];
+			char *cmd;
+			sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
+			cmd = env_get(cmd_name);
+			if (cmd) {
+				env_set("preboot", cmd);
+				return;
+			}
+		}
+	}
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{"mmc1",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{NULL,		0},
+};
+#endif
+
+int misc_init_r(void)
+{
+	gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
+	gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
+	gpio_request(GP_USB_OTG_PWR, "usbotg power");
+	gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
+	gpio_request(IMX_GPIO_NR(2, 2), "back");
+	gpio_request(IMX_GPIO_NR(2, 4), "home");
+	gpio_request(IMX_GPIO_NR(2, 1), "menu");
+	gpio_request(IMX_GPIO_NR(2, 3), "search");
+	gpio_request(IMX_GPIO_NR(7, 13), "volup");
+	gpio_request(IMX_GPIO_NR(4, 5), "voldown");
+#ifdef CONFIG_PREBOOT
+	preboot_keys();
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	env_set_hex("reset_cause", get_imx_reset_cause());
+	return 0;
+}
diff --git a/roms/u-boot/board/broadcom/bcm11130/MAINTAINERS b/roms/u-boot/board/broadcom/bcm11130/MAINTAINERS
new file mode 100644
index 000000000..54783501e
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm11130/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM11130 BOARD
+M:	Steve Rae <steve.rae@raedomain.com>
+S:	Maintained
+F:	board/broadcom/bcm28155_ap/
+F:	include/configs/bcm_ep_board.h
+F:	configs/bcm11130_defconfig
diff --git a/roms/u-boot/board/broadcom/bcm11130_nand/MAINTAINERS b/roms/u-boot/board/broadcom/bcm11130_nand/MAINTAINERS
new file mode 100644
index 000000000..4cf66b7e4
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm11130_nand/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM11130_NAND BOARD
+M:	Steve Rae <steve.rae@raedomain.com>
+S:	Maintained
+F:	board/broadcom/bcm28155_ap/
+F:	include/configs/bcm_ep_board.h
+F:	configs/bcm11130_nand_defconfig
diff --git a/roms/u-boot/board/broadcom/bcm28155_w1d/MAINTAINERS b/roms/u-boot/board/broadcom/bcm28155_w1d/MAINTAINERS
new file mode 100644
index 000000000..c0558e7f2
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm28155_w1d/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM28155_W1D BOARD
+M:	Steve Rae <steve.rae@raedomain.com>
+S:	Maintained
+F:	board/broadcom/bcm28155_ap/
+F:	include/configs/bcm28155_ap.h
+F:	configs/bcm28155_w1d_defconfig
diff --git a/roms/u-boot/board/broadcom/bcm963158/Kconfig b/roms/u-boot/board/broadcom/bcm963158/Kconfig
new file mode 100644
index 000000000..08a8bc1c1
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm963158/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_BCM963158
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_BOARD
+	default "bcm963158"
+
+config SYS_CONFIG_NAME
+	default "broadcom_bcm963158"
+
+endif
+
+config TARGET_BCM963158
+	bool "Support Broadcom bcm963158"
+	depends on ARCH_BCM63158
+	select ARM64
diff --git a/roms/u-boot/board/broadcom/bcm963158/MAINTAINERS b/roms/u-boot/board/broadcom/bcm963158/MAINTAINERS
new file mode 100644
index 000000000..d28d971f9
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm963158/MAINTAINERS
@@ -0,0 +1,6 @@
+BROADCOM BCM963158
+M:	Philippe Reynes <philippe.reynes@softathome.com>
+S:	Maintained
+F:	board/broadcom/bcm963158/
+F:	include/configs/broadcom_bcm963158.h
+F:	configs/bcm963158_ram_defconfig
diff --git a/roms/u-boot/board/broadcom/bcm963158/Makefile b/roms/u-boot/board/broadcom/bcm963158/Makefile
new file mode 100644
index 000000000..0a902c9cf
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm963158/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	+= bcm963158.o
diff --git a/roms/u-boot/board/broadcom/bcm963158/bcm963158.c b/roms/u-boot/board/broadcom/bcm963158/bcm963158.c
new file mode 100644
index 000000000..9feaee3c0
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm963158/bcm963158.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/io.h>
+
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+
+static struct mm_region broadcom_bcm963158_mem_map[] = {
+	{
+		/* RAM */
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 8UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* SoC */
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm963158_mem_map;
+#endif
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		printf("fdtdec_setup_mem_size_base() has failed\n");
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/board/broadcom/bcm968360bg/Kconfig b/roms/u-boot/board/broadcom/bcm968360bg/Kconfig
new file mode 100644
index 000000000..dd372f126
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968360bg/Kconfig
@@ -0,0 +1,17 @@
+if ARCH_BCM68360
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_BOARD
+	default "bcm968360bg"
+
+config SYS_CONFIG_NAME
+	default "broadcom_bcm968360bg"
+
+endif
+
+config TARGET_BCM968360BG
+	bool "Support Broadcom bcm968360bg"
+	depends on ARCH_BCM68360
+	select ARM64
diff --git a/roms/u-boot/board/broadcom/bcm968360bg/MAINTAINERS b/roms/u-boot/board/broadcom/bcm968360bg/MAINTAINERS
new file mode 100644
index 000000000..cfcbbc51f
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968360bg/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM968360BG BOARD
+M:	Philippe Reynes <philippe.reynes@softathome.com>
+S:	Maintained
+F:	board/broadcom/bcm968360bg
+F:	include/configs/broadcom_bcm968360bg.h
+F:	configs/bcm968360bg_ram_defconfig
diff --git a/roms/u-boot/board/broadcom/bcm968360bg/Makefile b/roms/u-boot/board/broadcom/bcm968360bg/Makefile
new file mode 100644
index 000000000..d099c1cf3
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968360bg/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	+= bcm968360bg.o
diff --git a/roms/u-boot/board/broadcom/bcm968360bg/bcm968360bg.c b/roms/u-boot/board/broadcom/bcm968360bg/bcm968360bg.c
new file mode 100644
index 000000000..90af6b88b
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968360bg/bcm968360bg.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/io.h>
+
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+
+static struct mm_region broadcom_bcm968360bg_mem_map[] = {
+	{
+		/* RAM */
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 8UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* SoC */
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm968360bg_mem_map;
+#endif
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		printf("fdtdec_setup_mem_size_base() has failed\n");
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/board/broadcom/bcm968380gerg/Kconfig b/roms/u-boot/board/broadcom/bcm968380gerg/Kconfig
new file mode 100644
index 000000000..c33e25d1a
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968380gerg/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_BROADCOM_BCM968380GERG
+
+config SYS_BOARD
+	default "bcm968380gerg"
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_CONFIG_NAME
+	default "broadcom_bcm968380gerg"
+
+endif
diff --git a/roms/u-boot/board/broadcom/bcm968380gerg/MAINTAINERS b/roms/u-boot/board/broadcom/bcm968380gerg/MAINTAINERS
new file mode 100644
index 000000000..52747cd9e
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968380gerg/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM968380GERG BOARD
+M:	Philippe Reynes <philippe.reynes@softathome.com>
+S:	Maintained
+F:	board/broadcom/bcm968380gerg/
+F:	include/configs/broadcom_bcm968380gerg.h
+F:	configs/bcm968380gerg_ram_defconfig
diff --git a/roms/u-boot/board/broadcom/bcm968380gerg/Makefile b/roms/u-boot/board/broadcom/bcm968380gerg/Makefile
new file mode 100644
index 000000000..a525b7b9b
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968380gerg/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += bcm968380gerg.o
diff --git a/roms/u-boot/board/broadcom/bcm968380gerg/bcm968380gerg.c b/roms/u-boot/board/broadcom/bcm968380gerg/bcm968380gerg.c
new file mode 100644
index 000000000..044b3554b
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968380gerg/bcm968380gerg.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/broadcom/bcm968380gerg/board.c b/roms/u-boot/board/broadcom/bcm968380gerg/board.c
new file mode 100644
index 000000000..044b3554b
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968380gerg/board.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/broadcom/bcm968580xref/Kconfig b/roms/u-boot/board/broadcom/bcm968580xref/Kconfig
new file mode 100644
index 000000000..b5730367a
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968580xref/Kconfig
@@ -0,0 +1,17 @@
+if ARCH_BCM6858
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_BOARD
+	default "bcm968580xref"
+
+config SYS_CONFIG_NAME
+	default "broadcom_bcm968580xref"
+
+endif
+
+config TARGET_BCM968580XREF
+	bool "Support Broadcom bcm968580xref"
+	depends on ARCH_BCM6858
+	select ARM64
diff --git a/roms/u-boot/board/broadcom/bcm968580xref/MAINTAINERS b/roms/u-boot/board/broadcom/bcm968580xref/MAINTAINERS
new file mode 100644
index 000000000..5ee0c4dd4
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968580xref/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM968580XREF BOARD
+M:	Philippe Reynes <philippe.reynes@softathome.com>
+S:	Maintained
+F:	board/broadcom/bcm968580xref/
+F:	include/configs/broadcom_bcm968580xref.h
+F:	configs/bcm968580xref_ram_defconfig
diff --git a/roms/u-boot/board/broadcom/bcm968580xref/Makefile b/roms/u-boot/board/broadcom/bcm968580xref/Makefile
new file mode 100644
index 000000000..5cd393b19
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968580xref/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	+= bcm968580xref.o
diff --git a/roms/u-boot/board/broadcom/bcm968580xref/bcm968580xref.c b/roms/u-boot/board/broadcom/bcm968580xref/bcm968580xref.c
new file mode 100644
index 000000000..1bd723d49
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm968580xref/bcm968580xref.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/io.h>
+
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+
+static struct mm_region broadcom_bcm968580xref_mem_map[] = {
+	{
+		/* RAM */
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 8UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* SoC */
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm968580xref_mem_map;
+#endif
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		printf("fdtdec_setup_mem_size_base() has failed\n");
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/board/broadcom/bcm_ep/Makefile b/roms/u-boot/board/broadcom/bcm_ep/Makefile
new file mode 100644
index 000000000..29a3ea7ed
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm_ep/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2014 Broadcom Corporation.
+
+obj-y	+= board.o
diff --git a/roms/u-boot/board/broadcom/bcm_ep/board.c b/roms/u-boot/board/broadcom/bcm_ep/board.c
new file mode 100644
index 000000000..6064eb43d
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcm_ep/board.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <net.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <config.h>
+#include <netdev.h>
+#include <asm/system.h>
+#include <asm/iproc-common/armpll.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * board_init - early hardware init
+ */
+int board_init(void)
+{
+	/*
+	 * Address of boot parameters passed to kernel
+	 * Use default offset 0x100
+	 */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+/*
+ * dram_init - sets u-boot's idea of sdram size
+ */
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	uint32_t status = 0;
+
+	/* Setup PLL if required */
+#if defined(CONFIG_ARMCLK)
+	armpll_config(CONFIG_ARMCLK);
+#endif
+
+	return status;
+}
+
+#ifdef CONFIG_ARMV7_NONSEC
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+}
+
+void smp_kick_all_cpus(void)
+{
+}
+
+void smp_waitloop(unsigned previous_address)
+{
+}
+#endif
+
+#ifdef CONFIG_BCM_SF2_ETH
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = -1;
+	printf("Registering BCM sf2 eth\n");
+	rc = bcm_sf2_eth_register(bis, 0);
+	return rc;
+}
+#endif
diff --git a/roms/u-boot/board/broadcom/bcmns3/Kconfig b/roms/u-boot/board/broadcom/bcmns3/Kconfig
new file mode 100644
index 000000000..cb73f98ea
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcmns3/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_BCMNS3
+
+config SYS_BOARD
+	default "bcmns3"
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_SOC
+	default "bcmns3"
+
+config SYS_CONFIG_NAME
+	default "bcm_ns3"
+
+config CMD_BCM_EXT_UTILS
+	bool "Enable Broadcom-specific U-Boot commands"
+	default y
+	help
+	  Enable Broadcom specific U-Boot commands such as error log setup
+	  command or any other commands specific to NS3 platform.
+
+endif
diff --git a/roms/u-boot/board/broadcom/bcmns3/Makefile b/roms/u-boot/board/broadcom/bcmns3/Makefile
new file mode 100644
index 000000000..340426014
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcmns3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 Broadcom.
+
+obj-y	:= ns3.o
diff --git a/roms/u-boot/board/broadcom/bcmns3/fit/keys/dev.crt b/roms/u-boot/board/broadcom/bcmns3/fit/keys/dev.crt
new file mode 100644
index 000000000..75b75db95
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcmns3/fit/keys/dev.crt
@@ -0,0 +1,21 @@
+-----BEGIN CERTIFICATE-----
+MIIDXTCCAkWgAwIBAgIJAJgq/5aiJttEMA0GCSqGSIb3DQEBCwUAMEUxCzAJBgNV
+BAYTAkFVMRMwEQYDVQQIDApTb21lLVN0YXRlMSEwHwYDVQQKDBhJbnRlcm5ldCBX
+aWRnaXRzIFB0eSBMdGQwHhcNMTgwOTE5MDkzMzEwWhcNMTgxMDE5MDkzMzEwWjBF
+MQswCQYDVQQGEwJBVTETMBEGA1UECAwKU29tZS1TdGF0ZTEhMB8GA1UECgwYSW50
+ZXJuZXQgV2lkZ2l0cyBQdHkgTHRkMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIB
+CgKCAQEAzeMQ92YqrejtMCfxjDyHvDW34ATozXSlWsudR+AyCSuJVAIoHEenVh+/
+PuT0+/EMiwsUnLXYBeOsIXDW3k3eHgm88ccb+0g9J6mlHqMaN0tXP+Ua2GFEk2Wv
+5Bj5QynorOPoaWL/ecWus2Bvkmyt2pvIpaTjmkUKZ9al3z8WyS6wFlFitXyOWFcK
+7Xkl43cOHxYAfbny5loWYDCgpkV+dgYZOoCEmL+Y9HfrQ+uBKGducpzNKeQjX9bn
+UT9cleCtHZx0uY4wSGNgfmUMy7oUyVZhFpmjlcfjcfNFcBcoVF6StluoL6v1KRbH
+4xJDD/UCn2Uk0S6Zpd7TRc26faOtfwIDAQABo1AwTjAdBgNVHQ4EFgQUZk/KKaWG
+p4BtksPdQ8FLzWL/gAIwHwYDVR0jBBgwFoAUZk/KKaWGp4BtksPdQ8FLzWL/gAIw
+DAYDVR0TBAUwAwEB/zANBgkqhkiG9w0BAQsFAAOCAQEAPNveTvOC2bw91cUN1e+B
+95qFp2Xd5XGiV35F10dT3VN/Iv2dzHlThq7xaJGkA53lHIXgLUUfnDTHJmoluw+t
+UCpG8OWCxM0FbT8ZnXR4SmHK8k4yb7iZa7iu+Ey5B6F3247gJpEl+1iYxus0lqQW
+E9dTwMf1YP9Jdf+dRoLKAAI0n5J1PMuseQkGdlRBNUcEg+kXqBSz5hq0xkuPRtey
+GiAvpg3G93ft84Q4ov7IjAhJkY7whm6WktisU8mFPru3e9EouxjVtAvu6s9gQThm
+pvn6hSL2/3gEOP3v9yBsH6//SOgNdVBGZIdX+HkvD8NZLftbIrDaeL/IfKUm/zXB
+zA==
+-----END CERTIFICATE-----
diff --git a/roms/u-boot/board/broadcom/bcmns3/fit/keys/dev.key b/roms/u-boot/board/broadcom/bcmns3/fit/keys/dev.key
new file mode 100644
index 000000000..55b7033e9
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcmns3/fit/keys/dev.key
@@ -0,0 +1,28 @@
+-----BEGIN PRIVATE KEY-----
+MIIEvwIBADANBgkqhkiG9w0BAQEFAASCBKkwggSlAgEAAoIBAQDN4xD3Ziqt6O0w
+J/GMPIe8NbfgBOjNdKVay51H4DIJK4lUAigcR6dWH78+5PT78QyLCxSctdgF46wh
+cNbeTd4eCbzxxxv7SD0nqaUeoxo3S1c/5RrYYUSTZa/kGPlDKeis4+hpYv95xa6z
+YG+SbK3am8ilpOOaRQpn1qXfPxbJLrAWUWK1fI5YVwrteSXjdw4fFgB9ufLmWhZg
+MKCmRX52Bhk6gISYv5j0d+tD64EoZ25ynM0p5CNf1udRP1yV4K0dnHS5jjBIY2B+
+ZQzLuhTJVmEWmaOVx+Nx80VwFyhUXpK2W6gvq/UpFsfjEkMP9QKfZSTRLpml3tNF
+zbp9o61/AgMBAAECggEBAJ/TZClZk0ob5nyalWVS29/cJ5hs1zgfE/nu1HKmdNEv
+jdS8M9z4Nsuhq3msjQ1Da4RInsCkXUT9H3N6QCKkeggBcT6TXYJs6qRuijLFVKWW
+A+4i8PsGTxDJQIimZmGgF/KWnaWp5z7lmZ+//fzCBxgMFO+Zl+H7NH+1XmB2fj6/
+bfgnxLbiIqq/2oVJfdjA1Zs2ie3SE5U2hPNiE6TIajFS0PxUOGrojsSQ8z+gfqs3
+hyqo9msAqNQciT79vyXp+3HsxZo9rq5Tk5OtCEfgu0GED/d4/FHbDrZT3TorVYXr
+Z3dADxvnnJfBdlQIMetCy/X8z2vKRRXaoWpqg1aiFVECgYEA7Ap5D4nvOie2NXgI
+gMPzuYtpH4uF/cZMLGxTKZ3NG4RH6oVUdd4whETXfzBJdnJbIXDTphoHxjUhpGh8
+Ga+U1iqjp9c6Nd8ueVp/c5T1bD8/2RG0QM4iWgPbZDKtj1MqRg7vwAfpJ3kOIc/5
+bKJ4jAopNJMChL6vAZ9+ShPsRqkCgYEA30vbj6K7/giclJnyWkluQTqS8X/XjdAf
+F5PkCBHGJnYxkDSzWPq7O5E1wYqTAou1U6nNNoUvZZdpRvo39NSrMCaagQ7GE+xA
+j/h7tinD/lPlvoW9N4f4ddqWzsmf7I8OGZtP4IwVi9Pms+zPtrQ7TvuPT4UHTH2E
+eE1hlJtic+cCgYEA6oKdNGr+WvEJfqX7DLOiej2f+89LGI7jL1+QYFB/b09FhCNj
+fpd57G/ZCmyXEC8di2PlY6mI/8vZ2NZWNc7UONO0NRUIqG1MZxUae2MLUrikXq3Q
+QHKMfpJGbo5LEZK29VPxrwAtDSKgf8d5MA1bZwbRWYKVhf1NMnebqU2R+cECgYEA
+kOTKXhP85MR1xj928XtAnfcCLs8D8jOgWU5P46SU7ZQ4aRipYA2ivO5m8WWYK0i4
+qsc+MCiQLt3nJHVtJeNyCdai3yfVBEyDQGi+7d+AHGIYbF6f/46tfNwQi7JtobTa
+M2eCl3SO7qLbytjZl/avnXrC7Zimuc2gzed4cFO7uPUCgYAo66MLtRWLdHqPDTaa
+WhSQZkdKfZxlWNP6XIpBgHnYDIQGZddrjv+zZVFRxLCduh1v8xybbSDKwRkGuXVb
+eTQHP2Nc5XsOopCSsDP0v0dUxaOu14C0jJJG2E+EhJsWJ2Eua7o40LEIX2WY7N7f
+UqR3bLO5Qh/1OOwJj5WbpzkMwA==
+-----END PRIVATE KEY-----
diff --git a/roms/u-boot/board/broadcom/bcmns3/fit/multi.its b/roms/u-boot/board/broadcom/bcmns3/fit/multi.its
new file mode 100644
index 000000000..a0ff4bc90
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcmns3/fit/multi.its
@@ -0,0 +1,59 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ */
+
+/dts-v1/;
+
+/ {
+	description = "Various kernels, ramdisks and FDT blobs";
+	#address-cells = <1>;
+
+	images {
+		kernel {
+			description = "Linux kernel Image";
+			data = /incbin/("./Image");
+			type = "kernel";
+			arch = "arm64";
+			os = "linux";
+			compression = "none";
+			load = <0x80080000>;
+			entry = <0x80080000>;
+			hash-1 {
+				algo = "sha1";
+			};
+			signature {
+				algo = "sha1,rsa2048";
+				key-name-hint = "dev";
+			};
+		};
+
+		fdt-ns3 {
+			description = "FDT Blob";
+			data = /incbin/("./dt-blob.bin");
+			type = "flat_dt";
+			arch = "arm64";
+			compression = "none";
+			hash-1 {
+				algo = "sha1";
+			};
+			signature {
+				algo = "sha1,rsa2048";
+				key-name-hint = "dev";
+			};
+		};
+	};
+
+	configurations {
+		default = "config-ns3";
+		config-ns3 {
+			description = "FIT1 configuration";
+			kernel = "kernel";
+			fdt = "fdt-ns3";
+			signature {
+				algo = "sha1,rsa2048";
+				key-name-hint = "dev";
+				sign-images = "fdt", "kernel";
+			};
+		};
+	};
+};
diff --git a/roms/u-boot/board/broadcom/bcmns3/ns3.c b/roms/u-boot/board/broadcom/bcmns3/ns3.c
new file mode 100644
index 000000000..758a358f5
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcmns3/ns3.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Broadcom.
+ *
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/gic-v3.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+#include <asm/arch-bcmns3/bl33_info.h>
+#include <dt-bindings/memory/bcm-ns3-mc.h>
+#include <broadcom/chimp.h>
+
+#define BANK_OFFSET(bank)      ((u64)BCM_NS3_DDR_INFO_BASE + 8 + ((bank) * 16))
+
+/*
+ * ns3_dram_bank - DDR bank details
+ *
+ * @start: DDR bank start address
+ * @len: DDR bank length
+ */
+struct ns3_dram_bank {
+	u64 start[BCM_NS3_MAX_NR_BANKS];
+	u64 len[BCM_NS3_MAX_NR_BANKS];
+};
+
+/*
+ * ns3_dram_hdr - DDR header info
+ *
+ * @sig: DDR info signature
+ * @bank: DDR bank details
+ */
+struct ns3_dram_hdr {
+	u32 sig;
+	struct ns3_dram_bank bank;
+};
+
+static struct mm_region ns3_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = BCM_NS3_MEM_START,
+		.phys = BCM_NS3_MEM_START,
+		.size = BCM_NS3_MEM_LEN,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = BCM_NS3_BANK_1_MEM_START,
+		.phys = BCM_NS3_BANK_1_MEM_START,
+		.size = BCM_NS3_BANK_1_MEM_LEN,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = ns3_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Force the bl33_info to the data-section, as .bss will not be valid
+ * when save_boot_params is invoked.
+ */
+struct bl33_info *bl33_info __section(".data");
+
+/*
+ * Run modulo 256 checksum calculation and return the calculated checksum
+ */
+static u8 checksum_calc(u8 *p, unsigned int len)
+{
+	unsigned int i;
+	u8 chksum = 0;
+
+	for (i = 0; i < len; i++)
+		chksum += p[i];
+
+	return chksum;
+}
+
+/*
+ * This function parses the memory layout information from a reserved area in
+ * DDR, and then fix up the FDT before passing it to Linux.
+ *
+ * In the case of error, do nothing and the default memory layout in DT will
+ * be used
+ */
+static int mem_info_parse_fixup(void *fdt)
+{
+	struct ns3_dram_hdr hdr;
+	u32 *p32, i, nr_banks;
+	u64 *p64;
+
+	/* validate signature */
+	p32 = (u32 *)BCM_NS3_DDR_INFO_BASE;
+	hdr.sig = *p32;
+	if (hdr.sig != BCM_NS3_DDR_INFO_SIG) {
+		printf("DDR info signature 0x%x invalid\n", hdr.sig);
+		return -EINVAL;
+	}
+
+	/* run checksum test to validate data  */
+	if (checksum_calc((u8 *)p32, BCM_NS3_DDR_INFO_LEN) != 0) {
+		printf("Checksum on DDR info failed\n");
+		return -EINVAL;
+	}
+
+	/* parse information for each bank */
+	nr_banks = 0;
+	for (i = 0; i < BCM_NS3_MAX_NR_BANKS; i++) {
+		/* skip banks with a length of zero */
+		p64 = (u64 *)BANK_OFFSET(i);
+		if (*(p64 + 1) == 0)
+			continue;
+
+		hdr.bank.start[i] = *p64;
+		hdr.bank.len[i] = *(p64 + 1);
+
+		printf("mem[%u] 0x%llx - 0x%llx\n", i, hdr.bank.start[i],
+		       hdr.bank.start[i] + hdr.bank.len[i] - 1);
+		nr_banks++;
+	}
+
+	if (!nr_banks) {
+		printf("No DDR banks detected\n");
+		return -ENOMEM;
+	}
+
+	return fdt_fixup_memory_banks(fdt, hdr.bank.start, hdr.bank.len,
+				      nr_banks);
+}
+
+int board_init(void)
+{
+	/* Setup memory using "memory" node from DTB */
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+	fdtdec_setup_memory_banksize();
+
+	if (bl33_info->version != BL33_INFO_VERSION)
+		printf("*** warning: ATF BL31 and U-Boot not in sync! ***\n");
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	/*
+	 * Mark ram base as the last 16MB of 2GB DDR, which is 0xFF00_0000.
+	 * So that relocation happens with in the last 16MB memory.
+	 */
+	gd->ram_base = (phys_size_t)(BCM_NS3_MEM_END - SZ_16M);
+	gd->ram_size = (unsigned long)SZ_16M;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
+	gd->bd->bi_dram[0].size = SZ_16M;
+
+	return 0;
+}
+
+/* Limit RAM used by U-Boot to the DDR first bank End region */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	return BCM_NS3_MEM_END;
+}
+
+void reset_cpu(void)
+{
+	/* Perform a level 3 reset */
+	psci_system_reset2(3, 0);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *fdt, struct bd_info *bd)
+{
+	u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT;
+
+	gic_lpi_tables_init();
+
+	/*
+	 * Check for chimp handshake status.
+	 * Zero timeout value will actually fall to default timeout.
+	 *
+	 * System boot is independent of chimp handshake.
+	 * chimp handshake failure is not a catastrophic error.
+	 * Hence continue booting if chimp handshake fails.
+	 */
+	chimp_handshake_status_optee(0, &chimp_hs);
+	if (chimp_hs == CHIMP_HANDSHAKE_SUCCESS)
+		printf("ChiMP handshake successful\n");
+	else
+		printf("ERROR: ChiMP handshake status 0x%x\n", chimp_hs);
+
+	return mem_info_parse_fixup(fdt);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/roms/u-boot/board/broadcom/bcmstb/MAINTAINERS b/roms/u-boot/board/broadcom/bcmstb/MAINTAINERS
new file mode 100644
index 000000000..eda29b95c
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcmstb/MAINTAINERS
@@ -0,0 +1,15 @@
+BCM7445 BOARD
+M:	Thomas Fitzsimmons <fitzsim@fitzsim.org>
+S:	Maintained
+F:	board/broadcom/bcmstb/
+F:	include/configs/bcmstb.h
+F:	include/configs/bcm7445.h
+F:	configs/bcm7445_defconfig
+
+BCM7260 BOARD
+M:	Thomas Fitzsimmons <fitzsim@fitzsim.org>
+S:	Maintained
+F:	board/broadcom/bcmstb/
+F:	include/configs/bcmstb.h
+F:	include/configs/bcm7260.h
+F:	configs/bcm7260_defconfig
diff --git a/roms/u-boot/board/broadcom/bcmstb/Makefile b/roms/u-boot/board/broadcom/bcmstb/Makefile
new file mode 100644
index 000000000..960988776
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcmstb/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2018  Cisco Systems, Inc.
+#
+# Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
+#
+
+obj-y	:= bcmstb.o
diff --git a/roms/u-boot/board/broadcom/bcmstb/bcmstb.c b/roms/u-boot/board/broadcom/bcmstb/bcmstb.c
new file mode 100644
index 000000000..076ac9414
--- /dev/null
+++ b/roms/u-boot/board/broadcom/bcmstb/bcmstb.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018  Cisco Systems, Inc.
+ * (C) Copyright 2019  Synamedia
+ *
+ * Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
+ */
+
+#include <cpu_func.h>
+#include <init.h>
+#include <log.h>
+#include <time.h>
+#include <asm/global_data.h>
+#include <linux/types.h>
+#include <common.h>
+#include <env.h>
+#include <asm/io.h>
+#include <asm/bootm.h>
+#include <mach/timer.h>
+#include <mmc.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BCMSTB_DATA_SECTION __section(".data")
+
+struct bcmstb_boot_parameters bcmstb_boot_parameters BCMSTB_DATA_SECTION;
+
+phys_addr_t prior_stage_fdt_address BCMSTB_DATA_SECTION;
+
+union reg_value_union {
+	const char *data;
+	const phys_addr_t *address;
+};
+
+int board_init(void)
+{
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+void reset_cpu(void)
+{
+}
+
+int print_cpuinfo(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	/*
+	 * On this SoC, U-Boot is running as an ELF file.  Change the
+	 * relocation address to CONFIG_SYS_TEXT_BASE, so that in
+	 * setup_reloc, gd->reloc_off works out to 0, effectively
+	 * disabling relocation.  Otherwise U-Boot hangs in the setup
+	 * instructions just before relocate_code in
+	 * arch/arm/lib/crt0.S.
+	 */
+	gd->relocaddr = CONFIG_SYS_TEXT_BASE;
+
+	return 0;
+}
+
+void enable_caches(void)
+{
+	/*
+	 * This port assumes that the prior stage bootloader has
+	 * enabled I-cache and D-cache already.  Implementing this
+	 * function silences the warning in the default function.
+	 */
+}
+
+int timer_init(void)
+{
+	gd->arch.timer_rate_hz = readl(BCMSTB_TIMER_FREQUENCY);
+
+	return 0;
+}
+
+ulong get_tbclk(void)
+{
+	return gd->arch.timer_rate_hz;
+}
+
+uint64_t get_ticks(void)
+{
+	gd->timebase_h = readl(BCMSTB_TIMER_HIGH);
+	gd->timebase_l = readl(BCMSTB_TIMER_LOW);
+
+	return ((uint64_t)gd->timebase_h << 32) | gd->timebase_l;
+}
+
+int board_late_init(void)
+{
+	debug("Arguments from prior stage bootloader:\n");
+	debug("General Purpose Register 0: 0x%x\n", bcmstb_boot_parameters.r0);
+	debug("General Purpose Register 1: 0x%x\n", bcmstb_boot_parameters.r1);
+	debug("General Purpose Register 2: 0x%x\n", bcmstb_boot_parameters.r2);
+	debug("General Purpose Register 3: 0x%x\n", bcmstb_boot_parameters.r3);
+	debug("Stack Pointer Register:     0x%x\n", bcmstb_boot_parameters.sp);
+	debug("Link Register:              0x%x\n", bcmstb_boot_parameters.lr);
+	debug("Assuming timer frequency register at: 0x%p\n",
+	      (void *)BCMSTB_TIMER_FREQUENCY);
+	debug("Read timer frequency (in Hz): %ld\n", gd->arch.timer_rate_hz);
+	debug("Prior stage provided DTB at: 0x%p\n",
+	      (void *)prior_stage_fdt_address);
+
+	/*
+	 * Set fdtcontroladdr in the environment so that scripts can
+	 * refer to it, for example, to reuse it for fdtaddr.
+	 */
+	env_set_hex("fdtcontroladdr", prior_stage_fdt_address);
+
+	/*
+	 * Do not set machid to the machine identifier value provided
+	 * by the prior stage bootloader (bcmstb_boot_parameters.r1)
+	 * because we're using a device tree to boot Linux.
+	 */
+
+	return 0;
+}
diff --git a/roms/u-boot/board/bticino/mamoj/Kconfig b/roms/u-boot/board/bticino/mamoj/Kconfig
new file mode 100644
index 000000000..e5aec589c
--- /dev/null
+++ b/roms/u-boot/board/bticino/mamoj/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6DL_MAMOJ
+
+config SYS_BOARD
+	default "mamoj"
+
+config SYS_VENDOR
+	default "bticino"
+
+config SYS_CONFIG_NAME
+	default "imx6dl-mamoj"
+
+endif
diff --git a/roms/u-boot/board/bticino/mamoj/MAINTAINERS b/roms/u-boot/board/bticino/mamoj/MAINTAINERS
new file mode 100644
index 000000000..c35b387a8
--- /dev/null
+++ b/roms/u-boot/board/bticino/mamoj/MAINTAINERS
@@ -0,0 +1,10 @@
+MX6DL_MAMOJ BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+M:	Raffaele RECALCATI <raffaele.recalcati@bticino.it>
+M:	Simone CIANNI <simone.cianni@bticino.it>
+S:	Maintained
+F:	board/bticino/mamoj
+F:	include/configs/imx6dl-mamoj.h
+F:	configs/imx6dl_mamoj_defconfig
+F:	arch/arm/dts/imx6dl-mamoj.dts
+F:	arch/arm/dts/imx6dl-mamoj-u-boot.dtsi
diff --git a/roms/u-boot/board/bticino/mamoj/Makefile b/roms/u-boot/board/bticino/mamoj/Makefile
new file mode 100644
index 000000000..f1ddda489
--- /dev/null
+++ b/roms/u-boot/board/bticino/mamoj/Makefile
@@ -0,0 +1,8 @@
+# Copyright (C) 2018 BTicino
+# Copyright (C) 2017 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := mamoj.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/roms/u-boot/board/bticino/mamoj/README b/roms/u-boot/board/bticino/mamoj/README
new file mode 100644
index 000000000..5333c7253
--- /dev/null
+++ b/roms/u-boot/board/bticino/mamoj/README
@@ -0,0 +1,124 @@
+BTicino Mamoj board:
+===================
+
+Build:
+
+ $ make mrproper
+ $ make imx6dl_mamoj_defconfig
+ $ make
+
+   This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+The following methods can be used for booting Mamoj boards:
+
+1. USB SDP boot
+
+2. eMMC boot (via DFU)
+
+3. Falcon mode
+
+1. USB SDP boot:
+---------------
+
+ - Build imx_usb_loader
+
+    $ git clone git://github.com/boundarydevices/imx_usb_loader.git
+    $ cd imx_usb_loader
+    $ make
+
+ - Build the BSP and copy SPL, u-boot-dtb.img in imx_usb_loader directory
+
+ - Put the board in "Serial Download Mode"
+
+ - Plug-in USB-to-Serial, Open minicom 1152008N1 and USB OTG cables to Host
+
+ - Turn-on board
+
+ - Identify VID/PID using lsusb
+
+    Bus 001 Device 010: ID 15a2:0061 Freescale Semiconductor, Inc. i.MX 6Solo/6DualLite SystemOnChip in RecoveryMode
+
+ - Update the conf files
+
+    imx_usb.conf
+      0x15a2:0x0061, mx6_usb_rom.conf, 0x0525:0xb4a4, mx6_usb_sdp_spl.conf
+
+    mx6_usb_rom.conf
+      mx6_usb
+      hid,1024,0x910000,0x10000000,512M,0x00900000,0x40000
+      SPL:jump header2
+
+    mx6_usb_sdp_spl.conf
+      mx6_spl_sdp
+      hid,uboot_header,1024,0x910000,0x10000000,512M,0x00900000,0x40000
+      u-boot-dtb.img:jump header2
+
+  - Launch the loader
+
+     $ ./imx_usb
+
+  We can see U-Boot boot from USB SDP on minicom
+
+2. eMMC boot via DFU:
+--------------------
+
+  Once booted from USB SDP, program the eMMC as below(make sure to connect USB OTG)
+
+  - Change eMMC partition config
+
+     => mmc partconf 2 1 0 0
+
+  - Partition eMMC on host
+
+     => ums 0 mmc 2
+
+    Host will able to detect the eMMC disk as UMS, partition the same.
+
+  - Program SPL
+
+     => setenv dfu_alt_info $dfu_alt_info_spl
+     => dfu 0 mmc 2
+
+     At Host
+
+     # dfu-util -D SPL -a spl
+
+  - Program u-boot-dtb.img
+
+     => setenv dfu_alt_info $dfu_alt_info_uboot
+     => dfu 0 mmc 2
+
+     At Host
+
+     # dfu-util -D u-boot-dtb.img -a u-boot
+
+  Poweroff and Poweron the board and see U-Boot booting from eMMC.
+
+3. Falcon mode:
+--------------
+
+  - Skip 10M space and create dual partitions for eMMC, start sector is 20480
+
+    Partition Map for MMC device 2  --   Partition Type: DOS
+
+    Part    Start Sector    Num Sectors     UUID            Type
+      1     20480           131072          c52e78be-01     83
+      2     151552          7581696         c52e78be-02     83
+
+  - Write uImage
+
+    => fatload mmc 2:1 $kernel_addr_r uImage
+    => mmc write $kernel_addr_r 0x1000 0x4000
+
+  - Write dtb and args
+
+    => setenv bootargs console=ttymxc2,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait rw quiet
+    => fatload mmc 2:1 $fdt_addr_r imx6dl-mamoj.dtb
+    => spl export fdt $kernel_addr_r - $fdt_addr_r
+    => mmc write 0x13000000 0x800 0x800
+
+  Poweroff and Poweron the board and see Linux booting directly after SPL.
+
+--
+Jagan Teki <jagan@amarulasolutions.com>
+03/12/18
diff --git a/roms/u-boot/board/bticino/mamoj/mamoj.c b/roms/u-boot/board/bticino/mamoj/mamoj.c
new file mode 100644
index 000000000..c9da42b43
--- /dev/null
+++ b/roms/u-boot/board/bticino/mamoj/mamoj.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
+ * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/bticino/mamoj/spl.c b/roms/u-boot/board/bticino/mamoj/spl.c
new file mode 100644
index 000000000..883b7f413
--- /dev/null
+++ b/roms/u-boot/board/bticino/mamoj/spl.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
+ * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <serial.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMX6SDL_DRIVE_STRENGTH		0x28
+#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+	IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif
+
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
+	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
+	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 32,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+	.SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x0042004b,
+	.p0_mpwldectrl1 = 0x0038003c,
+	.p0_mpdgctrl0 = 0x42340230,
+	.p0_mpdgctrl1 = 0x0228022c,
+	.p0_mprddlctl = 0x42444646,
+	.p0_mpwrdlctl = 0x38382e2e,
+};
+
+static struct mx6_ddr_sysinfo mem_dl = {
+	.dsize		= 1,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 1,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+	.refsel		= 1,
+	.refr		= 7,
+};
+
+static void spl_dram_init(void)
+{
+	mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+	mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125);
+
+	udelay(100);
+}
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00003f3f, &ccm->CCGR0);
+	writel(0x0030fc00, &ccm->CCGR1);
+	writel(0x000fc000, &ccm->CCGR2);
+	writel(0x3f300000, &ccm->CCGR3);
+	writel(0xff00f300, &ccm->CCGR4);
+	writel(0x0f0000c3, &ccm->CCGR5);
+	writel(0x000003cc, &ccm->CCGR6);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* iomux */
+	SETUP_IOMUX_PADS(uart3_pads);
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
diff --git a/roms/u-boot/board/buffalo/lsxl/Kconfig b/roms/u-boot/board/buffalo/lsxl/Kconfig
new file mode 100644
index 000000000..ef7889637
--- /dev/null
+++ b/roms/u-boot/board/buffalo/lsxl/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LSXL
+
+config SYS_BOARD
+	default "lsxl"
+
+config SYS_VENDOR
+	default "buffalo"
+
+config SYS_CONFIG_NAME
+	default "lsxl"
+
+endif
diff --git a/roms/u-boot/board/buffalo/lsxl/MAINTAINERS b/roms/u-boot/board/buffalo/lsxl/MAINTAINERS
new file mode 100644
index 000000000..facc2dd7d
--- /dev/null
+++ b/roms/u-boot/board/buffalo/lsxl/MAINTAINERS
@@ -0,0 +1,7 @@
+LSXL BOARD
+M:	Michael Walle <michael@walle.cc>
+S:	Maintained
+F:	board/buffalo/lsxl/
+F:	include/configs/lsxl.h
+F:	configs/lschlv2_defconfig
+F:	configs/lsxhl_defconfig
diff --git a/roms/u-boot/board/buffalo/lsxl/Makefile b/roms/u-boot/board/buffalo/lsxl/Makefile
new file mode 100644
index 000000000..60babb0de
--- /dev/null
+++ b/roms/u-boot/board/buffalo/lsxl/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2012 Michael Walle
+# Michael Walle <michael@walle.cc>
+
+obj-y	:= lsxl.o
diff --git a/roms/u-boot/board/buffalo/lsxl/README b/roms/u-boot/board/buffalo/lsxl/README
new file mode 100644
index 000000000..fffb1ce8e
--- /dev/null
+++ b/roms/u-boot/board/buffalo/lsxl/README
@@ -0,0 +1,149 @@
+Intro
+-----
+The Buffalo Linkstation Pro/Live, codename LS-XHL and LS-CHLv2, is a single
+disk NAS server. The PCBs of the LS-XHL and LS-CHLv2 are almost the same.
+The LS-XHL has a faster CPU and more RAM with a wider data bus, therefore
+the LS-XHL PCB has two SDRAM chips. Both have a Kirkwood CPU (Marvell
+88F6281). The only on-board storage is a 4 Mbit SPI flash which stores the
+bootloader and its environment. The linux kernel and the initial ramdisk
+are loaded from the hard disk.
+
+Important! Changes since v2019.07
+---------------------------------
+In u-boot v2019.07 the driver for the SATA port was changed to a new
+one. This means that the old "ide" command and block interface is not
+supported anymore. More important, the boot commands have changed. You have
+to overwrite the boot commands in your envionment with the new ones:
+
+  env default -f bootcmd_legacy
+  env default -f bootcmd_hdd
+  saveenv
+
+Rescue Mode
+-----------
+These linkstations don't have a populated serial port. There is no way to
+access an (unmodified) board other than using the netconsole. If you want
+to recover from a bad environment setting or an empty environment, you can
+do this only with a working network connection.
+
+Therefore, on entering the resuce mode, a random ethernet address is
+generated if no valid address could be loaded from the environment variable
+'ethaddr' and a DHCP request is sent. After a successful DHCP response is
+received, the network settings are configured and the ncip is unset. Thus
+all netconsole packets are broadcasted and you can use the netconsole to
+access board from any host within the network segment. To determine the IP
+address assigned to the board, you either have to sniff the traffic or
+check the logs/leases of your DHCP server.
+
+The resuce mode is selected by holding the push button for at least one
+second, while powering-on the device. The status LED turns solid amber if
+the resuce mode is enabled, thus providing a visual feedback.
+
+Pressing the same button for at least 10 seconds on power-up will erase the
+environment and reset the board. In this case the visual indication will
+be:
+- blinking blue, for about one second
+- solid amber, for about nine seconds
+- blinking amber, until you release the button
+
+This ensures, that you still can recover a device with a broken
+environment by first erasing the environment and then entering the rescue
+mode.
+
+Once the rescue mode is started, use the ncb binary from the tools/
+directory to access your board. There is a helper script named
+'restore_env' to save your changes. It unsets all the network variables
+which were set by the rescue mode, saves your changes and then resets the
+board.
+
+The common use case for this is setting a MAC address. Let us assume you
+have an empty environment, the board comes up with the amber LED blinking.
+Then you enter the rescue mode, connect to the board with the ncb tool and
+use the following commands to set your MAC address:
+
+  setenv ethaddr 00:00:00:00:00:00
+  run restore_env
+
+Of course you need to replace the 00:00:00:00:00:00 with your valid MAC
+address, which can be found on a sticker on the bottom of your box.
+
+
+Status LED
+----------
+blinking blue
+  Bootloader is running normally.
+
+blinking amber
+  No ethaddr set. Use the `Rescue Mode` to set one.
+
+blinking red
+  Something bad happend during loading the operating system.
+
+The default behavior of the linux kernel is to turn on the blue LED. So if
+the blinking blue LED changes to solid blue the kernel was loaded
+successfully.
+
+
+Power-on Switch
+---------------
+The power-on switch is a software switch. If it is not in ON position when
+the bootloader starts, the bootloader will disable the HDD and USB power
+and stop the fan. Then it loops until the switch is in ON position again,
+enables the power and fan again and continue booting.
+
+
+Boot sources
+------------
+The environment defines several different boot sources:
+
+legacy
+  This is the default boot source. It loads the kernel and ramdisk from the
+  attached HDD using the original filenames. The load addresses were
+  modified to support loading larger kernels. But it should behave the same
+  as the original bootloader.
+
+hdd
+  Use this for new-style booting. Loads three files /vmlinuz, /initrd.img
+  and /dtb from the boot partition. This should work out of the box if you
+  have debian and the flash-kernel package installed.
+
+usb
+  Same as hdd expect, that the files are loaded from an attached USB mass
+  storage device and the filename for the device tree is kirkwood-lsxhl.dtb
+  (or kirkwood-lschlv2.dtb).
+
+net
+  Same as usb expect, that the file are loaded from the network.
+
+rescue
+  Automatically activated if the push button is pressed for at least one
+  second on power-up. Does a DHCP request and enables the network console.
+  See `Rescue Mode` for more information.
+
+You can change the boot source by setting the 'bootsource' variable to the
+corresponding value. Please note, that the restore_env script will the the
+bootsource back to 'legacy'.
+
+
+Flash map
+---------
+00000 - 5ffff   u-boot
+60000 - 6ffff   reserved, may be used to store dtb
+70000 - 7ffff   u-boot environment
+
+
+Compiling
+---------
+make lsxhl_config (or lschlv2_config)
+make u-boot.kwb
+
+
+Update your board
+-----------------
+Just flash the resulting u-boot.kwb to the beginning of the SPI flash. If
+you already have a bootloader CLI, you can use the following commands:
+
+ sf probe 0
+ bootp ${loadaddr} u-boot.kwb
+ sf erase 0 +${filelen}
+ sf write 0 ${fileaddr} ${filesize}
diff --git a/roms/u-boot/board/buffalo/lsxl/kwbimage-lschl.cfg b/roms/u-boot/board/buffalo/lsxl/kwbimage-lschl.cfg
new file mode 100644
index 000000000..4493307d8
--- /dev/null
+++ b/roms/u-boot/board/buffalo/lsxl/kwbimage-lschl.cfg
@@ -0,0 +1,211 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2012 Michael Walle
+# Michael Walle <michael@walle.cc>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100E0 0x1B1B1B9B
+
+# L2 RAM Timing 0
+DATA 0xFFD20134 0xBBBBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# L2 RAM Timing 1
+DATA 0xFFD20138 0x00BBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# DDR Configuration register
+DATA 0xFFD01400 0x43000618
+# bit13-0:  0x618, 1560 DDR2 clks refresh rate
+# bit23-14: 0 required
+# bit24:    1, enable exit self refresh mode on DDR access
+# bit25:    1 required
+# bit29-26: 0 required
+# bit31-30: 0b01 required
+
+# DDR Controller Control Low
+DATA 0xFFD01404 0x39543000
+# bit3-0:   0 required
+# bit4:     0, addr/cmd in same cycle
+# bit5:     0, clk is driven during self refresh, we don't care for APX
+# bit6:     0, use recommended falling edge of clk for addr/cmd
+# bit11-7:  0 required
+# bit12:    1 required
+# bit13:    1 required
+# bit14:    0, input buffer always powered up
+# bit17-15: 0 required
+# bit18:    1, cpu lock transaction enabled
+# bit19:    0 required
+# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0, no additional STARTBURST delay
+
+# DDR Timing (Low)
+DATA 0xFFD01408 0x3302444F
+# bit3-0:   0xf, 16 cycle tRAS (tRAS[3-0])
+# bit7-4:   4, 5 cycle tRCD
+# bit11-8:  4, 5 cyle tRP
+# bit15-12: 4, 5 cyle tWR
+# bit19-16: 2, 3 cyle tWTR
+# bit20:    0, 16 cycle tRAS (tRAS[4])
+# bit23-21: 0 required
+# bit27-24: 3, 4 cycle tRRD
+# bit31-28: 3, 4 cyle tRTP
+
+# DDR Timing (High)
+DATA 0xFFD0140C 0x00000823
+# bit6-0:   0x23, 35 cycle tRFC
+# bit8-7:   0, 1 cycle tR2R
+# bit10-9:  0, 1 cyle tR2W
+# bit12-11: 1, 2 cylce tW2W
+# bit31-13: 0 required
+
+# DDR Address Control
+DATA 0xFFD01410 0x00000009
+# bit1-0:   1, Cs0width=x16
+# bit3-2:   2, Cs0size=512Mbit
+# bit5-4:   0, Cs1width=nonexistent
+# bit7-6:   0, Cs1size=nonexistent
+# bit9-8:   0, Cs2width=nonexistent
+# bit11-10: 0, Cs2size=nonexistent
+# bit13-12: 0, Cs3width=nonexistent
+# bit15-14: 0, Cs3size=nonexistent
+# bit16:    0, Cs0AddrSel
+# bit17:    0, Cs1AddrSel
+# bit18:    0, Cs2AddrSel
+# bit19:    0, Cs3AddrSel
+# bit31-20: 0 required
+
+# DDR Open Pages Control
+DATA 0xFFD01414 0x00000000
+# bit0:    0, OPEn=OpenPage enabled
+# bit31-1: 0 required
+
+# DDR Operation
+DATA 0xFFD01418 0x00000000
+# bit3-0:   0, Cmd=Normal SDRAM Mode
+# bit31-4:  0 required
+
+# DDR Mode
+DATA 0xFFD0141C 0x00000652
+# bit2-0:   2, Burst Length (2 required)
+# bit3:     0, Burst Type (0 required)
+# bit6-4:   5, CAS Latency (CL) 5
+# bit7:     0, (Test Mode) Normal operation
+# bit8:     0, (Reset DLL) Normal operation
+# bit11-9:  3, Write recovery for auto-precharge (3 required)
+# bit12:    0, Fast Active power down exit time (0 required)
+# bit31-13: 0 required
+
+# DDR Extended Mode
+DATA 0xFFD01420 0x00000042
+# bit0:     0, DRAM DLL enabled
+# bit1:     1, DRAM drive strength reduced
+# bit2:     0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
+# bit5-3:   0 required
+# bit6:     1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
+# bit9-7:   0 required
+# bit10:    0, differential DQS enabled
+# bit11:    0 required
+# bit12:    0, DRAM output buffer enabled
+# bit31-13: 0 required
+
+# DDR Controller Control High
+DATA 0xFFD01424 0x0000F17F
+# bit2-0:   0x7 required
+# bit3:     1, MBUS Burst Chop disabled
+# bit6-4:   0x7 required
+# bit7:     0 required (???)
+# bit8:     1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9:     0, no half clock cycle addition to dataout
+# bit10:    0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11:    0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf required
+# bit31-16: 0 required
+
+# DDR2 ODT Read Timing (default values)
+DATA 0xFFD01428 0x00085520
+# bit3-0:   0 required
+# bit7-4:   2, 2 cycles from read command to assertion of M_ODT signal
+# bit11-8:  5, 5 cycles from read command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
+# bit31-20: 0 required
+
+# DDR2 ODT Write Timing (default values)
+DATA 0xFFD0147C 0x00008552
+# bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
+# bit7-4:   5, 5 cycles from write command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
+# bit31-16: 0 required
+
+# CS[0]n Base address
+DATA 0xFFD01500 0x00000000
+# at 0x0
+
+# CS[0]n Size
+DATA 0xFFD01504 0x03FFFFF1
+# bit0:     1, Window enabled
+# bit1:     0, Write Protect disabled
+# bit3-2:   0x0, CS0 hit selected
+# bit23-4:  0xfffff required
+# bit31-24: 0x03, Size (i.e. 64MB)
+
+# CS[1]n Size
+DATA 0xFFD0150C 0x00000000
+# window disabled
+
+# CS[2]n Size
+DATA 0xFFD01514 0x00000000
+# window disabled
+
+# CS[3]n Size
+DATA 0xFFD0151C 0x00000000
+# window disabled
+
+# DDR ODT Control (Low)
+DATA 0xFFD01494 0x003C0000
+# bit3-0:   0b0000, (read) M_ODT[0] is not asserted during read from DRAM
+# bit7-4:   0b0000, (read) M_ODT[1] is not asserted during read from DRAM
+# bit15-8:  0 required
+# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
+# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
+# bit31-24: 0 required
+
+# DDR ODT Control (High)
+DATA 0xFFD01498 0x00000000
+# bit1-0:   0, M_ODT[0] assertion is controlled by ODT Control Low register
+# bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
+# bit31-4   0 required
+
+# CPU ODT Control
+DATA 0xFFD0149C 0x0000E80F
+# bit3-0:   0b1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit7-4:   0b0000, internal ODT is not asserted during write to DRAM bank 0-3
+# bit9-8:   0, Internal ODT assertion is controlled by fiels
+# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
+# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
+# bit14:    1, M_STARTBURST_IN ODT enabled
+# bit15:    1, DDR IO ODT Unit: Drive ODT calibration values
+# bit20-16: 0, Pad N channel driving strength for ODT
+# bit25-21: 0, Pad P channel driving strength for ODT
+# bit31-26: 0 required
+
+# DDR Initialization Control
+DATA 0xFFD01480 0x00000001
+# bit0:     1, enable DDR init upon this register write
+# bit31-1:  0, required
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/buffalo/lsxl/kwbimage-lsxhl.cfg b/roms/u-boot/board/buffalo/lsxl/kwbimage-lsxhl.cfg
new file mode 100644
index 000000000..4335a663c
--- /dev/null
+++ b/roms/u-boot/board/buffalo/lsxl/kwbimage-lsxhl.cfg
@@ -0,0 +1,211 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2012 Michael Walle
+# Michael Walle <michael@walle.cc>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100E0 0x1B1B9B9B
+
+# L2 RAM Timing 0
+DATA 0xFFD20134 0xBBBBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# L2 RAM Timing 1
+DATA 0xFFD20138 0x00BBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# DDR Configuration register
+DATA 0xFFD01400 0x43000618
+# bit13-0:  0x618, 1560 DDR2 clks refresh rate
+# bit23-14: 0 required
+# bit24:    1, enable exit self refresh mode on DDR access
+# bit25:    1 required
+# bit29-26: 0 required
+# bit31-30: 0b01 required
+
+# DDR Controller Control Low
+DATA 0xFFD01404 0x39543010
+# bit3-0:   0 required
+# bit4:     1, T2 mode, addr/cmd are driven for two cycles
+# bit5:     0, clk is driven during self refresh, we don't care for APX
+# bit6:     0, use recommended falling edge of clk for addr/cmd
+# bit11-7:  0 required
+# bit12:    1 required
+# bit13:    1 required
+# bit14:    0, input buffer always powered up
+# bit17-15: 0 required
+# bit18:    1, cpu lock transaction enabled
+# bit19:    0 required
+# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0, no additional STARTBURST delay
+
+# DDR Timing (Low)
+DATA 0xFFD01408 0x22125441
+# bit3-0:   0x1, 18 cycle tRAS (tRAS[3-0])
+# bit7-4:   4, 5 cycle tRCD
+# bit11-8:  4, 5 cyle tRP
+# bit15-12: 5, 6 cyle tWR
+# bit19-16: 2, 3 cyle tWTR
+# bit20:    1, 18 cycle tRAS (tRAS[4])
+# bit23-21: 0 required
+# bit27-24: 2, 3 cycle tRRD
+# bit31-28: 2, 3 cyle tRTP
+
+# DDR Timing (High)
+DATA 0xFFD0140C 0x00000832
+# bit6-0:   0x32, 50 cycle tRFC
+# bit8-7:   0, 1 cycle tR2R
+# bit10-9:  0, 1 cyle tR2W
+# bit12-11: 1, 2 cylce tW2W
+# bit31-13: 0 required
+
+# DDR Address Control
+DATA 0xFFD01410 0x0000000C
+# bit1-0:   0, Cs0width=x8
+# bit3-2:   3, Cs0size=1Gbit
+# bit5-4:   0, Cs1width=nonexistent
+# bit7-6:   0, Cs1size=nonexistent
+# bit9-8:   0, Cs2width=nonexistent
+# bit11-10: 0, Cs2size=nonexistent
+# bit13-12: 0, Cs3width=nonexistent
+# bit15-14: 0, Cs3size=nonexistent
+# bit16:    0, Cs0AddrSel
+# bit17:    0, Cs1AddrSel
+# bit18:    0, Cs2AddrSel
+# bit19:    0, Cs3AddrSel
+# bit31-20: 0 required
+
+# DDR Open Pages Control
+DATA 0xFFD01414 0x00000000
+# bit0:    0, OPEn=OpenPage enabled
+# bit31-1: 0 required
+
+# DDR Operation
+DATA 0xFFD01418 0x00000000
+# bit3-0:   0, Cmd=Normal SDRAM Mode
+# bit31-4:  0 required
+
+# DDR Mode
+DATA 0xFFD0141C 0x00000652
+# bit2-0:   2, Burst Length (2 required)
+# bit3:     0, Burst Type (0 required)
+# bit6-4:   5, CAS Latency (CL) 5
+# bit7:     0, (Test Mode) Normal operation
+# bit8:     0, (Reset DLL) Normal operation
+# bit11-9:  3, Write recovery for auto-precharge (3 required)
+# bit12:    0, Fast Active power down exit time (0 required)
+# bit31-13: 0 required
+
+# DDR Extended Mode
+DATA 0xFFD01420 0x00000006
+# bit0:     0, DRAM DLL enabled
+# bit1:     1, DRAM drive strength reduced
+# bit2:     1, ODT control Rtt[0] (Rtt=1, 75 ohm termination)
+# bit5-3:   0 required
+# bit6:     0, ODT control Rtt[1] (Rtt=1, 75 ohm termination)
+# bit9-7:   0 required
+# bit10:    0, differential DQS enabled
+# bit11:    0 required
+# bit12:    0, DRAM output buffer enabled
+# bit31-13: 0 required
+
+# DDR Controller Control High
+DATA 0xFFD01424 0x0000F17F
+# bit2-0:   0x7 required
+# bit3:     1, MBUS Burst Chop disabled
+# bit6-4:   0x7 required
+# bit7:     0 required (???)
+# bit8:     1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9:     0, no half clock cycle addition to dataout
+# bit10:    0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11:    0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf required
+# bit31-16: 0 required
+
+# DDR2 ODT Read Timing (default values)
+DATA 0xFFD01428 0x00085520
+# bit3-0:   0 required
+# bit7-4:   2, 2 cycles from read command to assertion of M_ODT signal
+# bit11-8:  5, 5 cycles from read command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
+# bit31-20: 0 required
+
+# DDR2 ODT Write Timing (default values)
+DATA 0xFFD0147C 0x00008552
+# bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
+# bit7-4:   5, 5 cycles from write command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
+# bit31-16: 0 required
+
+# CS[0]n Base address
+DATA 0xFFD01500 0x00000000
+# at 0x0
+
+# CS[0]n Size
+DATA 0xFFD01504 0x0FFFFFF1
+# bit0:     1, Window enabled
+# bit1:     0, Write Protect disabled
+# bit3-2:   0x0, CS0 hit selected
+# bit23-4:  0xfffff required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+# CS[1]n Size
+DATA 0xFFD0150C 0x00000000
+# window disabled
+
+# CS[2]n Size
+DATA 0xFFD01514 0x00000000
+# window disabled
+
+# CS[3]n Size
+DATA 0xFFD0151C 0x00000000
+# window disabled
+
+# DDR ODT Control (Low)
+DATA 0xFFD01494 0x00010000
+# bit3-0:   0b0000, (read) M_ODT[0] is not asserted during read from DRAM
+# bit7-4:   0b0000, (read) M_ODT[1] is not asserted during read from DRAM
+# bit15-8:  0 required
+# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
+# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
+# bit31-24: 0 required
+
+# DDR ODT Control (High)
+DATA 0xFFD01498 0x00000000
+# bit1-0:   0, M_ODT[0] assertion is controlled by ODT Control Low register
+# bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
+# bit31-4   0 required
+
+# CPU ODT Control
+DATA 0xFFD0149C 0x0000E80F
+# bit3-0:   0b1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit7-4:   0b0000, internal ODT is not asserted during write to DRAM bank 0-3
+# bit9-8:   0, Internal ODT assertion is controlled by fiels
+# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
+# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
+# bit14:    1, M_STARTBURST_IN ODT enabled
+# bit15:    1, DDR IO ODT Unit: Drive ODT calibration values
+# bit20-16: 0, Pad N channel driving strength for ODT
+# bit25-21: 0, Pad P channel driving strength for ODT
+# bit31-26: 0 required
+
+# DDR Initialization Control
+DATA 0xFFD01480 0x00000001
+# bit0:     1, enable DDR init upon this register write
+# bit31-1:  0, required
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/buffalo/lsxl/lsxl.c b/roms/u-boot/board/buffalo/lsxl/lsxl.c
new file mode 100644
index 000000000..34be601fd
--- /dev/null
+++ b/roms/u-boot/board/buffalo/lsxl/lsxl.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * Based on sheevaplug/sheevaplug.c by
+ *   Marvell Semiconductor <www.marvell.com>
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <command.h>
+#include <env.h>
+#include <env_internal.h>
+#include <flash.h>
+#include <init.h>
+#include <net.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#include "lsxl.h"
+
+/*
+ * Rescue mode
+ *
+ * Selected by holding the push button for 3 seconds, while powering on
+ * the device.
+ *
+ * These linkstations don't have a (populated) serial port. There is no
+ * way to access an (unmodified) board other than using the netconsole. If
+ * you want to recover from a bad environment setting or an empty environment,
+ * you can do this only with a working network connection. Therefore, a random
+ * ethernet address is generated if none is set and a DHCP request is sent.
+ * After a successful DHCP response is received, the network settings are
+ * configured and the ncip is unset. Therefore, all netconsole packets are
+ * broadcasted.
+ * Additionally, the bootsource is set to 'rescue'.
+ */
+
+#ifndef CONFIG_ENV_OVERWRITE
+# error "You need to set CONFIG_ENV_OVERWRITE"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(LSXL_OE_VAL_LOW,
+			  LSXL_OE_VAL_HIGH,
+			  LSXL_OE_LOW, LSXL_OE_HIGH);
+
+	/*
+	 * Multi-Purpose Pins Functionality configuration
+	 * These strappings are taken from the original vendor uboot port.
+	 */
+	static const u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP4_UART0_RXD,
+		MPP5_UART0_TXD,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_GPIO,
+		MPP9_GPIO,
+		MPP10_GPO,		/* HDD power */
+		MPP11_GPIO,		/* USB Vbus enable */
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_GPO,		/* fan speed high */
+		MPP19_GPO,		/* fan speed low */
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,		/* function LED */
+		MPP37_GPIO,		/* alarm LED */
+		MPP38_GPIO,		/* info LED */
+		MPP39_GPIO,		/* power LED */
+		MPP40_GPIO,		/* fan alarm */
+		MPP41_GPIO,		/* funtion button */
+		MPP42_GPIO,		/* power switch */
+		MPP43_GPIO,		/* power auto switch */
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,		/* function red LED */
+		MPP49_GPIO,
+		0
+	};
+
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+
+	return 0;
+}
+
+#define LED_OFF             0
+#define LED_ALARM_ON        1
+#define LED_ALARM_BLINKING  2
+#define LED_POWER_ON        3
+#define LED_POWER_BLINKING  4
+#define LED_INFO_ON         5
+#define LED_INFO_BLINKING   6
+
+static void __set_led(int blink_alarm, int blink_info, int blink_power,
+		int value_alarm, int value_info, int value_power)
+{
+	kw_gpio_set_blink(GPIO_ALARM_LED, blink_alarm);
+	kw_gpio_set_blink(GPIO_INFO_LED, blink_info);
+	kw_gpio_set_blink(GPIO_POWER_LED, blink_power);
+	kw_gpio_set_value(GPIO_ALARM_LED, value_alarm);
+	kw_gpio_set_value(GPIO_INFO_LED, value_info);
+	kw_gpio_set_value(GPIO_POWER_LED, value_power);
+}
+
+static void set_led(int state)
+{
+	switch (state) {
+	case LED_OFF:
+		__set_led(0, 0, 0, 1, 1, 1);
+		break;
+	case LED_ALARM_ON:
+		__set_led(0, 0, 0, 0, 1, 1);
+		break;
+	case LED_ALARM_BLINKING:
+		__set_led(1, 0, 0, 1, 1, 1);
+		break;
+	case LED_INFO_ON:
+		__set_led(0, 0, 0, 1, 0, 1);
+		break;
+	case LED_INFO_BLINKING:
+		__set_led(0, 1, 0, 1, 1, 1);
+		break;
+	case LED_POWER_ON:
+		__set_led(0, 0, 0, 1, 1, 0);
+		break;
+	case LED_POWER_BLINKING:
+		__set_led(0, 0, 1, 1, 1, 1);
+		break;
+	}
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	set_led(LED_POWER_BLINKING);
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+static void check_power_switch(void)
+{
+	if (kw_gpio_get_value(GPIO_POWER_SWITCH)) {
+		/* turn off fan, HDD and USB power */
+		kw_gpio_set_value(GPIO_HDD_POWER, 0);
+		kw_gpio_set_value(GPIO_USB_VBUS, 0);
+		kw_gpio_set_value(GPIO_FAN_HIGH, 1);
+		kw_gpio_set_value(GPIO_FAN_LOW, 1);
+		set_led(LED_OFF);
+
+		/* loop until released */
+		while (kw_gpio_get_value(GPIO_POWER_SWITCH))
+			;
+
+		/* turn power on again */
+		kw_gpio_set_value(GPIO_HDD_POWER, 1);
+		kw_gpio_set_value(GPIO_USB_VBUS, 1);
+		kw_gpio_set_value(GPIO_FAN_HIGH, 0);
+		kw_gpio_set_value(GPIO_FAN_LOW, 0);
+		set_led(LED_POWER_BLINKING);
+	}
+}
+
+void check_enetaddr(void)
+{
+	uchar enetaddr[6];
+
+	if (!eth_env_get_enetaddr("ethaddr", enetaddr)) {
+		/* signal unset/invalid ethaddr to user */
+		set_led(LED_INFO_BLINKING);
+	}
+}
+
+static void erase_environment(void)
+{
+	struct spi_flash *flash;
+
+	printf("Erasing environment..\n");
+	flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+	if (!flash) {
+		printf("Erasing flash failed\n");
+		return;
+	}
+
+	spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE);
+	spi_flash_free(flash);
+	do_reset(NULL, 0, 0, NULL);
+}
+
+static void rescue_mode(void)
+{
+	printf("Entering rescue mode..\n");
+	env_set("bootsource", "rescue");
+}
+
+static void check_push_button(void)
+{
+	int i = 0;
+
+	while (!kw_gpio_get_value(GPIO_FUNC_BUTTON)) {
+		udelay(100000);
+		i++;
+
+		if (i == 10)
+			set_led(LED_INFO_ON);
+
+		if (i >= 100) {
+			set_led(LED_INFO_BLINKING);
+			break;
+		}
+	}
+
+	if (i >= 100)
+		erase_environment();
+	else if (i >= 10)
+		rescue_mode();
+}
+
+int misc_init_r(void)
+{
+	check_power_switch();
+	check_enetaddr();
+	check_push_button();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int progress)
+{
+	if (progress > 0)
+		return;
+
+	/* this is not an error, eg. bootp with autoload=no will trigger this */
+	if (progress == -BOOTSTAGE_ID_NET_LOADED)
+		return;
+
+	set_led(LED_ALARM_BLINKING);
+}
+#endif
diff --git a/roms/u-boot/board/buffalo/lsxl/lsxl.h b/roms/u-boot/board/buffalo/lsxl/lsxl.h
new file mode 100644
index 000000000..8ff3f2f3a
--- /dev/null
+++ b/roms/u-boot/board/buffalo/lsxl/lsxl.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ */
+
+#ifndef __LSXL_H
+#define __LSXL_H
+
+#define GPIO_HDD_POWER		10
+#define GPIO_USB_VBUS		11
+#define GPIO_FAN_HIGH		18
+#define GPIO_FAN_LOW		19
+#define GPIO_FUNC_LED		36
+#define GPIO_ALARM_LED		37
+#define GPIO_INFO_LED		38
+#define GPIO_POWER_LED		39
+#define GPIO_FAN_LOCK		40
+#define GPIO_FUNC_BUTTON	41
+#define GPIO_POWER_SWITCH	42
+#define GPIO_POWER_AUTO_SWITCH	43
+#define GPIO_FUNC_RED_LED	48
+
+#define _BIT(x) (1<<(x))
+
+#define LSXL_OE_LOW (~(_BIT(GPIO_HDD_POWER)		    \
+			| _BIT(GPIO_USB_VBUS)		    \
+			| _BIT(GPIO_FAN_HIGH)		    \
+			| _BIT(GPIO_FAN_LOW)))
+
+#define LSXL_OE_HIGH (~(_BIT(GPIO_FUNC_LED - 32)	    \
+			| _BIT(GPIO_ALARM_LED - 32)	    \
+			| _BIT(GPIO_INFO_LED - 32)	    \
+			| _BIT(GPIO_POWER_LED - 32)	    \
+			| _BIT(GPIO_FUNC_RED_LED - 32)))
+
+#define LSXL_OE_VAL_LOW (_BIT(GPIO_HDD_POWER)		    \
+			| _BIT(GPIO_USB_VBUS))
+
+#define LSXL_OE_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32)	    \
+			| _BIT(GPIO_ALARM_LED - 32)	    \
+			| _BIT(GPIO_INFO_LED - 32)	    \
+			| _BIT(GPIO_POWER_LED - 32)	    \
+			| _BIT(GPIO_FUNC_RED_LED - 32))
+
+#define LSXL_POL_VAL_LOW (_BIT(GPIO_FAN_HIGH)		    \
+			| _BIT(GPIO_FAN_LOW))
+
+#define LSXL_POL_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32)	    \
+			| _BIT(GPIO_ALARM_LED - 32)	    \
+			| _BIT(GPIO_INFO_LED - 32)	    \
+			| _BIT(GPIO_POWER_LED - 32)	    \
+			| _BIT(GPIO_FUNC_BUTTON - 32)	    \
+			| _BIT(GPIO_POWER_SWITCH - 32)	    \
+			| _BIT(GPIO_POWER_AUTO_SWITCH - 32) \
+			| _BIT(GPIO_FUNC_RED_LED - 32))
+
+#endif /* __LSXL_H */
diff --git a/roms/u-boot/board/cadence/xtfpga/Kconfig b/roms/u-boot/board/cadence/xtfpga/Kconfig
new file mode 100644
index 000000000..69296be49
--- /dev/null
+++ b/roms/u-boot/board/cadence/xtfpga/Kconfig
@@ -0,0 +1,39 @@
+if TARGET_XTFPGA
+
+choice
+	prompt "XTFPGA board type select"
+
+config XTFPGA_LX60
+	bool "Support Avnet LX60"
+config XTFPGA_LX110
+	bool "Support Avnet LX110"
+config XTFPGA_LX200
+	bool "Support Avnet LX200"
+config XTFPGA_ML605
+	bool "Support Xilinx ML605"
+config XTFPGA_KC705
+	bool "Support Xilinx KC705"
+
+endchoice
+
+config SYS_BOARD
+	string
+	default "xtfpga"
+
+config SYS_VENDOR
+	string
+	default "cadence"
+
+config SYS_CONFIG_NAME
+	string
+	default "xtfpga"
+
+config BOARD_SDRAM_SIZE
+	hex
+	default 0x04000000 if XTFPGA_LX60
+	default 0x03000000 if XTFPGA_LX110
+	default 0x06000000 if XTFPGA_LX200
+	default 0x18000000 if XTFPGA_ML605
+	default 0x38000000 if XTFPGA_KC705
+
+endif
diff --git a/roms/u-boot/board/cadence/xtfpga/MAINTAINERS b/roms/u-boot/board/cadence/xtfpga/MAINTAINERS
new file mode 100644
index 000000000..f4a2b942d
--- /dev/null
+++ b/roms/u-boot/board/cadence/xtfpga/MAINTAINERS
@@ -0,0 +1,7 @@
+XTFPGA BOARD
+M:	Max Filippov <jcmvbkbc@gmail.com>
+S:	Maintained
+F:	board/cadence/xtfpga/
+F:	include/configs/xtfpga.h
+F:	configs/xtfpga_defconfig
+F:	drivers/sysreset/sysreset_xtfpga.c
diff --git a/roms/u-boot/board/cadence/xtfpga/Makefile b/roms/u-boot/board/cadence/xtfpga/Makefile
new file mode 100644
index 000000000..64bce9e6b
--- /dev/null
+++ b/roms/u-boot/board/cadence/xtfpga/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2007 - 2013, Tensilica Inc.
+
+obj-y				+= ${BOARD}.o
diff --git a/roms/u-boot/board/cadence/xtfpga/README b/roms/u-boot/board/cadence/xtfpga/README
new file mode 100644
index 000000000..5f29e2592
--- /dev/null
+++ b/roms/u-boot/board/cadence/xtfpga/README
@@ -0,0 +1,125 @@
+		Tensilica 'xtfpga' Evaluation Boards
+		====================================
+
+Tensilica's 'xtfpga' evaluation boards are actually a set of different
+boards that share configurations. The following is a list of supported
+hardware by this board type:
+
+- XT-AV60  / LX60
+- XT-AV110 / LX110
+- XT-AV200 / LX200
+- ML605
+- KC705
+
+All boards provide the following common configurations:
+
+- An Xtensa or Diamond processor core.
+- An on-chip-debug (OCD) JTAG interface.
+- A 16550 compatible UART and serial port.
+- An OpenCores Wishbone 10/100-base-T ethernet interface.
+- A 32 char two line LCD display. (except for the LX200)
+
+LX60/LX110/LX200:
+
+- Virtex-4 (XC4VLX60 / XCV4LX200) / Virtext-5 (XC5VLX110)
+- 128MB / 64MB (LX60) memory
+- 16MB / 4MB (LX60) Linear Flash
+
+ML605
+
+- Virtex-6 (XC6VLX240T)
+- 512MB DDR3 memory
+- 16MB Linear BPI Flash
+
+KC705 (Xilinx)
+
+- Kintex-7 XC7K325T FPGA
+- 1GB DDR3 memory
+- 128MB Linear BPI Flash
+
+
+Setting up the Board
+--------------------
+
+The serial port defaults to 115200 baud, no parity and 1 stop bit.
+A terminal emulator must be set accordingly to see the U-Boot prompt.
+
+
+Board Configurations LX60/LX110/LX200/ML605/KC705
+-------------------------------------------------
+
+The LX60/LX110/LX200/ML605 contain an 8-way DIP switch that controls
+the boot mapping and selects from a range of default ethernet MAC
+addresses.
+
+Boot Mapping (DIP switch 8):
+
+    DIP switch 8 maps the system ROM address space (in which the
+    reset vector resides) to either SRAM (off, 0, down) or Flash
+    (on, 1, up).  This mapping is implemented in the FPGA bitstream
+    and cannot be disabled by software, therefore DIP switch 8 is no
+    available for application use. Note DIP switch 7 is reserved by
+    Tensilica for future possible hardware use.
+
+    Mapping to SRAM allows U-Boot to be debugged with an OCD/JTAG
+    tool such as the Xtensa OCD Daemon connected via a suppored probe.
+    See the tools documentation for supported probes and how to
+    connect them.  Be aware that the board has only 128 KB of SRAM,
+    therefore U-Boot must fit within this space to debug an image
+    intended for the Flash.  This issues is discussed in a separate
+    section toward the end.
+
+    Mapping to flash allows U-Boot to start on reset, provided it
+    has been programmed into the first two 64 KB sectors of the Flash.
+
+    The Flash is always mapped at a device (memory mapped I/O) address
+    (the address is board specific and is expressed as CFG_FLASH_BASE).
+    The device address is used by U-Boot to program the flash, and may
+    be used to specify an application to run or U-Boot image to boot.
+
+Default MAC Address (DIP switches 1-6):
+
+    When the board is first powered on, or after the environment has
+    been reinitialized, the ethernet MAC address receives a default
+    value whose least significant 6 bits come from DIP switches 1-6.
+    The default is 00:50:C2:13:6F:xx where xx ranges from 0..3F
+    according to the DIP switches, where "on"==1 and "off"==0, and
+    switch 1 is the least-significant bit.
+
+    After initial startup, the MAC address is stored in the U-Boot
+    environment variable 'ethaddr'. The user may change this to any
+    other address with the "setenv" comamnd. After the environment
+    has been saved to Flash by the "saveenv" command, this will be
+    used and the DIP switches no longer consulted. DIP swithes 1-6
+    may then be used for application purposes.
+
+The KC705 board contains 4-way DIP switch, way 1 is the boot mapping
+switch and ways 2-4 control the low three bits of the MAC address.
+
+
+Limitation of SDRAM Size for OCD Debugging on the LX60
+------------------------------------------------------
+
+The XT-AV60 board has only 128 KB of SDRAM that can be mapped
+to the system ROM address space for debugging a ROM image under
+OCD/JTAG. This limits the useful size of U-Boot to 128 KB (0x20000)
+or the first 2 sectors of the flash.
+
+This can pose a problem if all the sources are compiled with -O0
+for debugging. The code size is then too large, in which case it
+would be necessary to temporarily alter the linker script to place
+the load addresses (LMA) in the RAM (VMA) so that OCD loads U-Boot
+directly there and does not unpack. In practice this is not really
+necessary as long as only a limited set of sources need to be
+debugged, because the image can still fit into the 128 KB SRAM.
+
+The recommended procedure for debugging is to first build U-Boot
+with the default optimization level (-Os), and then touch and
+rebuild incrementally with -O0 so that only the touched sources
+are recompiled with -O0. To build with -O0, pass it in the KCFLAGS
+variable to make.
+
+Because this problem is easy to fall into and difficult to debug
+if one doesn't expect it, the linker script provides a link-time
+check and fatal error message if the image size exceeds 128 KB.
+
diff --git a/roms/u-boot/board/cadence/xtfpga/xtfpga.c b/roms/u-boot/board/cadence/xtfpga/xtfpga.c
new file mode 100644
index 000000000..c26793d76
--- /dev/null
+++ b/roms/u-boot/board/cadence/xtfpga/xtfpga.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007 - 2013 Tensilica Inc.
+ * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <init.h>
+#include <dm/platform_data/net_ethoc.h>
+#include <env.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/stringify.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Check board idendity.
+ * (Print information about the board to stdout.)
+ */
+
+
+#if defined(CONFIG_XTFPGA_LX60)
+const char *board = "XT_AV60";
+const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
+#elif defined(CONFIG_XTFPGA_LX110)
+const char *board = "XT_AV110";
+const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
+#elif defined(CONFIG_XTFPGA_LX200)
+const char *board = "XT_AV200";
+const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
+#elif defined(CONFIG_XTFPGA_ML605)
+const char *board = "XT_ML605";
+const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
+#elif defined(CONFIG_XTFPGA_KC705)
+const char *board = "XT_KC705";
+const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
+#else
+const char *board = "<unknown>";
+const char *description = "";
+#endif
+
+int checkboard(void)
+{
+	printf("Board: %s: %sTensilica bitstream\n", board, description);
+	return 0;
+}
+
+int board_postclk_init(void)
+{
+	/*
+	 * Obtain CPU clock frequency from board and cache in global
+	 * data structure (Hz). Return 0 on success (OK to continue),
+	 * else non-zero (hang).
+	 */
+
+#ifdef CONFIG_SYS_FPGAREG_FREQ
+	gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
+#else
+	/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
+	gd->cpu_clk = 50000000UL;
+#endif
+	return 0;
+}
+
+/*
+ *  Miscellaneous late initializations.
+ *  The environment has been set up, so we can set the Ethernet address.
+ */
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_NET
+	/*
+	 * Initialize ethernet environment variables and board info.
+	 * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
+	 */
+
+	char *s = env_get("ethaddr");
+	if (s == 0) {
+		unsigned int x;
+		char s[] = __stringify(CONFIG_ETHBASE);
+		x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW)
+			& FPGAREG_MAC_MASK;
+		sprintf(&s[15], "%02x", x);
+		env_set("ethaddr", s);
+	}
+#endif /* CONFIG_CMD_NET */
+
+	return 0;
+}
+
+U_BOOT_DRVINFO(sysreset) = {
+	.name = "xtfpga_sysreset",
+};
+
+static struct ethoc_eth_pdata ethoc_pdata = {
+	.eth_pdata = {
+		.iobase = CONFIG_SYS_ETHOC_BASE,
+	},
+	.packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
+};
+
+U_BOOT_DRVINFO(ethoc) = {
+	.name = "ethoc",
+	.plat = &ethoc_pdata,
+};
diff --git a/roms/u-boot/board/calao/usb_a9263/Kconfig b/roms/u-boot/board/calao/usb_a9263/Kconfig
new file mode 100644
index 000000000..19e446ded
--- /dev/null
+++ b/roms/u-boot/board/calao/usb_a9263/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_USB_A9263
+
+config SYS_BOARD
+	default "usb_a9263"
+
+config SYS_VENDOR
+	default "calao"
+
+config SYS_CONFIG_NAME
+	default "usb_a9263"
+
+endif
diff --git a/roms/u-boot/board/calao/usb_a9263/MAINTAINERS b/roms/u-boot/board/calao/usb_a9263/MAINTAINERS
new file mode 100644
index 000000000..2f39cd3de
--- /dev/null
+++ b/roms/u-boot/board/calao/usb_a9263/MAINTAINERS
@@ -0,0 +1,6 @@
+USB_A9263 BOARD
+M:	Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+S:	Maintained
+F:	board/calao/usb_a9263/
+F:	include/configs/usb_a9263.h
+F:	configs/usb_a9263_dataflash_defconfig
diff --git a/roms/u-boot/board/calao/usb_a9263/Makefile b/roms/u-boot/board/calao/usb_a9263/Makefile
new file mode 100644
index 000000000..2d8f1401a
--- /dev/null
+++ b/roms/u-boot/board/calao/usb_a9263/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+#
+
+obj-y	+= usb_a9263.o
diff --git a/roms/u-boot/board/calao/usb_a9263/usb_a9263.c b/roms/u-boot/board/calao/usb_a9263/usb_a9263.c
new file mode 100644
index 000000000..c0a5c518c
--- /dev/null
+++ b/roms/u-boot/board/calao/usb_a9263/usb_a9263.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2013
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
+ * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm-generic/gpio.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static void usb_a9263_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0;
+	at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
+
+	/* Configure RDY/BSY */
+	gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+	/* Enable NandFlash */
+	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void usb_a9263_macb_hw_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *  RXDV (PC25) => PHY normal mode (not Test mode)
+	 *  ERX0 (PE25) => PHY ADDR0
+	 *  ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal weak pull-up/pull-down
+	 */
+	gpio_request(GPIO_PIN_PC(25), "PHY mode");
+	gpio_direction_input(GPIO_PIN_PC(25));
+
+	gpio_request(GPIO_PIN_PE(25), "PHY ADDR0");
+	gpio_direction_input(GPIO_PIN_PE(25));
+
+	gpio_request(GPIO_PIN_PE(26), "PHY ADDR1");
+	gpio_direction_input(GPIO_PIN_PE(26));
+
+	at91_phy_reset();
+
+	/* It will set proper pinmux for ports PC25, PE25-26 */
+	at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	usb_a9263_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	usb_a9263_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x0001);
+#endif
+	return rc;
+}
diff --git a/roms/u-boot/board/cavium/thunderx/Kconfig b/roms/u-boot/board/cavium/thunderx/Kconfig
new file mode 100644
index 000000000..927d8765d
--- /dev/null
+++ b/roms/u-boot/board/cavium/thunderx/Kconfig
@@ -0,0 +1,27 @@
+if TARGET_THUNDERX_88XX
+
+config SYS_CPU
+	string
+	default "armv8"
+
+config SYS_BOARD
+	string
+	default "thunderx"
+
+config SYS_VENDOR
+	string
+	default "cavium"
+
+config SYS_CONFIG_NAME
+	string
+	default "thunderx_88xx"
+
+config CMD_ATF
+	bool "Enable ATF query commands"
+	default y
+	help
+	  Enable vendor specific ATF query commands such as SPI and SD/MMC
+	  devices access, low level environment query, boot device layout
+	  and node count.
+
+endif
diff --git a/roms/u-boot/board/cavium/thunderx/MAINTAINERS b/roms/u-boot/board/cavium/thunderx/MAINTAINERS
new file mode 100644
index 000000000..c84d3b553
--- /dev/null
+++ b/roms/u-boot/board/cavium/thunderx/MAINTAINERS
@@ -0,0 +1,6 @@
+THUNDERX BOARD
+M:	Sergey Temerkhanov <s.temerkhanov@gmail.com>
+S:	Maintained
+F:	board/cavium/thunderx/
+F:	include/configs/thunderx_88xx.h
+F:	configs/thunderx_88xx_defconfig
diff --git a/roms/u-boot/board/cavium/thunderx/Makefile b/roms/u-boot/board/cavium/thunderx/Makefile
new file mode 100644
index 000000000..4088c7678
--- /dev/null
+++ b/roms/u-boot/board/cavium/thunderx/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2014, Cavium Inc.
+#
+#
+
+obj-y	:= thunderx.o atf.o
diff --git a/roms/u-boot/board/cavium/thunderx/atf.c b/roms/u-boot/board/cavium/thunderx/atf.c
new file mode 100644
index 000000000..64aa19876
--- /dev/null
+++ b/roms/u-boot/board/cavium/thunderx/atf.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * (C) Copyright 2014, Cavium Inc.
+**/
+
+#include <common.h>
+#include <command.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/ptrace.h>
+
+#include <asm/system.h>
+#include <cavium/thunderx_svc.h>
+#include <cavium/atf.h>
+#include <cavium/atf_part.h>
+
+#include <asm/psci.h>
+
+#include <malloc.h>
+
+ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size)
+{
+	struct pt_regs regs;
+	regs.regs[0] = THUNDERX_MMC_READ;
+	regs.regs[1] = offset;
+	regs.regs[2] = size;
+	regs.regs[3] = (uintptr_t)buffer;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size)
+{
+	struct pt_regs regs;
+	regs.regs[0] = THUNDERX_NOR_READ;
+	regs.regs[1] = offset;
+	regs.regs[2] = size;
+	regs.regs[3] = (uintptr_t)buffer;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t atf_get_pcount(void)
+{
+	struct pt_regs regs;
+	regs.regs[0] = THUNDERX_PART_COUNT;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t atf_get_part(struct storage_partition *part, unsigned int index)
+{
+	struct pt_regs regs;
+	regs.regs[0] = THUNDERX_GET_PART;
+	regs.regs[1] = (uintptr_t)part;
+	regs.regs[2] = index;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t atf_erase_nor(uintptr_t offset, size_t size)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = THUNDERX_NOR_ERASE;
+	regs.regs[1] = offset;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = THUNDERX_NOR_WRITE;
+	regs.regs[1] = offset;
+	regs.regs[2] = size;
+	regs.regs[3] = (uintptr_t)buffer;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = THUNDERX_MMC_WRITE;
+	regs.regs[1] = offset;
+	regs.regs[2] = size;
+	regs.regs[3] = (uintptr_t)buffer;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t atf_dram_size(unsigned int node)
+{
+	struct pt_regs regs;
+	regs.regs[0] = THUNDERX_DRAM_SIZE;
+	regs.regs[1] = node;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t atf_node_count(void)
+{
+	struct pt_regs regs;
+	regs.regs[0] = THUNDERX_NODE_COUNT;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t atf_env_count(void)
+{
+	struct pt_regs regs;
+	regs.regs[0] = THUNDERX_ENV_COUNT;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+ssize_t atf_env_string(size_t index, char *str)
+{
+	uint64_t *buf = (void *)str;
+	struct pt_regs regs;
+	regs.regs[0] = THUNDERX_ENV_STRING;
+	regs.regs[1] = index;
+
+	smc_call(&regs);
+
+	if (regs.regs > 0) {
+		buf[0] = regs.regs[0];
+		buf[1] = regs.regs[1];
+		buf[2] = regs.regs[2];
+		buf[3] = regs.regs[3];
+
+		return 1;
+	} else {
+		return regs.regs[0];
+	}
+}
+
+#ifdef CONFIG_CMD_ATF
+
+static void atf_print_ver(void)
+{
+	struct pt_regs regs;
+	regs.regs[0] = ARM_STD_SVC_VERSION;
+
+	smc_call(&regs);
+
+	printf("ARM Std FW version: %ld.%ld\n", regs.regs[0], regs.regs[1]);
+
+	regs.regs[0] = THUNDERX_SVC_VERSION;
+
+	smc_call(&regs);
+
+	printf("ThunderX OEM ver: %ld.%ld\n", regs.regs[0], regs.regs[1]);
+}
+
+static void atf_print_uid(void)
+{
+}
+
+static void atf_print_part_table(void)
+{
+	size_t pcount;
+	unsigned long i;
+	int ret;
+	char *ptype;
+
+	struct storage_partition *part = (void *)CONFIG_SYS_LOWMEM_BASE;
+
+	pcount = atf_get_pcount();
+
+	printf("Partition count: %lu\n\n", pcount);
+	printf("%10s %10s %10s\n", "Type", "Size", "Offset");
+
+	for (i = 0; i < pcount; i++) {
+		ret = atf_get_part(part, i);
+
+		if (ret < 0) {
+			printf("Uknown error while reading partition: %d\n",
+			       ret);
+			return;
+		}
+
+		switch (part->type) {
+		case PARTITION_NBL1FW_REST:
+			ptype = "NBL1FW";
+			break;
+		case PARTITION_BL2_BL31:
+			ptype = "BL2_BL31";
+			break;
+		case PARTITION_UBOOT:
+			ptype = "BOOTLDR";
+			break;
+		case PARTITION_KERNEL:
+			ptype = "KERNEL";
+			break;
+		case PARTITION_DEVICE_TREE:
+			ptype = "DEVTREE";
+			break;
+		default:
+			ptype = "UNKNOWN";
+		}
+		printf("%10s %10d %10lx\n", ptype, part->size, part->offset);
+	}
+}
+
+int do_atf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	ssize_t ret;
+	size_t size, offset;
+	void *buffer = 0;
+	unsigned int index, node;
+	char str[4 * sizeof(uint64_t)];
+
+	if ((argc == 5) && !strcmp(argv[1], "readmmc")) {
+		buffer = (void *)simple_strtoul(argv[2], NULL, 16);
+		offset = simple_strtoul(argv[3], NULL, 10);
+		size = simple_strtoul(argv[4], NULL, 10);
+
+		ret = atf_read_mmc(offset, buffer, size);
+	} else if ((argc == 5) && !strcmp(argv[1], "readnor")) {
+		buffer = (void *)simple_strtoul(argv[2], NULL, 16);
+		offset = simple_strtoul(argv[3], NULL, 10);
+		size = simple_strtoul(argv[4], NULL, 10);
+
+		ret = atf_read_nor(offset, buffer, size);
+	} else if ((argc == 5) && !strcmp(argv[1], "writemmc")) {
+		buffer = (void *)simple_strtoul(argv[2], NULL, 16);
+		offset = simple_strtoul(argv[3], NULL, 10);
+		size = simple_strtoul(argv[4], NULL, 10);
+
+		ret = atf_write_mmc(offset, buffer, size);
+	} else if ((argc == 5) && !strcmp(argv[1], "writenor")) {
+		buffer = (void *)simple_strtoul(argv[2], NULL, 16);
+		offset = simple_strtoul(argv[3], NULL, 10);
+		size = simple_strtoul(argv[4], NULL, 10);
+
+		ret = atf_write_nor(offset, buffer, size);
+	} else if ((argc == 2) && !strcmp(argv[1], "part")) {
+		atf_print_part_table();
+	} else if ((argc == 4) && !strcmp(argv[1], "erasenor")) {
+		offset = simple_strtoul(argv[2], NULL, 10);
+		size = simple_strtoul(argv[3], NULL, 10);
+
+		ret = atf_erase_nor(offset, size);
+	} else if ((argc == 2) && !strcmp(argv[1], "envcount")) {
+		ret = atf_env_count();
+		printf("Number of environment strings: %zd\n", ret);
+	} else if ((argc == 3) && !strcmp(argv[1], "envstring")) {
+		index = simple_strtoul(argv[2], NULL, 10);
+		ret = atf_env_string(index, str);
+		if (ret > 0)
+			printf("Environment string %d: %s\n", index, str);
+		else
+			printf("Return code: %zd\n", ret);
+	} else if ((argc == 3) && !strcmp(argv[1], "dramsize")) {
+		node = simple_strtoul(argv[2], NULL, 10);
+		ret = atf_dram_size(node);
+		printf("DRAM size: %zd Mbytes\n", ret >> 20);
+	} else if ((argc == 2) && !strcmp(argv[1], "nodes")) {
+		ret = atf_node_count();
+		printf("Nodes count: %zd\n", ret);
+	} else if ((argc == 2) && !strcmp(argv[1], "ver")) {
+		atf_print_ver();
+	} else if ((argc == 2) && !strcmp(argv[1], "uid")) {
+		atf_print_uid();
+	} else {
+		return CMD_RET_USAGE;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	atf,   10,   1,     do_atf,
+	"issue calls to ATF",
+	"\t readmmc addr offset size - read MMC card\n"
+	"\t readnor addr offset size - read NOR flash\n"
+	"\t writemmc addr offset size - write MMC card\n"
+	"\t writenor addr offset size - write NOR flash\n"
+	"\t erasenor offset size - erase NOR flash\n"
+	"\t nodes - number of nodes\n"
+	"\t dramsize node - size of DRAM attached to node\n"
+	"\t envcount - number of environment strings\n"
+	"\t envstring index - print the environment string\n"
+	"\t part - print MMC partition table\n"
+	"\t ver - print ATF call set versions\n"
+);
+
+#endif
diff --git a/roms/u-boot/board/cavium/thunderx/thunderx.c b/roms/u-boot/board/cavium/thunderx/thunderx.c
new file mode 100644
index 000000000..a7dc5c6ae
--- /dev/null
+++ b/roms/u-boot/board/cavium/thunderx/thunderx.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * (C) Copyright 2014, Cavium Inc.
+**/
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <linux/compiler.h>
+
+#include <cavium/atf.h>
+#include <asm/armv8/mmu.h>
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#include <dm/platform_data/serial_pl01x.h>
+
+static const struct pl01x_serial_plat serial0 = {
+	.base = CONFIG_SYS_SERIAL0,
+	.type = TYPE_PL011,
+	.clock = 0,
+	.skip_init = true,
+};
+
+U_BOOT_DRVINFO(thunderx_serial0) = {
+	.name = "serial_pl01x",
+	.plat = &serial0,
+};
+
+static const struct pl01x_serial_plat serial1 = {
+	.base = CONFIG_SYS_SERIAL1,
+	.type = TYPE_PL011,
+	.clock = 0,
+	.skip_init = true,
+};
+
+U_BOOT_DRVINFO(thunderx_serial1) = {
+	.name = "serial_pl01x",
+	.plat = &serial1,
+};
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region thunderx_mem_map[] = {
+	{
+		.virt = 0x000000000000UL,
+		.phys = 0x000000000000UL,
+		.size = 0x40000000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
+	}, {
+		.virt = 0x800000000000UL,
+		.phys = 0x800000000000UL,
+		.size = 0x40000000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE,
+	}, {
+		.virt = 0x840000000000UL,
+		.phys = 0x840000000000UL,
+		.size = 0x40000000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE,
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = thunderx_mem_map;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int timer_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	ssize_t node_count = atf_node_count();
+	ssize_t dram_size;
+	int node;
+
+	printf("Initializing\nNodes in system: %zd\n", node_count);
+
+	gd->ram_size = 0;
+
+	for (node = 0; node < node_count; node++) {
+		dram_size = atf_dram_size(node);
+		printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
+		gd->ram_size += dram_size;
+	}
+
+	gd->ram_size -= MEM_BASE;
+
+	*(unsigned long *)CPU_RELEASE_ADDR = 0;
+
+	puts("DRAM size:");
+
+	return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+}
+
+/*
+ * Board specific ethernet initialization routine.
+ */
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+
+	return rc;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	printf("DEBUG: PCI Init TODO *****\n");
+}
+#endif
diff --git a/roms/u-boot/board/cei/cei-tk1-som/Kconfig b/roms/u-boot/board/cei/cei-tk1-som/Kconfig
new file mode 100644
index 000000000..5fcb51f2f
--- /dev/null
+++ b/roms/u-boot/board/cei/cei-tk1-som/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CEI_TK1_SOM
+
+config SYS_BOARD
+	default "cei-tk1-som"
+
+config SYS_VENDOR
+	default "cei"
+
+config SYS_CONFIG_NAME
+	default "cei-tk1-som"
+
+endif
diff --git a/roms/u-boot/board/cei/cei-tk1-som/MAINTAINERS b/roms/u-boot/board/cei/cei-tk1-som/MAINTAINERS
new file mode 100644
index 000000000..192e1a34a
--- /dev/null
+++ b/roms/u-boot/board/cei/cei-tk1-som/MAINTAINERS
@@ -0,0 +1,6 @@
+TK1-SOM BOARD
+M:	Peter.Chubb@data61.csiro.au
+S:	Maintained
+F:	board/cei/tk1-som/
+F:	include/configs/cei-tk1-som.h
+F:	configs/cei-tk1-som_defconfig
diff --git a/roms/u-boot/board/cei/cei-tk1-som/Makefile b/roms/u-boot/board/cei/cei-tk1-som/Makefile
new file mode 100644
index 000000000..127b1043a
--- /dev/null
+++ b/roms/u-boot/board/cei/cei-tk1-som/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= ../../nvidia/venice2/as3722_init.o
+obj-y	+= cei-tk1-som.o
diff --git a/roms/u-boot/board/cei/cei-tk1-som/cei-tk1-som.c b/roms/u-boot/board/cei/cei-tk1-som/cei-tk1-som.c
new file mode 100644
index 000000000..95ee7bbfe
--- /dev/null
+++ b/roms/u-boot/board/cei/cei-tk1-som/cei-tk1-som.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#include <common.h>
+#include <power/as3722.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+
+#include "pinmux-config-cei-tk1-som.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_clear_tristate_input_clamping();
+
+	gpio_config_table(cei_tk1_som_gpio_inits,
+			  ARRAY_SIZE(cei_tk1_som_gpio_inits));
+
+	pinmux_config_pingrp_table(cei_tk1_som_pingrps,
+				   ARRAY_SIZE(cei_tk1_som_pingrps));
+
+	pinmux_config_drvgrp_table(cei_tk1_som_drvgrps,
+				   ARRAY_SIZE(cei_tk1_som_drvgrps));
+
+	pinmux_config_mipipadctrlgrp_table(cei_tk1_som_mipipadctrlgrps,
+                                           ARRAY_SIZE(cei_tk1_som_mipipadctrlgrps));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+/* TODO: Convert to driver model
+	struct udevice *pmic;
+	int err;
+
+	err = as3722_init(&pmic);
+	if (err) {
+		error("failed to initialize AS3722 PMIC: %d\n", err);
+		return err;
+	}
+
+	err = as3722_sd_enable(pmic, 4);
+	if (err < 0) {
+		error("failed to enable SD4: %d\n", err);
+		return err;
+	}
+
+	err = as3722_sd_set_voltage(pmic, 4, 0x24);
+	if (err < 0) {
+		error("failed to set SD4 voltage: %d\n", err);
+		return err;
+	}
+*/
+
+	return 0;
+}
+#endif /* PCI */
diff --git a/roms/u-boot/board/cei/cei-tk1-som/pinmux-config-cei-tk1-som.h b/roms/u-boot/board/cei/cei-tk1-som/pinmux-config-cei-tk1-som.h
new file mode 100644
index 000000000..eff52cf94
--- /dev/null
+++ b/roms/u-boot/board/cei/cei-tk1-som/pinmux-config-cei-tk1-som.h
@@ -0,0 +1,300 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ */
+
+/*
+ * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
+ *
+ * To generate this file, use the tegra-pinmux-scripts tool available from
+ * https://github.com/NVIDIA/tegra-pinmux-scripts
+ * Run "board-to-uboot.py cei-tk1-som".
+ */
+
+#ifndef _PINMUX_CONFIG_CEI_TK1_SOM_H_
+#define _PINMUX_CONFIG_CEI_TK1_SOM_H_
+
+#define GPIO_INIT(_port, _gpio, _init)			\
+	{						\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
+		.init	= TEGRA_GPIO_INIT_##_init,	\
+	}
+
+static const struct tegra_gpio_config cei_tk1_som_gpio_inits[] = {
+	/*        port, pin, init_val */
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(G,    4,   IN),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    7,   IN),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    3,   IN),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(J,    2,   IN),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(O,    1,   IN),
+	GPIO_INIT(O,    4,   IN),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(R,    0,   IN),
+	GPIO_INIT(R,    2,   OUT0),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(R,    6,   IN),
+	GPIO_INIT(S,    2,   IN),
+	GPIO_INIT(S,    3,   IN),
+	GPIO_INIT(S,    4,   IN),
+	GPIO_INIT(S,    5,   IN),
+	GPIO_INIT(S,    6,   IN),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    0,   IN),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(V,    1,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(BB,   3,   OUT0),
+	GPIO_INIT(BB,   6,   OUT0),
+	GPIO_INIT(BB,   7,   OUT0),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   2,   IN),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+static const struct pmux_pingrp_config cei_tk1_som_pingrps[] = {
+	/*     pingrp,                 mux,         pull,   tri,      e_input, od,      rcv_sel */
+	PINCFG(CLK_32K_OUT_PA0,        SOC,         UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_CTS_N_PA1,        GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP2_FS_PA2,            I2S1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP2_SCLK_PA3,          I2S1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP2_DIN_PA4,           I2S1,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_DOUT_PA5,          I2S1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_PA6,         SDMMC3,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CMD_PA7,         SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PB0,                    UARTD,       UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PB1,                    UARTD,       UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT3_PB4,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT2_PB5,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT1_PB6,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT0_PB7,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_RTS_N_PC0,        GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_TXD_PC2,          IRDA,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_RXD_PC3,          IRDA,        UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GEN1_I2C_SCL_PC4,       I2C1,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN1_I2C_SDA_PC5,       I2C1,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PC7,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG0,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG1,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG2,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG3,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG4,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG5,                    SPI4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG6,                    SPI4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG7,                    SPI4,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH0,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH1,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH2,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH3,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH4,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH5,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH6,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH7,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI0,                    DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI1,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI2,                    RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI3,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI4,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI5,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI6,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI7,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ0,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PJ2,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART2_CTS_N_PJ5,        UARTB,       UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART2_RTS_N_PJ6,        UARTB,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ7,                    UARTD,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK0,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK1,                    RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK2,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PK3,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK4,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_OUT_PK5,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_IN_PK6,           DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK7,                    UARTD,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_FS_PN0,            RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_DIN_PN1,           RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_DOUT_PN2,          I2S0,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_SCLK_PN3,          RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN0_PN4,       USB,         NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(USB_VBUS_EN1_PN5,       USB,         NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(HDMI_INT_PN7,           DEFAULT,     DOWN,   TRISTATE, INPUT,   DEFAULT, NORMAL),
+	PINCFG(ULPI_DATA7_PO0,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA0_PO1,         DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA1_PO2,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA2_PO3,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA3_PO4,         DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA4_PO5,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA5_PO6,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA6_PO7,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_FS_PP0,            I2S2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_DIN_PP1,           I2S2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_DOUT_PP2,          RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_SCLK_PP3,          RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_FS_PP4,            RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DIN_PP5,           RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DOUT_PP6,          RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_SCLK_PP7,          RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL0_PQ0,            DEFAULT,     UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL1_PQ1,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL2_PQ2,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL3_PQ3,            DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL4_PQ4,            KBC,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL5_PQ5,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL6_PQ6,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL7_PQ7,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW0_PR0,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW1_PR1,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW2_PR2,            DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW3_PR3,            KBC,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW4_PR4,            DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW5_PR5,            RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW6_PR6,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW7_PR7,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW8_PS0,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW9_PS1,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW10_PS2,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW11_PS3,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW12_PS4,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW13_PS5,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW14_PS6,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW15_PS7,           DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW16_PT0,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW17_PT1,           DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GEN2_I2C_SCL_PT5,       I2C2,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN2_I2C_SDA_PT6,       I2C2,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_CMD_PT7,         SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU0,                    RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU1,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU2,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU3,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU4,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU5,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU6,                    RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PV0,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PV1,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CD_N_PV2,        RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_WP_N_PV3,        SDMMC1,      DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DDC_SCL_PV4,            I2C4,        NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+	PINCFG(DDC_SDA_PV5,            I2C4,        NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+	PINCFG(GPIO_W2_AUD_PW2,        RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_W3_AUD_PW3,        SPI6,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_PW4,          EXTPERIPH1,  NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK2_OUT_PW5,           RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART3_TXD_PW6,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART3_RXD_PW7,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DVFS_PWM_PX0,           CLDVFS,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X1_AUD_PX1,        DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DVFS_CLK_PX2,           CLDVFS,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X3_AUD_PX3,        RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X4_AUD_PX4,        DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GPIO_X5_AUD_PX5,        RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X6_AUD_PX6,        GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X7_AUD_PX7,        RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_CLK_PY0,           SPI1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DIR_PY1,           SPI1,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_NXT_PY2,           SPI1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_STP_PY3,           SPI1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT3_PY4,        SDMMC1,      DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT2_PY5,        SDMMC1,      DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT1_PY6,        SDMMC1,      DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT0_PY7,        RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CLK_PZ0,         RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CMD_PZ1,         SDMMC1,      DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PWR_I2C_SCL_PZ6,        I2CPWR,      NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PWR_I2C_SDA_PZ7,        I2CPWR,      NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_DAT0_PAA0,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT1_PAA1,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT2_PAA2,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT3_PAA3,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT4_PAA4,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT5_PAA5,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT6_PAA6,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT7_PAA7,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PBB0,                   VIMCLK2_ALT, NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CAM_I2C_SCL_PBB1,       I2C3,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(CAM_I2C_SDA_PBB2,       I2C3,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PBB3,                   DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB4,                   VGP4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB5,                   RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB6,                   DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB7,                   DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CAM_MCLK_PCC0,          VI_ALT3,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PCC1,                   DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PCC2,                   DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_CLK_PCC4,        SDMMC4,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK2_REQ_PCC5,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_RST_N_PDD1,      PE0,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_CLKREQ_N_PDD2,   PE0,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_WAKE_N_PDD3,        PE,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_RST_N_PDD5,      PE1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_CLKREQ_N_PDD6,   PE1,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK3_OUT_PEE0,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK3_REQ_PEE1,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_REQ_PEE2,     RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(HDMI_CEC_PEE3,          CEC,         NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DP_HPD_PFF0,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN2_PFF1,      RSVD2,       DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(PFF2,                   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(CORE_PWR_REQ,           PWRON,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CPU_PWR_REQ,            CPU,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PWR_INT_N,              PMI,         UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(RESET_OUT_N,            RESET_OUT_N, NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK_32K_IN,             CLK,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(JTAG_RTCK,              RTCK,        UP,     NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{						\
+		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
+		.slwf   = _slwf,			\
+		.slwr   = _slwr,			\
+		.drvup  = _drvup,			\
+		.drvdn  = _drvdn,			\
+		.lpmd   = PMUX_LPMD_##_lpmd,		\
+		.schmt  = PMUX_SCHMT_##_schmt,		\
+		.hsm    = PMUX_HSM_##_hsm,		\
+	}
+
+static const struct pmux_drvgrp_config cei_tk1_som_drvgrps[] = {
+};
+
+#define MIPIPADCTRLCFG(_grp, _mux) \
+	{							\
+		.grp		= PMUX_MIPIPADCTRLGRP_##_grp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+	}
+
+static const struct pmux_mipipadctrlgrp_config cei_tk1_som_mipipadctrlgrps[] = {
+	/*             grp,   mux */
+	MIPIPADCTRLCFG(DSI_B, DSI_B),
+};
+
+#endif /* PINMUX_CONFIG_CEI_TK1_SOM_H */
diff --git a/roms/u-boot/board/chipspark/popmetal_rk3288/Kconfig b/roms/u-boot/board/chipspark/popmetal_rk3288/Kconfig
new file mode 100644
index 000000000..a5f404306
--- /dev/null
+++ b/roms/u-boot/board/chipspark/popmetal_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_POPMETAL_RK3288
+
+config SYS_BOARD
+	default "popmetal_rk3288"
+
+config SYS_VENDOR
+	default "chipspark"
+
+config SYS_CONFIG_NAME
+	default "popmetal_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/chipspark/popmetal_rk3288/MAINTAINERS b/roms/u-boot/board/chipspark/popmetal_rk3288/MAINTAINERS
new file mode 100644
index 000000000..1a6a1bb2c
--- /dev/null
+++ b/roms/u-boot/board/chipspark/popmetal_rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+POPMETAL-RK3288
+M:	Lin Huang <hl@rock-chips.com>
+S:	Maintained
+F:	board/chipspark/popmetal_rk3288
+F:	include/configs/popmetal_rk3288.h
+F:	configs/popmetal-rk3288_defconfig
diff --git a/roms/u-boot/board/chipspark/popmetal_rk3288/Makefile b/roms/u-boot/board/chipspark/popmetal_rk3288/Makefile
new file mode 100644
index 000000000..86d66b0bf
--- /dev/null
+++ b/roms/u-boot/board/chipspark/popmetal_rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= popmetal-rk3288.o
diff --git a/roms/u-boot/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/roms/u-boot/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
new file mode 100644
index 000000000..e6909b3b1
--- /dev/null
+++ b/roms/u-boot/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/gpio.h>
+
+#define GPIO7A3_HUB_RST	227
+
+int rk3288_board_late_init(void)
+{
+	int ret;
+
+	ret = gpio_request(GPIO7A3_HUB_RST, "hub_rst");
+	if (ret)
+		return ret;
+	ret = gpio_direction_output(GPIO7A3_HUB_RST, 1);
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/cirrus/edb93xx/Kconfig b/roms/u-boot/board/cirrus/edb93xx/Kconfig
new file mode 100644
index 000000000..c5f4897f8
--- /dev/null
+++ b/roms/u-boot/board/cirrus/edb93xx/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EDB93XX
+
+config SYS_BOARD
+	default "edb93xx"
+
+config SYS_VENDOR
+	default "cirrus"
+
+config SYS_SOC
+	default "ep93xx"
+
+config SYS_CONFIG_NAME
+	default "edb93xx"
+
+endif
diff --git a/roms/u-boot/board/cirrus/edb93xx/MAINTAINERS b/roms/u-boot/board/cirrus/edb93xx/MAINTAINERS
new file mode 100644
index 000000000..3bb284335
--- /dev/null
+++ b/roms/u-boot/board/cirrus/edb93xx/MAINTAINERS
@@ -0,0 +1,6 @@
+EDB93XX BOARD
+M:	Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
+S:	Maintained
+F:	board/cirrus/edb93xx/
+F:	include/configs/edb93xx.h
+F:	configs/edb9315a_defconfig
diff --git a/roms/u-boot/board/cirrus/edb93xx/Makefile b/roms/u-boot/board/cirrus/edb93xx/Makefile
new file mode 100644
index 000000000..0cf04b13b
--- /dev/null
+++ b/roms/u-boot/board/cirrus/edb93xx/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2013
+# Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
+#
+
+obj-y	:= edb93xx.o
diff --git a/roms/u-boot/board/cirrus/edb93xx/edb93xx.c b/roms/u-boot/board/cirrus/edb93xx/edb93xx.c
new file mode 100644
index 000000000..7a7f62fe8
--- /dev/null
+++ b/roms/u-boot/board/cirrus/edb93xx/edb93xx.c
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board initialization for EP93xx
+ *
+ * Copyright (C) 2013
+ * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+ *
+ * Copyright (C) 2009
+ * Matthias Kaehlcke <matthias <at> kaehlcke.net>
+ *
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson <at> netaudiotech.com>
+ */
+
+#include <config.h>
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <irq_func.h>
+#include <net.h>
+#include <netdev.h>
+#include <status_led.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/ep93xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * usb_div: 4, nbyp2: 1, pll2_en: 1
+ * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
+ * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
+ */
+#define CLKSET2_VAL	(23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |	\
+			24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |	\
+			24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |	\
+			1 << SYSCON_CLKSET_PLL_PS_SHIFT |	\
+			SYSCON_CLKSET2_PLL2_EN |		\
+			SYSCON_CLKSET2_NBYP2 |			\
+			3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
+
+#define SMC_BCR6_VALUE	(2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
+			SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
+			1 << SMC_BCR_MW_SHIFT)
+
+/* delay execution before timers are initialized */
+static inline void early_udelay(uint32_t usecs)
+{
+	/* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
+	register uint32_t loops = (usecs * 1000) / 20;
+
+	__asm__ volatile ("1:\n"
+			"subs %0, %1, #1\n"
+			"bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+#ifndef CONFIG_EP93XX_NO_FLASH_CFG
+static void flash_cfg(void)
+{
+	struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
+
+	writel(SMC_BCR6_VALUE, &smc->bcr6);
+}
+#else
+#define flash_cfg()
+#endif
+
+int board_init(void)
+{
+	/*
+	 * Setup PLL2, PPL1 has been set during lowlevel init
+	 */
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	writel(CLKSET2_VAL, &syscon->clkset2);
+
+	/*
+	 * the user's guide recommends to wait at least 1 ms for PLL2 to
+	 * stabilize
+	 */
+	early_udelay(1000);
+
+	/* Go to Async mode */
+	__asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
+	__asm__ volatile ("orr r0, r0, #0xc0000000");
+	__asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
+
+	icache_enable();
+
+#ifdef USE_920T_MMU
+	dcache_enable();
+#endif
+
+	/* Machine number, as defined in linux/arch/arm/tools/mach-types */
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* We have a console */
+	gd->have_console = 1;
+
+	enable_interrupts();
+
+	flash_cfg();
+
+	green_led_on();
+	red_led_off();
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
+	 * 14.7456/2 MHz
+	 */
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bd)
+{
+	return ep93xx_eth_initialize(0, MAC_BASE);
+}
+
+static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
+				unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
+{
+	if (dram_bank_cnt == 1) {
+		dram_bank_base[0] = PHYS_SDRAM_1;
+	} else {
+		/* Table lookup for holes in address space. Maximum memory
+		 * for the single SDCS may be up to 256Mb. We start scanning
+		 * banks from 1Mb, so it could be up to 128 banks theoretically.
+		 * We need at maximum 7 bits for the loockup, 8 slots is
+		 * enough for the worst case.
+		 */
+		unsigned tbl[8];
+		unsigned i = dram_bank_cnt / 2;
+		unsigned j = 0x00100000; /* 1 Mb */
+		unsigned *ptbl = tbl;
+		do {
+			while (!(dram_addr_mask & j)) {
+				j <<= 1;
+			}
+			*ptbl++ = j;
+			j <<= 1;
+			i >>= 1;
+		} while (i != 0);
+
+		for (i = dram_bank_cnt, j = 0;
+		     (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
+			unsigned addr = PHYS_SDRAM_1;
+			unsigned k;
+			unsigned bit;
+
+			for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
+				if (bit & j)
+					addr |= tbl[k];
+			}
+
+			dram_bank_base[j] = addr;
+		}
+	}
+}
+
+/* called in board_init_f (before relocation) */
+static unsigned dram_init_banksize_int(int print)
+{
+	/*
+	 * Collect information of banks that has been filled during lowlevel
+	 * initialization
+	 */
+	unsigned i;
+	unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
+	unsigned dram_total = 0;
+	unsigned dram_bank_size = *(unsigned *)
+				  (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
+	unsigned dram_addr_mask = *(unsigned *)
+				  (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
+	unsigned dram_bank_cnt = *(unsigned *)
+				 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
+
+	dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
+
+	for (i = 0; i < dram_bank_cnt; i++) {
+		gd->bd->bi_dram[i].start = dram_bank_base[i];
+		gd->bd->bi_dram[i].size = dram_bank_size;
+		dram_total += dram_bank_size;
+	}
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+
+	if (print) {
+		printf("DRAM mask: %08x\n", dram_addr_mask);
+		printf("DRAM total %u banks:\n", dram_bank_cnt);
+		printf("bank          base-address          size\n");
+
+		if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
+			printf("WARNING! UBoot was configured for %u banks,\n"
+				"but %u has been found. "
+				"Supressing extra memory banks\n",
+				 CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
+			dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
+		}
+
+		for (i = 0; i < dram_bank_cnt; i++) {
+			printf("  %u             %08x            %08x\n",
+			       i, dram_bank_base[i], dram_bank_size);
+		}
+		printf("  ------------------------------------------\n"
+			"Total                              %9d\n\n",
+			dram_total);
+	}
+
+	return dram_total;
+}
+
+int dram_init_banksize(void)
+{
+	dram_init_banksize_int(0);
+
+	return 0;
+}
+
+/* called in board_init_f (before relocation) */
+int dram_init(void)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	unsigned sec_id = readl(SECURITY_EXTENSIONID);
+	unsigned chip_id = readl(&syscon->chipid);
+
+	printf("CPU: Cirrus Logic ");
+	switch (sec_id & 0x000001FE) {
+	case 0x00000008:
+		printf("EP9301");
+		break;
+	case 0x00000004:
+		printf("EP9307");
+		break;
+	case 0x00000002:
+		printf("EP931x");
+		break;
+	case 0x00000000:
+		printf("EP9315");
+		break;
+	default:
+		printf("<unknown>");
+		break;
+	}
+
+	printf(" - Rev. ");
+	switch (chip_id & 0xF0000000) {
+	case 0x00000000:
+		printf("A");
+		break;
+	case 0x10000000:
+		printf("B");
+		break;
+	case 0x20000000:
+		printf("C");
+		break;
+	case 0x30000000:
+		printf("D0");
+		break;
+	case 0x40000000:
+		printf("D1");
+		break;
+	case 0x50000000:
+		printf("E0");
+		break;
+	case 0x60000000:
+		printf("E1");
+		break;
+	case 0x70000000:
+		printf("E2");
+		break;
+	default:
+		printf("?");
+		break;
+	}
+	printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
+
+	gd->ram_size = dram_init_banksize_int(1);
+	return 0;
+}
diff --git a/roms/u-boot/board/cirrus/edb93xx/u-boot.lds b/roms/u-boot/board/cirrus/edb93xx/u-boot.lds
new file mode 100644
index 000000000..db45c00e1
--- /dev/null
+++ b/roms/u-boot/board/cirrus/edb93xx/u-boot.lds
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *
+ * Copyright (C) 2013
+ * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+ *
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text : {
+		*(.__image_copy_start)
+		*(.vectors)
+		arch/arm/cpu/arm920t/start.o (.text*)
+		. = 0x1000;
+
+		LONG(0x53555243)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+	.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
+}
diff --git a/roms/u-boot/board/cloudengines/pogo_e02/Kconfig b/roms/u-boot/board/cloudengines/pogo_e02/Kconfig
new file mode 100644
index 000000000..eaa68d937
--- /dev/null
+++ b/roms/u-boot/board/cloudengines/pogo_e02/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_POGO_E02
+
+config SYS_BOARD
+	default "pogo_e02"
+
+config SYS_VENDOR
+	default "cloudengines"
+
+config SYS_CONFIG_NAME
+	default "pogo_e02"
+
+endif
diff --git a/roms/u-boot/board/cloudengines/pogo_e02/MAINTAINERS b/roms/u-boot/board/cloudengines/pogo_e02/MAINTAINERS
new file mode 100644
index 000000000..42c5dda30
--- /dev/null
+++ b/roms/u-boot/board/cloudengines/pogo_e02/MAINTAINERS
@@ -0,0 +1,6 @@
+POGO_E02 BOARD
+M:	Dave Purdy <david.c.purdy@gmail.com>
+S:	Maintained
+F:	board/cloudengines/pogo_e02/
+F:	include/configs/pogo_e02.h
+F:	configs/pogo_e02_defconfig
diff --git a/roms/u-boot/board/cloudengines/pogo_e02/Makefile b/roms/u-boot/board/cloudengines/pogo_e02/Makefile
new file mode 100644
index 000000000..f2d930e24
--- /dev/null
+++ b/roms/u-boot/board/cloudengines/pogo_e02/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= pogo_e02.o
diff --git a/roms/u-boot/board/cloudengines/pogo_e02/kwbimage.cfg b/roms/u-boot/board/cloudengines/pogo_e02/kwbimage.cfg
new file mode 100644
index 000000000..84cfa90c1
--- /dev/null
+++ b/roms/u-boot/board/cloudengines/pogo_e02/kwbimage.cfg
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2012
+# David Purdy <david.c.purdy@gmail.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xffd100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xffd01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xffd01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xffd01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xffd01410 0x000000cc	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=x8
+# bit7-6:   11, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xffd01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xffd01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xffd0141c 0x00000c52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xffd01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xffd01424 0x0000f17f	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xffd01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xffd01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xffd01504 0x0ffffff1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xffd01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xffd0150c 0x00000000	# CS[2]n Size, window disabled
+
+DATA 0xffd01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xffd0151c 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000	#  DDR ODT Control (Low)
+# bit3-0:  2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xffd0149c 0x0000e803	# CPU ODT Control
+DATA 0xffd01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/cloudengines/pogo_e02/pogo_e02.c b/roms/u-boot/board/cloudengines/pogo_e02/pogo_e02.c
new file mode 100644
index 000000000..039fd6e3d
--- /dev/null
+++ b/roms/u-boot/board/cloudengines/pogo_e02/pogo_e02.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012
+ * David Purdy <david.c.purdy@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/global_data.h>
+#include "pogo_e02.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
+			  POGO_E02_OE_VAL_HIGH,
+			  POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_UART0_RTS,
+		MPP9_UART0_CTS,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP29_TSMP9,	/* USB Power Enable */
+		MPP48_GPIO,	/* LED green */
+		MPP49_GPIO,	/* LED orange */
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Boot parameters address */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..(%s) could not read PHY dev address\n", __func__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	debug("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/roms/u-boot/board/cloudengines/pogo_e02/pogo_e02.h b/roms/u-boot/board/cloudengines/pogo_e02/pogo_e02.h
new file mode 100644
index 000000000..c8397b4d4
--- /dev/null
+++ b/roms/u-boot/board/cloudengines/pogo_e02/pogo_e02.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012
+ * David Purdy <david.c.purdy@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef __POGO_E02_H
+#define __POGO_E02_H
+
+/* GPIO configuration */
+#define POGO_E02_OE_LOW				(~(0))
+#define POGO_E02_OE_HIGH			(~(0))
+#define POGO_E02_OE_VAL_LOW			(1 << 29)
+#define POGO_E02_OE_VAL_HIGH			0
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG			10
+#define MV88E1116_CPRSP_CR3_REG			21
+#define MV88E1116_MAC_CTRL_REG			21
+#define MV88E1116_PGADR_REG			22
+#define MV88E1116_RGMII_TXTM_CTRL		(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL		(1 << 5)
+
+#endif /* __POGO_E02_H */
diff --git a/roms/u-boot/board/cobra5272/Kconfig b/roms/u-boot/board/cobra5272/Kconfig
new file mode 100644
index 000000000..ba04622c2
--- /dev/null
+++ b/roms/u-boot/board/cobra5272/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_COBRA5272
+
+config SYS_CPU
+	default "mcf52x2"
+
+config SYS_BOARD
+	default "cobra5272"
+
+config SYS_CONFIG_NAME
+	default "cobra5272"
+
+endif
diff --git a/roms/u-boot/board/cobra5272/MAINTAINERS b/roms/u-boot/board/cobra5272/MAINTAINERS
new file mode 100644
index 000000000..a064da2f1
--- /dev/null
+++ b/roms/u-boot/board/cobra5272/MAINTAINERS
@@ -0,0 +1,6 @@
+COBRA5272 BOARD
+#M:	-
+S:	Maintained
+F:	board/cobra5272/
+F:	include/configs/cobra5272.h
+F:	configs/cobra5272_defconfig
diff --git a/roms/u-boot/board/cobra5272/Makefile b/roms/u-boot/board/cobra5272/Makefile
new file mode 100644
index 000000000..c6a9e4840
--- /dev/null
+++ b/roms/u-boot/board/cobra5272/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= cobra5272.o flash.o
diff --git a/roms/u-boot/board/cobra5272/README b/roms/u-boot/board/cobra5272/README
new file mode 100644
index 000000000..1dad7e3ea
--- /dev/null
+++ b/roms/u-boot/board/cobra5272/README
@@ -0,0 +1,156 @@
+File:		README.COBRA5272
+Author:		Florian Schlote for Sentec elektronik (linux@sentec-elektronik.de)
+Contents:	This is the README of u-boot (Universal bootloader) for our
+		COBRA5272 board.
+Version:	v01.00
+Date:		Tue Mar 30 00:28:33 CEST 2004
+License:	This document is published under the GNU GPL
+______________________________________________________________________
+
+CHANGES
+040330   v01.00 Creation
+
+______________________________________________________________________
+
+
+CONFIGURING
+-----------
+
+1. Modify include/configs/cobra5272.h acc. to your prefs
+
+2. If necessary, modify board/cobra5272/config.mk (see below)
+
+3.
+
+> make cobra5272_config
+
+> make
+
+
+Please refer to u-boot README (general info, u-boot-x-x-x/README),
+to u-boot-x-x-x/board/cobra5272/README and
+to the comments in u-boot-x-x-x/include/configs/cobra5272.h
+
+Configuring u-boot is done by commenting/uncommenting preprocessor defines.
+
+Default configuration is
+
+	FLASH version (for further info see subsection below)
+	link address 0xffe00000
+
+	16 MB RAM
+
+	network enabled
+	no default IP address for target, host set, no MACaddress set
+
+	bootdelay for autoboot 5 sec.
+	autoboot disabled
+
+
+#-----------------------------------
+# u-boot FLASH version & RAM version
+#-----------------------------------
+
+The u-boot bootloader for Coldfire processors can be configured
+
+	1. as a standalone bootloader residing in flash & relocating itself to RAM on
+	startup automatically => "FLASH version"
+
+	2. as a RAM version which will not load from flash automatically as it needs a
+	prestage bootloader ("chainloading") & is running only from the RAM address it
+	is linked to => "RAM version"
+
+	This version may be very helpful when installing u-boot for the first time
+	since it can be used to make available s. th. like a "bootstrap
+	mechanism".
+
+
+How to build the different images:
+
+------------------------------
+Flash version
+------------------------------
+
+Compile u-boot
+
+in dir ./u-boot-x-x-x/
+
+please first check:
+
+	in ./include/configs/cobra5272.h
+
+		CONFIG_MONITOR_IS_IN_RAM has to be undefined, e. g. as follows:
+
+		#if 0
+			#define CONFIG_MONITOR_IS_IN_RAM
+			/* define if monitor is started from a pre-loader */
+		#endif
+
+	=> u-boot as single bootloader starting from flash
+
+
+	in board/cobra5272/config.mk CONFIG_SYS_TEXT_BASE should be
+
+		CONFIG_SYS_TEXT_BASE = 0xffe00000
+
+	=> linking address for u-boot as single bootloader stored in flash
+
+then:
+
+	host> make cobra5272_config
+		rm -f include/config.h include/config.mk
+		Configuring for cobra5272 board...
+	host> make
+		[...]
+
+	host> cp u-boot.bin /tftpboot/u-boot_flash.bin
+
+
+------------------------------
+RAM version
+------------------------------
+
+in dir ./u-boot-x-x-x/
+
+	host> make distclean
+
+please modify the settings:
+
+	in ./include/configs/cobra5272.h
+
+		CONFIG_MONITOR_IS_IN_RAM now has to be defined, e. g. as follows:
+
+		#if 1
+			#define CONFIG_MONITOR_IS_IN_RAM
+			/*define if monitor is started from a pre-loader */
+		#endif
+
+	=> u-boot as RAM version, chainloaded by another bootloader or using bdm cable
+
+
+	in board/cobra5272/config.mk CONFIG_SYS_TEXT_BASE should be
+
+		CONFIG_SYS_TEXT_BASE = 0x00020000
+
+	=> target linking address for RAM
+
+
+then:
+
+	host> make cobra5272_config
+		rm -f include/config.h include/config.mk
+		Configuring for cobra5272 board...
+	host> make
+		[...]
+
+	host> cp u-boot.bin /tftpboot/u-boot_ram.bin
+
+
+----
+HINT
+----
+
+If the m68k-elf-toolchain & the m68k-bdm-gdb is installed you can run the RAM
+version by typing (in dir ./u-boot-x-x-x/)
+"board/cobra5272/bdm/load-cobra_uboot" ,
+in ./u-boot-x-x-x/ the RAM version u-boot (elf format) has to be available.
diff --git a/roms/u-boot/board/cobra5272/bdm/cobra5272_uboot.gdb b/roms/u-boot/board/cobra5272/bdm/cobra5272_uboot.gdb
new file mode 100644
index 000000000..61e778ea5
--- /dev/null
+++ b/roms/u-boot/board/cobra5272/bdm/cobra5272_uboot.gdb
@@ -0,0 +1,169 @@
+#
+# GDB Init script for the Coldfire 5272 processor.
+#
+# The main purpose of this script is to configure the 
+# DRAM controller so code can be loaded.
+#
+# This file was changed to suite the senTec COBRA5272 board.
+# 
+
+define addresses
+
+set $mbar  = 0x10000001
+set $scr   = $mbar - 1 + 0x004
+set $spr   = $mbar - 1 + 0x006
+set $pmr   = $mbar - 1 + 0x008
+set $apmr  = $mbar - 1 + 0x00e
+set $dir   = $mbar - 1 + 0x010
+set $icr1  = $mbar - 1 + 0x020
+set $icr2  = $mbar - 1 + 0x024
+set $icr3  = $mbar - 1 + 0x028
+set $icr4  = $mbar - 1 + 0x02c
+set $isr   = $mbar - 1 + 0x030
+set $pitr  = $mbar - 1 + 0x034
+set $piwr  = $mbar - 1 + 0x038
+set $pivr  = $mbar - 1 + 0x03f
+set $csbr0 = $mbar - 1 + 0x040
+set $csor0 = $mbar - 1 + 0x044
+set $csbr1 = $mbar - 1 + 0x048
+set $csor1 = $mbar - 1 + 0x04c
+set $csbr2 = $mbar - 1 + 0x050
+set $csor2 = $mbar - 1 + 0x054
+set $csbr3 = $mbar - 1 + 0x058
+set $csor3 = $mbar - 1 + 0x05c
+set $csbr4 = $mbar - 1 + 0x060
+set $csor4 = $mbar - 1 + 0x064
+set $csbr5 = $mbar - 1 + 0x068
+set $csor5 = $mbar - 1 + 0x06c
+set $csbr6 = $mbar - 1 + 0x070
+set $csor6 = $mbar - 1 + 0x074
+set $csbr7 = $mbar - 1 + 0x078
+set $csor7 = $mbar - 1 + 0x07c
+set $pacnt = $mbar - 1 + 0x080
+set $paddr = $mbar - 1 + 0x084
+set $padat = $mbar - 1 + 0x086
+set $pbcnt = $mbar - 1 + 0x088
+set $pbddr = $mbar - 1 + 0x08c
+set $pbdat = $mbar - 1 + 0x08e
+set $pcddr = $mbar - 1 + 0x094
+set $pcdat = $mbar - 1 + 0x096
+set $pdcnt = $mbar - 1 + 0x098
+set $sdcr  = $mbar - 1 + 0x180
+set $sdtr  = $mbar - 1 + 0x184
+set $wrrr  = $mbar - 1 + 0x280
+set $wirr  = $mbar - 1 + 0x283
+set $wcr   = $mbar - 1 + 0x288
+set $wer   = $mbar - 1 + 0x28c
+
+end
+
+
+#
+# Setup system configuration
+#
+define setup-sys
+set *((unsigned short *) $scr) = 0x0003
+set *((unsigned short *) $spr) = 0xffff
+set *((unsigned char *) $pivr) = 0x4f
+end
+
+
+#
+# Setup Chip Selects (as per Motorola M5272C3 board)
+#
+define setup-cs
+
+# CS0 -- FLASH
+set *((unsigned long *) $csbr0) = 0xffe00201
+set *((unsigned long *) $csor0) = 0xffe00014
+
+# CS1 -- external bus test
+set *((unsigned long *) $csbr1) = 0x0
+set *((unsigned long *) $csor1) = 0x0
+
+# CS2 -- Optional FSRAM
+set *((unsigned long *) $csbr2) = 0x30000001
+set *((unsigned long *) $csor2) = 0xfff80000
+
+# CS3 -- not used
+set *((unsigned long *) $csbr3) = 0x0
+set *((unsigned long *) $csor3) = 0x0
+
+# CS4 --  not used
+set *((unsigned long *) $csbr4) = 0x0
+set *((unsigned long *) $csor4) = 0x0
+
+# CS5 -- PLI socket0
+set *((unsigned long *) $csbr5) = 0x0
+set *((unsigned long *) $csor5) = 0x0
+
+# CS6 -- PLI socket1
+set *((unsigned long *) $csbr6) = 0x0
+set *((unsigned long *) $csor6) = 0x0
+
+# CS7 -- SDRAM
+set *((unsigned long *) $csbr7) = 0x00000701
+set *((unsigned long *) $csor7) = 0xff00007c
+
+end
+
+
+#
+# Setup the DRAM controller.
+#
+
+define setup-dram
+set *((unsigned long *) $sdtr) = 0x0000f539
+set *((unsigned long *) $sdcr) = 0x00004211
+
+# Dummy write to start SDRAM
+set *((unsigned long *) 0) = 0
+end
+
+
+#
+# Setup for GPIO pins
+#
+define setup-ppio
+
+# PORT A -- the LED's
+set *((unsigned long *) $pacnt) = 0x00000000
+# lower 8 bits for output:
+set *((unsigned short *) $paddr) = 0xff
+# LED's off:
+set *((unsigned short *) $padat) = 0xff
+
+# PORT B
+set *((unsigned long *) $pbcnt) = 0x55554155
+set *((unsigned short *) $pbddr) = 0x0000
+set *((unsigned short *) $pbdat) = 0x17ea
+
+# PORT C
+#set *((unsigned short *) $pcddr) = 0x0000
+#set *((unsigned short *) $pcdat) = 0x1898
+
+# PORT D
+set *((unsigned long *) $pdcnt) = 0x00000000
+
+end
+
+
+#
+#	Added for uClinux-coldfire target...
+#
+target bdm /dev/bdm
+
+addresses
+setup-sys
+setup-cs
+setup-dram
+setup-ppio
+set print pretty
+set print asm-demangle
+display/i $pc
+
+
+#
+load u-boot
+set $pc=0x20000
+c
diff --git a/roms/u-boot/board/cobra5272/bdm/gdbinit.reset b/roms/u-boot/board/cobra5272/bdm/gdbinit.reset
new file mode 100644
index 000000000..5f1e48217
--- /dev/null
+++ b/roms/u-boot/board/cobra5272/bdm/gdbinit.reset
@@ -0,0 +1,2 @@
+target bdm /dev/bdmcf0
+q
diff --git a/roms/u-boot/board/cobra5272/bdm/load-cobra_uboot b/roms/u-boot/board/cobra5272/bdm/load-cobra_uboot
new file mode 100644
index 000000000..933c7e723
--- /dev/null
+++ b/roms/u-boot/board/cobra5272/bdm/load-cobra_uboot
@@ -0,0 +1,2 @@
+m68k-bdm-elf-gdb -n -x board/cobra5272/bdm/cobra5272_uboot.gdb u-boot
+
diff --git a/roms/u-boot/board/cobra5272/bdm/reset b/roms/u-boot/board/cobra5272/bdm/reset
new file mode 100644
index 000000000..8bef00bf1
--- /dev/null
+++ b/roms/u-boot/board/cobra5272/bdm/reset
@@ -0,0 +1,2 @@
+m68k-bdm-elf-gdb -n -x bdm/gdbinit.reset
+
diff --git a/roms/u-boot/board/cobra5272/cobra5272.c b/roms/u-boot/board/cobra5272/cobra5272.c
new file mode 100644
index 000000000..3e2418866
--- /dev/null
+++ b/roms/u-boot/board/cobra5272/cobra5272.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard (void)
+{
+	puts ("Board: ");
+	puts ("senTec COBRA5272 Board\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
+
+	sdp->sdram_sdtr = 0xf539;
+	sdp->sdram_sdcr = 0x4211;
+
+	/* Dummy write to start SDRAM */
+	*((volatile unsigned long *) 0) = 0;
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/roms/u-boot/board/cobra5272/flash.c b/roms/u-boot/board/cobra5272/flash.c
new file mode 100644
index 000000000..4337f4879
--- /dev/null
+++ b/roms/u-boot/board/cobra5272/flash.c
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <console.h>
+#include <cpu_func.h>
+#include <flash.h>
+#include <irq_func.h>
+#include <uuid.h>
+#include <linux/delay.h>
+
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
+#define FLASH_BANK_SIZE 0x200000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_PL160CB & FLASH_TYPEMASK):
+		printf ("AM29PL160CB (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:
+	return;
+}
+
+
+unsigned long flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_PL160CB & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured to many flash banks!\n");
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j == 0) {
+				/* 1st is 16 KiB */
+				flash_info[i].start[j] = flashbase;
+			}
+			if ((j >= 1) && (j <= 2)) {
+				/* 2nd and 3rd are 8 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x4000 + 0x2000 * (j - 1);
+			}
+			if (j == 3) {
+				/* 4th is 224 KiB */
+				flash_info[i].start[j] = flashbase + 0x8000;
+			}
+			if ((j >= 4) && (j <= 10)) {
+				/* rest is 256 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x40000 + 0x40000 * (j -
+									 4);
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_FLASH_BASE,
+		      CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
+
+	return size;
+}
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+	ulong start;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status();
+	icache_disable();
+	iflag = disable_interrupts();
+
+	printf ("\n");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		start = get_timer(0);
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr =
+				(volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMEOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	mdelay(10);
+
+	if (iflag)
+		enable_interrupts();
+
+	if (cflag)
+		icache_enable();
+
+	return rc;
+}
+
+static int write_word(flash_info_t *info, ulong dest, ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip1;
+	ulong start;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status();
+	icache_disable();
+	iflag = disable_interrupts();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer(0);
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts();
+
+	if (cflag)
+		icache_enable();
+
+	return rc;
+}
+
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	}
+
+#if 0
+	if (cnt & 1) {
+		printf ("odd transfer sizes not supported\n");
+		return ERR_ALIGN;
+	}
+#endif
+
+	wp = addr;
+
+	if (addr & 1) {
+		data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
+							  src);
+		if ((rc = write_word (info, wp - 1, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src) << 8) |
+			*((volatile u8 *) (wp + 1));
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}
diff --git a/roms/u-boot/board/compal/paz00/Kconfig b/roms/u-boot/board/compal/paz00/Kconfig
new file mode 100644
index 000000000..30ba11d36
--- /dev/null
+++ b/roms/u-boot/board/compal/paz00/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PAZ00
+
+config SYS_BOARD
+	default "paz00"
+
+config SYS_VENDOR
+	default "compal"
+
+config SYS_CONFIG_NAME
+	default "paz00"
+
+endif
diff --git a/roms/u-boot/board/compal/paz00/MAINTAINERS b/roms/u-boot/board/compal/paz00/MAINTAINERS
new file mode 100644
index 000000000..ee2b2e954
--- /dev/null
+++ b/roms/u-boot/board/compal/paz00/MAINTAINERS
@@ -0,0 +1,7 @@
+PAZ00 BOARD
+M:	Tom Warren <twarren@nvidia.com>
+M:	Stephen Warren <swarren@nvidia.com>
+S:	Maintained
+F:	board/compal/paz00/
+F:	include/configs/paz00.h
+F:	configs/paz00_defconfig
diff --git a/roms/u-boot/board/compal/paz00/Makefile b/roms/u-boot/board/compal/paz00/Makefile
new file mode 100644
index 000000000..22c26ed1f
--- /dev/null
+++ b/roms/u-boot/board/compal/paz00/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+
+obj-y	:= paz00.o
diff --git a/roms/u-boot/board/compal/paz00/paz00.c b/roms/u-boot/board/compal/paz00/paz00.c
new file mode 100644
index 000000000..64d0860d2
--- /dev/null
+++ b/roms/u-boot/board/compal/paz00/paz00.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+	/* SDMMC4: config 3, x8 on 2nd set of pins */
+	pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
+	pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
+	pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
+
+	pinmux_tristate_disable(PMUX_PINGRP_ATB);
+	pinmux_tristate_disable(PMUX_PINGRP_GMA);
+	pinmux_tristate_disable(PMUX_PINGRP_GME);
+
+	/* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
+	pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
+
+	pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
+
+	/* For power GPIO PV1 */
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
+	/* For CD GPIO PV5 */
+	pinmux_tristate_disable(PMUX_PINGRP_GPV);
+}
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+/* this is a weak define that we are overriding */
+void pin_mux_display(void)
+{
+	debug("init display pinmux\n");
+
+	/* EN_VDD_PANEL GPIO A4 */
+	pinmux_tristate_disable(PMUX_PINGRP_DAP2);
+}
+#endif
diff --git a/roms/u-boot/board/compulab/cl-som-imx7/Kconfig b/roms/u-boot/board/compulab/cl-som-imx7/Kconfig
new file mode 100644
index 000000000..6d69cf31f
--- /dev/null
+++ b/roms/u-boot/board/compulab/cl-som-imx7/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_CL_SOM_IMX7
+
+config SYS_BOARD
+	default "cl-som-imx7"
+
+config SYS_VENDOR
+	default "compulab"
+
+config SYS_CONFIG_NAME
+	default "cl-som-imx7"
+
+config SYS_MMC_DEV
+	int
+	default 0
+
+config SYS_USB_DEV
+	int
+	default 0
+
+config SYS_MMC_IMG_LOAD_PART
+	int
+	default 1
+
+config SYS_USB_IMG_LOAD_PART
+	int
+	default 1
+
+endif
diff --git a/roms/u-boot/board/compulab/cl-som-imx7/MAINTAINERS b/roms/u-boot/board/compulab/cl-som-imx7/MAINTAINERS
new file mode 100644
index 000000000..2b917a5c8
--- /dev/null
+++ b/roms/u-boot/board/compulab/cl-som-imx7/MAINTAINERS
@@ -0,0 +1,6 @@
+CL-SOM-IMX7 BOARD
+M:	Uri Mashiach <uri.mashiach@compulab.co.il>
+S:	Maintained
+F:	board/compulab/cl-som-imx7
+F:	include/configs/cl-som-imx7.h
+F:	configs/cl-som-imx7_defconfig
diff --git a/roms/u-boot/board/compulab/cl-som-imx7/Makefile b/roms/u-boot/board/compulab/cl-som-imx7/Makefile
new file mode 100644
index 000000000..8f0e068b7
--- /dev/null
+++ b/roms/u-boot/board/compulab/cl-som-imx7/Makefile
@@ -0,0 +1,17 @@
+#
+# Makefile
+#
+# (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+#
+# Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y := mux.o common.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y  += spl.o
+else
+obj-y  += cl-som-imx7.o
+endif
diff --git a/roms/u-boot/board/compulab/cl-som-imx7/cl-som-imx7.c b/roms/u-boot/board/compulab/cl-som-imx7/cl-som-imx7.c
new file mode 100644
index 000000000..454c93a57
--- /dev/null
+++ b/roms/u-boot/board/compulab/cl-som-imx7/cl-som-imx7.c
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot board functions for CompuLab CL-SOM-iMX7 module
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <mmc.h>
+#include <net.h>
+#include <phy.h>
+#include <netdev.h>
+#include <fsl_esdhc_imx.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch-mx7/mx7-pins.h>
+#include <asm/arch-mx7/sys_proto.h>
+#include <asm/arch-mx7/clock.h>
+#include "../common/eeprom.h"
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SYS_I2C_MXC
+
+#define I2C_PAD_CTRL		(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+				PAD_CTL_HYS)
+
+#define CL_SOM_IMX7_GPIO_I2C2_SCL	IMX_GPIO_NR(1, 6)
+#define CL_SOM_IMX7_GPIO_I2C2_SDA	IMX_GPIO_NR(1, 7)
+
+static struct i2c_pads_info cl_som_imx7_i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL |
+			MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 |
+			MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = CL_SOM_IMX7_GPIO_I2C2_SCL,
+	},
+	.sda = {
+		.i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA |
+			MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 |
+			MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = CL_SOM_IMX7_GPIO_I2C2_SDA,
+	},
+};
+
+/*
+ * cl_som_imx7_setup_i2c() - I2C  pinmux configuration.
+ */
+static void cl_som_imx7_setup_i2c(void)
+{
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &cl_som_imx7_i2c_pad_info2);
+}
+#else /* !CONFIG_SYS_I2C_MXC */
+static void cl_som_imx7_setup_i2c(void) {}
+#endif /* CONFIG_SYS_I2C_MXC */
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+#define CL_SOM_IMX7_GPIO_USDHC3_PWR	IMX_GPIO_NR(6, 11)
+
+static struct fsl_esdhc_cfg cl_som_imx7_usdhc_cfg[3] = {
+	{USDHC1_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc2                    USDHC3 (eMMC)
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			cl_som_imx7_usdhc1_pads_set();
+			gpio_request(CL_SOM_IMX7_GPIO_USDHC1_CD, "usdhc1_cd");
+			cl_som_imx7_usdhc_cfg[0].sdhc_clk =
+				mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+			cl_som_imx7_usdhc3_emmc_pads_set();
+			gpio_request(CL_SOM_IMX7_GPIO_USDHC3_PWR, "usdhc3_pwr");
+			gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 0);
+			udelay(500);
+			gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 1);
+			cl_som_imx7_usdhc_cfg[1].sdhc_clk =
+				mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers "
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &cl_som_imx7_usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+#ifdef CONFIG_FEC_MXC
+
+#define CL_SOM_IMX7_ETH1_PHY_NRST	IMX_GPIO_NR(1, 4)
+
+/*
+ * cl_som_imx7_rgmii_rework() - Ethernet PHY configuration.
+ */
+static void cl_som_imx7_rgmii_rework(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* Ar8031 phy SmartEEE feature cause link status generates glitch,
+	 * which cause ethernet link down/up issue, so disable SmartEEE
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= ~(0x1 << 8);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	cl_som_imx7_rgmii_rework(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+/*
+ * cl_som_imx7_handle_mac_address() - set Ethernet MAC address environment.
+ *
+ * @env_var: MAC address environment variable
+ * @eeprom_bus: I2C bus of the environment EEPROM
+ *
+ * @return: 0 on success, < 0 on failure
+ */
+static int cl_som_imx7_handle_mac_address(char *env_var, uint eeprom_bus)
+{
+	int ret;
+	unsigned char enetaddr[6];
+
+	ret = eth_env_get_enetaddr(env_var, enetaddr);
+	if (ret)
+		return 0;
+
+	ret = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
+	if (ret)
+		return ret;
+
+	ret = is_valid_ethaddr(enetaddr);
+	if (!ret)
+		return -1;
+
+	return eth_env_set_enetaddr(env_var, enetaddr);
+}
+
+#define CL_SOM_IMX7_FEC_DEV_ID_PRI 0
+
+int board_eth_init(struct bd_info *bis)
+{
+	/* set Ethernet MAC address environment */
+	cl_som_imx7_handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS);
+	/* Ethernet interface pinmux configuration  */
+	cl_som_imx7_phy1_rst_pads_set();
+	cl_som_imx7_fec1_pads_set();
+	/* PHY reset */
+	gpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, "eth1_phy_nrst");
+	gpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0);
+	mdelay(10);
+	gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1);
+	/* MAC initialization */
+	return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI,
+				       CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+}
+
+/*
+ * cl_som_imx7_setup_fec() - Ethernet MAC 1 clock configuration.
+ * - ENET1 reference clock mode select.
+ * - ENET1_TX_CLK output driver is disabled when configured for ALT1.
+ */
+static void cl_som_imx7_setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
+			 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
+
+	set_clk_enet(ENET_125MHZ);
+}
+#else /* !CONFIG_FEC_MXC */
+static void cl_som_imx7_setup_fec(void) {}
+#endif /* CONFIG_FEC_MXC */
+
+#ifdef CONFIG_SPI
+
+static void cl_som_imx7_spi_init(void)
+{
+	cl_som_imx7_espi1_pads_set();
+}
+#else /* !CONFIG_SPI */
+static void cl_som_imx7_spi_init(void) {}
+#endif /* CONFIG_SPI */
+
+int board_early_init_f(void)
+{
+	cl_som_imx7_uart1_pads_set();
+	cl_som_imx7_usb_otg1_pads_set();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	cl_som_imx7_setup_i2c();
+	cl_som_imx7_setup_fec();
+	cl_som_imx7_spi_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg, rev_id;
+
+	ret = power_pfuze3000_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE3000");
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
+	pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1);
+
+	return 0;
+}
+#endif /* CONFIG_POWER */
+
+/*
+ * cl_som_imx7_setup_wdog() - watchdog configuration.
+ * - Output WDOG_B signal to reset external pmic.
+ * - Suspend the watchdog timer during low-power modes.
+ */
+void cl_som_imx7_setup_wdog(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	cl_som_imx7_wdog_pads_set();
+	set_wdog_reset(wdog);
+       /*
+	* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+	* since we use PMIC_PWRON to reset the board.
+	*/
+	clrsetbits_le16(&wdog->wcr, 0, 0x10);
+}
+
+int board_late_init(void)
+{
+	env_set("board_name", "CL-SOM-iMX7");
+	cl_som_imx7_setup_wdog();
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *mode;
+
+	if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
+		mode = "secure";
+	else
+		mode = "non-secure";
+
+	printf("Board: CL-SOM-iMX7 in %s mode\n", mode);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/compulab/cl-som-imx7/common.c b/roms/u-boot/board/compulab/cl-som-imx7/common.c
new file mode 100644
index 000000000..40ba0f7a9
--- /dev/null
+++ b/roms/u-boot/board/compulab/cl-som-imx7/common.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SPL/U-Boot common functions for CompuLab CL-SOM-iMX7 module
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ */
+
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <asm-generic/gpio.h>
+#include "common.h"
+
+#ifdef CONFIG_SPI
+
+#define CL_SOM_IMX7_GPIO_SPI_CS	IMX_GPIO_NR(4, 19)
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+	return CL_SOM_IMX7_GPIO_SPI_CS;
+}
+
+#endif /* CONFIG_SPI */
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(CL_SOM_IMX7_GPIO_USDHC1_CD);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = 1; /* Assume uSDHC3 emmc is always present */
+		break;
+	}
+
+	return ret;
+}
+
+#endif /* CONFIG_FSL_ESDHC_IMX */
diff --git a/roms/u-boot/board/compulab/cl-som-imx7/common.h b/roms/u-boot/board/compulab/cl-som-imx7/common.h
new file mode 100644
index 000000000..bc19867f8
--- /dev/null
+++ b/roms/u-boot/board/compulab/cl-som-imx7/common.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * SPL/U-Boot common header file for CompuLab CL-SOM-iMX7 module
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ */
+
+#define PADS_SET_PROT(pads_array) void cl_som_imx7_##pads_array##_set(void)
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+#define CL_SOM_IMX7_GPIO_USDHC1_CD	IMX_GPIO_NR(5, 0)
+PADS_SET_PROT(usdhc1_pads);
+#endif /* CONFIG_FSL_ESDHC_IMX */
+PADS_SET_PROT(uart1_pads);
+#ifdef CONFIG_SPI
+PADS_SET_PROT(espi1_pads);
+#endif /* CONFIG_SPI */
+
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_FSL_ESDHC_IMX
+PADS_SET_PROT(usdhc3_emmc_pads);
+#endif /* CONFIG_FSL_ESDHC_IMX */
+#ifdef CONFIG_FEC_MXC
+PADS_SET_PROT(phy1_rst_pads);
+PADS_SET_PROT(fec1_pads);
+#endif /* CONFIG_FEC_MXC */
+PADS_SET_PROT(usb_otg1_pads);
+PADS_SET_PROT(wdog_pads);
+#endif /* !CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/compulab/cl-som-imx7/mux.c b/roms/u-boot/board/compulab/cl-som-imx7/mux.c
new file mode 100644
index 000000000..18f16a487
--- /dev/null
+++ b/roms/u-boot/board/compulab/cl-som-imx7/mux.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SPL/U-Boot mux functions for CompuLab CL-SOM-iMX7 module
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ */
+
+#include <common.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch-mx7/mx7-pins.h>
+
+#define PADS_SET(pads_array)						       \
+void cl_som_imx7_##pads_array##_set(void)				       \
+{									       \
+	imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array));  \
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+#define USDHC_PAD_CTRL		(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+				PAD_CTL_HYS | PAD_CTL_PUE | \
+				PAD_CTL_PUS_PU47KOHM)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+PADS_SET(usdhc1_pads)
+
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+#define UART_PAD_CTRL		(PAD_CTL_DSE_3P3V_49OHM | \
+				PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+PADS_SET(uart1_pads)
+
+#ifdef CONFIG_SPI
+
+#define SPI_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_3P3V_32OHM)
+
+#define GPIO_PAD_CTRL	(PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \
+			PAD_CTL_SRE_SLOW)
+
+static iomux_v3_cfg_t const espi1_pads[] = {
+	MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+PADS_SET(espi1_pads)
+
+#endif /* CONFIG_SPI */
+
+#ifndef CONFIG_SPL_BUILD
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
+	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_STROBE__SD3_STROBE	 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+PADS_SET(usdhc3_emmc_pads)
+
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+#ifdef CONFIG_FEC_MXC
+
+#define ENET_PAD_CTRL		(PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+#define ENET_PAD_CTRL_MII	(PAD_CTL_PUS_PU5KOHM)
+
+static iomux_v3_cfg_t const phy1_rst_pads[] = {
+	/* PHY1 RST */
+	MX7D_PAD_GPIO1_IO04__GPIO1_IO4	| MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+PADS_SET(phy1_rst_pads)
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL |
+	MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL |
+	MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+	MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+};
+
+PADS_SET(fec1_pads)
+
+#endif /* CONFIG_FEC_MXC */
+
+static iomux_v3_cfg_t const usb_otg1_pads[] = {
+	MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+PADS_SET(usb_otg1_pads)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+PADS_SET(wdog_pads)
+
+#endif /* !CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/compulab/cl-som-imx7/spl.c b/roms/u-boot/board/compulab/cl-som-imx7/spl.c
new file mode 100644
index 000000000..9c7332b43
--- /dev/null
+++ b/roms/u-boot/board/compulab/cl-som-imx7/spl.c
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SPL board functions for CompuLab CL-SOM-iMX7 module
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <spl.h>
+#include <fsl_esdhc_imx.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch-mx7/mx7-pins.h>
+#include <asm/arch-mx7/clock.h>
+#include <asm/arch-mx7/mx7-ddr.h>
+#include "common.h"
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+static struct fsl_esdhc_cfg cl_som_imx7_spl_usdhc_cfg = {
+	USDHC1_BASE_ADDR, 0, 4};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	cl_som_imx7_usdhc1_pads_set();
+	cl_som_imx7_spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	return fsl_esdhc_initialize(bis, &cl_som_imx7_spl_usdhc_cfg);
+}
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+static iomux_v3_cfg_t const led_pads[] = {
+	MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM |
+		PAD_CTL_PUE | PAD_CTL_SRE_SLOW)
+};
+
+static struct ddrc cl_som_imx7_spl_ddrc_regs_val = {
+	.init1		= 0x00690000,
+	.init0		= 0x00020083,
+	.init3		= 0x09300004,
+	.init4		= 0x04080000,
+	.init5		= 0x00100004,
+	.rankctl	= 0x0000033F,
+	.dramtmg1	= 0x0007020E,
+	.dramtmg2	= 0x03040407,
+	.dramtmg3	= 0x00002006,
+	.dramtmg4	= 0x04020305,
+	.dramtmg5	= 0x03030202,
+	.dramtmg8	= 0x00000803,
+	.zqctl0		= 0x00810021,
+	.dfitmg0	= 0x02098204,
+	.dfitmg1	= 0x00030303,
+	.dfiupd0	= 0x80400003,
+	.dfiupd1	= 0x00100020,
+	.dfiupd2	= 0x80100004,
+	.addrmap4	= 0x00000F0F,
+	.odtcfg		= 0x06000604,
+	.odtmap		= 0x00000001,
+};
+
+static struct ddrc_mp cl_som_imx7_spl_ddrc_mp_val = {
+	.pctrl_0	= 0x00000001,
+};
+
+static struct ddr_phy cl_som_imx7_spl_ddr_phy_regs_val = {
+	.phy_con0	= 0x17420F40,
+	.phy_con1	= 0x10210100,
+	.phy_con4	= 0x00060807,
+	.mdll_con0	= 0x1010007E,
+	.drvds_con0	= 0x00000D6E,
+	.cmd_sdll_con0	= 0x00000010,
+	.offset_lp_con0	= 0x0000000F,
+};
+
+struct mx7_calibration cl_som_imx7_spl_calib_param = {
+	.num_val	= 5,
+	.values		= {
+		0x0E407304,
+		0x0E447304,
+		0x0E447306,
+		0x0E447304,
+		0x0E407304,
+	},
+};
+
+static void cl_som_imx7_spl_dram_cfg_size(u32 ram_size)
+{
+	switch (ram_size) {
+	case SZ_256M:
+		cl_som_imx7_spl_ddrc_regs_val.mstr		= 0x01041001;
+		cl_som_imx7_spl_ddrc_regs_val.rfshtmg		= 0x00400046;
+		cl_som_imx7_spl_ddrc_regs_val.dramtmg0		= 0x090E1109;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap0		= 0x00000014;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap1		= 0x00151515;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap5		= 0x03030303;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap6		= 0x0F0F0303;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0	= 0x0C0C0C0C;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0	= 0x04040404;
+		break;
+	case SZ_512M:
+		cl_som_imx7_spl_ddrc_regs_val.mstr		= 0x01040001;
+		cl_som_imx7_spl_ddrc_regs_val.rfshtmg		= 0x00400046;
+		cl_som_imx7_spl_ddrc_regs_val.dramtmg0		= 0x090E1109;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap0		= 0x00000015;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap1		= 0x00161616;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap5		= 0x04040404;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap6		= 0x0F0F0404;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0	= 0x0C0C0C0C;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0	= 0x04040404;
+		break;
+	case SZ_1G:
+		cl_som_imx7_spl_ddrc_regs_val.mstr		= 0x01040001;
+		cl_som_imx7_spl_ddrc_regs_val.rfshtmg		= 0x00400046;
+		cl_som_imx7_spl_ddrc_regs_val.dramtmg0		= 0x090E1109;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap0		= 0x00000016;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap1		= 0x00171717;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap5		= 0x04040404;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap6		= 0x0F040404;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0	= 0x0A0A0A0A;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0	= 0x02020202;
+		break;
+	case SZ_2G:
+		cl_som_imx7_spl_ddrc_regs_val.mstr		= 0x01040001;
+		cl_som_imx7_spl_ddrc_regs_val.rfshtmg		= 0x0040005E;
+		cl_som_imx7_spl_ddrc_regs_val.dramtmg0		= 0x090E110A;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap0		= 0x00000018;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap1		= 0x00181818;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap5		= 0x04040404;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap6		= 0x04040404;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0	= 0x0A0A0A0A;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0	= 0x04040404;
+		break;
+	}
+
+	mx7_dram_cfg(&cl_som_imx7_spl_ddrc_regs_val,
+		     &cl_som_imx7_spl_ddrc_mp_val,
+		     &cl_som_imx7_spl_ddr_phy_regs_val,
+		     &cl_som_imx7_spl_calib_param);
+}
+
+static void cl_som_imx7_spl_dram_cfg(void)
+{
+	ulong ram_size_test, ram_size = 0;
+
+	for (ram_size = SZ_2G; ram_size >= SZ_256M; ram_size >>= 1) {
+		cl_som_imx7_spl_dram_cfg_size(ram_size);
+		ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
+		if (ram_size_test == ram_size)
+			break;
+	}
+
+	if (ram_size < SZ_256M) {
+		puts("!!!ERROR!!! DRAM detection failed!!!\n");
+		hang();
+	}
+}
+
+#ifdef CONFIG_SPL_SPI_SUPPORT
+
+static void cl_som_imx7_spl_spi_init(void)
+{
+	cl_som_imx7_espi1_pads_set();
+}
+#else /* !CONFIG_SPL_SPI_SUPPORT */
+static void cl_som_imx7_spl_spi_init(void) {}
+#endif /* CONFIG_SPL_SPI_SUPPORT */
+
+void board_init_f(ulong dummy)
+{
+	imx_iomux_v3_setup_multiple_pads(led_pads, 1);
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+	/* setup GP timer */
+	timer_init();
+	cl_som_imx7_spl_spi_init();
+	cl_som_imx7_uart1_pads_set();
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+	/* DRAM detection  */
+	cl_som_imx7_spl_dram_cfg();
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+	u32 boot_device = spl_boot_device();
+
+	if (boot_device == BOOT_DEVICE_SPI)
+		puts("Booting from SPI flash\n");
+	else if (boot_device == BOOT_DEVICE_MMC1)
+		puts("Booting from SD card\n");
+	else
+		puts("Unknown boot device\n");
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+	switch (spl_boot_list[0]) {
+	case BOOT_DEVICE_SPI:
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+		break;
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[1] = BOOT_DEVICE_SPI;
+		break;
+	}
+}
diff --git a/roms/u-boot/board/compulab/cm_fx6/Kconfig b/roms/u-boot/board/compulab/cm_fx6/Kconfig
new file mode 100644
index 000000000..59070c5f7
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_fx6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CM_FX6
+
+config SYS_BOARD
+	default "cm_fx6"
+
+config SYS_VENDOR
+	default "compulab"
+
+config SYS_CONFIG_NAME
+	default "cm_fx6"
+
+endif
diff --git a/roms/u-boot/board/compulab/cm_fx6/MAINTAINERS b/roms/u-boot/board/compulab/cm_fx6/MAINTAINERS
new file mode 100644
index 000000000..5b2623a66
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_fx6/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_FX6 BOARD
+M:	Nikita Kiryanov <nikita@compulab.co.il>
+S:	Maintained
+F:	board/compulab/cm_fx6/
+F:	include/configs/cm_fx6.h
+F:	configs/cm_fx6_defconfig
diff --git a/roms/u-boot/board/compulab/cm_fx6/Makefile b/roms/u-boot/board/compulab/cm_fx6/Makefile
new file mode 100644
index 000000000..e648db26a
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_fx6/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ifdef CONFIG_SPL_BUILD
+obj-y = common.o spl.o
+else
+obj-y = common.o cm_fx6.o
+endif
diff --git a/roms/u-boot/board/compulab/cm_fx6/cm_fx6.c b/roms/u-boot/board/compulab/cm_fx6/cm_fx6.c
new file mode 100644
index 000000000..f29b08247
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_fx6/cm_fx6.c
@@ -0,0 +1,798 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <dm.h>
+#include <dwc_ahsata.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
+#include <init.h>
+#include <miiphy.h>
+#include <mtd_node.h>
+#include <net.h>
+#include <netdev.h>
+#include <errno.h>
+#include <usb.h>
+#include <fdt_support.h>
+#include <sata.h>
+#include <splash.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <dm/device-internal.h>
+#include <jffs2/load_kernel.h>
+#include <linux/delay.h>
+#include "common.h"
+#include "../common/eeprom.h"
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPLASH_SCREEN
+static struct splash_location cm_fx6_splash_locations[] = {
+	{
+		.name = "sf",
+		.storage = SPLASH_STORAGE_SF,
+		.flags = SPLASH_STORAGE_RAW,
+		.offset = 0x100000,
+	},
+	{
+		.name = "mmc_fs",
+		.storage = SPLASH_STORAGE_MMC,
+		.flags = SPLASH_STORAGE_FS,
+		.devpart = "2:1",
+	},
+	{
+		.name = "usb_fs",
+		.storage = SPLASH_STORAGE_USB,
+		.flags = SPLASH_STORAGE_FS,
+		.devpart = "0:1",
+	},
+	{
+		.name = "sata_fs",
+		.storage = SPLASH_STORAGE_SATA,
+		.flags = SPLASH_STORAGE_FS,
+		.devpart = "0:1",
+	},
+};
+
+int splash_screen_prepare(void)
+{
+	return splash_source_load(cm_fx6_splash_locations,
+				  ARRAY_SIZE(cm_fx6_splash_locations));
+}
+#endif
+
+#ifdef CONFIG_IMX_HDMI
+static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	imx_setup_hdmi();
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
+	imx_enable_hdmi_phy();
+}
+
+static struct display_info_t preset_hdmi_1024X768 = {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.enable	= cm_fx6_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 40385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED,
+	}
+};
+
+static void cm_fx6_setup_display(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	enable_ipu_clock();
+	clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
+}
+
+int board_video_skip(void)
+{
+	int ret;
+	struct display_info_t *preset;
+	char const *panel = env_get("displaytype");
+
+	if (!panel) /* Also accept panel for backward compatibility */
+		panel = env_get("panel");
+
+	if (!panel)
+		return -ENOENT;
+
+	if (!strcmp(panel, "HDMI"))
+		preset = &preset_hdmi_1024X768;
+	else
+		return -EINVAL;
+
+	ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
+	if (ret) {
+		printf("Can't init display %s: %d\n", preset->mode.name, ret);
+		return ret;
+	}
+
+	preset->enable(preset);
+	printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
+	       preset->mode.yres);
+
+	return 0;
+}
+#else
+static inline void cm_fx6_setup_display(void) {}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+int ipu_displays_init(void)
+{
+	return board_video_skip();
+}
+
+#ifdef CONFIG_DWC_AHSATA
+static int cm_fx6_issd_gpios[] = {
+	/* The order of the GPIOs in the array is important! */
+	CM_FX6_SATA_LDO_EN,
+	CM_FX6_SATA_PHY_SLP,
+	CM_FX6_SATA_NRSTDLY,
+	CM_FX6_SATA_PWREN,
+	CM_FX6_SATA_NSTANDBY1,
+	CM_FX6_SATA_NSTANDBY2,
+};
+
+static void cm_fx6_sata_power(int on)
+{
+	int i;
+
+	if (!on) { /* tell the iSSD that the power will be removed */
+		gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
+		mdelay(10);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
+		gpio_direction_output(cm_fx6_issd_gpios[i], on);
+		udelay(100);
+	}
+
+	if (!on) /* for compatibility lower the power loss interrupt */
+		gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
+}
+
+static iomux_v3_cfg_t const sata_pads[] = {
+	/* SATA PWR */
+	IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* SATA CTRL */
+	IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static int cm_fx6_setup_issd(void)
+{
+	int ret, i;
+
+	SETUP_IOMUX_PADS(sata_pads);
+
+	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
+		ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
+		if (ret)
+			return ret;
+	}
+
+	ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+#define CM_FX6_SATA_INIT_RETRIES	10
+
+#else
+static int cm_fx6_setup_issd(void) { return 0; }
+#endif
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+			PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+I2C_PADS(i2c0_pads,
+	 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(3, 21),
+	 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(3, 28));
+
+I2C_PADS(i2c1_pads,
+	 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(4, 12),
+	 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(4, 13));
+
+I2C_PADS(i2c2_pads,
+	 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(1, 3),
+	 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(1, 6));
+
+
+static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
+{
+	int ret;
+
+	ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
+	if (ret)
+		printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
+
+	return ret;
+}
+
+static int cm_fx6_setup_i2c(void)
+{
+	int ret = 0, err;
+
+	/* i2c<x>_pads are wierd macro variables; we can't use an array */
+	err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
+	if (err)
+		ret = err;
+	err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
+	if (err)
+		ret = err;
+	err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
+	if (err)
+		ret = err;
+
+	return ret;
+}
+#else
+static int cm_fx6_setup_i2c(void) { return 0; }
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
+			PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+			PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+#define MX6_USBNC_BASEADDR	0x2184800
+#define USBNC_USB_H1_PWR_POL	(1 << 9)
+
+static int cm_fx6_setup_usb_host(void)
+{
+	int err;
+
+	err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
+	if (err)
+		return err;
+
+	SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
+	SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
+
+	return 0;
+}
+
+static int cm_fx6_setup_usb_otg(void)
+{
+	int err;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
+	if (err) {
+		printf("USB OTG pwr gpio request failed: %d\n", err);
+		return err;
+	}
+
+	SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
+	SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
+						MUX_PAD_CTRL(WEAK_PULLDOWN));
+	clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
+	/* disable ext. charger detect, or it'll affect signal quality at dp. */
+	return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
+}
+
+int board_usb_phy_mode(int port)
+{
+	return USB_INIT_HOST;
+}
+
+int board_ehci_hcd_init(int port)
+{
+	int ret;
+	u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
+
+	/* Only 1 host controller in use. port 0 is OTG & needs no attention */
+	if (port != 1)
+		return 0;
+
+	/* Set PWR polarity to match power switch's enable polarity */
+	setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
+	ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
+	if (ret)
+		return ret;
+
+	udelay(10);
+	ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
+	if (ret)
+		return ret;
+
+	mdelay(1);
+
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	if (port == 0)
+		return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
+
+	return 0;
+}
+#else
+static int cm_fx6_setup_usb_otg(void) { return 0; }
+static int cm_fx6_setup_usb_host(void) { return 0; }
+#endif
+
+#ifdef CONFIG_FEC_MXC
+#define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+				 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* Ar8031 phy SmartEEE feature cause link status generates glitch,
+	 * which cause ethernet link down/up issue, so disable SmartEEE
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= ~(0x1 << 8);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+
+	if (phydev->drv->config)
+		return phydev->drv->config(phydev);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
+	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+};
+
+static int handle_mac_address(char *env_var, uint eeprom_bus)
+{
+	unsigned char enetaddr[6];
+	int rc;
+
+	rc = eth_env_get_enetaddr(env_var, enetaddr);
+	if (rc)
+		return 0;
+
+	rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
+	if (rc)
+		return rc;
+
+	if (!is_valid_ethaddr(enetaddr))
+		return -1;
+
+	return eth_env_set_enetaddr(env_var, enetaddr);
+}
+
+#define SB_FX6_I2C_EEPROM_BUS	0
+#define NO_MAC_ADDR		"No MAC address found for %s\n"
+int board_eth_init(struct bd_info *bis)
+{
+	int err;
+
+	if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
+		printf(NO_MAC_ADDR, "primary NIC");
+
+	if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
+		printf(NO_MAC_ADDR, "secondary NIC");
+
+	SETUP_IOMUX_PADS(enet_pads);
+	/* phy reset */
+	err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
+	if (err)
+		printf("Etnernet NRST gpio request failed: %d\n", err);
+	gpio_direction_output(CM_FX6_ENET_NRST, 0);
+	udelay(500);
+	gpio_set_value(CM_FX6_ENET_NRST, 1);
+	enable_enet_clk(1);
+	return cpu_eth_init(bis);
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const nand_pads[] = {
+	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_gpmi_nand(void)
+{
+	SETUP_IOMUX_PADS(nand_pads);
+	/* Enable clock roots */
+	enable_usdhc_clk(1, 3);
+	enable_usdhc_clk(1, 4);
+
+	setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
+			  MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
+			  MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
+}
+#else
+static void cm_fx6_setup_gpmi_nand(void) {}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+int cm_fx6_setup_ecspi(void)
+{
+	cm_fx6_set_ecspi_iomux();
+	return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
+}
+#else
+int cm_fx6_setup_ecspi(void) { return 0; }
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+#define USDHC3_PATH	"/soc/aips-bus@02100000/usdhc@02198000/"
+
+static const struct node_info nodes[] = {
+	/*
+	 * Both entries target the same flash chip. The st,m25p compatible
+	 * is used in the vendor device trees, while upstream uses (the
+	 * documented) jedec,spi-nor compatible.
+	 */
+	{ "st,m25p",	MTD_DEV_TYPE_NOR,	},
+	{ "jedec,spi-nor",	MTD_DEV_TYPE_NOR,	},
+};
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u32 baseboard_rev;
+	int nodeoffset;
+	uint8_t enetaddr[6];
+	char baseboard_name[16];
+	int err;
+
+	fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */
+
+	/* MAC addr */
+	if (eth_env_get_enetaddr("ethaddr", enetaddr)) {
+		fdt_find_and_setprop(blob,
+				     "/soc/aips-bus@02100000/ethernet@02188000",
+				     "local-mac-address", enetaddr, 6, 1);
+	}
+
+	if (eth_env_get_enetaddr("eth1addr", enetaddr)) {
+		fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
+				     enetaddr, 6, 1);
+	}
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+	baseboard_rev = cl_eeprom_get_board_rev(0);
+	err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
+	if (err || baseboard_rev == 0)
+		return 0; /* Assume not an early revision SB-FX6m baseboard */
+
+	if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
+		nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
+		fdt_delprop(blob, nodeoffset, "cd-gpios");
+		fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
+				     NULL, 0, 1);
+		fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
+				     NULL, 0, 1);
+	}
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	int ret;
+
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+	cm_fx6_setup_gpmi_nand();
+
+	ret = cm_fx6_setup_ecspi();
+	if (ret)
+		printf("Warning: ECSPI setup failed: %d\n", ret);
+
+	ret = cm_fx6_setup_usb_otg();
+	if (ret)
+		printf("Warning: USB OTG setup failed: %d\n", ret);
+
+	ret = cm_fx6_setup_usb_host();
+	if (ret)
+		printf("Warning: USB host setup failed: %d\n", ret);
+
+	/*
+	 * cm-fx6 may have iSSD not assembled and in this case it has
+	 * bypasses for a (m)SATA socket on the baseboard. The socketed
+	 * device is not controlled by those GPIOs. So just print a warning
+	 * if the setup fails.
+	 */
+	ret = cm_fx6_setup_issd();
+	if (ret)
+		printf("Warning: iSSD setup failed: %d\n", ret);
+
+	/* Warn on failure but do not abort boot */
+	ret = cm_fx6_setup_i2c();
+	if (ret)
+		printf("Warning: I2C setup failed: %d\n", ret);
+
+	cm_fx6_setup_display();
+
+	/* This should be done in the MMC driver when MX6 has a clock driver */
+#ifdef CONFIG_FSL_ESDHC_IMX
+	if (IS_ENABLED(CONFIG_BLK)) {
+		int i;
+
+		cm_fx6_set_usdhc_iomux();
+		for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
+			enable_usdhc_clk(1, i);
+	}
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	char baseboard_name[16];
+	int err;
+
+	if (is_mx6dq())
+		env_set("board_rev", "MX6Q");
+	else if (is_mx6dl())
+		env_set("board_rev", "MX6DL");
+
+	err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
+	if (err)
+		return 0;
+
+	if (!strncmp("SB-FX6m", baseboard_name, 7))
+		env_set("board_name", "Utilite");
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: CM-FX6\n");
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	cl_print_pcb_info();
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+
+	switch (gd->ram_size) {
+	case 0x10000000: /* DDR_16BIT_256MB */
+		gd->bd->bi_dram[0].size = 0x10000000;
+		gd->bd->bi_dram[1].size = 0;
+		break;
+	case 0x20000000: /* DDR_32BIT_512MB */
+		gd->bd->bi_dram[0].size = 0x20000000;
+		gd->bd->bi_dram[1].size = 0;
+		break;
+	case 0x40000000:
+		if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
+			gd->bd->bi_dram[0].size = 0x20000000;
+			gd->bd->bi_dram[1].size = 0x20000000;
+		} else { /* DDR_64BIT_1GB */
+			gd->bd->bi_dram[0].size = 0x40000000;
+			gd->bd->bi_dram[1].size = 0;
+		}
+		break;
+	case 0x80000000: /* DDR_64BIT_2GB */
+		gd->bd->bi_dram[0].size = 0x40000000;
+		gd->bd->bi_dram[1].size = 0x40000000;
+		break;
+	case 0xEFF00000: /* DDR_64BIT_4GB */
+		gd->bd->bi_dram[0].size = 0x70000000;
+		gd->bd->bi_dram[1].size = 0x7FF00000;
+		break;
+	}
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	switch (gd->ram_size) {
+	case 0x10000000:
+	case 0x20000000:
+	case 0x40000000:
+	case 0x80000000:
+		break;
+	case 0xF0000000:
+		gd->ram_size -= 0x100000;
+		break;
+	default:
+		printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
+		return -1;
+	}
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
+}
+
+static struct mxc_serial_plat cm_fx6_mxc_serial_plat = {
+	.reg = (struct mxc_uart *)UART4_BASE,
+};
+
+U_BOOT_DRVINFO(cm_fx6_serial) = {
+	.name	= "serial_mxc",
+	.plat = &cm_fx6_mxc_serial_plat,
+};
+
+#if CONFIG_IS_ENABLED(AHCI)
+static int sata_imx_probe(struct udevice *dev)
+{
+	int i, err;
+
+	/* Make sure this gpio has logical 0 value */
+	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
+	udelay(100);
+	cm_fx6_sata_power(1);
+
+	for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
+		err = setup_sata();
+		if (err) {
+			printf("SATA setup failed: %d\n", err);
+			return err;
+		}
+
+		udelay(100);
+
+		err = dwc_ahsata_probe(dev);
+		if (!err)
+			break;
+
+		/* There is no device on the SATA port */
+		if (sata_dm_port_status(0, 0) == 0)
+			break;
+
+		/* There's a device, but link not established. Retry */
+		device_remove(dev, DM_REMOVE_NORMAL);
+	}
+
+	return 0;
+}
+
+static int sata_imx_remove(struct udevice *dev)
+{
+	cm_fx6_sata_power(0);
+	mdelay(250);
+
+	return 0;
+}
+
+struct ahci_ops sata_imx_ops = {
+	.port_status = dwc_ahsata_port_status,
+	.reset	= dwc_ahsata_bus_reset,
+	.scan	= dwc_ahsata_scan,
+};
+
+static const struct udevice_id sata_imx_ids[] = {
+	{ .compatible = "fsl,imx6q-ahci" },
+	{ }
+};
+
+U_BOOT_DRIVER(sata_imx) = {
+	.name		= "dwc_ahci",
+	.id		= UCLASS_AHCI,
+	.of_match	= sata_imx_ids,
+	.ops		= &sata_imx_ops,
+	.probe		= sata_imx_probe,
+	.remove		= sata_imx_remove,  /* reset bus to stop it */
+};
+#endif /* AHCI */
diff --git a/roms/u-boot/board/compulab/cm_fx6/common.c b/roms/u-boot/board/compulab/cm_fx6/common.c
new file mode 100644
index 000000000..ed8c7a3bf
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_fx6/common.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Code used by both U-Boot and SPL for Compulab CM-FX6
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/spi.h>
+#include <fsl_esdhc_imx.h>
+#include "common.h"
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc_pads[] = {
+	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+void cm_fx6_set_usdhc_iomux(void)
+{
+	SETUP_IOMUX_PADS(usdhc_pads);
+}
+
+/* CINS bit doesn't work, so always try to access the MMC card */
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#define ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+		PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const ecspi_pads[] = {
+	IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30  | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__ECSPI1_SS1  | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+};
+
+void cm_fx6_set_ecspi_iomux(void)
+{
+	SETUP_IOMUX_PADS(ecspi_pads);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1;
+}
+#endif
diff --git a/roms/u-boot/board/compulab/cm_fx6/common.h b/roms/u-boot/board/compulab/cm_fx6/common.h
new file mode 100644
index 000000000..debef1588
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_fx6/common.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ */
+
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/clock.h>
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |	\
+			PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+			PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define CM_FX6_ECSPI_BUS0_CS0	IMX_GPIO_NR(2, 30)
+#define CM_FX6_GREEN_LED	IMX_GPIO_NR(2, 31)
+#define CM_FX6_ENET_NRST	IMX_GPIO_NR(2, 8)
+#define CM_FX6_ENET_NRST	IMX_GPIO_NR(2, 8)
+#define CM_FX6_USB_HUB_RST	IMX_GPIO_NR(7, 8)
+#define SB_FX6_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
+#define CM_FX6_ENET_NRST	IMX_GPIO_NR(2, 8)
+#define CM_FX6_USB_HUB_RST	IMX_GPIO_NR(7, 8)
+#define SB_FX6_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
+#define CM_FX6_SATA_PWREN	IMX_GPIO_NR(1, 28)
+#define CM_FX6_SATA_VDDC_CTRL	IMX_GPIO_NR(1, 30)
+#define CM_FX6_SATA_LDO_EN	IMX_GPIO_NR(2, 16)
+#define CM_FX6_SATA_NSTANDBY1	IMX_GPIO_NR(3, 20)
+#define CM_FX6_SATA_PHY_SLP	IMX_GPIO_NR(3, 23)
+#define CM_FX6_SATA_STBY_REQ	IMX_GPIO_NR(3, 29)
+#define CM_FX6_SATA_NSTANDBY2	IMX_GPIO_NR(5, 2)
+#define CM_FX6_SATA_NRSTDLY	IMX_GPIO_NR(6, 6)
+#define CM_FX6_SATA_PWLOSS_INT	IMX_GPIO_NR(6, 31)
+
+
+void cm_fx6_set_usdhc_iomux(void);
+void cm_fx6_set_ecspi_iomux(void);
diff --git a/roms/u-boot/board/compulab/cm_fx6/spl.c b/roms/u-boot/board/compulab/cm_fx6/spl.c
new file mode 100644
index 000000000..c3c816181
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_fx6/spl.c
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SPL specific code for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <hang.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/delay.h>
+#include "common.h"
+
+enum ddr_config {
+	DDR_16BIT_256MB,
+	DDR_32BIT_512MB,
+	DDR_32BIT_1GB,
+	DDR_64BIT_1GB,
+	DDR_64BIT_2GB,
+	DDR_64BIT_4GB,
+	DDR_UNKNOWN,
+};
+
+/*
+ * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
+ * Freescale QRM, but this is exactly the value used by the automatic
+ * calibration script and it works also in all our tests, so we leave
+ * it as is at this point.
+ */
+#define CM_FX6_DDR_IOMUX_CFG \
+	.dram_sdqs0	= 0x00000038, \
+	.dram_sdqs1	= 0x00000038, \
+	.dram_sdqs2	= 0x00000038, \
+	.dram_sdqs3	= 0x00000038, \
+	.dram_sdqs4	= 0x00000038, \
+	.dram_sdqs5	= 0x00000038, \
+	.dram_sdqs6	= 0x00000038, \
+	.dram_sdqs7	= 0x00000038, \
+	.dram_dqm0	= 0x00000038, \
+	.dram_dqm1	= 0x00000038, \
+	.dram_dqm2	= 0x00000038, \
+	.dram_dqm3	= 0x00000038, \
+	.dram_dqm4	= 0x00000038, \
+	.dram_dqm5	= 0x00000038, \
+	.dram_dqm6	= 0x00000038, \
+	.dram_dqm7	= 0x00000038, \
+	.dram_cas	= 0x00000038, \
+	.dram_ras	= 0x00000038, \
+	.dram_sdclk_0	= 0x00000038, \
+	.dram_sdclk_1	= 0x00000038, \
+	.dram_sdcke0	= 0x00003000, \
+	.dram_sdcke1	= 0x00003000, \
+	.dram_reset	= 0x00000038, \
+	.dram_sdba2	= 0x00000000, \
+	.dram_sdodt0	= 0x00000038, \
+	.dram_sdodt1	= 0x00000038,
+
+#define CM_FX6_GPR_IOMUX_CFG \
+	.grp_b0ds	= 0x00000038, \
+	.grp_b1ds	= 0x00000038, \
+	.grp_b2ds	= 0x00000038, \
+	.grp_b3ds	= 0x00000038, \
+	.grp_b4ds	= 0x00000038, \
+	.grp_b5ds	= 0x00000038, \
+	.grp_b6ds	= 0x00000038, \
+	.grp_b7ds	= 0x00000038, \
+	.grp_addds	= 0x00000038, \
+	.grp_ddrmode_ctl = 0x00020000, \
+	.grp_ddrpke	= 0x00000000, \
+	.grp_ddrmode	= 0x00020000, \
+	.grp_ctlds	= 0x00000038, \
+	.grp_ddr_type	= 0x000C0000,
+
+static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
+static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
+static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
+static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
+
+static struct mx6_mmdc_calibration cm_fx6_calib_s = {
+	.p0_mpwldectrl0	= 0x005B0061,
+	.p0_mpwldectrl1	= 0x004F0055,
+	.p0_mpdgctrl0	= 0x0314030C,
+	.p0_mpdgctrl1	= 0x025C0268,
+	.p0_mprddlctl	= 0x42464646,
+	.p0_mpwrdlctl	= 0x36322C34,
+};
+
+static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
+	.cs1_mirror	= 1,
+	.cs_density	= 16,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 1,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
+	.mem_speed	= 800,
+	.density	= 4,
+	.rowaddr	= 14,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1800,
+	.trcmin		= 5200,
+	.trasmin	= 3600,
+	.SRT		= 0,
+};
+
+static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
+{
+	if (reset)
+		((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
+
+	switch (dram_config) {
+	case DDR_16BIT_256MB:
+		cm_fx6_sysinfo_s.dsize = 0;
+		cm_fx6_sysinfo_s.ncs = 1;
+		break;
+	case DDR_32BIT_512MB:
+		cm_fx6_sysinfo_s.dsize = 1;
+		cm_fx6_sysinfo_s.ncs = 1;
+		break;
+	case DDR_32BIT_1GB:
+		cm_fx6_sysinfo_s.dsize = 1;
+		cm_fx6_sysinfo_s.ncs = 2;
+		break;
+	default:
+		puts("Tried to setup invalid DDR configuration\n");
+		hang();
+	}
+
+	mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
+	udelay(100);
+}
+
+static struct mx6_mmdc_calibration cm_fx6_calib_q = {
+	.p0_mpwldectrl0	= 0x00630068,
+	.p0_mpwldectrl1	= 0x0068005D,
+	.p0_mpdgctrl0	= 0x04140428,
+	.p0_mpdgctrl1	= 0x037C037C,
+	.p0_mprddlctl	= 0x3C30303A,
+	.p0_mpwrdlctl	= 0x3A344038,
+	.p1_mpwldectrl0	= 0x0035004C,
+	.p1_mpwldectrl1	= 0x00170026,
+	.p1_mpdgctrl0	= 0x0374037C,
+	.p1_mpdgctrl1	= 0x0350032C,
+	.p1_mprddlctl	= 0x30322A3C,
+	.p1_mpwrdlctl	= 0x48304A3E,
+};
+
+static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
+	.cs_density	= 16,
+	.cs1_mirror	= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 1,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+	.refsel = 1,		/* Refresh cycles at 32KHz */
+	.refr = 7,		/* 8 refresh commands per refresh cycle */
+};
+
+static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
+	.mem_speed	= 1066,
+	.density	= 4,
+	.rowaddr	= 14,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1324,
+	.trcmin		= 59500,
+	.trasmin	= 9750,
+	.SRT		= 0,
+};
+
+static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
+{
+	if (reset)
+		((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
+
+	cm_fx6_ddr3_cfg_q.rowaddr = 14;
+	switch (dram_config) {
+	case DDR_16BIT_256MB:
+		cm_fx6_sysinfo_q.dsize = 0;
+		cm_fx6_sysinfo_q.ncs = 1;
+		break;
+	case DDR_32BIT_512MB:
+		cm_fx6_sysinfo_q.dsize = 1;
+		cm_fx6_sysinfo_q.ncs = 1;
+		break;
+	case DDR_64BIT_1GB:
+		cm_fx6_sysinfo_q.dsize = 2;
+		cm_fx6_sysinfo_q.ncs = 1;
+		break;
+	case DDR_64BIT_2GB:
+		cm_fx6_sysinfo_q.dsize = 2;
+		cm_fx6_sysinfo_q.ncs = 2;
+		break;
+	case DDR_64BIT_4GB:
+		cm_fx6_sysinfo_q.dsize = 2;
+		cm_fx6_sysinfo_q.ncs = 2;
+		cm_fx6_ddr3_cfg_q.rowaddr = 15;
+		break;
+	default:
+		puts("Tried to setup invalid DDR configuration\n");
+		hang();
+	}
+
+	mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
+	udelay(100);
+}
+
+static int cm_fx6_spl_dram_init(void)
+{
+	unsigned long bank1_size, bank2_size;
+
+	switch (get_cpu_type()) {
+	case MXC_CPU_MX6SOLO:
+		mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
+
+		spl_mx6s_dram_init(DDR_32BIT_1GB, false);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000);
+		if (bank1_size == 0x20000000) {
+			if (bank2_size == 0x20000000)
+				return 0;
+
+			spl_mx6s_dram_init(DDR_32BIT_512MB, true);
+			return 0;
+		}
+
+		spl_mx6s_dram_init(DDR_16BIT_256MB, true);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x10000000)
+			return 0;
+
+		break;
+	case MXC_CPU_MX6D:
+	case MXC_CPU_MX6Q:
+		mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
+
+		spl_mx6q_dram_init(DDR_64BIT_4GB, false);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x80000000)
+			return 0;
+
+		if (bank1_size == 0x40000000) {
+			bank2_size = get_ram_size((long int *)PHYS_SDRAM_2,
+								0x80000000);
+			if (bank2_size == 0x40000000) {
+				/* Don't do a full reset here */
+				spl_mx6q_dram_init(DDR_64BIT_2GB, false);
+			} else {
+				spl_mx6q_dram_init(DDR_64BIT_1GB, true);
+			}
+
+			return 0;
+		}
+
+		spl_mx6q_dram_init(DDR_32BIT_512MB, true);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x20000000)
+			return 0;
+
+		spl_mx6q_dram_init(DDR_16BIT_256MB, true);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x10000000)
+			return 0;
+
+		break;
+	}
+
+	return -1;
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_uart(void)
+{
+	SETUP_IOMUX_PADS(uart4_pads);
+	enable_uart_clk(1);
+}
+
+#ifdef CONFIG_SPL_SPI_SUPPORT
+static void cm_fx6_setup_ecspi(void)
+{
+	cm_fx6_set_ecspi_iomux();
+	enable_spi_clk(1, 0);
+}
+#else
+static void cm_fx6_setup_ecspi(void) { }
+#endif
+
+void board_init_f(ulong dummy)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/*
+	 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
+	 * initializes DMA very early (before all board code), so the only
+	 * opportunity we have to initialize APBHDMA clocks is in SPL.
+	 */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+	enable_usdhc_clk(1, 2);
+
+	arch_cpu_init();
+	timer_init();
+	cm_fx6_setup_ecspi();
+	cm_fx6_setup_uart();
+	get_clocks();
+	preloader_console_init();
+	gpio_direction_output(CM_FX6_GREEN_LED, 1);
+	if (cm_fx6_spl_dram_init()) {
+		puts("!!!ERROR!!! DRAM detection failed!!!\n");
+		hang();
+	}
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+	switch (spl_boot_list[0]) {
+	case BOOT_DEVICE_SPI:
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+		break;
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[1] = BOOT_DEVICE_SPI;
+		break;
+	}
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+static struct fsl_esdhc_cfg usdhc_cfg = {
+	.esdhc_base = USDHC3_BASE_ADDR,
+	.max_bus_width = 4,
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	cm_fx6_set_usdhc_iomux();
+
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif
diff --git a/roms/u-boot/board/compulab/cm_t335/Kconfig b/roms/u-boot/board/compulab/cm_t335/Kconfig
new file mode 100644
index 000000000..683efde76
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t335/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CM_T335
+
+config SYS_BOARD
+	default "cm_t335"
+
+config SYS_VENDOR
+	default "compulab"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "cm_t335"
+
+endif
diff --git a/roms/u-boot/board/compulab/cm_t335/MAINTAINERS b/roms/u-boot/board/compulab/cm_t335/MAINTAINERS
new file mode 100644
index 000000000..5fb922c68
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t335/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_T335 BOARD
+M:	Igor Grinberg <grinberg@compulab.co.il>
+S:	Maintained
+F:	board/compulab/cm_t335/
+F:	include/configs/cm_t335.h
+F:	configs/cm_t335_defconfig
diff --git a/roms/u-boot/board/compulab/cm_t335/Makefile b/roms/u-boot/board/compulab/cm_t335/Makefile
new file mode 100644
index 000000000..34f671311
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t335/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/
+#
+# Author: Ilya Ledvich <ilya@compulab.co.il>
+
+obj-y	+= cm_t335.o
+obj-$(CONFIG_SPL_BUILD) += mux.o spl.o
diff --git a/roms/u-boot/board/compulab/cm_t335/cm_t335.c b/roms/u-boot/board/compulab/cm_t335/cm_t335.c
new file mode 100644
index 000000000..1d4a3acee
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t335/cm_t335.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <net.h>
+#include <status_led.h>
+#include <cpsw.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware_am33xx.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	gpmc_init();
+
+#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
+	status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF);
+#endif
+	return 0;
+}
+
+#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slave = {
+	.slave_reg_ofs	= 0x208,
+	.sliver_reg_ofs	= 0xd80,
+	.phy_addr	= 0,
+	.phy_if		= PHY_INTERFACE_MODE_RGMII,
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= &cpsw_slave,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+/* PHY reset GPIO */
+#define GPIO_PHY_RST		GPIO_PIN(3, 7)
+
+static void board_phy_init(void)
+{
+	gpio_request(GPIO_PHY_RST, "phy_rst");
+	gpio_direction_output(GPIO_PHY_RST, 0);
+	mdelay(2);
+	gpio_set_value(GPIO_PHY_RST, 1);
+	mdelay(2);
+}
+
+static void get_efuse_mac_addr(uchar *enetaddr)
+{
+	uint32_t mac_hi, mac_lo;
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	enetaddr[0] = mac_hi & 0xFF;
+	enetaddr[1] = (mac_hi & 0xFF00) >> 8;
+	enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
+	enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
+	enetaddr[4] = mac_lo & 0xFF;
+	enetaddr[5] = (mac_lo & 0xFF00) >> 8;
+}
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int handle_mac_address(void)
+{
+	uchar enetaddr[6];
+	int rv;
+
+	rv = eth_env_get_enetaddr("ethaddr", enetaddr);
+	if (rv)
+		return 0;
+
+	rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
+	if (rv)
+		get_efuse_mac_addr(enetaddr);
+
+	if (!is_valid_ethaddr(enetaddr))
+		return -1;
+
+	return eth_env_set_enetaddr("ethaddr", enetaddr);
+}
+
+#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
+#define AR8051_PHY_DEBUG_DATA_REG	0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
+#define AR8051_RGMII_TX_CLK_DLY		0x100
+
+int board_eth_init(struct bd_info *bis)
+{
+	int rv, n = 0;
+	const char *devname;
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	rv = handle_mac_address();
+	if (rv)
+		printf("No MAC address found!\n");
+
+	writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
+
+	board_phy_init();
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+
+	/*
+	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
+	 * operating points.  So we must set the TX clock delay feature
+	 * in the AR8051 PHY.  Since we only support a single ethernet
+	 * device, we only do this for the first instance.
+	 */
+	devname = miiphy_get_current_dev();
+
+	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
+		     AR8051_DEBUG_RGMII_CLK_DLY_REG);
+	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
+		     AR8051_RGMII_TX_CLK_DLY);
+	return n;
+}
+#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/compulab/cm_t335/mux.c b/roms/u-boot/board/compulab/cm_t335/mux.c
new file mode 100644
index 000000000..1c326bd1b
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t335/mux.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Pinmux configuration for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
+	{OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},		/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+static struct module_pin_mux eth_phy_rst_pin_mux[] = {
+	{OFFSET(emu0), (MODE(7) | PULLUDDIS)},	/* GPIO3_7 */
+	{-1},
+};
+
+static struct module_pin_mux status_led_pin_mux[] = {
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)},	/* GPIO2_0 */
+	{-1},
+};
+
+void set_uart_mux_conf(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+	configure_module_pin_mux(uart1_pin_mux);
+}
+
+void set_mux_conf_regs(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(i2c1_pin_mux);
+	configure_module_pin_mux(rgmii1_pin_mux);
+	configure_module_pin_mux(eth_phy_rst_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(nand_pin_mux);
+	configure_module_pin_mux(status_led_pin_mux);
+}
diff --git a/roms/u-boot/board/compulab/cm_t335/spl.c b/roms/u-boot/board/compulab/cm_t335/spl.c
new file mode 100644
index 000000000..33264dfa7
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t335/spl.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SPL specific code for Compulab CM-T335 board
+ *
+ * Board functions for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <errno.h>
+#include <init.h>
+#include <log.h>
+
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clocks_am33xx.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware_am33xx.h>
+#include <linux/sizes.h>
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0		= MT41J128MJT125_RD_DQS,
+	.datawdsratio0		= MT41J128MJT125_WR_DQS,
+	.datafwsratio0		= MT41J128MJT125_PHY_FIFO_WE,
+	.datawrsratio0		= MT41J128MJT125_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio		= MT41J128MJT125_RATIO,
+	.cmd0iclkout		= MT41J128MJT125_INVERT_CLKOUT,
+
+	.cmd1csratio		= MT41J128MJT125_RATIO,
+	.cmd1iclkout		= MT41J128MJT125_INVERT_CLKOUT,
+
+	.cmd2csratio		= MT41J128MJT125_RATIO,
+	.cmd2iclkout		= MT41J128MJT125_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config		= MT41J128MJT125_EMIF_SDCFG,
+	.ref_ctrl		= MT41J128MJT125_EMIF_SDREF,
+	.sdram_tim1		= MT41J128MJT125_EMIF_TIM1,
+	.sdram_tim2		= MT41J128MJT125_EMIF_TIM2,
+	.sdram_tim3		= MT41J128MJT125_EMIF_TIM3,
+	.zq_config		= MT41J128MJT125_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1	= MT41J128MJT125_EMIF_READ_LATENCY |
+					PHY_EN_DYN_PWRDN,
+};
+
+const struct dpll_params dpll_ddr = {
+/*       M           N            M2  M3  M4  M5  M6 */
+	303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
+static void probe_sdram_size(long size)
+{
+	switch (size) {
+	case SZ_512M:
+		ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
+		break;
+	case SZ_256M:
+		ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
+		break;
+	case SZ_128M:
+		ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
+		break;
+	default:
+		puts("Failed configuring DRAM, resetting...\n\n");
+		reset_cpu();
+	}
+	debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
+	config_ddr(303, &ioregs, &ddr3_data,
+		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+
+void sdram_init(void)
+{
+	long size = SZ_1G;
+
+	do {
+		size = size / 2;
+		probe_sdram_size(size);
+	} while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
+
+	return;
+}
diff --git a/roms/u-boot/board/compulab/cm_t335/u-boot.lds b/roms/u-boot/board/compulab/cm_t335/u-boot.lds
new file mode 100644
index 000000000..b00e466d5
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t335/u-boot.lds
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+		board/compulab/cm_t335/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}
diff --git a/roms/u-boot/board/compulab/cm_t43/Kconfig b/roms/u-boot/board/compulab/cm_t43/Kconfig
new file mode 100644
index 000000000..a19188975
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t43/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CM_T43
+
+config SYS_BOARD
+	default "cm_t43"
+
+config SYS_VENDOR
+	default "compulab"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "cm_t43"
+
+endif
diff --git a/roms/u-boot/board/compulab/cm_t43/MAINTAINERS b/roms/u-boot/board/compulab/cm_t43/MAINTAINERS
new file mode 100644
index 000000000..951c370dd
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t43/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_T43 BOARD
+M:	Nikita Kiryanov <nikita@compulab.co.il>
+S:	Maintained
+F:	board/compulab/cm_t43/
+F:	include/configs/cm_t43.h
+F:	configs/cm_t43_defconfig
diff --git a/roms/u-boot/board/compulab/cm_t43/Makefile b/roms/u-boot/board/compulab/cm_t43/Makefile
new file mode 100644
index 000000000..6fa231a04
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t43/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2015 Compulab, Ltd.
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o mux.o
+else
+obj-y	+= cm_t43.o mux.o
+endif
diff --git a/roms/u-boot/board/compulab/cm_t43/board.h b/roms/u-boot/board/compulab/cm_t43/board.h
new file mode 100644
index 000000000..fcacd2bc0
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t43/board.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Compulab, Ltd.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+void set_i2c_pin_mux(void);
+void set_mdio_pin_mux(void);
+void set_rgmii_pin_mux(void);
+#endif
diff --git a/roms/u-boot/board/compulab/cm_t43/cm_t43.c b/roms/u-boot/board/compulab/cm_t43/cm_t43.c
new file mode 100644
index 000000000..efdade155
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t43/cm_t43.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Compulab, Ltd.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/emif.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/tps65218.h>
+#include "board.h"
+#include <usb.h>
+#include <asm/omap_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	struct pmic *p;
+	uchar tps_status = 0;
+
+	power_tps65218_init(I2C_PMIC);
+	p = pmic_get("TPS65218_PMIC");
+	if (p && !pmic_probe(p)) {
+		puts("PMIC:  TPS65218\n");
+		/* We don't care if fseal is locked, but we do need it set */
+		tps65218_lock_fseal();
+		tps65218_reg_read(TPS65218_STATUS, &tps_status);
+		if (!(tps_status & TPS65218_FSEAL))
+			printf("WARNING: RTC not backed by battery!\n");
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+	set_i2c_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	i2c_probe(TPS65218_CHIP_PM);
+
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	enable_usb_clocks(index);
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	disable_usb_clocks(index);
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+static void cpsw_control(int enabled)
+{
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+		.phy_if		= PHY_INTERFACE_MODE_RGMII,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+		.phy_if		= PHY_INTERFACE_MODE_RGMII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 2,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+#define GPIO_PHY1_RST		170
+#define GPIO_PHY2_RST		168
+
+int board_phy_config(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	if (phydev->drv->config)
+		return phydev->drv->config(phydev);
+
+	return 0;
+}
+
+static void board_phy_init(void)
+{
+	set_mdio_pin_mux();
+	writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
+	writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
+	writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
+
+	/* For revision A */
+	writel(0x2000009, 0x44df2e6c);
+	writel(0x38a, 0x44df2e70);
+
+	mdelay(10);
+
+	gpio_request(GPIO_PHY1_RST, "phy1_rst");
+	gpio_request(GPIO_PHY2_RST, "phy2_rst");
+	gpio_direction_output(GPIO_PHY1_RST, 0);
+	gpio_direction_output(GPIO_PHY2_RST, 0);
+	mdelay(2);
+
+	gpio_set_value(GPIO_PHY1_RST, 1);
+	gpio_set_value(GPIO_PHY2_RST, 1);
+	mdelay(2);
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int rv;
+
+	set_rgmii_pin_mux();
+	writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
+	board_phy_init();
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+
+	return rv;
+}
+#endif
diff --git a/roms/u-boot/board/compulab/cm_t43/mux.c b/roms/u-boot/board/compulab/cm_t43/mux.c
new file mode 100644
index 000000000..778ea05e8
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t43/mux.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Compulab, Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include "board.h"
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen),  MODE(2)},
+	{OFFSET(mii1_txd3),  MODE(2)},
+	{OFFSET(mii1_txd2),  MODE(2)},
+	{OFFSET(mii1_txd1),  MODE(2)},
+	{OFFSET(mii1_txd0),  MODE(2)},
+	{OFFSET(mii1_txclk), MODE(2)},
+	{OFFSET(mii1_rxdv),  MODE(2) | RXACTIVE | PULLDOWN_EN},
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE | PULLDOWN_EN},
+	{OFFSET(mii1_rxd3),  MODE(2) | RXACTIVE | PULLDOWN_EN},
+	{OFFSET(mii1_rxd2),  MODE(2) | RXACTIVE | PULLDOWN_EN},
+	{OFFSET(mii1_rxd1),  MODE(2) | RXACTIVE | PULLDOWN_EN},
+	{OFFSET(mii1_rxd0),  MODE(2) | RXACTIVE | PULLDOWN_EN},
+	{-1},
+};
+
+static struct module_pin_mux rgmii2_pin_mux[] = {
+	{OFFSET(gpmc_a0),  MODE(2)}, /* txen */
+	{OFFSET(gpmc_a2),  MODE(2)}, /* txd3 */
+	{OFFSET(gpmc_a3),  MODE(2)}, /* txd2 */
+	{OFFSET(gpmc_a4),  MODE(2)}, /* txd1 */
+	{OFFSET(gpmc_a5),  MODE(2)}, /* txd0 */
+	{OFFSET(gpmc_a6),  MODE(2)}, /* txclk */
+	{OFFSET(gpmc_a1),  MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxvd */
+	{OFFSET(gpmc_a7),  MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxclk */
+	{OFFSET(gpmc_a8),  MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd3 */
+	{OFFSET(gpmc_a9),  MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd2 */
+	{OFFSET(gpmc_a10), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd1 */
+	{OFFSET(gpmc_a11), MODE(2) | RXACTIVE | PULLUP_EN},   /* rxd0 */
+	{-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+	{OFFSET(mdio_data), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(mdio_clk),  (MODE(0) | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE  | SLEWCTRL)},
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_clk),  (MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(mmc0_cmd),  (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{-1},
+};
+
+static struct module_pin_mux i2c_pin_mux[] = {
+	{OFFSET(i2c0_sda),  (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(i2c0_scl),  (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(spi2_sclk), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(spi2_cs0),  (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0),	(MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad1),	(MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad2),	(MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad3),	(MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad4),	(MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad5),	(MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad6),	(MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_ad7),	(MODE(0) | PULLUDDIS | RXACTIVE)},
+	{OFFSET(gpmc_wait0),	(MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(gpmc_wpn),	(MODE(0) | PULLUP_EN)},
+	{OFFSET(gpmc_csn0),	(MODE(0) | PULLUP_EN)},
+	{OFFSET(gpmc_wen),	(MODE(0) | PULLDOWN_EN)},
+	{OFFSET(gpmc_oen_ren),	(MODE(0) | PULLDOWN_EN)},
+	{OFFSET(gpmc_advn_ale),	(MODE(0) | PULLDOWN_EN)},
+	{OFFSET(gpmc_be0n_cle),	(MODE(0) | PULLDOWN_EN)},
+	{-1},
+};
+
+static struct module_pin_mux emmc_pin_mux[] = {
+	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDDIS | RXACTIVE)}, /* EMMC_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_CMD */
+	{OFFSET(gpmc_ad8),  (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT0 */
+	{OFFSET(gpmc_ad9),  (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT1 */
+	{OFFSET(gpmc_ad10), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT2 */
+	{OFFSET(gpmc_ad11), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT3 */
+	{OFFSET(gpmc_ad12), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT4 */
+	{OFFSET(gpmc_ad13), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT5 */
+	{OFFSET(gpmc_ad14), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT6 */
+	{OFFSET(gpmc_ad15), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT7 */
+	{-1},
+};
+
+static struct module_pin_mux spi_flash_pin_mux[] = {
+	{OFFSET(spi0_d0),   (MODE(0) | RXACTIVE | PULLUDEN)},
+	{OFFSET(spi0_d1),   (MODE(0) | RXACTIVE | PULLUDEN)},
+	{OFFSET(spi0_cs0),  (MODE(0) | RXACTIVE | PULLUDEN)},
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},
+	{-1},
+};
+
+void set_uart_mux_conf(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void set_mdio_pin_mux(void)
+{
+	configure_module_pin_mux(mdio_pin_mux);
+}
+
+void set_rgmii_pin_mux(void)
+{
+	configure_module_pin_mux(rgmii1_pin_mux);
+	configure_module_pin_mux(rgmii2_pin_mux);
+}
+
+void set_mux_conf_regs(void)
+{
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(emmc_pin_mux);
+	configure_module_pin_mux(i2c_pin_mux);
+	configure_module_pin_mux(spi_flash_pin_mux);
+	configure_module_pin_mux(nand_pin_mux);
+}
+
+void set_i2c_pin_mux(void)
+{
+	configure_module_pin_mux(i2c_pin_mux);
+}
diff --git a/roms/u-boot/board/compulab/cm_t43/spl.c b/roms/u-boot/board/compulab/cm_t43/spl.c
new file mode 100644
index 000000000..016c63a50
--- /dev/null
+++ b/roms/u-boot/board/compulab/cm_t43/spl.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Compulab, Ltd.
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <spl.h>
+#include <i2c.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/gpio.h>
+#include <power/pmic.h>
+#include <power/tps65218.h>
+#include "board.h"
+
+const struct dpll_params dpll_mpu  = { 800,  24, 1,  -1, -1, -1, -1 };
+const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10,  8,  4 };
+const struct dpll_params dpll_per  = { 960,  24, 5,  -1, -1, -1, -1 };
+const struct dpll_params dpll_ddr  = { 400,  23, 1,  -1,  1, -1, -1 };
+
+const struct ctrl_ioregs ioregs_ddr3 = {
+	.cm0ioctl		= DDR3_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0x0143,
+};
+
+/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
+struct emif_regs ddr3_emif_regs = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000066,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
+	.emif_ddr_ext_phy_ctrl_4	= 0x000000B9,
+	.emif_ddr_ext_phy_ctrl_5	= 0x000000E6,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3[] = {
+	0x00000000,
+	0x00000044,
+	0x00000044,
+	0x00000046,
+	0x00000046,
+	0x00000000,
+	0x00000059,
+	0x00000077,
+	0x00000093,
+	0x000000A8,
+	0x00000000,
+	0x00000019,
+	0x00000037,
+	0x00000053,
+	0x00000068,
+	0x00000000,
+	0x0,
+	0x0,
+	0x40000000,
+	0x08102040
+};
+
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+	*regs = ext_phy_ctrl_const_base_ddr3;
+	*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	return &dpll_mpu;
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+	return &dpll_core;
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+	return &dpll_per;
+}
+
+void scale_vcores(void)
+{
+	set_i2c_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	if (i2c_probe(TPS65218_CHIP_PM))
+		return;
+
+	tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV);
+	tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV);
+}
+
+void sdram_init(void)
+{
+	unsigned long ram_size;
+
+	config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
+	ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (ram_size == 0x80000000 ||
+	    ram_size == 0x40000000 ||
+	    ram_size == 0x20000000)
+		return;
+
+	ddr3_emif_regs.sdram_config = 0x638453B2;
+	config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
+	ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (ram_size == 0x08000000)
+		return;
+
+	hang();
+}
+
diff --git a/roms/u-boot/board/compulab/common/Makefile b/roms/u-boot/board/compulab/common/Makefile
new file mode 100644
index 000000000..7ba92f5db
--- /dev/null
+++ b/roms/u-boot/board/compulab/common/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Author: Igor Grinberg <grinberg@compulab.co.il>
+
+obj-y				+= common.o
+obj-$(CONFIG_SYS_I2C)		+= eeprom.o
+obj-$(CONFIG_LCD)		+= omap3_display.o
+obj-$(CONFIG_SMC911X)		+= omap3_smc911x.o
diff --git a/roms/u-boot/board/compulab/common/common.c b/roms/u-boot/board/compulab/common/common.c
new file mode 100644
index 000000000..528c97df1
--- /dev/null
+++ b/roms/u-boot/board/compulab/common/common.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/bootm.h>
+#include <asm/gpio.h>
+#include <asm/setup.h>
+#include <linux/delay.h>
+
+#include "common.h"
+#include "eeprom.h"
+
+void cl_print_pcb_info(void)
+{
+	u32 board_rev = get_board_rev();
+	u32 rev_major = board_rev / 100;
+	u32 rev_minor = board_rev - (rev_major * 100);
+
+	if ((rev_minor / 10) * 10 == rev_minor)
+		rev_minor = rev_minor / 10;
+
+	printf("PCB:   %u.%u\n", rev_major, rev_minor);
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void __weak get_board_serial(struct tag_serialnr *serialnr)
+{
+	/*
+	 * This corresponds to what happens when we can communicate with the
+	 * eeprom but don't get a valid board serial value.
+	 */
+	serialnr->low = 0;
+	serialnr->high = 0;
+};
+#endif
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label)
+{
+	if (gpio_request(gpio, label)) {
+		printf("Error: can't obtain GPIO%d for %s", gpio, label);
+		return -1;
+	}
+
+	gpio_direction_output(gpio, 0);
+	udelay(10);
+	gpio_set_value(gpio, 1);
+	udelay(1000);
+	return 0;
+}
+
+void cl_usb_hub_deinit(int gpio)
+{
+	gpio_free(gpio);
+}
+#endif
diff --git a/roms/u-boot/board/compulab/common/common.h b/roms/u-boot/board/compulab/common/common.h
new file mode 100644
index 000000000..17cfbb6f2
--- /dev/null
+++ b/roms/u-boot/board/compulab/common/common.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ */
+
+#ifndef _CL_COMMON_
+#define _CL_COMMON_
+
+#include <linux/errno.h>
+
+void cl_print_pcb_info(void);
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label);
+void cl_usb_hub_deinit(int gpio);
+#else /* !CONFIG_CMD_USB */
+static inline int cl_usb_hub_init(int gpio, const char *label)
+{
+	return -ENOSYS;
+}
+static inline void cl_usb_hub_deinit(int gpio) {}
+#endif /* CONFIG_CMD_USB */
+
+#ifdef CONFIG_SMC911X
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+			  int (*reset)(int), int rst_gpio);
+#else /* !CONFIG_SMC911X */
+static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+					int (*reset)(int), int rst_gpio)
+{
+	return -ENOSYS;
+}
+#endif /* CONFIG_SMC911X */
+
+#endif /* _CL_COMMON_ */
diff --git a/roms/u-boot/board/compulab/common/eeprom.c b/roms/u-boot/board/compulab/common/eeprom.c
new file mode 100644
index 000000000..5206cf5c0
--- /dev/null
+++ b/roms/u-boot/board/compulab/common/eeprom.c
@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ */
+
+#include <common.h>
+#include <eeprom.h>
+#include <i2c.h>
+#include <eeprom_layout.h>
+#include <eeprom_field.h>
+#include <asm/setup.h>
+#include <linux/kernel.h>
+#include "eeprom.h"
+
+#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
+# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#endif
+
+#ifndef CONFIG_SYS_I2C_EEPROM_BUS
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
+#endif
+
+#define EEPROM_LAYOUT_VER_OFFSET	44
+#define BOARD_SERIAL_OFFSET		20
+#define BOARD_SERIAL_OFFSET_LEGACY	8
+#define BOARD_REV_OFFSET		0
+#define BOARD_REV_OFFSET_LEGACY		6
+#define BOARD_REV_SIZE			2
+#define PRODUCT_NAME_OFFSET		128
+#define PRODUCT_NAME_SIZE		16
+#define MAC_ADDR_OFFSET			4
+#define MAC_ADDR_OFFSET_LEGACY		0
+
+#define LAYOUT_INVALID	0
+#define LAYOUT_LEGACY	0xff
+
+static int cl_eeprom_bus;
+static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */
+
+static int cl_eeprom_read(uint offset, uchar *buf, int len)
+{
+	int res;
+	unsigned int current_i2c_bus = i2c_get_bus_num();
+
+	res = i2c_set_bus_num(cl_eeprom_bus);
+	if (res < 0)
+		return res;
+
+	res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
+			CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len);
+
+	i2c_set_bus_num(current_i2c_bus);
+
+	return res;
+}
+
+static int cl_eeprom_setup(uint eeprom_bus)
+{
+	int res;
+
+	/*
+	 * We know the setup was already done when the layout is set to a valid
+	 * value and we're using the same bus as before.
+	 */
+	if (cl_eeprom_layout != LAYOUT_INVALID && eeprom_bus == cl_eeprom_bus)
+		return 0;
+
+	cl_eeprom_bus = eeprom_bus;
+	res = cl_eeprom_read(EEPROM_LAYOUT_VER_OFFSET,
+			     (uchar *)&cl_eeprom_layout, 1);
+	if (res) {
+		cl_eeprom_layout = LAYOUT_INVALID;
+		return res;
+	}
+
+	if (cl_eeprom_layout == 0 || cl_eeprom_layout >= 0x20)
+		cl_eeprom_layout = LAYOUT_LEGACY;
+
+	return 0;
+}
+
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	u32 serial[2];
+	uint offset;
+
+	memset(serialnr, 0, sizeof(*serialnr));
+
+	if (cl_eeprom_setup(CONFIG_SYS_I2C_EEPROM_BUS))
+		return;
+
+	offset = (cl_eeprom_layout != LAYOUT_LEGACY) ?
+		BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY;
+
+	if (cl_eeprom_read(offset, (uchar *)serial, 8))
+		return;
+
+	if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) {
+		serialnr->low = serial[0];
+		serialnr->high = serial[1];
+	}
+}
+
+/*
+ * Routine: cl_eeprom_read_mac_addr
+ * Description: read mac address and store it in buf.
+ */
+int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus)
+{
+	uint offset;
+	int err;
+
+	err = cl_eeprom_setup(eeprom_bus);
+	if (err)
+		return err;
+
+	offset = (cl_eeprom_layout != LAYOUT_LEGACY) ?
+			MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY;
+
+	return cl_eeprom_read(offset, buf, 6);
+}
+
+static u32 board_rev;
+
+/*
+ * Routine: cl_eeprom_get_board_rev
+ * Description: read system revision from eeprom
+ */
+u32 cl_eeprom_get_board_rev(uint eeprom_bus)
+{
+	char str[5]; /* Legacy representation can contain at most 4 digits */
+	uint offset = BOARD_REV_OFFSET_LEGACY;
+
+	if (board_rev)
+		return board_rev;
+
+	if (cl_eeprom_setup(eeprom_bus))
+		return 0;
+
+	if (cl_eeprom_layout != LAYOUT_LEGACY)
+		offset = BOARD_REV_OFFSET;
+
+	if (cl_eeprom_read(offset, (uchar *)&board_rev, BOARD_REV_SIZE))
+		return 0;
+
+	/*
+	 * Convert legacy syntactic representation to semantic
+	 * representation. i.e. for rev 1.00: 0x100 --> 0x64
+	 */
+	if (cl_eeprom_layout == LAYOUT_LEGACY) {
+		sprintf(str, "%x", board_rev);
+		board_rev = simple_strtoul(str, NULL, 10);
+	}
+
+	return board_rev;
+};
+
+/*
+ * Routine: cl_eeprom_get_board_rev
+ * Description: read system revision from eeprom
+ *
+ * @buf: buffer to store the product name
+ * @eeprom_bus: i2c bus num of the eeprom
+ *
+ * @return: 0 on success, < 0 on failure
+ */
+int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus)
+{
+	int err;
+
+	if (buf == NULL)
+		return -EINVAL;
+
+	err = cl_eeprom_setup(eeprom_bus);
+	if (err)
+		return err;
+
+	err = cl_eeprom_read(PRODUCT_NAME_OFFSET, buf, PRODUCT_NAME_SIZE);
+	if (!err) /* Protect ourselves from invalid data (unterminated str) */
+		buf[PRODUCT_NAME_SIZE - 1] = '\0';
+
+	return err;
+}
+
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+/**
+ * eeprom_field_print_bin_ver() - print a "version field" which contains binary
+ *				  data
+ *
+ * Treat the field data as simple binary data, and print it formatted as a
+ * version number (2 digits after decimal point).
+ * The field size must be exactly 2 bytes.
+ *
+ * Sample output:
+ *      Field Name      123.45
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_bin_ver(const struct eeprom_field *field)
+{
+	if ((field->buf[0] == 0xff) && (field->buf[1] == 0xff)) {
+		field->buf[0] = 0;
+		field->buf[1] = 0;
+	}
+
+	printf(PRINT_FIELD_SEGMENT, field->name);
+	int major = (field->buf[1] << 8 | field->buf[0]) / 100;
+	int minor = (field->buf[1] << 8 | field->buf[0]) - major * 100;
+	printf("%d.%02d\n", major, minor);
+}
+
+/**
+ * eeprom_field_update_bin_ver() - update a "version field" which contains
+ *				   binary data
+ *
+ * This function takes a version string in the form of x.y (x and y are both
+ * decimal values, y is limited to two digits), translates it to the binary
+ * form, then writes it to the field. The field size must be exactly 2 bytes.
+ *
+ * This function strictly enforces the data syntax, and will not update the
+ * field if there's any deviation from it. It also protects from overflow.
+ *
+ * @field:	an initialized field
+ * @value:	a version string
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+int eeprom_field_update_bin_ver(struct eeprom_field *field, char *value)
+{
+	char *endptr;
+	char *tok = strtok(value, ".");
+	if (tok == NULL)
+		return -1;
+
+	int num = simple_strtol(tok, &endptr, 0);
+	if (*endptr != '\0')
+		return -1;
+
+	tok = strtok(NULL, "");
+	if (tok == NULL)
+		return -1;
+
+	int remainder = simple_strtol(tok, &endptr, 0);
+	if (*endptr != '\0')
+		return -1;
+
+	num = num * 100 + remainder;
+	if (num >> 16)
+		return -1;
+
+	field->buf[0] = (unsigned char)num;
+	field->buf[1] = num >> 8;
+
+	return 0;
+}
+
+char *months[12] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun",
+		    "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"};
+
+/**
+ * eeprom_field_print_date() - print a field which contains date data
+ *
+ * Treat the field data as simple binary data, and print it formatted as a date.
+ * Sample output:
+ *      Field Name      07/Feb/2014
+ *      Field Name      56/BAD/9999
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_date(const struct eeprom_field *field)
+{
+	printf(PRINT_FIELD_SEGMENT, field->name);
+	printf("%02d/", field->buf[0]);
+	if (field->buf[1] >= 1 && field->buf[1] <= 12)
+		printf("%s", months[field->buf[1] - 1]);
+	else
+		printf("BAD");
+
+	printf("/%d\n", field->buf[3] << 8 | field->buf[2]);
+}
+
+static int validate_date(unsigned char day, unsigned char month,
+			unsigned int year)
+{
+	int days_in_february;
+
+	switch (month) {
+	case 0:
+	case 2:
+	case 4:
+	case 6:
+	case 7:
+	case 9:
+	case 11:
+		if (day > 31)
+			return -1;
+		break;
+	case 3:
+	case 5:
+	case 8:
+	case 10:
+		if (day > 30)
+			return -1;
+		break;
+	case 1:
+		days_in_february = 28;
+		if (year % 4 == 0) {
+			if (year % 100 != 0)
+				days_in_february = 29;
+			else if (year % 400 == 0)
+				days_in_february = 29;
+		}
+
+		if (day > days_in_february)
+			return -1;
+
+		break;
+	default:
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * eeprom_field_update_date() - update a date field which contains binary data
+ *
+ * This function takes a date string in the form of x/Mon/y (x and y are both
+ * decimal values), translates it to the binary representation, then writes it
+ * to the field.
+ *
+ * This function strictly enforces the data syntax, and will not update the
+ * field if there's any deviation from it. It also protects from overflow in the
+ * year value, and checks the validity of the date.
+ *
+ * @field:	an initialized field
+ * @value:	a date string
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+int eeprom_field_update_date(struct eeprom_field *field, char *value)
+{
+	char *endptr;
+	char *tok1 = strtok(value, "/");
+	char *tok2 = strtok(NULL, "/");
+	char *tok3 = strtok(NULL, "/");
+
+	if (tok1 == NULL || tok2 == NULL || tok3 == NULL) {
+		printf("%s: syntax error\n", field->name);
+		return -1;
+	}
+
+	unsigned char day = (unsigned char)simple_strtol(tok1, &endptr, 0);
+	if (*endptr != '\0' || day == 0) {
+		printf("%s: invalid day\n", field->name);
+		return -1;
+	}
+
+	unsigned char month;
+	for (month = 1; month <= 12; month++)
+		if (!strcmp(tok2, months[month - 1]))
+			break;
+
+	unsigned int year = simple_strtol(tok3, &endptr, 0);
+	if (*endptr != '\0') {
+		printf("%s: invalid year\n", field->name);
+		return -1;
+	}
+
+	if (validate_date(day, month - 1, year)) {
+		printf("%s: invalid date\n", field->name);
+		return -1;
+	}
+
+	if (year >> 16) {
+		printf("%s: year overflow\n", field->name);
+		return -1;
+	}
+
+	field->buf[0] = day;
+	field->buf[1] = month;
+	field->buf[2] = (unsigned char)year;
+	field->buf[3] = (unsigned char)(year >> 8);
+
+	return 0;
+}
+
+#define	LAYOUT_VERSION_LEGACY 1
+#define	LAYOUT_VERSION_VER1 2
+#define	LAYOUT_VERSION_VER2 3
+#define	LAYOUT_VERSION_VER3 4
+
+extern struct eeprom_field layout_unknown[1];
+
+#define DEFINE_PRINT_UPDATE(x) eeprom_field_print_##x, eeprom_field_update_##x
+
+#ifdef CONFIG_CM_T3X
+struct eeprom_field layout_legacy[5] = {
+	{ "MAC address",          6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Board Revision",       2, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ "Serial Number",        8, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ "Board Configuration", 64, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ RESERVED_FIELDS,      176, NULL, eeprom_field_print_reserved,
+					   eeprom_field_update_ascii },
+};
+#else
+#define layout_legacy layout_unknown
+#endif
+
+#if defined(CONFIG_CM_T3X)
+struct eeprom_field layout_v1[12] = {
+	{ "Major Revision",      2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "Minor Revision",      2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "1st MAC Address",     6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "2nd MAC Address",     6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Production Date",     4, NULL, DEFINE_PRINT_UPDATE(date) },
+	{ "Serial Number",      12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
+	{ RESERVED_FIELDS,      96, NULL, DEFINE_PRINT_UPDATE(reserved) },
+	{ "Product Name",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ RESERVED_FIELDS,      64, NULL, eeprom_field_print_reserved,
+					  eeprom_field_update_ascii },
+};
+#else
+#define layout_v1 layout_unknown
+#endif
+
+struct eeprom_field layout_v2[15] = {
+	{ "Major Revision",            2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "Minor Revision",            2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "1st MAC Address",           6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "2nd MAC Address",           6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Production Date",           4, NULL, DEFINE_PRINT_UPDATE(date) },
+	{ "Serial Number",            12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
+	{ "3rd MAC Address (WIFI)",    6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "4th MAC Address (Bluetooth)", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Layout Version",            1, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ RESERVED_FIELDS,            83, NULL, DEFINE_PRINT_UPDATE(reserved) },
+	{ "Product Name",             16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #1",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #2",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #3",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ RESERVED_FIELDS,            64, NULL, eeprom_field_print_reserved,
+						eeprom_field_update_ascii },
+};
+
+struct eeprom_field layout_v3[16] = {
+	{ "Major Revision",            2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "Minor Revision",            2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "1st MAC Address",           6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "2nd MAC Address",           6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Production Date",           4, NULL, DEFINE_PRINT_UPDATE(date) },
+	{ "Serial Number",            12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
+	{ "3rd MAC Address (WIFI)",    6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "4th MAC Address (Bluetooth)", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Layout Version",            1, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ "CompuLab EEPROM ID",        3, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ RESERVED_FIELDS,            80, NULL, DEFINE_PRINT_UPDATE(reserved) },
+	{ "Product Name",             16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #1",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #2",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #3",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ RESERVED_FIELDS,            64, NULL, eeprom_field_print_reserved,
+						eeprom_field_update_ascii },
+};
+
+void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version)
+{
+	switch (layout->layout_version) {
+	case LAYOUT_VERSION_LEGACY:
+		layout->fields = layout_legacy;
+		layout->num_of_fields = ARRAY_SIZE(layout_legacy);
+		break;
+	case LAYOUT_VERSION_VER1:
+		layout->fields = layout_v1;
+		layout->num_of_fields = ARRAY_SIZE(layout_v1);
+		break;
+	case LAYOUT_VERSION_VER2:
+		layout->fields = layout_v2;
+		layout->num_of_fields = ARRAY_SIZE(layout_v2);
+		break;
+	case LAYOUT_VERSION_VER3:
+		layout->fields = layout_v3;
+		layout->num_of_fields = ARRAY_SIZE(layout_v3);
+		break;
+	default:
+		__eeprom_layout_assign(layout, layout_version);
+	}
+}
+
+int eeprom_parse_layout_version(char *str)
+{
+	if (!strcmp(str, "legacy"))
+		return LAYOUT_VERSION_LEGACY;
+	else if (!strcmp(str, "v1"))
+		return LAYOUT_VERSION_VER1;
+	else if (!strcmp(str, "v2"))
+		return LAYOUT_VERSION_VER2;
+	else if (!strcmp(str, "v3"))
+		return LAYOUT_VERSION_VER3;
+	else
+		return LAYOUT_VERSION_UNRECOGNIZED;
+}
+
+int eeprom_layout_detect(unsigned char *data)
+{
+	switch (data[EEPROM_LAYOUT_VER_OFFSET]) {
+	case 0xff:
+	case 0:
+		return LAYOUT_VERSION_VER1;
+	case 2:
+		return LAYOUT_VERSION_VER2;
+	case 3:
+		return LAYOUT_VERSION_VER3;
+	}
+
+	if (data[EEPROM_LAYOUT_VER_OFFSET] >= 0x20)
+		return LAYOUT_VERSION_LEGACY;
+
+	return LAYOUT_VERSION_UNRECOGNIZED;
+}
+#endif
diff --git a/roms/u-boot/board/compulab/common/eeprom.h b/roms/u-boot/board/compulab/common/eeprom.h
new file mode 100644
index 000000000..a9c0203b8
--- /dev/null
+++ b/roms/u-boot/board/compulab/common/eeprom.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ */
+
+#ifndef _EEPROM_
+#define _EEPROM_
+#include <errno.h>
+
+#ifdef CONFIG_SYS_I2C
+int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus);
+u32 cl_eeprom_get_board_rev(uint eeprom_bus);
+int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus);
+#else
+static inline int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus)
+{
+	return 1;
+}
+static inline u32 cl_eeprom_get_board_rev(uint eeprom_bus)
+{
+	return 0;
+}
+static inline int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus)
+{
+	return -ENOSYS;
+}
+#endif
+
+#endif
diff --git a/roms/u-boot/board/compulab/common/omap3_display.c b/roms/u-boot/board/compulab/common/omap3_display.c
new file mode 100644
index 000000000..cb9ebae7f
--- /dev/null
+++ b/roms/u-boot/board/compulab/common/omap3_display.c
@@ -0,0 +1,452 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012 - 2013 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * Parsing code based on linux/drivers/video/pxafb.c
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <env.h>
+#include <stdio_dev.h>
+#include <asm/arch/dss.h>
+#include <lcd.h>
+#include <scf0403_lcd.h>
+#include <asm/arch-omap3/dss.h>
+
+enum display_type {
+	NONE,
+	DVI,
+	DVI_CUSTOM,
+	DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */
+};
+
+#define CMAP_ADDR	0x80100000
+
+/*
+ * The frame buffer is allocated before we have the chance to parse user input.
+ * To make sure enough memory is allocated for all resolutions, we define
+ * vl_{col | row} to the maximal resolution supported by OMAP3.
+ */
+vidinfo_t panel_info = {
+	.vl_col  = 1400,
+	.vl_row  = 1050,
+	.vl_bpix = LCD_BPP,
+	.cmap = (ushort *)CMAP_ADDR,
+};
+
+static struct panel_config panel_cfg;
+static enum display_type lcd_def;
+
+/*
+ * A note on DVI presets;
+ * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can
+ * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to
+ * support two BMP types with one setting.
+ */
+static const struct panel_config preset_dvi_640X480 = {
+	.lcd_size	= PANEL_LCD_SIZE(640, 480),
+	.timing_h	= DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96),
+	.timing_v	= DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2),
+	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
+	.divisor	= 12 | (1 << 16),
+	.data_lines	= LCD_INTERFACE_24_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_800X600 = {
+	.lcd_size	= PANEL_LCD_SIZE(800, 600),
+	.timing_h	= DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128),
+	.timing_v	= DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4),
+	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
+	.divisor	= 8 | (1 << 16),
+	.data_lines	= LCD_INTERFACE_24_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1024X768 = {
+	.lcd_size	= PANEL_LCD_SIZE(1024, 768),
+	.timing_h	= DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136),
+	.timing_v	= DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6),
+	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
+	.divisor	= 5 | (1 << 16),
+	.data_lines	= LCD_INTERFACE_24_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1152X864 = {
+	.lcd_size	= PANEL_LCD_SIZE(1152, 864),
+	.timing_h	= DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128),
+	.timing_v	= DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3),
+	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
+	.divisor	= 4 | (1 << 16),
+	.data_lines	= LCD_INTERFACE_24_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1280X960 = {
+	.lcd_size	= PANEL_LCD_SIZE(1280, 960),
+	.timing_h	= DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112),
+	.timing_v	= DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3),
+	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
+	.divisor	= 3 | (1 << 16),
+	.data_lines	= LCD_INTERFACE_24_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1280X1024 = {
+	.lcd_size	= PANEL_LCD_SIZE(1280, 1024),
+	.timing_h	= DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112),
+	.timing_v	= DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3),
+	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
+	.divisor	= 3 | (1 << 16),
+	.data_lines	= LCD_INTERFACE_24_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dataimage_480X800 = {
+	.lcd_size	= PANEL_LCD_SIZE(480, 800),
+	.timing_h	= DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2),
+	.timing_v	= DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3),
+	.pol_freq	= DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF,
+	.divisor	= 10 | (1 << 10),
+	.data_lines	= LCD_INTERFACE_18_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+/*
+ * set_resolution_params()
+ *
+ * Due to usage of multiple display related APIs resolution data is located in
+ * more than one place. This function updates them all.
+ */
+static void set_resolution_params(int x, int y)
+{
+	panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y);
+	panel_info.vl_col = x;
+	panel_info.vl_row = y;
+	lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+}
+
+static void set_preset(const struct panel_config preset, int x_res, int y_res)
+{
+	panel_cfg = preset;
+	set_resolution_params(x_res, y_res);
+}
+
+static enum display_type set_dvi_preset(const struct panel_config preset,
+					int x_res, int y_res)
+{
+	set_preset(preset, x_res, y_res);
+	return DVI;
+}
+
+static enum display_type set_dataimage_preset(const struct panel_config preset,
+		int x_res, int y_res)
+{
+	set_preset(preset, x_res, y_res);
+	return DATA_IMAGE;
+}
+
+/*
+ * parse_mode() - parse the mode parameter of custom lcd settings
+ *
+ * @mode:	<res_x>x<res_y>
+ *
+ * Returns -1 on error, 0 on success.
+ */
+static int parse_mode(const char *mode)
+{
+	unsigned int modelen = strlen(mode);
+	int res_specified = 0;
+	unsigned int xres = 0, yres = 0;
+	int yres_specified = 0;
+	int i;
+
+	for (i = modelen - 1; i >= 0; i--) {
+		switch (mode[i]) {
+		case 'x':
+			if (!yres_specified) {
+				yres = simple_strtoul(&mode[i + 1], NULL, 0);
+				yres_specified = 1;
+			} else {
+				goto done_parsing;
+			}
+
+			break;
+		case '0' ... '9':
+			break;
+		default:
+			goto done_parsing;
+		}
+	}
+
+	if (i < 0 && yres_specified) {
+		xres = simple_strtoul(mode, NULL, 0);
+		res_specified = 1;
+	}
+
+done_parsing:
+	if (res_specified) {
+		set_resolution_params(xres, yres);
+	} else {
+		printf("LCD: invalid mode: %s\n", mode);
+		return -1;
+	}
+
+	return 0;
+}
+
+#define PIXEL_CLK_NUMERATOR (26 * 432 / 39)
+/*
+ * parse_pixclock() - Parse the pixclock parameter of custom lcd settings
+ *
+ * @pixclock:	the desired pixel clock
+ *
+ * Returns -1 on error, 0 on success.
+ *
+ * Handling the pixel_clock:
+ *
+ * Pixel clock is defined in the OMAP35x TRM as follows:
+ * pixel_clock =
+ * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) /
+ * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] *
+ * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1))
+ *
+ * In practice, this means that in order to set the
+ * divisor for the desired pixel clock one needs to
+ * solve the following equation:
+ *
+ * 26 * 432 / (39 * <pixel_clock>) = DSS.DISPC_DIVISOR[6:0]
+ *
+ * NOTE: the explicit equation above is reduced. Do not
+ * try to infer anything from these numbers.
+ */
+static int parse_pixclock(char *pixclock)
+{
+	int divisor, pixclock_val;
+	char *pixclk_start = pixclock;
+
+	pixclock_val = simple_strtoul(pixclock, &pixclock, 10);
+	divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val);
+	/* 0 and 1 are illegal values for PCD */
+	if (divisor <= 1)
+		divisor = 2;
+
+	panel_cfg.divisor = divisor | (1 << 16);
+	if (pixclock[0] != '\0') {
+		printf("LCD: invalid value for pixclock:%s\n", pixclk_start);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * parse_setting() - parse a single setting of custom lcd parameters
+ *
+ * @setting:	The custom lcd setting <name>:<value>
+ *
+ * Returns -1 on failure, 0 on success.
+ */
+static int parse_setting(char *setting)
+{
+	int num_val;
+	char *setting_start = setting;
+
+	if (!strncmp(setting, "mode:", 5)) {
+		return parse_mode(setting + 5);
+	} else if (!strncmp(setting, "pixclock:", 9)) {
+		return parse_pixclock(setting + 9);
+	} else if (!strncmp(setting, "left:", 5)) {
+		num_val = simple_strtoul(setting + 5, &setting, 0);
+		panel_cfg.timing_h |= DSS_HBP(num_val);
+	} else if (!strncmp(setting, "right:", 6)) {
+		num_val = simple_strtoul(setting + 6, &setting, 0);
+		panel_cfg.timing_h |= DSS_HFP(num_val);
+	} else if (!strncmp(setting, "upper:", 6)) {
+		num_val = simple_strtoul(setting + 6, &setting, 0);
+		panel_cfg.timing_v |= DSS_VBP(num_val);
+	} else if (!strncmp(setting, "lower:", 6)) {
+		num_val = simple_strtoul(setting + 6, &setting, 0);
+		panel_cfg.timing_v |= DSS_VFP(num_val);
+	} else if (!strncmp(setting, "hsynclen:", 9)) {
+		num_val = simple_strtoul(setting + 9, &setting, 0);
+		panel_cfg.timing_h |= DSS_HSW(num_val);
+	} else if (!strncmp(setting, "vsynclen:", 9)) {
+		num_val = simple_strtoul(setting + 9, &setting, 0);
+		panel_cfg.timing_v |= DSS_VSW(num_val);
+	} else if (!strncmp(setting, "hsync:", 6)) {
+		if (simple_strtoul(setting + 6, &setting, 0) == 0)
+			panel_cfg.pol_freq |= DSS_IHS;
+		else
+			panel_cfg.pol_freq &= ~DSS_IHS;
+	} else if (!strncmp(setting, "vsync:", 6)) {
+		if (simple_strtoul(setting + 6, &setting, 0) == 0)
+			panel_cfg.pol_freq |= DSS_IVS;
+		else
+			panel_cfg.pol_freq &= ~DSS_IVS;
+	} else if (!strncmp(setting, "outputen:", 9)) {
+		if (simple_strtoul(setting + 9, &setting, 0) == 0)
+			panel_cfg.pol_freq |= DSS_IEO;
+		else
+			panel_cfg.pol_freq &= ~DSS_IEO;
+	} else if (!strncmp(setting, "pixclockpol:", 12)) {
+		if (simple_strtoul(setting + 12, &setting, 0) == 0)
+			panel_cfg.pol_freq |= DSS_IPC;
+		else
+			panel_cfg.pol_freq &= ~DSS_IPC;
+	} else if (!strncmp(setting, "active", 6)) {
+		panel_cfg.panel_type = ACTIVE_DISPLAY;
+		return 0; /* Avoid sanity check below */
+	} else if (!strncmp(setting, "passive", 7)) {
+		panel_cfg.panel_type = PASSIVE_DISPLAY;
+		return 0; /* Avoid sanity check below */
+	} else if (!strncmp(setting, "display:", 8)) {
+		if (!strncmp(setting + 8, "dvi", 3)) {
+			lcd_def = DVI_CUSTOM;
+			return 0; /* Avoid sanity check below */
+		}
+	} else {
+		printf("LCD: unknown option %s\n", setting_start);
+		return -1;
+	}
+
+	if (setting[0] != '\0') {
+		printf("LCD: invalid value for %s\n", setting_start);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * env_parse_customlcd() - parse custom lcd params from an environment variable.
+ *
+ * @custom_lcd_params:	The environment variable containing the lcd params.
+ *
+ * Returns -1 on failure, 0 on success.
+ */
+static int parse_customlcd(char *custom_lcd_params)
+{
+	char params_cpy[160];
+	char *setting;
+
+	strncpy(params_cpy, custom_lcd_params, 160);
+	setting = strtok(params_cpy, ",");
+	while (setting) {
+		if (parse_setting(setting) < 0)
+			return -1;
+
+		setting = strtok(NULL, ",");
+	}
+
+	/* Currently we don't support changing this via custom lcd params */
+	panel_cfg.data_lines = LCD_INTERFACE_24_BIT;
+	panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */
+
+	return 0;
+}
+
+/*
+ * env_parse_displaytype() - parse display type.
+ *
+ * Parses the environment variable "displaytype", which contains the
+ * name of the display type or preset, in which case it applies its
+ * configurations.
+ *
+ * Returns the type of display that was specified.
+ */
+static enum display_type env_parse_displaytype(char *displaytype)
+{
+	if (!strncmp(displaytype, "dvi640x480", 10))
+		return set_dvi_preset(preset_dvi_640X480, 640, 480);
+	else if (!strncmp(displaytype, "dvi800x600", 10))
+		return set_dvi_preset(preset_dvi_800X600, 800, 600);
+	else if (!strncmp(displaytype, "dvi1024x768", 11))
+		return set_dvi_preset(preset_dvi_1024X768, 1024, 768);
+	else if (!strncmp(displaytype, "dvi1152x864", 11))
+		return set_dvi_preset(preset_dvi_1152X864, 1152, 864);
+	else if (!strncmp(displaytype, "dvi1280x960", 11))
+		return set_dvi_preset(preset_dvi_1280X960, 1280, 960);
+	else if (!strncmp(displaytype, "dvi1280x1024", 12))
+		return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024);
+	else if (!strncmp(displaytype, "dataimage480x800", 16))
+		return set_dataimage_preset(preset_dataimage_480X800, 480, 800);
+
+	return NONE;
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	struct prcm *prcm = (struct prcm *)PRCM_BASE;
+	char *custom_lcd;
+	char *displaytype = env_get("displaytype");
+
+	if (displaytype == NULL)
+		return;
+
+	lcd_def = env_parse_displaytype(displaytype);
+	/* If we did not recognize the preset, check if it's an env variable */
+	if (lcd_def == NONE) {
+		custom_lcd = env_get(displaytype);
+		if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0)
+			return;
+	}
+
+	panel_cfg.frame_buffer = lcdbase;
+	omap3_dss_panel_config(&panel_cfg);
+	/*
+	 * Pixel clock is defined with many divisions and only few
+	 * multiplications of the system clock. Since DSS FCLK divisor is set
+	 * to 16 by default, we need to set it to a smaller value, like 3
+	 * (chosen via trial and error).
+	 */
+	clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
+}
+
+#ifdef CONFIG_SCF0403_LCD
+static void scf0403_enable(void)
+{
+	gpio_direction_output(58, 1);
+	scf0403_init(157);
+}
+#else
+static inline void scf0403_enable(void) {}
+#endif
+
+void lcd_enable(void)
+{
+	switch (lcd_def) {
+	case NONE:
+		return;
+	case DVI:
+	case DVI_CUSTOM:
+		gpio_direction_output(54, 0); /* Turn on DVI */
+		break;
+	case DATA_IMAGE:
+		scf0403_enable();
+		break;
+	}
+
+	omap3_dss_enable();
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {}
diff --git a/roms/u-boot/board/compulab/common/omap3_smc911x.c b/roms/u-boot/board/compulab/common/omap3_smc911x.c
new file mode 100644
index 000000000..f0d365272
--- /dev/null
+++ b/roms/u-boot/board/compulab/common/omap3_smc911x.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+
+#include "common.h"
+
+static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = {
+	NET_GPMC_CONFIG1,
+	NET_GPMC_CONFIG2,
+	NET_GPMC_CONFIG3,
+	NET_GPMC_CONFIG4,
+	NET_GPMC_CONFIG5,
+	NET_GPMC_CONFIG6,
+	0
+};
+
+static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr)
+{
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config,
+			      &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+	       &ctrl_base->gpmc_nadv_ale);
+}
+
+#ifdef CONFIG_OMAP_GPIO
+static int cl_omap3_smc911x_reset_net_chip(int gpio)
+{
+	int err;
+
+	if (!gpio_is_valid(gpio))
+		return -EINVAL;
+
+	err = gpio_request(gpio, "eth rst");
+	if (err)
+		return err;
+
+	/* Set gpio as output and send a pulse */
+	gpio_direction_output(gpio, 1);
+	udelay(1);
+	gpio_set_value(gpio, 0);
+	mdelay(40);
+	gpio_set_value(gpio, 1);
+	mdelay(1);
+
+	return 0;
+}
+#else /* !CONFIG_OMAP_GPIO */
+static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; }
+#endif /* CONFIG_OMAP_GPIO */
+
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+			  int (*reset)(int), int rst_gpio)
+{
+	int ret;
+
+	cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr);
+
+	if (reset)
+		reset(rst_gpio);
+	else
+		cl_omap3_smc911x_reset_net_chip(rst_gpio);
+
+	ret = smc911x_initialize(id, base_addr);
+	if (ret > 0)
+		return ret;
+
+	printf("Failed initializing SMC911x! ");
+	return 0;
+}
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/Kconfig b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/Kconfig
new file mode 100644
index 000000000..7f5c794bf
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MM_CL_IOT_GATE
+
+config SYS_BOARD
+	default "imx8mm-cl-iot-gate"
+
+config SYS_VENDOR
+	default "compulab"
+
+config SYS_CONFIG_NAME
+	default "imx8mm-cl-iot-gate"
+
+endif
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS
new file mode 100644
index 000000000..9c6b17095
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS
@@ -0,0 +1,6 @@
+Compulab IOT-GATE-iMX8 BOARD
+M:	Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
+S:	Maintained
+F:	board/compulab/imx8mm-cl-iot-gate/
+F:	include/configs/imx8mm-cl-iot-gate.h
+F:	configs/imx8mm-cl-iot-gate_defconfig
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/Makefile b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/Makefile
new file mode 100644
index 000000000..3a2bfc4dc
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2018 NXP
+# Copyright 2020 Linaro
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mm-cl-iot-gate.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += ddr/
+endif
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile
new file mode 100644
index 000000000..591479662
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile
@@ -0,0 +1,8 @@
+obj-y += ddr.o
+obj-y += lpddr4_timing_ff020008.o
+obj-y += lpddr4_timing_ff000110.o
+ifdef CONFIG_TARGET_MCM_IMX8M_MINI
+obj-y += lpddr4_timing_01061010.o
+else
+obj-y += lpddr4_timing_01061010.1_2.o
+endif
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
new file mode 100644
index 000000000..42dd0dbf1
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ * Copyright 2020 Linaro
+ *
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/arch/lpddr4_define.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/gpio.h>
+#include "ddr.h"
+
+static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
+{
+	unsigned int tmp;
+
+	reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
+	do {
+		tmp = reg32_read(DDRC_MRSTAT(0));
+	} while (tmp & 0x1);
+
+	reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
+	reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
+	reg32setbit(DDRC_MRCTRL0(0), 31);
+	do {
+		tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
+	} while ((tmp & 0x8) == 0);
+	tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
+	reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
+	while (tmp) { //try to find a significant byte in the word
+		if (tmp & 0xff) {
+			tmp &= 0xff;
+			break;
+		}
+		tmp >>= 8;
+	}
+	return tmp;
+}
+
+struct lpddr4_desc {
+	char name[16];
+	unsigned int id;
+	unsigned int size;
+	unsigned int count;
+	/* an optional field
+	 * use it if default is not the
+	 * 1-st array entry
+	 */
+	unsigned int _default;
+	/* An optional field to distiguish DRAM chips that
+	 * have different geometry, though return the same MRR.
+	 * Default value 0xff
+	 */
+	u8	subind;
+	struct dram_timing_info *timing;
+	char *desc[4];
+};
+
+#define DEFAULT (('D' << 24) + ('E' << 16) + ('F' << 8) + 'A')
+static const struct lpddr4_desc lpddr4_array[] = {
+	{ .name = "Nanya",	.id = 0x05000010, .subind = 0xff,
+	  .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
+	{ .name = "Samsung",	.id = 0x01061010, .subind = 0xff,
+	  .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
+	{ .name = "Kingston",	.id = 0xff000010, .subind = 0x04,
+	  .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
+	{ .name = "Kingston",	.id = 0xff000010, .subind = 0x02,
+	  .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
+	{ .name = "Micron",	.id = 0xff020008, .subind = 0xff,
+	  .size = 2048, .count = 1, .timing = &ucm_dram_timing_ff020008},
+	{ .name = "Micron",	.id = 0xff000110, .subind = 0xff,
+	  .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
+};
+
+static unsigned int lpddr4_get_mr(void)
+{
+	int i = 0, attempts = 5;
+	unsigned int ddr_info = 0;
+	unsigned int regs[] = { 5, 6, 7, 8 };
+
+	do {
+		for (i = 0 ; i < ARRAY_SIZE(regs) ; i++) {
+			unsigned int data = 0;
+
+			data = lpddr4_mr_read(0xF, regs[i]);
+			ddr_info <<= 8;
+			ddr_info += (data & 0xFF);
+		}
+		if (ddr_info != 0xFFFFFFFF && ddr_info != 0)
+			break; // The attempt was successful
+	} while (--attempts);
+	return	ddr_info;
+}
+
+static void spl_tcm_init(struct lpddr4_tcm_desc *lpddr4_tcm_desc)
+{
+	if (lpddr4_tcm_desc->sign == DEFAULT)
+		return;
+
+	lpddr4_tcm_desc->sign = DEFAULT;
+	lpddr4_tcm_desc->index = 0;
+}
+
+static void spl_tcm_fini(struct lpddr4_tcm_desc *lpddr4_tcm_desc)
+{
+	if (lpddr4_tcm_desc->sign != DEFAULT)
+		return;
+
+	lpddr4_tcm_desc->sign = ~DEFAULT;
+	lpddr4_tcm_desc->index = 0;
+}
+
+#define SPL_TCM_DATA 0x7e0000
+#define SPL_TCM_INIT spl_tcm_init(lpddr4_tcm_desc)
+#define SPL_TCM_FINI spl_tcm_fini(lpddr4_tcm_desc)
+
+void spl_dram_init_compulab(void)
+{
+	unsigned int ddr_info = 0xdeadbeef;
+	unsigned int ddr_info_mrr = 0xdeadbeef;
+	unsigned int ddr_found = 0;
+	int i = 0;
+
+	struct lpddr4_tcm_desc *lpddr4_tcm_desc =
+		(struct lpddr4_tcm_desc *)SPL_TCM_DATA;
+
+	if (lpddr4_tcm_desc->sign != DEFAULT) {
+		/* if not in tcm scan mode */
+		for (i = 0; i < ARRAY_SIZE(lpddr4_array); i++) {
+			if (lpddr4_array[i].id == ddr_info &&
+			    lpddr4_array[i].subind == 0xff) {
+				ddr_found = 1;
+				break;
+			}
+		}
+	}
+
+	/* Walk trought all available ddr ids and apply
+	 * one by one. Save the index at the tcm memory that
+	 * persists after the reset.
+	 */
+	if (ddr_found == 0) {
+		SPL_TCM_INIT;
+
+		if (lpddr4_tcm_desc->index < ARRAY_SIZE(lpddr4_array)) {
+			printf("DDRINFO: Cfg attempt: [ %d/%lu ]\n",
+			       lpddr4_tcm_desc->index + 1,
+			       ARRAY_SIZE(lpddr4_array));
+			i = lpddr4_tcm_desc->index;
+			lpddr4_tcm_desc->index += 1;
+		} else {
+			/* Ran out all available ddr setings */
+			printf("DDRINFO: Ran out all [ %lu ] cfg attempts. A non supported configuration.\n",
+			       ARRAY_SIZE(lpddr4_array));
+			while (1)
+				;
+		}
+		ddr_info = lpddr4_array[i].id;
+	} else {
+		printf("DDRINFO(%s): %s %dG\n", (ddr_found ? "D" : "?"),
+		       lpddr4_array[i].name,
+		       lpddr4_array[i].size);
+	}
+
+	if (ddr_init(lpddr4_array[i].timing)) {
+		SPL_TCM_INIT;
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	ddr_info_mrr = lpddr4_get_mr();
+	if (ddr_info_mrr == 0xFFFFFFFF) {
+		printf("DDRINFO(M): mr5-8 [ 0x%x ] is invalid; reset\n",
+		       ddr_info_mrr);
+		SPL_TCM_INIT;
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	printf("DDRINFO(M): mr5-8 [ 0x%x ]\n", ddr_info_mrr);
+	printf("DDRINFO(%s): mr5-8 [ 0x%x ]\n", (ddr_found ? "E" : "T"),
+	       ddr_info);
+
+	if (ddr_info_mrr != ddr_info) {
+		SPL_TCM_INIT;
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	SPL_TCM_FINI;
+
+	/* Pass the dram size to th U-Boot through the tcm memory */
+	{ /* To figure out what to store into the TCM buffer */
+	  /* For debug purpouse only. To override the real memsize */
+		unsigned int ddr_tcm_size = 0;
+
+		if (ddr_tcm_size == 0 || ddr_tcm_size == -1)
+			ddr_tcm_size = lpddr4_array[i].size;
+
+		lpddr4_tcm_desc->size = ddr_tcm_size;
+	}
+}
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h
new file mode 100644
index 000000000..59c189115
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ * Copyright 2020 Linaro
+ *
+ */
+
+#ifndef __COMPULAB_DDR_H__
+#define __COMPULAB_DDR_H__
+
+extern struct dram_timing_info ucm_dram_timing_ff020008;
+extern struct dram_timing_info ucm_dram_timing_ff000110;
+extern struct dram_timing_info ucm_dram_timing_01061010;
+
+void spl_dram_init_compulab(void);
+
+#define TCM_DATA_CFG 0x7e0000
+
+struct lpddr4_tcm_desc {
+	unsigned int size;
+	unsigned int sign;
+	unsigned int index;
+	unsigned int count;
+};
+
+#endif
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c
new file mode 100644
index 000000000..870a94aec
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c
@@ -0,0 +1,1848 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa1080020},
+	{0x3d400020, 0x223},
+	{0x3d400024, 0x2ee00},
+	{0x3d400064, 0x4900a8},
+	{0x3d4000d0, 0xc0030495},
+	{0x3d4000d4, 0x770000},
+	{0x3d4000dc, 0xc40024},
+	{0x3d4000e0, 0x310000},
+	{0x3d4000e8, 0x66004d},
+	{0x3d4000ec, 0x16004d},
+	{0x3d400100, 0x1618141a},
+	{0x3d400104, 0x504a6},
+	{0x3d40010c, 0x909000},
+	{0x3d400110, 0xb04060b},
+	{0x3d400114, 0x2030909},
+	{0x3d400118, 0x1010006},
+	{0x3d40011c, 0x301},
+	{0x3d400130, 0x20500},
+	{0x3d400134, 0xb100002},
+	{0x3d400138, 0xad},
+	{0x3d400144, 0x78003c},
+	{0x3d400180, 0x2580012},
+	{0x3d400184, 0x1e0493e},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x4938208},
+	{0x3d400194, 0x80303},
+	{0x3d4001b4, 0x1308},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x0},
+	{0x3d4000f4, 0xc99},
+	{0x3d400108, 0x60c1514},
+	{0x3d400200, 0x1f},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0x7070707},
+	{0x3d400250, 0x29001701},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x4000030},
+	{0x3d400264, 0x900093e7},
+	{0x3d40026c, 0x2005574},
+	{0x3d400400, 0x111},
+	{0x3d400408, 0x72ff},
+	{0x3d400494, 0x2100e07},
+	{0x3d400498, 0x620096},
+	{0x3d40049c, 0x1100e07},
+	{0x3d4004a0, 0xc8012c},
+	{0x3d402020, 0x21},
+	{0x3d402024, 0x7d00},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0xc001c},
+	{0x3d4020dc, 0x840000},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004d},
+	{0x3d4020ec, 0x16004d},
+	{0x3d402100, 0xa040305},
+	{0x3d402104, 0x30407},
+	{0x3d402108, 0x203060b},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x2040202},
+	{0x3d402114, 0x2030202},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x1d},
+	{0x3d402144, 0x14000a},
+	{0x3d402180, 0x640004},
+	{0x3d402190, 0x3818200},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x100},
+	{0x3d403020, 0x21},
+	{0x3d403024, 0x1f40},
+	{0x3d403050, 0x20d040},
+	{0x3d403064, 0x30007},
+	{0x3d4030dc, 0x840000},
+	{0x3d4030e0, 0x310000},
+	{0x3d4030e8, 0x66004d},
+	{0x3d4030ec, 0x16004d},
+	{0x3d403100, 0xa010102},
+	{0x3d403104, 0x30404},
+	{0x3d403108, 0x203060b},
+	{0x3d40310c, 0x505000},
+	{0x3d403110, 0x2040202},
+	{0x3d403114, 0x2030202},
+	{0x3d403118, 0x1010004},
+	{0x3d40311c, 0x301},
+	{0x3d403130, 0x20300},
+	{0x3d403134, 0xa100002},
+	{0x3d403138, 0x8},
+	{0x3d403144, 0x50003},
+	{0x3d403180, 0x190004},
+	{0x3d403190, 0x3818200},
+	{0x3d403194, 0x80303},
+	{0x3d4031b4, 0x100},
+	{0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x3},
+	{0x110a3, 0x4},
+	{0x110a4, 0x5},
+	{0x110a5, 0x2},
+	{0x110a6, 0x7},
+	{0x110a7, 0x6},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x3},
+	{0x120a3, 0x2},
+	{0x120a4, 0x5},
+	{0x120a5, 0x4},
+	{0x120a6, 0x7},
+	{0x120a7, 0x6},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x21005f, 0x1ff},
+	{0x21015f, 0x1ff},
+	{0x21105f, 0x1ff},
+	{0x21115f, 0x1ff},
+	{0x21205f, 0x1ff},
+	{0x21215f, 0x1ff},
+	{0x21305f, 0x1ff},
+	{0x21315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0xa},
+	{0x1200c5, 0x7},
+	{0x2200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x2},
+	{0x22002e, 0x2},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x220024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x2},
+	{0x120056, 0xa},
+	{0x220056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x21004d, 0xe00},
+	{0x21014d, 0xe00},
+	{0x21104d, 0xe00},
+	{0x21114d, 0xe00},
+	{0x21204d, 0xe00},
+	{0x21214d, 0xe00},
+	{0x21304d, 0xe00},
+	{0x21314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x210049, 0xeba},
+	{0x210149, 0xeba},
+	{0x211049, 0xeba},
+	{0x211149, 0xeba},
+	{0x212049, 0xeba},
+	{0x212149, 0xeba},
+	{0x213049, 0xeba},
+	{0x213149, 0xeba},
+	{0x43, 0x63},
+	{0x1043, 0x63},
+	{0x2043, 0x63},
+	{0x3043, 0x63},
+	{0x4043, 0x63},
+	{0x5043, 0x63},
+	{0x6043, 0x63},
+	{0x7043, 0x63},
+	{0x8043, 0x63},
+	{0x9043, 0x63},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x258},
+	{0x120008, 0x64},
+	{0x220008, 0x19},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x2200b2, 0xdc},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
+	{0x212043, 0x5a1},
+	{0x212143, 0x5a1},
+	{0x213043, 0x5a1},
+	{0x213143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x2200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
+	{0x200f0, 0x660},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5665},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x200c7, 0x21},
+	{0x1200c7, 0x21},
+	{0x2200c7, 0x21},
+	{0x200ca, 0x24},
+	{0x1200ca, 0x24},
+	{0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0},
+	{ 0x1200b2, 0x0},
+	{ 0x2200b2, 0x0},
+	{ 0x200cb, 0x0},
+	{ 0x10043, 0x0},
+	{ 0x110043, 0x0},
+	{ 0x210043, 0x0},
+	{ 0x10143, 0x0},
+	{ 0x110143, 0x0},
+	{ 0x210143, 0x0},
+	{ 0x11043, 0x0},
+	{ 0x111043, 0x0},
+	{ 0x211043, 0x0},
+	{ 0x11143, 0x0},
+	{ 0x111143, 0x0},
+	{ 0x211143, 0x0},
+	{ 0x12043, 0x0},
+	{ 0x112043, 0x0},
+	{ 0x212043, 0x0},
+	{ 0x12143, 0x0},
+	{ 0x112143, 0x0},
+	{ 0x212143, 0x0},
+	{ 0x13043, 0x0},
+	{ 0x113043, 0x0},
+	{ 0x213043, 0x0},
+	{ 0x13143, 0x0},
+	{ 0x113143, 0x0},
+	{ 0x213143, 0x0},
+	{ 0x80, 0x0},
+	{ 0x100080, 0x0},
+	{ 0x200080, 0x0},
+	{ 0x1080, 0x0},
+	{ 0x101080, 0x0},
+	{ 0x201080, 0x0},
+	{ 0x2080, 0x0},
+	{ 0x102080, 0x0},
+	{ 0x202080, 0x0},
+	{ 0x3080, 0x0},
+	{ 0x103080, 0x0},
+	{ 0x203080, 0x0},
+	{ 0x4080, 0x0},
+	{ 0x104080, 0x0},
+	{ 0x204080, 0x0},
+	{ 0x5080, 0x0},
+	{ 0x105080, 0x0},
+	{ 0x205080, 0x0},
+	{ 0x6080, 0x0},
+	{ 0x106080, 0x0},
+	{ 0x206080, 0x0},
+	{ 0x7080, 0x0},
+	{ 0x107080, 0x0},
+	{ 0x207080, 0x0},
+	{ 0x8080, 0x0},
+	{ 0x108080, 0x0},
+	{ 0x208080, 0x0},
+	{ 0x9080, 0x0},
+	{ 0x109080, 0x0},
+	{ 0x209080, 0x0},
+	{ 0x10080, 0x0},
+	{ 0x110080, 0x0},
+	{ 0x210080, 0x0},
+	{ 0x10180, 0x0},
+	{ 0x110180, 0x0},
+	{ 0x210180, 0x0},
+	{ 0x11080, 0x0},
+	{ 0x111080, 0x0},
+	{ 0x211080, 0x0},
+	{ 0x11180, 0x0},
+	{ 0x111180, 0x0},
+	{ 0x211180, 0x0},
+	{ 0x12080, 0x0},
+	{ 0x112080, 0x0},
+	{ 0x212080, 0x0},
+	{ 0x12180, 0x0},
+	{ 0x112180, 0x0},
+	{ 0x212180, 0x0},
+	{ 0x13080, 0x0},
+	{ 0x113080, 0x0},
+	{ 0x213080, 0x0},
+	{ 0x13180, 0x0},
+	{ 0x113180, 0x0},
+	{ 0x213180, 0x0},
+	{ 0x10081, 0x0},
+	{ 0x110081, 0x0},
+	{ 0x210081, 0x0},
+	{ 0x10181, 0x0},
+	{ 0x110181, 0x0},
+	{ 0x210181, 0x0},
+	{ 0x11081, 0x0},
+	{ 0x111081, 0x0},
+	{ 0x211081, 0x0},
+	{ 0x11181, 0x0},
+	{ 0x111181, 0x0},
+	{ 0x211181, 0x0},
+	{ 0x12081, 0x0},
+	{ 0x112081, 0x0},
+	{ 0x212081, 0x0},
+	{ 0x12181, 0x0},
+	{ 0x112181, 0x0},
+	{ 0x212181, 0x0},
+	{ 0x13081, 0x0},
+	{ 0x113081, 0x0},
+	{ 0x213081, 0x0},
+	{ 0x13181, 0x0},
+	{ 0x113181, 0x0},
+	{ 0x213181, 0x0},
+	{ 0x100d0, 0x0},
+	{ 0x1100d0, 0x0},
+	{ 0x2100d0, 0x0},
+	{ 0x101d0, 0x0},
+	{ 0x1101d0, 0x0},
+	{ 0x2101d0, 0x0},
+	{ 0x110d0, 0x0},
+	{ 0x1110d0, 0x0},
+	{ 0x2110d0, 0x0},
+	{ 0x111d0, 0x0},
+	{ 0x1111d0, 0x0},
+	{ 0x2111d0, 0x0},
+	{ 0x120d0, 0x0},
+	{ 0x1120d0, 0x0},
+	{ 0x2120d0, 0x0},
+	{ 0x121d0, 0x0},
+	{ 0x1121d0, 0x0},
+	{ 0x2121d0, 0x0},
+	{ 0x130d0, 0x0},
+	{ 0x1130d0, 0x0},
+	{ 0x2130d0, 0x0},
+	{ 0x131d0, 0x0},
+	{ 0x1131d0, 0x0},
+	{ 0x2131d0, 0x0},
+	{ 0x100d1, 0x0},
+	{ 0x1100d1, 0x0},
+	{ 0x2100d1, 0x0},
+	{ 0x101d1, 0x0},
+	{ 0x1101d1, 0x0},
+	{ 0x2101d1, 0x0},
+	{ 0x110d1, 0x0},
+	{ 0x1110d1, 0x0},
+	{ 0x2110d1, 0x0},
+	{ 0x111d1, 0x0},
+	{ 0x1111d1, 0x0},
+	{ 0x2111d1, 0x0},
+	{ 0x120d1, 0x0},
+	{ 0x1120d1, 0x0},
+	{ 0x2120d1, 0x0},
+	{ 0x121d1, 0x0},
+	{ 0x1121d1, 0x0},
+	{ 0x2121d1, 0x0},
+	{ 0x130d1, 0x0},
+	{ 0x1130d1, 0x0},
+	{ 0x2130d1, 0x0},
+	{ 0x131d1, 0x0},
+	{ 0x1131d1, 0x0},
+	{ 0x2131d1, 0x0},
+	{ 0x10068, 0x0},
+	{ 0x10168, 0x0},
+	{ 0x10268, 0x0},
+	{ 0x10368, 0x0},
+	{ 0x10468, 0x0},
+	{ 0x10568, 0x0},
+	{ 0x10668, 0x0},
+	{ 0x10768, 0x0},
+	{ 0x10868, 0x0},
+	{ 0x11068, 0x0},
+	{ 0x11168, 0x0},
+	{ 0x11268, 0x0},
+	{ 0x11368, 0x0},
+	{ 0x11468, 0x0},
+	{ 0x11568, 0x0},
+	{ 0x11668, 0x0},
+	{ 0x11768, 0x0},
+	{ 0x11868, 0x0},
+	{ 0x12068, 0x0},
+	{ 0x12168, 0x0},
+	{ 0x12268, 0x0},
+	{ 0x12368, 0x0},
+	{ 0x12468, 0x0},
+	{ 0x12568, 0x0},
+	{ 0x12668, 0x0},
+	{ 0x12768, 0x0},
+	{ 0x12868, 0x0},
+	{ 0x13068, 0x0},
+	{ 0x13168, 0x0},
+	{ 0x13268, 0x0},
+	{ 0x13368, 0x0},
+	{ 0x13468, 0x0},
+	{ 0x13568, 0x0},
+	{ 0x13668, 0x0},
+	{ 0x13768, 0x0},
+	{ 0x13868, 0x0},
+	{ 0x10069, 0x0},
+	{ 0x10169, 0x0},
+	{ 0x10269, 0x0},
+	{ 0x10369, 0x0},
+	{ 0x10469, 0x0},
+	{ 0x10569, 0x0},
+	{ 0x10669, 0x0},
+	{ 0x10769, 0x0},
+	{ 0x10869, 0x0},
+	{ 0x11069, 0x0},
+	{ 0x11169, 0x0},
+	{ 0x11269, 0x0},
+	{ 0x11369, 0x0},
+	{ 0x11469, 0x0},
+	{ 0x11569, 0x0},
+	{ 0x11669, 0x0},
+	{ 0x11769, 0x0},
+	{ 0x11869, 0x0},
+	{ 0x12069, 0x0},
+	{ 0x12169, 0x0},
+	{ 0x12269, 0x0},
+	{ 0x12369, 0x0},
+	{ 0x12469, 0x0},
+	{ 0x12569, 0x0},
+	{ 0x12669, 0x0},
+	{ 0x12769, 0x0},
+	{ 0x12869, 0x0},
+	{ 0x13069, 0x0},
+	{ 0x13169, 0x0},
+	{ 0x13269, 0x0},
+	{ 0x13369, 0x0},
+	{ 0x13469, 0x0},
+	{ 0x13569, 0x0},
+	{ 0x13669, 0x0},
+	{ 0x13769, 0x0},
+	{ 0x13869, 0x0},
+	{ 0x1008c, 0x0},
+	{ 0x11008c, 0x0},
+	{ 0x21008c, 0x0},
+	{ 0x1018c, 0x0},
+	{ 0x11018c, 0x0},
+	{ 0x21018c, 0x0},
+	{ 0x1108c, 0x0},
+	{ 0x11108c, 0x0},
+	{ 0x21108c, 0x0},
+	{ 0x1118c, 0x0},
+	{ 0x11118c, 0x0},
+	{ 0x21118c, 0x0},
+	{ 0x1208c, 0x0},
+	{ 0x11208c, 0x0},
+	{ 0x21208c, 0x0},
+	{ 0x1218c, 0x0},
+	{ 0x11218c, 0x0},
+	{ 0x21218c, 0x0},
+	{ 0x1308c, 0x0},
+	{ 0x11308c, 0x0},
+	{ 0x21308c, 0x0},
+	{ 0x1318c, 0x0},
+	{ 0x11318c, 0x0},
+	{ 0x21318c, 0x0},
+	{ 0x1008d, 0x0},
+	{ 0x11008d, 0x0},
+	{ 0x21008d, 0x0},
+	{ 0x1018d, 0x0},
+	{ 0x11018d, 0x0},
+	{ 0x21018d, 0x0},
+	{ 0x1108d, 0x0},
+	{ 0x11108d, 0x0},
+	{ 0x21108d, 0x0},
+	{ 0x1118d, 0x0},
+	{ 0x11118d, 0x0},
+	{ 0x21118d, 0x0},
+	{ 0x1208d, 0x0},
+	{ 0x11208d, 0x0},
+	{ 0x21208d, 0x0},
+	{ 0x1218d, 0x0},
+	{ 0x11218d, 0x0},
+	{ 0x21218d, 0x0},
+	{ 0x1308d, 0x0},
+	{ 0x11308d, 0x0},
+	{ 0x21308d, 0x0},
+	{ 0x1318d, 0x0},
+	{ 0x11318d, 0x0},
+	{ 0x21318d, 0x0},
+	{ 0x100c0, 0x0},
+	{ 0x1100c0, 0x0},
+	{ 0x2100c0, 0x0},
+	{ 0x101c0, 0x0},
+	{ 0x1101c0, 0x0},
+	{ 0x2101c0, 0x0},
+	{ 0x102c0, 0x0},
+	{ 0x1102c0, 0x0},
+	{ 0x2102c0, 0x0},
+	{ 0x103c0, 0x0},
+	{ 0x1103c0, 0x0},
+	{ 0x2103c0, 0x0},
+	{ 0x104c0, 0x0},
+	{ 0x1104c0, 0x0},
+	{ 0x2104c0, 0x0},
+	{ 0x105c0, 0x0},
+	{ 0x1105c0, 0x0},
+	{ 0x2105c0, 0x0},
+	{ 0x106c0, 0x0},
+	{ 0x1106c0, 0x0},
+	{ 0x2106c0, 0x0},
+	{ 0x107c0, 0x0},
+	{ 0x1107c0, 0x0},
+	{ 0x2107c0, 0x0},
+	{ 0x108c0, 0x0},
+	{ 0x1108c0, 0x0},
+	{ 0x2108c0, 0x0},
+	{ 0x110c0, 0x0},
+	{ 0x1110c0, 0x0},
+	{ 0x2110c0, 0x0},
+	{ 0x111c0, 0x0},
+	{ 0x1111c0, 0x0},
+	{ 0x2111c0, 0x0},
+	{ 0x112c0, 0x0},
+	{ 0x1112c0, 0x0},
+	{ 0x2112c0, 0x0},
+	{ 0x113c0, 0x0},
+	{ 0x1113c0, 0x0},
+	{ 0x2113c0, 0x0},
+	{ 0x114c0, 0x0},
+	{ 0x1114c0, 0x0},
+	{ 0x2114c0, 0x0},
+	{ 0x115c0, 0x0},
+	{ 0x1115c0, 0x0},
+	{ 0x2115c0, 0x0},
+	{ 0x116c0, 0x0},
+	{ 0x1116c0, 0x0},
+	{ 0x2116c0, 0x0},
+	{ 0x117c0, 0x0},
+	{ 0x1117c0, 0x0},
+	{ 0x2117c0, 0x0},
+	{ 0x118c0, 0x0},
+	{ 0x1118c0, 0x0},
+	{ 0x2118c0, 0x0},
+	{ 0x120c0, 0x0},
+	{ 0x1120c0, 0x0},
+	{ 0x2120c0, 0x0},
+	{ 0x121c0, 0x0},
+	{ 0x1121c0, 0x0},
+	{ 0x2121c0, 0x0},
+	{ 0x122c0, 0x0},
+	{ 0x1122c0, 0x0},
+	{ 0x2122c0, 0x0},
+	{ 0x123c0, 0x0},
+	{ 0x1123c0, 0x0},
+	{ 0x2123c0, 0x0},
+	{ 0x124c0, 0x0},
+	{ 0x1124c0, 0x0},
+	{ 0x2124c0, 0x0},
+	{ 0x125c0, 0x0},
+	{ 0x1125c0, 0x0},
+	{ 0x2125c0, 0x0},
+	{ 0x126c0, 0x0},
+	{ 0x1126c0, 0x0},
+	{ 0x2126c0, 0x0},
+	{ 0x127c0, 0x0},
+	{ 0x1127c0, 0x0},
+	{ 0x2127c0, 0x0},
+	{ 0x128c0, 0x0},
+	{ 0x1128c0, 0x0},
+	{ 0x2128c0, 0x0},
+	{ 0x130c0, 0x0},
+	{ 0x1130c0, 0x0},
+	{ 0x2130c0, 0x0},
+	{ 0x131c0, 0x0},
+	{ 0x1131c0, 0x0},
+	{ 0x2131c0, 0x0},
+	{ 0x132c0, 0x0},
+	{ 0x1132c0, 0x0},
+	{ 0x2132c0, 0x0},
+	{ 0x133c0, 0x0},
+	{ 0x1133c0, 0x0},
+	{ 0x2133c0, 0x0},
+	{ 0x134c0, 0x0},
+	{ 0x1134c0, 0x0},
+	{ 0x2134c0, 0x0},
+	{ 0x135c0, 0x0},
+	{ 0x1135c0, 0x0},
+	{ 0x2135c0, 0x0},
+	{ 0x136c0, 0x0},
+	{ 0x1136c0, 0x0},
+	{ 0x2136c0, 0x0},
+	{ 0x137c0, 0x0},
+	{ 0x1137c0, 0x0},
+	{ 0x2137c0, 0x0},
+	{ 0x138c0, 0x0},
+	{ 0x1138c0, 0x0},
+	{ 0x2138c0, 0x0},
+	{ 0x100c1, 0x0},
+	{ 0x1100c1, 0x0},
+	{ 0x2100c1, 0x0},
+	{ 0x101c1, 0x0},
+	{ 0x1101c1, 0x0},
+	{ 0x2101c1, 0x0},
+	{ 0x102c1, 0x0},
+	{ 0x1102c1, 0x0},
+	{ 0x2102c1, 0x0},
+	{ 0x103c1, 0x0},
+	{ 0x1103c1, 0x0},
+	{ 0x2103c1, 0x0},
+	{ 0x104c1, 0x0},
+	{ 0x1104c1, 0x0},
+	{ 0x2104c1, 0x0},
+	{ 0x105c1, 0x0},
+	{ 0x1105c1, 0x0},
+	{ 0x2105c1, 0x0},
+	{ 0x106c1, 0x0},
+	{ 0x1106c1, 0x0},
+	{ 0x2106c1, 0x0},
+	{ 0x107c1, 0x0},
+	{ 0x1107c1, 0x0},
+	{ 0x2107c1, 0x0},
+	{ 0x108c1, 0x0},
+	{ 0x1108c1, 0x0},
+	{ 0x2108c1, 0x0},
+	{ 0x110c1, 0x0},
+	{ 0x1110c1, 0x0},
+	{ 0x2110c1, 0x0},
+	{ 0x111c1, 0x0},
+	{ 0x1111c1, 0x0},
+	{ 0x2111c1, 0x0},
+	{ 0x112c1, 0x0},
+	{ 0x1112c1, 0x0},
+	{ 0x2112c1, 0x0},
+	{ 0x113c1, 0x0},
+	{ 0x1113c1, 0x0},
+	{ 0x2113c1, 0x0},
+	{ 0x114c1, 0x0},
+	{ 0x1114c1, 0x0},
+	{ 0x2114c1, 0x0},
+	{ 0x115c1, 0x0},
+	{ 0x1115c1, 0x0},
+	{ 0x2115c1, 0x0},
+	{ 0x116c1, 0x0},
+	{ 0x1116c1, 0x0},
+	{ 0x2116c1, 0x0},
+	{ 0x117c1, 0x0},
+	{ 0x1117c1, 0x0},
+	{ 0x2117c1, 0x0},
+	{ 0x118c1, 0x0},
+	{ 0x1118c1, 0x0},
+	{ 0x2118c1, 0x0},
+	{ 0x120c1, 0x0},
+	{ 0x1120c1, 0x0},
+	{ 0x2120c1, 0x0},
+	{ 0x121c1, 0x0},
+	{ 0x1121c1, 0x0},
+	{ 0x2121c1, 0x0},
+	{ 0x122c1, 0x0},
+	{ 0x1122c1, 0x0},
+	{ 0x2122c1, 0x0},
+	{ 0x123c1, 0x0},
+	{ 0x1123c1, 0x0},
+	{ 0x2123c1, 0x0},
+	{ 0x124c1, 0x0},
+	{ 0x1124c1, 0x0},
+	{ 0x2124c1, 0x0},
+	{ 0x125c1, 0x0},
+	{ 0x1125c1, 0x0},
+	{ 0x2125c1, 0x0},
+	{ 0x126c1, 0x0},
+	{ 0x1126c1, 0x0},
+	{ 0x2126c1, 0x0},
+	{ 0x127c1, 0x0},
+	{ 0x1127c1, 0x0},
+	{ 0x2127c1, 0x0},
+	{ 0x128c1, 0x0},
+	{ 0x1128c1, 0x0},
+	{ 0x2128c1, 0x0},
+	{ 0x130c1, 0x0},
+	{ 0x1130c1, 0x0},
+	{ 0x2130c1, 0x0},
+	{ 0x131c1, 0x0},
+	{ 0x1131c1, 0x0},
+	{ 0x2131c1, 0x0},
+	{ 0x132c1, 0x0},
+	{ 0x1132c1, 0x0},
+	{ 0x2132c1, 0x0},
+	{ 0x133c1, 0x0},
+	{ 0x1133c1, 0x0},
+	{ 0x2133c1, 0x0},
+	{ 0x134c1, 0x0},
+	{ 0x1134c1, 0x0},
+	{ 0x2134c1, 0x0},
+	{ 0x135c1, 0x0},
+	{ 0x1135c1, 0x0},
+	{ 0x2135c1, 0x0},
+	{ 0x136c1, 0x0},
+	{ 0x1136c1, 0x0},
+	{ 0x2136c1, 0x0},
+	{ 0x137c1, 0x0},
+	{ 0x1137c1, 0x0},
+	{ 0x2137c1, 0x0},
+	{ 0x138c1, 0x0},
+	{ 0x1138c1, 0x0},
+	{ 0x2138c1, 0x0},
+	{ 0x10020, 0x0},
+	{ 0x110020, 0x0},
+	{ 0x210020, 0x0},
+	{ 0x11020, 0x0},
+	{ 0x111020, 0x0},
+	{ 0x211020, 0x0},
+	{ 0x12020, 0x0},
+	{ 0x112020, 0x0},
+	{ 0x212020, 0x0},
+	{ 0x13020, 0x0},
+	{ 0x113020, 0x0},
+	{ 0x213020, 0x0},
+	{ 0x20072, 0x0},
+	{ 0x20073, 0x0},
+	{ 0x20074, 0x0},
+	{ 0x100aa, 0x0},
+	{ 0x110aa, 0x0},
+	{ 0x120aa, 0x0},
+	{ 0x130aa, 0x0},
+	{ 0x20010, 0x0},
+	{ 0x120010, 0x0},
+	{ 0x220010, 0x0},
+	{ 0x20011, 0x0},
+	{ 0x120011, 0x0},
+	{ 0x220011, 0x0},
+	{ 0x100ae, 0x0},
+	{ 0x1100ae, 0x0},
+	{ 0x2100ae, 0x0},
+	{ 0x100af, 0x0},
+	{ 0x1100af, 0x0},
+	{ 0x2100af, 0x0},
+	{ 0x110ae, 0x0},
+	{ 0x1110ae, 0x0},
+	{ 0x2110ae, 0x0},
+	{ 0x110af, 0x0},
+	{ 0x1110af, 0x0},
+	{ 0x2110af, 0x0},
+	{ 0x120ae, 0x0},
+	{ 0x1120ae, 0x0},
+	{ 0x2120ae, 0x0},
+	{ 0x120af, 0x0},
+	{ 0x1120af, 0x0},
+	{ 0x2120af, 0x0},
+	{ 0x130ae, 0x0},
+	{ 0x1130ae, 0x0},
+	{ 0x2130ae, 0x0},
+	{ 0x130af, 0x0},
+	{ 0x1130af, 0x0},
+	{ 0x2130af, 0x0},
+	{ 0x20020, 0x0},
+	{ 0x120020, 0x0},
+	{ 0x220020, 0x0},
+	{ 0x100a0, 0x0},
+	{ 0x100a1, 0x0},
+	{ 0x100a2, 0x0},
+	{ 0x100a3, 0x0},
+	{ 0x100a4, 0x0},
+	{ 0x100a5, 0x0},
+	{ 0x100a6, 0x0},
+	{ 0x100a7, 0x0},
+	{ 0x110a0, 0x0},
+	{ 0x110a1, 0x0},
+	{ 0x110a2, 0x0},
+	{ 0x110a3, 0x0},
+	{ 0x110a4, 0x0},
+	{ 0x110a5, 0x0},
+	{ 0x110a6, 0x0},
+	{ 0x110a7, 0x0},
+	{ 0x120a0, 0x0},
+	{ 0x120a1, 0x0},
+	{ 0x120a2, 0x0},
+	{ 0x120a3, 0x0},
+	{ 0x120a4, 0x0},
+	{ 0x120a5, 0x0},
+	{ 0x120a6, 0x0},
+	{ 0x120a7, 0x0},
+	{ 0x130a0, 0x0},
+	{ 0x130a1, 0x0},
+	{ 0x130a2, 0x0},
+	{ 0x130a3, 0x0},
+	{ 0x130a4, 0x0},
+	{ 0x130a5, 0x0},
+	{ 0x130a6, 0x0},
+	{ 0x130a7, 0x0},
+	{ 0x2007c, 0x0},
+	{ 0x12007c, 0x0},
+	{ 0x22007c, 0x0},
+	{ 0x2007d, 0x0},
+	{ 0x12007d, 0x0},
+	{ 0x22007d, 0x0},
+	{ 0x400fd, 0x0},
+	{ 0x400c0, 0x0},
+	{ 0x90201, 0x0},
+	{ 0x190201, 0x0},
+	{ 0x290201, 0x0},
+	{ 0x90202, 0x0},
+	{ 0x190202, 0x0},
+	{ 0x290202, 0x0},
+	{ 0x90203, 0x0},
+	{ 0x190203, 0x0},
+	{ 0x290203, 0x0},
+	{ 0x90204, 0x0},
+	{ 0x190204, 0x0},
+	{ 0x290204, 0x0},
+	{ 0x90205, 0x0},
+	{ 0x190205, 0x0},
+	{ 0x290205, 0x0},
+	{ 0x90206, 0x0},
+	{ 0x190206, 0x0},
+	{ 0x290206, 0x0},
+	{ 0x90207, 0x0},
+	{ 0x190207, 0x0},
+	{ 0x290207, 0x0},
+	{ 0x90208, 0x0},
+	{ 0x190208, 0x0},
+	{ 0x290208, 0x0},
+	{ 0x10062, 0x0},
+	{ 0x10162, 0x0},
+	{ 0x10262, 0x0},
+	{ 0x10362, 0x0},
+	{ 0x10462, 0x0},
+	{ 0x10562, 0x0},
+	{ 0x10662, 0x0},
+	{ 0x10762, 0x0},
+	{ 0x10862, 0x0},
+	{ 0x11062, 0x0},
+	{ 0x11162, 0x0},
+	{ 0x11262, 0x0},
+	{ 0x11362, 0x0},
+	{ 0x11462, 0x0},
+	{ 0x11562, 0x0},
+	{ 0x11662, 0x0},
+	{ 0x11762, 0x0},
+	{ 0x11862, 0x0},
+	{ 0x12062, 0x0},
+	{ 0x12162, 0x0},
+	{ 0x12262, 0x0},
+	{ 0x12362, 0x0},
+	{ 0x12462, 0x0},
+	{ 0x12562, 0x0},
+	{ 0x12662, 0x0},
+	{ 0x12762, 0x0},
+	{ 0x12862, 0x0},
+	{ 0x13062, 0x0},
+	{ 0x13162, 0x0},
+	{ 0x13262, 0x0},
+	{ 0x13362, 0x0},
+	{ 0x13462, 0x0},
+	{ 0x13562, 0x0},
+	{ 0x13662, 0x0},
+	{ 0x13762, 0x0},
+	{ 0x13862, 0x0},
+	{ 0x20077, 0x0},
+	{ 0x10001, 0x0},
+	{ 0x11001, 0x0},
+	{ 0x12001, 0x0},
+	{ 0x13001, 0x0},
+	{ 0x10040, 0x0},
+	{ 0x10140, 0x0},
+	{ 0x10240, 0x0},
+	{ 0x10340, 0x0},
+	{ 0x10440, 0x0},
+	{ 0x10540, 0x0},
+	{ 0x10640, 0x0},
+	{ 0x10740, 0x0},
+	{ 0x10840, 0x0},
+	{ 0x10030, 0x0},
+	{ 0x10130, 0x0},
+	{ 0x10230, 0x0},
+	{ 0x10330, 0x0},
+	{ 0x10430, 0x0},
+	{ 0x10530, 0x0},
+	{ 0x10630, 0x0},
+	{ 0x10730, 0x0},
+	{ 0x10830, 0x0},
+	{ 0x11040, 0x0},
+	{ 0x11140, 0x0},
+	{ 0x11240, 0x0},
+	{ 0x11340, 0x0},
+	{ 0x11440, 0x0},
+	{ 0x11540, 0x0},
+	{ 0x11640, 0x0},
+	{ 0x11740, 0x0},
+	{ 0x11840, 0x0},
+	{ 0x11030, 0x0},
+	{ 0x11130, 0x0},
+	{ 0x11230, 0x0},
+	{ 0x11330, 0x0},
+	{ 0x11430, 0x0},
+	{ 0x11530, 0x0},
+	{ 0x11630, 0x0},
+	{ 0x11730, 0x0},
+	{ 0x11830, 0x0},
+	{ 0x12040, 0x0},
+	{ 0x12140, 0x0},
+	{ 0x12240, 0x0},
+	{ 0x12340, 0x0},
+	{ 0x12440, 0x0},
+	{ 0x12540, 0x0},
+	{ 0x12640, 0x0},
+	{ 0x12740, 0x0},
+	{ 0x12840, 0x0},
+	{ 0x12030, 0x0},
+	{ 0x12130, 0x0},
+	{ 0x12230, 0x0},
+	{ 0x12330, 0x0},
+	{ 0x12430, 0x0},
+	{ 0x12530, 0x0},
+	{ 0x12630, 0x0},
+	{ 0x12730, 0x0},
+	{ 0x12830, 0x0},
+	{ 0x13040, 0x0},
+	{ 0x13140, 0x0},
+	{ 0x13240, 0x0},
+	{ 0x13340, 0x0},
+	{ 0x13440, 0x0},
+	{ 0x13540, 0x0},
+	{ 0x13640, 0x0},
+	{ 0x13740, 0x0},
+	{ 0x13840, 0x0},
+	{ 0x13030, 0x0},
+	{ 0x13130, 0x0},
+	{ 0x13230, 0x0},
+	{ 0x13330, 0x0},
+	{ 0x13430, 0x0},
+	{ 0x13530, 0x0},
+	{ 0x13630, 0x0},
+	{ 0x13730, 0x0},
+	{ 0x13830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0x960},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x24c4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x24c4},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xc400},
+	{0x54033, 0x3124},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0xc400},
+	{0x54039, 0x3124},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x101},
+	{0x54003, 0x190},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x64},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0x960},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x110},
+	{0x54019, 0x24c4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x24c4},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xc400},
+	{0x54033, 0x3124},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0xc400},
+	{0x54039, 0x3124},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x4b},
+	{0x2000c, 0x96},
+	{0x2000d, 0x5dc},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xc},
+	{0x12000c, 0x19},
+	{0x12000d, 0xfa},
+	{0x12000e, 0x10},
+	{0x22000b, 0x3},
+	{0x22000c, 0x6},
+	{0x22000d, 0x3e},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x220010, 0x5a},
+	{0x220011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info ucm_dram_timing_01061010 = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 2400, 400, 100, },
+};
+
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c
new file mode 100644
index 000000000..5141c04f1
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c
@@ -0,0 +1,1847 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa1080020},
+	{0x3d400020, 0x223},
+	{0x3d400024, 0x3a980},
+	{0x3d400064, 0x5b00d2},
+	{0x3d4000d0, 0xc00305ba},
+	{0x3d4000d4, 0x940000},
+	{0x3d4000dc, 0xd4002d},
+	{0x3d4000e0, 0x310000},
+	{0x3d4000e8, 0x66004d},
+	{0x3d4000ec, 0x16004d},
+	{0x3d400100, 0x191e1920},
+	{0x3d400104, 0x60630},
+	{0x3d40010c, 0xb0b000},
+	{0x3d400110, 0xe04080e},
+	{0x3d400114, 0x2040c0c},
+	{0x3d400118, 0x1010007},
+	{0x3d40011c, 0x401},
+	{0x3d400130, 0x20600},
+	{0x3d400134, 0xc100002},
+	{0x3d400138, 0xd8},
+	{0x3d400144, 0x96004b},
+	{0x3d400180, 0x2ee0017},
+	{0x3d400184, 0x2605b8e},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x497820a},
+	{0x3d400194, 0x80303},
+	{0x3d4001b4, 0x170a},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x0},
+	{0x3d4000f4, 0xc99},
+	{0x3d400108, 0x70e1617},
+	{0x3d400200, 0x1f},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0x7070707},
+	{0x3d400250, 0x29001701},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x4000030},
+	{0x3d400264, 0x900093e7},
+	{0x3d40026c, 0x2005574},
+	{0x3d400400, 0x111},
+	{0x3d400408, 0x72ff},
+	{0x3d400494, 0x2100e07},
+	{0x3d400498, 0x620096},
+	{0x3d40049c, 0x1100e07},
+	{0x3d4004a0, 0xc8012c},
+	{0x3d402020, 0x21},
+	{0x3d402024, 0x7d00},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0xc001c},
+	{0x3d4020dc, 0x840000},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004d},
+	{0x3d4020ec, 0x16004d},
+	{0x3d402100, 0xa040305},
+	{0x3d402104, 0x30407},
+	{0x3d402108, 0x203060b},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x2040202},
+	{0x3d402114, 0x2030202},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x1d},
+	{0x3d402144, 0x14000a},
+	{0x3d402180, 0x640004},
+	{0x3d402190, 0x3818200},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x100},
+	{0x3d403020, 0x21},
+	{0x3d403024, 0x1f40},
+	{0x3d403050, 0x20d040},
+	{0x3d403064, 0x30007},
+	{0x3d4030dc, 0x840000},
+	{0x3d4030e0, 0x310000},
+	{0x3d4030e8, 0x66004d},
+	{0x3d4030ec, 0x16004d},
+	{0x3d403100, 0xa010102},
+	{0x3d403104, 0x30404},
+	{0x3d403108, 0x203060b},
+	{0x3d40310c, 0x505000},
+	{0x3d403110, 0x2040202},
+	{0x3d403114, 0x2030202},
+	{0x3d403118, 0x1010004},
+	{0x3d40311c, 0x301},
+	{0x3d403130, 0x20300},
+	{0x3d403134, 0xa100002},
+	{0x3d403138, 0x8},
+	{0x3d403144, 0x50003},
+	{0x3d403180, 0x190004},
+	{0x3d403190, 0x3818200},
+	{0x3d403194, 0x80303},
+	{0x3d4031b4, 0x100},
+	{0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x3},
+	{0x110a3, 0x4},
+	{0x110a4, 0x5},
+	{0x110a5, 0x2},
+	{0x110a6, 0x7},
+	{0x110a7, 0x6},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x3},
+	{0x120a3, 0x2},
+	{0x120a4, 0x5},
+	{0x120a5, 0x4},
+	{0x120a6, 0x7},
+	{0x120a7, 0x6},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x21005f, 0x1ff},
+	{0x21015f, 0x1ff},
+	{0x21105f, 0x1ff},
+	{0x21115f, 0x1ff},
+	{0x21205f, 0x1ff},
+	{0x21215f, 0x1ff},
+	{0x21305f, 0x1ff},
+	{0x21315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x19},
+	{0x1200c5, 0x7},
+	{0x2200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x2},
+	{0x22002e, 0x2},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x220024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x3},
+	{0x120056, 0xa},
+	{0x220056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x21004d, 0xe00},
+	{0x21014d, 0xe00},
+	{0x21104d, 0xe00},
+	{0x21114d, 0xe00},
+	{0x21204d, 0xe00},
+	{0x21214d, 0xe00},
+	{0x21304d, 0xe00},
+	{0x21314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x210049, 0xeba},
+	{0x210149, 0xeba},
+	{0x211049, 0xeba},
+	{0x211149, 0xeba},
+	{0x212049, 0xeba},
+	{0x212149, 0xeba},
+	{0x213049, 0xeba},
+	{0x213149, 0xeba},
+	{0x43, 0x63},
+	{0x1043, 0x63},
+	{0x2043, 0x63},
+	{0x3043, 0x63},
+	{0x4043, 0x63},
+	{0x5043, 0x63},
+	{0x6043, 0x63},
+	{0x7043, 0x63},
+	{0x8043, 0x63},
+	{0x9043, 0x63},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x2ee},
+	{0x120008, 0x64},
+	{0x220008, 0x19},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x2200b2, 0xdc},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
+	{0x212043, 0x5a1},
+	{0x212143, 0x5a1},
+	{0x213043, 0x5a1},
+	{0x213143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x2200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
+	{0x200f0, 0x660},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5665},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x200c7, 0x21},
+	{0x1200c7, 0x21},
+	{0x2200c7, 0x21},
+	{0x200ca, 0x24},
+	{0x1200ca, 0x24},
+	{0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0},
+	{ 0x1200b2, 0x0},
+	{ 0x2200b2, 0x0},
+	{ 0x200cb, 0x0},
+	{ 0x10043, 0x0},
+	{ 0x110043, 0x0},
+	{ 0x210043, 0x0},
+	{ 0x10143, 0x0},
+	{ 0x110143, 0x0},
+	{ 0x210143, 0x0},
+	{ 0x11043, 0x0},
+	{ 0x111043, 0x0},
+	{ 0x211043, 0x0},
+	{ 0x11143, 0x0},
+	{ 0x111143, 0x0},
+	{ 0x211143, 0x0},
+	{ 0x12043, 0x0},
+	{ 0x112043, 0x0},
+	{ 0x212043, 0x0},
+	{ 0x12143, 0x0},
+	{ 0x112143, 0x0},
+	{ 0x212143, 0x0},
+	{ 0x13043, 0x0},
+	{ 0x113043, 0x0},
+	{ 0x213043, 0x0},
+	{ 0x13143, 0x0},
+	{ 0x113143, 0x0},
+	{ 0x213143, 0x0},
+	{ 0x80, 0x0},
+	{ 0x100080, 0x0},
+	{ 0x200080, 0x0},
+	{ 0x1080, 0x0},
+	{ 0x101080, 0x0},
+	{ 0x201080, 0x0},
+	{ 0x2080, 0x0},
+	{ 0x102080, 0x0},
+	{ 0x202080, 0x0},
+	{ 0x3080, 0x0},
+	{ 0x103080, 0x0},
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+	{ 0x400c0, 0x0},
+	{ 0x90201, 0x0},
+	{ 0x190201, 0x0},
+	{ 0x290201, 0x0},
+	{ 0x90202, 0x0},
+	{ 0x190202, 0x0},
+	{ 0x290202, 0x0},
+	{ 0x90203, 0x0},
+	{ 0x190203, 0x0},
+	{ 0x290203, 0x0},
+	{ 0x90204, 0x0},
+	{ 0x190204, 0x0},
+	{ 0x290204, 0x0},
+	{ 0x90205, 0x0},
+	{ 0x190205, 0x0},
+	{ 0x290205, 0x0},
+	{ 0x90206, 0x0},
+	{ 0x190206, 0x0},
+	{ 0x290206, 0x0},
+	{ 0x90207, 0x0},
+	{ 0x190207, 0x0},
+	{ 0x290207, 0x0},
+	{ 0x90208, 0x0},
+	{ 0x190208, 0x0},
+	{ 0x290208, 0x0},
+	{ 0x10062, 0x0},
+	{ 0x10162, 0x0},
+	{ 0x10262, 0x0},
+	{ 0x10362, 0x0},
+	{ 0x10462, 0x0},
+	{ 0x10562, 0x0},
+	{ 0x10662, 0x0},
+	{ 0x10762, 0x0},
+	{ 0x10862, 0x0},
+	{ 0x11062, 0x0},
+	{ 0x11162, 0x0},
+	{ 0x11262, 0x0},
+	{ 0x11362, 0x0},
+	{ 0x11462, 0x0},
+	{ 0x11562, 0x0},
+	{ 0x11662, 0x0},
+	{ 0x11762, 0x0},
+	{ 0x11862, 0x0},
+	{ 0x12062, 0x0},
+	{ 0x12162, 0x0},
+	{ 0x12262, 0x0},
+	{ 0x12362, 0x0},
+	{ 0x12462, 0x0},
+	{ 0x12562, 0x0},
+	{ 0x12662, 0x0},
+	{ 0x12762, 0x0},
+	{ 0x12862, 0x0},
+	{ 0x13062, 0x0},
+	{ 0x13162, 0x0},
+	{ 0x13262, 0x0},
+	{ 0x13362, 0x0},
+	{ 0x13462, 0x0},
+	{ 0x13562, 0x0},
+	{ 0x13662, 0x0},
+	{ 0x13762, 0x0},
+	{ 0x13862, 0x0},
+	{ 0x20077, 0x0},
+	{ 0x10001, 0x0},
+	{ 0x11001, 0x0},
+	{ 0x12001, 0x0},
+	{ 0x13001, 0x0},
+	{ 0x10040, 0x0},
+	{ 0x10140, 0x0},
+	{ 0x10240, 0x0},
+	{ 0x10340, 0x0},
+	{ 0x10440, 0x0},
+	{ 0x10540, 0x0},
+	{ 0x10640, 0x0},
+	{ 0x10740, 0x0},
+	{ 0x10840, 0x0},
+	{ 0x10030, 0x0},
+	{ 0x10130, 0x0},
+	{ 0x10230, 0x0},
+	{ 0x10330, 0x0},
+	{ 0x10430, 0x0},
+	{ 0x10530, 0x0},
+	{ 0x10630, 0x0},
+	{ 0x10730, 0x0},
+	{ 0x10830, 0x0},
+	{ 0x11040, 0x0},
+	{ 0x11140, 0x0},
+	{ 0x11240, 0x0},
+	{ 0x11340, 0x0},
+	{ 0x11440, 0x0},
+	{ 0x11540, 0x0},
+	{ 0x11640, 0x0},
+	{ 0x11740, 0x0},
+	{ 0x11840, 0x0},
+	{ 0x11030, 0x0},
+	{ 0x11130, 0x0},
+	{ 0x11230, 0x0},
+	{ 0x11330, 0x0},
+	{ 0x11430, 0x0},
+	{ 0x11530, 0x0},
+	{ 0x11630, 0x0},
+	{ 0x11730, 0x0},
+	{ 0x11830, 0x0},
+	{ 0x12040, 0x0},
+	{ 0x12140, 0x0},
+	{ 0x12240, 0x0},
+	{ 0x12340, 0x0},
+	{ 0x12440, 0x0},
+	{ 0x12540, 0x0},
+	{ 0x12640, 0x0},
+	{ 0x12740, 0x0},
+	{ 0x12840, 0x0},
+	{ 0x12030, 0x0},
+	{ 0x12130, 0x0},
+	{ 0x12230, 0x0},
+	{ 0x12330, 0x0},
+	{ 0x12430, 0x0},
+	{ 0x12530, 0x0},
+	{ 0x12630, 0x0},
+	{ 0x12730, 0x0},
+	{ 0x12830, 0x0},
+	{ 0x13040, 0x0},
+	{ 0x13140, 0x0},
+	{ 0x13240, 0x0},
+	{ 0x13340, 0x0},
+	{ 0x13440, 0x0},
+	{ 0x13540, 0x0},
+	{ 0x13640, 0x0},
+	{ 0x13740, 0x0},
+	{ 0x13840, 0x0},
+	{ 0x13030, 0x0},
+	{ 0x13130, 0x0},
+	{ 0x13230, 0x0},
+	{ 0x13330, 0x0},
+	{ 0x13430, 0x0},
+	{ 0x13530, 0x0},
+	{ 0x13630, 0x0},
+	{ 0x13730, 0x0},
+	{ 0x13830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xbb8},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x101},
+	{0x54003, 0x190},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x64},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xbb8},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x5d},
+	{0x2000c, 0xbb},
+	{0x2000d, 0x753},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xc},
+	{0x12000c, 0x19},
+	{0x12000d, 0xfa},
+	{0x12000e, 0x10},
+	{0x22000b, 0x3},
+	{0x22000c, 0x6},
+	{0x22000d, 0x3e},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x220010, 0x5a},
+	{0x220011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info ucm_dram_timing_01061010 = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c
new file mode 100644
index 000000000..233472249
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c
@@ -0,0 +1,1847 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa3080020},
+	{0x3d400020, 0x223},
+	{0x3d400024, 0x3a980},
+	{0x3d400064, 0x5b00d2},
+	{0x3d4000d0, 0xc00305ba},
+	{0x3d4000d4, 0x940000},
+	{0x3d4000dc, 0xd4002d},
+	{0x3d4000e0, 0x310000},
+	{0x3d4000e8, 0x66004d},
+	{0x3d4000ec, 0x16004d},
+	{0x3d400100, 0x191e1920},
+	{0x3d400104, 0x60630},
+	{0x3d40010c, 0xb0b000},
+	{0x3d400110, 0xe04080e},
+	{0x3d400114, 0x2040c0c},
+	{0x3d400118, 0x1010007},
+	{0x3d40011c, 0x401},
+	{0x3d400130, 0x20600},
+	{0x3d400134, 0xc100002},
+	{0x3d400138, 0xd8},
+	{0x3d400144, 0x96004b},
+	{0x3d400180, 0x2ee0017},
+	{0x3d400184, 0x2605b8e},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x497820a},
+	{0x3d400194, 0x80303},
+	{0x3d4001b4, 0x170a},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x0},
+	{0x3d4000f4, 0xc99},
+	{0x3d400108, 0x70e1617},
+	{0x3d400200, 0x17},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0x7070707},
+	{0x3d400250, 0x29001701},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x4000030},
+	{0x3d400264, 0x900093e7},
+	{0x3d40026c, 0x2005574},
+	{0x3d400400, 0x111},
+	{0x3d400408, 0x72ff},
+	{0x3d400494, 0x2100e07},
+	{0x3d400498, 0x620096},
+	{0x3d40049c, 0x1100e07},
+	{0x3d4004a0, 0xc8012c},
+	{0x3d402020, 0x21},
+	{0x3d402024, 0x7d00},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0xc001c},
+	{0x3d4020dc, 0x840000},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004d},
+	{0x3d4020ec, 0x16004d},
+	{0x3d402100, 0xa040305},
+	{0x3d402104, 0x30407},
+	{0x3d402108, 0x203060b},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x2040202},
+	{0x3d402114, 0x2030202},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x1d},
+	{0x3d402144, 0x14000a},
+	{0x3d402180, 0x640004},
+	{0x3d402190, 0x3818200},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x100},
+	{0x3d403020, 0x21},
+	{0x3d403024, 0x1f40},
+	{0x3d403050, 0x20d040},
+	{0x3d403064, 0x30007},
+	{0x3d4030dc, 0x840000},
+	{0x3d4030e0, 0x310000},
+	{0x3d4030e8, 0x66004d},
+	{0x3d4030ec, 0x16004d},
+	{0x3d403100, 0xa010102},
+	{0x3d403104, 0x30404},
+	{0x3d403108, 0x203060b},
+	{0x3d40310c, 0x505000},
+	{0x3d403110, 0x2040202},
+	{0x3d403114, 0x2030202},
+	{0x3d403118, 0x1010004},
+	{0x3d40311c, 0x301},
+	{0x3d403130, 0x20300},
+	{0x3d403134, 0xa100002},
+	{0x3d403138, 0x8},
+	{0x3d403144, 0x50003},
+	{0x3d403180, 0x190004},
+	{0x3d403190, 0x3818200},
+	{0x3d403194, 0x80303},
+	{0x3d4031b4, 0x100},
+	{0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x3},
+	{0x110a3, 0x4},
+	{0x110a4, 0x5},
+	{0x110a5, 0x2},
+	{0x110a6, 0x7},
+	{0x110a7, 0x6},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x3},
+	{0x120a3, 0x2},
+	{0x120a4, 0x5},
+	{0x120a5, 0x4},
+	{0x120a6, 0x7},
+	{0x120a7, 0x6},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x21005f, 0x1ff},
+	{0x21015f, 0x1ff},
+	{0x21105f, 0x1ff},
+	{0x21115f, 0x1ff},
+	{0x21205f, 0x1ff},
+	{0x21215f, 0x1ff},
+	{0x21305f, 0x1ff},
+	{0x21315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x19},
+	{0x1200c5, 0x7},
+	{0x2200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x2},
+	{0x22002e, 0x2},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x220024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x3},
+	{0x120056, 0xa},
+	{0x220056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x21004d, 0xe00},
+	{0x21014d, 0xe00},
+	{0x21104d, 0xe00},
+	{0x21114d, 0xe00},
+	{0x21204d, 0xe00},
+	{0x21214d, 0xe00},
+	{0x21304d, 0xe00},
+	{0x21314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x210049, 0xeba},
+	{0x210149, 0xeba},
+	{0x211049, 0xeba},
+	{0x211149, 0xeba},
+	{0x212049, 0xeba},
+	{0x212149, 0xeba},
+	{0x213049, 0xeba},
+	{0x213149, 0xeba},
+	{0x43, 0x63},
+	{0x1043, 0x63},
+	{0x2043, 0x63},
+	{0x3043, 0x63},
+	{0x4043, 0x63},
+	{0x5043, 0x63},
+	{0x6043, 0x63},
+	{0x7043, 0x63},
+	{0x8043, 0x63},
+	{0x9043, 0x63},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x2ee},
+	{0x120008, 0x64},
+	{0x220008, 0x19},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x2200b2, 0xdc},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
+	{0x212043, 0x5a1},
+	{0x212143, 0x5a1},
+	{0x213043, 0x5a1},
+	{0x213143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x2200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
+	{0x200f0, 0x660},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5665},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x200c7, 0x21},
+	{0x1200c7, 0x21},
+	{0x2200c7, 0x21},
+	{0x200ca, 0x24},
+	{0x1200ca, 0x24},
+	{0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0},
+	{ 0x1200b2, 0x0},
+	{ 0x2200b2, 0x0},
+	{ 0x200cb, 0x0},
+	{ 0x10043, 0x0},
+	{ 0x110043, 0x0},
+	{ 0x210043, 0x0},
+	{ 0x10143, 0x0},
+	{ 0x110143, 0x0},
+	{ 0x210143, 0x0},
+	{ 0x11043, 0x0},
+	{ 0x111043, 0x0},
+	{ 0x211043, 0x0},
+	{ 0x11143, 0x0},
+	{ 0x111143, 0x0},
+	{ 0x211143, 0x0},
+	{ 0x12043, 0x0},
+	{ 0x112043, 0x0},
+	{ 0x212043, 0x0},
+	{ 0x12143, 0x0},
+	{ 0x112143, 0x0},
+	{ 0x212143, 0x0},
+	{ 0x13043, 0x0},
+	{ 0x113043, 0x0},
+	{ 0x213043, 0x0},
+	{ 0x13143, 0x0},
+	{ 0x113143, 0x0},
+	{ 0x213143, 0x0},
+	{ 0x80, 0x0},
+	{ 0x100080, 0x0},
+	{ 0x200080, 0x0},
+	{ 0x1080, 0x0},
+	{ 0x101080, 0x0},
+	{ 0x201080, 0x0},
+	{ 0x2080, 0x0},
+	{ 0x102080, 0x0},
+	{ 0x202080, 0x0},
+	{ 0x3080, 0x0},
+	{ 0x103080, 0x0},
+	{ 0x203080, 0x0},
+	{ 0x4080, 0x0},
+	{ 0x104080, 0x0},
+	{ 0x204080, 0x0},
+	{ 0x5080, 0x0},
+	{ 0x105080, 0x0},
+	{ 0x205080, 0x0},
+	{ 0x6080, 0x0},
+	{ 0x106080, 0x0},
+	{ 0x206080, 0x0},
+	{ 0x7080, 0x0},
+	{ 0x107080, 0x0},
+	{ 0x207080, 0x0},
+	{ 0x8080, 0x0},
+	{ 0x108080, 0x0},
+	{ 0x208080, 0x0},
+	{ 0x9080, 0x0},
+	{ 0x109080, 0x0},
+	{ 0x209080, 0x0},
+	{ 0x10080, 0x0},
+	{ 0x110080, 0x0},
+	{ 0x210080, 0x0},
+	{ 0x10180, 0x0},
+	{ 0x110180, 0x0},
+	{ 0x210180, 0x0},
+	{ 0x11080, 0x0},
+	{ 0x111080, 0x0},
+	{ 0x211080, 0x0},
+	{ 0x11180, 0x0},
+	{ 0x111180, 0x0},
+	{ 0x211180, 0x0},
+	{ 0x12080, 0x0},
+	{ 0x112080, 0x0},
+	{ 0x212080, 0x0},
+	{ 0x12180, 0x0},
+	{ 0x112180, 0x0},
+	{ 0x212180, 0x0},
+	{ 0x13080, 0x0},
+	{ 0x113080, 0x0},
+	{ 0x213080, 0x0},
+	{ 0x13180, 0x0},
+	{ 0x113180, 0x0},
+	{ 0x213180, 0x0},
+	{ 0x10081, 0x0},
+	{ 0x110081, 0x0},
+	{ 0x210081, 0x0},
+	{ 0x10181, 0x0},
+	{ 0x110181, 0x0},
+	{ 0x210181, 0x0},
+	{ 0x11081, 0x0},
+	{ 0x111081, 0x0},
+	{ 0x211081, 0x0},
+	{ 0x11181, 0x0},
+	{ 0x111181, 0x0},
+	{ 0x211181, 0x0},
+	{ 0x12081, 0x0},
+	{ 0x112081, 0x0},
+	{ 0x212081, 0x0},
+	{ 0x12181, 0x0},
+	{ 0x112181, 0x0},
+	{ 0x212181, 0x0},
+	{ 0x13081, 0x0},
+	{ 0x113081, 0x0},
+	{ 0x213081, 0x0},
+	{ 0x13181, 0x0},
+	{ 0x113181, 0x0},
+	{ 0x213181, 0x0},
+	{ 0x100d0, 0x0},
+	{ 0x1100d0, 0x0},
+	{ 0x2100d0, 0x0},
+	{ 0x101d0, 0x0},
+	{ 0x1101d0, 0x0},
+	{ 0x2101d0, 0x0},
+	{ 0x110d0, 0x0},
+	{ 0x1110d0, 0x0},
+	{ 0x2110d0, 0x0},
+	{ 0x111d0, 0x0},
+	{ 0x1111d0, 0x0},
+	{ 0x2111d0, 0x0},
+	{ 0x120d0, 0x0},
+	{ 0x1120d0, 0x0},
+	{ 0x2120d0, 0x0},
+	{ 0x121d0, 0x0},
+	{ 0x1121d0, 0x0},
+	{ 0x2121d0, 0x0},
+	{ 0x130d0, 0x0},
+	{ 0x1130d0, 0x0},
+	{ 0x2130d0, 0x0},
+	{ 0x131d0, 0x0},
+	{ 0x1131d0, 0x0},
+	{ 0x2131d0, 0x0},
+	{ 0x100d1, 0x0},
+	{ 0x1100d1, 0x0},
+	{ 0x2100d1, 0x0},
+	{ 0x101d1, 0x0},
+	{ 0x1101d1, 0x0},
+	{ 0x2101d1, 0x0},
+	{ 0x110d1, 0x0},
+	{ 0x1110d1, 0x0},
+	{ 0x2110d1, 0x0},
+	{ 0x111d1, 0x0},
+	{ 0x1111d1, 0x0},
+	{ 0x2111d1, 0x0},
+	{ 0x120d1, 0x0},
+	{ 0x1120d1, 0x0},
+	{ 0x2120d1, 0x0},
+	{ 0x121d1, 0x0},
+	{ 0x1121d1, 0x0},
+	{ 0x2121d1, 0x0},
+	{ 0x130d1, 0x0},
+	{ 0x1130d1, 0x0},
+	{ 0x2130d1, 0x0},
+	{ 0x131d1, 0x0},
+	{ 0x1131d1, 0x0},
+	{ 0x2131d1, 0x0},
+	{ 0x10068, 0x0},
+	{ 0x10168, 0x0},
+	{ 0x10268, 0x0},
+	{ 0x10368, 0x0},
+	{ 0x10468, 0x0},
+	{ 0x10568, 0x0},
+	{ 0x10668, 0x0},
+	{ 0x10768, 0x0},
+	{ 0x10868, 0x0},
+	{ 0x11068, 0x0},
+	{ 0x11168, 0x0},
+	{ 0x11268, 0x0},
+	{ 0x11368, 0x0},
+	{ 0x11468, 0x0},
+	{ 0x11568, 0x0},
+	{ 0x11668, 0x0},
+	{ 0x11768, 0x0},
+	{ 0x11868, 0x0},
+	{ 0x12068, 0x0},
+	{ 0x12168, 0x0},
+	{ 0x12268, 0x0},
+	{ 0x12368, 0x0},
+	{ 0x12468, 0x0},
+	{ 0x12568, 0x0},
+	{ 0x12668, 0x0},
+	{ 0x12768, 0x0},
+	{ 0x12868, 0x0},
+	{ 0x13068, 0x0},
+	{ 0x13168, 0x0},
+	{ 0x13268, 0x0},
+	{ 0x13368, 0x0},
+	{ 0x13468, 0x0},
+	{ 0x13568, 0x0},
+	{ 0x13668, 0x0},
+	{ 0x13768, 0x0},
+	{ 0x13868, 0x0},
+	{ 0x10069, 0x0},
+	{ 0x10169, 0x0},
+	{ 0x10269, 0x0},
+	{ 0x10369, 0x0},
+	{ 0x10469, 0x0},
+	{ 0x10569, 0x0},
+	{ 0x10669, 0x0},
+	{ 0x10769, 0x0},
+	{ 0x10869, 0x0},
+	{ 0x11069, 0x0},
+	{ 0x11169, 0x0},
+	{ 0x11269, 0x0},
+	{ 0x11369, 0x0},
+	{ 0x11469, 0x0},
+	{ 0x11569, 0x0},
+	{ 0x11669, 0x0},
+	{ 0x11769, 0x0},
+	{ 0x11869, 0x0},
+	{ 0x12069, 0x0},
+	{ 0x12169, 0x0},
+	{ 0x12269, 0x0},
+	{ 0x12369, 0x0},
+	{ 0x12469, 0x0},
+	{ 0x12569, 0x0},
+	{ 0x12669, 0x0},
+	{ 0x12769, 0x0},
+	{ 0x12869, 0x0},
+	{ 0x13069, 0x0},
+	{ 0x13169, 0x0},
+	{ 0x13269, 0x0},
+	{ 0x13369, 0x0},
+	{ 0x13469, 0x0},
+	{ 0x13569, 0x0},
+	{ 0x13669, 0x0},
+	{ 0x13769, 0x0},
+	{ 0x13869, 0x0},
+	{ 0x1008c, 0x0},
+	{ 0x11008c, 0x0},
+	{ 0x21008c, 0x0},
+	{ 0x1018c, 0x0},
+	{ 0x11018c, 0x0},
+	{ 0x21018c, 0x0},
+	{ 0x1108c, 0x0},
+	{ 0x11108c, 0x0},
+	{ 0x21108c, 0x0},
+	{ 0x1118c, 0x0},
+	{ 0x11118c, 0x0},
+	{ 0x21118c, 0x0},
+	{ 0x1208c, 0x0},
+	{ 0x11208c, 0x0},
+	{ 0x21208c, 0x0},
+	{ 0x1218c, 0x0},
+	{ 0x11218c, 0x0},
+	{ 0x21218c, 0x0},
+	{ 0x1308c, 0x0},
+	{ 0x11308c, 0x0},
+	{ 0x21308c, 0x0},
+	{ 0x1318c, 0x0},
+	{ 0x11318c, 0x0},
+	{ 0x21318c, 0x0},
+	{ 0x1008d, 0x0},
+	{ 0x11008d, 0x0},
+	{ 0x21008d, 0x0},
+	{ 0x1018d, 0x0},
+	{ 0x11018d, 0x0},
+	{ 0x21018d, 0x0},
+	{ 0x1108d, 0x0},
+	{ 0x11108d, 0x0},
+	{ 0x21108d, 0x0},
+	{ 0x1118d, 0x0},
+	{ 0x11118d, 0x0},
+	{ 0x21118d, 0x0},
+	{ 0x1208d, 0x0},
+	{ 0x11208d, 0x0},
+	{ 0x21208d, 0x0},
+	{ 0x1218d, 0x0},
+	{ 0x11218d, 0x0},
+	{ 0x21218d, 0x0},
+	{ 0x1308d, 0x0},
+	{ 0x11308d, 0x0},
+	{ 0x21308d, 0x0},
+	{ 0x1318d, 0x0},
+	{ 0x11318d, 0x0},
+	{ 0x21318d, 0x0},
+	{ 0x100c0, 0x0},
+	{ 0x1100c0, 0x0},
+	{ 0x2100c0, 0x0},
+	{ 0x101c0, 0x0},
+	{ 0x1101c0, 0x0},
+	{ 0x2101c0, 0x0},
+	{ 0x102c0, 0x0},
+	{ 0x1102c0, 0x0},
+	{ 0x2102c0, 0x0},
+	{ 0x103c0, 0x0},
+	{ 0x1103c0, 0x0},
+	{ 0x2103c0, 0x0},
+	{ 0x104c0, 0x0},
+	{ 0x1104c0, 0x0},
+	{ 0x2104c0, 0x0},
+	{ 0x105c0, 0x0},
+	{ 0x1105c0, 0x0},
+	{ 0x2105c0, 0x0},
+	{ 0x106c0, 0x0},
+	{ 0x1106c0, 0x0},
+	{ 0x2106c0, 0x0},
+	{ 0x107c0, 0x0},
+	{ 0x1107c0, 0x0},
+	{ 0x2107c0, 0x0},
+	{ 0x108c0, 0x0},
+	{ 0x1108c0, 0x0},
+	{ 0x2108c0, 0x0},
+	{ 0x110c0, 0x0},
+	{ 0x1110c0, 0x0},
+	{ 0x2110c0, 0x0},
+	{ 0x111c0, 0x0},
+	{ 0x1111c0, 0x0},
+	{ 0x2111c0, 0x0},
+	{ 0x112c0, 0x0},
+	{ 0x1112c0, 0x0},
+	{ 0x2112c0, 0x0},
+	{ 0x113c0, 0x0},
+	{ 0x1113c0, 0x0},
+	{ 0x2113c0, 0x0},
+	{ 0x114c0, 0x0},
+	{ 0x1114c0, 0x0},
+	{ 0x2114c0, 0x0},
+	{ 0x115c0, 0x0},
+	{ 0x1115c0, 0x0},
+	{ 0x2115c0, 0x0},
+	{ 0x116c0, 0x0},
+	{ 0x1116c0, 0x0},
+	{ 0x2116c0, 0x0},
+	{ 0x117c0, 0x0},
+	{ 0x1117c0, 0x0},
+	{ 0x2117c0, 0x0},
+	{ 0x118c0, 0x0},
+	{ 0x1118c0, 0x0},
+	{ 0x2118c0, 0x0},
+	{ 0x120c0, 0x0},
+	{ 0x1120c0, 0x0},
+	{ 0x2120c0, 0x0},
+	{ 0x121c0, 0x0},
+	{ 0x1121c0, 0x0},
+	{ 0x2121c0, 0x0},
+	{ 0x122c0, 0x0},
+	{ 0x1122c0, 0x0},
+	{ 0x2122c0, 0x0},
+	{ 0x123c0, 0x0},
+	{ 0x1123c0, 0x0},
+	{ 0x2123c0, 0x0},
+	{ 0x124c0, 0x0},
+	{ 0x1124c0, 0x0},
+	{ 0x2124c0, 0x0},
+	{ 0x125c0, 0x0},
+	{ 0x1125c0, 0x0},
+	{ 0x2125c0, 0x0},
+	{ 0x126c0, 0x0},
+	{ 0x1126c0, 0x0},
+	{ 0x2126c0, 0x0},
+	{ 0x127c0, 0x0},
+	{ 0x1127c0, 0x0},
+	{ 0x2127c0, 0x0},
+	{ 0x128c0, 0x0},
+	{ 0x1128c0, 0x0},
+	{ 0x2128c0, 0x0},
+	{ 0x130c0, 0x0},
+	{ 0x1130c0, 0x0},
+	{ 0x2130c0, 0x0},
+	{ 0x131c0, 0x0},
+	{ 0x1131c0, 0x0},
+	{ 0x2131c0, 0x0},
+	{ 0x132c0, 0x0},
+	{ 0x1132c0, 0x0},
+	{ 0x2132c0, 0x0},
+	{ 0x133c0, 0x0},
+	{ 0x1133c0, 0x0},
+	{ 0x2133c0, 0x0},
+	{ 0x134c0, 0x0},
+	{ 0x1134c0, 0x0},
+	{ 0x2134c0, 0x0},
+	{ 0x135c0, 0x0},
+	{ 0x1135c0, 0x0},
+	{ 0x2135c0, 0x0},
+	{ 0x136c0, 0x0},
+	{ 0x1136c0, 0x0},
+	{ 0x2136c0, 0x0},
+	{ 0x137c0, 0x0},
+	{ 0x1137c0, 0x0},
+	{ 0x2137c0, 0x0},
+	{ 0x138c0, 0x0},
+	{ 0x1138c0, 0x0},
+	{ 0x2138c0, 0x0},
+	{ 0x100c1, 0x0},
+	{ 0x1100c1, 0x0},
+	{ 0x2100c1, 0x0},
+	{ 0x101c1, 0x0},
+	{ 0x1101c1, 0x0},
+	{ 0x2101c1, 0x0},
+	{ 0x102c1, 0x0},
+	{ 0x1102c1, 0x0},
+	{ 0x2102c1, 0x0},
+	{ 0x103c1, 0x0},
+	{ 0x1103c1, 0x0},
+	{ 0x2103c1, 0x0},
+	{ 0x104c1, 0x0},
+	{ 0x1104c1, 0x0},
+	{ 0x2104c1, 0x0},
+	{ 0x105c1, 0x0},
+	{ 0x1105c1, 0x0},
+	{ 0x2105c1, 0x0},
+	{ 0x106c1, 0x0},
+	{ 0x1106c1, 0x0},
+	{ 0x2106c1, 0x0},
+	{ 0x107c1, 0x0},
+	{ 0x1107c1, 0x0},
+	{ 0x2107c1, 0x0},
+	{ 0x108c1, 0x0},
+	{ 0x1108c1, 0x0},
+	{ 0x2108c1, 0x0},
+	{ 0x110c1, 0x0},
+	{ 0x1110c1, 0x0},
+	{ 0x2110c1, 0x0},
+	{ 0x111c1, 0x0},
+	{ 0x1111c1, 0x0},
+	{ 0x2111c1, 0x0},
+	{ 0x112c1, 0x0},
+	{ 0x1112c1, 0x0},
+	{ 0x2112c1, 0x0},
+	{ 0x113c1, 0x0},
+	{ 0x1113c1, 0x0},
+	{ 0x2113c1, 0x0},
+	{ 0x114c1, 0x0},
+	{ 0x1114c1, 0x0},
+	{ 0x2114c1, 0x0},
+	{ 0x115c1, 0x0},
+	{ 0x1115c1, 0x0},
+	{ 0x2115c1, 0x0},
+	{ 0x116c1, 0x0},
+	{ 0x1116c1, 0x0},
+	{ 0x2116c1, 0x0},
+	{ 0x117c1, 0x0},
+	{ 0x1117c1, 0x0},
+	{ 0x2117c1, 0x0},
+	{ 0x118c1, 0x0},
+	{ 0x1118c1, 0x0},
+	{ 0x2118c1, 0x0},
+	{ 0x120c1, 0x0},
+	{ 0x1120c1, 0x0},
+	{ 0x2120c1, 0x0},
+	{ 0x121c1, 0x0},
+	{ 0x1121c1, 0x0},
+	{ 0x2121c1, 0x0},
+	{ 0x122c1, 0x0},
+	{ 0x1122c1, 0x0},
+	{ 0x2122c1, 0x0},
+	{ 0x123c1, 0x0},
+	{ 0x1123c1, 0x0},
+	{ 0x2123c1, 0x0},
+	{ 0x124c1, 0x0},
+	{ 0x1124c1, 0x0},
+	{ 0x2124c1, 0x0},
+	{ 0x125c1, 0x0},
+	{ 0x1125c1, 0x0},
+	{ 0x2125c1, 0x0},
+	{ 0x126c1, 0x0},
+	{ 0x1126c1, 0x0},
+	{ 0x2126c1, 0x0},
+	{ 0x127c1, 0x0},
+	{ 0x1127c1, 0x0},
+	{ 0x2127c1, 0x0},
+	{ 0x128c1, 0x0},
+	{ 0x1128c1, 0x0},
+	{ 0x2128c1, 0x0},
+	{ 0x130c1, 0x0},
+	{ 0x1130c1, 0x0},
+	{ 0x2130c1, 0x0},
+	{ 0x131c1, 0x0},
+	{ 0x1131c1, 0x0},
+	{ 0x2131c1, 0x0},
+	{ 0x132c1, 0x0},
+	{ 0x1132c1, 0x0},
+	{ 0x2132c1, 0x0},
+	{ 0x133c1, 0x0},
+	{ 0x1133c1, 0x0},
+	{ 0x2133c1, 0x0},
+	{ 0x134c1, 0x0},
+	{ 0x1134c1, 0x0},
+	{ 0x2134c1, 0x0},
+	{ 0x135c1, 0x0},
+	{ 0x1135c1, 0x0},
+	{ 0x2135c1, 0x0},
+	{ 0x136c1, 0x0},
+	{ 0x1136c1, 0x0},
+	{ 0x2136c1, 0x0},
+	{ 0x137c1, 0x0},
+	{ 0x1137c1, 0x0},
+	{ 0x2137c1, 0x0},
+	{ 0x138c1, 0x0},
+	{ 0x1138c1, 0x0},
+	{ 0x2138c1, 0x0},
+	{ 0x10020, 0x0},
+	{ 0x110020, 0x0},
+	{ 0x210020, 0x0},
+	{ 0x11020, 0x0},
+	{ 0x111020, 0x0},
+	{ 0x211020, 0x0},
+	{ 0x12020, 0x0},
+	{ 0x112020, 0x0},
+	{ 0x212020, 0x0},
+	{ 0x13020, 0x0},
+	{ 0x113020, 0x0},
+	{ 0x213020, 0x0},
+	{ 0x20072, 0x0},
+	{ 0x20073, 0x0},
+	{ 0x20074, 0x0},
+	{ 0x100aa, 0x0},
+	{ 0x110aa, 0x0},
+	{ 0x120aa, 0x0},
+	{ 0x130aa, 0x0},
+	{ 0x20010, 0x0},
+	{ 0x120010, 0x0},
+	{ 0x220010, 0x0},
+	{ 0x20011, 0x0},
+	{ 0x120011, 0x0},
+	{ 0x220011, 0x0},
+	{ 0x100ae, 0x0},
+	{ 0x1100ae, 0x0},
+	{ 0x2100ae, 0x0},
+	{ 0x100af, 0x0},
+	{ 0x1100af, 0x0},
+	{ 0x2100af, 0x0},
+	{ 0x110ae, 0x0},
+	{ 0x1110ae, 0x0},
+	{ 0x2110ae, 0x0},
+	{ 0x110af, 0x0},
+	{ 0x1110af, 0x0},
+	{ 0x2110af, 0x0},
+	{ 0x120ae, 0x0},
+	{ 0x1120ae, 0x0},
+	{ 0x2120ae, 0x0},
+	{ 0x120af, 0x0},
+	{ 0x1120af, 0x0},
+	{ 0x2120af, 0x0},
+	{ 0x130ae, 0x0},
+	{ 0x1130ae, 0x0},
+	{ 0x2130ae, 0x0},
+	{ 0x130af, 0x0},
+	{ 0x1130af, 0x0},
+	{ 0x2130af, 0x0},
+	{ 0x20020, 0x0},
+	{ 0x120020, 0x0},
+	{ 0x220020, 0x0},
+	{ 0x100a0, 0x0},
+	{ 0x100a1, 0x0},
+	{ 0x100a2, 0x0},
+	{ 0x100a3, 0x0},
+	{ 0x100a4, 0x0},
+	{ 0x100a5, 0x0},
+	{ 0x100a6, 0x0},
+	{ 0x100a7, 0x0},
+	{ 0x110a0, 0x0},
+	{ 0x110a1, 0x0},
+	{ 0x110a2, 0x0},
+	{ 0x110a3, 0x0},
+	{ 0x110a4, 0x0},
+	{ 0x110a5, 0x0},
+	{ 0x110a6, 0x0},
+	{ 0x110a7, 0x0},
+	{ 0x120a0, 0x0},
+	{ 0x120a1, 0x0},
+	{ 0x120a2, 0x0},
+	{ 0x120a3, 0x0},
+	{ 0x120a4, 0x0},
+	{ 0x120a5, 0x0},
+	{ 0x120a6, 0x0},
+	{ 0x120a7, 0x0},
+	{ 0x130a0, 0x0},
+	{ 0x130a1, 0x0},
+	{ 0x130a2, 0x0},
+	{ 0x130a3, 0x0},
+	{ 0x130a4, 0x0},
+	{ 0x130a5, 0x0},
+	{ 0x130a6, 0x0},
+	{ 0x130a7, 0x0},
+	{ 0x2007c, 0x0},
+	{ 0x12007c, 0x0},
+	{ 0x22007c, 0x0},
+	{ 0x2007d, 0x0},
+	{ 0x12007d, 0x0},
+	{ 0x22007d, 0x0},
+	{ 0x400fd, 0x0},
+	{ 0x400c0, 0x0},
+	{ 0x90201, 0x0},
+	{ 0x190201, 0x0},
+	{ 0x290201, 0x0},
+	{ 0x90202, 0x0},
+	{ 0x190202, 0x0},
+	{ 0x290202, 0x0},
+	{ 0x90203, 0x0},
+	{ 0x190203, 0x0},
+	{ 0x290203, 0x0},
+	{ 0x90204, 0x0},
+	{ 0x190204, 0x0},
+	{ 0x290204, 0x0},
+	{ 0x90205, 0x0},
+	{ 0x190205, 0x0},
+	{ 0x290205, 0x0},
+	{ 0x90206, 0x0},
+	{ 0x190206, 0x0},
+	{ 0x290206, 0x0},
+	{ 0x90207, 0x0},
+	{ 0x190207, 0x0},
+	{ 0x290207, 0x0},
+	{ 0x90208, 0x0},
+	{ 0x190208, 0x0},
+	{ 0x290208, 0x0},
+	{ 0x10062, 0x0},
+	{ 0x10162, 0x0},
+	{ 0x10262, 0x0},
+	{ 0x10362, 0x0},
+	{ 0x10462, 0x0},
+	{ 0x10562, 0x0},
+	{ 0x10662, 0x0},
+	{ 0x10762, 0x0},
+	{ 0x10862, 0x0},
+	{ 0x11062, 0x0},
+	{ 0x11162, 0x0},
+	{ 0x11262, 0x0},
+	{ 0x11362, 0x0},
+	{ 0x11462, 0x0},
+	{ 0x11562, 0x0},
+	{ 0x11662, 0x0},
+	{ 0x11762, 0x0},
+	{ 0x11862, 0x0},
+	{ 0x12062, 0x0},
+	{ 0x12162, 0x0},
+	{ 0x12262, 0x0},
+	{ 0x12362, 0x0},
+	{ 0x12462, 0x0},
+	{ 0x12562, 0x0},
+	{ 0x12662, 0x0},
+	{ 0x12762, 0x0},
+	{ 0x12862, 0x0},
+	{ 0x13062, 0x0},
+	{ 0x13162, 0x0},
+	{ 0x13262, 0x0},
+	{ 0x13362, 0x0},
+	{ 0x13462, 0x0},
+	{ 0x13562, 0x0},
+	{ 0x13662, 0x0},
+	{ 0x13762, 0x0},
+	{ 0x13862, 0x0},
+	{ 0x20077, 0x0},
+	{ 0x10001, 0x0},
+	{ 0x11001, 0x0},
+	{ 0x12001, 0x0},
+	{ 0x13001, 0x0},
+	{ 0x10040, 0x0},
+	{ 0x10140, 0x0},
+	{ 0x10240, 0x0},
+	{ 0x10340, 0x0},
+	{ 0x10440, 0x0},
+	{ 0x10540, 0x0},
+	{ 0x10640, 0x0},
+	{ 0x10740, 0x0},
+	{ 0x10840, 0x0},
+	{ 0x10030, 0x0},
+	{ 0x10130, 0x0},
+	{ 0x10230, 0x0},
+	{ 0x10330, 0x0},
+	{ 0x10430, 0x0},
+	{ 0x10530, 0x0},
+	{ 0x10630, 0x0},
+	{ 0x10730, 0x0},
+	{ 0x10830, 0x0},
+	{ 0x11040, 0x0},
+	{ 0x11140, 0x0},
+	{ 0x11240, 0x0},
+	{ 0x11340, 0x0},
+	{ 0x11440, 0x0},
+	{ 0x11540, 0x0},
+	{ 0x11640, 0x0},
+	{ 0x11740, 0x0},
+	{ 0x11840, 0x0},
+	{ 0x11030, 0x0},
+	{ 0x11130, 0x0},
+	{ 0x11230, 0x0},
+	{ 0x11330, 0x0},
+	{ 0x11430, 0x0},
+	{ 0x11530, 0x0},
+	{ 0x11630, 0x0},
+	{ 0x11730, 0x0},
+	{ 0x11830, 0x0},
+	{ 0x12040, 0x0},
+	{ 0x12140, 0x0},
+	{ 0x12240, 0x0},
+	{ 0x12340, 0x0},
+	{ 0x12440, 0x0},
+	{ 0x12540, 0x0},
+	{ 0x12640, 0x0},
+	{ 0x12740, 0x0},
+	{ 0x12840, 0x0},
+	{ 0x12030, 0x0},
+	{ 0x12130, 0x0},
+	{ 0x12230, 0x0},
+	{ 0x12330, 0x0},
+	{ 0x12430, 0x0},
+	{ 0x12530, 0x0},
+	{ 0x12630, 0x0},
+	{ 0x12730, 0x0},
+	{ 0x12830, 0x0},
+	{ 0x13040, 0x0},
+	{ 0x13140, 0x0},
+	{ 0x13240, 0x0},
+	{ 0x13340, 0x0},
+	{ 0x13440, 0x0},
+	{ 0x13540, 0x0},
+	{ 0x13640, 0x0},
+	{ 0x13740, 0x0},
+	{ 0x13840, 0x0},
+	{ 0x13030, 0x0},
+	{ 0x13130, 0x0},
+	{ 0x13230, 0x0},
+	{ 0x13330, 0x0},
+	{ 0x13430, 0x0},
+	{ 0x13530, 0x0},
+	{ 0x13630, 0x0},
+	{ 0x13730, 0x0},
+	{ 0x13830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xbb8},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x310},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x101},
+	{0x54003, 0x190},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x310},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x64},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x310},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xbb8},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x310},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x5d},
+	{0x2000c, 0xbb},
+	{0x2000d, 0x753},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xc},
+	{0x12000c, 0x19},
+	{0x12000d, 0xfa},
+	{0x12000e, 0x10},
+	{0x22000b, 0x3},
+	{0x22000c, 0x6},
+	{0x22000d, 0x3e},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x220010, 0x5a},
+	{0x220011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info ucm_dram_timing_ff000110 = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c
new file mode 100644
index 000000000..e65445e01
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c
@@ -0,0 +1,1847 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa3080020},
+	{0x3d400020, 0x223},
+	{0x3d400024, 0x3a980},
+	{0x3d400064, 0x5b00d2},
+	{0x3d4000d0, 0xc00305ba},
+	{0x3d4000d4, 0x940000},
+	{0x3d4000dc, 0xd4002d},
+	{0x3d4000e0, 0x310000},
+	{0x3d4000e8, 0x66004d},
+	{0x3d4000ec, 0x16004d},
+	{0x3d400100, 0x191e1920},
+	{0x3d400104, 0x60630},
+	{0x3d40010c, 0xb0b000},
+	{0x3d400110, 0xe04080e},
+	{0x3d400114, 0x2040c0c},
+	{0x3d400118, 0x1010007},
+	{0x3d40011c, 0x401},
+	{0x3d400130, 0x20600},
+	{0x3d400134, 0xc100002},
+	{0x3d400138, 0xd8},
+	{0x3d400144, 0x96004b},
+	{0x3d400180, 0x2ee0017},
+	{0x3d400184, 0x2605b8e},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x497820a},
+	{0x3d400194, 0x80303},
+	{0x3d4001b4, 0x170a},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x0},
+	{0x3d4000f4, 0xc99},
+	{0x3d400108, 0x70e1617},
+	{0x3d400200, 0x16},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0xf070707},
+	{0x3d400250, 0x29001701},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x4000030},
+	{0x3d400264, 0x900093e7},
+	{0x3d40026c, 0x2005574},
+	{0x3d400400, 0x111},
+	{0x3d400408, 0x72ff},
+	{0x3d400494, 0x2100e07},
+	{0x3d400498, 0x620096},
+	{0x3d40049c, 0x1100e07},
+	{0x3d4004a0, 0xc8012c},
+	{0x3d402020, 0x21},
+	{0x3d402024, 0x7d00},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0xc001c},
+	{0x3d4020dc, 0x840000},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004d},
+	{0x3d4020ec, 0x16004d},
+	{0x3d402100, 0xa040305},
+	{0x3d402104, 0x30407},
+	{0x3d402108, 0x203060b},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x2040202},
+	{0x3d402114, 0x2030202},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x1d},
+	{0x3d402144, 0x14000a},
+	{0x3d402180, 0x640004},
+	{0x3d402190, 0x3818200},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x100},
+	{0x3d403020, 0x21},
+	{0x3d403024, 0x1f40},
+	{0x3d403050, 0x20d040},
+	{0x3d403064, 0x30007},
+	{0x3d4030dc, 0x840000},
+	{0x3d4030e0, 0x310000},
+	{0x3d4030e8, 0x66004d},
+	{0x3d4030ec, 0x16004d},
+	{0x3d403100, 0xa010102},
+	{0x3d403104, 0x30404},
+	{0x3d403108, 0x203060b},
+	{0x3d40310c, 0x505000},
+	{0x3d403110, 0x2040202},
+	{0x3d403114, 0x2030202},
+	{0x3d403118, 0x1010004},
+	{0x3d40311c, 0x301},
+	{0x3d403130, 0x20300},
+	{0x3d403134, 0xa100002},
+	{0x3d403138, 0x8},
+	{0x3d403144, 0x50003},
+	{0x3d403180, 0x190004},
+	{0x3d403190, 0x3818200},
+	{0x3d403194, 0x80303},
+	{0x3d4031b4, 0x100},
+	{0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x3},
+	{0x110a3, 0x4},
+	{0x110a4, 0x5},
+	{0x110a5, 0x2},
+	{0x110a6, 0x7},
+	{0x110a7, 0x6},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x3},
+	{0x120a3, 0x2},
+	{0x120a4, 0x5},
+	{0x120a5, 0x4},
+	{0x120a6, 0x7},
+	{0x120a7, 0x6},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x21005f, 0x1ff},
+	{0x21015f, 0x1ff},
+	{0x21105f, 0x1ff},
+	{0x21115f, 0x1ff},
+	{0x21205f, 0x1ff},
+	{0x21215f, 0x1ff},
+	{0x21305f, 0x1ff},
+	{0x21315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x19},
+	{0x1200c5, 0x7},
+	{0x2200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x2},
+	{0x22002e, 0x2},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x220024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x3},
+	{0x120056, 0xa},
+	{0x220056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x21004d, 0xe00},
+	{0x21014d, 0xe00},
+	{0x21104d, 0xe00},
+	{0x21114d, 0xe00},
+	{0x21204d, 0xe00},
+	{0x21214d, 0xe00},
+	{0x21304d, 0xe00},
+	{0x21314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x210049, 0xeba},
+	{0x210149, 0xeba},
+	{0x211049, 0xeba},
+	{0x211149, 0xeba},
+	{0x212049, 0xeba},
+	{0x212149, 0xeba},
+	{0x213049, 0xeba},
+	{0x213149, 0xeba},
+	{0x43, 0x63},
+	{0x1043, 0x63},
+	{0x2043, 0x63},
+	{0x3043, 0x63},
+	{0x4043, 0x63},
+	{0x5043, 0x63},
+	{0x6043, 0x63},
+	{0x7043, 0x63},
+	{0x8043, 0x63},
+	{0x9043, 0x63},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x2ee},
+	{0x120008, 0x64},
+	{0x220008, 0x19},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x2200b2, 0xdc},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
+	{0x212043, 0x5a1},
+	{0x212143, 0x5a1},
+	{0x213043, 0x5a1},
+	{0x213143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x2200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
+	{0x200f0, 0x660},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5665},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x200c7, 0x21},
+	{0x1200c7, 0x21},
+	{0x2200c7, 0x21},
+	{0x200ca, 0x24},
+	{0x1200ca, 0x24},
+	{0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0},
+	{ 0x1200b2, 0x0},
+	{ 0x2200b2, 0x0},
+	{ 0x200cb, 0x0},
+	{ 0x10043, 0x0},
+	{ 0x110043, 0x0},
+	{ 0x210043, 0x0},
+	{ 0x10143, 0x0},
+	{ 0x110143, 0x0},
+	{ 0x210143, 0x0},
+	{ 0x11043, 0x0},
+	{ 0x111043, 0x0},
+	{ 0x211043, 0x0},
+	{ 0x11143, 0x0},
+	{ 0x111143, 0x0},
+	{ 0x211143, 0x0},
+	{ 0x12043, 0x0},
+	{ 0x112043, 0x0},
+	{ 0x212043, 0x0},
+	{ 0x12143, 0x0},
+	{ 0x112143, 0x0},
+	{ 0x212143, 0x0},
+	{ 0x13043, 0x0},
+	{ 0x113043, 0x0},
+	{ 0x213043, 0x0},
+	{ 0x13143, 0x0},
+	{ 0x113143, 0x0},
+	{ 0x213143, 0x0},
+	{ 0x80, 0x0},
+	{ 0x100080, 0x0},
+	{ 0x200080, 0x0},
+	{ 0x1080, 0x0},
+	{ 0x101080, 0x0},
+	{ 0x201080, 0x0},
+	{ 0x2080, 0x0},
+	{ 0x102080, 0x0},
+	{ 0x202080, 0x0},
+	{ 0x3080, 0x0},
+	{ 0x103080, 0x0},
+	{ 0x203080, 0x0},
+	{ 0x4080, 0x0},
+	{ 0x104080, 0x0},
+	{ 0x204080, 0x0},
+	{ 0x5080, 0x0},
+	{ 0x105080, 0x0},
+	{ 0x205080, 0x0},
+	{ 0x6080, 0x0},
+	{ 0x106080, 0x0},
+	{ 0x206080, 0x0},
+	{ 0x7080, 0x0},
+	{ 0x107080, 0x0},
+	{ 0x207080, 0x0},
+	{ 0x8080, 0x0},
+	{ 0x108080, 0x0},
+	{ 0x208080, 0x0},
+	{ 0x9080, 0x0},
+	{ 0x109080, 0x0},
+	{ 0x209080, 0x0},
+	{ 0x10080, 0x0},
+	{ 0x110080, 0x0},
+	{ 0x210080, 0x0},
+	{ 0x10180, 0x0},
+	{ 0x110180, 0x0},
+	{ 0x210180, 0x0},
+	{ 0x11080, 0x0},
+	{ 0x111080, 0x0},
+	{ 0x211080, 0x0},
+	{ 0x11180, 0x0},
+	{ 0x111180, 0x0},
+	{ 0x211180, 0x0},
+	{ 0x12080, 0x0},
+	{ 0x112080, 0x0},
+	{ 0x212080, 0x0},
+	{ 0x12180, 0x0},
+	{ 0x112180, 0x0},
+	{ 0x212180, 0x0},
+	{ 0x13080, 0x0},
+	{ 0x113080, 0x0},
+	{ 0x213080, 0x0},
+	{ 0x13180, 0x0},
+	{ 0x113180, 0x0},
+	{ 0x213180, 0x0},
+	{ 0x10081, 0x0},
+	{ 0x110081, 0x0},
+	{ 0x210081, 0x0},
+	{ 0x10181, 0x0},
+	{ 0x110181, 0x0},
+	{ 0x210181, 0x0},
+	{ 0x11081, 0x0},
+	{ 0x111081, 0x0},
+	{ 0x211081, 0x0},
+	{ 0x11181, 0x0},
+	{ 0x111181, 0x0},
+	{ 0x211181, 0x0},
+	{ 0x12081, 0x0},
+	{ 0x112081, 0x0},
+	{ 0x212081, 0x0},
+	{ 0x12181, 0x0},
+	{ 0x112181, 0x0},
+	{ 0x212181, 0x0},
+	{ 0x13081, 0x0},
+	{ 0x113081, 0x0},
+	{ 0x213081, 0x0},
+	{ 0x13181, 0x0},
+	{ 0x113181, 0x0},
+	{ 0x213181, 0x0},
+	{ 0x100d0, 0x0},
+	{ 0x1100d0, 0x0},
+	{ 0x2100d0, 0x0},
+	{ 0x101d0, 0x0},
+	{ 0x1101d0, 0x0},
+	{ 0x2101d0, 0x0},
+	{ 0x110d0, 0x0},
+	{ 0x1110d0, 0x0},
+	{ 0x2110d0, 0x0},
+	{ 0x111d0, 0x0},
+	{ 0x1111d0, 0x0},
+	{ 0x2111d0, 0x0},
+	{ 0x120d0, 0x0},
+	{ 0x1120d0, 0x0},
+	{ 0x2120d0, 0x0},
+	{ 0x121d0, 0x0},
+	{ 0x1121d0, 0x0},
+	{ 0x2121d0, 0x0},
+	{ 0x130d0, 0x0},
+	{ 0x1130d0, 0x0},
+	{ 0x2130d0, 0x0},
+	{ 0x131d0, 0x0},
+	{ 0x1131d0, 0x0},
+	{ 0x2131d0, 0x0},
+	{ 0x100d1, 0x0},
+	{ 0x1100d1, 0x0},
+	{ 0x2100d1, 0x0},
+	{ 0x101d1, 0x0},
+	{ 0x1101d1, 0x0},
+	{ 0x2101d1, 0x0},
+	{ 0x110d1, 0x0},
+	{ 0x1110d1, 0x0},
+	{ 0x2110d1, 0x0},
+	{ 0x111d1, 0x0},
+	{ 0x1111d1, 0x0},
+	{ 0x2111d1, 0x0},
+	{ 0x120d1, 0x0},
+	{ 0x1120d1, 0x0},
+	{ 0x2120d1, 0x0},
+	{ 0x121d1, 0x0},
+	{ 0x1121d1, 0x0},
+	{ 0x2121d1, 0x0},
+	{ 0x130d1, 0x0},
+	{ 0x1130d1, 0x0},
+	{ 0x2130d1, 0x0},
+	{ 0x131d1, 0x0},
+	{ 0x1131d1, 0x0},
+	{ 0x2131d1, 0x0},
+	{ 0x10068, 0x0},
+	{ 0x10168, 0x0},
+	{ 0x10268, 0x0},
+	{ 0x10368, 0x0},
+	{ 0x10468, 0x0},
+	{ 0x10568, 0x0},
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+	{ 0x13740, 0x0},
+	{ 0x13840, 0x0},
+	{ 0x13030, 0x0},
+	{ 0x13130, 0x0},
+	{ 0x13230, 0x0},
+	{ 0x13330, 0x0},
+	{ 0x13430, 0x0},
+	{ 0x13530, 0x0},
+	{ 0x13630, 0x0},
+	{ 0x13730, 0x0},
+	{ 0x13830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xbb8},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x310},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x101},
+	{0x54003, 0x190},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x310},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x64},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x310},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xbb8},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x310},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x5d},
+	{0x2000c, 0xbb},
+	{0x2000d, 0x753},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xc},
+	{0x12000c, 0x19},
+	{0x12000d, 0xfa},
+	{0x12000e, 0x10},
+	{0x22000b, 0x3},
+	{0x22000c, 0x6},
+	{0x22000d, 0x3e},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x220010, 0x5a},
+	{0x220011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info ucm_dram_timing_ff020008 = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
new file mode 100644
index 000000000..eabcc842a
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright 2020 Linaro
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int setup_fec(void)
+{
+	if (IS_ENABLED(CONFIG_FEC_MXC)) {
+		struct iomuxc_gpr_base_regs *gpr =
+			(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+		/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+		clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+	}
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (IS_ENABLED(CONFIG_FEC_MXC)) {
+		/* enable rgmii rxc skew and phy mode select to RGMII copper */
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+		if (phydev->drv->config)
+			phydev->drv->config(phydev);
+	}
+	return 0;
+}
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_FEC_MXC))
+		setup_fec();
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+		env_set("board_name", "IOT-GATE-IMX8");
+		env_set("board_rev", "SBC-IOTMX8");
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg
new file mode 100644
index 000000000..b89092a55
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#define __ASSEMBLY__
+
+BOOT_FROM	sd
+LOADER		mkimage.flash.mkimage	0x7E1000
diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/spl.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/spl.c
new file mode 100644
index 000000000..8f592457d
--- /dev/null
+++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/spl.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright 2020 Linaro
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/arch/ddr.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/pmic.h>
+#include <power/bd71837.h>
+
+#include "ddr/ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MM_PAD_I2C2_SCL_I2C2_SCL | PC,
+		.gpio_mode = IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 | PC,
+		.gp = IMX_GPIO_NR(5, 16),
+	},
+	.sda = {
+		.i2c_mode = IMX8MM_PAD_I2C2_SDA_I2C2_SDA | PC,
+		.gpio_mode = IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 | PC,
+		.gp = IMX_GPIO_NR(5, 17),
+	},
+};
+
+static void spl_dram_init(void)
+{
+	spl_dram_init_compulab();
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+static int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pmic@4b", &dev);
+	if (ret == -ENODEV) {
+		puts("No pmic\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
+
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+
+	/* unlock the PMIC regs */
+	pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+
+	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
+	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+	pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+
+	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+	pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
+
+	/* lock the PMIC regs */
+	pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	init_uart_clk(2);
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0) {
+		printf("Failed to find clock node. Check device tree\n");
+		hang();
+	}
+
+	enable_tzc380();
+
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/compulab/trimslice/Kconfig b/roms/u-boot/board/compulab/trimslice/Kconfig
new file mode 100644
index 000000000..357691403
--- /dev/null
+++ b/roms/u-boot/board/compulab/trimslice/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TRIMSLICE
+
+config SYS_BOARD
+	default "trimslice"
+
+config SYS_VENDOR
+	default "compulab"
+
+config SYS_CONFIG_NAME
+	default "trimslice"
+
+endif
diff --git a/roms/u-boot/board/compulab/trimslice/MAINTAINERS b/roms/u-boot/board/compulab/trimslice/MAINTAINERS
new file mode 100644
index 000000000..85b120017
--- /dev/null
+++ b/roms/u-boot/board/compulab/trimslice/MAINTAINERS
@@ -0,0 +1,7 @@
+TRIMSLICE BOARD
+M:	Tom Warren <twarren@nvidia.com>
+M:	Stephen Warren <swarren@nvidia.com>
+S:	Maintained
+F:	board/compulab/trimslice/
+F:	include/configs/trimslice.h
+F:	configs/trimslice_defconfig
diff --git a/roms/u-boot/board/compulab/trimslice/Makefile b/roms/u-boot/board/compulab/trimslice/Makefile
new file mode 100644
index 000000000..abdf47191
--- /dev/null
+++ b/roms/u-boot/board/compulab/trimslice/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2010-2012
+#  NVIDIA Corporation <www.nvidia.com>
+
+obj-y	:= trimslice.o
diff --git a/roms/u-boot/board/compulab/trimslice/trimslice.c b/roms/u-boot/board/compulab/trimslice/trimslice.c
new file mode 100644
index 000000000..21ff0cda7
--- /dev/null
+++ b/roms/u-boot/board/compulab/trimslice/trimslice.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+
+void pin_mux_usb(void)
+{
+	/*
+	 * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
+	 * in the current device tree.
+	 */
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
+}
+
+void pin_mux_spi(void)
+{
+	funcmux_select(PERIPH_ID_SPI1, FUNCMUX_SPI1_GMC_GMD);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+	funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT);
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+
+	/* For CD GPIO PP1 */
+	pinmux_tristate_disable(PMUX_PINGRP_DAP3);
+}
diff --git a/roms/u-boot/board/comtrend/ar5315u/Kconfig b/roms/u-boot/board/comtrend/ar5315u/Kconfig
new file mode 100644
index 000000000..4baae4000
--- /dev/null
+++ b/roms/u-boot/board/comtrend/ar5315u/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_AR5315U
+
+config SYS_BOARD
+	default "ar5315u"
+
+config SYS_VENDOR
+	default "comtrend"
+
+config SYS_CONFIG_NAME
+	default "comtrend_ar5315u"
+
+endif
diff --git a/roms/u-boot/board/comtrend/ar5315u/MAINTAINERS b/roms/u-boot/board/comtrend/ar5315u/MAINTAINERS
new file mode 100644
index 000000000..048073cb4
--- /dev/null
+++ b/roms/u-boot/board/comtrend/ar5315u/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND AR-5315U BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/comtrend/ar-5315u/
+F:	include/configs/comtrend_ar5315u.h
+F:	configs/comtrend_ar5315u_ram_defconfig
diff --git a/roms/u-boot/board/comtrend/ar5315u/Makefile b/roms/u-boot/board/comtrend/ar5315u/Makefile
new file mode 100644
index 000000000..25656a8ca
--- /dev/null
+++ b/roms/u-boot/board/comtrend/ar5315u/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += ar-5315u.o
diff --git a/roms/u-boot/board/comtrend/ar5315u/ar-5315u.c b/roms/u-boot/board/comtrend/ar5315u/ar-5315u.c
new file mode 100644
index 000000000..343798587
--- /dev/null
+++ b/roms/u-boot/board/comtrend/ar5315u/ar-5315u.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/comtrend/ar5387un/Kconfig b/roms/u-boot/board/comtrend/ar5387un/Kconfig
new file mode 100644
index 000000000..45ab7e284
--- /dev/null
+++ b/roms/u-boot/board/comtrend/ar5387un/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_AR5387UN
+
+config SYS_BOARD
+	default "ar5387un"
+
+config SYS_VENDOR
+	default "comtrend"
+
+config SYS_CONFIG_NAME
+	default "comtrend_ar5387un"
+
+endif
diff --git a/roms/u-boot/board/comtrend/ar5387un/MAINTAINERS b/roms/u-boot/board/comtrend/ar5387un/MAINTAINERS
new file mode 100644
index 000000000..bcaac64db
--- /dev/null
+++ b/roms/u-boot/board/comtrend/ar5387un/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND AR-5387UN BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/comtrend/ar-5387un/
+F:	include/configs/comtrend_ar5387un.h
+F:	configs/comtrend_ar5387un_ram_defconfig
diff --git a/roms/u-boot/board/comtrend/ar5387un/Makefile b/roms/u-boot/board/comtrend/ar5387un/Makefile
new file mode 100644
index 000000000..572ae1f09
--- /dev/null
+++ b/roms/u-boot/board/comtrend/ar5387un/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += ar-5387un.o
diff --git a/roms/u-boot/board/comtrend/ar5387un/ar-5387un.c b/roms/u-boot/board/comtrend/ar5387un/ar-5387un.c
new file mode 100644
index 000000000..1e4b7281d
--- /dev/null
+++ b/roms/u-boot/board/comtrend/ar5387un/ar-5387un.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/comtrend/ct5361/Kconfig b/roms/u-boot/board/comtrend/ct5361/Kconfig
new file mode 100644
index 000000000..d77d814db
--- /dev/null
+++ b/roms/u-boot/board/comtrend/ct5361/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_CT5361
+
+config SYS_BOARD
+	default "ct5361"
+
+config SYS_VENDOR
+	default "comtrend"
+
+config SYS_CONFIG_NAME
+	default "comtrend_ct5361"
+
+endif
diff --git a/roms/u-boot/board/comtrend/ct5361/MAINTAINERS b/roms/u-boot/board/comtrend/ct5361/MAINTAINERS
new file mode 100644
index 000000000..aea737a0b
--- /dev/null
+++ b/roms/u-boot/board/comtrend/ct5361/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND CT-5361 BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/comtrend/ct-5361/
+F:	include/configs/comtrend_ct5361.h
+F:	configs/comtrend_ct5361_ram_defconfig
diff --git a/roms/u-boot/board/comtrend/ct5361/Makefile b/roms/u-boot/board/comtrend/ct5361/Makefile
new file mode 100644
index 000000000..8b41c4a07
--- /dev/null
+++ b/roms/u-boot/board/comtrend/ct5361/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += ct-5361.o
diff --git a/roms/u-boot/board/comtrend/ct5361/ct-5361.c b/roms/u-boot/board/comtrend/ct5361/ct-5361.c
new file mode 100644
index 000000000..1e4b7281d
--- /dev/null
+++ b/roms/u-boot/board/comtrend/ct5361/ct-5361.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/comtrend/vr3032u/Kconfig b/roms/u-boot/board/comtrend/vr3032u/Kconfig
new file mode 100644
index 000000000..6f552cf22
--- /dev/null
+++ b/roms/u-boot/board/comtrend/vr3032u/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_VR3032U
+
+config SYS_BOARD
+	default "vr3032u"
+
+config SYS_VENDOR
+	default "comtrend"
+
+config SYS_CONFIG_NAME
+	default "comtrend_vr3032u"
+
+endif
diff --git a/roms/u-boot/board/comtrend/vr3032u/MAINTAINERS b/roms/u-boot/board/comtrend/vr3032u/MAINTAINERS
new file mode 100644
index 000000000..833d7da4a
--- /dev/null
+++ b/roms/u-boot/board/comtrend/vr3032u/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND VR-3032U BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/comtrend/vr-3032u/
+F:	include/configs/comtrend_vr-3032u.h
+F:	configs/comtrend_vr3032u_ram_defconfig
diff --git a/roms/u-boot/board/comtrend/vr3032u/Makefile b/roms/u-boot/board/comtrend/vr3032u/Makefile
new file mode 100644
index 000000000..3542fea58
--- /dev/null
+++ b/roms/u-boot/board/comtrend/vr3032u/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += vr-3032u.o
diff --git a/roms/u-boot/board/comtrend/vr3032u/vr-3032u.c b/roms/u-boot/board/comtrend/vr3032u/vr-3032u.c
new file mode 100644
index 000000000..1e4b7281d
--- /dev/null
+++ b/roms/u-boot/board/comtrend/vr3032u/vr-3032u.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/comtrend/wap5813n/Kconfig b/roms/u-boot/board/comtrend/wap5813n/Kconfig
new file mode 100644
index 000000000..2f2a14faa
--- /dev/null
+++ b/roms/u-boot/board/comtrend/wap5813n/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_WAP5813N
+
+config SYS_BOARD
+	default "wap5813n"
+
+config SYS_VENDOR
+	default "comtrend"
+
+config SYS_CONFIG_NAME
+	default "comtrend_wap5813n"
+
+endif
diff --git a/roms/u-boot/board/comtrend/wap5813n/MAINTAINERS b/roms/u-boot/board/comtrend/wap5813n/MAINTAINERS
new file mode 100644
index 000000000..f4d99796b
--- /dev/null
+++ b/roms/u-boot/board/comtrend/wap5813n/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND WAP-5813N BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/comtrend/wap-5813n/
+F:	include/configs/comtrend_wap-5813n.h
+F:	configs/comtrend_wap5813n_ram_defconfig
diff --git a/roms/u-boot/board/comtrend/wap5813n/Makefile b/roms/u-boot/board/comtrend/wap5813n/Makefile
new file mode 100644
index 000000000..b8d4a6d5f
--- /dev/null
+++ b/roms/u-boot/board/comtrend/wap5813n/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += wap-5813n.o
diff --git a/roms/u-boot/board/comtrend/wap5813n/wap-5813n.c b/roms/u-boot/board/comtrend/wap5813n/wap-5813n.c
new file mode 100644
index 000000000..1e4b7281d
--- /dev/null
+++ b/roms/u-boot/board/comtrend/wap5813n/wap-5813n.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/congatec/Kconfig b/roms/u-boot/board/congatec/Kconfig
new file mode 100644
index 000000000..e9fa15375
--- /dev/null
+++ b/roms/u-boot/board/congatec/Kconfig
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+
+if VENDOR_CONGATEC
+
+choice
+	prompt "Mainboard model"
+	optional
+
+config TARGET_CONGA_QEVAL20_QA3_E3845
+	bool "congatec QEVAL 2.0 & conga-QA3/E3845"
+	select BOARD_LATE_INIT
+	imply SCSI
+	help
+	  This is the congatec Qseven 2.0 evaluation carrier board
+	  (conga-QEVAL) equipped with the conga-QA3/E3845-4G SoM.
+	  It contains an Atom E3845 with Ethernet, micro-SD, USB 2,
+	  USB 3, SATA, serial console and HDMI 1.3 video out.
+	  It requires some binary blobs - see README.x86 for details.
+
+	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+	  by U-Boot matches that value.
+
+config TARGET_THEADORABLE_X86_CONGA_QA3_E3845
+	bool "theadorable-x86 baseboard & conga-QA3/E3845"
+	help
+	  This is the theadorable-x86 baseboard board equipped with the
+	  conga-QA3/E3845-4G SoM. It contains an Atom E3845 with Ethernet,
+	  micro-SD, USB 2, USB 3, SATA, serial console and HDMI 1.3 video
+	  out. It requires some binary blobs - see README.x86 for details.
+
+	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+	  by U-Boot matches that value.
+
+endchoice
+
+source "board/congatec/conga-qeval20-qa3-e3845/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/congatec/cgtqmx8/Kconfig b/roms/u-boot/board/congatec/cgtqmx8/Kconfig
new file mode 100644
index 000000000..727303926
--- /dev/null
+++ b/roms/u-boot/board/congatec/cgtqmx8/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_CONGA_QMX8
+
+config SYS_BOARD
+	default "cgtqmx8"
+
+config SYS_VENDOR
+	default "congatec"
+
+config SYS_CONFIG_NAME
+	default "cgtqmx8"
+
+source "board/congatec/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/congatec/cgtqmx8/MAINTAINERS b/roms/u-boot/board/congatec/cgtqmx8/MAINTAINERS
new file mode 100644
index 000000000..53bc0f93b
--- /dev/null
+++ b/roms/u-boot/board/congatec/cgtqmx8/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX8QM CGTQMX8 BOARD
+M:	Oliver Graute <oliver.graute@kococonnector.com>
+S:	Maintained
+F:	board/congatec/cgtqmx8/
+F:	arch/arm/dts/imx8qm-cgtqmx8.dts
+F:	include/configs/cgtqmx8.h
+F:	configs/cgtqmx8_defconfig
diff --git a/roms/u-boot/board/congatec/cgtqmx8/Makefile b/roms/u-boot/board/congatec/cgtqmx8/Makefile
new file mode 100644
index 000000000..4b59dbb6b
--- /dev/null
+++ b/roms/u-boot/board/congatec/cgtqmx8/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cgtqmx8.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/roms/u-boot/board/congatec/cgtqmx8/cgtqmx8.c b/roms/u-boot/board/congatec/cgtqmx8/cgtqmx8.c
new file mode 100644
index 000000000..fb0cf0913
--- /dev/null
+++ b/roms/u-boot/board/congatec/cgtqmx8/cgtqmx8.c
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 congatec AG
+ * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
+ */
+#include <common.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+#include <fsl_esdhc.h>
+#include <init.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <usb.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/delay.h>
+#include <power-domain.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ESDHC_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ESDHC_CLK_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define FSPI_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define I2C_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+void board_late_mmc_env_init(void);
+void init_clk_usdhc(u32 index);
+int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg);
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+	/* sc_ipc_t ipcHndl = 0; */
+	sc_err_t scierr = 0;
+
+	/* When start u-boot in XEN VM, directly return */
+	/* if (IS_ENABLED(CONFIG_XEN)) */
+		/* return 0; */
+
+	/* ipcHndl = gd->arch.ipc_channel_handle; */
+
+	/* Power up UART0, this is very early while power domain is not working */
+	scierr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
+	if (scierr != SC_ERR_NONE)
+		return 0;
+
+	/* Set UART0 clock root to 80 MHz */
+	sc_pm_clock_rate_t rate = 80000000;
+
+	scierr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
+	if (scierr != SC_ERR_NONE)
+		return 0;
+
+	/* Enable UART0 clock root */
+	scierr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
+	if (scierr != SC_ERR_NONE)
+		return 0;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX)
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 22)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 12)
+
+static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR, 0, 4},
+};
+
+static iomux_cfg_t emmc0[] = {
+	SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+static iomux_cfg_t usdhc1_sd[] = {
+	SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA6 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_DATA7 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+static iomux_cfg_t usdhc2_sd[] = {
+	SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	struct power_domain pd;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0 (onboard eMMC)     USDHC1
+	 * mmc1 (external SD card) USDHC2
+	 * mmc2 (onboard µSD)      USDHC3
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+		  /* onboard eMMC */
+			if (!imx8_power_domain_lookup_name("conn_sdhc0", &pd))
+				power_domain_on(&pd);
+
+			imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
+			init_clk_usdhc(0);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+		  /* external SD card */
+			if (!imx8_power_domain_lookup_name("conn_sdhc1", &pd))
+				power_domain_on(&pd);
+
+			imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd));
+			init_clk_usdhc(1);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			gpio_request(USDHC1_CD_GPIO, "sd1_cd");
+			gpio_direction_input(USDHC1_CD_GPIO);
+			break;
+		case 2:
+		  /* onboard µSD */
+			if (!imx8_power_domain_lookup_name("conn_sdhc2", &pd))
+				power_domain_on(&pd);
+
+			imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
+			init_clk_usdhc(2);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			gpio_request(USDHC2_CD_GPIO, "sd2_cd");
+			gpio_direction_input(USDHC2_CD_GPIO);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return 0;
+		}
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+#if (IS_ENABLED(CONFIG_FEC_MXC))
+
+#include <miiphy.h>
+
+static iomux_cfg_t pad_enet0[] = {
+	SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
+}
+
+static void enet_device_phy_reset(void)
+{
+	gpio_set_value(FEC0_RESET, 0);
+	udelay(50);
+	gpio_set_value(FEC0_RESET, 1);
+
+	/* The board has a long delay for this reset to become stable */
+	mdelay(200);
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	setup_iomux_fec();
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+static int setup_fec(void)
+{
+	/* Reset ENET PHY */
+	enet_device_phy_reset();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MXC_GPIO
+
+#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
+#define BKL_ENABLE  IMX_GPIO_NR(1, 7)
+
+static iomux_cfg_t board_gpios[] = {
+	SC_P_LVDS0_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+	SC_P_LVDS0_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+	SC_P_ESAI1_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+static void board_gpio_init(void)
+{
+	imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
+
+	/* enable LVDS */
+	gpio_request(LVDS_ENABLE, "lvds_enable");
+	gpio_direction_output(LVDS_ENABLE, 1);
+
+	/* enable backlight */
+	gpio_request(BKL_ENABLE, "bkl_enable");
+	gpio_direction_output(BKL_ENABLE, 1);
+
+	/* ethernet reset */
+	gpio_request(FEC0_RESET, "enet0_reset");
+	gpio_direction_output(FEC0_RESET, 1);
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: conga-QMX8\n");
+
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+#ifdef CONFIG_MXC_GPIO
+	board_gpio_init();
+#endif
+
+#if (IS_ENABLED(CONFIG_FEC_MXC))
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+	/* TODO */
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	/* Use EMMC */
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int dev_no)
+{
+	/* Use EMMC */
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+	return dev_no;
+}
+
+extern u32 _end_ofs;
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "QMX8");
+	env_set("board_rev", "iMX8QM");
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+#ifdef IMX_LOAD_HDMI_FIMRWARE
+	char *end_of_uboot;
+	char command[256];
+
+	end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs
+			+ fdt_totalsize(gd->fdt_blob));
+	end_of_uboot += 9;
+
+	/* load hdmitxfw.bin and hdmirxfw.bin*/
+	memcpy(IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot,
+	       IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE);
+
+	sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR);
+	run_command(command, 0);
+
+	sprintf(command, "hdprx load 0x%x",
+		IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE);
+	run_command(command, 0);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+	return 0; /*TODO*/
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
+
+/* Only Enable USB3 resources currently */
+int board_usb_init(int index, enum usb_init_type init)
+{
+	return 0;
+}
diff --git a/roms/u-boot/board/congatec/cgtqmx8/imximage.cfg b/roms/u-boot/board/congatec/cgtqmx8/imximage.cfg
new file mode 100644
index 000000000..e324c7ca3
--- /dev/null
+++ b/roms/u-boot/board/congatec/cgtqmx8/imximage.cfg
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier:	GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QM */
+SOC_TYPE IMX8QM
+/* Append seco container image */
+APPEND mx8qm-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qm-val-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/roms/u-boot/board/congatec/cgtqmx8/spl.c b/roms/u-boot/board/congatec/cgtqmx8/spl.c
new file mode 100644
index 000000000..2a5d4c1bc
--- /dev/null
+++ b/roms/u-boot/board/congatec/cgtqmx8/spl.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+	int offset;
+
+	uclass_find_first_device(UCLASS_MISC, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
+	while (offset != -FDT_ERR_NOTFOUND) {
+		lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
+			       NULL, true);
+		offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
+						       "nxp,imx8-pd");
+	}
+
+	uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	puts("Normal Boot\n");
+}
+
+#if (IS_ENABLED(CONFIG_SPL_LOAD_FIT))
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/congatec/common/Kconfig b/roms/u-boot/board/congatec/common/Kconfig
new file mode 100644
index 000000000..5c205bd83
--- /dev/null
+++ b/roms/u-boot/board/congatec/common/Kconfig
@@ -0,0 +1,48 @@
+if !ARCH_IMX8M && !ARCH_IMX8
+
+config CHAIN_OF_TRUST
+	depends on !FIT_SIGNATURE && SECURE_BOOT
+	imply CMD_BLOB
+	imply CMD_HASH if ARM
+	select FSL_CAAM
+	select SPL_BOARD_INIT if (ARM && SPL)
+	select SHA_HW_ACCEL
+	select SHA_PROG_HW_ACCEL
+	select ENV_IS_NOWHERE
+	select CMD_EXT4 if ARM
+	select CMD_EXT4_WRITE if ARM
+	bool
+	default y
+
+config CMD_ESBC_VALIDATE
+	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
+	default y if CHAIN_OF_TRUST
+	help
+	  This option enables two commands used for secure booting:
+
+	    esbc_validate - validate signature using RSA verification
+	    esbc_halt - put the core in spin loop (Secure Boot Only)
+
+endif
+
+config VOL_MONITOR_LTC3882_READ
+	depends on VID
+	bool "Enable the LTC3882 voltage monitor read"
+	default n
+	help
+	 This option enables LTC3882 voltage monitor read
+	 functionality. It is used by common VID driver.
+
+config VOL_MONITOR_LTC3882_SET
+	depends on VID
+	bool "Enable the LTC3882 voltage monitor set"
+	default n
+	help
+	 This option enables LTC3882 voltage monitor set
+	 functionality. It is used by common VID driver.
+
+config USB_TCPC
+	bool "USB Typec port controller simple driver"
+	default n
+	help
+	  Enable USB type-c port controller (TCPC) driver
diff --git a/roms/u-boot/board/congatec/common/Makefile b/roms/u-boot/board/congatec/common/Makefile
new file mode 100644
index 000000000..d4ddfbf97
--- /dev/null
+++ b/roms/u-boot/board/congatec/common/Makefile
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+
+obj-y				+= mmc.o
+
+endif
diff --git a/roms/u-boot/board/congatec/common/mmc.c b/roms/u-boot/board/congatec/common/mmc.c
new file mode 100644
index 000000000..bb7a3d4a9
--- /dev/null
+++ b/roms/u-boot/board/congatec/common/mmc.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
+ *
+ */
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <env.h>
+#include <command.h>
+#include <stdbool.h>
+#include <mmc.h>
+
+static int check_mmc_autodetect(void)
+{
+	char *autodetect_str = env_get("mmcautodetect");
+
+	if ((autodetect_str) && (strcmp(autodetect_str, "yes") == 0))
+		return 1;
+
+	return 0;
+}
+
+/* This should be defined for each board */
+__weak int mmc_map_to_kernel_blk(int dev_no)
+{
+	return dev_no;
+}
+
+void board_late_mmc_env_init(void)
+{
+	char cmd[32];
+	char mmcblk[32];
+	u32 dev_no = mmc_get_env_dev();
+
+	if (!check_mmc_autodetect())
+		return;
+
+	env_set_ulong("mmcdev", dev_no);
+
+	/* Set mmcblk env */
+	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+		mmc_map_to_kernel_blk(dev_no));
+	env_set("mmcroot", mmcblk);
+
+	sprintf(cmd, "mmc dev %d", dev_no);
+	run_command(cmd, 0);
+}
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/.gitignore b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/.gitignore
new file mode 100644
index 000000000..6eb8a5481
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/Kconfig
new file mode 100644
index 000000000..64692509f
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/Kconfig
@@ -0,0 +1,30 @@
+config SYS_BOARD
+	default "conga-qeval20-qa3-e3845"
+
+config SYS_VENDOR
+	default "congatec"
+
+config SYS_SOC
+	default "baytrail"
+
+config SYS_CONFIG_NAME
+	default "conga-qeval20-qa3-e3845" if TARGET_CONGA_QEVAL20_QA3_E3845
+	default "theadorable-x86-conga-qa3-e3845" if TARGET_THEADORABLE_X86_CONGA_QA3_E3845
+
+config SYS_TEXT_BASE
+	default 0xfff00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
+	select BOARD_LATE_INIT
+	select SPI_FLASH_STMICRO
+	imply SPI_FLASH_SPANSION
+	imply SPI_FLASH_WINBOND
+	select SERIAL_RX_BUFFER
+
+config PCIE_ECAM_BASE
+	default 0xe0000000
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
new file mode 100644
index 000000000..cceda4f49
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
@@ -0,0 +1,11 @@
+congatec EVAL20-QA3-E3845
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/congatec/conga-qeval20-qa3-e3845
+F:	include/configs/conga-qeval20-qa3-e3845.h
+F:	include/configs/theadorable-x86-conga-qa3-e3845.h
+F:	configs/conga-qeval20-qa3-e3845_defconfig
+F:	configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+F:	configs/theadorable-x86-conga-qa3-e3845_defconfig
+F:	configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
+F:	arch/x86/dts/conga-qeval20-qa3-e3845.dts
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/Makefile b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/Makefile
new file mode 100644
index 000000000..451a4fcd6
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Google, Inc
+
+obj-y	+= conga-qeval20-qa3.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/README b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/README
new file mode 100644
index 000000000..98ff992a3
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/README
@@ -0,0 +1,23 @@
+------------------------------
+U-Boot console UART selection:
+------------------------------
+
+The U-Boot port for this congatec board currently supports two different
+configurations (defconfig files). The only difference is the UART that
+is used as the U-Boot console UART. The default defconfig file:
+
+conga-qeval20-qa3-e3845_defconfig
+
+provides this console on the UART0 which is provided via a Winbond
+Super-IO chip connected on the congatec Qseven 2.0 evaluation carrier
+board (conga-QEVAL). This UART is the one provided with a SubD9
+connector on the mainboard (the low one). The 2nd defconfig file:
+
+conga-qeval20-qa3-e3845-internal-uart_defconfig
+
+provides the U-Boot console on the BayTrail internal legacy UART,
+which is routed from the QSeven SoM to the X300 connector on the
+baseboard. Here is called COM2. The baseboard already provides the
+RS232 level shifters. So a TTL-USB UART adapter does not work in
+this case. The signals need to get connected directly to the
+RS232 level signals of the PC UART via some adapter cable.
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl
new file mode 100644
index 000000000..856960d5e
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
+
+/* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
new file mode 100644
index 000000000..315b6dc54
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <init.h>
+#include <winbond_w83627.h>
+#include <asm/gpio.h>
+#include <asm/ibmpc.h>
+#include <asm/pnp_def.h>
+
+int board_early_init_f(void)
+{
+#ifndef CONFIG_INTERNAL_UART
+	/*
+	 * The FSP enables the BayTrail internal legacy UART (again).
+	 * Disable it again, so that the Winbond one can be used.
+	 */
+	setup_internal_uart(0);
+
+	/* Enable the legacy UART in the Winbond W83627 Super IO chip */
+	winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
+			      UART0_BASE, UART0_IRQ);
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct udevice *dev;
+	u8 buf[8];
+	int ret;
+
+	/* Configure SMSC USB2513 USB Hub: 7bit address 0x2c */
+	ret = i2c_get_chip_for_busnum(0, 0x2c, 1, &dev);
+	if (ret) {
+		printf("Cannot find USB2513: %d\n", ret);
+		return 0;
+	}
+
+	/*
+	 * The first access to the USB Hub fails sometimes, so lets read
+	 * a dummy byte to be sure here
+	 */
+	dm_i2c_read(dev, 0x00, buf, 1);
+
+	/*
+	 * The SMSC hub is not visible on the I2C bus after the first
+	 * configuration at power-up. The following code deliberately
+	 * does not report upon failure of these I2C write calls.
+	 */
+	buf[0] = 0x93;
+	dm_i2c_write(dev, 0x06, buf, 1);
+
+	buf[0] = 0xaa;
+	dm_i2c_write(dev, 0xf8, buf, 1);
+
+	buf[0] = 0x0f;
+	dm_i2c_write(dev, 0xfa, buf, 1);
+
+	buf[0] = 0x01;
+	dm_i2c_write(dev, 0xff, buf, 1);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl
new file mode 100644
index 000000000..d2297ef59
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/roms/u-boot/board/coreboot/Kconfig b/roms/u-boot/board/coreboot/Kconfig
new file mode 100644
index 000000000..05a72d3c5
--- /dev/null
+++ b/roms/u-boot/board/coreboot/Kconfig
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+
+if VENDOR_COREBOOT
+
+choice
+	prompt "Mainboard model"
+	optional
+
+config TARGET_COREBOOT
+	bool "coreboot"
+	help
+	  This target is used for running U-Boot on top of coreboot. In
+	  this case coreboot does the early inititalisation, and U-Boot
+	  takes over once the RAM, video and CPU are fully running.
+	  U-Boot is loaded as a fallback payload from coreboot, in
+	  coreboot terminology. This method was used for the Chromebook
+	  Pixel when launched.
+
+endchoice
+
+source "board/coreboot/coreboot/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/coreboot/coreboot/Kconfig b/roms/u-boot/board/coreboot/coreboot/Kconfig
new file mode 100644
index 000000000..5bd6465d9
--- /dev/null
+++ b/roms/u-boot/board/coreboot/coreboot/Kconfig
@@ -0,0 +1,34 @@
+if TARGET_COREBOOT
+
+config SYS_BOARD
+	default "coreboot"
+
+config SYS_VENDOR
+	default "coreboot"
+
+config SYS_SOC
+	default "coreboot"
+
+config SYS_CONFIG_NAME
+	default "coreboot"
+
+config SYS_TEXT_BASE
+	default 0x01110000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select BOARD_EARLY_INIT_R
+
+config SYS_CAR_ADDR
+	hex "Board specific Cache-As-RAM (CAR) address"
+	default 0x01920000
+	help
+	  This option specifies the board specific Cache-As-RAM (CAR) address.
+
+config SYS_CAR_SIZE
+	hex "Board specific Cache-As-RAM (CAR) size"
+	default 0x4000
+	help
+	  This option specifies the board specific Cache-As-RAM (CAR) size.
+
+endif
diff --git a/roms/u-boot/board/coreboot/coreboot/MAINTAINERS b/roms/u-boot/board/coreboot/coreboot/MAINTAINERS
new file mode 100644
index 000000000..a05673bb0
--- /dev/null
+++ b/roms/u-boot/board/coreboot/coreboot/MAINTAINERS
@@ -0,0 +1,13 @@
+COREBOOT BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/coreboot/coreboot/
+F:	include/configs/chromebook_link.h
+F:	configs/coreboot_defconfig
+
+COREBOOT64 BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/coreboot/coreboot/
+F:	include/configs/chromebook_link.h
+F:	configs/coreboot64_defconfig
diff --git a/roms/u-boot/board/coreboot/coreboot/Makefile b/roms/u-boot/board/coreboot/coreboot/Makefile
new file mode 100644
index 000000000..d292b7032
--- /dev/null
+++ b/roms/u-boot/board/coreboot/coreboot/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+
+obj-y	+= coreboot.o
diff --git a/roms/u-boot/board/coreboot/coreboot/coreboot.c b/roms/u-boot/board/coreboot/coreboot/coreboot.c
new file mode 100644
index 000000000..175d3ce69
--- /dev/null
+++ b/roms/u-boot/board/coreboot/coreboot/coreboot.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/cb_sysinfo.h>
+#include <asm/global_data.h>
+#include <init.h>
+#include <smbios.h>
+
+int board_early_init_r(void)
+{
+	/*
+	 * Make sure PCI bus is enumerated so that peripherals on the PCI bus
+	 * can be discovered by their drivers
+	 */
+	pci_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_SMBIOS_PARSER
+int show_board_info(void)
+{
+	const struct smbios_entry *smbios = smbios_entry(lib_sysinfo.smbios_start, lib_sysinfo.smbios_size);
+
+	if (!smbios)
+		goto fallback;
+
+	const struct smbios_header *bios = smbios_header(smbios, SMBIOS_BIOS_INFORMATION);
+	const struct smbios_header *system = smbios_header(smbios, SMBIOS_SYSTEM_INFORMATION);
+	const struct smbios_type0 *t0 = (struct smbios_type0 *)bios;
+	const struct smbios_type1 *t1 = (struct smbios_type1 *)system;
+
+	if (!t0 || !t1)
+		goto fallback;
+
+	const char *bios_ver = smbios_string(bios, t0->bios_ver);
+	const char *model = smbios_string(system, t1->product_name);
+	const char *manufacturer = smbios_string(system, t1->manufacturer);
+
+	if (!model || !manufacturer || !bios_ver)
+		goto fallback;
+
+	printf("Vendor: %s\n", manufacturer);
+	printf("Model: %s\n", model);
+	printf("BIOS Version: %s\n", bios_ver);
+
+	return 0;
+
+fallback:
+#ifdef CONFIG_OF_CONTROL
+	DECLARE_GLOBAL_DATA_PTR;
+
+	model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+
+	if (model)
+		printf("Model: %s\n", model);
+#endif
+
+	return checkboard();
+}
+#endif
diff --git a/roms/u-boot/board/cortina/common/Kconfig b/roms/u-boot/board/cortina/common/Kconfig
new file mode 100644
index 000000000..00c709e70
--- /dev/null
+++ b/roms/u-boot/board/cortina/common/Kconfig
@@ -0,0 +1,6 @@
+config CORTINA_PLATFORM
+       bool "Cortina-Access Platform"
+       default y
+       help
+         Select this option for Cortina-Access platforms
+	 to enables selection of CAxxxx drivers
diff --git a/roms/u-boot/board/cortina/presidio-asic/Kconfig b/roms/u-boot/board/cortina/presidio-asic/Kconfig
new file mode 100644
index 000000000..8e6f6cfa2
--- /dev/null
+++ b/roms/u-boot/board/cortina/presidio-asic/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_PRESIDIO_ASIC
+config BIT64
+       bool
+       default y
+
+select SOC_CA7774
+
+config SYS_BOARD
+	default "presidio-asic"
+
+config SYS_VENDOR
+	default "cortina"
+
+config SYS_CONFIG_NAME
+	default "presidio_asic"
+
+source "board/cortina/common/Kconfig"
+endif
diff --git a/roms/u-boot/board/cortina/presidio-asic/MAINTAINERS b/roms/u-boot/board/cortina/presidio-asic/MAINTAINERS
new file mode 100644
index 000000000..9db17bd14
--- /dev/null
+++ b/roms/u-boot/board/cortina/presidio-asic/MAINTAINERS
@@ -0,0 +1,6 @@
+Cortina Presidio ASIC G3 Engineering BOARD
+M:	Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
+S:	Supported
+F:	board/cortina/presidio-asic/
+F:	include/configs/presidio_asic.h
+F:	configs/cortina_presidio-asic*defconfig
diff --git a/roms/u-boot/board/cortina/presidio-asic/Makefile b/roms/u-boot/board/cortina/presidio-asic/Makefile
new file mode 100644
index 000000000..d167a157f
--- /dev/null
+++ b/roms/u-boot/board/cortina/presidio-asic/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# (C) Copyright 2020 Cortina-Access.Inc.
+#
+#
+
+obj-y	:= presidio.o
+obj-y	+= lowlevel_init.o
diff --git a/roms/u-boot/board/cortina/presidio-asic/lowlevel_init.S b/roms/u-boot/board/cortina/presidio-asic/lowlevel_init.S
new file mode 100644
index 000000000..4450a5df7
--- /dev/null
+++ b/roms/u-boot/board/cortina/presidio-asic/lowlevel_init.S
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Cortina-Access
+ *
+ */
+
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/armv8/mmu.h>
+
+	.globl lowlevel_init
+lowlevel_init:
+	mov	x29, lr			/* Save LR */
+
+#if defined(CONFIG_SOC_CA7774)
+	/* Enable SMPEN in CPUECTLR */
+	mrs     x0, s3_1_c15_c2_1
+	tst     x0, #0x40
+        b.ne    skip_smp_setup
+	orr     x0, x0, #0x40
+	msr     s3_1_c15_c2_1, x0
+skip_smp_setup:
+#endif
+
+#if defined(CONFIG_SOC_CA8277B)
+	/* Enable CPU Timer */
+	ldr x0, =CONFIG_SYS_TIMER_BASE
+	mov x1, #1
+	str w1, [x0]
+#endif
+
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+	branch_if_slave x0, 1f
+#ifndef CONFIG_TARGET_VENUS
+	ldr	x0, =GICD_BASE
+	bl	gic_init_secure
+#endif
+1:
+#if defined(CONFIG_GICV3)
+	ldr	x0, =GICR_BASE
+	bl	gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+	ldr	x0, =GICD_BASE
+	ldr	x1, =GICC_BASE
+	bl	gic_init_secure_percpu
+#endif
+#endif
+
+#ifdef CONFIG_ARMV8_MULTIENTRY
+	branch_if_master x0, x1, 2f
+
+	/*
+	 * Slave should wait for master clearing spin table.
+	 * This sync prevent salves observing incorrect
+	 * value of spin table and jumping to wrong place.
+	 */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+	ldr	x0, =GICC_BASE
+#endif
+	bl	gic_wait_for_interrupt
+#endif
+
+	/*
+	 * All slaves will enter EL2 and optionally EL1.
+	 */
+	adr	x4, lowlevel_in_el2
+	ldr	x5, =ES_TO_AARCH64
+	bl	armv8_switch_to_el2
+
+lowlevel_in_el2:
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	adr	x4, lowlevel_in_el1
+	ldr	x5, =ES_TO_AARCH64
+	bl	armv8_switch_to_el1
+
+lowlevel_in_el1:
+#endif
+
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
+2:
+	mov	lr, x29			/* Restore LR */
+	ret
diff --git a/roms/u-boot/board/cortina/presidio-asic/presidio.c b/roms/u-boot/board/cortina/presidio-asic/presidio.c
new file mode 100644
index 000000000..f344622b0
--- /dev/null
+++ b/roms/u-boot/board/cortina/presidio-asic/presidio.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 - Cortina Access Inc.
+ *
+ */
+#include <common.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/compiler.h>
+#include <configs/presidio_asic.h>
+#include <linux/psci.h>
+#include <asm/psci.h>
+#include <cpu_func.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CA_PERIPH_BASE                  0xE0000000UL
+#define CA_PERIPH_SIZE                  0x20000000UL
+#define CA_GLOBAL_BASE                  0xf4320000
+#define CA_GLOBAL_JTAG_ID               0xf4320000
+#define CA_GLOBAL_BLOCK_RESET           0xf4320004
+#define CA_GLOBAL_BLOCK_RESET_RESET_DMA BIT(16)
+#define CA_DMA_SEC_SSP_BAUDRATE_CTRL    0xf7001b94
+#define CA_DMA_SEC_SSP_ID               0xf7001b80
+
+int print_cpuinfo(void)
+{
+	printf("CPU:   Cortina Presidio G3\n");
+	return 0;
+}
+
+static struct mm_region presidio_mem_map[] = {
+	{
+	.virt = DDR_BASE,
+	.phys = DDR_BASE,
+	.size = PHYS_SDRAM_1_SIZE,
+	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+		 PTE_BLOCK_OUTER_SHARE
+	},
+	{
+	.virt = CA_PERIPH_BASE,
+	.phys = CA_PERIPH_BASE,
+	.size = CA_PERIPH_SIZE,
+	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+		 PTE_BLOCK_NON_SHARE
+	},
+	{
+	/* List terminator */
+	0,
+	}
+};
+
+struct mm_region *mem_map = presidio_mem_map;
+
+static noinline int invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
+				       u64 arg2)
+{
+	asm volatile("mov x0, %0\n"
+		    "mov x1, %1\n"
+		    "mov x2, %2\n"
+		    "mov x3, %3\n"
+		    "smc	#0\n"
+		    : "+r" (function_id)
+		    : "r" (arg0), "r" (arg1), "r" (arg2)
+		    );
+
+	return function_id;
+}
+
+int board_early_init_r(void)
+{
+	dcache_disable();
+	return 0;
+}
+
+int board_init(void)
+{
+	unsigned int reg_data, jtag_id;
+
+	/* Enable timer */
+	writel(1, CONFIG_SYS_TIMER_BASE);
+
+	/* Enable snoop in CCI400 slave port#4 */
+	writel(3, 0xF5595000);
+
+	jtag_id = readl(CA_GLOBAL_JTAG_ID);
+
+	/* If this is HGU variant then do not use
+	 * the Saturn daughter card ref. clk
+	 */
+	if (jtag_id == 0x1010D8F3) {
+		reg_data = readl(0xF3100064);
+		/* change multifunc. REF CLK pin to
+		 * a simple GPIO pin
+		 */
+		reg_data |= (1 << 1);
+		writel(reg_data, 0xf3100064);
+	}
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned int ddr_size;
+
+	ddr_size = readl(0x111100c);
+	gd->ram_size = ddr_size * 0x100000;
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	invoke_psci_fn_smc(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
+}
+
+#ifdef CONFIG_LAST_STAGE_INIT
+int last_stage_init(void)
+{
+	u32 val;
+
+	val = readl(CA_GLOBAL_BLOCK_RESET);
+	val &= ~CA_GLOBAL_BLOCK_RESET_RESET_DMA;
+	writel(val, CA_GLOBAL_BLOCK_RESET);
+
+	/* reduce output pclk ~3.7Hz to save power consumption */
+	writel(0x000000FF, CA_DMA_SEC_SSP_BAUDRATE_CTRL);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/cssi/MAINTAINERS b/roms/u-boot/board/cssi/MAINTAINERS
new file mode 100644
index 000000000..cbf1406a5
--- /dev/null
+++ b/roms/u-boot/board/cssi/MAINTAINERS
@@ -0,0 +1,6 @@
+BOARDS from CS Systemes d'Information
+M:	Christophe Leroy <christophe.leroy@c-s.fr>
+S:	Maintained
+F:	board/cssi/
+F:	include/configs/MCR3000.h
+F:	configs/MCR3000_defconfig
diff --git a/roms/u-boot/board/cssi/MCR3000/Kconfig b/roms/u-boot/board/cssi/MCR3000/Kconfig
new file mode 100644
index 000000000..ecfd90fd4
--- /dev/null
+++ b/roms/u-boot/board/cssi/MCR3000/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MCR3000
+
+config SYS_BOARD
+	default "MCR3000"
+
+config SYS_VENDOR
+	default "cssi"
+
+config SYS_CONFIG_NAME
+	default "MCR3000"
+
+config SYS_TEXT_BASE
+	default 0x04000000
+
+endif
diff --git a/roms/u-boot/board/cssi/MCR3000/MCR3000.c b/roms/u-boot/board/cssi/MCR3000/MCR3000.c
new file mode 100644
index 000000000..c20e87149
--- /dev/null
+++ b/roms/u-boot/board/cssi/MCR3000/MCR3000.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * Board specific routines for the MCR3000 board
+ */
+
+#include <common.h>
+#include <env.h>
+#include <hwconfig.h>
+#include <init.h>
+#include <mpc8xx.h>
+#include <fdt_support.h>
+#include <serial.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dm/uclass.h>
+#include <wdt.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SDRAM_MAX_SIZE			(32 * 1024 * 1024)
+
+static const uint cs1_dram_table_66[] = {
+	/* DRAM - single read. (offset 0 in upm RAM) */
+	0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
+	0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* DRAM - burst read. (offset 8 in upm RAM) */
+	0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
+	0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* DRAM - single write. (offset 18 in upm RAM) */
+	0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
+	0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* DRAM - burst write. (offset 20 in upm RAM) */
+	0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
+	0x00FFFC00, 0x00FFFC04,	0x0FFEF804, 0x0FFDF404,
+	0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* refresh  (offset 30 in upm RAM) */
+	0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
+	0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
+
+	/* init */
+	0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
+
+	/* exception. (offset 3c in upm RAM) */
+	0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	const char *sync = "receive";
+
+	ft_cpu_setup(blob, bd);
+
+	/* BRG */
+	do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
+			     bd->bi_busfreq, 1);
+
+	/* MAC addr */
+	fdt_fixup_ethernet(blob);
+
+	/* Bus Frequency for CPM */
+	do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
+
+	/* E1 interface - Set data rate */
+	do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
+
+	/* E1 interface - Set channel phase to 0 */
+	do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
+
+	/* E1 interface - rising edge sync pulse transmit */
+	do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
+			 sync, strlen(sync), 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	serial_puts("BOARD: MCR3000 CSSI\n");
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	memctl8xx_t __iomem *memctl = &immap->im_memctl;
+
+	printf("UPMA init for SDRAM (CAS latency 2), ");
+	printf("init address 0x%08x, size ", (int)dram_init);
+	/* Configure UPMA for cs1 */
+	upmconfig(UPMA, (uint *)cs1_dram_table_66,
+		  sizeof(cs1_dram_table_66) / sizeof(uint));
+	udelay(10);
+	out_be16(&memctl->memc_mptpr, 0x0200);
+	out_be32(&memctl->memc_mamr, 0x14904000);
+	udelay(10);
+	out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
+	out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
+	udelay(10);
+	out_be32(&memctl->memc_mcr, 0x80002830);
+	out_be32(&memctl->memc_mar, 0x00000088);
+	out_be32(&memctl->memc_mcr, 0x80002038);
+	udelay(200);
+
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				    SDRAM_MAX_SIZE);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	iop8xx_t __iomem *iop = &immr->im_ioport;
+
+	/* Set port C13 as GPIO (BTN_ACQ_AL) */
+	clrbits_be16(&iop->iop_pcpar, 0x4);
+	clrbits_be16(&iop->iop_pcdir, 0x4);
+
+	/* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
+	if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
+		env_set("bootdelay", "60");
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	/*
+	 * Erase FPGA(s) for reboot
+	 */
+	clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
+	setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
+	udelay(1);				/* Wait more than 300ns */
+	setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	struct udevice *watchdog_dev = NULL;
+
+	if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
+		puts("Cannot find watchdog!\n");
+	} else {
+		puts("Enabling watchdog.\n");
+		wdt_start(watchdog_dev, 0xffff, 0);
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/cssi/MCR3000/Makefile b/roms/u-boot/board/cssi/MCR3000/Makefile
new file mode 100644
index 000000000..68d6812a8
--- /dev/null
+++ b/roms/u-boot/board/cssi/MCR3000/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2010-2017 CS Systemes d'Information
+# Christophe Leroy <christophe.leroy@c-s.fr>
+#
+
+obj-y += MCR3000.o
+obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/roms/u-boot/board/cssi/MCR3000/nand.c b/roms/u-boot/board/cssi/MCR3000/nand.c
new file mode 100644
index 000000000..15a10bffa
--- /dev/null
+++ b/roms/u-boot/board/cssi/MCR3000/nand.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ */
+
+#include <config.h>
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+#define BIT_CLE			((unsigned short)0x0800)
+#define BIT_ALE			((unsigned short)0x0400)
+#define BIT_NCE			((unsigned short)0x1000)
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this	= mtd_to_nand(mtdinfo);
+	immap_t __iomem *immr	= (immap_t __iomem *)CONFIG_SYS_IMMR;
+	unsigned short pddat	= 0;
+
+	/* The hardware control change */
+	if (ctrl & NAND_CTRL_CHANGE) {
+		pddat = in_be16(&immr->im_ioport.iop_pddat);
+
+		/* Clearing ALE and CLE */
+		pddat &= ~(BIT_CLE | BIT_ALE);
+
+		/* Driving NCE pin */
+		if (ctrl & NAND_NCE)
+			pddat &= ~BIT_NCE;
+		else
+			pddat |= BIT_NCE;
+
+		/* Driving CLE and ALE pin */
+		if (ctrl & NAND_CLE)
+			pddat |= BIT_CLE;
+		if (ctrl & NAND_ALE)
+			pddat |= BIT_ALE;
+
+		out_be16(&immr->im_ioport.iop_pddat, pddat);
+	}
+
+	/* Writing the command */
+	if (cmd != NAND_CMD_NONE)
+		out_8(this->IO_ADDR_W, cmd);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	immap_t __iomem *immr	= (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	/* Set GPIO Port */
+	setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
+	clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
+	clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
+
+	nand->chip_delay	= 60;
+	nand->ecc.mode		= NAND_ECC_SOFT;
+	nand->cmd_ctrl		= nand_hwcontrol;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/cssi/MCR3000/u-boot.lds b/roms/u-boot/board/cssi/MCR3000/u-boot.lds
new file mode 100644
index 000000000..70aef3241
--- /dev/null
+++ b/roms/u-boot/board/cssi/MCR3000/u-boot.lds
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+	/* Read-only sections, merged into text segment: */
+	. = + SIZEOF_HEADERS;
+	.text          :
+	{
+		arch/powerpc/cpu/mpc8xx/start.o	(.text)
+		arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+		arch/powerpc/lib/built-in.o		(.text*)
+		drivers/net/built-in.o		(.text*)
+
+		. = DEFINED(env_offset) ? env_offset : .;
+		env/embedded.o			(.text.environment)
+
+		*(.text)
+	}
+	_etext = .;
+	PROVIDE (etext = .);
+	.rodata    :
+	{
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	/* Read-write section, merged into data segment: */
+	. = (. + 0x0FFF) & 0xFFFFF000;
+	_erotext = .;
+	PROVIDE (erotext = .);
+	.reloc   :
+	{
+		_GOT2_TABLE_ = .;
+		KEEP(*(.got2))
+		KEEP(*(.got))
+		_FIXUP_TABLE_ = .;
+		KEEP(*(.fixup))
+	}
+	__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+	__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+	.data    :
+	{
+		*(.data*)
+		*(.sdata*)
+	}
+	_edata  =  .;
+	PROVIDE (edata = .);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = .;
+	__start___ex_table = .;
+	__ex_table : { *(__ex_table) }
+	__stop___ex_table = .;
+
+	/*
+	 * _end - This is end of u-boot.bin image.
+	 * dtb will be appended here to make u-boot-dtb.bin
+	 */
+	_end = .;
+
+	. = ALIGN(4096);
+	__init_begin = .;
+	.text.init : { *(.text.init) }
+	.data.init : { *(.data.init) }
+	. = ALIGN(4096);
+	__init_end = .;
+
+	__bss_start = .;
+	.bss (NOLOAD)       :
+	{
+		*(.bss*)
+		*(.sbss*)
+		*(COMMON)
+		. = ALIGN(4);
+	}
+	__bss_end = . ;
+	PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/roms/u-boot/board/d-link/dns325/Kconfig b/roms/u-boot/board/d-link/dns325/Kconfig
new file mode 100644
index 000000000..f6341ada6
--- /dev/null
+++ b/roms/u-boot/board/d-link/dns325/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DNS325
+
+config SYS_BOARD
+	default "dns325"
+
+config SYS_VENDOR
+	default "d-link"
+
+config SYS_CONFIG_NAME
+	default "dns325"
+
+endif
diff --git a/roms/u-boot/board/d-link/dns325/MAINTAINERS b/roms/u-boot/board/d-link/dns325/MAINTAINERS
new file mode 100644
index 000000000..a37b7990e
--- /dev/null
+++ b/roms/u-boot/board/d-link/dns325/MAINTAINERS
@@ -0,0 +1,6 @@
+DNS325 BOARD
+M:	Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
+S:	Maintained
+F:	board/d-link/dns325/
+F:	include/configs/dns325.h
+F:	configs/dns325_defconfig
diff --git a/roms/u-boot/board/d-link/dns325/Makefile b/roms/u-boot/board/d-link/dns325/Makefile
new file mode 100644
index 000000000..e78f6d9c3
--- /dev/null
+++ b/roms/u-boot/board/d-link/dns325/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011
+# Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= dns325.o
diff --git a/roms/u-boot/board/d-link/dns325/dns325.c b/roms/u-boot/board/d-link/dns325/dns325.c
new file mode 100644
index 000000000..055783f63
--- /dev/null
+++ b/roms/u-boot/board/d-link/dns325/dns325.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011
+ * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+#include <asm/global_data.h>
+#include "dns325.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/* Gpio configuration */
+	mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
+			  DNS325_OE_LOW, DNS325_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_SATA1_ACTn,	/* sata1(left) status led */
+		MPP21_SATA0_ACTn,	/* sata0(right) status led */
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,		/* power off out */
+		MPP25_GPIO,
+		MPP26_GPIO,		/* power led */
+		MPP27_GPIO,		/* sata0(right) error led */
+		MPP28_GPIO,		/* sata1(left) error led */
+		MPP29_GPIO,		/* usb error led */
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,		/* power key */
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,		/* enable sata 0 */
+		MPP40_GPIO,		/* enable sata 1 */
+		MPP41_GPIO,		/* hdd0 present */
+		MPP42_GPIO,		/* hdd1 present */
+		MPP43_GPIO,		/* usb status led */
+		MPP44_GPIO,		/* fan status */
+		MPP45_GPIO,		/* fan high speed */
+		MPP46_GPIO,		/* fan low speed */
+		MPP47_GPIO,		/* usb umount */
+		MPP48_GPIO,		/* factory reset */
+		MPP49_GPIO,		/* thermal sensor */
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+
+	kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
+
+	kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Boot parameters address */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..(%s) could not read PHY dev address\n", __func__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	debug("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/roms/u-boot/board/d-link/dns325/dns325.h b/roms/u-boot/board/d-link/dns325/dns325.h
new file mode 100644
index 000000000..62ced6814
--- /dev/null
+++ b/roms/u-boot/board/d-link/dns325/dns325.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011
+ * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef __DNS325_H
+#define __DNS325_H
+
+/* GPIO configuration */
+#define DNS325_OE_LOW			0x00000000
+#define DNS325_OE_HIGH			0x00039604
+#define DNS325_OE_VAL_LOW		0x38000000	/* disable leds */
+#define DNS325_OE_VAL_HIGH		0x00000800	/* disable leds */
+
+#define DNS325_GPIO_LED_POWER		26
+#define DNS325_GPIO_SATA0_EN		39
+#define DNS325_GPIO_SATA1_EN		40
+
+/* PHY related */
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __DNS325_H */
diff --git a/roms/u-boot/board/d-link/dns325/kwbimage.cfg b/roms/u-boot/board/d-link/dns325/kwbimage.cfg
new file mode 100644
index 000000000..dc2a34513
--- /dev/null
+++ b/roms/u-boot/board/d-link/dns325/kwbimage.cfg
@@ -0,0 +1,190 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011
+# Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30, 3120 DDR2 clks refresh rate
+# bit23-14: 0 required
+# bit24:    1, enable exit self refresh mode on DDR access
+# bit25:    1 required
+# bit29-26: 0 required
+# bit31-30: 0b01 required
+
+DATA 0xFFD01404 0x39543000	# DDR Controller Control Low
+# bit3-0:   0 required
+# bit4:     0, addr/cmd in smame cycle
+# bit5:     0, clk is driven during self refresh, we don't care for APX
+# bit6:     0, use recommended falling edge of clk for addr/cmd
+# bit11-7:  0 required
+# bit12:    1 required
+# bit13:    1 required
+# bit14:    0, input buffer always powered up
+# bit17-15: 0 required
+# bit18:    1, cpu lock transaction enabled
+# bit19:    0 required
+# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0, no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low)
+# bit3-0:   1, 18 cycle tRAS (tRAS[3-0])
+# bit7-4:   5, 6 cycle tRCD
+# bit11-8:  4, 5 cyle tRP
+# bit15-12: 5, 6 cyle tWR
+# bit19-16: 2, 3 cyle tWTR
+# bit20:    1, 18 cycle tRAS (tRAS[4])
+# bit23-21: 0 required
+# bit27-24: 2, 3 cycle tRRD
+# bit31-28: 2, 3 cyle tRTP
+
+DATA 0xFFD0140C 0x00000833	#  DDR Timing (High)
+# bit6-0:   0x33, 33 cycle tRFC
+# bit8-7:   0, 1 cycle tR2R
+# bit10-9:  0, 1 cyle tR2W
+# bit12-11: 1, 2 cylce tW2W
+# bit31-13: 0 required
+
+DATA 0xFFD01410 0x0000000c	#  DDR Address Control
+# bit1-0:   0, Cs0width=x8
+# bit3-2:   3, Cs0size=1Gb
+# bit5-4:   0, Cs1width=nonexistent
+# bit7-6:   0, Cs1size=nonexistent
+# bit9-8:   0, Cs2width=nonexistent
+# bit11-10: 0, Cs2size=nonexistent
+# bit13-12: 0, Cs3width=nonexistent
+# bit15-14: 0, Cs3size=nonexistent
+# bit16:    0, Cs0AddrSel
+# bit17:    0, Cs1AddrSel
+# bit18:    0, Cs2AddrSel
+# bit19:    0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0, OPEn=OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0, Cmd=Normal SDRAM Mode
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, Burst Length (2 required)
+# bit3:     0, Burst Type (0 required)
+# bit6-4:   5, CAS Latency (CL) 5
+# bit7:     0, (Test Mode) Normal operation
+# bit8:     0, (Reset DLL) Normal operation
+# bit11-9:  0, Write recovery for auto-precharge (3 required ??)
+# bit12:    0, Fast Active power down exit time (0 required)
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:     0, DRAM DLL enabled
+# bit1:     0, DRAM drive strength normal
+# bit2:     0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
+# bit5-3:   0 required
+# bit6:     1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
+# bit9-7:   0 required
+# bit10:    0, differential DQS enabled
+# bit11:    0 required
+# bit12:    0, DRAM output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:   0x7 required
+# bit3:     1, MBUS Burst Chop disabled
+# bit6-4:   0x7 required
+# bit7:     0 required
+# bit8:     1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9:     0, no half clock cycle addition to dataout
+# bit10:    0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11:    0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing
+# bit3-0:   0 required
+# bit7-4:   2, 2 cycles from read command to assertion of M_ODT signal
+# bit11-8:  5, 5 cycles from read command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
+# bit31-20: 0 required
+
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing
+# bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
+# bit7-4:   5, 5 cycles from write command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
+# bit31-16: 0 required
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:     1, Window enabled
+# bit1:     0, Write Protect disabled
+# bit3-2:   0x0, CS0 hit selected
+# bit23-4:  0xfffff required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
+# bit0:     1, Window enabled
+# bit1:     0, Write Protect disabled
+# bit3-2:   1, CS1 hit selected
+# bit23-4:  0xfffff required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+# bit3-0:   0b0000, (read) M_ODT[0] is not asserted during read from DRAM
+# bit7-4:   0b0000, (read) M_ODT[1] is not asserted during read from DRAM
+# bit15-8:  0 required
+# bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
+# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
+# bit31-24: 0 required
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:   0, M_ODT[0] assertion is controlled by ODT Control Low register
+# bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
+# bit31-4   0 required
+
+DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+# bit3-0:   0b0011, internal ODT is asserted during read from DRAM bank 0-1
+# bit7-4:   0b0000, internal ODT is not asserted during write to DRAM bank 0-4
+# bit9-8:   0, Internal ODT assertion is controlled by fiels
+# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
+# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
+# bit14:    1, M_STARTBURST_IN ODT enabled
+# bit15:    1, DDR IO ODT Unit: Drive ODT calibration values
+# bit20-16: 0, Pad N channel driving strength for ODT
+# bit25-21: 0, Pad P channel driving strength for ODT
+# bit31-26: 0 required
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit0:     1, enable DDR init upon this register write
+# bit31-1:  0, required
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/davinci/da8xxevm/Kconfig b/roms/u-boot/board/davinci/da8xxevm/Kconfig
new file mode 100644
index 000000000..bb1188b4e
--- /dev/null
+++ b/roms/u-boot/board/davinci/da8xxevm/Kconfig
@@ -0,0 +1,51 @@
+if TARGET_DA850EVM
+
+config SYS_BOARD
+	default "da8xxevm"
+
+config SYS_VENDOR
+	default "davinci"
+
+config SYS_CONFIG_NAME
+	default "da850evm"
+
+menuconfig DA850_MAC
+	bool "Use MAC Address"
+	default y
+
+if DA850_MAC
+config MAC_ADDR_IN_SPIFLASH
+	bool "MAC address in SPI Flash"
+	default y
+	help
+	  The OMAP-L138 and AM1808 SoM are programmed with
+	  their MAC address in SPI Flash from the factory
+	  Enable this option to read the MAC from SPI Flash
+
+config MAC_ADDR_IN_EEPROM
+	bool "MAC address in EEPROM"
+	help
+	  The DA850 EVM comes with SoM are programmed with
+	  their MAC address in SPI Flash from the factory,
+	  but the kit has an optional expansion board with
+	  EEPROM available.  Enable this option to read the
+	  MAC from the EEPROM
+
+endif
+
+endif
+
+if TARGET_OMAPL138_LCDK
+
+config SYS_BOARD
+	default "da8xxevm"
+
+config SYS_VENDOR
+	default "davinci"
+
+config SYS_CONFIG_NAME
+	default "omapl138_lcdk"
+
+endif
+
+source "board/ti/common/Kconfig"
diff --git a/roms/u-boot/board/davinci/da8xxevm/MAINTAINERS b/roms/u-boot/board/davinci/da8xxevm/MAINTAINERS
new file mode 100644
index 000000000..16f103266
--- /dev/null
+++ b/roms/u-boot/board/davinci/da8xxevm/MAINTAINERS
@@ -0,0 +1,14 @@
+DA850_EVM BOARD
+M:	Adam Ford <aford173@gmail.com>
+S:	Maintained
+F:	board/davinci/da8xxevm/
+F:	include/configs/da850evm.h
+F:	configs/da850evm_defconfig
+F:	configs/da850evm_nand_defconfig
+F:	configs/da850evm_direct_nor_defconfig
+
+OMAPL138_LCDK BOARD
+M:	Lokesh Vutla <lokeshvutla@ti.com>
+S:	Maintained
+F:	include/configs/omap1l38_lcdk.h
+F:	configs/omapl138_lcdk_defconfig
diff --git a/roms/u-boot/board/davinci/da8xxevm/Makefile b/roms/u-boot/board/davinci/da8xxevm/Makefile
new file mode 100644
index 000000000..3fac615d7
--- /dev/null
+++ b/roms/u-boot/board/davinci/da8xxevm/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+
+obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)	+= da830evm.o
+obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= da850evm.o
+obj-$(CONFIG_MACH_OMAPL138_LCDK) += omapl138_lcdk.o
diff --git a/roms/u-boot/board/davinci/da8xxevm/README.da850 b/roms/u-boot/board/davinci/da8xxevm/README.da850
new file mode 100644
index 000000000..8cebdcc1b
--- /dev/null
+++ b/roms/u-boot/board/davinci/da8xxevm/README.da850
@@ -0,0 +1,157 @@
+Summary
+=======
+The README is for the boot procedure used for various DA850 (or compatible
+parts such as the AM1808) based boards.
+
+In the context of U-Boot, the board is booted in three stages. The initial
+bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits
+in the internal ROM. The RBL initializes the internal memory and then
+depending on the exact board and pin configurations will initialize another
+controller (such as SPI or NAND) to continue the boot process by loading
+the secondary program loader (SPL).  The SPL will initialize the system
+further (some clocks, SDRAM) and then load the full u-boot from a
+predefined location in persistent storage to DDR and jumps to the u-boot
+entry point.
+
+AIS is an image format defined by TI for the images that are to be loaded
+to memory by the RBL. The image is divided into a series of sections and
+the image's entry point is specified. Each section comes with meta data
+like the target address the section is to be copied to and the size of the
+section, which is used by the RBL to load the image. At the end of the
+image the RBL jumps to the image entry point.  The AIS format allows for
+other things such as programming the clocks and SDRAM if the header is
+programmed for it.  We do not take advantage of this and instead use SPL as
+it allows for additional flexibility (run-time detect of board revision,
+loading the next image from a different media, etc).
+
+
+Compilation
+===========
+The exact build target you need will depend on the board you have.  For
+Logic PD boards, or other boards which store the ethernet MAC address at
+the end of SPI flash, run 'make da850evm'.  Once this build completes you will have a
+u-boot.ais file that needs to be written to the correct persistent
+storage.
+
+
+Flashing the images to SPI
+==========================
+The AIS image can be written to SPI flash using the following commands.
+Assuming that the network is configured and enabled and the u-boot.ais file
+is tftp'able.
+
+U-Boot > sf probe 0
+U-Boot > sf erase 0 +320000
+U-Boot > tftp u-boot.ais
+U-Boot > sf write c0700000 0 $filesize
+
+Flashing the images to NAND
+===========================
+The AIS image can be written to NAND using the u-boot "nand" commands.
+
+Example:
+
+OMAPL138_LCDK requires the AIS image to be written to the second block of
+the NAND flash.
+
+From the "nand info" command we see that the second block would start at
+offset 0x20000:
+
+  U-Boot > nand info
+      sector size      128 KiB (0x20000)
+      Page size       2048 b
+
+From the tftp command we see that we need to copy 0x74908 bytes from
+memory address 0xc0700000 (0x75000 if we align a page of 2048):
+
+  U-Boot > tftp u-boot.ais
+      Load address: 0xc0700000
+      Bytes transferred = 477448 (74908 hex)
+
+The commands to write the image from memory to NAND would be:
+
+  U-Boot > nand erase 0x20000 0x75000
+  U-Boot > nand write 0xc0700000 0x20000 0x75000
+
+Alternatively, MTD partitions may be defined. Using "mtdparts" to
+conveniently have a bootloader partition starting at the second block
+(offset 0x20000):
+
+  setenv mtdids nand0=davinci_nand.0
+  setenv mtdparts mtdparts=davinci_nand.0:128k(bootenv),2m(bootloader)
+
+In this case the commands would be simplified to:
+
+  U-Boot > tftp u-boot.ais
+  U-Boot > nand erase.part bootloader
+  U-Boot > nand write 0xc0700000 bootloader
+
+On the DA850-EVM, NAND can also be written with SW7:7-8 ON and
+
+  sudo mono sfh_OMAP-L138.exe -targetType AM1808 -p /dev/ttyUSB0 \
+	-flash_noubl -flashType NAND ~/src/u-boot/u-boot.ais
+
+To boot the DA850-EVM from NAND, SW7:5 should be switched on and all others
+off.
+
+Flashing the images to MMC
+==========================
+If the boot pins are set to boot from mmc, the RBL will try to load the
+next boot stage form the first couple of sectors of an external mmc card.
+As sector 0 is usually used for storing the partition information, the
+AIS image should be written at least after the first sector, but before the
+first partition begins. (e.g: make sure to leave at least 500KB of unallocated
+space at the start of the mmc when creating the partitions)
+
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is used by SPL, and should
+point to the sector were the u-boot image is located. (eg. After SPL)
+
+There are 2 ways to copy the AIS image to the mmc card:
+
+ 1 - Using the TI tool "uflash"
+	$ uflash -d /dev/mmcblk0  -b ./u-boot.ais -p OMAPL138  -vv
+
+ 2 - using the "dd" command
+	$ dd if=u-boot.ais of=/dev/mmcblk0 seek=117 bs=512 conv=fsync
+
+uflash writes the AIS image at offset 117. For compatibility with uflash,
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is set to take into account this
+offset, and the dd command is adjusted accordingly.
+
+Flashing the images to NOR
+==========================
+NOR Flash is XIP (execute-in-place), so no AIS (or SPL) is needed. The
+u-boot.bin is directy flashed, but CONFIT_DA850_LOWLEVEL must be set
+to initialize hardware that's normally done by SPL.
+
+For this case, CONFIG_SYS_TEXT_BASE=0x60000000 which is the address to
+which the bootloader jumps when powered on.
+
+Example:
+For the da850evm, there is a defconfig setup to use the NOR flash on
+the UI expander board called da850evm_direct_nor_defconfig.
+
+Flash to NOR directly using
+sudo mono ./sfh_OMAP-L138.exe -p /dev/ttyUSB0 -flash_noubl
+  -flashType NOR u-boot.bin
+
+SW7:5 through SW7:7 should be switched on and all others off.
+
+Recovery
+========
+
+In the case of a "bricked" board, you need to use the TI tools found
+here[1] to write the u-boot.ais file.  An example of recovering to the SPI
+flash of an AM1808 would be:
+
+$ mono sfh_OMAP-L138.exe -targetType AM1808 -p /dev/ttyUSB0 \
+	-flash_noubl /path/to/u-boot.ais
+
+For other target types and flash locations:
+
+$ mono sfh_OMAP-L138.exe -h
+
+Links
+=====
+[1]
+ http://processors.wiki.ti.com/index.php/Serial_Boot_and_Flash_Loading_Utility_for_OMAP-L138
diff --git a/roms/u-boot/board/davinci/da8xxevm/da850evm.c b/roms/u-boot/board/davinci/da8xxevm/da850evm.c
new file mode 100644
index 000000000..383a86173
--- /dev/null
+++ b/roms/u-boot/board/davinci/da8xxevm/da850evm.c
@@ -0,0 +1,466 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/arch/hardware.h>
+#include <asm/global_data.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/pinmux_defs.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <linux/errno.h>
+#include <hwconfig.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_MMC_DAVINCI
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define HAS_RMII 1
+#else
+#define HAS_RMII 0
+#endif
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+#define CFG_MAC_ADDR_SPI_BUS	0
+#define CFG_MAC_ADDR_SPI_CS	0
+#define CFG_MAC_ADDR_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+#define CFG_MAC_ADDR_SPI_MODE	SPI_MODE_3
+
+#define CFG_MAC_ADDR_OFFSET	(flash->size - SZ_64K)
+
+#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
+static int get_mac_addr(u8 *addr)
+{
+	struct spi_flash *flash;
+	int ret;
+
+	flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS,
+			CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE);
+	if (!flash) {
+		printf("Error - unable to probe SPI flash.\n");
+		return -1;
+	}
+
+	ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr);
+	if (ret) {
+		printf("Error - unable to read MAC address from SPI flash.\n");
+		return -1;
+	}
+
+	return ret;
+}
+#endif
+
+void dsp_lpsc_on(unsigned domain, unsigned int id)
+{
+	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
+	struct davinci_psc_regs *psc_regs;
+
+	psc_regs = davinci_psc0_regs;
+	mdstat = &psc_regs->psc0.mdstat[id];
+	mdctl = &psc_regs->psc0.mdctl[id];
+	ptstat = &psc_regs->ptstat;
+	ptcmd = &psc_regs->ptcmd;
+
+	while (*ptstat & (0x1 << domain))
+		;
+
+	if ((*mdstat & 0x1f) == 0x03)
+		return;                 /* Already on and enabled */
+
+	*mdctl |= 0x03;
+
+	*ptcmd = 0x1 << domain;
+
+	while (*ptstat & (0x1 << domain))
+		;
+	while ((*mdstat & 0x1f) != 0x03)
+		;		/* Probably an overkill... */
+}
+
+static void dspwake(void)
+{
+	unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
+	u32 val;
+
+	/* if the device is ARM only, return */
+	if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
+		return;
+
+	if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
+		return;
+
+	*resetvect++ = 0x1E000; /* DSP Idle */
+	/* clear out the next 10 words as NOP */
+	memset(resetvect, 0, sizeof(unsigned) *10);
+
+	/* setup the DSP reset vector */
+	writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
+
+	dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
+	val = readl(PSC0_MDCTL + (15 * 4));
+	val |= 0x100;
+	writel(val, (PSC0_MDCTL + (15 * 4)));
+}
+
+int misc_init_r(void)
+{
+	dspwake();
+
+#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM)
+
+	uchar env_enetaddr[6];
+	int enetaddr_found;
+
+	enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr);
+
+#endif
+
+#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
+	int spi_mac_read;
+	uchar buff[6];
+
+	spi_mac_read = get_mac_addr(buff);
+	buff[0] = 0;
+
+	/*
+	 * MAC address not present in the environment
+	 * try and read the MAC address from SPI flash
+	 * and set it.
+	 */
+	if (!enetaddr_found) {
+		if (!spi_mac_read) {
+			if (is_valid_ethaddr(buff)) {
+				if (eth_env_set_enetaddr("ethaddr", buff)) {
+					printf("Warning: Failed to "
+					"set MAC address from SPI flash\n");
+				}
+			} else {
+					printf("Warning: Invalid "
+					"MAC address read from SPI flash\n");
+			}
+		}
+	} else {
+		/*
+		 * MAC address present in environment compare it with
+		 * the MAC address in SPI flash and warn on mismatch
+		 */
+		if (!spi_mac_read && is_valid_ethaddr(buff) &&
+		    memcmp(env_enetaddr, buff, 6))
+			printf("Warning: MAC address in SPI flash don't match "
+					"with the MAC address in the environment\n");
+		printf("Default using MAC address from environment\n");
+	}
+
+#elif defined(CONFIG_MAC_ADDR_IN_EEPROM)
+	uint8_t enetaddr[8];
+	int eeprom_mac_read;
+
+	/* Read Ethernet MAC address from EEPROM */
+	eeprom_mac_read = dvevm_read_mac_address(enetaddr);
+
+	/*
+	 * MAC address not present in the environment
+	 * try and read the MAC address from EEPROM flash
+	 * and set it.
+	 */
+	if (!enetaddr_found) {
+		if (eeprom_mac_read)
+			/* Set Ethernet MAC address from EEPROM */
+			davinci_sync_env_enetaddr(enetaddr);
+	} else {
+		/*
+		 * MAC address present in environment compare it with
+		 * the MAC address in EEPROM and warn on mismatch
+		 */
+		if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
+			printf("Warning: MAC address in EEPROM don't match "
+					"with the MAC address in the environment\n");
+		printf("Default using MAC address from environment\n");
+	}
+
+#endif
+	return 0;
+}
+
+static const struct pinmux_config gpio_pins[] = {
+#ifdef CONFIG_MTD_NOR_FLASH
+	/* GP0[11] is required for NOR to work on Rev 3 EVMs */
+	{ pinmux(0), 8, 4 },	/* GP0[11] */
+#endif
+#ifdef CONFIG_MMC_DAVINCI
+	/* GP0[11] is required for SD to work on Rev 3 EVMs */
+	{ pinmux(0),  8, 4 },	/* GP0[11] */
+#endif
+};
+
+const struct pinmux_resource pinmuxes[] = {
+#ifdef CONFIG_DRIVER_TI_EMAC
+	PINMUX_ITEM(emac_pins_mdio),
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+	PINMUX_ITEM(emac_pins_rmii),
+#else
+	PINMUX_ITEM(emac_pins_mii),
+#endif
+#endif
+#ifdef CONFIG_SPI_FLASH
+	PINMUX_ITEM(spi1_pins_base),
+	PINMUX_ITEM(spi1_pins_scs0),
+#endif
+	PINMUX_ITEM(uart2_pins_txrx),
+	PINMUX_ITEM(uart2_pins_rtscts),
+	PINMUX_ITEM(i2c0_pins),
+#ifdef CONFIG_NAND_DAVINCI
+	PINMUX_ITEM(emifa_pins_cs3),
+	PINMUX_ITEM(emifa_pins_cs4),
+	PINMUX_ITEM(emifa_pins_nand),
+#elif defined(CONFIG_MTD_NOR_FLASH)
+	PINMUX_ITEM(emifa_pins_cs2),
+	PINMUX_ITEM(emifa_pins_nor),
+#endif
+	PINMUX_ITEM(gpio_pins),
+#ifdef CONFIG_MMC_DAVINCI
+	PINMUX_ITEM(mmc0_pins),
+#endif
+};
+
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
+const struct lpsc_resource lpsc[] = {
+	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
+	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
+	{ DAVINCI_LPSC_EMAC },	/* image download */
+	{ DAVINCI_LPSC_UART2 },	/* console */
+	{ DAVINCI_LPSC_GPIO },
+#ifdef CONFIG_MMC_DAVINCI
+	{ DAVINCI_LPSC_MMC_SD },
+#endif
+};
+
+const int lpsc_size = ARRAY_SIZE(lpsc);
+
+#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
+#define CONFIG_DA850_EVM_MAX_CPU_CLK	300000000
+#endif
+
+#define REV_AM18X_EVM		0x100
+
+/*
+ * get_board_rev() - setup to pass kernel board revision information
+ * Returns:
+ * bit[0-3]	Maximum cpu clock rate supported by onboard SoC
+ *		0000b - 300 MHz
+ *		0001b - 372 MHz
+ *		0010b - 408 MHz
+ *		0011b - 456 MHz
+ */
+u32 get_board_rev(void)
+{
+	char *s;
+	u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
+	u32 rev = 0;
+
+	s = env_get("maxcpuclk");
+	if (s)
+		maxcpuclk = simple_strtoul(s, NULL, 10);
+
+	if (maxcpuclk >= 456000000)
+		rev = 3;
+	else if (maxcpuclk >= 408000000)
+		rev = 2;
+	else if (maxcpuclk >= 372000000)
+		rev = 1;
+	return rev;
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * Power on required peripherals
+	 * ARM does not have access by default to PSC0 and PSC1
+	 * assuming here that the DSP bootloader has set the IOPU
+	 * such that PSC access is available to ARM
+	 */
+	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+		return 1;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	irq_init();
+
+#ifdef CONFIG_NAND_DAVINCI
+	/*
+	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
+	 * Linux kernel @ 25MHz EMIFA
+	 */
+	writel((DAVINCI_ABCR_WSETUP(2) |
+		DAVINCI_ABCR_WSTROBE(2) |
+		DAVINCI_ABCR_WHOLD(1) |
+		DAVINCI_ABCR_RSETUP(1) |
+		DAVINCI_ABCR_RSTROBE(4) |
+		DAVINCI_ABCR_RHOLD(0) |
+		DAVINCI_ABCR_TA(1) |
+		DAVINCI_ABCR_ASIZE_8BIT),
+	       &davinci_emif_regs->ab2cr); /* CS3 */
+#endif
+
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* setup the SUSPSRC for ARM to control emulation suspend */
+	writel(readl(&davinci_syscfg_regs->suspsrc) &
+	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+		 DAVINCI_SYSCFG_SUSPSRC_UART2),
+	       &davinci_syscfg_regs->suspsrc);
+
+#ifdef CONFIG_MTD_NOR_FLASH
+	/* Set the GPIO direction as output */
+	clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
+
+	/* Set the output as low */
+	writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
+#endif
+
+#ifdef CONFIG_MMC_DAVINCI
+	/* Set the GPIO direction as output */
+	clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
+
+	/* Set the output as high */
+	writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+	davinci_emac_mii_mode_sel(HAS_RMII);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+/**
+ * rmii_hw_init
+ *
+ * DA850/OMAP-L138 EVM can interface to a daughter card for
+ * additional features. This card has an I2C GPIO Expander TCA6416
+ * to select the required functions like camera, RMII Ethernet,
+ * character LCD, video.
+ *
+ * Initialization of the expander involves configuring the
+ * polarity and direction of the ports. P07-P05 are used here.
+ * These ports are connected to a Mux chip which enables only one
+ * functionality at a time.
+ *
+ * For RMII phy to respond, the MII MDIO clock has to be  disabled
+ * since both the PHY devices have address as zero. The MII MDIO
+ * clock is controlled via GPIO2[6].
+ *
+ * This code is valid for Beta version of the hardware
+ */
+int rmii_hw_init(void)
+{
+	const struct pinmux_config gpio_pins[] = {
+		{ pinmux(6), 8, 1 }
+	};
+	u_int8_t buf[2];
+	unsigned int temp;
+	int ret;
+
+	/* PinMux for GPIO */
+	if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
+		return 1;
+
+	/* I2C Exapnder configuration */
+	/* Set polarity to non-inverted */
+	buf[0] = 0x0;
+	buf[1] = 0x0;
+	ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
+	if (ret) {
+		printf("\nExpander @ 0x%02x write FAILED!!!\n",
+				CONFIG_SYS_I2C_EXPANDER_ADDR);
+		return ret;
+	}
+
+	/* Configure P07-P05 as outputs */
+	buf[0] = 0x1f;
+	buf[1] = 0xff;
+	ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
+	if (ret) {
+		printf("\nExpander @ 0x%02x write FAILED!!!\n",
+				CONFIG_SYS_I2C_EXPANDER_ADDR);
+	}
+
+	/* For Ethernet RMII selection
+	 * P07(SelA)=0
+	 * P06(SelB)=1
+	 * P05(SelC)=1
+	 */
+	if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+		printf("\nExpander @ 0x%02x read FAILED!!!\n",
+				CONFIG_SYS_I2C_EXPANDER_ADDR);
+	}
+
+	buf[0] &= 0x1f;
+	buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
+	if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+		printf("\nExpander @ 0x%02x write FAILED!!!\n",
+				CONFIG_SYS_I2C_EXPANDER_ADDR);
+	}
+
+	/* Set the output as high */
+	temp = REG(GPIO_BANK2_REG_SET_ADDR);
+	temp |= (0x01 << 6);
+	REG(GPIO_BANK2_REG_SET_ADDR) = temp;
+
+	/* Set the GPIO direction as output */
+	temp = REG(GPIO_BANK2_REG_DIR_ADDR);
+	temp &= ~(0x01 << 6);
+	REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
+
+	return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+	/* Select RMII fucntion through the expander */
+	if (rmii_hw_init())
+		printf("RMII hardware init failed!!!\n");
+#endif
+	return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/roms/u-boot/board/davinci/da8xxevm/omapl138_lcdk.c b/roms/u-boot/board/davinci/da8xxevm/omapl138_lcdk.c
new file mode 100644
index 000000000..d5f43bf52
--- /dev/null
+++ b/roms/u-boot/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -0,0 +1,392 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da850evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch/hardware.h>
+#include <asm/global_data.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <dm/platdata.h>
+#include <linux/errno.h>
+#include <asm/mach-types.h>
+#include <asm/arch/davinci_misc.h>
+#ifdef CONFIG_MMC_DAVINCI
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
+
+#ifdef CONFIG_MMC_DAVINCI
+/* MMC0 pin muxer settings */
+const struct pinmux_config mmc0_pins[] = {
+	/* GP0[11] is required for SD to work on Rev 3 EVMs */
+	{ pinmux(0),  8, 4 },	/* GP0[11] */
+	{ pinmux(10), 2, 0 },	/* MMCSD0_CLK */
+	{ pinmux(10), 2, 1 },	/* MMCSD0_CMD */
+	{ pinmux(10), 2, 2 },	/* MMCSD0_DAT_0 */
+	{ pinmux(10), 2, 3 },	/* MMCSD0_DAT_1 */
+	{ pinmux(10), 2, 4 },	/* MMCSD0_DAT_2 */
+	{ pinmux(10), 2, 5 },	/* MMCSD0_DAT_3 */
+	/* LCDK supports only 4-bit mode, remaining pins are not configured */
+};
+#endif
+
+/* UART pin muxer settings */
+static const struct pinmux_config uart_pins[] = {
+	{ pinmux(0), 4, 6 },
+	{ pinmux(0), 4, 7 },
+	{ pinmux(4), 2, 4 },
+	{ pinmux(4), 2, 5 }
+};
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+static const struct pinmux_config emac_pins[] = {
+	{ pinmux(2), 8, 1 },
+	{ pinmux(2), 8, 2 },
+	{ pinmux(2), 8, 3 },
+	{ pinmux(2), 8, 4 },
+	{ pinmux(2), 8, 5 },
+	{ pinmux(2), 8, 6 },
+	{ pinmux(2), 8, 7 },
+	{ pinmux(3), 8, 0 },
+	{ pinmux(3), 8, 1 },
+	{ pinmux(3), 8, 2 },
+	{ pinmux(3), 8, 3 },
+	{ pinmux(3), 8, 4 },
+	{ pinmux(3), 8, 5 },
+	{ pinmux(3), 8, 6 },
+	{ pinmux(3), 8, 7 },
+	{ pinmux(4), 8, 0 },
+	{ pinmux(4), 8, 1 }
+};
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+/* I2C pin muxer settings */
+static const struct pinmux_config i2c_pins[] = {
+	{ pinmux(4), 2, 2 },
+	{ pinmux(4), 2, 3 }
+};
+
+#ifdef CONFIG_NAND_DAVINCI
+const struct pinmux_config nand_pins[] = {
+	{ pinmux(7), 1, 1 },
+	{ pinmux(7), 1, 2 },
+	{ pinmux(7), 1, 4 },
+	{ pinmux(7), 1, 5 },
+	{ pinmux(8), 1, 0 },
+	{ pinmux(8), 1, 1 },
+	{ pinmux(8), 1, 2 },
+	{ pinmux(8), 1, 3 },
+	{ pinmux(8), 1, 4 },
+	{ pinmux(8), 1, 5 },
+	{ pinmux(8), 1, 6 },
+	{ pinmux(8), 1, 7 },
+	{ pinmux(9), 1, 0 },
+	{ pinmux(9), 1, 1 },
+	{ pinmux(9), 1, 2 },
+	{ pinmux(9), 1, 3 },
+	{ pinmux(9), 1, 4 },
+	{ pinmux(9), 1, 5 },
+	{ pinmux(9), 1, 6 },
+	{ pinmux(9), 1, 7 },
+	{ pinmux(12), 1, 5 },
+	{ pinmux(12), 1, 6 }
+};
+
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define HAS_RMII 1
+#else
+#define HAS_RMII 0
+#endif
+
+const struct pinmux_resource pinmuxes[] = {
+	PINMUX_ITEM(uart_pins),
+	PINMUX_ITEM(i2c_pins),
+#ifdef CONFIG_NAND_DAVINCI
+	PINMUX_ITEM(nand_pins),
+#endif
+};
+
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
+const struct lpsc_resource lpsc[] = {
+	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
+	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
+	{ DAVINCI_LPSC_EMAC },	/* image download */
+	{ DAVINCI_LPSC_UART2 },	/* console */
+	{ DAVINCI_LPSC_GPIO },
+#ifdef CONFIG_MMC_DAVINCI
+	{ DAVINCI_LPSC_MMC_SD },
+#endif
+};
+
+const int lpsc_size = ARRAY_SIZE(lpsc);
+
+#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
+#define CONFIG_DA850_EVM_MAX_CPU_CLK	456000000
+#endif
+
+/*
+ * get_board_rev() - setup to pass kernel board revision information
+ * Returns:
+ * bit[0-3]	Maximum cpu clock rate supported by onboard SoC
+ *		0000b - 300 MHz
+ *		0001b - 372 MHz
+ *		0010b - 408 MHz
+ *		0011b - 456 MHz
+ */
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * Power on required peripherals
+	 * ARM does not have access by default to PSC0 and PSC1
+	 * assuming here that the DSP bootloader has set the IOPU
+	 * such that PSC access is available to ARM
+	 */
+	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+		return 1;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	irq_init();
+
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+
+	/* setup the SUSPSRC for ARM to control emulation suspend */
+	writel(readl(&davinci_syscfg_regs->suspsrc) &
+	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+		 DAVINCI_SYSCFG_SUSPSRC_UART2),
+	       &davinci_syscfg_regs->suspsrc);
+
+	/* configure pinmux settings */
+	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+		return 1;
+
+#ifdef CONFIG_NAND_DAVINCI
+	/*
+	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
+	 * Linux kernel @ 25MHz EMIFA
+	 */
+	writel((DAVINCI_ABCR_WSETUP(15) |
+		DAVINCI_ABCR_WSTROBE(63) |
+		DAVINCI_ABCR_WHOLD(7) |
+		DAVINCI_ABCR_RSETUP(15) |
+		DAVINCI_ABCR_RSTROBE(63) |
+		DAVINCI_ABCR_RHOLD(7) |
+		DAVINCI_ABCR_TA(3) |
+		DAVINCI_ABCR_ASIZE_16BIT),
+	       &davinci_emif_regs->ab2cr); /* CS3 */
+#endif
+
+
+#ifdef CONFIG_MMC_DAVINCI
+	if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
+		return 1;
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+	if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
+		return 1;
+	davinci_emac_mii_mode_sel(HAS_RMII);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+	/* enable the console UART */
+	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+		DAVINCI_UART_PWREMU_MGMT_UTRST),
+	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+	return 0;
+}
+
+#define CFG_MAC_ADDR_SPI_BUS	0
+#define CFG_MAC_ADDR_SPI_CS	0
+#define CFG_MAC_ADDR_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+#define CFG_MAC_ADDR_SPI_MODE	SPI_MODE_3
+
+#define CFG_MAC_ADDR_OFFSET	(flash->size - SZ_64K)
+
+static int  get_mac_addr(u8 *addr)
+{
+	/* Need to find a way to get MAC ADDRESS */
+	return 0;
+}
+
+void dsp_lpsc_on(unsigned domain, unsigned int id)
+{
+	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
+	struct davinci_psc_regs *psc_regs;
+
+	psc_regs = davinci_psc0_regs;
+	mdstat = &psc_regs->psc0.mdstat[id];
+	mdctl = &psc_regs->psc0.mdctl[id];
+	ptstat = &psc_regs->ptstat;
+	ptcmd = &psc_regs->ptcmd;
+
+	while (*ptstat & (0x1 << domain))
+		;
+
+	if ((*mdstat & 0x1f) == 0x03)
+		return;                 /* Already on and enabled */
+
+	*mdctl |= 0x03;
+
+	*ptcmd = 0x1 << domain;
+
+	while (*ptstat & (0x1 << domain))
+		;
+	while ((*mdstat & 0x1f) != 0x03)
+		;		/* Probably an overkill... */
+}
+
+static void dspwake(void)
+{
+	unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
+
+	/* if the device is ARM only, return */
+	if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10)
+		return;
+
+	if (!strcmp(env_get("dspwake"), "no"))
+		return;
+
+	*resetvect++ = 0x1E000; /* DSP Idle */
+	/* clear out the next 10 words as NOP */
+	memset(resetvect, 0, sizeof(unsigned) * 10);
+
+	/* setup the DSP reset vector */
+	REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE;
+
+	dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
+	REG(PSC0_MDCTL + (15 * 4)) |= 0x100;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+/**
+ * rmii_hw_init
+ *
+ */
+int rmii_hw_init(void)
+{
+	return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
+
+int misc_init_r(void)
+{
+	uint8_t tmp[20], addr[10];
+
+
+	if (env_get("ethaddr") == NULL) {
+		/* Read Ethernet MAC address from EEPROM */
+		if (dvevm_read_mac_address(addr)) {
+			/* Set Ethernet MAC address from EEPROM */
+			davinci_sync_env_enetaddr(addr);
+		} else {
+			get_mac_addr(addr);
+		}
+
+		if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
+			sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
+				addr[0], addr[1], addr[2], addr[3], addr[4],
+				addr[5]);
+
+			env_set("ethaddr", (char *)tmp);
+		} else {
+			printf("Invalid MAC address read.\n");
+		}
+	}
+
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+	/* Select RMII fucntion through the expander */
+	if (rmii_hw_init())
+		printf("RMII hardware init failed!!!\n");
+#endif
+
+	dspwake();
+
+	return 0;
+}
+
+#if !CONFIG_IS_ENABLED(DM_MMC)
+#ifdef CONFIG_MMC_DAVINCI
+static struct davinci_mmc mmc_sd0 = {
+	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+	.host_caps = MMC_MODE_4BIT,     /* DA850 supports only 4-bit SD/MMC */
+	.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
+
+	/* Add slot-0 to mmc subsystem */
+	return davinci_mmc_init(bis, &mmc_sd0);
+}
+#endif
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+static const struct ns16550_plat serial_pdata = {
+	.base = DAVINCI_UART2_BASE,
+	.reg_shift = 2,
+	.clock = 228000000,
+	.fcr = UART_FCR_DEFVAL,
+};
+
+U_BOOT_DRVINFO(omapl138_uart) = {
+	.name = "ns16550_serial",
+	.plat = &serial_pdata,
+};
+
+static const struct davinci_mmc_plat mmc_plat = {
+	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+	.cfg = {
+		.f_min = 200000,
+		.f_max = 25000000,
+		.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+		.host_caps = MMC_MODE_4BIT,
+		.b_max = DAVINCI_MAX_BLOCKS,
+		.name = "da830-mmc",
+	},
+};
+U_BOOT_DRVINFO(omapl138_mmc) = {
+	.name = "ti_da830_mmc",
+	.plat = &mmc_plat,
+};
+
+void spl_board_init(void)
+{
+	davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins));
+}
+#endif
diff --git a/roms/u-boot/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/roms/u-boot/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
new file mode 100644
index 000000000..8f0491130
--- /dev/null
+++ b/roms/u-boot/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ */
+
+MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
+
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+                LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	__start = .;
+	  *(.vectors)
+	  arch/arm/cpu/arm926ejs/start.o	(.text*)
+	  *(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	. = ALIGN(4);
+	.u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } >.sram
+
+	. = ALIGN(4);
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	} >.sram
+
+	__image_copy_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} >.sdram
+}
diff --git a/roms/u-boot/board/devboards/dbm-soc1/MAINTAINERS b/roms/u-boot/board/devboards/dbm-soc1/MAINTAINERS
new file mode 100644
index 000000000..625f2c889
--- /dev/null
+++ b/roms/u-boot/board/devboards/dbm-soc1/MAINTAINERS
@@ -0,0 +1,5 @@
+Devboards.de DBM-SoC1 BOARD
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+F:	include/configs/socfpga_dbm_soc1.h
+F:	configs/socfpga_dbm_soc1_defconfig
diff --git a/roms/u-boot/board/devboards/dbm-soc1/Makefile b/roms/u-boot/board/devboards/dbm-soc1/Makefile
new file mode 100644
index 000000000..88621b04c
--- /dev/null
+++ b/roms/u-boot/board/devboards/dbm-soc1/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Marek Vasut <marex@denx.de>
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/devboards/dbm-soc1/qts/iocsr_config.h b/roms/u-boot/board/devboards/dbm-soc1/qts/iocsr_config.h
new file mode 100644
index 000000000..99ed62bb5
--- /dev/null
+++ b/roms/u-boot/board/devboards/dbm-soc1/qts/iocsr_config.h
@@ -0,0 +1,659 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00004824,
+	0x01209000,
+	0x82400000,
+	0x00018004,
+	0x00000000,
+	0x00004000,
+	0x00002412,
+	0x00904800,
+	0x41200000,
+	0x80000002,
+	0x00000904,
+	0x00002000,
+	0x00001209,
+	0x00482400,
+	0x20900000,
+	0x40000001,
+	0x00000482,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00009048,
+	0x02412000,
+	0x048000C0,
+	0x00000009,
+	0x00002412,
+	0x00008000,
+	0x00004824,
+	0x01209000,
+	0x82400000,
+	0x00000004,
+	0x00001209,
+	0x00004000,
+	0x00002412,
+	0x00904800,
+	0x41200000,
+	0x80000002,
+	0x00000904,
+	0x00002000,
+	0x06001209,
+	0x00482400,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x80001000,
+	0x00000904,
+	0x00241200,
+	0x90480000,
+	0x20003000,
+	0x00000241,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x48240000,
+	0x90000000,
+	0x00000120,
+	0x00000400,
+	0x00000000,
+	0x00090480,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x90000200,
+	0x00600120,
+	0x00000000,
+	0x12090000,
+	0x24000600,
+	0x00000048,
+	0x48000100,
+	0x00300090,
+	0xC0024120,
+	0x09048000,
+	0x12000300,
+	0x000C0024,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x30009048,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x0C002412,
+	0x00008000,
+	0x18004824,
+	0x01209000,
+	0x82400060,
+	0x00018004,
+	0x06001209,
+	0x00004000,
+	0x00002412,
+	0x00904800,
+	0x00000030,
+	0x80000000,
+	0x03000904,
+	0x00002000,
+	0x00001209,
+	0x00482400,
+	0x20900000,
+	0x40000001,
+	0x00000482,
+	0x80001000,
+	0x00000904,
+	0x00000000,
+	0x90480000,
+	0x20000000,
+	0x00C00241,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x45034071,
+	0x0A281A01,
+	0x806180D0,
+	0x34071C06,
+	0x01A034D0,
+	0x180D0000,
+	0x71C06806,
+	0x01450340,
+	0xD000001A,
+	0x0680E380,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x45034071,
+	0x0A281A01,
+	0x806180D0,
+	0x34071C06,
+	0x01A00040,
+	0x180D0002,
+	0x71C06806,
+	0x01450340,
+	0xD00A281A,
+	0x06806180,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xCB2CA3DD,
+	0xF5D1451E,
+	0x034AD348,
+	0x821A0000,
+	0x0000D000,
+	0x030C0680,
+	0xDD59647A,
+	0x1ECB2CA3,
+	0x48F5D145,
+	0x00035AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8B2CA3DD,
+	0xF6D1451E,
+	0x035AD348,
+	0x821A0041,
+	0x0000D000,
+	0x00000680,
+	0xDD59647A,
+	0x1ECB2CA3,
+	0x48F6D145,
+	0x00035AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xCB2CA3D5,
+	0xF6D1451E,
+	0x035AB2C8,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDD59647A,
+	0x1ECB2CA3,
+	0x48F6D145,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x04864000,
+	0x69A47A01,
+	0x8B2CA3D5,
+	0xF6D1451E,
+	0x034A9248,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD569A47A,
+	0x1E8B2CA3,
+	0x48F6D145,
+	0x00034A92,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/devboards/dbm-soc1/qts/pinmux_config.h b/roms/u-boot/board/devboards/dbm-soc1/qts/pinmux_config.h
new file mode 100644
index 000000000..3f34b131f
--- /dev/null
+++ b/roms/u-boot/board/devboards/dbm-soc1/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	0, /* GENERALIO3 */
+	0, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	0, /* GENERALIO7 */
+	0, /* GENERALIO8 */
+	3, /* GENERALIO9 */
+	3, /* GENERALIO10 */
+	3, /* GENERALIO11 */
+	3, /* GENERALIO12 */
+	1, /* GENERALIO13 */
+	1, /* GENERALIO14 */
+	1, /* GENERALIO15 */
+	1, /* GENERALIO16 */
+	1, /* GENERALIO17 */
+	1, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/devboards/dbm-soc1/qts/pll_config.h b/roms/u-boot/board/devboards/dbm-soc1/qts/pll_config.h
new file mode 100644
index 000000000..f6ffa0865
--- /dev/null
+++ b/roms/u-boot/board/devboards/dbm-soc1/qts/pll_config.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/roms/u-boot/board/devboards/dbm-soc1/qts/sdram_config.h b/roms/u-boot/board/devboards/dbm-soc1/qts/sdram_config.h
new file mode 100644
index 000000000..2022969be
--- /dev/null
+++ b/roms/u-boot/board/devboards/dbm-soc1/qts/sdram_config.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			140
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	7
+#define CALIB_VFIFO_OFFSET	5
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x555504a1
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080421,
+	0x10080520,
+	0x10090044,
+	0x100a0008,
+	0x100b0000,
+	0x10380400,
+	0x10080441,
+	0x100804c0,
+	0x100a0024,
+	0x10090010,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/roms/u-boot/board/devboards/dbm-soc1/socfpga.c b/roms/u-boot/board/devboards/dbm-soc1/socfpga.c
new file mode 100644
index 000000000..a907ee605
--- /dev/null
+++ b/roms/u-boot/board/devboards/dbm-soc1/socfpga.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ */
+#include <common.h>
diff --git a/roms/u-boot/board/dfi/Kconfig b/roms/u-boot/board/dfi/Kconfig
new file mode 100644
index 000000000..267ac50a3
--- /dev/null
+++ b/roms/u-boot/board/dfi/Kconfig
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+
+if VENDOR_DFI
+
+choice
+	prompt "Mainboard model"
+
+config TARGET_Q7X_151_DFI_BT700
+	bool "DFI BT700 BayTrail on DFI Q7X-151 baseboard"
+	imply SCSI
+	help
+	  This is the DFI Q7X-151 baseboard equipped with the
+	  DFI BayTrail Bt700 SoM. It contains an Atom E3845 with
+	  Ethernet (in non-PCIe-x4 configuration), micro-SD, USB 2,
+	  USB 3, SATA, serial console and DisplayPort video out.
+	  It requires some binary blobs - see README.x86 for details.
+
+	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+	  by U-Boot matches that value.
+
+config TARGET_THEADORABLE_X86_DFI_BT700
+	bool "DFI BT700 BayTrail on theadorable-x86 baseboard"
+	imply SCSI
+	help
+	  This is the theadorable-x86 baseboard equipped with the
+	  DFI BayTrail Bt700 SoM. It contains an Atom E3845 with
+	  Ethernet (in non-PCIe-x4 configuration), micro-SD, USB 2,
+	  USB 3, SATA, serial console and DisplayPort video out.
+	  It requires some binary blobs - see README.x86 for details.
+
+	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+	  by U-Boot matches that value.
+
+endchoice
+
+source "board/dfi/dfi-bt700/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/dfi/dfi-bt700/Kconfig b/roms/u-boot/board/dfi/dfi-bt700/Kconfig
new file mode 100644
index 000000000..50c7b2a2f
--- /dev/null
+++ b/roms/u-boot/board/dfi/dfi-bt700/Kconfig
@@ -0,0 +1,30 @@
+config SYS_BOARD
+	default "dfi-bt700"
+
+config SYS_VENDOR
+	default "dfi"
+
+config SYS_SOC
+	default "baytrail"
+
+config SYS_CONFIG_NAME
+	default "dfi-bt700" if TARGET_Q7X_151_DFI_BT700
+	default "theadorable-x86-dfi-bt700" if TARGET_THEADORABLE_X86_DFI_BT700
+
+config SYS_TEXT_BASE
+	default 0xfff00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
+	select BOARD_LATE_INIT
+	select SPI_FLASH_STMICRO
+	imply SPI_FLASH_SPANSION
+	imply SPI_FLASH_WINBOND
+	select SERIAL_RX_BUFFER
+
+config PCIE_ECAM_BASE
+	default 0xe0000000
diff --git a/roms/u-boot/board/dfi/dfi-bt700/MAINTAINERS b/roms/u-boot/board/dfi/dfi-bt700/MAINTAINERS
new file mode 100644
index 000000000..a99a7250b
--- /dev/null
+++ b/roms/u-boot/board/dfi/dfi-bt700/MAINTAINERS
@@ -0,0 +1,11 @@
+congatec DFI-BT700
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/dfi/dfi-bt700
+F:	include/configs/dfi-bt700.h
+F:	include/configs/theadorable-x86-dfi-bt700.h
+F:	configs/dfi-bt700-q7x-151_defconfig
+F:	configs/theadorable-x86-dfi-bt700_defconfig
+F:	arch/x86/dts/dfi-bt700.dtsi
+F:	arch/x86/dts/dfi-bt700-q7x-151.dts
+F:	arch/x86/dts/theadorable-x86-dfi-bt700.dts
diff --git a/roms/u-boot/board/dfi/dfi-bt700/Makefile b/roms/u-boot/board/dfi/dfi-bt700/Makefile
new file mode 100644
index 000000000..50d88f295
--- /dev/null
+++ b/roms/u-boot/board/dfi/dfi-bt700/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Google, Inc
+
+obj-y	+= dfi-bt700.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/roms/u-boot/board/dfi/dfi-bt700/acpi/mainboard.asl b/roms/u-boot/board/dfi/dfi-bt700/acpi/mainboard.asl
new file mode 100644
index 000000000..4863fbf6d
--- /dev/null
+++ b/roms/u-boot/board/dfi/dfi-bt700/acpi/mainboard.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
+
+/* TODO: Need add Nuvoton SuperIO chipset NCT6102D ASL codes */
diff --git a/roms/u-boot/board/dfi/dfi-bt700/dfi-bt700.c b/roms/u-boot/board/dfi/dfi-bt700/dfi-bt700.c
new file mode 100644
index 000000000..87506a77a
--- /dev/null
+++ b/roms/u-boot/board/dfi/dfi-bt700/dfi-bt700.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <nuvoton_nct6102d.h>
+#include <asm/gpio.h>
+#include <asm/ibmpc.h>
+#include <asm/pnp_def.h>
+#include <linux/delay.h>
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_INTERNAL_UART
+	/* Disable the legacy UART which is enabled per default */
+	nct6102d_uarta_disable();
+#else
+	/*
+	 * The FSP enables the BayTrail internal legacy UART (again).
+	 * Disable it again, so that the Nuvoton one can be used.
+	 */
+	setup_internal_uart(0);
+#endif
+
+	/* Disable the watchdog which is enabled per default */
+	nct6102d_wdt_disable();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct gpio_desc desc;
+	int ret;
+
+	ret = dm_gpio_lookup_name("F10", &desc);
+	if (ret)
+		debug("gpio ret=%d\n", ret);
+	ret = dm_gpio_request(&desc, "xhci_hub_reset");
+	if (ret)
+		debug("gpio_request ret=%d\n", ret);
+	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	if (ret)
+		debug("gpio dir ret=%d\n", ret);
+
+	/* Pull xHCI hub reset to low (active low) */
+	dm_gpio_set_value(&desc, 0);
+
+	/* Wait at least 5 ms, so lets choose 10 to be safe */
+	mdelay(10);
+
+	/* Pull xHCI hub reset to high (active low) */
+	dm_gpio_set_value(&desc, 1);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/dfi/dfi-bt700/dsdt.asl b/roms/u-boot/board/dfi/dfi-bt700/dsdt.asl
new file mode 100644
index 000000000..d2297ef59
--- /dev/null
+++ b/roms/u-boot/board/dfi/dfi-bt700/dsdt.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/roms/u-boot/board/dhelectronics/dh_imx6/Kconfig b/roms/u-boot/board/dhelectronics/dh_imx6/Kconfig
new file mode 100644
index 000000000..0cfef9b09
--- /dev/null
+++ b/roms/u-boot/board/dhelectronics/dh_imx6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DHCOMIMX6
+
+config SYS_BOARD
+	default "dh_imx6"
+
+config SYS_VENDOR
+	default "dhelectronics"
+
+config SYS_CONFIG_NAME
+	default "dh_imx6"
+
+endif
diff --git a/roms/u-boot/board/dhelectronics/dh_imx6/MAINTAINERS b/roms/u-boot/board/dhelectronics/dh_imx6/MAINTAINERS
new file mode 100644
index 000000000..ab4e16bd5
--- /dev/null
+++ b/roms/u-boot/board/dhelectronics/dh_imx6/MAINTAINERS
@@ -0,0 +1,7 @@
+DH_IMX6 BOARD
+M:	Andreas Geisreiter <ageisreiter@dh-electronics.de>
+M:	Ludwig Zenz <lzenz@dh-electronics.de>
+S:	Maintained
+F:	board/dhelectronics/dh_imx6/
+F:	include/configs/dh_imx6.h
+F:	configs/dh_imx6_defconfig
diff --git a/roms/u-boot/board/dhelectronics/dh_imx6/Makefile b/roms/u-boot/board/dhelectronics/dh_imx6/Makefile
new file mode 100644
index 000000000..70ca30d39
--- /dev/null
+++ b/roms/u-boot/board/dhelectronics/dh_imx6/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Marek Vasut <marex@denx.de>
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= dh_imx6_spl.o
+else
+obj-y	:= dh_imx6.o
+endif
diff --git a/roms/u-boot/board/dhelectronics/dh_imx6/dh_imx6.c b/roms/u-boot/board/dhelectronics/dh_imx6/dh_imx6.c
new file mode 100644
index 000000000..2969e90a7
--- /dev/null
+++ b/roms/u-boot/board/dhelectronics/dh_imx6/dh_imx6.c
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DHCOM DH-iMX6 PDK board support
+ *
+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <eeprom.h>
+#include <image.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <ahci.h>
+#include <dwc_ahsata.h>
+#include <env.h>
+#include <errno.h>
+#include <fsl_esdhc_imx.h>
+#include <fuse.h>
+#include <i2c_eeprom.h>
+#include <mmc.h>
+#include <usb.h>
+#include <linux/delay.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+static int setup_fec_clock(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* set gpr1[21] to select anatop clock */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
+
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+static void setup_usb(void)
+{
+	/*
+	 * Set daisy chain for otg_pin_id on MX6Q.
+	 * For MX6DL, this bit is reserved.
+	 */
+	imx_iomux_set_gpr_register(1, 13, 1, 0);
+}
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return USB_INIT_DEVICE;
+}
+#endif
+
+static int setup_dhcom_mac_from_fuse(void)
+{
+	struct udevice *dev;
+	ofnode eeprom;
+	unsigned char enetaddr[6];
+	int ret;
+
+	ret = eth_env_get_enetaddr("ethaddr", enetaddr);
+	if (ret)	/* ethaddr is already set */
+		return 0;
+
+	imx_get_mac_from_fuse(0, enetaddr);
+
+	if (is_valid_ethaddr(enetaddr)) {
+		eth_env_set_enetaddr("ethaddr", enetaddr);
+		return 0;
+	}
+
+	eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50");
+	if (!ofnode_valid(eeprom)) {
+		printf("Invalid hardware path to EEPROM!\n");
+		return -ENODEV;
+	}
+
+	ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
+	if (ret) {
+		printf("Cannot find EEPROM!\n");
+		return ret;
+	}
+
+	ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
+	if (ret) {
+		printf("Error reading configuration EEPROM!\n");
+		return ret;
+	}
+
+	if (is_valid_ethaddr(enetaddr))
+		eth_env_set_enetaddr("ethaddr", enetaddr);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_USB_EHCI_MX6
+	setup_usb();
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* Enable eim_slow clocks */
+	setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
+
+	setup_fec_clock();
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+#define HW_CODE_BIT_0	IMX_GPIO_NR(2, 19)
+#define HW_CODE_BIT_1	IMX_GPIO_NR(6, 6)
+#define HW_CODE_BIT_2	IMX_GPIO_NR(2, 16)
+
+static int board_get_hwcode(void)
+{
+	int hw_code;
+
+	gpio_request(HW_CODE_BIT_0, "HW-code-bit-0");
+	gpio_request(HW_CODE_BIT_1, "HW-code-bit-1");
+	gpio_request(HW_CODE_BIT_2, "HW-code-bit-2");
+
+	gpio_direction_input(HW_CODE_BIT_0);
+	gpio_direction_input(HW_CODE_BIT_1);
+	gpio_direction_input(HW_CODE_BIT_2);
+
+	/* HW 100 + HW 200 = 00b; HW 300 = 01b */
+	hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
+		   (gpio_get_value(HW_CODE_BIT_1) << 1) |
+		    gpio_get_value(HW_CODE_BIT_0)) + 2;
+
+	return hw_code;
+}
+
+int board_late_init(void)
+{
+	u32 hw_code;
+	char buf[16];
+
+	setup_dhcom_mac_from_fuse();
+
+	hw_code = board_get_hwcode();
+
+	switch (get_cpu_type()) {
+	case MXC_CPU_MX6SOLO:
+		snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
+		break;
+	case MXC_CPU_MX6DL:
+		snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
+		break;
+	case MXC_CPU_MX6D:
+		snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
+		break;
+	case MXC_CPU_MX6Q:
+		snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
+		break;
+	default:
+		snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
+		break;
+	}
+
+	env_set("dhcom", buf);
+
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: DHCOM i.MX6\n");
+	return 0;
+}
+
+#ifdef CONFIG_MULTI_DTB_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_mx6dq()) {
+		if (!strcmp(name, "imx6q-dhcom-pdk2"))
+			return 0;
+	} else if (is_mx6sdl()) {
+		if (!strcmp(name, "imx6dl-dhcom-pdk2"))
+			return 0;
+	}
+
+	return -1;
+}
+#endif
diff --git a/roms/u-boot/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/roms/u-boot/board/dhelectronics/dh_imx6/dh_imx6_spl.c
new file mode 100644
index 000000000..e49e97724
--- /dev/null
+++ b/roms/u-boot/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -0,0 +1,644 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DHCOM DH-iMX6 PDK SPL support
+ *
+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <fuse.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <spl.h>
+#include <linux/delay.h>
+
+#define ENET_PAD_CTRL							\
+	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	 PAD_CTL_HYS)
+
+#define GPIO_PAD_CTRL							\
+	(PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define SPI_PAD_CTRL							\
+	(PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |		\
+	PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL							\
+	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	 PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL							\
+	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |	\
+	 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
+	.dram_sdclk_0	= 0x00020030,
+	.dram_sdclk_1	= 0x00020030,
+	.dram_cas	= 0x00020030,
+	.dram_ras	= 0x00020030,
+	.dram_reset	= 0x00020030,
+	.dram_sdcke0	= 0x00003000,
+	.dram_sdcke1	= 0x00003000,
+	.dram_sdba2	= 0x00000000,
+	.dram_sdodt0	= 0x00003030,
+	.dram_sdodt1	= 0x00003030,
+	.dram_sdqs0	= 0x00000030,
+	.dram_sdqs1	= 0x00000030,
+	.dram_sdqs2	= 0x00000030,
+	.dram_sdqs3	= 0x00000030,
+	.dram_sdqs4	= 0x00000030,
+	.dram_sdqs5	= 0x00000030,
+	.dram_sdqs6	= 0x00000030,
+	.dram_sdqs7	= 0x00000030,
+	.dram_dqm0	= 0x00020030,
+	.dram_dqm1	= 0x00020030,
+	.dram_dqm2	= 0x00020030,
+	.dram_dqm3	= 0x00020030,
+	.dram_dqm4	= 0x00020030,
+	.dram_dqm5	= 0x00020030,
+	.dram_dqm6	= 0x00020030,
+	.dram_dqm7	= 0x00020030,
+};
+
+static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
+	.grp_ddr_type	= 0x000C0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke	= 0x00000000,
+	.grp_addds	= 0x00000030,
+	.grp_ctlds	= 0x00000030,
+	.grp_ddrmode	= 0x00020000,
+	.grp_b0ds	= 0x00000030,
+	.grp_b1ds	= 0x00000030,
+	.grp_b2ds	= 0x00000030,
+	.grp_b3ds	= 0x00000030,
+	.grp_b4ds	= 0x00000030,
+	.grp_b5ds	= 0x00000030,
+	.grp_b6ds	= 0x00000030,
+	.grp_b7ds	= 0x00000030,
+};
+
+static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
+	.dram_sdclk_0	= 0x00020030,
+	.dram_sdclk_1	= 0x00020030,
+	.dram_cas	= 0x00020030,
+	.dram_ras	= 0x00020030,
+	.dram_reset	= 0x00020030,
+	.dram_sdcke0	= 0x00003000,
+	.dram_sdcke1	= 0x00003000,
+	.dram_sdba2	= 0x00000000,
+	.dram_sdodt0	= 0x00003030,
+	.dram_sdodt1	= 0x00003030,
+	.dram_sdqs0	= 0x00000030,
+	.dram_sdqs1	= 0x00000030,
+	.dram_sdqs2	= 0x00000030,
+	.dram_sdqs3	= 0x00000030,
+	.dram_sdqs4	= 0x00000030,
+	.dram_sdqs5	= 0x00000030,
+	.dram_sdqs6	= 0x00000030,
+	.dram_sdqs7	= 0x00000030,
+	.dram_dqm0	= 0x00020030,
+	.dram_dqm1	= 0x00020030,
+	.dram_dqm2	= 0x00020030,
+	.dram_dqm3	= 0x00020030,
+	.dram_dqm4	= 0x00020030,
+	.dram_dqm5	= 0x00020030,
+	.dram_dqm6	= 0x00020030,
+	.dram_dqm7	= 0x00020030,
+};
+
+static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
+	.grp_ddr_type	= 0x000C0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke	= 0x00000000,
+	.grp_addds	= 0x00000030,
+	.grp_ctlds	= 0x00000030,
+	.grp_ddrmode	= 0x00020000,
+	.grp_b0ds	= 0x00000030,
+	.grp_b1ds	= 0x00000030,
+	.grp_b2ds	= 0x00000030,
+	.grp_b3ds	= 0x00000030,
+	.grp_b4ds	= 0x00000030,
+	.grp_b5ds	= 0x00000030,
+	.grp_b6ds	= 0x00000030,
+	.grp_b7ds	= 0x00000030,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
+	.p0_mpwldectrl0	= 0x00150019,
+	.p0_mpwldectrl1	= 0x001C000B,
+	.p1_mpwldectrl0	= 0x00020018,
+	.p1_mpwldectrl1	= 0x0002000C,
+	.p0_mpdgctrl0	= 0x43140320,
+	.p0_mpdgctrl1	= 0x03080304,
+	.p1_mpdgctrl0	= 0x43180320,
+	.p1_mpdgctrl1	= 0x03100254,
+	.p0_mprddlctl	= 0x4830383C,
+	.p1_mprddlctl	= 0x3836323E,
+	.p0_mpwrdlctl	= 0x3E444642,
+	.p1_mpwrdlctl	= 0x42344442,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
+	.p0_mpwldectrl0	= 0x0040003C,
+	.p0_mpwldectrl1	= 0x0032003E,
+	.p0_mpdgctrl0	= 0x42350231,
+	.p0_mpdgctrl1	= 0x021A0218,
+	.p0_mprddlctl	= 0x4B4B4E49,
+	.p0_mpwrdlctl	= 0x3F3F3035,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
+	.p0_mpwldectrl0	= 0x001a001a,
+	.p0_mpwldectrl1	= 0x00260015,
+	.p0_mpdgctrl0	= 0x030c0320,
+	.p0_mpdgctrl1	= 0x03100304,
+	.p0_mprddlctl	= 0x432e3538,
+	.p0_mpwrdlctl	= 0x363f423d,
+	.p1_mpwldectrl0	= 0x0006001e,
+	.p1_mpwldectrl1	= 0x00050015,
+	.p1_mpdgctrl0	= 0x031c0324,
+	.p1_mpdgctrl1	= 0x030c0258,
+	.p1_mprddlctl	= 0x3834313f,
+	.p1_mpwrdlctl	= 0x47374a42,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
+	.p0_mpwldectrl0	= 0x003A003A,
+	.p0_mpwldectrl1	= 0x0030002F,
+	.p1_mpwldectrl0	= 0x002F0038,
+	.p1_mpwldectrl1	= 0x00270039,
+	.p0_mpdgctrl0	= 0x420F020F,
+	.p0_mpdgctrl1	= 0x01760175,
+	.p1_mpdgctrl0	= 0x41640171,
+	.p1_mpdgctrl1	= 0x015E0160,
+	.p0_mprddlctl	= 0x45464B4A,
+	.p1_mprddlctl	= 0x49484A46,
+	.p0_mpwrdlctl	= 0x40402E32,
+	.p1_mpwrdlctl	= 0x3A3A3231,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
+	.p0_mpwldectrl0	= 0x0040003C,
+	.p0_mpwldectrl1	= 0x0032003E,
+	.p0_mpdgctrl0	= 0x42350231,
+	.p0_mpdgctrl1	= 0x021A0218,
+	.p0_mprddlctl	= 0x4B4B4E49,
+	.p0_mpwrdlctl	= 0x3F3F3035,
+};
+
+/*
+ * 2 Gbit DDR3 memory
+ *   - NANYA #NT5CC128M16IP-DII
+ *   - NANYA #NT5CB128M16FP-DII
+ */
+static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
+	.mem_speed	= 1600,
+	.density	= 2,
+	.width		= 16,
+	.banks		= 8,
+	.rowaddr	= 14,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1375,
+	.trcmin		= 5863,
+	.trasmin	= 3750,
+};
+
+/*
+ * 4 Gbit DDR3 memory
+ *   - Intelligent Memory #IM4G16D3EABG-125I
+ */
+static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
+	.mem_speed	= 1600,
+	.density	= 4,
+	.width		= 16,
+	.banks		= 8,
+	.rowaddr	= 15,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1375,
+	.trcmin		= 4875,
+	.trasmin	= 3500,
+};
+
+/* DDR3 64bit */
+static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
+	/* width of data bus:0=16,1=32,2=64 */
+	.dsize		= 2,
+	.cs_density	= 32,
+	.ncs		= 1,	/* single chip select */
+	.cs1_mirror	= 1,
+	.rtt_wr		= 1,	/* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
+	.rtt_nom	= 1,	/* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
+	.walat		= 1,	/* Write additional latency */
+	.ralat		= 5,	/* Read additional latency */
+	.mif3_mode	= 3,	/* Command prediction working mode */
+	.bi_on		= 1,	/* Bank interleaving enabled */
+	.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.refsel		= 1,	/* Refresh cycles at 32KHz */
+	.refr		= 3,	/* 4 refresh commands per refresh cycle */
+};
+
+/* DDR3 32bit */
+static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
+	/* width of data bus:0=16,1=32,2=64 */
+	.dsize		= 1,
+	.cs_density	= 32,
+	.ncs		= 1,	/* single chip select */
+	.cs1_mirror	= 1,
+	.rtt_wr		= 1,	/* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
+	.rtt_nom	= 1,	/* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
+	.walat		= 1,	/* Write additional latency */
+	.ralat		= 5,	/* Read additional latency */
+	.mif3_mode	= 3,	/* Command prediction working mode */
+	.bi_on		= 1,	/* Bank interleaving enabled */
+	.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.refsel		= 1,	/* Refresh cycles at 32KHz */
+	.refr		= 3,	/* 4 refresh commands per refresh cycle */
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+/* Board ID */
+static iomux_v3_cfg_t const hwcode_pads[] = {
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+};
+
+static void setup_iomux_boardid(void)
+{
+	/* HW code pins: Setup alternate function and configure pads */
+	SETUP_IOMUX_PADS(hwcode_pads);
+}
+
+/* DDR Code */
+static iomux_v3_cfg_t const ddrcode_pads[] = {
+	IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+};
+
+static void setup_iomux_ddrcode(void)
+{
+	/* ddr code pins */
+	SETUP_IOMUX_PADS(ddrcode_pads);
+}
+
+enum dhcom_ddr3_code {
+	DH_DDR3_SIZE_256MIB = 0x00,
+	DH_DDR3_SIZE_512MIB = 0x01,
+	DH_DDR3_SIZE_1GIB   = 0x02,
+	DH_DDR3_SIZE_2GIB   = 0x03
+};
+
+#define DDR3_CODE_BIT_0   IMX_GPIO_NR(2, 22)
+#define DDR3_CODE_BIT_1   IMX_GPIO_NR(2, 21)
+
+enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
+{
+	enum dhcom_ddr3_code ddr3_code;
+
+	gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
+	gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
+
+	gpio_direction_input(DDR3_CODE_BIT_0);
+	gpio_direction_input(DDR3_CODE_BIT_1);
+
+	/* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
+	ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
+	     | (!!gpio_get_value(DDR3_CODE_BIT_0));
+
+	return ddr3_code;
+}
+
+/* GPIO */
+static iomux_v3_cfg_t const gpio_pads[] = {
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+};
+
+static void setup_iomux_gpio(void)
+{
+	SETUP_IOMUX_PADS(gpio_pads);
+}
+
+/* Ethernet */
+static iomux_v3_cfg_t const enet_pads[] = {
+	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	/* SMSC PHY Reset */
+	IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* ENET_VIO_GPIO */
+	IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* ENET_Interrupt - (not used) */
+	IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_enet(void)
+{
+	SETUP_IOMUX_PADS(enet_pads);
+}
+
+/* SD interface */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+/* onboard microSD */
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+/* eMMC */
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+/* SD */
+static void setup_iomux_sd(void)
+{
+	SETUP_IOMUX_PADS(usdhc2_pads);
+	SETUP_IOMUX_PADS(usdhc3_pads);
+	SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+/* SPI */
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	/* SS0 - SS of boot flash */
+	IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30	|
+		MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
+	/* SS2 - SS of DHCOM SPI1 */
+	IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11	|
+		MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
+
+	IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO	| MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI	| MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK	| MUX_PAD_CTRL(SPI_PAD_CTRL)),
+};
+
+static void setup_iomux_spi(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	if (bus == 0 && cs == 0)
+		return IMX_GPIO_NR(2, 30);
+	else
+		return -1;
+}
+
+/* UART */
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA	| MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA	| MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+#ifdef CONFIG_FSL_USDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC4_BASE_ADDR},
+};
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno - 1;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1; /* eMMC/uSDHC4 is always present */
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	SETUP_IOMUX_PADS(usdhc4_pads);
+	usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+	usdhc_cfg[0].max_bus_width = 8;
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+/* USB */
+static iomux_v3_cfg_t const usb_pads[] = {
+	IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_usb(void)
+{
+	SETUP_IOMUX_PADS(usb_pads);
+}
+
+/* Perform DDR DRAM calibration */
+static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+	int ret = 0;
+
+#ifdef CONFIG_MX6_DDRCAL
+	udelay(100);
+	ret = mmdc_do_write_level_calibration(sysinfo);
+	if (ret) {
+		printf("DDR3: Write level calibration error [%d]\n", ret);
+		return ret;
+	}
+
+	ret = mmdc_do_dqs_calibration(sysinfo);
+	if (ret) {
+		printf("DDR3: DQS calibration error [%d]\n", ret);
+		return ret;
+	}
+#endif /* CONFIG_MX6_DDRCAL */
+
+	return ret;
+}
+
+
+/* DRAM */
+static void dhcom_spl_dram_init(void)
+{
+	enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
+
+	if (is_mx6dq()) {
+		mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
+					&dhcom6dq_grp_ioregs);
+		switch (ddr3_code) {
+		default:
+			printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
+			printf("        choosing 1024 MB\n");
+			/* fall through */
+		case DH_DDR3_SIZE_1GIB:
+			mx6_dram_cfg(&dhcom_ddr_64bit,
+				     &dhcom_mmdc_calib_4x2g_1066,
+				     &dhcom_mem_ddr_2g);
+			break;
+		case DH_DDR3_SIZE_2GIB:
+			mx6_dram_cfg(&dhcom_ddr_64bit,
+				     &dhcom_mmdc_calib_4x4g_1066,
+				     &dhcom_mem_ddr_4g);
+			break;
+		}
+
+		/* Perform DDR DRAM calibration */
+		spl_dram_perform_cal(&dhcom_ddr_64bit);
+
+	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
+		mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
+					  &dhcom6sdl_grp_ioregs);
+		switch (ddr3_code) {
+		default:
+			printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
+			printf("        choosing 1024 MB\n");
+			/* fall through */
+		case DH_DDR3_SIZE_1GIB:
+			mx6_dram_cfg(&dhcom_ddr_64bit,
+				     &dhcom_mmdc_calib_4x2g_800,
+				     &dhcom_mem_ddr_2g);
+			break;
+		}
+
+		/* Perform DDR DRAM calibration */
+		spl_dram_perform_cal(&dhcom_ddr_64bit);
+
+	} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+		mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
+					  &dhcom6sdl_grp_ioregs);
+		switch (ddr3_code) {
+		default:
+			printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
+			printf("       choosing 512 MB\n");
+			/* fall through */
+		case DH_DDR3_SIZE_512MIB:
+			mx6_dram_cfg(&dhcom_ddr_32bit,
+				     &dhcom_mmdc_calib_2x2g_800,
+				     &dhcom_mem_ddr_2g);
+			break;
+		case DH_DDR3_SIZE_1GIB:
+			mx6_dram_cfg(&dhcom_ddr_32bit,
+				     &dhcom_mmdc_calib_2x4g_800,
+				     &dhcom_mem_ddr_4g);
+			break;
+		}
+
+		/* Perform DDR DRAM calibration */
+		spl_dram_perform_cal(&dhcom_ddr_32bit);
+	}
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+	setup_iomux_boardid();
+	setup_iomux_ddrcode();
+	setup_iomux_gpio();
+	setup_iomux_enet();
+	setup_iomux_sd();
+	setup_iomux_spi();
+	setup_iomux_uart();
+	setup_iomux_usb();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR3 initialization */
+	dhcom_spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/dhelectronics/dh_stm32mp1/Kconfig b/roms/u-boot/board/dhelectronics/dh_stm32mp1/Kconfig
new file mode 100644
index 000000000..1fc792c9d
--- /dev/null
+++ b/roms/u-boot/board/dhelectronics/dh_stm32mp1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_DH_STM32MP1_PDK2
+
+config SYS_BOARD
+	default "dh_stm32mp1"
+
+config SYS_VENDOR
+	default "dhelectronics"
+
+config SYS_CONFIG_NAME
+	default "dh_stm32mp1"
+
+config ENV_SECT_SIZE
+	default 0x10000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+	default 0x1E0000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET_REDUND
+	default 0x1F0000 if ENV_IS_IN_SPI_FLASH
+
+source "board/st/common/Kconfig"
+endif
diff --git a/roms/u-boot/board/dhelectronics/dh_stm32mp1/MAINTAINERS b/roms/u-boot/board/dhelectronics/dh_stm32mp1/MAINTAINERS
new file mode 100644
index 000000000..9ce21c3ab
--- /dev/null
+++ b/roms/u-boot/board/dhelectronics/dh_stm32mp1/MAINTAINERS
@@ -0,0 +1,9 @@
+DH_STM32MP1_PDK2 BOARD
+M:	Marek Vasut <marex@denx.de>
+L:	u-boot@dh-electronics.com
+S:	Maintained
+F:	arch/arm/dts/stm32mp15xx-dhcom*
+F:	board/dhelectronics/dh_stm32mp1/
+F:	configs/stm32mp15_dhcom_basic_defconfig
+F:	configs/stm32mp15_dhcor_basic_defconfig
+F:	include/configs/stm32mp1.h
diff --git a/roms/u-boot/board/dhelectronics/dh_stm32mp1/Makefile b/roms/u-boot/board/dhelectronics/dh_stm32mp1/Makefile
new file mode 100644
index 000000000..b368b396a
--- /dev/null
+++ b/roms/u-boot/board/dhelectronics/dh_stm32mp1/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+
+obj-y += ../../st/common/stpmic1.o board.o
+
+obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += ../../st/common/stm32mp_mtdparts.o
+obj-$(CONFIG_SET_DFU_ALT_INFO) += ../../st/common/stm32mp_dfu.o
diff --git a/roms/u-boot/board/dhelectronics/dh_stm32mp1/board.c b/roms/u-boot/board/dhelectronics/dh_stm32mp1/board.c
new file mode 100644
index 000000000..ac1af718d
--- /dev/null
+++ b/roms/u-boot/board/dhelectronics/dh_stm32mp1/board.c
@@ -0,0 +1,751 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <adc.h>
+#include <log.h>
+#include <net.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <bootm.h>
+#include <clk.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <env_internal.h>
+#include <g_dnl.h>
+#include <generic-phy.h>
+#include <hang.h>
+#include <i2c.h>
+#include <i2c_eeprom.h>
+#include <init.h>
+#include <led.h>
+#include <memalign.h>
+#include <misc.h>
+#include <mtd.h>
+#include <mtd_node.h>
+#include <netdev.h>
+#include <phy.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+#include <remoteproc.h>
+#include <reset.h>
+#include <syscon.h>
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+#include <watchdog.h>
+#include "../../st/common/stpmic1.h"
+
+/* SYSCFG registers */
+#define SYSCFG_BOOTR		0x00
+#define SYSCFG_PMCSETR		0x04
+#define SYSCFG_IOCTRLSETR	0x18
+#define SYSCFG_ICNR		0x1C
+#define SYSCFG_CMPCR		0x20
+#define SYSCFG_CMPENSETR	0x24
+#define SYSCFG_PMCCLRR		0x44
+
+#define SYSCFG_BOOTR_BOOT_MASK		GENMASK(2, 0)
+#define SYSCFG_BOOTR_BOOTPD_SHIFT	4
+
+#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE		BIT(0)
+#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI	BIT(1)
+#define SYSCFG_IOCTRLSETR_HSLVEN_ETH		BIT(2)
+#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC		BIT(3)
+#define SYSCFG_IOCTRLSETR_HSLVEN_SPI		BIT(4)
+
+#define SYSCFG_CMPCR_SW_CTRL		BIT(1)
+#define SYSCFG_CMPCR_READY		BIT(8)
+
+#define SYSCFG_CMPENSETR_MPU_EN		BIT(0)
+
+#define SYSCFG_PMCSETR_ETH_CLK_SEL	BIT(16)
+#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL	BIT(17)
+
+#define SYSCFG_PMCSETR_ETH_SELMII	BIT(20)
+
+#define SYSCFG_PMCSETR_ETH_SEL_MASK	GENMASK(23, 21)
+#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII	0
+#define SYSCFG_PMCSETR_ETH_SEL_RGMII	BIT(21)
+#define SYSCFG_PMCSETR_ETH_SEL_RMII	BIT(23)
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+#define KS_CCR		0x08
+#define KS_CCR_EEPROM	BIT(9)
+#define KS_BE0		BIT(12)
+#define KS_BE1		BIT(13)
+#define KS_CIDER	0xC0
+#define CIDER_ID	0x8870
+
+int setup_mac_address(void)
+{
+	unsigned char enetaddr[6];
+	bool skip_eth0 = false;
+	bool skip_eth1 = false;
+	struct udevice *dev;
+	int off, ret;
+
+	ret = eth_env_get_enetaddr("ethaddr", enetaddr);
+	if (ret)	/* ethaddr is already set */
+		skip_eth0 = true;
+
+	off = fdt_path_offset(gd->fdt_blob, "ethernet1");
+	if (off < 0) {
+		/* ethernet1 is not present in the system */
+		skip_eth1 = true;
+		goto out_set_ethaddr;
+	}
+
+	ret = eth_env_get_enetaddr("eth1addr", enetaddr);
+	if (ret) {
+		/* eth1addr is already set */
+		skip_eth1 = true;
+		goto out_set_ethaddr;
+	}
+
+	ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll");
+	if (ret)
+		goto out_set_ethaddr;
+
+	/*
+	 * KS8851 with EEPROM may use custom MAC from EEPROM, read
+	 * out the KS8851 CCR register to determine whether EEPROM
+	 * is present. If EEPROM is present, it must contain valid
+	 * MAC address.
+	 */
+	u32 reg, cider, ccr;
+	reg = fdt_get_base_address(gd->fdt_blob, off);
+	if (!reg)
+		goto out_set_ethaddr;
+
+	writew(KS_BE0 | KS_BE1 | KS_CIDER, reg + 2);
+	cider = readw(reg);
+	if ((cider & 0xfff0) != CIDER_ID) {
+		skip_eth1 = true;
+		goto out_set_ethaddr;
+	}
+
+	writew(KS_BE0 | KS_BE1 | KS_CCR, reg + 2);
+	ccr = readw(reg);
+	if (ccr & KS_CCR_EEPROM) {
+		skip_eth1 = true;
+		goto out_set_ethaddr;
+	}
+
+out_set_ethaddr:
+	if (skip_eth0 && skip_eth1)
+		return 0;
+
+	off = fdt_path_offset(gd->fdt_blob, "eeprom0");
+	if (off < 0) {
+		printf("%s: No eeprom0 path offset\n", __func__);
+		return off;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+	if (ret) {
+		printf("Cannot find EEPROM!\n");
+		return ret;
+	}
+
+	ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
+	if (ret) {
+		printf("Error reading configuration EEPROM!\n");
+		return ret;
+	}
+
+	if (is_valid_ethaddr(enetaddr)) {
+		if (!skip_eth0)
+			eth_env_set_enetaddr("ethaddr", enetaddr);
+
+		enetaddr[5]++;
+		if (!skip_eth1)
+			eth_env_set_enetaddr("eth1addr", enetaddr);
+	}
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *mode;
+	const char *fdt_compat;
+	int fdt_compat_len;
+
+	if (IS_ENABLED(CONFIG_TFABOOT))
+		mode = "trusted";
+	else
+		mode = "basic";
+
+	printf("Board: stm32mp1 in %s mode", mode);
+	fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
+				 &fdt_compat_len);
+	if (fdt_compat && fdt_compat_len)
+		printf(" (%s)", fdt_compat);
+	puts("\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+static u8 brdcode __section("data");
+static u8 ddr3code __section("data");
+static u8 somcode __section("data");
+static u32 opp_voltage_mv __section(".data");
+
+static void board_get_coding_straps(void)
+{
+	struct gpio_desc gpio[4];
+	ofnode node;
+	int i, ret;
+
+	node = ofnode_path("/config");
+	if (!ofnode_valid(node)) {
+		printf("%s: no /config node?\n", __func__);
+		return;
+	}
+
+	brdcode = 0;
+	ddr3code = 0;
+	somcode = 0;
+
+	ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
+					      gpio, ARRAY_SIZE(gpio),
+					      GPIOD_IS_IN);
+	for (i = 0; i < ret; i++)
+		somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
+	ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
+					      gpio, ARRAY_SIZE(gpio),
+					      GPIOD_IS_IN);
+	for (i = 0; i < ret; i++)
+		ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
+	ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
+					      gpio, ARRAY_SIZE(gpio),
+					      GPIOD_IS_IN);
+	for (i = 0; i < ret; i++)
+		brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
+	printf("Code:  SoM:rev=%d,ddr3=%d Board:rev=%d\n",
+		somcode, ddr3code, brdcode);
+}
+
+int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
+					 const char *name)
+{
+	if (ddr3code == 1 &&
+	    !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
+		return 0;
+
+	if (ddr3code == 2 &&
+	    !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
+		return 0;
+
+	if (ddr3code == 3 &&
+	    !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
+		return 0;
+
+	return -EINVAL;
+}
+
+void board_vddcore_init(u32 voltage_mv)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		opp_voltage_mv = voltage_mv;
+}
+
+int board_early_init_f(void)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		stpmic1_init(opp_voltage_mv);
+	board_get_coding_straps();
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	const char *compat;
+	char test[128];
+
+	compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
+
+	snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
+		compat, somcode, brdcode);
+
+	if (!strcmp(name, test))
+		return 0;
+
+	return -EINVAL;
+}
+#endif
+#endif
+
+static void board_key_check(void)
+{
+#if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
+	ofnode node;
+	struct gpio_desc gpio;
+	enum forced_boot_mode boot_mode = BOOT_NORMAL;
+
+	node = ofnode_path("/config");
+	if (!ofnode_valid(node)) {
+		debug("%s: no /config node?\n", __func__);
+		return;
+	}
+#ifdef CONFIG_FASTBOOT
+	if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
+				       &gpio, GPIOD_IS_IN)) {
+		debug("%s: could not find a /config/st,fastboot-gpios\n",
+		      __func__);
+	} else {
+		if (dm_gpio_get_value(&gpio)) {
+			puts("Fastboot key pressed, ");
+			boot_mode = BOOT_FASTBOOT;
+		}
+
+		dm_gpio_free(NULL, &gpio);
+	}
+#endif
+#ifdef CONFIG_CMD_STM32PROG
+	if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
+				       &gpio, GPIOD_IS_IN)) {
+		debug("%s: could not find a /config/st,stm32prog-gpios\n",
+		      __func__);
+	} else {
+		if (dm_gpio_get_value(&gpio)) {
+			puts("STM32Programmer key pressed, ");
+			boot_mode = BOOT_STM32PROG;
+		}
+		dm_gpio_free(NULL, &gpio);
+	}
+#endif
+
+	if (boot_mode != BOOT_NORMAL) {
+		puts("entering download mode...\n");
+		clrsetbits_le32(TAMP_BOOT_CONTEXT,
+				TAMP_BOOT_FORCED_MASK,
+				boot_mode);
+	}
+#endif
+}
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+
+#include <usb/dwc2_udc.h>
+int g_dnl_board_usb_cable_connected(void)
+{
+	struct udevice *dwc2_udc_otg;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
+					  DM_DRIVER_GET(dwc2_udc_otg),
+					  &dwc2_udc_otg);
+	if (!ret)
+		debug("dwc2_udc_otg init failed\n");
+
+	return dwc2_udc_B_session_valid(dwc2_udc_otg);
+}
+
+#define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
+#define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	if (!strcmp(name, "usb_dnl_dfu"))
+		put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
+	else if (!strcmp(name, "usb_dnl_fastboot"))
+		put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
+			      &dev->idProduct);
+	else
+		put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
+
+	return 0;
+}
+
+#endif /* CONFIG_USB_GADGET */
+
+#ifdef CONFIG_LED
+static int get_led(struct udevice **dev, char *led_string)
+{
+	char *led_name;
+	int ret;
+
+	led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
+	if (!led_name) {
+		pr_debug("%s: could not find %s config string\n",
+			 __func__, led_string);
+		return -ENOENT;
+	}
+	ret = led_get_by_label(led_name, dev);
+	if (ret) {
+		debug("%s: get=%d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int setup_led(enum led_state_t cmd)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = get_led(&dev, "u-boot,boot-led");
+	if (ret)
+		return ret;
+
+	ret = led_set_state(dev, cmd);
+	return ret;
+}
+#endif
+
+static void __maybe_unused led_error_blink(u32 nb_blink)
+{
+#ifdef CONFIG_LED
+	int ret;
+	struct udevice *led;
+	u32 i;
+#endif
+
+	if (!nb_blink)
+		return;
+
+#ifdef CONFIG_LED
+	ret = get_led(&led, "u-boot,error-led");
+	if (!ret) {
+		/* make u-boot,error-led blinking */
+		/* if U32_MAX and 125ms interval, for 17.02 years */
+		for (i = 0; i < 2 * nb_blink; i++) {
+			led_set_state(led, LEDST_TOGGLE);
+			mdelay(125);
+			WATCHDOG_RESET();
+		}
+	}
+#endif
+
+	/* infinite: the boot process must be stopped */
+	if (nb_blink == U32_MAX)
+		hang();
+}
+
+static void sysconf_init(void)
+{
+#ifndef CONFIG_TFABOOT
+	u8 *syscfg;
+#ifdef CONFIG_DM_REGULATOR
+	struct udevice *pwr_dev;
+	struct udevice *pwr_reg;
+	struct udevice *dev;
+	int ret;
+	u32 otp = 0;
+#endif
+	u32 bootr;
+
+	syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+
+	/* interconnect update : select master using the port 1 */
+	/* LTDC = AXI_M9 */
+	/* GPU  = AXI_M8 */
+	/* today information is hardcoded in U-Boot */
+	writel(BIT(9), syscfg + SYSCFG_ICNR);
+
+	/* disable Pull-Down for boot pin connected to VDD */
+	bootr = readl(syscfg + SYSCFG_BOOTR);
+	bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
+	bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
+	writel(bootr, syscfg + SYSCFG_BOOTR);
+
+#ifdef CONFIG_DM_REGULATOR
+	/* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
+	 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
+	 * The customer will have to disable this for low frequencies
+	 * or if AFMUX is selected but the function not used, typically for
+	 * TRACE. Otherwise, impact on power consumption.
+	 *
+	 * WARNING:
+	 *   enabling High Speed mode while VDD>2.7V
+	 *   with the OTP product_below_2v5 (OTP 18, BIT 13)
+	 *   erroneously set to 1 can damage the IC!
+	 *   => U-Boot set the register only if VDD < 2.7V (in DT)
+	 *      but this value need to be consistent with board design
+	 */
+	ret = uclass_get_device_by_driver(UCLASS_PMIC,
+					  DM_DRIVER_GET(stm32mp_pwr_pmic),
+					  &pwr_dev);
+	if (!ret) {
+		ret = uclass_get_device_by_driver(UCLASS_MISC,
+						  DM_DRIVER_GET(stm32mp_bsec),
+						  &dev);
+		if (ret) {
+			pr_err("Can't find stm32mp_bsec driver\n");
+			return;
+		}
+
+		ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
+		if (ret > 0)
+			otp = otp & BIT(13);
+
+		/* get VDD = vdd-supply */
+		ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
+						  &pwr_reg);
+
+		/* check if VDD is Low Voltage */
+		if (!ret) {
+			if (regulator_get_value(pwr_reg) < 2700000) {
+				writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
+				       SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
+				       SYSCFG_IOCTRLSETR_HSLVEN_ETH |
+				       SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
+				       SYSCFG_IOCTRLSETR_HSLVEN_SPI,
+				       syscfg + SYSCFG_IOCTRLSETR);
+
+				if (!otp)
+					pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
+			} else {
+				if (otp)
+					pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
+			}
+		} else {
+			debug("VDD unknown");
+		}
+	}
+#endif
+
+	/* activate automatic I/O compensation
+	 * warning: need to ensure CSI enabled and ready in clock driver
+	 */
+	writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
+
+	while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
+		;
+	clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+#endif
+}
+
+static void board_init_fmc2(void)
+{
+#define STM32_FMC2_BCR1			0x0
+#define STM32_FMC2_BTR1			0x4
+#define STM32_FMC2_BWTR1		0x104
+#define STM32_FMC2_BCR(x)		((x) * 0x8 + STM32_FMC2_BCR1)
+#define STM32_FMC2_BCRx_FMCEN		BIT(31)
+#define STM32_FMC2_BCRx_WREN		BIT(12)
+#define STM32_FMC2_BCRx_RSVD		BIT(7)
+#define STM32_FMC2_BCRx_FACCEN		BIT(6)
+#define STM32_FMC2_BCRx_MWID(n)		((n) << 4)
+#define STM32_FMC2_BCRx_MTYP(n)		((n) << 2)
+#define STM32_FMC2_BCRx_MUXEN		BIT(1)
+#define STM32_FMC2_BCRx_MBKEN		BIT(0)
+#define STM32_FMC2_BTR(x)		((x) * 0x8 + STM32_FMC2_BTR1)
+#define STM32_FMC2_BTRx_DATAHLD(n)	((n) << 30)
+#define STM32_FMC2_BTRx_BUSTURN(n)	((n) << 16)
+#define STM32_FMC2_BTRx_DATAST(n)	((n) << 8)
+#define STM32_FMC2_BTRx_ADDHLD(n)	((n) << 4)
+#define STM32_FMC2_BTRx_ADDSET(n)	((n) << 0)
+
+#define RCC_MP_AHB6RSTCLRR		0x218
+#define RCC_MP_AHB6RSTCLRR_FMCRST	BIT(12)
+#define RCC_MP_AHB6ENSETR		0x19c
+#define RCC_MP_AHB6ENSETR_FMCEN		BIT(12)
+
+	const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
+			STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
+			STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
+			STM32_FMC2_BCRx_MBKEN;
+	const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
+			STM32_FMC2_BTRx_BUSTURN(2) |
+			STM32_FMC2_BTRx_DATAST(0x22) |
+			STM32_FMC2_BTRx_ADDHLD(2) |
+			STM32_FMC2_BTRx_ADDSET(2);
+
+	/* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
+	writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
+	writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
+
+	/* KS8851-16MLL -- Muxed mode */
+	writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
+	writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
+	/* AS7C34098 SRAM on X11 -- Muxed mode */
+	writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
+	writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
+
+	setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
+}
+
+/* board dependent setup after realloc */
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
+
+	if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
+		gpio_hog_probe_all();
+
+	board_key_check();
+
+#ifdef CONFIG_DM_REGULATOR
+	regulators_enable_boot_on(_DEBUG);
+#endif
+
+	sysconf_init();
+
+	board_init_fmc2();
+
+	if (CONFIG_IS_ENABLED(LED))
+		led_default_state();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	char *boot_device;
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	const void *fdt_compat;
+	int fdt_compat_len;
+
+	fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
+				 &fdt_compat_len);
+	if (fdt_compat && fdt_compat_len) {
+		if (strncmp(fdt_compat, "st,", 3) != 0)
+			env_set("board_name", fdt_compat);
+		else
+			env_set("board_name", fdt_compat + 3);
+	}
+#endif
+
+	/* Check the boot-source to disable bootdelay */
+	boot_device = env_get("boot_device");
+	if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
+		env_set("bootdelay", "0");
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+	env_set_ulong("dh_som_rev", somcode);
+	env_set_ulong("dh_board_rev", brdcode);
+	env_set_ulong("dh_ddr3_code", ddr3code);
+#endif
+
+	return 0;
+}
+
+void board_quiesce_devices(void)
+{
+#ifdef CONFIG_LED
+	setup_led(LEDST_OFF);
+#endif
+}
+
+/* eth init function : weak called in eqos driver */
+int board_interface_eth_init(struct udevice *dev,
+			     phy_interface_t interface_type)
+{
+	u8 *syscfg;
+	u32 value;
+	bool eth_clk_sel_reg = false;
+	bool eth_ref_clk_sel_reg = false;
+
+	/* Gigabit Ethernet 125MHz clock selection. */
+	eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
+
+	/* Ethernet 50Mhz RMII clock selection */
+	eth_ref_clk_sel_reg =
+		dev_read_bool(dev, "st,eth_ref_clk_sel");
+
+	syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+
+	if (!syscfg)
+		return -ENODEV;
+
+	switch (interface_type) {
+	case PHY_INTERFACE_MODE_MII:
+		value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
+			SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
+		debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
+		break;
+	case PHY_INTERFACE_MODE_GMII:
+		if (eth_clk_sel_reg)
+			value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
+				SYSCFG_PMCSETR_ETH_CLK_SEL;
+		else
+			value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
+		debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
+		break;
+	case PHY_INTERFACE_MODE_RMII:
+		if (eth_ref_clk_sel_reg)
+			value = SYSCFG_PMCSETR_ETH_SEL_RMII |
+				SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
+		else
+			value = SYSCFG_PMCSETR_ETH_SEL_RMII;
+		debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		if (eth_clk_sel_reg)
+			value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
+				SYSCFG_PMCSETR_ETH_CLK_SEL;
+		else
+			value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
+		debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
+		break;
+	default:
+		debug("%s: Do not manage %d interface\n",
+		      __func__, interface_type);
+		/* Do not manage others interfaces */
+		return -EINVAL;
+	}
+
+	/* clear and set ETH configuration bits */
+	writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
+	       SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
+	       syscfg + SYSCFG_PMCCLRR);
+	writel(value, syscfg + SYSCFG_PMCSETR);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
+
+static void board_copro_image_process(ulong fw_image, size_t fw_size)
+{
+	int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
+
+	if (!rproc_is_initialized())
+		if (rproc_init()) {
+			printf("Remote Processor %d initialization failed\n",
+			       id);
+			return;
+		}
+
+	ret = rproc_load(id, fw_image, fw_size);
+	printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
+	       id, fw_image, fw_size, ret ? " Failed!" : " Success!");
+
+	if (!ret) {
+		rproc_start(id);
+		env_set("copro_state", "booted");
+	}
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);
diff --git a/roms/u-boot/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its b/roms/u-boot/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
new file mode 100644
index 000000000..8eed9d0fb
--- /dev/null
+++ b/roms/u-boot/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
@@ -0,0 +1,91 @@
+/dts-v1/;
+
+/ {
+	description = "U-Boot mainline";
+	#address-cells = <1>;
+
+	images {
+		uboot {
+			description = "U-Boot (32-bit)";
+			data = /incbin/("u-boot-nodtb.bin");
+			type = "standalone";
+			os = "U-Boot";
+			arch = "arm";
+			compression = "none";
+			load = <0xc0100000>;
+			entry = <0xc0100000>;
+		};
+
+		fdt-1 {
+			description = ".dtb";
+			data = /incbin/("arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+		};
+
+		fdt-2 {
+			description = ".dtb";
+			data = /incbin/("arch/arm/dts/stm32mp15xx-dhcom-drc02.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+		};
+
+		fdt-3 {
+			description = ".dtb";
+			data = /incbin/("arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "config-1";
+
+		config-1 {
+			/* DT+SoM+board model */
+			description = "dh,stm32mp15xx-dhcom-pdk2_somrev0_boardrev0";
+			firmware = "uboot";
+			fdt = "fdt-1";
+		};
+
+		config-2 {
+			/* DT+SoM+board model */
+			description = "dh,stm32mp15xx-dhcom-pdk2_somrev1_boardrev0";
+			firmware = "uboot";
+			fdt = "fdt-1";
+		};
+
+		config-3 {
+			/* DT+SoM+board model */
+			description = "dh,stm32mp15xx-dhcom-drc02_somrev0_boardrev0";
+			firmware = "uboot";
+			fdt = "fdt-2";
+		};
+
+		config-4 {
+			/* DT+SoM+board model */
+			description = "dh,stm32mp15xx-dhcom-drc02_somrev1_boardrev0";
+			firmware = "uboot";
+			fdt = "fdt-2";
+		};
+
+		config-5 {
+			/* DT+SoM+board model */
+			description = "dh,stm32mp15xx-dhcom-picoitx_somrev0_boardrev0";
+			loadables = "uboot";
+			fdt = "fdt-3";
+		};
+
+		config-6 {
+			/* DT+SoM+board model */
+			description = "dh,stm32mp15xx-dhcom-picoitx_somrev1_boardrev0";
+			loadables = "uboot";
+			fdt = "fdt-3";
+		};
+
+		/* Add 587-100..587-400 with fdt-2..fdt-4 here */
+	};
+};
diff --git a/roms/u-boot/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its b/roms/u-boot/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
new file mode 100644
index 000000000..0ea10a149
--- /dev/null
+++ b/roms/u-boot/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
@@ -0,0 +1,40 @@
+/dts-v1/;
+
+/ {
+	description = "U-Boot mainline";
+	#address-cells = <1>;
+
+	images {
+		uboot {
+			description = "U-Boot (32-bit)";
+			data = /incbin/("u-boot-nodtb.bin");
+			type = "standalone";
+			os = "U-Boot";
+			arch = "arm";
+			compression = "none";
+			load = <0xc0100000>;
+			entry = <0xc0100000>;
+		};
+
+		fdt-1 {
+			description = ".dtb";
+			data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "config-1";
+
+		config-1 {
+			/* DT+SoM+board model */
+			description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1";
+			firmware = "uboot";
+			fdt = "fdt-1";
+		};
+
+		/* Add 586-200..586-400 with fdt-2..fdt-4 here */
+	};
+};
diff --git a/roms/u-boot/board/ea/mx7ulp_com/Kconfig b/roms/u-boot/board/ea/mx7ulp_com/Kconfig
new file mode 100644
index 000000000..90883aced
--- /dev/null
+++ b/roms/u-boot/board/ea/mx7ulp_com/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX7ULP_COM
+
+config SYS_BOARD
+	default "mx7ulp_com"
+
+config SYS_VENDOR
+	default "ea"
+
+config SYS_CONFIG_NAME
+	default "mx7ulp_com"
+
+endif
diff --git a/roms/u-boot/board/ea/mx7ulp_com/MAINTAINERS b/roms/u-boot/board/ea/mx7ulp_com/MAINTAINERS
new file mode 100644
index 000000000..3f69511b1
--- /dev/null
+++ b/roms/u-boot/board/ea/mx7ulp_com/MAINTAINERS
@@ -0,0 +1,6 @@
+MX7ULPCOM BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/ea/mx7ulp_com/
+F:	include/configs/mx7ulp_com.h
+F:	configs/mx7ulp_com_defconfig
diff --git a/roms/u-boot/board/ea/mx7ulp_com/Makefile b/roms/u-boot/board/ea/mx7ulp_com/Makefile
new file mode 100644
index 000000000..b3b230b17
--- /dev/null
+++ b/roms/u-boot/board/ea/mx7ulp_com/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx7ulp_com.o
diff --git a/roms/u-boot/board/ea/mx7ulp_com/imximage.cfg b/roms/u-boot/board/ea/mx7ulp_com/imximage.cfg
new file mode 100644
index 000000000..1b218996a
--- /dev/null
+++ b/roms/u-boot/board/ea/mx7ulp_com/imximage.cfg
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00dc 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e0508 0x00160002
+DATA 4   0x403E0510 0x00000001
+DATA 4   0x403E0514 0x00000014
+DATA 4   0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+/*
+ * Default PFD0 divide is 27, which generates:
+ * PFD0 Freq = A7 APLL (528MHz) * 18 / 27 = 352MHz
+ *
+ * i.MX7ULP COM board can not run DDR at 352MHz, so
+ * use a divider of 30 (0x1E), which gives:
+ *
+ * PFD0 Freq = A7 APLL (528MHz) * 18 / 30 = 316.8MHz
+ */
+DATA 4   0x403e050c 0x8080801E
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00dc 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB0890 0x00400000
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB0848 0x3A3E3838
+DATA 4   0x40AB0850 0x28282C2A
+DATA 4   0x40AB083C 0x20000000
+DATA 4   0x40AB0840 0x00000000
+DATA 4   0x40AB08B8 0x00000800
+DATA 4   0x40AB000C 0x292C40F5
+DATA 4   0x40AB0004 0x00020064
+DATA 4   0x40AB0010 0xB6AD0A83
+DATA 4   0x40AB0014 0x00C70093
+DATA 4   0x40AB0018 0x00211708
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0038 0x00130556
+DATA 4   0x40AB0008 0x12272000
+DATA 4   0x40AB0040 0x0000003F
+DATA 4   0x40AB0000 0xC3110000
+DATA 4   0x40AB001C 0x00008010
+DATA 4   0x40AB001C 0x00008018
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0x82018030
+DATA 4   0x40AB001C 0x06028030
+DATA 4   0x40AB001C 0x01038030
+DATA 4   0x40AB001C 0x003F8038
+DATA 4   0x40AB001C 0xFF0A8038
+DATA 4   0x40AB001C 0x82018038
+DATA 4   0x40AB001C 0x06028038
+DATA 4   0x40AB001C 0x01038038
+DATA 4   0x40AB083C 0xA0000000
+DATA 4   0x40AB083C 0xA0000000
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1310003
+DATA 4   0x40AB001C 0x00000000
+#endif
diff --git a/roms/u-boot/board/ea/mx7ulp_com/mx7ulp_com.c b/roms/u-boot/board/ea/mx7ulp_com/mx7ulp_com.c
new file mode 100644
index 000000000..5b2d44436
--- /dev/null
+++ b/roms/u-boot/board/ea/mx7ulp_com/mx7ulp_com.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx7ulp-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL		(PAD_CTL_PUS_UP)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_cfg_t const lpuart4_pads[] = {
+	MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
+					 ARRAY_SIZE(lpuart4_pads));
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/ebv/socrates/MAINTAINERS b/roms/u-boot/board/ebv/socrates/MAINTAINERS
new file mode 100644
index 000000000..e48236fc8
--- /dev/null
+++ b/roms/u-boot/board/ebv/socrates/MAINTAINERS
@@ -0,0 +1,6 @@
+SOCRATES BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/ebv/socrates/
+F:	include/configs/socfpga_socrates.h
+F:	configs/socfpga_socrates_defconfig
diff --git a/roms/u-boot/board/ebv/socrates/Makefile b/roms/u-boot/board/ebv/socrates/Makefile
new file mode 100644
index 000000000..e1c8a6b3c
--- /dev/null
+++ b/roms/u-boot/board/ebv/socrates/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/ebv/socrates/qts/iocsr_config.h b/roms/u-boot/board/ebv/socrates/qts/iocsr_config.h
new file mode 100644
index 000000000..18b9c6ce4
--- /dev/null
+++ b/roms/u-boot/board/ebv/socrates/qts/iocsr_config.h
@@ -0,0 +1,659 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00004824,
+	0x01209000,
+	0x82400000,
+	0x00018004,
+	0x00000000,
+	0x00004000,
+	0x00002412,
+	0x00904800,
+	0x41200000,
+	0x80000002,
+	0x00000904,
+	0x00002000,
+	0x00001209,
+	0x00482400,
+	0x20900000,
+	0x40000001,
+	0x00000482,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00009048,
+	0x02412000,
+	0x048000C0,
+	0x00000009,
+	0x00002412,
+	0x00008000,
+	0x00004824,
+	0x01209000,
+	0x82400000,
+	0x00000004,
+	0x00001209,
+	0x00004000,
+	0x00002412,
+	0x00904800,
+	0x41200000,
+	0x80000002,
+	0x00000904,
+	0x00002000,
+	0x06001209,
+	0x00482400,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x80001000,
+	0x00000904,
+	0x00241200,
+	0x90480000,
+	0x20003000,
+	0x00000241,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x48240000,
+	0x90000000,
+	0x00000120,
+	0x00000400,
+	0x00000000,
+	0x00090480,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x90000200,
+	0x00600120,
+	0x00000000,
+	0x12090000,
+	0x24000600,
+	0x00000048,
+	0x48000100,
+	0x00300090,
+	0xC0024120,
+	0x09048000,
+	0x12000300,
+	0x000C0024,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x30009048,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x0C002412,
+	0x00008000,
+	0x18004824,
+	0x00000000,
+	0x82400000,
+	0x00018004,
+	0x06001209,
+	0x00004000,
+	0x20042412,
+	0x00904800,
+	0x00000030,
+	0x80000000,
+	0x03000904,
+	0x00002000,
+	0x10001209,
+	0x00482400,
+	0x20900000,
+	0x40010001,
+	0x00000482,
+	0x80001000,
+	0x00000904,
+	0x00000000,
+	0x90480000,
+	0x20008000,
+	0x00C00241,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0CC20D80,
+	0x0C3000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x20430000,
+	0x0C003001,
+	0x00C00481,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x90218000,
+	0x86001800,
+	0x00600240,
+	0x80090218,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x4810C000,
+	0x43000C00,
+	0x00300120,
+	0xC004810C,
+	0x12043000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680A28,
+	0x45034030,
+	0x12481A01,
+	0x80A280D0,
+	0x34030C06,
+	0x01A01450,
+	0x280D0000,
+	0x30C0680A,
+	0x02490340,
+	0xD000001A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x18000000,
+	0x01800902,
+	0x00240860,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x20430000,
+	0x0C003001,
+	0x00C00481,
+	0x00000FF0,
+	0x4810C000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x90218000,
+	0x86001800,
+	0x00600240,
+	0x80090218,
+	0x24086001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x4810C000,
+	0x43000C00,
+	0x00300120,
+	0xC004810C,
+	0x12043000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680A28,
+	0x49034030,
+	0x12481A02,
+	0x80A280D0,
+	0x34030C06,
+	0x01A00040,
+	0x280D0002,
+	0x30C0680A,
+	0x02490340,
+	0xD00A281A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x18000000,
+	0x01800902,
+	0x00240860,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x2043090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xF228A3D5,
+	0xF6D1451E,
+	0x0342E388,
+	0x821A0000,
+	0x0000D000,
+	0x05140680,
+	0xD949247A,
+	0x1EF228A3,
+	0x88F6D145,
+	0x000352E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x86120800,
+	0x00600240,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xF3CF23D5,
+	0xF4D1451E,
+	0x034A9248,
+	0x821A038E,
+	0x0000D000,
+	0x00000680,
+	0xD949247A,
+	0x1EF3CF23,
+	0x88F4D145,
+	0x000352E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x2043090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xF228A3D9,
+	0xF4D1451E,
+	0x034A9248,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD949247A,
+	0x1EF228A3,
+	0x88F4D145,
+	0x000352E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x08864000,
+	0x49247A02,
+	0xF3CF23D9,
+	0xF4D1451E,
+	0x0342E388,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD949247A,
+	0x1EF3CF23,
+	0x88F4DE79,
+	0x000342A2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/ebv/socrates/qts/pinmux_config.h b/roms/u-boot/board/ebv/socrates/qts/pinmux_config.h
new file mode 100644
index 000000000..41b634315
--- /dev/null
+++ b/roms/u-boot/board/ebv/socrates/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	3, /* GENERALIO9 */
+	3, /* GENERALIO10 */
+	3, /* GENERALIO11 */
+	3, /* GENERALIO12 */
+	2, /* GENERALIO13 */
+	2, /* GENERALIO14 */
+	1, /* GENERALIO15 */
+	1, /* GENERALIO16 */
+	1, /* GENERALIO17 */
+	1, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/ebv/socrates/qts/pll_config.h b/roms/u-boot/board/ebv/socrates/qts/pll_config.h
new file mode 100644
index 000000000..71d367475
--- /dev/null
+++ b/roms/u-boot/board/ebv/socrates/qts/pll_config.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/roms/u-boot/board/ebv/socrates/qts/sdram_config.h b/roms/u-boot/board/ebv/socrates/qts/sdram_config.h
new file mode 100644
index 000000000..2f8465bf7
--- /dev/null
+++ b/roms/u-boot/board/ebv/socrates/qts/sdram_config.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			117
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		1300
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			12
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			17
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	7
+#define CALIB_VFIFO_OFFSET	5
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	375
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x5555048d
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	82
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	82
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080221,
+	0x10080320,
+	0x10090044,
+	0x100a0008,
+	0x100b0000,
+	0x10380400,
+	0x10080241,
+	0x100802c0,
+	0x100a0024,
+	0x10090010,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/roms/u-boot/board/ebv/socrates/socfpga.c b/roms/u-boot/board/ebv/socrates/socfpga.c
new file mode 100644
index 000000000..48bfe3295
--- /dev/null
+++ b/roms/u-boot/board/ebv/socrates/socfpga.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+#include <common.h>
diff --git a/roms/u-boot/board/eets/pdu001/Kconfig b/roms/u-boot/board/eets/pdu001/Kconfig
new file mode 100644
index 000000000..e64ae2887
--- /dev/null
+++ b/roms/u-boot/board/eets/pdu001/Kconfig
@@ -0,0 +1,50 @@
+# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+if TARGET_PDU001
+
+config SYS_BOARD
+	default "pdu001"
+
+config SYS_VENDOR
+	default "eets"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "pdu001"
+
+choice
+	prompt "State of Run LED"
+	default RUN_LED_RED
+	help
+	  The PDU001 has a bi-color (red/green) LED labeled 'Run' which
+	  can be used to indicate the operating state of the board. By
+	  default it will be lit red by U-Boot. Later in the start-up
+	  process it can be changed to green (or heartbeat or anything else)
+	  by the kernel or some other software.
+
+config RUN_LED_RED
+	bool
+	prompt "Red"
+	help
+	  Lit Run LED red.
+
+config RUN_LED_GREEN
+	bool
+	prompt "Green"
+	help
+	  Lit Run LED green.
+
+config RUN_LED_OFF
+	bool
+	prompt "Off"
+	help
+	  Do not lit Run LED.
+
+endchoice
+
+endif
diff --git a/roms/u-boot/board/eets/pdu001/MAINTAINERS b/roms/u-boot/board/eets/pdu001/MAINTAINERS
new file mode 100644
index 000000000..95295ddea
--- /dev/null
+++ b/roms/u-boot/board/eets/pdu001/MAINTAINERS
@@ -0,0 +1,6 @@
+PDU001 BOARD
+M:	Felix Brack <fb@ltec.ch>
+S:	Maintained
+F:	board/eets/pdu001/
+F:	include/configs/pdu001.h
+F:	configs/am335x_pdu001_defconfig
diff --git a/roms/u-boot/board/eets/pdu001/Makefile b/roms/u-boot/board/eets/pdu001/Makefile
new file mode 100644
index 000000000..08c6d536d
--- /dev/null
+++ b/roms/u-boot/board/eets/pdu001/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/roms/u-boot/board/eets/pdu001/README b/roms/u-boot/board/eets/pdu001/README
new file mode 100644
index 000000000..50e715446
--- /dev/null
+++ b/roms/u-boot/board/eets/pdu001/README
@@ -0,0 +1,35 @@
+# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+Summary
+=======
+
+This document covers the PDU001 target.
+
+Hardware
+========
+
+The PDU-001 (Processor and Display Unit) is a plugin card for 19" racks. It is
+manufactured by EETS GmbH (https://www.eets.ch). The core of the board is a m2
+SOM from bytes at work (https://www.bytesatwork.ch) which in turn is based on
+AM3352 SOC from TI (http://www.ti.com).
+
+Customization
+=============
+
+As usual the console serial interface is set by CONFIG_CONS_INDEX. Best choice
+is 4 here since UART3 is wired to the connector K2.
+The Run LED on the PDU-001 can be turned on red by setting CONFIG_RUN_LED_RED
+or green by setting CONFIG_RUN_LED_GREEN. Setting CONFIG_RUN_LED_OFF will turn
+off the Run LED.
+
+Booting
+=======
+
+The system boots from either eMMC or SD card cage. It will first try to boot
+from the SD card cage. If this fails (missing or unbootable SD card) it will
+try to boot from the internal eMMC. The root file system is always expected to
+be located in the second partition of the device (eMMC or SD card) that pro-
+vided the boot loader.
diff --git a/roms/u-boot/board/eets/pdu001/board.c b/roms/u-boot/board/eets/pdu001/board.c
new file mode 100644
index 000000000..f806d1e76
--- /dev/null
+++ b/roms/u-boot/board/eets/pdu001/board.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for EETS PDU001 board
+ *
+ * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <i2c.h>
+#include <watchdog.h>
+#include <debug_uart.h>
+#include <asm/global_data.h>
+#include <dm/ofnode.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_ADDR_NODE_ID	0x50
+#define I2C_REG_NODE_ID_BASE	0xfa
+#define NODE_ID_BYTE_COUNT	6
+
+#define I2C_ADDR_LEDS		0x60
+#define I2C_REG_RUN_LED		0x06
+#define RUN_LED_OFF		0x0
+#define RUN_LED_RED		0x1
+#define RUN_LED_GREEN		(0x1 << 2)
+
+#define VDD_MPU_REGULATOR	"regulator@2"
+#define VDD_CORE_REGULATOR	"regulator@3"
+#define DEFAULT_CORE_VOLTAGE	1137500
+
+/*
+ *  boot device save register
+ * -------------------------
+ * The boot device can be quired by 'spl_boot_device()' in
+ * 'am33xx_spl_board_init'. However it can't be saved in the u-boot
+ * environment here. In turn 'spl_boot_device' can't be called in
+ * 'board_late_init' which allows writing to u-boot environment.
+ * To get the boot device from 'am33xx_spl_board_init' to
+ * 'board_late_init' we therefore use a scratch register from the RTC.
+ */
+#define CONFIG_SYS_RTC_SCRATCH0 0x60
+#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0)
+
+#ifdef CONFIG_SPL_BUILD
+static void save_boot_device(void)
+{
+	*((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device();
+}
+#endif
+
+u32 boot_device(void)
+{
+	return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER));
+}
+
+/* Store the boot device in the environment variable 'boot_device' */
+static void env_set_boot_device(void)
+{
+	switch (boot_device()) {
+		case BOOT_DEVICE_MMC1: {
+			env_set("boot_device", "emmc");
+			break;
+		}
+		case BOOT_DEVICE_MMC2: {
+			env_set("boot_device", "sdcard");
+			break;
+		}
+		default: {
+			env_set("boot_device", "unknown");
+			break;
+		}
+	}
+}
+
+static void set_run_led(struct udevice *dev)
+{
+	int val = RUN_LED_OFF;
+
+	if (IS_ENABLED(CONFIG_RUN_LED_RED))
+		val = RUN_LED_RED;
+	else if (IS_ENABLED(CONFIG_RUN_LED_GREEN))
+		val = RUN_LED_GREEN;
+
+	dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val);
+}
+
+/* Set 'serial#' to the EUI-48 value of board node ID chip */
+static void env_set_serial(struct udevice *dev)
+{
+	int val;
+	char serial[2 * NODE_ID_BYTE_COUNT + 1];
+	int n;
+
+	for (n = 0; n < sizeof(serial); n += 2) {
+		val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2);
+		sprintf(serial + n, "%02X", val);
+	}
+	serial[2 * NODE_ID_BYTE_COUNT] = '\0';
+	env_set("serial#", serial);
+}
+
+static void set_mpu_and_core_voltage(void)
+{
+	int mpu_vdd;
+	int sil_rev;
+	struct udevice *dev;
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	/*
+	 * The PDU001 (more precisely the computing module m2) uses a
+	 * TPS65910 PMIC.  For all MPU frequencies we support we use a CORE
+	 * voltage of 1.1375V.  For MPU voltage we need to switch based on
+	 * the frequency we are running at.
+	 */
+
+	/*
+	 * Depending on MPU clock and PG we will need a different VDD
+	 * to drive at that speed.
+	 */
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m);
+
+	/* first update the MPU voltage */
+	if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) {
+		if (regulator_set_value(dev, mpu_vdd))
+			debug("failed to set MPU voltage\n");
+	} else {
+		debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR);
+	}
+
+	/* second update the CORE voltage */
+	if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) {
+		if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE))
+			debug("failed to set CORE voltage\n");
+	} else {
+		debug("invalid CORE voltage ragulator %s\n",
+		      VDD_CORE_REGULATOR);
+	}
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static const struct ddr_data ddr2_data = {
+	.datardsratio0 = MT47H128M16RT25E_RD_DQS,
+	.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+	.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+	.cmd0csratio = MT47H128M16RT25E_RATIO,
+	.cmd1csratio = MT47H128M16RT25E_RATIO,
+	.cmd2csratio = MT47H128M16RT25E_RATIO,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
+#define OSC	(V_OSCK / 1000000)
+const struct dpll_params dpll_ddr = {
+		266, OSC - 1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_evm_sk = {
+		303, OSC - 1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_bone_black = {
+		400, OSC - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+
+	/* save boot device for later use by 'board_late_init' */
+	save_boot_device();
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	enable_i2c0_pin_mux();
+
+	return &dpll_ddr;
+}
+
+void set_mux_conf_regs(void)
+{
+	/* done first by the ROM and afterwards by the pin controller driver */
+	enable_i2c0_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+	config_ddr(266, &ioregs, &ddr2_data,
+		   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
+}
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#ifdef CONFIG_DEBUG_UART
+void board_debug_uart_init(void)
+{
+	/* done by pin controller driver if not debugging */
+	enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	struct udevice *dev;
+
+	set_mpu_and_core_voltage();
+	env_set_boot_device();
+
+	/* second I2C bus connects to node ID and front panel LED chip */
+	if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev))
+		set_run_led(dev);
+	if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev))
+		env_set_serial(dev);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/eets/pdu001/board.h b/roms/u-boot/board/eets/pdu001/board.h
new file mode 100644
index 000000000..bfea96e5f
--- /dev/null
+++ b/roms/u-boot/board/eets/pdu001/board.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * EETS GmbH PDU001 board information header
+ *
+ * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have two pin mux functions that must exist. First we need I2C0 to
+ * access the TPS65910 PMIC located on the M2 computing module.
+ * Second, if we want low-level debugging or a early UART (ie. before the
+ * pin controller driver is running), we need one of the UART ports UART0 to
+ * UART5 (usually UART3 since it is wired to K2).
+ * In case of I2C0 access we explicitly don't rely on the the ROM but we could
+ * do so as we use the primary mode (mode 0) for I2C0.
+ * All other multiplexing and pin configuration is done by the DT once it
+ * gets parsed by the pin controller driver.
+ * However we relay on the ROM to configure the pins of MMC0 (eMMC) as well
+ * as MMC1 (microSD card-cage) since these are our boot devices.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_uart_pin_mux(u32 addr);
+void enable_i2c0_pin_mux(void);
+
+#endif
diff --git a/roms/u-boot/board/eets/pdu001/mux.c b/roms/u-boot/board/eets/pdu001/mux.c
new file mode 100644
index 000000000..f0f9e262e
--- /dev/null
+++ b/roms/u-boot/board/eets/pdu001/mux.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART1_RXD */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},		/* UART1_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART2_RXD */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)},			/* I2C_DATA  */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)},			/* I2C_SCLK  */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+	configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+	configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_uart_pin_mux(u32 addr)
+{
+	switch (addr) {
+	case CONFIG_SYS_NS16550_COM1:
+		enable_uart0_pin_mux();
+		break;
+	case CONFIG_SYS_NS16550_COM2:
+		enable_uart1_pin_mux();
+		break;
+	case CONFIG_SYS_NS16550_COM3:
+		enable_uart2_pin_mux();
+		break;
+	case CONFIG_SYS_NS16550_COM4:
+		enable_uart3_pin_mux();
+		break;
+	case CONFIG_SYS_NS16550_COM5:
+		enable_uart4_pin_mux();
+		break;
+	case CONFIG_SYS_NS16550_COM6:
+		enable_uart5_pin_mux();
+		break;
+	}
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
diff --git a/roms/u-boot/board/efi/Kconfig b/roms/u-boot/board/efi/Kconfig
new file mode 100644
index 000000000..291bd2ca1
--- /dev/null
+++ b/roms/u-boot/board/efi/Kconfig
@@ -0,0 +1,28 @@
+if VENDOR_EFI
+
+choice
+	prompt "Mainboard model"
+	optional
+
+config TARGET_EFI_APP
+	bool "efi application"
+	help
+	  This target is used for running U-Boot on top of EFI. In
+	  this case EFI does the early initialisation, and U-Boot
+	  takes over once the RAM, video and CPU are fully running.
+	  U-Boot is loaded as an application from EFI.
+
+config TARGET_EFI_PAYLOAD
+	bool "efi payload"
+	help
+	  This target is used for running U-Boot on top of EFI. In
+	  this case EFI does the early initialisation, and U-Boot
+	  takes over once the RAM, video and CPU are fully running.
+	  U-Boot is loaded as a payload from EFI.
+
+endchoice
+
+source "board/efi/efi-x86_app/Kconfig"
+source "board/efi/efi-x86_payload/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/efi/efi-x86_app/Kconfig b/roms/u-boot/board/efi/efi-x86_app/Kconfig
new file mode 100644
index 000000000..ae87bf34d
--- /dev/null
+++ b/roms/u-boot/board/efi/efi-x86_app/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EFI_APP
+
+config SYS_BOARD
+	default "efi-x86_app"
+
+config SYS_VENDOR
+	default "efi"
+
+config SYS_SOC
+	default "efi"
+
+config SYS_CONFIG_NAME
+	default "efi-x86_app"
+
+endif
diff --git a/roms/u-boot/board/efi/efi-x86_app/MAINTAINERS b/roms/u-boot/board/efi/efi-x86_app/MAINTAINERS
new file mode 100644
index 000000000..fb8a6b1c2
--- /dev/null
+++ b/roms/u-boot/board/efi/efi-x86_app/MAINTAINERS
@@ -0,0 +1,6 @@
+EFI-X86_APP BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/efi/efi-x86_app/
+F:	include/configs/efi-x86_app.h
+F:	configs/efi-x86_app_defconfig
diff --git a/roms/u-boot/board/efi/efi-x86_app/Makefile b/roms/u-boot/board/efi/efi-x86_app/Makefile
new file mode 100644
index 000000000..cb48d1ccc
--- /dev/null
+++ b/roms/u-boot/board/efi/efi-x86_app/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2015 Google, Inc
+
+obj-y	+= app.o
diff --git a/roms/u-boot/board/efi/efi-x86_app/app.c b/roms/u-boot/board/efi/efi-x86_app/app.c
new file mode 100644
index 000000000..da3445bb1
--- /dev/null
+++ b/roms/u-boot/board/efi/efi-x86_app/app.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Google, Inc
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/efi/efi-x86_payload/Kconfig b/roms/u-boot/board/efi/efi-x86_payload/Kconfig
new file mode 100644
index 000000000..08dd0c2ed
--- /dev/null
+++ b/roms/u-boot/board/efi/efi-x86_payload/Kconfig
@@ -0,0 +1,40 @@
+if TARGET_EFI_PAYLOAD
+
+config SYS_BOARD
+	default "efi-x86_payload"
+
+config SYS_VENDOR
+	default "efi"
+
+config SYS_SOC
+	default "efi"
+
+config SYS_CONFIG_NAME
+	default "efi-x86_payload"
+
+config SYS_TEXT_BASE
+	default 0x00200000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select BOARD_EARLY_INIT_R
+	imply SYS_NS16550
+	imply SCSI
+	imply SCSI_AHCI
+	imply AHCI_PCI
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply USB
+	imply USB_EHCI_HCD
+	imply USB_XHCI_HCD
+	imply USB_STORAGE
+	imply USB_KEYBOARD
+	imply VIDEO_EFI
+	imply E1000
+	imply ETH_DESIGNWARE
+	imply PCH_GBE
+	imply RTL8169
+
+endif
diff --git a/roms/u-boot/board/efi/efi-x86_payload/MAINTAINERS b/roms/u-boot/board/efi/efi-x86_payload/MAINTAINERS
new file mode 100644
index 000000000..abf3a1574
--- /dev/null
+++ b/roms/u-boot/board/efi/efi-x86_payload/MAINTAINERS
@@ -0,0 +1,7 @@
+EFI-X86_PAYLOAD BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/efi/efi-x86_payload/
+F:	include/configs/efi-x86_payload.h
+F:	configs/efi-x86_payload32_defconfig
+F:	configs/efi-x86_payload64_defconfig
diff --git a/roms/u-boot/board/efi/efi-x86_payload/Makefile b/roms/u-boot/board/efi/efi-x86_payload/Makefile
new file mode 100644
index 000000000..a4ebc85aa
--- /dev/null
+++ b/roms/u-boot/board/efi/efi-x86_payload/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y	+= payload.o
diff --git a/roms/u-boot/board/efi/efi-x86_payload/payload.c b/roms/u-boot/board/efi/efi-x86_payload/payload.c
new file mode 100644
index 000000000..5d4492cdc
--- /dev/null
+++ b/roms/u-boot/board/efi/efi-x86_payload/payload.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <usb.h>
+
+int board_early_init_r(void)
+{
+	/*
+	 * Make sure PCI bus is enumerated so that peripherals on the PCI bus
+	 * can be discovered by their drivers
+	 */
+	pci_init();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/egnite/ethernut5/Kconfig b/roms/u-boot/board/egnite/ethernut5/Kconfig
new file mode 100644
index 000000000..5a6c1c5de
--- /dev/null
+++ b/roms/u-boot/board/egnite/ethernut5/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ETHERNUT5
+
+config SYS_BOARD
+	default "ethernut5"
+
+config SYS_VENDOR
+	default "egnite"
+
+config SYS_CONFIG_NAME
+	default "ethernut5"
+
+endif
diff --git a/roms/u-boot/board/egnite/ethernut5/MAINTAINERS b/roms/u-boot/board/egnite/ethernut5/MAINTAINERS
new file mode 100644
index 000000000..a4ad913b6
--- /dev/null
+++ b/roms/u-boot/board/egnite/ethernut5/MAINTAINERS
@@ -0,0 +1,6 @@
+ETHERNUT5 BOARD
+M:	egnite GmbH <info@egnite.de>
+S:	Maintained
+F:	board/egnite/ethernut5/
+F:	include/configs/ethernut5.h
+F:	configs/ethernut5_defconfig
diff --git a/roms/u-boot/board/egnite/ethernut5/Makefile b/roms/u-boot/board/egnite/ethernut5/Makefile
new file mode 100644
index 000000000..580f44056
--- /dev/null
+++ b/roms/u-boot/board/egnite/ethernut5/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2010
+# egnite GmbH
+
+obj-y	+= ethernut5.o
+obj-y	+= ethernut5_pwrman.o
diff --git a/roms/u-boot/board/egnite/ethernut5/ethernut5.c b/roms/u-boot/board/egnite/ethernut5/ethernut5.c
new file mode 100644
index 000000000..559fdd2f6
--- /dev/null
+++ b/roms/u-boot/board/egnite/ethernut5/ethernut5.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011
+ * egnite GmbH <info@egnite.de>
+ *
+ * (C) Copyright 2010
+ * Ole Reinhardt <ole.reinhardt@thermotemp.de>
+ */
+
+/*
+ * Ethernut 5 general board support
+ *
+ * Ethernut is an open source hardware and software project for
+ * embedded Ethernet devices. Hardware layouts and CAD files are
+ * freely available under BSD-like license.
+ *
+ * Ethernut 5 is the first member of the Ethernut board family
+ * with U-Boot and Linux support. This implementation is based
+ * on the original work done by Ole Reinhardt, but heavily modified
+ * to support additional features and the latest board revision 5.0F.
+ *
+ * Main board components are by default:
+ *
+ * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
+ * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
+ * 512 MBytes Micron MT29F4G08ABADA NAND Flash
+ * 4 MBytes Atmel AT45DB321D DataFlash
+ * SMSC LAN8710 Ethernet PHY
+ * Atmel ATmega168 MCU used for power management
+ * Linear Technology LTC4411 PoE controller
+ *
+ * U-Boot relevant board interfaces are:
+ *
+ * 100 Mbit Ethernet with IEEE 802.3af PoE
+ * RS-232 serial port
+ * USB host and device
+ * MMC/SD-Card slot
+ * Expansion port with I2C, SPI and more...
+ *
+ * Typically the U-Boot image is loaded from serial DataFlash into
+ * SDRAM by the samboot boot loader, which is located in internal
+ * NOR Flash and provides all essential initializations like CPU
+ * and peripheral clocks and, of course, the SDRAM configuration.
+ *
+ * For testing purposes it is also possibly to directly transfer
+ * the image into SDRAM via JTAG. A tested configuration exists
+ * for the Turtelizer 2 hardware dongle and the OpenOCD software.
+ * In this case the latter will do the basic hardware configuration
+ * via its reset-init script.
+ *
+ * For additional information visit the project home page at
+ * http://www.ethernut.de/
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <atmel_mci.h>
+#include <asm/global_data.h>
+
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include "ethernut5_pwrman.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This is called last during early initialization. Most of the basic
+ * hardware interfaces are up and running.
+ *
+ * The SDRAM hardware has been configured by the first stage boot loader.
+ * We only need to announce its size, using u-boot's memory check.
+ */
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(
+			(void *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void ethernut5_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_DBW_8 |
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+#ifdef CONFIG_SYS_NAND_READY_PIN
+	/* Ready pin is optional. */
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+#endif
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+/*
+ * This is called first during late initialization.
+ */
+int board_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+	/* Set adress of boot parameters. */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	/* Initialize UARTs and power management. */
+	ethernut5_power_init();
+#ifdef CONFIG_CMD_NAND
+	ethernut5_nand_hw_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_MACB
+/*
+ * This is optionally called last during late initialization.
+ */
+int board_eth_init(struct bd_info *bis)
+{
+	const char *devname;
+	unsigned short mode;
+
+	at91_periph_clk_enable(ATMEL_ID_EMAC0);
+
+	/* Need to reset PHY via power management. */
+	ethernut5_phy_reset();
+	/* Set peripheral pins. */
+	at91_macb_hw_init();
+	/* Basic EMAC initialization. */
+	if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
+		return -1;
+	/*
+	 * Early board revisions have a pull-down at the PHY's MODE0
+	 * strap pin, which forces the PHY into power down. Here we
+	 * switch to all-capable mode.
+	 */
+	devname = miiphy_get_current_dev();
+	if (miiphy_read(devname, 0, 18, &mode) == 0) {
+		/* Set mode[2:0] to 0b111. */
+		mode |= 0x00E0;
+		miiphy_write(devname, 0, 18, mode);
+		/* Soft reset overrides strap pins. */
+		miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
+	}
+	/* Sync environment with network devices, needed for nfsroot. */
+	return eth_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(struct bd_info *bd)
+{
+	at91_periph_clk_enable(ATMEL_ID_MCI);
+
+	/* Initialize MCI hardware. */
+	at91_mci_hw_init();
+	/* Register the device. */
+	return atmel_mci_init((void *)ATMEL_BASE_MCI);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
+}
+#endif
diff --git a/roms/u-boot/board/egnite/ethernut5/ethernut5_pwrman.c b/roms/u-boot/board/egnite/ethernut5/ethernut5_pwrman.c
new file mode 100644
index 000000000..81f1abf2f
--- /dev/null
+++ b/roms/u-boot/board/egnite/ethernut5/ethernut5_pwrman.c
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011
+ * egnite GmbH <info@egnite.de>
+ */
+
+/*
+ * Ethernut 5 power management support
+ *
+ * This board may be supplied via USB, IEEE 802.3af PoE or an
+ * auxiliary DC input. An on-board ATmega168 microcontroller,
+ * the so called power management controller or PMC, is used
+ * to select the supply source and to switch on and off certain
+ * energy consuming board components. This allows to reduce the
+ * total stand-by consumption to less than 70mW.
+ *
+ * The main CPU communicates with the PMC via I2C. When
+ * CONFIG_CMD_BSP is defined in the board configuration file,
+ * then the board specific command 'pwrman' becomes available,
+ * which allows to manually deal with the PMC.
+ *
+ * Two distinct registers are provided by the PMC for enabling
+ * and disabling specific features. This avoids the often seen
+ * read-modify-write cycle or shadow register requirement.
+ * Additional registers are available to query the board
+ * status and temperature, the auxiliary voltage and to control
+ * the green user LED that is integrated in the reset switch.
+ *
+ * Note, that the AVR firmware of the PMC is released under BSDL.
+ *
+ * For additional information visit the project home page at
+ * http://www.ethernut.de/
+ */
+#include <common.h>
+#include <command.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <linux/delay.h>
+
+#include "ethernut5_pwrman.h"
+
+/* PMC firmware version */
+static int pwrman_major;
+static int pwrman_minor;
+
+/*
+ * Enable Ethernut 5 power management.
+ *
+ * This function must be called during board initialization.
+ * While we are using u-boot's I2C subsystem, it may be required
+ * to enable the serial port before calling this function,
+ * in particular when debugging is enabled.
+ *
+ * If board specific commands are not available, we will activate
+ * all board components.
+ */
+void ethernut5_power_init(void)
+{
+	pwrman_minor = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VERS);
+	pwrman_major = pwrman_minor >> 4;
+	pwrman_minor &= 15;
+
+#ifndef CONFIG_CMD_BSP
+	/* Do not modify anything, if we do not have a known version. */
+	if (pwrman_major == 2) {
+		/* Without board specific commands we enable all features. */
+		i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, ~PWRMAN_ETHRST);
+		i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
+	}
+#endif
+}
+
+/*
+ * Reset Ethernet PHY.
+ *
+ * This function allows the re-configure the PHY after
+ * changing its strap pins.
+ */
+void ethernut5_phy_reset(void)
+{
+	/* Do not modify anything, if we do not have a known version. */
+	if (pwrman_major != 2)
+		return;
+
+	/*
+	 * Make sure that the Ethernet clock is enabled and the PHY reset
+	 * is disabled for at least 100 us.
+	 */
+	i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHCLK);
+	i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
+	udelay(100);
+
+	/*
+	 * LAN8710 strap pins are
+	 * PA14 => PHY MODE0
+	 * PA15 => PHY MODE1
+	 * PA17 => PHY MODE2 => 111b all capable
+	 * PA18 => PHY ADDR0 => 0b
+	 */
+	at91_set_pio_input(AT91_PIO_PORTA, 14, 1);
+	at91_set_pio_input(AT91_PIO_PORTA, 15, 1);
+	at91_set_pio_input(AT91_PIO_PORTA, 17, 1);
+	at91_set_pio_input(AT91_PIO_PORTA, 18, 0);
+
+	/* Activate PHY reset for 100 us. */
+	i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHRST);
+	udelay(100);
+	i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
+
+	at91_set_pio_input(AT91_PIO_PORTA, 14, 1);
+}
+
+/*
+ * Output the firmware version we got during initialization.
+ */
+void ethernut5_print_version(void)
+{
+	printf("%u.%u\n", pwrman_major, pwrman_minor);
+}
+
+/*
+ * All code below this point is optional and implements
+ * the 'pwrman' command.
+ */
+#ifdef CONFIG_CMD_BSP
+
+/* Human readable names of PMC features */
+char *pwrman_feat[8] = {
+	"board", "vbin", "vbout", "mmc",
+	"rs232", "ethclk", "ethrst", "wakeup"
+};
+
+/*
+ * Print all feature names, that have its related flags enabled.
+ */
+static void print_flagged_features(u8 flags)
+{
+	int i;
+
+	for (i = 0; i < 8; i++) {
+		if (flags & (1 << i))
+			printf("%s ", pwrman_feat[i]);
+	}
+}
+
+/*
+ * Return flags of a given list of feature names.
+ *
+ * The function stops at the first unknown list entry and
+ * returns the number of detected names as a function result.
+ */
+static int feature_flags(char * const names[], int num, u8 *flags)
+{
+	int i, j;
+
+	*flags = 0;
+	for (i = 0; i < num; i++) {
+		for (j = 0; j < 8; j++) {
+			if (strcmp(pwrman_feat[j], names[i]) == 0) {
+				*flags |= 1 << j;
+				break;
+			}
+		}
+		if (j > 7)
+			break;
+	}
+	return i;
+}
+
+void ethernut5_print_power(void)
+{
+	u8 flags;
+	int i;
+
+	flags = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA);
+	for (i = 0; i < 2; i++) {
+		if (flags) {
+			print_flagged_features(flags);
+			printf("%s\n", i ? "off" : "on");
+		}
+		flags = ~flags;
+	}
+}
+
+void ethernut5_print_celsius(void)
+{
+	int val;
+
+	/* Read ADC value from LM50 and return Celsius degrees. */
+	val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_TEMP);
+	val *= 5000;	/* 100mV/degree with 5V reference */
+	val += 128;	/* 8 bit resolution */
+	val /= 256;
+	val -= 450;	/* Celsius offset, still x10 */
+	/* Output full degrees. */
+	printf("%d\n", (val + 5) / 10);
+}
+
+void ethernut5_print_voltage(void)
+{
+	int val;
+
+	/* Read ADC value from divider and return voltage. */
+	val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VAUX);
+	/* Resistors are 100k and 12.1k */
+	val += 5;
+	val *= 180948;
+	val /= 100000;
+	val++;
+	/* Calculation was done in 0.1V units. */
+	printf("%d\n", (val + 5) / 10);
+}
+
+/*
+ * Process the board specific 'pwrman' command.
+ */
+int do_pwrman(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	u8 val;
+	int i;
+
+	if (argc == 1) {
+		ethernut5_print_power();
+	} else if (argc == 2 && strcmp(argv[1], "reset") == 0) {
+		at91_set_pio_output(AT91_PIO_PORTB, 8, 1);
+		udelay(100);
+		at91_set_pio_output(AT91_PIO_PORTB, 8, 0);
+		udelay(100000);
+	} else if (argc == 2 && strcmp(argv[1], "temp") == 0) {
+		ethernut5_print_celsius();
+	} else if (argc == 2 && strcmp(argv[1], "vaux") == 0) {
+		ethernut5_print_voltage();
+	} else if (argc == 2 && strcmp(argv[1], "version") == 0) {
+		ethernut5_print_version();
+	} else if (strcmp(argv[1], "led") == 0) {
+		/* Control the green status LED. Blink frequency unit
+		** is 0.1s, very roughly. */
+		if (argc == 2) {
+			/* No more arguments, output current settings. */
+			val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL);
+			printf("led %u %u\n", val >> 4, val & 15);
+		} else {
+			/* First argument specifies the on-time. */
+			val = (u8) simple_strtoul(argv[2], NULL, 0);
+			val <<= 4;
+			if (argc > 3) {
+				/* Second argument specifies the off-time. */
+				val |= (u8) (simple_strtoul(argv[3], NULL, 0)
+						& 15);
+			}
+			/* Update the LED control register. */
+			i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL, val);
+		}
+	} else {
+		/* We expect a list of features followed an optional status. */
+		argc--;
+		i = feature_flags(&argv[1], argc, &val);
+		if (argc == i) {
+			/* We got a list only, print status. */
+			val &= i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_STA);
+			if (val) {
+				if (i > 1)
+					print_flagged_features(val);
+				printf("active\n");
+			} else {
+				printf("inactive\n");
+			}
+		} else {
+			/* More arguments. */
+			if (i == 0) {
+				/* No given feature, use despensibles. */
+				val = PWRMAN_DISPENSIBLE;
+			}
+			if (strcmp(argv[i + 1], "on") == 0) {
+				/* Enable features. */
+				i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA,
+						val);
+			} else if (strcmp(argv[i + 1], "off") == 0) {
+				/* Disable features. */
+				i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS,
+						val);
+			} else {
+				printf("Bad parameter %s\n", argv[i + 1]);
+				return 1;
+			}
+		}
+	}
+	return 0;
+}
+
+U_BOOT_CMD(
+	pwrman,	CONFIG_SYS_MAXARGS, 1, do_pwrman,
+	"power management",
+		   "- print settings\n"
+	"pwrman feature ...\n"
+	"       - print status\n"
+	"pwrman [feature ...] on|off\n"
+	"       - enable/disable specified or all dispensible features\n"
+	"pwrman led [on-time [off-time]]\n"
+	"       - print or set led blink timer\n"
+	"pwrman temp\n"
+	"       - print board temperature (Celsius)\n"
+	"pwrman vaux\n"
+	"       - print auxiliary input voltage\n"
+	"pwrman reset\n"
+	"       - reset power management controller\n"
+	"pwrman version\n"
+	"       - print firmware version\n"
+	"\n"
+	"        features, (*)=dispensible:\n"
+	"          board  - 1.8V and 3.3V supply\n"
+	"          vbin   - supply via USB device connector\n"
+	"          vbout  - USB host connector supply(*)\n"
+	"          mmc    - MMC slot supply(*)\n"
+	"          rs232  - RS232 driver\n"
+	"          ethclk - Ethernet PHY clock(*)\n"
+	"          ethrst - Ethernet PHY reset\n"
+	"          wakeup - RTC alarm"
+);
+#endif /* CONFIG_CMD_BSP */
diff --git a/roms/u-boot/board/egnite/ethernut5/ethernut5_pwrman.h b/roms/u-boot/board/egnite/ethernut5/ethernut5_pwrman.h
new file mode 100644
index 000000000..103f55832
--- /dev/null
+++ b/roms/u-boot/board/egnite/ethernut5/ethernut5_pwrman.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * egnite GmbH <info@egnite.de>
+ */
+
+/*
+ * Ethernut 5 power management support
+ *
+ * For additional information visit the project home page at
+ * http://www.ethernut.de/
+ */
+
+/* I2C address of the PMC */
+#define PWRMAN_I2C_ADDR 0x22
+
+/* PMC registers */
+#define PWRMAN_REG_VERS		0	/* Version register */
+#define PWRMAN_REG_STA		1	/* Feature status register */
+#define PWRMAN_REG_ENA		2	/* Feature enable register */
+#define PWRMAN_REG_DIS		3	/* Feature disable register */
+#define PWRMAN_REG_TEMP		4	/* Board temperature */
+#define PWRMAN_REG_VAUX		6	/* Auxiliary input voltage */
+#define PWRMAN_REG_LEDCTL	8	/* LED blinking timer. */
+
+/* Feature flags used in status, enable and disable registers */
+#define PWRMAN_BOARD	0x01	/* 1.8V and 3.3V supply */
+#define PWRMAN_VBIN	0x02	/* VBUS input at device connector */
+#define PWRMAN_VBOUT	0x04	/* VBUS output at host connector */
+#define PWRMAN_MMC	0x08	/* Memory card supply */
+#define PWRMAN_RS232	0x10	/* RS-232 driver shutdown */
+#define PWRMAN_ETHCLK	0x20	/* Ethernet clock enable */
+#define PWRMAN_ETHRST	0x40	/* Ethernet PHY reset */
+#define PWRMAN_WAKEUP	0x80	/* RTC wake-up */
+
+/* Features, which are not essential to keep u-boot alive */
+#define PWRMAN_DISPENSIBLE	(PWRMAN_VBOUT | PWRMAN_MMC | PWRMAN_ETHCLK)
+
+/* Enable Ethernut 5 power management. */
+extern void ethernut5_power_init(void);
+
+/* Reset Ethernet PHY. */
+extern void ethernut5_phy_reset(void);
+
+extern void ethernut5_print_version(void);
+
+#ifdef CONFIG_CMD_BSP
+extern void ethernut5_print_power(void);
+extern void ethernut5_print_celsius(void);
+extern void ethernut5_print_voltage(void);
+#endif
diff --git a/roms/u-boot/board/elgin/elgin_rv1108/Kconfig b/roms/u-boot/board/elgin/elgin_rv1108/Kconfig
new file mode 100644
index 000000000..be9243164
--- /dev/null
+++ b/roms/u-boot/board/elgin/elgin_rv1108/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ELGIN_RV1108
+
+config SYS_BOARD
+	default "elgin_rv1108"
+
+config SYS_VENDOR
+	default "elgin"
+
+config SYS_CONFIG_NAME
+	default "elgin_rv1108"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/elgin/elgin_rv1108/MAINTAINERS b/roms/u-boot/board/elgin/elgin_rv1108/MAINTAINERS
new file mode 100644
index 000000000..774749016
--- /dev/null
+++ b/roms/u-boot/board/elgin/elgin_rv1108/MAINTAINERS
@@ -0,0 +1,6 @@
+ELGIN-RV1108
+M:      Otavio Salvador <otavio@ossystems.com.br>
+S:      Maintained
+F:      board/elgin/elgin_rv1108
+F:      include/configs/elgin_rv1108.h
+F:      configs/elgin-rv1108_defconfig
diff --git a/roms/u-boot/board/elgin/elgin_rv1108/Makefile b/roms/u-boot/board/elgin/elgin_rv1108/Makefile
new file mode 100644
index 000000000..382218006
--- /dev/null
+++ b/roms/u-boot/board/elgin/elgin_rv1108/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= elgin_rv1108.o
diff --git a/roms/u-boot/board/elgin/elgin_rv1108/elgin_rv1108.c b/roms/u-boot/board/elgin/elgin_rv1108/elgin_rv1108.c
new file mode 100644
index 000000000..eb7a322d8
--- /dev/null
+++ b/roms/u-boot/board/elgin/elgin_rv1108/elgin_rv1108.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C)Copyright 2016 Rockchip Electronics Co., Ltd
+ * Authors: Andy Yan <andy.yan@rock-chips.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <syscon.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rv1108.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	struct rv1108_grf *grf;
+	enum {
+		GPIO3C3_SHIFT           = 6,
+		GPIO3C3_MASK            = 3 << GPIO3C3_SHIFT,
+
+		GPIO3C2_SHIFT           = 4,
+		GPIO3C2_MASK            = 3 << GPIO3C2_SHIFT,
+
+		GPIO2D2_SHIFT		= 4,
+		GPIO2D2_MASK		= 3 << GPIO2D2_SHIFT,
+		GPIO2D2_GPIO            = 0,
+		GPIO2D2_UART2_SOUT_M0,
+
+		GPIO2D1_SHIFT		= 2,
+		GPIO2D1_MASK		= 3 << GPIO2D1_SHIFT,
+		GPIO2D1_GPIO            = 0,
+		GPIO2D1_UART2_SIN_M0,
+	};
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+	/* Elgin board use UART2 m0 for debug*/
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D2_MASK | GPIO2D1_MASK,
+		     GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
+		     GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
+	rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
+
+	return 0;
+}
+
+#define MODEM_ENABLE_GPIO 111
+
+int rk_board_late_init(void)
+{
+	gpio_request(MODEM_ENABLE_GPIO, "modem_enable");
+	gpio_direction_output(MODEM_ENABLE_GPIO, 0);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = 0x8000000;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = 0x60000000;
+	gd->bd->bi_dram[0].size = 0x8000000;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/embest/mx6boards/Kconfig b/roms/u-boot/board/embest/mx6boards/Kconfig
new file mode 100644
index 000000000..24d01f226
--- /dev/null
+++ b/roms/u-boot/board/embest/mx6boards/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_EMBESTMX6BOARDS
+
+config SYS_BOARD
+	default "mx6boards"
+
+config SYS_VENDOR
+	default "embest"
+
+config SYS_CONFIG_NAME
+	default "embestmx6boards"
+
+endif
diff --git a/roms/u-boot/board/embest/mx6boards/MAINTAINERS b/roms/u-boot/board/embest/mx6boards/MAINTAINERS
new file mode 100644
index 000000000..02756c58b
--- /dev/null
+++ b/roms/u-boot/board/embest/mx6boards/MAINTAINERS
@@ -0,0 +1,8 @@
+MX6BOARDS BOARD
+M:	Eric Bénard <eric@eukrea.com>
+S:	Maintained
+F:	board/embest/mx6boards/
+F:	include/configs/embestmx6boards.h
+F:	configs/marsboard_defconfig
+F:	configs/riotboard_defconfig
+F:	configs/riotboard_spl_defconfig
diff --git a/roms/u-boot/board/embest/mx6boards/Makefile b/roms/u-boot/board/embest/mx6boards/Makefile
new file mode 100644
index 000000000..a032a3df9
--- /dev/null
+++ b/roms/u-boot/board/embest/mx6boards/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+
+obj-y  := mx6boards.o
diff --git a/roms/u-boot/board/embest/mx6boards/mx6boards.c b/roms/u-boot/board/embest/mx6boards/mx6boards.c
new file mode 100644
index 000000000..dda8502c6
--- /dev/null
+++ b/roms/u-boot/board/embest/mx6boards/mx6boards.c
@@ -0,0 +1,502 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Eukréa Electromatique
+ * Author: Eric Bénard <eric@eukrea.com>
+ *         Fabio Estevam <fabio.estevam@freescale.com>
+ *         Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * based on sabresd.c which is :
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * and on hummingboard.c which is :
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/video.h>
+#include <i2c.h>
+#include <input.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST |			\
+	PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |		\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+static int board_type = -1;
+#define BOARD_IS_MARSBOARD	0
+#define BOARD_IS_RIOTBOARD	1
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+iomux_v3_cfg_t const enet_pads[] = {
+	/* AR8035 PHY Reset */
+	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+	/* AR8035 PHY Interrupt */
+	MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+	/* Reset AR8035 PHY */
+	gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
+	mdelay(2);
+	gpio_set_value(IMX_GPIO_NR(3, 31), 1);
+}
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	/* from linux/arch/arm/mach-imx/mach-imx6q.c :
+	 * Ar803x phy SmartEEE feature cause link status generates glitch,
+	 * which cause ethernet link down/up issue, so disable SmartEEE
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
+}
+
+static void setup_spi(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
+				| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
+				| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(5, 27)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
+				| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
+				| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(5, 26)
+	}
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
+				| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
+				| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
+				| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
+				| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+struct i2c_pads_info i2c_pad_info3 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
+				| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
+				| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(1, 5)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
+				| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
+				| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(1, 6)
+	}
+};
+
+iomux_v3_cfg_t const tft_pads_riot[] = {
+	/* LCD_PWR_EN */
+	MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* TOUCH_INT */
+	MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* LED_PWR_EN */
+	MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* BL LEVEL */
+	MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const tft_pads_mars[] = {
+	/* LCD_PWR_EN */
+	MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* TOUCH_INT */
+	MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* LED_PWR_EN */
+	MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* BL LEVEL (PWM4) */
+	MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)
+				IOMUXC_BASE_ADDR;
+	setbits_le32(&iomux->gpr[2],
+		     IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
+	/* set backlight level to ON */
+	if (board_type == BOARD_IS_RIOTBOARD)
+		gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
+	else if (board_type == BOARD_IS_MARSBOARD)
+		gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
+}
+
+static void disable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* set backlight level to OFF */
+	if (board_type == BOARD_IS_RIOTBOARD)
+		gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
+	else if (board_type == BOARD_IS_MARSBOARD)
+		gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
+
+	clrbits_le32(&iomux->gpr[2],
+		     IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	disable_lvds(dev);
+	imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+	return (0 == i2c_set_bus_num(dev->bus)) &&
+		(0 == i2c_probe(dev->addr));
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 2,
+	.addr	= 0x1,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.detect	= detect_i2c,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "LCD8000-97C",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 100,
+		.right_margin   = 200,
+		.upper_margin   = 10,
+		.lower_margin   = 20,
+		.hsync_len      = 20,
+		.vsync_len      = 8,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	/* Turn on LDB0, IPU,IPU DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR3,
+		     MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+	/* set LDB0 clk select to 011/011 */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
+			(3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+
+	setbits_le32(&mxc_ccm->cscmr2,
+		     MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+	setbits_le32(&mxc_ccm->chsccdr,
+		     (CHSCCDR_CLK_SEL_LDB_DI0
+		     << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+	     | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+	     | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+	     | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	clrsetbits_le32(&iomux->gpr[3],
+			IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+			IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
+			IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+			<< IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_early_init_f(void)
+{
+	u32 cputype = cpu_type(get_cpu_rev());
+
+	switch (cputype) {
+	case MXC_CPU_MX6SOLO:
+		board_type = BOARD_IS_RIOTBOARD;
+		break;
+	case MXC_CPU_MX6D:
+		board_type = BOARD_IS_MARSBOARD;
+		break;
+	}
+
+	setup_iomux_uart();
+
+	if (board_type == BOARD_IS_RIOTBOARD)
+		imx_iomux_v3_setup_multiple_pads(
+			tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
+	else if (board_type == BOARD_IS_MARSBOARD)
+		imx_iomux_v3_setup_multiple_pads(
+			tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
+#if defined(CONFIG_VIDEO_IPUV3)
+	/* power ON LCD */
+	gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
+	/* touch interrupt is an input */
+	gpio_direction_input(IMX_GPIO_NR(6, 14));
+	/* power ON backlight */
+	gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
+	/* set backlight level to off */
+	if (board_type == BOARD_IS_RIOTBOARD)
+		gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
+	else if (board_type == BOARD_IS_MARSBOARD)
+		gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
+	setup_display();
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	/* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	/* i2c2 : HDMI EDID */
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+	/* i2c3 : LVDS, Expansion connector */
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode riotboard_boot_modes[] = {
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{NULL,	 0},
+};
+static const struct boot_mode marsboard_boot_modes[] = {
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	if (board_type == BOARD_IS_RIOTBOARD)
+		add_board_boot_modes(riotboard_boot_modes);
+	else if (board_type == BOARD_IS_RIOTBOARD)
+		add_board_boot_modes(marsboard_boot_modes);
+#endif
+	setup_iomux_enet();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: ");
+	if (board_type == BOARD_IS_MARSBOARD)
+		puts("MarSBoard\n");
+	else if (board_type == BOARD_IS_RIOTBOARD)
+		puts("RIoTboard\n");
+	else
+		printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+
+void board_init_f(ulong dummy)
+{
+	u32 cputype = cpu_type(get_cpu_rev());
+
+	switch (cputype) {
+	case MXC_CPU_MX6SOLO:
+		board_type = BOARD_IS_RIOTBOARD;
+		break;
+	case MXC_CPU_MX6D:
+		board_type = BOARD_IS_MARSBOARD;
+		break;
+	}
+	arch_cpu_init();
+
+	/* setup GP timer */
+	timer_init();
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	setup_iomux_uart();
+	preloader_console_init();
+#endif
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = BOOT_DEVICE_MMC1;
+}
+
+/*
+ * In order to jump to standard u-boot shell, you have to connect pin 5 of J13
+ * to pin 3 (ground).
+ */
+int spl_start_uboot(void)
+{
+	int gpio_key = IMX_GPIO_NR(4, 16);
+
+	gpio_direction_input(gpio_key);
+	if (gpio_get_value(gpio_key) == 0)
+		return 1;
+	else
+		return 0;
+}
+
+#endif
diff --git a/roms/u-boot/board/emulation/Kconfig b/roms/u-boot/board/emulation/Kconfig
new file mode 100644
index 000000000..f821458fa
--- /dev/null
+++ b/roms/u-boot/board/emulation/Kconfig
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+
+if VENDOR_EMULATION
+
+choice
+	prompt "Mainboard model"
+
+config TARGET_QEMU_X86
+	bool "QEMU x86"
+	help
+	  This is the QEMU emulated x86 board. U-Boot supports running
+	  as a coreboot payload as well as bare boot without coreboot.
+	  There are two types of x86 boards supported by QEMU which are
+	  supported by U-Boot. They are via QEMU '-M pc', an i440FX/PIIX
+	  chipset platform and '-M q35', a Q35/ICH9 chipset platform.
+
+config TARGET_QEMU_X86_64
+	bool "QEMU x86 64-bit"
+	help
+	  This is the QEMU emulated x86 64-bit board. With this config
+	  U-Boot is built as a 64-bit binary. This allows testing while
+	  this feature is being completed.
+
+endchoice
+
+source "board/emulation/qemu-x86/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/emulation/common/Kconfig b/roms/u-boot/board/emulation/common/Kconfig
new file mode 100644
index 000000000..4c15c8bcb
--- /dev/null
+++ b/roms/u-boot/board/emulation/common/Kconfig
@@ -0,0 +1,15 @@
+config MTDPARTS_NOR0
+	string "mtd boot partition for nor0"
+	default "64m(u-boot)" if TARGET_QEMU_ARM_64BIT && !TFABOOT
+	depends on SYS_MTDPARTS_RUNTIME
+	help
+	  This define the partition of nor0 used to build mtparts dynamically
+	  for boot from nor0.
+
+config MTDPARTS_NOR1
+	string "mtd u-boot env partition for nor1"
+	default "64m(u-boot-env)" if TARGET_QEMU_ARM_64BIT && !TFABOOT
+	depends on SYS_MTDPARTS_RUNTIME
+	help
+	  This define the partition of nor1 used to build mtparts dynamically
+	  for the u-boot env stored on nor1.
diff --git a/roms/u-boot/board/emulation/common/Makefile b/roms/u-boot/board/emulation/common/Makefile
new file mode 100644
index 000000000..7ed447a69
--- /dev/null
+++ b/roms/u-boot/board/emulation/common/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += qemu_mtdparts.o
+obj-$(CONFIG_SET_DFU_ALT_INFO) += qemu_dfu.o
+obj-$(CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT) += qemu_capsule.o
diff --git a/roms/u-boot/board/emulation/common/qemu_capsule.c b/roms/u-boot/board/emulation/common/qemu_capsule.c
new file mode 100644
index 000000000..6b8a87022
--- /dev/null
+++ b/roms/u-boot/board/emulation/common/qemu_capsule.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Linaro Limited
+ */
+
+#include <common.h>
+#include <efi_api.h>
+#include <efi_loader.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
+{
+	const void *fdt_blob = gd->fdt_blob;
+	const void *blob;
+	const char *cnode_name = "capsule-key";
+	const char *snode_name = "signature";
+	int sig_node;
+	int len;
+
+	sig_node = fdt_subnode_offset(fdt_blob, 0, snode_name);
+	if (sig_node < 0) {
+		EFI_PRINT("Unable to get signature node offset\n");
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	blob = fdt_getprop(fdt_blob, sig_node, cnode_name, &len);
+
+	if (!blob || len < 0) {
+		EFI_PRINT("Unable to get capsule-key value\n");
+		*pkey = NULL;
+		*pkey_len = 0;
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	*pkey = (void *)blob;
+	*pkey_len = len;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/emulation/common/qemu_dfu.c b/roms/u-boot/board/emulation/common/qemu_dfu.c
new file mode 100644
index 000000000..62234a764
--- /dev/null
+++ b/roms/u-boot/board/emulation/common/qemu_dfu.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Linaro Limited
+ */
+
+#include <common.h>
+#include <dfu.h>
+#include <env.h>
+#include <memalign.h>
+#include <mtd.h>
+
+#define DFU_ALT_BUF_LEN		SZ_1K
+
+static void board_get_alt_info(struct mtd_info *mtd, char *buf)
+{
+	struct mtd_info *part;
+	bool first = true;
+	const char *name;
+	int len, partnum = 0;
+
+	name = mtd->name;
+	len = strlen(buf);
+
+	if (buf[0] != '\0')
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, "&");
+	len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
+			"mtd %s=", name);
+
+	list_for_each_entry(part, &mtd->partitions, node) {
+		partnum++;
+		if (!first)
+			len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, ";");
+		first = false;
+
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
+				"%s part %d",
+				part->name, partnum);
+	}
+}
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+	struct mtd_info *mtd;
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+
+	if (env_get("dfu_alt_info"))
+		return;
+
+	memset(buf, 0, sizeof(buf));
+
+	/*
+	 * Currently dfu_alt_info is needed on Qemu ARM64 for
+	 * capsule updates
+	*/
+	if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT) &&
+	    IS_ENABLED(CONFIG_TARGET_QEMU_ARM_64BIT)) {
+		/* probe all MTD devices */
+		mtd_probe_devices();
+
+		mtd = get_mtd_device_nm("nor0");
+		if (!IS_ERR_OR_NULL(mtd))
+			board_get_alt_info(mtd, buf);
+	}
+
+	env_set("dfu_alt_info", buf);
+	printf("dfu_alt_info set\n");
+}
diff --git a/roms/u-boot/board/emulation/common/qemu_mtdparts.c b/roms/u-boot/board/emulation/common/qemu_mtdparts.c
new file mode 100644
index 000000000..60212e97a
--- /dev/null
+++ b/roms/u-boot/board/emulation/common/qemu_mtdparts.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Linaro Limited
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mtd.h>
+
+#include <linux/string.h>
+
+#define MTDPARTS_LEN		256
+#define MTDIDS_LEN		128
+
+static void board_get_mtdparts(const char *dev, const char *partition,
+			       char *mtdids, char *mtdparts)
+{
+	/* mtdids: "<dev>=<dev>, ...." */
+	if (mtdids[0] != '\0')
+		strcat(mtdids, ",");
+	strcat(mtdids, dev);
+	strcat(mtdids, "=");
+	strcat(mtdids, dev);
+
+	/* mtdparts: "mtdparts=<dev>:<mtdparts_<dev>>;..." */
+	if (mtdparts[0] != '\0')
+		strncat(mtdparts, ";", MTDPARTS_LEN);
+	else
+		strcat(mtdparts, "mtdparts=");
+
+	strncat(mtdparts, dev, MTDPARTS_LEN);
+	strncat(mtdparts, ":", MTDPARTS_LEN);
+	strncat(mtdparts, partition, MTDPARTS_LEN);
+}
+
+void board_mtdparts_default(const char **mtdids, const char **mtdparts)
+{
+	struct mtd_info *mtd;
+	struct udevice *dev;
+	const char *mtd_partition;
+	static char parts[3 * MTDPARTS_LEN + 1];
+	static char ids[MTDIDS_LEN + 1];
+	static bool mtd_initialized;
+
+	if (mtd_initialized) {
+		*mtdids = ids;
+		*mtdparts = parts;
+		return;
+	}
+
+	memset(parts, 0, sizeof(parts));
+	memset(ids, 0, sizeof(ids));
+
+	/* Currently mtdparts is needed on Qemu ARM64 for capsule updates */
+	if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT) &&
+	    IS_ENABLED(CONFIG_TARGET_QEMU_ARM_64BIT)) {
+		/* probe all MTD devices */
+		for (uclass_first_device(UCLASS_MTD, &dev); dev;
+		     uclass_next_device(&dev)) {
+			debug("mtd device = %s\n", dev->name);
+		}
+
+		mtd = get_mtd_device_nm("nor0");
+		if (!IS_ERR_OR_NULL(mtd)) {
+			mtd_partition = CONFIG_MTDPARTS_NOR0;
+			board_get_mtdparts("nor0", mtd_partition, ids, parts);
+			put_mtd_device(mtd);
+		}
+
+		mtd = get_mtd_device_nm("nor1");
+		if (!IS_ERR_OR_NULL(mtd)) {
+			mtd_partition = CONFIG_MTDPARTS_NOR1;
+			board_get_mtdparts("nor1", mtd_partition, ids, parts);
+			put_mtd_device(mtd);
+		}
+	}
+
+	mtd_initialized = true;
+	*mtdids = ids;
+	*mtdparts = parts;
+	debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts);
+}
diff --git a/roms/u-boot/board/emulation/qemu-arm/Kconfig b/roms/u-boot/board/emulation/qemu-arm/Kconfig
new file mode 100644
index 000000000..95dbefa78
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-arm/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_QEMU_ARM_32BIT || TARGET_QEMU_ARM_64BIT
+
+config SYS_TEXT_BASE
+	default 0x00000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select CMD_QFW
+	select QFW_MMIO
+	imply VIRTIO_MMIO
+	imply VIRTIO_PCI
+	imply VIRTIO_NET
+	imply VIRTIO_BLK
+
+endif
+
+if TARGET_QEMU_ARM_64BIT && !TFABOOT
+config BOARD_SPECIFIC_OPTIONS
+	imply SYS_MTDPARTS_RUNTIME
+	imply SET_DFU_ALT_INFO
+
+source "board/emulation/common/Kconfig"
+endif
diff --git a/roms/u-boot/board/emulation/qemu-arm/MAINTAINERS b/roms/u-boot/board/emulation/qemu-arm/MAINTAINERS
new file mode 100644
index 000000000..e757ffc64
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-arm/MAINTAINERS
@@ -0,0 +1,7 @@
+QEMU ARM 'VIRT' BOARD
+M:	Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
+S:	Maintained
+F:	board/emulation/qemu-arm/
+F:	include/configs/qemu-arm.h
+F:	configs/qemu_arm_defconfig
+F:	configs/qemu_arm64_defconfig
diff --git a/roms/u-boot/board/emulation/qemu-arm/Makefile b/roms/u-boot/board/emulation/qemu-arm/Makefile
new file mode 100644
index 000000000..a22d1237f
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-arm/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	+= qemu-arm.o
diff --git a/roms/u-boot/board/emulation/qemu-arm/qemu-arm.c b/roms/u-boot/board/emulation/qemu-arm/qemu-arm.c
new file mode 100644
index 000000000..aa68bef46
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-arm/qemu-arm.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Tuomas Tynkkynen
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <log.h>
+#include <virtio_types.h>
+#include <virtio.h>
+
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+
+static struct mm_region qemu_arm64_mem_map[] = {
+	{
+		/* Flash */
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 0x08000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* Lowmem peripherals */
+		.virt = 0x08000000UL,
+		.phys = 0x08000000UL,
+		.size = 0x38000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* RAM */
+		.virt = 0x40000000UL,
+		.phys = 0x40000000UL,
+		.size = 255UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* Highmem PCI-E ECAM memory area */
+		.virt = 0x4010000000ULL,
+		.phys = 0x4010000000ULL,
+		.size = 0x10000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* Highmem PCI-E MMIO memory area */
+		.virt = 0x8000000000ULL,
+		.phys = 0x8000000000ULL,
+		.size = 0x8000000000ULL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = qemu_arm64_mem_map;
+#endif
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	/*
+	 * Make sure virtio bus is enumerated so that peripherals
+	 * on the virtio bus can be discovered by their drivers
+	 */
+	virtio_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+void *board_fdt_blob_setup(void)
+{
+	/* QEMU loads a generated DTB for us at the start of RAM. */
+	return (void *)CONFIG_SYS_SDRAM_BASE;
+}
+
+void enable_caches(void)
+{
+	 icache_enable();
+	 dcache_enable();
+}
+
+#if defined(CONFIG_EFI_RNG_PROTOCOL)
+#include <efi_loader.h>
+#include <efi_rng.h>
+
+#include <dm/device-internal.h>
+
+efi_status_t platform_get_rng_device(struct udevice **dev)
+{
+	int ret;
+	efi_status_t status = EFI_DEVICE_ERROR;
+	struct udevice *bus, *devp;
+
+	for (uclass_first_device(UCLASS_VIRTIO, &bus); bus;
+	     uclass_next_device(&bus)) {
+		for (device_find_first_child(bus, &devp); devp;
+		     device_find_next_child(&devp)) {
+			if (device_get_uclass_id(devp) == UCLASS_RNG) {
+				*dev = devp;
+				status = EFI_SUCCESS;
+				break;
+			}
+		}
+	}
+
+	if (status != EFI_SUCCESS) {
+		debug("No rng device found\n");
+		return EFI_DEVICE_ERROR;
+	}
+
+	if (*dev) {
+		ret = device_probe(*dev);
+		if (ret)
+			return EFI_DEVICE_ERROR;
+	} else {
+		debug("Couldn't get child device\n");
+		return EFI_DEVICE_ERROR;
+	}
+
+	return EFI_SUCCESS;
+}
+#endif /* CONFIG_EFI_RNG_PROTOCOL */
+
+#ifdef CONFIG_ARM64
+#define __W	"w"
+#else
+#define __W
+#endif
+
+u8 flash_read8(void *addr)
+{
+	u8 ret;
+
+	asm("ldrb %" __W "0, %1" : "=r"(ret) : "m"(*(u8 *)addr));
+	return ret;
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 ret;
+
+	asm("ldrh %" __W "0, %1" : "=r"(ret) : "m"(*(u16 *)addr));
+	return ret;
+}
+
+u32 flash_read32(void *addr)
+{
+	u32 ret;
+
+	asm("ldr %" __W "0, %1" : "=r"(ret) : "m"(*(u32 *)addr));
+	return ret;
+}
+
+void flash_write8(u8 value, void *addr)
+{
+	asm("strb %" __W "1, %0" : "=m"(*(u8 *)addr) : "r"(value));
+}
+
+void flash_write16(u16 value, void *addr)
+{
+	asm("strh %" __W "1, %0" : "=m"(*(u16 *)addr) : "r"(value));
+}
+
+void flash_write32(u32 value, void *addr)
+{
+	asm("str %" __W "1, %0" : "=m"(*(u32 *)addr) : "r"(value));
+}
diff --git a/roms/u-boot/board/emulation/qemu-ppce500/Kconfig b/roms/u-boot/board/emulation/qemu-ppce500/Kconfig
new file mode 100644
index 000000000..1c5aa18aa
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-ppce500/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_QEMU_PPCE500
+
+config SYS_BOARD
+	default "qemu-ppce500"
+
+config SYS_VENDOR
+	default "emulation"
+
+config SYS_CONFIG_NAME
+	default "qemu-ppce500"
+
+config PLATFORM_BUS_MAP_ADDR
+	hex
+	default 0xf0000000
+	help
+	  The QEMU platform bus base mapped address in the virtual memory space.
+
+endif
diff --git a/roms/u-boot/board/emulation/qemu-ppce500/MAINTAINERS b/roms/u-boot/board/emulation/qemu-ppce500/MAINTAINERS
new file mode 100644
index 000000000..7317983d6
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-ppce500/MAINTAINERS
@@ -0,0 +1,7 @@
+QEMU-PPCE500 BOARD
+M:	Alexander Graf <agraf@csgraf.de>
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/emulation/qemu-ppce500/
+F:	include/configs/qemu-ppce500.h
+F:	configs/qemu-ppce500_defconfig
diff --git a/roms/u-boot/board/emulation/qemu-ppce500/Makefile b/roms/u-boot/board/emulation/qemu-ppce500/Makefile
new file mode 100644
index 000000000..817d06d84
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-ppce500/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= qemu-ppce500.o
diff --git a/roms/u-boot/board/emulation/qemu-ppce500/qemu-ppce500.c b/roms/u-boot/board/emulation/qemu-ppce500/qemu-ppce500.c
new file mode 100644
index 000000000..924cc02c4
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-ppce500/qemu-ppce500.c
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <pci.h>
+#include <time.h>
+#include <dm/simple_bus.h>
+#include <dm/uclass-internal.h>
+#include <asm/global_data.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <malloc.h>
+#include <virtio_types.h>
+#include <virtio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void *get_fdt_virt(void)
+{
+	if (gd->flags & GD_FLG_RELOC)
+		return (void *)gd->fdt_blob;
+	else
+		return (void *)CONFIG_SYS_TMPVIRT;
+}
+
+static uint64_t get_fdt_phys(void)
+{
+	return (uint64_t)(uintptr_t)gd->fdt_blob;
+}
+
+static void map_fdt_as(int esel)
+{
+	u32 mas0, mas1, mas2, mas3, mas7;
+	uint64_t fdt_phys = get_fdt_phys();
+	unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful;
+	unsigned long fdt_virt_tlb = (ulong)get_fdt_virt() & ~0xffffful;
+
+	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(esel);
+	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
+	mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0);
+	mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR);
+	mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb);
+
+	write_tlb(mas0, mas1, mas2, mas3, mas7);
+}
+
+uint64_t get_phys_ccsrbar_addr_early(void)
+{
+	void *fdt = get_fdt_virt();
+	uint64_t r;
+	int size, node;
+	u32 naddr;
+	const fdt32_t *prop;
+
+	/*
+	 * To be able to read the FDT we need to create a temporary TLB
+	 * map for it.
+	 */
+	map_fdt_as(10);
+	node = fdt_path_offset(fdt, "/soc");
+	naddr = fdt_address_cells(fdt, node);
+	prop = fdt_getprop(fdt, node, "ranges", &size);
+	r = fdt_translate_address(fdt, node, prop + naddr);
+	disable_tlb(10);
+
+	return r;
+}
+
+int checkboard(void)
+{
+	return 0;
+}
+
+static int pci_map_region(phys_addr_t paddr, phys_size_t size, ulong *pmap_addr)
+{
+	ulong map_addr;
+
+	if (!pmap_addr)
+		return 0;
+
+	map_addr = *pmap_addr;
+
+	/* Align map_addr */
+	map_addr += size - 1;
+	map_addr &= ~(size - 1);
+
+	if (map_addr + size >= CONFIG_SYS_PCI_MAP_END)
+		return -1;
+
+	/* Map virtual memory for range */
+	assert(!tlb_map_range(map_addr, paddr, size, TLB_MAP_IO));
+	*pmap_addr = map_addr + size;
+
+	return 0;
+}
+
+static void platform_bus_map_region(ulong map_addr, phys_addr_t paddr,
+				    phys_size_t size)
+{
+	/* Align map_addr */
+	map_addr += size - 1;
+	map_addr &= ~(size - 1);
+
+	/* Map virtual memory for range */
+	assert(!tlb_map_range(map_addr, paddr, size, TLB_MAP_IO));
+}
+
+int misc_init_r(void)
+{
+	struct udevice *dev;
+	struct pci_region *io;
+	struct pci_region *mem;
+	struct pci_region *pre;
+	ulong map_addr;
+	int ret;
+
+	/* Ensure PCI is probed */
+	uclass_first_device(UCLASS_PCI, &dev);
+
+	pci_get_regions(dev, &io, &mem, &pre);
+
+	/* Start MMIO and PIO range maps above RAM */
+	map_addr = CONFIG_SYS_PCI_MAP_START;
+
+	/* Map MMIO range */
+	ret = pci_map_region(mem->phys_start, mem->size, &map_addr);
+	if (ret)
+		return ret;
+
+	/* Map PIO range */
+	ret = pci_map_region(io->phys_start, io->size, &map_addr);
+	if (ret)
+		return ret;
+
+	/*
+	 * Make sure virtio bus is enumerated so that peripherals
+	 * on the virtio bus can be discovered by their drivers.
+	 */
+	virtio_init();
+
+	/*
+	 * U-Boot is relocated to RAM already, let's delete the temporary FDT
+	 * virtual-physical mapping that was used in the pre-relocation phase.
+	 */
+	disable_tlb(find_tlb_idx((void *)CONFIG_SYS_TMPVIRT, 1));
+
+	/*
+	 * Detect the presence of the platform bus node, and
+	 * create a virtual memory mapping for it.
+	 */
+	for (ret = uclass_find_first_device(UCLASS_SIMPLE_BUS, &dev);
+	     dev;
+	     ret = uclass_find_next_device(&dev)) {
+		if (device_is_compatible(dev, "qemu,platform")) {
+			struct simple_bus_plat *plat = dev_get_uclass_plat(dev);
+
+			platform_bus_map_region(CONFIG_PLATFORM_BUS_MAP_ADDR,
+						plat->target, plat->size);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	void *fdt = get_fdt_virt();
+	int len = 0;
+	const uint64_t *prop;
+	int chosen;
+
+	chosen = fdt_path_offset(fdt, "/chosen");
+	if (chosen < 0) {
+		printf("Couldn't find /chosen node in fdt\n");
+		return -EIO;
+	}
+
+	/* -kernel boot */
+	prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len);
+	if (prop && (len >= 8))
+		env_set_hex("qemu_kernel_addr", *prop);
+
+	return 0;
+}
+
+static uint64_t get_linear_ram_size(void)
+{
+	void *fdt = get_fdt_virt();
+	const void *prop;
+	int memory;
+	int len;
+
+	memory = fdt_path_offset(fdt, "/memory");
+	prop = fdt_getprop(fdt, memory, "reg", &len);
+
+	if (prop && len >= 16)
+		return *(uint64_t *)(prop+8);
+
+	panic("Couldn't determine RAM size");
+}
+
+phys_size_t fsl_ddr_sdram_size(void)
+{
+	return get_linear_ram_size();
+}
+
+void init_tlbs(void)
+{
+	phys_size_t ram_size;
+
+	/*
+	 * Create a temporary AS=1 map for the fdt
+	 *
+	 * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves
+	 * which was only 4k big. This way we don't have to clear any other maps.
+	 */
+	map_fdt_as(0);
+
+	/* Fetch RAM size from the fdt */
+	ram_size = get_linear_ram_size();
+
+	/* And remove our fdt map again */
+	disable_tlb(0);
+
+	/* Create an internal map of manually created TLB maps */
+	init_used_tlb_cams();
+
+	/* Create a dynamic AS=0 CCSRBAR mapping */
+	assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+			      1024 * 1024, TLB_MAP_IO));
+
+	/* Create a RAM map that spans all accessible RAM */
+	setup_ddr_tlbs(ram_size >> 20);
+
+	/* Create a map for the TLB */
+	assert(!tlb_map_range((ulong)get_fdt_virt(), get_fdt_phys(),
+			      1024 * 1024, TLB_MAP_RAM));
+}
+
+static uint32_t get_cpu_freq(void)
+{
+	void *fdt = get_fdt_virt();
+	int cpus_node = fdt_path_offset(fdt, "/cpus");
+	int cpu_node = fdt_first_subnode(fdt, cpus_node);
+	const char *prop = "clock-frequency";
+	return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
+}
+
+void get_sys_info(sys_info_t *sys_info)
+{
+	int freq = get_cpu_freq();
+
+	memset(sys_info, 0, sizeof(sys_info_t));
+	sys_info->freq_systembus = freq;
+	sys_info->freq_ddrbus = freq;
+	sys_info->freq_processor[0] = freq;
+}
+
+int get_clocks(void)
+{
+	sys_info_t sys_info;
+
+	get_sys_info(&sys_info);
+
+	gd->cpu_clk = sys_info.freq_processor[0];
+	gd->bus_clk = sys_info.freq_systembus;
+	gd->mem_clk = sys_info.freq_ddrbus;
+	gd->arch.lbc_clk = sys_info.freq_ddrbus;
+
+	return 0;
+}
+
+unsigned long get_tbclk(void)
+{
+	void *fdt = get_fdt_virt();
+	int cpus_node = fdt_path_offset(fdt, "/cpus");
+	int cpu_node = fdt_first_subnode(fdt, cpus_node);
+	const char *prop = "timebase-frequency";
+	return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
+}
+
+/********************************************
+ * get_bus_freq
+ * return system bus freq in Hz
+ *********************************************/
+ulong get_bus_freq(ulong dummy)
+{
+	sys_info_t sys_info;
+	get_sys_info(&sys_info);
+	return sys_info.freq_systembus;
+}
+
+/*
+ * Return the number of cores on this SOC.
+ */
+int cpu_numcores(void)
+{
+	/*
+	 * The QEMU u-boot target only needs to drive the first core,
+	 * spinning and device tree nodes get driven by QEMU itself
+	 */
+	return 1;
+}
+
+/*
+ * Return a 32-bit mask indicating which cores are present on this SOC.
+ */
+u32 cpu_mask(void)
+{
+	return (1 << cpu_numcores()) - 1;
+}
+
+/**
+ * Return the virtual address of FDT that was passed by QEMU
+ *
+ * @return virtual address of FDT received from QEMU in r3 register
+ */
+void *board_fdt_blob_setup(void)
+{
+	return get_fdt_virt();
+}
+
+/* See CONFIG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */
+int get_serial_clock(void)
+{
+	return get_bus_freq(0);
+}
diff --git a/roms/u-boot/board/emulation/qemu-riscv/Kconfig b/roms/u-boot/board/emulation/qemu-riscv/Kconfig
new file mode 100644
index 000000000..0818048ba
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-riscv/Kconfig
@@ -0,0 +1,68 @@
+if TARGET_QEMU_VIRT
+
+config SYS_BOARD
+	default "qemu-riscv"
+
+config SYS_VENDOR
+	default "emulation"
+
+config SYS_CPU
+	default "generic"
+
+config SYS_CONFIG_NAME
+	default "qemu-riscv"
+
+config SYS_TEXT_BASE
+	default 0x81200000 if SPL
+	default 0x80000000 if !RISCV_SMODE
+	default 0x80200000 if RISCV_SMODE && ARCH_RV64I
+	default 0x80400000 if RISCV_SMODE && ARCH_RV32I
+
+config SPL_TEXT_BASE
+	default 0x80000000
+
+config SPL_OPENSBI_LOAD_ADDR
+	hex
+	default 0x81000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select GENERIC_RISCV
+	select SUPPORT_SPL
+	imply AHCI
+	imply SMP
+	imply BOARD_LATE_INIT
+	imply PCI_INIT_R
+	imply SPL_RAM_SUPPORT
+	imply SPL_RAM_DEVICE
+	imply CMD_PCI
+	imply CMD_POWEROFF
+	imply CMD_SCSI
+	imply CMD_PING
+	imply CMD_EXT2
+	imply CMD_EXT4
+	imply CMD_FAT
+	imply CMD_FS_GENERIC
+	imply DOS_PARTITION
+	imply ISO_PARTITION
+	imply EFI_PARTITION
+	imply SCSI_AHCI
+	imply AHCI_PCI
+	imply E1000
+	imply NVME
+	imply PCI
+	imply DM_PCI
+	imply PCIE_ECAM_GENERIC
+	imply SCSI
+	imply DM_SCSI
+	imply SYS_NS16550
+	imply SIFIVE_SERIAL
+	imply SYSRESET
+	imply SYSRESET_CMD_POWEROFF
+	imply SYSRESET_SYSCON
+	imply VIRTIO_MMIO
+	imply VIRTIO_PCI
+	imply VIRTIO_NET
+	imply VIRTIO_BLK
+
+endif
diff --git a/roms/u-boot/board/emulation/qemu-riscv/MAINTAINERS b/roms/u-boot/board/emulation/qemu-riscv/MAINTAINERS
new file mode 100644
index 000000000..78969ed6b
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-riscv/MAINTAINERS
@@ -0,0 +1,11 @@
+QEMU RISC-V 'VIRT' BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/emulation/qemu-riscv/
+F:	include/configs/qemu-riscv.h
+F:	configs/qemu-riscv32_defconfig
+F:	configs/qemu-riscv32_smode_defconfig
+F:	configs/qemu-riscv32_spl_defconfig
+F:	configs/qemu-riscv64_defconfig
+F:	configs/qemu-riscv64_smode_defconfig
+F:	configs/qemu-riscv64_spl_defconfig
diff --git a/roms/u-boot/board/emulation/qemu-riscv/Makefile b/roms/u-boot/board/emulation/qemu-riscv/Makefile
new file mode 100644
index 000000000..3f29b90a4
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-riscv/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y	+= qemu-riscv.o
diff --git a/roms/u-boot/board/emulation/qemu-riscv/qemu-riscv.c b/roms/u-boot/board/emulation/qemu-riscv/qemu-riscv.c
new file mode 100644
index 000000000..dcfd3f20b
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-riscv/qemu-riscv.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <image.h>
+#include <log.h>
+#include <spl.h>
+#include <init.h>
+#include <virtio_types.h>
+#include <virtio.h>
+
+int board_init(void)
+{
+	/*
+	 * Make sure virtio bus is enumerated so that peripherals
+	 * on the virtio bus can be discovered by their drivers
+	 */
+	virtio_init();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	ulong kernel_start;
+	ofnode chosen_node;
+	int ret;
+
+	chosen_node = ofnode_path("/chosen");
+	if (!ofnode_valid(chosen_node)) {
+		debug("No chosen node found, can't get kernel start address\n");
+		return 0;
+	}
+
+#ifdef CONFIG_ARCH_RV64I
+	ret = ofnode_read_u64(chosen_node, "riscv,kernel-start",
+			      (u64 *)&kernel_start);
+#else
+	ret = ofnode_read_u32(chosen_node, "riscv,kernel-start",
+			      (u32 *)&kernel_start);
+#endif
+	if (ret) {
+		debug("Can't find kernel start address in device tree\n");
+		return 0;
+	}
+
+	env_set_hex("kernel_start", kernel_start);
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL
+u32 spl_boot_device(void)
+{
+	/* RISC-V QEMU only supports RAM as SPL boot device */
+	return BOOT_DEVICE_RAM;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/emulation/qemu-x86/Kconfig b/roms/u-boot/board/emulation/qemu-x86/Kconfig
new file mode 100644
index 000000000..9bb8a726e
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-x86/Kconfig
@@ -0,0 +1,29 @@
+if TARGET_QEMU_X86 || TARGET_QEMU_X86_64
+
+config SYS_BOARD
+	default "qemu-x86"
+
+config SYS_VENDOR
+	default "emulation"
+
+config SYS_SOC
+	default "qemu"
+
+config SYS_CONFIG_NAME
+	default "qemu-x86"
+
+config SYS_TEXT_BASE
+	default 0xfff00000 if !SUPPORT_SPL
+	default 0x01110000 if SUPPORT_SPL
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select QEMU
+	select QFW_PIO
+	select BOARD_ROMSIZE_KB_1024
+	imply VIRTIO_PCI
+	imply VIRTIO_NET
+	imply VIRTIO_BLK
+
+endif
diff --git a/roms/u-boot/board/emulation/qemu-x86/MAINTAINERS b/roms/u-boot/board/emulation/qemu-x86/MAINTAINERS
new file mode 100644
index 000000000..9a99d38ca
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-x86/MAINTAINERS
@@ -0,0 +1,13 @@
+QEMU X86 BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/emulation/qemu-x86/
+F:	include/configs/qemu-x86.h
+F:	configs/qemu-x86_defconfig
+
+QEMU X86 64-bit BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/emulation/qemu-x86/
+F:	include/configs/qemu-x86.h
+F:	configs/qemu-x86_64_defconfig
diff --git a/roms/u-boot/board/emulation/qemu-x86/Makefile b/roms/u-boot/board/emulation/qemu-x86/Makefile
new file mode 100644
index 000000000..ff4aaa51c
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-x86/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y	+= qemu-x86.o
diff --git a/roms/u-boot/board/emulation/qemu-x86/qemu-x86.c b/roms/u-boot/board/emulation/qemu-x86/qemu-x86.c
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/roms/u-boot/board/emulation/qemu-x86/qemu-x86.c
diff --git a/roms/u-boot/board/engicam/common/Kconfig b/roms/u-boot/board/engicam/common/Kconfig
new file mode 100644
index 000000000..38328fd5e
--- /dev/null
+++ b/roms/u-boot/board/engicam/common/Kconfig
@@ -0,0 +1,8 @@
+config IMX6_ENGICAM_COMMON
+	bool "Engicam i.MX6 Common code"
+	depends on SPL && MX6
+	default y if TARGET_MX6Q_ENGICAM || TARGET_MX6UL_ENGICAM
+	help
+	  Common SPL and U-Boot proper code for Engicam i.MX6 targets.
+
+	  Enable it in board Kconfig if it uses i.MX6 variant Engicam boards.
diff --git a/roms/u-boot/board/engicam/common/Makefile b/roms/u-boot/board/engicam/common/Makefile
new file mode 100644
index 000000000..15f0eaa1e
--- /dev/null
+++ b/roms/u-boot/board/engicam/common/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2016 Amarula Solutions B.V.
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_IMX6_ENGICAM_COMMON) += spl.o
+else
+obj-$(CONFIG_IMX6_ENGICAM_COMMON) += board.o
+endif
diff --git a/roms/u-boot/board/engicam/common/board.c b/roms/u-boot/board/engicam/common/board.c
new file mode 100644
index 000000000..df9149e0d
--- /dev/null
+++ b/roms/u-boot/board/engicam/common/board.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <mmc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <watchdog.h>
+#include <asm/global_data.h>
+
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+static void mmc_late_init(void)
+{
+	char cmd[32];
+	char mmcblk[32];
+	u32 dev_no = mmc_get_env_dev();
+
+	env_set_ulong("mmcdev", dev_no);
+
+	/* Set mmcblk env */
+	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
+	env_set("mmcroot", mmcblk);
+
+	sprintf(cmd, "mmc dev %d", dev_no);
+	run_command(cmd, 0);
+}
+#endif
+
+enum engicam_boards {
+	IMX6Q_ICORE,
+	IMX6DL_ICORE,
+	IMX6Q_ICORE_MIPI,
+	IMX6DL_ICORE_MIPI,
+	IMX6Q_ICORE_RQS,
+	IMX6DL_ICORE_RQS,
+	IMX6UL_GEAM,
+	IMX6UL_ISIOT_EMMC,
+	IMX6UL_ISIOT_NAND,
+	ENGICAM_BOARDS,
+};
+
+static const char * const board_fdt_file[ENGICAM_BOARDS] = {
+	[IMX6Q_ICORE] = "imx6q-icore.dtb",
+	[IMX6DL_ICORE] = "imx6dl-icore.dtb",
+	[IMX6Q_ICORE_MIPI] = "imx6q-icore-mipi.dtb",
+	[IMX6DL_ICORE_MIPI] = "imx6dl-icore-mipi.dtb",
+	[IMX6Q_ICORE_RQS] = "imx6q-icore-rqs.dtb",
+	[IMX6DL_ICORE_RQS] = "imx6dl-icore-rqs.dtb",
+	[IMX6UL_GEAM] = "imx6ul-geam.dtb",
+	[IMX6UL_ISIOT_EMMC] = "imx6ul-isiot-emmc.dtb",
+	[IMX6UL_ISIOT_NAND] = "imx6ul-isiot-nand.dtb",
+};
+
+static int setenv_fdt_file(int board_detected)
+{
+	if (board_detected < 0 || board_detected >= ENGICAM_BOARDS)
+		return -EINVAL;
+
+	if (!board_fdt_file[board_detected])
+		return -ENODEV;
+
+	env_set("fdt_file", board_fdt_file[board_detected]);
+	return 0;
+}
+
+static enum engicam_boards engicam_board_detect(void)
+{
+	const char *cmp_dtb = CONFIG_DEFAULT_DEVICE_TREE;
+
+	if (!strcmp(cmp_dtb, "imx6q-icore")) {
+		if (is_mx6dq())
+			return IMX6Q_ICORE;
+		else if (is_mx6dl() || is_mx6solo())
+			return IMX6DL_ICORE;
+	} else if (!strcmp(cmp_dtb, "imx6q-icore-mipi")) {
+		if (is_mx6dq())
+			return IMX6Q_ICORE_MIPI;
+		else if (is_mx6dl() || is_mx6solo())
+			return IMX6DL_ICORE_MIPI;
+	} else if (!strcmp(cmp_dtb, "imx6q-icore-rqs")) {
+		if (is_mx6dq())
+			return IMX6Q_ICORE_RQS;
+		else if (is_mx6dl() || is_mx6solo())
+			return IMX6DL_ICORE_RQS;
+	} else if (!strcmp(cmp_dtb, "imx6ul-geam"))
+			return IMX6UL_GEAM;
+	else if (!strcmp(cmp_dtb, "imx6ul-isiot-emmc"))
+			return IMX6UL_ISIOT_EMMC;
+	else if (!strcmp(cmp_dtb, "imx6ul-isiot-nand"))
+			return IMX6UL_ISIOT_NAND;
+
+	return -EINVAL;
+}
+
+static int fixup_enet_clock(enum engicam_boards board_detected)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int clk_internal = 0;
+
+	switch (board_detected) {
+	case IMX6Q_ICORE_MIPI:
+	case IMX6DL_ICORE_MIPI:
+		clk_internal = 1;
+		break;
+	default:
+		break;
+	}
+
+	/* set gpr1[21] to select anatop clock */
+	debug("fixup_enet_clock %d\n", clk_internal);
+	clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, clk_internal << 21);
+
+	if (!clk_internal) {
+		/* clock is external */
+		return 0;
+	}
+
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
+}
+
+int board_late_init(void)
+{
+	enum engicam_boards board_detected = IMX6Q_ICORE;
+
+	switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
+			IMX6_BMODE_SHIFT) {
+	case IMX6_BMODE_SD:
+	case IMX6_BMODE_ESD:
+	case IMX6_BMODE_MMC:
+	case IMX6_BMODE_EMMC:
+#ifdef CONFIG_ENV_IS_IN_MMC
+		mmc_late_init();
+#endif
+		env_set("modeboot", "mmcboot");
+		break;
+	case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
+		env_set("modeboot", "nandboot");
+		break;
+	default:
+		env_set("modeboot", "");
+		break;
+	}
+
+	if (is_mx6ul())
+		env_set("console", "ttymxc0");
+	else
+		env_set("console", "ttymxc3");
+
+	board_detected = engicam_board_detect();
+	if (board_detected < 0)
+		hang();
+
+	fixup_enet_clock(board_detected);
+	setenv_fdt_file(board_detected);
+
+#ifdef CONFIG_HW_WATCHDOG
+	hw_watchdog_init();
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_VIDEO_IPUV3
+	setup_display();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/engicam/common/board.h b/roms/u-boot/board/engicam/common/board.h
new file mode 100644
index 000000000..9f47e18ca
--- /dev/null
+++ b/roms/u-boot/board/engicam/common/board.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+void setup_gpmi_nand(void);
+void setup_display(void);
+#endif /* _BOARD_H_ */
diff --git a/roms/u-boot/board/engicam/common/spl.c b/roms/u-boot/board/engicam/common/spl.c
new file mode 100644
index 000000000..6a0612481
--- /dev/null
+++ b/roms/u-boot/board/engicam/common/spl.c
@@ -0,0 +1,435 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <serial.h>
+#include <spl.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
+        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+        PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+#ifdef CONFIG_MX6QDL
+        IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+        IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif CONFIG_MX6UL
+	IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#endif
+};
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+        if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
+                return 0;
+        else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
+                return 0;
+        else if (is_mx6dq() && !strcmp(name, "imx6q-icore-mipi"))
+                return 0;
+        else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
+                return 0;
+        else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
+                return 0;
+        else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-mipi"))
+                return 0;
+        else
+                return -1;
+}
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+void board_boot_order(u32 *spl_boot_list)
+{
+	u32 bmode = imx6_src_get_boot_mode();
+	u8 boot_dev = BOOT_DEVICE_MMC1;
+
+	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
+	case IMX6_BMODE_SD:
+	case IMX6_BMODE_ESD:
+		/* SD/eSD - BOOT_DEVICE_MMC1 */
+		break;
+	case IMX6_BMODE_MMC:
+	case IMX6_BMODE_EMMC:
+		/* MMC/eMMC */
+		boot_dev = BOOT_DEVICE_MMC2;
+		break;
+	default:
+		/* Default - BOOT_DEVICE_MMC1 */
+		printf("Wrong board boot order\n");
+		break;
+	}
+
+	spl_boot_list[0] = boot_dev;
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MX6QDL
+/*
+ * Driving strength:
+ *   0x30 == 40 Ohm
+ *   0x28 == 48 Ohm
+ */
+#define IMX6DQ_DRIVE_STRENGTH		0x30
+#define IMX6SDL_DRIVE_STRENGTH		0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
+	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddr_type = 0x000c0000,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
+	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
+	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* mt41j256 */
+static struct mx6_ddr3_cfg mt41j256 = {
+	.mem_speed = 1066,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 13,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+	.SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x000E0009,
+	.p0_mpwldectrl1 = 0x0018000E,
+	.p1_mpwldectrl0 = 0x00000007,
+	.p1_mpwldectrl1 = 0x00000000,
+	.p0_mpdgctrl0 = 0x43280334,
+	.p0_mpdgctrl1 = 0x031C0314,
+	.p1_mpdgctrl0 = 0x4318031C,
+	.p1_mpdgctrl1 = 0x030C0258,
+	.p0_mprddlctl = 0x3E343A40,
+	.p1_mprddlctl = 0x383C3844,
+	.p0_mpwrdlctl = 0x40404440,
+	.p1_mpwrdlctl = 0x4C3E4446,
+};
+
+/* DDR 64bit */
+static struct mx6_ddr_sysinfo mem_q = {
+	.ddr_type	= DDR_TYPE_DDR3,
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 2,
+	.rtt_wr		= 2,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x001F0024,
+	.p0_mpwldectrl1 = 0x00110018,
+	.p1_mpwldectrl0 = 0x001F0024,
+	.p1_mpwldectrl1 = 0x00110018,
+	.p0_mpdgctrl0 = 0x4230022C,
+	.p0_mpdgctrl1 = 0x02180220,
+	.p1_mpdgctrl0 = 0x42440248,
+	.p1_mpdgctrl1 = 0x02300238,
+	.p0_mprddlctl = 0x44444A48,
+	.p1_mprddlctl = 0x46484A42,
+	.p0_mpwrdlctl = 0x38383234,
+	.p1_mpwrdlctl = 0x3C34362E,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 1,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+	.dsize		= 1,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 1,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+#endif /* CONFIG_MX6QDL */
+
+#ifdef CONFIG_MX6UL
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000008,
+	.dram_sdqs0 = 0x00000038,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00070007,
+	.p0_mpdgctrl0 = 0x41490145,
+	.p0_mprddlctl = 0x40404546,
+	.p0_mpwrdlctl = 0x4040524D,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,
+	.cs_density = 20,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 2,
+	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
+	.walat = 1,		/* Write additional latency */
+	.ralat = 5,		/* Read additional latency */
+	.mif3_mode = 3,		/* Command prediction working mode */
+	.bi_on = 1,		/* Bank interleaving enabled */
+	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.ddr_type = DDR_TYPE_DDR3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+#ifdef TARGET_MX6UL_ISIOT
+	.rowaddr = 15,
+#else
+	.rowaddr = 13,
+#endif
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+#endif /* CONFIG_MX6UL */
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+#ifdef CONFIG_MX6QDL
+	writel(0x00003F3F, &ccm->CCGR0);
+	writel(0x0030FC00, &ccm->CCGR1);
+	writel(0x000FC000, &ccm->CCGR2);
+	writel(0x3F300000, &ccm->CCGR3);
+	writel(0xFF00F300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003CC, &ccm->CCGR6);
+#elif CONFIG_MX6UL
+	writel(0x00c03f3f, &ccm->CCGR0);
+	writel(0xfcffff00, &ccm->CCGR1);
+	writel(0x0cffffcc, &ccm->CCGR2);
+	writel(0x3f3c3030, &ccm->CCGR3);
+	writel(0xff00fffc, &ccm->CCGR4);
+	writel(0x033f30ff, &ccm->CCGR5);
+	writel(0x00c00fff, &ccm->CCGR6);
+#endif
+}
+
+static void spl_dram_init(void)
+{
+#ifdef CONFIG_MX6QDL
+	if (is_mx6solo()) {
+		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
+	} else if (is_mx6dl()) {
+		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
+	} else if (is_mx6dq()) {
+		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+		mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
+	}
+#elif CONFIG_MX6UL
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+#endif
+
+	udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	if (!(is_mx6ul()))
+		gpr_init();
+
+	/* iomux */
+	SETUP_IOMUX_PADS(uart_pads);
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
diff --git a/roms/u-boot/board/engicam/imx6q/Kconfig b/roms/u-boot/board/engicam/imx6q/Kconfig
new file mode 100644
index 000000000..fab8da0e7
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx6q/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_MX6Q_ENGICAM
+
+config SYS_BOARD
+	default "imx6q"
+
+config SYS_VENDOR
+	default "engicam"
+
+config SYS_CONFIG_NAME
+	default "imx6-engicam"
+
+source "board/engicam/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/engicam/imx6q/MAINTAINERS b/roms/u-boot/board/engicam/imx6q/MAINTAINERS
new file mode 100644
index 000000000..6b46378c5
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx6q/MAINTAINERS
@@ -0,0 +1,29 @@
+MX6Q_ENGICAM BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	board/engicam/imx6q
+F:	include/configs/imx6-engicam.h
+F:	configs/imx6qdl_icore_mmc_defconfig
+F:	configs/imx6q_icore_nand_defconfig
+F:	configs/imx6dl_icore_nand_defconfig
+F:	configs/imx6qdl_icore_rqs_defconfig
+F:	configs/imx6qdl_icore_mipi_defconfig
+F:	configs/imx6qdl_icore_nand_defconfig
+F:	arch/arm/dts/imx6qdl.dtsi
+F:	arch/arm/dts/imx6qdl-u-boot.dtsi
+F:	arch/arm/dts/imx6qdl-icore.dtsi
+F:	arch/arm/dts/imx6qdl-icore-u-boot.dtsi
+F:	arch/arm/dts/imx6q-icore.dts
+F:	arch/arm/dts/imx6q-icore-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-icore.dts
+F:	arch/arm/dts/imx6dl-icore-u-boot.dtsi
+F:	arch/arm/dts/imx6qdl-icore-rqs.dtsi
+F:	arch/arm/dts/imx6qdl-icore-rqs-u-boot.dtsi
+F:	arch/arm/dts/imx6q-icore-rqs.dts
+F:	arch/arm/dts/imx6q-icore-rqs-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-icore-rqs.dts
+F:	arch/arm/dts/imx6dl-icore-rqs-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-icore-mipi.dts
+F:	arch/arm/dts/imx6dl-icore-mipi-u-boot.dtsi
+F:	arch/arm/dts/imx6q-icore-mipi.dts
+F:	arch/arm/dts/imx6q-icore-mipi-u-boot.dtsi
diff --git a/roms/u-boot/board/engicam/imx6q/Makefile b/roms/u-boot/board/engicam/imx6q/Makefile
new file mode 100644
index 000000000..39554797a
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx6q/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2016 Amarula Solutions B.V.
+
+obj-y  := imx6q.o
diff --git a/roms/u-boot/board/engicam/imx6q/README b/roms/u-boot/board/engicam/imx6q/README
new file mode 100644
index 000000000..3f3478cc8
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx6q/README
@@ -0,0 +1,33 @@
+Hsow to use U-Boot on Engicam i.CoreM6 (RQS) Solo/DualLite/Quad/Dual Starter Kit:
+--------------------------------------------------------------------------------
+
+$ make mrproper
+
+- Configure U-Boot for Engicam i.CoreM6 Quad/Duali/Solo/DualLite:
+$ make imx6qdl_icore_mmc_defconfig
+
+- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Duali/Solo/DualLite:
+$ make imx6qdl_icore_rqs_defconfig
+
+- Build U-Boot
+$ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot-dtb.img image into the micro SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/roms/u-boot/board/engicam/imx6q/imx6q.c b/roms/u-boot/board/engicam/imx6q/imx6q.c
new file mode 100644
index 000000000..e6c888fcf
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx6q/imx6q.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
+
+#include "../common/board.h"
+
+#ifdef CONFIG_NAND_MXS
+#define GPMI_PAD_CTRL0	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1	(PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2	(GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+static iomux_v3_cfg_t gpmi_pads[] = {
+	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
+	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+};
+
+void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	SETUP_IOMUX_PADS(gpmi_pads);
+
+	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
+	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+	/* config gpmi and bch clock to 100 MHz */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+	/* enable ENFC_CLK_ROOT clock */
+	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static iomux_v3_cfg_t const rgb_pads[] = {
+	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
+	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
+	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
+	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
+	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
+	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
+	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
+	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
+	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
+	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
+	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
+	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
+	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
+	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
+	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
+	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
+	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
+	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
+	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
+	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
+	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
+};
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+	SETUP_IOMUX_PADS(rgb_pads);
+}
+
+struct display_info_t const displays[] = {
+	{
+		.bus	= -1,
+		.addr	= 0,
+		.pixfmt	= IPU_PIX_FMT_RGB666,
+		.detect	= NULL,
+		.enable	= enable_rgb,
+		.mode	= {
+			.name           = "Amp-WD",
+			.refresh        = 60,
+			.xres           = 800,
+			.yres           = 480,
+			.pixclock       = 30000,
+			.left_margin    = 30,
+			.right_margin   = 30,
+			.upper_margin   = 5,
+			.lower_margin   = 5,
+			.hsync_len      = 64,
+			.vsync_len      = 20,
+			.sync           = FB_SYNC_EXT,
+			.vmode          = FB_VMODE_NONINTERLACED
+		}
+	},
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+
+	/* Turn on LDB0,IPU,IPU DI0 clocks */
+	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg |=  (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+		MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+		(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+		MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+		IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
+		IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+		IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+		IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+		IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+		IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+		IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
+		IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
+		(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+		IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+int board_mmc_get_env_dev(int devno)
+{
+	/* i.CoreM6 RQS has USDHC3 for SD and USDHC4 for eMMC */
+	return (devno == 0) ? 0: (devno - 1);
+}
+#endif
diff --git a/roms/u-boot/board/engicam/imx6ul/Kconfig b/roms/u-boot/board/engicam/imx6ul/Kconfig
new file mode 100644
index 000000000..58f25d062
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx6ul/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_MX6UL_ENGICAM
+
+config SYS_BOARD
+	default "imx6ul"
+
+config SYS_VENDOR
+	default "engicam"
+
+config SYS_CONFIG_NAME
+	default "imx6-engicam"
+
+source "board/engicam/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/engicam/imx6ul/MAINTAINERS b/roms/u-boot/board/engicam/imx6ul/MAINTAINERS
new file mode 100644
index 000000000..88db309ae
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx6ul/MAINTAINERS
@@ -0,0 +1,19 @@
+MX6UL_ENGICAM BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	board/engicam/imx6ul
+F:	include/configs/imx6-engicam.h
+F:	configs/imx6ul_geam_mmc_defconfig
+F:	configs/imx6ul_geam_nand_defconfig
+F:	configs/imx6ul_isiot_emmc_defconfig
+F:	configs/imx6ul_isiot_mmc_defconfig
+F:	configs/imx6ul_isiot_nand_defconfig
+F:	arch/arm/dts/imx6ul.dtsi
+F:	arch/arm/dts/imx6ul-u-boot.dtsi
+F:	arch/arm/dts/imx6ul-geam-kit.dts
+F:	arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi
+F:	arch/arm/dts/imx6ul-isiot.dtsi
+F:	arch/arm/dts/imx6ul-isiot-u-boot.dtsi
+F:	arch/arm/dts/imx6ul-isiot-emmc.dts
+F:	arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi
+F:	arch/arm/dts/imx6ul-isiot-nand.dts
diff --git a/roms/u-boot/board/engicam/imx6ul/Makefile b/roms/u-boot/board/engicam/imx6ul/Makefile
new file mode 100644
index 000000000..5cf8f30f3
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx6ul/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2016 Amarula Solutions B.V.
+
+obj-y  := imx6ul.o
diff --git a/roms/u-boot/board/engicam/imx6ul/README b/roms/u-boot/board/engicam/imx6ul/README
new file mode 100644
index 000000000..1e85f618f
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx6ul/README
@@ -0,0 +1,33 @@
+Hsow to use U-Boot on Engicam GEAM6UL and Is.IoT MX6UL Starter Kit:
+-------------------------------------------------------------------
+
+$ make mrproper
+
+- Configure U-Boot for Engicam GEAM6UL:
+$ make imx6ul_geam_mmc_defconfig
+
+- Configure U-Boot for Engicam Is.IoT MX6UL:
+$ make imx6ul_isiot_mmc_defconfig
+
+- Build U-Boot
+$ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot-dtb.img image into the micro SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/roms/u-boot/board/engicam/imx6ul/imx6ul.c b/roms/u-boot/board/engicam/imx6ul/imx6ul.c
new file mode 100644
index 000000000..412d6c302
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx6ul/imx6ul.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <mmc.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+
+#include "../common/board.h"
+
+#ifdef CONFIG_NAND_MXS
+
+#define GPMI_PAD_CTRL0		(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1		(PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+				PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2		(GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+static iomux_v3_cfg_t const nand_pads[] = {
+	IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+};
+
+void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	SETUP_IOMUX_PADS(nand_pads);
+
+	clrbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+	/*
+	 * config gpmi and bch clock to 100 MHz
+	 * bch/gpmi select PLL2 PFD2 400M
+	 * 100M = 400M / 4
+	 */
+	clrbits_le32(&mxc_ccm->cscmr1,
+		     MXC_CCM_CSCMR1_BCH_CLK_SEL |
+		     MXC_CCM_CSCMR1_GPMI_CLK_SEL);
+	clrsetbits_le32(&mxc_ccm->cscdr1,
+			MXC_CCM_CSCDR1_BCH_PODF_MASK |
+			MXC_CCM_CSCDR1_GPMI_PODF_MASK,
+			(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
+			(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif /* CONFIG_NAND_MXS */
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+int board_mmc_get_env_dev(int devno)
+{
+	/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
+	return (devno == 0) ? 0 : 1;
+}
+#endif
diff --git a/roms/u-boot/board/engicam/imx8mm/Kconfig b/roms/u-boot/board/engicam/imx8mm/Kconfig
new file mode 100644
index 000000000..ed68516df
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx8mm/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_IMX8MM_ICORE_MX8MM
+
+config SYS_BOARD
+	default "imx8mm"
+
+config SYS_VENDOR
+	default "engicam"
+
+config SYS_CONFIG_NAME
+	default "imx8mm_icore_mx8mm"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/engicam/imx8mm/MAINTAINERS b/roms/u-boot/board/engicam/imx8mm/MAINTAINERS
new file mode 100644
index 000000000..2e99a5995
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx8mm/MAINTAINERS
@@ -0,0 +1,13 @@
+i.Core-MX8M-Mini-CTOUCH2.0
+M:	Jagan Teki <jagan@amarulasolutions.com>
+M:	Matteo Lisi <matteo.lisi@engicam.com>
+S:	Maintained
+F:	configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+
+i.Core-MX8M-Mini-EDIMM2.2
+M:	Jagan Teki <jagan@amarulasolutions.com>
+M:	Matteo Lisi <matteo.lisi@engicam.com>
+S:	Maintained
+F:	board/engicam/imx8mm
+F:	include/configs/imx8mm_icore_mx8mm.h
+F:	configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
diff --git a/roms/u-boot/board/engicam/imx8mm/Makefile b/roms/u-boot/board/engicam/imx8mm/Makefile
new file mode 100644
index 000000000..3392d6192
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx8mm/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2020 Amarula Solutions(India)
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += icore_mx8mm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += lpddr4_timing.o
+endif
diff --git a/roms/u-boot/board/engicam/imx8mm/icore_mx8mm.c b/roms/u-boot/board/engicam/imx8mm/icore_mx8mm.c
new file mode 100644
index 000000000..4f7c699d7
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx8mm/icore_mx8mm.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+
+#include <linux/delay.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+
+#define FEC_RST_PAD IMX_GPIO_NR(3, 7)
+static iomux_v3_cfg_t const fec1_rst_pads[] = {
+	IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
+					 ARRAY_SIZE(fec1_rst_pads));
+
+	gpio_request(FEC_RST_PAD, "fec1_rst");
+	gpio_direction_output(FEC_RST_PAD, 0);
+	udelay(500);
+	gpio_direction_output(FEC_RST_PAD, 1);
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	setup_iomux_fec();
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], 13, 0);
+
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_FEC_MXC))
+		setup_fec();
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
diff --git a/roms/u-boot/board/engicam/imx8mm/lpddr4_timing.c b/roms/u-boot/board/engicam/imx8mm/lpddr4_timing.c
new file mode 100644
index 000000000..821212740
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx8mm/lpddr4_timing.c
@@ -0,0 +1,1846 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/* Initialize DDRC registers */
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa1080020},
+	{0x3d400020, 0x223},
+	{0x3d400024, 0x3a980},
+	{0x3d400064, 0x5b0087},
+	{0x3d4000d0, 0xc00305ba},
+	{0x3d4000d4, 0x940000},
+	{0x3d4000dc, 0xd4002d},
+	{0x3d4000e0, 0x210000},
+	{0x3d4000e8, 0x44004d},
+	{0x3d4000ec, 0x14004d},
+	{0x3d400100, 0x191f1920},
+	{0x3d400104, 0x60630},
+	{0x3d40010c, 0xb0b000},
+	{0x3d400110, 0xe04080e},
+	{0x3d400114, 0x2040c0c},
+	{0x3d400118, 0x1010007},
+	{0x3d40011c, 0x401},
+	{0x3d400130, 0x20600},
+	{0x3d400134, 0xc100002},
+	{0x3d400138, 0x8d},
+	{0x3d400144, 0x96004b},
+	{0x3d400180, 0x2ee0017},
+	{0x3d400184, 0x2605b8e},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x497820a},
+	{0x3d400194, 0x80303},
+	{0x3d4001b4, 0x170a},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x0},
+	{0x3d4000f4, 0xc99},
+	{0x3d400108, 0x70e1617},
+	{0x3d400200, 0x1f},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0xf070707},
+	{0x3d400250, 0x29001701},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x4000030},
+	{0x3d400264, 0x900093e7},
+	{0x3d40026c, 0x2005574},
+	{0x3d400400, 0x111},
+	{0x3d400408, 0x72ff},
+	{0x3d400494, 0x2100e07},
+	{0x3d400498, 0x620096},
+	{0x3d40049c, 0x1100e07},
+	{0x3d4004a0, 0xc8012c},
+	{0x3d402020, 0x21},
+	{0x3d402024, 0x7d00},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0xc0012},
+	{0x3d4020dc, 0x840000},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004d},
+	{0x3d4020ec, 0x16004d},
+	{0x3d402100, 0xa050305},
+	{0x3d402104, 0x30407},
+	{0x3d402108, 0x203060b},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x2040202},
+	{0x3d402114, 0x2030202},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x13},
+	{0x3d402144, 0x14000a},
+	{0x3d402180, 0x640004},
+	{0x3d402190, 0x3818200},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x100},
+	{0x3d403020, 0x21},
+	{0x3d403024, 0x1f40},
+	{0x3d403050, 0x20d040},
+	{0x3d403064, 0x30005},
+	{0x3d4030dc, 0x840000},
+	{0x3d4030e0, 0x310000},
+	{0x3d4030e8, 0x66004d},
+	{0x3d4030ec, 0x16004d},
+	{0x3d403100, 0xa020102},
+	{0x3d403104, 0x30404},
+	{0x3d403108, 0x203060b},
+	{0x3d40310c, 0x505000},
+	{0x3d403110, 0x2040202},
+	{0x3d403114, 0x2030202},
+	{0x3d403118, 0x1010004},
+	{0x3d40311c, 0x301},
+	{0x3d403130, 0x20300},
+	{0x3d403134, 0xa100002},
+	{0x3d403138, 0x5},
+	{0x3d403144, 0x50003},
+	{0x3d403180, 0x190004},
+	{0x3d403190, 0x3818200},
+	{0x3d403194, 0x80303},
+	{0x3d4031b4, 0x100},
+	{0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x3},
+	{0x110a3, 0x4},
+	{0x110a4, 0x5},
+	{0x110a5, 0x2},
+	{0x110a6, 0x7},
+	{0x110a7, 0x6},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x3},
+	{0x120a3, 0x2},
+	{0x120a4, 0x5},
+	{0x120a5, 0x4},
+	{0x120a6, 0x7},
+	{0x120a7, 0x6},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x21005f, 0x1ff},
+	{0x21015f, 0x1ff},
+	{0x21105f, 0x1ff},
+	{0x21115f, 0x1ff},
+	{0x21205f, 0x1ff},
+	{0x21215f, 0x1ff},
+	{0x21305f, 0x1ff},
+	{0x21315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x19},
+	{0x1200c5, 0x7},
+	{0x2200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x2},
+	{0x22002e, 0x2},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x220024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x3},
+	{0x120056, 0xa},
+	{0x220056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x21004d, 0xe00},
+	{0x21014d, 0xe00},
+	{0x21104d, 0xe00},
+	{0x21114d, 0xe00},
+	{0x21204d, 0xe00},
+	{0x21214d, 0xe00},
+	{0x21304d, 0xe00},
+	{0x21314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x210049, 0xeba},
+	{0x210149, 0xeba},
+	{0x211049, 0xeba},
+	{0x211149, 0xeba},
+	{0x212049, 0xeba},
+	{0x212149, 0xeba},
+	{0x213049, 0xeba},
+	{0x213149, 0xeba},
+	{0x43, 0x63},
+	{0x1043, 0x63},
+	{0x2043, 0x63},
+	{0x3043, 0x63},
+	{0x4043, 0x63},
+	{0x5043, 0x63},
+	{0x6043, 0x63},
+	{0x7043, 0x63},
+	{0x8043, 0x63},
+	{0x9043, 0x63},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x2ee},
+	{0x120008, 0x64},
+	{0x220008, 0x19},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x2200b2, 0xdc},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
+	{0x212043, 0x5a1},
+	{0x212143, 0x5a1},
+	{0x213043, 0x5a1},
+	{0x213143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x2200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
+	{0x200f0, 0x660},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5665},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x200c7, 0x21},
+	{0x1200c7, 0x21},
+	{0x2200c7, 0x21},
+	{0x200ca, 0x24},
+	{0x1200ca, 0x24},
+	{0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xbb8},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x21},
+	{0x5401b, 0x4d44},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x14},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x21},
+	{0x54021, 0x4d44},
+	{0x54022, 0x4d00},
+	{0x54024, 0x14},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x212d},
+	{0x54034, 0x4400},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1400},
+	{0x54038, 0xd400},
+	{0x54039, 0x212d},
+	{0x5403a, 0x4400},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1400},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x101},
+	{0x54003, 0x190},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x64},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xbb8},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x21},
+	{0x5401b, 0x4d44},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x14},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x21},
+	{0x54021, 0x4d44},
+	{0x54022, 0x4d00},
+	{0x54024, 0x14},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x212d},
+	{0x54034, 0x4400},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1400},
+	{0x54038, 0xd400},
+	{0x54039, 0x212d},
+	{0x5403a, 0x4400},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1400},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x5d},
+	{0x2000c, 0xbb},
+	{0x2000d, 0x753},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xc},
+	{0x12000c, 0x19},
+	{0x12000d, 0xfa},
+	{0x12000e, 0x10},
+	{0x22000b, 0x3},
+	{0x22000c, 0x6},
+	{0x22000d, 0x3e},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x220010, 0x5a},
+	{0x220011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
diff --git a/roms/u-boot/board/engicam/imx8mm/spl.c b/roms/u-boot/board/engicam/imx8mm/spl.c
new file mode 100644
index 000000000..f9be769ec
--- /dev/null
+++ b/roms/u-boot/board/engicam/imx8mm/spl.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Engicam s.r.l.
+ * Copyright (C) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case SD1_BOOT:
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+static void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+	debug("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	arch_cpu_init();
+
+	init_uart_clk(1);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/engicam/px30_core/Kconfig b/roms/u-boot/board/engicam/px30_core/Kconfig
new file mode 100644
index 000000000..a03be7836
--- /dev/null
+++ b/roms/u-boot/board/engicam/px30_core/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_PX30_CORE
+
+config SYS_BOARD
+	default "px30_core"
+
+config SYS_VENDOR
+	default "engicam"
+
+config SYS_CONFIG_NAME
+	default "px30_core"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select RAM_PX30_DDR4 
+
+endif
diff --git a/roms/u-boot/board/engicam/px30_core/MAINTAINERS b/roms/u-boot/board/engicam/px30_core/MAINTAINERS
new file mode 100644
index 000000000..b87ca2220
--- /dev/null
+++ b/roms/u-boot/board/engicam/px30_core/MAINTAINERS
@@ -0,0 +1,13 @@
+PX30-Core-CTOUCH2.0
+M:	Jagan Teki <jagan@amarulasolutions.com>
+M:	Suniel Mahesh <sunil@amarulasolutions.com>
+S:	Maintained
+F:	configs/px30-core-ctouch2-px30_defconfig
+
+PX30-Core-EDIMM2.2
+M:	Jagan Teki <jagan@amarulasolutions.com>
+M:	Suniel Mahesh <sunil@amarulasolutions.com>
+S:	Maintained
+F:	board/engicam/px30_core
+F:	include/configs/px30_core.h
+F:	configs/px30-core-edimm2.2-px30_defconfig
diff --git a/roms/u-boot/board/engicam/px30_core/Makefile b/roms/u-boot/board/engicam/px30_core/Makefile
new file mode 100644
index 000000000..321fdb017
--- /dev/null
+++ b/roms/u-boot/board/engicam/px30_core/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2020 Amarula Solutions(India)
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= px30_core.o
diff --git a/roms/u-boot/board/engicam/px30_core/px30_core.c b/roms/u-boot/board/engicam/px30_core/px30_core.c
new file mode 100644
index 000000000..3adc2f11d
--- /dev/null
+++ b/roms/u-boot/board/engicam/px30_core/px30_core.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
diff --git a/roms/u-boot/board/engicam/stm32mp1/Kconfig b/roms/u-boot/board/engicam/stm32mp1/Kconfig
new file mode 100644
index 000000000..c800fd4e6
--- /dev/null
+++ b/roms/u-boot/board/engicam/stm32mp1/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ICORE_STM32MP1 || TARGET_MICROGEA_STM32MP1
+
+config SYS_BOARD
+	default "stm32mp1"
+
+config SYS_VENDOR
+	default "engicam"
+
+config SYS_CONFIG_NAME
+	default "stm32mp1"
+
+endif
diff --git a/roms/u-boot/board/engicam/stm32mp1/MAINTAINERS b/roms/u-boot/board/engicam/stm32mp1/MAINTAINERS
new file mode 100644
index 000000000..405ff9918
--- /dev/null
+++ b/roms/u-boot/board/engicam/stm32mp1/MAINTAINERS
@@ -0,0 +1,26 @@
+MicroGEA-STM32MP1-MICRODEV2.0
+M:	Jagan Teki <jagan@amarulasolutions.com>
+M:	Matteo Lisi <matteo.lisi@engicam.com>
+S:	Maintained
+F:	arch/arm/dts/stm32mp15*microgea*
+F:	configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
+
+MicroGEA-STM32MP1-MICRODEV2.0-OF7
+M:	Jagan Teki <jagan@amarulasolutions.com>
+M:	Matteo Lisi <matteo.lisi@engicam.com>
+S:	Maintained
+F:	configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
+
+i.Core-STM32MP1-CTOUCH2.0
+M:	Jagan Teki <jagan@amarulasolutions.com>
+M:	Matteo Lisi <matteo.lisi@engicam.com>
+S:	Maintained
+F:	configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
+
+i.Core-STM32MP1-EDIMM2.2
+M:	Jagan Teki <jagan@amarulasolutions.com>
+M:	Matteo Lisi <matteo.lisi@engicam.com>
+S:	Maintained
+F:	arch/arm/dts/stm32mp15*icore*
+F:	board/engicam/stm32mp1
+F:	configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
diff --git a/roms/u-boot/board/engicam/stm32mp1/Makefile b/roms/u-boot/board/engicam/stm32mp1/Makefile
new file mode 100644
index 000000000..65560df29
--- /dev/null
+++ b/roms/u-boot/board/engicam/stm32mp1/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += stm32mp1.o
+endif
diff --git a/roms/u-boot/board/engicam/stm32mp1/spl.c b/roms/u-boot/board/engicam/stm32mp1/spl.c
new file mode 100644
index 000000000..79adb5f52
--- /dev/null
+++ b/roms/u-boot/board/engicam/stm32mp1/spl.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2020 Engicam S.r.l.
+ * Copyright (C) 2020 Amarula Solutions(India)
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+/* board early initialisation in board_f: need to use global variable */
+static u32 opp_voltage_mv __section(".data");
+
+void board_vddcore_init(u32 voltage_mv)
+{
+	if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER_SUPPORT))
+		opp_voltage_mv = voltage_mv;
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
+
+#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
+#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
+
+	/* UART4 clock enable */
+	setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
+
+#define GPIOG_BASE 0x50008000
+	/* GPIOG clock enable */
+	writel(BIT(6), RCC_MP_AHB4ENSETR);
+	/* GPIO configuration for ST boards: Uart4 TX = G11 */
+	writel(0xffbfffff, GPIOG_BASE + 0x00);
+	writel(0x00006000, GPIOG_BASE + 0x24);
+#else
+
+#error("CONFIG_DEBUG_UART_BASE: not supported value")
+
+#endif
+}
+#endif
diff --git a/roms/u-boot/board/engicam/stm32mp1/stm32mp1.c b/roms/u-boot/board/engicam/stm32mp1/stm32mp1.c
new file mode 100644
index 000000000..8bf9c9c67
--- /dev/null
+++ b/roms/u-boot/board/engicam/stm32mp1/stm32mp1.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2020 Engicam S.r.l.
+ * Copyright (C) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <env_internal.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	char *mode;
+	const char *fdt_compat;
+	int fdt_compat_len;
+
+	if (IS_ENABLED(CONFIG_TFABOOT))
+		mode = "trusted";
+	else
+		mode = "basic";
+
+	printf("Board: stm32mp1 in %s mode", mode);
+	fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
+				 &fdt_compat_len);
+	if (fdt_compat && fdt_compat_len)
+		printf(" (%s)", fdt_compat);
+	puts("\n");
+
+	return 0;
+}
+
+/* board dependent setup after realloc */
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
+
+	if (IS_ENABLED(CONFIG_DM_REGULATOR))
+		regulators_enable_boot_on(_DEBUG);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	u32 bootmode = get_bootmode();
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
+	case BOOT_FLASH_SD:
+	case BOOT_FLASH_EMMC:
+		if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
+			return ENVL_MMC;
+		else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4))
+			return ENVL_EXT4;
+		else
+			return ENVL_NOWHERE;
+
+	case BOOT_FLASH_NAND:
+	case BOOT_FLASH_SPINAND:
+		if (CONFIG_IS_ENABLED(ENV_IS_IN_UBI))
+			return ENVL_UBI;
+		else
+			return ENVL_NOWHERE;
+
+	case BOOT_FLASH_NOR:
+		if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		else
+			return ENVL_NOWHERE;
+
+	default:
+		return ENVL_NOWHERE;
+	}
+}
+
+const char *env_ext4_get_intf(void)
+{
+	u32 bootmode = get_bootmode();
+
+	switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
+	case BOOT_FLASH_SD:
+	case BOOT_FLASH_EMMC:
+		return "mmc";
+	default:
+		return "";
+	}
+}
+
+const char *env_ext4_get_dev_part(void)
+{
+	static char *const dev_part[] = {"0:auto", "1:auto", "2:auto"};
+	u32 bootmode = get_bootmode();
+
+	return dev_part[(bootmode & TAMP_BOOT_INSTANCE_MASK) - 1];
+}
+
+int mmc_get_env_dev(void)
+{
+	u32 bootmode = get_bootmode();
+
+	return (bootmode & TAMP_BOOT_INSTANCE_MASK) - 1;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/esd/meesc/Kconfig b/roms/u-boot/board/esd/meesc/Kconfig
new file mode 100644
index 000000000..150348ac3
--- /dev/null
+++ b/roms/u-boot/board/esd/meesc/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MEESC
+
+config SYS_BOARD
+	default "meesc"
+
+config SYS_VENDOR
+	default "esd"
+
+config SYS_CONFIG_NAME
+	default "meesc"
+
+endif
diff --git a/roms/u-boot/board/esd/meesc/MAINTAINERS b/roms/u-boot/board/esd/meesc/MAINTAINERS
new file mode 100644
index 000000000..94036991b
--- /dev/null
+++ b/roms/u-boot/board/esd/meesc/MAINTAINERS
@@ -0,0 +1,7 @@
+MEESC BOARD
+M:	Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+S:	Maintained
+F:	board/esd/meesc/
+F:	include/configs/meesc.h
+F:	configs/meesc_defconfig
+F:	configs/meesc_dataflash_defconfig
diff --git a/roms/u-boot/board/esd/meesc/Makefile b/roms/u-boot/board/esd/meesc/Makefile
new file mode 100644
index 000000000..c13e22109
--- /dev/null
+++ b/roms/u-boot/board/esd/meesc/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+
+obj-y	+= meesc.o
diff --git a/roms/u-boot/board/esd/meesc/meesc.c b/roms/u-boot/board/esd/meesc/meesc.c
new file mode 100644
index 000000000..eaa525eb0
--- /dev/null
+++ b/roms/u-boot/board/esd/meesc/meesc.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2009-2015
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <serial.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/setup.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_REVISION_TAG
+static int hw_rev = -1;	/* hardware revision */
+
+int get_hw_rev(void)
+{
+	if (hw_rev >= 0)
+		return hw_rev;
+
+	hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
+
+	if (hw_rev == 15)
+		hw_rev = 0;
+
+	return hw_rev;
+}
+#endif /* CONFIG_REVISION_TAG */
+
+#ifdef CONFIG_CMD_NAND
+static void meesc_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t	*smc	= (at91_smc_t *) ATMEL_BASE_SMC0;
+	at91_matrix_t	*matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_DBW_8 |
+		AT91_SMC_MODE_TDF_CYCLE(12),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+	/* Enable NandFlash */
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif /* CONFIG_CMD_NAND */
+
+#ifdef CONFIG_MACB
+static void meesc_macb_hw_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+
+	at91_macb_hw_init();
+}
+#endif
+
+/*
+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
+ * controller debugging
+ * The ET1100 is located at physical address 0x70000000
+ * Its process memory is located at physical address 0x70001000
+ */
+static void meesc_ethercat_hw_init(void)
+{
+	at91_smc_t	*smc1	= (at91_smc_t *) ATMEL_BASE_SMC1;
+
+	/* Configure SMC EBI1_CS0 for EtherCAT */
+	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc1->cs[0].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
+		AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
+		&smc1->cs[0].pulse);
+	writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
+		&smc1->cs[0].cycle);
+	/*
+	 * Configure behavior at external wait signal, byte-select mode, 16 bit
+	 * data bus width, none data float wait states and TDF optimization
+	 */
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
+		AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
+		AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_b_periph(AT91_PIO_PORTE, 20, 0);	/* EBI1_NWAIT */
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+				PHYS_SDRAM_SIZE);
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	char str[32];
+	u_char hw_type;	/* hardware type */
+
+	/* read the "Type" register of the ET1100 controller */
+	hw_type = readb(CONFIG_ET1100_BASE);
+
+	switch (hw_type) {
+	case 0x11:
+	case 0x3F:
+		/* ET1100 present, arch number of MEESC-Board */
+		gd->bd->bi_arch_number = MACH_TYPE_MEESC;
+		puts("Board: CAN-EtherCAT Gateway");
+		break;
+	case 0xFF:
+		/* no ET1100 present, arch number of EtherCAN/2-Board */
+		gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
+		puts("Board: EtherCAN/2 Gateway");
+		/* switch on LED1D */
+		at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
+		break;
+	default:
+		/* assume, no ET1100 present, arch number of EtherCAN/2-Board */
+		gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
+		printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
+		puts("Board: EtherCAN/2 Gateway");
+		break;
+	}
+	if (env_get_f("serial#", str, sizeof(str)) > 0) {
+		puts(", serial# ");
+		puts(str);
+	}
+#ifdef CONFIG_REVISION_TAG
+	printf("\nHardware-revision: 1.%d\n", get_hw_rev());
+#endif
+	printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *str;
+
+	char *serial = env_get("serial#");
+	if (serial) {
+		str = strchr(serial, '_');
+		if (str && (strlen(str) >= 4)) {
+			serialnr->high = (*(str + 1) << 8) | *(str + 2);
+			serialnr->low = simple_strtoul(str + 3, NULL, 16);
+		}
+	} else {
+		serialnr->high = 0;
+		serialnr->low = 0;
+	}
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	return hw_rev | 0x100;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char		*str;
+	char		buf[32];
+	at91_pmc_t	*pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	/*
+	 * Normally the processor clock has a divisor of 2.
+	 * In some cases this this needs to be set to 4.
+	 * Check the user has set environment mdiv to 4 to change the divisor.
+	 */
+	str = env_get("mdiv");
+	if (str && (strcmp(str, "4") == 0)) {
+		writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
+			AT91SAM9_PMC_MDIV_4, &pmc->mckr);
+		at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+		serial_setbrg();
+		/* Notify the user that the clock is not default */
+		printf("Setting master clock to %s MHz\n",
+			strmhz(buf, get_mck_clk_rate()));
+	}
+
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_UHP);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* initialize ET1100 Controller */
+	meesc_ethercat_hw_init();
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	meesc_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	meesc_macb_hw_init();
+#endif
+#ifdef CONFIG_AT91_CAN
+	at91_can_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+	return 0;
+}
diff --git a/roms/u-boot/board/esd/vme8349/Kconfig b/roms/u-boot/board/esd/vme8349/Kconfig
new file mode 100644
index 000000000..ef2af40f7
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_VME8349
+
+config SYS_BOARD
+	default "vme8349"
+
+config SYS_VENDOR
+	default "esd"
+
+config SYS_CONFIG_NAME
+	default "vme8349"
+
+endif
+
+if TARGET_CADDY2
+
+config SYS_BOARD
+	default "vme8349"
+
+config SYS_VENDOR
+	default "esd"
+
+config SYS_CONFIG_NAME
+	default "caddy2"
+
+endif
diff --git a/roms/u-boot/board/esd/vme8349/MAINTAINERS b/roms/u-boot/board/esd/vme8349/MAINTAINERS
new file mode 100644
index 000000000..a88ba13c3
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/MAINTAINERS
@@ -0,0 +1,7 @@
+VME8349 BOARD
+M:	Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+S:	Maintained
+F:	board/esd/vme8349/
+F:	include/configs/vme8349.h
+F:	configs/caddy2_defconfig
+F:	configs/vme8349_defconfig
diff --git a/roms/u-boot/board/esd/vme8349/Makefile b/roms/u-boot/board/esd/vme8349/Makefile
new file mode 100644
index 000000000..850c16ba6
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (c) 2009 esd gmbh hannover germany.
+
+obj-y += vme8349.o caddy.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/roms/u-boot/board/esd/vme8349/caddy.c b/roms/u-boot/board/esd/vme8349/caddy.c
new file mode 100644
index 000000000..ba91f4b3c
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/caddy.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+
+#include "caddy.h"
+
+static struct caddy_interface *caddy_interface;
+
+void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
+{
+	struct caddy_answer *answer;
+	uint32_t ptr;
+
+	answer = &caddy_interface->answer[caddy_interface->answer_in];
+	memset((void *)answer, 0, sizeof(struct caddy_answer));
+	answer->answer = cmd->cmd;
+	answer->issue = cmd->issue;
+	answer->status = status;
+	memcpy(answer->par, result, 5 * sizeof(result[0]));
+	ptr = caddy_interface->answer_in + 1;
+	ptr = ptr & (ANSWER_SIZE - 1);
+	if (ptr != caddy_interface->answer_out)
+		caddy_interface->answer_in = ptr;
+}
+
+int do_caddy(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	unsigned long base_addr;
+	uint32_t ptr;
+	struct caddy_cmd *caddy_cmd;
+	uint32_t result[5];
+	uint16_t data16;
+	uint8_t data8;
+	uint32_t status;
+	pci_dev_t dev;
+	void *pci_ptr;
+
+	if (argc < 2) {
+		puts("Missing parameter\n");
+		return 1;
+	}
+
+	base_addr = simple_strtoul(argv[1], NULL, 16);
+	caddy_interface = (struct caddy_interface *) base_addr;
+
+	memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
+	memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
+
+	while (ctrlc() == 0) {
+		if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
+			memset(result, 0, 5 * sizeof(result[0]));
+			status = 0;
+			caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
+			pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
+				(caddy_cmd->addr & 0x001fffff);
+
+			switch (caddy_cmd->cmd) {
+			case CADDY_CMD_IO_READ_8:
+				result[0] = in_8(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_READ_16:
+				result[0] = in_be16(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_READ_32:
+				result[0] = in_be32(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_WRITE_8:
+				data8 = caddy_cmd->par[0] & 0x000000ff;
+				out_8(pci_ptr, data8);
+				break;
+
+			case CADDY_CMD_IO_WRITE_16:
+				data16 = caddy_cmd->par[0] & 0x0000ffff;
+				out_be16(pci_ptr, data16);
+				break;
+
+			case CADDY_CMD_IO_WRITE_32:
+				out_be32(pci_ptr, caddy_cmd->par[0]);
+				break;
+
+			case CADDY_CMD_CONFIG_READ_8:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_byte(dev,
+							      caddy_cmd->addr,
+							      &data8);
+				result[0] = data8;
+				break;
+
+			case CADDY_CMD_CONFIG_READ_16:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_word(dev,
+							      caddy_cmd->addr,
+							      &data16);
+				result[0] = data16;
+				break;
+
+			case CADDY_CMD_CONFIG_READ_32:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_dword(dev,
+							       caddy_cmd->addr,
+							       &result[0]);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_8:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				data8 = caddy_cmd->par[3] & 0x000000ff;
+				status = pci_write_config_byte(dev,
+							       caddy_cmd->addr,
+							       data8);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_16:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				data16 = caddy_cmd->par[3] & 0x0000ffff;
+				status = pci_write_config_word(dev,
+							       caddy_cmd->addr,
+							       data16);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_32:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_write_config_dword(dev,
+								caddy_cmd->addr,
+								caddy_cmd->par[3]);
+				break;
+
+			default:
+				status = 0xffffffff;
+				break;
+			}
+
+			generate_answer(caddy_cmd, status, &result[0]);
+
+			ptr = caddy_interface->cmd_out + 1;
+			ptr = ptr & (CMD_SIZE - 1);
+			caddy_interface->cmd_out = ptr;
+		}
+
+		caddy_interface->heartbeat++;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	caddy,	2,	0,	do_caddy,
+	"Start Caddy server.",
+	"Start Caddy server with Data structure a given addr\n"
+	);
diff --git a/roms/u-boot/board/esd/vme8349/caddy.h b/roms/u-boot/board/esd/vme8349/caddy.h
new file mode 100644
index 000000000..8e3033ba2
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/caddy.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ */
+
+#ifndef __CADDY_H__
+#define __CADDY_H__
+
+#define CMD_SIZE	1024
+#define ANSWER_SIZE	1024
+#define CADDY_MAGIC	"esd vme8349 V1.0"
+
+enum caddy_cmds {
+	CADDY_CMD_IO_READ_8,
+	CADDY_CMD_IO_READ_16,
+	CADDY_CMD_IO_READ_32,
+	CADDY_CMD_IO_WRITE_8,
+	CADDY_CMD_IO_WRITE_16,
+	CADDY_CMD_IO_WRITE_32,
+	CADDY_CMD_CONFIG_READ_8,
+	CADDY_CMD_CONFIG_READ_16,
+	CADDY_CMD_CONFIG_READ_32,
+	CADDY_CMD_CONFIG_WRITE_8,
+	CADDY_CMD_CONFIG_WRITE_16,
+	CADDY_CMD_CONFIG_WRITE_32,
+};
+
+struct caddy_cmd {
+	uint32_t cmd;
+	uint32_t issue;
+	uint32_t addr;
+	uint32_t par[5];
+};
+
+struct caddy_answer {
+	uint32_t answer;
+	uint32_t issue;
+	uint32_t status;
+	uint32_t par[5];
+};
+
+struct caddy_interface {
+	uint8_t  magic[16];
+	uint32_t cmd_in;
+	uint32_t cmd_out;
+	uint32_t heartbeat;
+	uint32_t reserved1;
+	struct caddy_cmd cmd[CMD_SIZE];
+	uint32_t answer_in;
+	uint32_t answer_out;
+	uint32_t reserved2;
+	uint32_t reserved3;
+	struct caddy_answer answer[CMD_SIZE];
+};
+
+#endif /* of __CADDY_H__ */
diff --git a/roms/u-boot/board/esd/vme8349/pci.c b/roms/u-boot/board/esd/vme8349/pci.c
new file mode 100644
index 000000000..bf51d39b6
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/pci.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * pci.c -- esd VME8349 PCI board support.
+ * Copyright (c) 2006 Wind River Systems, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * Based on MPC8349 PCI support but w/o PIB related code.
+ */
+
+#include <init.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+#include <linux/delay.h>
+#include "vme8349pin.h"
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not supported. There is only one
+ * physical PCI slot on the board.
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci1_regions };
+	u8 reg8;
+	int monarch = 0;
+
+	i2c_set_bus_num(1);
+	/* Read the PCI_M66EN jumper setting */
+	if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, 1) == 0) ||
+	    (i2c_read(0x38                     , 0, 0, &reg8, 1) == 0)) {
+		if (reg8 & 0x40) {
+			clk->occr = 0xff000000;	/* 66 MHz PCI */
+			printf("PCI:   66MHz\n");
+		} else {
+			clk->occr = 0xffff0003;	/* 33 MHz PCI */
+			printf("PCI:   33MHz\n");
+		}
+		if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
+			monarch = 1;
+	} else {
+		clk->occr = 0xffff0003;	/* 33 MHz PCI */
+		printf("PCI:   33MHz (I2C read failed)\n");
+	}
+	udelay(2000);
+
+	/*
+	 * Assert/deassert VME reset
+	 */
+	clrsetbits_be32(&immr->gpio[1].dat,
+			GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
+			GPIO2_VME_RESET_N  | GPIO2_L_RESET_EN_N);
+	setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
+		     GPIO2_TSI_POWERUP_RESET_N |
+		     GPIO2_VME_RESET_N |
+		     GPIO2_L_RESET_EN_N);
+	clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
+	udelay(200);
+	setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
+	udelay(200);
+	setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
+	udelay(600000);
+	clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	udelay(2000);
+
+	if (monarch == 0) {
+		mpc83xx_pci_init(1, reg);
+	} else {
+		/*
+		 * Release PCI RST Output signal
+		 */
+		out_be32(&immr->pci_ctrl[0].gcr, 0);
+		udelay(2000);
+		out_be32(&immr->pci_ctrl[0].gcr, 1);
+	}
+}
diff --git a/roms/u-boot/board/esd/vme8349/vme8349.c b/roms/u-boot/board/esd/vme8349/vme8349.c
new file mode 100644
index 000000000..d388fc6d4
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/vme8349.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * vme8349.c -- esd VME8349 board support
+ *
+ * Copyright (c) 2008-2009 esd gmbh.
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/mpc8349_pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <linux/libfdt.h>
+#endif
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <spd.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void ddr_enable_ecc(unsigned int dram_size);
+
+int dram_init(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -ENXIO;
+
+	/* DDR SDRAM - Main memory */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
+
+	msize = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+	/* Now check memory size (after ECC is initialized) */
+	msize = get_ram_size(0, msize);
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_TARGET_CADDY2
+	puts("Board: esd VME-CADDY/2\n");
+#else
+	puts("Board: esd VME-CPU/8349\n");
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_TARGET_CADDY2
+int board_eth_init(struct bd_info *bis)
+{
+	return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
+#endif
+
+int misc_init_r()
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
+
+	return 0;
+}
+
+/*
+ * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
+ * and VME-CADDY/2) have different SDRAM configurations.
+ */
+#ifdef CONFIG_TARGET_CADDY2
+#define SMALL_RAM	0xff
+#define LARGE_RAM	0x00
+#else
+#define SMALL_RAM	0x00
+#define LARGE_RAM	0xff
+#endif
+
+#define SPD_VAL(a, b)	(((a) & SMALL_RAM) | ((b) & LARGE_RAM))
+
+static spd_eeprom_t default_spd_eeprom = {
+	SPD_VAL(0x80, 0x80),	/* 00 use 128 Bytes */
+	SPD_VAL(0x07, 0x07),	/* 01 use 128 Bytes */
+	SPD_MEMTYPE_DDR2,	/* 02 type is DDR2 */
+	SPD_VAL(0x0d, 0x0d),	/* 03 rows: 13 */
+	SPD_VAL(0x09, 0x0a),	/* 04 cols:  9 / 10 */
+	SPD_VAL(0x00, 0x00),	/* 05 */
+	SPD_VAL(0x40, 0x40),	/* 06 */
+	SPD_VAL(0x00, 0x00),	/* 07 */
+	SPD_VAL(0x05, 0x05),	/* 08 */
+	SPD_VAL(0x30, 0x30),	/* 09 */
+	SPD_VAL(0x45, 0x45),	/* 10 */
+	SPD_VAL(0x02, 0x02),	/* 11 ecc used */
+	SPD_VAL(0x82, 0x82),	/* 12 */
+	SPD_VAL(0x10, 0x10),	/* 13 */
+	SPD_VAL(0x08, 0x08),	/* 14 */
+	SPD_VAL(0x00, 0x00),	/* 15 */
+	SPD_VAL(0x0c, 0x0c),	/* 16 */
+	SPD_VAL(0x04, 0x08),	/* 17 banks: 4 / 8 */
+	SPD_VAL(0x38, 0x38),	/* 18 */
+	SPD_VAL(0x00, 0x00),	/* 19 */
+	SPD_VAL(0x02, 0x02),	/* 20 */
+	SPD_VAL(0x00, 0x00),	/* 21 */
+	SPD_VAL(0x03, 0x03),	/* 22 */
+	SPD_VAL(0x3d, 0x3d),	/* 23 */
+	SPD_VAL(0x45, 0x45),	/* 24 */
+	SPD_VAL(0x50, 0x50),	/* 25 */
+	SPD_VAL(0x45, 0x45),	/* 26 */
+	SPD_VAL(0x3c, 0x3c),	/* 27 */
+	SPD_VAL(0x28, 0x28),	/* 28 */
+	SPD_VAL(0x3c, 0x3c),	/* 29 */
+	SPD_VAL(0x2d, 0x2d),	/* 30 */
+	SPD_VAL(0x20, 0x80),	/* 31 */
+	SPD_VAL(0x20, 0x20),	/* 32 */
+	SPD_VAL(0x27, 0x27),	/* 33 */
+	SPD_VAL(0x10, 0x10),	/* 34 */
+	SPD_VAL(0x17, 0x17),	/* 35 */
+	SPD_VAL(0x3c, 0x3c),	/* 36 */
+	SPD_VAL(0x1e, 0x1e),	/* 37 */
+	SPD_VAL(0x1e, 0x1e),	/* 38 */
+	SPD_VAL(0x00, 0x00),	/* 39 */
+	SPD_VAL(0x00, 0x06),	/* 40 */
+	SPD_VAL(0x37, 0x37),	/* 41 */
+	SPD_VAL(0x4b, 0x7f),	/* 42 */
+	SPD_VAL(0x80, 0x80),	/* 43 */
+	SPD_VAL(0x18, 0x18),	/* 44 */
+	SPD_VAL(0x22, 0x22),	/* 45 */
+	SPD_VAL(0x00, 0x00),	/* 46 */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	SPD_VAL(0x10, 0x10),	/* 62 */
+	SPD_VAL(0x7e, 0x1d),	/* 63 */
+	{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
+	SPD_VAL(0x00, 0x00),	/* 72 */
+#ifdef CONFIG_TARGET_CADDY2
+	{ "vme-caddy/2 ram   " }
+#else
+	{ "vme-cpu/2 ram     " }
+#endif
+};
+
+int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	int old_bus = i2c_get_bus_num();
+	unsigned int l, sum;
+	int valid = 0;
+
+	i2c_set_bus_num(0);
+
+	if (i2c_read(chip, addr, alen, buffer, len) == 0)
+		if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
+			sum = 0;
+			for (l = 0; l < 63; l++)
+				sum = (sum + buffer[l]) & 0xff;
+			if (sum == buffer[63])
+				valid = 1;
+			else
+				printf("Invalid checksum in EEPROM %02x %02x\n",
+				       sum, buffer[63]);
+		}
+
+	if (valid == 0) {
+		memcpy(buffer, (void *)&default_spd_eeprom, len);
+		sum = 0;
+		for (l = 0; l < 63; l++)
+			sum = (sum + buffer[l]) & 0xff;
+		if (sum != buffer[63])
+			printf("Invalid checksum in FLASH %02x %02x\n",
+			       sum, buffer[63]);
+		buffer[63] = sum;
+	}
+
+	i2c_set_bus_num(old_bus);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/esd/vme8349/vme8349pin.h b/roms/u-boot/board/esd/vme8349/vme8349pin.h
new file mode 100644
index 000000000..9ae9c7bec
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/vme8349pin.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ */
+
+#ifndef __VME8349PIN_H__
+#define __VME8349PIN_H__
+
+#define GPIO2_V_SCON		0x80000000 /* In:  from tsi148 1: is syscon */
+#define GPIO2_VME_RESET_N	0x20000000 /* Out: to tsi148                */
+#define GPIO2_TSI_PLL_RESET_N	0x08000000 /* Out: to tsi148                */
+#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148              */
+#define GPIO2_L_RESET_EN_N	0x00100000 /* Out: 0:vme can assert cpu lrst*/
+
+#endif /* of ifndef __VME8349PIN_H__ */
diff --git a/roms/u-boot/board/firefly/firefly-rk3288/Kconfig b/roms/u-boot/board/firefly/firefly-rk3288/Kconfig
new file mode 100644
index 000000000..1c2bca868
--- /dev/null
+++ b/roms/u-boot/board/firefly/firefly-rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_FIREFLY_RK3288
+
+config SYS_BOARD
+	default "firefly-rk3288"
+
+config SYS_VENDOR
+	default "firefly"
+
+config SYS_CONFIG_NAME
+	default "firefly-rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/firefly/firefly-rk3288/MAINTAINERS b/roms/u-boot/board/firefly/firefly-rk3288/MAINTAINERS
new file mode 100644
index 000000000..42db0bd5e
--- /dev/null
+++ b/roms/u-boot/board/firefly/firefly-rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+FIREFLY
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/firefly/firefly-rk3288
+F:	include/configs/firefly-rk3288.h
+F:	configs/firefly-rk3288_defconfig
diff --git a/roms/u-boot/board/firefly/firefly-rk3288/Makefile b/roms/u-boot/board/firefly/firefly-rk3288/Makefile
new file mode 100644
index 000000000..671684597
--- /dev/null
+++ b/roms/u-boot/board/firefly/firefly-rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= firefly-rk3288.o
diff --git a/roms/u-boot/board/firefly/firefly-rk3288/firefly-rk3288.c b/roms/u-boot/board/firefly/firefly-rk3288/firefly-rk3288.c
new file mode 100644
index 000000000..41c49e5da
--- /dev/null
+++ b/roms/u-boot/board/firefly/firefly-rk3288/firefly-rk3288.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <led.h>
+#include <log.h>
+#include <asm/global_data.h>
+
+#ifdef CONFIG_SPL_BUILD
+DECLARE_GLOBAL_DATA_PTR;
+static int setup_led(void)
+{
+#ifdef CONFIG_SPL_LED
+	struct udevice *dev;
+	char *led_name;
+	int ret;
+
+	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
+	if (!led_name)
+		return 0;
+	ret = led_get_by_label(led_name, &dev);
+	if (ret) {
+		debug("%s: get=%d\n", __func__, ret);
+		return ret;
+	}
+	ret = led_set_state(dev, LEDST_ON);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	int ret;
+
+	ret = setup_led();
+	if (ret) {
+		debug("LED ret=%d\n", ret);
+		hang();
+	}
+}
+#endif
diff --git a/roms/u-boot/board/firefly/firefly-rk3308/Kconfig b/roms/u-boot/board/firefly/firefly-rk3308/Kconfig
new file mode 100644
index 000000000..80b1ad85a
--- /dev/null
+++ b/roms/u-boot/board/firefly/firefly-rk3308/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROC_RK3308_CC
+
+config SYS_BOARD
+	default "firefly-rk3308"
+
+config SYS_VENDOR
+	default "firefly"
+
+config SYS_CONFIG_NAME
+	default "firefly_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/firefly/firefly-rk3308/MAINTAINERS b/roms/u-boot/board/firefly/firefly-rk3308/MAINTAINERS
new file mode 100644
index 000000000..199079717
--- /dev/null
+++ b/roms/u-boot/board/firefly/firefly-rk3308/MAINTAINERS
@@ -0,0 +1,5 @@
+ROC-RK3308-CC
+M:      Andy Yan <andy.yan@rock-chips.com>
+S:      Maintained
+F:      board/firefly/firefly-rk3308/roc_cc_rk3308.c
+F:      configs/roc-cc-rk3308_defconfig
diff --git a/roms/u-boot/board/firefly/firefly-rk3308/Makefile b/roms/u-boot/board/firefly/firefly-rk3308/Makefile
new file mode 100644
index 000000000..4c50b26ea
--- /dev/null
+++ b/roms/u-boot/board/firefly/firefly-rk3308/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= roc_cc_rk3308.o
diff --git a/roms/u-boot/board/firefly/firefly-rk3308/roc_cc_rk3308.c b/roms/u-boot/board/firefly/firefly-rk3308/roc_cc_rk3308.c
new file mode 100644
index 000000000..28dcc2a69
--- /dev/null
+++ b/roms/u-boot/board/firefly/firefly-rk3308/roc_cc_rk3308.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <adc.h>
+#include <asm/io.h>
+#include <asm/arch/grf_rk3308.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <linux/bitops.h>
+
+#if defined(CONFIG_DEBUG_UART)
+#define GRF_BASE	0xff000000
+
+enum {
+	GPIO1C7_SHIFT		= 8,
+	GPIO1C7_MASK		= GENMASK(11, 8),
+	GPIO1C7_GPIO		= 0,
+	GPIO1C7_UART1_RTSN,
+	GPIO1C7_UART2_TX_M0,
+	GPIO1C7_SPI2_MOSI,
+	GPIO1C7_JTAG_TMS,
+
+	GPIO1C6_SHIFT		= 4,
+	GPIO1C6_MASK		= GENMASK(7, 4),
+	GPIO1C6_GPIO		= 0,
+	GPIO1C6_UART1_CTSN,
+	GPIO1C6_UART2_RX_M0,
+	GPIO1C6_SPI2_MISO,
+	GPIO1C6_JTAG_TCLK,
+
+	GPIO4D3_SHIFT           = 6,
+	GPIO4D3_MASK            = GENMASK(7, 6),
+	GPIO4D3_GPIO            = 0,
+	GPIO4D3_SDMMC_D3,
+	GPIO4D3_UART2_TX_M1,
+
+	GPIO4D2_SHIFT           = 4,
+	GPIO4D2_MASK            = GENMASK(5, 4),
+	GPIO4D2_GPIO            = 0,
+	GPIO4D2_SDMMC_D2,
+	GPIO4D2_UART2_RX_M1,
+
+	UART2_IO_SEL_SHIFT	= 2,
+	UART2_IO_SEL_MASK	= GENMASK(3, 2),
+	UART2_IO_SEL_M0		= 0,
+	UART2_IO_SEL_M1,
+	UART2_IO_SEL_USB,
+};
+
+void board_debug_uart_init(void)
+{
+	static struct rk3308_grf * const grf = (void *)GRF_BASE;
+
+	/* Enable early UART2 channel m0 on the rk3308 */
+	rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
+		     UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
+	rk_clrsetreg(&grf->gpio1ch_iomux,
+		     GPIO1C6_MASK | GPIO1C7_MASK,
+		     GPIO1C6_UART2_RX_M0 << GPIO1C6_SHIFT |
+		     GPIO1C7_UART2_TX_M0 << GPIO1C7_SHIFT);
+}
+#endif
+
+#define KEY_DOWN_MIN_VAL        0
+#define KEY_DOWN_MAX_VAL        30
+
+int rockchip_dnl_key_pressed(void)
+{
+	unsigned int val;
+
+	if (adc_channel_single_shot("saradc", 1, &val)) {
+		printf("%s read adc key val failed\n", __func__);
+		return false;
+	}
+
+	if (val >= KEY_DOWN_MIN_VAL && val <= KEY_DOWN_MAX_VAL)
+		return true;
+	else
+		return false;
+}
diff --git a/roms/u-boot/board/firefly/roc-pc-rk3399/Kconfig b/roms/u-boot/board/firefly/roc-pc-rk3399/Kconfig
new file mode 100644
index 000000000..720fbbb5f
--- /dev/null
+++ b/roms/u-boot/board/firefly/roc-pc-rk3399/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_ROC_PC_RK3399
+
+config SYS_BOARD
+        default "roc-pc-rk3399"
+
+config SYS_VENDOR
+        default "firefly"
+
+config SYS_CONFIG_NAME
+        default "roc-pc-rk3399"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+        def_bool y
+
+endif
+
diff --git a/roms/u-boot/board/firefly/roc-pc-rk3399/MAINTAINERS b/roms/u-boot/board/firefly/roc-pc-rk3399/MAINTAINERS
new file mode 100644
index 000000000..68a5b757d
--- /dev/null
+++ b/roms/u-boot/board/firefly/roc-pc-rk3399/MAINTAINERS
@@ -0,0 +1,8 @@
+ROC-RK3399-PC
+M:	Levin Du <djw@t-chip.com.cn>
+M:	Suniel Mahesh <sunil@amarulasolutions.com>
+S:	Maintained
+F:	board/firefly/roc-pc-rk3399
+F:	include/configs/roc-pc-rk3399.h
+F:	configs/roc-pc-rk3399_defconfig
+F:	configs/roc-pc-mezzanine-rk3399_defconfig
diff --git a/roms/u-boot/board/firefly/roc-pc-rk3399/Makefile b/roms/u-boot/board/firefly/roc-pc-rk3399/Makefile
new file mode 100644
index 000000000..29c79b25d
--- /dev/null
+++ b/roms/u-boot/board/firefly/roc-pc-rk3399/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= roc-pc-rk3399.o
diff --git a/roms/u-boot/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/roms/u-boot/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
new file mode 100644
index 000000000..93e7d776f
--- /dev/null
+++ b/roms/u-boot/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <log.h>
+#include <spl_gpio.h>
+#include <asm/io.h>
+#include <power/regulator.h>
+
+#include <asm/arch-rockchip/cru.h>
+#include <asm/arch-rockchip/gpio.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+
+#ifndef CONFIG_SPL_BUILD
+int board_early_init_f(void)
+{
+	struct udevice *regulator;
+	int ret;
+
+	ret = regulator_get_by_platname("vcc5v0_host", &regulator);
+	if (ret) {
+		debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
+		goto out;
+	}
+
+	ret = regulator_set_enable(regulator, true);
+	if (ret)
+		debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret);
+out:
+	return 0;
+}
+
+#else
+
+#define PMUGRF_BASE	0xff320000
+#define GPIO0_BASE	0xff720000
+
+/**
+ * LED setup for roc-rk3399-pc
+ *
+ * 1. Set the low power leds (only during POR, pwr_key env is 'y')
+ *    glow yellow LED, termed as low power
+ *    poll for on board power key press
+ *    once powe key pressed, turn off yellow
+ * 2. Turn on red LED, indicating full power mode
+ */
+void led_setup(void)
+{
+	struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE;
+	struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
+	bool press_pwr_key = false;
+
+	if (IS_ENABLED(CONFIG_SPL_ENV_SUPPORT)) {
+		env_init();
+		env_load();
+		if (env_get_yesno("pwr_key") == 1)
+			press_pwr_key = true;
+	}
+
+	if (press_pwr_key && !strcmp(get_reset_cause(), "POR")) {
+		spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1);
+
+		spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5),
+				  GPIO_PULL_NORMAL);
+		while (readl(&gpio0->ext_port) & 0x20)
+			;
+
+		spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0);
+	}
+
+	spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
+}
+
+#endif
diff --git a/roms/u-boot/board/freescale/common/Kconfig b/roms/u-boot/board/freescale/common/Kconfig
new file mode 100644
index 000000000..17db75595
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/Kconfig
@@ -0,0 +1,57 @@
+config CHAIN_OF_TRUST
+	depends on !FIT_SIGNATURE && NXP_ESBC
+	imply CMD_BLOB
+	imply CMD_HASH if ARM
+	select FSL_CAAM
+	select SPL_BOARD_INIT if (ARM && SPL)
+	select SHA_HW_ACCEL
+	select SHA_PROG_HW_ACCEL
+	select ENV_IS_NOWHERE
+	select CMD_EXT4 if ARM
+	select CMD_EXT4_WRITE if ARM
+	bool
+	default y
+
+config CMD_ESBC_VALIDATE
+	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
+	default y if CHAIN_OF_TRUST
+	help
+	  This option enables two commands used for secure booting:
+
+	    esbc_validate - validate signature using RSA verification
+	    esbc_halt - put the core in spin loop (Secure Boot Only)
+
+config VID
+	depends on DM_I2C
+	bool "Enable Freescale VID"
+	help
+	 This option enables setting core voltage based on individual
+	 values saved in SoC fuses.
+
+config VOL_MONITOR_LTC3882_READ
+	depends on VID
+	bool "Enable the LTC3882 voltage monitor read"
+	help
+	 This option enables LTC3882 voltage monitor read
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_LTC3882_SET
+	depends on VID
+	bool "Enable the LTC3882 voltage monitor set"
+	help
+	 This option enables LTC3882 voltage monitor set
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_ISL68233_READ
+	depends on VID
+	bool "Enable the ISL68233 voltage monitor read"
+	help
+	 This option enables ISL68233 voltage monitor read
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_ISL68233_SET
+	depends on VID
+	bool "Enable the ISL68233 voltage monitor set"
+	help
+	 This option enables ISL68233 voltage monitor set
+	 functionality. It is used by the common VID driver.
diff --git a/roms/u-boot/board/freescale/common/Makefile b/roms/u-boot/board/freescale/common/Makefile
new file mode 100644
index 000000000..114b7ba8f
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/Makefile
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-$(CONFIG_FSL_CADMUS)	+= cadmus.o
+obj-$(CONFIG_FSL_VIA)		+= cds_via.o
+obj-$(CONFIG_FMAN_ENET)	+= fman.o
+obj-$(CONFIG_FSL_PIXIS)	+= pixis.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_FSL_NGPIXIS)	+= ngpixis.o
+endif
+obj-$(CONFIG_VID)		+= vid.o
+obj-$(CONFIG_FSL_QIXIS)	+= qixis.o
+obj-$(CONFIG_PQ_MDS_PIB)	+= pq-mds-pib.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ID_EEPROM)	+= sys_eeprom.o
+endif
+obj-$(CONFIG_FSL_SGMII_RISER)	+= sgmii_riser.o
+ifndef CONFIG_RAMBOOT_PBL
+obj-$(CONFIG_FSL_FIXED_MMC_LOCATION)	+= sdhc_boot.o
+endif
+
+obj-$(CONFIG_FSL_DIU_CH7301)	+= diu_ch7301.o
+
+ifdef CONFIG_ARM
+obj-$(CONFIG_DEEP_SLEEP)		+= arm_sleep.o
+else
+obj-$(CONFIG_DEEP_SLEEP)		+= mpc85xx_sleep.o
+endif
+
+obj-$(CONFIG_FSL_DCU_SII9022A)    += dcu_sii9022a.o
+
+obj-$(CONFIG_TARGET_MPC8541CDS)	+= cds_pci_ft.o
+obj-$(CONFIG_TARGET_MPC8548CDS)	+= cds_pci_ft.o
+obj-$(CONFIG_TARGET_MPC8555CDS)	+= cds_pci_ft.o
+
+obj-$(CONFIG_TARGET_MPC8536DS)	+= ics307_clk.o
+obj-$(CONFIG_TARGET_P1022DS)		+= ics307_clk.o
+obj-$(CONFIG_P2020DS)		+= ics307_clk.o
+obj-$(CONFIG_TARGET_P3041DS)		+= ics307_clk.o
+obj-$(CONFIG_TARGET_P4080DS)		+= ics307_clk.o
+obj-$(CONFIG_TARGET_P5040DS)		+= ics307_clk.o
+obj-$(CONFIG_VSC_CROSSBAR)    += vsc3316_3308.o
+obj-$(CONFIG_IDT8T49N222A)	+= idt8t49n222a_serdes_clk.o
+obj-$(CONFIG_ZM7300)		+= zm7300.o
+obj-$(CONFIG_POWER_PFUZE100)	+= pfuze.o
+obj-$(CONFIG_DM_PMIC_PFUZE100)	+= pfuze.o
+obj-$(CONFIG_POWER_MC34VR500)	+= mc34vr500.o
+
+obj-$(CONFIG_LS102XA_STREAM_ID)	+= ls102xa_stream_id.o
+
+obj-$(CONFIG_EMC2305)              += emc2305.o
+
+# deal with common files for P-series corenet based devices
+obj-$(CONFIG_TARGET_P2041RDB)	+= p_corenet/
+obj-$(CONFIG_TARGET_P3041DS)	+= p_corenet/
+obj-$(CONFIG_TARGET_P4080DS)	+= p_corenet/
+obj-$(CONFIG_TARGET_P5020DS)	+= p_corenet/
+obj-$(CONFIG_TARGET_P5040DS)	+= p_corenet/
+
+obj-$(CONFIG_LAYERSCAPE_NS_ACCESS)	+= ns_access.o
+
+ifdef CONFIG_NXP_ESBC
+obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
+endif
+obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
+
+endif
diff --git a/roms/u-boot/board/freescale/common/arm_sleep.c b/roms/u-boot/board/freescale/common/arm_sleep.c
new file mode 100644
index 000000000..733940860
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/arm_sleep.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#ifndef CONFIG_ARMV7_NONSEC
+#error " Deep sleep needs non-secure mode support. "
+#else
+#include <asm/secure.h>
+#endif
+#include <asm/armv7.h>
+
+#if defined(CONFIG_ARCH_LS1021A)
+#include <asm/arch/immap_ls102xa.h>
+#endif
+
+#include "sleep.h"
+#ifdef CONFIG_U_QE
+#include <fsl_qe.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+void __weak board_sleep_prepare(void)
+{
+}
+
+bool is_warm_boot(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
+		return 1;
+
+	return 0;
+}
+
+void fsl_dp_disable_console(void)
+{
+	gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+}
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+static void dp_ddr_restore(void)
+{
+	u64 *src, *dst;
+	int i;
+	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+	/* get the address of ddr date from SPARECR3 */
+	src = (u64 *)in_le32(&scfg->sparecr[2]);
+	dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+
+	for (i = 0; i < DDR_BUFF_LEN / 8; i++)
+		*dst++ = *src++;
+}
+
+#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A)
+void ls1_psci_resume_fixup(void)
+{
+	u32 tmp;
+	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef QIXIS_BASE
+	void *qixis_base = (void *)QIXIS_BASE;
+
+	/* Pull on PCIe RST# */
+	out_8(qixis_base + QIXIS_RST_FORCE_3, 0);
+
+	/* disable deep sleep signals in FPGA */
+	tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
+	tmp &= ~QIXIS_PWR_CTL2_PCTL;
+	out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
+#endif
+
+	/* Disable wakeup interrupt during deep sleep */
+	out_be32(&scfg->pmcintecr, 0);
+	/* Clear PMC interrupt status */
+	out_be32(&scfg->pmcintsr, 0xffffffff);
+
+	/* Disable Warm Device Reset */
+	tmp = in_be32(&scfg->dpslpcr);
+	tmp &= ~SCFG_DPSLPCR_WDRR_EN;
+	out_be32(&scfg->dpslpcr, tmp);
+}
+#endif
+
+static void dp_resume_prepare(void)
+{
+	dp_ddr_restore();
+	board_sleep_prepare();
+	armv7_init_nonsec();
+#ifdef CONFIG_U_QE
+	u_qe_resume();
+#endif
+#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A)
+	ls1_psci_resume_fixup();
+#endif
+}
+
+int fsl_dp_resume(void)
+{
+	u32 start_addr;
+	void (*kernel_resume)(void);
+	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+	if (!is_warm_boot())
+		return 0;
+
+	dp_resume_prepare();
+
+	/* Get the entry address and jump to kernel */
+	start_addr = in_le32(&scfg->sparecr[3]);
+	debug("Entry address is 0x%08x\n", start_addr);
+	kernel_resume = (void (*)(void))start_addr;
+	secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/common/cadmus.c b/roms/u-boot/board/freescale/common/cadmus.c
new file mode 100644
index 000000000..7e7394f33
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/cadmus.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ */
+
+
+#include <common.h>
+
+
+/*
+ * CADMUS Board System Registers
+ */
+#ifndef CONFIG_SYS_CADMUS_BASE_REG
+#define CONFIG_SYS_CADMUS_BASE_REG	(CADMUS_BASE_ADDR + 0x4000)
+#endif
+
+typedef struct cadmus_reg {
+    u_char cm_ver;		/* Board version */
+    u_char cm_csr;		/* General control/status */
+    u_char cm_rst;		/* Reset control */
+    u_char cm_hsclk;		/* High speed clock */
+    u_char cm_hsxclk;		/* High speed clock extended */
+    u_char cm_led;		/* LED data */
+    u_char cm_pci;		/* PCI control/status */
+    u_char cm_dma;		/* DMA control */
+    u_char cm_reserved[248];	/* Total 256 bytes */
+} cadmus_reg_t;
+
+
+unsigned int
+get_board_version(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+
+	return cadmus->cm_ver;
+}
+
+
+unsigned long
+get_clock_freq(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+
+	uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
+
+	if (pci1_speed == 0) {
+		return 33333333;
+	} else if (pci1_speed == 1) {
+		return 66666666;
+	} else {
+		/* Really, unknown. Be safe? */
+		return 33333333;
+	}
+}
+
+
+unsigned int
+get_pci_slot(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+
+	/*
+	 * PCI slot in USER bits CSR[6:7] by convention.
+	 */
+	return ((cadmus->cm_csr >> 6) & 0x3) + 1;
+}
+
+
+unsigned int
+get_pci_dual(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+
+	/*
+	 * PCI DUAL in CM_PCI[3]
+	 */
+	return cadmus->cm_pci & 0x10;
+}
diff --git a/roms/u-boot/board/freescale/common/cadmus.h b/roms/u-boot/board/freescale/common/cadmus.h
new file mode 100644
index 000000000..ddc2bb6c1
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/cadmus.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ */
+
+#ifndef __CADMUS_H_
+#define __CADMUS_H_
+
+
+/*
+ * CADMUS Board System Register interface.
+ */
+
+/*
+ * Returns board version register.
+ */
+extern unsigned int get_board_version(void);
+
+/*
+ * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
+ */
+extern unsigned long get_clock_freq(void);
+
+
+/*
+ * Returns 1 - 4, as found in the USER CSR[6:7] bits.
+ */
+extern unsigned int get_pci_slot(void);
+
+
+/*
+ * Returns PCI DUAL as found in CM_PCI[3].
+ */
+extern unsigned int get_pci_dual(void);
+
+
+#endif	/* __CADMUS_H_ */
diff --git a/roms/u-boot/board/freescale/common/cds_pci_ft.c b/roms/u-boot/board/freescale/common/cds_pci_ft.c
new file mode 100644
index 000000000..be97a28ed
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/cds_pci_ft.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ */
+
+#include <common.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include "cadmus.h"
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
+static void cds_pci_fixup(void *blob)
+{
+	int node;
+	const char *path;
+	int len, slot, i;
+	u32 *map = NULL, *piccells = NULL;
+	int off, cells;
+
+	node = fdt_path_offset(blob, "/aliases");
+	if (node >= 0) {
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			node = fdt_path_offset(blob, path);
+			if (node >= 0) {
+				map = fdt_getprop_w(blob, node, "interrupt-map", &len);
+			}
+			/* Each item in "interrupt-map" property is translated with
+			 * following cells:
+			 * PCI #address-cells, PCI #interrupt-cells,
+			 * PIC address, PIC #address-cells, PIC #interrupt-cells.
+			 */
+			cells = fdt_getprop_u32_default(blob, path, "#address-cells", 1);
+			cells += fdt_getprop_u32_default(blob, path, "#interrupt-cells", 1);
+			off = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*(map+cells)));
+			if (off <= 0)
+				return;
+			cells += 1;
+			piccells = (u32 *)fdt_getprop(blob, off, "#address-cells", NULL);
+			if (piccells == NULL)
+				return;
+			cells += *piccells;
+			piccells = (u32 *)fdt_getprop(blob, off, "#interrupt-cells", NULL);
+			if (piccells == NULL)
+				return;
+			cells += *piccells;
+		}
+	}
+
+	if (map) {
+		len /= sizeof(u32);
+
+		slot = get_pci_slot();
+
+		for (i=0;i<len;i+=cells) {
+			/* We rotate the interrupt pins so that the mapping
+			 * changes depending on the slot the carrier card is in.
+			 */
+			map[3] = ((map[3] + slot - 2) % 4) + 1;
+			map+=cells;
+		}
+	}
+}
+#endif
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
+	ft_pci_setup(blob, bd);
+	cds_pci_fixup(blob);
+#endif
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/common/cds_via.c b/roms/u-boot/board/freescale/common/cds_via.c
new file mode 100644
index 000000000..8f8f0d1f5
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/cds_via.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ */
+
+#include <common.h>
+#include <pci.h>
+
+/* Config the VIA chip */
+void mpc85xx_config_via(struct pci_controller *hose,
+			pci_dev_t dev, struct pci_config_table *tab)
+{
+	pci_dev_t bridge;
+	unsigned int cmdstat;
+
+	/* Enable USB and IDE functions */
+	pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
+
+	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+	cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
+	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+
+	/*
+	 * Force the backplane P2P bridge to have a window
+	 * open from 0x00000000-0x00001fff in PCI I/O space.
+	 * This allows legacy I/O (i8259, etc) on the VIA
+	 * southbridge to be accessed.
+	 */
+	bridge = PCI_BDF(0,BRIDGE_ID,0);
+	pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
+	pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
+	pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
+	pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
+}
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller *hose,
+			       pci_dev_t dev, struct pci_config_table *tab)
+{
+	pciauto_config_device(hose, dev);
+	/*
+	 * Since the P2P window was forced to cover the fixed
+	 * legacy I/O addresses, it is necessary to manually
+	 * place the base addresses for the IDE and USB functions
+	 * within this window.
+	 */
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
+}
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller *hose,
+			    pci_dev_t dev, struct pci_config_table *tab)
+{
+	pciauto_config_device(hose, dev);
+
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
+}
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller *hose,
+			     pci_dev_t dev, struct pci_config_table *tab)
+{
+	pciauto_config_device(hose, dev);
+
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
+}
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller *hose,
+			      pci_dev_t dev, struct pci_config_table *tab)
+{
+	pciauto_config_device(hose, dev);
+
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
+}
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller *hose,
+			     pci_dev_t dev, struct pci_config_table *tab)
+{
+	pciauto_config_device(hose, dev);
+
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
+}
diff --git a/roms/u-boot/board/freescale/common/cmd_esbc_validate.c b/roms/u-boot/board/freescale/common/cmd_esbc_validate.c
new file mode 100644
index 000000000..638aa3c19
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/cmd_esbc_validate.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <fsl_validate.h>
+
+int do_esbc_halt(struct cmd_tbl *cmdtp, int flag, int argc,
+		 char *const argv[])
+{
+	if (fsl_check_boot_mode_secure() == 0) {
+		printf("Boot Mode is Non-Secure. Not entering spin loop.\n");
+		return 0;
+	}
+
+	printf("Core is entering spin loop.\n");
+loop:
+	goto loop;
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int do_esbc_validate(struct cmd_tbl *cmdtp, int flag, int argc,
+			    char *const argv[])
+{
+	char *hash_str = NULL;
+	uintptr_t haddr;
+	int ret;
+	uintptr_t img_addr = 0;
+	char buf[20];
+
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+	else if (argc > 2)
+		/* Second arg - Optional - Hash Str*/
+		hash_str = argv[2];
+
+	/* First argument - header address -32/64bit */
+	haddr = (uintptr_t)simple_strtoul(argv[1], NULL, 16);
+
+	/* With esbc_validate command, Image address must be
+	 * part of header. So, the function is called
+	 * by passing this argument as 0.
+	 */
+	ret = fsl_secboot_validate(haddr, hash_str, &img_addr);
+
+	/* Need to set "img_addr" even if validation failure.
+	 * Required when SB_EN in RCW set and non-fatal error
+	 * to continue U-Boot
+	 */
+	sprintf(buf, "%lx", img_addr);
+	env_set("img_addr", buf);
+
+	if (ret)
+		return 1;
+
+	printf("esbc_validate command successful\n");
+	return 0;
+}
+
+/***************************************************/
+static char esbc_validate_help_text[] =
+	"esbc_validate hdr_addr <hash_val> - Validates signature using\n"
+	"                          RSA verification\n"
+	"                          $hdr_addr Address of header of the image\n"
+	"                          to be validated.\n"
+	"                          $hash_val -Optional\n"
+	"                          It provides Hash of public/srk key to be\n"
+	"                          used to verify signature.\n";
+
+U_BOOT_CMD(
+	esbc_validate,	3,	0,	do_esbc_validate,
+	"Validates signature on a given image using RSA verification",
+	esbc_validate_help_text
+);
+
+U_BOOT_CMD(
+	esbc_halt,	1,	0,	do_esbc_halt,
+	"Put the core in spin loop (Secure Boot Only)",
+	""
+);
+#endif
diff --git a/roms/u-boot/board/freescale/common/dcu_sii9022a.c b/roms/u-boot/board/freescale/common/dcu_sii9022a.c
new file mode 100644
index 000000000..9137d246e
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/dcu_sii9022a.c
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include <i2c.h>
+#include <linux/fb.h>
+
+#define PIXEL_CLK_LSB_REG		0x00
+#define PIXEL_CLK_MSB_REG		0x01
+#define VERT_FREQ_LSB_REG		0x02
+#define VERT_FREQ_MSB_REG		0x03
+#define TOTAL_PIXELS_LSB_REG		0x04
+#define TOTAL_PIXELS_MSB_REG		0x05
+#define TOTAL_LINES_LSB_REG		0x06
+#define TOTAL_LINES_MSB_REG		0x07
+#define TPI_INBUS_FMT_REG		0x08
+#define TPI_INPUT_FMT_REG		0x09
+#define TPI_OUTPUT_FMT_REG		0x0A
+#define TPI_SYS_CTRL_REG		0x1A
+#define TPI_PWR_STAT_REG		0x1E
+#define TPI_AUDIO_HANDING_REG		0x25
+#define TPI_AUDIO_INTF_REG		0x26
+#define TPI_AUDIO_FREQ_REG		0x27
+#define TPI_SET_PAGE_REG		0xBC
+#define TPI_SET_OFFSET_REG		0xBD
+#define TPI_RW_ACCESS_REG		0xBE
+#define TPI_TRANS_MODE_REG		0xC7
+
+#define TPI_INBUS_CLOCK_RATIO_1		(1 << 6)
+#define TPI_INBUS_FULL_PIXEL_WIDE	(1 << 5)
+#define TPI_INBUS_RISING_EDGE		(1 << 4)
+#define TPI_INPUT_CLR_DEPTH_8BIT	(0 << 6)
+#define TPI_INPUT_VRANGE_EXPAN_AUTO	(0 << 2)
+#define TPI_INPUT_CLR_RGB		(0 << 0)
+#define TPI_OUTPUT_CLR_DEPTH_8BIT	(0 << 6)
+#define TPI_OUTPUT_VRANGE_COMPRE_AUTO	(0 << 2)
+#define TPI_OUTPUT_CLR_HDMI_RGB		(0 << 0)
+#define TPI_SYS_TMDS_OUTPUT		(0 << 4)
+#define TPI_SYS_AV_NORAML		(0 << 3)
+#define TPI_SYS_AV_MUTE			(1 << 3)
+#define TPI_SYS_DVI_MODE		(0 << 0)
+#define TPI_SYS_HDMI_MODE		(1 << 0)
+#define TPI_PWR_STAT_MASK		(3 << 0)
+#define TPI_PWR_STAT_D0			(0 << 0)
+#define TPI_AUDIO_PASS_BASIC		(0 << 0)
+#define TPI_AUDIO_INTF_I2S		(2 << 6)
+#define TPI_AUDIO_INTF_NORMAL		(0 << 4)
+#define TPI_AUDIO_TYPE_PCM		(1 << 0)
+#define TPI_AUDIO_SAMP_SIZE_16BIT	(1 << 6)
+#define TPI_AUDIO_SAMP_FREQ_44K		(2 << 3)
+#define TPI_SET_PAGE_SII9022A		0x01
+#define TPI_SET_OFFSET_SII9022A		0x82
+#define TPI_RW_EN_SRC_TERMIN		(1 << 0)
+#define TPI_TRANS_MODE_ENABLE		(0 << 7)
+
+/* Programming of Silicon SIi9022a HDMI Transmitter */
+int dcu_set_dvi_encoder(struct fb_videomode *videomode)
+{
+	u8 temp;
+	u16 temp1, temp2;
+	u32 temp3;
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
+				      CONFIG_SYS_I2C_DVI_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       CONFIG_SYS_I2C_DVI_BUS_NUM);
+		return ret;
+	}
+
+	/* Enable TPI transmitter mode */
+	temp = TPI_TRANS_MODE_ENABLE;
+	dm_i2c_write(dev, TPI_TRANS_MODE_REG, &temp, 1);
+
+	/* Enter into D0 state, full operation */
+	dm_i2c_read(dev, TPI_PWR_STAT_REG, &temp, 1);
+	temp &= ~TPI_PWR_STAT_MASK;
+	temp |= TPI_PWR_STAT_D0;
+	dm_i2c_write(dev, TPI_PWR_STAT_REG, &temp, 1);
+
+	/* Enable source termination */
+	temp = TPI_SET_PAGE_SII9022A;
+	dm_i2c_write(dev, TPI_SET_PAGE_REG, &temp, 1);
+	temp = TPI_SET_OFFSET_SII9022A;
+	dm_i2c_write(dev, TPI_SET_OFFSET_REG, &temp, 1);
+
+	dm_i2c_read(dev, TPI_RW_ACCESS_REG, &temp, 1);
+	temp |= TPI_RW_EN_SRC_TERMIN;
+	dm_i2c_write(dev, TPI_RW_ACCESS_REG, &temp, 1);
+
+	/* Set TPI system control */
+	temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
+	dm_i2c_write(dev, TPI_SYS_CTRL_REG, &temp, 1);
+
+	/* Set pixel clock */
+	temp1 = PICOS2KHZ(videomode->pixclock) / 10;
+	temp = (u8)(temp1 & 0xFF);
+	dm_i2c_write(dev, PIXEL_CLK_LSB_REG, &temp, 1);
+	temp = (u8)(temp1 >> 8);
+	dm_i2c_write(dev, PIXEL_CLK_MSB_REG, &temp, 1);
+
+	/* Set total pixels per line */
+	temp1 = videomode->hsync_len + videomode->left_margin +
+		videomode->xres + videomode->right_margin;
+	temp = (u8)(temp1 & 0xFF);
+	dm_i2c_write(dev, TOTAL_PIXELS_LSB_REG, &temp, 1);
+	temp = (u8)(temp1 >> 8);
+	dm_i2c_write(dev, TOTAL_PIXELS_MSB_REG, &temp, 1);
+
+	/* Set total lines */
+	temp2 = videomode->vsync_len + videomode->upper_margin +
+		videomode->yres + videomode->lower_margin;
+	temp = (u8)(temp2 & 0xFF);
+	dm_i2c_write(dev, TOTAL_LINES_LSB_REG, &temp, 1);
+	temp = (u8)(temp2 >> 8);
+	dm_i2c_write(dev, TOTAL_LINES_MSB_REG, &temp, 1);
+
+	/* Set vertical frequency in Hz */
+	temp3 = temp1 * temp2;
+	temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3;
+	temp1 = (u16)temp3 * 100;
+	temp = (u8)(temp1 & 0xFF);
+	dm_i2c_write(dev, VERT_FREQ_LSB_REG, &temp, 1);
+	temp = (u8)(temp1 >> 8);
+	dm_i2c_write(dev, VERT_FREQ_MSB_REG, &temp, 1);
+
+	/* Set TPI input bus and pixel repetition data */
+	temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE |
+		TPI_INBUS_RISING_EDGE;
+	dm_i2c_write(dev, TPI_INBUS_FMT_REG, &temp, 1);
+
+	/* Set TPI AVI Input format data */
+	temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO |
+		TPI_INPUT_CLR_RGB;
+	dm_i2c_write(dev, TPI_INPUT_FMT_REG, &temp, 1);
+
+	/* Set TPI AVI Output format data */
+	temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO |
+		TPI_OUTPUT_CLR_HDMI_RGB;
+	dm_i2c_write(dev, TPI_OUTPUT_FMT_REG, &temp, 1);
+
+	/* Set TPI audio configuration write data */
+	temp = TPI_AUDIO_PASS_BASIC;
+	dm_i2c_write(dev, TPI_AUDIO_HANDING_REG, &temp, 1);
+
+	temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL |
+		TPI_AUDIO_TYPE_PCM;
+	dm_i2c_write(dev, TPI_AUDIO_INTF_REG, &temp, 1);
+
+	temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
+	dm_i2c_write(dev, TPI_AUDIO_FREQ_REG, &temp, 1);
+#else
+	i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
+
+	/* Enable TPI transmitter mode */
+	temp = TPI_TRANS_MODE_ENABLE;
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_TRANS_MODE_REG, 1, &temp, 1);
+
+	/* Enter into D0 state, full operation */
+	i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
+	temp &= ~TPI_PWR_STAT_MASK;
+	temp |= TPI_PWR_STAT_D0;
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
+
+	/* Enable source termination */
+	temp = TPI_SET_PAGE_SII9022A;
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_PAGE_REG, 1, &temp, 1);
+	temp = TPI_SET_OFFSET_SII9022A;
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_OFFSET_REG, 1, &temp, 1);
+
+	i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
+	temp |= TPI_RW_EN_SRC_TERMIN;
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
+
+	/* Set TPI system control */
+	temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SYS_CTRL_REG, 1, &temp, 1);
+
+	/* Set pixel clock */
+	temp1 = PICOS2KHZ(videomode->pixclock) / 10;
+	temp = (u8)(temp1 & 0xFF);
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_LSB_REG, 1, &temp, 1);
+	temp = (u8)(temp1 >> 8);
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_MSB_REG, 1, &temp, 1);
+
+	/* Set total pixels per line */
+	temp1 = videomode->hsync_len + videomode->left_margin +
+		videomode->xres + videomode->right_margin;
+	temp = (u8)(temp1 & 0xFF);
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_LSB_REG, 1, &temp, 1);
+	temp = (u8)(temp1 >> 8);
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_MSB_REG, 1, &temp, 1);
+
+	/* Set total lines */
+	temp2 = videomode->vsync_len + videomode->upper_margin +
+		videomode->yres + videomode->lower_margin;
+	temp = (u8)(temp2 & 0xFF);
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_LSB_REG, 1, &temp, 1);
+	temp = (u8)(temp2 >> 8);
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_MSB_REG, 1, &temp, 1);
+
+	/* Set vertical frequency in Hz */
+	temp3 = temp1 * temp2;
+	temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3;
+	temp1 = (u16)temp3 * 100;
+	temp = (u8)(temp1 & 0xFF);
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_LSB_REG, 1, &temp, 1);
+	temp = (u8)(temp1 >> 8);
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_MSB_REG, 1, &temp, 1);
+
+	/* Set TPI input bus and pixel repetition data */
+	temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE |
+		TPI_INBUS_RISING_EDGE;
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INBUS_FMT_REG, 1, &temp, 1);
+
+	/* Set TPI AVI Input format data */
+	temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO |
+		TPI_INPUT_CLR_RGB;
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INPUT_FMT_REG, 1, &temp, 1);
+
+	/* Set TPI AVI Output format data */
+	temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO |
+		TPI_OUTPUT_CLR_HDMI_RGB;
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_OUTPUT_FMT_REG, 1, &temp, 1);
+
+	/* Set TPI audio configuration write data */
+	temp = TPI_AUDIO_PASS_BASIC;
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_HANDING_REG, 1, &temp, 1);
+
+	temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL |
+		TPI_AUDIO_TYPE_PCM;
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_INTF_REG, 1, &temp, 1);
+
+	temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
+	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1);
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/common/dcu_sii9022a.h b/roms/u-boot/board/freescale/common/dcu_sii9022a.h
new file mode 100644
index 000000000..785177553
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/dcu_sii9022a.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DCU_HDMI_SII9022A__
+#define __DCU_HDMI_SII9022A__
+
+/* Programming of Silicon SII9022A connector HDMI Transmitter*/
+int dcu_set_dvi_encoder(struct fb_videomode *videomode);
+
+#endif
diff --git a/roms/u-boot/board/freescale/common/diu_ch7301.c b/roms/u-boot/board/freescale/common/diu_ch7301.c
new file mode 100644
index 000000000..05e6a3acf
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/diu_ch7301.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
+ * Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
+ *	    Wang Dongsheng <dongsheng.wang@freescale.com>
+ *
+ * This file is copied and modified from the original t1040qds/diu.c.
+ * Encoder can be used in T104x and LSx Platform.
+ */
+
+#include <common.h>
+#include <stdio_dev.h>
+#include <i2c.h>
+#include <linux/delay.h>
+
+#define I2C_DVI_INPUT_DATA_FORMAT_REG		0x1F
+#define I2C_DVI_PLL_CHARGE_CNTL_REG		0x33
+#define I2C_DVI_PLL_DIVIDER_REG			0x34
+#define I2C_DVI_PLL_SUPPLY_CNTL_REG		0x35
+#define I2C_DVI_PLL_FILTER_REG			0x36
+#define I2C_DVI_TEST_PATTERN_REG		0x48
+#define I2C_DVI_POWER_MGMT_REG			0x49
+#define I2C_DVI_LOCK_STATE_REG			0x4D
+#define I2C_DVI_SYNC_POLARITY_REG		0x56
+
+/*
+ * Set VSYNC/HSYNC to active high. This is polarity of sync signals
+ * from DIU->DVI. The DIU default is active igh, so DVI is set to
+ * active high.
+ */
+#define I2C_DVI_INPUT_DATA_FORMAT_VAL		0x98
+
+#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL	0x06
+#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL	0x26
+#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL	0xA0
+#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL	0x08
+#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL	0x16
+#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL	0x60
+
+/* Clear test pattern */
+#define I2C_DVI_TEST_PATTERN_VAL		0x18
+/* Exit Power-down mode */
+#define I2C_DVI_POWER_MGMT_VAL			0xC0
+
+/* Monitor polarity is handled via DVI Sync Polarity Register */
+#define I2C_DVI_SYNC_POLARITY_VAL		0x00
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock)
+{
+	int ret;
+	u8 temp;
+
+	temp = I2C_DVI_TEST_PATTERN_VAL;
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
+				      CONFIG_SYS_I2C_DVI_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       CONFIG_SYS_I2C_DVI_BUS_NUM);
+		return ret;
+	}
+	ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1);
+	if (ret) {
+		puts("I2C: failed to select proper dvi test pattern\n");
+		return ret;
+	}
+	temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
+	ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi input data format\n");
+		return ret;
+	}
+
+	/* Set Sync polarity register */
+	temp = I2C_DVI_SYNC_POLARITY_VAL;
+	ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi syc polarity\n");
+		return ret;
+	}
+
+	/* Set PLL registers based on pixel clock rate*/
+	if (pixclock > 65000000) {
+		temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
+		ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll charge_cntl\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
+		ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll divider\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
+		ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll filter\n");
+			return ret;
+		}
+	} else {
+		temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
+		ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll charge_cntl\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
+		ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll divider\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
+		ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll filter\n");
+			return ret;
+		}
+	}
+
+	temp = I2C_DVI_POWER_MGMT_VAL;
+	ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi power mgmt\n");
+		return ret;
+	}
+#else
+	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
+			&temp, 1);
+	if (ret) {
+		puts("I2C: failed to select proper dvi test pattern\n");
+		return ret;
+	}
+	temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
+	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
+			1, &temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi input data format\n");
+		return ret;
+	}
+
+	/* Set Sync polarity register */
+	temp = I2C_DVI_SYNC_POLARITY_VAL;
+	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
+			&temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi syc polarity\n");
+		return ret;
+	}
+
+	/* Set PLL registers based on pixel clock rate*/
+	if (pixclock > 65000000) {
+		temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_CHARGE_CNTL_REG, 1,	&temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll charge_cntl\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll divider\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll filter\n");
+			return ret;
+		}
+	} else {
+		temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll charge_cntl\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll divider\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll filter\n");
+			return ret;
+		}
+	}
+
+	temp = I2C_DVI_POWER_MGMT_VAL;
+	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
+			&temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi power mgmt\n");
+		return ret;
+	}
+#endif
+
+	udelay(500);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/common/diu_ch7301.h b/roms/u-boot/board/freescale/common/diu_ch7301.h
new file mode 100644
index 000000000..f35661cdc
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/diu_ch7301.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DIU_HDMI_CH7301__
+#define __DIU_HDMI_CH7301__
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock);
+
+#endif
diff --git a/roms/u-boot/board/freescale/common/eeprom.h b/roms/u-boot/board/freescale/common/eeprom.h
new file mode 100644
index 000000000..328fd3974
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/eeprom.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ */
+
+#ifndef __EEPROM_H_
+#define __EEPROM_H_
+
+
+/*
+ * EEPROM Board System Register interface.
+ */
+
+
+/*
+ * CPU Board Revision
+ */
+#define MPC85XX_CPU_BOARD_REV(maj, min)	((((maj)&0xff) << 8) | ((min) & 0xff))
+#define MPC85XX_CPU_BOARD_MAJOR(rev)	(((rev) >> 8) & 0xff)
+#define MPC85XX_CPU_BOARD_MINOR(rev)	((rev) & 0xff)
+
+#define MPC85XX_CPU_BOARD_REV_UNKNOWN	MPC85XX_CPU_BOARD_REV(0,0)
+#define MPC85XX_CPU_BOARD_REV_1_0	MPC85XX_CPU_BOARD_REV(1,0)
+#define MPC85XX_CPU_BOARD_REV_1_1	MPC85XX_CPU_BOARD_REV(1,1)
+
+/*
+ * Returns CPU board revision register as a 16-bit value with
+ * the Major in the high byte, and Minor in the low byte.
+ */
+extern unsigned int get_cpu_board_revision(void);
+
+
+#endif	/* __CADMUS_H_ */
diff --git a/roms/u-boot/board/freescale/common/emc2305.c b/roms/u-boot/board/freescale/common/emc2305.c
new file mode 100644
index 000000000..9a75c5a09
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/emc2305.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2020 NXP.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+
+#include "emc2305.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void set_fan_speed(u8 data, int chip_addr)
+{
+	u8 index;
+	u8 Fan[NUM_OF_FANS] = {I2C_EMC2305_FAN1,
+			       I2C_EMC2305_FAN2,
+			       I2C_EMC2305_FAN3,
+			       I2C_EMC2305_FAN4,
+			       I2C_EMC2305_FAN5};
+
+	for (index = 0; index < NUM_OF_FANS; index++) {
+#if !CONFIG_IS_ENABLED(DM_I2C)
+		if (i2c_write(chip_addr, Fan[index], 1, &data, 1) != 0) {
+			printf("Error: failed to change fan speed @%x\n",
+			       Fan[index]);
+		}
+#else
+		struct udevice *dev;
+
+		if (i2c_get_chip_for_busnum(0, chip_addr, 1, &dev))
+			continue;
+
+		if (dm_i2c_write(dev, Fan[index], &data, 1) != 0) {
+			printf("Error: failed to change fan speed @%x\n",
+			       Fan[index]);
+		}
+#endif
+	}
+}
+
+void emc2305_init(int chip_addr)
+{
+	u8 data;
+
+	data = I2C_EMC2305_CMD;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	if (i2c_write(chip_addr, I2C_EMC2305_CONF, 1, &data, 1) != 0)
+		printf("Error: failed to configure EMC2305\n");
+#else
+	struct udevice *dev;
+
+	if (!i2c_get_chip_for_busnum(0, chip_addr, 1, &dev))
+		if (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1))
+			printf("Error: failed to configure EMC2305\n");
+#endif
+
+}
diff --git a/roms/u-boot/board/freescale/common/emc2305.h b/roms/u-boot/board/freescale/common/emc2305.h
new file mode 100644
index 000000000..24c5410d1
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/emc2305.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2020 NXP
+ *
+ */
+
+#ifndef __EMC2305_H_
+#define __EMC2305_H_
+
+#define I2C_EMC2305_CONF		0x20
+#define I2C_EMC2305_FAN1		0x30
+#define I2C_EMC2305_FAN2		0x40
+#define I2C_EMC2305_FAN3		0x50
+#define I2C_EMC2305_FAN4		0x60
+#define I2C_EMC2305_FAN5		0x70
+
+#define NUM_OF_FANS			5
+
+void emc2305_init(int chip_addr);
+void set_fan_speed(u8 data, int chip_addr);
+
+#endif  /* __EMC2305_H_ */
diff --git a/roms/u-boot/board/freescale/common/fman.c b/roms/u-boot/board/freescale/common/fman.c
new file mode 100644
index 000000000..358303108
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/fman.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2011-2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <linux/libfdt.h>
+#include <linux/libfdt_env.h>
+#include <fdt_support.h>
+
+#include <fm_eth.h>
+#ifdef CONFIG_FSL_LAYERSCAPE
+#include <asm/arch/fsl_serdes.h>
+#else
+#include <asm/fsl_serdes.h>
+#endif
+
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) The name of an alias that points to the ethernet-phy node (usually inside
+ * a virtual MDIO node)
+ *
+ * ... update that Ethernet node's phy-handle property to point to the
+ * ethernet-phy node.  This is how we link an Ethernet node to its PHY, so each
+ * PHY in a virtual MDIO node must have an alias.
+ *
+ * Returns 0 on success, or a negative FDT error code on error.
+ */
+int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
+			const char *alias)
+{
+	int offset;
+	unsigned int ph;
+	const char *path;
+
+	/* Get a path to the node that 'alias' points to */
+	path = fdt_get_alias(fdt, alias);
+	if (!path)
+		return -FDT_ERR_BADPATH;
+
+	/* Get the offset of that node */
+	offset = fdt_path_offset(fdt, path);
+	if (offset < 0)
+		return offset;
+
+	ph = fdt_create_phandle(fdt, offset);
+	if (!ph)
+		return -FDT_ERR_BADPHANDLE;
+
+	ph = cpu_to_fdt32(ph);
+
+	offset = fdt_node_offset_by_compat_reg(fdt, compat, addr);
+	if (offset < 0)
+		return offset;
+
+	return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph));
+}
+
+/*
+ * Return the SerDes device enum for a given Fman port
+ *
+ * This function just maps the fm_port namespace to the srds_prtcl namespace.
+ */
+enum srds_prtcl serdes_device_from_fm_port(enum fm_port port)
+{
+	static const enum srds_prtcl srds_table[] = {
+		[FM1_DTSEC1] = SGMII_FM1_DTSEC1,
+		[FM1_DTSEC2] = SGMII_FM1_DTSEC2,
+		[FM1_DTSEC3] = SGMII_FM1_DTSEC3,
+		[FM1_DTSEC4] = SGMII_FM1_DTSEC4,
+		[FM1_DTSEC5] = SGMII_FM1_DTSEC5,
+		[FM1_10GEC1] = XAUI_FM1,
+		[FM2_DTSEC1] = SGMII_FM2_DTSEC1,
+		[FM2_DTSEC2] = SGMII_FM2_DTSEC2,
+		[FM2_DTSEC3] = SGMII_FM2_DTSEC3,
+		[FM2_DTSEC4] = SGMII_FM2_DTSEC4,
+		[FM2_DTSEC5] = SGMII_FM2_DTSEC5,
+		[FM2_10GEC1] = XAUI_FM2,
+	};
+
+	if ((port < FM1_DTSEC1) || (port > FM2_10GEC1))
+		return NONE;
+	else
+		return srds_table[port];
+}
diff --git a/roms/u-boot/board/freescale/common/fman.h b/roms/u-boot/board/freescale/common/fman.h
new file mode 100644
index 000000000..16afc34b0
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/fman.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FMAN_BOARD_HELPER__
+#define __FMAN_BOARD_HELPER__
+
+int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
+			const char *alias);
+
+enum srds_prtcl serdes_device_from_fm_port(enum fm_port port);
+
+#endif
diff --git a/roms/u-boot/board/freescale/common/fsl_chain_of_trust.c b/roms/u-boot/board/freescale/common/fsl_chain_of_trust.c
new file mode 100644
index 000000000..cafb24971
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/fsl_chain_of_trust.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <fsl_validate.h>
+#include <fsl_secboot_err.h>
+#include <fsl_sfp.h>
+#include <log.h>
+#include <dm/root.h>
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
+#include <spl.h>
+#endif
+
+#ifdef CONFIG_ADDR_MAP
+#include <asm/mmu.h>
+#endif
+
+#ifdef CONFIG_FSL_CORENET
+#include <asm/fsl_pamu.h>
+#endif
+
+#ifdef CONFIG_ARCH_LS1021A
+#include <asm/arch/immap_ls102xa.h>
+#endif
+
+#if defined(CONFIG_MPC85xx)
+#define CONFIG_DCFG_ADDR	CONFIG_SYS_MPC85xx_GUTS_ADDR
+#else
+#define CONFIG_DCFG_ADDR	CONFIG_SYS_FSL_GUTS_ADDR
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a)       in_le32(a)
+#else
+#define gur_in32(a)       in_be32(a)
+#endif
+
+/* Check the Boot Mode. If Secure, return 1 else return 0 */
+int fsl_check_boot_mode_secure(void)
+{
+	uint32_t val;
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
+
+	val = sfp_in32(&sfp_regs->ospr) & ITS_MASK;
+	if (val == ITS_MASK)
+		return 1;
+
+#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx)
+	/* For PBL based platforms check the SB_EN bit in RCWSR */
+	val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK;
+	if (val == RCW_SB_EN_MASK)
+		return 1;
+#endif
+
+#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET)
+	/* For Non-PBL Platforms, check the Device Status register 2*/
+	val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK;
+	if (val != MPC85xx_PORDEVSR2_SBC_MASK)
+		return 1;
+
+#endif
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+int fsl_setenv_chain_of_trust(void)
+{
+	/* Check Boot Mode
+	 * If Boot Mode is Non-Secure, no changes are required
+	 */
+	if (fsl_check_boot_mode_secure() == 0)
+		return 0;
+
+	/* If Boot mode is Secure, set the environment variables
+	 * bootdelay = 0 (To disable Boot Prompt)
+	 * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
+	 */
+	env_set("bootdelay", "-2");
+
+#ifdef CONFIG_ARM
+	env_set("secureboot", "y");
+#else
+	env_set("bootcmd", CONFIG_CHAIN_BOOT_CMD);
+#endif
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
+{
+	int res;
+
+	/*
+	 * Check Boot Mode
+	 * If Boot Mode is Non-Secure, skip validation
+	 */
+	if (fsl_check_boot_mode_secure() == 0)
+		return;
+
+	printf("SPL: Validating U-Boot image\n");
+
+#ifdef CONFIG_ADDR_MAP
+	init_addr_map();
+#endif
+
+#ifdef CONFIG_FSL_CORENET
+	if (pamu_init() < 0)
+		fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	if (sec_init() < 0)
+		fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT);
+#endif
+
+/*
+ * dm_init_and_scan() is called as part of common SPL framework, so no
+ * need to call it again but in case of powerpc platforms which currently
+ * do not use common SPL framework, so need to call this function here.
+ */
+#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK))
+	dm_init_and_scan(true);
+#endif
+	res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH,
+				   &img_addr);
+
+	if (res == 0)
+		printf("SPL: Validation of U-boot successful\n");
+}
+
+#ifdef CONFIG_SPL_FRAMEWORK
+/* Override weak funtion defined in SPL framework to enable validation
+ * of main u-boot image before jumping to u-boot image.
+ */
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	typedef void __noreturn (*image_entry_noargs_t)(void);
+	uint32_t hdr_addr;
+
+	image_entry_noargs_t image_entry =
+		(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
+
+	hdr_addr = (spl_image->entry_point + spl_image->size -
+			CONFIG_U_BOOT_HDR_SIZE);
+	spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point);
+	/*
+	 * In case of failure in validation, spl_validate_uboot would
+	 * not return back in case of Production environment with ITS=1.
+	 * Thus U-Boot will not start.
+	 * In Development environment (ITS=0 and SB_EN=1), the function
+	 * may return back in case of non-fatal failures.
+	 */
+
+	debug("image entry point: 0x%lX\n", spl_image->entry_point);
+	image_entry();
+}
+#endif /* ifdef CONFIG_SPL_FRAMEWORK */
+#endif /* ifdef CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/freescale/common/fsl_validate.c b/roms/u-boot/board/freescale/common/fsl_validate.c
new file mode 100644
index 000000000..564a8b3b5
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/fsl_validate.c
@@ -0,0 +1,964 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <flash.h>
+#include <fsl_validate.h>
+#include <fsl_secboot_err.h>
+#include <fsl_sfp.h>
+#include <fsl_sec.h>
+#include <command.h>
+#include <log.h>
+#include <malloc.h>
+#include <u-boot/rsa-mod-exp.h>
+#include <hash.h>
+#include <fsl_secboot_err.h>
+#ifdef CONFIG_ARCH_LS1021A
+#include <asm/arch/immap_ls102xa.h>
+#endif
+
+#define SHA256_BITS	256
+#define SHA256_BYTES	(256/8)
+#define SHA256_NIBBLES	(256/4)
+#define NUM_HEX_CHARS	(sizeof(ulong) * 2)
+
+#define CHECK_KEY_LEN(key_len)	(((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
+				 ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
+				 ((key_len) == 2 * KEY_SIZE_BYTES))
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+/* Global data structure */
+static struct fsl_secboot_glb glb;
+#endif
+
+/* This array contains DER value for SHA-256 */
+static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
+		0x86, 0x48, 0x01, 0x65,	0x03, 0x04, 0x02, 0x01, 0x05, 0x00,
+		0x04, 0x20
+		};
+
+static u8 hash_val[SHA256_BYTES];
+
+#ifdef CONFIG_ESBC_HDR_LS
+/* New Barker Code for LS ESBC Header */
+static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 };
+#else
+static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
+#endif
+
+void branch_to_self(void) __attribute__ ((noreturn));
+
+/*
+ * This function will put core in infinite loop.
+ * This will be called when the ESBC can not proceed further due
+ * to some unknown errors.
+ */
+void branch_to_self(void)
+{
+	printf("Core is in infinite loop due to errors.\n");
+self:
+	goto self;
+}
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+static u32 check_ie(struct fsl_secboot_img_priv *img)
+{
+	if (img->hdr.ie_flag & IE_FLAG_MASK)
+		return 1;
+
+	return 0;
+}
+
+/* This function returns the CSF Header Address of uboot
+ * For MPC85xx based platforms, the LAW mapping for NOR
+ * flash changes in uboot code. Hence the offset needs
+ * to be calculated and added to the new NOR flash base
+ * address
+ */
+#if defined(CONFIG_MPC85xx)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
+	u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
+	u32 flash_addr, addr;
+	int found = 0;
+	int i = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		flash_addr = flash_info[i].start[0];
+		addr = flash_info[i].start[0] + csf_flash_offset;
+		if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) {
+			debug("Barker found on addr %x\n", addr);
+			found = 1;
+			break;
+		}
+	}
+
+	if (!found)
+		return -1;
+
+	*csf_addr = addr;
+	*flash_base_addr = flash_addr;
+
+	return 0;
+}
+#else
+/* For platforms like LS1020, correct flash address is present in
+ * the header. So the function reqturns flash base address as 0
+ */
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
+
+	if (memcmp((u8 *)(uintptr_t)csf_hdr_addr,
+		   barker_code, ESBC_BARKER_LEN))
+		return -1;
+
+	*csf_addr = csf_hdr_addr;
+	*flash_base_addr = 0;
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_ESBC_HDR_LS)
+static int get_ie_info_addr(uintptr_t *ie_addr)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	/* For LS-CH3, the address of IE Table is
+	 * stated in Scratch13 and scratch14 of DCFG.
+	 * Bootrom validates this table while validating uboot.
+	 * DCFG is LE*/
+	*ie_addr = in_le32(&gur->scratchrw[SCRATCH_IE_HIGH_ADR - 1]);
+	*ie_addr = *ie_addr << 32;
+	*ie_addr |= in_le32(&gur->scratchrw[SCRATCH_IE_LOW_ADR - 1]);
+	return 0;
+}
+#else /* CONFIG_ESBC_HDR_LS */
+static int get_ie_info_addr(uintptr_t *ie_addr)
+{
+	struct fsl_secboot_img_hdr *hdr;
+	struct fsl_secboot_sg_table *sg_tbl;
+	u32 flash_base_addr, csf_addr;
+
+	if (get_csf_base_addr(&csf_addr, &flash_base_addr))
+		return -1;
+
+	hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr;
+
+	/* For SoC's with Trust Architecture v1 with corenet bus
+	 * the sg table field in CSF header has absolute address
+	 * for sg table in memory. In other Trust Architecture,
+	 * this field specifies the offset of sg table from the
+	 * base address of CSF Header
+	 */
+#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
+	sg_tbl = (struct fsl_secboot_sg_table *)
+		 (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+		  flash_base_addr);
+#else
+	sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr +
+						 (u32)hdr->psgtable);
+#endif
+
+	/* IE Key Table is the first entry in the SG Table */
+#if defined(CONFIG_MPC85xx)
+	*ie_addr = (uintptr_t)((sg_tbl->src_addr &
+			~(CONFIG_SYS_PBI_FLASH_BASE)) +
+			flash_base_addr);
+#else
+	*ie_addr = (uintptr_t)sg_tbl->src_addr;
+#endif
+
+	debug("IE Table address is %lx\n", *ie_addr);
+	return 0;
+}
+#endif /* CONFIG_ESBC_HDR_LS */
+#endif
+
+#ifdef CONFIG_KEY_REVOCATION
+/* This function checks srk_table_flag in header and set/reset srk_flag.*/
+static u32 check_srk(struct fsl_secboot_img_priv *img)
+{
+#ifdef CONFIG_ESBC_HDR_LS
+	/* In LS, No SRK Flag as SRK is always present if IE not present*/
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+	return !check_ie(img);
+#endif
+	return 1;
+#else
+	if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
+		return 1;
+
+	return 0;
+#endif
+}
+
+/* This function returns ospr's key_revoc values.*/
+static u32 get_key_revoc(void)
+{
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >>
+		OSPR_KEY_REVOC_SHIFT;
+}
+
+/* This function checks if selected key is revoked or not.*/
+static u32 is_key_revoked(u32 keynum, u32 rev_flag)
+{
+	if (keynum == UNREVOCABLE_KEY)
+		return 0;
+
+	if ((u32)(1 << (ALIGN_REVOC_KEY - keynum)) & rev_flag)
+		return 1;
+
+	return 0;
+}
+
+/* It read validates srk_table key lengths.*/
+static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img)
+{
+	int i = 0;
+	u32 ret, key_num, key_revoc_flag, size;
+	struct fsl_secboot_img_hdr *hdr = &img->hdr;
+	void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
+
+	if ((hdr->len_kr.num_srk == 0) ||
+	    (hdr->len_kr.num_srk > MAX_KEY_ENTRIES))
+		return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY;
+
+	key_num = hdr->len_kr.srk_sel;
+	if (key_num == 0 || key_num > hdr->len_kr.num_srk)
+		return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM;
+
+	/* Get revoc key from sfp */
+	key_revoc_flag = get_key_revoc();
+	ret = is_key_revoked(key_num, key_revoc_flag);
+	if (ret)
+		return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED;
+
+	size = hdr->len_kr.num_srk * sizeof(struct srk_table);
+
+	memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size);
+
+	for (i = 0; i < hdr->len_kr.num_srk; i++) {
+		if (!CHECK_KEY_LEN(img->srk_tbl[i].key_len))
+			return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN;
+	}
+
+	img->key_len = img->srk_tbl[key_num - 1].key_len;
+
+	memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey),
+	       img->key_len);
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_ESBC_HDR_LS
+static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
+{
+	struct fsl_secboot_img_hdr *hdr = &img->hdr;
+	void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
+
+	/* check key length */
+	if (!CHECK_KEY_LEN(hdr->key_len))
+		return ERROR_ESBC_CLIENT_HEADER_KEY_LEN;
+
+	memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len);
+
+	img->key_len = hdr->key_len;
+
+	return 0;
+}
+#endif /* CONFIG_ESBC_HDR_LS */
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+
+static void install_ie_tbl(uintptr_t ie_tbl_addr,
+		struct fsl_secboot_img_priv *img)
+{
+	/* Copy IE tbl to Global Data */
+	memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info));
+	img->ie_addr = (uintptr_t)&glb.ie_tbl;
+	glb.ie_addr = img->ie_addr;
+}
+
+static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
+{
+	struct fsl_secboot_img_hdr *hdr = &img->hdr;
+	u32 ie_key_len, ie_revoc_flag, ie_num;
+	struct ie_key_info *ie_info;
+
+	if (!img->ie_addr) {
+		if (get_ie_info_addr(&img->ie_addr))
+			return ERROR_IE_TABLE_NOT_FOUND;
+		else
+			install_ie_tbl(img->ie_addr, img);
+		}
+
+	ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr;
+	if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
+		return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;
+
+	ie_num = hdr->ie_key_sel;
+	if (ie_num == 0 || ie_num > ie_info->num_keys)
+		return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM;
+
+	ie_revoc_flag = ie_info->key_revok;
+	if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag)
+		return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED;
+
+	ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len;
+
+	if (!CHECK_KEY_LEN(ie_key_len))
+		return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN;
+
+	memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey),
+	       ie_key_len);
+
+	img->key_len = ie_key_len;
+	return 0;
+}
+#endif
+
+
+/* This function return length of public key.*/
+static inline u32 get_key_len(struct fsl_secboot_img_priv *img)
+{
+	return img->key_len;
+}
+
+/*
+ * Handles the ESBC uboot client header verification failure.
+ * This  function  handles all the errors which might occur in the
+ * parsing and checking of ESBC uboot client header. It will also
+ * set the error bits in the SEC_MON.
+ */
+static void fsl_secboot_header_verification_failure(void)
+{
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+
+	/* 29th bit of OSPR is ITS */
+	u32 its = sfp_in32(&sfp_regs->ospr) >> 2;
+
+	if (its == 1)
+		set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
+	else
+		set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
+
+	printf("Generating reset request\n");
+	do_reset(NULL, 0, 0, NULL);
+	/* If reset doesn't coocur, halt execution */
+	do_esbc_halt(NULL, 0, 0, NULL);
+}
+
+/*
+ * Handles the ESBC uboot client image verification failure.
+ * This  function  handles all the errors which might occur in the
+ * public key hash comparison and signature verification of
+ * ESBC uboot client image. It will also
+ * set the error bits in the SEC_MON.
+ */
+static void fsl_secboot_image_verification_failure(void)
+{
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+
+	u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT;
+
+	if (its == 1) {
+		set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
+
+		printf("Generating reset request\n");
+		do_reset(NULL, 0, 0, NULL);
+		/* If reset doesn't coocur, halt execution */
+		do_esbc_halt(NULL, 0, 0, NULL);
+
+	} else {
+		set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
+	}
+}
+
+static void fsl_secboot_bootscript_parse_failure(void)
+{
+	fsl_secboot_header_verification_failure();
+}
+
+/*
+ * Handles the errors in esbc boot.
+ * This  function  handles all the errors which might occur in the
+ * esbc boot phase. It will call the appropriate api to log the
+ * errors and set the error bits in the SEC_MON.
+ */
+void fsl_secboot_handle_error(int error)
+{
+#ifndef CONFIG_SPL_BUILD
+	const struct fsl_secboot_errcode *e;
+
+	for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX;
+		e++) {
+		if (e->errcode == error)
+			printf("ERROR :: %x :: %s\n", error, e->name);
+	}
+#else
+	printf("ERROR :: %x\n", error);
+#endif
+
+	/* If Boot Mode is secure, transition the SNVS state and issue
+	 * reset based on type of failure and ITS setting.
+	 * If Boot mode is non-secure, return from this function.
+	 */
+	if (fsl_check_boot_mode_secure() == 0)
+		return;
+
+	switch (error) {
+	case ERROR_ESBC_CLIENT_HEADER_BARKER:
+	case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE:
+	case ERROR_ESBC_CLIENT_HEADER_KEY_LEN:
+	case ERROR_ESBC_CLIENT_HEADER_SIG_LEN:
+	case ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN:
+	case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1:
+	case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2:
+	case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD:
+	case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP:
+	case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD:
+	case ERROR_KEY_TABLE_NOT_FOUND:
+#ifdef CONFIG_KEY_REVOCATION
+	case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED:
+	case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY:
+	case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM:
+	case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN:
+#endif
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+	/*@fallthrough@*/
+	case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED:
+	case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY:
+	case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM:
+	case ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN:
+	case ERROR_IE_TABLE_NOT_FOUND:
+#endif
+		fsl_secboot_header_verification_failure();
+		break;
+	case ERROR_ESBC_SEC_RESET:
+	case ERROR_ESBC_SEC_DEQ:
+	case ERROR_ESBC_SEC_ENQ:
+	case ERROR_ESBC_SEC_DEQ_TO:
+	case ERROR_ESBC_SEC_JOBQ_STATUS:
+	case ERROR_ESBC_CLIENT_HASH_COMPARE_KEY:
+	case ERROR_ESBC_CLIENT_HASH_COMPARE_EM:
+		fsl_secboot_image_verification_failure();
+		break;
+	case ERROR_ESBC_MISSING_BOOTM:
+		fsl_secboot_bootscript_parse_failure();
+		break;
+	case ERROR_ESBC_WRONG_CMD:
+	default:
+		branch_to_self();
+		break;
+	}
+}
+
+static void fsl_secblk_handle_error(int error)
+{
+	switch (error) {
+	case ERROR_ESBC_SEC_ENQ:
+		fsl_secboot_handle_error(ERROR_ESBC_SEC_ENQ);
+		break;
+	case ERROR_ESBC_SEC_DEQ:
+		fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ);
+		break;
+	case ERROR_ESBC_SEC_DEQ_TO:
+		fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ_TO);
+		break;
+	default:
+		printf("Job Queue Output status %x\n", error);
+		fsl_secboot_handle_error(ERROR_ESBC_SEC_JOBQ_STATUS);
+		break;
+	}
+}
+
+/*
+ * Calculate hash of key obtained via offset present in ESBC uboot
+ * client hdr. This function calculates the hash of key which is obtained
+ * through offset present in ESBC uboot client header.
+ */
+static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
+{
+	struct hash_algo *algo;
+	void *ctx;
+	int i, srk = 0;
+	int ret = 0;
+	const char *algo_name = "sha256";
+
+	/* Calculate hash of the esbc key */
+	ret = hash_progressive_lookup_algo(algo_name, &algo);
+	if (ret)
+		return ret;
+
+	ret = algo->hash_init(algo, &ctx);
+	if (ret)
+		return ret;
+
+	/* Update hash for ESBC key */
+#ifdef CONFIG_KEY_REVOCATION
+	if (check_srk(img)) {
+		ret = algo->hash_update(algo, ctx,
+		      (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
+		      img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
+		srk = 1;
+	}
+#endif
+	if (!srk)
+		ret = algo->hash_update(algo, ctx,
+			img->img_key, img->key_len, 1);
+	if (ret)
+		return ret;
+
+	/* Copy hash at destination buffer */
+	ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < SHA256_BYTES; i++)
+		img->img_key_hash[i] = hash_val[i];
+
+	return 0;
+}
+
+/*
+ * Calculate hash of ESBC hdr and ESBC. This function calculates the
+ * single hash of ESBC header and ESBC image. If SG flag is on, all
+ * SG entries are also hashed alongwith the complete SG table.
+ */
+static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
+{
+	struct hash_algo *algo;
+	void *ctx;
+	int ret = 0;
+	int key_hash = 0;
+	const char *algo_name = "sha256";
+
+	/* Calculate the hash of the ESBC */
+	ret = hash_progressive_lookup_algo(algo_name, &algo);
+	if (ret)
+		return ret;
+
+	ret = algo->hash_init(algo, &ctx);
+	/* Copy hash at destination buffer */
+	if (ret)
+		return ret;
+
+	/* Update hash for CSF Header */
+	ret = algo->hash_update(algo, ctx,
+		(u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0);
+	if (ret)
+		return ret;
+
+	/* Update the hash with that of srk table if srk flag is 1
+	 * If IE Table is selected, key is not added in the hash
+	 * If neither srk table nor IE key table available, add key
+	 * from header in the hash calculation
+	 */
+#ifdef CONFIG_KEY_REVOCATION
+	if (check_srk(img)) {
+		ret = algo->hash_update(algo, ctx,
+		      (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
+		      img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0);
+		key_hash = 1;
+	}
+#endif
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+	if (!key_hash && check_ie(img))
+		key_hash = 1;
+#endif
+#ifndef CONFIG_ESBC_HDR_LS
+/* No single key support in LS ESBC header */
+	if (!key_hash) {
+		ret = algo->hash_update(algo, ctx,
+			img->img_key, img->hdr.key_len, 0);
+		key_hash = 1;
+	}
+#endif
+	if (ret)
+		return ret;
+	if (!key_hash)
+		return ERROR_KEY_TABLE_NOT_FOUND;
+
+	/* Update hash for actual Image */
+	ret = algo->hash_update(algo, ctx,
+		(u8 *)(*(img->img_addr_ptr)), img->img_size, 1);
+	if (ret)
+		return ret;
+
+	/* Copy hash at destination buffer */
+	ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/*
+ * Construct encoded hash EM' wrt PKCSv1.5. This function calculates the
+ * pointers for padding, DER value and hash. And finally, constructs EM'
+ * which includes hash of complete CSF header and ESBC image. If SG flag
+ * is on, hash of SG table and entries is also included.
+ */
+static void construct_img_encoded_hash_second(struct fsl_secboot_img_priv *img)
+{
+	/*
+	 * RSA PKCSv1.5 encoding format for encoded message is below
+	 * EM = 0x0 || 0x1 || PS || 0x0 || DER || Hash
+	 * PS is Padding String
+	 * DER is DER value for SHA-256
+	 * Hash is SHA-256 hash
+	 * *********************************************************
+	 * representative points to first byte of EM initially and is
+	 * filled with 0x0
+	 * representative is incremented by 1 and second byte is filled
+	 * with 0x1
+	 * padding points to third byte of EM
+	 * digest points to full length of EM - 32 bytes
+	 * hash_id (DER value) points to 19 bytes before pDigest
+	 * separator is one byte which separates padding and DER
+	 */
+
+	size_t len;
+	u8 *representative;
+	u8 *padding, *digest;
+	u8 *hash_id, *separator;
+	int i;
+
+	len = (get_key_len(img) / 2) - 1;
+	representative = img->img_encoded_hash_second;
+	representative[0] = 0;
+	representative[1] = 1;  /* block type 1 */
+
+	padding = &representative[2];
+	digest = &representative[1] + len - 32;
+	hash_id = digest - sizeof(hash_identifier);
+	separator = hash_id - 1;
+
+	/* fill padding area pointed by padding with 0xff */
+	memset(padding, 0xff, separator - padding);
+
+	/* fill byte pointed by separator */
+	*separator = 0;
+
+	/* fill SHA-256 DER value  pointed by HashId */
+	memcpy(hash_id, hash_identifier, sizeof(hash_identifier));
+
+	/* fill hash pointed by Digest */
+	for (i = 0; i < SHA256_BYTES; i++)
+		digest[i] = hash_val[i];
+}
+
+/*
+ * Reads and validates the ESBC client header.
+ * This function reads key and signature from the ESBC client header.
+ * If Scatter/Gather flag is on, lengths and offsets of images
+ * present as SG entries are also read. This function also checks
+ * whether the header is valid or not.
+ */
+static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
+{
+	struct fsl_secboot_img_hdr *hdr = &img->hdr;
+	void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
+	u8 *k, *s;
+	u32 ret = 0;
+
+	int  key_found = 0;
+
+	/* check barker code */
+	if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN))
+		return ERROR_ESBC_CLIENT_HEADER_BARKER;
+
+	/* If Image Address is not passed as argument to function,
+	 * then Address and Size must be read from the Header.
+	 */
+	if (*(img->img_addr_ptr) == 0) {
+	#ifdef CONFIG_ESBC_ADDR_64BIT
+		*(img->img_addr_ptr) = hdr->pimg64;
+	#else
+		*(img->img_addr_ptr) = hdr->pimg;
+	#endif
+	}
+
+	if (!hdr->img_size)
+		return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;
+
+	img->img_size = hdr->img_size;
+
+	/* Key checking*/
+#ifdef CONFIG_KEY_REVOCATION
+	if (check_srk(img)) {
+		ret = read_validate_srk_tbl(img);
+		if (ret != 0)
+			return ret;
+		key_found = 1;
+	}
+#endif
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+	if (!key_found && check_ie(img)) {
+		ret = read_validate_ie_tbl(img);
+		if (ret != 0)
+			return ret;
+		key_found = 1;
+	}
+#endif
+#ifndef CONFIG_ESBC_HDR_LS
+/* Single Key Feature not available in LS ESBC Header */
+	if (key_found == 0) {
+		ret = read_validate_single_key(img);
+		if (ret != 0)
+			return ret;
+		key_found = 1;
+	}
+#endif
+	if (!key_found)
+		return ERROR_KEY_TABLE_NOT_FOUND;
+
+	/* check signaure */
+	if (get_key_len(img) == 2 * hdr->sign_len) {
+		/* check signature length */
+		if (!((hdr->sign_len == KEY_SIZE_BYTES / 4) ||
+		      (hdr->sign_len == KEY_SIZE_BYTES / 2) ||
+		      (hdr->sign_len == KEY_SIZE_BYTES)))
+			return ERROR_ESBC_CLIENT_HEADER_SIG_LEN;
+	} else {
+		return ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN;
+	}
+
+	memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len);
+/* No SG support in LS-CH3 */
+#ifndef CONFIG_ESBC_HDR_LS
+	/* No SG support */
+	if (hdr->sg_flag)
+		return ERROR_ESBC_CLIENT_HEADER_SG;
+#endif
+
+	/* modulus most significant bit should be set */
+	k = (u8 *)&img->img_key;
+
+	if ((k[0] & 0x80) == 0)
+		return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1;
+
+	/* modulus value should be odd */
+	if ((k[get_key_len(img) / 2 - 1] & 0x1) == 0)
+		return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2;
+
+	/* Check signature value < modulus value */
+	s = (u8 *)&img->img_sign;
+
+	if (!(memcmp(s, k, hdr->sign_len) < 0))
+		return ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD;
+
+	return ESBC_VALID_HDR;
+}
+
+static inline int str2longbe(const char *p, ulong *num)
+{
+	char *endptr;
+	ulong tmp;
+
+	if (!p) {
+		return 0;
+	} else {
+		tmp = simple_strtoul(p, &endptr, 16);
+		if (sizeof(ulong) == 4)
+			*num = cpu_to_be32(tmp);
+		else
+			*num = cpu_to_be64(tmp);
+	}
+
+	return *p != '\0' && *endptr == '\0';
+}
+/* Function to calculate the ESBC Image Hash
+ * and hash from Digital signature.
+ * The Two hash's are compared to yield the
+ * result of signature validation.
+ */
+static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
+{
+	int ret;
+	uint32_t key_len;
+	struct key_prop prop;
+#if !defined(USE_HOSTCC)
+	struct udevice *mod_exp_dev;
+#endif
+	ret = calc_esbchdr_esbc_hash(img);
+	if (ret)
+		return ret;
+
+	/* Construct encoded hash EM' wrt PKCSv1.5 */
+	construct_img_encoded_hash_second(img);
+
+	/* Fill prop structure for public key */
+	memset(&prop, 0, sizeof(struct key_prop));
+	key_len = get_key_len(img) / 2;
+	prop.modulus = img->img_key;
+	prop.public_exponent = img->img_key + key_len;
+	prop.num_bits = key_len * 8;
+	prop.exp_len = key_len;
+
+	ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev);
+	if (ret) {
+		printf("RSA: Can't find Modular Exp implementation\n");
+		return -EINVAL;
+	}
+
+	ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len,
+			  &prop, img->img_encoded_hash);
+	if (ret)
+		return ret;
+
+	/*
+	 * compare the encoded messages EM' and EM wrt RSA PKCSv1.5
+	 * memcmp returns zero on success
+	 * memcmp returns non-zero on failure
+	 */
+	ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash,
+		img->hdr.sign_len);
+
+	if (ret)
+		return ERROR_ESBC_CLIENT_HASH_COMPARE_EM;
+
+	return 0;
+}
+/* Function to initialize img priv and global data structure
+ */
+static int secboot_init(struct fsl_secboot_img_priv **img_ptr)
+{
+	*img_ptr = malloc(sizeof(struct fsl_secboot_img_priv));
+
+	struct fsl_secboot_img_priv *img = *img_ptr;
+
+	if (!img)
+		return -ENOMEM;
+	memset(img, 0, sizeof(struct fsl_secboot_img_priv));
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+	if (glb.ie_addr)
+		img->ie_addr = glb.ie_addr;
+#endif
+	return 0;
+}
+
+
+/* haddr - Address of the header of image to be validated.
+ * arg_hash_str - Option hash string. If provided, this
+ * overrides the key hash in the SFP fuses.
+ * img_addr_ptr - Optional pointer to address of image to be validated.
+ * If non zero addr, this overrides the addr of image in header,
+ * otherwise updated to image addr in header.
+ * Acts as both input and output of function.
+ * This pointer shouldn't be NULL.
+ */
+int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
+			uintptr_t *img_addr_ptr)
+{
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	ulong hash[SHA256_BYTES/sizeof(ulong)];
+	char hash_str[NUM_HEX_CHARS + 1];
+	struct fsl_secboot_img_priv *img;
+	struct fsl_secboot_img_hdr *hdr;
+	void *esbc;
+	int ret, i, hash_cmd = 0;
+	u32 srk_hash[8];
+
+	if (arg_hash_str != NULL) {
+		const char *cp = arg_hash_str;
+		int i = 0;
+
+		if (*cp == '0' && *(cp + 1) == 'x')
+			cp += 2;
+
+		/* The input string expected is in hex, where
+		 * each 4 bits would be represented by a hex
+		 * sha256 hash is 256 bits long, which would mean
+		 * num of characters = 256 / 4
+		 */
+		if (strlen(cp) != SHA256_NIBBLES) {
+			printf("%s is not a 256 bits hex string as expected\n",
+			       arg_hash_str);
+			return -1;
+		}
+
+		for (i = 0; i < sizeof(hash)/sizeof(ulong); i++) {
+			strncpy(hash_str, cp + (i * NUM_HEX_CHARS),
+				NUM_HEX_CHARS);
+			hash_str[NUM_HEX_CHARS] = '\0';
+			if (!str2longbe(hash_str, &hash[i])) {
+				printf("%s is not a 256 bits hex string ",
+				       arg_hash_str);
+				return -1;
+			}
+		}
+
+		hash_cmd = 1;
+	}
+
+	ret = secboot_init(&img);
+	if (ret)
+		goto exit;
+
+	/* Update the information in Private Struct */
+	hdr = &img->hdr;
+	img->ehdrloc = haddr;
+	img->img_addr_ptr = img_addr_ptr;
+	esbc = (u8 *)img->ehdrloc;
+
+	memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr));
+
+	/* read and validate esbc header */
+	ret = read_validate_esbc_client_header(img);
+
+	if (ret != ESBC_VALID_HDR) {
+		fsl_secboot_handle_error(ret);
+		goto exit;
+	}
+
+	/* SRKH present in SFP */
+	for (i = 0; i < NUM_SRKH_REGS; i++)
+		srk_hash[i] = srk_in32(&sfp_regs->srk_hash[i]);
+
+	/*
+	 * Calculate hash of key obtained via offset present in
+	 * ESBC uboot client hdr
+	 */
+	ret = calc_img_key_hash(img);
+	if (ret) {
+		fsl_secblk_handle_error(ret);
+		goto exit;
+	}
+
+	/* Compare hash obtained above with SRK hash present in SFP */
+	if (hash_cmd)
+		ret = memcmp(&hash, &img->img_key_hash, SHA256_BYTES);
+	else
+		ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES);
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+	if (!hash_cmd && check_ie(img))
+		ret = 0;
+#endif
+
+	if (ret != 0) {
+		fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_KEY);
+		goto exit;
+	}
+
+	ret = calculate_cmp_img_sig(img);
+	if (ret) {
+		fsl_secboot_handle_error(ret);
+		goto exit;
+	}
+
+exit:
+	/* Free Img as it was malloc'ed*/
+	free(img);
+	return ret;
+}
diff --git a/roms/u-boot/board/freescale/common/ics307_clk.c b/roms/u-boot/board/freescale/common/ics307_clk.c
new file mode 100644
index 000000000..214339578
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/ics307_clk.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+
+#include "ics307_clk.h"
+
+#if defined(CONFIG_FSL_NGPIXIS)
+#include "ngpixis.h"
+#define fpga_reg pixis
+#elif defined(CONFIG_FSL_QIXIS)
+#include "qixis.h"
+#define fpga_reg ((struct qixis *)QIXIS_BASE)
+#else
+#include "pixis.h"
+#define fpga_reg pixis
+#endif
+
+/* define for SYS CLK or CLK1Frequency */
+#define TTL		1
+#define CLK2		0
+#define CRYSTAL		0
+#define MAX_VDW		(511 + 8)
+#define MAX_RDW		(127 + 2)
+#define MIN_VDW		(4 + 8)
+#define MIN_RDW		(1 + 2)
+#define NUM_OD_SETTING	8
+/*
+ * These defines cover the industrial temperature range part,
+ * for commercial, change below to 400000 and 55000, respectively
+ */
+#define MAX_VCO		360000
+#define MIN_VCO		60000
+
+/* decode S[0-2] to Output Divider (OD) */
+static u8 ics307_s_to_od[] = {
+	10, 2, 8, 4, 5, 7, 3, 6
+};
+
+/*
+ * Find one solution to generate required frequency for SYSCLK
+ * out_freq: KHz, required frequency to the SYSCLK
+ * the result will be retuned with component RDW, VDW, OD, TTL,
+ * CLK2 and crystal
+ */
+unsigned long ics307_sysclk_calculator(unsigned long out_freq)
+{
+	const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
+	unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
+	unsigned long tmp_out, diff, result = 0;
+	int found = 0;
+
+	for (odp = 0; odp < NUM_OD_SETTING; odp++) {
+		od = ics307_s_to_od[odp];
+		if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
+			continue;
+		for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
+			/* Calculate the VDW */
+			vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
+			if (vdw > MAX_VDW)
+				vdw = MAX_VDW;
+			if (vdw < MIN_VDW)
+				continue;
+			/* Calculate the temp out frequency */
+			tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
+			diff = max(out_freq, tmp_out) - min(out_freq, tmp_out);
+			/*
+			 * calculate the percent, the precision is 1/1000
+			 * If greater than 1/1000, continue
+			 * otherwise, we think the solution is we required
+			 */
+			if (diff * 1000 / out_freq > 1)
+				continue;
+			else {
+				s_vdw = vdw;
+				s_rdw = rdw;
+				s_odp = odp;
+				found = 1;
+				break;
+			}
+		}
+	}
+
+	if (found)
+		result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
+			CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
+
+	debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
+			ics307_s_to_od[s_odp]);
+	return result;
+}
+
+/*
+ * Calculate frequency being generated by ICS307-02 clock chip based upon
+ * the control bytes being programmed into it.
+ */
+static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
+{
+	const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
+	unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
+	unsigned long rdw = cw2 & 0x7F;
+	unsigned long od = ics307_s_to_od[cw0 & 0x7];
+	unsigned long freq;
+
+	/*
+	 * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
+	 *
+	 * cw0:  C1 C0 TTL F1 F0 S2 S1 S0
+	 * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
+	 * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
+	 *
+	 * R6:R0 = Reference Divider Word (RDW)
+	 * V8:V0 = VCO Divider Word (VDW)
+	 * S2:S0 = Output Divider Select (OD)
+	 * F1:F0 = Function of CLK2 Output
+	 * TTL = duty cycle
+	 * C1:C0 = internal load capacitance for cyrstal
+	 *
+	 */
+
+	freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
+
+	debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
+			freq);
+	return freq;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return ics307_clk_freq(
+			in_8(&fpga_reg->sclk[0]),
+			in_8(&fpga_reg->sclk[1]),
+			in_8(&fpga_reg->sclk[2]));
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return ics307_clk_freq(
+			in_8(&fpga_reg->dclk[0]),
+			in_8(&fpga_reg->dclk[1]),
+			in_8(&fpga_reg->dclk[2]));
+}
diff --git a/roms/u-boot/board/freescale/common/ics307_clk.h b/roms/u-boot/board/freescale/common/ics307_clk.h
new file mode 100644
index 000000000..81d1aa715
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/ics307_clk.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+#ifndef __ICS_CLK_H_
+#define __ICS_CLK_H_	1
+
+#ifndef __ASSEMBLY__
+
+extern unsigned long get_board_sys_clk(void);
+extern unsigned long get_board_ddr_clk(void);
+extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);
+#endif
+
+#endif	/* __ICS_CLK_H_ */
diff --git a/roms/u-boot/board/freescale/common/idt8t49n222a_serdes_clk.c b/roms/u-boot/board/freescale/common/idt8t49n222a_serdes_clk.c
new file mode 100644
index 000000000..bb3cdac84
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/idt8t49n222a_serdes_clk.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Shaveta Leekha <shaveta@freescale.com>
+ */
+
+#include "idt8t49n222a_serdes_clk.h"
+#include <log.h>
+#include <linux/delay.h>
+
+#define DEVICE_ID_REG		0x00
+
+static int check_pll_status(u8 idt_addr)
+{
+	u8 val = 0;
+	int ret;
+
+	ret = i2c_read(idt_addr, 0x17, 1, &val, 1);
+	if (ret < 0) {
+		printf("IDT:0x%x could not read status register from device.\n",
+			idt_addr);
+		return ret;
+	}
+
+	if (val & 0x04) {
+		debug("idt8t49n222a PLL is LOCKED: %x\n", val);
+	} else {
+		printf("idt8t49n222a PLL is not LOCKED: %x\n", val);
+		return -1;
+	}
+
+	return 0;
+}
+
+int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
+			enum serdes_refclk refclk1,
+			enum serdes_refclk refclk2, u8 feedback)
+{
+	u8 dev_id = 0;
+	int i, ret;
+
+	debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n",
+		idt_addr);
+
+	ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1);
+	if (ret < 0) {
+		debug("IDT:0x%x could not read DEV_ID from device.\n",
+			idt_addr);
+		return ret;
+	}
+
+	if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) {
+		debug("IDT: device at address 0x%x is not idt8t49n222a.\n",
+			idt_addr);
+	}
+
+	if (serdes_num != 1 && serdes_num != 2) {
+		debug("serdes_num should be 1 for SerDes1 and"
+			" 2 for SerDes2.\n");
+		return -1;
+	}
+
+	if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88)
+		|| (refclk1 != SERDES_REFCLK_122_88
+			&& refclk2 == SERDES_REFCLK_122_88)) {
+		debug("Only one refclk at 122.88MHz is not supported."
+			" Please set both refclk1 & refclk2 to 122.88MHz"
+			" or both not to 122.88MHz.\n");
+		return -1;
+	}
+
+	if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88
+					&& refclk1 != SERDES_REFCLK_125
+					&& refclk1 != SERDES_REFCLK_156_25) {
+		debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz"
+			" or 156.25MHz.\n");
+		return -1;
+	}
+
+	if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88
+					&& refclk2 != SERDES_REFCLK_125
+					&& refclk2 != SERDES_REFCLK_156_25) {
+		debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz"
+			" or 156.25MHz.\n");
+		return -1;
+	}
+
+	if (feedback != 0 && feedback != 1) {
+		debug("valid values for feedback are 0(default) or 1.\n");
+		return -1;
+	}
+
+	/* Configuring IDT for output refclks as
+	 * Refclk1 = 122.88MHz  Refclk2 = 122.88MHz
+	 */
+	if (refclk1 == SERDES_REFCLK_122_88 &&
+			refclk2 == SERDES_REFCLK_122_88) {
+		printf("Setting refclk1:122.88 and refclk2:122.88\n");
+		for (i = 0; i < NUM_IDT_REGS; i++)
+			i2c_reg_write(idt_addr, idt_conf_122_88[i][0],
+						idt_conf_122_88[i][1]);
+
+		if (feedback) {
+			for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++)
+				i2c_reg_write(idt_addr,
+					idt_conf_122_88_feedback[i][0],
+					idt_conf_122_88_feedback[i][1]);
+		}
+	}
+
+	if (refclk1 != SERDES_REFCLK_122_88 &&
+			refclk2 != SERDES_REFCLK_122_88) {
+		for (i = 0; i < NUM_IDT_REGS; i++)
+			i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0],
+						idt_conf_not_122_88[i][1]);
+	}
+
+	/* Configuring IDT for output refclks as
+	 * Refclk1 = 100MHz  Refclk2 = 125MHz
+	 */
+	if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) {
+		printf("Setting refclk1:100 and refclk2:125\n");
+		i2c_reg_write(idt_addr, 0x11, 0x10);
+	}
+
+	/* Configuring IDT for output refclks as
+	 * Refclk1 = 125MHz  Refclk2 = 125MHz
+	 */
+	if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) {
+		printf("Setting refclk1:125 and refclk2:125\n");
+		i2c_reg_write(idt_addr, 0x10, 0x10);
+		i2c_reg_write(idt_addr, 0x11, 0x10);
+	}
+
+	/* Configuring IDT for output refclks as
+	 * Refclk1 = 125MHz  Refclk2 = 100MHz
+	 */
+	if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) {
+		printf("Setting refclk1:125 and refclk2:100\n");
+		i2c_reg_write(idt_addr, 0x10, 0x10);
+	}
+
+	/* Configuring IDT for output refclks as
+	 * Refclk1 = 156.25MHz  Refclk2 = 156.25MHz
+	 */
+	if (refclk1 == SERDES_REFCLK_156_25 &&
+			refclk2 == SERDES_REFCLK_156_25) {
+		printf("Setting refclk1:156.25 and refclk2:156.25\n");
+		for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+			i2c_reg_write(idt_addr, idt_conf_156_25[i][0],
+						idt_conf_156_25[i][1]);
+	}
+
+	/* Configuring IDT for output refclks as
+	 * Refclk1 = 100MHz  Refclk2 = 156.25MHz
+	 */
+	if (refclk1 == SERDES_REFCLK_100 &&
+			refclk2 == SERDES_REFCLK_156_25) {
+		printf("Setting refclk1:100 and refclk2:156.25\n");
+		for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+			i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0],
+						idt_conf_100_156_25[i][1]);
+	}
+
+	/* Configuring IDT for output refclks as
+	 * Refclk1 = 125MHz  Refclk2 = 156.25MHz
+	 */
+	if (refclk1 == SERDES_REFCLK_125 &&
+			refclk2 == SERDES_REFCLK_156_25) {
+		printf("Setting refclk1:125 and refclk2:156.25\n");
+		for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+			i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0],
+						idt_conf_125_156_25[i][1]);
+	}
+
+	/* Configuring IDT for output refclks as
+	 * Refclk1 = 156.25MHz  Refclk2 = 100MHz
+	 */
+	if (refclk1 == SERDES_REFCLK_156_25 &&
+			refclk2 == SERDES_REFCLK_100) {
+		printf("Setting refclk1:156.25 and refclk2:100\n");
+		for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+			i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0],
+						idt_conf_156_25_100[i][1]);
+	}
+
+	/* Configuring IDT for output refclks as
+	 * Refclk1 = 156.25MHz  Refclk2 = 125MHz
+	 */
+	if (refclk1 == SERDES_REFCLK_156_25 &&
+			refclk2 == SERDES_REFCLK_125) {
+		printf("Setting refclk1:156.25 and refclk2:125\n");
+		for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+			i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0],
+						idt_conf_156_25_125[i][1]);
+	}
+
+	/* waiting for maximum of 1 second if PLL doesn'r get locked
+	 * initially. then check the status again.
+	 */
+	if (check_pll_status(idt_addr)) {
+		mdelay(1000);
+		if (check_pll_status(idt_addr))
+			return -1;
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/common/idt8t49n222a_serdes_clk.h b/roms/u-boot/board/freescale/common/idt8t49n222a_serdes_clk.h
new file mode 100644
index 000000000..b1528e326
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/idt8t49n222a_serdes_clk.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Shaveta Leekha <shaveta@freescale.com>
+ */
+
+#ifndef __IDT8T49N222A_SERDES_CLK_H_
+#define __IDT8T49N222A_SERDES_CLK_H_	1
+
+#include <common.h>
+#include <i2c.h>
+#include "qixis.h"
+#include "../b4860qds/b4860qds_qixis.h"
+#include <errno.h>
+
+#define NUM_IDT_REGS		23
+#define NUM_IDT_REGS_FEEDBACK	12
+#define NUM_IDT_REGS_156_25	11
+
+/* CLK */
+enum serdes_refclk {
+	SERDES_REFCLK_100,	/* refclk 100Mhz */
+	SERDES_REFCLK_122_88,	/* refclk 122.88Mhz */
+	SERDES_REFCLK_125,	/* refclk 125Mhz */
+	SERDES_REFCLK_156_25,	/* refclk 156.25Mhz */
+	SERDES_REFCLK_NONE = -1,
+};
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
+ */
+static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
+		{0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00},
+		{0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
+		{0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
+		{0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12},
+		{0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
+		{0x16, 0xA0} };
+
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
+ */
+static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
+		{0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00},
+		{0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
+		{0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
+		{0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14},
+		{0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
+		{0x16, 0xA0} };
+
+/* Reconfiguration values for some of IDT registers for
+ * Output Refclks:
+ * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
+ * and with feedback as 1
+ */
+static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
+		{0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07},
+		{0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B},
+		{0x14, 0x00}, {0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
+ */
+static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+		{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+		{0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
+		{0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 100MHz Refclk2 : 156.25MHz
+ */
+static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+		{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+		{0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
+		{0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 125MHz Refclk2 : 156.25MHz
+ */
+static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+		{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+		{0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
+		{0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 156.25MHz Refclk2 : 100MHz
+ */
+static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+		{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+		{0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C},
+		{0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 156.25MHz Refclk2 : 125MHz
+ */
+static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+		{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+		{0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C},
+		{0x15, 0xE8} };
+
+int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
+			enum serdes_refclk refclk1,
+			enum serdes_refclk refclk2, u8 feedback);
+
+#endif	/*__IDT8T49N222A_SERDES_CLK_H_ */
diff --git a/roms/u-boot/board/freescale/common/ls102xa_stream_id.c b/roms/u-boot/board/freescale/common/ls102xa_stream_id.c
new file mode 100644
index 000000000..a6ee87da9
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/ls102xa_stream_id.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ls102xa_stream_id.h>
+
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
+{
+	void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+	int i;
+	u32 icid;
+
+	for (i = 0; i < num; i++) {
+		icid = (id[i].stream_id & 0xff) << 24;
+		out_be32((u32 *)(scfg + id[i].offset), icid);
+	}
+}
+
+void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
+{
+	int i;
+	u32 liodn;
+
+	for (i = 0; i < size; i++) {
+		if (tbl[i].num_ids == 2)
+			liodn = (tbl[i].id[0] << 16) | tbl[i].id[1];
+		else
+			liodn = tbl[i].id[0];
+
+		out_le32((u32 *)(tbl[i].reg_offset), liodn);
+	}
+}
diff --git a/roms/u-boot/board/freescale/common/mc34vr500.c b/roms/u-boot/board/freescale/common/mc34vr500.c
new file mode 100644
index 000000000..d6b4c65a3
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/mc34vr500.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+#include <log.h>
+#include <power/pmic.h>
+#include <power/mc34vr500_pmic.h>
+
+static uint8_t swxvolt_addr[4] = { MC34VR500_SW1VOLT,
+				   MC34VR500_SW2VOLT,
+				   MC34VR500_SW3VOLT,
+				   MC34VR500_SW4VOLT };
+
+static uint8_t swx_set_point_base[4] = { 13, 9, 9, 9 };
+
+int mc34vr500_get_sw_volt(uint8_t sw)
+{
+	struct pmic *p;
+	u32 swxvolt;
+	uint8_t spb;
+	int sw_volt;
+	int ret;
+
+	debug("%s: Get SW%u volt from swxvolt_addr = 0x%x\n",
+	      __func__, sw + 1, swxvolt_addr[sw]);
+	if (sw > SW4) {
+		printf("%s: Unsupported SW(sw%d)\n", __func__, sw + 1);
+		return -EINVAL;
+	}
+
+	p = pmic_get("MC34VR500");
+	if (!p) {
+		printf("%s: Did NOT find PMIC MC34VR500\n", __func__);
+		return -ENODEV;
+	}
+
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	ret = pmic_reg_read(p, swxvolt_addr[sw], &swxvolt);
+	if (ret) {
+		printf("%s: Failed to get SW%u volt\n", __func__, sw + 1);
+		return ret;
+	}
+
+	debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt);
+	spb = swx_set_point_base[sw];
+	/* The base of SW volt is 625mV and increase by step 25mV */
+	sw_volt = 625 + (swxvolt - spb) * 25;
+
+	debug("%s: SW%u volt = %dmV\n", __func__, sw + 1, sw_volt);
+	return sw_volt;
+}
+
+int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt)
+{
+	struct pmic *p;
+	u32 swxvolt;
+	uint8_t spb;
+	int ret;
+
+	debug("%s: Set SW%u volt to %dmV\n", __func__, sw + 1, sw_volt);
+	/* The least SW volt is 625mV, and only 4 SW outputs */
+	if (sw > SW4 || sw_volt < 625)
+		return -EINVAL;
+
+	p = pmic_get("MC34VR500");
+	if (!p) {
+		printf("%s: Did NOT find PMIC MC34VR500\n", __func__);
+		return -ENODEV;
+	}
+
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	spb = swx_set_point_base[sw];
+	/* The base of SW volt is 625mV and increase by step 25mV */
+	swxvolt = (sw_volt - 625) / 25 + spb;
+	debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt);
+	if (swxvolt > 63)
+		return -EINVAL;
+
+	ret = pmic_reg_write(p, swxvolt_addr[sw], swxvolt);
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/common/mpc85xx_sleep.c b/roms/u-boot/board/freescale/common/mpc85xx_sleep.c
new file mode 100644
index 000000000..d2bb173c1
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/mpc85xx_sleep.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/immap_85xx.h>
+#include "sleep.h"
+#ifdef CONFIG_U_QE
+#include <fsl_qe.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+void __weak board_sleep_prepare(void)
+{
+}
+
+bool is_warm_boot(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
+		return 1;
+
+	return 0;
+}
+
+void fsl_dp_disable_console(void)
+{
+	gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+}
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+static void dp_ddr_restore(void)
+{
+	u64 *src, *dst;
+	int i;
+	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+	/* get the address of ddr date from SPARECR3 */
+	src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
+	dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
+
+	for (i = 0; i < DDR_BUFF_LEN / 8; i++)
+		*dst-- = *src--;
+
+	flush_dcache();
+}
+
+static void dp_resume_prepare(void)
+{
+	dp_ddr_restore();
+
+	board_sleep_prepare();
+
+	l2cache_init();
+#if defined(CONFIG_RAMBOOT_PBL)
+	disable_cpc_sram();
+#endif
+	enable_cpc();
+
+#ifdef CONFIG_U_QE
+	u_qe_resume();
+#endif
+
+}
+
+int fsl_dp_resume(void)
+{
+	u32 start_addr;
+	void (*kernel_resume)(void);
+	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+	if (!is_warm_boot())
+		return 0;
+
+	dp_resume_prepare();
+
+	/* Get the entry address and jump to kernel */
+	start_addr = in_be32(&scfg->sparecr[1]);
+	debug("Entry address is 0x%08x\n", start_addr);
+	kernel_resume = (void (*)(void))start_addr;
+	kernel_resume();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/common/ngpixis.c b/roms/u-boot/board/freescale/common/ngpixis.c
new file mode 100644
index 000000000..37a6f775a
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/ngpixis.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * Copyright 2010-2011 Freescale Semiconductor
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ *
+ * A "switch" is black rectangular block on the motherboard.  It contains
+ * eight "bits".  The ngPIXIS has a set of memory-mapped registers (SWx) that
+ * shadow the actual physical switches.  There is also another set of
+ * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
+ * used to override the values of the bits in the physical switches.
+ *
+ * The following macros need to be defined:
+ *
+ * PIXIS_BASE - The virtual address of the base of the PIXIS register map
+ *
+ * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
+ *    is used in the PIXIS_SW() macro to determine which offset in
+ *    the PIXIS register map corresponds to the physical switch that controls
+ *    the boot bank.
+ *
+ * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
+ *
+ * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
+ *
+ * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
+ *    boot from the alternate bank.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "ngpixis.h"
+
+static u8 __pixis_read(unsigned int reg)
+{
+	void *p = (void *)PIXIS_BASE;
+
+	return in_8(p + reg);
+}
+u8 pixis_read(unsigned int reg) __attribute__((weak, alias("__pixis_read")));
+
+static void __pixis_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)PIXIS_BASE;
+
+	out_8(p + reg, value);
+}
+void pixis_write(unsigned int reg, u8 value)
+	__attribute__((weak, alias("__pixis_write")));
+
+/*
+ * Reset the board. This ignores the ENx registers.
+ */
+void __pixis_reset(void)
+{
+	PIXIS_WRITE(rst, 0);
+
+	while (1);
+}
+void pixis_reset(void) __attribute__((weak, alias("__pixis_reset")));
+
+/*
+ * Reset the board.  Like pixis_reset(), but it honors the ENx registers.
+ */
+void __pixis_bank_reset(void)
+{
+	PIXIS_WRITE(vctl, 0);
+	PIXIS_WRITE(vctl, 1);
+
+	while (1);
+}
+void pixis_bank_reset(void) __attribute__((weak, alias("__pixis_bank_reset")));
+
+/**
+ * Set the boot bank to the power-on default bank
+ */
+void __clear_altbank(void)
+{
+	u8 reg;
+
+	/* Tell the ngPIXIS to use this the bits in the physical switch for the
+	 * boot bank value, instead of the SWx register.  We need to be careful
+	 * only to set the bits in SWx that correspond to the boot bank.
+	 */
+	reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en);
+	reg &= ~PIXIS_LBMAP_MASK;
+	PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg);
+}
+void clear_altbank(void) __attribute__((weak, alias("__clear_altbank")));
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void __set_altbank(void)
+{
+	u8 reg;
+
+	/* Program the alternate bank number into the SWx register.
+	 */
+	reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].sw);
+	reg = (reg & ~PIXIS_LBMAP_MASK) | PIXIS_LBMAP_ALTBANK;
+	PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].sw, reg);
+
+	/* Tell the ngPIXIS to use this the bits in the SWx register for the
+	 * boot bank value, instead of the physical switch.  We need to be
+	 * careful only to set the bits in SWx that correspond to the boot bank.
+	 */
+	reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en);
+	reg |= PIXIS_LBMAP_MASK;
+	PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg);
+}
+void set_altbank(void) __attribute__((weak, alias("__set_altbank")));
+
+#ifdef DEBUG
+static void pixis_dump_regs(void)
+{
+	unsigned int i;
+
+	printf("id=%02x\n", PIXIS_READ(id));
+	printf("arch=%02x\n", PIXIS_READ(arch));
+	printf("scver=%02x\n", PIXIS_READ(scver));
+	printf("csr=%02x\n", PIXIS_READ(csr));
+	printf("rst=%02x\n", PIXIS_READ(rst));
+	printf("aux=%02x\n", PIXIS_READ(aux));
+	printf("spd=%02x\n", PIXIS_READ(spd));
+	printf("brdcfg0=%02x\n", PIXIS_READ(brdcfg0));
+	printf("brdcfg1=%02x\n", PIXIS_READ(brdcfg1));
+	printf("addr=%02x\n", PIXIS_READ(addr));
+	printf("data=%02x\n", PIXIS_READ(data));
+	printf("led=%02x\n", PIXIS_READ(led));
+	printf("vctl=%02x\n", PIXIS_READ(vctl));
+	printf("vstat=%02x\n", PIXIS_READ(vstat));
+	printf("vcfgen0=%02x\n", PIXIS_READ(vcfgen0));
+	printf("ocmcsr=%02x\n", PIXIS_READ(ocmcsr));
+	printf("ocmmsg=%02x\n", PIXIS_READ(ocmmsg));
+	printf("gmdbg=%02x\n", PIXIS_READ(gmdbg));
+	printf("sclk=%02x%02x%02x\n",
+	       PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2]));
+	printf("dclk=%02x%02x%02x\n",
+	       PIXIS_READ(dclk[0]), PIXIS_READ(dclk[1]), PIXIS_READ(dclk[2]));
+	printf("watch=%02x\n", PIXIS_READ(watch));
+
+	for (i = 0; i < 8; i++) {
+		printf("SW%u=%02x/%02x ", i + 1,
+			PIXIS_READ(s[i].sw), PIXIS_READ(s[i].en));
+	}
+	putc('\n');
+}
+#endif
+
+void pixis_sysclk_set(unsigned long sysclk)
+{
+	unsigned long freq_word;
+	u8 sclk0, sclk1, sclk2;
+
+	freq_word = ics307_sysclk_calculator(sysclk);
+	sclk2 = freq_word & 0xff;
+	sclk1 = (freq_word >> 8) & 0xff;
+	sclk0 = (freq_word >> 16) & 0xff;
+
+	/* set SYSCLK enable bit */
+	PIXIS_WRITE(vcfgen0, 0x01);
+
+	/* SYSCLK to required frequency */
+	PIXIS_WRITE(sclk[0], sclk0);
+	PIXIS_WRITE(sclk[1], sclk1);
+	PIXIS_WRITE(sclk[2], sclk2);
+}
+
+int pixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+		    char *const argv[])
+{
+	unsigned int i;
+	unsigned long sysclk;
+	char *p_altbank = NULL;
+#ifdef DEBUG
+	char *p_dump = NULL;
+#endif
+	char *unknown_param = NULL;
+
+	/* No args is a simple reset request.
+	 */
+	if (argc <= 1)
+		pixis_reset();
+
+	for (i = 1; i < argc; i++) {
+		if (strcmp(argv[i], "altbank") == 0) {
+			p_altbank = argv[i];
+			continue;
+		}
+
+#ifdef DEBUG
+		if (strcmp(argv[i], "dump") == 0) {
+			p_dump = argv[i];
+			continue;
+		}
+#endif
+		if (strcmp(argv[i], "sysclk") == 0) {
+			sysclk = simple_strtoul(argv[i + 1], NULL, 0);
+			i += 1;
+			pixis_sysclk_set(sysclk);
+			continue;
+		}
+
+		unknown_param = argv[i];
+	}
+
+	if (unknown_param) {
+		printf("Invalid option: %s\n", unknown_param);
+		return 1;
+	}
+
+#ifdef DEBUG
+	if (p_dump) {
+		pixis_dump_regs();
+
+		/* 'dump' ignores other commands */
+		return 0;
+	}
+#endif
+
+	if (p_altbank)
+		set_altbank();
+	else
+		clear_altbank();
+
+	pixis_bank_reset();
+
+	/* Shouldn't be reached. */
+	return 0;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char pixis_help_text[] =
+	"- hard reset to default bank\n"
+	"pixis_reset altbank - reset to alternate bank\n"
+#ifdef DEBUG
+	"pixis_reset dump - display the PIXIS registers\n"
+#endif
+	"pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n";
+#endif
+
+U_BOOT_CMD(
+	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+	"Reset the board using the FPGA sequencer", pixis_help_text
+	);
diff --git a/roms/u-boot/board/freescale/common/ngpixis.h b/roms/u-boot/board/freescale/common/ngpixis.h
new file mode 100644
index 000000000..7a20ee015
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/ngpixis.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/**
+ * Copyright 2010-2011 Freescale Semiconductor
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/* ngPIXIS register set. Hopefully, this won't change too much over time.
+ * Feel free to add board-specific #ifdefs where necessary.
+ */
+typedef struct ngpixis {
+	u8 id;
+	u8 arch;
+	u8 scver;
+	u8 csr;
+	u8 rst;
+	u8 serclk;
+	u8 aux;
+	u8 spd;
+	u8 brdcfg0;
+	u8 brdcfg1;	/* On some boards, this register is called 'dma' */
+	u8 addr;
+	u8 brdcfg2;
+	u8 gpiodir;
+	u8 data;
+	u8 led;
+	u8 tag;
+	u8 vctl;
+	u8 vstat;
+	u8 vcfgen0;
+	u8 res4;
+	u8 ocmcsr;
+	u8 ocmmsg;
+	u8 gmdbg;
+	u8 res5[2];
+	u8 sclk[3];
+	u8 dclk[3];
+	u8 watch;
+	struct {
+		u8 sw;
+		u8 en;
+	} s[9];		/* s[0]..s[7] is SW1..SW8, and s[8] is SW11 */
+} __attribute__ ((packed)) ngpixis_t;
+
+/* Pointer to the PIXIS register set */
+#define pixis ((ngpixis_t *)PIXIS_BASE)
+
+/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */
+#define PIXIS_SW(x)		(pixis->s[(x) - 1].sw)
+
+/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */
+#define PIXIS_EN(x)		(pixis->s[(x) - 1].en)
+
+u8 pixis_read(unsigned int reg);
+void pixis_write(unsigned int reg, u8 value);
+
+#define PIXIS_READ(reg) pixis_read(offsetof(ngpixis_t, reg))
+#define PIXIS_WRITE(reg, value) pixis_write(offsetof(ngpixis_t, reg), value)
diff --git a/roms/u-boot/board/freescale/common/ns_access.c b/roms/u-boot/board/freescale/common/ns_access.c
new file mode 100644
index 000000000..ee8ed616c
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/ns_access.c
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <fsl_csu.h>
+#include <asm/arch/ns_access.h>
+#include <asm/arch/fsl_serdes.h>
+
+#ifdef CONFIG_ARCH_LS1021A
+static struct csu_ns_dev ns_dev[] = {
+	{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+	{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+	{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+	{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+	{ CSU_CSLX_OCRAM, CSU_ALL_RW },
+	{ CSU_CSLX_GIC, CSU_ALL_RW },
+	{ CSU_CSLX_PCIE1, CSU_ALL_RW },
+	{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
+	{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+	{ CSU_CSLX_PCIE2, CSU_ALL_RW },
+	{ CSU_CSLX_SATA, CSU_ALL_RW },
+	{ CSU_CSLX_USB3, CSU_ALL_RW },
+	{ CSU_CSLX_SERDES, CSU_ALL_RW },
+	{ CSU_CSLX_QDMA, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART2, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART1, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART4, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART3, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART6, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART5, CSU_ALL_RW },
+	{ CSU_CSLX_DSPI2, CSU_ALL_RW },
+	{ CSU_CSLX_DSPI1, CSU_ALL_RW },
+	{ CSU_CSLX_QSPI, CSU_ALL_RW },
+	{ CSU_CSLX_ESDHC, CSU_ALL_RW },
+	{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
+	{ CSU_CSLX_IFC, CSU_ALL_RW },
+	{ CSU_CSLX_I2C1, CSU_ALL_RW },
+	{ CSU_CSLX_USB2, CSU_ALL_RW },
+	{ CSU_CSLX_I2C3, CSU_ALL_RW },
+	{ CSU_CSLX_I2C2, CSU_ALL_RW },
+	{ CSU_CSLX_DUART2, CSU_ALL_RW },
+	{ CSU_CSLX_DUART1, CSU_ALL_RW },
+	{ CSU_CSLX_WDT2, CSU_ALL_RW },
+	{ CSU_CSLX_WDT1, CSU_ALL_RW },
+	{ CSU_CSLX_EDMA, CSU_ALL_RW },
+	{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+	{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+	{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+	{ CSU_CSLX_DDR, CSU_ALL_RW },
+	{ CSU_CSLX_QUICC, CSU_ALL_RW },
+	{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+	{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+	{ CSU_CSLX_SFP, CSU_ALL_RW },
+	{ CSU_CSLX_TMU, CSU_ALL_RW },
+	{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+	{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
+	{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
+	{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
+	{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
+	{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO2, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO1, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO4, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO3, CSU_ALL_RW },
+	{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+	{ CSU_CSLX_CSU, CSU_ALL_RW },
+	{ CSU_CSLX_ASRC, CSU_ALL_RW },
+	{ CSU_CSLX_SPDIF, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+	{ CSU_CSLX_SAI2, CSU_ALL_RW },
+	{ CSU_CSLX_SAI1, CSU_ALL_RW },
+	{ CSU_CSLX_SAI4, CSU_ALL_RW },
+	{ CSU_CSLX_SAI3, CSU_ALL_RW },
+	{ CSU_CSLX_FTM2, CSU_ALL_RW },
+	{ CSU_CSLX_FTM1, CSU_ALL_RW },
+	{ CSU_CSLX_FTM4, CSU_ALL_RW },
+	{ CSU_CSLX_FTM3, CSU_ALL_RW },
+	{ CSU_CSLX_FTM6, CSU_ALL_RW },
+	{ CSU_CSLX_FTM5, CSU_ALL_RW },
+	{ CSU_CSLX_FTM8, CSU_ALL_RW },
+	{ CSU_CSLX_FTM7, CSU_ALL_RW },
+	{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+	{ CSU_CSLX_EPU, CSU_ALL_RW },
+	{ CSU_CSLX_GDI, CSU_ALL_RW },
+	{ CSU_CSLX_DDI, CSU_ALL_RW },
+	{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
+	{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+	{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+
+#else
+static struct csu_ns_dev ns_dev[] = {
+	 {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
+	 {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
+	 {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
+	 {CSU_CSLX_OCRAM, CSU_ALL_RW},
+	 {CSU_CSLX_GIC, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE1, CSU_ALL_RW},
+	 {CSU_CSLX_OCRAM2, CSU_ALL_RW},
+	 {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE2, CSU_ALL_RW},
+	 {CSU_CSLX_SATA, CSU_ALL_RW},
+	 {CSU_CSLX_USB1, CSU_ALL_RW},
+	 {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE3, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
+	 {CSU_CSLX_USB3, CSU_ALL_RW},
+	 {CSU_CSLX_USB2, CSU_ALL_RW},
+	 {CSU_CSLX_PFE, CSU_ALL_RW},
+	 {CSU_CSLX_SERDES, CSU_ALL_RW},
+	 {CSU_CSLX_QDMA, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART2, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART1, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART4, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART3, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART6, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART5, CSU_ALL_RW},
+	 {CSU_CSLX_DSPI1, CSU_ALL_RW},
+	 {CSU_CSLX_QSPI, CSU_ALL_RW},
+	 {CSU_CSLX_ESDHC, CSU_ALL_RW},
+	 {CSU_CSLX_IFC, CSU_ALL_RW},
+	 {CSU_CSLX_I2C1, CSU_ALL_RW},
+	 {CSU_CSLX_I2C3, CSU_ALL_RW},
+	 {CSU_CSLX_I2C2, CSU_ALL_RW},
+	 {CSU_CSLX_DUART2, CSU_ALL_RW},
+	 {CSU_CSLX_DUART1, CSU_ALL_RW},
+	 {CSU_CSLX_WDT2, CSU_ALL_RW},
+	 {CSU_CSLX_WDT1, CSU_ALL_RW},
+	 {CSU_CSLX_EDMA, CSU_ALL_RW},
+	 {CSU_CSLX_SYS_CNT, CSU_ALL_RW},
+	 {CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
+	 {CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
+	 {CSU_CSLX_DDR, CSU_ALL_RW},
+	 {CSU_CSLX_QUICC, CSU_ALL_RW},
+	 {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
+	 {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
+	 {CSU_CSLX_SFP, CSU_ALL_RW},
+	 {CSU_CSLX_TMU, CSU_ALL_RW},
+	 {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
+	 {CSU_CSLX_SCFG, CSU_ALL_RW},
+	 {CSU_CSLX_FM, CSU_ALL_RW},
+	 {CSU_CSLX_SEC5_5, CSU_ALL_RW},
+	 {CSU_CSLX_BM, CSU_ALL_RW},
+	 {CSU_CSLX_QM, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO2, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO1, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO4, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO3, CSU_ALL_RW},
+	 {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
+	 {CSU_CSLX_CSU, CSU_ALL_RW},
+	 {CSU_CSLX_IIC4, CSU_ALL_RW},
+	 {CSU_CSLX_WDT4, CSU_ALL_RW},
+	 {CSU_CSLX_WDT3, CSU_ALL_RW},
+	 {CSU_CSLX_ESDHC2, CSU_ALL_RW},
+	 {CSU_CSLX_WDT5, CSU_ALL_RW},
+	 {CSU_CSLX_SAI2, CSU_ALL_RW},
+	 {CSU_CSLX_SAI1, CSU_ALL_RW},
+	 {CSU_CSLX_SAI4, CSU_ALL_RW},
+	 {CSU_CSLX_SAI3, CSU_ALL_RW},
+	 {CSU_CSLX_FTM2, CSU_ALL_RW},
+	 {CSU_CSLX_FTM1, CSU_ALL_RW},
+	 {CSU_CSLX_FTM4, CSU_ALL_RW},
+	 {CSU_CSLX_FTM3, CSU_ALL_RW},
+	 {CSU_CSLX_FTM6, CSU_ALL_RW},
+	 {CSU_CSLX_FTM5, CSU_ALL_RW},
+	 {CSU_CSLX_FTM8, CSU_ALL_RW},
+	 {CSU_CSLX_FTM7, CSU_ALL_RW},
+	 {CSU_CSLX_DSCR, CSU_ALL_RW},
+};
+#endif
+
+void set_devices_ns_access(unsigned long index, u16 val)
+{
+	u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
+	u32 *reg;
+	uint32_t tmp;
+
+	reg = base + index / 2;
+	tmp = in_be32(reg);
+	if (index % 2 == 0) {
+		tmp &= 0x0000ffff;
+		tmp |= val << 16;
+	} else {
+		tmp &= 0xffff0000;
+		tmp |= val;
+	}
+
+	out_be32(reg, tmp);
+}
+
+static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+{
+	int i;
+
+	for (i = 0; i < num; i++)
+		set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
+}
+
+void enable_layerscape_ns_access(void)
+{
+#ifdef CONFIG_ARM64
+	if (current_el() == 3)
+#endif
+		enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+}
+
+void set_pcie_ns_access(int pcie, u16 val)
+{
+	switch (pcie) {
+#ifdef CONFIG_PCIE1
+	case PCIE1:
+		set_devices_ns_access(CSU_CSLX_PCIE1, val);
+		set_devices_ns_access(CSU_CSLX_PCIE1_IO, val);
+		return;
+#endif
+#ifdef CONFIG_PCIE2
+	case PCIE2:
+		set_devices_ns_access(CSU_CSLX_PCIE2, val);
+		set_devices_ns_access(CSU_CSLX_PCIE2_IO, val);
+		return;
+#endif
+#ifdef CONFIG_PCIE3
+	case PCIE3:
+		set_devices_ns_access(CSU_CSLX_PCIE3, val);
+		set_devices_ns_access(CSU_CSLX_PCIE3_IO, val);
+		return;
+#endif
+	default:
+		debug("The PCIE%d doesn't exist!\n", pcie);
+		return;
+	}
+}
diff --git a/roms/u-boot/board/freescale/common/p_corenet/Makefile b/roms/u-boot/board/freescale/common/p_corenet/Makefile
new file mode 100644
index 000000000..29c9d544a
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/p_corenet/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y			+= law.o
+obj-$(CONFIG_PCI)	+= pci.o
+obj-y			+= tlb.o
diff --git a/roms/u-boot/board/freescale/common/p_corenet/law.c b/roms/u-boot/board/freescale/common/p_corenet/law.c
new file mode 100644
index 000000000..603384ac4
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/p_corenet/law.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef PIXIS_BASE_PHYS
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CPLD_BASE_PHYS
+	SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/common/p_corenet/pci.c b/roms/u-boot/board/freescale/common/p_corenet/pci.c
new file mode 100644
index 000000000..636334863
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/p_corenet/pci.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+#if !defined(CONFIG_DM_PCI)
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, struct bd_info *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/common/p_corenet/tlb.c b/roms/u-boot/board/freescale/common/p_corenet/tlb.c
new file mode 100644
index 000000000..c0ab1a5fd
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/p_corenet/tlb.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+#ifdef CPLD_BASE
+	SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+#endif
+
+#ifdef PIXIS_BASE
+	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+#endif
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+
+#if !defined(CONFIG_NXP_ESBC)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot
+	 * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR,
+	 * and virtual address is CONFIG_SYS_MONITOR_BASE
+	 */
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000,
+			CONFIG_SYS_INIT_L3_ADDR & 0xfff00000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_1M, 1),
+#endif
+
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+	 * space is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+			CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+			0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 16, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+	 * fetching ucode and ENV from master
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/freescale/common/pfuze.c b/roms/u-boot/board/freescale/common/pfuze.c
new file mode 100644
index 000000000..6dca22960
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/pfuze.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+
+#ifndef CONFIG_DM_PMIC_PFUZE100
+int pfuze_mode_init(struct pmic *p, u32 mode)
+{
+	unsigned char offset, i, switch_num;
+	u32 id;
+	int ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
+	id = id & 0xf;
+
+	if (id == 0) {
+		switch_num = 6;
+		offset = PFUZE100_SW1CMODE;
+	} else if (id == 1) {
+		switch_num = 4;
+		offset = PFUZE100_SW2MODE;
+	} else {
+		printf("Not supported, id=%d\n", id);
+		return -EINVAL;
+	}
+
+	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+	if (ret < 0) {
+		printf("Set SW1AB mode error!\n");
+		return ret;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
+		if (ret < 0) {
+			printf("Set switch 0x%x mode error!\n",
+			       offset + i * SWITCH_SIZE);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+struct pmic *pfuze_common_init(unsigned char i2cbus)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(i2cbus);
+	if (ret)
+		return NULL;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return NULL;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+	return p;
+}
+#else
+int pfuze_mode_init(struct udevice *dev, u32 mode)
+{
+	unsigned char offset, i, switch_num;
+	u32 id;
+	int ret;
+
+	id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	id = id & 0xf;
+
+	if (id == 0) {
+		switch_num = 6;
+		offset = PFUZE100_SW1CMODE;
+	} else if (id == 1) {
+		switch_num = 4;
+		offset = PFUZE100_SW2MODE;
+	} else {
+		printf("Not supported, id=%d\n", id);
+		return -EINVAL;
+	}
+
+	ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
+	if (ret < 0) {
+		printf("Set SW1AB mode error!\n");
+		return ret;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
+		if (ret < 0) {
+			printf("Set switch 0x%x mode error!\n",
+			       offset + i * SWITCH_SIZE);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+struct udevice *pfuze_common_init(void)
+{
+	struct udevice *dev;
+	int ret;
+	unsigned int reg, dev_id, rev_id;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV)
+		return NULL;
+
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+
+	return dev;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/common/pfuze.h b/roms/u-boot/board/freescale/common/pfuze.h
new file mode 100644
index 000000000..45b49afae
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/pfuze.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __PFUZE_BOARD_HELPER__
+#define __PFUZE_BOARD_HELPER__
+
+#ifdef CONFIG_DM_PMIC_PFUZE100
+struct udevice *pfuze_common_init(void);
+int pfuze_mode_init(struct udevice *dev, u32 mode);
+#else
+struct pmic *pfuze_common_init(unsigned char i2cbus);
+int pfuze_mode_init(struct pmic *p, u32 mode);
+#endif
+
+#endif
diff --git a/roms/u-boot/board/freescale/common/pixis.c b/roms/u-boot/board/freescale/common/pixis.c
new file mode 100644
index 000000000..4127fbc13
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/pixis.c
@@ -0,0 +1,543 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2006,2010 Freescale Semiconductor
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#define pixis_base (u8 *)PIXIS_BASE
+
+/*
+ * Simple board reset.
+ */
+void pixis_reset(void)
+{
+	out_8(pixis_base + PIXIS_RST, 0);
+
+	while (1);
+}
+
+/*
+ * Per table 27, page 58 of MPC8641HPCN spec.
+ */
+static int set_px_sysclk(unsigned long sysclk)
+{
+	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
+
+	switch (sysclk) {
+	case 33:
+		sysclk_s = 0x04;
+		sysclk_r = 0x04;
+		sysclk_v = 0x07;
+		sysclk_aux = 0x00;
+		break;
+	case 40:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x20;
+		sysclk_aux = 0x01;
+		break;
+	case 50:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x2A;
+		sysclk_aux = 0x02;
+		break;
+	case 66:
+		sysclk_s = 0x01;
+		sysclk_r = 0x04;
+		sysclk_v = 0x04;
+		sysclk_aux = 0x03;
+		break;
+	case 83:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x4B;
+		sysclk_aux = 0x04;
+		break;
+	case 100:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x5C;
+		sysclk_aux = 0x05;
+		break;
+	case 134:
+		sysclk_s = 0x06;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x3B;
+		sysclk_aux = 0x06;
+		break;
+	case 166:
+		sysclk_s = 0x06;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x4B;
+		sysclk_aux = 0x07;
+		break;
+	default:
+		printf("Unsupported SYSCLK frequency.\n");
+		return 0;
+	}
+
+	vclkh = (sysclk_s << 5) | sysclk_r;
+	vclkl = sysclk_v;
+
+	out_8(pixis_base + PIXIS_VCLKH, vclkh);
+	out_8(pixis_base + PIXIS_VCLKL, vclkl);
+
+	out_8(pixis_base + PIXIS_AUX, sysclk_aux);
+
+	return 1;
+}
+
+/* Set the CFG_SYSPLL bits
+ *
+ * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
+ * read_from_px_regs() is called.
+ */
+static int set_px_mpxpll(unsigned long mpxpll)
+{
+	switch (mpxpll) {
+	case 2:
+	case 4:
+	case 6:
+	case 8:
+	case 10:
+	case 12:
+	case 14:
+	case 16:
+		clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
+		return 1;
+	}
+
+	printf("Unsupported MPXPLL ratio.\n");
+	return 0;
+}
+
+static int set_px_corepll(unsigned long corepll)
+{
+	u8 val;
+
+	switch (corepll) {
+	case 20:
+		val = 0x08;
+		break;
+	case 25:
+		val = 0x0C;
+		break;
+	case 30:
+		val = 0x10;
+		break;
+	case 35:
+		val = 0x1C;
+		break;
+	case 40:
+		val = 0x14;
+		break;
+	case 45:
+		val = 0x0E;
+		break;
+	default:
+		printf("Unsupported COREPLL ratio.\n");
+		return 0;
+	}
+
+	clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
+	return 1;
+}
+
+#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
+#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE		0x1C
+#endif
+
+/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
+ *
+ * The PIXIS can be programmed to look at either the on-board dip switches
+ * or various other PIXIS registers to determine the values for COREPLL,
+ * MPXPLL, and SYSCLK.
+ *
+ * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
+ * register that tells the pixis to use the various PIXIS register.
+ */
+static void read_from_px_regs(int set)
+{
+	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
+
+	if (set)
+		tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+	else
+		tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+
+	out_8(pixis_base + PIXIS_VCFGEN0, tmp);
+}
+
+/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
+ * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
+ */
+#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
+#define CONFIG_SYS_PIXIS_VBOOT_ENABLE	0x04
+#endif
+
+/* Configure the source of the boot location
+ *
+ * The PIXIS can be programmed to look at either the on-board dip switches
+ * or the PX_VBOOT[LBMAP] register to determine where we should boot.
+ *
+ * If we want to boot from the alternate boot bank, we need to tell the PIXIS
+ * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
+ */
+static void read_from_px_regs_altbank(int set)
+{
+	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
+
+	if (set)
+		tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+	else
+		tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+
+	out_8(pixis_base + PIXIS_VCFGEN1, tmp);
+}
+
+/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
+ * tells the PIXIS what the alternate flash bank is.
+ *
+ * Note that it's not really a mask.  It contains the actual LBMAP bits that
+ * must be set to select the alternate bank.  This code assumes that the
+ * primary bank has these bits set to 0, and the alternate bank has these
+ * bits set to 1.
+ */
+#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	(0x40)
+#endif
+
+/* Tell the PIXIS to boot from the default flash bank
+ *
+ * Program the default flash bank into the VBOOT register.  This register is
+ * used only if PX_VCFGEN1[FLASH]=1.
+ */
+static void clear_altbank(void)
+{
+	clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
+}
+
+/* Tell the PIXIS to boot from the alternate flash bank
+ *
+ * Program the alternate flash bank into the VBOOT register.  This register is
+ * used only if PX_VCFGEN1[FLASH]=1.
+ */
+static void set_altbank(void)
+{
+	setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
+}
+
+/* Reset the board with watchdog disabled.
+ *
+ * This respects the altbank setting.
+ */
+static void set_px_go(void)
+{
+	/* Disable the VELA sequencer and watchdog */
+	clrbits_8(pixis_base + PIXIS_VCTL, 9);
+
+	/* Reboot by starting the VELA sequencer */
+	setbits_8(pixis_base + PIXIS_VCTL, 0x1);
+
+	while (1);
+}
+
+/* Reset the board with watchdog enabled.
+ *
+ * This respects the altbank setting.
+ */
+static void set_px_go_with_watchdog(void)
+{
+	/* Disable the VELA sequencer */
+	clrbits_8(pixis_base + PIXIS_VCTL, 1);
+
+	/* Enable the watchdog and reboot by starting the VELA sequencer */
+	setbits_8(pixis_base + PIXIS_VCTL, 0x9);
+
+	while (1);
+}
+
+/* Disable the watchdog
+ *
+ */
+static int pixis_disable_watchdog_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+				      char *const argv[])
+{
+	/* Disable the VELA sequencer and the watchdog */
+	clrbits_8(pixis_base + PIXIS_VCTL, 9);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	diswd, 1, 0, pixis_disable_watchdog_cmd,
+	"Disable watchdog timer",
+	""
+);
+
+#ifdef CONFIG_PIXIS_SGMII_CMD
+
+/* Enable or disable SGMII mode for a TSEC
+ */
+static int pixis_set_sgmii(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	int which_tsec = -1;
+	unsigned char mask;
+	unsigned char switch_mask;
+
+	if ((argc > 2) && (strcmp(argv[1], "all") != 0))
+		which_tsec = simple_strtoul(argv[1], NULL, 0);
+
+	switch (which_tsec) {
+#ifdef CONFIG_TSEC1
+	case 1:
+		mask = PIXIS_VSPEED2_TSEC1SER;
+		switch_mask = PIXIS_VCFGEN1_TSEC1SER;
+		break;
+#endif
+#ifdef CONFIG_TSEC2
+	case 2:
+		mask = PIXIS_VSPEED2_TSEC2SER;
+		switch_mask = PIXIS_VCFGEN1_TSEC2SER;
+		break;
+#endif
+#ifdef CONFIG_TSEC3
+	case 3:
+		mask = PIXIS_VSPEED2_TSEC3SER;
+		switch_mask = PIXIS_VCFGEN1_TSEC3SER;
+		break;
+#endif
+#ifdef CONFIG_TSEC4
+	case 4:
+		mask = PIXIS_VSPEED2_TSEC4SER;
+		switch_mask = PIXIS_VCFGEN1_TSEC4SER;
+		break;
+#endif
+	default:
+		mask = PIXIS_VSPEED2_MASK;
+		switch_mask = PIXIS_VCFGEN1_MASK;
+		break;
+	}
+
+	/* Toggle whether the switches or FPGA control the settings */
+	if (!strcmp(argv[argc - 1], "switch"))
+		clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
+	else
+		setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
+
+	/* If it's not the switches, enable or disable SGMII, as specified */
+	if (!strcmp(argv[argc - 1], "on"))
+		clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
+	else if (!strcmp(argv[argc - 1], "off"))
+		setbits_8(pixis_base + PIXIS_VSPEED2, mask);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
+	"pixis_set_sgmii"
+	" - Enable or disable SGMII mode for a given TSEC \n",
+	"\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
+	"    TSEC num: 1,2,3,4 or 'all'.  'all' is default.\n"
+	"    on - enables SGMII\n"
+	"    off - disables SGMII\n"
+	"    switch - use switch settings"
+);
+
+#endif
+
+/*
+ * This function takes the non-integral cpu:mpx pll ratio
+ * and converts it to an integer that can be used to assign
+ * FPGA register values.
+ * input: strptr i.e. argv[2]
+ */
+static unsigned long strfractoint(char *strptr)
+{
+	int i, j;
+	int mulconst;
+	int no_dec = 0;
+	unsigned long intval = 0, decval = 0;
+	char intarr[3], decarr[3];
+
+	/* Assign the integer part to intarr[]
+	 * If there is no decimal point i.e.
+	 * if the ratio is an integral value
+	 * simply create the intarr.
+	 */
+	i = 0;
+	while (strptr[i] != '.') {
+		if (strptr[i] == 0) {
+			no_dec = 1;
+			break;
+		}
+		intarr[i] = strptr[i];
+		i++;
+	}
+
+	intarr[i] = '\0';
+
+	if (no_dec) {
+		/* Currently needed only for single digit corepll ratios */
+		mulconst = 10;
+		decval = 0;
+	} else {
+		j = 0;
+		i++;		/* Skipping the decimal point */
+		while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
+			decarr[j] = strptr[i];
+			i++;
+			j++;
+		}
+
+		decarr[j] = '\0';
+
+		mulconst = 1;
+		for (i = 0; i < j; i++)
+			mulconst *= 10;
+		decval = simple_strtoul(decarr, NULL, 10);
+	}
+
+	intval = simple_strtoul(intarr, NULL, 10);
+	intval = intval * mulconst;
+
+	return intval + decval;
+}
+
+static int pixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	unsigned int i;
+	char *p_cf = NULL;
+	char *p_cf_sysclk = NULL;
+	char *p_cf_corepll = NULL;
+	char *p_cf_mpxpll = NULL;
+	char *p_altbank = NULL;
+	char *p_wd = NULL;
+	int unknown_param = 0;
+
+	/*
+	 * No args is a simple reset request.
+	 */
+	if (argc <= 1) {
+		pixis_reset();
+		/* not reached */
+	}
+
+	for (i = 1; i < argc; i++) {
+		if (strcmp(argv[i], "cf") == 0) {
+			p_cf = argv[i];
+			if (i + 3 >= argc) {
+				break;
+			}
+			p_cf_sysclk = argv[i+1];
+			p_cf_corepll = argv[i+2];
+			p_cf_mpxpll = argv[i+3];
+			i += 3;
+			continue;
+		}
+
+		if (strcmp(argv[i], "altbank") == 0) {
+			p_altbank = argv[i];
+			continue;
+		}
+
+		if (strcmp(argv[i], "wd") == 0) {
+			p_wd = argv[i];
+			continue;
+		}
+
+		unknown_param = 1;
+	}
+
+	/*
+	 * Check that cf has all required parms
+	 */
+	if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
+	    ||	unknown_param) {
+#ifdef CONFIG_SYS_LONGHELP
+		puts(cmdtp->help);
+		putc('\n');
+#endif
+		return 1;
+	}
+
+	/*
+	 * PIXIS seems to be sensitive to the ordering of
+	 * the registers that are touched.
+	 */
+	read_from_px_regs(0);
+
+	if (p_altbank)
+		read_from_px_regs_altbank(0);
+
+	clear_altbank();
+
+	/*
+	 * Clock configuration specified.
+	 */
+	if (p_cf) {
+		unsigned long sysclk;
+		unsigned long corepll;
+		unsigned long mpxpll;
+
+		sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
+		corepll = strfractoint(p_cf_corepll);
+		mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
+
+		if (!(set_px_sysclk(sysclk)
+		      && set_px_corepll(corepll)
+		      && set_px_mpxpll(mpxpll))) {
+#ifdef CONFIG_SYS_LONGHELP
+			puts(cmdtp->help);
+			putc('\n');
+#endif
+			return 1;
+		}
+		read_from_px_regs(1);
+	}
+
+	/*
+	 * Altbank specified
+	 *
+	 * NOTE CHANGE IN BEHAVIOR: previous code would default
+	 * to enabling watchdog if altbank is specified.
+	 * Now the watchdog must be enabled explicitly using 'wd'.
+	 */
+	if (p_altbank) {
+		set_altbank();
+		read_from_px_regs_altbank(1);
+	}
+
+	/*
+	 * Reset with watchdog specified.
+	 */
+	if (p_wd)
+		set_px_go_with_watchdog();
+	else
+		set_px_go();
+
+	/*
+	 * Shouldn't be reached.
+	 */
+	return 0;
+}
+
+
+U_BOOT_CMD(
+	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+	"Reset the board using the FPGA sequencer",
+	"    pixis_reset\n"
+	"    pixis_reset [altbank]\n"
+	"    pixis_reset altbank wd\n"
+	"    pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
+	"    pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
+);
diff --git a/roms/u-boot/board/freescale/common/pixis.h b/roms/u-boot/board/freescale/common/pixis.h
new file mode 100644
index 000000000..f19e85cb1
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/pixis.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ */
+#ifndef __PIXIS_H_
+#define __PIXIS_H_	1
+
+/* PIXIS register set. */
+#if defined(CONFIG_TARGET_MPC8536DS)
+typedef struct pixis {
+	u8 id;
+	u8 ver;
+	u8 pver;
+	u8 csr;
+	u8 rst;
+	u8 rst2;
+	u8 aux1;
+	u8 spd;
+	u8 aux2;
+	u8 csr2;
+	u8 watch;
+	u8 led;
+	u8 pwr;
+	u8 res[3];
+	u8 vctl;
+	u8 vstat;
+	u8 vcfgen0;
+	u8 vcfgen1;
+	u8 vcore0;
+	u8 res1;
+	u8 vboot;
+	u8 vspeed[3];
+	u8 sclk[3];
+	u8 dclk[3];
+	u8 i2cdacr;
+	u8 vcoreacc[4];
+	u8 vcorecnt[3];
+	u8 vcoremax[2];
+	u8 vplatacc[4];
+	u8 vplatcnt[3];
+	u8 vplatmax[2];
+	u8 vtempacc[4];
+	u8 vtempcnt[3];
+	u8 vtempmax[2];
+	u8 res2[4];
+} __attribute__ ((packed)) pixis_t;
+#else
+#error Need to define pixis_t for this board
+#endif
+
+/* Pointer to the PIXIS register set */
+#define pixis ((pixis_t *)PIXIS_BASE)
+
+#endif	/* __PIXIS_H_ */
diff --git a/roms/u-boot/board/freescale/common/pq-mds-pib.c b/roms/u-boot/board/freescale/common/pq-mds-pib.c
new file mode 100644
index 000000000..596cd0018
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/pq-mds-pib.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Tony Li <tony.li@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#include "pq-mds-pib.h"
+
+int pib_init(void)
+{
+	u8 val8;
+	u8 orig_i2c_bus;
+
+	/* Switch temporarily to I2C bus #2 */
+	orig_i2c_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	val8 = 0;
+#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE)
+	/* Assign PIB PMC slot to desired PCI bus */
+	i2c_write(0x23, 0x6, 1, &val8, 1);
+	i2c_write(0x23, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x23, 0x2, 1, &val8, 1);
+	i2c_write(0x23, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x26, 0x6, 1, &val8, 1);
+	val8 = 0x34;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+#if defined(CONFIG_TARGET_MPC832XEMDS)
+	val8 = 0xf9;            /* PMC2, PMC3 slot to PCI bus */
+#else
+	val8 = 0xf3;		/* PMC1, PMC2, PMC3 slot to PCI bus */
+#endif
+	i2c_write(0x26, 0x2, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x27, 0x6, 1, &val8, 1);
+	i2c_write(0x27, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x27, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x27, 0x3, 1, &val8, 1);
+
+	eieio();
+
+#if defined(CONFIG_TARGET_MPC832XEMDS)
+	printf("PCI 32bit bus on PMC2 &PMC3\n");
+#else
+	printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
+#endif
+#endif
+
+#if defined(CONFIG_PQ_MDS_PIB_ATM)
+#if defined(CONFIG_TARGET_MPC832XEMDS)
+	val8 = 0;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+	val8 = 0xf7;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x21, 0x6, 1, &val8, 1);
+	i2c_write(0x21, 0x7, 1, &val8, 1);
+
+	val8 = 0xdf;
+	i2c_write(0x21, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x21, 0x3, 1, &val8, 1);
+
+	eieio();
+
+	printf("QOC3 ATM card on PMC1\n");
+#endif
+#endif
+	/* Reset to original I2C bus */
+	i2c_set_bus_num(orig_i2c_bus);
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/common/pq-mds-pib.h b/roms/u-boot/board/freescale/common/pq-mds-pib.h
new file mode 100644
index 000000000..67066fd11
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/pq-mds-pib.h
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+extern int pib_init(void);
diff --git a/roms/u-boot/board/freescale/common/qixis.c b/roms/u-boot/board/freescale/common/qixis.c
new file mode 100644
index 000000000..2bb838cea
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/qixis.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2011 Freescale Semiconductor
+ * Copyright 2020 NXP
+ * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * This file provides support for the QIXIS of some Freescale reference boards.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <linux/time.h>
+#include <i2c.h>
+#include "qixis.h"
+
+#ifndef QIXIS_LBMAP_BRDCFG_REG
+/*
+ * For consistency with existing platforms
+ */
+#define QIXIS_LBMAP_BRDCFG_REG 0x00
+#endif
+
+#ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#endif
+#ifndef QIXIS_RCFG_CTL_RECONFIG_START
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#endif
+
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+u8 qixis_read_i2c(unsigned int reg)
+{
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
+#else
+	struct udevice *dev;
+
+	if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+		return 0xff;
+
+	return dm_i2c_reg_read(dev, reg);
+#endif
+}
+
+void qixis_write_i2c(unsigned int reg, u8 value)
+{
+	u8 val = value;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
+#else
+	struct udevice *dev;
+
+	if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+		dm_i2c_reg_write(dev, reg, val);
+#endif
+
+}
+#endif
+
+#ifdef QIXIS_BASE
+u8 qixis_read(unsigned int reg)
+{
+	void *p = (void *)QIXIS_BASE;
+
+	return in_8(p + reg);
+}
+
+void qixis_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)QIXIS_BASE;
+
+	out_8(p + reg, value);
+}
+#endif
+
+u16 qixis_read_minor(void)
+{
+	u16 minor;
+
+	/* this data is in little endian */
+	QIXIS_WRITE(tagdata, 5);
+	minor = QIXIS_READ(tagdata);
+	QIXIS_WRITE(tagdata, 6);
+	minor += QIXIS_READ(tagdata) << 8;
+
+	return minor;
+}
+
+char *qixis_read_time(char *result)
+{
+	time_t time = 0;
+	int i;
+
+	/* timestamp is in 32-bit big endian */
+	for (i = 8; i <= 11; i++) {
+		QIXIS_WRITE(tagdata, i);
+		time =  (time << 8) + QIXIS_READ(tagdata);
+	}
+
+	return ctime_r(&time, result);
+}
+
+char *qixis_read_tag(char *buf)
+{
+	int i;
+	char tag, *ptr = buf;
+
+	for (i = 16; i <= 63; i++) {
+		QIXIS_WRITE(tagdata, i);
+		tag = QIXIS_READ(tagdata);
+		*(ptr++) = tag;
+		if (!tag)
+			break;
+	}
+	if (i > 63)
+		*ptr = '\0';
+
+	return buf;
+}
+
+/*
+ * return the string of binary of u8 in the format of
+ * 1010 10_0. The masked bit is filled as underscore.
+ */
+const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
+{
+	char *ptr;
+	int i;
+
+	ptr = buf;
+	for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
+		*ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
+	*(ptr++) = ' ';
+	for (i = 0x08; i > 0 ; i >>= 1, ptr++)
+		*ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
+
+	*ptr = '\0';
+
+	return buf;
+}
+
+#ifdef QIXIS_RST_FORCE_MEM
+void board_assert_mem_reset(void)
+{
+	u8 rst;
+
+	rst = QIXIS_READ(rst_frc[0]);
+	if (!(rst & QIXIS_RST_FORCE_MEM))
+		QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
+}
+
+void board_deassert_mem_reset(void)
+{
+	u8 rst;
+
+	rst = QIXIS_READ(rst_frc[0]);
+	if (rst & QIXIS_RST_FORCE_MEM)
+		QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
+}
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+static void qixis_reset(void)
+{
+	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
+}
+
+#ifdef QIXIS_LBMAP_ALTBANK
+static void qixis_bank_reset(void)
+{
+	QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+	QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
+}
+#endif
+
+static void __maybe_unused set_lbmap(int lbmap)
+{
+	u8 reg;
+
+	reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+	reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
+	QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
+}
+
+static void __maybe_unused set_rcw_src(int rcw_src)
+{
+#ifdef CONFIG_NXP_LSCH3_2
+	QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff));
+#else
+	u8 reg;
+
+	reg = QIXIS_READ(dutcfg[1]);
+	reg = (reg & ~1) | (rcw_src & 1);
+	QIXIS_WRITE(dutcfg[1], reg);
+	QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
+#endif
+}
+
+static void qixis_dump_regs(void)
+{
+	int i;
+
+	printf("id	= %02x\n", QIXIS_READ(id));
+	printf("arch	= %02x\n", QIXIS_READ(arch));
+	printf("scver	= %02x\n", QIXIS_READ(scver));
+	printf("model	= %02x\n", QIXIS_READ(model));
+	printf("rst_ctl	= %02x\n", QIXIS_READ(rst_ctl));
+	printf("aux	= %02x\n", QIXIS_READ(aux));
+	for (i = 0; i < 16; i++)
+		printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
+	for (i = 0; i < 16; i++)
+		printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
+	printf("sclk	= %02x%02x%02x\n", QIXIS_READ(sclk[0]),
+		QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
+	printf("dclk	= %02x%02x%02x\n", QIXIS_READ(dclk[0]),
+		QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
+	printf("aux     = %02x\n", QIXIS_READ(aux));
+	printf("watch	= %02x\n", QIXIS_READ(watch));
+	printf("ctl_sys	= %02x\n", QIXIS_READ(ctl_sys));
+	printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
+	printf("present = %02x\n", QIXIS_READ(present));
+	printf("present2 = %02x\n", QIXIS_READ(present2));
+	printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
+	printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
+	printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
+	printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
+}
+
+void __weak qixis_dump_switch(void)
+{
+	puts("Reverse engineering switch is not implemented for this board\n");
+}
+
+static int qixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	int i;
+
+	if (argc <= 1) {
+		set_lbmap(QIXIS_LBMAP_DFLTBANK);
+		qixis_reset();
+	} else if (strcmp(argv[1], "altbank") == 0) {
+#ifdef QIXIS_LBMAP_ALTBANK
+		set_lbmap(QIXIS_LBMAP_ALTBANK);
+		qixis_bank_reset();
+#else
+		printf("No Altbank!\n");
+#endif
+	} else if (strcmp(argv[1], "nand") == 0) {
+#ifdef QIXIS_LBMAP_NAND
+		QIXIS_WRITE(rst_ctl, 0x30);
+		QIXIS_WRITE(rcfg_ctl, 0);
+		set_lbmap(QIXIS_LBMAP_NAND);
+		set_rcw_src(QIXIS_RCW_SRC_NAND);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
+#else
+		printf("Not implemented\n");
+#endif
+	} else if (strcmp(argv[1], "sd") == 0) {
+#ifdef QIXIS_LBMAP_SD
+		QIXIS_WRITE(rst_ctl, 0x30);
+		QIXIS_WRITE(rcfg_ctl, 0);
+#ifdef NON_EXTENDED_DUTCFG
+		QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD);
+#else
+		set_lbmap(QIXIS_LBMAP_SD);
+		set_rcw_src(QIXIS_RCW_SRC_SD);
+#endif
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
+#else
+		printf("Not implemented\n");
+#endif
+	} else if (strcmp(argv[1], "ifc") == 0) {
+#ifdef QIXIS_LBMAP_IFC
+		QIXIS_WRITE(rst_ctl, 0x30);
+		QIXIS_WRITE(rcfg_ctl, 0);
+		set_lbmap(QIXIS_LBMAP_IFC);
+		set_rcw_src(QIXIS_RCW_SRC_IFC);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
+#else
+		printf("Not implemented\n");
+#endif
+	} else if (strcmp(argv[1], "emmc") == 0) {
+#ifdef QIXIS_LBMAP_EMMC
+		QIXIS_WRITE(rst_ctl, 0x30);
+		QIXIS_WRITE(rcfg_ctl, 0);
+#ifndef NON_EXTENDED_DUTCFG
+		set_lbmap(QIXIS_LBMAP_EMMC);
+#endif
+		set_rcw_src(QIXIS_RCW_SRC_EMMC);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
+#else
+		printf("Not implemented\n");
+#endif
+	} else if (strcmp(argv[1], "sd_qspi") == 0) {
+#ifdef QIXIS_LBMAP_SD_QSPI
+		QIXIS_WRITE(rst_ctl, 0x30);
+		QIXIS_WRITE(rcfg_ctl, 0);
+		set_lbmap(QIXIS_LBMAP_SD_QSPI);
+		set_rcw_src(QIXIS_RCW_SRC_SD);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+				QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+				QIXIS_RCFG_CTL_RECONFIG_START);
+#else
+		printf("Not implemented\n");
+#endif
+	} else if (strcmp(argv[1], "qspi") == 0) {
+#ifdef QIXIS_LBMAP_QSPI
+		QIXIS_WRITE(rst_ctl, 0x30);
+		QIXIS_WRITE(rcfg_ctl, 0);
+		set_lbmap(QIXIS_LBMAP_QSPI);
+		set_rcw_src(QIXIS_RCW_SRC_QSPI);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+				QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+				QIXIS_RCFG_CTL_RECONFIG_START);
+#else
+		printf("Not implemented\n");
+#endif
+	} else if (strcmp(argv[1], "xspi") == 0) {
+#ifdef QIXIS_LBMAP_XSPI
+		QIXIS_WRITE(rst_ctl, 0x30);
+		QIXIS_WRITE(rcfg_ctl, 0);
+		set_lbmap(QIXIS_LBMAP_XSPI);
+		set_rcw_src(QIXIS_RCW_SRC_XSPI);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+				QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+				QIXIS_RCFG_CTL_RECONFIG_START);
+#else
+		printf("Not implemented\n");
+#endif
+	} else if (strcmp(argv[1], "watchdog") == 0) {
+		static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
+					  "1min", "2min", "4min", "8min"};
+		u8 rcfg = QIXIS_READ(rcfg_ctl);
+
+		if (argv[2] == NULL) {
+			printf("qixis watchdog <watchdog_period>\n");
+			return 0;
+		}
+		for (i = 0; i < ARRAY_SIZE(period); i++) {
+			if (strcmp(argv[2], period[i]) == 0) {
+				/* disable watchdog */
+				QIXIS_WRITE(rcfg_ctl,
+					rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
+				QIXIS_WRITE(watch, ((i<<2) - 1));
+				QIXIS_WRITE(rcfg_ctl, rcfg);
+				return 0;
+			}
+		}
+	} else if (strcmp(argv[1], "dump") == 0) {
+		qixis_dump_regs();
+		return 0;
+	} else if (strcmp(argv[1], "switch") == 0) {
+		qixis_dump_switch();
+		return 0;
+	} else {
+		printf("Invalid option: %s\n", argv[1]);
+		return 1;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
+	"Reset the board using the FPGA sequencer",
+	"- hard reset to default bank\n"
+	"qixis_reset altbank - reset to alternate bank\n"
+	"qixis_reset nand - reset to nand\n"
+	"qixis_reset sd - reset to sd\n"
+	"qixis_reset sd_qspi - reset to sd with qspi support\n"
+	"qixis_reset qspi - reset to qspi\n"
+	"qixis watchdog <watchdog_period> - set the watchdog period\n"
+	"	period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
+	"qixis_reset dump - display the QIXIS registers\n"
+	"qixis_reset emmc - reset to emmc\n"
+	"qixis_reset switch - display switch\n"
+	);
+#endif
diff --git a/roms/u-boot/board/freescale/common/qixis.h b/roms/u-boot/board/freescale/common/qixis.h
new file mode 100644
index 000000000..0860bd231
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/qixis.h
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011 Freescale Semiconductor
+ * Copyright 2020 NXP
+ * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * This file provides support for the QIXIS of some Freescale reference boards.
+ */
+
+#ifndef __QIXIS_H_
+#define __QIXIS_H_
+
+struct qixis {
+	u8 id;      /* ID value uniquely identifying each QDS board type */
+	u8 arch;    /* Board version information */
+	u8 scver;   /* QIXIS Version Register */
+	u8 model;   /* Information of software programming model version */
+	u8 tagdata;
+	u8 ctl_sys;
+	u8 aux;         /* Auxiliary Register,0x06 */
+	u8 clk_spd;
+	u8 stat_dut;
+	u8 stat_sys;
+	u8 stat_alrm;
+	u8 present;
+	u8 present2;    /* Presence Status Register 2,0x0c */
+	u8 rcw_ctl;
+	u8 ctl_led;
+	u8 i2cblk;
+	u8 rcfg_ctl;    /* Reconfig Control Register,0x10 */
+	u8 rcfg_st;
+	u8 dcm_ad;
+	u8 dcm_da;
+	u8 dcmd;
+	u8 dmsg;
+	u8 gdc;
+	u8 gdd;         /* DCM Debug Data Register,0x17 */
+	u8 dmack;
+	u8 res1;
+	u8 sdhc1;
+	u8 sdhc2;
+	u8 stat_pres3;
+	u8 los_stat;
+	u8 usb_ctl;
+	u8 watch;       /* Watchdog Register,0x1F */
+	u8 pwr_ctl[2];  /* Power Control Register,0x20 */
+	u8 res2[2];
+	u8 pwr_stat[4]; /* Power Status Register,0x24 */
+	u8 res3[8];
+	u8 clk_spd2[2];  /* SYSCLK clock Speed Register,0x30 */
+	u8 res4[2];
+	u8 sclk[3];  /* Clock Configuration Registers,0x34 */
+	u8 res5;
+	u8 dclk[3];
+	u8 res6;
+	u8 clk_dspd[3];
+	u8 res7;
+	u8 rst_ctl;     /* Reset Control Register,0x40 */
+	u8 rst_stat;    /* Reset Status Register */
+	u8 rst_rsn;     /* Reset Reason Register */
+	u8 rst_frc[2];  /* Reset Force Registers,0x43 */
+	u8 res8[11];
+	u8 brdcfg[16];  /* Board Configuration Register,0x50 */
+	u8 dutcfg[16];
+	u8 rcw_ad[2];   /* RCW SRAM Address Registers,0x70 */
+	u8 rcw_data;
+	u8 res9[5];
+	u8 post_ctl;
+	u8 post_stat;
+	u8 post_dat[2];
+	u8 pi_d[4];
+	u8 gpio_io[4];
+	u8 gpio_dir[4];
+	u8 res10[20];
+	u8 rjtag_ctl;
+	u8 rjtag_dat;
+	u8 res11[2];
+	u8 trig_src[4];
+	u8 trig_dst[4];
+	u8 trig_stat;
+	u8 res12[3];
+	u8 trig_ctr[4];
+	u8 res13[16];
+	u8 clk_freq[6];	/* Clock Measurement Registers */
+	u8 res_c6[8];
+	u8 clk_base[2];	/* Clock Frequency Base Reg */
+	u8 res_d0[8];
+	u8 cms[2];	/* Core Management Space Address Register, 0xD8 */
+	u8 res_c0[6];
+	u8 aux2[4];	/* Auxiliary Registers,0xE0 */
+	u8 res14[10];
+	u8 aux_ad;
+	u8 aux_da;
+	u8 res15[16];
+};
+
+u8 qixis_read(unsigned int reg);
+void qixis_write(unsigned int reg, u8 value);
+u16 qixis_read_minor(void);
+char *qixis_read_time(char *result);
+char *qixis_read_tag(char *buf);
+const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+u8 qixis_read_i2c(unsigned int reg);
+void qixis_write_i2c(unsigned int reg, u8 value);
+#endif
+
+#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
+#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
+#define QIXIS_WRITE(reg, value) \
+	qixis_write_i2c(offsetof(struct qixis, reg), value)
+#else
+#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
+#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
+#endif
+
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
+#define QIXIS_WRITE_I2C(reg, value) \
+			qixis_write_i2c(offsetof(struct qixis, reg), value)
+#endif
+
+/* Use for SDHC adapter card type identification and operation */
+#define QIXIS_SDID_MASK                         0x07
+
+#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45         0x1	/* eMMC Card Rev4.5 */
+#define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY   0x2	/* SD/MMC Legacy Card */
+#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44         0x3	/* eMMC Card Rev4.4 */
+#define QIXIS_ESDHC_ADAPTER_TYPE_RSV            0x4	/* Reserved */
+#define QIXIS_ESDHC_ADAPTER_TYPE_MMC            0x5	/* MMC Card */
+#define QIXIS_ESDHC_ADAPTER_TYPE_SD             0x6	/* SD Card Rev2.0 3.0 */
+#define QIXIS_ESDHC_NO_ADAPTER                  0x7	/* No Card is Present*/
+
+#define QIXIS_SDHC1_S1V3	0x80	/* SDHC1: SDHC1 3.3V power control */
+#define QIXIS_SDHC1_VS		0x30	/* BRDCFG11: route to SDHC1_VS */
+
+#define QIXIS_SDCLKIN		0x08
+#define QIXIS_SDCLKOUT		0x02
+#define QIXIS_DAT5_6_7		0X02
+#define QIXIS_DAT4		0X01
+
+#define QIXIS_EVDD_BY_SDHC_VS	0x0c
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
+defined(CONFIG_TARGET_LX2160ARDB)
+#define QIXIS_XMAP_MASK			0x07
+#define QIXIS_RST_CTL_RESET_EN		0x30
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x20
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_QSPI		0xff
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SD
+#define QIXIS_LBMAP_EMMC
+#define QIXIS_RCW_SRC_SD		0x08
+#define QIXIS_RCW_SRC_EMMC         0x09
+#define NON_EXTENDED_DUTCFG
+#endif
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+#define QIXIS_SDID_MASK			0x07
+#define QIXIS_ESDHC_NO_ADAPTER		0x7
+#endif
+
+#endif
diff --git a/roms/u-boot/board/freescale/common/sdhc_boot.c b/roms/u-boot/board/freescale/common/sdhc_boot.c
new file mode 100644
index 000000000..a1c7a94a9
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/sdhc_boot.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <malloc.h>
+
+/*
+ * The environment variables are written to just after the u-boot image
+ * on SDCard, so we must read the MBR to get the start address and code
+ * length of the u-boot image, then calculate the address of the env.
+ */
+#define ESDHC_BOOT_IMAGE_SIZE	0x48
+#define ESDHC_BOOT_IMAGE_ADDR	0x50
+
+#define ESDHC_DEFAULT_ENVADDR	0x400
+
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
+{
+	u8 *tmp_buf;
+	u32 blklen, code_offset, code_len, n;
+
+	blklen = mmc->read_bl_len;
+	tmp_buf = malloc(blklen);
+	if (!tmp_buf)
+		return 1;
+
+	/* read out the first block, get the config data information */
+#ifdef CONFIG_BLK
+	n = blk_dread(mmc_get_blk_desc(mmc), 0, 1, tmp_buf);
+#else
+	n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf);
+#endif
+	if (!n) {
+		free(tmp_buf);
+		return 1;
+	}
+
+	/* Get the Source Address, from offset 0x50 */
+	code_offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR);
+
+	/* Get the code size from offset 0x48 */
+	code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
+
+#ifdef CONFIG_ESDHC_HC_BLK_ADDR
+	/*
+	 * On soc BSC9131, BSC9132:
+	 * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
+	 * code length of these soc specify the memory address in block address
+	 * format. Block length is fixed to 512 bytes as per the SD High
+	 * Capacity specification.
+	 */
+	u64 tmp;
+
+	if (mmc->high_capacity) {
+		tmp = (u64)code_offset * blklen;
+		tmp += code_len * blklen;
+	} else
+		tmp = code_offset + code_len;
+
+	if ((tmp + CONFIG_ENV_SIZE > mmc->capacity) ||
+			(tmp > 0xFFFFFFFFU))
+		*env_addr = ESDHC_DEFAULT_ENVADDR;
+	else
+		*env_addr = tmp;
+
+	free(tmp_buf);
+
+	return 0;
+#endif
+
+	*env_addr = code_offset + code_len;
+
+	free(tmp_buf);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/common/sgmii_riser.c b/roms/u-boot/board/freescale/common/sgmii_riser.c
new file mode 100644
index 000000000..231579301
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/sgmii_riser.c
@@ -0,0 +1,130 @@
+/*
+ * Freescale SGMII Riser Card
+ *
+ * This driver supports the SGMII Riser card found on the
+ * "DS" style of development board from Freescale.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <log.h>
+#include <net.h>
+#include <linux/libfdt.h>
+#include <tsec.h>
+#include <fdt_support.h>
+
+void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num)
+{
+	int i;
+
+	for (i = 0; i < num; i++)
+		if (tsec_info[i].flags & TSEC_SGMII)
+			tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET;
+}
+
+void fsl_sgmii_riser_fdt_fixup(void *fdt)
+{
+	struct eth_device *dev;
+	int node;
+	int mdio_node;
+	int i = -1;
+	int etsec_num = 0;
+
+	node = fdt_path_offset(fdt, "/aliases");
+	if (node < 0)
+		return;
+
+	while ((dev = eth_get_dev_by_index(++i)) != NULL) {
+		struct tsec_private *priv;
+		int phy_node;
+		int enet_node;
+		uint32_t ph;
+		char sgmii_phy[16];
+		char enet[16];
+		const u32 *phyh;
+		const char *model;
+		const char *path;
+
+		if (!strstr(dev->name, "eTSEC"))
+			continue;
+
+		priv = dev->priv;
+		if (!(priv->flags & TSEC_SGMII)) {
+			etsec_num++;
+			continue;
+		}
+
+		mdio_node = fdt_node_offset_by_compatible(fdt, -1,
+				"fsl,gianfar-mdio");
+		if (mdio_node < 0)
+			return;
+
+		sprintf(sgmii_phy, "sgmii-phy@%d", etsec_num);
+		phy_node = fdt_subnode_offset(fdt, mdio_node, sgmii_phy);
+		if (phy_node > 0) {
+			fdt_increase_size(fdt, 32);
+			ph = fdt_create_phandle(fdt, phy_node);
+			if (!ph)
+				continue;
+		}
+
+		sprintf(enet, "ethernet%d", etsec_num++);
+		path = fdt_getprop(fdt, node, enet, NULL);
+		if (!path) {
+			debug("No alias for %s\n", enet);
+			continue;
+		}
+
+		enet_node = fdt_path_offset(fdt, path);
+		if (enet_node < 0)
+			continue;
+
+		model = fdt_getprop(fdt, enet_node, "model", NULL);
+
+		/*
+		 * We only want to do this to eTSECs.  On some platforms
+		 * there are more than one type of gianfar-style ethernet
+		 * controller, and as we are creating an implicit connection
+		 * between ethernet nodes and eTSEC devices, it is best to
+		 * make the connection use as much explicit information
+		 * as exists.
+		 */
+		if (!strstr(model, "TSEC"))
+			continue;
+
+		if (phy_node < 0) {
+			/*
+			 * This part is only for old device tree without
+			 * sgmii_phy nodes. It's kept just for compatible
+			 * reason. Soon to be deprecated if all device tree
+			 * get updated.
+			 */
+			phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL);
+			if (!phyh)
+				continue;
+
+			phy_node = fdt_node_offset_by_phandle(fdt,
+					fdt32_to_cpu(*phyh));
+
+			priv = dev->priv;
+
+			if (priv->flags & TSEC_SGMII)
+				fdt_setprop_cell(fdt, phy_node, "reg",
+						priv->phyaddr);
+		} else {
+			fdt_setprop(fdt, enet_node, "phy-handle", &ph,
+					sizeof(ph));
+			fdt_setprop_string(fdt, enet_node,
+					"phy-connection-type",
+					phy_string_for_interface(
+						PHY_INTERFACE_MODE_SGMII));
+		}
+	}
+}
diff --git a/roms/u-boot/board/freescale/common/sgmii_riser.h b/roms/u-boot/board/freescale/common/sgmii_riser.h
new file mode 100644
index 000000000..e1fcc858f
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/sgmii_riser.h
@@ -0,0 +1,16 @@
+/*
+ * Freescale SGMII Riser Card
+ *
+ * This driver supports the SGMII Riser card found on the
+ * "DS" style of development board from Freescale.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ */
+
+void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num);
+void fsl_sgmii_riser_fdt_fixup(void *fdt);
diff --git a/roms/u-boot/board/freescale/common/sleep.h b/roms/u-boot/board/freescale/common/sleep.h
new file mode 100644
index 000000000..1450baa07
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/sleep.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __SLEEP_H
+#define __SLEEP_H
+
+#define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
+#define DDR_BUFF_LEN			128
+
+/* determine if it is a wakeup from deep sleep */
+bool is_warm_boot(void);
+
+/* disable console output */
+void fsl_dp_disable_console(void);
+
+/* clean up everything and jump to kernel */
+int fsl_dp_resume(void);
+#endif
diff --git a/roms/u-boot/board/freescale/common/spl.h b/roms/u-boot/board/freescale/common/spl.h
new file mode 100644
index 000000000..d4689d3d7
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/spl.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Google, Inc
+ */
+
+#ifndef __FREESCALE_BOARD_SPL_H
+#define __FREESCALE_BOARD_SPL_H
+
+void fsl_spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
+void fsl_spi_boot(void) __noreturn;
+
+#endif
diff --git a/roms/u-boot/board/freescale/common/sys_eeprom.c b/roms/u-boot/board/freescale/common/sys_eeprom.c
new file mode 100644
index 000000000..be0fda063
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/sys_eeprom.c
@@ -0,0 +1,625 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ * Haiying Wang (haiying.wang@freescale.com)
+ * Timur Tabi (timur@freescale.com)
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <linux/ctype.h>
+#include <linux/delay.h>
+#include <u-boot/crc.h>
+
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
+#include "../common/eeprom.h"
+#define MAX_NUM_PORTS	8
+#endif
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+/* some boards with non-256-bytes EEPROM have special define */
+/* for MAX_NUM_PORTS in board-specific file */
+#ifndef MAX_NUM_PORTS
+#define MAX_NUM_PORTS	16
+#endif
+#define NXID_VERSION	1
+#endif
+
+/**
+ * static eeprom: EEPROM layout for CCID or NXID formats
+ *
+ * See application note AN3638 for details.
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
+	u8 id[4];         /* 0x00 - 0x03 EEPROM Tag 'CCID' */
+	u8 major;         /* 0x04        Board revision, major */
+	u8 minor;         /* 0x05        Board revision, minor */
+	u8 sn[10];        /* 0x06 - 0x0F Serial Number*/
+	u8 errata[2];     /* 0x10 - 0x11 Errata Level */
+	u8 date[6];       /* 0x12 - 0x17 Build Date */
+	u8 res_0[40];     /* 0x18 - 0x3f Reserved */
+	u8 mac_count;     /* 0x40        Number of MAC addresses */
+	u8 mac_flag;      /* 0x41        MAC table flags */
+	u8 mac[MAX_NUM_PORTS][6];     /* 0x42 - 0x71 MAC addresses */
+	u32 crc;          /* 0x72        CRC32 checksum */
+#endif
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	u8 id[4];         /* 0x00 - 0x03 EEPROM Tag 'NXID' */
+	u8 sn[12];        /* 0x04 - 0x0F Serial Number */
+	u8 errata[5];     /* 0x10 - 0x14 Errata Level */
+	u8 date[6];       /* 0x15 - 0x1a Build Date */
+	u8 res_0;         /* 0x1b        Reserved */
+	u32 version;      /* 0x1c - 0x1f NXID Version */
+	u8 tempcal[8];    /* 0x20 - 0x27 Temperature Calibration Factors */
+	u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */
+	u8 tempcalflags;  /* 0x2a        Temperature Calibration Flags */
+	u8 res_1[21];     /* 0x2b - 0x3f Reserved */
+	u8 mac_count;     /* 0x40        Number of MAC addresses */
+	u8 mac_flag;      /* 0x41        MAC table flags */
+	u8 mac[MAX_NUM_PORTS][6];     /* 0x42 - 0xa1 MAC addresses */
+	u8 res_2[90];     /* 0xa2 - 0xfb Reserved */	
+	u32 crc;          /* 0xfc - 0xff CRC32 checksum */
+#endif
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read = 0;
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+/* Is this a valid NXID EEPROM? */
+#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \
+		  (e.id[2] == 'I') || (e.id[3] == 'D'))
+#endif
+
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
+/* Is this a valid CCID EEPROM? */
+#define is_valid ((e.id[0] == 'C') || (e.id[1] == 'C') || \
+		  (e.id[2] == 'I') || (e.id[3] == 'D'))
+#endif
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+	int i;
+	unsigned int crc;
+
+	/* EEPROM tag ID, either CCID or NXID */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
+	       be32_to_cpu(e.version));
+#else
+	printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
+#endif
+
+	/* Serial number */
+	printf("SN: %s\n", e.sn);
+
+	/* Errata level. */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	printf("Errata: %s\n", e.errata);
+#else
+	printf("Errata: %c%c\n",
+		e.errata[0] ? e.errata[0] : '.',
+		e.errata[1] ? e.errata[1] : '.');
+#endif
+
+	/* Build date, BCD date values, as YYMMDDhhmmss */
+	printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+		e.date[0], e.date[1], e.date[2],
+		e.date[3] & 0x7F, e.date[4], e.date[5],
+		e.date[3] & 0x80 ? "PM" : "");
+
+	/* Show MAC addresses  */
+	for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
+
+		u8 *p = e.mac[i];
+
+		printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
+			p[0], p[1], p[2], p[3],	p[4], p[5]);
+	}
+
+	crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+	if (crc == be32_to_cpu(e.crc))
+		printf("CRC: %08x\n", be32_to_cpu(e.crc));
+	else
+		printf("CRC: %08x (should be %08x)\n",
+			be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+	printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+	for (i = 0; i < sizeof(e); i++) {
+		if ((i % 16) == 0)
+			printf("%02X: ", i);
+		printf("%02X ", ((u8 *)&e)[i]);
+		if (((i % 16) == 15) || (i == sizeof(e) - 1))
+			printf("\n");
+	}
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+	int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	unsigned int bus;
+#endif
+#endif
+
+	if (has_been_read)
+		return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+#endif
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+		       CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+		       (void *)&e, sizeof(e));
+#else
+	struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+				      CONFIG_SYS_I2C_EEPROM_ADDR,
+				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
+#else
+	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
+#endif
+	if (!ret)
+		ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e));
+#endif
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_set_bus_num(bus);
+#endif
+#endif
+
+#ifdef DEBUG
+	show_eeprom();
+#endif
+
+	has_been_read = (ret == 0) ? 1 : 0;
+
+	return ret;
+}
+
+/**
+ *  update_crc - update the CRC
+ *
+ *  This function should be called after each update to the EEPROM structure,
+ *  to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+	u32 crc;
+
+	crc = crc32(0, (void *)&e, sizeof(e) - 4);
+	e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+	int ret = 0;
+	int i;
+	void *p;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	unsigned int bus;
+#endif
+#endif
+
+	/* Set the reserved values to 0xFF   */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	e.res_0 = 0xFF;
+	memset(e.res_1, 0xFF, sizeof(e.res_1));
+#else
+	memset(e.res_0, 0xFF, sizeof(e.res_0));
+#endif
+	update_crc();
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+#endif
+
+	/*
+	 * The AT24C02 datasheet says that data can only be written in page
+	 * mode, which means 8 bytes at a time, and it takes up to 5ms to
+	 * complete a given write.
+	 */
+	for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
+#if !CONFIG_IS_ENABLED(DM_I2C)
+		ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i,
+				CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+				p, min((int)(sizeof(e) - i), 8));
+#else
+		struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+		ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+					      CONFIG_SYS_I2C_EEPROM_ADDR,
+					      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+					      &dev);
+#else
+		ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+					      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+					      &dev);
+#endif
+		if (!ret)
+			ret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i),
+							  8));
+#endif
+		if (ret)
+			break;
+		udelay(5000);	/* 5ms write cycle timing */
+	}
+
+	if (!ret) {
+		/* Verify the write by reading back the EEPROM and comparing */
+		struct eeprom e2;
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+		ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+			       CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+			       (void *)&e2, sizeof(e2));
+#else
+		struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+		ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+					      CONFIG_SYS_I2C_EEPROM_ADDR,
+					      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+					      &dev);
+#else
+		ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+					      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+					      &dev);
+#endif
+		if (!ret)
+			ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2));
+#endif
+		if (!ret && memcmp(&e, &e2, sizeof(e)))
+			ret = -1;
+	}
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	i2c_set_bus_num(bus);
+#endif
+#endif
+
+	if (ret) {
+		printf("Programming failed.\n");
+		has_been_read = 0;
+		return -1;
+	}
+
+	printf("Programming passed.\n");
+	return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+	if ((p >= '0') && (p <= '9'))
+		return p - '0';
+
+	if ((p >= 'A') && (p <= 'F'))
+		return (p - 'A') + 10;
+
+	if ((p >= 'a') && (p <= 'f'))
+		return (p - 'a') + 10;
+
+	return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+	unsigned int i;
+
+	if (strlen(string) != 12) {
+		printf("Usage: mac date YYMMDDhhmmss\n");
+		return;
+	}
+
+	for (i = 0; i < 6; i++)
+		e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+	update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in one of the MAC address fields of the EEPROM local copy.
+ */
+static void set_mac_address(unsigned int index, const char *string)
+{
+	char *p = (char *) string;
+	unsigned int i;
+
+	if ((index >= MAX_NUM_PORTS) || !string) {
+		printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
+		return;
+	}
+
+	for (i = 0; *p && (i < 6); i++) {
+		e.mac[index][i] = simple_strtoul(p, &p, 16);
+		if (*p == ':')
+			p++;
+	}
+
+	update_crc();
+}
+
+int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	char cmd;
+
+	if (argc == 1) {
+		show_eeprom();
+		return 0;
+	}
+
+	cmd = argv[1][0];
+
+	if (cmd == 'r') {
+		read_eeprom();
+		return 0;
+	}
+
+	if (cmd == 'i') {
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+		memcpy(e.id, "NXID", sizeof(e.id));
+		e.version = cpu_to_be32(NXID_VERSION);
+#else
+		memcpy(e.id, "CCID", sizeof(e.id));
+#endif
+		update_crc();
+		return 0;
+	}
+
+	if (!is_valid) {
+		printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n");
+		return 0;
+	}
+
+	if (argc == 2) {
+		switch (cmd) {
+		case 's':	/* save */
+			prog_eeprom();
+			break;
+		default:
+			return cmd_usage(cmdtp);
+		}
+
+		return 0;
+	}
+
+	/* We know we have at least one parameter  */
+
+	switch (cmd) {
+	case 'n':	/* serial number */
+		memset(e.sn, 0, sizeof(e.sn));
+		strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+		update_crc();
+		break;
+	case 'e':	/* errata */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+		memset(e.errata, 0, 5);
+		strncpy((char *)e.errata, argv[2], 4);
+#else
+		e.errata[0] = argv[2][0];
+		e.errata[1] = argv[2][1];
+#endif
+		update_crc();
+		break;
+	case 'd':	/* date BCD format YYMMDDhhmmss */
+		set_date(argv[2]);
+		break;
+	case 'p':	/* MAC table size */
+		e.mac_count = simple_strtoul(argv[2], NULL, 16);
+		update_crc();
+		break;
+	case '0' ... '9':	/* "mac 0" through "mac 22" */
+		set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]);
+		break;
+	case 'h':	/* help */
+	default:
+		return cmd_usage(cmdtp);
+	}
+
+	return 0;
+}
+
+/**
+ * mac_read_from_eeprom - read the MAC addresses from EEPROM
+ *
+ * This function reads the MAC addresses from EEPROM and sets the
+ * appropriate environment variables for each one read.
+ *
+ * The environment variables are only set if they haven't been set already.
+ * This ensures that any user-saved variables are never overwritten.
+ *
+ * This function must be called after relocation.
+ *
+ * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0
+ * format.  In a v0 EEPROM, there are only eight MAC addresses and the CRC is
+ * located at a different offset.
+ */
+int mac_read_from_eeprom(void)
+{
+	unsigned int i;
+	u32 crc, crc_offset = offsetof(struct eeprom, crc);
+	u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+	puts("EEPROM: ");
+
+	if (read_eeprom()) {
+		printf("Read failed.\n");
+		return 0;
+	}
+
+	if (!is_valid) {
+		printf("Invalid ID (%02x %02x %02x %02x)\n",
+		       e.id[0], e.id[1], e.id[2], e.id[3]);
+		return 0;
+	}
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	/*
+	 * If we've read an NXID v0 EEPROM, then we need to set the CRC offset
+	 * to where it is in v0.
+	 */
+	if (e.version == 0)
+		crc_offset = 0x72;
+#endif
+
+	crc = crc32(0, (void *)&e, crc_offset);
+	crcp = (void *)&e + crc_offset;
+	if (crc != be32_to_cpu(*crcp)) {
+		printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc));
+		return 0;
+	}
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	/*
+	 * MAC address #9 in v1 occupies the same position as the CRC in v0.
+	 * Erase it so that it's not mistaken for a MAC address.  We'll
+	 * update the CRC later.
+	 */
+	if (e.version == 0)
+		memset(e.mac[8], 0xff, 6);
+#endif
+
+	for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
+		if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
+		    memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+			char ethaddr[18];
+			char enetvar[9];
+
+			sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+				e.mac[i][0],
+				e.mac[i][1],
+				e.mac[i][2],
+				e.mac[i][3],
+				e.mac[i][4],
+				e.mac[i][5]);
+			sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i);
+			/* Only initialize environment variables that are blank
+			 * (i.e. have not yet been set)
+			 */
+			if (!env_get(enetvar))
+				env_set(enetvar, ethaddr);
+		}
+	}
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
+	       be32_to_cpu(e.version));
+#else
+	printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
+#endif
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+	/*
+	 * Now we need to upconvert the data into v1 format.  We do this last so
+	 * that at boot time, U-Boot will still say "NXID v0".
+	 */
+	if (e.version == 0) {
+		e.version = cpu_to_be32(NXID_VERSION);
+		update_crc();
+	}
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
+
+/**
+ * get_cpu_board_revision - get the CPU board revision on 85xx boards
+ *
+ * Read the EEPROM to determine the board revision.
+ *
+ * This function is called before relocation, so we need to read a private
+ * copy of the EEPROM into a local variable on the stack.
+ *
+ * Also, we assume that CONFIG_SYS_EEPROM_BUS_NUM == CONFIG_SYS_SPD_BUS_NUM.  The global
+ * variable i2c_bus_num must be compile-time initialized to CONFIG_SYS_SPD_BUS_NUM,
+ * so that the SPD code will work.  This means that all pre-relocation I2C
+ * operations can only occur on the CONFIG_SYS_SPD_BUS_NUM bus.  So if
+ * CONFIG_SYS_EEPROM_BUS_NUM != CONFIG_SYS_SPD_BUS_NUM, then we can't read the EEPROM when
+ * this function is called.  Oh well.
+ */
+unsigned int get_cpu_board_revision(void)
+{
+	struct board_eeprom {
+		u32 id;           /* 0x00 - 0x03 EEPROM Tag 'CCID' */
+		u8 major;         /* 0x04        Board revision, major */
+		u8 minor;         /* 0x05        Board revision, minor */
+	} be;
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+		(void *)&be, sizeof(be));
+#else
+	struct udevice *dev;
+	int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+				      CONFIG_SYS_I2C_EEPROM_ADDR,
+				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+				      &dev);
+#else
+	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+				      &dev);
+#endif
+	if (!ret)
+		dm_i2c_read(dev, 0, (void *)&be, sizeof(be));
+#endif
+
+	if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
+		return MPC85XX_CPU_BOARD_REV(0, 0);
+
+	if ((be.major == 0xff) && (be.minor == 0xff))
+		return MPC85XX_CPU_BOARD_REV(0, 0);
+
+	return MPC85XX_CPU_BOARD_REV(be.major, be.minor);
+}
+#endif
diff --git a/roms/u-boot/board/freescale/common/via.h b/roms/u-boot/board/freescale/common/via.h
new file mode 100644
index 000000000..77cfacc52
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/via.h
@@ -0,0 +1,18 @@
+#ifndef _MPC85xx_VIA_H
+void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+#endif /* _MPC85xx_VIA_H */
diff --git a/roms/u-boot/board/freescale/common/vid.c b/roms/u-boot/board/freescale/common/vid.c
new file mode 100644
index 000000000..13ef101e7
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/vid.c
@@ -0,0 +1,830 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020-21 NXP
+ * Copyright 2020 Stephen Carlson <stcarlso@linux.microsoft.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <i2c.h>
+#include <irq_func.h>
+#include <log.h>
+#include <asm/io.h>
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/immap_lsch2.h>
+#elif defined(CONFIG_FSL_LSCH3)
+#include <asm/arch/immap_lsch3.h>
+#else
+#include <asm/immap_85xx.h>
+#endif
+#include <linux/delay.h>
+#include "vid.h"
+
+/* Voltages are generally handled in mV to keep them as integers */
+#define MV_PER_V 1000
+
+/*
+ * Select the channel on the I2C mux (on some NXP boards) that contains
+ * the voltage regulator to use for VID. Return 0 for success or nonzero
+ * for failure.
+ */
+int __weak i2c_multiplexer_select_vid_channel(u8 channel)
+{
+	return 0;
+}
+
+/*
+ * Compensate for a board specific voltage drop between regulator and SoC.
+ * Returns the voltage offset in mV.
+ */
+int __weak board_vdd_drop_compensation(void)
+{
+	return 0;
+}
+
+/*
+ * Performs any board specific adjustments after the VID voltage has been
+ * set. Return 0 for success or nonzero for failure.
+ */
+int __weak board_adjust_vdd(int vdd)
+{
+	return 0;
+}
+
+/*
+ * Processor specific method of converting the fuse value read from VID
+ * registers into the core voltage to supply. Return the voltage in mV.
+ */
+u16 __weak soc_get_fuse_vid(int vid_index)
+{
+	/* Default VDD for Layerscape Chassis 1 devices */
+	static const u16 vdd[32] = {
+		0,      /* unused */
+		9875,   /* 0.9875V */
+		9750,
+		9625,
+		9500,
+		9375,
+		9250,
+		9125,
+		9000,
+		8875,
+		8750,
+		8625,
+		8500,
+		8375,
+		8250,
+		8125,
+		10000,  /* 1.0000V */
+		10125,
+		10250,
+		10375,
+		10500,
+		10625,
+		10750,
+		10875,
+		11000,
+		0,      /* reserved */
+	};
+	return vdd[vid_index];
+}
+
+#ifndef I2C_VOL_MONITOR_ADDR
+#define I2C_VOL_MONITOR_ADDR                    0
+#endif
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+#define DEVICE_HANDLE_T struct udevice *
+
+#ifndef I2C_VOL_MONITOR_BUS
+#define I2C_VOL_MONITOR_BUS			0
+#endif
+
+/* If DM is in use, retrieve the udevice chip for the specified bus number */
+static int vid_get_device(int address, DEVICE_HANDLE_T *dev)
+{
+	int ret = i2c_get_chip_for_busnum(I2C_VOL_MONITOR_BUS, address, 1, dev);
+
+	if (ret)
+		printf("VID: Bus %d has no device with address 0x%02X\n",
+		       I2C_VOL_MONITOR_BUS, address);
+	return ret;
+}
+
+#define I2C_READ(dev, register, data, length) \
+	dm_i2c_read(dev, register, data, length)
+#define I2C_WRITE(dev, register, data, length) \
+	dm_i2c_write(dev, register, data, length)
+#else
+#define DEVICE_HANDLE_T int
+
+/* If DM is not in use, I2C addresses are passed directly */
+static int vid_get_device(int address, DEVICE_HANDLE_T *dev)
+{
+	*dev = address;
+	return 0;
+}
+
+#define I2C_READ(dev, register, data, length) \
+	i2c_read(dev, register, 1, data, length)
+#define I2C_WRITE(dev, register, data, length) \
+	i2c_write(dev, register, 1, data, length)
+#endif
+
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+	defined(CONFIG_VOL_MONITOR_IR36021_READ)
+/*
+ * Get the i2c address configuration for the IR regulator chip
+ *
+ * There are some variance in the RDB HW regarding the I2C address configuration
+ * for the IR regulator chip, which is likely a problem of external resistor
+ * accuracy. So we just check each address in a hopefully non-intrusive mode
+ * and use the first one that seems to work
+ *
+ * The IR chip can show up under the following addresses:
+ * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
+ * 0x09 (Verified on T1040RDB-PA)
+ * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB)
+ */
+static int find_ir_chip_on_i2c(void)
+{
+	int i2caddress, ret, i;
+	u8 mfrID;
+	const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
+	DEVICE_HANDLE_T dev;
+
+	/* Check all the address */
+	for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
+		i2caddress = ir_i2c_addr[i];
+		ret = vid_get_device(i2caddress, &dev);
+		if (!ret) {
+			ret = I2C_READ(dev, IR36021_MFR_ID_OFFSET,
+				       (void *)&mfrID, sizeof(mfrID));
+			/* If manufacturer ID matches the IR36021 */
+			if (!ret && mfrID == IR36021_MFR_ID)
+				return i2caddress;
+		}
+	}
+	return -1;
+}
+#endif
+
+/* Maximum loop count waiting for new voltage to take effect */
+#define MAX_LOOP_WAIT_NEW_VOL		100
+/* Maximum loop count waiting for the voltage to be stable */
+#define MAX_LOOP_WAIT_VOL_STABLE	100
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for WAIT_FOR_ADC before
+ * another reading
+ */
+#define NUM_READINGS    4       /* prefer to be power of 2 for efficiency */
+
+/* If an INA220 chip is available, we can use it to read back the voltage
+ * as it may have a higher accuracy than the IR chip for the same purpose
+ */
+#ifdef CONFIG_VOL_MONITOR_INA220
+#define WAIT_FOR_ADC	532	/* wait for 532 microseconds for ADC */
+#define ADC_MIN_ACCURACY	4
+#else
+#define WAIT_FOR_ADC	138	/* wait for 138 microseconds for ADC */
+#define ADC_MIN_ACCURACY	4
+#endif
+
+#ifdef CONFIG_VOL_MONITOR_INA220
+static int read_voltage_from_INA220(int i2caddress)
+{
+	int i, ret, voltage_read = 0;
+	u16 vol_mon;
+	u8 buf[2];
+	DEVICE_HANDLE_T dev;
+
+	/* Open device handle */
+	ret = vid_get_device(i2caddress, &dev);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < NUM_READINGS; i++) {
+		ret = I2C_READ(dev, I2C_VOL_MONITOR_BUS_V_OFFSET,
+			       (void *)&buf[0], sizeof(buf));
+		if (ret) {
+			printf("VID: failed to read core voltage\n");
+			return ret;
+		}
+
+		vol_mon = (buf[0] << 8) | buf[1];
+		if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+			printf("VID: Core voltage sensor error\n");
+			return -1;
+		}
+
+		debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+		/* LSB = 4mv */
+		voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+		udelay(WAIT_FOR_ADC);
+	}
+
+	/* calculate the average */
+	voltage_read /= NUM_READINGS;
+
+	return voltage_read;
+}
+#endif
+
+#ifdef CONFIG_VOL_MONITOR_IR36021_READ
+/* read voltage from IR */
+static int read_voltage_from_IR(int i2caddress)
+{
+	int i, ret, voltage_read = 0;
+	u16 vol_mon;
+	u8 buf;
+	DEVICE_HANDLE_T dev;
+
+	/* Open device handle */
+	ret = vid_get_device(i2caddress, &dev);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < NUM_READINGS; i++) {
+		ret = I2C_READ(dev, IR36021_LOOP1_VOUT_OFFSET, (void *)&buf,
+			       sizeof(buf));
+		if (ret) {
+			printf("VID: failed to read core voltage\n");
+			return ret;
+		}
+		vol_mon = buf;
+		if (!vol_mon) {
+			printf("VID: Core voltage sensor error\n");
+			return -1;
+		}
+		debug("VID: bus voltage reads 0x%02x\n", vol_mon);
+		/* Resolution is 1/128V. We scale up here to get 1/128mV
+		 * and divide at the end
+		 */
+		voltage_read += vol_mon * MV_PER_V;
+		udelay(WAIT_FOR_ADC);
+	}
+	/* Scale down to the real mV as IR resolution is 1/128V, rounding up */
+	voltage_read = DIV_ROUND_UP(voltage_read, 128);
+
+	/* calculate the average */
+	voltage_read /= NUM_READINGS;
+
+	/* Compensate for a board specific voltage drop between regulator and
+	 * SoC before converting into an IR VID value
+	 */
+	voltage_read -= board_vdd_drop_compensation();
+
+	return voltage_read;
+}
+#endif
+
+#if defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \
+	defined(CONFIG_VOL_MONITOR_LTC3882_READ) || \
+	defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \
+	defined(CONFIG_VOL_MONITOR_LTC3882_SET)
+
+/*
+ * The message displayed if the VOUT exponent causes a resolution
+ * worse than 1.0 V (if exponent is >= 0).
+ */
+#define VOUT_WARNING "VID: VOUT_MODE exponent has resolution worse than 1 V!\n"
+
+/* Checks the PMBus voltage monitor for the format used for voltage values */
+static int get_pmbus_multiplier(DEVICE_HANDLE_T dev)
+{
+	u8 mode;
+	int exponent, multiplier, ret;
+
+	ret = I2C_READ(dev, PMBUS_CMD_VOUT_MODE, &mode, sizeof(mode));
+	if (ret) {
+		printf("VID: unable to determine voltage multiplier\n");
+		return 1;
+	}
+
+	/* Upper 3 bits is mode, lower 5 bits is exponent */
+	exponent = (int)mode & 0x1F;
+	mode >>= 5;
+	switch (mode) {
+	case 0:
+		/* Linear, 5 bit twos component exponent */
+		if (exponent & 0x10) {
+			multiplier = 1 << (16 - (exponent & 0xF));
+		} else {
+			/* If exponent is >= 0, then resolution is 1 V! */
+			printf(VOUT_WARNING);
+			multiplier = 1;
+		}
+		break;
+	case 1:
+		/* VID code identifier */
+		printf("VID: custom VID codes are not supported\n");
+		multiplier = MV_PER_V;
+		break;
+	default:
+		/* Direct, in mV */
+		multiplier = MV_PER_V;
+		break;
+	}
+
+	debug("VID: calculated multiplier is %d\n", multiplier);
+	return multiplier;
+}
+#endif
+
+#if defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \
+	defined(CONFIG_VOL_MONITOR_LTC3882_READ)
+static int read_voltage_from_pmbus(int i2caddress)
+{
+	int ret, multiplier, vout;
+	u8 channel = PWM_CHANNEL0;
+	u16 vcode;
+	DEVICE_HANDLE_T dev;
+
+	/* Open device handle */
+	ret = vid_get_device(i2caddress, &dev);
+	if (ret)
+		return ret;
+
+	/* Select the right page */
+	ret = I2C_WRITE(dev, PMBUS_CMD_PAGE, &channel, sizeof(channel));
+	if (ret) {
+		printf("VID: failed to select VDD page %d\n", channel);
+		return ret;
+	}
+
+	/* VOUT is little endian */
+	ret = I2C_READ(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, sizeof(vcode));
+	if (ret) {
+		printf("VID: failed to read core voltage\n");
+		return ret;
+	}
+
+	/* Scale down to the real mV */
+	multiplier = get_pmbus_multiplier(dev);
+	vout = (int)vcode;
+	/* Multiplier 1000 (direct mode) requires no change to convert */
+	if (multiplier != MV_PER_V)
+		vout = DIV_ROUND_UP(vout * MV_PER_V, multiplier);
+	return vout - board_vdd_drop_compensation();
+}
+#endif
+
+static int read_voltage(int i2caddress)
+{
+	int voltage_read;
+#ifdef CONFIG_VOL_MONITOR_INA220
+	voltage_read = read_voltage_from_INA220(I2C_VOL_MONITOR_ADDR);
+#elif defined CONFIG_VOL_MONITOR_IR36021_READ
+	voltage_read = read_voltage_from_IR(i2caddress);
+#elif defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \
+	  defined(CONFIG_VOL_MONITOR_LTC3882_READ)
+	voltage_read = read_voltage_from_pmbus(i2caddress);
+#else
+	voltage_read = -1;
+#endif
+	return voltage_read;
+}
+
+#ifdef CONFIG_VOL_MONITOR_IR36021_SET
+/*
+ * We need to calculate how long before the voltage stops to drop
+ * or increase. It returns with the loop count. Each loop takes
+ * several readings (WAIT_FOR_ADC)
+ */
+static int wait_for_new_voltage(int vdd, int i2caddress)
+{
+	int timeout, vdd_current;
+
+	vdd_current = read_voltage(i2caddress);
+	/* wait until voltage starts to reach the target. Voltage slew
+	 * rates by typical regulators will always lead to stable readings
+	 * within each fairly long ADC interval in comparison to the
+	 * intended voltage delta change until the target voltage is
+	 * reached. The fairly small voltage delta change to any target
+	 * VID voltage also means that this function will always complete
+	 * within few iterations. If the timeout was ever reached, it would
+	 * point to a serious failure in the regulator system.
+	 */
+	for (timeout = 0;
+	     abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) &&
+	     timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) {
+		vdd_current = read_voltage(i2caddress);
+	}
+	if (timeout >= MAX_LOOP_WAIT_NEW_VOL) {
+		printf("VID: Voltage adjustment timeout\n");
+		return -1;
+	}
+	return timeout;
+}
+
+/*
+ * Blocks and reads the VID voltage until it stabilizes, or the
+ * timeout expires
+ */
+static int wait_for_voltage_stable(int i2caddress)
+{
+	int timeout, vdd_current, vdd;
+
+	vdd = read_voltage(i2caddress);
+	udelay(NUM_READINGS * WAIT_FOR_ADC);
+
+	vdd_current = read_voltage(i2caddress);
+	/*
+	 * The maximum timeout is
+	 * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC
+	 */
+	for (timeout = MAX_LOOP_WAIT_VOL_STABLE;
+	     abs(vdd - vdd_current) > ADC_MIN_ACCURACY &&
+	     timeout > 0; timeout--) {
+		vdd = vdd_current;
+		udelay(NUM_READINGS * WAIT_FOR_ADC);
+		vdd_current = read_voltage(i2caddress);
+	}
+	if (timeout == 0)
+		return -1;
+	return vdd_current;
+}
+
+/* Sets the VID voltage using the IR36021 */
+static int set_voltage_to_IR(int i2caddress, int vdd)
+{
+	int wait, vdd_last;
+	int ret;
+	u8 vid;
+	DEVICE_HANDLE_T dev;
+
+	/* Open device handle */
+	ret = vid_get_device(i2caddress, &dev);
+	if (ret)
+		return ret;
+
+	/* Compensate for a board specific voltage drop between regulator and
+	 * SoC before converting into an IR VID value
+	 */
+	vdd += board_vdd_drop_compensation();
+#ifdef CONFIG_FSL_LSCH2
+	vid = DIV_ROUND_UP(vdd - 265, 5);
+#else
+	vid = DIV_ROUND_UP(vdd - 245, 5);
+#endif
+
+	ret = I2C_WRITE(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, (void *)&vid,
+			sizeof(vid));
+	if (ret) {
+		printf("VID: failed to write new voltage\n");
+		return -1;
+	}
+	wait = wait_for_new_voltage(vdd, i2caddress);
+	if (wait < 0)
+		return -1;
+	debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
+
+	vdd_last = wait_for_voltage_stable(i2caddress);
+	if (vdd_last < 0)
+		return -1;
+	debug("VID: Current voltage is %d mV\n", vdd_last);
+	return vdd_last;
+}
+#endif
+
+#if defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \
+	defined(CONFIG_VOL_MONITOR_LTC3882_SET)
+static int set_voltage_to_pmbus(int i2caddress, int vdd)
+{
+	int ret, vdd_last, vdd_target = vdd;
+	int count = MAX_LOOP_WAIT_NEW_VOL, temp = 0, multiplier;
+	unsigned char value;
+
+	/* The data to be sent with the PMBus command PAGE_PLUS_WRITE */
+	u8 buffer[5] = { 0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 0, 0 };
+	DEVICE_HANDLE_T dev;
+
+	/* Open device handle */
+	ret = vid_get_device(i2caddress, &dev);
+	if (ret)
+		return ret;
+
+	/* Scale up to the proper value for the VOUT command, little endian */
+	multiplier = get_pmbus_multiplier(dev);
+	vdd += board_vdd_drop_compensation();
+	if (multiplier != MV_PER_V)
+		vdd = DIV_ROUND_UP(vdd * multiplier, MV_PER_V);
+	buffer[3] = vdd & 0xFF;
+	buffer[4] = (vdd & 0xFF00) >> 8;
+
+	/* Check write protect state */
+	ret = I2C_READ(dev, PMBUS_CMD_WRITE_PROTECT, (void *)&value,
+		       sizeof(value));
+	if (ret)
+		goto exit;
+
+	if (value != EN_WRITE_ALL_CMD) {
+		value = EN_WRITE_ALL_CMD;
+		ret = I2C_WRITE(dev, PMBUS_CMD_WRITE_PROTECT,
+				(void *)&value, sizeof(value));
+		if (ret)
+			goto exit;
+	}
+
+	/* Write the desired voltage code to the regulator */
+	ret = I2C_WRITE(dev, PMBUS_CMD_PAGE_PLUS_WRITE, (void *)&buffer[0],
+			sizeof(buffer));
+	if (ret) {
+		printf("VID: I2C failed to write to the voltage regulator\n");
+		return -1;
+	}
+
+exit:
+	/* Wait for the voltage to get to the desired value */
+	do {
+		vdd_last = read_voltage_from_pmbus(i2caddress);
+		if (vdd_last < 0) {
+			printf("VID: Couldn't read sensor abort VID adjust\n");
+			return -1;
+		}
+		count--;
+		temp = vdd_last - vdd_target;
+	} while ((abs(temp) > 2)  && (count > 0));
+
+	return vdd_last;
+}
+#endif
+
+static int set_voltage(int i2caddress, int vdd)
+{
+	int vdd_last = -1;
+
+#ifdef CONFIG_VOL_MONITOR_IR36021_SET
+	vdd_last = set_voltage_to_IR(i2caddress, vdd);
+#elif defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \
+	  defined(CONFIG_VOL_MONITOR_LTC3882_SET)
+	vdd_last = set_voltage_to_pmbus(i2caddress, vdd);
+#else
+	#error Specific voltage monitor must be defined
+#endif
+	return vdd_last;
+}
+
+int adjust_vdd(ulong vdd_override)
+{
+	int re_enable = disable_interrupts();
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#else
+	ccsr_gur_t __iomem *gur =
+		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+	u8 vid;
+	u32 fusesr;
+	int vdd_current, vdd_last, vdd_target;
+	int ret, i2caddress = I2C_VOL_MONITOR_ADDR;
+	unsigned long vdd_string_override;
+	char *vdd_string;
+
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+	defined(CONFIG_VOL_MONITOR_IR36021_READ)
+	u8 buf;
+	DEVICE_HANDLE_T dev;
+#endif
+
+	/*
+	 * VID is used according to the table below
+	 *                ---------------------------------------
+	 *                |                DA_V                 |
+	 *                |-------------------------------------|
+	 *                | 5b00000 | 5b00001-5b11110 | 5b11111 |
+	 * ---------------+---------+-----------------+---------|
+	 * | D | 5b00000  | NO VID  | VID = DA_V      | NO VID  |
+	 * | A |----------+---------+-----------------+---------|
+	 * | _ | 5b00001  |VID =    | VID =           |VID =    |
+	 * | V |   ~      | DA_V_ALT|   DA_V_ALT      | DA_A_VLT|
+	 * | _ | 5b11110  |         |                 |         |
+	 * | A |----------+---------+-----------------+---------|
+	 * | L | 5b11111  | No VID  | VID = DA_V      | NO VID  |
+	 * | T |          |         |                 |         |
+	 * ------------------------------------------------------
+	 */
+#if defined(CONFIG_FSL_LSCH3)
+	fusesr = in_le32(&gur->dcfg_fusesr);
+	vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+	       FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+	if (vid == 0 || vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK) {
+		vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
+		       FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+	}
+#elif defined(CONFIG_FSL_LSCH2)
+	fusesr = in_be32(&gur->dcfg_fusesr);
+	vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
+	       FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
+	if (vid == 0 || vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK) {
+		vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
+		       FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
+	}
+#else
+	fusesr = in_be32(&gur->dcfg_fusesr);
+	vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+	       FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+	if (vid == 0 || vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK) {
+		vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+		       FSL_CORENET_DCFG_FUSESR_VID_MASK;
+	}
+#endif
+	vdd_target = soc_get_fuse_vid((int)vid);
+
+	ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+	if (ret) {
+		debug("VID: I2C failed to switch channel\n");
+		ret = -1;
+		goto exit;
+	}
+
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+	defined(CONFIG_VOL_MONITOR_IR36021_READ)
+	ret = find_ir_chip_on_i2c();
+	if (ret < 0) {
+		printf("VID: Could not find voltage regulator on I2C.\n");
+		ret = -1;
+		goto exit;
+	} else {
+		i2caddress = ret;
+		debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+	}
+
+	ret = vid_get_device(i2caddress, &dev);
+	if (ret)
+		return ret;
+
+	/* check IR chip work on Intel mode */
+	ret = I2C_READ(dev, IR36021_INTEL_MODE_OFFSET, (void *)&buf,
+		       sizeof(buf));
+	if (ret) {
+		printf("VID: failed to read IR chip mode.\n");
+		ret = -1;
+		goto exit;
+	}
+	if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
+		printf("VID: IR Chip is not used in Intel mode.\n");
+		ret = -1;
+		goto exit;
+	}
+#endif
+
+	/* check override variable for overriding VDD */
+	vdd_string = env_get(CONFIG_VID_FLS_ENV);
+	debug("VID: Initial VDD value is %d mV\n",
+	      DIV_ROUND_UP(vdd_target, 10));
+	if (vdd_override == 0 && vdd_string &&
+	    !strict_strtoul(vdd_string, 10, &vdd_string_override))
+		vdd_override = vdd_string_override;
+	if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
+		vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+		debug("VID: VDD override is %lu\n", vdd_override);
+	} else if (vdd_override != 0) {
+		printf("VID: Invalid VDD value.\n");
+	}
+	if (vdd_target == 0) {
+		debug("VID: VID not used\n");
+		ret = 0;
+		goto exit;
+	} else {
+		/* divide and round up by 10 to get a value in mV */
+		vdd_target = DIV_ROUND_UP(vdd_target, 10);
+		debug("VID: vid = %d mV\n", vdd_target);
+	}
+
+	/*
+	 * Read voltage monitor to check real voltage.
+	 */
+	vdd_last = read_voltage(i2caddress);
+	if (vdd_last < 0) {
+		printf("VID: Couldn't read sensor abort VID adjustment\n");
+		ret = -1;
+		goto exit;
+	}
+	vdd_current = vdd_last;
+	debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+
+#if defined(CONFIG_VOL_MONITOR_LTC3882_SET) || \
+	defined(CONFIG_VOL_MONITOR_ISL68233_SET)
+	/* Set the target voltage */
+	vdd_current = set_voltage(i2caddress, vdd_target);
+	vdd_last = vdd_current;
+#else
+	/*
+	  * Adjust voltage to at or one step above target.
+	  * As measurements are less precise than setting the values
+	  * we may run through dummy steps that cancel each other
+	  * when stepping up and then down.
+	  */
+	while (vdd_last > 0 &&
+	       vdd_last < vdd_target) {
+		vdd_current += IR_VDD_STEP_UP;
+		vdd_last = set_voltage(i2caddress, vdd_current);
+	}
+	while (vdd_last > 0 &&
+	       vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
+		vdd_current -= IR_VDD_STEP_DOWN;
+		vdd_last = set_voltage(i2caddress, vdd_current);
+	}
+#endif
+
+	/* Board specific adjustments */
+	if (board_adjust_vdd(vdd_target) < 0) {
+		ret = -1;
+		goto exit;
+	}
+
+	if (vdd_last > 0)
+		printf("VID: Core voltage after adjustment is at %d mV\n",
+		       vdd_last);
+	else
+		ret = -1;
+exit:
+	if (re_enable)
+		enable_interrupts();
+
+	i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+
+	return ret;
+}
+
+static int print_vdd(void)
+{
+	int vdd_last, ret, i2caddress = I2C_VOL_MONITOR_ADDR;
+
+	ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+	if (ret) {
+		debug("VID : I2c failed to switch channel\n");
+		return -1;
+	}
+#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
+	defined(CONFIG_VOL_MONITOR_IR36021_READ)
+	ret = find_ir_chip_on_i2c();
+	if (ret < 0) {
+		printf("VID: Could not find voltage regulator on I2C.\n");
+		goto exit;
+	} else {
+		i2caddress = ret;
+		debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+	}
+#endif
+
+	/*
+	 * Read voltage monitor to check real voltage.
+	 */
+	vdd_last = read_voltage(i2caddress);
+	if (vdd_last < 0) {
+		printf("VID: Couldn't read sensor abort VID adjustment\n");
+		goto exit;
+	}
+	printf("VID: Core voltage is at %d mV\n", vdd_last);
+exit:
+	i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+
+	return ret < 0 ? -1 : 0;
+
+}
+
+static int do_vdd_override(struct cmd_tbl *cmdtp,
+			   int flag, int argc,
+			   char *const argv[])
+{
+	ulong override;
+	int ret = 0;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	if (!strict_strtoul(argv[1], 10, &override)) {
+		ret = adjust_vdd(override);
+		if (ret < 0)
+			return CMD_RET_FAILURE;
+	} else
+		return CMD_RET_USAGE;
+	return 0;
+}
+
+static int do_vdd_read(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	if (argc < 1)
+		return CMD_RET_USAGE;
+	print_vdd();
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	vdd_override, 2, 0, do_vdd_override,
+	"override VDD",
+	" - override with the voltage specified in mV, eg. 1050"
+);
+
+U_BOOT_CMD(
+	vdd_read, 1, 0, do_vdd_read,
+	"read VDD",
+	" - Read the voltage specified in mV"
+)
diff --git a/roms/u-boot/board/freescale/common/vid.h b/roms/u-boot/board/freescale/common/vid.h
new file mode 100644
index 000000000..b34c080b4
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/vid.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
+ */
+
+#ifndef __VID_H_
+#define __VID_H_
+
+/* IR36021 command codes */
+#define IR36021_LOOP1_MANUAL_ID_OFFSET	0x6A
+#define IR36021_LOOP1_VOUT_OFFSET	0x9A
+#define IR36021_MFR_ID_OFFSET		0x92
+#define IR36021_MFR_ID			0x43
+#define IR36021_INTEL_MODE_OFFSET	0x14
+#define IR36021_MODE_MASK		0x20
+#define IR36021_INTEL_MODE		0x00
+#define IR36021_AMD_MODE		0x20
+
+/* Step the IR regulator in 5mV increments */
+#define IR_VDD_STEP_DOWN		5
+#define IR_VDD_STEP_UP			5
+
+/* LTC3882 */
+#define PMBUS_CMD_WRITE_PROTECT         0x10
+/*
+ * WRITE_PROTECT command supported values
+ * 0x80: Disable all writes except WRITE_PROTECT, PAGE,
+ *       STORE_USER_ALL and MFR_EE_UNLOCK commands.
+ * 0x40: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL,
+ *       MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_FAULTS commands.
+ *       Individual faults can also be cleared by writing a 1 to the
+ *       respective status bit.
+ * 0x20: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL,
+ *       MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS, ON_OFF_CONFIG
+ *       and VOUT_COMMAND commands. Individual faults can be cleared by
+ *       writing a 1 to the respective status bit.
+ * 0x00: Enables write to all commands
+ */
+#define EN_WRITE_ALL_CMD (0)
+
+#ifdef CONFIG_TARGET_LX2160ARDB
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN			775
+#define VDD_MV_MAX			855
+#endif
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN			775
+#define VDD_MV_MAX			925
+#endif
+
+/* PM Bus commands code for LTC3882*/
+#define PWM_CHANNEL0                    0x0
+#define PMBUS_CMD_PAGE                  0x0
+#define PMBUS_CMD_READ_VOUT             0x8B
+#define PMBUS_CMD_VOUT_MODE			0x20
+#define PMBUS_CMD_VOUT_COMMAND          0x21
+#define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
+defined(CONFIG_TARGET_LX2160ARDB)
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+#define I2C_VOL_MONITOR_ADDR            0x63
+#define I2C_MUX_CH_VOL_MONITOR		0xA
+#endif
+
+int adjust_vdd(ulong vdd_override);
+u16 soc_get_fuse_vid(int vid_index);
+
+#endif  /* __VID_H_ */
diff --git a/roms/u-boot/board/freescale/common/vsc3316_3308.c b/roms/u-boot/board/freescale/common/vsc3316_3308.c
new file mode 100644
index 000000000..c51f3c5ac
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/vsc3316_3308.c
@@ -0,0 +1,530 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
+ */
+
+#include "vsc3316_3308.h"
+#include <log.h>
+
+#define REVISION_ID_REG		0x7E
+#define INTERFACE_MODE_REG		0x79
+#define CURRENT_PAGE_REGISTER		0x7F
+#define CONNECTION_CONFIG_PAGE		0x00
+#define INPUT_STATE_REG		0x13
+#define GLOBAL_INPUT_ISE1		0x51
+#define GLOBAL_INPUT_ISE2		0x52
+#define GLOBAL_INPUT_GAIN		0x53
+#define GLOBAL_INPUT_LOS		0x55
+#define GLOBAL_OUTPUT_PE1		0x56
+#define GLOBAL_OUTPUT_PE2		0x57
+#define GLOBAL_OUTPUT_LEVEL		0x58
+#define GLOBAL_OUTPUT_TERMINATION	0x5A
+#define GLOBAL_CORE_CNTRL		0x5D
+#define OUTPUT_MODE_PAGE		0x23
+#define CORE_CONTROL_PAGE		0x25
+#define CORE_CONFIG_REG		0x75
+
+int vsc_if_enable(unsigned int vsc_addr)
+{
+	u8 data;
+
+	debug("VSC:Configuring VSC at I2C address 0x%2x"
+			" for 2-wire interface\n", vsc_addr);
+
+	/* enable 2-wire Serial InterFace (I2C) */
+	data = 0x02;
+#if CONFIG_IS_ENABLED(DM_I2C)
+	int ret, bus_num = 0;
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+
+	return dm_i2c_write(dev, INTERFACE_MODE_REG, &data, 1);
+#else
+	return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1);
+#endif
+}
+
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
+		unsigned int num_con)
+{
+	unsigned int i;
+	u8 rev_id = 0;
+	int ret;
+
+	debug("VSC:Initializing VSC3316 at I2C address 0x%2x"
+		" for Tx\n", vsc_addr);
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	int bus_num = 0;
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+
+	ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1);
+	if (ret < 0) {
+		printf("VSC:0x%x could not read REV_ID from device.\n",
+		       vsc_addr);
+		return ret;
+	}
+
+	if (rev_id != 0xab) {
+		printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+		       vsc_addr);
+		return -ENODEV;
+	}
+
+	ret = vsc_if_enable(vsc_addr);
+	if (ret) {
+		printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+		       vsc_addr);
+		return ret;
+	}
+
+	/* config connections - page 0x00 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+	/* Making crosspoint connections, by connecting required
+	 * input to output
+	 */
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);
+
+	/* input state - page 0x13 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+	/* Configuring the required input of the switch */
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev, con_arr[i][0], 0x80);
+
+	/* Setting Global Input LOS threshold value */
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60);
+
+	/* config output mode - page 0x23 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+	/* Turn ON the Output driver correspond to required output*/
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev,  con_arr[i][1], 0);
+
+	/* configure global core control register, Turn on Global core power */
+	dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0);
+
+#else
+	ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
+	if (ret < 0) {
+		printf("VSC:0x%x could not read REV_ID from device.\n",
+			vsc_addr);
+		return ret;
+	}
+
+	if (rev_id != 0xab) {
+		printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+			vsc_addr);
+		return -ENODEV;
+	}
+
+	ret = vsc_if_enable(vsc_addr);
+	if (ret) {
+		printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+			vsc_addr);
+		return ret;
+	}
+
+	/* config connections - page 0x00 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+	/* Making crosspoint connections, by connecting required
+	 * input to output */
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
+
+	/* input state - page 0x13 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+	/* Configuring the required input of the switch */
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr, con_arr[i][0], 0x80);
+
+	/* Setting Global Input LOS threshold value */
+	i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60);
+
+	/* config output mode - page 0x23 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+	/* Turn ON the Output driver correspond to required output*/
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr,  con_arr[i][1], 0);
+
+	/* configure global core control register, Turn on Global core power */
+	i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
+#endif
+
+	vsc_wp_config(vsc_addr);
+
+	return 0;
+}
+
+#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
+		unsigned int num_con)
+{
+	unsigned int i;
+	u8 rev_id = 0;
+	int ret;
+
+	debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n",
+	      vsc_addr);
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	int bus_num = 0;
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+
+	ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1);
+	if (ret < 0) {
+		printf("VSC:0x%x could not read REV_ID from device.\n",
+		       vsc_addr);
+		return ret;
+	}
+
+	if (rev_id != 0xab) {
+		printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+		       vsc_addr);
+		return -ENODEV;
+	}
+
+	ret = vsc_if_enable(vsc_addr);
+	if (ret) {
+		printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+		       vsc_addr);
+		return ret;
+	}
+
+	/* config connections - page 0x00 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+	/* Configure Global Input ISE */
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0);
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0);
+
+	/* Configure Tx/Rx Global Output PE1 */
+	dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE1, 0);
+
+	/* Configure Tx/Rx Global Output PE2 */
+	dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE2, 0);
+
+	/* Configure Tx/Rx Global Input GAIN */
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_GAIN, 0x3F);
+
+	/* Setting Global Input LOS threshold value */
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0xE0);
+
+	/* Setting Global output termination */
+	dm_i2c_reg_write(dev, GLOBAL_OUTPUT_TERMINATION, 0);
+
+	/* Configure Tx/Rx Global Output level */
+	if (vsc_addr == VSC3308_TX_ADDRESS)
+		dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 4);
+	else
+		dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 2);
+
+	/* Making crosspoint connections, by connecting required
+	 * input to output
+	 */
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);
+
+	/* input state - page 0x13 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+	/* Turning off all the required input of the switch */
+	for (i = 0; i < num_con; i++)
+		dm_i2c_reg_write(dev, con_arr[i][0], 1);
+
+	/* only turn on specific Tx/Rx requested by the XFI erratum */
+	if (vsc_addr == VSC3308_TX_ADDRESS) {
+		dm_i2c_reg_write(dev, 2, 0);
+		dm_i2c_reg_write(dev, 3, 0);
+	} else {
+		dm_i2c_reg_write(dev, 0, 0);
+		dm_i2c_reg_write(dev, 1, 0);
+	}
+
+	/* config output mode - page 0x23 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+	/* Turn off the Output driver correspond to required output*/
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev,  con_arr[i][1], 1);
+
+	/* only turn on specific Tx/Rx requested by the XFI erratum */
+	if (vsc_addr == VSC3308_TX_ADDRESS) {
+		dm_i2c_reg_write(dev, 0, 0);
+		dm_i2c_reg_write(dev, 1, 0);
+	} else {
+		dm_i2c_reg_write(dev, 3, 0);
+		dm_i2c_reg_write(dev, 4, 0);
+	}
+
+	/* configure global core control register, Turn on Global core power */
+	dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0);
+#else
+	ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
+	if (ret < 0) {
+		printf("VSC:0x%x could not read REV_ID from device.\n",
+		       vsc_addr);
+		return ret;
+	}
+
+	if (rev_id != 0xab) {
+		printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+		       vsc_addr);
+		return -ENODEV;
+	}
+
+	ret = vsc_if_enable(vsc_addr);
+	if (ret) {
+		printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+		       vsc_addr);
+		return ret;
+	}
+
+	/* config connections - page 0x00 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+	/* Configure Global Input ISE */
+	i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0);
+	i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0);
+
+	/* Configure Tx/Rx Global Output PE1 */
+	i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE1, 0);
+
+	/* Configure Tx/Rx Global Output PE2 */
+	i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE2, 0);
+
+	/* Configure Tx/Rx Global Input GAIN */
+	i2c_reg_write(vsc_addr, GLOBAL_INPUT_GAIN, 0x3F);
+
+	/* Setting Global Input LOS threshold value */
+	i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0xE0);
+
+	/* Setting Global output termination */
+	i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_TERMINATION, 0);
+
+	/* Configure Tx/Rx Global Output level */
+	if (vsc_addr == VSC3308_TX_ADDRESS)
+		i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 4);
+	else
+		i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 2);
+
+	/* Making crosspoint connections, by connecting required
+	 * input to output */
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
+
+	/* input state - page 0x13 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+	/* Turning off all the required input of the switch */
+	for (i = 0; i < num_con; i++)
+		i2c_reg_write(vsc_addr, con_arr[i][0], 1);
+
+	/* only turn on specific Tx/Rx requested by the XFI erratum */
+	if (vsc_addr == VSC3308_TX_ADDRESS) {
+		i2c_reg_write(vsc_addr, 2, 0);
+		i2c_reg_write(vsc_addr, 3, 0);
+	} else {
+		i2c_reg_write(vsc_addr, 0, 0);
+		i2c_reg_write(vsc_addr, 1, 0);
+	}
+
+	/* config output mode - page 0x23 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+	/* Turn off the Output driver correspond to required output*/
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr,  con_arr[i][1], 1);
+
+	/* only turn on specific Tx/Rx requested by the XFI erratum */
+	if (vsc_addr == VSC3308_TX_ADDRESS) {
+		i2c_reg_write(vsc_addr, 0, 0);
+		i2c_reg_write(vsc_addr, 1, 0);
+	} else {
+		i2c_reg_write(vsc_addr, 3, 0);
+		i2c_reg_write(vsc_addr, 4, 0);
+	}
+
+	/* configure global core control register, Turn on Global core power */
+	i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
+#endif
+	vsc_wp_config(vsc_addr);
+
+	return 0;
+}
+#endif
+
+int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+		unsigned int num_con)
+{
+	unsigned int i;
+	u8 rev_id = 0;
+	int ret;
+
+	debug("VSC:Initializing VSC3308 at I2C address 0x%x"
+		" for Tx\n", vsc_addr);
+#if CONFIG_IS_ENABLED(DM_I2C)
+	int bus_num = 0;
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+
+	ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1);
+	if (ret < 0) {
+		printf("VSC:0x%x could not read REV_ID from device.\n",
+		       vsc_addr);
+		return ret;
+	}
+
+	if (rev_id != 0xab) {
+		printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+		       vsc_addr);
+		return -ENODEV;
+	}
+
+	ret = vsc_if_enable(vsc_addr);
+	if (ret) {
+		printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+		       vsc_addr);
+		return ret;
+	}
+
+	/* config connections - page 0x00 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+	/* Making crosspoint connections, by connecting required
+	 * input to output
+	 */
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);
+
+	/*Configure Global Input ISE and gain */
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0x12);
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0x12);
+
+	/* input state - page 0x13 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+	/* Turning ON the required input of the switch */
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev, con_arr[i][0], 0);
+
+	/* Setting Global Input LOS threshold value */
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60);
+
+	/* config output mode - page 0x23 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+	/* Turn ON the Output driver correspond to required output*/
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev,  con_arr[i][1], 0);
+
+	/* configure global core control register, Turn on Global core power */
+	dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0);
+#else
+	ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
+	if (ret < 0) {
+		printf("VSC:0x%x could not read REV_ID from device.\n",
+			vsc_addr);
+		return ret;
+	}
+
+	if (rev_id != 0xab) {
+		printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+			vsc_addr);
+		return -ENODEV;
+	}
+
+	ret = vsc_if_enable(vsc_addr);
+	if (ret) {
+		printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+			vsc_addr);
+		return ret;
+	}
+
+	/* config connections - page 0x00 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+	/* Making crosspoint connections, by connecting required
+	 * input to output */
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
+
+	/*Configure Global Input ISE and gain */
+	i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0x12);
+	i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0x12);
+
+	/* input state - page 0x13 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+	/* Turning ON the required input of the switch */
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr, con_arr[i][0], 0);
+
+	/* Setting Global Input LOS threshold value */
+	i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60);
+
+	/* config output mode - page 0x23 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+	/* Turn ON the Output driver correspond to required output*/
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr,  con_arr[i][1], 0);
+
+	/* configure global core control register, Turn on Global core power */
+	i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
+#endif
+	vsc_wp_config(vsc_addr);
+
+	return 0;
+}
+
+void vsc_wp_config(unsigned int vsc_addr)
+{
+	debug("VSC:Configuring VSC at address:0x%x for WP\n", vsc_addr);
+
+	/* For new crosspoint configuration to occur, WP bit of
+	 * CORE_CONFIG_REG should be set 1 and then reset to 0 */
+#if CONFIG_IS_ENABLED(DM_I2C)
+	int ret, bus_num = 0;
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return;
+	}
+
+	dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x01);
+	dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x0);
+#else
+	i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01);
+	i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0);
+#endif
+}
diff --git a/roms/u-boot/board/freescale/common/vsc3316_3308.h b/roms/u-boot/board/freescale/common/vsc3316_3308.h
new file mode 100644
index 000000000..49a684f9f
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/vsc3316_3308.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __VSC_CROSSBAR_H_
+#define __VSC_CROSSBAR_H	1_
+
+#include <common.h>
+#include <i2c.h>
+#include <errno.h>
+
+int vsc_if_enable(unsigned int vsc_addr);
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
+		unsigned int num_con);
+#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
+		unsigned int num_con);
+#endif
+int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+		unsigned int num_con);
+void vsc_wp_config(unsigned int vsc_addr);
+
+#endif	/* __VSC_CROSSBAR_H_ */
diff --git a/roms/u-boot/board/freescale/common/zm7300.c b/roms/u-boot/board/freescale/common/zm7300.c
new file mode 100644
index 000000000..03679e723
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/zm7300.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+/* Power-One ZM7300 DPM */
+#include "zm7300.h"
+#include <log.h>
+
+#define DPM_WP 0x96
+#define WRP_OPCODE 0x01
+#define WRM_OPCODE 0x02
+#define RRP_OPCODE 0x11
+
+#define DPM_SUCCESS 0x01
+#define DPM_EXEC_FAIL 0x00
+
+static const uint16_t hex_to_1_10mv[] = {
+	5000,
+	5125,
+	5250,
+	5375,
+	5500,
+	5625,
+	5750,
+	5875,
+	6000,
+	6125,
+	6250,
+	6375,
+	6500,
+	6625,
+	6750,
+	6875,
+	7000,
+	7125,
+	7250,
+	7375,
+	7500,
+	7625,
+	7750,
+	7875,
+	8000,
+	8125,
+	8250,
+	8375,
+	8500,
+	8625,
+	8750,
+	8875,
+	9000,
+	9125,
+	9250,
+	9375,
+	9500,  /* 0.95mV */
+	9625,
+	9750,
+	9875,
+	10000,  /* 1.0V */
+	10125,
+	10250,
+	10375,
+	10500,
+	10625,
+	10750,
+	10875,
+	11000,
+	11125,
+	11250,
+	11375,
+	11500,
+	11625,
+	11750,
+	11875,
+	12000,
+	12125,
+	12250,
+	12375,
+	0,	/* reserved */
+};
+
+
+/* Read Data d from Register r of POL p */
+u8 dpm_rrp(uchar r)
+{
+	u8 ret[5];
+
+	ret[0] = RRP_OPCODE;
+	/* POL is 0 */
+	ret[1] = 0;
+	ret[2] = r;
+	i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2);
+	if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */
+		debug("RRP_OPCODE returned success data is %x\n", ret[0]);
+		return ret[0];
+	} else {
+		return -1;
+	}
+}
+
+/* Write Data d into DPM register r (RAM) */
+int dpm_wrm(u8 r, u8 d)
+{
+	u8 ret[5];
+
+	ret[0] = WRM_OPCODE;
+	ret[1] = r;
+	ret[2] = d;
+	i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1);
+	if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+		debug("WRM_OPCODE returned success data is %x\n", ret[0]);
+		return ret[0];
+	} else {
+		return -1;
+	}
+}
+
+/* Write Data d into Register r of POL(s) a */
+int dpm_wrp(u8 r, u8 d)
+{
+	u8 ret[7];
+
+	ret[0] = WRP_OPCODE;
+	/* only POL0 is present */
+	ret[1] = 0x01;
+	ret[2] = 0x00;
+	ret[3] = 0x00;
+	ret[4] = 0x00;
+	ret[5] = r;
+	ret[6] = d;
+	i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1);
+	if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+		debug("WRP_OPCODE returned success data is %x\n", ret[0]);
+		return 0;
+	} else {
+		return -1;
+	}
+}
+
+/* Uses the DPM command RRP */
+u8 zm_read(uchar reg)
+{
+	return dpm_rrp(reg);
+}
+
+/* ZM_write --
+	Steps:
+	a. Write data to the register
+	b. Read data from register and compare to written value
+	c. Return return_code & voltage_read
+*/
+u8 zm_write(u8 reg, u8 data)
+{
+	u8 d;
+
+	/* write data to register */
+	dpm_wrp(reg, data);
+
+	/* read register and compare to written value */
+	d = dpm_rrp(reg);
+	if (d != data) {
+		printf("zm_write : Comparison register data failed\n");
+		return -1;
+	}
+
+	return d;
+}
+
+/* zm_write_out_voltage
+ * voltage in 1/10 mV
+ */
+int zm_write_voltage(int voltage)
+{
+	u8 reg = 0x7, vid;
+	uint16_t voltage_read;
+	u8 ret;
+
+	vid =  (voltage - 5000) / ZM_STEP;
+
+	ret = zm_write(reg, vid);
+	if (ret != -1) {
+		voltage_read = hex_to_1_10mv[ret];
+		debug("voltage set to %dmV\n", voltage_read/10);
+		return voltage_read;
+	}
+	return -1;
+}
+
+/* zm_read_out_voltage
+ * voltage in 1/10 mV
+ */
+int zm_read_voltage(void)
+{
+	u8 reg = 0x7;
+	u8 ret;
+	int voltage;
+
+	ret = zm_read(reg);
+	if (ret != -1) {
+		voltage =  hex_to_1_10mv[ret];
+		debug("Voltage read is %dmV\n", voltage/10);
+		return voltage;
+	} else {
+		return -1;
+	}
+}
+
+int zm_disable_wp()
+{
+	u8 new_wp_value;
+
+	/* Disable using Write-Protect register 0x96 */
+	new_wp_value = 0x8;
+	if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) {
+		printf("Disable Write-Protect register failed\n");
+		return -1;
+	}
+	return 0;
+}
+
+int zm_enable_wp()
+{
+	u8 orig_wp_value;
+	orig_wp_value = 0x0;
+
+	/* Enable using Write-Protect register 0x96 */
+	if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) {
+		printf("Enable Write-Protect register failed\n");
+		return -1;
+	}
+	return 0;
+}
+
diff --git a/roms/u-boot/board/freescale/common/zm7300.h b/roms/u-boot/board/freescale/common/zm7300.h
new file mode 100644
index 000000000..9ce24afc1
--- /dev/null
+++ b/roms/u-boot/board/freescale/common/zm7300.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ZM7300_H_
+#define __ZM7300_H	1_
+
+#include <common.h>
+#include <i2c.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#define ZM_STEP 125
+int zm7300_set_voltage(int voltage_1_10mv);
+int zm_write_voltage(int voltage);
+int zm_read_voltage(void);
+int zm_disable_wp(void);
+int zm_enable_wp(void);
+
+#endif	/* __ZM7300_H_ */
diff --git a/roms/u-boot/board/freescale/corenet_ds/Kconfig b/roms/u-boot/board/freescale/corenet_ds/Kconfig
new file mode 100644
index 000000000..e92b0d099
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/Kconfig
@@ -0,0 +1,44 @@
+if TARGET_P3041DS
+
+config SYS_BOARD
+	default "corenet_ds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "P3041DS"
+
+source "board/freescale/common/Kconfig"
+
+endif
+
+if TARGET_P4080DS
+
+config SYS_BOARD
+	default "corenet_ds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "P4080DS"
+
+source "board/freescale/common/Kconfig"
+
+endif
+
+if TARGET_P5040DS
+
+config SYS_BOARD
+	default "corenet_ds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "P5040DS"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/corenet_ds/MAINTAINERS b/roms/u-boot/board/freescale/corenet_ds/MAINTAINERS
new file mode 100644
index 000000000..f0da86a34
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/MAINTAINERS
@@ -0,0 +1,21 @@
+CORENET_DS BOARD
+#M:	-
+S:	Maintained
+F:	board/freescale/corenet_ds/
+F:	include/configs/P3041DS.h
+F:	configs/P3041DS_defconfig
+F:	configs/P3041DS_NAND_defconfig
+F:	configs/P3041DS_SDCARD_defconfig
+F:	configs/P3041DS_SPIFLASH_defconfig
+F:	configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+F:	include/configs/P4080DS.h
+F:	configs/P4080DS_defconfig
+F:	configs/P4080DS_SDCARD_defconfig
+F:	configs/P4080DS_SPIFLASH_defconfig
+F:	configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+F:	include/configs/P5040DS.h
+F:	configs/P5040DS_defconfig
+F:	configs/P5040DS_NAND_defconfig
+F:	configs/P5040DS_SDCARD_defconfig
+F:	configs/P5040DS_SPIFLASH_defconfig
+F:	configs/P5040DS_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/corenet_ds/Makefile b/roms/u-boot/board/freescale/corenet_ds/Makefile
new file mode 100644
index 000000000..4d62fc9ce
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= corenet_ds.o
+obj-y	+= ddr.o
+obj-$(CONFIG_TARGET_P3041DS)	+= eth_hydra.o
+obj-$(CONFIG_TARGET_P4080DS)	+= eth_p4080.o
+obj-$(CONFIG_TARGET_P5040DS)	+= eth_superhydra.o
+obj-$(CONFIG_TARGET_P3041DS)	+= p3041ds_ddr.o
+obj-$(CONFIG_TARGET_P4080DS)	+= p4080ds_ddr.o
+obj-$(CONFIG_TARGET_P5040DS)	+= p5040ds_ddr.o
diff --git a/roms/u-boot/board/freescale/corenet_ds/corenet_ds.c b/roms/u-boot/board/freescale/corenet_ds/corenet_ds.c
new file mode 100644
index 000000000..3a83e65f2
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/corenet_ds.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <image.h>
+#include <init.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/ngpixis.h"
+#include "corenet_ds.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard (void)
+{
+	u8 sw;
+	struct cpu_type *cpu = gd->arch.cpu;
+#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
+	defined(CONFIG_TARGET_P5040DS)
+	unsigned int i;
+#endif
+	static const char * const freq[] = {"100", "125", "156.25", "212.5" };
+
+	printf("Board: %sDS, ", cpu->name);
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
+
+	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+	sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("Promjet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
+
+	/* Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES Reference Clocks: ");
+#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
+	defined(CONFIG_TARGET_P5040DS)
+	sw = in_8(&PIXIS_SW(5));
+	for (i = 0; i < 3; i++) {
+		unsigned int clock = (sw >> (6 - (2 * i))) & 3;
+
+		printf("Bank%u=%sMhz ", i+1, freq[clock]);
+	}
+#ifdef CONFIG_TARGET_P5040DS
+	/* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
+	sw = in_8(&PIXIS_SW(9));
+	printf("Bank4=%sMhz ", freq[sw & 3]);
+#endif
+	puts("\n");
+#else
+	sw = in_8(&PIXIS_SW(3));
+	/* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
+	/* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
+	/* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
+	printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
+	printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
+	printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
+#endif
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/*
+	 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
+	 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
+	 * the noise introduced by these unterminated and unused clock pairs.
+	 */
+	setbits_be32(&gur->ddrclkdr, 0x001B001B);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 2;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash + promjet */
+		disable_tlb(flash_esel);
+	}
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
+
+	return 0;
+}
+
+#define NUM_SRDS_BANKS	3
+
+int misc_init_r(void)
+{
+	serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 actual[NUM_SRDS_BANKS];
+	unsigned int i;
+	u8 sw;
+
+#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
+	defined(CONFIG_TARGET_P5040DS)
+	sw = in_8(&PIXIS_SW(5));
+	for (i = 0; i < 3; i++) {
+		unsigned int clock = (sw >> (6 - (2 * i))) & 3;
+		switch (clock) {
+		case 0:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+			break;
+		case 1:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+			break;
+		case 2:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+			break;
+		default:
+			printf("Warning: SDREFCLK%u switch setting of '11' is "
+			       "unsupported\n", i + 1);
+			break;
+		}
+	}
+#else
+	/* Warn if the expected SERDES reference clocks don't match the
+	 * actual reference clocks.  This needs to be done after calling
+	 * p4080_erratum_serdes8(), since that function may modify the clocks.
+	 */
+	sw = in_8(&PIXIS_SW(3));
+	actual[0] = (sw & 0x40) ?
+		SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
+	actual[1] = (sw & 0x20) ?
+		SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
+	actual[2] = (sw & 0x10) ?
+		SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
+#endif
+
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (expected != actual[i]) {
+			printf("Warning: SERDES bank %u expects reference clock"
+			       " %sMHz, but actual is %sMHz\n", i + 1,
+			       serdes_clock_to_string(expected),
+			       serdes_clock_to_string(actual[i]));
+		}
+	}
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+	fsl_fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
+	fdt_fixup_fman_ethernet(blob);
+#endif
+	fdt_fixup_board_enet(blob);
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/corenet_ds/corenet_ds.h b/roms/u-boot/board/freescale/corenet_ds/corenet_ds.h
new file mode 100644
index 000000000..84e5c4a2d
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/corenet_ds.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, struct bd_info *bd);
+
+#endif
diff --git a/roms/u-boot/board/freescale/corenet_ds/ddr.c b/roms/u-boot/board/freescale/corenet_ds/ddr.c
new file mode 100644
index 000000000..2c440673e
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/ddr.c
@@ -0,0 +1,287 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <init.h>
+#include <log.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+extern fixed_ddr_parm_t fixed_ddr_parm_0[];
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
+extern fixed_ddr_parm_t fixed_ddr_parm_1[];
+#endif
+
+phys_size_t fixed_sdram(void)
+{
+	int i;
+	char buf[32];
+	fsl_ddr_cfg_regs_t ddr_cfg_regs;
+	phys_size_t ddr_size;
+	unsigned int lawbar1_target_id;
+	ulong ddr_freq, ddr_freq_mhz;
+
+	ddr_freq = get_ddr_freq(0);
+	ddr_freq_mhz = ddr_freq / 1000000;
+
+	printf("Configuring DDR for %s MT/s data rate\n",
+				strmhz(buf, ddr_freq));
+
+	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+			memcpy(&ddr_cfg_regs,
+				fixed_ddr_parm_0[i].ddr_settings,
+				sizeof(ddr_cfg_regs));
+			break;
+		}
+	}
+
+	if (fixed_ddr_parm_0[i].max_freq == 0)
+		panic("Unsupported DDR data rate %s MT/s data rate\n",
+			strmhz(buf, ddr_freq));
+
+	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
+	memcpy(&ddr_cfg_regs,
+		fixed_ddr_parm_1[i].ddr_settings,
+		sizeof(ddr_cfg_regs));
+	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0);
+#endif
+
+	/*
+	 * setup laws for DDR. If not interleaving, presuming half memory on
+	 * DDR1 and the other half on DDR2
+	 */
+	if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
+		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+				 ddr_size,
+				 LAW_TRGT_IF_DDR_INTRLV) < 0) {
+			printf("ERROR setting Local Access Windows for DDR\n");
+			return 0;
+		}
+	} else {
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
+		/* We require both controllers have identical DIMMs */
+		lawbar1_target_id = LAW_TRGT_IF_DDR_1;
+		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+				 ddr_size / 2,
+				 lawbar1_target_id) < 0) {
+			printf("ERROR setting Local Access Windows for DDR\n");
+			return 0;
+		}
+		lawbar1_target_id = LAW_TRGT_IF_DDR_2;
+		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
+				 ddr_size / 2,
+				 lawbar1_target_id) < 0) {
+			printf("ERROR setting Local Access Windows for DDR\n");
+			return 0;
+		}
+#else
+		lawbar1_target_id = LAW_TRGT_IF_DDR_1;
+		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+				 ddr_size,
+				 lawbar1_target_id) < 0) {
+			printf("ERROR setting Local Access Windows for DDR\n");
+			return 0;
+		}
+#endif
+	}
+	return ddr_size;
+}
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2t;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz|adjst| start |      |delay |
+	 */
+	{4,   850,    4,     6,   0xff,    2,  0},
+	{4,   950,    5,     7,   0xff,    2,  0},
+	{4,  1050,    5,     8,   0xff,    2,  0},
+	{4,  1250,    5,    10,   0xff,    2,  0},
+	{4,  1350,    5,    11,   0xff,    2,  0},
+	{4,  1666,    5,    12,   0xff,    2,  0},
+	{2,   850,    5,     6,   0xff,    2,  0},
+	{2,  1050,    5,     7,   0xff,    2,  0},
+	{2,  1250,    4,     6,   0xff,    2,  0},
+	{2,  1350,    5,     7,   0xff,    2,  0},
+	{2,  1666,    5,     8,   0xff,    2,  0},
+	{1,  1250,    4,     6,   0xff,    2,  0},
+	{1,  1335,    4,     7,   0xff,    2,  0},
+	{1,  1666,    4,     8,   0xff,    2,  0},
+	{}
+};
+
+/*
+ * The two slots have slightly different timing. The center values are good
+ * for both slots. We use identical speed tables for them. In future use, if
+ * DIMMs have fewer center values that require two separated tables, copy the
+ * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
+ */
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+	udimm0,
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz|adjst| start |      |delay |
+	 */
+	{4,   850,    4,     6,   0xff,    2,  0},
+	{4,   950,    5,     7,   0xff,    2,  0},
+	{4,  1050,    5,     8,   0xff,    2,  0},
+	{4,  1250,    5,    10,   0xff,    2,  0},
+	{4,  1350,    5,    11,   0xff,    2,  0},
+	{4,  1666,    5,    12,   0xff,    2,  0},
+	{2,   850,    4,     6,   0xff,    2,  0},
+	{2,  1050,    4,     7,   0xff,    2,  0},
+	{2,  1666,    4,     8,   0xff,    2,  0},
+	{1,   850,    4,     5,   0xff,    2,  0},
+	{1,   950,    4,     7,   0xff,    2,  0},
+	{1,  1666,    4,     8,   0xff,    2,  0},
+	{}
+};
+
+/*
+ * The two slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+	rdimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Wrong parameter for controller number %d", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[ctrl_num];
+	else
+		pbsp = udimms[ctrl_num];
+
+
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->cpo_override = pbsp->cpo;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->twot_en = pbsp->force_2t;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found "
+			"for data rate %lu MT/s!\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->cpo_override = pbsp_highest->cpo;
+		popts->write_data_delay = pbsp_highest->write_data_delay;
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->twot_en = pbsp_highest->force_2t;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 60 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
+}
+
+int dram_init(void)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....");
+
+	if (fsl_use_spd()) {
+		puts("using SPD\n");
+		dram_size = fsl_ddr_sdram();
+	} else {
+		puts("using fixed parameters\n");
+		dram_size = fixed_sdram();
+	}
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	debug("    DDR: ");
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/corenet_ds/eth_hydra.c b/roms/u-boot/board/freescale/corenet_ds/eth_hydra.c
new file mode 100644
index 000000000..6500c2fcf
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/eth_hydra.c
@@ -0,0 +1,526 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * Author: Timur Tabi <timur@freescale.com>
+ */
+
+/*
+ * This file handles the board muxing between the Fman Ethernet MACs and
+ * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference
+ * board. The RGMII PHYs are the two on-board 1Gb ports.  The SGMII PHYs are
+ * provided by the standard Freescale four-port SGMII riser card.  The 10Gb
+ * XGMII PHY is provided via the XAUI riser card.  Since there is only one
+ * Fman device on a P3041 and P5020, we only support one SGMII card and one
+ * RGMII card.
+ *
+ * Muxing is handled via the PIXIS BRDCFG1 register.  The EMI1 bits control
+ * muxing among the RGMII PHYs and the SGMII PHYs.  The value for RGMII is
+ * always the same (0).  The value for SGMII depends on which slot the riser is
+ * inserted in.  The EMI2 bits control muxing for the the XGMII.  Like SGMII,
+ * the value is based on which slot the XAUI is inserted in.
+ *
+ * The SERDES configuration is used to determine where the SGMII and XAUI cards
+ * exist, and also which Fman MACs are routed to which PHYs.  So for a given
+ * Fman MAC, there is one and only PHY it connects to.  MACs cannot be routed
+ * to PHYs dynamically.
+ *
+ *
+ * This file also updates the device tree in three ways:
+ *
+ * 1) The status of each virtual MDIO node that is referenced by an Ethernet
+ *    node is set to "okay".
+ *
+ * 2) The phy-handle property of each active Ethernet MAC node is set to the
+ *    appropriate PHY node.
+ *
+ * 3) The "mux value" for each virtual MDIO node is set to the correct value,
+ *    if necessary.  Some virtual MDIO nodes do not have configurable mux
+ *    values, so those values are hard-coded in the DTS.  On the HYDRA board,
+ *    the virtual MDIO node for the SGMII card needs to be updated.
+ *
+ * For all this to work, the device tree needs to have the following:
+ *
+ * 1) An alias for each PHY node that an Ethernet node could be routed to.
+ *
+ * 2) An alias for each real and virtual MDIO node that is disabled by default
+ * and might need to be enabled, and also might need to have its mux-value
+ * updated.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fdt_support.h>
+#include <fsl_dtsec.h>
+
+#include "../common/ngpixis.h"
+#include "../common/fman.h"
+
+#ifdef CONFIG_FMAN_ENET
+
+#define BRDCFG1_EMI1_SEL_MASK	0x78
+#define BRDCFG1_EMI1_SEL_SLOT1	0x10
+#define BRDCFG1_EMI1_SEL_SLOT2	0x20
+#define BRDCFG1_EMI1_SEL_SLOT5	0x30
+#define BRDCFG1_EMI1_SEL_SLOT6	0x40
+#define BRDCFG1_EMI1_SEL_SLOT7	0x50
+#define BRDCFG1_EMI1_SEL_RGMII	0x00
+#define BRDCFG1_EMI1_EN		0x08
+#define BRDCFG1_EMI2_SEL_MASK	0x06
+#define BRDCFG1_EMI2_SEL_SLOT1	0x00
+#define BRDCFG1_EMI2_SEL_SLOT2	0x02
+
+#define BRDCFG2_REG_GPIO_SEL	0x20
+
+#define PHY_BASE_ADDR		0x00
+
+/*
+ * BRDCFG1 mask and value for each MAC
+ *
+ * This array contains the BRDCFG1 values (in mask/val format) that route the
+ * MDIO bus to a particular RGMII or SGMII PHY.
+ */
+struct {
+	u8 mask;
+	u8 val;
+} mdio_mux[NUM_FM_PORTS];
+
+/*
+ * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot
+ */
+static u8 lane_to_slot[] = {
+	7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
+};
+
+/*
+ * Set the board muxing for a given MAC
+ *
+ * The MDIO layer calls this function every time it wants to talk to a PHY.
+ */
+void hydra_mux_mdio(u8 mask, u8 val)
+{
+	clrsetbits_8(&pixis->brdcfg1, mask, val);
+}
+
+struct hydra_mdio {
+	u8 mask;
+	u8 val;
+	struct mii_dev *realbus;
+};
+
+static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
+				int regnum)
+{
+	struct hydra_mdio *priv = bus->priv;
+
+	hydra_mux_mdio(priv->mask, priv->val);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
+				int regnum, u16 value)
+{
+	struct hydra_mdio *priv = bus->priv;
+
+	hydra_mux_mdio(priv->mask, priv->val);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int hydra_mdio_reset(struct mii_dev *bus)
+{
+	struct hydra_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static void hydra_mdio_set_mux(char *name, u8 mask, u8 val)
+{
+	struct mii_dev *bus = miiphy_get_dev_by_name(name);
+	struct hydra_mdio *priv = bus->priv;
+
+	priv->mask = mask;
+	priv->val = val;
+}
+
+static int hydra_mdio_init(char *realbusname, char *fakebusname)
+{
+	struct hydra_mdio *hmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate Hydra MDIO bus\n");
+		return -1;
+	}
+
+	hmdio = malloc(sizeof(*hmdio));
+	if (!hmdio) {
+		printf("Failed to allocate Hydra private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = hydra_mdio_read;
+	bus->write = hydra_mdio_write;
+	bus->reset = hydra_mdio_reset;
+	strcpy(bus->name, fakebusname);
+
+	hmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!hmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(hmdio);
+		return -1;
+	}
+
+	bus->priv = hmdio;
+
+	return mdio_register(bus);
+}
+
+/*
+ * Given an alias or a path for a node, set the mux value of that node.
+ *
+ * If 'alias' is not a valid alias, then it is treated as a full path to the
+ * node.  No error checking is performed.
+ *
+ * This function is normally called to set the fsl,hydra-mdio-muxval property
+ * of a virtual MDIO node.
+ */
+static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
+{
+	const char *path = fdt_get_alias(fdt, alias);
+
+	if (!path)
+		path = alias;
+
+	do_fixup_by_path(fdt, path, "reg",
+			 &mux, sizeof(mux), 1);
+	do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
+			 &mux, sizeof(mux), 1);
+}
+
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) An Fman port
+ *
+ * ... update the phy-handle property of the Ethernet node to point to the
+ * right PHY.  This assumes that we already know the PHY for each port.  That
+ * information is stored in mdio_mux[].
+ *
+ * The offset of the Fman Ethernet node is also passed in for convenience, but
+ * it is not used, and we recalculate the offset anyway.
+ *
+ * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
+ * Inside the Fman, "ports" are things that connect to MACs.  We only call them
+ * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
+ * and ports are the same thing.
+ *
+ * Note that this code would be cleaner if had a function called
+ * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[]
+ * array.  That's because all we're doing is figuring out the PHY address for
+ * a given Fman MAC and writing it to the device tree.  Well, we already did
+ * the hard work to figure that out in board_eth_init(), so it's silly to
+ * repeat that here.
+ */
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+			      enum fm_port port, int offset)
+{
+	unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask;
+	char phy[16];
+
+	if (port == FM1_10GEC1) {
+		/* XAUI */
+		int lane = serdes_get_first_lane(XAUI_FM1);
+		if (lane >= 0) {
+			/* The XAUI PHY is identified by the slot */
+			sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
+			fdt_set_phy_handle(fdt, compat, addr, phy);
+		}
+		return;
+	}
+
+	if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
+		/* RGMII */
+		/* The RGMII PHY is identified by the MAC connected to it */
+		sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
+		fdt_set_phy_handle(fdt, compat, addr, phy);
+		return;
+	}
+
+	/* If it's not RGMII or XGMII, it must be SGMII */
+	if (mux) {
+		/* The SGMII PHY is identified by the MAC connected to it */
+		sprintf(phy, "phy_sgmii_%x",
+			CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1));
+		fdt_set_phy_handle(fdt, compat, addr, phy);
+	}
+}
+
+#define PIXIS_SW2_LANE_23_SEL		0x80
+#define PIXIS_SW2_LANE_45_SEL		0x40
+#define PIXIS_SW2_LANE_67_SEL_MASK	0x30
+#define PIXIS_SW2_LANE_67_SEL_5		0x00
+#define PIXIS_SW2_LANE_67_SEL_6		0x20
+#define PIXIS_SW2_LANE_67_SEL_7		0x10
+#define PIXIS_SW2_LANE_8_SEL		0x08
+#define PIXIS_SW2_LANE_1617_SEL		0x04
+
+/*
+ * Initialize the lane_to_slot[] array.
+ *
+ * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
+ * slots is hard-coded.  On the Hydra board, however, the mapping is controlled
+ * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
+ * initialized.
+ */
+static void initialize_lane_to_slot(void)
+{
+	u8 sw2 = in_8(&PIXIS_SW(2));
+
+	lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
+	lane_to_slot[3] = lane_to_slot[2];
+
+	lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
+	lane_to_slot[5] = lane_to_slot[4];
+
+	switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
+	case PIXIS_SW2_LANE_67_SEL_5:
+		lane_to_slot[6] = 5;
+		break;
+	case PIXIS_SW2_LANE_67_SEL_6:
+		lane_to_slot[6] = 6;
+		break;
+	case PIXIS_SW2_LANE_67_SEL_7:
+		lane_to_slot[6] = 7;
+		break;
+	}
+	lane_to_slot[7] = lane_to_slot[6];
+
+	lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
+
+	lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
+	lane_to_slot[17] = lane_to_slot[16];
+}
+
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+/*
+ * Configure the status for the virtual MDIO nodes
+ *
+ * Rather than create the virtual MDIO nodes from scratch for each active
+ * virtual MDIO, we expect the DTS to have the nodes defined already, and we
+ * only enable the ones that are actually active.
+ *
+ * We assume that the DTS already hard-codes the status for all the
+ * virtual MDIO nodes to "disabled", so all we need to do is enable the
+ * active ones.
+ *
+ * For SGMII, we also need to set the mux value in the node.
+ */
+void fdt_fixup_board_enet(void *fdt)
+{
+#ifdef CONFIG_FMAN_ENET
+	unsigned int i;
+	int lane;
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+			if (lane >= 0) {
+				fdt_status_okay_by_alias(fdt, "emi1_sgmii");
+				/* Also set the MUX value */
+				fdt_set_mdio_mux(fdt, "emi1_sgmii",
+						 mdio_mux[i].val);
+			}
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			fdt_status_okay_by_alias(fdt, "emi1_rgmii");
+			break;
+		default:
+			break;
+		}
+	}
+
+	lane = serdes_get_first_lane(XAUI_FM1);
+	if (lane >= 0)
+		fdt_status_okay_by_alias(fdt, "emi2_xgmii");
+#endif
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct fsl_pq_mdio_info dtsec_mdio_info;
+	struct tgec_mdio_info tgec_mdio_info;
+	unsigned int i, slot;
+	int lane;
+	struct mii_dev *bus;
+
+	printf("Initializing Fman\n");
+
+	initialize_lane_to_slot();
+
+	/* We want to use the PIXIS to configure MUX routing, not GPIOs. */
+	setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
+
+	memset(mdio_mux, 0, sizeof(mdio_mux));
+
+	dtsec_mdio_info.regs =
+		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the real 10G MDIO bus */
+	fm_tgec_mdio_init(bis, &tgec_mdio_info);
+
+	/* Register the three virtual MDIO front-ends */
+	hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
+	hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
+
+	/*
+	 * Program the DTSEC PHY addresses assuming that they are all SGMII.
+	 * For any DTSEC that's RGMII, we'll override its PHY address later.
+	 * We assume that DTSEC5 is only used for RGMII.
+	 */
+	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
+			switch (slot) {
+			case 1:
+				/* Always DTSEC5 on Bank 3 */
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
+						  BRDCFG1_EMI1_EN;
+				break;
+			case 2:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
+						  BRDCFG1_EMI1_EN;
+				break;
+			case 5:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
+						  BRDCFG1_EMI1_EN;
+				break;
+			case 6:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
+						  BRDCFG1_EMI1_EN;
+				break;
+			case 7:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
+						  BRDCFG1_EMI1_EN;
+				break;
+			};
+
+			hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
+					mdio_mux[i].mask, mdio_mux[i].val);
+			fm_info_set_mdio(i,
+				miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			/*
+			 * If DTSEC4 is RGMII, then it's routed via via EC1 to
+			 * the first on-board RGMII port.  If DTSEC5 is RGMII,
+			 * then it's routed via via EC2 to the second on-board
+			 * RGMII port. The other DTSECs cannot be routed to
+			 * RGMII.
+			 */
+			fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
+			mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
+			mdio_mux[i].val  = BRDCFG1_EMI1_SEL_RGMII |
+					   BRDCFG1_EMI1_EN;
+			hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
+					mdio_mux[i].mask, mdio_mux[i].val);
+			fm_info_set_mdio(i,
+				miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
+			break;
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
+			break;
+		default:
+			printf("Fman1: DTSEC%u set to unknown interface %i\n",
+			       idx + 1, fm_info_get_enet_if(i));
+			fm_info_set_phy_address(i, 0);
+			break;
+		}
+	}
+
+	bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
+	set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
+
+	/*
+	 * For 10G, we only support one XAUI card per Fman.  If present, then we
+	 * force its routing and never touch those bits again, which removes the
+	 * need for Linux to do any muxing.  This works because of the way
+	 * BRDCFG1 is defined, but it's a bit hackish.
+	 *
+	 * The PHY address for the XAUI card depends on which slot it's in. The
+	 * macros we use imply that the PHY address is based on which FM, but
+	 * that's not true.  On the P4080DS, FM1 could only use XAUI in slot 5,
+	 * and FM2 could only use a XAUI in slot 4.  On the Hydra board, we
+	 * check the actual slot and just use the macros as-is, even though
+	 * the P3041 and P5020 only have one Fman.
+	 */
+	lane = serdes_get_first_lane(XAUI_FM1);
+	if (lane >= 0) {
+		slot = lane_to_slot[lane];
+		if (slot == 1) {
+			/* XAUI card is in slot 1 */
+			clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
+				     BRDCFG1_EMI2_SEL_SLOT1);
+			fm_info_set_phy_address(FM1_10GEC1,
+						CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+		} else {
+			/* XAUI card is in slot 2 */
+			clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
+				     BRDCFG1_EMI2_SEL_SLOT2);
+			fm_info_set_phy_address(FM1_10GEC1,
+						CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
+		}
+	}
+
+	fm_info_set_mdio(FM1_10GEC1,
+			miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/freescale/corenet_ds/eth_p4080.c b/roms/u-boot/board/freescale/corenet_ds/eth_p4080.c
new file mode 100644
index 000000000..df5a69bcb
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/eth_p4080.c
@@ -0,0 +1,489 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fdt_support.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <linux/delay.h>
+
+#include "../common/ngpixis.h"
+#include "../common/fman.h"
+#include <fsl_dtsec.h>
+
+#define EMI_NONE	0xffffffff
+#define EMI_MASK	0xf0000000
+#define EMI1_RGMII	0x0
+#define EMI1_SLOT3	0x80000000	/* bank1 EFGH */
+#define EMI1_SLOT4	0x40000000	/* bank2 ABCD */
+#define EMI1_SLOT5	0xc0000000	/* bank3 ABCD */
+#define EMI2_SLOT4	0x10000000	/* bank2 ABCD */
+#define EMI2_SLOT5	0x30000000	/* bank3 ABCD */
+#define EMI1_MASK	0xc0000000
+#define EMI2_MASK	0x30000000
+
+#define PHY_BASE_ADDR	0x00
+#define PHY_BASE_ADDR_SLOT5	0x10
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static char *mdio_names[16] = {
+	"P4080DS_MDIO0",
+	"P4080DS_MDIO1",
+	NULL,
+	"P4080DS_MDIO3",
+	"P4080DS_MDIO4",
+	NULL, NULL, NULL,
+	"P4080DS_MDIO8",
+	NULL, NULL, NULL,
+	"P4080DS_MDIO12",
+	NULL, NULL, NULL,
+};
+
+/*
+ * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot.
+ */
+static u8 lane_to_slot[] = {
+	1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
+};
+
+static char *p4080ds_mdio_name_for_muxval(u32 muxval)
+{
+	return mdio_names[(muxval & EMI_MASK) >> 28];
+}
+
+struct mii_dev *mii_dev_for_muxval(u32 muxval)
+{
+	struct mii_dev *bus;
+	char *name = p4080ds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	if (phydev->drv->uid == PHY_UID_TN2020) {
+		unsigned long timeout = 1 * 1000; /* 1 seconds */
+		enum srds_prtcl device;
+
+		/*
+		 * Wait for the XAUI to come out of reset.  This is when it
+		 * starts transmitting alignment signals.
+		 */
+		while (--timeout) {
+			int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
+			if (reg < 0) {
+				printf("TN2020: Error reading from PHY at "
+				       "address %u\n", phydev->addr);
+				break;
+			}
+			/*
+			 * Note that we've never actually seen
+			 * MDIO_CTRL1_RESET set to 1.
+			 */
+			if ((reg & MDIO_CTRL1_RESET) == 0)
+				break;
+			udelay(1000);
+		}
+
+		if (!timeout) {
+			printf("TN2020: Timeout waiting for PHY at address %u "
+			       " to reset.\n", phydev->addr);
+		}
+
+		switch (phydev->addr) {
+		case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
+			device = XAUI_FM1;
+			break;
+		case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
+			device = XAUI_FM2;
+			break;
+		default:
+			device = NONE;
+		}
+
+		serdes_reset_rx(device);
+	}
+
+	return 0;
+}
+#endif
+
+struct p4080ds_mdio {
+	u32 muxval;
+	struct mii_dev *realbus;
+};
+
+static void p4080ds_mux_mdio(u32 muxval)
+{
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
+	gpioval |= muxval;
+
+	out_be32(&pgpio->gpdat, gpioval);
+}
+
+static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
+				int regnum)
+{
+	struct p4080ds_mdio *priv = bus->priv;
+
+	p4080ds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				int regnum, u16 value)
+{
+	struct p4080ds_mdio *priv = bus->priv;
+
+	p4080ds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int p4080ds_mdio_reset(struct mii_dev *bus)
+{
+	struct p4080ds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int p4080ds_mdio_init(char *realbusname, u32 muxval)
+{
+	struct p4080ds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate P4080DS MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate P4080DS private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = p4080ds_mdio_read;
+	bus->write = p4080ds_mdio_write;
+	bus->reset = p4080ds_mdio_reset;
+	sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+
+	return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
+				enum fm_port port, int offset)
+{
+	if (mdio_mux[port] == EMI1_RGMII)
+		fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
+
+	if (mdio_mux[port] == EMI1_SLOT3) {
+		int idx = port - FM2_DTSEC1 + 5;
+		char phy[16];
+
+		sprintf(phy, "phy%d_slot3", idx);
+
+		fdt_set_phy_handle(blob, prop, pa, phy);
+	}
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	int i;
+
+	/*
+	 * P4080DS can be configured in many different ways, supporting a number
+	 * of combinations of ethernet devices and phy types.  In order to
+	 * have just one device tree for all of those configurations, we fix up
+	 * the tree here.  By default, the device tree configures FM1 and FM2
+	 * for SGMII, and configures XAUI on both 10G interfaces.  So we have
+	 * a number of different variables to track:
+	 *
+	 * 1) Whether the device is configured at all.  Whichever devices are
+	 *    not enabled should be disabled by setting the "status" property
+	 *    to "disabled".
+	 * 2) What the PHY interface is.  If this is an RGMII connection,
+	 *    we should change the "phy-connection-type" property to
+	 *    "rgmii"
+	 * 3) Which PHY is being used.  Because the MDIO buses are muxed,
+	 *    we need to redirect the "phy-handle" property to point at the
+	 *    PHY on the right slot/bus.
+	 */
+
+	/* We've got six MDIO nodes that may or may not need to exist */
+	fdt_status_disabled_by_alias(fdt, "emi1_slot3");
+	fdt_status_disabled_by_alias(fdt, "emi1_slot4");
+	fdt_status_disabled_by_alias(fdt, "emi1_slot5");
+	fdt_status_disabled_by_alias(fdt, "emi2_slot4");
+	fdt_status_disabled_by_alias(fdt, "emi2_slot5");
+
+	for (i = 0; i < NUM_FM_PORTS; i++) {
+		switch (mdio_mux[i]) {
+		case EMI1_SLOT3:
+			fdt_status_okay_by_alias(fdt, "emi1_slot3");
+			break;
+		case EMI1_SLOT4:
+			fdt_status_okay_by_alias(fdt, "emi1_slot4");
+			break;
+		case EMI1_SLOT5:
+			fdt_status_okay_by_alias(fdt, "emi1_slot5");
+			break;
+		case EMI2_SLOT4:
+			fdt_status_okay_by_alias(fdt, "emi2_slot4");
+			break;
+		case EMI2_SLOT5:
+			fdt_status_okay_by_alias(fdt, "emi2_slot5");
+			break;
+		}
+	}
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	int i;
+	struct fsl_pq_mdio_info dtsec_mdio_info;
+	struct tgec_mdio_info tgec_mdio_info;
+	struct mii_dev *bus;
+
+	/* Initialize the mdio_mux array so we can recognize empty elements */
+	for (i = 0; i < NUM_FM_PORTS; i++)
+		mdio_mux[i] = EMI_NONE;
+
+	/* The first 4 GPIOs are outputs to control MDIO bus muxing */
+	out_be32(&pgpio->gpdir, EMI_MASK);
+
+	dtsec_mdio_info.regs =
+		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_tgec_mdio_init(bis, &tgec_mdio_info);
+
+	/* Register the 6 muxing front-ends to the MDIO buses */
+	p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
+	p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+	p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+	p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+	p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
+	p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
+
+	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+	fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
+	fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
+	fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
+	fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
+	fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
+#endif
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1, lane, slot;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			switch (slot) {
+			case 3:
+				mdio_mux[i] = EMI1_SLOT3;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			case 4:
+				mdio_mux[i] = EMI1_SLOT4;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			case 5:
+				mdio_mux[i] = EMI1_SLOT5;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			};
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			fm_info_set_phy_address(i, 0);
+			mdio_mux[i] = EMI1_RGMII;
+			fm_info_set_mdio(i,
+				mii_dev_for_muxval(mdio_mux[i]));
+			break;
+		default:
+			break;
+		}
+	}
+	bus = mii_dev_for_muxval(EMI1_SLOT5);
+	set_sgmii_phy(bus, FM1_DTSEC1,
+		      CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5);
+
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		int idx = i - FM1_10GEC1, lane, slot;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			lane = serdes_get_first_lane(XAUI_FM1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			switch (slot) {
+			case 4:
+				mdio_mux[i] = EMI2_SLOT4;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			case 5:
+				mdio_mux[i] = EMI2_SLOT5;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			};
+			break;
+		default:
+			break;
+		}
+	}
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+		int idx = i - FM2_DTSEC1, lane, slot;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			switch (slot) {
+			case 3:
+				mdio_mux[i] = EMI1_SLOT3;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			case 4:
+				mdio_mux[i] = EMI1_SLOT4;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			case 5:
+				mdio_mux[i] = EMI1_SLOT5;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			};
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			fm_info_set_phy_address(i, 0);
+			mdio_mux[i] = EMI1_RGMII;
+			fm_info_set_mdio(i,
+				mii_dev_for_muxval(mdio_mux[i]));
+			break;
+		default:
+			break;
+		}
+	}
+
+	bus = mii_dev_for_muxval(EMI1_SLOT3);
+	set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
+	bus = mii_dev_for_muxval(EMI1_SLOT4);
+	set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
+
+	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+		int idx = i - FM2_10GEC1, lane, slot;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			lane = serdes_get_first_lane(XAUI_FM2 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			switch (slot) {
+			case 4:
+				mdio_mux[i] = EMI2_SLOT4;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			case 5:
+				mdio_mux[i] = EMI2_SLOT5;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			};
+			break;
+		default:
+			break;
+		}
+	}
+#endif
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/freescale/corenet_ds/eth_superhydra.c b/roms/u-boot/board/freescale/corenet_ds/eth_superhydra.c
new file mode 100644
index 000000000..de7b692f3
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/eth_superhydra.c
@@ -0,0 +1,783 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ */
+
+/*
+ * This file handles the board muxing between the Fman Ethernet MACs and
+ * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference
+ * board. The RGMII PHYs are the two on-board 1Gb ports.  The SGMII PHYs are
+ * provided by the standard Freescale four-port SGMII riser card.  The 10Gb
+ * XGMII PHYs are provided via the XAUI riser card.  The P5040 has 2 FMans
+ * and 5 1G interfaces and 10G interface per FMan. Based on the options in
+ * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time.
+ *
+ * Muxing is handled via the PIXIS BRDCFG1 register.  The EMI1 bits control
+ * muxing among the RGMII PHYs and the SGMII PHYs.  The value for RGMII is
+ * always the same (0).  The value for SGMII depends on which slot the riser is
+ * inserted in.  The EMI2 bits control muxing for the the XGMII.  Like SGMII,
+ * the value is based on which slot the XAUI is inserted in.
+ *
+ * The SERDES configuration is used to determine where the SGMII and XAUI cards
+ * exist, and also which Fman's MACs are routed to which PHYs.  So for a given
+ * Fman MAC, there is one and only PHY it connects to.  MACs cannot be routed
+ * to PHYs dynamically.
+ *
+ *
+ * This file also updates the device tree in three ways:
+ *
+ * 1) The status of each virtual MDIO node that is referenced by an Ethernet
+ *    node is set to "okay".
+ *
+ * 2) The phy-handle property of each active Ethernet MAC node is set to the
+ *    appropriate PHY node.
+ *
+ * 3) The "mux value" for each virtual MDIO node is set to the correct value,
+ *    if necessary.  Some virtual MDIO nodes do not have configurable mux
+ *    values, so those values are hard-coded in the DTS.  On the HYDRA board,
+ *    the virtual MDIO node for the SGMII card needs to be updated.
+ *
+ * For all this to work, the device tree needs to have the following:
+ *
+ * 1) An alias for each PHY node that an Ethernet node could be routed to.
+ *
+ * 2) An alias for each real and virtual MDIO node that is disabled by default
+ * and might need to be enabled, and also might need to have its mux-value
+ * updated.
+ */
+
+#include <common.h>
+#include <log.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fdt_support.h>
+#include <fsl_dtsec.h>
+
+#include "../common/ngpixis.h"
+#include "../common/fman.h"
+
+#ifdef CONFIG_FMAN_ENET
+
+#define BRDCFG1_EMI1_SEL_MASK	0x70
+#define BRDCFG1_EMI1_SEL_SLOT1	0x10
+#define BRDCFG1_EMI1_SEL_SLOT2	0x20
+#define BRDCFG1_EMI1_SEL_SLOT5	0x30
+#define BRDCFG1_EMI1_SEL_SLOT6	0x40
+#define BRDCFG1_EMI1_SEL_SLOT7	0x50
+#define BRDCFG1_EMI1_SEL_SLOT3	0x60
+#define BRDCFG1_EMI1_SEL_RGMII	0x00
+#define BRDCFG1_EMI1_EN		0x08
+#define BRDCFG1_EMI2_SEL_MASK	0x06
+#define BRDCFG1_EMI2_SEL_SLOT1	0x00
+#define BRDCFG1_EMI2_SEL_SLOT2	0x02
+
+#define BRDCFG2_REG_GPIO_SEL	0x20
+
+/* SGMII */
+#define PHY_BASE_ADDR		0x00
+#define REGNUM			0x00
+#define PORT_NUM_FM1		0x04
+#define PORT_NUM_FM2		0x02
+
+/*
+ * BRDCFG1 mask and value for each MAC
+ *
+ * This array contains the BRDCFG1 values (in mask/val format) that route the
+ * MDIO bus to a particular RGMII or SGMII PHY.
+ */
+static struct {
+	u8 mask;
+	u8 val;
+} mdio_mux[NUM_FM_PORTS];
+
+/*
+ * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot
+ */
+static u8 lane_to_slot[] = {
+	7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0
+};
+
+/*
+ * Set the board muxing for a given MAC
+ *
+ * The MDIO layer calls this function every time it wants to talk to a PHY.
+ */
+void super_hydra_mux_mdio(u8 mask, u8 val)
+{
+	clrsetbits_8(&pixis->brdcfg1, mask, val);
+}
+
+struct super_hydra_mdio {
+	u8 mask;
+	u8 val;
+	struct mii_dev *realbus;
+};
+
+static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
+				int regnum)
+{
+	struct super_hydra_mdio *priv = bus->priv;
+
+	super_hydra_mux_mdio(priv->mask, priv->val);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
+				int regnum, u16 value)
+{
+	struct super_hydra_mdio *priv = bus->priv;
+
+	super_hydra_mux_mdio(priv->mask, priv->val);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int super_hydra_mdio_reset(struct mii_dev *bus)
+{
+	struct super_hydra_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val)
+{
+	struct mii_dev *bus = miiphy_get_dev_by_name(name);
+	struct super_hydra_mdio *priv = bus->priv;
+
+	priv->mask = mask;
+	priv->val = val;
+}
+
+static int super_hydra_mdio_init(char *realbusname, char *fakebusname)
+{
+	struct super_hydra_mdio *hmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate Hydra MDIO bus\n");
+		return -1;
+	}
+
+	hmdio = malloc(sizeof(*hmdio));
+	if (!hmdio) {
+		printf("Failed to allocate Hydra private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = super_hydra_mdio_read;
+	bus->write = super_hydra_mdio_write;
+	bus->reset = super_hydra_mdio_reset;
+	strcpy(bus->name, fakebusname);
+
+	hmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!hmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(hmdio);
+		return -1;
+	}
+
+	bus->priv = hmdio;
+
+	return mdio_register(bus);
+}
+
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) An Fman port
+ *
+ * ... update the phy-handle property of the Ethernet node to point to the
+ * right PHY.  This assumes that we already know the PHY for each port.  That
+ * information is stored in mdio_mux[].
+ *
+ * The offset of the Fman Ethernet node is also passed in for convenience, but
+ * it is not used.
+ *
+ * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
+ * Inside the Fman, "ports" are things that connect to MACs.  We only call them
+ * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
+ * and ports are the same thing.
+ */
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+			      enum fm_port port, int offset)
+{
+	enum srds_prtcl device;
+	int lane, slot, phy;
+	char alias[32];
+
+	/* RGMII and XGMII are already mapped correctly in the DTS */
+
+	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+		device = serdes_device_from_fm_port(port);
+		lane = serdes_get_first_lane(device);
+		slot = lane_to_slot[lane];
+		phy = fm_info_get_phy_address(port);
+
+		sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy);
+		fdt_set_phy_handle(fdt, compat, addr, alias);
+	}
+}
+
+#define PIXIS_SW2_LANE_23_SEL		0x80
+#define PIXIS_SW2_LANE_45_SEL		0x40
+#define PIXIS_SW2_LANE_67_SEL_MASK	0x30
+#define PIXIS_SW2_LANE_67_SEL_5		0x00
+#define PIXIS_SW2_LANE_67_SEL_6		0x20
+#define PIXIS_SW2_LANE_67_SEL_7		0x10
+#define PIXIS_SW2_LANE_8_SEL		0x08
+#define PIXIS_SW2_LANE_1617_SEL		0x04
+#define PIXIS_SW11_LANE_9_SEL		0x04
+/*
+ * Initialize the lane_to_slot[] array.
+ *
+ * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
+ * slots is hard-coded.  On the Hydra board, however, the mapping is controlled
+ * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
+ * initialized.
+ */
+static void initialize_lane_to_slot(void)
+{
+	u8 sw2 = in_8(&PIXIS_SW(2));
+	/* SW11 appears in the programming model as SW9 */
+	u8 sw11 = in_8(&PIXIS_SW(9));
+
+	lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
+	lane_to_slot[3] = lane_to_slot[2];
+
+	lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
+	lane_to_slot[5] = lane_to_slot[4];
+
+	switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
+	case PIXIS_SW2_LANE_67_SEL_5:
+		lane_to_slot[6] = 5;
+		break;
+	case PIXIS_SW2_LANE_67_SEL_6:
+		lane_to_slot[6] = 6;
+		break;
+	case PIXIS_SW2_LANE_67_SEL_7:
+		lane_to_slot[6] = 7;
+		break;
+	}
+	lane_to_slot[7] = lane_to_slot[6];
+
+	lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
+	lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3;
+
+	lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
+	lane_to_slot[17] = lane_to_slot[16];
+}
+
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+/*
+ * Configure the status for the virtual MDIO nodes
+ *
+ * Rather than create the virtual MDIO nodes from scratch for each active
+ * virtual MDIO, we expect the DTS to have the nodes defined already, and we
+ * only enable the ones that are actually active.
+ *
+ * We assume that the DTS already hard-codes the status for all the
+ * virtual MDIO nodes to "disabled", so all we need to do is enable the
+ * active ones.
+ */
+void fdt_fixup_board_enet(void *fdt)
+{
+#ifdef CONFIG_FMAN_ENET
+	enum fm_port i;
+	int lane, slot;
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+			if (lane >= 0) {
+				char alias[32];
+
+				slot = lane_to_slot[lane];
+				sprintf(alias, "hydra_sg_slot%u", slot);
+				fdt_status_okay_by_alias(fdt, alias);
+				debug("Enabled MDIO node %s (slot %i)\n",
+				      alias, slot);
+			}
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			fdt_status_okay_by_alias(fdt, "hydra_rg");
+			debug("Enabled MDIO node hydra_rg\n");
+			break;
+		default:
+			break;
+		}
+	}
+
+	lane = serdes_get_first_lane(XAUI_FM1);
+	if (lane >= 0) {
+		char alias[32];
+
+		slot = lane_to_slot[lane];
+		sprintf(alias, "hydra_xg_slot%u", slot);
+		fdt_status_okay_by_alias(fdt, alias);
+		debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
+	}
+
+#if CONFIG_SYS_NUM_FMAN == 2
+	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+		int idx = i - FM2_DTSEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
+			if (lane >= 0) {
+				char alias[32];
+
+				slot = lane_to_slot[lane];
+				sprintf(alias, "hydra_sg_slot%u", slot);
+				fdt_status_okay_by_alias(fdt, alias);
+				debug("Enabled MDIO node %s (slot %i)\n",
+				      alias, slot);
+			}
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			fdt_status_okay_by_alias(fdt, "hydra_rg");
+			debug("Enabled MDIO node hydra_rg\n");
+			break;
+		default:
+			break;
+		}
+	}
+
+	lane = serdes_get_first_lane(XAUI_FM2);
+	if (lane >= 0) {
+		char alias[32];
+
+		slot = lane_to_slot[lane];
+		sprintf(alias, "hydra_xg_slot%u", slot);
+		fdt_status_okay_by_alias(fdt, alias);
+		debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
+	}
+#endif /* CONFIG_SYS_NUM_FMAN == 2 */
+#endif /* CONFIG_FMAN_ENET */
+}
+
+/*
+ * Mapping of SerDes Protocol to MDIO MUX value and PHY address.
+ *
+ * Fman 1:
+ *       DTSEC1        |   DTSEC2        |   DTSEC3        |   DTSEC4
+ *       Mux     Phy   |   Mux     Phy   |   Mux     Phy   |   Mux     Phy
+ *       Value   Addr  |   Value   Addr  |   Value   Addr  |   Value   Addr
+ * 0x00  2       1c    |   2       1d    |   2       1e    |   2       1f
+ * 0x01                |                 |   6       1c    |
+ * 0x02                |                 |   3       1c    |   3       1d
+ * 0x03  2       1c    |   2       1d    |   2       1e    |   2       1f
+ * 0x04  2       1c    |   2       1d    |   2       1e    |   2       1f
+ * 0x05                |                 |   3       1c    |   3       1d
+ * 0x06  2       1c    |   2       1d    |   2       1e    |   2       1f
+ * 0x07                |                 |   6       1c    |
+ * 0x11  2       1c    |   2       1d    |   2       1e    |   2       1f
+ * 0x2a  2             |                 |   2       1e    |   2       1f
+ * 0x34  6       1c    |   6       1d    |   4       1e    |   4       1f
+ * 0x35                |                 |   3       1c    |   3       1d
+ * 0x36  6       1c    |   6       1d    |   4       1e    |   4       1f
+ *                     |                 |                 |
+ * Fman  2:            |                 |                 |
+ *       DTSEC1        |   DTSEC2        |   DTSEC3        |   DTSEC4
+ *       EMI1          |   EMI1          |   EMI1          |   EMI1
+ *       Mux     Phy   |   Mux     Phy   |   Mux     Phy   |   Mux     Phy
+ *       Value   Addr  |   Value   Addr  |   Value   Addr  |   Value   Addr
+ * 0x00                |                 |   6       1c    |   6       1d
+ * 0x01                |                 |                 |
+ * 0x02                |                 |   6       1c    |   6       1d
+ * 0x03  3       1c    |   3       1d    |   6       1c    |   6       1d
+ * 0x04  3       1c    |   3       1d    |   6       1c    |   6       1d
+ * 0x05                |                 |   6       1c    |   6       1d
+ * 0x06                |                 |   6       1c    |   6       1d
+ * 0x07                |                 |                 |
+ * 0x11                |                 |                 |
+ * 0x2a                |                 |                 |
+ * 0x34                |                 |                 |
+ * 0x35                |                 |                 |
+ * 0x36                |                 |                 |
+ */
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct fsl_pq_mdio_info dtsec_mdio_info;
+	struct tgec_mdio_info tgec_mdio_info;
+	unsigned int i, slot;
+	int lane;
+	struct mii_dev *bus;
+	int qsgmii;
+	int phy_real_addr;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+	printf("Initializing Fman\n");
+
+	initialize_lane_to_slot();
+
+	/* We want to use the PIXIS to configure MUX routing, not GPIOs. */
+	setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
+
+	memset(mdio_mux, 0, sizeof(mdio_mux));
+
+	dtsec_mdio_info.regs =
+		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the real 10G MDIO bus */
+	fm_tgec_mdio_init(bis, &tgec_mdio_info);
+
+	/* Register the three virtual MDIO front-ends */
+	super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
+				"SUPER_HYDRA_RGMII_MDIO");
+	super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
+				"SUPER_HYDRA_FM1_SGMII_MDIO");
+	super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
+				"SUPER_HYDRA_FM2_SGMII_MDIO");
+	super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
+			      "SUPER_HYDRA_FM3_SGMII_MDIO");
+	super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
+				"SUPER_HYDRA_FM1_TGEC_MDIO");
+	super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
+				"SUPER_HYDRA_FM2_TGEC_MDIO");
+
+	/*
+	 * Program the DTSEC PHY addresses assuming that they are all SGMII.
+	 * For any DTSEC that's RGMII, we'll override its PHY address later.
+	 * We assume that DTSEC5 is only used for RGMII.
+	 */
+	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+	fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
+	fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
+	fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
+	fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
+	fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+#endif
+
+	switch (srds_prtcl) {
+	case 0:
+	case 3:
+	case 4:
+	case 6:
+	case 0x11:
+	case 0x2a:
+	case 0x34:
+	case 0x36:
+		fm_info_set_phy_address(FM1_DTSEC3,
+					CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC4,
+					CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+		break;
+	case 1:
+	case 2:
+	case 5:
+	case 7:
+	case 0x35:
+		fm_info_set_phy_address(FM1_DTSEC3,
+					CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC4,
+					CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+		break;
+	default:
+		printf("Fman:  Unsupport SerDes Protocol 0x%02x\n", srds_prtcl);
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
+			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+			      idx + 1, slot);
+			switch (slot) {
+			case 1:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
+						BRDCFG1_EMI1_EN;
+				break;
+			case 2:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
+						BRDCFG1_EMI1_EN;
+				break;
+			case 3:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
+						BRDCFG1_EMI1_EN;
+				break;
+			case 5:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
+						BRDCFG1_EMI1_EN;
+				break;
+			case 6:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
+						BRDCFG1_EMI1_EN;
+				break;
+			case 7:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
+						BRDCFG1_EMI1_EN;
+				break;
+			};
+
+			super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO",
+					mdio_mux[i].mask, mdio_mux[i].val);
+			fm_info_set_mdio(i,
+			miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			/*
+			 * FM1 DTSEC5 is routed via EC1 to the first on-board
+			 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
+			 * second on-board RGMII port. The other DTSECs cannot
+			 * be routed to RGMII.
+			 */
+			debug("FM1@DTSEC%u is RGMII at address %u\n",
+			      idx + 1, 0);
+			fm_info_set_phy_address(i, 0);
+			mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
+			mdio_mux[i].val  = BRDCFG1_EMI1_SEL_RGMII |
+					   BRDCFG1_EMI1_EN;
+			super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
+					mdio_mux[i].mask, mdio_mux[i].val);
+			fm_info_set_mdio(i,
+				miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
+			break;
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
+			break;
+		default:
+			printf("Fman1: DTSEC%u set to unknown interface %i\n",
+			       idx + 1, fm_info_get_enet_if(i));
+			fm_info_set_phy_address(i, 0);
+			break;
+		}
+	}
+
+	bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO");
+	qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM);
+
+	if (qsgmii) {
+		for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) {
+			if (fm_info_get_enet_if(i) ==
+					PHY_INTERFACE_MODE_SGMII) {
+				phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1;
+				fm_info_set_phy_address(i, phy_real_addr);
+			}
+		}
+		switch (srds_prtcl) {
+		case 0x00:
+		case 0x03:
+		case 0x04:
+		case 0x06:
+		case 0x11:
+		case 0x2a:
+		case 0x34:
+		case 0x36:
+			fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2);
+			fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3);
+			break;
+		case 0x01:
+		case 0x02:
+		case 0x05:
+		case 0x07:
+		case 0x35:
+			fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0);
+			fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
+			break;
+		default:
+			break;
+		}
+	}
+
+	/*
+	 * For 10G, we only support one XAUI card per Fman.  If present, then we
+	 * force its routing and never touch those bits again, which removes the
+	 * need for Linux to do any muxing.  This works because of the way
+	 * BRDCFG1 is defined, but it's a bit hackish.
+	 *
+	 * The PHY address for the XAUI card depends on which slot it's in. The
+	 * macros we use imply that the PHY address is based on which FM, but
+	 * that's not true.  On the P4080DS, FM1 could only use XAUI in slot 5,
+	 * and FM2 could only use a XAUI in slot 4.  On the Hydra board, we
+	 * check the actual slot and just use the macros as-is, even though
+	 * the P3041 and P5020 only have one Fman.
+	 */
+	lane = serdes_get_first_lane(XAUI_FM1);
+	if (lane >= 0) {
+		debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
+		mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
+		mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2;
+		super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
+					mdio_mux[i].mask, mdio_mux[i].val);
+	}
+
+	fm_info_set_mdio(FM1_10GEC1,
+			miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO"));
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+		int idx = i - FM2_DTSEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
+			debug("FM2@DTSEC%u expects SGMII in slot %u\n",
+			      idx + 1, slot);
+			switch (slot) {
+			case 1:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
+						BRDCFG1_EMI1_EN;
+				break;
+			case 2:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
+						BRDCFG1_EMI1_EN;
+				break;
+			case 3:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
+						BRDCFG1_EMI1_EN;
+				break;
+			case 5:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
+						BRDCFG1_EMI1_EN;
+				break;
+			case 6:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
+						BRDCFG1_EMI1_EN;
+				break;
+			case 7:
+				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
+						BRDCFG1_EMI1_EN;
+				break;
+			};
+
+			if (i == FM2_DTSEC1 || i == FM2_DTSEC2) {
+				super_hydra_mdio_set_mux(
+						"SUPER_HYDRA_FM3_SGMII_MDIO",
+						mdio_mux[i].mask,
+						mdio_mux[i].val);
+				fm_info_set_mdio(i, miiphy_get_dev_by_name(
+						"SUPER_HYDRA_FM3_SGMII_MDIO"));
+			} else {
+				super_hydra_mdio_set_mux(
+						"SUPER_HYDRA_FM2_SGMII_MDIO",
+						mdio_mux[i].mask,
+						mdio_mux[i].val);
+				fm_info_set_mdio(i, miiphy_get_dev_by_name(
+						"SUPER_HYDRA_FM2_SGMII_MDIO"));
+			}
+
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			/*
+			 * FM1 DTSEC5 is routed via EC1 to the first on-board
+			 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
+			 * second on-board RGMII port. The other DTSECs cannot
+			 * be routed to RGMII.
+			 */
+			debug("FM2@DTSEC%u is RGMII at address %u\n",
+			      idx + 1, 1);
+			fm_info_set_phy_address(i, 1);
+			mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
+			mdio_mux[i].val  = BRDCFG1_EMI1_SEL_RGMII |
+					BRDCFG1_EMI1_EN;
+			super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
+					mdio_mux[i].mask, mdio_mux[i].val);
+			fm_info_set_mdio(i,
+			miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
+			break;
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
+			break;
+		default:
+			printf("Fman2: DTSEC%u set to unknown interface %i\n",
+				idx + 1, fm_info_get_enet_if(i));
+			fm_info_set_phy_address(i, 0);
+			break;
+		}
+	}
+
+	bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO");
+	set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR);
+	bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO");
+	set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR);
+
+	/*
+	 * For 10G, we only support one XAUI card per Fman.  If present, then we
+	 * force its routing and never touch those bits again, which removes the
+	 * need for Linux to do any muxing.  This works because of the way
+	 * BRDCFG1 is defined, but it's a bit hackish.
+	 *
+	 * The PHY address for the XAUI card depends on which slot it's in. The
+	 * macros we use imply that the PHY address is based on which FM, but
+	 * that's not true.  On the P4080DS, FM1 could only use XAUI in slot 5,
+	 * and FM2 could only use a XAUI in slot 4.  On the Hydra board, we
+	 * check the actual slot and just use the macros as-is, even though
+	 * the P3041 and P5020 only have one Fman.
+	 */
+	lane = serdes_get_first_lane(XAUI_FM2);
+	if (lane >= 0) {
+		debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
+		mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
+		mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1;
+		super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
+					mdio_mux[i].mask, mdio_mux[i].val);
+	}
+
+	fm_info_set_mdio(FM2_10GEC1,
+			miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO"));
+
+#endif
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/freescale/corenet_ds/p3041ds_ddr.c b/roms/u-boot/board/freescale/corenet_ds/p3041ds_ddr.c
new file mode 100644
index 000000000..c62d85ccc
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/p3041ds_ddr.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{0, 0, NULL}
+};
diff --git a/roms/u-boot/board/freescale/corenet_ds/p4080ds_ddr.c b/roms/u-boot/board/freescale/corenet_ds/p4080ds_ddr.c
new file mode 100644
index 000000000..346906456
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+#define CONFIG_SYS_DDR_TIMING_3_1200	0x01030000
+#define CONFIG_SYS_DDR_TIMING_0_1200	0xCC550104
+#define CONFIG_SYS_DDR_TIMING_1_1200	0x868FAA45
+#define CONFIG_SYS_DDR_TIMING_2_1200	0x0FB8A912
+#define CONFIG_SYS_DDR_MODE_1_1200	0x00441A40
+#define CONFIG_SYS_DDR_MODE_2_1200	0x00100000
+#define CONFIG_SYS_DDR_INTERVAL_1200	0x12480100
+#define CONFIG_SYS_DDR_CLK_CTRL_1200	0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_1000	0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_1000	0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_1000	0x727DF944
+#define CONFIG_SYS_DDR_TIMING_2_1000	0x0FB088CF
+#define CONFIG_SYS_DDR_MODE_1_1000	0x00441830
+#define CONFIG_SYS_DDR_MODE_2_1000	0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_1000	0x0F3C0100
+#define CONFIG_SYS_DDR_CLK_CTRL_1000	0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_900	0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_900	0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_900	0x616ba844
+#define CONFIG_SYS_DDR_TIMING_2_900	0x0fb088ce
+#define CONFIG_SYS_DDR_MODE_1_900	0x00441620
+#define CONFIG_SYS_DDR_MODE_2_900	0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_900	0x0db60100
+#define CONFIG_SYS_DDR_CLK_CTRL_900	0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_800	0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_800	0xcc330104
+#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b4744
+#define CONFIG_SYS_DDR_TIMING_2_800	0x0fa888cc
+#define CONFIG_SYS_DDR_MODE_1_800	0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800	0x0c300100
+#define CONFIG_SYS_DDR_CLK_CTRL_800	0x02800000
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x000000FF
+#define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
+#define CONFIG_SYS_DDR_CS2_BNDS		0x000000FF
+#define CONFIG_SYS_DDR_CS3_BNDS		0x000000FF
+#define CONFIG_SYS_DDR2_CS0_BNDS	0x000000FF
+#define CONFIG_SYS_DDR2_CS1_BNDS	0x00000000
+#define CONFIG_SYS_DDR2_CS2_BNDS	0x000000FF
+#define CONFIG_SYS_DDR2_CS3_BNDS	0x000000FF
+#define CONFIG_SYS_DDR_CS0_CONFIG	0xA0044202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80004202
+#define CONFIG_SYS_DDR_CS2_CONFIG	0x00000000
+#define CONFIG_SYS_DDR_CS3_CONFIG	0x00000000
+#define CONFIG_SYS_DDR2_CS0_CONFIG	0x80044202
+#define CONFIG_SYS_DDR2_CS1_CONFIG	0x80004202
+#define CONFIG_SYS_DDR2_CS2_CONFIG	0x00000000
+#define CONFIG_SYS_DDR2_CS3_CONFIG	0x00000000
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80004202
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_TIMING_4		0x00000001
+#define CONFIG_SYS_DDR_TIMING_5		0x02401400
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL	0x8675F607
+#define CONFIG_SYS_DDR_SDRAM_CFG	0xE7044000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x24401031
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
+	.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
+	.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
+	.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
+	.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+	.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+	.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+	.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+	.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+	.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{750, 850, &ddr_cfg_regs_800},
+	{850, 950, &ddr_cfg_regs_900},
+	{950, 1050, &ddr_cfg_regs_1000},
+	{1050, 1250, &ddr_cfg_regs_1200},
+	{0, 0, NULL}
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_1[] = {
+	{750, 850, &ddr_cfg_regs_800_2nd},
+	{850, 950, &ddr_cfg_regs_900_2nd},
+	{950, 1050, &ddr_cfg_regs_1000_2nd},
+	{1050, 1250, &ddr_cfg_regs_1200_2nd},
+	{0, 0, NULL}
+};
diff --git a/roms/u-boot/board/freescale/corenet_ds/p5040ds_ddr.c b/roms/u-boot/board/freescale/corenet_ds/p5040ds_ddr.c
new file mode 100644
index 000000000..112733be7
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/p5040ds_ddr.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{0, 0, NULL}
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_1[] = {
+	{0, 0, NULL}
+};
diff --git a/roms/u-boot/board/freescale/corenet_ds/pbi.cfg b/roms/u-boot/board/freescale/corenet_ds/pbi.cfg
new file mode 100644
index 000000000..75dfc3216
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/pbi.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1 as 1MB SRAM
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+09010100 00000000
+09010104 fff0000b
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff00000
+09000d08 81000013
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/roms/u-boot/board/freescale/corenet_ds/rcw_p2041rdb.cfg b/roms/u-boot/board/freescale/corenet_ds/rcw_p2041rdb.cfg
new file mode 100644
index 000000000..8df19dd3f
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/rcw_p2041rdb.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P2041RDB.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+12600000 00000000 241C0000 00000000
+649FA0C1 C3C02000 58000000 40000000
+00000000 00000000 00000000 D0030F07
+00000000 00000000 00000000 00000000
diff --git a/roms/u-boot/board/freescale/corenet_ds/rcw_p3041ds.cfg b/roms/u-boot/board/freescale/corenet_ds/rcw_p3041ds.cfg
new file mode 100644
index 000000000..881315621
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/rcw_p3041ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P3041DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+12600000 00000000 241C0000 00000000
+D8984A01 03002000 58000000 41000000
+00000000 00000000 00000000 10070000
+00000000 00000000 00000000 00000000
diff --git a/roms/u-boot/board/freescale/corenet_ds/rcw_p4080ds.cfg b/roms/u-boot/board/freescale/corenet_ds/rcw_p4080ds.cfg
new file mode 100644
index 000000000..6a2633959
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/rcw_p4080ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P4080DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+105a0000 00000000 1e1e181e 0000cccc
+58400000 3c3c2000 58000000 e1000000
+00000000 00000000 00000000 008b6000
+00000000 00000000 00000000 00000000
diff --git a/roms/u-boot/board/freescale/corenet_ds/rcw_p5040ds.cfg b/roms/u-boot/board/freescale/corenet_ds/rcw_p5040ds.cfg
new file mode 100644
index 000000000..82fa7417d
--- /dev/null
+++ b/roms/u-boot/board/freescale/corenet_ds/rcw_p5040ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P5040DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+0c580000 00000000 22121200 00000000
+089c4400 00283000 58000000 61000000
+00000000 00000000 00000000 10070000
+00000000 00000000 00000000 00000000
diff --git a/roms/u-boot/board/freescale/imx8mm_evk/Kconfig b/roms/u-boot/board/freescale/imx8mm_evk/Kconfig
new file mode 100644
index 000000000..299691a61
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mm_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MM_EVK
+
+config SYS_BOARD
+	default "imx8mm_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8mm_evk"
+
+endif
diff --git a/roms/u-boot/board/freescale/imx8mm_evk/MAINTAINERS b/roms/u-boot/board/freescale/imx8mm_evk/MAINTAINERS
new file mode 100644
index 000000000..b031bb067
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mm_evk/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8MM EVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/imx8mm_evk/
+F:	include/configs/imx8mm_evk.h
+F:	configs/imx8mm_evk_defconfig
diff --git a/roms/u-boot/board/freescale/imx8mm_evk/Makefile b/roms/u-boot/board/freescale/imx8mm_evk/Makefile
new file mode 100644
index 000000000..1db7b62ca
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mm_evk/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mm_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/roms/u-boot/board/freescale/imx8mm_evk/imx8mm_evk.c b/roms/u-boot/board/freescale/imx8mm_evk/imx8mm_evk.c
new file mode 100644
index 000000000..ab55135a9
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mm_evk/imx8mm_evk.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_FEC_MXC))
+		setup_fec();
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "EVK");
+	env_set("board_rev", "iMX8MM");
+#endif
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg b/roms/u-boot/board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg
new file mode 100644
index 000000000..b89092a55
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#define __ASSEMBLY__
+
+BOOT_FROM	sd
+LOADER		mkimage.flash.mkimage	0x7E1000
diff --git a/roms/u-boot/board/freescale/imx8mm_evk/lpddr4_timing.c b/roms/u-boot/board/freescale/imx8mm_evk/lpddr4_timing.c
new file mode 100644
index 000000000..4373ca624
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mm_evk/lpddr4_timing.c
@@ -0,0 +1,1848 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/* Initialize DDRC registers */
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400020, 0x223 },
+	{ 0x3d400024, 0x16e3600 },
+	{ 0x3d400064, 0x5b00d2 },
+	{ 0x3d4000d0, 0xc00305ba },
+	{ 0x3d4000d4, 0x940000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000ec, 0x16004d },
+	{ 0x3d400100, 0x191e1920 },
+	{ 0x3d400104, 0x60630 },
+	{ 0x3d40010c, 0xb0b000 },
+	{ 0x3d400110, 0xe04080e },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x401 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0xd8 },
+	{ 0x3d400144, 0x96004b },
+	{ 0x3d400180, 0x2ee0017 },
+	{ 0x3d400184, 0x2605b8e },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+
+	/* performance setting */
+	{ 0x3d400250, 0x29001701 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+
+	/* P1: 400mts */
+	{ 0x3d402020, 0x21 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020ec, 0x16004d },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+
+	/* p2: 100mts */
+	{ 0x3d403020, 0x21 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x310000 },
+	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030ec, 0x16004d },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+
+	/* default boot point */
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x220024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0xa },
+	{ 0x220056, 0xa },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x2ee },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x1200c7, 0x21 },
+	{ 0x2200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200ca, 0x24 },
+	{ 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xf },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a7, 0x0 },
+	{ 0x900a8, 0x790 },
+	{ 0x900a9, 0x11a },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x7b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x0 },
+	{ 0x900b1, 0x7c8 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xc },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x0 },
+	{ 0x90169, 0x8 },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x448 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
+	{ 0x9016e, 0x7c0 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x7c8 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x5d },
+	{ 0x2000c, 0xbb },
+	{ 0x2000d, 0x753 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x2003a, 0x2 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
diff --git a/roms/u-boot/board/freescale/imx8mm_evk/spl.c b/roms/u-boot/board/freescale/imx8mm_evk/spl.c
new file mode 100644
index 000000000..4ef7f6f18
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mm_evk/spl.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/pmic.h>
+#include <power/pca9450.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+static void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+static int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pca9450@25", &dev);
+	if (ret == -ENODEV) {
+		puts("No pmic\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
+
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+	/* Buck 1 DVS control through PMIC_STBY_REQ */
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+	/* Set DVS1 to 0.8v for suspend */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
+
+	/* increase VDD_DRAM to 0.95v for 3Ghz DDR */
+	pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
+
+	/* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
+	pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
+
+	/* set VDD_SNVS_0V8 from default 0.85V */
+	pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
+
+	/* set WDOG_B_CFG to cold reset */
+	pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+
+	arch_cpu_init();
+
+	init_uart_clk(1);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0) {
+		printf("Failed to find clock node. Check device tree\n");
+		hang();
+	}
+
+	enable_tzc380();
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/freescale/imx8mn_evk/Kconfig b/roms/u-boot/board/freescale/imx8mn_evk/Kconfig
new file mode 100644
index 000000000..478f4ed66
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mn_evk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK
+
+config SYS_BOARD
+	default "imx8mn_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8mn_evk"
+
+config IMX8MN_LOW_DRIVE_MODE
+	bool "Enable the low drive mode of iMX8MN on EVK board"
+	default n
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/imx8mn_evk/MAINTAINERS b/roms/u-boot/board/freescale/imx8mn_evk/MAINTAINERS
new file mode 100644
index 000000000..6d110ccf2
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mn_evk/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX8MN EVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/imx8mn_evk/
+F:	include/configs/imx8mn_evk.h
+F:	configs/imx8mn_ddr4_evk_defconfig
+F:	configs/imx8mn_evk_defconfig
diff --git a/roms/u-boot/board/freescale/imx8mn_evk/Makefile b/roms/u-boot/board/freescale/imx8mn_evk/Makefile
new file mode 100644
index 000000000..42d117972
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mn_evk/Makefile
@@ -0,0 +1,18 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mn_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_ld.o
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing_ld.o
+else
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
+endif
+endif
diff --git a/roms/u-boot/board/freescale/imx8mn_evk/ddr4_timing.c b/roms/u-boot/board/freescale/imx8mn_evk/ddr4_timing.c
new file mode 100644
index 000000000..f1509e215
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mn_evk/ddr4_timing.c
@@ -0,0 +1,1055 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400000, 0x81040010 },
+	{ 0x3d400030, 0x20 },
+	{ 0x3d400034, 0x221306 },
+	{ 0x3d400050, 0x210070 },
+	{ 0x3d400054, 0x10008 },
+	{ 0x3d400060, 0x0 },
+	{ 0x3d400064, 0x92014a },
+	{ 0x3d4000c0, 0x0 },
+	{ 0x3d4000c4, 0x1000 },
+	{ 0x3d4000d0, 0xc0030126 },
+	{ 0x3d4000d4, 0x770000 },
+	{ 0x3d4000dc, 0x8340105 },
+	{ 0x3d4000e0, 0x180200 },
+	{ 0x3d4000e4, 0x110000 },
+	{ 0x3d4000e8, 0x2000600 },
+	{ 0x3d4000ec, 0x810 },
+	{ 0x3d4000f0, 0x20 },
+	{ 0x3d4000f4, 0xec7 },
+	{ 0x3d400100, 0x11122914 },
+	{ 0x3d400104, 0x4051c },
+	{ 0x3d400108, 0x608050d },
+	{ 0x3d40010c, 0x400c },
+	{ 0x3d400110, 0x8030409 },
+	{ 0x3d400114, 0x6060403 },
+	{ 0x3d40011c, 0x606 },
+	{ 0x3d400120, 0x7070d0c },
+	{ 0x3d400124, 0x2040a },
+	{ 0x3d40012c, 0x1809010e },
+	{ 0x3d400130, 0x8 },
+	{ 0x3d40013c, 0x0 },
+	{ 0x3d400180, 0x1000040 },
+	{ 0x3d400184, 0x493e },
+	{ 0x3d400190, 0x38b8207 },
+	{ 0x3d400194, 0x2020303 },
+	{ 0x3d400198, 0x7f04011 },
+	{ 0x3d40019c, 0xb0 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0x48005a },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x1 },
+	{ 0x3d4001b4, 0xb07 },
+	{ 0x3d4001b8, 0x4 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d400200, 0x3f1f },
+	{ 0x3d400204, 0x3f0909 },
+	{ 0x3d400208, 0x700 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf07 },
+	{ 0x3d400220, 0x3f01 },
+	{ 0x3d400240, 0x6000610 },
+	{ 0x3d400244, 0x1323 },
+	{ 0x3d400400, 0x100 },
+
+	/* performance setting */
+	{ 0x3d400250, 0x00001f05 },
+	{ 0x3d400254, 0x1f },
+	{ 0x3d400264, 0x900003ff },
+	{ 0x3d40026c, 0x200003ff },
+	{ 0x3d400494, 0x01000e00 },
+	{ 0x3d400498, 0x03ff0000 },
+	{ 0x3d40049c, 0x01000e00 },
+	{ 0x3d4004a0, 0x03ff0000 },
+
+	{ 0x3d402050, 0x210070 },
+	{ 0x3d402064, 0x400093 },
+	{ 0x3d4020dc, 0x105 },
+	{ 0x3d4020e0, 0x0 },
+	{ 0x3d4020e8, 0x2000600 },
+	{ 0x3d4020ec, 0x10 },
+	{ 0x3d402100, 0xb081209 },
+	{ 0x3d402104, 0x2020d },
+	{ 0x3d402108, 0x5050309 },
+	{ 0x3d40210c, 0x400c },
+	{ 0x3d402110, 0x5030206 },
+	{ 0x3d402114, 0x3030202 },
+	{ 0x3d40211c, 0x303 },
+	{ 0x3d402120, 0x4040d06 },
+	{ 0x3d402124, 0x20208 },
+	{ 0x3d40212c, 0x1205010e },
+	{ 0x3d402130, 0x8 },
+	{ 0x3d40213c, 0x0 },
+	{ 0x3d402180, 0x1000040 },
+	{ 0x3d402190, 0x3848204 },
+	{ 0x3d402194, 0x2020303 },
+	{ 0x3d4021b4, 0x404 },
+	{ 0x3d4021b8, 0x4 },
+	{ 0x3d402240, 0x6000600 },
+	{ 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x1005f, 0x2fd },
+	{ 0x1015f, 0x2fd },
+	{ 0x1105f, 0x2fd },
+	{ 0x1115f, 0x2fd },
+	{ 0x11005f, 0x2fd },
+	{ 0x11015f, 0x2fd },
+	{ 0x11105f, 0x2fd },
+	{ 0x11115f, 0x2fd },
+	{ 0x55, 0x355 },
+	{ 0x1055, 0x355 },
+	{ 0x2055, 0x355 },
+	{ 0x3055, 0x355 },
+	{ 0x4055, 0x55 },
+	{ 0x5055, 0x55 },
+	{ 0x6055, 0x355 },
+	{ 0x7055, 0x355 },
+	{ 0x8055, 0x355 },
+	{ 0x9055, 0x355 },
+	{ 0x200c5, 0xa },
+	{ 0x1200c5, 0x6 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x1 },
+	{ 0x20024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x6 },
+	{ 0x120056, 0xa },
+	{ 0x1004d, 0x1a },
+	{ 0x1014d, 0x1a },
+	{ 0x1104d, 0x1a },
+	{ 0x1114d, 0x1a },
+	{ 0x11004d, 0x1a },
+	{ 0x11014d, 0x1a },
+	{ 0x11104d, 0x1a },
+	{ 0x11114d, 0x1a },
+	{ 0x10049, 0xe38 },
+	{ 0x10149, 0xe38 },
+	{ 0x11049, 0xe38 },
+	{ 0x11149, 0xe38 },
+	{ 0x110049, 0xe38 },
+	{ 0x110149, 0xe38 },
+	{ 0x111049, 0xe38 },
+	{ 0x111149, 0xe38 },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x2 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x258 },
+	{ 0x120008, 0x10a },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x268 },
+	{ 0x10043, 0x5b1 },
+	{ 0x10143, 0x5b1 },
+	{ 0x11043, 0x5b1 },
+	{ 0x11143, 0x5b1 },
+	{ 0x1200b2, 0x268 },
+	{ 0x110043, 0x5b1 },
+	{ 0x110143, 0x5b1 },
+	{ 0x111043, 0x5b1 },
+	{ 0x111143, 0x5b1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x20019, 0x5 },
+	{ 0x120019, 0x5 },
+	{ 0x200f0, 0x5555 },
+	{ 0x200f1, 0x5555 },
+	{ 0x200f2, 0x5555 },
+	{ 0x200f3, 0x5555 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x5555 },
+	{ 0x200f6, 0x5555 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x2005b, 0x7529 },
+	{ 0x2005c, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x200cc, 0x1f7 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x1200cc, 0x1f7 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2, 0x0},
+	{0x1200b2, 0x0},
+	{0x2200b2, 0x0},
+	{0x0200cb, 0x0},
+	{0x010043, 0x0},
+	{0x110043, 0x0},
+	{0x210043, 0x0},
+	{0x010143, 0x0},
+	{0x110143, 0x0},
+	{0x210143, 0x0},
+	{0x011043, 0x0},
+	{0x111043, 0x0},
+	{0x211043, 0x0},
+	{0x011143, 0x0},
+	{0x111143, 0x0},
+	{0x211143, 0x0},
+	{0x000080, 0x0},
+	{0x100080, 0x0},
+	{0x200080, 0x0},
+	{0x001080, 0x0},
+	{0x101080, 0x0},
+	{0x201080, 0x0},
+	{0x002080, 0x0},
+	{0x102080, 0x0},
+	{0x202080, 0x0},
+	{0x003080, 0x0},
+	{0x103080, 0x0},
+	{0x203080, 0x0},
+	{0x004080, 0x0},
+	{0x104080, 0x0},
+	{0x204080, 0x0},
+	{0x005080, 0x0},
+	{0x105080, 0x0},
+	{0x205080, 0x0},
+	{0x006080, 0x0},
+	{0x106080, 0x0},
+	{0x206080, 0x0},
+	{0x007080, 0x0},
+	{0x107080, 0x0},
+	{0x207080, 0x0},
+	{0x008080, 0x0},
+	{0x108080, 0x0},
+	{0x208080, 0x0},
+	{0x009080, 0x0},
+	{0x109080, 0x0},
+	{0x209080, 0x0},
+	{0x010080, 0x0},
+	{0x110080, 0x0},
+	{0x210080, 0x0},
+	{0x010180, 0x0},
+	{0x110180, 0x0},
+	{0x210180, 0x0},
+	{0x010081, 0x0},
+	{0x110081, 0x0},
+	{0x210081, 0x0},
+	{0x010181, 0x0},
+	{0x110181, 0x0},
+	{0x210181, 0x0},
+	{0x010082, 0x0},
+	{0x110082, 0x0},
+	{0x210082, 0x0},
+	{0x010182, 0x0},
+	{0x110182, 0x0},
+	{0x210182, 0x0},
+	{0x010083, 0x0},
+	{0x110083, 0x0},
+	{0x210083, 0x0},
+	{0x010183, 0x0},
+	{0x110183, 0x0},
+	{0x210183, 0x0},
+	{0x011080, 0x0},
+	{0x111080, 0x0},
+	{0x211080, 0x0},
+	{0x011180, 0x0},
+	{0x111180, 0x0},
+	{0x211180, 0x0},
+	{0x011081, 0x0},
+	{0x111081, 0x0},
+	{0x211081, 0x0},
+	{0x011181, 0x0},
+	{0x111181, 0x0},
+	{0x211181, 0x0},
+	{0x011082, 0x0},
+	{0x111082, 0x0},
+	{0x211082, 0x0},
+	{0x011182, 0x0},
+	{0x111182, 0x0},
+	{0x211182, 0x0},
+	{0x011083, 0x0},
+	{0x111083, 0x0},
+	{0x211083, 0x0},
+	{0x011183, 0x0},
+	{0x111183, 0x0},
+	{0x211183, 0x0},
+	{0x0100d0, 0x0},
+	{0x1100d0, 0x0},
+	{0x2100d0, 0x0},
+	{0x0101d0, 0x0},
+	{0x1101d0, 0x0},
+	{0x2101d0, 0x0},
+	{0x0100d1, 0x0},
+	{0x1100d1, 0x0},
+	{0x2100d1, 0x0},
+	{0x0101d1, 0x0},
+	{0x1101d1, 0x0},
+	{0x2101d1, 0x0},
+	{0x0100d2, 0x0},
+	{0x1100d2, 0x0},
+	{0x2100d2, 0x0},
+	{0x0101d2, 0x0},
+	{0x1101d2, 0x0},
+	{0x2101d2, 0x0},
+	{0x0100d3, 0x0},
+	{0x1100d3, 0x0},
+	{0x2100d3, 0x0},
+	{0x0101d3, 0x0},
+	{0x1101d3, 0x0},
+	{0x2101d3, 0x0},
+	{0x0110d0, 0x0},
+	{0x1110d0, 0x0},
+	{0x2110d0, 0x0},
+	{0x0111d0, 0x0},
+	{0x1111d0, 0x0},
+	{0x2111d0, 0x0},
+	{0x0110d1, 0x0},
+	{0x1110d1, 0x0},
+	{0x2110d1, 0x0},
+	{0x0111d1, 0x0},
+	{0x1111d1, 0x0},
+	{0x2111d1, 0x0},
+	{0x0110d2, 0x0},
+	{0x1110d2, 0x0},
+	{0x2110d2, 0x0},
+	{0x0111d2, 0x0},
+	{0x1111d2, 0x0},
+	{0x2111d2, 0x0},
+	{0x0110d3, 0x0},
+	{0x1110d3, 0x0},
+	{0x2110d3, 0x0},
+	{0x0111d3, 0x0},
+	{0x1111d3, 0x0},
+	{0x2111d3, 0x0},
+	{0x010068, 0x0},
+	{0x010168, 0x0},
+	{0x010268, 0x0},
+	{0x010368, 0x0},
+	{0x010468, 0x0},
+	{0x010568, 0x0},
+	{0x010668, 0x0},
+	{0x010768, 0x0},
+	{0x010868, 0x0},
+	{0x010069, 0x0},
+	{0x010169, 0x0},
+	{0x010269, 0x0},
+	{0x010369, 0x0},
+	{0x010469, 0x0},
+	{0x010569, 0x0},
+	{0x010669, 0x0},
+	{0x010769, 0x0},
+	{0x010869, 0x0},
+	{0x01006a, 0x0},
+	{0x01016a, 0x0},
+	{0x01026a, 0x0},
+	{0x01036a, 0x0},
+	{0x01046a, 0x0},
+	{0x01056a, 0x0},
+	{0x01066a, 0x0},
+	{0x01076a, 0x0},
+	{0x01086a, 0x0},
+	{0x01006b, 0x0},
+	{0x01016b, 0x0},
+	{0x01026b, 0x0},
+	{0x01036b, 0x0},
+	{0x01046b, 0x0},
+	{0x01056b, 0x0},
+	{0x01066b, 0x0},
+	{0x01076b, 0x0},
+	{0x01086b, 0x0},
+	{0x011068, 0x0},
+	{0x011168, 0x0},
+	{0x011268, 0x0},
+	{0x011368, 0x0},
+	{0x011468, 0x0},
+	{0x011568, 0x0},
+	{0x011668, 0x0},
+	{0x011768, 0x0},
+	{0x011868, 0x0},
+	{0x011069, 0x0},
+	{0x011169, 0x0},
+	{0x011269, 0x0},
+	{0x011369, 0x0},
+	{0x011469, 0x0},
+	{0x011569, 0x0},
+	{0x011669, 0x0},
+	{0x011769, 0x0},
+	{0x011869, 0x0},
+	{0x01106a, 0x0},
+	{0x01116a, 0x0},
+	{0x01126a, 0x0},
+	{0x01136a, 0x0},
+	{0x01146a, 0x0},
+	{0x01156a, 0x0},
+	{0x01166a, 0x0},
+	{0x01176a, 0x0},
+	{0x01186a, 0x0},
+	{0x01106b, 0x0},
+	{0x01116b, 0x0},
+	{0x01126b, 0x0},
+	{0x01136b, 0x0},
+	{0x01146b, 0x0},
+	{0x01156b, 0x0},
+	{0x01166b, 0x0},
+	{0x01176b, 0x0},
+	{0x01186b, 0x0},
+	{0x01008c, 0x0},
+	{0x11008c, 0x0},
+	{0x21008c, 0x0},
+	{0x01018c, 0x0},
+	{0x11018c, 0x0},
+	{0x21018c, 0x0},
+	{0x01008d, 0x0},
+	{0x11008d, 0x0},
+	{0x21008d, 0x0},
+	{0x01018d, 0x0},
+	{0x11018d, 0x0},
+	{0x21018d, 0x0},
+	{0x01008e, 0x0},
+	{0x11008e, 0x0},
+	{0x21008e, 0x0},
+	{0x01018e, 0x0},
+	{0x11018e, 0x0},
+	{0x21018e, 0x0},
+	{0x01008f, 0x0},
+	{0x11008f, 0x0},
+	{0x21008f, 0x0},
+	{0x01018f, 0x0},
+	{0x11018f, 0x0},
+	{0x21018f, 0x0},
+	{0x01108c, 0x0},
+	{0x11108c, 0x0},
+	{0x21108c, 0x0},
+	{0x01118c, 0x0},
+	{0x11118c, 0x0},
+	{0x21118c, 0x0},
+	{0x01108d, 0x0},
+	{0x11108d, 0x0},
+	{0x21108d, 0x0},
+	{0x01118d, 0x0},
+	{0x11118d, 0x0},
+	{0x21118d, 0x0},
+	{0x01108e, 0x0},
+	{0x11108e, 0x0},
+	{0x21108e, 0x0},
+	{0x01118e, 0x0},
+	{0x11118e, 0x0},
+	{0x21118e, 0x0},
+	{0x01108f, 0x0},
+	{0x11108f, 0x0},
+	{0x21108f, 0x0},
+	{0x01118f, 0x0},
+	{0x11118f, 0x0},
+	{0x21118f, 0x0},
+	{0x0100c0, 0x0},
+	{0x1100c0, 0x0},
+	{0x2100c0, 0x0},
+	{0x0101c0, 0x0},
+	{0x1101c0, 0x0},
+	{0x2101c0, 0x0},
+	{0x0102c0, 0x0},
+	{0x1102c0, 0x0},
+	{0x2102c0, 0x0},
+	{0x0103c0, 0x0},
+	{0x1103c0, 0x0},
+	{0x2103c0, 0x0},
+	{0x0104c0, 0x0},
+	{0x1104c0, 0x0},
+	{0x2104c0, 0x0},
+	{0x0105c0, 0x0},
+	{0x1105c0, 0x0},
+	{0x2105c0, 0x0},
+	{0x0106c0, 0x0},
+	{0x1106c0, 0x0},
+	{0x2106c0, 0x0},
+	{0x0107c0, 0x0},
+	{0x1107c0, 0x0},
+	{0x2107c0, 0x0},
+	{0x0108c0, 0x0},
+	{0x1108c0, 0x0},
+	{0x2108c0, 0x0},
+	{0x0100c1, 0x0},
+	{0x1100c1, 0x0},
+	{0x2100c1, 0x0},
+	{0x0101c1, 0x0},
+	{0x1101c1, 0x0},
+	{0x2101c1, 0x0},
+	{0x0102c1, 0x0},
+	{0x1102c1, 0x0},
+	{0x2102c1, 0x0},
+	{0x0103c1, 0x0},
+	{0x1103c1, 0x0},
+	{0x2103c1, 0x0},
+	{0x0104c1, 0x0},
+	{0x1104c1, 0x0},
+	{0x2104c1, 0x0},
+	{0x0105c1, 0x0},
+	{0x1105c1, 0x0},
+	{0x2105c1, 0x0},
+	{0x0106c1, 0x0},
+	{0x1106c1, 0x0},
+	{0x2106c1, 0x0},
+	{0x0107c1, 0x0},
+	{0x1107c1, 0x0},
+	{0x2107c1, 0x0},
+	{0x0108c1, 0x0},
+	{0x1108c1, 0x0},
+	{0x2108c1, 0x0},
+	{0x0100c2, 0x0},
+	{0x1100c2, 0x0},
+	{0x2100c2, 0x0},
+	{0x0101c2, 0x0},
+	{0x1101c2, 0x0},
+	{0x2101c2, 0x0},
+	{0x0102c2, 0x0},
+	{0x1102c2, 0x0},
+	{0x2102c2, 0x0},
+	{0x0103c2, 0x0},
+	{0x1103c2, 0x0},
+	{0x2103c2, 0x0},
+	{0x0104c2, 0x0},
+	{0x1104c2, 0x0},
+	{0x2104c2, 0x0},
+	{0x0105c2, 0x0},
+	{0x1105c2, 0x0},
+	{0x2105c2, 0x0},
+	{0x0106c2, 0x0},
+	{0x1106c2, 0x0},
+	{0x2106c2, 0x0},
+	{0x0107c2, 0x0},
+	{0x1107c2, 0x0},
+	{0x2107c2, 0x0},
+	{0x0108c2, 0x0},
+	{0x1108c2, 0x0},
+	{0x2108c2, 0x0},
+	{0x0100c3, 0x0},
+	{0x1100c3, 0x0},
+	{0x2100c3, 0x0},
+	{0x0101c3, 0x0},
+	{0x1101c3, 0x0},
+	{0x2101c3, 0x0},
+	{0x0102c3, 0x0},
+	{0x1102c3, 0x0},
+	{0x2102c3, 0x0},
+	{0x0103c3, 0x0},
+	{0x1103c3, 0x0},
+	{0x2103c3, 0x0},
+	{0x0104c3, 0x0},
+	{0x1104c3, 0x0},
+	{0x2104c3, 0x0},
+	{0x0105c3, 0x0},
+	{0x1105c3, 0x0},
+	{0x2105c3, 0x0},
+	{0x0106c3, 0x0},
+	{0x1106c3, 0x0},
+	{0x2106c3, 0x0},
+	{0x0107c3, 0x0},
+	{0x1107c3, 0x0},
+	{0x2107c3, 0x0},
+	{0x0108c3, 0x0},
+	{0x1108c3, 0x0},
+	{0x2108c3, 0x0},
+	{0x0110c0, 0x0},
+	{0x1110c0, 0x0},
+	{0x2110c0, 0x0},
+	{0x0111c0, 0x0},
+	{0x1111c0, 0x0},
+	{0x2111c0, 0x0},
+	{0x0112c0, 0x0},
+	{0x1112c0, 0x0},
+	{0x2112c0, 0x0},
+	{0x0113c0, 0x0},
+	{0x1113c0, 0x0},
+	{0x2113c0, 0x0},
+	{0x0114c0, 0x0},
+	{0x1114c0, 0x0},
+	{0x2114c0, 0x0},
+	{0x0115c0, 0x0},
+	{0x1115c0, 0x0},
+	{0x2115c0, 0x0},
+	{0x0116c0, 0x0},
+	{0x1116c0, 0x0},
+	{0x2116c0, 0x0},
+	{0x0117c0, 0x0},
+	{0x1117c0, 0x0},
+	{0x2117c0, 0x0},
+	{0x0118c0, 0x0},
+	{0x1118c0, 0x0},
+	{0x2118c0, 0x0},
+	{0x0110c1, 0x0},
+	{0x1110c1, 0x0},
+	{0x2110c1, 0x0},
+	{0x0111c1, 0x0},
+	{0x1111c1, 0x0},
+	{0x2111c1, 0x0},
+	{0x0112c1, 0x0},
+	{0x1112c1, 0x0},
+	{0x2112c1, 0x0},
+	{0x0113c1, 0x0},
+	{0x1113c1, 0x0},
+	{0x2113c1, 0x0},
+	{0x0114c1, 0x0},
+	{0x1114c1, 0x0},
+	{0x2114c1, 0x0},
+	{0x0115c1, 0x0},
+	{0x1115c1, 0x0},
+	{0x2115c1, 0x0},
+	{0x0116c1, 0x0},
+	{0x1116c1, 0x0},
+	{0x2116c1, 0x0},
+	{0x0117c1, 0x0},
+	{0x1117c1, 0x0},
+	{0x2117c1, 0x0},
+	{0x0118c1, 0x0},
+	{0x1118c1, 0x0},
+	{0x2118c1, 0x0},
+	{0x0110c2, 0x0},
+	{0x1110c2, 0x0},
+	{0x2110c2, 0x0},
+	{0x0111c2, 0x0},
+	{0x1111c2, 0x0},
+	{0x2111c2, 0x0},
+	{0x0112c2, 0x0},
+	{0x1112c2, 0x0},
+	{0x2112c2, 0x0},
+	{0x0113c2, 0x0},
+	{0x1113c2, 0x0},
+	{0x2113c2, 0x0},
+	{0x0114c2, 0x0},
+	{0x1114c2, 0x0},
+	{0x2114c2, 0x0},
+	{0x0115c2, 0x0},
+	{0x1115c2, 0x0},
+	{0x2115c2, 0x0},
+	{0x0116c2, 0x0},
+	{0x1116c2, 0x0},
+	{0x2116c2, 0x0},
+	{0x0117c2, 0x0},
+	{0x1117c2, 0x0},
+	{0x2117c2, 0x0},
+	{0x0118c2, 0x0},
+	{0x1118c2, 0x0},
+	{0x2118c2, 0x0},
+	{0x0110c3, 0x0},
+	{0x1110c3, 0x0},
+	{0x2110c3, 0x0},
+	{0x0111c3, 0x0},
+	{0x1111c3, 0x0},
+	{0x2111c3, 0x0},
+	{0x0112c3, 0x0},
+	{0x1112c3, 0x0},
+	{0x2112c3, 0x0},
+	{0x0113c3, 0x0},
+	{0x1113c3, 0x0},
+	{0x2113c3, 0x0},
+	{0x0114c3, 0x0},
+	{0x1114c3, 0x0},
+	{0x2114c3, 0x0},
+	{0x0115c3, 0x0},
+	{0x1115c3, 0x0},
+	{0x2115c3, 0x0},
+	{0x0116c3, 0x0},
+	{0x1116c3, 0x0},
+	{0x2116c3, 0x0},
+	{0x0117c3, 0x0},
+	{0x1117c3, 0x0},
+	{0x2117c3, 0x0},
+	{0x0118c3, 0x0},
+	{0x1118c3, 0x0},
+	{0x2118c3, 0x0},
+	{0x010020, 0x0},
+	{0x110020, 0x0},
+	{0x210020, 0x0},
+	{0x011020, 0x0},
+	{0x111020, 0x0},
+	{0x211020, 0x0},
+	{0x02007d, 0x0},
+	{0x12007d, 0x0},
+	{0x22007d, 0x0},
+	{0x010040, 0x0},
+	{0x010140, 0x0},
+	{0x010240, 0x0},
+	{0x010340, 0x0},
+	{0x010440, 0x0},
+	{0x010540, 0x0},
+	{0x010640, 0x0},
+	{0x010740, 0x0},
+	{0x010840, 0x0},
+	{0x010030, 0x0},
+	{0x010130, 0x0},
+	{0x010230, 0x0},
+	{0x010330, 0x0},
+	{0x010430, 0x0},
+	{0x010530, 0x0},
+	{0x010630, 0x0},
+	{0x010730, 0x0},
+	{0x010830, 0x0},
+	{0x011040, 0x0},
+	{0x011140, 0x0},
+	{0x011240, 0x0},
+	{0x011340, 0x0},
+	{0x011440, 0x0},
+	{0x011540, 0x0},
+	{0x011640, 0x0},
+	{0x011740, 0x0},
+	{0x011840, 0x0},
+	{0x011030, 0x0},
+	{0x011130, 0x0},
+	{0x011230, 0x0},
+	{0x011330, 0x0},
+	{0x011430, 0x0},
+	{0x011530, 0x0},
+	{0x011630, 0x0},
+	{0x011730, 0x0},
+	{0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x834 },
+	{ 0x54030, 0x105 },
+	{ 0x54031, 0x18 },
+	{ 0x54032, 0x200 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x810 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x42a },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x1 },
+	{ 0x54030, 0x105 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x10 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x61 },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400e, 0x1f7f },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x834 },
+	{ 0x54030, 0x105 },
+	{ 0x54031, 0x18 },
+	{ 0x54032, 0x200 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x810 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x2 },
+	{ 0x90033, 0x10 },
+	{ 0x90034, 0x139 },
+	{ 0x90035, 0xb },
+	{ 0x90036, 0x7c0 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0x44 },
+	{ 0x90039, 0x633 },
+	{ 0x9003a, 0x159 },
+	{ 0x9003b, 0x14f },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x47 },
+	{ 0x9003f, 0x633 },
+	{ 0x90040, 0x149 },
+	{ 0x90041, 0x4f },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x179 },
+	{ 0x90044, 0x8 },
+	{ 0x90045, 0xe0 },
+	{ 0x90046, 0x109 },
+	{ 0x90047, 0x0 },
+	{ 0x90048, 0x7c8 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x1 },
+	{ 0x9004c, 0x8 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x45a },
+	{ 0x9004f, 0x9 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x448 },
+	{ 0x90052, 0x109 },
+	{ 0x90053, 0x40 },
+	{ 0x90054, 0x633 },
+	{ 0x90055, 0x179 },
+	{ 0x90056, 0x1 },
+	{ 0x90057, 0x618 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40c0 },
+	{ 0x9005a, 0x633 },
+	{ 0x9005b, 0x149 },
+	{ 0x9005c, 0x8 },
+	{ 0x9005d, 0x4 },
+	{ 0x9005e, 0x48 },
+	{ 0x9005f, 0x4040 },
+	{ 0x90060, 0x633 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x0 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x40 },
+	{ 0x90066, 0x633 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x10 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x18 },
+	{ 0x9006b, 0x0 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x78 },
+	{ 0x9006e, 0x549 },
+	{ 0x9006f, 0x633 },
+	{ 0x90070, 0x159 },
+	{ 0x90071, 0xd49 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0x94a },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x441 },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x149 },
+	{ 0x9007a, 0x42 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x1 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x0 },
+	{ 0x90081, 0xe0 },
+	{ 0x90082, 0x109 },
+	{ 0x90083, 0xa },
+	{ 0x90084, 0x10 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0x9 },
+	{ 0x90087, 0x3c0 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x159 },
+	{ 0x9008c, 0x18 },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x0 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x18 },
+	{ 0x90093, 0x4 },
+	{ 0x90094, 0x48 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x58 },
+	{ 0x90098, 0xb },
+	{ 0x90099, 0x10 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x1 },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x5 },
+	{ 0x9009f, 0x7c0 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x0 },
+	{ 0x900a2, 0x8140 },
+	{ 0x900a3, 0x10c },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x8138 },
+	{ 0x900a6, 0x10c },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7c8 },
+	{ 0x900a9, 0x101 },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x448 },
+	{ 0x900ac, 0x109 },
+	{ 0x900ad, 0xf },
+	{ 0x900ae, 0x7c0 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x47 },
+	{ 0x900b1, 0x630 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x8 },
+	{ 0x900b4, 0x618 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0xe0 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x0 },
+	{ 0x900ba, 0x7c8 },
+	{ 0x900bb, 0x109 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0x8140 },
+	{ 0x900be, 0x10c },
+	{ 0x900bf, 0x0 },
+	{ 0x900c0, 0x1 },
+	{ 0x900c1, 0x8 },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x8 },
+	{ 0x900c5, 0x8 },
+	{ 0x900c6, 0x7c8 },
+	{ 0x900c7, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x90026, 0x2b },
+	{ 0x2000b, 0x4b },
+	{ 0x2000c, 0x96 },
+	{ 0x2000d, 0x5dc },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x21 },
+	{ 0x12000c, 0x42 },
+	{ 0x12000d, 0x29a },
+	{ 0x12000e, 0x21 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0xffff },
+	{ 0x90013, 0x6152 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 1066mts 1D */
+		.drate = 1066,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 2400, 1066, },
+};
+
diff --git a/roms/u-boot/board/freescale/imx8mn_evk/ddr4_timing_ld.c b/roms/u-boot/board/freescale/imx8mn_evk/ddr4_timing_ld.c
new file mode 100644
index 000000000..983fc7d99
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mn_evk/ddr4_timing_ld.c
@@ -0,0 +1,1057 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400000, 0x81040010 },
+	{ 0x3d400030, 0x20 },
+	{ 0x3d400034, 0x221306 },
+	{ 0x3d400050, 0x210070 },
+	{ 0x3d400054, 0x10008 },
+	{ 0x3d400060, 0x0 },
+	{ 0x3d400064, 0x6100dc },
+	{ 0x3d4000c0, 0x0 },
+	{ 0x3d4000c4, 0x1000 },
+	{ 0x3d4000d0, 0xc00200c5 },
+	{ 0x3d4000d4, 0x500000 },
+	{ 0x3d4000dc, 0x2340105 },
+	{ 0x3d4000e0, 0x0 },
+	{ 0x3d4000e4, 0x110000 },
+	{ 0x3d4000e8, 0x2000600 },
+	{ 0x3d4000ec, 0x410 },
+	{ 0x3d4000f0, 0x20 },
+	{ 0x3d4000f4, 0xec7 },
+	{ 0x3d400100, 0xd0c1b0d },
+	{ 0x3d400104, 0x30313 },
+	{ 0x3d400108, 0x508060a },
+	{ 0x3d40010c, 0x400c },
+	{ 0x3d400110, 0x6030306 },
+	{ 0x3d400114, 0x4040302 },
+	{ 0x3d40011c, 0x404 },
+	{ 0x3d400120, 0x5050d08 },
+	{ 0x3d400124, 0x20308 },
+	{ 0x3d40012c, 0x1406010e },
+	{ 0x3d400130, 0x8 },
+	{ 0x3d40013c, 0x0 },
+	{ 0x3d400180, 0x1000040 },
+	{ 0x3d400184, 0x30d4 },
+	{ 0x3d400190, 0x38b8204 },
+	{ 0x3d400194, 0x2020303 },
+	{ 0x3d400198, 0x7f04011 },
+	{ 0x3d40019c, 0xb0 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0x48005a },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x1 },
+	{ 0x3d4001b4, 0xb04 },
+	{ 0x3d4001b8, 0x4 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d400200, 0x3f1f },
+	{ 0x3d400204, 0x3f0909 },
+	{ 0x3d400208, 0x700 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf07 },
+	{ 0x3d400220, 0x3f01 },
+	{ 0x3d400240, 0x600061c },
+	{ 0x3d400244, 0x1323 },
+	{ 0x3d400400, 0x100 },
+	{ 0x3d400250, 0x317d1a07 },
+	{ 0x3d400254, 0xf },
+	{ 0x3d40025c, 0x2a001b76 },
+	{ 0x3d400264, 0x7300b473 },
+	{ 0x3d40026c, 0x30000e06 },
+	{ 0x3d400300, 0x14 },
+	{ 0x3d40036c, 0x10 },
+	{ 0x3d400404, 0x13193 },
+	{ 0x3d400408, 0x6096 },
+	{ 0x3d400490, 0x1 },
+	{ 0x3d400494, 0x2000c00 },
+	{ 0x3d400498, 0x3c00db },
+	{ 0x3d40049c, 0x100009 },
+	{ 0x3d4004a0, 0x2 },
+	{ 0x3d402050, 0x210070 },
+	{ 0x3d402064, 0x400093 },
+	{ 0x3d4020dc, 0x40105 },
+	{ 0x3d4020e0, 0x0 },
+	{ 0x3d4020e8, 0x2000600 },
+	{ 0x3d4020ec, 0x10 },
+	{ 0x3d402100, 0xb081209 },
+	{ 0x3d402104, 0x2020d },
+	{ 0x3d402108, 0x5050309 },
+	{ 0x3d40210c, 0x400c },
+	{ 0x3d402110, 0x5030206 },
+	{ 0x3d402114, 0x3030202 },
+	{ 0x3d40211c, 0x303 },
+	{ 0x3d402120, 0x4040d06 },
+	{ 0x3d402124, 0x20208 },
+	{ 0x3d40212c, 0x1205010e },
+	{ 0x3d402130, 0x8 },
+	{ 0x3d40213c, 0x0 },
+	{ 0x3d402180, 0x1000040 },
+	{ 0x3d402190, 0x3858204 },
+	{ 0x3d402194, 0x2020303 },
+	{ 0x3d4021b4, 0x504 },
+	{ 0x3d4021b8, 0x4 },
+	{ 0x3d402240, 0x6000604 },
+	{ 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x1005f, 0x2fd },
+	{ 0x1015f, 0x2fd },
+	{ 0x1105f, 0x2fd },
+	{ 0x1115f, 0x2fd },
+	{ 0x11005f, 0x2fd },
+	{ 0x11015f, 0x2fd },
+	{ 0x11105f, 0x2fd },
+	{ 0x11115f, 0x2fd },
+	{ 0x55, 0x355 },
+	{ 0x1055, 0x355 },
+	{ 0x2055, 0x355 },
+	{ 0x3055, 0x355 },
+	{ 0x4055, 0x55 },
+	{ 0x5055, 0x55 },
+	{ 0x6055, 0x355 },
+	{ 0x7055, 0x355 },
+	{ 0x8055, 0x355 },
+	{ 0x9055, 0x355 },
+	{ 0x200c5, 0xb },
+	{ 0x1200c5, 0x6 },
+	{ 0x2002e, 0x1 },
+	{ 0x12002e, 0x1 },
+	{ 0x20024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0xa },
+	{ 0x120056, 0xa },
+	{ 0x1004d, 0x1a },
+	{ 0x1014d, 0x1a },
+	{ 0x1104d, 0x1a },
+	{ 0x1114d, 0x1a },
+	{ 0x11004d, 0x1a },
+	{ 0x11014d, 0x1a },
+	{ 0x11104d, 0x1a },
+	{ 0x11114d, 0x1a },
+	{ 0x10049, 0xe38 },
+	{ 0x10149, 0xe38 },
+	{ 0x11049, 0xe38 },
+	{ 0x11149, 0xe38 },
+	{ 0x110049, 0xe38 },
+	{ 0x110149, 0xe38 },
+	{ 0x111049, 0xe38 },
+	{ 0x111149, 0xe38 },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x2 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x190 },
+	{ 0x120008, 0x10a },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x268 },
+	{ 0x10043, 0x5b1 },
+	{ 0x10143, 0x5b1 },
+	{ 0x11043, 0x5b1 },
+	{ 0x11143, 0x5b1 },
+	{ 0x1200b2, 0x268 },
+	{ 0x110043, 0x5b1 },
+	{ 0x110143, 0x5b1 },
+	{ 0x111043, 0x5b1 },
+	{ 0x111143, 0x5b1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x20019, 0x5 },
+	{ 0x120019, 0x5 },
+	{ 0x200f0, 0x5555 },
+	{ 0x200f1, 0x5555 },
+	{ 0x200f2, 0x5555 },
+	{ 0x200f3, 0x5555 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x5555 },
+	{ 0x200f6, 0x5555 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x2005b, 0x7529 },
+	{ 0x2005c, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x200cc, 0x1f7 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x1200cc, 0x1f7 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2, 0x0},
+	{0x1200b2, 0x0},
+	{0x2200b2, 0x0},
+	{0x0200cb, 0x0},
+	{0x010043, 0x0},
+	{0x110043, 0x0},
+	{0x210043, 0x0},
+	{0x010143, 0x0},
+	{0x110143, 0x0},
+	{0x210143, 0x0},
+	{0x011043, 0x0},
+	{0x111043, 0x0},
+	{0x211043, 0x0},
+	{0x011143, 0x0},
+	{0x111143, 0x0},
+	{0x211143, 0x0},
+	{0x000080, 0x0},
+	{0x100080, 0x0},
+	{0x200080, 0x0},
+	{0x001080, 0x0},
+	{0x101080, 0x0},
+	{0x201080, 0x0},
+	{0x002080, 0x0},
+	{0x102080, 0x0},
+	{0x202080, 0x0},
+	{0x003080, 0x0},
+	{0x103080, 0x0},
+	{0x203080, 0x0},
+	{0x004080, 0x0},
+	{0x104080, 0x0},
+	{0x204080, 0x0},
+	{0x005080, 0x0},
+	{0x105080, 0x0},
+	{0x205080, 0x0},
+	{0x006080, 0x0},
+	{0x106080, 0x0},
+	{0x206080, 0x0},
+	{0x007080, 0x0},
+	{0x107080, 0x0},
+	{0x207080, 0x0},
+	{0x008080, 0x0},
+	{0x108080, 0x0},
+	{0x208080, 0x0},
+	{0x009080, 0x0},
+	{0x109080, 0x0},
+	{0x209080, 0x0},
+	{0x010080, 0x0},
+	{0x110080, 0x0},
+	{0x210080, 0x0},
+	{0x010180, 0x0},
+	{0x110180, 0x0},
+	{0x210180, 0x0},
+	{0x010081, 0x0},
+	{0x110081, 0x0},
+	{0x210081, 0x0},
+	{0x010181, 0x0},
+	{0x110181, 0x0},
+	{0x210181, 0x0},
+	{0x010082, 0x0},
+	{0x110082, 0x0},
+	{0x210082, 0x0},
+	{0x010182, 0x0},
+	{0x110182, 0x0},
+	{0x210182, 0x0},
+	{0x010083, 0x0},
+	{0x110083, 0x0},
+	{0x210083, 0x0},
+	{0x010183, 0x0},
+	{0x110183, 0x0},
+	{0x210183, 0x0},
+	{0x011080, 0x0},
+	{0x111080, 0x0},
+	{0x211080, 0x0},
+	{0x011180, 0x0},
+	{0x111180, 0x0},
+	{0x211180, 0x0},
+	{0x011081, 0x0},
+	{0x111081, 0x0},
+	{0x211081, 0x0},
+	{0x011181, 0x0},
+	{0x111181, 0x0},
+	{0x211181, 0x0},
+	{0x011082, 0x0},
+	{0x111082, 0x0},
+	{0x211082, 0x0},
+	{0x011182, 0x0},
+	{0x111182, 0x0},
+	{0x211182, 0x0},
+	{0x011083, 0x0},
+	{0x111083, 0x0},
+	{0x211083, 0x0},
+	{0x011183, 0x0},
+	{0x111183, 0x0},
+	{0x211183, 0x0},
+	{0x0100d0, 0x0},
+	{0x1100d0, 0x0},
+	{0x2100d0, 0x0},
+	{0x0101d0, 0x0},
+	{0x1101d0, 0x0},
+	{0x2101d0, 0x0},
+	{0x0100d1, 0x0},
+	{0x1100d1, 0x0},
+	{0x2100d1, 0x0},
+	{0x0101d1, 0x0},
+	{0x1101d1, 0x0},
+	{0x2101d1, 0x0},
+	{0x0100d2, 0x0},
+	{0x1100d2, 0x0},
+	{0x2100d2, 0x0},
+	{0x0101d2, 0x0},
+	{0x1101d2, 0x0},
+	{0x2101d2, 0x0},
+	{0x0100d3, 0x0},
+	{0x1100d3, 0x0},
+	{0x2100d3, 0x0},
+	{0x0101d3, 0x0},
+	{0x1101d3, 0x0},
+	{0x2101d3, 0x0},
+	{0x0110d0, 0x0},
+	{0x1110d0, 0x0},
+	{0x2110d0, 0x0},
+	{0x0111d0, 0x0},
+	{0x1111d0, 0x0},
+	{0x2111d0, 0x0},
+	{0x0110d1, 0x0},
+	{0x1110d1, 0x0},
+	{0x2110d1, 0x0},
+	{0x0111d1, 0x0},
+	{0x1111d1, 0x0},
+	{0x2111d1, 0x0},
+	{0x0110d2, 0x0},
+	{0x1110d2, 0x0},
+	{0x2110d2, 0x0},
+	{0x0111d2, 0x0},
+	{0x1111d2, 0x0},
+	{0x2111d2, 0x0},
+	{0x0110d3, 0x0},
+	{0x1110d3, 0x0},
+	{0x2110d3, 0x0},
+	{0x0111d3, 0x0},
+	{0x1111d3, 0x0},
+	{0x2111d3, 0x0},
+	{0x010068, 0x0},
+	{0x010168, 0x0},
+	{0x010268, 0x0},
+	{0x010368, 0x0},
+	{0x010468, 0x0},
+	{0x010568, 0x0},
+	{0x010668, 0x0},
+	{0x010768, 0x0},
+	{0x010868, 0x0},
+	{0x010069, 0x0},
+	{0x010169, 0x0},
+	{0x010269, 0x0},
+	{0x010369, 0x0},
+	{0x010469, 0x0},
+	{0x010569, 0x0},
+	{0x010669, 0x0},
+	{0x010769, 0x0},
+	{0x010869, 0x0},
+	{0x01006a, 0x0},
+	{0x01016a, 0x0},
+	{0x01026a, 0x0},
+	{0x01036a, 0x0},
+	{0x01046a, 0x0},
+	{0x01056a, 0x0},
+	{0x01066a, 0x0},
+	{0x01076a, 0x0},
+	{0x01086a, 0x0},
+	{0x01006b, 0x0},
+	{0x01016b, 0x0},
+	{0x01026b, 0x0},
+	{0x01036b, 0x0},
+	{0x01046b, 0x0},
+	{0x01056b, 0x0},
+	{0x01066b, 0x0},
+	{0x01076b, 0x0},
+	{0x01086b, 0x0},
+	{0x011068, 0x0},
+	{0x011168, 0x0},
+	{0x011268, 0x0},
+	{0x011368, 0x0},
+	{0x011468, 0x0},
+	{0x011568, 0x0},
+	{0x011668, 0x0},
+	{0x011768, 0x0},
+	{0x011868, 0x0},
+	{0x011069, 0x0},
+	{0x011169, 0x0},
+	{0x011269, 0x0},
+	{0x011369, 0x0},
+	{0x011469, 0x0},
+	{0x011569, 0x0},
+	{0x011669, 0x0},
+	{0x011769, 0x0},
+	{0x011869, 0x0},
+	{0x01106a, 0x0},
+	{0x01116a, 0x0},
+	{0x01126a, 0x0},
+	{0x01136a, 0x0},
+	{0x01146a, 0x0},
+	{0x01156a, 0x0},
+	{0x01166a, 0x0},
+	{0x01176a, 0x0},
+	{0x01186a, 0x0},
+	{0x01106b, 0x0},
+	{0x01116b, 0x0},
+	{0x01126b, 0x0},
+	{0x01136b, 0x0},
+	{0x01146b, 0x0},
+	{0x01156b, 0x0},
+	{0x01166b, 0x0},
+	{0x01176b, 0x0},
+	{0x01186b, 0x0},
+	{0x01008c, 0x0},
+	{0x11008c, 0x0},
+	{0x21008c, 0x0},
+	{0x01018c, 0x0},
+	{0x11018c, 0x0},
+	{0x21018c, 0x0},
+	{0x01008d, 0x0},
+	{0x11008d, 0x0},
+	{0x21008d, 0x0},
+	{0x01018d, 0x0},
+	{0x11018d, 0x0},
+	{0x21018d, 0x0},
+	{0x01008e, 0x0},
+	{0x11008e, 0x0},
+	{0x21008e, 0x0},
+	{0x01018e, 0x0},
+	{0x11018e, 0x0},
+	{0x21018e, 0x0},
+	{0x01008f, 0x0},
+	{0x11008f, 0x0},
+	{0x21008f, 0x0},
+	{0x01018f, 0x0},
+	{0x11018f, 0x0},
+	{0x21018f, 0x0},
+	{0x01108c, 0x0},
+	{0x11108c, 0x0},
+	{0x21108c, 0x0},
+	{0x01118c, 0x0},
+	{0x11118c, 0x0},
+	{0x21118c, 0x0},
+	{0x01108d, 0x0},
+	{0x11108d, 0x0},
+	{0x21108d, 0x0},
+	{0x01118d, 0x0},
+	{0x11118d, 0x0},
+	{0x21118d, 0x0},
+	{0x01108e, 0x0},
+	{0x11108e, 0x0},
+	{0x21108e, 0x0},
+	{0x01118e, 0x0},
+	{0x11118e, 0x0},
+	{0x21118e, 0x0},
+	{0x01108f, 0x0},
+	{0x11108f, 0x0},
+	{0x21108f, 0x0},
+	{0x01118f, 0x0},
+	{0x11118f, 0x0},
+	{0x21118f, 0x0},
+	{0x0100c0, 0x0},
+	{0x1100c0, 0x0},
+	{0x2100c0, 0x0},
+	{0x0101c0, 0x0},
+	{0x1101c0, 0x0},
+	{0x2101c0, 0x0},
+	{0x0102c0, 0x0},
+	{0x1102c0, 0x0},
+	{0x2102c0, 0x0},
+	{0x0103c0, 0x0},
+	{0x1103c0, 0x0},
+	{0x2103c0, 0x0},
+	{0x0104c0, 0x0},
+	{0x1104c0, 0x0},
+	{0x2104c0, 0x0},
+	{0x0105c0, 0x0},
+	{0x1105c0, 0x0},
+	{0x2105c0, 0x0},
+	{0x0106c0, 0x0},
+	{0x1106c0, 0x0},
+	{0x2106c0, 0x0},
+	{0x0107c0, 0x0},
+	{0x1107c0, 0x0},
+	{0x2107c0, 0x0},
+	{0x0108c0, 0x0},
+	{0x1108c0, 0x0},
+	{0x2108c0, 0x0},
+	{0x0100c1, 0x0},
+	{0x1100c1, 0x0},
+	{0x2100c1, 0x0},
+	{0x0101c1, 0x0},
+	{0x1101c1, 0x0},
+	{0x2101c1, 0x0},
+	{0x0102c1, 0x0},
+	{0x1102c1, 0x0},
+	{0x2102c1, 0x0},
+	{0x0103c1, 0x0},
+	{0x1103c1, 0x0},
+	{0x2103c1, 0x0},
+	{0x0104c1, 0x0},
+	{0x1104c1, 0x0},
+	{0x2104c1, 0x0},
+	{0x0105c1, 0x0},
+	{0x1105c1, 0x0},
+	{0x2105c1, 0x0},
+	{0x0106c1, 0x0},
+	{0x1106c1, 0x0},
+	{0x2106c1, 0x0},
+	{0x0107c1, 0x0},
+	{0x1107c1, 0x0},
+	{0x2107c1, 0x0},
+	{0x0108c1, 0x0},
+	{0x1108c1, 0x0},
+	{0x2108c1, 0x0},
+	{0x0100c2, 0x0},
+	{0x1100c2, 0x0},
+	{0x2100c2, 0x0},
+	{0x0101c2, 0x0},
+	{0x1101c2, 0x0},
+	{0x2101c2, 0x0},
+	{0x0102c2, 0x0},
+	{0x1102c2, 0x0},
+	{0x2102c2, 0x0},
+	{0x0103c2, 0x0},
+	{0x1103c2, 0x0},
+	{0x2103c2, 0x0},
+	{0x0104c2, 0x0},
+	{0x1104c2, 0x0},
+	{0x2104c2, 0x0},
+	{0x0105c2, 0x0},
+	{0x1105c2, 0x0},
+	{0x2105c2, 0x0},
+	{0x0106c2, 0x0},
+	{0x1106c2, 0x0},
+	{0x2106c2, 0x0},
+	{0x0107c2, 0x0},
+	{0x1107c2, 0x0},
+	{0x2107c2, 0x0},
+	{0x0108c2, 0x0},
+	{0x1108c2, 0x0},
+	{0x2108c2, 0x0},
+	{0x0100c3, 0x0},
+	{0x1100c3, 0x0},
+	{0x2100c3, 0x0},
+	{0x0101c3, 0x0},
+	{0x1101c3, 0x0},
+	{0x2101c3, 0x0},
+	{0x0102c3, 0x0},
+	{0x1102c3, 0x0},
+	{0x2102c3, 0x0},
+	{0x0103c3, 0x0},
+	{0x1103c3, 0x0},
+	{0x2103c3, 0x0},
+	{0x0104c3, 0x0},
+	{0x1104c3, 0x0},
+	{0x2104c3, 0x0},
+	{0x0105c3, 0x0},
+	{0x1105c3, 0x0},
+	{0x2105c3, 0x0},
+	{0x0106c3, 0x0},
+	{0x1106c3, 0x0},
+	{0x2106c3, 0x0},
+	{0x0107c3, 0x0},
+	{0x1107c3, 0x0},
+	{0x2107c3, 0x0},
+	{0x0108c3, 0x0},
+	{0x1108c3, 0x0},
+	{0x2108c3, 0x0},
+	{0x0110c0, 0x0},
+	{0x1110c0, 0x0},
+	{0x2110c0, 0x0},
+	{0x0111c0, 0x0},
+	{0x1111c0, 0x0},
+	{0x2111c0, 0x0},
+	{0x0112c0, 0x0},
+	{0x1112c0, 0x0},
+	{0x2112c0, 0x0},
+	{0x0113c0, 0x0},
+	{0x1113c0, 0x0},
+	{0x2113c0, 0x0},
+	{0x0114c0, 0x0},
+	{0x1114c0, 0x0},
+	{0x2114c0, 0x0},
+	{0x0115c0, 0x0},
+	{0x1115c0, 0x0},
+	{0x2115c0, 0x0},
+	{0x0116c0, 0x0},
+	{0x1116c0, 0x0},
+	{0x2116c0, 0x0},
+	{0x0117c0, 0x0},
+	{0x1117c0, 0x0},
+	{0x2117c0, 0x0},
+	{0x0118c0, 0x0},
+	{0x1118c0, 0x0},
+	{0x2118c0, 0x0},
+	{0x0110c1, 0x0},
+	{0x1110c1, 0x0},
+	{0x2110c1, 0x0},
+	{0x0111c1, 0x0},
+	{0x1111c1, 0x0},
+	{0x2111c1, 0x0},
+	{0x0112c1, 0x0},
+	{0x1112c1, 0x0},
+	{0x2112c1, 0x0},
+	{0x0113c1, 0x0},
+	{0x1113c1, 0x0},
+	{0x2113c1, 0x0},
+	{0x0114c1, 0x0},
+	{0x1114c1, 0x0},
+	{0x2114c1, 0x0},
+	{0x0115c1, 0x0},
+	{0x1115c1, 0x0},
+	{0x2115c1, 0x0},
+	{0x0116c1, 0x0},
+	{0x1116c1, 0x0},
+	{0x2116c1, 0x0},
+	{0x0117c1, 0x0},
+	{0x1117c1, 0x0},
+	{0x2117c1, 0x0},
+	{0x0118c1, 0x0},
+	{0x1118c1, 0x0},
+	{0x2118c1, 0x0},
+	{0x0110c2, 0x0},
+	{0x1110c2, 0x0},
+	{0x2110c2, 0x0},
+	{0x0111c2, 0x0},
+	{0x1111c2, 0x0},
+	{0x2111c2, 0x0},
+	{0x0112c2, 0x0},
+	{0x1112c2, 0x0},
+	{0x2112c2, 0x0},
+	{0x0113c2, 0x0},
+	{0x1113c2, 0x0},
+	{0x2113c2, 0x0},
+	{0x0114c2, 0x0},
+	{0x1114c2, 0x0},
+	{0x2114c2, 0x0},
+	{0x0115c2, 0x0},
+	{0x1115c2, 0x0},
+	{0x2115c2, 0x0},
+	{0x0116c2, 0x0},
+	{0x1116c2, 0x0},
+	{0x2116c2, 0x0},
+	{0x0117c2, 0x0},
+	{0x1117c2, 0x0},
+	{0x2117c2, 0x0},
+	{0x0118c2, 0x0},
+	{0x1118c2, 0x0},
+	{0x2118c2, 0x0},
+	{0x0110c3, 0x0},
+	{0x1110c3, 0x0},
+	{0x2110c3, 0x0},
+	{0x0111c3, 0x0},
+	{0x1111c3, 0x0},
+	{0x2111c3, 0x0},
+	{0x0112c3, 0x0},
+	{0x1112c3, 0x0},
+	{0x2112c3, 0x0},
+	{0x0113c3, 0x0},
+	{0x1113c3, 0x0},
+	{0x2113c3, 0x0},
+	{0x0114c3, 0x0},
+	{0x1114c3, 0x0},
+	{0x2114c3, 0x0},
+	{0x0115c3, 0x0},
+	{0x1115c3, 0x0},
+	{0x2115c3, 0x0},
+	{0x0116c3, 0x0},
+	{0x1116c3, 0x0},
+	{0x2116c3, 0x0},
+	{0x0117c3, 0x0},
+	{0x1117c3, 0x0},
+	{0x2117c3, 0x0},
+	{0x0118c3, 0x0},
+	{0x1118c3, 0x0},
+	{0x2118c3, 0x0},
+	{0x010020, 0x0},
+	{0x110020, 0x0},
+	{0x210020, 0x0},
+	{0x011020, 0x0},
+	{0x111020, 0x0},
+	{0x211020, 0x0},
+	{0x02007d, 0x0},
+	{0x12007d, 0x0},
+	{0x22007d, 0x0},
+	{0x010040, 0x0},
+	{0x010140, 0x0},
+	{0x010240, 0x0},
+	{0x010340, 0x0},
+	{0x010440, 0x0},
+	{0x010540, 0x0},
+	{0x010640, 0x0},
+	{0x010740, 0x0},
+	{0x010840, 0x0},
+	{0x010030, 0x0},
+	{0x010130, 0x0},
+	{0x010230, 0x0},
+	{0x010330, 0x0},
+	{0x010430, 0x0},
+	{0x010530, 0x0},
+	{0x010630, 0x0},
+	{0x010730, 0x0},
+	{0x010830, 0x0},
+	{0x011040, 0x0},
+	{0x011140, 0x0},
+	{0x011240, 0x0},
+	{0x011340, 0x0},
+	{0x011440, 0x0},
+	{0x011540, 0x0},
+	{0x011640, 0x0},
+	{0x011740, 0x0},
+	{0x011840, 0x0},
+	{0x011030, 0x0},
+	{0x011130, 0x0},
+	{0x011230, 0x0},
+	{0x011330, 0x0},
+	{0x011430, 0x0},
+	{0x011530, 0x0},
+	{0x011630, 0x0},
+	{0x011730, 0x0},
+	{0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x640 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x234 },
+	{ 0x54030, 0x105 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x410 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x42a },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x4 },
+	{ 0x54030, 0x105 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x10 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x640 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x61 },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400e, 0x1f7f },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x234 },
+	{ 0x54030, 0x105 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x410 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x2 },
+	{ 0x90033, 0x10 },
+	{ 0x90034, 0x139 },
+	{ 0x90035, 0xb },
+	{ 0x90036, 0x7c0 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0x44 },
+	{ 0x90039, 0x633 },
+	{ 0x9003a, 0x159 },
+	{ 0x9003b, 0x14f },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x47 },
+	{ 0x9003f, 0x633 },
+	{ 0x90040, 0x149 },
+	{ 0x90041, 0x4f },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x179 },
+	{ 0x90044, 0x8 },
+	{ 0x90045, 0xe0 },
+	{ 0x90046, 0x109 },
+	{ 0x90047, 0x0 },
+	{ 0x90048, 0x7c8 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x1 },
+	{ 0x9004c, 0x8 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x45a },
+	{ 0x9004f, 0x9 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x448 },
+	{ 0x90052, 0x109 },
+	{ 0x90053, 0x40 },
+	{ 0x90054, 0x633 },
+	{ 0x90055, 0x179 },
+	{ 0x90056, 0x1 },
+	{ 0x90057, 0x618 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40c0 },
+	{ 0x9005a, 0x633 },
+	{ 0x9005b, 0x149 },
+	{ 0x9005c, 0x8 },
+	{ 0x9005d, 0x4 },
+	{ 0x9005e, 0x48 },
+	{ 0x9005f, 0x4040 },
+	{ 0x90060, 0x633 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x0 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x40 },
+	{ 0x90066, 0x633 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x10 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x18 },
+	{ 0x9006b, 0x0 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x78 },
+	{ 0x9006e, 0x549 },
+	{ 0x9006f, 0x633 },
+	{ 0x90070, 0x159 },
+	{ 0x90071, 0xd49 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0x94a },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x441 },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x149 },
+	{ 0x9007a, 0x42 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x1 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x0 },
+	{ 0x90081, 0xe0 },
+	{ 0x90082, 0x109 },
+	{ 0x90083, 0xa },
+	{ 0x90084, 0x10 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0x9 },
+	{ 0x90087, 0x3c0 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x159 },
+	{ 0x9008c, 0x18 },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x0 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x18 },
+	{ 0x90093, 0x4 },
+	{ 0x90094, 0x48 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x58 },
+	{ 0x90098, 0xb },
+	{ 0x90099, 0x10 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x1 },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x5 },
+	{ 0x9009f, 0x7c0 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x0 },
+	{ 0x900a2, 0x8140 },
+	{ 0x900a3, 0x10c },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x8138 },
+	{ 0x900a6, 0x10c },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7c8 },
+	{ 0x900a9, 0x101 },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x448 },
+	{ 0x900ac, 0x109 },
+	{ 0x900ad, 0xf },
+	{ 0x900ae, 0x7c0 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x47 },
+	{ 0x900b1, 0x630 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x8 },
+	{ 0x900b4, 0x618 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0xe0 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x0 },
+	{ 0x900ba, 0x7c8 },
+	{ 0x900bb, 0x109 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0x8140 },
+	{ 0x900be, 0x10c },
+	{ 0x900bf, 0x0 },
+	{ 0x900c0, 0x1 },
+	{ 0x900c1, 0x8 },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x8 },
+	{ 0x900c5, 0x8 },
+	{ 0x900c6, 0x7c8 },
+	{ 0x900c7, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x90026, 0x2b },
+	{ 0x2000b, 0x32 },
+	{ 0x2000c, 0x64 },
+	{ 0x2000d, 0x3e8 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x21 },
+	{ 0x12000c, 0x42 },
+	{ 0x12000d, 0x29a },
+	{ 0x12000e, 0x21 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0xffff },
+	{ 0x90013, 0x6152 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 1600mts 1D */
+		.drate = 1600,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 1066mts 1D */
+		.drate = 1066,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 1600mts 2D */
+		.drate = 1600,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 1600, 1066, },
+};
+
diff --git a/roms/u-boot/board/freescale/imx8mn_evk/imx8mn_evk.c b/roms/u-boot/board/freescale/imx8mn_evk/imx8mn_evk.c
new file mode 100644
index 000000000..9a0a0488b
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mn_evk/imx8mn_evk.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "DDR4 EVK");
+	env_set("board_rev", "iMX8MN");
+#endif
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg b/roms/u-boot/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg
new file mode 100644
index 000000000..22aec26da
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#define __ASSEMBLY__
+
+ROM_VERSION	v2
+BOOT_FROM	sd
+LOADER		mkimage.flash.mkimage	0x912000
diff --git a/roms/u-boot/board/freescale/imx8mn_evk/lpddr4_timing.c b/roms/u-boot/board/freescale/imx8mn_evk/lpddr4_timing.c
new file mode 100644
index 000000000..671e92413
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mn_evk/lpddr4_timing.c
@@ -0,0 +1,1587 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	{0x3d400020, 0x00000213},
+	{0x3d400024, 0x0003e800},
+	{0x3d400030, 0x00000120},
+	{0x3d400000, 0xa3080020},
+	{0x3d400064, 0x006100e0},
+	{0x3d4000d0, 0xc003061c},
+	{0x3d4000d4, 0x009e0000},
+	{0x3d4000dc, 0x00d4002d},
+	{0x3d4000e0, 0x00310000},
+	{0x3d4000e8, 0x0066004d},
+	{0x3d4000ec, 0x0016004a},
+	{0x3d400100, 0x1a201b22},
+	{0x3d400104, 0x00060633},
+	{0x3d40010c, 0x00c0c000},
+	{0x3d400110, 0x0f04080f},
+	{0x3d400114, 0x02040c0c},
+	{0x3d400118, 0x01010007},
+	{0x3d40011c, 0x00000401},
+	{0x3d400130, 0x00020600},
+	{0x3d400134, 0x0c100002},
+	{0x3d400138, 0x000000e6},
+	{0x3d400144, 0x00a00050},
+	{0x3d400180, 0x03200018},
+	{0x3d400184, 0x028061a8},
+	{0x3d400188, 0x00000000},
+	{0x3d400190, 0x0497820a},
+	{0x3d4001b4, 0x0000170a},
+	{0x3d400108, 0x070e1617},
+	{0x3d4001c0, 0x00000001},
+	{0x3d400194, 0x00080303},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0x00df00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x00000011},
+	{0x3d4001c4, 0x00000001},
+	{0x3d4000f4, 0x00000c99},
+	{0x3d400200, 0x00000017},
+	{0x3d400204, 0x00080808},
+	{0x3d400208, 0x00000000},
+	{0x3d40020c, 0x00000000},
+	{0x3d400210, 0x00001f1f},
+	{0x3d400214, 0x07070707},
+	{0x3d400218, 0x07070707},
+	{0x3d40021c, 0x00000f0f},
+	{0x3d400250, 0x29001701},
+	{0x3d400254, 0x0000002c},
+	{0x3d40025c, 0x04000030},
+	{0x3d400264, 0x900093e7},
+	{0x3d40026c, 0x20005574},
+	{0x3d400400, 0x00000111},
+	{0x3d400408, 0x000072ff},
+	{0x3d400494, 0x02100e07},
+	{0x3d400498, 0x00620096},
+	{0x3d40049c, 0x01100e07},
+	{0x3d4004a0, 0x00c8012c},
+	{0x3d402020, 0x00000011},
+	{0x3d402024, 0x00007d00},
+	{0x3d402050, 0x0020d040},
+	{0x3d402064, 0x000c001d},
+	{0x3d4020f4, 0x00000c99},
+	{0x3d402100, 0x0a040305},
+	{0x3d402104, 0x00030407},
+	{0x3d402108, 0x0203060b},
+	{0x3d40210c, 0x00505000},
+	{0x3d402110, 0x02040202},
+	{0x3d402114, 0x02030202},
+	{0x3d402118, 0x01010004},
+	{0x3d40211c, 0x00000301},
+	{0x3d402130, 0x00020300},
+	{0x3d402134, 0x0a100002},
+	{0x3d402138, 0x0000001d},
+	{0x3d402144, 0x0014000a},
+	{0x3d402180, 0x00650004},
+	{0x3d402190, 0x03818200},
+	{0x3d402194, 0x00080303},
+	{0x3d4021b4, 0x00000100},
+	{0x3d4020dc, 0x00840000},
+	{0x3d4020e0, 0x00310000},
+	{0x3d4020e8, 0x0066004d},
+	{0x3d4020ec, 0x0016004a},
+	{0x3d403020, 0x00000011},
+	{0x3d403024, 0x00001f40},
+	{0x3d403050, 0x0020d040},
+	{0x3d403064, 0x00030007},
+	{0x3d4030f4, 0x00000c99},
+	{0x3d403100, 0x0a010102},
+	{0x3d403104, 0x00030404},
+	{0x3d403108, 0x0203060b},
+	{0x3d40310c, 0x00505000},
+	{0x3d403110, 0x02040202},
+	{0x3d403114, 0x02030202},
+	{0x3d403118, 0x01010004},
+	{0x3d40311c, 0x00000301},
+	{0x3d403130, 0x00020300},
+	{0x3d403134, 0x0a100002},
+	{0x3d403138, 0x00000008},
+	{0x3d403144, 0x00050003},
+	{0x3d403180, 0x00190004},
+	{0x3d403190, 0x03818200},
+	{0x3d403194, 0x00080303},
+	{0x3d4031b4, 0x00000100},
+	{0x3d4030dc, 0x00840000},
+	{0x3d4030e0, 0x00310000},
+	{0x3d4030e8, 0x0066004d},
+	{0x3d4030ec, 0x0016004a},
+
+	/* default boot point */
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x000100a0, 0x00000000},
+	{0x000100a1, 0x00000001},
+	{0x000100a2, 0x00000002},
+	{0x000100a3, 0x00000003},
+	{0x000100a4, 0x00000004},
+	{0x000100a5, 0x00000005},
+	{0x000100a6, 0x00000006},
+	{0x000100a7, 0x00000007},
+	{0x000110a0, 0x00000000},
+	{0x000110a1, 0x00000001},
+	{0x000110a2, 0x00000003},
+	{0x000110a3, 0x00000004},
+	{0x000110a4, 0x00000005},
+	{0x000110a5, 0x00000002},
+	{0x000110a6, 0x00000007},
+	{0x000110a7, 0x00000006},
+	{0x0001005f, 0x0000015f},
+	{0x0001015f, 0x0000015f},
+	{0x0001105f, 0x0000015f},
+	{0x0001115f, 0x0000015f},
+	{0x0011005f, 0x0000015f},
+	{0x0011015f, 0x0000015f},
+	{0x0011105f, 0x0000015f},
+	{0x0011115f, 0x0000015f},
+	{0x0021005f, 0x0000015f},
+	{0x0021015f, 0x0000015f},
+	{0x0021105f, 0x0000015f},
+	{0x0021115f, 0x0000015f},
+	{0x00000055, 0x0000016f},
+	{0x00001055, 0x0000016f},
+	{0x00002055, 0x0000016f},
+	{0x00003055, 0x0000016f},
+	{0x00004055, 0x0000016f},
+	{0x00005055, 0x0000016f},
+	{0x00006055, 0x0000016f},
+	{0x00007055, 0x0000016f},
+	{0x00008055, 0x0000016f},
+	{0x00009055, 0x0000016f},
+	{0x000200c5, 0x00000019},
+	{0x001200c5, 0x00000007},
+	{0x002200c5, 0x00000007},
+	{0x0002002e, 0x00000002},
+	{0x0012002e, 0x00000002},
+	{0x0022002e, 0x00000002},
+	{0x00090204, 0x00000000},
+	{0x00190204, 0x00000000},
+	{0x00290204, 0x00000000},
+	{0x00020024, 0x000001a3},
+	{0x0002003a, 0x00000002},
+	{0x0002007d, 0x00000212},
+	{0x0002007c, 0x00000061},
+	{0x00120024, 0x000001a3},
+	{0x0002003a, 0x00000002},
+	{0x0012007d, 0x00000212},
+	{0x0012007c, 0x00000061},
+	{0x00220024, 0x000001a3},
+	{0x0002003a, 0x00000002},
+	{0x0022007d, 0x00000212},
+	{0x0022007c, 0x00000061},
+	{0x00020056, 0x00000003},
+	{0x00120056, 0x00000003},
+	{0x00220056, 0x00000003},
+	{0x0001004d, 0x00000f80},
+	{0x0001014d, 0x00000f80},
+	{0x0001104d, 0x00000f80},
+	{0x0001114d, 0x00000f80},
+	{0x0011004d, 0x00000f80},
+	{0x0011014d, 0x00000f80},
+	{0x0011104d, 0x00000f80},
+	{0x0011114d, 0x00000f80},
+	{0x0021004d, 0x00000f80},
+	{0x0021014d, 0x00000f80},
+	{0x0021104d, 0x00000f80},
+	{0x0021114d, 0x00000f80},
+	{0x00010049, 0x00000fbe},
+	{0x00010149, 0x00000fbe},
+	{0x00011049, 0x00000fbe},
+	{0x00011149, 0x00000fbe},
+	{0x00110049, 0x00000fbe},
+	{0x00110149, 0x00000fbe},
+	{0x00111049, 0x00000fbe},
+	{0x00111149, 0x00000fbe},
+	{0x00210049, 0x00000fbe},
+	{0x00210149, 0x00000fbe},
+	{0x00211049, 0x00000fbe},
+	{0x00211149, 0x00000fbe},
+	{0x00000043, 0x00000063},
+	{0x00001043, 0x00000063},
+	{0x00002043, 0x00000063},
+	{0x00003043, 0x00000063},
+	{0x00004043, 0x00000063},
+	{0x00005043, 0x00000063},
+	{0x00006043, 0x00000063},
+	{0x00007043, 0x00000063},
+	{0x00008043, 0x00000063},
+	{0x00009043, 0x00000063},
+	{0x00020018, 0x00000001},
+	{0x00020075, 0x00000004},
+	{0x00020050, 0x00000000},
+	{0x00020008, 0x00000320},
+	{0x00120008, 0x00000064},
+	{0x00220008, 0x00000019},
+	{0x00020088, 0x00000009},
+	{0x000200b2, 0x000000dc},
+	{0x00010043, 0x000005a1},
+	{0x00010143, 0x000005a1},
+	{0x00011043, 0x000005a1},
+	{0x00011143, 0x000005a1},
+	{0x001200b2, 0x000000dc},
+	{0x00110043, 0x000005a1},
+	{0x00110143, 0x000005a1},
+	{0x00111043, 0x000005a1},
+	{0x00111143, 0x000005a1},
+	{0x002200b2, 0x000000dc},
+	{0x00210043, 0x000005a1},
+	{0x00210143, 0x000005a1},
+	{0x00211043, 0x000005a1},
+	{0x00211143, 0x000005a1},
+	{0x000200fa, 0x00000001},
+	{0x001200fa, 0x00000001},
+	{0x002200fa, 0x00000001},
+	{0x00020019, 0x00000001},
+	{0x00120019, 0x00000001},
+	{0x00220019, 0x00000001},
+	{0x000200f0, 0x00000660},
+	{0x000200f1, 0x00000000},
+	{0x000200f2, 0x00004444},
+	{0x000200f3, 0x00008888},
+	{0x000200f4, 0x00005665},
+	{0x000200f5, 0x00000000},
+	{0x000200f6, 0x00000000},
+	{0x000200f7, 0x0000f000},
+	{0x0001004a, 0x00000500},
+	{0x0001104a, 0x00000500},
+	{0x00020025, 0x00000000},
+	{0x0002002d, 0x00000000},
+	{0x0012002d, 0x00000000},
+	{0x0022002d, 0x00000000},
+	{0x0002002c, 0x00000000},
+	{0x000200c7, 0x00000021},
+	{0x000200ca, 0x00000024},
+	{0x000200cc, 0x000001f7},
+	{0x001200c7, 0x00000021},
+	{0x001200ca, 0x00000024},
+	{0x001200cc, 0x000001f7},
+	{0x002200c7, 0x00000021},
+	{0x002200ca, 0x00000024},
+	{0x002200cc, 0x000001f7},
+	{0x00020060, 0x00000002},
+	{0x000d0000, 0x00000001},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2, 0x0},
+	{0x1200b2, 0x0},
+	{0x2200b2, 0x0},
+	{0x0200cb, 0x0},
+	{0x010043, 0x0},
+	{0x110043, 0x0},
+	{0x210043, 0x0},
+	{0x010143, 0x0},
+	{0x110143, 0x0},
+	{0x210143, 0x0},
+	{0x011043, 0x0},
+	{0x111043, 0x0},
+	{0x211043, 0x0},
+	{0x011143, 0x0},
+	{0x111143, 0x0},
+	{0x211143, 0x0},
+	{0x000080, 0x0},
+	{0x100080, 0x0},
+	{0x200080, 0x0},
+	{0x001080, 0x0},
+	{0x101080, 0x0},
+	{0x201080, 0x0},
+	{0x002080, 0x0},
+	{0x102080, 0x0},
+	{0x202080, 0x0},
+	{0x003080, 0x0},
+	{0x103080, 0x0},
+	{0x203080, 0x0},
+	{0x004080, 0x0},
+	{0x104080, 0x0},
+	{0x204080, 0x0},
+	{0x005080, 0x0},
+	{0x105080, 0x0},
+	{0x205080, 0x0},
+	{0x006080, 0x0},
+	{0x106080, 0x0},
+	{0x206080, 0x0},
+	{0x007080, 0x0},
+	{0x107080, 0x0},
+	{0x207080, 0x0},
+	{0x008080, 0x0},
+	{0x108080, 0x0},
+	{0x208080, 0x0},
+	{0x009080, 0x0},
+	{0x109080, 0x0},
+	{0x209080, 0x0},
+	{0x010080, 0x0},
+	{0x110080, 0x0},
+	{0x210080, 0x0},
+	{0x010180, 0x0},
+	{0x110180, 0x0},
+	{0x210180, 0x0},
+	{0x011080, 0x0},
+	{0x111080, 0x0},
+	{0x211080, 0x0},
+	{0x011180, 0x0},
+	{0x111180, 0x0},
+	{0x211180, 0x0},
+	{0x010081, 0x0},
+	{0x110081, 0x0},
+	{0x210081, 0x0},
+	{0x010181, 0x0},
+	{0x110181, 0x0},
+	{0x210181, 0x0},
+	{0x011081, 0x0},
+	{0x111081, 0x0},
+	{0x211081, 0x0},
+	{0x011181, 0x0},
+	{0x111181, 0x0},
+	{0x211181, 0x0},
+	{0x0100d0, 0x0},
+	{0x1100d0, 0x0},
+	{0x2100d0, 0x0},
+	{0x0101d0, 0x0},
+	{0x1101d0, 0x0},
+	{0x2101d0, 0x0},
+	{0x0110d0, 0x0},
+	{0x1110d0, 0x0},
+	{0x2110d0, 0x0},
+	{0x0111d0, 0x0},
+	{0x1111d0, 0x0},
+	{0x2111d0, 0x0},
+	{0x0100d1, 0x0},
+	{0x1100d1, 0x0},
+	{0x2100d1, 0x0},
+	{0x0101d1, 0x0},
+	{0x1101d1, 0x0},
+	{0x2101d1, 0x0},
+	{0x0110d1, 0x0},
+	{0x1110d1, 0x0},
+	{0x2110d1, 0x0},
+	{0x0111d1, 0x0},
+	{0x1111d1, 0x0},
+	{0x2111d1, 0x0},
+	{0x010068, 0x0},
+	{0x010168, 0x0},
+	{0x010268, 0x0},
+	{0x010368, 0x0},
+	{0x010468, 0x0},
+	{0x010568, 0x0},
+	{0x010668, 0x0},
+	{0x010768, 0x0},
+	{0x010868, 0x0},
+	{0x011068, 0x0},
+	{0x011168, 0x0},
+	{0x011268, 0x0},
+	{0x011368, 0x0},
+	{0x011468, 0x0},
+	{0x011568, 0x0},
+	{0x011668, 0x0},
+	{0x011768, 0x0},
+	{0x011868, 0x0},
+	{0x010069, 0x0},
+	{0x010169, 0x0},
+	{0x010269, 0x0},
+	{0x010369, 0x0},
+	{0x010469, 0x0},
+	{0x010569, 0x0},
+	{0x010669, 0x0},
+	{0x010769, 0x0},
+	{0x010869, 0x0},
+	{0x011069, 0x0},
+	{0x011169, 0x0},
+	{0x011269, 0x0},
+	{0x011369, 0x0},
+	{0x011469, 0x0},
+	{0x011569, 0x0},
+	{0x011669, 0x0},
+	{0x011769, 0x0},
+	{0x011869, 0x0},
+	{0x01008c, 0x0},
+	{0x11008c, 0x0},
+	{0x21008c, 0x0},
+	{0x01018c, 0x0},
+	{0x11018c, 0x0},
+	{0x21018c, 0x0},
+	{0x01108c, 0x0},
+	{0x11108c, 0x0},
+	{0x21108c, 0x0},
+	{0x01118c, 0x0},
+	{0x11118c, 0x0},
+	{0x21118c, 0x0},
+	{0x01008d, 0x0},
+	{0x11008d, 0x0},
+	{0x21008d, 0x0},
+	{0x01018d, 0x0},
+	{0x11018d, 0x0},
+	{0x21018d, 0x0},
+	{0x01108d, 0x0},
+	{0x11108d, 0x0},
+	{0x21108d, 0x0},
+	{0x01118d, 0x0},
+	{0x11118d, 0x0},
+	{0x21118d, 0x0},
+	{0x0100c0, 0x0},
+	{0x1100c0, 0x0},
+	{0x2100c0, 0x0},
+	{0x0101c0, 0x0},
+	{0x1101c0, 0x0},
+	{0x2101c0, 0x0},
+	{0x0102c0, 0x0},
+	{0x1102c0, 0x0},
+	{0x2102c0, 0x0},
+	{0x0103c0, 0x0},
+	{0x1103c0, 0x0},
+	{0x2103c0, 0x0},
+	{0x0104c0, 0x0},
+	{0x1104c0, 0x0},
+	{0x2104c0, 0x0},
+	{0x0105c0, 0x0},
+	{0x1105c0, 0x0},
+	{0x2105c0, 0x0},
+	{0x0106c0, 0x0},
+	{0x1106c0, 0x0},
+	{0x2106c0, 0x0},
+	{0x0107c0, 0x0},
+	{0x1107c0, 0x0},
+	{0x2107c0, 0x0},
+	{0x0108c0, 0x0},
+	{0x1108c0, 0x0},
+	{0x2108c0, 0x0},
+	{0x0110c0, 0x0},
+	{0x1110c0, 0x0},
+	{0x2110c0, 0x0},
+	{0x0111c0, 0x0},
+	{0x1111c0, 0x0},
+	{0x2111c0, 0x0},
+	{0x0112c0, 0x0},
+	{0x1112c0, 0x0},
+	{0x2112c0, 0x0},
+	{0x0113c0, 0x0},
+	{0x1113c0, 0x0},
+	{0x2113c0, 0x0},
+	{0x0114c0, 0x0},
+	{0x1114c0, 0x0},
+	{0x2114c0, 0x0},
+	{0x0115c0, 0x0},
+	{0x1115c0, 0x0},
+	{0x2115c0, 0x0},
+	{0x0116c0, 0x0},
+	{0x1116c0, 0x0},
+	{0x2116c0, 0x0},
+	{0x0117c0, 0x0},
+	{0x1117c0, 0x0},
+	{0x2117c0, 0x0},
+	{0x0118c0, 0x0},
+	{0x1118c0, 0x0},
+	{0x2118c0, 0x0},
+	{0x0100c1, 0x0},
+	{0x1100c1, 0x0},
+	{0x2100c1, 0x0},
+	{0x0101c1, 0x0},
+	{0x1101c1, 0x0},
+	{0x2101c1, 0x0},
+	{0x0102c1, 0x0},
+	{0x1102c1, 0x0},
+	{0x2102c1, 0x0},
+	{0x0103c1, 0x0},
+	{0x1103c1, 0x0},
+	{0x2103c1, 0x0},
+	{0x0104c1, 0x0},
+	{0x1104c1, 0x0},
+	{0x2104c1, 0x0},
+	{0x0105c1, 0x0},
+	{0x1105c1, 0x0},
+	{0x2105c1, 0x0},
+	{0x0106c1, 0x0},
+	{0x1106c1, 0x0},
+	{0x2106c1, 0x0},
+	{0x0107c1, 0x0},
+	{0x1107c1, 0x0},
+	{0x2107c1, 0x0},
+	{0x0108c1, 0x0},
+	{0x1108c1, 0x0},
+	{0x2108c1, 0x0},
+	{0x0110c1, 0x0},
+	{0x1110c1, 0x0},
+	{0x2110c1, 0x0},
+	{0x0111c1, 0x0},
+	{0x1111c1, 0x0},
+	{0x2111c1, 0x0},
+	{0x0112c1, 0x0},
+	{0x1112c1, 0x0},
+	{0x2112c1, 0x0},
+	{0x0113c1, 0x0},
+	{0x1113c1, 0x0},
+	{0x2113c1, 0x0},
+	{0x0114c1, 0x0},
+	{0x1114c1, 0x0},
+	{0x2114c1, 0x0},
+	{0x0115c1, 0x0},
+	{0x1115c1, 0x0},
+	{0x2115c1, 0x0},
+	{0x0116c1, 0x0},
+	{0x1116c1, 0x0},
+	{0x2116c1, 0x0},
+	{0x0117c1, 0x0},
+	{0x1117c1, 0x0},
+	{0x2117c1, 0x0},
+	{0x0118c1, 0x0},
+	{0x1118c1, 0x0},
+	{0x2118c1, 0x0},
+	{0x010020, 0x0},
+	{0x110020, 0x0},
+	{0x210020, 0x0},
+	{0x011020, 0x0},
+	{0x111020, 0x0},
+	{0x211020, 0x0},
+	{0x020072, 0x0},
+	{0x020073, 0x0},
+	{0x020074, 0x0},
+	{0x0100aa, 0x0},
+	{0x0110aa, 0x0},
+	{0x020010, 0x0},
+	{0x120010, 0x0},
+	{0x220010, 0x0},
+	{0x020011, 0x0},
+	{0x120011, 0x0},
+	{0x220011, 0x0},
+	{0x0100ae, 0x0},
+	{0x1100ae, 0x0},
+	{0x2100ae, 0x0},
+	{0x0100af, 0x0},
+	{0x1100af, 0x0},
+	{0x2100af, 0x0},
+	{0x0110ae, 0x0},
+	{0x1110ae, 0x0},
+	{0x2110ae, 0x0},
+	{0x0110af, 0x0},
+	{0x1110af, 0x0},
+	{0x2110af, 0x0},
+	{0x020020, 0x0},
+	{0x120020, 0x0},
+	{0x220020, 0x0},
+	{0x0100a0, 0x0},
+	{0x0100a1, 0x0},
+	{0x0100a2, 0x0},
+	{0x0100a3, 0x0},
+	{0x0100a4, 0x0},
+	{0x0100a5, 0x0},
+	{0x0100a6, 0x0},
+	{0x0100a7, 0x0},
+	{0x0110a0, 0x0},
+	{0x0110a1, 0x0},
+	{0x0110a2, 0x0},
+	{0x0110a3, 0x0},
+	{0x0110a4, 0x0},
+	{0x0110a5, 0x0},
+	{0x0110a6, 0x0},
+	{0x0110a7, 0x0},
+	{0x02007c, 0x0},
+	{0x12007c, 0x0},
+	{0x22007c, 0x0},
+	{0x02007d, 0x0},
+	{0x12007d, 0x0},
+	{0x22007d, 0x0},
+	{0x0400fd, 0x0},
+	{0x0400c0, 0x0},
+	{0x090201, 0x0},
+	{0x190201, 0x0},
+	{0x290201, 0x0},
+	{0x090202, 0x0},
+	{0x190202, 0x0},
+	{0x290202, 0x0},
+	{0x090203, 0x0},
+	{0x190203, 0x0},
+	{0x290203, 0x0},
+	{0x090204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x090205, 0x0},
+	{0x190205, 0x0},
+	{0x290205, 0x0},
+	{0x090206, 0x0},
+	{0x190206, 0x0},
+	{0x290206, 0x0},
+	{0x090207, 0x0},
+	{0x190207, 0x0},
+	{0x290207, 0x0},
+	{0x090208, 0x0},
+	{0x190208, 0x0},
+	{0x290208, 0x0},
+	{0x010062, 0x0},
+	{0x010162, 0x0},
+	{0x010262, 0x0},
+	{0x010362, 0x0},
+	{0x010462, 0x0},
+	{0x010562, 0x0},
+	{0x010662, 0x0},
+	{0x010762, 0x0},
+	{0x010862, 0x0},
+	{0x011062, 0x0},
+	{0x011162, 0x0},
+	{0x011262, 0x0},
+	{0x011362, 0x0},
+	{0x011462, 0x0},
+	{0x011562, 0x0},
+	{0x011662, 0x0},
+	{0x011762, 0x0},
+	{0x011862, 0x0},
+	{0x020077, 0x0},
+	{0x010001, 0x0},
+	{0x011001, 0x0},
+	{0x010040, 0x0},
+	{0x010140, 0x0},
+	{0x010240, 0x0},
+	{0x010340, 0x0},
+	{0x010440, 0x0},
+	{0x010540, 0x0},
+	{0x010640, 0x0},
+	{0x010740, 0x0},
+	{0x010840, 0x0},
+	{0x010030, 0x0},
+	{0x010130, 0x0},
+	{0x010230, 0x0},
+	{0x010330, 0x0},
+	{0x010430, 0x0},
+	{0x010530, 0x0},
+	{0x010630, 0x0},
+	{0x010730, 0x0},
+	{0x010830, 0x0},
+	{0x011040, 0x0},
+	{0x011140, 0x0},
+	{0x011240, 0x0},
+	{0x011340, 0x0},
+	{0x011440, 0x0},
+	{0x011540, 0x0},
+	{0x011640, 0x0},
+	{0x011740, 0x0},
+	{0x011840, 0x0},
+	{0x011030, 0x0},
+	{0x011130, 0x0},
+	{0x011230, 0x0},
+	{0x011330, 0x0},
+	{0x011430, 0x0},
+	{0x011530, 0x0},
+	{0x011630, 0x0},
+	{0x011730, 0x0},
+	{0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000000},
+	{0x00054003, 0x00000c80},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x00000011},
+	{0x00054007, 0x00000000},
+	{0x00054008, 0x0000131f},
+	{0x00054009, 0x000000c8},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000002},
+	{0x0005400c, 0x00000000},
+	{0x0005400d, 0x00000000},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000100},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000310},
+	{0x00054013, 0x00000000},
+	{0x00054014, 0x00000000},
+	{0x00054015, 0x00000000},
+	{0x00054016, 0x00000000},
+	{0x00054017, 0x00000000},
+	{0x00054018, 0x00000000},
+	{0x00054019, 0x00002dd4},
+	{0x0005401a, 0x00000031},
+	{0x0005401b, 0x00004d66},
+	{0x0005401c, 0x00004a00},
+	{0x0005401d, 0x00000000},
+	{0x0005401e, 0x00000016},
+	{0x0005401f, 0x00002dd4},
+	{0x00054020, 0x00000031},
+	{0x00054021, 0x00004d66},
+	{0x00054022, 0x00004a00},
+	{0x00054023, 0x00000000},
+	{0x00054024, 0x0000002e},
+	{0x00054025, 0x00000000},
+	{0x00054026, 0x00000000},
+	{0x00054027, 0x00000000},
+	{0x00054028, 0x00000000},
+	{0x00054029, 0x00000000},
+	{0x0005402a, 0x00000000},
+	{0x0005402b, 0x00000000},
+	{0x0005402c, 0x00000000},
+	{0x0005402d, 0x00000000},
+	{0x0005402e, 0x00000000},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000000},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x0000d400},
+	{0x00054033, 0x0000312d},
+	{0x00054034, 0x00006600},
+	{0x00054035, 0x0000004d},
+	{0x00054036, 0x0000004a},
+	{0x00054037, 0x00001600},
+	{0x00054038, 0x0000d400},
+	{0x00054039, 0x0000312d},
+	{0x0005403a, 0x00006600},
+	{0x0005403b, 0x0000004d},
+	{0x0005403c, 0x0000004a},
+	{0x0005403d, 0x00002e00},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00000000},
+	{0x00054040, 0x00000000},
+	{0x00054041, 0x00000000},
+	{0x00054042, 0x00000000},
+	{0x00054043, 0x00000000},
+	{0x00054044, 0x00000000},
+	{0x000d0000, 0x00000001},
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000101},
+	{0x00054003, 0x00000190},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x00000011},
+	{0x00054007, 0x00000000},
+	{0x00054008, 0x0000121f},
+	{0x00054009, 0x000000c8},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000002},
+	{0x0005400c, 0x00000000},
+	{0x0005400d, 0x00000000},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000100},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000310},
+	{0x00054013, 0x00000000},
+	{0x00054014, 0x00000000},
+	{0x00054015, 0x00000000},
+	{0x00054016, 0x00000000},
+	{0x00054017, 0x00000000},
+	{0x00054018, 0x00000000},
+	{0x00054019, 0x00000084},
+	{0x0005401a, 0x00000031},
+	{0x0005401b, 0x00004d66},
+	{0x0005401c, 0x00004a00},
+	{0x0005401d, 0x00000000},
+	{0x0005401e, 0x00000016},
+	{0x0005401f, 0x00000084},
+	{0x00054020, 0x00000031},
+	{0x00054021, 0x00004d66},
+	{0x00054022, 0x00004a00},
+	{0x00054023, 0x00000000},
+	{0x00054024, 0x0000002e},
+	{0x00054025, 0x00000000},
+	{0x00054026, 0x00000000},
+	{0x00054027, 0x00000000},
+	{0x00054028, 0x00000000},
+	{0x00054029, 0x00000000},
+	{0x0005402a, 0x00000000},
+	{0x0005402b, 0x00000000},
+	{0x0005402c, 0x00000000},
+	{0x0005402d, 0x00000000},
+	{0x0005402e, 0x00000000},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000000},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x00008400},
+	{0x00054033, 0x00003100},
+	{0x00054034, 0x00006600},
+	{0x00054035, 0x0000004d},
+	{0x00054036, 0x0000004a},
+	{0x00054037, 0x00001600},
+	{0x00054038, 0x00008400},
+	{0x00054039, 0x00003100},
+	{0x0005403a, 0x00006600},
+	{0x0005403b, 0x0000004d},
+	{0x0005403c, 0x0000004a},
+	{0x0005403d, 0x00002e00},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00000000},
+	{0x00054040, 0x00000000},
+	{0x00054041, 0x00000000},
+	{0x00054042, 0x00000000},
+	{0x00054043, 0x00000000},
+	{0x00054044, 0x00000000},
+	{0x000d0000, 0x00000001},
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000102},
+	{0x00054003, 0x00000064},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x00000011},
+	{0x00054007, 0x00000000},
+	{0x00054008, 0x0000121f},
+	{0x00054009, 0x000000c8},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000002},
+	{0x0005400c, 0x00000000},
+	{0x0005400d, 0x00000000},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000100},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000310},
+	{0x00054013, 0x00000000},
+	{0x00054014, 0x00000000},
+	{0x00054015, 0x00000000},
+	{0x00054016, 0x00000000},
+	{0x00054017, 0x00000000},
+	{0x00054018, 0x00000000},
+	{0x00054019, 0x00000084},
+	{0x0005401a, 0x00000031},
+	{0x0005401b, 0x00004d66},
+	{0x0005401c, 0x00004a00},
+	{0x0005401d, 0x00000000},
+	{0x0005401e, 0x00000016},
+	{0x0005401f, 0x00000084},
+	{0x00054020, 0x00000031},
+	{0x00054021, 0x00004d66},
+	{0x00054022, 0x00004a00},
+	{0x00054023, 0x00000000},
+	{0x00054024, 0x0000002e},
+	{0x00054025, 0x00000000},
+	{0x00054026, 0x00000000},
+	{0x00054027, 0x00000000},
+	{0x00054028, 0x00000000},
+	{0x00054029, 0x00000000},
+	{0x0005402a, 0x00000000},
+	{0x0005402b, 0x00000000},
+	{0x0005402c, 0x00000000},
+	{0x0005402d, 0x00000000},
+	{0x0005402e, 0x00000000},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000000},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x00008400},
+	{0x00054033, 0x00003100},
+	{0x00054034, 0x00006600},
+	{0x00054035, 0x0000004d},
+	{0x00054036, 0x0000004a},
+	{0x00054037, 0x00001600},
+	{0x00054038, 0x00008400},
+	{0x00054039, 0x00003100},
+	{0x0005403a, 0x00006600},
+	{0x0005403b, 0x0000004d},
+	{0x0005403c, 0x0000004a},
+	{0x0005403d, 0x00002e00},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00000000},
+	{0x00054040, 0x00000000},
+	{0x00054041, 0x00000000},
+	{0x00054042, 0x00000000},
+	{0x00054043, 0x00000000},
+	{0x00054044, 0x00000000},
+	{0x000d0000, 0x00000001},
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000000},
+	{0x00054003, 0x00000c80},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x00000011},
+	{0x00054007, 0x00000000},
+	{0x00054008, 0x00000061},
+	{0x00054009, 0x000000c8},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000002},
+	{0x0005400c, 0x00000000},
+	{0x0005400d, 0x00000000},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000100},
+	{0x00054010, 0x00001f7f},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000310},
+	{0x00054013, 0x00000000},
+	{0x00054014, 0x00000000},
+	{0x00054015, 0x00000000},
+	{0x00054016, 0x00000000},
+	{0x00054017, 0x00000000},
+	{0x00054018, 0x00000000},
+	{0x00054019, 0x00002dd4},
+	{0x0005401a, 0x00000031},
+	{0x0005401b, 0x00004d66},
+	{0x0005401c, 0x00004a00},
+	{0x0005401d, 0x00000000},
+	{0x0005401e, 0x00000016},
+	{0x0005401f, 0x00002dd4},
+	{0x00054020, 0x00000031},
+	{0x00054021, 0x00004d66},
+	{0x00054022, 0x00004a00},
+	{0x00054023, 0x00000000},
+	{0x00054024, 0x0000002e},
+	{0x00054025, 0x00000000},
+	{0x00054026, 0x00000000},
+	{0x00054027, 0x00000000},
+	{0x00054028, 0x00000000},
+	{0x00054029, 0x00000000},
+	{0x0005402a, 0x00000000},
+	{0x0005402b, 0x00000000},
+	{0x0005402c, 0x00000000},
+	{0x0005402d, 0x00000000},
+	{0x0005402e, 0x00000000},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000000},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x0000d400},
+	{0x00054033, 0x0000312d},
+	{0x00054034, 0x00006600},
+	{0x00054035, 0x0000004d},
+	{0x00054036, 0x0000004a},
+	{0x00054037, 0x00001600},
+	{0x00054038, 0x0000d400},
+	{0x00054039, 0x0000312d},
+	{0x0005403a, 0x00006600},
+	{0x0005403b, 0x0000004d},
+	{0x0005403c, 0x0000004a},
+	{0x0005403d, 0x00002e00},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00000000},
+	{0x00054040, 0x00000000},
+	{0x00054041, 0x00000000},
+	{0x00054042, 0x00000000},
+	{0x00054043, 0x00000000},
+	{0x00054044, 0x00000000},
+	{0x000d0000, 0x00000001},
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xb},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x633},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x633},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x633},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x633},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x633},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x633},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x633},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x633},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x633},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x633},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x633},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x633},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x633},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xb},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x1},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x625},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x625},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a4, 0x0},
+	{0x900a5, 0x790},
+	{0x900a6, 0x11a},
+	{0x900a7, 0x8},
+	{0x900a8, 0x7aa},
+	{0x900a9, 0x2a},
+	{0x900aa, 0x10},
+	{0x900ab, 0x7b2},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x0},
+	{0x900ae, 0x7c8},
+	{0x900af, 0x109},
+	{0x900b0, 0x10},
+	{0x900b1, 0x10},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x1},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xd},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x448},
+	{0x90169, 0x109},
+	{0x9016a, 0xf},
+	{0x9016b, 0x7c0},
+	{0x9016c, 0x109},
+	{0x9016d, 0x0},
+	{0x9016e, 0xe8},
+	{0x9016f, 0x109},
+	{0x90170, 0x47},
+	{0x90171, 0x630},
+	{0x90172, 0x109},
+	{0x90173, 0x8},
+	{0x90174, 0x618},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0xe0},
+	{0x90178, 0x109},
+	{0x90179, 0x0},
+	{0x9017a, 0x7c8},
+	{0x9017b, 0x109},
+	{0x9017c, 0x8},
+	{0x9017d, 0x8140},
+	{0x9017e, 0x10c},
+	{0x9017f, 0x0},
+	{0x90180, 0x1},
+	{0x90181, 0x8},
+	{0x90182, 0x8},
+	{0x90183, 0x4},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x7c8},
+	{0x90187, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x29},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x64},
+	{0x2000c, 0xc8},
+	{0x2000d, 0x7d0},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xc},
+	{0x12000c, 0x19},
+	{0x12000d, 0xfa},
+	{0x12000e, 0x10},
+	{0x22000b, 0x3},
+	{0x22000c, 0x6},
+	{0x22000d, 0x3e},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x2060},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x20089, 0x1},
+	{0x20088, 0x19},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1},
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 400, 100, },
+};
diff --git a/roms/u-boot/board/freescale/imx8mn_evk/lpddr4_timing_ld.c b/roms/u-boot/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
new file mode 100644
index 000000000..aa23c3509
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
@@ -0,0 +1,1440 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa3080020 },
+	{ 0x3d400020, 0x111 },
+	{ 0x3d400024, 0x1f400 },
+	{ 0x3d400064, 0x300070 },
+	{ 0x3d4000d0, 0xc002030f },
+	{ 0x3d4000d4, 0x500000 },
+	{ 0x3d4000dc, 0xa40012 },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000ec, 0x16004d },
+	{ 0x3d400100, 0x10100d11 },
+	{ 0x3d400104, 0x3041a },
+	{ 0x3d40010c, 0x606000 },
+	{ 0x3d400110, 0x8040408 },
+	{ 0x3d400114, 0x2030606 },
+	{ 0x3d400118, 0x1010004 },
+	{ 0x3d40011c, 0x301 },
+	{ 0x3d400130, 0x20300 },
+	{ 0x3d400134, 0xa100002 },
+	{ 0x3d400138, 0x73 },
+	{ 0x3d400144, 0x500028 },
+	{ 0x3d400180, 0x190000c },
+	{ 0x3d400184, 0x14030d4 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x4898204 },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x904 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x4070f0f },
+	{ 0x3d400200, 0x17 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d400250, 0x29001701 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x11 },
+	{ 0x3d402024, 0x7d00 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020ec, 0x16004d },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x11 },
+	{ 0x3d403024, 0x1f40 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x310000 },
+	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030ec, 0x16004d },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0xb },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x1 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x190 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2005b, 0x7529 },
+	{ 0x2005c, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x200cc, 0x1f7 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x1200cc, 0x1f7 },
+	{ 0x2200c7, 0x21 },
+	{ 0x2200ca, 0x24 },
+	{ 0x2200cc, 0x1f7 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2, 0x0},
+	{0x1200b2, 0x0},
+	{0x2200b2, 0x0},
+	{0x0200cb, 0x0},
+	{0x010043, 0x0},
+	{0x110043, 0x0},
+	{0x210043, 0x0},
+	{0x010143, 0x0},
+	{0x110143, 0x0},
+	{0x210143, 0x0},
+	{0x011043, 0x0},
+	{0x111043, 0x0},
+	{0x211043, 0x0},
+	{0x011143, 0x0},
+	{0x111143, 0x0},
+	{0x211143, 0x0},
+	{0x000080, 0x0},
+	{0x100080, 0x0},
+	{0x200080, 0x0},
+	{0x001080, 0x0},
+	{0x101080, 0x0},
+	{0x201080, 0x0},
+	{0x002080, 0x0},
+	{0x102080, 0x0},
+	{0x202080, 0x0},
+	{0x003080, 0x0},
+	{0x103080, 0x0},
+	{0x203080, 0x0},
+	{0x004080, 0x0},
+	{0x104080, 0x0},
+	{0x204080, 0x0},
+	{0x005080, 0x0},
+	{0x105080, 0x0},
+	{0x205080, 0x0},
+	{0x006080, 0x0},
+	{0x106080, 0x0},
+	{0x206080, 0x0},
+	{0x007080, 0x0},
+	{0x107080, 0x0},
+	{0x207080, 0x0},
+	{0x008080, 0x0},
+	{0x108080, 0x0},
+	{0x208080, 0x0},
+	{0x009080, 0x0},
+	{0x109080, 0x0},
+	{0x209080, 0x0},
+	{0x010080, 0x0},
+	{0x110080, 0x0},
+	{0x210080, 0x0},
+	{0x010180, 0x0},
+	{0x110180, 0x0},
+	{0x210180, 0x0},
+	{0x011080, 0x0},
+	{0x111080, 0x0},
+	{0x211080, 0x0},
+	{0x011180, 0x0},
+	{0x111180, 0x0},
+	{0x211180, 0x0},
+	{0x010081, 0x0},
+	{0x110081, 0x0},
+	{0x210081, 0x0},
+	{0x010181, 0x0},
+	{0x110181, 0x0},
+	{0x210181, 0x0},
+	{0x011081, 0x0},
+	{0x111081, 0x0},
+	{0x211081, 0x0},
+	{0x011181, 0x0},
+	{0x111181, 0x0},
+	{0x211181, 0x0},
+	{0x0100d0, 0x0},
+	{0x1100d0, 0x0},
+	{0x2100d0, 0x0},
+	{0x0101d0, 0x0},
+	{0x1101d0, 0x0},
+	{0x2101d0, 0x0},
+	{0x0110d0, 0x0},
+	{0x1110d0, 0x0},
+	{0x2110d0, 0x0},
+	{0x0111d0, 0x0},
+	{0x1111d0, 0x0},
+	{0x2111d0, 0x0},
+	{0x0100d1, 0x0},
+	{0x1100d1, 0x0},
+	{0x2100d1, 0x0},
+	{0x0101d1, 0x0},
+	{0x1101d1, 0x0},
+	{0x2101d1, 0x0},
+	{0x0110d1, 0x0},
+	{0x1110d1, 0x0},
+	{0x2110d1, 0x0},
+	{0x0111d1, 0x0},
+	{0x1111d1, 0x0},
+	{0x2111d1, 0x0},
+	{0x010068, 0x0},
+	{0x010168, 0x0},
+	{0x010268, 0x0},
+	{0x010368, 0x0},
+	{0x010468, 0x0},
+	{0x010568, 0x0},
+	{0x010668, 0x0},
+	{0x010768, 0x0},
+	{0x010868, 0x0},
+	{0x011068, 0x0},
+	{0x011168, 0x0},
+	{0x011268, 0x0},
+	{0x011368, 0x0},
+	{0x011468, 0x0},
+	{0x011568, 0x0},
+	{0x011668, 0x0},
+	{0x011768, 0x0},
+	{0x011868, 0x0},
+	{0x010069, 0x0},
+	{0x010169, 0x0},
+	{0x010269, 0x0},
+	{0x010369, 0x0},
+	{0x010469, 0x0},
+	{0x010569, 0x0},
+	{0x010669, 0x0},
+	{0x010769, 0x0},
+	{0x010869, 0x0},
+	{0x011069, 0x0},
+	{0x011169, 0x0},
+	{0x011269, 0x0},
+	{0x011369, 0x0},
+	{0x011469, 0x0},
+	{0x011569, 0x0},
+	{0x011669, 0x0},
+	{0x011769, 0x0},
+	{0x011869, 0x0},
+	{0x01008c, 0x0},
+	{0x11008c, 0x0},
+	{0x21008c, 0x0},
+	{0x01018c, 0x0},
+	{0x11018c, 0x0},
+	{0x21018c, 0x0},
+	{0x01108c, 0x0},
+	{0x11108c, 0x0},
+	{0x21108c, 0x0},
+	{0x01118c, 0x0},
+	{0x11118c, 0x0},
+	{0x21118c, 0x0},
+	{0x01008d, 0x0},
+	{0x11008d, 0x0},
+	{0x21008d, 0x0},
+	{0x01018d, 0x0},
+	{0x11018d, 0x0},
+	{0x21018d, 0x0},
+	{0x01108d, 0x0},
+	{0x11108d, 0x0},
+	{0x21108d, 0x0},
+	{0x01118d, 0x0},
+	{0x11118d, 0x0},
+	{0x21118d, 0x0},
+	{0x0100c0, 0x0},
+	{0x1100c0, 0x0},
+	{0x2100c0, 0x0},
+	{0x0101c0, 0x0},
+	{0x1101c0, 0x0},
+	{0x2101c0, 0x0},
+	{0x0102c0, 0x0},
+	{0x1102c0, 0x0},
+	{0x2102c0, 0x0},
+	{0x0103c0, 0x0},
+	{0x1103c0, 0x0},
+	{0x2103c0, 0x0},
+	{0x0104c0, 0x0},
+	{0x1104c0, 0x0},
+	{0x2104c0, 0x0},
+	{0x0105c0, 0x0},
+	{0x1105c0, 0x0},
+	{0x2105c0, 0x0},
+	{0x0106c0, 0x0},
+	{0x1106c0, 0x0},
+	{0x2106c0, 0x0},
+	{0x0107c0, 0x0},
+	{0x1107c0, 0x0},
+	{0x2107c0, 0x0},
+	{0x0108c0, 0x0},
+	{0x1108c0, 0x0},
+	{0x2108c0, 0x0},
+	{0x0110c0, 0x0},
+	{0x1110c0, 0x0},
+	{0x2110c0, 0x0},
+	{0x0111c0, 0x0},
+	{0x1111c0, 0x0},
+	{0x2111c0, 0x0},
+	{0x0112c0, 0x0},
+	{0x1112c0, 0x0},
+	{0x2112c0, 0x0},
+	{0x0113c0, 0x0},
+	{0x1113c0, 0x0},
+	{0x2113c0, 0x0},
+	{0x0114c0, 0x0},
+	{0x1114c0, 0x0},
+	{0x2114c0, 0x0},
+	{0x0115c0, 0x0},
+	{0x1115c0, 0x0},
+	{0x2115c0, 0x0},
+	{0x0116c0, 0x0},
+	{0x1116c0, 0x0},
+	{0x2116c0, 0x0},
+	{0x0117c0, 0x0},
+	{0x1117c0, 0x0},
+	{0x2117c0, 0x0},
+	{0x0118c0, 0x0},
+	{0x1118c0, 0x0},
+	{0x2118c0, 0x0},
+	{0x0100c1, 0x0},
+	{0x1100c1, 0x0},
+	{0x2100c1, 0x0},
+	{0x0101c1, 0x0},
+	{0x1101c1, 0x0},
+	{0x2101c1, 0x0},
+	{0x0102c1, 0x0},
+	{0x1102c1, 0x0},
+	{0x2102c1, 0x0},
+	{0x0103c1, 0x0},
+	{0x1103c1, 0x0},
+	{0x2103c1, 0x0},
+	{0x0104c1, 0x0},
+	{0x1104c1, 0x0},
+	{0x2104c1, 0x0},
+	{0x0105c1, 0x0},
+	{0x1105c1, 0x0},
+	{0x2105c1, 0x0},
+	{0x0106c1, 0x0},
+	{0x1106c1, 0x0},
+	{0x2106c1, 0x0},
+	{0x0107c1, 0x0},
+	{0x1107c1, 0x0},
+	{0x2107c1, 0x0},
+	{0x0108c1, 0x0},
+	{0x1108c1, 0x0},
+	{0x2108c1, 0x0},
+	{0x0110c1, 0x0},
+	{0x1110c1, 0x0},
+	{0x2110c1, 0x0},
+	{0x0111c1, 0x0},
+	{0x1111c1, 0x0},
+	{0x2111c1, 0x0},
+	{0x0112c1, 0x0},
+	{0x1112c1, 0x0},
+	{0x2112c1, 0x0},
+	{0x0113c1, 0x0},
+	{0x1113c1, 0x0},
+	{0x2113c1, 0x0},
+	{0x0114c1, 0x0},
+	{0x1114c1, 0x0},
+	{0x2114c1, 0x0},
+	{0x0115c1, 0x0},
+	{0x1115c1, 0x0},
+	{0x2115c1, 0x0},
+	{0x0116c1, 0x0},
+	{0x1116c1, 0x0},
+	{0x2116c1, 0x0},
+	{0x0117c1, 0x0},
+	{0x1117c1, 0x0},
+	{0x2117c1, 0x0},
+	{0x0118c1, 0x0},
+	{0x1118c1, 0x0},
+	{0x2118c1, 0x0},
+	{0x010020, 0x0},
+	{0x110020, 0x0},
+	{0x210020, 0x0},
+	{0x011020, 0x0},
+	{0x111020, 0x0},
+	{0x211020, 0x0},
+	{0x020072, 0x0},
+	{0x020073, 0x0},
+	{0x020074, 0x0},
+	{0x0100aa, 0x0},
+	{0x0110aa, 0x0},
+	{0x020010, 0x0},
+	{0x120010, 0x0},
+	{0x220010, 0x0},
+	{0x020011, 0x0},
+	{0x120011, 0x0},
+	{0x220011, 0x0},
+	{0x0100ae, 0x0},
+	{0x1100ae, 0x0},
+	{0x2100ae, 0x0},
+	{0x0100af, 0x0},
+	{0x1100af, 0x0},
+	{0x2100af, 0x0},
+	{0x0110ae, 0x0},
+	{0x1110ae, 0x0},
+	{0x2110ae, 0x0},
+	{0x0110af, 0x0},
+	{0x1110af, 0x0},
+	{0x2110af, 0x0},
+	{0x020020, 0x0},
+	{0x120020, 0x0},
+	{0x220020, 0x0},
+	{0x0100a0, 0x0},
+	{0x0100a1, 0x0},
+	{0x0100a2, 0x0},
+	{0x0100a3, 0x0},
+	{0x0100a4, 0x0},
+	{0x0100a5, 0x0},
+	{0x0100a6, 0x0},
+	{0x0100a7, 0x0},
+	{0x0110a0, 0x0},
+	{0x0110a1, 0x0},
+	{0x0110a2, 0x0},
+	{0x0110a3, 0x0},
+	{0x0110a4, 0x0},
+	{0x0110a5, 0x0},
+	{0x0110a6, 0x0},
+	{0x0110a7, 0x0},
+	{0x02007c, 0x0},
+	{0x12007c, 0x0},
+	{0x22007c, 0x0},
+	{0x02007d, 0x0},
+	{0x12007d, 0x0},
+	{0x22007d, 0x0},
+	{0x0400fd, 0x0},
+	{0x0400c0, 0x0},
+	{0x090201, 0x0},
+	{0x190201, 0x0},
+	{0x290201, 0x0},
+	{0x090202, 0x0},
+	{0x190202, 0x0},
+	{0x290202, 0x0},
+	{0x090203, 0x0},
+	{0x190203, 0x0},
+	{0x290203, 0x0},
+	{0x090204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x090205, 0x0},
+	{0x190205, 0x0},
+	{0x290205, 0x0},
+	{0x090206, 0x0},
+	{0x190206, 0x0},
+	{0x290206, 0x0},
+	{0x090207, 0x0},
+	{0x190207, 0x0},
+	{0x290207, 0x0},
+	{0x090208, 0x0},
+	{0x190208, 0x0},
+	{0x290208, 0x0},
+	{0x010062, 0x0},
+	{0x010162, 0x0},
+	{0x010262, 0x0},
+	{0x010362, 0x0},
+	{0x010462, 0x0},
+	{0x010562, 0x0},
+	{0x010662, 0x0},
+	{0x010762, 0x0},
+	{0x010862, 0x0},
+	{0x011062, 0x0},
+	{0x011162, 0x0},
+	{0x011262, 0x0},
+	{0x011362, 0x0},
+	{0x011462, 0x0},
+	{0x011562, 0x0},
+	{0x011662, 0x0},
+	{0x011762, 0x0},
+	{0x011862, 0x0},
+	{0x020077, 0x0},
+	{0x010001, 0x0},
+	{0x011001, 0x0},
+	{0x010040, 0x0},
+	{0x010140, 0x0},
+	{0x010240, 0x0},
+	{0x010340, 0x0},
+	{0x010440, 0x0},
+	{0x010540, 0x0},
+	{0x010640, 0x0},
+	{0x010740, 0x0},
+	{0x010840, 0x0},
+	{0x010030, 0x0},
+	{0x010130, 0x0},
+	{0x010230, 0x0},
+	{0x010330, 0x0},
+	{0x010430, 0x0},
+	{0x010530, 0x0},
+	{0x010630, 0x0},
+	{0x010730, 0x0},
+	{0x010830, 0x0},
+	{0x011040, 0x0},
+	{0x011140, 0x0},
+	{0x011240, 0x0},
+	{0x011340, 0x0},
+	{0x011440, 0x0},
+	{0x011540, 0x0},
+	{0x011640, 0x0},
+	{0x011740, 0x0},
+	{0x011840, 0x0},
+	{0x011030, 0x0},
+	{0x011130, 0x0},
+	{0x011230, 0x0},
+	{0x011330, 0x0},
+	{0x011430, 0x0},
+	{0x011530, 0x0},
+	{0x011630, 0x0},
+	{0x011730, 0x0},
+	{0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x640 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x12a4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x12a4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0xa400 },
+	{ 0x54033, 0x3112 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xa400 },
+	{ 0x54039, 0x3112 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x640 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x12a4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x12a4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0xa400 },
+	{ 0x54033, 0x3112 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xa400 },
+	{ 0x54039, 0x3112 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x448 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0xf },
+	{ 0x9016b, 0x7c0 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x0 },
+	{ 0x9016e, 0xe8 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x47 },
+	{ 0x90171, 0x630 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x8 },
+	{ 0x90174, 0x618 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0xe0 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x7c8 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x8 },
+	{ 0x9017d, 0x8140 },
+	{ 0x9017e, 0x10c },
+	{ 0x9017f, 0x0 },
+	{ 0x90180, 0x1 },
+	{ 0x90181, 0x8 },
+	{ 0x90182, 0x8 },
+	{ 0x90183, 0x4 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x7c8 },
+	{ 0x90187, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x32 },
+	{ 0x2000c, 0x64 },
+	{ 0x2000d, 0x3e8 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 1600mts 1D */
+		.drate = 1600,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 1600mts 2D */
+		.drate = 1600,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 1600, 400, 100, },
+};
diff --git a/roms/u-boot/board/freescale/imx8mn_evk/spl.c b/roms/u-boot/board/freescale/imx8mn_evk/spl.c
new file mode 100644
index 000000000..03f2a56e8
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mn_evk/spl.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mn_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	puts("Normal Boot\n");
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0)
+		printf("Failed to find clock node. Check device tree\n");
+}
+
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pca9450@25", &dev);
+	if (ret == -ENODEV) {
+		puts("No pca9450@25\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
+
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
+	/* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
+#else
+	/* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
+#endif
+	/* Set DVS1 to 0.85v for suspend */
+	/* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+	/* set VDD_SNVS_0V8 from default 0.85V */
+	pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
+
+	/* enable LDO4 to 1.2v */
+	pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44);
+
+	/* set WDOG_B_CFG to cold reset */
+	pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	arch_cpu_init();
+
+	init_uart_clk(1);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/freescale/imx8mp_evk/Kconfig b/roms/u-boot/board/freescale/imx8mp_evk/Kconfig
new file mode 100644
index 000000000..49bb29a45
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mp_evk/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_IMX8MP_EVK
+
+config SYS_BOARD
+	default "imx8mp_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8mp_evk"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/imx8mp_evk/MAINTAINERS b/roms/u-boot/board/freescale/imx8mp_evk/MAINTAINERS
new file mode 100644
index 000000000..2759652cc
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mp_evk/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8MP EVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/imx8mp_evk/
+F:	include/configs/imx8mp_evk.h
+F:	configs/imx8mp_evk_defconfig
diff --git a/roms/u-boot/board/freescale/imx8mp_evk/Makefile b/roms/u-boot/board/freescale/imx8mp_evk/Makefile
new file mode 100644
index 000000000..106bf9a1e
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mp_evk/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2019 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mp_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/roms/u-boot/board/freescale/imx8mp_evk/imx8mp_evk.c b/roms/u-boot/board/freescale/imx8mp_evk/imx8mp_evk.c
new file mode 100644
index 000000000..89cc17cbe
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <linux/delay.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+static void setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Enable RGMII TX clk output */
+	setbits_le32(&gpr->gpr[1], BIT(22));
+}
+
+#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
+static iomux_v3_cfg_t const eqos_rst_pads[] = {
+	MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_eqos(void)
+{
+	imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
+					 ARRAY_SIZE(eqos_rst_pads));
+
+	gpio_request(EQOS_RST_PAD, "eqos_rst");
+	gpio_direction_output(EQOS_RST_PAD, 0);
+	mdelay(15);
+	gpio_direction_output(EQOS_RST_PAD, 1);
+	mdelay(100);
+}
+
+static int setup_eqos(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	setup_iomux_eqos();
+
+	/* set INTF as RGMII, enable RGMII TXC clock */
+	clrsetbits_le32(&gpr->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
+	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
+
+	return set_clk_eqos(ENET_125MHZ);
+}
+
+#if CONFIG_IS_ENABLED(NET)
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	int ret = 0;
+
+	if (CONFIG_IS_ENABLED(FEC_MXC)) {
+		setup_fec();
+
+		if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
+			ret = setup_eqos();
+	}
+
+	return ret;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "EVK");
+	env_set("board_rev", "iMX8MP");
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg b/roms/u-boot/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg
new file mode 100644
index 000000000..b2920b490
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#define __ASSEMBLY__
+
+ROM_VERSION	v2
+BOOT_FROM	sd
+LOADER		mkimage.flash.mkimage	0x920000
diff --git a/roms/u-boot/board/freescale/imx8mp_evk/lpddr4_timing.c b/roms/u-boot/board/freescale/imx8mp_evk/lpddr4_timing.c
new file mode 100644
index 000000000..8c5306d5d
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -0,0 +1,2048 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa3080020 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+	{ 0x3d400020, 0x223 },
+	{ 0x3d400024, 0x124f800 },
+	{ 0x3d400064, 0x4900a8 },
+	{ 0x3d400070, 0x1027f90 },
+	{ 0x3d400074, 0x790 },
+	{ 0x3d4000d0, 0xc0030495 },
+	{ 0x3d4000d4, 0x770000 },
+	{ 0x3d4000dc, 0xc40024 },
+#else
+	{ 0x3d400020, 0x1323 },
+	{ 0x3d400024, 0x1e84800 },
+	{ 0x3d400064, 0x7a017c },
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+	{ 0x3d400070, 0x1027f54 },
+#else
+	{ 0x3d400070, 0x1027f10 },
+#endif
+	{ 0x3d400074, 0x7b0 },
+	{ 0x3d4000d0, 0xc00307a3 },
+	{ 0x3d4000d4, 0xc50000 },
+	{ 0x3d4000dc, 0xf4003f },
+#endif
+	{ 0x3d4000e0, 0x330000 },
+	{ 0x3d4000e8, 0x660048 },
+	{ 0x3d4000ec, 0x160048 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+	{ 0x3d400100, 0x1618141a },
+	{ 0x3d400104, 0x504a6 },
+	{ 0x3d40010c, 0x909000 },
+	{ 0x3d400110, 0xb04060b },
+	{ 0x3d400114, 0x2030909 },
+	{ 0x3d400118, 0x1010006 },
+	{ 0x3d40011c, 0x301 },
+	{ 0x3d400130, 0x20500 },
+	{ 0x3d400134, 0xb100002 },
+	{ 0x3d400138, 0xad },
+	{ 0x3d400144, 0x78003c },
+	{ 0x3d400180, 0x2580012 },
+	{ 0x3d400184, 0x1e0493e },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x4938208 },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x1308 },
+#else
+	{ 0x3d400100, 0x2028222a },
+	{ 0x3d400104, 0x807bf },
+	{ 0x3d40010c, 0xe0e000 },
+	{ 0x3d400110, 0x12040a12 },
+	{ 0x3d400114, 0x2050f0f },
+	{ 0x3d400118, 0x1010009 },
+	{ 0x3d40011c, 0x501 },
+	{ 0x3d400130, 0x20800 },
+	{ 0x3d400134, 0xe100002 },
+	{ 0x3d400138, 0x184 },
+	{ 0x3d400144, 0xc80064 },
+	{ 0x3d400180, 0x3e8001e },
+	{ 0x3d400184, 0x3207a12 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x49f820e },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x1f0e },
+#endif
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+	{ 0x3d400108, 0x60c1514 },
+	{ 0x3d400200, 0x16 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x68070707 },
+	{ 0x3d40021c, 0xf08 },
+	{ 0x3d400250, 0x1f05 },
+	{ 0x3d400254, 0x1f },
+	{ 0x3d400264, 0x90003ff },
+	{ 0x3d40026c, 0x20003ff },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x1000e00 },
+	{ 0x3d400498, 0x3ff0000 },
+	{ 0x3d40049c, 0x1000e00 },
+	{ 0x3d4004a0, 0x3ff0000 },
+	{ 0x3d402020, 0x21 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d000 },
+	{ 0x3d402064, 0xc001c },
+#else
+	{ 0x3d400108, 0x9121c1c },
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+	{ 0x3d400200, 0x13 },
+	{ 0x3d40020c, 0x13131300 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x50505 },
+	{ 0x3d400214, 0x4040404 },
+	{ 0x3d400218, 0x68040404 },
+#else
+	{ 0x3d400200, 0x16 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x68070707 },
+#endif
+	{ 0x3d40021c, 0xf08 },
+	{ 0x3d400250, 0x1705 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400404, 0x72ff },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x1021 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d000 },
+	{ 0x3d402064, 0xc0026 },
+#endif
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x330000 },
+	{ 0x3d4020e8, 0x660048 },
+	{ 0x3d4020ec, 0x160048 },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x27 },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+	{ 0x3d403020, 0x21 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d000 },
+	{ 0x3d403064, 0x30007 },
+#else
+	{ 0x3d403020, 0x1021 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d000 },
+	{ 0x3d403064, 0x3000a },
+#endif
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x330000 },
+	{ 0x3d4030e8, 0x660048 },
+	{ 0x3d4030ec, 0x160048 },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0xa },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+	{ 0x200c5, 0xa },
+#else
+	{ 0x200c5, 0x18 },
+#endif
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+	{ 0x20008, 0x258 },
+#else
+	{ 0x20008, 0x3e8 },
+#endif
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x1204a, 0x500 },
+	{ 0x1304a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x24c4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x24c4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xc400 },
+	{ 0x54033, 0x3324 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xc400 },
+	{ 0x54039, 0x3324 },
+#else
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xfa0 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x3ff4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x3ff4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xf400 },
+	{ 0x54033, 0x333f },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xf400 },
+	{ 0x54039, 0x333f },
+#endif
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x24c4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x24c4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xc400 },
+	{ 0x54033, 0x3324 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xc400 },
+	{ 0x54039, 0x3324 },
+#else
+	{ 0x54003, 0xfa0 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x3ff4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x3ff4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xf400 },
+	{ 0x54033, 0x333f },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xf400 },
+	{ 0x54039, 0x333f },
+#endif
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x1 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x8 },
+	{ 0x90159, 0xe8 },
+	{ 0x9015a, 0x109 },
+	{ 0x9015b, 0x0 },
+	{ 0x9015c, 0x8140 },
+	{ 0x9015d, 0x10c },
+	{ 0x9015e, 0x10 },
+	{ 0x9015f, 0x8138 },
+	{ 0x90160, 0x104 },
+	{ 0x90161, 0x8 },
+	{ 0x90162, 0x448 },
+	{ 0x90163, 0x109 },
+	{ 0x90164, 0xf },
+	{ 0x90165, 0x7c0 },
+	{ 0x90166, 0x109 },
+	{ 0x90167, 0x0 },
+	{ 0x90168, 0xe8 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0x47 },
+	{ 0x9016b, 0x630 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x8 },
+	{ 0x9016e, 0x618 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0xe0 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x0 },
+	{ 0x90174, 0x7c8 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x8140 },
+	{ 0x90178, 0x10c },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x478 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x1 },
+	{ 0x9017e, 0x8 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x4 },
+	{ 0x90181, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x68 },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+	{ 0x2000b, 0x4b },
+	{ 0x2000c, 0x96 },
+	{ 0x2000d, 0x5dc },
+#else
+	{ 0x200be, 0x3 },
+	{ 0x2000b, 0x7d },
+	{ 0x2000c, 0xfa },
+	{ 0x2000d, 0x9c4 },
+#endif
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
+#endif
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+		/* P0 2400mts 1D */
+		.drate = 2400,
+#else
+		/* P0 4000mts 1D */
+		.drate = 4000,
+#endif
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+		/* P0 2400mts 2D */
+		.drate = 2400,
+#else
+		/* P0 4000mts 2D */
+		.drate = 4000,
+#endif
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+	.fsp_table = { 2400, 400, 100, },
+#else
+	.fsp_table = { 4000, 400, 100, },
+#endif
+};
+
+#ifndef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+void board_dram_ecc_scrub(void)
+{
+	ddrc_inline_ecc_scrub(0x0, 0x3ffffff);
+	ddrc_inline_ecc_scrub(0x20000000, 0x23ffffff);
+	ddrc_inline_ecc_scrub(0x40000000, 0x43ffffff);
+	ddrc_inline_ecc_scrub(0x4000000, 0x7ffffff);
+	ddrc_inline_ecc_scrub(0x24000000, 0x27ffffff);
+	ddrc_inline_ecc_scrub(0x44000000, 0x47ffffff);
+	ddrc_inline_ecc_scrub(0x8000000, 0xbffffff);
+	ddrc_inline_ecc_scrub(0x28000000, 0x2bffffff);
+	ddrc_inline_ecc_scrub(0x48000000, 0x4bffffff);
+	ddrc_inline_ecc_scrub(0xc000000, 0xfffffff);
+	ddrc_inline_ecc_scrub(0x2c000000, 0x2fffffff);
+	ddrc_inline_ecc_scrub(0x4c000000, 0x4fffffff);
+	ddrc_inline_ecc_scrub(0x10000000, 0x13ffffff);
+	ddrc_inline_ecc_scrub(0x30000000, 0x33ffffff);
+	ddrc_inline_ecc_scrub(0x50000000, 0x53ffffff);
+	ddrc_inline_ecc_scrub(0x14000000, 0x17ffffff);
+	ddrc_inline_ecc_scrub(0x34000000, 0x37ffffff);
+	ddrc_inline_ecc_scrub(0x54000000, 0x57ffffff);
+	ddrc_inline_ecc_scrub(0x18000000, 0x1bffffff);
+	ddrc_inline_ecc_scrub(0x38000000, 0x3bffffff);
+	ddrc_inline_ecc_scrub(0x58000000, 0x5bffffff);
+	ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff);
+}
+#endif
+#endif
diff --git a/roms/u-boot/board/freescale/imx8mp_evk/spl.c b/roms/u-boot/board/freescale/imx8mp_evk/spl.c
new file mode 100644
index 000000000..a7564e9b1
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mp_evk/spl.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+	/*
+	 * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
+	 * not allow to change it. Should set the clock after PMIC
+	 * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
+	 * set by ROM for ND VDD_SOC
+	 */
+	clock_enable(CCGR_GIC, 0);
+	clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+	clock_enable(CCGR_GIC, 1);
+
+	puts("Normal Boot\n");
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+
+	ret = power_pca9450_init(I2C_PMIC, 0x25);
+	if (ret)
+		printf("power init failed");
+	p = pmic_get("PCA9450");
+	pmic_probe(p);
+
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+
+	/*
+	 * increase VDD_SOC to typical value 0.95V before first
+	 * DRAM access, set DVS1 to 0.85v for suspend.
+	 * Enable DVS control through PMIC_STBY_REQ and
+	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+	 */
+#ifdef CONFIG_IMX8M_VDD_SOC_850MV
+	/* set DVS0 to 0.85v for special case*/
+	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
+#else
+	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
+#endif
+	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
+	pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+
+	/* Kernel uses OD/OD freq for SOC */
+	/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
+	pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
+
+	/* set WDOG_B_CFG to cold reset */
+	pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+/* Do not use BSS area in this phase */
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	arch_cpu_init();
+
+	init_uart_clk(1);
+
+	board_early_init_f();
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	preloader_console_init();
+
+	enable_tzc380();
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
diff --git a/roms/u-boot/board/freescale/imx8mq_evk/Kconfig b/roms/u-boot/board/freescale/imx8mq_evk/Kconfig
new file mode 100644
index 000000000..421b081c7
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mq_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MQ_EVK
+
+config SYS_BOARD
+	default "imx8mq_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_evk"
+
+endif
diff --git a/roms/u-boot/board/freescale/imx8mq_evk/MAINTAINERS b/roms/u-boot/board/freescale/imx8mq_evk/MAINTAINERS
new file mode 100644
index 000000000..a00bb4ef7
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mq_evk/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX8MQ EVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/freescale/imx8mq_evk/
+F:	include/configs/imx8mq_evk.h
+F:	configs/imx8mq_evk_defconfig
diff --git a/roms/u-boot/board/freescale/imx8mq_evk/Makefile b/roms/u-boot/board/freescale/imx8mq_evk/Makefile
new file mode 100644
index 000000000..cf046963d
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mq_evk/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mq_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
+endif
diff --git a/roms/u-boot/board/freescale/imx8mq_evk/imx8mq_evk.c b/roms/u-boot/board/freescale/imx8mq_evk/imx8mq_evk.c
new file mode 100644
index 000000000..93da67d77
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mq_evk/imx8mq_evk.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <linux/bitops.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "EVK");
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/imx8mq_evk/lpddr4_timing.c b/roms/u-boot/board/freescale/imx8mq_evk/lpddr4_timing.c
new file mode 100644
index 000000000..46bc7f859
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mq_evk/lpddr4_timing.c
@@ -0,0 +1,1324 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+#define WR_POST_EXT_3200	/* recommened to define */
+
+struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/* Start to config, default 3200mbps */
+	{ DDRC_DBG1(0), 0x00000001 },
+	{ DDRC_PWRCTL(0), 0x00000001 },
+	{ DDRC_MSTR(0), 0xa3080020 },
+	{ DDRC_MSTR2(0), 0x00000000 },
+	{ DDRC_RFSHTMG(0), 0x006100E0 },
+	{ DDRC_INIT0(0), 0xC003061B },
+	{ DDRC_INIT1(0), 0x009D0000 },
+	{ DDRC_INIT3(0), 0x00D4002D },
+#ifdef WR_POST_EXT_3200
+	{ DDRC_INIT4(0), 0x00330008 },
+#else
+	{ DDRC_INIT4(0), 0x00310008 },
+#endif
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0006004a },
+
+	{ DDRC_DRAMTMG0(0), 0x1A201B22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00C0C000 },
+	{ DDRC_DRAMTMG4(0), 0x0F04080F },
+	{ DDRC_DRAMTMG5(0), 0x02040C0C },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x00000401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0C100002 },
+	{ DDRC_DRAMTMG14(0), 0x000000E6 },
+	{ DDRC_DRAMTMG17(0), 0x00A00050 },
+
+	{ DDRC_ZQCTL0(0), 0x03200018 },
+	{ DDRC_ZQCTL1(0), 0x028061A8 },
+	{ DDRC_ZQCTL2(0), 0x00000000 },
+
+	{ DDRC_DFITMG0(0), 0x0497820A },
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xE0400018 },
+	{ DDRC_DFIUPD1(0), 0x00DF00E4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x00000011 },
+	{ DDRC_DFITMG2(0), 0x0000170A },
+
+	{ DDRC_DBICTL(0), 0x00000001 },
+	{ DDRC_DFIPHYMSTR(0), 0x00000001 },
+	{ DDRC_RANKCTL(0), 0x00000c99 },
+	{ DDRC_DRAMTMG2(0), 0x070E171a },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), 0x00000015 },
+	{ DDRC_ADDRMAP3(0), 0x00000000 },
+	{ DDRC_ADDRMAP4(0), 0x00001F1F },
+	/* bank interleave */
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	{ DDRC_ADDRMAP6(0), 0x08080707 },
+
+	/* performance setting */
+	{ DDRC_ODTCFG(0), 0x0b060908 },
+	{ DDRC_ODTMAP(0), 0x00000000 },
+	{ DDRC_SCHED(0), 0x29511505 },
+	{ DDRC_SCHED1(0), 0x0000002c },
+	{ DDRC_PERFHPR1(0), 0x5900575b },
+	/* 150T starve and 0x90 max tran len */
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	/* 300T starve and 0x10 max tran len */
+	{ DDRC_PERFWR1(0), 0x1000012c },
+	{ DDRC_DBG0(0), 0x00000016 },
+	{ DDRC_DBG1(0), 0x00000000 },
+	{ DDRC_DBGCMD(0), 0x00000000 },
+	{ DDRC_SWCTL(0), 0x00000001 },
+	{ DDRC_POISONCFG(0), 0x00000011 },
+	{ DDRC_PCCFG(0), 0x00000111 },
+	{ DDRC_PCFGR_0(0), 0x000010f3 },
+	{ DDRC_PCFGW_0(0), 0x000072ff },
+	{ DDRC_PCTRL_0(0), 0x00000001 },
+	/* disable Read Qos*/
+	{ DDRC_PCFGQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	/* disable Write Qos*/
+	{ DDRC_PCFGWQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0x0000ffff },
+
+	/* Frequency 1: 400mbps */
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
+	{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
+	{ DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03818200 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x00000000 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
+	{ DDRC_FREQ1_INIT3(0), 0x00840000 },
+	{ DDRC_FREQ1_INIT4(0), 0x00310008 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0006004a },
+
+	/* Frequency 2: 100mbps */
+	{ DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
+	{ DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
+	{ DDRC_FREQ2_DRAMTMG2(0), 0x0305090c },
+	{ DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
+	{ DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
+	{ DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
+	{ DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
+	{ DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
+	{ DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
+	{ DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
+	{ DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
+	{ DDRC_FREQ2_DFITMG0(0), 0x03818200 },
+	{ DDRC_FREQ2_DFITMG2(0), 0x00000000 },
+	{ DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
+	{ DDRC_FREQ2_INIT3(0), 0x00840000 },
+	{ DDRC_FREQ2_INIT4(0), 0x00310008 },
+	{ DDRC_FREQ2_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ2_INIT7(0), 0x0006004a },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x20110, 0x02 },
+	{ 0x20111, 0x03 },
+	{ 0x20112, 0x04 },
+	{ 0x20113, 0x05 },
+	{ 0x20114, 0x00 },
+	{ 0x20115, 0x01 },
+
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+
+#ifdef WR_POST_EXT_3200
+	{ 0x20024, 0xeb },
+#else
+	{ 0x20024, 0xab },
+#endif
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0xab },
+	{ 0x2003a, 0x0 },
+	{ 0x220024, 0xab },
+	{ 0x2003a, 0x0 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0xa },
+	{ 0x220056, 0xa },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+
+	{ 0x10049, 0xfbe },
+	{ 0x10149, 0xfbe },
+	{ 0x11049, 0xfbe },
+	{ 0x11149, 0xfbe },
+	{ 0x12049, 0xfbe },
+	{ 0x12149, 0xfbe },
+	{ 0x13049, 0xfbe },
+	{ 0x13149, 0xfbe },
+	{ 0x110049, 0xfbe },
+	{ 0x110149, 0xfbe },
+	{ 0x111049, 0xfbe },
+	{ 0x111149, 0xfbe },
+	{ 0x112049, 0xfbe },
+	{ 0x112149, 0xfbe },
+	{ 0x113049, 0xfbe },
+	{ 0x113149, 0xfbe },
+	{ 0x210049, 0xfbe },
+	{ 0x210149, 0xfbe },
+	{ 0x211049, 0xfbe },
+	{ 0x211149, 0xfbe },
+	{ 0x212049, 0xfbe },
+	{ 0x212149, 0xfbe },
+	{ 0x213049, 0xfbe },
+	{ 0x213149, 0xfbe },
+
+	{ 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x320 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+
+	{ 0x200c7, 0x80 },
+	{ 0x1200c7, 0x80 },
+	{ 0x2200c7, 0x80 },
+	{ 0x200ca, 0x106 },
+	{ 0x1200ca, 0x106 },
+	{ 0x2200ca, 0x106 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+
+	{ 0x54019, 0x2dd4 },
+#ifdef WR_POST_EXT_3200
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
+#else
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
+#endif
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401f, 0x2dd4 },
+#ifdef WR_POST_EXT_3200
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
+#else
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
+#endif
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	/* MR3/MR2 */
+#ifdef WR_POST_EXT_3200
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ },
+#else
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
+#endif
+	/* MR11/MR4 */
+	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+	/* self:0x284d//MR13/MR12 */
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
+	/* MR16/MR14*/
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ },
+	/* MR1 */
+	{ 0x54038, 0xd400 },
+	/* MR3/MR2 */
+#ifdef WR_POST_EXT_3200
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ },
+#else
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
+#endif
+	/* MR11/MR4 */
+	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+	/* self:0x284d//MR13/MR12 */
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
+	/* MR16/MR14 */
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
+	/* { 0x5403d, 0x500 } */
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	/* PHY Ron/Rtt */
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, LPDDR4_TRAIN_SEQ_400 },
+	{ 0x54009, LPDDR4_HDT_CTL_400_1D },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, (LPDDR4_CATRAIN_400 << 8) },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	/* MR4/MR3 */
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ },
+	/* MR12/MR11 */
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
+		    LPDDR4_RTT_DQ)/*0x4d46*/ },
+	/* self:0x4d28//MR14/MR13 */
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
+		    LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */
+	/* self:0x4d28//MR14/MR13 */
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
+	{ 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
+	{ 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, LPDDR4_TRAIN_SEQ_100 },
+	{ 0x54009, LPDDR4_HDT_CTL_100_1D },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, (LPDDR4_CATRAIN_100 << 8) },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
+		    LPDDR4_RTT_DQ) },
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
+		    LPDDR4_RTT_DQ) },
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
+	{ 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
+	{ 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, LPDDR4_HDT_CTL_2D },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
+	{ 0x54010, LPDDR4_2D_WEIGHT },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+#ifdef WR_POST_EXT_3200
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
+#else
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
+#endif
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401f, 0x2dd4 },
+#ifdef WR_POST_EXT_3200
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
+#else
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
+#endif
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+
+	{ 0x54032, 0xd400 },
+#ifdef WR_POST_EXT_3200
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+#else
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
+#endif
+	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54038, 0xd400 },
+#ifdef WR_POST_EXT_3200
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+#else
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
+#endif
+	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xf },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a7, 0x0 },
+	{ 0x900a8, 0x790 },
+	{ 0x900a9, 0x11a },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x7b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x0 },
+	{ 0x900b1, 0x7c8 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xc },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x0 },
+	{ 0x90169, 0x8 },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x448 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
+	{ 0x9016e, 0x7c0 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x7c8 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x7d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x2003a, 0x2 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P1 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.fsp_table = { 3200, 400, 100, },
+};
diff --git a/roms/u-boot/board/freescale/imx8mq_evk/lpddr4_timing_b0.c b/roms/u-boot/board/freescale/imx8mq_evk/lpddr4_timing_b0.c
new file mode 100644
index 000000000..ec68edaf6
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mq_evk/lpddr4_timing_b0.c
@@ -0,0 +1,1191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+#define WR_POST_EXT_3200  /* recommened to define */
+
+static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/* Start to config, default 3200mbps */
+	/* dis_dq=1, indicates no reads or writes are issued to SDRAM */
+	{ DDRC_DBG1(0), 0x00000001 },
+	/* selfref_en=1, SDRAM enter self-refresh state */
+	{ DDRC_PWRCTL(0), 0x00000001 },
+	{ DDRC_MSTR(0), 0xa3080020 },
+	{ DDRC_MSTR2(0), 0x00000000 },
+	{ DDRC_RFSHTMG(0), 0x006100E0 },
+	{ DDRC_INIT0(0), 0xC003061B },
+	{ DDRC_INIT1(0), 0x009D0000 },
+	{ DDRC_INIT3(0), 0x00D4002D },
+#ifdef WR_POST_EXT_3200  /* recommened to define */
+	{ DDRC_INIT4(0), 0x00330008 },
+#else
+	{ DDRC_INIT4(0), 0x00310008 },
+#endif
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0006004a },
+
+	{ DDRC_DRAMTMG0(0), 0x1A201B22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00C0C000 },
+	{ DDRC_DRAMTMG4(0), 0x0F04080F },
+	{ DDRC_DRAMTMG5(0), 0x02040C0C },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x00000401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0C100002 },
+	{ DDRC_DRAMTMG14(0), 0x000000E6 },
+	{ DDRC_DRAMTMG17(0), 0x00A00050 },
+
+	{ DDRC_ZQCTL0(0), 0x03200018 },
+	{ DDRC_ZQCTL1(0), 0x028061A8 },
+	{ DDRC_ZQCTL2(0), 0x00000000 },
+
+	{ DDRC_DFITMG0(0), 0x0497820A },
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xE0400018 },
+	{ DDRC_DFIUPD1(0), 0x00DF00E4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x00000011 },
+	{ DDRC_DFITMG2(0), 0x0000170A },
+
+	{ DDRC_DBICTL(0), 0x00000001 },
+	{ DDRC_DFIPHYMSTR(0), 0x00000001 },
+
+	/* need be refined by ddrphy trained value */
+	{ DDRC_RANKCTL(0), 0x00000c99 },
+	{ DDRC_DRAMTMG2(0), 0x070E171a },
+
+	/* address mapping */
+	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+	{ DDRC_ADDRMAP0(0), 0x00000015 },
+	{ DDRC_ADDRMAP3(0), 0x00000000 },
+	/* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */
+	{ DDRC_ADDRMAP4(0), 0x00001F1F },
+	/* bank interleave */
+	/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	/* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	/* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */
+	{ DDRC_ADDRMAP6(0), 0x08080707 },
+
+	/* 667mts frequency setting */
+	{ DDRC_FREQ1_DERATEEN(0), 0x0000000 },
+	{ DDRC_FREQ1_DERATEINT(0), 0x0800000 },
+	{ DDRC_FREQ1_RFSHCTL0(0), 0x0210000 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x014001E },
+	{ DDRC_FREQ1_INIT3(0), 0x0140009 },
+	{ DDRC_FREQ1_INIT4(0), 0x00310008 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0006004a },
+	{ DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x003040A },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x305080C },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x0505000 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x3040203 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x2030303 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x2020004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0000302 },
+	{ DDRC_FREQ1_DRAMTMG12(0), 0x0020310 },
+	{ DDRC_FREQ1_DRAMTMG13(0), 0xA100002 },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x0000020 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x0220011 },
+	{ DDRC_FREQ1_ZQCTL0(0), 0x0A70005 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x3858202 },
+	{ DDRC_FREQ1_DFITMG1(0), 0x0000404 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x0000502 },
+
+	/* performance setting */
+	{ DDRC_ODTCFG(0), 0x0b060908 },
+	{ DDRC_ODTMAP(0), 0x00000000 },
+	{ DDRC_SCHED(0), 0x29511505 },
+	{ DDRC_SCHED1(0), 0x0000002c },
+	{ DDRC_PERFHPR1(0), 0x5900575b },
+	/* 150T starve and 0x90 max tran len */
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	/* 300T starve and 0x10 max tran len */
+	{ DDRC_PERFWR1(0), 0x1000012c },
+	{ DDRC_DBG0(0), 0x00000016 },
+	{ DDRC_DBG1(0), 0x00000000 },
+	{ DDRC_DBGCMD(0), 0x00000000 },
+	{ DDRC_SWCTL(0), 0x00000001 },
+	{ DDRC_POISONCFG(0), 0x00000011 },
+	{ DDRC_PCCFG(0), 0x00000111 },
+	{ DDRC_PCFGR_0(0), 0x000010f3 },
+	{ DDRC_PCFGW_0(0), 0x000072ff },
+	{ DDRC_PCTRL_0(0), 0x00000001 },
+	/* disable Read Qos*/
+	{ DDRC_PCFGQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	/* disable Write Qos*/
+	{ DDRC_PCFGWQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0x0000ffff },
+	{ DDRC_FREQ1_DERATEEN(0), 0x00000202 },
+	{ DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 },
+	{ DDRC_FREQ1_RFSHCTL0(0), 0x00618040 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x00610090 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x20110, 0x02 }, /* MapCAB0toDFI */
+	{ 0x20111, 0x03 }, /* MapCAB1toDFI */
+	{ 0x20112, 0x04 }, /* MapCAB2toDFI */
+	{ 0x20113, 0x05 }, /* MapCAB3toDFI */
+	{ 0x20114, 0x00 }, /* MapCAB4toDFI */
+	{ 0x20115, 0x01 }, /* MapCAB5toDFI */
+
+	/* Initialize PHY Configuration */
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x1 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+
+	{ 0x20024, 0xe3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0xa3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0xa3 },
+	{ 0x2003a, 0x2 },
+
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0xa },
+	{ 0x220056, 0xa },
+
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+
+	{ 0x10049, 0xfbe },
+	{ 0x10149, 0xfbe },
+	{ 0x11049, 0xfbe },
+	{ 0x11149, 0xfbe },
+	{ 0x12049, 0xfbe },
+	{ 0x12149, 0xfbe },
+	{ 0x13049, 0xfbe },
+	{ 0x13149, 0xfbe },
+
+	{ 0x110049, 0xfbe },
+	{ 0x110149, 0xfbe },
+	{ 0x111049, 0xfbe },
+	{ 0x111149, 0xfbe },
+	{ 0x112049, 0xfbe },
+	{ 0x112149, 0xfbe },
+	{ 0x113049, 0xfbe },
+	{ 0x113149, 0xfbe },
+
+	{ 0x210049, 0xfbe },
+	{ 0x210149, 0xfbe },
+	{ 0x211049, 0xfbe },
+	{ 0x211149, 0xfbe },
+	{ 0x212049, 0xfbe },
+	{ 0x212149, 0xfbe },
+	{ 0x213049, 0xfbe },
+	{ 0x213149, 0xfbe },
+
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x320 },
+	{ 0x120008, 0xa7 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x600 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5655 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x29c },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x914 },
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+	{ 0x5401e, 0x6 },
+	{ 0x5401f, 0x914 },
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x1400 },
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
+	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+	{ 0x54037, 0x600 },
+	{ 0x54038, 0x1400 },
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
+	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0xd0000, 0x1 },
+
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, LPDDR4_HDT_CTL_2D },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
+	{ 0x54010, LPDDR4_2D_WEIGHT },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54024, 0x5 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0xd },
+	{ 0x900a5, 0x7c0 },
+	{ 0x900a6, 0x109 },
+	{ 0x900a7, 0x4 },
+	{ 0x900a8, 0x7c0 },
+	{ 0x900a9, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900aa, 0x0 },
+	{ 0x900ab, 0x790 },
+	{ 0x900ac, 0x11a },
+	{ 0x900ad, 0x8 },
+	{ 0x900ae, 0x7aa },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x7b2 },
+	{ 0x900b2, 0x2a },
+	{ 0x900b3, 0x0 },
+	{ 0x900b4, 0x7c8 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x10 },
+	{ 0x900b7, 0x10 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x10 },
+	{ 0x900ba, 0x2a8 },
+	{ 0x900bb, 0x129 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0x370 },
+	{ 0x900be, 0x129 },
+	{ 0x900bf, 0xa },
+	{ 0x900c0, 0x3c8 },
+	{ 0x900c1, 0x1a9 },
+	{ 0x900c2, 0xc },
+	{ 0x900c3, 0x408 },
+	{ 0x900c4, 0x199 },
+	{ 0x900c5, 0x14 },
+	{ 0x900c6, 0x790 },
+	{ 0x900c7, 0x11a },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x4 },
+	{ 0x900ca, 0x18 },
+	{ 0x900cb, 0xe },
+	{ 0x900cc, 0x408 },
+	{ 0x900cd, 0x199 },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x8568 },
+	{ 0x900d0, 0x108 },
+	{ 0x900d1, 0x18 },
+	{ 0x900d2, 0x790 },
+	{ 0x900d3, 0x16a },
+	{ 0x900d4, 0x8 },
+	{ 0x900d5, 0x1d8 },
+	{ 0x900d6, 0x169 },
+	{ 0x900d7, 0x10 },
+	{ 0x900d8, 0x8558 },
+	{ 0x900d9, 0x168 },
+	{ 0x900da, 0x70 },
+	{ 0x900db, 0x788 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x1ff8 },
+	{ 0x900de, 0x85a8 },
+	{ 0x900df, 0x1e8 },
+	{ 0x900e0, 0x50 },
+	{ 0x900e1, 0x798 },
+	{ 0x900e2, 0x16a },
+	{ 0x900e3, 0x60 },
+	{ 0x900e4, 0x7a0 },
+	{ 0x900e5, 0x16a },
+	{ 0x900e6, 0x8 },
+	{ 0x900e7, 0x8310 },
+	{ 0x900e8, 0x168 },
+	{ 0x900e9, 0x8 },
+	{ 0x900ea, 0xa310 },
+	{ 0x900eb, 0x168 },
+	{ 0x900ec, 0xa },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x6e },
+	{ 0x900f0, 0x0 },
+	{ 0x900f1, 0x68 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0x408 },
+	{ 0x900f4, 0x169 },
+	{ 0x900f5, 0x0 },
+	{ 0x900f6, 0x8310 },
+	{ 0x900f7, 0x168 },
+	{ 0x900f8, 0x0 },
+	{ 0x900f9, 0xa310 },
+	{ 0x900fa, 0x168 },
+	{ 0x900fb, 0x1ff8 },
+	{ 0x900fc, 0x85a8 },
+	{ 0x900fd, 0x1e8 },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x798 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x78 },
+	{ 0x90102, 0x7a0 },
+	{ 0x90103, 0x16a },
+	{ 0x90104, 0x68 },
+	{ 0x90105, 0x790 },
+	{ 0x90106, 0x16a },
+	{ 0x90107, 0x8 },
+	{ 0x90108, 0x8b10 },
+	{ 0x90109, 0x168 },
+	{ 0x9010a, 0x8 },
+	{ 0x9010b, 0xab10 },
+	{ 0x9010c, 0x168 },
+	{ 0x9010d, 0xa },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x58 },
+	{ 0x90111, 0x0 },
+	{ 0x90112, 0x68 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0x408 },
+	{ 0x90115, 0x169 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x8b10 },
+	{ 0x90118, 0x168 },
+	{ 0x90119, 0x0 },
+	{ 0x9011a, 0xab10 },
+	{ 0x9011b, 0x168 },
+	{ 0x9011c, 0x0 },
+	{ 0x9011d, 0x1d8 },
+	{ 0x9011e, 0x169 },
+	{ 0x9011f, 0x80 },
+	{ 0x90120, 0x790 },
+	{ 0x90121, 0x16a },
+	{ 0x90122, 0x18 },
+	{ 0x90123, 0x7aa },
+	{ 0x90124, 0x6a },
+	{ 0x90125, 0xa },
+	{ 0x90126, 0x0 },
+	{ 0x90127, 0x1e9 },
+	{ 0x90128, 0x8 },
+	{ 0x90129, 0x8080 },
+	{ 0x9012a, 0x108 },
+	{ 0x9012b, 0xf },
+	{ 0x9012c, 0x408 },
+	{ 0x9012d, 0x169 },
+	{ 0x9012e, 0xc },
+	{ 0x9012f, 0x0 },
+	{ 0x90130, 0x68 },
+	{ 0x90131, 0x9 },
+	{ 0x90132, 0x0 },
+	{ 0x90133, 0x1a9 },
+	{ 0x90134, 0x0 },
+	{ 0x90135, 0x408 },
+	{ 0x90136, 0x169 },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8080 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0x8 },
+	{ 0x9013b, 0x7aa },
+	{ 0x9013c, 0x6a },
+	{ 0x9013d, 0x0 },
+	{ 0x9013e, 0x8568 },
+	{ 0x9013f, 0x108 },
+	{ 0x90140, 0xb7 },
+	{ 0x90141, 0x790 },
+	{ 0x90142, 0x16a },
+	{ 0x90143, 0x1f },
+	{ 0x90144, 0x0 },
+	{ 0x90145, 0x68 },
+	{ 0x90146, 0x8 },
+	{ 0x90147, 0x8558 },
+	{ 0x90148, 0x168 },
+	{ 0x90149, 0xf },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0xc },
+	{ 0x9014d, 0x0 },
+	{ 0x9014e, 0x68 },
+	{ 0x9014f, 0x0 },
+	{ 0x90150, 0x408 },
+	{ 0x90151, 0x169 },
+	{ 0x90152, 0x0 },
+	{ 0x90153, 0x8558 },
+	{ 0x90154, 0x168 },
+	{ 0x90155, 0x8 },
+	{ 0x90156, 0x3c8 },
+	{ 0x90157, 0x1a9 },
+	{ 0x90158, 0x3 },
+	{ 0x90159, 0x370 },
+	{ 0x9015a, 0x129 },
+	{ 0x9015b, 0x20 },
+	{ 0x9015c, 0x2aa },
+	{ 0x9015d, 0x9 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x400 },
+	{ 0x90160, 0x10e },
+	{ 0x90161, 0x8 },
+	{ 0x90162, 0xe8 },
+	{ 0x90163, 0x109 },
+	{ 0x90164, 0x0 },
+	{ 0x90165, 0x8140 },
+	{ 0x90166, 0x10c },
+	{ 0x90167, 0x10 },
+	{ 0x90168, 0x8138 },
+	{ 0x90169, 0x10c },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x7c8 },
+	{ 0x9016c, 0x101 },
+	{ 0x9016d, 0x8 },
+	{ 0x9016e, 0x0 },
+	{ 0x9016f, 0x8 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0x448 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0xf },
+	{ 0x90174, 0x7c0 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x0 },
+	{ 0x90177, 0xe8 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x47 },
+	{ 0x9017a, 0x630 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x8 },
+	{ 0x9017d, 0x618 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0xe0 },
+	{ 0x90181, 0x109 },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x7c8 },
+	{ 0x90184, 0x109 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x8140 },
+	{ 0x90187, 0x10c },
+	{ 0x90188, 0x0 },
+	{ 0x90189, 0x1 },
+	{ 0x9018a, 0x8 },
+	{ 0x9018b, 0x8 },
+	{ 0x9018c, 0x4 },
+	{ 0x9018d, 0x8 },
+	{ 0x9018e, 0x8 },
+	{ 0x9018f, 0x7c8 },
+	{ 0x90190, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2b },
+	{ 0x90026, 0x6c },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x7d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x14 },
+	{ 0x12000c, 0x29 },
+	{ 0x12000d, 0x1a1 },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing_b0 = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	/*
+	 * this table must be initialized if DDRPHY bypass mode is
+	 * not used: all fsp drate > 666MTS.
+	 */
+	.fsp_table = { 3200, 667, },
+};
diff --git a/roms/u-boot/board/freescale/imx8mq_evk/spl.c b/roms/u-boot/board/freescale/imx8mq_evk/spl.c
new file mode 100644
index 000000000..e8e0efe48
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8mq_evk/spl.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <spl.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern struct dram_timing_info dram_timing_b0;
+
+static void spl_dram_init(void)
+{
+	/* ddr init */
+	if (soc_rev() >= CHIP_REV_2_1)
+		ddr_init(&dram_timing);
+	else
+		ddr_init(&dram_timing_b0);
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+							 ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+							 ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return -ENODEV;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return -ENODEV;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
+	if ((reg & 0x3f) != 0x18) {
+		reg &= ~0x3f;
+		reg |= 0x18;
+		pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
+	}
+
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* set SW3A standby mode to off */
+	pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
+	reg &= ~0xf;
+	reg |= APS_OFF;
+	pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
+
+	return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/freescale/imx8qm_mek/Kconfig b/roms/u-boot/board/freescale/imx8qm_mek/Kconfig
new file mode 100644
index 000000000..93d7d5f9c
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qm_mek/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_IMX8QM_MEK
+
+config SYS_BOARD
+	default "imx8qm_mek"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8qm_mek"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/imx8qm_mek/MAINTAINERS b/roms/u-boot/board/freescale/imx8qm_mek/MAINTAINERS
new file mode 100644
index 000000000..115830df1
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qm_mek/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8QM MEK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/imx8qm_mek/
+F:	include/configs/imx8qm_mek.h
+F:	configs/imx8qm_mek_defconfig
diff --git a/roms/u-boot/board/freescale/imx8qm_mek/Makefile b/roms/u-boot/board/freescale/imx8qm_mek/Makefile
new file mode 100644
index 000000000..bc9a1260b
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qm_mek/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += imx8qm_mek.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/roms/u-boot/board/freescale/imx8qm_mek/README b/roms/u-boot/board/freescale/imx8qm_mek/README
new file mode 100644
index 000000000..570ed7e21
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qm_mek/README
@@ -0,0 +1,54 @@
+U-Boot for the NXP i.MX8QM EVK board
+
+Quick Start
+===========
+
+- Build the ARM Trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ cd imx-atf/
+$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
+$ make PLAT=imx8qm bl31
+
+And copy the resulting bl31.bin to u-boot directory:
+
+$ cp build/imx8qm/release/bl31.bin path/to/u-boot/
+
+Get scfw_tcm.bin and ahab-container.img
+=======================================
+
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
+$ chmod +x imx-sc-firmware-1.1.bin
+$ ./imx-sc-firmware-1.1.bin
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+$ chmod +x firmware-imx-8.0.bin
+$ ./firmware-imx-8.0.bin
+
+
+And copy the following firmwares to U-Boot folder:
+
+* `imx-sc-firmware-1.1/mx8qm-mek-scfw-tcm.bin`
+* `firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img`
+
+Build U-Boot
+============
+$ make imx8qm_mek_defconfig
+$ make flash.bin
+
+Flash the binary into the SD card
+=================================
+
+Burn the flash.bin binary to SD card offset 32KB:
+
+$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
+
+Boot
+====
+Set Boot switch SW2: 001100.
diff --git a/roms/u-boot/board/freescale/imx8qm_mek/imx8qm_mek.c b/roms/u-boot/board/freescale/imx8qm_mek/imx8qm_mek.c
new file mode 100644
index 000000000..682099ad9
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qm_mek/imx8qm_mek.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	int ret;
+
+	/* Set UART0 clock root to 80 MHz */
+	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+	sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
+
+	return 0;
+}
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
+static void board_gpio_init(void)
+{
+	/* TODO */
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: iMX8QM MEK\n");
+
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Power up base board */
+	sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
+
+	board_gpio_init();
+
+	return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+	/* TODO */
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+	char *fdt_file;
+	bool m4_booted;
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "MEK");
+	env_set("board_rev", "iMX8QM");
+#endif
+
+	fdt_file = env_get("fdt_file");
+	m4_booted = m4_parts_booted();
+
+	if (fdt_file && !strcmp(fdt_file, "undefined")) {
+		if (m4_booted)
+			env_set("fdt_file", "imx8qm-mek-rpmsg.dtb");
+		else
+			env_set("fdt_file", "imx8qm-mek.dtb");
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/imx8qm_mek/imximage.cfg b/roms/u-boot/board/freescale/imx8qm_mek/imximage.cfg
new file mode 100644
index 000000000..7dc6b93eb
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qm_mek/imximage.cfg
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QM */
+SOC_TYPE IMX8QM
+/* Append seco container image */
+APPEND mx8qm-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qm-mek-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/roms/u-boot/board/freescale/imx8qm_mek/spl.c b/roms/u-boot/board/freescale/imx8qm_mek/spl.c
new file mode 100644
index 000000000..944ba745c
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qm_mek/spl.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+
+	uclass_find_first_device(UCLASS_MISC, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	puts("Normal Boot\n");
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	imx8_power_off_pd_devices(NULL, 0);
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/freescale/imx8qm_mek/uboot-container.cfg b/roms/u-boot/board/freescale/imx8qm_mek/uboot-container.cfg
new file mode 100644
index 000000000..6cc47cd10
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qm_mek/uboot-container.cfg
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* This file is to create a container image could be loaded by SPL */
+BOOT_FROM SD 0x400
+SOC_TYPE IMX8QM
+CONTAINER
+IMAGE A35 bl31.bin	0x80000000
+IMAGE A35 u-boot.bin	CONFIG_SYS_TEXT_BASE
diff --git a/roms/u-boot/board/freescale/imx8qxp_mek/Kconfig b/roms/u-boot/board/freescale/imx8qxp_mek/Kconfig
new file mode 100644
index 000000000..b67300d81
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qxp_mek/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_IMX8QXP_MEK
+
+config SYS_BOARD
+	default "imx8qxp_mek"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8qxp_mek"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/imx8qxp_mek/MAINTAINERS b/roms/u-boot/board/freescale/imx8qxp_mek/MAINTAINERS
new file mode 100644
index 000000000..3a21f5521
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qxp_mek/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX8QXP MEK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/freescale/imx8qxp_mek/
+F:	include/configs/imx8qxp_mek.h
+F:	configs/imx8qxp_mek_defconfig
diff --git a/roms/u-boot/board/freescale/imx8qxp_mek/Makefile b/roms/u-boot/board/freescale/imx8qxp_mek/Makefile
new file mode 100644
index 000000000..acaadcd84
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qxp_mek/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += imx8qxp_mek.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/roms/u-boot/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/roms/u-boot/board/freescale/imx8qxp_mek/imx8qxp_mek.c
new file mode 100644
index 000000000..21cfa142f
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fsl_esdhc_imx.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/snvs_security_sc.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	int ret;
+
+	/* Set UART0 clock root to 80 MHz */
+	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
+static void board_gpio_init(void)
+{
+	struct gpio_desc desc;
+	int ret;
+
+	ret = dm_gpio_lookup_name("gpio@1a_3", &desc);
+	if (ret)
+		return;
+
+	ret = dm_gpio_request(&desc, "bb_per_rst_b");
+	if (ret)
+		return;
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc, 0);
+	udelay(50);
+	dm_gpio_set_value(&desc, 1);
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: iMX8QXP MEK\n");
+
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	board_gpio_init();
+
+#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
+	{
+		int ret = snvs_security_sc_init();
+
+		if (ret)
+			return ret;
+	}
+#endif
+
+	return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+	/* TODO */
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+	char *fdt_file;
+	bool m4_booted;
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "MEK");
+	env_set("board_rev", "iMX8QXP");
+#endif
+
+	fdt_file = env_get("fdt_file");
+	m4_booted = m4_parts_booted();
+
+	if (fdt_file && !strcmp(fdt_file, "undefined")) {
+		if (m4_booted)
+			env_set("fdt_file", "imx8qxp-mek-rpmsg.dtb");
+		else
+			env_set("fdt_file", "imx8qxp-mek.dtb");
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/imx8qxp_mek/imximage.cfg b/roms/u-boot/board/freescale/imx8qxp_mek/imximage.cfg
new file mode 100644
index 000000000..cd747d2ee
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qxp_mek/imximage.cfg
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ *
+ * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qx-mek-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/roms/u-boot/board/freescale/imx8qxp_mek/spl.c b/roms/u-boot/board/freescale/imx8qxp_mek/spl.c
new file mode 100644
index 000000000..ae6b64ff6
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qxp_mek/spl.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define USDHC2_SD_PWR IMX_GPIO_NR(4, 19)
+static iomux_cfg_t usdhc2_sd_pwr[] = {
+	SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+
+	uclass_find_first_device(UCLASS_MISC, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	imx8_iomux_setup_multiple_pads(usdhc2_sd_pwr, ARRAY_SIZE(usdhc2_sd_pwr));
+	gpio_direction_output(USDHC2_SD_PWR, 0);
+
+	preloader_console_init();
+
+	puts("Normal Boot\n");
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	imx8_power_off_pd_devices(NULL, 0);
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/freescale/imx8qxp_mek/uboot-container.cfg b/roms/u-boot/board/freescale/imx8qxp_mek/uboot-container.cfg
new file mode 100644
index 000000000..816581181
--- /dev/null
+++ b/roms/u-boot/board/freescale/imx8qxp_mek/uboot-container.cfg
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* This file is to create a container image could be loaded by SPL */
+BOOT_FROM SD 0x400
+SOC_TYPE IMX8QX
+CONTAINER
+IMAGE A35 bl31.bin	0x80000000
+IMAGE A35 u-boot.bin	CONFIG_SYS_TEXT_BASE
diff --git a/roms/u-boot/board/freescale/imxrt1020-evk/Kconfig b/roms/u-boot/board/freescale/imxrt1020-evk/Kconfig
new file mode 100644
index 000000000..d00cbff09
--- /dev/null
+++ b/roms/u-boot/board/freescale/imxrt1020-evk/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_IMXRT1020_EVK
+
+config SYS_BOARD
+	string
+	default "imxrt1020-evk"
+
+config SYS_VENDOR
+	string
+	default "freescale"
+
+config SYS_SOC
+	string
+	default "imxrt1020"
+
+config SYS_CONFIG_NAME
+	string
+	default "imxrt1020-evk"
+
+config IMX_CONFIG
+	default "board/freescale/imxrt1020-evk/imximage.cfg"
+
+endif
diff --git a/roms/u-boot/board/freescale/imxrt1020-evk/MAINTAINERS b/roms/u-boot/board/freescale/imxrt1020-evk/MAINTAINERS
new file mode 100644
index 000000000..05f017b2b
--- /dev/null
+++ b/roms/u-boot/board/freescale/imxrt1020-evk/MAINTAINERS
@@ -0,0 +1,6 @@
+IMXRT1020 EVALUATION KIT
+M:	Giulio Benetti <giulio.benetti@benettiengineering.com>
+S:	Maintained
+F:	board/freescale/imxrt1020-evk
+F:	include/configs/imxrt1020-evk.h
+F:	configs/imxrt1020-evk_defconfig
diff --git a/roms/u-boot/board/freescale/imxrt1020-evk/Makefile b/roms/u-boot/board/freescale/imxrt1020-evk/Makefile
new file mode 100644
index 000000000..807dc7c35
--- /dev/null
+++ b/roms/u-boot/board/freescale/imxrt1020-evk/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+
+obj-y	:= imxrt1020-evk.o
diff --git a/roms/u-boot/board/freescale/imxrt1020-evk/imximage.cfg b/roms/u-boot/board/freescale/imxrt1020-evk/imximage.cfg
new file mode 100644
index 000000000..9bcc2c159
--- /dev/null
+++ b/roms/u-boot/board/freescale/imxrt1020-evk/imximage.cfg
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Set all FlexRAM as OCRAM(01b) */
+DATA 4 0x400AC044 0x00005555
+/* Use FLEXRAM_BANK_CFG to config FlexRAM */
+SET_BIT 4 0x400AC040 0x4
diff --git a/roms/u-boot/board/freescale/imxrt1020-evk/imxrt1020-evk.c b/roms/u-boot/board/freescale/imxrt1020-evk/imxrt1020-evk.c
new file mode 100644
index 000000000..479e66bdd
--- /dev/null
+++ b/roms/u-boot/board/freescale/imxrt1020-evk/imxrt1020-evk.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SUPPORT_SPL
+	int rv;
+	struct udevice *dev;
+
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv) {
+		debug("DRAM init failed: %d\n", rv);
+		return rv;
+	}
+
+#endif
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	debug("SPL: booting kernel\n");
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+int spl_dram_init(void)
+{
+	struct udevice *dev;
+	int rv;
+
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv)
+		debug("DRAM init failed: %d\n", rv);
+	return rv;
+}
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+	spl_dram_init();
+	arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_MMC1;
+}
+#endif
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/imxrt1050-evk/Kconfig b/roms/u-boot/board/freescale/imxrt1050-evk/Kconfig
new file mode 100644
index 000000000..79e6e4524
--- /dev/null
+++ b/roms/u-boot/board/freescale/imxrt1050-evk/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_IMXRT1050_EVK
+
+config SYS_BOARD
+	string
+	default "imxrt1050-evk"
+
+config SYS_VENDOR
+	string
+	default "freescale"
+
+config SYS_SOC
+	string
+	default "imxrt1050"
+
+config SYS_CONFIG_NAME
+	string
+	default "imxrt1050-evk"
+
+config IMX_CONFIG
+	default "board/freescale/imxrt1050-evk/imximage.cfg"
+
+endif
diff --git a/roms/u-boot/board/freescale/imxrt1050-evk/MAINTAINERS b/roms/u-boot/board/freescale/imxrt1050-evk/MAINTAINERS
new file mode 100644
index 000000000..a87285545
--- /dev/null
+++ b/roms/u-boot/board/freescale/imxrt1050-evk/MAINTAINERS
@@ -0,0 +1,6 @@
+IMXRT1050 EVALUATION KIT
+M:	Giulio Benetti <giulio.benetti@benettiengineering.com>
+S:	Maintained
+F:	board/freescale/imxrt1050-evk
+F:	include/configs/imxrt1050-evk.h
+F:	configs/imxrt1050-evk_defconfig
diff --git a/roms/u-boot/board/freescale/imxrt1050-evk/Makefile b/roms/u-boot/board/freescale/imxrt1050-evk/Makefile
new file mode 100644
index 000000000..0e984d1d7
--- /dev/null
+++ b/roms/u-boot/board/freescale/imxrt1050-evk/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+
+obj-y	:= imxrt1050-evk.o
diff --git a/roms/u-boot/board/freescale/imxrt1050-evk/imximage.cfg b/roms/u-boot/board/freescale/imxrt1050-evk/imximage.cfg
new file mode 100644
index 000000000..cf1665be6
--- /dev/null
+++ b/roms/u-boot/board/freescale/imxrt1050-evk/imximage.cfg
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Set all FlexRAM as OCRAM(01b) */
+DATA 4 0x400AC044 0x55555555
+/* Use FLEXRAM_BANK_CFG to config FlexRAM */
+SET_BIT 4 0x400AC040 0x4
diff --git a/roms/u-boot/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/roms/u-boot/board/freescale/imxrt1050-evk/imxrt1050-evk.c
new file mode 100644
index 000000000..eb492390d
--- /dev/null
+++ b/roms/u-boot/board/freescale/imxrt1050-evk/imxrt1050-evk.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SUPPORT_SPL
+	int rv;
+	struct udevice *dev;
+
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv) {
+		debug("DRAM init failed: %d\n", rv);
+		return rv;
+	}
+
+#endif
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	debug("SPL: booting kernel\n");
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+int spl_dram_init(void)
+{
+	struct udevice *dev;
+	int rv;
+
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv)
+		debug("DRAM init failed: %d\n", rv);
+	return rv;
+}
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+	spl_dram_init();
+	arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_MMC1;
+}
+#endif
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/ls1012afrdm/Kconfig b/roms/u-boot/board/freescale/ls1012afrdm/Kconfig
new file mode 100644
index 000000000..4ac69d711
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012afrdm/Kconfig
@@ -0,0 +1,95 @@
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+	default "ls1012afrdm"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012afrdm"
+
+config SYS_LS_PFE_FW_ADDR
+	hex "Flash address of PFE firmware"
+	default 0x40a00000
+
+config SYS_LS_PFE_FW_LENGTH
+	hex "length of PFE firmware"
+	default 0x40000
+
+config SYS_LS_PPA_FW_ADDR
+	hex "PPA Firmware Addr"
+	default 0x40400000
+endif
+
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select PHYLIB
+	imply PHY_REALTEK
+	imply PHY_ATHEROS
+
+config DDR_PFE_PHYS_BASEADDR
+	hex "PFE DDR physical base address"
+	default 0x03800000
+
+config DDR_PFE_BASEADDR
+	hex "PFE DDR base address"
+	default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+	hex "PFE DDR base address"
+	default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+	hex "PFE DDR base address"
+	default 0x1
+
+endif
+
+if TARGET_LS1012AFRWY
+
+config SYS_BOARD
+	default "ls1012afrdm"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012afrwy"
+
+config SYS_LS_PFE_FW_ADDR
+	hex "Flash address of PFE firmware"
+	default 0x40020000
+
+config SYS_LS_PFE_FW_LENGTH
+	hex "length of PFE firmware"
+	default 0x40000
+
+config SYS_LS_PPA_FW_ADDR
+	hex "PPA Firmware Addr"
+	default 0x40060000
+
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA Firmware HDR Addr"
+	default 0x401f4000
+
+config SYS_LS_PFE_ESBC_ADDR
+	hex "PFE Firmware HDR Addr"
+	default 0x401f8000
+
+config SYS_LS_PFE_ESBC_LENGTH
+	hex "length of PFE Firmware HDR"
+	default 0xc00
+endif
+
+if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY
+source "board/freescale/common/Kconfig"
+endif
diff --git a/roms/u-boot/board/freescale/ls1012afrdm/MAINTAINERS b/roms/u-boot/board/freescale/ls1012afrdm/MAINTAINERS
new file mode 100644
index 000000000..5fc7e9385
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012afrdm/MAINTAINERS
@@ -0,0 +1,17 @@
+LS1012AFRDM BOARD
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012afrdm/
+F:	include/configs/ls1012afrdm.h
+F:	configs/ls1012afrdm_qspi_defconfig
+F:	configs/ls1012afrdm_tfa_defconfig
+F:	configs/ls1012afrwy_tfa_defconfig
+F:	configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+
+LS1012AFRWY BOARD
+M:	Pramod Kumar <pramod.kumar_1@nxp.com>
+S:      Maintained
+F:      board/freescale/ls1012afrwy/
+F:      include/configs/ls1012afrwy.h
+F:      configs/ls1012afrwy_qspi_defconfig
+F:	configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/ls1012afrdm/Makefile b/roms/u-boot/board/freescale/ls1012afrdm/Makefile
new file mode 100644
index 000000000..1e53c9673
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012afrdm/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012afrdm.o
+obj-$(CONFIG_FSL_PFE) += eth.o
diff --git a/roms/u-boot/board/freescale/ls1012afrdm/README b/roms/u-boot/board/freescale/ls1012afrdm/README
new file mode 100644
index 000000000..181c4615a
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012afrdm/README
@@ -0,0 +1,58 @@
+Overview
+--------
+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
+platform, with a complete debugging environment. The LS1012AFRDM board
+supports the QorIQ LS1012A processor and is optimized to support the
+high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+ LS1012AFRDM board Overview
+ -----------------------
+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
+     - 2 SGMII 1G PHYs
+ - DDR Controller
+     - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
+	operating at 1.35 V
+ - QSPI
+     - Onboard 512 Mbit QSPI flash memory running at speed up
+      to 108/54 MHz
+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
+     - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
+       Micro-AB connector.
+     - USB 2.0 port is a debug port (CMSIS DAP) and is configured
+       as a Micro-AB device.
+ - I2C controller
+     - One I2C bus with connectivity to Arduino headers
+ - UART
+     - UART (Console): UART1 (Without flow control) for console
+ - ARM JTAG support
+     - ARM Cortex® 10-pin JTAG connector for LS1012A
+     - CMSIS DAP through K20 microcontroller
+ - SAI Audio interface
+     - One SAI port, SAI 2 with full duplex support
+ - Clocks
+     - 25 MHz crystal for LS1012A
+     - 8 MHz Crystal for K20
+     - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
+ - Power Supplies
+     - 5 V input supply from USB
+     - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
+       other board interfaces
+
+Booting Options
+---------------
+QSPI Flash 1
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000
diff --git a/roms/u-boot/board/freescale/ls1012afrdm/eth.c b/roms/u-boot/board/freescale/ls1012afrdm/eth.c
new file mode 100644
index 000000000..d2df9351e
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012afrdm/eth.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include <linux/delay.h>
+#include <net/pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+#define MASK_ETH_PHY_RST	0x00000100
+
+static inline void ls1012afrdm_reset_phy(void)
+{
+	unsigned int val;
+	struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
+
+	setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST);
+
+	val = in_be32(&pgpio->gpdat);
+	setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST);
+	mdelay(10);
+
+	val = in_be32(&pgpio->gpdat);
+	setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
+	mdelay(50);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+	static int init_done;
+	struct mii_dev *bus;
+	struct pfe_mdio_info mac_mdio_info;
+	struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+	if (!init_done) {
+		ls1012afrdm_reset_phy();
+
+		mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+		mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+		bus = pfe_mdio_init(&mac_mdio_info);
+		if (!bus) {
+			printf("Failed to register mdio\n");
+			return -1;
+		}
+
+		init_done = 1;
+	}
+
+	if (priv->gemac_port) {
+		mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+		mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+		bus = pfe_mdio_init(&mac_mdio_info);
+		if (!bus) {
+			printf("Failed to register mdio\n");
+			return -1;
+		}
+	}
+
+	pfe_set_mdio(priv->gemac_port,
+		     miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+	if (!priv->gemac_port)
+		/* MAC1 */
+		pfe_set_phy_address_mode(priv->gemac_port,
+					 CONFIG_PFE_EMAC1_PHY_ADDR,
+					 PHY_INTERFACE_MODE_SGMII);
+	else
+		/* MAC2 */
+		pfe_set_phy_address_mode(priv->gemac_port,
+					 CONFIG_PFE_EMAC2_PHY_ADDR,
+					 PHY_INTERFACE_MODE_SGMII);
+	return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+	.pfe_eth_pdata_mac = {
+		.iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+		.phy_interface = 0,
+	},
+
+	.pfe_ddr_addr = {
+		.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+		.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+	},
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+	.pfe_eth_pdata_mac = {
+		.iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+		.phy_interface = 1,
+	},
+
+	.pfe_ddr_addr = {
+		.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+		.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+	},
+};
+
+U_BOOT_DRVINFO(ls1012a_pfe0) = {
+	.name = "pfe_eth",
+	.plat = &pfe_pdata0,
+};
+
+U_BOOT_DRVINFO(ls1012a_pfe1) = {
+	.name = "pfe_eth",
+	.plat = &pfe_pdata1,
+};
diff --git a/roms/u-boot/board/freescale/ls1012afrdm/ls1012afrdm.c b/roms/u-boot/board/freescale/ls1012afrdm/ls1012afrdm.c
new file mode 100644
index 000000000..6473ee057
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <asm/cache.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
+#include <asm/arch/mmu.h>
+#include <asm/arch/soc.h>
+#include <fsl_esdhc.h>
+#include <hwconfig.h>
+#include <env_internal.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+#include <fsl_sec.h>
+#include <net/pfe_eth/pfe/pfe_hw.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline int get_board_version(void)
+{
+	uint32_t val;
+#ifdef CONFIG_TARGET_LS1012AFRDM
+	val = 0;
+#else
+	struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
+
+	val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
+
+#endif
+	return val;
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_TARGET_LS1012AFRDM
+	puts("Board: LS1012AFRDM ");
+#else
+	int rev;
+
+	rev = get_board_version();
+
+	puts("Board: FRWY-LS1012A ");
+
+	puts("Version");
+
+	switch (rev) {
+	case BOARD_REV_A_B:
+		puts(": RevA/B ");
+		break;
+	case BOARD_REV_C:
+		puts(": RevC ");
+		break;
+	default:
+		puts(": unknown");
+		break;
+	}
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_TARGET_LS1012AFRWY
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+	char esdhc0_path[] = "/soc/esdhc@1560000";
+	char esdhc1_path[] = "/soc/esdhc@1580000";
+
+	do_fixup_by_path(blob, esdhc0_path, "status", "okay",
+			 sizeof("okay"), 1);
+
+	do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+			 sizeof("disabled"), 1);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_TFABOOT
+int dram_init(void)
+{
+#ifdef CONFIG_TARGET_LS1012AFRWY
+	int board_rev;
+#endif
+
+	gd->ram_size = tfa_get_dram_size();
+
+	if (!gd->ram_size) {
+#ifdef CONFIG_TARGET_LS1012AFRWY
+		board_rev = get_board_version();
+
+		if (board_rev & BOARD_REV_C)
+			gd->ram_size = SYS_SDRAM_SIZE_1024;
+		else
+			gd->ram_size = SYS_SDRAM_SIZE_512;
+#else
+		gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#endif
+	}
+	return 0;
+}
+#else
+int dram_init(void)
+{
+#ifdef CONFIG_TARGET_LS1012AFRWY
+	int board_rev;
+#endif
+	struct fsl_mmdc_info mparam = {
+		0x04180000,	/* mdctl */
+		0x00030035,	/* mdpdc */
+		0x12554000,	/* mdotc */
+		0xbabf7954,	/* mdcfg0 */
+		0xdb328f64,	/* mdcfg1 */
+		0x01ff00db,	/* mdcfg2 */
+		0x00001680,	/* mdmisc */
+		0x0f3c8000,	/* mdref */
+		0x00002000,	/* mdrwd */
+		0x00bf1023,	/* mdor */
+		0x0000003f,	/* mdasp */
+		0x0000022a,	/* mpodtctrl */
+		0xa1390003,	/* mpzqhwctrl */
+	};
+
+#ifdef CONFIG_TARGET_LS1012AFRWY
+	board_rev = get_board_version();
+
+	if (board_rev == BOARD_REV_C) {
+		mparam.mdctl = 0x05180000;
+		gd->ram_size = SYS_SDRAM_SIZE_1024;
+	} else {
+		gd->ram_size = SYS_SDRAM_SIZE_512;
+	}
+#else
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#endif
+	mmdc_init(&mparam);
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+	/* This will break-before-make MMU for DDR */
+	update_early_mmu_table();
+#endif
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+					CONFIG_SYS_CCI400_OFFSET);
+
+	/*
+	 * Set CCI-400 control override register to enable barrier
+	 * transaction
+	 */
+	if (current_el() == 3)
+		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_FSL_PFE
+void board_quiesce_devices(void)
+{
+	pfe_command_stop(0, NULL);
+}
+#endif
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/ls1012aqds/Kconfig b/roms/u-boot/board/freescale/ls1012aqds/Kconfig
new file mode 100644
index 000000000..59b1a8766
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012aqds/Kconfig
@@ -0,0 +1,83 @@
+if TARGET_LS1012AQDS
+
+config SYS_BOARD
+	default "ls1012aqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012aqds"
+
+config SYS_LS_PPA_FW_ADDR
+        hex "PPA Firmware Addr"
+        default 0x40400000
+
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA Firmware HDR Addr"
+	default 0x40680000
+
+config SYS_LS_PFE_ESBC_ADDR
+	hex "PFE Firmware HDR Addr"
+	default 0x40700000
+
+config SYS_LS_PFE_ESBC_LENGTH
+	hex "length of PFE Firmware HDR"
+	default 0xc00
+endif
+
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select PHYLIB
+	imply PHY_VITESSE
+	imply PHY_REALTEK
+	imply PHY_AQUANTIA
+	imply PHYLIB_10G
+
+config PFE_RGMII_RESET_WA
+	def_bool y
+
+config SYS_LS_PFE_FW_ADDR
+	hex "Flash address of PFE firmware"
+	default 0x40a00000
+
+config SYS_LS_PFE_FW_LENGTH
+	hex "length of PFE firmware"
+	default 0x300000
+
+config DDR_PFE_PHYS_BASEADDR
+	hex "PFE DDR physical base address"
+	default 0x03800000
+
+config DDR_PFE_BASEADDR
+	hex "PFE DDR base address"
+	default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+	hex "PFE DDR base address"
+	default 0x1e
+
+config PFE_EMAC2_PHY_ADDR
+	hex "PFE DDR base address"
+	default 0x1
+
+config PFE_SGMII_2500_PHY1_ADDR
+	hex "PFE DDR base address"
+	default 0x1
+
+config PFE_SGMII_2500_PHY2_ADDR
+	hex "PFE DDR base address"
+	default 0x2
+
+endif
+
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/ls1012aqds/MAINTAINERS b/roms/u-boot/board/freescale/ls1012aqds/MAINTAINERS
new file mode 100644
index 000000000..c1bb8d515
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012aqds/MAINTAINERS
@@ -0,0 +1,9 @@
+LS1012AQDS BOARD
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M:	Pramod Kumar <pramod.kumar_1@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012aqds/
+F:	include/configs/ls1012aqds.h
+F:	configs/ls1012aqds_qspi_defconfig
+F:	configs/ls1012aqds_tfa_defconfig
+F:	configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/ls1012aqds/Makefile b/roms/u-boot/board/freescale/ls1012aqds/Makefile
new file mode 100644
index 000000000..5aba9caf9
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012aqds/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012aqds.o
+obj-$(CONFIG_FSL_PFE) += eth.o
diff --git a/roms/u-boot/board/freescale/ls1012aqds/README b/roms/u-boot/board/freescale/ls1012aqds/README
new file mode 100644
index 000000000..dee4b302c
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012aqds/README
@@ -0,0 +1,59 @@
+Overview
+--------
+QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AQDS board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
+SoC overview.
+
+LS1012AQDS board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ - QSPI Controller
+     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
+       emulator
+ - USB 3.0
+    - One USB 3.0 controller with integrated PHY
+    - One high-speed USB 3.0 port
+ - USB 2.0
+    - One USB 2.0 controller with ULPI interface
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - 5 SAI
+    - One SAI port with audio codec SGTL5000:
+	• Provides MIC bias
+	• Provides headphone and line output
+    - One SAI port terminated at 2x6 header
+    - Three SAI Tx/Rx ports terminated at 2x3 headers
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000
diff --git a/roms/u-boot/board/freescale/ls1012aqds/eth.c b/roms/u-boot/board/freescale/ls1012aqds/eth.c
new file mode 100644
index 000000000..8189f41be
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012aqds/eth.c
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include <linux/delay.h>
+#include "../common/qixis.h"
+#include <net/pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include "ls1012aqds_qixis.h"
+
+#define EMI_NONE	0xFF
+#define EMI1_RGMII	1
+#define EMI1_SLOT1	2
+#define EMI1_SLOT2	3
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+static const char * const mdio_names[] = {
+	"NULL",
+	"LS1012AQDS_MDIO_RGMII",
+	"LS1012AQDS_MDIO_SLOT1",
+	"LS1012AQDS_MDIO_SLOT2",
+	"NULL",
+};
+
+static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct ls1012aqds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+static void ls1012aqds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+
+	if (muxval < 7) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+				int regnum)
+{
+	struct ls1012aqds_mdio *priv = bus->priv;
+
+	ls1012aqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				 int regnum, u16 value)
+{
+	struct ls1012aqds_mdio *priv = bus->priv;
+
+	ls1012aqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls1012aqds_mdio_reset(struct mii_dev *bus)
+{
+	struct ls1012aqds_mdio *priv = bus->priv;
+
+	if (priv->realbus->reset)
+		return priv->realbus->reset(priv->realbus);
+	else
+		return -1;
+}
+
+static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct ls1012aqds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate ls1012aqds MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate ls1012aqds private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = ls1012aqds_mdio_read;
+	bus->write = ls1012aqds_mdio_write;
+	bus->reset = ls1012aqds_mdio_reset;
+	sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+	return mdio_register(bus);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+	static int init_done;
+	struct mii_dev *bus;
+	static const char *mdio_name;
+	struct pfe_mdio_info mac_mdio_info;
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u8 data8;
+	struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+	int srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	ls1012aqds_mux_mdio(EMI1_SLOT1);
+
+	if (!init_done) {
+		mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+		mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+		bus = pfe_mdio_init(&mac_mdio_info);
+		if (!bus) {
+			printf("Failed to register mdio\n");
+			return -1;
+		}
+		init_done = 1;
+	}
+
+	if (priv->gemac_port) {
+		mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+		mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+
+		bus = pfe_mdio_init(&mac_mdio_info);
+		if (!bus) {
+			printf("Failed to register mdio\n");
+			return -1;
+		}
+	}
+
+	switch (srds_s1) {
+	case 0x3508:
+		printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
+#ifdef CONFIG_PFE_RGMII_RESET_WA
+		/*
+		 * Work around for FPGA registers initialization
+		 * This is needed for RGMII to work.
+		 */
+		printf("Reset RGMII WA....\n");
+		data8 = QIXIS_READ(rst_frc[0]);
+		data8 |= 0x2;
+		QIXIS_WRITE(rst_frc[0], data8);
+		data8 = QIXIS_READ(rst_frc[0]);
+
+		data8 = QIXIS_READ(res8[6]);
+		data8 |= 0xff;
+		QIXIS_WRITE(res8[6], data8);
+		data8 = QIXIS_READ(res8[6]);
+#endif
+	if (priv->gemac_port) {
+		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
+		if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII)
+		    < 0) {
+			printf("Failed to register mdio for %s\n", mdio_name);
+		}
+
+		/* MAC2 */
+		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
+		bus = miiphy_get_dev_by_name(mdio_name);
+		pfe_set_mdio(priv->gemac_port, bus);
+		pfe_set_phy_address_mode(priv->gemac_port,
+					 CONFIG_PFE_EMAC2_PHY_ADDR,
+					 PHY_INTERFACE_MODE_RGMII);
+
+	} else {
+		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+		if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
+		< 0) {
+			printf("Failed to register mdio for %s\n", mdio_name);
+		}
+
+		/* MAC1 */
+		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+		bus = miiphy_get_dev_by_name(mdio_name);
+		pfe_set_mdio(priv->gemac_port, bus);
+		pfe_set_phy_address_mode(priv->gemac_port,
+					 CONFIG_PFE_EMAC1_PHY_ADDR,
+					 PHY_INTERFACE_MODE_SGMII);
+	}
+
+		break;
+
+	case 0x2205:
+		printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
+		/*
+		 * Work around for FPGA registers initialization
+		 * This is needed for RGMII to work.
+		 */
+		printf("Reset SLOT1 SLOT2....\n");
+		data8 = QIXIS_READ(rst_frc[2]);
+		data8 |= 0xc0;
+		QIXIS_WRITE(rst_frc[2], data8);
+		mdelay(100);
+		data8 = QIXIS_READ(rst_frc[2]);
+		data8 &= 0x3f;
+		QIXIS_WRITE(rst_frc[2], data8);
+
+	if (priv->gemac_port) {
+		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
+		if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2)
+		< 0) {
+			printf("Failed to register mdio for %s\n", mdio_name);
+		}
+		/* MAC2 */
+		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
+		bus = miiphy_get_dev_by_name(mdio_name);
+		pfe_set_mdio(1, bus);
+		pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
+					 PHY_INTERFACE_MODE_SGMII_2500);
+
+		data8 = QIXIS_READ(brdcfg[12]);
+		data8 |= 0x20;
+		QIXIS_WRITE(brdcfg[12], data8);
+
+	} else {
+		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+		if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
+		    < 0) {
+			printf("Failed to register mdio for %s\n", mdio_name);
+		}
+
+		/* MAC1 */
+		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+		bus = miiphy_get_dev_by_name(mdio_name);
+		pfe_set_mdio(0, bus);
+		pfe_set_phy_address_mode(0,
+					 CONFIG_PFE_SGMII_2500_PHY1_ADDR,
+					 PHY_INTERFACE_MODE_SGMII_2500);
+	}
+		break;
+
+	default:
+		printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1);
+		break;
+	}
+	return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+	.pfe_eth_pdata_mac = {
+		.iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+		.phy_interface = 0,
+	},
+
+	.pfe_ddr_addr = {
+		.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+		.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+	},
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+	.pfe_eth_pdata_mac = {
+		.iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+		.phy_interface = 1,
+	},
+
+	.pfe_ddr_addr = {
+		.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+		.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+	},
+};
+
+U_BOOT_DRVINFO(ls1012a_pfe0) = {
+	.name = "pfe_eth",
+	.plat = &pfe_pdata0,
+};
+
+U_BOOT_DRVINFO(ls1012a_pfe1) = {
+	.name = "pfe_eth",
+	.plat = &pfe_pdata1,
+};
diff --git a/roms/u-boot/board/freescale/ls1012aqds/ls1012aqds.c b/roms/u-boot/board/freescale/ls1012aqds/ls1012aqds.c
new file mode 100644
index 000000000..33a0910a1
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012aqds/ls1012aqds.c
@@ -0,0 +1,301 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/cache.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
+#include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <env_internal.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_esdhc.h>
+#include <fsl_mmdc.h>
+#include <spl.h>
+#include <netdev.h>
+#include <fsl_sec.h>
+#include "../common/qixis.h"
+#include "ls1012aqds_qixis.h"
+#include "ls1012aqds_pfe.h"
+#include <net/pfe_eth/pfe/pfe_hw.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+	sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+
+	if (sw & QIXIS_LBMAP_ALTBANK)
+		printf("flash: 2\n");
+	else
+		printf("flash: 1\n");
+
+	printf("FPGA: v%d (%s), build %d",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+	return 0;
+}
+
+#ifdef CONFIG_TFABOOT
+int dram_init(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+	if (!gd->ram_size)
+		gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+#else
+int dram_init(void)
+{
+	static const struct fsl_mmdc_info mparam = {
+		0x05180000,	/* mdctl */
+		0x00030035,	/* mdpdc */
+		0x12554000,	/* mdotc */
+		0xbabf7954,	/* mdcfg0 */
+		0xdb328f64,	/* mdcfg1 */
+		0x01ff00db,	/* mdcfg2 */
+		0x00001680,	/* mdmisc */
+		0x0f3c8000,	/* mdref */
+		0x00002000,	/* mdrwd */
+		0x00bf1023,	/* mdor */
+		0x0000003f,	/* mdasp */
+		0x0000022a,	/* mpodtctrl */
+		0xa1390003,	/* mpzqhwctrl */
+	};
+
+	mmdc_init(&mparam);
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+	/* This will break-before-make MMU for DDR */
+	update_early_mmu_table();
+#endif
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	u8 mux_sdhc_cd = 0x80;
+	int bus_num = 0;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
+#else
+	i2c_set_bus_num(bus_num);
+
+	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+#endif
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+				   CONFIG_SYS_CCI400_OFFSET);
+
+	/* Set CCI-400 control override register to enable barrier
+	 * transaction */
+	if (current_el() == 3)
+		out_le32(&cci->ctrl_ord,
+			 CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+	erratum_a010315();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_FSL_PFE
+void board_quiesce_devices(void)
+{
+	pfe_command_stop(0, NULL);
+}
+#endif
+
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+	char esdhc0_path[] = "/soc/esdhc@1560000";
+	char esdhc1_path[] = "/soc/esdhc@1580000";
+	u8 card_id;
+
+	do_fixup_by_path(blob, esdhc0_path, "status", "okay",
+			 sizeof("okay"), 1);
+
+	/*
+	 * The Presence Detect 2 register detects the installation
+	 * of cards in various PCI Express or SGMII slots.
+	 *
+	 * STAT_PRS2[7:5]: Specifies the type of card installed in the
+	 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
+	 */
+	card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
+
+	/* If no adapter is installed in SDHC2, disable SDHC2 */
+	if (card_id == 0x7)
+		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+				 sizeof("disabled"), 1);
+	else
+		do_fixup_by_path(blob, esdhc1_path, "status", "okay",
+				 sizeof("okay"), 1);
+	return 0;
+}
+
+static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
+			      char *enet_path, char *mdio_path)
+{
+	do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
+			 &prop_val.busid, PFE_PROP_LEN, 1);
+	do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
+			 &prop_val.phyid, PFE_PROP_LEN, 1);
+	do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
+			 &prop_val.mux_val, PFE_PROP_LEN, 1);
+	do_fixup_by_path(set_blob, enet_path, "phy-mode",
+			 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
+	do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
+			 &prop_val.phy_mask, PFE_PROP_LEN, 1);
+	return 0;
+}
+
+static void fdt_fsl_fixup_of_pfe(void *blob)
+{
+	int i = 0;
+	struct pfe_prop_val prop_val;
+	void *l_blob = blob;
+
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
+		FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	for (i = 0; i < NUM_ETH_NODE; i++) {
+		switch (srds_s1) {
+		case SERDES_1_G_PROTOCOL:
+			if (i == 0) {
+				prop_val.busid = cpu_to_fdt32(
+						ETH_1_1G_BUS_ID);
+				prop_val.phyid = cpu_to_fdt32(
+						ETH_1_1G_PHY_ID);
+				prop_val.mux_val = cpu_to_fdt32(
+						ETH_1_1G_MDIO_MUX);
+				prop_val.phy_mask = cpu_to_fdt32(
+						ETH_1G_MDIO_PHY_MASK);
+				prop_val.phy_mode = "sgmii";
+				pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
+						   ETH_1_MDIO);
+			} else {
+				prop_val.busid = cpu_to_fdt32(
+						ETH_2_1G_BUS_ID);
+				prop_val.phyid = cpu_to_fdt32(
+						ETH_2_1G_PHY_ID);
+				prop_val.mux_val = cpu_to_fdt32(
+						ETH_2_1G_MDIO_MUX);
+				prop_val.phy_mask = cpu_to_fdt32(
+						ETH_1G_MDIO_PHY_MASK);
+				prop_val.phy_mode = "rgmii";
+				pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
+						   ETH_2_MDIO);
+			}
+		break;
+		case SERDES_2_5_G_PROTOCOL:
+			if (i == 0) {
+				prop_val.busid = cpu_to_fdt32(
+						ETH_1_2_5G_BUS_ID);
+				prop_val.phyid = cpu_to_fdt32(
+						ETH_1_2_5G_PHY_ID);
+				prop_val.mux_val = cpu_to_fdt32(
+						ETH_1_2_5G_MDIO_MUX);
+				prop_val.phy_mask = cpu_to_fdt32(
+						ETH_2_5G_MDIO_PHY_MASK);
+				prop_val.phy_mode = "sgmii-2500";
+				pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
+						   ETH_1_MDIO);
+			} else {
+				prop_val.busid = cpu_to_fdt32(
+						ETH_2_2_5G_BUS_ID);
+				prop_val.phyid = cpu_to_fdt32(
+						ETH_2_2_5G_PHY_ID);
+				prop_val.mux_val = cpu_to_fdt32(
+						ETH_2_2_5G_MDIO_MUX);
+				prop_val.phy_mask = cpu_to_fdt32(
+						ETH_2_5G_MDIO_PHY_MASK);
+				prop_val.phy_mode = "sgmii-2500";
+				pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
+						   ETH_2_MDIO);
+			}
+		break;
+		default:
+			printf("serdes:[%d]\n", srds_s1);
+		}
+	}
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+	fdt_fsl_fixup_of_pfe(blob);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/roms/u-boot/board/freescale/ls1012aqds/ls1012aqds_pfe.h
new file mode 100644
index 000000000..05ccb71aa
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012aqds/ls1012aqds_pfe.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#define ETH_1_1G_BUS_ID		0x1
+#define ETH_1_1G_PHY_ID		0x1e
+#define ETH_1_1G_MDIO_MUX	0x2
+#define ETH_1G_MDIO_PHY_MASK	0xBFFFFFFD
+#define ETH_1_1G_PHY_MODE	"sgmii"
+#define ETH_2_1G_BUS_ID		0x1
+#define ETH_2_1G_PHY_ID		0x1
+#define ETH_2_1G_MDIO_MUX	0x1
+#define ETH_2_1G_PHY_MODE	"rgmii"
+
+#define ETH_1_2_5G_BUS_ID	0x0
+#define ETH_1_2_5G_PHY_ID	0x1
+#define ETH_1_2_5G_MDIO_MUX	0x2
+#define ETH_2_5G_MDIO_PHY_MASK	0xFFFFFFF9
+#define ETH_2_5G_PHY_MODE	"sgmii-2500"
+#define ETH_2_2_5G_BUS_ID	0x1
+#define ETH_2_2_5G_PHY_ID	0x2
+#define ETH_2_2_5G_MDIO_MUX	0x3
+
+#define SERDES_1_G_PROTOCOL	0x3508
+#define SERDES_2_5_G_PROTOCOL	0x2205
+
+#define PFE_PROP_LEN		4
+
+#define ETH_1_PATH		"/pfe@04000000/ethernet@0"
+#define ETH_1_MDIO		ETH_1_PATH "/mdio@0"
+
+#define ETH_2_PATH		"/pfe@04000000/ethernet@1"
+#define ETH_2_MDIO		ETH_2_PATH "/mdio@0"
+
+#define NUM_ETH_NODE		2
+
+struct pfe_prop_val {
+	int busid;
+	int phyid;
+	int mux_val;
+	int phy_mask;
+	char *phy_mode;
+};
diff --git a/roms/u-boot/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/roms/u-boot/board/freescale/ls1012aqds/ls1012aqds_qixis.h
new file mode 100644
index 000000000..19f522d9e
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012aqds/ls1012aqds_qixis.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		6
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls1012ardb/Kconfig b/roms/u-boot/board/freescale/ls1012ardb/Kconfig
new file mode 100644
index 000000000..c4acea3ae
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012ardb/Kconfig
@@ -0,0 +1,124 @@
+if TARGET_LS1012ARDB
+
+config SYS_BOARD
+	default "ls1012ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012ardb"
+
+config SYS_LS_PPA_FW_ADDR
+        hex "PPA Firmware Addr"
+        default 0x40400000
+
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA Firmware HDR Addr"
+	default 0x40680000
+
+config SYS_LS_PFE_ESBC_ADDR
+	hex "PFE Firmware HDR Addr"
+	default 0x40640000
+
+config SYS_LS_PFE_ESBC_LENGTH
+	hex "length of PFE Firmware HDR"
+	default 0xc00
+endif
+
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select PHYLIB
+	imply PHY_REALTEK
+
+config SYS_LS_PFE_FW_ADDR
+	hex "Flash address of PFE firmware"
+	default 0x40a00000
+
+config SYS_LS_PFE_FW_LENGTH
+	hex "length of PFE firmware"
+	default 0x300000
+
+config DDR_PFE_PHYS_BASEADDR
+	hex "PFE DDR physical base address"
+	default 0x03800000
+
+config DDR_PFE_BASEADDR
+	hex "PFE DDR base address"
+	default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+	hex "PFE DDR base address"
+	default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+	hex "PFE DDR base address"
+	default 0x1
+
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
+
+if TARGET_LS1012A2G5RDB
+
+config SYS_BOARD
+        default "ls1012ardb"
+
+config SYS_VENDOR
+        default "freescale"
+
+config SYS_SOC
+        default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+        default "ls1012a2g5rdb"
+
+config SYS_LS_PPA_FW_ADDR
+        hex "PPA Firmware Addr"
+        default 0x40400000
+
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select PHYLIB
+	imply PHYLIB_10G
+	imply PHY_AQUANTIA
+
+config SYS_LS_PFE_FW_ADDR
+	hex "Flash address of PFE firmware"
+	default 0x40a00000
+
+config SYS_LS_PFE_FW_LENGTH
+	hex "length of PFE firmware"
+	default 0x300000
+
+config DDR_PFE_PHYS_BASEADDR
+	hex "PFE DDR physical base address"
+	default 0x03800000
+
+config DDR_PFE_BASEADDR
+	hex "PFE DDR base address"
+	default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+	hex "PFE DDR base address"
+	default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+	hex "PFE DDR base address"
+	default 0x1
+
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/ls1012ardb/MAINTAINERS b/roms/u-boot/board/freescale/ls1012ardb/MAINTAINERS
new file mode 100644
index 000000000..b0c008b5f
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012ardb/MAINTAINERS
@@ -0,0 +1,18 @@
+LS1012ARDB BOARD
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M:	Pramod Kumar <pramod.kumar_1@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012ardb/
+F:	include/configs/ls1012ardb.h
+F:	configs/ls1012ardb_qspi_defconfig
+F:	configs/ls1012ardb_tfa_defconfig
+F:	configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+F:	configs/ls1012a2g5rdb_tfa_defconfig
+F:	configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+
+LS1012A2G5RDB BOARD
+M:	Pramod Kumar <pramod.kumar_1@nxp.com>
+S:      Maintained
+F:      board/freescale/ls1012ardb/
+F:      include/configs/ls1012a2g5rdb.h
+F:      configs/ls1012a2g5rdb_qspi_defconfig
diff --git a/roms/u-boot/board/freescale/ls1012ardb/Makefile b/roms/u-boot/board/freescale/ls1012ardb/Makefile
new file mode 100644
index 000000000..70c7b3327
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012ardb/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012ardb.o
+obj-$(CONFIG_FSL_PFE) += eth.o
diff --git a/roms/u-boot/board/freescale/ls1012ardb/README b/roms/u-boot/board/freescale/ls1012ardb/README
new file mode 100644
index 000000000..572fd8c7d
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012ardb/README
@@ -0,0 +1,97 @@
+Overview
+--------
+QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012ARDB board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+LS1012ARDB board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+    - QSPI NOR flash memory (2 virtual banks)
+    - the QSPI emulator.s
+ - USB 3.0
+    - one high-speed USB 2.0/3.0 port.
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: Three dual 1:4 mux/demux devices,
+    74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
+    SDIO WiFi, SPI, and Ardiuno shield
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+   - The LS1012A processor consists of two UART controllers,
+   out of which only UART1 is used on RDB.
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000
+
+LS1012A2G5RDB board Overview
+-----------------------
+ - SERDES Connections, 3 lanes supporting:
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+    - QSPI NOR flash memory
+ - USB 3.0
+    - one high-speed USB 2.0/3.0 port.
+ - SDIO WiFi, SPI
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+   - The LS1012A processor consists of two UART controllers,
+   out of which only UART1 is used on 2G5RDB.
+ - ARM JTAG support
+
+Major Difference between LS1012ARDB and LS1012A-2G5RDB
+------------------------------------------------------
+1. LS1012A-2G5RDB has Type C USB connector unlike USB Type A/B of LS1012ARDB
+2. LS1012A-2G5RDB has 2 2.5G AQR PHY unlike 2 1G Realtek RTL8211FS PHYs
+   of LS1012ARDB
+3. LS1012A-2G5RDB is not having Arduino header
+4. LS1012A-2G5RDB doesn't have PCI slot
+
+Booting Options
+---------------
+QSPI Flash
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4030_0000
+PPA FIT image	| 2MB	| 0x4040_0000
+PFE firmware	| 20K	| 0x00a0_0000
+Linux ITB	| ~53MB | 0x4100_0000
diff --git a/roms/u-boot/board/freescale/ls1012ardb/eth.c b/roms/u-boot/board/freescale/ls1012ardb/eth.c
new file mode 100644
index 000000000..bb3fbc71e
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012ardb/eth.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include <linux/delay.h>
+#include <net/pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include <i2c.h>
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+
+static inline void ls1012ardb_reset_phy(void)
+{
+#ifdef CONFIG_TARGET_LS1012ARDB
+	/* Through reset IO expander reset both RGMII and SGMII PHYs */
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+	int ret;
+
+	/*
+	 * The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number is 0).
+	 */
+	ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       0);
+		return;
+	}
+	/* Config port 0
+	 * - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B
+	 *   are enabled as an output.
+	 */
+	dm_i2c_reg_write(dev, 6, __PHY_MASK);
+
+	/*
+	 * Set port 0 output a value to reset ETH2 interface
+	 * - pin IOXP_RST_ETH2_B output 0b0
+	 */
+	dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK);
+	mdelay(10);
+	dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK);
+	/*
+	 * Set port 0 output a value to reset ETH1 interface
+	 * - pin IOXP_RST_ETH1_B output 0b0
+	 */
+	mdelay(10);
+	dm_i2c_reg_write(dev, 2, 0xFF);
+#else
+	i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
+	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
+	mdelay(10);
+	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
+	mdelay(10);
+	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
+#endif
+	mdelay(50);
+#endif
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+	static int init_done;
+	struct mii_dev *bus;
+	struct pfe_mdio_info mac_mdio_info;
+	struct pfe_eth_dev *priv = dev_get_priv(dev);
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+	int srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	if (!init_done) {
+		ls1012ardb_reset_phy();
+		mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+		mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+		bus = pfe_mdio_init(&mac_mdio_info);
+		if (!bus) {
+			printf("Failed to register mdio\n");
+			return -1;
+		}
+		init_done = 1;
+	}
+
+	pfe_set_mdio(priv->gemac_port,
+		     miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+
+	switch (srds_s1) {
+	case 0x3508:
+		if (!priv->gemac_port) {
+			/* MAC1 */
+			pfe_set_phy_address_mode(priv->gemac_port,
+						 CONFIG_PFE_EMAC1_PHY_ADDR,
+						 PHY_INTERFACE_MODE_SGMII);
+		} else {
+			/* MAC2 */
+			pfe_set_phy_address_mode(priv->gemac_port,
+						 CONFIG_PFE_EMAC2_PHY_ADDR,
+						 PHY_INTERFACE_MODE_RGMII_ID);
+		}
+		break;
+	case 0x2208:
+		if (!priv->gemac_port) {
+			/* MAC1 */
+			pfe_set_phy_address_mode(priv->gemac_port,
+						 CONFIG_PFE_EMAC1_PHY_ADDR,
+						 PHY_INTERFACE_MODE_SGMII_2500);
+		} else {
+			/* MAC2 */
+			pfe_set_phy_address_mode(priv->gemac_port,
+						 CONFIG_PFE_EMAC2_PHY_ADDR,
+						 PHY_INTERFACE_MODE_SGMII_2500);
+		}
+		break;
+	default:
+		printf("unsupported SerDes PRCTL= %d\n", srds_s1);
+		break;
+	}
+	return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+	.pfe_eth_pdata_mac = {
+		.iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+		.phy_interface = 0,
+	},
+
+	.pfe_ddr_addr = {
+		.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+		.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+	},
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+	.pfe_eth_pdata_mac = {
+		.iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+		.phy_interface = 1,
+	},
+
+	.pfe_ddr_addr = {
+		.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+		.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+	},
+};
+
+U_BOOT_DRVINFO(ls1012a_pfe0) = {
+	.name = "pfe_eth",
+	.plat = &pfe_pdata0,
+};
+
+U_BOOT_DRVINFO(ls1012a_pfe1) = {
+	.name = "pfe_eth",
+	.plat = &pfe_pdata1,
+};
diff --git a/roms/u-boot/board/freescale/ls1012ardb/ls1012ardb.c b/roms/u-boot/board/freescale/ls1012ardb/ls1012ardb.c
new file mode 100644
index 000000000..62e8af48c
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1012ardb/ls1012ardb.c
@@ -0,0 +1,426 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fdt_support.h>
+#include <hang.h>
+#include <i2c.h>
+#include <asm/cache.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
+#include <asm/arch/mmu.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fsl_esdhc.h>
+#include <env_internal.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+#include <fsl_sec.h>
+#include <net/pfe_eth/pfe/pfe_hw.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BOOT_FROM_UPPER_BANK	0x2
+#define BOOT_FROM_LOWER_BANK	0x1
+
+int checkboard(void)
+{
+#ifdef CONFIG_TARGET_LS1012ARDB
+	u8 in1;
+	int ret, bus_num = 0;
+
+	puts("Board: LS1012ARDB ");
+
+	/* Initialize i2c early for Serial flash bank information */
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return -ENXIO;
+	}
+	ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1);
+#else /* Non DM I2C support - will be removed */
+	i2c_set_bus_num(bus_num);
+	ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1);
+#endif
+	if (ret < 0) {
+		printf("Error reading i2c boot information!\n");
+		return 0; /* Don't want to hang() on this error */
+	}
+
+	puts("Version");
+	switch (in1 & SW_REV_MASK) {
+	case SW_REV_A:
+		puts(": RevA");
+		break;
+	case SW_REV_B:
+		puts(": RevB");
+		break;
+	case SW_REV_C:
+		puts(": RevC");
+		break;
+	case SW_REV_C1:
+		puts(": RevC1");
+		break;
+	case SW_REV_C2:
+		puts(": RevC2");
+		break;
+	case SW_REV_D:
+		puts(": RevD");
+		break;
+	case SW_REV_E:
+		puts(": RevE");
+		break;
+	default:
+		puts(": unknown");
+		break;
+	}
+
+	printf(", boot from QSPI");
+	if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
+		puts(": emu\n");
+	else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
+		puts(": bank1\n");
+	else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
+		puts(": bank2\n");
+	else
+		puts("unknown\n");
+#else
+
+	puts("Board: LS1012A2G5RDB ");
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_TFABOOT
+int dram_init(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+	if (!gd->ram_size)
+		gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+#else
+int dram_init(void)
+{
+#ifndef CONFIG_TFABOOT
+	static const struct fsl_mmdc_info mparam = {
+		0x05180000,	/* mdctl */
+		0x00030035,	/* mdpdc */
+		0x12554000,	/* mdotc */
+		0xbabf7954,	/* mdcfg0 */
+		0xdb328f64,	/* mdcfg1 */
+		0x01ff00db,	/* mdcfg2 */
+		0x00001680,	/* mdmisc */
+		0x0f3c8000,	/* mdref */
+		0x00002000,	/* mdrwd */
+		0x00bf1023,	/* mdor */
+		0x0000003f,	/* mdasp */
+		0x0000022a,	/* mpodtctrl */
+		0xa1390003,	/* mpzqhwctrl */
+	};
+
+	mmdc_init(&mparam);
+#endif
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+	/* This will break-before-make MMU for DDR */
+	update_early_mmu_table();
+#endif
+
+	return 0;
+}
+#endif
+
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+					CONFIG_SYS_CCI400_OFFSET);
+	/*
+	 * Set CCI-400 control override register to enable barrier
+	 * transaction
+	 */
+	if (current_el() == 3)
+		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+	erratum_a010315();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_FSL_PFE
+void board_quiesce_devices(void)
+{
+	pfe_command_stop(0, NULL);
+}
+#endif
+
+#ifdef CONFIG_TARGET_LS1012ARDB
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+	char esdhc1_path[] = "/soc/esdhc@1580000";
+	bool sdhc2_en = false;
+	u8 mux_sdhc2;
+	u8 io = 0;
+	int ret, bus_num = 0;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return -ENXIO;
+	}
+	ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1);
+#else
+	i2c_set_bus_num(bus_num);
+	/* IO1[7:3] is the field of board revision info. */
+	ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1);
+#endif
+	if (ret < 0) {
+		printf("Error reading i2c boot information!\n");
+		return 0;
+	}
+
+	/* hwconfig method is used for RevD and later versions. */
+	if ((io & SW_REV_MASK) <= SW_REV_D) {
+#ifdef CONFIG_HWCONFIG
+		if (hwconfig("esdhc1"))
+			sdhc2_en = true;
+#endif
+	} else {
+		/*
+		 * The I2C IO-expander for mux select is used to control
+		 * the muxing of various onboard interfaces.
+		 *
+		 * IO0[3:2] indicates SDHC2 interface demultiplexer
+		 * select lines.
+		 *	00 - SDIO wifi
+		 *	01 - GPIO (to Arduino)
+		 *	10 - eMMC Memory
+		 *	11 - SPI
+		 */
+#if CONFIG_IS_ENABLED(DM_I2C)
+		ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
+#else
+		ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
+#endif
+		if (ret < 0) {
+			printf("Error reading i2c boot information!\n");
+			return 0;
+		}
+
+		mux_sdhc2 = (io & 0x0c) >> 2;
+		/* Enable SDHC2 only when use SDIO wifi and eMMC */
+		if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
+			sdhc2_en = true;
+	}
+	if (sdhc2_en)
+		do_fixup_by_path(blob, esdhc1_path, "status", "okay",
+				 sizeof("okay"), 1);
+	else
+		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+				 sizeof("disabled"), 1);
+	return 0;
+}
+#endif
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+
+static int switch_to_bank1(void)
+{
+	u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
+	int ret, bus_num = 0;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return -ENXIO;
+	}
+	/*
+	 * --------------------------------------------------------------------
+	 * |bus |I2C address|       Device     |          Notes               |
+	 * --------------------------------------------------------------------
+	 * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General   |
+	 * |    |0x26	    | RESET, and INT/  | Purpose parallel Input/Output|
+	 * |    |           | KW41GPIO) - NXP  | (GPIO) expansion for the     |
+	 * |    |           | PCAL9555AHF      | I2C bus                      |
+	 * ----- --------------------------------------------------------------
+	 * - mount three IO expander(PCAL9555AHF) on I2C1
+	 *
+	 * PCAL9555A device address
+	 *           slave address
+	 *  --------------------------------------
+	 *  | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W |
+	 *  --------------------------------------
+	 *  |     fixed     | hardware selectable|
+	 *
+	 * Output port 1(Pinter register bits = 0x03)
+	 *
+	 * P1_[7~0] = 0xf4
+	 * P1_0 <---> CFG_MUX_QSPI_S0
+	 * P1_1 <---> CFG_MUX_QSPI_S1
+	 * CFG_MUX_QSPI_S[1:0] = 0b00
+	 *
+	 * QSPI chip-select demultiplexer select
+	 * ---------------------------------------------------------------------
+	 * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0|              Values
+	 * ---------------------------------------------------------------------
+	 *    0           | 0            |CS routed to SPI memory bank1(default)
+	 * ---------------------------------------------------------------------
+	 *    0           | 1             |CS routed to SPI memory bank2
+	 * ---------------------------------------------------------------------
+	 *
+	 */
+	ret = dm_i2c_write(dev, offset_addr, &data, 1);
+#else /* Non DM I2C support - will be removed */
+	i2c_set_bus_num(bus_num);
+	ret = i2c_write(chip_addr, offset_addr, 1, &data, 1);
+#endif
+
+	if (ret) {
+		printf("i2c write error to chip : %u, addr : %u, data : %u\n",
+		       chip_addr, offset_addr, data);
+	}
+
+	return ret;
+}
+
+static int switch_to_bank2(void)
+{
+	u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3};
+	u8 chip_addr = 0x24;
+	int ret, i, bus_num = 0;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return -ENXIO;
+	}
+#else /* Non DM I2C support - will be removed */
+	i2c_set_bus_num(bus_num);
+#endif
+
+	/*
+	 * 1th step: config port 1
+	 *	- the port 1 pin is enabled as an output
+	 * 2th step: output port 1
+	 *	- P1_[7:0] output 0xf5,
+	 *	  then CFG_MUX_QSPI_S[1:0] equal to 0b01,
+	 *	  CS routed to SPI memory bank2
+	 */
+	for (i = 0; i < sizeof(data); i++) {
+#if CONFIG_IS_ENABLED(DM_I2C)
+		ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
+#else /* Non DM I2C support - will be removed */
+		ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
+#endif
+		if (ret) {
+			printf("i2c write error to chip : %u, addr : %u, data : %u\n",
+			       chip_addr, offset_addr[i], data[i]);
+			goto err;
+		}
+	}
+
+err:
+	return ret;
+}
+
+static int convert_flash_bank(int bank)
+{
+	int ret = 0;
+
+	switch (bank) {
+	case BOOT_FROM_UPPER_BANK:
+		ret = switch_to_bank2();
+		break;
+	case BOOT_FROM_LOWER_BANK:
+		ret = switch_to_bank1();
+		break;
+	default:
+		ret = CMD_RET_USAGE;
+		break;
+	};
+
+	return ret;
+}
+
+static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;
+	if (strcmp(argv[1], "1") == 0)
+		convert_flash_bank(BOOT_FROM_LOWER_BANK);
+	else if (strcmp(argv[1], "2") == 0)
+		convert_flash_bank(BOOT_FROM_UPPER_BANK);
+	else
+		return CMD_RET_USAGE;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	boot_bank, 2, 0, flash_bank_cmd,
+	"Flash bank Selection Control",
+	"bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
+);
diff --git a/roms/u-boot/board/freescale/ls1021aiot/Kconfig b/roms/u-boot/board/freescale/ls1021aiot/Kconfig
new file mode 100644
index 000000000..c6b16063a
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aiot/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_LS1021AIOT
+
+config SYS_BOARD
+	default "ls1021aiot"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "ls102xa"
+
+config SYS_CONFIG_NAME
+	default "ls1021aiot"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/ls1021aiot/MAINTAINERS b/roms/u-boot/board/freescale/ls1021aiot/MAINTAINERS
new file mode 100644
index 000000000..65f21bee3
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aiot/MAINTAINERS
@@ -0,0 +1,7 @@
+LS1021AIOT BOARD
+M:	Alison Wang <alison.wang@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1021aiot/
+F:	include/configs/ls1021aiot.h
+F:	configs/ls1021aiot_sdcard_defconfig
+F:	configs/ls1021aiot_qspi_defconfig
diff --git a/roms/u-boot/board/freescale/ls1021aiot/Makefile b/roms/u-boot/board/freescale/ls1021aiot/Makefile
new file mode 100644
index 000000000..bec151fd2
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aiot/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+
+obj-y += ls1021aiot.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/roms/u-boot/board/freescale/ls1021aiot/README b/roms/u-boot/board/freescale/ls1021aiot/README
new file mode 100644
index 000000000..08b0268b9
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aiot/README
@@ -0,0 +1,58 @@
+Overview
+--------
+The LS1021A-IOT is a Freescale reference board that hosts
+the LS1021A SoC.
+
+LS1021AIOT board Overview
+-------------------------
+ - DDR Controller
+	- Supports 1GB un-buffered DDR3L SDRAM discrete
+	devices(32-bit bus) with 4 bit ECC
+	- DDR power supplies 1.35V to all devices with
+	automatic tracking of VTT
+	- Soldered DDR chip
+	- Supprot one fixed speed
+ - Ethernet
+	- Two on-board SGMII 10/100/1G ethernet ports
+	- One Gbit Etherent RGMII interface to 4-ports switch
+	with 4x 10/100/1000 RJ145 ports
+ - CPLD
+	- 8-bit registers in CPLD for system configuration
+	- connected to IFC_AD[0:7]
+ - Power Supplies
+	- 12V@5A DC
+ - SDHC
+	- SDHC port connects directly to a full 8-bit SD/MMC slot
+	- Support for SDIO devices
+ - USB
+	- Two on-board USB 3.0
+	- One on-board USB k22
+ - PCIe
+	- Two MiniPCIe Solts
+ - SATA
+	- Support SATA Connector
+ - AUDIO
+	- AUDIO in and out
+ - I/O Expansion
+	- Arduino Shield Connector
+	- Port0 - CAN/GPIO/Flextimer
+	- Port1 - GPIO/CPLD Expansion
+	- Port2 - SPI/I2C/UART
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address	End Address		Description			Size
+0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR				240MB
+0x00_4000_0000	0x00_43FF_FFFF	QSPI(Chip select 0)	64MB
+0x00_4400_0000	0x00_47FF_FFFF	QSPI(Chip select 1)	64MB
+0x00_6000_0000	0x00_6000_FFFF	CPLD				64K
+0x00_8000_0000	0x00_BFFF_FFFF	DDR					1GB
+
+Boot description
+-----------------
+LS1021A-IOT support two ways of boot:
+Qspi boot and SD boot
+The board doesn't support boot from another
+source without changing any switch/jumper.
diff --git a/roms/u-boot/board/freescale/ls1021aiot/dcu.c b/roms/u-boot/board/freescale/ls1021aiot/dcu.c
new file mode 100644
index 000000000..e4fbcbcaa
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aiot/dcu.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ */
+
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include <asm/global_data.h>
+#include "div64.h"
+#include "../common/dcu_sii9022a.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+	unsigned long long div;
+
+	div = (unsigned long long)(gd->bus_clk / 1000);
+	div *= (unsigned long long)pixclock;
+	do_div(div, 1000000000);
+
+	return div;
+}
+
+int platform_dcu_init(struct fb_info *fbinfo,
+		      unsigned int xres, unsigned int yres,
+		      const char *port,
+		      struct fb_videomode *dcu_fb_videomode)
+{
+	const char *name;
+	unsigned int pixel_format;
+
+	if (strncmp(port, "twr_lcd", 4) == 0) {
+		name = "TWR_LCD_RGB card";
+	} else {
+		name = "HDMI";
+		dcu_set_dvi_encoder(dcu_fb_videomode);
+	}
+
+	printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+	pixel_format = 32;
+	fsl_dcu_init(fbinfo, xres, yres, pixel_format);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/ls1021aiot/ls1021aiot.c b/roms/u-boot/board/freescale/ls1021aiot/ls1021aiot.c
new file mode 100644
index 000000000..bfe613760
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aiot/ls1021aiot.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <fsl_csu.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <spl.h>
+
+#include <fsl_validate.h>
+#include "../common/sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_SIZE		0x40000000
+
+
+int checkboard(void)
+{
+	puts("Board: LS1021AIOT\n");
+
+#ifndef CONFIG_QSPI_BOOT
+	struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 cpldrev;
+
+	cpldrev = in_be32(&dcfg->gpporcr1);
+
+	printf("CPLD:  V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
+		0xf));
+#endif
+	return 0;
+}
+
+void ddrmc_init(void)
+{
+	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+	u32 temp_sdram_cfg, tmp;
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
+
+	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
+	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
+	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
+	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
+	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
+	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
+
+	out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+	out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
+
+	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
+	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
+
+	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
+
+	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
+
+	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
+	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
+
+	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
+
+	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
+	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
+
+	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+
+	/* DDR erratum A-009942 */
+	tmp = in_be32(&ddr->debug[28]);
+	out_be32(&ddr->debug[28], tmp | 0x0070006f);
+
+	udelay(500);
+
+	temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
+}
+
+int dram_init(void)
+{
+#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+	ddrmc_init();
+#endif
+
+	erratum_a008850_post();
+
+	gd->ram_size = DDR_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(struct bd_info *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	if (is_serdes_configured(SGMII_TSEC1)) {
+		puts("eTSEC1 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (is_serdes_configured(SGMII_TSEC2)) {
+		puts("eTSEC2 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_TSEC_ENET
+	/* clear BD & FR bits for BE BD's and frame data */
+	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+
+#endif
+
+	arch_soc_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	get_clocks();
+
+	preloader_console_init();
+
+	dram_init();
+
+	/* Allow OCRAM access permission as R/W */
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	board_init_r(NULL, 0);
+}
+#endif
+
+int board_init(void)
+{
+#ifndef CONFIG_SYS_FSL_NO_SERDES
+	fsl_serdes_init();
+#endif
+
+	ls102xa_smmu_stream_id_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_DEVICE_DISABLE
+	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	return sec_init();
+#endif
+}
+#endif
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
+
+void flash_write16(u16 val, void *addr)
+{
+	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+	__raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 val = __raw_readw(addr);
+
+	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
diff --git a/roms/u-boot/board/freescale/ls1021aiot/ls102xa_pbi.cfg b/roms/u-boot/board/freescale/ls1021aiot/ls102xa_pbi.cfg
new file mode 100644
index 000000000..b5ac5e27e
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aiot/ls102xa_pbi.cfg
@@ -0,0 +1,14 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
+
+09ea085c 00502880
diff --git a/roms/u-boot/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg b/roms/u-boot/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
new file mode 100644
index 000000000..a1984c713
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
@@ -0,0 +1,27 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+
+#Default with 2 x SGMII (no SATA)
+0608000a 00000000 00000000 00000000
+20000000 08407900 60025a00 21046000
+00000000 00000000 00000000 20038000
+20024800 881b1340 00000000 00000000
+
+#SATA set-up
+#0608000a 00000000 00000000 00000000
+#70000000 08007900 60025a00 21046000
+#00000000 00000000 00000000 20038000
+#20024800 881b1340 00000000 00000000
+
+#HDMI set-up
+#0608000a 00000000 00000000 00000000
+#20000000 08407900 60025a00 21046000
+#00000000 00000000 00000000 20038000
+#00000000 881b1340 00000000 00000000
+
+#QE testing
+#0608000a 00000000 00000000 00000000
+#20000000 08407900 60025a00 21046000
+#00000000 00000000 00000000 00038000
+#20094800 881b1340 00000000 00000000
diff --git a/roms/u-boot/board/freescale/ls1021aiot/psci.S b/roms/u-boot/board/freescale/ls1021aiot/psci.S
new file mode 100644
index 000000000..d0106ba39
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aiot/psci.S
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 NXP Semiconductor.
+ * Author: Feng Li <feng.li_2@nxp.com>
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+	.align	5
+
+.globl	psci_system_off
+psci_system_off:
+1:	wfi
+	b	1b
+
+.globl	psci_text_end
+psci_text_end:
+	nop
+	.popsection
diff --git a/roms/u-boot/board/freescale/ls1021aqds/Kconfig b/roms/u-boot/board/freescale/ls1021aqds/Kconfig
new file mode 100644
index 000000000..60b847299
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_LS1021AQDS
+
+config SYS_BOARD
+	default "ls1021aqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "ls102xa"
+
+config SYS_CONFIG_NAME
+	default "ls1021aqds"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/ls1021aqds/MAINTAINERS b/roms/u-boot/board/freescale/ls1021aqds/MAINTAINERS
new file mode 100644
index 000000000..913d251ee
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/MAINTAINERS
@@ -0,0 +1,14 @@
+LS1021AQDS BOARD
+M:	Alison Wang <alison.wang@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1021aqds/
+F:	include/configs/ls1021aqds.h
+F:	configs/ls1021aqds_nor_defconfig
+F:	configs/ls1021aqds_ddr4_nor_defconfig
+F:	configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+F:	configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+F:	configs/ls1021aqds_nor_lpuart_defconfig
+F:	configs/ls1021aqds_sdcard_ifc_defconfig
+F:	configs/ls1021aqds_sdcard_qspi_defconfig
+F:	configs/ls1021aqds_qspi_defconfig
+F:	configs/ls1021aqds_nand_defconfig
diff --git a/roms/u-boot/board/freescale/ls1021aqds/Makefile b/roms/u-boot/board/freescale/ls1021aqds/Makefile
new file mode 100644
index 000000000..1e50e468a
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1021aqds.o
+obj-y += ddr.o
+obj-y += eth.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/roms/u-boot/board/freescale/ls1021aqds/README b/roms/u-boot/board/freescale/ls1021aqds/README
new file mode 100644
index 000000000..6cf7146fb
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/README
@@ -0,0 +1,118 @@
+Overview
+--------
+The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC.
+
+LS1021A SoC Overview
+------------------
+The QorIQ LS1 family, which includes the LS1021A communications processor,
+is built on Layerscape architecture, the industry's first software-aware,
+core-agnostic networking architecture to offer unprecedented efficiency
+and scale.
+
+A member of the value-performance tier, the QorIQ LS1021A processor provides
+extensive integration and power efficiency for fanless, small form factor
+enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
+running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
+performance of over 6,000, as well as virtualization support, advanced
+security features and the broadest array of high-speed interconnects and
+optimized peripheral features ever offered in a sub-3 W processor.
+
+The QorIQ LS1021A processor features an integrated LCD controller,
+CAN controller for implementing industrial protocols, DDR3L/4 running
+up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
+protection on both L1 and L2 caches. The LS1021A processor is pin- and
+software-compatible with the QorIQ LS1020A and LS1022A processors.
+
+The LS1021A SoC includes the following function and features:
+
+ - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
+ - Dual high-preformance ARM Cortex-A7 cores, each core includes:
+   - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
+   - 512 Kbyte shared coherent L2 Cache (with ECC protection)
+   - NEON Co-processor (per core)
+   - 40-bit physical addressing
+   - Vector floating-point support
+ - ARM Core-Link CCI-400 Cache Coherent Interconnect
+ - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
+   supporting speeds up to 1600Mtps
+   - ECC and interleaving support
+ - VeTSEC Ethernet complex
+   - Up to 3x virtualized 10/100/1000 Ethernet controllers
+   - MII, RMII, RGMII, and SGMII support
+   - QoS, lossless flow control, and IEEE 1588 support
+ - 4-lane 6GHz SerDes
+ - High speed interconnect (4 SerDes lanes with are muxed for these protocol)
+   - Two PCI Express Gen2 controllers running at up to 5 GHz
+   - One Serial ATA 3.0 supporting 6 GT/s operation
+   - Two SGMII interfaces supporting 1000 Mbps
+ - Additional peripheral interfaces
+   - One high-speed USB 3.0 controller with integrated PHY and one high-speed
+     USB 2.00 controller with ULPI
+   - Integrated flash controller (IFC) with 16-bit interface
+   - Quad SPI NOR Flash
+   - One enhanced Secure digital host controller
+   - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface)
+   - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power
+     UARTs
+   - Three I2C controllers
+   - Eight FlexTimers four supporting PWM and four FlexCAN ports
+   - Four GPIO controllers supporting up to 109 general purpose I/O signals
+ - Integrated advanced audio block:
+   - Four synchronous audio interfaces (SAI)
+   - Sony/Philips Digital Interconnect Format (SPDIF)
+   - Asynchronous Sample Rate Converter (ASRC)
+ - Hardware based crypto offload engine
+   - IPSec forwarding at up to 1Gbps
+   - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported
+   - Public key hardware accelerator
+   - True Random Number Generator (NIST Certified)
+   - Advanced Encryption Standard Accelerators (AESA)
+   - Data Encryption Standard Accelerators
+ - QUICC Engine ULite block
+   - Two universal communication controllers (TDM and HDLC) supporting 64
+   multichannels, each running at 64 Kbps
+   - Support for 256 channels of HDLC
+ - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported
+
+LS1021AQDS board Overview
+-------------------------
+ - DDR Controller
+     - Supports rates of up to 1600 MHz data-rate
+     - Supports one DDR3LP UDIMM, of single-, dual- types.
+ - IFC/Local Bus
+     - NAND flash: 512M 8-bit NAND flash
+     - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+     - Three on-board RGMII 10/100/1G ethernet ports.
+ - FPGA
+ - Clocks
+     - System and DDR clock (SYSCLK, DDRCLK)
+     - SERDES clocks
+ - Power Supplies
+ - SDHC
+     - SDHC/SDXC connector
+ - Other IO
+    - Two Serial ports
+    - Three I2C ports
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address	End Address	Description			Size
+0x00_0000_0000	0x00_000F_FFFF	Secure Boot ROM			1MB
+0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR				240MB
+0x00_1000_0000	0x00_1000_FFFF	OCRAM0				64KB
+0x00_1001_0000	0x00_1001_FFFF	OCRAM1				64KB
+0x00_2000_0000	0x00_20FF_FFFF	DCSR				16MB
+0x00_4000_0000	0x00_5FFF_FFFF	QSPI				512MB
+0x00_6000_0000	0x00_67FF_FFFF	IFC - NOR Flash			128MB
+0x00_7E80_0000	0x00_7E80_FFFF	IFC - NAND Flash		64KB
+0x00_7FB0_0000	0x00_7FB0_0FFF	IFC - FPGA			4KB
+0x00_8000_0000	0x00_FFFF_FFFF	DRAM1				2GB
+
+LS1021a rev1.0 Soc specific Options/Settings
+--------------------------------------------
+If the LS1021a Soc is rev1.0, you need modify the configure file.
+Add the following define in include/configs/ls1021aqds.h:
+#define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/roms/u-boot/board/freescale/ls1021aqds/dcu.c b/roms/u-boot/board/freescale/ls1021aqds/dcu.c
new file mode 100644
index 000000000..7532f7c0b
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/dcu.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
+ *
+ * FSL DCU Framebuffer driver
+ */
+
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include <i2c.h>
+#include "div64.h"
+#include "../common/diu_ch7301.h"
+#include "ls1021aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int select_i2c_ch_pca9547(u8 ch, int bus_num)
+{
+	int ret;
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+	unsigned long long div;
+
+	div = (unsigned long long)(gd->bus_clk / 1000);
+	div *= (unsigned long long)pixclock;
+	do_div(div, 1000000000);
+
+	return div;
+}
+
+int platform_dcu_init(struct fb_info *fbinfo,
+		      unsigned int xres,
+		      unsigned int yres,
+		      const char *port,
+		      struct fb_videomode *dcu_fb_videomode)
+{
+	const char *name;
+	unsigned int pixel_format;
+	int ret;
+	u8 ch;
+
+	/* Mux I2C3+I2C4 as HSYNC+VSYNC */
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	/* QIXIS device mount on I2C1 bus*/
+	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       0);
+		return ret;
+	}
+	ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
+	if (ret) {
+		printf("Error: failed to read I2C @%02x\n",
+		       CONFIG_SYS_I2C_QIXIS_ADDR);
+		return ret;
+	}
+	ch &= 0x1F;
+	ch |= 0xA0;
+	ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
+
+#else
+	ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
+		       1, &ch, 1);
+	if (ret) {
+		printf("Error: failed to read I2C @%02x\n",
+		       CONFIG_SYS_I2C_QIXIS_ADDR);
+		return ret;
+	}
+	ch &= 0x1F;
+	ch |= 0xA0;
+	ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
+			1, &ch, 1);
+#endif
+	if (ret) {
+		printf("Error: failed to write I2C @%02x\n",
+		       CONFIG_SYS_I2C_QIXIS_ADDR);
+		return ret;
+	}
+
+	if (strncmp(port, "hdmi", 4) == 0) {
+		unsigned long pixval;
+
+		name = "HDMI";
+
+		pixval = 1000000000 / dcu_fb_videomode->pixclock;
+		pixval *= 1000;
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+		i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
+#endif
+		select_i2c_ch_pca9547(I2C_MUX_CH_CH7301,
+				      CONFIG_SYS_I2C_DVI_BUS_NUM);
+		diu_set_dvi_encoder(pixval);
+		select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT,
+				      CONFIG_SYS_I2C_DVI_BUS_NUM);
+	} else {
+		return 0;
+	}
+
+	printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+	pixel_format = 32;
+	fsl_dcu_init(fbinfo, xres, yres, pixel_format);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/ls1021aqds/ddr.c b/roms/u-boot/board/freescale/ls1021aqds/ddr.c
new file mode 100644
index 000000000..66fe1519c
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/ddr.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <linux/delay.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 3) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				popts->cpo_override = pbsp->cpo_override;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for %lu MT/s\n",
+		       ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+	/* force DDR bus width to 32 bits */
+	popts->data_bus_width = 1;
+	popts->otf_burst_chop_en = 0;
+	popts->burst_length = DDR_BL8;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 1;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
+#else
+	popts->cswl_override = DDR_CSWL_CS0;
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x58;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 1071,
+	.caslat_x = 0xfe << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			    unsigned int controller_number,
+			    unsigned int dimm_number)
+{
+	static const char dimm_model[] = "Fixed DDR on board";
+
+	if (((controller_number == 0) && (dimm_number == 0)) ||
+	    ((controller_number == 1) && (dimm_number == 0))) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+	void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+	/* does not provide HW signals for power management */
+	clrbits_8(qixis_base + 0x21, 0x2);
+	udelay(1);
+}
+#endif
+
+int fsl_initdram(void)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+	puts("Initializing DDR....using SPD\n");
+	dram_size = fsl_ddr_sdram();
+#else
+	dram_size =  fsl_ddr_sdram_size();
+#endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+	fsl_dp_resume();
+#endif
+
+	erratum_a008850_post();
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/ls1021aqds/ddr.h b/roms/u-boot/board/freescale/ls1021aqds/ddr.h
new file mode 100644
index 000000000..58a883843
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/ddr.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+void erratum_a008850_post(void);
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+	u32 cpo_override;
+	u32 write_data_delay;
+	u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0, 8,     8, 0x090A0B0B, 0x0C0D0E0C,},
+	{1,  1900, 0, 8,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+	{1,  2200, 0, 8,    10, 0x0B0C0D0C, 0x0E0F110E,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+	{1,  833,  1, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 1, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{1,  833,  2, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 2, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  833,  4, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{2,  1350, 4, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1350, 0, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1666, 4, 8,    0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{2,  1666, 0, 8,    0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+#else
+#error DDR type not defined
+#endif
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls1021aqds/eth.c b/roms/u-boot/board/freescale/ls1021aqds/eth.c
new file mode 100644
index 000000000..a9f162b97
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/eth.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This file handles the board muxing between the RGMII/SGMII PHYs on
+ * Freescale LS1021AQDS board. The RGMII PHYs are the three on-board 1Gb
+ * ports. The SGMII PHYs are provided by the standard Freescale four-port
+ * SGMII riser card.
+ *
+ * Muxing is handled via the PIXIS BRDCFG4 register. The EMI1 bits control
+ * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII depends
+ * on which port is used. The value for SGMII depends on which slot the riser
+ * is inserted in.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <malloc.h>
+
+#include "../common/sgmii_riser.h"
+#include "../common/qixis.h"
+
+#define EMI1_MASK       0x1f
+#define EMI1_RGMII0     1
+#define EMI1_RGMII1     2
+#define EMI1_RGMII2     3
+#define EMI1_SGMII1     0x1c
+#define EMI1_SGMII2     0x1d
+
+struct ls1021a_mdio {
+	struct mii_dev *realbus;
+};
+
+static void ls1021a_mux_mdio(int addr)
+{
+	u8 brdcfg4;
+
+	brdcfg4 = QIXIS_READ(brdcfg[4]);
+	brdcfg4 &= EMI1_MASK;
+
+	switch (addr) {
+	case EMI1_RGMII0:
+		brdcfg4 |= 0;
+		break;
+	case EMI1_RGMII1:
+		brdcfg4 |= 0x20;
+		break;
+	case EMI1_RGMII2:
+		brdcfg4 |= 0x40;
+		break;
+	case EMI1_SGMII1:
+		brdcfg4 |= 0x60;
+		break;
+	case EMI1_SGMII2:
+		brdcfg4 |= 0x80;
+		break;
+	default:
+		brdcfg4 |= 0xa0;
+		break;
+	}
+
+	QIXIS_WRITE(brdcfg[4], brdcfg4);
+}
+
+static int ls1021a_mdio_read(struct mii_dev *bus, int addr, int devad,
+			     int regnum)
+{
+	struct ls1021a_mdio *priv = bus->priv;
+
+	ls1021a_mux_mdio(addr);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1021a_mdio_write(struct mii_dev *bus, int addr, int devad,
+			      int regnum, u16 value)
+{
+	struct ls1021a_mdio *priv = bus->priv;
+
+	ls1021a_mux_mdio(addr);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls1021a_mdio_reset(struct mii_dev *bus)
+{
+	struct ls1021a_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int ls1021a_mdio_init(char *realbusname, char *fakebusname)
+{
+	struct ls1021a_mdio *lsmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate LS102xA MDIO bus\n");
+		return -1;
+	}
+
+	lsmdio = malloc(sizeof(*lsmdio));
+	if (!lsmdio) {
+		printf("Failed to allocate LS102xA private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = ls1021a_mdio_read;
+	bus->write = ls1021a_mdio_write;
+	bus->reset = ls1021a_mdio_reset;
+	strcpy(bus->name, fakebusname);
+
+	lsmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!lsmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(lsmdio);
+		return -1;
+	}
+
+	bus->priv = lsmdio;
+
+	return mdio_register(bus);
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[3];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	if (is_serdes_configured(SGMII_TSEC1)) {
+		puts("eTSEC1 is in sgmii mode\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+		tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO";
+	} else {
+		tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO";
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (is_serdes_configured(SGMII_TSEC2)) {
+		puts("eTSEC2 is in sgmii mode\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+		tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO";
+	} else {
+		tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO";
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO";
+	num++;
+#endif
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_init(tsec_info, num);
+#endif
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	/* Register the virtual MDIO front-ends */
+	ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_RGMII_MDIO");
+	ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_SGMII_MDIO");
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/freescale/ls1021aqds/ls1021aqds.c b/roms/u-boot/board/freescale/ls1021aqds/ls1021aqds.c
new file mode 100644
index 000000000..aa1f6025c
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/ls1021aqds.c
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <init.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <asm/arch/ls102xa_devdis.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <fsl_csu.h>
+#include <fsl_ifc.h>
+#include <fsl_sec.h>
+#include <spl.h>
+#include <fsl_devdis.h>
+#include <fsl_validate.h>
+#include <fsl_ddr.h>
+#include "../common/sleep.h"
+#include "../common/qixis.h"
+#include "ls1021aqds_qixis.h"
+#ifdef CONFIG_U_QE
+#include <fsl_qe.h>
+#endif
+
+#define PIN_MUX_SEL_CAN		0x03
+#define PIN_MUX_SEL_IIC2	0xa0
+#define PIN_MUX_SEL_RGMII	0x00
+#define PIN_MUX_SEL_SAI		0x0c
+#define PIN_MUX_SEL_SDHC	0x00
+
+#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0x0f) | value)
+#define SET_EC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
+enum {
+	MUX_TYPE_CAN,
+	MUX_TYPE_IIC2,
+	MUX_TYPE_RGMII,
+	MUX_TYPE_SAI,
+	MUX_TYPE_SDHC,
+	MUX_TYPE_SD_PCI4,
+	MUX_TYPE_SD_PC_SA_SG_SG,
+	MUX_TYPE_SD_PC_SA_PC_SG,
+	MUX_TYPE_SD_PC_SG_SG,
+};
+
+enum {
+	GE0_CLK125,
+	GE2_CLK125,
+	GE1_CLK125,
+};
+
+int checkboard(void)
+{
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+	char buf[64];
+#endif
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
+	u8 sw;
+#endif
+
+	puts("Board: LS1021AQDS\n");
+
+#ifdef CONFIG_SD_BOOT
+	puts("SD\n");
+#elif CONFIG_QSPI_BOOT
+	puts("QSPI\n");
+#else
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("PromJet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else if (sw == 0x15)
+		printf("IFCCard\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+	printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
+	       QIXIS_READ(id), QIXIS_READ(arch));
+
+	printf("FPGA:  v%d (%s), build %d\n",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+#endif
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0f) {
+	case QIXIS_SYSCLK_64:
+		return 64000000;
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
+{
+	int ret;
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	/*
+	 * When resuming from deep sleep, the I2C channel may not be
+	 * in the default channel. So, switch to the default channel
+	 * before accessing DDR SPD.
+	 *
+	 * PCA9547(0x77) mount on I2C1 bus
+	 */
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
+	return fsl_initdram();
+}
+
+int board_early_init_f(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_TSEC_ENET
+	/* clear BD & FR bits for BE BD's and frame data */
+	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+#endif
+
+#ifdef CONFIG_FSL_IFC
+	init_early_memctl_regs();
+#endif
+
+	arch_soc_init();
+
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+#ifdef CONFIG_NAND_BOOT
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 porsr1, pinctl;
+
+	/*
+	 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
+	 * NAND boot because IFC signals > IFC_AD7 are not enabled.
+	 * This workaround changes RCW source to make all signals enabled.
+	 */
+	porsr1 = in_be32(&gur->porsr1);
+	pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
+		 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
+	out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+		 pinctl);
+#endif
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_FSL_IFC
+	init_early_memctl_regs();
+#endif
+
+	get_clocks();
+
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
+	preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+	i2c_init_all();
+#endif
+
+	timer_init();
+	dram_init();
+
+	/* Allow OCRAM access permission as R/W */
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	board_init_r(NULL, 0);
+}
+#endif
+
+void config_etseccm_source(int etsec_gtx_125_mux)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+	switch (etsec_gtx_125_mux) {
+	case GE0_CLK125:
+		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
+		debug("etseccm set to GE0_CLK125\n");
+		break;
+
+	case GE2_CLK125:
+		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+		debug("etseccm set to GE2_CLK125\n");
+		break;
+
+	case GE1_CLK125:
+		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
+		debug("etseccm set to GE1_CLK125\n");
+		break;
+
+	default:
+		printf("Error! trying to set etseccm to invalid value\n");
+		break;
+	}
+}
+
+int config_board_mux(int ctrl_type)
+{
+	u8 reg12, reg14;
+
+	reg12 = QIXIS_READ(brdcfg[12]);
+	reg14 = QIXIS_READ(brdcfg[14]);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_CAN:
+		config_etseccm_source(GE2_CLK125);
+		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
+		break;
+	case MUX_TYPE_IIC2:
+		reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
+		break;
+	case MUX_TYPE_RGMII:
+		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
+		break;
+	case MUX_TYPE_SAI:
+		config_etseccm_source(GE2_CLK125);
+		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
+		break;
+	case MUX_TYPE_SDHC:
+		reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
+		break;
+	case MUX_TYPE_SD_PCI4:
+		reg12 = 0x38;
+		break;
+	case MUX_TYPE_SD_PC_SA_SG_SG:
+		reg12 = 0x01;
+		break;
+	case MUX_TYPE_SD_PC_SA_PC_SG:
+		reg12 = 0x01;
+		break;
+	case MUX_TYPE_SD_PC_SG_SG:
+		reg12 = 0x21;
+		break;
+	default:
+		printf("Wrong mux interface type\n");
+		return -1;
+	}
+
+	QIXIS_WRITE(brdcfg[12], reg12);
+	QIXIS_WRITE(brdcfg[14], reg14);
+
+	return 0;
+}
+
+int config_serdes_mux(void)
+{
+	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 cfg;
+
+	cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
+	cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	switch (cfg) {
+	case 0x0:
+		config_board_mux(MUX_TYPE_SD_PCI4);
+		break;
+	case 0x30:
+		config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
+		break;
+	case 0x60:
+		config_board_mux(MUX_TYPE_SD_PC_SG_SG);
+		break;
+	case 0x70:
+		config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
+		break;
+	default:
+		printf("SRDS1 prtcl:0x%x\n", cfg);
+		break;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_CHAIN_OF_TRUST
+	fsl_setenv_chain_of_trust();
+#endif
+
+	return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+	int conflict_flag;
+
+	/* some signals can not enable simultaneous*/
+	conflict_flag = 0;
+	if (hwconfig("sdhc"))
+		conflict_flag++;
+	if (hwconfig("iic2"))
+		conflict_flag++;
+	if (conflict_flag > 1) {
+		printf("WARNING: pin conflict !\n");
+		return 0;
+	}
+
+	conflict_flag = 0;
+	if (hwconfig("rgmii"))
+		conflict_flag++;
+	if (hwconfig("can"))
+		conflict_flag++;
+	if (hwconfig("sai"))
+		conflict_flag++;
+	if (conflict_flag > 1) {
+		printf("WARNING: pin conflict !\n");
+		return 0;
+	}
+
+	if (hwconfig("can"))
+		config_board_mux(MUX_TYPE_CAN);
+	else if (hwconfig("rgmii"))
+		config_board_mux(MUX_TYPE_RGMII);
+	else if (hwconfig("sai"))
+		config_board_mux(MUX_TYPE_SAI);
+
+	if (hwconfig("iic2"))
+		config_board_mux(MUX_TYPE_IIC2);
+	else if (hwconfig("sdhc"))
+		config_board_mux(MUX_TYPE_SDHC);
+
+#ifdef CONFIG_FSL_DEVICE_DISABLE
+	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+#endif
+#ifdef CONFIG_FSL_CAAM
+	return sec_init();
+#endif
+	return 0;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+	erratum_a010315();
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+	erratum_a009942_check_cpo();
+#endif
+
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
+
+#ifndef CONFIG_SYS_FSL_NO_SERDES
+	fsl_serdes_init();
+	config_serdes_mux();
+#endif
+
+	ls102xa_smmu_stream_id_init();
+
+#ifdef CONFIG_U_QE
+	u_qe_init();
+#endif
+
+	return 0;
+}
+
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+}
+#endif
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
+
+u8 flash_read8(void *addr)
+{
+	return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+	__raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 val = __raw_readw(addr);
+
+	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
diff --git a/roms/u-boot/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/roms/u-boot/board/freescale/ls1021aqds/ls1021aqds_qixis.h
new file mode 100644
index 000000000..7ad08a54e
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/ls1021aqds_qixis.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __LS1021AQDS_QIXIS_H__
+#define __LS1021AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1021AQDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+#define QIXIS_SYSCLK_64			0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+#define QIXIS_SRDS1CLK_100		0x0
+
+#define QIXIS_DCU_BRDCFG5		0x55
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls1021aqds/ls102xa_pbi.cfg b/roms/u-boot/board/freescale/ls1021aqds/ls102xa_pbi.cfg
new file mode 100644
index 000000000..f1a1b63ab
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/ls102xa_pbi.cfg
@@ -0,0 +1,12 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
diff --git a/roms/u-boot/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/roms/u-boot/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
new file mode 100644
index 000000000..d76e9132e
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0608000c 00000000 00000000 00000000
+60000000 00407900 e0106a00 21046000
+00000000 00000000 00000000 00038000
+00000000 001b7200 00000000 00000000
diff --git a/roms/u-boot/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg b/roms/u-boot/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
new file mode 100644
index 000000000..f0cf9c2b3
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
@@ -0,0 +1,14 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+0608000c 00000000 00000000 00000000
+60000000 00407900 60040a00 21046000
+00000000 00000000 00000000 00038000
+00000000 001b7200 00000000 00000000
+
+#disable IFC, enable QSPI and DSPI
+#0608000c 00000000 00000000 00000000
+#60000000 00407900 60040a00 21046000
+#00000000 00000000 00000000 00038000
+#20024800 001b7200 00000000 00000000
diff --git a/roms/u-boot/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg b/roms/u-boot/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
new file mode 100644
index 000000000..10cc4a9ab
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
@@ -0,0 +1,14 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+#0608000c 00000000 00000000 00000000
+#60000000 00407900 60040a00 21046000
+#00000000 00000000 00000000 00038000
+#00000000 001b7200 00000000 00000000
+
+#disable IFC, enable QSPI and DSPI
+0608000c 00000000 00000000 00000000
+60000000 00407900 60040a00 21046000
+00000000 00000000 00000000 00038000
+20024800 001b7200 00000000 00000000
diff --git a/roms/u-boot/board/freescale/ls1021aqds/psci.S b/roms/u-boot/board/freescale/ls1021aqds/psci.S
new file mode 100644
index 000000000..0f38c934d
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021aqds/psci.S
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 NXP Semiconductor.
+ * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+	.align	5
+
+.globl	psci_system_off
+psci_system_off:
+	@ Get QIXIS base address
+	movw	r1, #(QIXIS_BASE & 0xffff)
+	movt	r1, #(QIXIS_BASE >> 16)
+
+	ldrb	r2, [r1, #QIXIS_PWR_CTL]
+	orr	r2, r2, #QIXIS_PWR_CTL_POWEROFF
+	strb	r2, [r1, #QIXIS_PWR_CTL]
+
+1:	wfi
+	b	1b
+
+	.popsection
diff --git a/roms/u-boot/board/freescale/ls1021atsn/Kconfig b/roms/u-boot/board/freescale/ls1021atsn/Kconfig
new file mode 100644
index 000000000..d999fa469
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atsn/Kconfig
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0
+if TARGET_LS1021ATSN
+
+config SYS_BOARD
+	default "ls1021atsn"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "ls102xa"
+
+config SYS_CONFIG_NAME
+	default "ls1021atsn"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/ls1021atsn/MAINTAINERS b/roms/u-boot/board/freescale/ls1021atsn/MAINTAINERS
new file mode 100644
index 000000000..560bb615d
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atsn/MAINTAINERS
@@ -0,0 +1,8 @@
+NXP LS1021A-TSN Board
+M:	Vladimir Oltean <olteanv@gmail.com>
+S:	Maintained
+F:	arch/arm/dts/ls1021a-tsn.dts
+F:	board/freescale/ls1021atsn/
+F:	include/configs/ls1021atsn.h
+F:	configs/ls1021atsn_qspi_defconfig
+F:	configs/ls1021atsn_sdcard_defconfig
diff --git a/roms/u-boot/board/freescale/ls1021atsn/Makefile b/roms/u-boot/board/freescale/ls1021atsn/Makefile
new file mode 100644
index 000000000..b4808f05e
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atsn/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-y += ls1021atsn.o
+obj-$(CONFIG_ARMV7_PSCI) += ../ls1021atwr/psci.o
diff --git a/roms/u-boot/board/freescale/ls1021atsn/README.rst b/roms/u-boot/board/freescale/ls1021atsn/README.rst
new file mode 100644
index 000000000..cdec02f1a
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atsn/README.rst
@@ -0,0 +1,97 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+LS1021A-TSN Board Overview
+==========================
+
+ - 1GB DDR3 at 800 MHz
+ - Spansion/Cypress 64 MB (Rev. A) / 32 MB (Rev. B and C) QSPI NOR flash
+ - Ethernet
+     - 2 SGMII 10/100/1G Ethernet ports (Atheros AR8031)
+     - One SJA1105T switch with 4 Ethernet ports (Broadcom BCM5464R)
+     - One internal RGMII port connected to the switch
+ - SDHC
+     - microSDHC/SDXC connector
+ - Other I/O
+    - One Serial port
+    - Arduino and expansion headers
+    - mPCIE slot
+    - SATA port
+    - USB3.0 port
+
+LS1021A Memory map
+==================
+
+The addresses in brackets are physical addresses.
+
+==============  ==============  ==============================  =======
+Start Address   End Address     Description                     Size
+==============  ==============  ==============================  =======
+0x00_0000_0000  0x00_000F_FFFF  Secure Boot ROM                 1MB
+0x00_0100_0000  0x00_0FFF_FFFF  CCSRBAR                         240MB
+0x00_1000_0000  0x00_1000_FFFF  OCRAM0                          64KB
+0x00_1001_0000  0x00_1001_FFFF  OCRAM1                          64KB
+0x00_2000_0000  0x00_20FF_FFFF  DCSR                            16MB
+0x00_4000_0000  0x00_5FFF_FFFF  QSPI                            512MB
+0x00_6000_0000  0x00_67FF_FFFF  IFC - NOR Flash                 128MB
+0x00_8000_0000  0x00_FFFF_FFFF  DRAM1                           2GB
+==============  ==============  ==============================  =======
+
+Compiling and flashing
+======================
+
+The LS1021A-TSN board comes along with a microSD card with OpenIL U-Boot that
+can be used to update its internal QSPI flash (which is empty out of the
+factory).
+
+To compile and flash an SD card image::
+
+  make ls1021atsn_sdcard_defconfig && make -j 8 && sudo cp u-boot-with-spl-pbl.bin /srv/tftpboot/
+  => tftp 0x82000000 u-boot-with-spl-pbl.bin && mmc rescan && mmc erase 8 0x1100 && mmc write 0x82000000 8 0x1100
+
+For the QSPI flash, first obtain the Reset Configuration Word binary for
+bootimg from the QSPI flash from the rcw project
+(https://source.codeaurora.org/external/qoriq/qoriq-components/rcw)::
+
+  make -j 8 && sudo cp ls1021atsn/SSR_PNS_30/rcw_1200_qspiboot.bin.swapped /srv/tftpboot/
+
+The above RCW binary takes care of swapping the QSPI AMBA memory, so that the
+U-Boot binary does not need to be swapped when flashing it.
+
+To compile and flash a U-Boot image for QSPI::
+
+  make ls1021atsn_qspi_defconfig && make -j 8 && sudo cp u-boot.bin /srv/tftpboot/
+
+Then optionally create a custom uboot-env.txt file (although the default
+environment already supports distro boot) and convert it to binary format::
+
+  mkenvimage -s 2M -o /srv/tftpboot/uboot-env.bin uboot-env.txt
+
+To program the QSPI flash with the images::
+
+  => tftp 0x82000000 rcw_1200_qspiboot.bin.swapped && sf probe && sf erase 0x0 +${filesize} && sf write 0x82000000 0x0 ${filesize}
+  => tftp 0x82000000 u-boot.bin && sf probe && sf erase 0x100000 +${filesize} && sf write 0x82000000 0x100000 ${filesize}
+  => tftp 0x82000000 uboot-env.bin && sf probe && sf erase 0x400000 +${filesize} && sf write 0x82000000 0x400000 ${filesize}
+
+The boards contain an AT24 I2C EEPROM that is supposed to hold the MAC
+addresses of the Ethernet interfaces, however the EEPROM comes blank out of
+the factory, and the MAC addresses are printed on a label on the bottom of
+the boards.
+
+To write the MAC addresses to the EEPROM, the following needs to be done once::
+
+  => mac id
+  => mac 0 00:1F:7B:xx:xx:xx
+  => mac 1 00:1F:7B:xx:xx:xx
+  => mac 2 00:1F:7B:xx:xx:xx
+  => mac save
+
+The switch ports do not have their own MAC address - they inherit it from the
+master enet2 port.
+
+Known issues and limitations
+============================
+
+- The 4 SJA1105 switch ports are not functional in U-Boot for now.
+- Since the IFC pins are multiplexed with QSPI on LS1021A, currently there is
+  no way to talk to the CPLD for e.g. running the "qixis_reset" command, or
+  turning the fan on, etc.
diff --git a/roms/u-boot/board/freescale/ls1021atsn/ls1021atsn.c b/roms/u-boot/board/freescale/ls1021atsn/ls1021atsn.c
new file mode 100644
index 000000000..c1acd3040
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atsn/ls1021atsn.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2016-2019 NXP Semiconductors
+ */
+#include <common.h>
+#include <clock_legacy.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch-ls102xa/ls102xa_soc.h>
+#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include "../common/sleep.h"
+#include <fsl_validate.h>
+#include <fsl_immap.h>
+#include <fsl_csu.h>
+#include <netdev.h>
+#include <spl.h>
+#ifdef CONFIG_U_QE
+#include <fsl_qe.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ddrmc_init(void)
+{
+#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+	u32 temp_sdram_cfg, tmp;
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
+
+	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
+	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
+	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
+	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
+	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
+	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
+
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot()) {
+		out_be32(&ddr->sdram_cfg_2,
+			 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
+		out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+		out_be32(&ddr->init_ext_addr, (1 << 31));
+
+		/* DRAM VRef will not be trained */
+		out_be32(&ddr->ddr_cdr2,
+			 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
+	} else
+#endif
+	{
+		out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+		out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
+	}
+
+	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
+	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
+
+	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
+
+	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
+
+	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
+	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
+
+	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
+
+	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
+	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
+
+	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+
+	/* DDR erratum A-009942 */
+	tmp = in_be32(&ddr->debug[28]);
+	out_be32(&ddr->debug[28], tmp | 0x0070006f);
+
+	udelay(1);
+
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot()) {
+		/* enter self-refresh */
+		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+		temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+
+		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
+	} else
+#endif
+		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
+
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot()) {
+		/* exit self-refresh */
+		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+		temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+	}
+#endif
+#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
+}
+
+int dram_init(void)
+{
+	ddrmc_init();
+
+	erratum_a008850_post();
+
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+	fsl_dp_resume();
+#endif
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_TSEC_ENET
+	/*
+	 * Clear BD & FR bits for big endian BD's and frame data (aka set
+	 * correct eTSEC endianness). This is crucial in ensuring that it does
+	 * not report Data Parity Errors in its RX/TX FIFOs when attempting to
+	 * send traffic.
+	 */
+	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+	/* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
+	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+#endif
+
+	arch_soc_init();
+
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot()) {
+		timer_init();
+		dram_init();
+	}
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	void (*second_uboot)(void);
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	get_clocks();
+
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
+	preloader_console_init();
+
+	dram_init();
+
+	/* Allow OCRAM access permission as R/W */
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+	enable_layerscape_ns_access();
+#endif
+
+	/*
+	 * if it is woken up from deep sleep, then jump to second
+	 * stage U-Boot and continue executing without recopying
+	 * it from SD since it has already been reserved in memory
+	 * in last boot.
+	 */
+	if (is_warm_boot()) {
+		second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
+		second_uboot();
+	}
+
+	board_init_r(NULL, 0);
+}
+#endif
+
+int board_init(void)
+{
+#ifndef CONFIG_SYS_FSL_NO_SERDES
+	fsl_serdes_init();
+#endif
+	ls102xa_smmu_stream_id_init();
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_U_QE
+	u_qe_init();
+#endif
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+void spl_board_init(void)
+{
+	ls102xa_smmu_stream_id_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_CHAIN_OF_TRUST
+	fsl_setenv_chain_of_trust();
+#endif
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_DEVICE_DISABLE
+	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	return sec_init();
+#endif
+}
+#endif
+
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+}
+#endif
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/ls1021atsn/ls102xa_pbi.cfg b/roms/u-boot/board/freescale/ls1021atsn/ls102xa_pbi.cfg
new file mode 100644
index 000000000..ba1499b26
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atsn/ls102xa_pbi.cfg
@@ -0,0 +1,15 @@
+# PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+# Configure Scratch register
+09ee0200 10000000
+# Configure alternate space
+09570158 00001000
+# Flush PBL data
+096100c0 000FFFFF
+
+09ea085c 00502880
+09ea0560 80800000
diff --git a/roms/u-boot/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg b/roms/u-boot/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg
new file mode 100644
index 000000000..a6fc91436
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg
@@ -0,0 +1,8 @@
+# PBL preamble and RCW header
+aa55aa55 01ee0100
+
+# Disable IFC, enable QSPI and DSPI
+0608000c 00000000 00000000 00000000
+30000000 08007900 40105a00 21046000
+00000000 00000000 00000000 10002000
+20124801 8804b340 00000000 00000000
diff --git a/roms/u-boot/board/freescale/ls1021atwr/Kconfig b/roms/u-boot/board/freescale/ls1021atwr/Kconfig
new file mode 100644
index 000000000..a4641cbca
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atwr/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_LS1021ATWR
+
+config SYS_BOARD
+	default "ls1021atwr"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "ls102xa"
+
+config SYS_CONFIG_NAME
+	default "ls1021atwr"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/ls1021atwr/MAINTAINERS b/roms/u-boot/board/freescale/ls1021atwr/MAINTAINERS
new file mode 100644
index 000000000..7ab8347e9
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atwr/MAINTAINERS
@@ -0,0 +1,12 @@
+LS1021ATWR BOARD
+M:	Alison Wang <alison.wang@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1021atwr/
+F:	include/configs/ls1021atwr.h
+F:	configs/ls1021atwr_nor_defconfig
+F:	configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+F:	configs/ls1021atwr_nor_lpuart_defconfig
+F:	configs/ls1021atwr_sdcard_ifc_defconfig
+F:	configs/ls1021atwr_sdcard_qspi_defconfig
+F:	configs/ls1021atwr_qspi_defconfig
+F:	configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/ls1021atwr/Makefile b/roms/u-boot/board/freescale/ls1021atwr/Makefile
new file mode 100644
index 000000000..d9a2f52f2
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atwr/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1021atwr.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/roms/u-boot/board/freescale/ls1021atwr/README b/roms/u-boot/board/freescale/ls1021atwr/README
new file mode 100644
index 000000000..896a65947
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atwr/README
@@ -0,0 +1,115 @@
+Overview
+--------
+The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC.
+
+LS1021A SoC Overview
+------------------
+The QorIQ LS1 family, which includes the LS1021A communications processor,
+is built on Layerscape architecture, the industry's first software-aware,
+core-agnostic networking architecture to offer unprecedented efficiency
+and scale.
+
+A member of the value-performance tier, the QorIQ LS1021A processor provides
+extensive integration and power efficiency for fanless, small form factor
+enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
+running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
+performance of over 6,000, as well as virtualization support, advanced
+security features and the broadest array of high-speed interconnects and
+optimized peripheral features ever offered in a sub-3 W processor.
+
+The QorIQ LS1021A processor features an integrated LCD controller,
+CAN controller for implementing industrial protocols, DDR3L/4 running
+up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
+protection on both L1 and L2 caches. The LS1021A processor is pin- and
+software-compatible with the QorIQ LS1020A and LS1022A processors.
+
+The LS1021A SoC includes the following function and features:
+
+ - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
+ - Dual high-preformance ARM Cortex-A7 cores, each core includes:
+   - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
+   - 512 Kbyte shared coherent L2 Cache (with ECC protection)
+   - NEON Co-processor (per core)
+   - 40-bit physical addressing
+   - Vector floating-point support
+ - ARM Core-Link CCI-400 Cache Coherent Interconnect
+ - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
+   supporting speeds up to 1600Mtps
+   - ECC and interleaving support
+ - VeTSEC Ethernet complex
+   - Up to 3x virtualized 10/100/1000 Ethernet controllers
+   - MII, RMII, RGMII, and SGMII support
+   - QoS, lossless flow control, and IEEE 1588 support
+ - 4-lane 6GHz SerDes
+ - High speed interconnect (4 SerDes lanes with are muxed for these protocol)
+   - Two PCI Express Gen2 controllers running at up to 5 GHz
+   - One Serial ATA 3.0 supporting 6 GT/s operation
+   - Two SGMII interfaces supporting 1000 Mbps
+ - Additional peripheral interfaces
+   - One high-speed USB 3.0 controller with integrated PHY and one high-speed
+     USB 2.00 controller with ULPI
+   - Integrated flash controller (IFC) with 16-bit interface
+   - Quad SPI NOR Flash
+   - One enhanced Secure digital host controller
+   - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface)
+   - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power
+     UARTs
+   - Three I2C controllers
+   - Eight FlexTimers four supporting PWM and four FlexCAN ports
+   - Four GPIO controllers supporting up to 109 general purpose I/O signals
+ - Integrated advanced audio block:
+   - Four synchronous audio interfaces (SAI)
+   - Sony/Philips Digital Interconnect Format (SPDIF)
+   - Asynchronous Sample Rate Converter (ASRC)
+ - Hardware based crypto offload engine
+   - IPSec forwarding at up to 1Gbps
+   - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported
+   - Public key hardware accelerator
+   - True Random Number Generator (NIST Certified)
+   - Advanced Encryption Standard Accelerators (AESA)
+   - Data Encryption Standard Accelerators
+ - QUICC Engine ULite block
+   - Two universal communication controllers (TDM and HDLC) supporting 64
+   multichannels, each running at 64 Kbps
+   - Support for 256 channels of HDLC
+ - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported
+
+LS1021ATWR board Overview
+-------------------------
+ - DDR Controller
+     - Supports rates of up to 1600 MHz data-rate
+     - Supports one DDR3LP SDRAM.
+ - IFC/Local Bus
+     - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+     - Three on-board RGMII 10/100/1G ethernet ports.
+ - CPLD
+ - Clocks
+     - System and DDR clock (SYSCLK, DDRCLK)
+     - SERDES clocks
+ - Power Supplies
+ - SDHC
+     - SDHC/SDXC connector
+ - Other IO
+    - One Serial port
+    - Three I2C ports
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address	End Address	Description			Size
+0x00_0000_0000	0x00_000F_FFFF	Secure Boot ROM			1MB
+0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR				240MB
+0x00_1000_0000	0x00_1000_FFFF	OCRAM0				64KB
+0x00_1001_0000	0x00_1001_FFFF	OCRAM1				64KB
+0x00_2000_0000	0x00_20FF_FFFF	DCSR				16MB
+0x00_4000_0000	0x00_5FFF_FFFF	QSPI				512MB
+0x00_6000_0000	0x00_67FF_FFFF	IFC - NOR Flash			128MB
+0x00_8000_0000	0x00_FFFF_FFFF	DRAM1				2GB
+
+LS1021a rev1.0 Soc specific Options/Settings
+--------------------------------------------
+If the LS1021a Soc is rev1.0, you need modify the configure file.
+Add the following define in include/configs/ls1021atwr.h:
+#define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/roms/u-boot/board/freescale/ls1021atwr/dcu.c b/roms/u-boot/board/freescale/ls1021atwr/dcu.c
new file mode 100644
index 000000000..7bf283e3d
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atwr/dcu.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ */
+
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include <asm/global_data.h>
+#include "div64.h"
+#include "../common/dcu_sii9022a.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+	unsigned long long div;
+
+	div = (unsigned long long)(gd->bus_clk / 1000);
+	div *= (unsigned long long)pixclock;
+	do_div(div, 1000000000);
+
+	return div;
+}
+
+int platform_dcu_init(struct fb_info *fbinfo,
+		      unsigned int xres, unsigned int yres,
+		      const char *port,
+		      struct fb_videomode *dcu_fb_videomode)
+{
+	const char *name;
+	unsigned int pixel_format;
+
+	if (strncmp(port, "twr_lcd", 4) == 0) {
+		name = "TWR_LCD_RGB card";
+	} else {
+		name = "HDMI";
+		dcu_set_dvi_encoder(dcu_fb_videomode);
+	}
+
+	printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+	pixel_format = 32;
+	fsl_dcu_init(fbinfo, xres, yres, pixel_format);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/ls1021atwr/ls1021atwr.c b/roms/u-boot/board/freescale/ls1021atwr/ls1021atwr.c
new file mode 100644
index 000000000..f0b441db6
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atwr/ls1021atwr.c
@@ -0,0 +1,747 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <command.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <fsl_csu.h>
+#include <fsl_ifc.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <fsl_sec.h>
+#include <fsl_devdis.h>
+#include <spl.h>
+#include <linux/delay.h>
+#include "../common/sleep.h"
+#ifdef CONFIG_U_QE
+#include <fsl_qe.h>
+#endif
+#include <fsl_validate.h>
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define VERSION_MASK		0x00FF
+#define BANK_MASK		0x0001
+#define CFG_RESET		0x1
+#define INIT_RESET		0x1
+
+#define CPLD_SET_MUX_SERDES	0x20
+#define CPLD_SET_BOOT_BANK	0x40
+
+#define BOOT_FROM_UPPER_BANK	0x0
+#define BOOT_FROM_LOWER_BANK	0x1
+
+#define LANEB_SATA		(0x01)
+#define LANEB_SGMII1		(0x02)
+#define LANEC_SGMII1		(0x04)
+#define LANEC_PCIEX1		(0x08)
+#define LANED_PCIEX2		(0x10)
+#define LANED_SGMII2		(0x20)
+
+#define MASK_LANE_B		0x1
+#define MASK_LANE_C		0x2
+#define MASK_LANE_D		0x4
+#define MASK_SGMII		0x8
+
+#define KEEP_STATUS		0x0
+#define NEED_RESET		0x1
+
+#define SOFT_MUX_ON_I2C3_IFC	0x2
+#define SOFT_MUX_ON_CAN3_USB2	0x8
+#define SOFT_MUX_ON_QE_LCD	0x10
+
+#define PIN_I2C3_IFC_MUX_I2C3	0x0
+#define PIN_I2C3_IFC_MUX_IFC	0x1
+#define PIN_CAN3_USB2_MUX_USB2	0x0
+#define PIN_CAN3_USB2_MUX_CAN3	0x1
+#define PIN_QE_LCD_MUX_LCD	0x0
+#define PIN_QE_LCD_MUX_QE	0x1
+
+struct cpld_data {
+	u8 cpld_ver;		/* cpld revision */
+	u8 cpld_ver_sub;	/* cpld sub revision */
+	u8 pcba_ver;		/* pcb revision number */
+	u8 system_rst;		/* reset system by cpld */
+	u8 soft_mux_on;		/* CPLD override physical switches Enable */
+	u8 cfg_rcw_src1;	/* Reset config word 1 */
+	u8 cfg_rcw_src2;	/* Reset config word 2 */
+	u8 vbank;		/* Flash bank selection Control */
+	u8 gpio;		/* GPIO for TWR-ELEV */
+	u8 i2c3_ifc_mux;
+	u8 mux_spi2;
+	u8 can3_usb2_mux;	/* CAN3 and USB2 Selection */
+	u8 qe_lcd_mux;		/* QE and LCD Selection */
+	u8 serdes_mux;		/* Multiplexed pins for SerDes Lanes */
+	u8 global_rst;		/* reset with init CPLD reg to default */
+	u8 rev1;		/* Reserved */
+	u8 rev2;		/* Reserved */
+};
+
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+static void cpld_show(void)
+{
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
+	       in_8(&cpld_data->cpld_ver) & VERSION_MASK,
+	       in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
+	       in_8(&cpld_data->pcba_ver) & VERSION_MASK,
+	       in_8(&cpld_data->vbank) & BANK_MASK);
+
+#ifdef CONFIG_DEBUG
+	printf("soft_mux_on =%x\n",
+	       in_8(&cpld_data->soft_mux_on));
+	printf("cfg_rcw_src1 =%x\n",
+	       in_8(&cpld_data->cfg_rcw_src1));
+	printf("cfg_rcw_src2 =%x\n",
+	       in_8(&cpld_data->cfg_rcw_src2));
+	printf("vbank =%x\n",
+	       in_8(&cpld_data->vbank));
+	printf("gpio =%x\n",
+	       in_8(&cpld_data->gpio));
+	printf("i2c3_ifc_mux =%x\n",
+	       in_8(&cpld_data->i2c3_ifc_mux));
+	printf("mux_spi2 =%x\n",
+	       in_8(&cpld_data->mux_spi2));
+	printf("can3_usb2_mux =%x\n",
+	       in_8(&cpld_data->can3_usb2_mux));
+	printf("qe_lcd_mux =%x\n",
+	       in_8(&cpld_data->qe_lcd_mux));
+	printf("serdes_mux =%x\n",
+	       in_8(&cpld_data->serdes_mux));
+#endif
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: LS1021ATWR\n");
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+	cpld_show();
+#endif
+
+	return 0;
+}
+
+void ddrmc_init(void)
+{
+	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+	u32 temp_sdram_cfg, tmp;
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
+
+	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
+	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
+	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
+	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
+	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
+	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
+
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot()) {
+		out_be32(&ddr->sdram_cfg_2,
+			 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
+		out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+		out_be32(&ddr->init_ext_addr, (1 << 31));
+
+		/* DRAM VRef will not be trained */
+		out_be32(&ddr->ddr_cdr2,
+			 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
+	} else
+#endif
+	{
+		out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+		out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
+	}
+
+	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
+	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
+
+	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
+
+	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
+
+	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
+	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
+
+	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
+
+	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
+	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
+
+	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+
+	/* DDR erratum A-009942 */
+	tmp = in_be32(&ddr->debug[28]);
+	out_be32(&ddr->debug[28], tmp | 0x0070006f);
+
+	udelay(1);
+
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot()) {
+		/* enter self-refresh */
+		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+		temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+
+		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
+	} else
+#endif
+		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
+
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot()) {
+		/* exit self-refresh */
+		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+		temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+	}
+#endif
+}
+
+int dram_init(void)
+{
+#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+	ddrmc_init();
+#endif
+
+	erratum_a008850_post();
+
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+	fsl_dp_resume();
+#endif
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	return pci_eth_init(bis);
+}
+
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+static void convert_serdes_mux(int type, int need_reset)
+{
+	char current_serdes;
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	current_serdes = cpld_data->serdes_mux;
+
+	switch (type) {
+	case LANEB_SATA:
+		current_serdes &= ~MASK_LANE_B;
+		break;
+	case LANEB_SGMII1:
+		current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
+		break;
+	case LANEC_SGMII1:
+		current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
+		break;
+	case LANED_SGMII2:
+		current_serdes |= MASK_LANE_D;
+		break;
+	case LANEC_PCIEX1:
+		current_serdes |= MASK_LANE_C;
+		break;
+	case (LANED_PCIEX2 | LANEC_PCIEX1):
+		current_serdes |= MASK_LANE_C;
+		current_serdes &= ~MASK_LANE_D;
+		break;
+	default:
+		printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
+		return;
+	}
+
+	cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
+	cpld_data->serdes_mux = current_serdes;
+
+	if (need_reset == 1) {
+		printf("Reset board to enable configuration\n");
+		cpld_data->system_rst = CFG_RESET;
+	}
+}
+
+int config_serdes_mux(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
+
+	protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
+	switch (protocol) {
+	case 0x10:
+		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
+		convert_serdes_mux(LANED_PCIEX2 |
+				LANEC_PCIEX1, KEEP_STATUS);
+		break;
+	case 0x20:
+		convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
+		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
+		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
+		break;
+	case 0x30:
+		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
+		convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
+		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
+		break;
+	case 0x70:
+		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
+		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
+		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
+		break;
+	}
+
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+int config_board_mux(void)
+{
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	int conflict_flag;
+
+	conflict_flag = 0;
+	if (hwconfig("i2c3")) {
+		conflict_flag++;
+		cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
+		cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
+	}
+
+	if (hwconfig("ifc")) {
+		conflict_flag++;
+		/* some signals can not enable simultaneous*/
+		if (conflict_flag > 1)
+			goto conflict;
+		cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
+		cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
+	}
+
+	conflict_flag = 0;
+	if (hwconfig("usb2")) {
+		conflict_flag++;
+		cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
+		cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
+	}
+
+	if (hwconfig("can3")) {
+		conflict_flag++;
+		/* some signals can not enable simultaneous*/
+		if (conflict_flag > 1)
+			goto conflict;
+		cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
+		cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
+	}
+
+	conflict_flag = 0;
+	if (hwconfig("lcd")) {
+		conflict_flag++;
+		cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
+		cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
+	}
+
+	if (hwconfig("qe")) {
+		conflict_flag++;
+		/* some signals can not enable simultaneous*/
+		if (conflict_flag > 1)
+			goto conflict;
+		cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
+		cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
+	}
+
+	return 0;
+
+conflict:
+	printf("WARNING: pin conflict! MUX setting may failed!\n");
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_TSEC_ENET
+	/* clear BD & FR bits for BE BD's and frame data */
+	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+#endif
+
+#ifdef CONFIG_FSL_IFC
+	init_early_memctl_regs();
+#endif
+
+	arch_soc_init();
+
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot()) {
+		timer_init();
+		dram_init();
+	}
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	void (*second_uboot)(void);
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	get_clocks();
+
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
+	preloader_console_init();
+
+	timer_init();
+	dram_init();
+
+	/* Allow OCRAM access permission as R/W */
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	/*
+	 * if it is woken up from deep sleep, then jump to second
+	 * stage uboot and continue executing without recopying
+	 * it from SD since it has already been reserved in memeory
+	 * in last boot.
+	 */
+	if (is_warm_boot()) {
+		second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
+		second_uboot();
+	}
+
+	board_init_r(NULL, 0);
+}
+#endif
+
+#ifdef CONFIG_DEEP_SLEEP
+/* program the regulator (MC34VR500) to support deep sleep */
+void ls1twr_program_regulator(void)
+{
+	u8 i2c_device_id;
+
+#define LS1TWR_I2C_BUS_MC34VR500	1
+#define MC34VR500_ADDR			0x8
+#define MC34VR500_DEVICEID		0x4
+#define MC34VR500_DEVICEID_MASK		0x0f
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       LS1TWR_I2C_BUS_MC34VR500);
+		return;
+	}
+	i2c_device_id = dm_i2c_reg_read(dev, 0x0) &
+					MC34VR500_DEVICEID_MASK;
+	if (i2c_device_id != MC34VR500_DEVICEID) {
+		printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
+		return;
+	}
+
+	dm_i2c_reg_write(dev, 0x31, 0x4);
+	dm_i2c_reg_write(dev, 0x4d, 0x4);
+	dm_i2c_reg_write(dev, 0x6d, 0x38);
+	dm_i2c_reg_write(dev, 0x6f, 0x37);
+	dm_i2c_reg_write(dev, 0x71, 0x30);
+#else
+	unsigned int i2c_bus;
+	i2c_bus = i2c_get_bus_num();
+	i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
+	i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
+					MC34VR500_DEVICEID_MASK;
+	if (i2c_device_id != MC34VR500_DEVICEID) {
+		printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
+		return;
+	}
+
+	i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
+	i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
+	i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
+	i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
+	i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
+
+	i2c_set_bus_num(i2c_bus);
+#endif
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+	erratum_a010315();
+#endif
+
+#ifndef CONFIG_SYS_FSL_NO_SERDES
+	fsl_serdes_init();
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+	config_serdes_mux();
+#endif
+#endif
+
+	ls102xa_smmu_stream_id_init();
+
+#ifdef CONFIG_U_QE
+	u_qe_init();
+#endif
+
+#ifdef CONFIG_DEEP_SLEEP
+	ls1twr_program_regulator();
+#endif
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+void spl_board_init(void)
+{
+	ls102xa_smmu_stream_id_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_CHAIN_OF_TRUST
+	fsl_setenv_chain_of_trust();
+#endif
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_DEVICE_DISABLE
+	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+#endif
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+	config_board_mux();
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	return sec_init();
+#endif
+}
+#endif
+
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+}
+#endif
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
+
+u8 flash_read8(void *addr)
+{
+	return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+	__raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 val = __raw_readw(addr);
+
+	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
+
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
+	&& !defined(CONFIG_SPL_BUILD)
+static void convert_flash_bank(char bank)
+{
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	printf("Now switch to boot from flash bank %d.\n", bank);
+	cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
+	cpld_data->vbank = bank;
+
+	printf("Reset board to enable configuration.\n");
+	cpld_data->system_rst = CFG_RESET;
+}
+
+static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;
+	if (strcmp(argv[1], "0") == 0)
+		convert_flash_bank(BOOT_FROM_UPPER_BANK);
+	else if (strcmp(argv[1], "1") == 0)
+		convert_flash_bank(BOOT_FROM_LOWER_BANK);
+	else
+		return CMD_RET_USAGE;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	boot_bank, 2, 0, flash_bank_cmd,
+	"Flash bank Selection Control",
+	"bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
+);
+
+static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	if (argc > 2)
+		return CMD_RET_USAGE;
+	if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
+		cpld_data->system_rst = CFG_RESET;
+	else if (strcmp(argv[1], "init") == 0)
+		cpld_data->global_rst = INIT_RESET;
+	else
+		return CMD_RET_USAGE;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	cpld_reset, 2, 0, cpld_reset_cmd,
+	"Reset via CPLD",
+	"conf\n"
+	"	-reset with current CPLD configuration\n"
+	"init\n"
+	"	-reset and initial CPLD configuration with default value"
+
+);
+
+static void print_serdes_mux(void)
+{
+	char current_serdes;
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	current_serdes = cpld_data->serdes_mux;
+
+	printf("Serdes Lane B: ");
+	if ((current_serdes & MASK_LANE_B) == 0)
+		printf("SATA,\n");
+	else
+		printf("SGMII 1,\n");
+
+	printf("Serdes Lane C: ");
+	if ((current_serdes & MASK_LANE_C) == 0)
+		printf("SGMII 1,\n");
+	else
+		printf("PCIe,\n");
+
+	printf("Serdes Lane D: ");
+	if ((current_serdes & MASK_LANE_D) == 0)
+		printf("PCIe,\n");
+	else
+		printf("SGMII 2,\n");
+
+	printf("SGMII 1 is on lane ");
+	if ((current_serdes & MASK_SGMII) == 0)
+		printf("C.\n");
+	else
+		printf("B.\n");
+}
+
+static int serdes_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;
+	if (strcmp(argv[1], "sata") == 0) {
+		printf("Set serdes lane B to SATA.\n");
+		convert_serdes_mux(LANEB_SATA, NEED_RESET);
+	} else if (strcmp(argv[1], "sgmii1b") == 0) {
+		printf("Set serdes lane B to SGMII 1.\n");
+		convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
+	} else if (strcmp(argv[1], "sgmii1c") == 0) {
+		printf("Set serdes lane C to SGMII 1.\n");
+		convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
+	} else if (strcmp(argv[1], "sgmii2") == 0) {
+		printf("Set serdes lane D to SGMII 2.\n");
+		convert_serdes_mux(LANED_SGMII2, NEED_RESET);
+	} else if (strcmp(argv[1], "pciex1") == 0) {
+		printf("Set serdes lane C to PCIe X1.\n");
+		convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
+	} else if (strcmp(argv[1], "pciex2") == 0) {
+		printf("Set serdes lane C & lane D to PCIe X2.\n");
+		convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
+	} else if (strcmp(argv[1], "show") == 0) {
+		print_serdes_mux();
+	} else {
+		return CMD_RET_USAGE;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	lane_bank, 2, 0, serdes_mux_cmd,
+	"Multiplexed function setting for SerDes Lanes",
+	"sata\n"
+	"	-change lane B to sata\n"
+	"lane_bank sgmii1b\n"
+	"	-change lane B to SGMII1\n"
+	"lane_bank sgmii1c\n"
+	"	-change lane C to SGMII1\n"
+	"lane_bank sgmii2\n"
+	"	-change lane D to SGMII2\n"
+	"lane_bank pciex1\n"
+	"	-change lane C to PCIeX1\n"
+	"lane_bank pciex2\n"
+	"	-change lane C & lane D to PCIeX2\n"
+	"\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
+);
+#endif
diff --git a/roms/u-boot/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/roms/u-boot/board/freescale/ls1021atwr/ls102xa_pbi.cfg
new file mode 100644
index 000000000..f1a1b63ab
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atwr/ls102xa_pbi.cfg
@@ -0,0 +1,12 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
diff --git a/roms/u-boot/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg b/roms/u-boot/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
new file mode 100644
index 000000000..f94997d53
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+0608000c 00000000 00000000 00000000
+30000000 00007900 60040a00 21046000
+00000000 00000000 00000000 20000000
+00080000 881b7340 00000000 00000000
diff --git a/roms/u-boot/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg b/roms/u-boot/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
new file mode 100644
index 000000000..541b604cf
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#disable IFC, enable QSPI and DSPI
+0608000c 00000000 00000000 00000000
+30000000 00007900 60040a00 21046000
+00000000 00000000 00000000 20000000
+20024800 881b7340 00000000 00000000
diff --git a/roms/u-boot/board/freescale/ls1021atwr/psci.S b/roms/u-boot/board/freescale/ls1021atwr/psci.S
new file mode 100644
index 000000000..3c093aa33
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1021atwr/psci.S
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 NXP Semiconductor.
+ * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+	.align	5
+
+.globl	psci_system_off
+psci_system_off:
+1:	wfi
+	b	1b
+
+	.popsection
diff --git a/roms/u-boot/board/freescale/ls1028a/Kconfig b/roms/u-boot/board/freescale/ls1028a/Kconfig
new file mode 100644
index 000000000..ca22c9220
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1028a/Kconfig
@@ -0,0 +1,65 @@
+if TARGET_LS1028AQDS
+
+config SYS_BOARD
+	default "ls1028a"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1028aqds"
+
+config EMMC_BOOT
+	bool "Support for booting from EMMC"
+	default n
+
+config SYS_TEXT_BASE
+	default 0x96000000 if SD_BOOT || EMMC_BOOT
+	default 0x82000000 if TFABOOT
+	default 0x20100000
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+	hex "PPA Firmware Addr"
+	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA header Addr"
+	default 0x20600000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
+
+if TARGET_LS1028ARDB
+
+config SYS_BOARD
+	default "ls1028a"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1028ardb"
+
+config EMMC_BOOT
+	bool "Support for booting from EMMC"
+	default n
+
+config SYS_TEXT_BASE
+	default 0x96000000 if SD_BOOT || EMMC_BOOT
+	default 0x82000000 if TFABOOT
+	default 0x20100000
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/ls1028a/MAINTAINERS b/roms/u-boot/board/freescale/ls1028a/MAINTAINERS
new file mode 100644
index 000000000..9e7b0697f
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1028a/MAINTAINERS
@@ -0,0 +1,28 @@
+LS1028AQDS BOARD
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M:	Tang Yuantian <andy.tang@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1028a/
+F:	include/configs/ls1028a_common.h
+F:	include/configs/ls1028aqds.h
+F:	configs/ls1028aqds_tfa_defconfig
+F:	configs/ls1028aqds_tfa_lpuart_defconfig
+
+LS1028ARDB BOARD
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M:	Tang Yuantian <andy.tang@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1028a/
+F:	include/configs/ls1028a_common.h
+F:	include/configs/ls1028ardb.h
+F:	configs/ls1028ardb_tfa_defconfig
+
+LS1028AQDS_SECURE_BOOT BOARD
+M:	Tang Yuantian <andy.tang@nxp.com>
+S:	Maintained
+F:	configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+
+LS1028ARDB_SECURE_BOOT BOARD
+M:	Tang Yuantian <andy.tang@nxp.com>
+S:	Maintained
+F:	configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/ls1028a/Makefile b/roms/u-boot/board/freescale/ls1028a/Makefile
new file mode 100644
index 000000000..9bc144cbf
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1028a/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2019 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ls1028a.o
+obj-y += ddr.o
diff --git a/roms/u-boot/board/freescale/ls1028a/README b/roms/u-boot/board/freescale/ls1028a/README
new file mode 100644
index 000000000..323881faa
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1028a/README
@@ -0,0 +1,164 @@
+Overview
+--------
+The LS1028A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports ARM SoC LS1028A and its
+derivatives.
+
+LS1028A SoC Overview
+--------------------------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+
+RDB Default Switch Settings (1: ON; 0: OFF)
+-------------------------------------------
+For XSPI NOR boot (default)
+SW2: 1111_1000
+SW3: 1111_0000
+SW5: 0011_1001
+
+For SD Boot
+SW2: 1000_1000
+SW3: 1111_0000
+SW5: 0011_1001
+
+For eMMC Boot
+SW2: 1001_1000
+SW3: 1111_0000
+SW5: 0011_1001
+
+LS1028ARDB board Overview
+-------------------------
+Processor
+ Two Arm Cortex- A72 processor cores:
+  - Based on 64-bit ARMv8 architecture
+  - Up to 1.3 GHz operation
+  - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
+    data cache
+  - Arranged as a single cluster of two cores sharing a single 1 MB L2
+    cache
+DDR memory
+  - Five onboard 1G x8 discrete memory modules (Four data byte lanes
+    ECC)
+  - 32-bit data and 4-bit ECC
+  - One chip select
+  - Data transfer rates of up to 1.6 GT/s
+  - Single-bit error correction and double-bit error detection ECC (4-bit
+    check word across 32-bit data)
+High-speed serial ports(SerDes)
+ - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
+   Qualcomm AR8033 PHY
+ - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
+   through the NXP F104S8A PHY
+ - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
+   (8 Gbit/s) cards
+ - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
+   slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or
+   SATA Gen 3 cards (6 Gbit/s) at a time
+eSDHC
+ - eSDHC1, eSDHC2
+SPI
+ - Connects to two mikroBUS sockets to support mikro-click modules,
+   such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near
+   field communications (NFC) controller
+Octal SPI (XSPI)
+ - One 256 MB onboard XSPI serial NOR flash memory
+ - One 512 MB onboard XSPI serial NAND flash memory
+ - Supports a QSPI emulator for offboard QSPI emulation
+I2C
+ - All system devices are accessed via I2C1, which is multiplexed on
+   I2C multiplexer PCA9848 to isolate address conflicts and reduce
+   capacitive load
+ - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
+   thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules
+   1 and 2
+CAN
+ - The two CAN DB9 ports can support CAN FD fast phase at data rates of
+   up to 5 Mbit/s
+Serial audio interface(SAI)
+ - Audio codec SGTL5000 provides headphone and audio LINEOUT for
+   stereo speakers
+ - IEEE1588 interface to support audio on SAI4
+
+QDS Default Switch Settings (1: ON; 0: OFF)
+-------------------------------------------
+For SD Boot
+SW1 : 1000_0000
+SW2 : 1110_0110
+SW3 : 0000_0010
+SW4 : 0000_0000
+SW5 : 0000_0000
+SW6 : 0000_0000
+SW7 : 1111_0011
+SW8 : 1110_0000
+SW9 : 1000_0001
+SW10: 1110_0000
+
+For XSPI Boot
+SW1 : 1111_0000
+SW2 : 0000_0110
+SW3 : 0000_0010
+SW4 : 0000_0000
+SW5 : 0110_0000
+SW6 : 0101_0000
+SW7 : 1111_0011
+SW8 : 1110_0000
+SW9 : 1000_0000
+SW10: 1110_0000
+
+LS1028AQDS board Overview
+-------------------------
+Processor
+ Two Arm Cortex- A72 processor cores:
+  - Based on 64-bit ARMv8 architecture
+  - Up to 1.3 GHz operation
+  - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
+    data cache
+  - Arranged as a single cluster of two cores sharing a single 1 MB L2
+    cache
+DDR memory
+ - Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L
+ - Supports a single- or dual-ranked SODIMM or UDIMM connector
+ - 32-bit data and 4-bit ECC
+ - Supports x8/x16 devices
+ - Supports ECC error detection and correction
+ - 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to
+   all devices in case of DDR3L or DDR4, respectively. Power can
+   switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or
+   DDR4 devices, respectively
+SerDes (Serializer/Deserializer)
+ - Four-lane (0-3) SerDes:
+ - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10
+   Gbit SXGMII, 1 Gbit SGMII
+ - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
+   SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII
+ - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
+   SGMII
+ - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
+   SGMII, SATA 2.0/3.0
+ - Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII
+   add-in cards
+ - Lane 1 connects to a 2x10 connector with SFP+ through a retimer;
+   lane 2 (TX lines) connects to an SMA connector
+   Lane 3 connects to 1x7 header to support SATA devices
+eSDHC
+ - eSDHC1, eSDHC2
+SPI
+ - SPI1 and SPI2 support three onboard SPI flash memory devices:
+    512 Mbit high-speed flash (with speed of up to 108/54 MHz)
+    memory for storage
+    4 Mbit low-speed flash memory (with speed of up to 40 MHz)
+    64 Mbit high-speed flash memory (with speed of up to 104/80
+    MHz)
+ - SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of
+   up to 104/80 MHz)
+ - All memories operate at 1.8 V
+ - A header is provided on SPI1 to test SPI slave mode
+I2C
+ - LS1028A supports eight I2C controllers
+Serial audio interface(SAI)
+ Two SAI ports with audio codec SGTL5000:
+  - Include stereo LINEIN with support for external analog input
+  - Provide headphone and line output
+Display
+ - DisplayPort connector to connect the DP data to a 4K display device
+   (computer monitor)
+ - eDP connector to connect the DP data to a 4K display panel
diff --git a/roms/u-boot/board/freescale/ls1028a/ddr.c b/roms/u-boot/board/freescale/ls1028a/ddr.c
new file mode 100644
index 000000000..3e976da6b
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1028a/ddr.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/ls1028a/ls1028a.c b/roms/u-boot/board/freescale/ls1028a/ls1028a.c
new file mode 100644
index 000000000..5269fd34c
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1028a/ls1028a.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fsl_ddr.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <hwconfig.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <env_internal.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <i2c.h>
+#include <asm/arch/soc.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
+#include <fsl_immap.h>
+#include <netdev.h>
+
+#include <fdtdec.h>
+#include <miiphy.h>
+#include "../common/qixis.h"
+#include "../drivers/net/fsl_enetc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int config_board_mux(void)
+{
+#ifndef CONFIG_LPUART
+#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
+	u8 reg;
+
+	reg = QIXIS_READ(brdcfg[13]);
+	/* Field| Function
+	 * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
+	 * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
+	 * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
+	 * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
+	 */
+	reg &= ~(0xf0);
+	reg |= 0xb0;
+	QIXIS_WRITE(brdcfg[13], reg);
+
+	reg = QIXIS_READ(brdcfg[15]);
+	/* Field| Function
+	 * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
+	 * CAN1 | 0= CAN #1 transceiver enabled
+	 * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
+	 * CAN2 | 0= CAN #2 transceiver enabled
+	 */
+	reg &= ~(0xc0);
+	QIXIS_WRITE(brdcfg[15], reg);
+#endif
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
+{
+	return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+#ifndef CONFIG_SYS_EARLY_PCI_INIT
+	pci_init();
+#endif
+
+#if defined(CONFIG_TARGET_LS1028ARDB)
+	u8 val = I2C_MUX_CH_DEFAULT;
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
+#else
+	struct udevice *dev;
+
+	if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
+		dm_i2c_write(dev, 0x0b, &val, 1);
+#endif
+#endif
+
+#if defined(CONFIG_TARGET_LS1028ARDB)
+	u8 reg;
+
+	reg = QIXIS_READ(brdcfg[4]);
+	/*
+	 * Field | Function
+	 * 3     | DisplayPort Power Enable (net DP_PWR_EN):
+	 * DPPWR | 0= DP_PWR is enabled.
+	 */
+	reg &= ~(DP_PWD_EN_DEFAULT_MASK);
+	QIXIS_WRITE(brdcfg[4], reg);
+#endif
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	config_board_mux();
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_LPUART
+	u8 uart;
+#endif
+
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
+
+	fsl_lsch3_early_init_f();
+
+#ifdef CONFIG_LPUART
+	/*
+	 * Field| Function
+	 * --------------------------------------------------------------
+	 * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
+	 * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
+	 * --------------------------------------------------------------
+	 * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
+	 * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
+	 */
+	/* use lpuart0 as system console */
+	uart = QIXIS_READ(brdcfg[13]);
+	uart &= ~CFG_LPUART_MUX_MASK;
+	uart |= CFG_LPUART_EN;
+	QIXIS_WRITE(brdcfg[13], uart);
+#endif
+
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_ddr_info(0);
+}
+
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+	void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
+	char esdhc1_path[] = "/soc/mmc@2140000";
+	char esdhc2_path[] = "/soc/mmc@2150000";
+	char dspi1_path[] = "/soc/spi@2100000";
+	char dspi2_path[] = "/soc/spi@2110000";
+	u32 mux_sdhc1, mux_sdhc2;
+	u32 io = 0;
+
+	/*
+	 * The PMUX IO-expander for mux select is used to control
+	 * the muxing of various onboard interfaces.
+	 */
+
+	io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
+	mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
+
+	/* Disable esdhc1/dspi1 if not selected. */
+	if (mux_sdhc1 != 0)
+		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+				 sizeof("disabled"), 1);
+	if (mux_sdhc1 != 2)
+		do_fixup_by_path(blob, dspi1_path, "status", "disabled",
+				 sizeof("disabled"), 1);
+
+	io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
+	mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
+
+	/* Disable esdhc2/dspi2 if not selected. */
+	if (mux_sdhc2 != 0)
+		do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
+				 sizeof("disabled"), 1);
+	if (mux_sdhc2 != 2)
+		do_fixup_by_path(blob, dspi2_path, "status", "disabled",
+				 sizeof("disabled"), 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	ft_cpu_setup(blob, bd);
+
+	/* fixup DT for the two GPP DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+#ifdef CONFIG_RESV_RAM
+	/* reduce size if reserved memory is within this bank */
+	if (gd->arch.resv_ram >= base[0] &&
+	    gd->arch.resv_ram < base[0] + size[0])
+		size[0] = gd->arch.resv_ram - base[0];
+	else if (gd->arch.resv_ram >= base[1] &&
+		 gd->arch.resv_ram < base[1] + size[1])
+		size[1] = gd->arch.resv_ram - base[1];
+#endif
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
+
+	fdt_fixup_icid(blob);
+
+#ifdef CONFIG_FSL_ENETC
+	fdt_fixup_enetc_mac(blob);
+#endif
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_QIXIS
+int checkboard(void)
+{
+#ifdef CONFIG_TFABOOT
+	enum boot_src src = get_boot_src();
+#endif
+	u8 sw;
+
+	int clock;
+	char *board;
+	char buf[64] = {0};
+	static const char *freq[6] = {"100.00", "125.00", "156.25",
+					"161.13", "322.26", "100.00 SS"};
+
+	cpu_name(buf);
+	/* find the board details */
+	sw = QIXIS_READ(id);
+
+	switch (sw) {
+	case 0x46:
+		board = "QDS";
+		break;
+	case 0x47:
+		board = "RDB";
+		break;
+	case 0x49:
+		board = "HSSI";
+		break;
+	default:
+		board = "unknown";
+		break;
+	}
+
+	sw = QIXIS_READ(arch);
+	printf("Board: %s-%s, Version: %c, boot from ",
+	       buf, board, (sw & 0xf) + 'A' - 1);
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+#ifdef CONFIG_TFABOOT
+	if (src == BOOT_SOURCE_SD_MMC) {
+		puts("SD\n");
+	} else if (src == BOOT_SOURCE_SD_MMC2) {
+		puts("eMMC\n");
+	} else {
+#endif
+#ifdef CONFIG_SD_BOOT
+		puts("SD\n");
+#elif defined(CONFIG_EMMC_BOOT)
+		puts("eMMC\n");
+#else
+		switch (sw) {
+		case 0:
+		case 4:
+			printf("NOR\n");
+			break;
+		case 1:
+			printf("NAND\n");
+			break;
+		default:
+			printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+			break;
+		}
+#endif
+#ifdef CONFIG_TFABOOT
+	}
+#endif
+
+	printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
+	puts("SERDES1 Reference : ");
+
+	sw = QIXIS_READ(brdcfg[2]);
+#ifdef CONFIG_TARGET_LS1028ARDB
+	clock = (sw >> 6) & 3;
+#else
+	clock = (sw >> 4) & 0xf;
+#endif
+
+	printf("Clock1 = %sMHz ", freq[clock]);
+#ifdef CONFIG_TARGET_LS1028ARDB
+	clock = (sw >> 4) & 3;
+#else
+	clock = sw & 0xf;
+#endif
+	printf("Clock2 = %sMHz\n", freq[clock]);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/ls1043aqds/Kconfig b/roms/u-boot/board/freescale/ls1043aqds/Kconfig
new file mode 100644
index 000000000..182900efb
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/Kconfig
@@ -0,0 +1,33 @@
+if TARGET_LS1043AQDS
+
+config SYS_BOARD
+	default "ls1043aqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1043aqds"
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+	hex "PPA Firmware Addr"
+	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA Firmware HDR Addr"
+	default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x60680000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/ls1043aqds/MAINTAINERS b/roms/u-boot/board/freescale/ls1043aqds/MAINTAINERS
new file mode 100644
index 000000000..9fb6cc85c
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/MAINTAINERS
@@ -0,0 +1,15 @@
+LS1043AQDS BOARD
+M:	Mingkai Hu <mingkai.hu@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1043aqds/
+F:	include/configs/ls1043aqds.h
+F:	configs/ls1043aqds_defconfig
+F:	configs/ls1043aqds_nor_ddr3_defconfig
+F:	configs/ls1043aqds_nand_defconfig
+F:	configs/ls1043aqds_sdcard_ifc_defconfig
+F:	configs/ls1043aqds_sdcard_qspi_defconfig
+F:	configs/ls1043aqds_qspi_defconfig
+F:	configs/ls1043aqds_lpuart_defconfig
+F:	configs/ls1043aqds_tfa_defconfig
+F:	configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/ls1043aqds/Makefile b/roms/u-boot/board/freescale/ls1043aqds/Makefile
new file mode 100644
index 000000000..49d8d7d9b
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ddr.o
+ifndef CONFIG_SPL_BUILD
+obj-y += eth.o
+endif
+obj-y += ls1043aqds.o
diff --git a/roms/u-boot/board/freescale/ls1043aqds/README b/roms/u-boot/board/freescale/ls1043aqds/README
new file mode 100644
index 000000000..913537d45
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/README
@@ -0,0 +1,64 @@
+Overview
+--------
+The LS1043A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1043A
+LayerScape Architecture processor. The LS1043AQDS provides SW development
+platform for the Freescale LS1043A processor series, with a complete
+debugging environment.
+
+LS1043A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
+
+ LS1043AQDS board Overview
+ -----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - QSGMII
+      - SATA 3.0
+      - XFI
+ - DDR Controller
+     - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
+ -IFC/Local Bus
+    - One in-socket 128 MB NOR flash 16-bit data bus
+    - One 512 MB NAND flash with ECC support
+    - PromJet Port
+    - FPGA connection
+ - USB 3.0
+    - Three high speed USB 3.0 ports
+    - First USB 3.0 port configured as Host with Type-A connector
+    - The other two USB 3.0 ports configured as OTG with micro-AB connector
+ - SDHC port connects directly to an adapter card slot, featuring:
+    - Optional clock feedback paths, and optional high-speed voltage translation assistance
+    - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC
+    - eMMC memory devices
+ - DSPI: Onboard support for three SPI flash memory devices
+ - 4 I2C controllers
+ - One SATA onboard connectors
+ - UART
+   - Two 4-pin serial ports at up to 115.2 Kbit/s
+   - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address	End Address	Description		Size
+0x00_0000_0000	0x00_000F_FFFF	Secure Boot ROM		1MB
+0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR			240MB
+0x00_1000_0000	0x00_1000_FFFF	OCRAM0			64KB
+0x00_1001_0000	0x00_1001_FFFF	OCRAM1			64KB
+0x00_2000_0000	0x00_20FF_FFFF	DCSR			16MB
+0x00_6000_0000	0x00_67FF_FFFF	IFC - NOR Flash		128MB
+0x00_7E80_0000	0x00_7E80_FFFF	IFC - NAND Flash	64KB
+0x00_7FB0_0000	0x00_7FB0_0FFF	IFC - FPGA		4KB
+0x00_8000_0000	0x00_FFFF_FFFF	DRAM1			2GB
+
+Booting Options
+---------------
+a) Promjet Boot
+b) NOR boot
+c) NAND boot
+d) SD boot
+e) QSPI boot
diff --git a/roms/u-boot/board/freescale/ls1043aqds/ddr.c b/roms/u-boot/board/freescale/ls1043aqds/ddr.c
new file mode 100644
index 000000000..23947bdb8
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/ddr.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
+#include <log.h>
+#include <asm/arch/clock.h>
+#include <asm/global_data.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 3) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				popts->cpo_override = pbsp->cpo_override;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for %lu MT/s\n",
+		       ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+	/* force DDR bus width to 32 bits */
+	popts->data_bus_width = 1;
+	popts->otf_burst_chop_en = 0;
+	popts->burst_length = DDR_BL8;
+	popts->bstopre = 0;		/* enable auto precharge */
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 1;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x59;
+#else
+	popts->cswl_override = DDR_CSWL_CS0;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
+#else
+int fsl_initdram(void)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+#else
+	puts("Initializing DDR....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+#endif
+	erratum_a008850_post();
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	fsl_dp_ddr_restore();
+#endif
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/ls1043aqds/ddr.h b/roms/u-boot/board/freescale/ls1043aqds/ddr.h
new file mode 100644
index 000000000..65b0250d3
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/ddr.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+extern void erratum_a008850_post(void);
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+	u32 cpo_override;
+	u32 write_data_delay;
+	u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	{2,  1666, 0,  8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0,  8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0,  8,     6, 0x0708090B, 0x0C0D0E0A,},
+	{1,  1900, 0,  8,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+	{1,  2200, 0,  8,    10, 0x0B0C0D0C, 0x0E0F110E,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+	{1,  833,  1, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 1, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{1,  833,  2, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 2, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  833,  4, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{2,  1350, 4, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1350, 0, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1666, 4,  8,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{2,  1666, 0,  8,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+#else
+#error DDR type not defined
+#endif
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls1043aqds/eth.c b/roms/u-boot/board/freescale/ls1043aqds/eth.c
new file mode 100644
index 000000000..c3efe8a0b
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/eth.c
@@ -0,0 +1,499 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <log.h>
+#include <net.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fdt_support.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <fsl_dtsec.h>
+#include <linux/libfdt.h>
+#include <malloc.h>
+#include <asm/arch/fsl_serdes.h>
+
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "ls1043aqds_qixis.h"
+
+#define EMI_NONE	0xFF
+#define EMI1_RGMII1	0
+#define EMI1_RGMII2	1
+#define EMI1_SLOT1	2
+#define EMI1_SLOT2	3
+#define EMI1_SLOT3	4
+#define EMI1_SLOT4	5
+#define EMI2		6
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+	"LS1043AQDS_MDIO_RGMII1",
+	"LS1043AQDS_MDIO_RGMII2",
+	"LS1043AQDS_MDIO_SLOT1",
+	"LS1043AQDS_MDIO_SLOT2",
+	"LS1043AQDS_MDIO_SLOT3",
+	"LS1043AQDS_MDIO_SLOT4",
+	"NULL",
+};
+
+/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
+static u8 lane_to_slot[] = {1, 2, 3, 4};
+
+static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+	struct mii_dev *bus;
+	const char *name;
+
+	if (muxval > EMI2)
+		return NULL;
+
+	name = ls1043aqds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+struct ls1043aqds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+static void ls1043aqds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+
+	if (muxval < 7) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+			      int regnum)
+{
+	struct ls1043aqds_mdio *priv = bus->priv;
+
+	ls1043aqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+			       int regnum, u16 value)
+{
+	struct ls1043aqds_mdio *priv = bus->priv;
+
+	ls1043aqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad,
+				    regnum, value);
+}
+
+static int ls1043aqds_mdio_reset(struct mii_dev *bus)
+{
+	struct ls1043aqds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct ls1043aqds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate ls1043aqds MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate ls1043aqds private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = ls1043aqds_mdio_read;
+	bus->write = ls1043aqds_mdio_write;
+	bus->reset = ls1043aqds_mdio_reset;
+	strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+	return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+			      enum fm_port port, int offset)
+{
+	struct fixed_link f_link;
+
+	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+		if (port == FM1_DTSEC9) {
+			fdt_set_phy_handle(fdt, compat, addr,
+					   "sgmii-riser-s1-p1");
+		} else if (port == FM1_DTSEC2) {
+			fdt_set_phy_handle(fdt, compat, addr,
+					   "sgmii-riser-s2-p1");
+		} else if (port == FM1_DTSEC5) {
+			fdt_set_phy_handle(fdt, compat, addr,
+					   "sgmii-riser-s3-p1");
+		} else if (port == FM1_DTSEC6) {
+			fdt_set_phy_handle(fdt, compat, addr,
+					   "sgmii-riser-s4-p1");
+		}
+	} else if (fm_info_get_enet_if(port) ==
+		   PHY_INTERFACE_MODE_SGMII_2500) {
+		/* 2.5G SGMII interface */
+		f_link.phy_id = cpu_to_fdt32(port);
+		f_link.duplex = cpu_to_fdt32(1);
+		f_link.link_speed = cpu_to_fdt32(1000);
+		f_link.pause = 0;
+		f_link.asym_pause = 0;
+		/* no PHY for 2.5G SGMII */
+		fdt_delprop(fdt, offset, "phy-handle");
+		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+		fdt_setprop_string(fdt, offset, "phy-connection-type",
+				   "sgmii-2500");
+	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
+		switch (mdio_mux[port]) {
+		case EMI1_SLOT1:
+			switch (port) {
+			case FM1_DTSEC1:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii-s1-p1");
+				break;
+			case FM1_DTSEC2:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii-s1-p2");
+				break;
+			case FM1_DTSEC5:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii-s1-p3");
+				break;
+			case FM1_DTSEC6:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii-s1-p4");
+				break;
+			default:
+				break;
+			}
+			break;
+		case EMI1_SLOT2:
+			switch (port) {
+			case FM1_DTSEC1:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii-s2-p1");
+				break;
+			case FM1_DTSEC2:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii-s2-p2");
+				break;
+			case FM1_DTSEC5:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii-s2-p3");
+				break;
+			case FM1_DTSEC6:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii-s2-p4");
+				break;
+			default:
+				break;
+			}
+			break;
+		default:
+			break;
+		}
+		fdt_delprop(fdt, offset, "phy-connection-type");
+		fdt_setprop_string(fdt, offset, "phy-connection-type",
+				   "qsgmii");
+	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
+		   port == FM1_10GEC1) {
+		/* XFI interface */
+		f_link.phy_id = cpu_to_fdt32(port);
+		f_link.duplex = cpu_to_fdt32(1);
+		f_link.link_speed = cpu_to_fdt32(10000);
+		f_link.pause = 0;
+		f_link.asym_pause = 0;
+		/* no PHY for XFI */
+		fdt_delprop(fdt, offset, "phy-handle");
+		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+		fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
+	}
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	int i;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+		case PHY_INTERFACE_MODE_QSGMII:
+			switch (mdio_mux[i]) {
+			case EMI1_SLOT1:
+				fdt_status_okay_by_alias(fdt, "emi1-slot1");
+				break;
+			case EMI1_SLOT2:
+				fdt_status_okay_by_alias(fdt, "emi1-slot2");
+				break;
+			case EMI1_SLOT3:
+				fdt_status_okay_by_alias(fdt, "emi1-slot3");
+				break;
+			case EMI1_SLOT4:
+				fdt_status_okay_by_alias(fdt, "emi1-slot4");
+				break;
+			default:
+				break;
+			}
+			break;
+		case PHY_INTERFACE_MODE_XGMII:
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	int i, idx, lane, slot, interface;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	/* Initialize the mdio_mux array so we can recognize empty elements */
+	for (i = 0; i < NUM_FM_PORTS; i++)
+		mdio_mux[i] = EMI_NONE;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	/* Register the muxing front-ends to the MDIO buses */
+	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+	ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+	/* Set the two on-board RGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+	switch (srds_s1) {
+	case 0x2555:
+		/* 2.5G SGMII on lane A, MAC 9 */
+		fm_info_set_phy_address(FM1_DTSEC9, 9);
+		break;
+	case 0x4555:
+	case 0x4558:
+		/* QSGMII on lane A, MAC 1/2/5/6 */
+		fm_info_set_phy_address(FM1_DTSEC1,
+					QSGMII_CARD_PORT1_PHY_ADDR_S1);
+		fm_info_set_phy_address(FM1_DTSEC2,
+					QSGMII_CARD_PORT2_PHY_ADDR_S1);
+		fm_info_set_phy_address(FM1_DTSEC5,
+					QSGMII_CARD_PORT3_PHY_ADDR_S1);
+		fm_info_set_phy_address(FM1_DTSEC6,
+					QSGMII_CARD_PORT4_PHY_ADDR_S1);
+		break;
+	case 0x1355:
+		/* SGMII on lane B, MAC 2*/
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+		break;
+	case 0x2355:
+		/* 2.5G SGMII on lane A, MAC 9 */
+		fm_info_set_phy_address(FM1_DTSEC9, 9);
+		/* SGMII on lane B, MAC 2*/
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+		break;
+	case 0x3335:
+		/* SGMII on lane C, MAC 5 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+	case 0x3355:
+	case 0x3358:
+		/* SGMII on lane B, MAC 2 */
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+	case 0x3555:
+	case 0x3558:
+		/* SGMII on lane A, MAC 9 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+		break;
+	case 0x1455:
+		/* QSGMII on lane B, MAC 1/2/5/6 */
+		fm_info_set_phy_address(FM1_DTSEC1,
+					QSGMII_CARD_PORT1_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC2,
+					QSGMII_CARD_PORT2_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC5,
+					QSGMII_CARD_PORT3_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC6,
+					QSGMII_CARD_PORT4_PHY_ADDR_S2);
+		break;
+	case 0x2455:
+		/* 2.5G SGMII on lane A, MAC 9 */
+		fm_info_set_phy_address(FM1_DTSEC9, 9);
+		/* QSGMII on lane B, MAC 1/2/5/6 */
+		fm_info_set_phy_address(FM1_DTSEC1,
+					QSGMII_CARD_PORT1_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC2,
+					QSGMII_CARD_PORT2_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC5,
+					QSGMII_CARD_PORT3_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC6,
+					QSGMII_CARD_PORT4_PHY_ADDR_S2);
+		break;
+	case 0x2255:
+		/* 2.5G SGMII on lane A, MAC 9 */
+		fm_info_set_phy_address(FM1_DTSEC9, 9);
+		/* 2.5G SGMII on lane B, MAC 2 */
+		fm_info_set_phy_address(FM1_DTSEC2, 2);
+		break;
+	case 0x3333:
+		/* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
+		fm_info_set_phy_address(FM1_DTSEC9,
+					SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2,
+					SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC5,
+					SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6,
+					SGMII_CARD_PORT1_PHY_ADDR);
+		break;
+	default:
+		printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
+		       srds_s1);
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		idx = i - FM1_DTSEC1;
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_SGMII:
+		case PHY_INTERFACE_MODE_SGMII_2500:
+		case PHY_INTERFACE_MODE_QSGMII:
+			if (interface == PHY_INTERFACE_MODE_SGMII) {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						SGMII_FM1_DTSEC1 + idx);
+			} else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						SGMII_2500_FM1_DTSEC1 + idx);
+			} else {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						QSGMII_FM1_A);
+			}
+
+			if (lane < 0)
+				break;
+
+			slot = lane_to_slot[lane];
+			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+			      idx + 1, slot);
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
+
+			switch (slot) {
+			case 1:
+				mdio_mux[i] = EMI1_SLOT1;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 2:
+				mdio_mux[i] = EMI1_SLOT2;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 3:
+				mdio_mux[i] = EMI1_SLOT3;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 4:
+				mdio_mux[i] = EMI1_SLOT4;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			default:
+				break;
+			}
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			if (i == FM1_DTSEC3)
+				mdio_mux[i] = EMI1_RGMII1;
+			else if (i == FM1_DTSEC4)
+				mdio_mux[i] = EMI1_RGMII2;
+			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+			break;
+		default:
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds.c b/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds.c
new file mode 100644
index 000000000..5b131d1d6
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds.c
@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <fsl_ddr_sdram.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ppa.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include <spl.h>
+
+#include "../common/qixis.h"
+#include "ls1043aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	MUX_TYPE_GPIO,
+};
+
+/* LS1043AQDS serdes mux */
+#define CFG_SD_MUX1_SLOT2	0x0 /* SLOT2 TX/RX0 */
+#define CFG_SD_MUX1_SLOT1	0x1 /* SLOT1 TX/RX1 */
+#define CFG_SD_MUX2_SLOT3	0x0 /* SLOT3 TX/RX0 */
+#define CFG_SD_MUX2_SLOT1	0x1 /* SLOT1 TX/RX2 */
+#define CFG_SD_MUX3_SLOT4	0x0 /* SLOT4 TX/RX0 */
+#define CFG_SD_MUX3_MUX4	0x1 /* MUX4 */
+#define CFG_SD_MUX4_SLOT3	0x0 /* SLOT3 TX/RX1 */
+#define CFG_SD_MUX4_SLOT1	0x1 /* SLOT1 TX/RX3 */
+#define CFG_UART_MUX_MASK	0x6
+#define CFG_UART_MUX_SHIFT	1
+#define CFG_LPUART_EN		0x1
+
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
+
+#ifdef CONFIG_TFABOOT
+struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"nor0",
+		CONFIG_SYS_NOR0_CSPR,
+		CONFIG_SYS_NOR0_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+
+	},
+	{
+		"nor1",
+		CONFIG_SYS_NOR1_CSPR,
+		CONFIG_SYS_NOR1_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+	},
+	{
+		"nand",
+		CONFIG_SYS_NAND_CSPR,
+		CONFIG_SYS_NAND_CSPR_EXT,
+		CONFIG_SYS_NAND_AMASK,
+		CONFIG_SYS_NAND_CSOR,
+		{
+			CONFIG_SYS_NAND_FTIM0,
+			CONFIG_SYS_NAND_FTIM1,
+			CONFIG_SYS_NAND_FTIM2,
+			CONFIG_SYS_NAND_FTIM3
+		},
+	},
+	{
+		"fpga",
+		CONFIG_SYS_FPGA_CSPR,
+		CONFIG_SYS_FPGA_CSPR_EXT,
+		CONFIG_SYS_FPGA_AMASK,
+		CONFIG_SYS_FPGA_CSOR,
+		{
+			CONFIG_SYS_FPGA_FTIM0,
+			CONFIG_SYS_FPGA_FTIM1,
+			CONFIG_SYS_FPGA_FTIM2,
+			CONFIG_SYS_FPGA_FTIM3
+		},
+	}
+};
+
+struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"nand",
+		CONFIG_SYS_NAND_CSPR,
+		CONFIG_SYS_NAND_CSPR_EXT,
+		CONFIG_SYS_NAND_AMASK,
+		CONFIG_SYS_NAND_CSOR,
+		{
+			CONFIG_SYS_NAND_FTIM0,
+			CONFIG_SYS_NAND_FTIM1,
+			CONFIG_SYS_NAND_FTIM2,
+			CONFIG_SYS_NAND_FTIM3
+		},
+	},
+	{
+		"nor0",
+		CONFIG_SYS_NOR0_CSPR,
+		CONFIG_SYS_NOR0_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+	},
+	{
+		"nor1",
+		CONFIG_SYS_NOR1_CSPR,
+		CONFIG_SYS_NOR1_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+	},
+	{
+		"fpga",
+		CONFIG_SYS_FPGA_CSPR,
+		CONFIG_SYS_FPGA_CSPR_EXT,
+		CONFIG_SYS_FPGA_AMASK,
+		CONFIG_SYS_FPGA_CSOR,
+		{
+			CONFIG_SYS_FPGA_FTIM0,
+			CONFIG_SYS_FPGA_FTIM1,
+			CONFIG_SYS_FPGA_FTIM2,
+			CONFIG_SYS_FPGA_FTIM3
+		},
+	}
+};
+
+void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
+{
+	enum boot_src src = get_boot_src();
+
+	if (src == BOOT_SOURCE_IFC_NAND)
+		regs_info->regs = ifc_cfg_nand_boot;
+	else
+		regs_info->regs = ifc_cfg_nor_boot;
+	regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
+}
+#endif
+
+int checkboard(void)
+{
+#ifdef CONFIG_TFABOOT
+	enum boot_src src = get_boot_src();
+#endif
+	char buf[64];
+#ifndef CONFIG_SD_BOOT
+	u8 sw;
+#endif
+
+	puts("Board: LS1043AQDS, boot from ");
+
+#ifdef CONFIG_TFABOOT
+	if (src == BOOT_SOURCE_SD_MMC)
+		puts("SD\n");
+	else {
+#endif
+
+#ifdef CONFIG_SD_BOOT
+	puts("SD\n");
+#else
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("PromJet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else if (sw == 0xF)
+		printf("QSPI\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+#ifdef CONFIG_TFABOOT
+	}
+#endif
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
+	       QIXIS_READ(id), QIXIS_READ(arch));
+
+	printf("FPGA:  v%d (%s), build %d\n",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+
+	return 0;
+}
+
+bool if_board_diff_clk(void)
+{
+	u8 diff_conf = QIXIS_READ(brdcfg[11]);
+
+	return diff_conf & 0x40;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0f) {
+	case QIXIS_SYSCLK_64:
+		return 64000000;
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	if (if_board_diff_clk())
+		return get_board_sys_clk();
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+
+	return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
+{
+	int ret;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	/*
+	 * When resuming from deep sleep, the I2C channel may not be
+	 * in the default channel. So, switch to the default channel
+	 * before accessing DDR SPD.
+	 *
+	 * PCA9547 mount on I2C1 bus
+	 */
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
+	fsl_initdram();
+#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
+	defined(CONFIG_SPL_BUILD)
+	/* This will break-before-make MMU for DDR */
+	update_early_mmu_table();
+#endif
+
+	return 0;
+}
+
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+	return select_i2c_ch_pca9547(channel, 0);
+}
+
+void board_retimer_init(void)
+{
+	u8 reg;
+	int bus_num = 0;
+
+	/* Retimer is connected to I2C1_CH7_CH5 */
+	select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
+	reg = I2C_MUX_CH5;
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return;
+	}
+	dm_i2c_write(dev, 0, &reg, 1);
+
+	/* Access to Control/Shared register */
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return;
+	}
+
+	reg = 0x0;
+	dm_i2c_write(dev, 0xff, &reg, 1);
+
+	/* Read device revision and ID */
+	dm_i2c_read(dev, 1, &reg, 1);
+	debug("Retimer version id = 0x%x\n", reg);
+
+	/* Enable Broadcast. All writes target all channel register sets */
+	reg = 0x0c;
+	dm_i2c_write(dev, 0xff, &reg, 1);
+
+	/* Reset Channel Registers */
+	dm_i2c_read(dev, 0, &reg, 1);
+	reg |= 0x4;
+	dm_i2c_write(dev, 0, &reg, 1);
+
+	/* Enable override divider select and Enable Override Output Mux */
+	dm_i2c_read(dev, 9, &reg, 1);
+	reg |= 0x24;
+	dm_i2c_write(dev, 9, &reg, 1);
+
+	/* Select VCO Divider to full rate (000) */
+	dm_i2c_read(dev, 0x18, &reg, 1);
+	reg &= 0x8f;
+	dm_i2c_write(dev, 0x18, &reg, 1);
+
+	/* Selects active PFD MUX Input as Re-timed Data (001) */
+	dm_i2c_read(dev, 0x1e, &reg, 1);
+	reg &= 0x3f;
+	reg |= 0x20;
+	dm_i2c_write(dev, 0x1e, &reg, 1);
+
+	/* Set data rate as 10.3125 Gbps */
+	reg = 0x0;
+	dm_i2c_write(dev, 0x60, &reg, 1);
+	reg = 0xb2;
+	dm_i2c_write(dev, 0x61, &reg, 1);
+	reg = 0x90;
+	dm_i2c_write(dev, 0x62, &reg, 1);
+	reg = 0xb3;
+	dm_i2c_write(dev, 0x63, &reg, 1);
+	reg = 0xcd;
+	dm_i2c_write(dev, 0x64, &reg, 1);
+#else
+	i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
+
+	/* Access to Control/Shared register */
+	reg = 0x0;
+	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
+
+	/* Read device revision and ID */
+	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
+	debug("Retimer version id = 0x%x\n", reg);
+
+	/* Enable Broadcast. All writes target all channel register sets */
+	reg = 0x0c;
+	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
+
+	/* Reset Channel Registers */
+	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
+	reg |= 0x4;
+	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
+
+	/* Enable override divider select and Enable Override Output Mux */
+	i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
+	reg |= 0x24;
+	i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
+
+	/* Select VCO Divider to full rate (000) */
+	i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
+	reg &= 0x8f;
+	i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
+
+	/* Selects active PFD MUX Input as Re-timed Data (001) */
+	i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
+	reg &= 0x3f;
+	reg |= 0x20;
+	i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
+
+	/* Set data rate as 10.3125 Gbps */
+	reg = 0x0;
+	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
+	reg = 0xb2;
+	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
+	reg = 0x90;
+	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
+	reg = 0xb3;
+	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
+	reg = 0xcd;
+	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
+#endif
+
+	/* Return the default channel */
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
+}
+
+int board_early_init_f(void)
+{
+	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	u32 usb_pwrfault;
+#endif
+#ifdef CONFIG_LPUART
+	u8 uart;
+#endif
+
+	/*
+	 * Enable secure system counter for timer
+	 */
+	out_le32(cntcr, 0x1);
+
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
+	fsl_lsch2_early_init_f();
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+	out_be32(&scfg->rcwpmuxcr0, 0x3333);
+	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+	usb_pwrfault =
+		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
+	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+
+#ifdef CONFIG_LPUART
+	/* We use lpuart0 as system console */
+	uart = QIXIS_READ(brdcfg[14]);
+	uart &= ~CFG_UART_MUX_MASK;
+	uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+	QIXIS_WRITE(brdcfg[14], uart);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+/* determine if it is a warm boot */
+bool is_warm_boot(void)
+{
+#define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
+		return 1;
+
+	return 0;
+}
+#endif
+
+int config_board_mux(int ctrl_type)
+{
+	u8 reg14;
+
+	reg14 = QIXIS_READ(brdcfg[14]);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_GPIO:
+		reg14 = (reg14 & (~0x30)) | 0x20;
+		break;
+	default:
+		puts("Unsupported mux interface type\n");
+		return -1;
+	}
+
+	QIXIS_WRITE(brdcfg[14], reg14);
+
+	return 0;
+}
+
+int config_serdes_mux(void)
+{
+	return 0;
+}
+
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	if (hwconfig("gpio"))
+		config_board_mux(MUX_TYPE_GPIO);
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+	erratum_a010315();
+#endif
+
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
+	board_retimer_init();
+
+#ifdef CONFIG_SYS_FSL_SERDES
+	config_serdes_mux();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+	u8 reg;
+
+	/* fixup DT for the two DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
+	fdt_fixup_fman_ethernet(blob);
+#endif
+	fdt_fixup_board_enet(blob);
+#endif
+
+	fdt_fixup_icid(blob);
+
+	reg = QIXIS_READ(brdcfg[0]);
+	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	/* Disable IFC if QSPI is enabled */
+	if (reg == 0xF)
+		do_fixup_by_compat(blob, "fsl,ifc",
+				   "status", "disabled", 8 + 1, 1);
+
+	return 0;
+}
+#endif
+
+u8 flash_read8(void *addr)
+{
+	return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+	__raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 val = __raw_readw(addr);
+
+	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
+
+#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+void *env_sf_get_env_addr(void)
+{
+	return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+}
+#endif
diff --git a/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg b/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
new file mode 100644
index 000000000..f072274f4
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
@@ -0,0 +1,14 @@
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Alt base register
+09570158 00001000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#flush PBI data
+096100c0 000fffff
diff --git a/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_qixis.h b/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_qixis.h
new file mode 100644
index 000000000..bba494ae4
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_qixis.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+#define QIXIS_SYSCLK_64			0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg b/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
new file mode 100644
index 000000000..d87058b7e
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+08100010 0a000000 00000000 00000000
+14550002 80004012 e0106000 c1002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg b/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
new file mode 100644
index 000000000..b6b5e0b10
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable IFC; disable QSPI
+08100010 0a000000 00000000 00000000
+14550002 80004012 60040000 c1002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg b/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
new file mode 100644
index 000000000..7783521b9
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable QSPI; disable IFC
+08100010 0a000000 00000000 00000000
+14550002 80004012 60040000 c1002000
+00000000 00000000 00000000 00038800
+20124000 00001100 00000096 00000001
diff --git a/roms/u-boot/board/freescale/ls1043ardb/Kconfig b/roms/u-boot/board/freescale/ls1043ardb/Kconfig
new file mode 100644
index 000000000..3d9e295c4
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/Kconfig
@@ -0,0 +1,41 @@
+
+if TARGET_LS1043ARDB
+
+config SYS_BOARD
+	default "ls1043ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1043ardb"
+
+config SYS_HAS_ARMV8_SECURE_BASE
+	bool "Enable secure address for PSCI image"
+	depends on ARMV8_PSCI
+	default n
+	help
+	  PSCI image can be re-located to secure RAM.
+	  If enabled, please also define the value for ARMV8_SECURE_BASE,
+	  for LS1043ARDB, it could be some address in OCRAM.
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+	hex "PPA Firmware Addr"
+	default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA Firmware HDR Addr"
+	default 0x60680000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/ls1043ardb/MAINTAINERS b/roms/u-boot/board/freescale/ls1043ardb/MAINTAINERS
new file mode 100644
index 000000000..36e733153
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/MAINTAINERS
@@ -0,0 +1,15 @@
+LS1043A BOARD
+M:	Mingkai Hu <mingkai.hu@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1043ardb/
+F:	board/freescale/ls1043ardb/ls1043ardb.c
+F:	include/configs/ls1043ardb.h
+F:	configs/ls1043ardb_defconfig
+F:	configs/ls1043ardb_nand_defconfig
+F:	configs/ls1043ardb_sdcard_defconfig
+F:	configs/ls1043ardb_tfa_defconfig
+F:	configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+F:	configs/ls1043ardb_SECURE_BOOT_defconfig
+F:	configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+F:	configs/ls1043ardb_nand_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/ls1043ardb/Makefile b/roms/u-boot/board/freescale/ls1043ardb/Makefile
new file mode 100644
index 000000000..5309576c6
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2015 Freescale Semiconductor
+
+obj-y += ddr.o
+obj-y += ls1043ardb.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_NET) += eth.o
+obj-y += cpld.o
+endif
diff --git a/roms/u-boot/board/freescale/ls1043ardb/README b/roms/u-boot/board/freescale/ls1043ardb/README
new file mode 100644
index 000000000..709ddbbef
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/README
@@ -0,0 +1,54 @@
+Overview
+--------
+The LS1043A Reference Design Board (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1043A
+LayerScape Architecture processor. The LS1043ARDB provides SW development
+platform for the Freescale LS1043A processor series, with a complete
+debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
+
+LS1043A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
+
+ LS1043ARDB board Overview
+ -----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
+        standard PCIe card
+      - QSGMII with x4 RJ45 connector
+      - XFI with x1 RJ45 connector
+ - DDR Controller
+     - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
+ -IFC/Local Bus
+    - One 128MB NOR flash 16-bit data bus
+    - One 512 MB NAND flash with ECC support
+    - CPLD connection
+ - USB 3.0
+    - Two super speed USB 3.0 Type A ports
+ - SDHC: connects directly to a full SD/MMC slot
+ - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
+ - 4 I2C controllers
+ - UART
+   - Two 4-pin serial ports at up to 115.2 Kbit/s
+   - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address	End Address	Description		Size
+0x00_0000_0000	0x00_000F_FFFF	Secure Boot ROM		1MB
+0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR			240MB
+0x00_1000_0000	0x00_1000_FFFF	OCRAM0			64KB
+0x00_1001_0000	0x00_1001_FFFF	OCRAM1			64KB
+0x00_2000_0000	0x00_20FF_FFFF	DCSR			16MB
+0x00_6000_0000	0x00_67FF_FFFF	IFC - NOR Flash		128MB
+0x00_7E80_0000	0x00_7E80_FFFF	IFC - NAND Flash	64KB
+0x00_7FB0_0000	0x00_7FB0_0FFF	IFC - FPGA		4KB
+0x00_8000_0000	0x00_FFFF_FFFF	DRAM1			2GB
+
+Booting Options
+---------------
+a) NOR boot
+b) NAND boot
+c) SD boot
diff --git a/roms/u-boot/board/freescale/ls1043ardb/cpld.c b/roms/u-boot/board/freescale/ls1043ardb/cpld.c
new file mode 100644
index 000000000..5d2e8015a
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/cpld.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * Freescale LS1043ARDB board-specific CPLD controlling supports.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	out_8(p + reg, value);
+}
+
+/* Set the boot bank to the alternate bank */
+void cpld_set_altbank(void)
+{
+	u16 reg = CPLD_CFG_RCW_SRC_NOR;
+	u8 reg4 = CPLD_READ(soft_mux_on);
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
+	u8 reg7 = CPLD_READ(vbank);
+
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
+
+	reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
+	CPLD_WRITE(vbank, reg7);
+
+	CPLD_WRITE(system_rst, 1);
+}
+
+/* Set the boot bank to the default bank */
+void cpld_set_defbank(void)
+{
+	u16 reg = CPLD_CFG_RCW_SRC_NOR;
+	u8 reg4 = CPLD_READ(soft_mux_on);
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
+
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
+
+	CPLD_WRITE(vbank, 0);
+
+	CPLD_WRITE(system_rst, 1);
+}
+
+void cpld_set_nand(void)
+{
+	u16 reg = CPLD_CFG_RCW_SRC_NAND;
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
+
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
+
+	CPLD_WRITE(system_rst, 1);
+}
+
+void cpld_set_sd(void)
+{
+	u16 reg = CPLD_CFG_RCW_SRC_SD;
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
+
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
+
+	CPLD_WRITE(system_rst, 1);
+}
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+	printf("cpld_ver	= %x\n", CPLD_READ(cpld_ver));
+	printf("cpld_ver_sub	= %x\n", CPLD_READ(cpld_ver_sub));
+	printf("pcba_ver	= %x\n", CPLD_READ(pcba_ver));
+	printf("soft_mux_on	= %x\n", CPLD_READ(soft_mux_on));
+	printf("cfg_rcw_src1	= %x\n", CPLD_READ(cfg_rcw_src1));
+	printf("cfg_rcw_src2	= %x\n", CPLD_READ(cfg_rcw_src2));
+	printf("vbank		= %x\n", CPLD_READ(vbank));
+	printf("sysclk_sel	= %x\n", CPLD_READ(sysclk_sel));
+	printf("uart_sel	= %x\n", CPLD_READ(uart_sel));
+	printf("sd1refclk_sel	= %x\n", CPLD_READ(sd1refclk_sel));
+	printf("tdmclk_mux_sel	= %x\n", CPLD_READ(tdmclk_mux_sel));
+	printf("sdhc_spics_sel	= %x\n", CPLD_READ(sdhc_spics_sel));
+	printf("status_led	= %x\n", CPLD_READ(status_led));
+	putc('\n');
+}
+#endif
+
+void cpld_rev_bit(unsigned char *value)
+{
+	u8 rev_val, val;
+	int i;
+
+	val = *value;
+	rev_val = val & 1;
+	for (i = 1; i <= 7; i++) {
+		val >>= 1;
+		rev_val <<= 1;
+		rev_val |= val & 1;
+	}
+
+	*value = rev_val;
+}
+
+int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int rc = 0;
+
+	if (argc <= 1)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		if (strcmp(argv[2], "altbank") == 0)
+			cpld_set_altbank();
+		else if (strcmp(argv[2], "nand") == 0)
+			cpld_set_nand();
+		else if (strcmp(argv[2], "sd") == 0)
+			cpld_set_sd();
+		else
+			cpld_set_defbank();
+#ifdef DEBUG
+	} else if (strcmp(argv[1], "dump") == 0) {
+		cpld_dump_regs();
+#endif
+	} else {
+		rc = cmd_usage(cmdtp);
+	}
+
+	return rc;
+}
+
+U_BOOT_CMD(
+	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+	"Reset the board or alternate bank",
+	"reset: reset to default bank\n"
+	"cpld reset altbank: reset to alternate bank\n"
+	"cpld reset nand: reset to boot from NAND flash\n"
+	"cpld reset sd: reset to boot from SD card\n"
+#ifdef DEBUG
+	"cpld dump - display the CPLD registers\n"
+#endif
+);
diff --git a/roms/u-boot/board/freescale/ls1043ardb/cpld.h b/roms/u-boot/board/freescale/ls1043ardb/cpld.h
new file mode 100644
index 000000000..2e757b557
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/cpld.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor
+ */
+
+#ifndef __CPLD_H__
+#define __CPLD_H__
+
+/*
+ * CPLD register set of LS1043ARDB board-specific.
+ */
+struct cpld_data {
+	u8 cpld_ver;		/* 0x0 - CPLD Major Revision Register */
+	u8 cpld_ver_sub;	/* 0x1 - CPLD Minor Revision Register */
+	u8 pcba_ver;		/* 0x2 - PCBA Revision Register */
+	u8 system_rst;		/* 0x3 - system reset register */
+	u8 soft_mux_on;		/* 0x4 - Switch Control Enable Register */
+	u8 cfg_rcw_src1;	/* 0x5 - Reset config word 1 */
+	u8 cfg_rcw_src2;	/* 0x6 - Reset config word 1 */
+	u8 vbank;		/* 0x7 - Flash bank selection Control */
+	u8 sysclk_sel;		/* 0x8 - */
+	u8 uart_sel;		/* 0x9 - */
+	u8 sd1refclk_sel;	/* 0xA - */
+	u8 tdmclk_mux_sel;	/* 0xB - */
+	u8 sdhc_spics_sel;	/* 0xC - */
+	u8 status_led;		/* 0xD - */
+	u8 global_rst;		/* 0xE - */
+};
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+void cpld_rev_bit(unsigned char *value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)  \
+	cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_SW_MUX_BANK_SEL	0x40
+#define CPLD_BANK_SEL_MASK	0x07
+#define CPLD_BANK_SEL_ALTBANK	0x04
+#define CPLD_CFG_RCW_SRC_NOR	0x025
+#define CPLD_CFG_RCW_SRC_NAND	0x106
+#define CPLD_CFG_RCW_SRC_SD	0x040
+#endif
diff --git a/roms/u-boot/board/freescale/ls1043ardb/ddr.c b/roms/u-boot/board/freescale/ls1043ardb/ddr.c
new file mode 100644
index 000000000..08b43ff5e
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/ddr.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/global_data.h>
+#include "ddr.h"
+#include <log.h>
+#include <vsprintf.h>
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				popts->cpo_override = pbsp->cpo_override;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for %lu MT/s\n",
+		       ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+	/* force DDR bus width to 32 bits */
+	popts->data_bus_width = 1;
+	popts->otf_burst_chop_en = 0;
+	popts->burst_length = DDR_BL8;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 1;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x46;
+
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
+}
+
+/* DDR model number: MT40A512M8HX-093E */
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 2147483648u,
+	.capacity = 2147483648u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.bank_addr_bits = 0,
+	.bank_group_bits = 2,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 938,
+	.tckmax_ps = 1500,
+	.caslat_x = 0x000DFA00,
+	.taa_ps = 13500,
+	.trcd_ps = 13500,
+	.trp_ps = 13500,
+	.tras_ps = 33000,
+	.trc_ps = 46500,
+	.trfc1_ps = 260000,
+	.trfc2_ps = 160000,
+	.trfc4_ps = 110000,
+	.tfaw_ps = 21000,
+	.trrds_ps = 3700,
+	.trrdl_ps = 5300,
+	.tccdl_ps = 5355,
+	.refresh_rate_ps = 7800000,
+	.dq_mapping[0] = 0x0,
+	.dq_mapping[1] = 0x0,
+	.dq_mapping[2] = 0x0,
+	.dq_mapping[3] = 0x0,
+	.dq_mapping[4] = 0x0,
+	.dq_mapping[5] = 0x0,
+	.dq_mapping[6] = 0x0,
+	.dq_mapping[7] = 0x0,
+	.dq_mapping[8] = 0x0,
+	.dq_mapping[9] = 0x0,
+	.dq_mapping[10] = 0x0,
+	.dq_mapping[11] = 0x0,
+	.dq_mapping[12] = 0x0,
+	.dq_mapping[13] = 0x0,
+	.dq_mapping[14] = 0x0,
+	.dq_mapping[15] = 0x0,
+	.dq_mapping[16] = 0x0,
+	.dq_mapping[17] = 0x0,
+	.dq_mapping_ors = 0,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			    unsigned int controller_number,
+			    unsigned int dimm_number)
+{
+	static const char dimm_model[] = "Fixed DDR on board";
+
+	if (((controller_number == 0) && (dimm_number == 0)) ||
+	    ((controller_number == 1) && (dimm_number == 0))) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+#else
+
+phys_size_t fixed_sdram(void)
+{
+	int i;
+	char buf[32];
+	fsl_ddr_cfg_regs_t ddr_cfg_regs;
+	phys_size_t ddr_size;
+	ulong ddr_freq, ddr_freq_mhz;
+
+	ddr_freq = get_ddr_freq(0);
+	ddr_freq_mhz = ddr_freq / 1000000;
+
+	printf("Configuring DDR for %s MT/s data rate\n",
+	       strmhz(buf, ddr_freq));
+
+	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+		    (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+			memcpy(&ddr_cfg_regs,
+			       fixed_ddr_parm_0[i].ddr_settings,
+			       sizeof(ddr_cfg_regs));
+			break;
+		}
+	}
+
+	if (fixed_ddr_parm_0[i].max_freq == 0)
+		panic("Unsupported DDR data rate %s MT/s data rate\n",
+		      strmhz(buf, ddr_freq));
+
+	ddr_size = (phys_size_t)2048 * 1024 * 1024;
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	return ddr_size;
+}
+#endif
+
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+	if (!gd->ram_size)
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+		gd->ram_size = fsl_ddr_sdram_size();
+#else
+		gd->ram_size = 0x80000000;
+#endif
+		return 0;
+}
+#else
+int fsl_initdram(void)
+{
+	phys_size_t dram_size;
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+	puts("Initializing DDR....\n");
+	dram_size = fsl_ddr_sdram();
+#else
+	dram_size =  fsl_ddr_sdram_size();
+#endif
+#else
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+	puts("Initialzing DDR using fixed setting\n");
+	dram_size = fixed_sdram();
+#else
+	gd->ram_size = 0x80000000;
+
+	return 0;
+#endif
+#endif
+	erratum_a008850_post();
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	fsl_dp_ddr_restore();
+#endif
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/ls1043ardb/ddr.h b/roms/u-boot/board/freescale/ls1043ardb/ddr.h
new file mode 100644
index 000000000..85ed920ca
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/ddr.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+extern void erratum_a008850_post(void);
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+	u32 cpo_override;
+	u32 write_data_delay;
+	u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	{1,  1666, 0, 12,     7, 0x07090800, 0x00000000,},
+	{1,  1900, 0, 12,     7, 0x07090800, 0x00000000,},
+	{1,  2200, 0, 12,     7, 0x07090800, 0x00000000,},
+#endif
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = {
+	.cs[0].bnds = 0x0000007F,
+	.cs[1].bnds = 0,
+	.cs[2].bnds = 0,
+	.cs[3].bnds = 0,
+	.cs[0].config = 0x80040322,
+	.cs[0].config_2 = 0,
+	.cs[1].config = 0,
+	.cs[1].config_2 = 0,
+	.cs[2].config = 0,
+	.cs[3].config = 0,
+	.timing_cfg_3 = 0x010C1000,
+	.timing_cfg_0 = 0x91550018,
+	.timing_cfg_1 = 0xBBB48C42,
+	.timing_cfg_2 = 0x0048C111,
+	.ddr_sdram_cfg = 0xC50C0008,
+	.ddr_sdram_cfg_2 = 0x00401100,
+	.ddr_sdram_cfg_3 = 0,
+	.ddr_sdram_mode = 0x03010210,
+	.ddr_sdram_mode_2 = 0,
+	.ddr_sdram_mode_3 = 0x00010210,
+	.ddr_sdram_mode_4 = 0,
+	.ddr_sdram_mode_5 = 0x00010210,
+	.ddr_sdram_mode_6 = 0,
+	.ddr_sdram_mode_7 = 0x00010210,
+	.ddr_sdram_mode_8 = 0,
+	.ddr_sdram_mode_9 = 0x00000500,
+	.ddr_sdram_mode_10 = 0x04000000,
+	.ddr_sdram_mode_11 = 0x00000400,
+	.ddr_sdram_mode_12 = 0x04000000,
+	.ddr_sdram_mode_13 = 0x00000400,
+	.ddr_sdram_mode_14 = 0x04000000,
+	.ddr_sdram_mode_15 = 0x00000400,
+	.ddr_sdram_mode_16 = 0x04000000,
+	.ddr_sdram_interval = 0x18600618,
+	.ddr_data_init = 0xDEADBEEF,
+	.ddr_sdram_clk_cntl = 0x03000000,
+	.ddr_init_addr = 0,
+	.ddr_init_ext_addr = 0,
+	.timing_cfg_4 = 0x00000002,
+	.timing_cfg_5 = 0x03401400,
+	.timing_cfg_6 = 0,
+	.timing_cfg_7 = 0x13300000,
+	.timing_cfg_8 = 0x02115600,
+	.timing_cfg_9 = 0,
+	.ddr_zq_cntl = 0x8A090705,
+	.ddr_wrlvl_cntl = 0x8675F607,
+	.ddr_wrlvl_cntl_2 = 0x07090800,
+	.ddr_wrlvl_cntl_3 = 0,
+	.ddr_sr_cntr = 0,
+	.ddr_sdram_rcw_1 = 0,
+	.ddr_sdram_rcw_2 = 0,
+	.ddr_cdr1 = 0x80040000,
+	.ddr_cdr2 = 0x0000A181,
+	.dq_map_0 = 0,
+	.dq_map_1 = 0,
+	.dq_map_2 = 0,
+	.dq_map_3 = 0,
+	.debug[28] = 0x00700046,
+
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{1550, 1650, &ddr_cfg_regs_1600},
+	{0, 0, NULL}
+};
+
+#endif
+#endif
diff --git a/roms/u-boot/board/freescale/ls1043ardb/eth.c b/roms/u-boot/board/freescale/ls1043ardb/eth.c
new file mode 100644
index 000000000..1f01c1551
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/eth.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+#include <common.h>
+#include <net.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_dtsec.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	int i;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	struct mii_dev *dev;
+	u32 srds_s1;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	/* Set the two on-board RGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+	/* QSGMII on lane B, MAC 1/2/5/6 */
+	fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR);
+
+	switch (srds_s1) {
+	case 0x1455:
+		break;
+	default:
+		printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n",
+		       srds_s1);
+		break;
+	}
+
+	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
+		fm_info_set_mdio(i, dev);
+
+	/* XFI on lane A, MAC 9 */
+	fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+	fm_info_set_mdio(FM1_10GEC1, dev);
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/freescale/ls1043ardb/ls1043ardb.c b/roms/u-boot/board/freescale/ls1043ardb/ls1043ardb.c
new file mode 100644
index 000000000..beef26b08
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/ls1043ardb.c
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <fdt_support.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include <fsl_sec.h>
+#include "cpld.h"
+#ifdef CONFIG_U_QE
+#include <fsl_qe.h>
+#endif
+#include <asm/arch/ppa.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_TFABOOT
+struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"nor",
+		CONFIG_SYS_NOR_CSPR,
+		CONFIG_SYS_NOR_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+
+	},
+	{
+		"nand",
+		CONFIG_SYS_NAND_CSPR,
+		CONFIG_SYS_NAND_CSPR_EXT,
+		CONFIG_SYS_NAND_AMASK,
+		CONFIG_SYS_NAND_CSOR,
+		{
+			CONFIG_SYS_NAND_FTIM0,
+			CONFIG_SYS_NAND_FTIM1,
+			CONFIG_SYS_NAND_FTIM2,
+			CONFIG_SYS_NAND_FTIM3
+		},
+	},
+	{
+		"cpld",
+		CONFIG_SYS_CPLD_CSPR,
+		CONFIG_SYS_CPLD_CSPR_EXT,
+		CONFIG_SYS_CPLD_AMASK,
+		CONFIG_SYS_CPLD_CSOR,
+		{
+			CONFIG_SYS_CPLD_FTIM0,
+			CONFIG_SYS_CPLD_FTIM1,
+			CONFIG_SYS_CPLD_FTIM2,
+			CONFIG_SYS_CPLD_FTIM3
+		},
+	}
+};
+
+struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"nand",
+		CONFIG_SYS_NAND_CSPR,
+		CONFIG_SYS_NAND_CSPR_EXT,
+		CONFIG_SYS_NAND_AMASK,
+		CONFIG_SYS_NAND_CSOR,
+		{
+			CONFIG_SYS_NAND_FTIM0,
+			CONFIG_SYS_NAND_FTIM1,
+			CONFIG_SYS_NAND_FTIM2,
+			CONFIG_SYS_NAND_FTIM3
+		},
+	},
+	{
+		"nor",
+		CONFIG_SYS_NOR_CSPR,
+		CONFIG_SYS_NOR_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+	},
+	{
+		"cpld",
+		CONFIG_SYS_CPLD_CSPR,
+		CONFIG_SYS_CPLD_CSPR_EXT,
+		CONFIG_SYS_CPLD_AMASK,
+		CONFIG_SYS_CPLD_CSOR,
+		{
+			CONFIG_SYS_CPLD_FTIM0,
+			CONFIG_SYS_CPLD_FTIM1,
+			CONFIG_SYS_CPLD_FTIM2,
+			CONFIG_SYS_CPLD_FTIM3
+		},
+	}
+};
+
+void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
+{
+	enum boot_src src = get_boot_src();
+
+	if (src == BOOT_SOURCE_IFC_NAND)
+		regs_info->regs = ifc_cfg_nand_boot;
+	else
+		regs_info->regs = ifc_cfg_nor_boot;
+	regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
+}
+
+#endif
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+
+int checkboard(void)
+{
+#ifdef CONFIG_TFABOOT
+	enum boot_src src = get_boot_src();
+#endif
+	static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
+#ifndef CONFIG_SD_BOOT
+	u8 cfg_rcw_src1, cfg_rcw_src2;
+	u16 cfg_rcw_src;
+#endif
+	u8 sd1refclk_sel;
+
+	printf("Board: LS1043ARDB, boot from ");
+
+#ifdef CONFIG_TFABOOT
+	if (src == BOOT_SOURCE_SD_MMC)
+		puts("SD\n");
+	else {
+#endif
+
+#ifdef CONFIG_SD_BOOT
+	puts("SD\n");
+#else
+	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
+	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
+	cpld_rev_bit(&cfg_rcw_src1);
+	cfg_rcw_src = cfg_rcw_src1;
+	cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
+
+	if (cfg_rcw_src == 0x25)
+		printf("vBank %d\n", CPLD_READ(vbank));
+	else if (cfg_rcw_src == 0x106)
+		puts("NAND\n");
+	else
+		printf("Invalid setting of SW4\n");
+#endif
+
+#ifdef CONFIG_TFABOOT
+	}
+#endif
+	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
+	       CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
+
+	puts("SERDES Reference Clocks:\n");
+	sd1refclk_sel = CPLD_READ(sd1refclk_sel);
+	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+	erratum_a010315();
+#endif
+
+#ifdef CONFIG_FSL_IFC
+	init_final_memctl_regs();
+#endif
+
+#ifdef CONFIG_NXP_ESBC
+	/* In case of Secure Boot, the IBR configures the SMMU
+	 * to allow only Secure transactions.
+	 * SMMU must be reset in bypass mode.
+	 * Set the ClientPD bit and Clear the USFCFG Bit
+	 */
+	u32 val;
+	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_SCR0, val);
+	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+#ifdef CONFIG_U_QE
+	u_qe_init();
+#endif
+	/* invert AQR105 IRQ pins polarity */
+	out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
+
+	return 0;
+}
+
+int config_board_mux(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	u32 usb_pwrfault;
+
+	if (hwconfig("qe-hdlc")) {
+		out_be32(&scfg->rcwpmuxcr0,
+			 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
+		printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
+		       in_be32(&scfg->rcwpmuxcr0));
+	} else {
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+		out_be32(&scfg->rcwpmuxcr0, 0x3333);
+		out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+		usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+				SCFG_USBPWRFAULT_USB3_SHIFT) |
+				(SCFG_USBPWRFAULT_DEDICATED <<
+				SCFG_USBPWRFAULT_USB2_SHIFT) |
+				(SCFG_USBPWRFAULT_SHARED <<
+				 SCFG_USBPWRFAULT_USB1_SHIFT);
+		out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+	}
+	return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+	config_board_mux();
+	return 0;
+}
+#endif
+
+void fdt_del_qe(void *blob)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+				"fsl,qe")) >= 0) {
+		fdt_del_node(blob, nodeoff);
+	}
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	/* fixup DT for the two DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
+	fdt_fixup_fman_ethernet(blob);
+#endif
+#endif
+
+	fdt_fixup_icid(blob);
+
+	/*
+	 * qe-hdlc and usb multi-use the pins,
+	 * when set hwconfig to qe-hdlc, delete usb node.
+	 */
+	if (hwconfig("qe-hdlc"))
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+		fdt_del_node_and_alias(blob, "usb1");
+#endif
+	/*
+	 * qe just support qe-uart and qe-hdlc,
+	 * if qe-uart and qe-hdlc are not set in hwconfig,
+	 * delete qe node.
+	 */
+	if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
+		fdt_del_qe(blob);
+
+	return 0;
+}
+
+u8 flash_read8(void *addr)
+{
+	return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+	__raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 val = __raw_readw(addr);
+
+	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg b/roms/u-boot/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
new file mode 100644
index 000000000..f072274f4
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
@@ -0,0 +1,14 @@
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Alt base register
+09570158 00001000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#flush PBI data
+096100c0 000fffff
diff --git a/roms/u-boot/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/roms/u-boot/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
new file mode 100644
index 000000000..d87058b7e
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+08100010 0a000000 00000000 00000000
+14550002 80004012 e0106000 c1002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/roms/u-boot/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/roms/u-boot/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
new file mode 100644
index 000000000..e2ee34b7d
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+08100010 0a000000 00000000 00000000
+14550002 80004012 60040000 c1002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/roms/u-boot/board/freescale/ls1046afrwy/Kconfig b/roms/u-boot/board/freescale/ls1046afrwy/Kconfig
new file mode 100644
index 000000000..6a4c3e92f
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046afrwy/Kconfig
@@ -0,0 +1,17 @@
+
+if TARGET_LS1046AFRWY
+
+config SYS_BOARD
+	default "ls1046afrwy"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1046afrwy"
+
+source "board/freescale/common/Kconfig"
+endif
diff --git a/roms/u-boot/board/freescale/ls1046afrwy/MAINTAINERS b/roms/u-boot/board/freescale/ls1046afrwy/MAINTAINERS
new file mode 100644
index 000000000..cb8aa8c37
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046afrwy/MAINTAINERS
@@ -0,0 +1,12 @@
+LS1046AFRWY BOARD
+M:	Pramod Kumar <pramod.kumar_1@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1046afrwy/
+F:	board/freescale/ls1046afrwy/ls1046afrwy.c
+F:	include/configs/ls1046afrwy.h
+F:	configs/ls1046afrwy_tfa_defconfig
+
+LS1046AFRWY_SECURE_BOOT BOARD
+M:	Manish Tomar <manish.tomar@nxp.com>
+S:	Maintained
+F:	configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/ls1046afrwy/Makefile b/roms/u-boot/board/freescale/ls1046afrwy/Makefile
new file mode 100644
index 000000000..c70f5cda7
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046afrwy/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 NXP
+
+obj-y += ddr.o
+obj-y += ls1046afrwy.o
+obj-$(CONFIG_NET) += eth.o
diff --git a/roms/u-boot/board/freescale/ls1046afrwy/README b/roms/u-boot/board/freescale/ls1046afrwy/README
new file mode 100644
index 000000000..d7b5a7794
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046afrwy/README
@@ -0,0 +1,76 @@
+Overview
+--------
+The LS1046A Freeway Board (iFRWY) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1046A
+LayerScape Architecture processor. The FRWY-LS1046A provides SW development
+platform for the Freescale LS1046A processor series, with a complete
+debugging environment. The FRWY-LS1046A  is lead-free and RoHS-compliant.
+
+LS1046A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
+SoC overview.
+
+ FRWY-LS1046A board Overview
+ -----------------------
+ - SERDES1 Connections, 4 lanes supporting:
+      - Lane0: Unused
+      - Lane1: Unused
+      - Lane2: QSGMII
+      - Lane3: Unused
+ - SERDES2 Connections, 4 lanes supporting:
+      - Lane0: Unused
+      - Lane1: PCIe3 with PCIe x1 slot
+      - Lane2: Unused
+      - Lane3: PCIe3 with PCIe x1 slot
+ - DDR Controller
+     - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
+ -IFC/Local Bus
+    - One 512 MB NAND flash with ECC support
+ - USB 3.0
+    - Two Type A port
+ - SDHC: connects directly to a full microSD slot
+ - QSPI: 64 MB high-speed flash Memory for boot code and storage
+ - 4 I2C controllers
+ - UART
+   - Two 4-pin serial ports at up to 115.2 Kbit/s
+   - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address	 End Address	 Description		Size
+0x00_0000_0000 - 0x00_000F_FFFF  Secure Boot ROM	1MB
+0x00_0100_0000 - 0x00_0FFF_FFFF  CCSRBAR		240MB
+0x00_1000_0000 - 0x00_1000_FFFF  OCRAM0 		64KB
+0x00_1001_0000 - 0x00_1001_FFFF  OCRAM1 		64KB
+0x00_2000_0000 - 0x00_20FF_FFFF  DCSR			16MB
+0x00_7E80_0000 - 0x00_7E80_FFFF  IFC - NAND Flash	64KB
+0x00_7FB0_0000 - 0x00_7FB0_0FFF  IFC - CPLD		4KB
+0x00_8000_0000 - 0x00_FFFF_FFFF  DRAM1			2GB
+0x05_0000_0000 - 0x05_07FF_FFFF  QMAN S/W Portal	128M
+0x05_0800_0000 - 0x05_0FFF_FFFF  BMAN S/W Portal	128M
+0x08_8000_0000 - 0x09_FFFF_FFFF  DRAM2			6GB
+0x40_0000_0000 - 0x47_FFFF_FFFF  PCI Express1		32G
+0x48_0000_0000 - 0x4F_FFFF_FFFF  PCI Express2		32G
+0x50_0000_0000 - 0x57_FFFF_FFFF  PCI Express3		32G
+
+QSPI flash map:
+Start Address    End Address     Description		Size
+0x00_4000_0000 - 0x00_400F_FFFF  RCW + PBI + BL2	1MB
+0x00_4010_0000 - 0x00_404F_FFFF  FIP Image
+				  (Bl31 + BL32(optee.
+				  bin) + Bl33(uboot)
+				  + headers for secure
+				  boot)			4MB
+0x00_4050_0000 - 0x00_405F_FFFF  Boot Firmware Env	1MB
+0x00_4060_0000 - 0x00_408F_FFFF  Secure boot headers	3MB
+0x00_4090_0000 - 0x00_4093_FFFF  FMan ucode		256KB
+0x00_4094_0000 - 0x00_4097_FFFF  QE/uQE firmware	256KB
+0x00_409C_0000 - 0x00_409F_FFFF  Reserved		256KB
+0x00_4100_0000 - 0x00_43FF_FFFF  FIT Image		48MB
+
+Booting Options
+---------------
+a) QSPI boot
+b) microSD boot
diff --git a/roms/u-boot/board/freescale/ls1046afrwy/ddr.c b/roms/u-boot/board/freescale/ls1046afrwy/ddr.c
new file mode 100644
index 000000000..256397b52
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046afrwy/ddr.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/ls1046afrwy/eth.c b/roms/u-boot/board/freescale/ls1046afrwy/eth.c
new file mode 100644
index 000000000..06ccfe9e8
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046afrwy/eth.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+#include <common.h>
+#include <fdt_support.h>
+#include <net.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_dtsec.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct memac_mdio_info dtsec_mdio_info;
+	struct mii_dev *dev;
+	u32 srds_s1;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	/* QSGMII on lane B, MAC 6/5/10/1 */
+	fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);
+
+	switch (srds_s1) {
+	case 0x3040:
+		break;
+	default:
+		printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n",
+		       srds_s1);
+		break;
+	}
+
+	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+	fm_info_set_mdio(FM1_DTSEC6, dev);
+	fm_info_set_mdio(FM1_DTSEC5, dev);
+	fm_info_set_mdio(FM1_DTSEC10, dev);
+	fm_info_set_mdio(FM1_DTSEC1, dev);
+
+	fm_disable_port(FM1_DTSEC9);
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_FMAN_ENET
+int fdt_update_ethernet_dt(void *blob)
+{
+	u32 srds_s1;
+	int i, prop;
+	int offset, nodeoff;
+	const char *path;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	/* Cycle through all aliases */
+	for (prop = 0; ; prop++) {
+		const char *name;
+
+		/* FDT might have been edited, recompute the offset */
+		offset = fdt_first_property_offset(blob,
+						   fdt_path_offset(blob,
+								   "/aliases")
+						   );
+		/* Select property number 'prop' */
+		for (i = 0; i < prop; i++)
+			offset = fdt_next_property_offset(blob, offset);
+
+		if (offset < 0)
+			break;
+
+		path = fdt_getprop_by_offset(blob, offset, &name, NULL);
+		nodeoff = fdt_path_offset(blob, path);
+
+		switch (srds_s1) {
+		case 0x3040:
+			if (!strcmp(name, "ethernet1"))
+				fdt_status_disabled(blob, nodeoff);
+			if (!strcmp(name, "ethernet2"))
+				fdt_status_disabled(blob, nodeoff);
+			if (!strcmp(name, "ethernet3"))
+				fdt_status_disabled(blob, nodeoff);
+			if (!strcmp(name, "ethernet6"))
+				fdt_status_disabled(blob, nodeoff);
+		break;
+		default:
+			printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n",
+			       __func__, srds_s1);
+		break;
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/ls1046afrwy/ls1046afrwy.c b/roms/u-boot/board/freescale/ls1046afrwy/ls1046afrwy.c
new file mode 100644
index 000000000..f1709dcd1
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_sec.h>
+#include <fsl_dspi.h>
+
+#define LS1046A_PORSR1_REG 0x1EE0000
+#define BOOT_SRC_SD        0x20000000
+#define BOOT_SRC_MASK	   0xFF800000
+#define BOARD_REV_GPIO_SHIFT	17
+#define BOARD_REV_MASK     0x03
+#define USB2_SEL_MASK	   0x00000100
+
+#define BYTE_SWAP_32(word)  ((((word) & 0xff000000) >> 24) |  \
+(((word) & 0x00ff0000) >>  8) | \
+(((word) & 0x0000ff00) <<  8) | \
+(((word) & 0x000000ff) << 24))
+#define SPI_MCR_REG	0x2100000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
+{
+	int ret;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static inline void demux_select_usb2(void)
+{
+	u32 val;
+	struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
+
+	val = in_be32(&pgpio->gpdir);
+	val |=  USB2_SEL_MASK;
+	out_be32(&pgpio->gpdir, val);
+
+	val = in_be32(&pgpio->gpdat);
+	val |=  USB2_SEL_MASK;
+	out_be32(&pgpio->gpdat, val);
+}
+
+static inline void set_spi_cs_signal_inactive(void)
+{
+	/* default: all CS signals inactive state is high */
+	uint mcr_val;
+	uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
+				DSPI_MCR_CRXF | DSPI_MCR_CTXF;
+
+	mcr_val = in_be32(SPI_MCR_REG);
+	mcr_val |= DSPI_MCR_HALT;
+	out_be32(SPI_MCR_REG, mcr_val);
+	out_be32(SPI_MCR_REG, mcr_cfg_val);
+	mcr_val = in_be32(SPI_MCR_REG);
+	mcr_val &= ~DSPI_MCR_HALT;
+	out_be32(SPI_MCR_REG, mcr_val);
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+static inline uint8_t get_board_version(void)
+{
+	struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
+
+	/* GPIO 13 and GPIO 14 are used for Board Rev */
+	u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT))
+				& BOARD_REV_MASK;
+
+	/* GPIOs' are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */
+	u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK;
+
+	return val;
+}
+
+int checkboard(void)
+{
+	static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
+	u32 boot_src;
+	u8 rev;
+
+	rev = get_board_version();
+	switch (rev) {
+	case 0x00:
+		puts("Board: LS1046AFRWY, Rev: A, boot from ");
+		break;
+	case 0x01:
+		puts("Board: LS1046AFRWY, Rev: B, boot from ");
+		break;
+	default:
+		puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
+		break;
+	}
+	boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
+
+	if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
+		puts("SD\n");
+	else
+		puts("QSPI\n");
+	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
+
+	return 0;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_NXP_ESBC
+	/*
+	 * In case of Secure Boot, the IBR configures the SMMU
+	 * to allow only Secure transactions.
+	 * SMMU must be reset in bypass mode.
+	 * Set the ClientPD bit and Clear the USFCFG Bit
+	 */
+	u32 val;
+val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_SCR0, val);
+	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
+	return 0;
+}
+
+int board_setup_core_volt(u32 vdd)
+{
+	return 0;
+}
+
+void config_board_mux(void)
+{
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	u32 usb_pwrfault;
+	/*
+	 * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
+	 * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
+	 */
+	out_be32(&scfg->rcwpmuxcr0, 0x3300);
+#ifdef CONFIG_HAS_FSL_IIC3
+	/* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
+	out_be32(&scfg->rcwpmuxcr0, 0x0000);
+#endif
+	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+	usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+			SCFG_USBPWRFAULT_USB3_SHIFT) |
+			(SCFG_USBPWRFAULT_DEDICATED <<
+			SCFG_USBPWRFAULT_USB2_SHIFT) |
+			(SCFG_USBPWRFAULT_SHARED <<
+			SCFG_USBPWRFAULT_USB1_SHIFT);
+	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#ifndef CONFIG_HAS_FSL_IIC3
+	/*
+	 * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
+	 * to select I2C3_USB2_SEL_IO
+	 * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
+	 * I2C3 header (default)
+	 * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
+	 * USB2 port
+	 * programmed to select USB2 by setting GPIO3_23 output to one
+	 */
+	demux_select_usb2();
+#endif
+#endif
+	set_spi_cs_signal_inactive();
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	config_board_mux();
+	return 0;
+}
+#endif
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	/* fixup DT for the two DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
+	fdt_fixup_fman_ethernet(blob);
+#endif
+#endif
+
+	fdt_fixup_icid(blob);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/ls1046aqds/Kconfig b/roms/u-boot/board/freescale/ls1046aqds/Kconfig
new file mode 100644
index 000000000..1616dcc68
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/Kconfig
@@ -0,0 +1,33 @@
+if TARGET_LS1046AQDS
+
+config SYS_BOARD
+	default "ls1046aqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1046aqds"
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+	hex "PPA Firmware Addr"
+	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA Firmware HDR Addr"
+	default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x60680000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/ls1046aqds/MAINTAINERS b/roms/u-boot/board/freescale/ls1046aqds/MAINTAINERS
new file mode 100644
index 000000000..72c4253fc
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/MAINTAINERS
@@ -0,0 +1,15 @@
+LS1046AQDS BOARD
+M:	Mingkai Hu <Mingkai.Hu@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1046aqds/
+F:	include/configs/ls1046aqds.h
+F:	configs/ls1046aqds_defconfig
+F:	configs/ls1046aqds_nand_defconfig
+F:	configs/ls1046aqds_sdcard_ifc_defconfig
+F:	configs/ls1046aqds_sdcard_qspi_defconfig
+F:	configs/ls1046aqds_qspi_defconfig
+F:	configs/ls1046aqds_lpuart_defconfig
+F:	configs/ls1046aqds_tfa_defconfig
+F:	configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+F:	configs/ls1046aqds_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/ls1046aqds/Makefile b/roms/u-boot/board/freescale/ls1046aqds/Makefile
new file mode 100644
index 000000000..6267522cc
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ddr.o
+ifndef CONFIG_SPL_BUILD
+obj-y += eth.o
+endif
+obj-y += ls1046aqds.o
diff --git a/roms/u-boot/board/freescale/ls1046aqds/README b/roms/u-boot/board/freescale/ls1046aqds/README
new file mode 100644
index 000000000..b8fa32652
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/README
@@ -0,0 +1,70 @@
+Overview
+--------
+The LS1046A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1046A
+LayerScape Architecture processor. The LS1046AQDS provides SW development
+platform for the Freescale LS1046A processor series, with a complete
+debugging environment.
+
+LS1046A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
+SoC overview.
+
+ LS1046AQDS board Overview
+ -----------------------
+ - SERDES Connections, 8 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - QSGMII
+      - SATA 3.0
+      - XFI
+ - DDR Controller
+     - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
+ -IFC/Local Bus
+    - One in-socket 128 MB NOR flash 16-bit data bus
+    - One 512 MB NAND flash with ECC support
+    - PromJet Port
+    - FPGA connection
+ - USB 3.0
+    - Three high speed USB 3.0 ports
+    - First USB 3.0 port configured as Host with Type-A connector
+    - The other two USB 3.0 ports configured as OTG with micro-AB connector
+ - SDHC port connects directly to an adapter card slot, featuring:
+    - Optional clock feedback paths, and optional high-speed voltage translation assistance
+    - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC
+    - eMMC memory devices
+ - DSPI: Onboard support for three SPI flash memory devices
+ - 4 I2C controllers
+ - One SATA onboard connectors
+ - UART
+   - Two 4-pin serial ports at up to 115.2 Kbit/s
+   - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address    End Address     Description		Size
+0x00_0000_0000 - 0x00_000F_FFFF  Secure Boot ROM	1MB
+0x00_0100_0000 - 0x00_0FFF_FFFF  CCSRBAR		240MB
+0x00_1000_0000 - 0x00_1000_FFFF  OCRAM0 		64KB
+0x00_1001_0000 - 0x00_1001_FFFF  OCRAM1 		64KB
+0x00_2000_0000 - 0x00_20FF_FFFF  DCSR			16MB
+0x00_6000_0000 - 0x00_67FF_FFFF  IFC - NOR Flash	128MB
+0x00_7E80_0000 - 0x00_7E80_FFFF  IFC - NAND Flash	64KB
+0x00_7FB0_0000 - 0x00_7FB0_0FFF  IFC - FPGA		4KB
+0x00_8000_0000 - 0x00_FFFF_FFFF  DRAM1			2GB
+0x05_0000_0000 - 0x05_07FF_FFFF  QMAN S/W Portal	128M
+0x05_0800_0000 - 0x05_0FFF_FFFF  BMAN S/W Portal	128M
+0x08_8000_0000 - 0x09_FFFF_FFFF  DRAM2			6GB
+0x40_0000_0000 - 0x47_FFFF_FFFF  PCI Express1		32G
+0x48_0000_0000 - 0x4F_FFFF_FFFF  PCI Express2		32G
+0x50_0000_0000 - 0x57_FFFF_FFFF  PCI Express3		32G
+
+Booting Options
+---------------
+a) Promjet Boot
+b) NOR boot
+c) NAND boot
+d) SD boot
+e) QSPI boot
diff --git a/roms/u-boot/board/freescale/ls1046aqds/ddr.c b/roms/u-boot/board/freescale/ls1046aqds/ddr.c
new file mode 100644
index 000000000..9a96de271
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/ddr.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
+#include <log.h>
+#include <asm/arch/clock.h>
+#include <asm/global_data.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 3) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for %lu MT/s\n",
+		       ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+	popts->data_bus_width = 0;      /* 64b data bus */
+	popts->otf_burst_chop_en = 0;
+	popts->burst_length = DDR_BL8;
+	popts->bstopre = 0;		/* enable auto precharge */
+
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+			  DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x70;
+}
+
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
+#else
+int fsl_initdram(void)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+#else
+	puts("Initializing DDR....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+#endif
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	fsl_dp_ddr_restore();
+#endif
+
+	erratum_a008850_post();
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/ls1046aqds/ddr.h b/roms/u-boot/board/freescale/ls1046aqds/ddr.h
new file mode 100644
index 000000000..e55446f2b
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/ddr.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+void erratum_a008850_post(void);
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 */
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2300, 0, 8,     9, 0x0A0C0D11, 0x1214150E,},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls1046aqds/eth.c b/roms/u-boot/board/freescale/ls1046aqds/eth.c
new file mode 100644
index 000000000..33db552ad
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/eth.c
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018-2020 NXP
+ */
+
+#include <common.h>
+#include <log.h>
+#include <net.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fdt_support.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <fsl_dtsec.h>
+#include <malloc.h>
+#include <asm/arch/fsl_serdes.h>
+
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "ls1046aqds_qixis.h"
+
+#define EMI_NONE	0xFF
+#define EMI1_RGMII1	0
+#define EMI1_RGMII2	1
+#define EMI1_SLOT1	2
+#define EMI1_SLOT2	3
+#define EMI1_SLOT4	4
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+	"LS1046AQDS_MDIO_RGMII1",
+	"LS1046AQDS_MDIO_RGMII2",
+	"LS1046AQDS_MDIO_SLOT1",
+	"LS1046AQDS_MDIO_SLOT2",
+	"LS1046AQDS_MDIO_SLOT4",
+	"NULL",
+};
+
+/* Map SerDes 1 & 2 lanes to default slot. */
+static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0};
+
+static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+	struct mii_dev *bus;
+	const char *name;
+
+	if (muxval > EMI1_SLOT4)
+		return NULL;
+
+	name = ls1046aqds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+struct ls1046aqds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+static void ls1046aqds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+
+	if (muxval < 7) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+			      int regnum)
+{
+	struct ls1046aqds_mdio *priv = bus->priv;
+
+	ls1046aqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+			       int regnum, u16 value)
+{
+	struct ls1046aqds_mdio *priv = bus->priv;
+
+	ls1046aqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad,
+				    regnum, value);
+}
+
+static int ls1046aqds_mdio_reset(struct mii_dev *bus)
+{
+	struct ls1046aqds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct ls1046aqds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate ls1046aqds MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate ls1046aqds private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = ls1046aqds_mdio_read;
+	bus->write = ls1046aqds_mdio_write;
+	bus->reset = ls1046aqds_mdio_reset;
+	sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+	return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+			      enum fm_port port, int offset)
+{
+	struct fixed_link f_link;
+	const char *phyconn;
+
+	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+		switch (port) {
+		case FM1_DTSEC9:
+			fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1");
+			break;
+		case FM1_DTSEC10:
+			fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2");
+			break;
+		case FM1_DTSEC5:
+			fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3");
+			break;
+		case FM1_DTSEC6:
+			fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4");
+			break;
+		case FM1_DTSEC2:
+			fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1");
+			break;
+		default:
+			break;
+		}
+	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
+		/* 2.5G SGMII interface */
+		f_link.phy_id = cpu_to_fdt32(port);
+		f_link.duplex = cpu_to_fdt32(1);
+		f_link.link_speed = cpu_to_fdt32(1000);
+		f_link.pause = 0;
+		f_link.asym_pause = 0;
+		/* no PHY for 2.5G SGMII on QDS */
+		fdt_delprop(fdt, offset, "phy-handle");
+		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+		fdt_setprop_string(fdt, offset, "phy-connection-type",
+				   "sgmii-2500");
+	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
+		switch (port) {
+		case FM1_DTSEC1:
+			fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4");
+			break;
+		case FM1_DTSEC5:
+			fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2");
+			break;
+		case FM1_DTSEC6:
+			fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1");
+			break;
+		case FM1_DTSEC10:
+			fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3");
+			break;
+		default:
+			break;
+		}
+		fdt_delprop(fdt, offset, "phy-connection-type");
+		fdt_setprop_string(fdt, offset, "phy-connection-type",
+				   "qsgmii");
+	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
+		   (port == FM1_10GEC1 || port == FM1_10GEC2)) {
+		phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
+		if (is_backplane_mode(phyconn)) {
+			/* Backplane KR mode: skip fixups */
+			printf("Interface %d in backplane KR mode\n", port);
+		} else {
+			/* XFI interface */
+			f_link.phy_id = cpu_to_fdt32(port);
+			f_link.duplex = cpu_to_fdt32(1);
+			f_link.link_speed = cpu_to_fdt32(10000);
+			f_link.pause = 0;
+			f_link.asym_pause = 0;
+			/* no PHY for XFI */
+			fdt_delprop(fdt, offset, "phy-handle");
+			fdt_setprop(fdt, offset, "fixed-link", &f_link,
+				    sizeof(f_link));
+			fdt_setprop_string(fdt, offset, "phy-connection-type",
+					   "xgmii");
+		}
+	}
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	int i;
+
+	for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+		case PHY_INTERFACE_MODE_QSGMII:
+			switch (mdio_mux[i]) {
+			case EMI1_SLOT1:
+				fdt_status_okay_by_alias(fdt, "emi1-slot1");
+				break;
+			case EMI1_SLOT2:
+				fdt_status_okay_by_alias(fdt, "emi1-slot2");
+				break;
+			case EMI1_SLOT4:
+				fdt_status_okay_by_alias(fdt, "emi1-slot4");
+				break;
+			default:
+				break;
+			}
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	int i, idx, lane, slot, interface;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 srds_s1, srds_s2;
+	u8 brdcfg12;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	srds_s2 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
+	srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+	/* Initialize the mdio_mux array so we can recognize empty elements */
+	for (i = 0; i < NUM_FM_PORTS; i++)
+		mdio_mux[i] = EMI_NONE;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	/* Register the muxing front-ends to the MDIO buses */
+	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+
+	/* Set the two on-board RGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+	switch (srds_s1) {
+	case 0x3333:
+		/* SGMII on slot 1, MAC 9 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+	case 0x1333:
+	case 0x2333:
+		/* SGMII on slot 1, MAC 10 */
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+	case 0x1133:
+	case 0x2233:
+		/* SGMII on slot 1, MAC 5/6 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	case 0x1040:
+	case 0x2040:
+		/* QSGMII on lane B, MAC 6/5/10/1 */
+		fm_info_set_phy_address(FM1_DTSEC6,
+					QSGMII_CARD_PORT1_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC5,
+					QSGMII_CARD_PORT2_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC10,
+					QSGMII_CARD_PORT3_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC1,
+					QSGMII_CARD_PORT4_PHY_ADDR_S2);
+		break;
+	case 0x3363:
+		/* SGMII on slot 1, MAC 9/10 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+	case 0x1163:
+	case 0x2263:
+	case 0x2223:
+		/* SGMII on slot 1, MAC 6 */
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	default:
+		printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n",
+		       srds_s1);
+		break;
+	}
+
+	if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)
+		/* SGMII on slot 4, MAC 2 */
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		idx = i - FM1_DTSEC1;
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_SGMII:
+		case PHY_INTERFACE_MODE_QSGMII:
+			if (interface == PHY_INTERFACE_MODE_SGMII) {
+				if (i == FM1_DTSEC5) {
+					/* route lane 2 to slot1 so to have
+					 * one sgmii riser card supports
+					 * MAC5 and MAC6.
+					 */
+					brdcfg12 = QIXIS_READ(brdcfg[12]);
+					QIXIS_WRITE(brdcfg[12],
+						    brdcfg12 | 0x80);
+				}
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						SGMII_FM1_DTSEC1 + idx);
+			} else {
+				/* clear the bit 7 to route lane B on slot2. */
+				brdcfg12 = QIXIS_READ(brdcfg[12]);
+				QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);
+
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						QSGMII_FM1_A);
+				lane_to_slot[lane] = 2;
+			}
+
+			if (i == FM1_DTSEC2)
+				lane = 5;
+
+			if (lane < 0)
+				break;
+
+			slot = lane_to_slot[lane];
+			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+			      idx + 1, slot);
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
+
+			switch (slot) {
+			case 1:
+				mdio_mux[i] = EMI1_SLOT1;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 2:
+				mdio_mux[i] = EMI1_SLOT2;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 4:
+				mdio_mux[i] = EMI1_SLOT4;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			default:
+				break;
+			}
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			if (i == FM1_DTSEC3)
+				mdio_mux[i] = EMI1_RGMII1;
+			else if (i == FM1_DTSEC4)
+				mdio_mux[i] = EMI1_RGMII2;
+			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+			break;
+		default:
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds.c b/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds.c
new file mode 100644
index 000000000..20694426a
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds.c
@@ -0,0 +1,519 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <fsl_ddr_sdram.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ppa.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include <fsl_sec.h>
+#include <spl.h>
+
+#include "../common/vid.h"
+#include "../common/qixis.h"
+#include "ls1046aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
+
+#ifdef CONFIG_TFABOOT
+struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"nor0",
+		CONFIG_SYS_NOR0_CSPR,
+		CONFIG_SYS_NOR0_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+
+	},
+	{
+		"nor1",
+		CONFIG_SYS_NOR1_CSPR,
+		CONFIG_SYS_NOR1_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+	},
+	{
+		"nand",
+		CONFIG_SYS_NAND_CSPR,
+		CONFIG_SYS_NAND_CSPR_EXT,
+		CONFIG_SYS_NAND_AMASK,
+		CONFIG_SYS_NAND_CSOR,
+		{
+			CONFIG_SYS_NAND_FTIM0,
+			CONFIG_SYS_NAND_FTIM1,
+			CONFIG_SYS_NAND_FTIM2,
+			CONFIG_SYS_NAND_FTIM3
+		},
+	},
+	{
+		"fpga",
+		CONFIG_SYS_FPGA_CSPR,
+		CONFIG_SYS_FPGA_CSPR_EXT,
+		CONFIG_SYS_FPGA_AMASK,
+		CONFIG_SYS_FPGA_CSOR,
+		{
+			CONFIG_SYS_FPGA_FTIM0,
+			CONFIG_SYS_FPGA_FTIM1,
+			CONFIG_SYS_FPGA_FTIM2,
+			CONFIG_SYS_FPGA_FTIM3
+		},
+	}
+};
+
+struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"nand",
+		CONFIG_SYS_NAND_CSPR,
+		CONFIG_SYS_NAND_CSPR_EXT,
+		CONFIG_SYS_NAND_AMASK,
+		CONFIG_SYS_NAND_CSOR,
+		{
+			CONFIG_SYS_NAND_FTIM0,
+			CONFIG_SYS_NAND_FTIM1,
+			CONFIG_SYS_NAND_FTIM2,
+			CONFIG_SYS_NAND_FTIM3
+		},
+	},
+	{
+		"nor0",
+		CONFIG_SYS_NOR0_CSPR,
+		CONFIG_SYS_NOR0_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+	},
+	{
+		"nor1",
+		CONFIG_SYS_NOR1_CSPR,
+		CONFIG_SYS_NOR1_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+	},
+	{
+		"fpga",
+		CONFIG_SYS_FPGA_CSPR,
+		CONFIG_SYS_FPGA_CSPR_EXT,
+		CONFIG_SYS_FPGA_AMASK,
+		CONFIG_SYS_FPGA_CSOR,
+		{
+			CONFIG_SYS_FPGA_FTIM0,
+			CONFIG_SYS_FPGA_FTIM1,
+			CONFIG_SYS_FPGA_FTIM2,
+			CONFIG_SYS_FPGA_FTIM3
+		},
+	}
+};
+
+void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
+{
+	enum boot_src src = get_boot_src();
+
+	if (src == BOOT_SOURCE_IFC_NAND)
+		regs_info->regs = ifc_cfg_nand_boot;
+	else
+		regs_info->regs = ifc_cfg_nor_boot;
+	regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
+}
+
+#endif
+
+enum {
+	MUX_TYPE_GPIO,
+};
+
+int checkboard(void)
+{
+#ifdef CONFIG_TFABOOT
+	enum boot_src src = get_boot_src();
+#endif
+	char buf[64];
+#ifndef CONFIG_SD_BOOT
+	u8 sw;
+#endif
+
+	puts("Board: LS1046AQDS, boot from ");
+
+#ifdef CONFIG_TFABOOT
+	if (src == BOOT_SOURCE_SD_MMC)
+		puts("SD\n");
+	else {
+#endif
+
+#ifdef CONFIG_SD_BOOT
+	puts("SD\n");
+#else
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("PromJet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else if (sw == 0xF)
+		printf("QSPI\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+#ifdef CONFIG_TFABOOT
+	}
+#endif
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
+	       QIXIS_READ(id), QIXIS_READ(arch));
+
+	printf("FPGA:  v%d (%s), build %d\n",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+
+	return 0;
+}
+
+bool if_board_diff_clk(void)
+{
+	u8 diff_conf = QIXIS_READ(brdcfg[11]);
+
+	return diff_conf & 0x40;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0f) {
+	case QIXIS_SYSCLK_64:
+		return 64000000;
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	if (if_board_diff_clk())
+		return get_board_sys_clk();
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+
+	return 66666666;
+}
+
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
+{
+	return gd->bus_clk;
+}
+#endif
+
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
+{
+	int ret;
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	/*
+	 * When resuming from deep sleep, the I2C channel may not be
+	 * in the default channel. So, switch to the default channel
+	 * before accessing DDR SPD.
+	 *
+	 * PCA9547 mount on I2C1 bus
+	 */
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
+	fsl_initdram();
+#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
+	defined(CONFIG_SPL_BUILD)
+	/* This will break-before-make MMU for DDR */
+	update_early_mmu_table();
+#endif
+
+	return 0;
+}
+
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+	return select_i2c_ch_pca9547(channel, 0);
+}
+
+int board_early_init_f(void)
+{
+	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	u32 usb_pwrfault;
+#endif
+#ifdef CONFIG_LPUART
+	u8 uart;
+#endif
+
+	/*
+	 * Enable secure system counter for timer
+	 */
+	out_le32(cntcr, 0x1);
+
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
+	fsl_lsch2_early_init_f();
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+	out_be32(&scfg->rcwpmuxcr0, 0x3333);
+	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+	usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+			SCFG_USBPWRFAULT_USB3_SHIFT) |
+			(SCFG_USBPWRFAULT_DEDICATED <<
+			SCFG_USBPWRFAULT_USB2_SHIFT) |
+			(SCFG_USBPWRFAULT_SHARED <<
+			SCFG_USBPWRFAULT_USB1_SHIFT);
+	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+
+#ifdef CONFIG_LPUART
+	/* We use lpuart0 as system console */
+	uart = QIXIS_READ(brdcfg[14]);
+	uart &= ~CFG_UART_MUX_MASK;
+	uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+	QIXIS_WRITE(brdcfg[14], uart);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+/* determine if it is a warm boot */
+bool is_warm_boot(void)
+{
+#define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
+		return 1;
+
+	return 0;
+}
+#endif
+
+int config_board_mux(int ctrl_type)
+{
+	u8 reg14;
+
+	reg14 = QIXIS_READ(brdcfg[14]);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_GPIO:
+		reg14 = (reg14 & (~0x6)) | 0x2;
+		break;
+	default:
+		puts("Unsupported mux interface type\n");
+		return -1;
+	}
+
+	QIXIS_WRITE(brdcfg[14], reg14);
+
+	return 0;
+}
+
+int config_serdes_mux(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	if (hwconfig("gpio"))
+		config_board_mux(MUX_TYPE_GPIO);
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
+
+#ifdef CONFIG_SYS_FSL_SERDES
+	config_serdes_mux();
+#endif
+
+	if (adjust_vdd(0))
+		printf("Warning: Adjusting core voltage failed.\n");
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+#ifdef CONFIG_NXP_ESBC
+	/*
+	 * In case of Secure Boot, the IBR configures the SMMU
+	 * to allow only Secure transactions.
+	 * SMMU must be reset in bypass mode.
+	 * Set the ClientPD bit and Clear the USFCFG Bit
+	 */
+	u32 val;
+	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_SCR0, val);
+	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+	u8 reg;
+
+	/* fixup DT for the two DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
+	fdt_fixup_fman_ethernet(blob);
+#endif
+	fdt_fixup_board_enet(blob);
+#endif
+
+	fdt_fixup_icid(blob);
+
+	reg = QIXIS_READ(brdcfg[0]);
+	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	/* Disable IFC if QSPI is enabled */
+	if (reg == 0xF)
+		do_fixup_by_compat(blob, "fsl,ifc",
+				   "status", "disabled", 8 + 1, 1);
+
+	return 0;
+}
+#endif
+
+u8 flash_read8(void *addr)
+{
+	return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+	__raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 val = __raw_readw(addr);
+
+	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
+
+#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+void *env_sf_get_env_addr(void)
+{
+	return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+}
+#endif
diff --git a/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_pbi.cfg b/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
new file mode 100644
index 000000000..5a6b7b84a
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
@@ -0,0 +1,17 @@
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Alt base register
+09570158 00001000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#Serdes SATA
+09eb1300 80104e20
+09eb08dc 00502880
+#flush PBI data
+096100c0 000fffff
diff --git a/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_qixis.h b/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_qixis.h
new file mode 100644
index 000000000..f371056e3
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_qixis.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __LS1046AQDS_QIXIS_H__
+#define __LS1046AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1046AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+#define QIXIS_SYSCLK_64			0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg b/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
new file mode 100644
index 000000000..b5fc08ce2
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0c150010 0e000000 00000000 00000000
+11335559 40005012 e0116000 c1000000
+00000000 00000000 00000000 00038800
+00000000 01001101 00000096 00000001
diff --git a/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg b/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
new file mode 100644
index 000000000..59d24d679
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable IFC; disable QSPI
+0c150010 0e000000 00000000 00000000
+11335559 40005012 60040000 c1000000
+00000000 00000000 00000000 00038800
+00000000 01001101 00000096 00000001
diff --git a/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg b/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
new file mode 100644
index 000000000..9401a6f0f
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable QSPI; disable IFC
+0c150010 0e000000 00000000 00000000
+11335559 40005012 60040000 c1000000
+00000000 00000000 00000000 00038800
+20124000 01001101 00000096 00000001
diff --git a/roms/u-boot/board/freescale/ls1046ardb/Kconfig b/roms/u-boot/board/freescale/ls1046ardb/Kconfig
new file mode 100644
index 000000000..4c31e0e88
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/Kconfig
@@ -0,0 +1,31 @@
+
+if TARGET_LS1046ARDB
+
+config SYS_BOARD
+	default "ls1046ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1046ardb"
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+	hex "PPA Firmware Addr"
+	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA Firmware HDR Addr"
+	default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+endif
diff --git a/roms/u-boot/board/freescale/ls1046ardb/MAINTAINERS b/roms/u-boot/board/freescale/ls1046ardb/MAINTAINERS
new file mode 100644
index 000000000..efdea22bd
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/MAINTAINERS
@@ -0,0 +1,16 @@
+LS1046A BOARD
+M:	Mingkai Hu <mingkai.hu@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1046ardb/
+F:	board/freescale/ls1046ardb/ls1046ardb.c
+F:	include/configs/ls1046ardb.h
+F:	configs/ls1046ardb_qspi_defconfig
+F:	configs/ls1046ardb_qspi_spl_defconfig
+F:	configs/ls1046ardb_sdcard_defconfig
+F:	configs/ls1046ardb_emmc_defconfig
+F:	configs/ls1046ardb_tfa_defconfig
+F:	configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+F:	configs/ls1046ardb_SECURE_BOOT_defconfig
+F:	configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+F:	configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/ls1046ardb/Makefile b/roms/u-boot/board/freescale/ls1046ardb/Makefile
new file mode 100644
index 000000000..1c13ed6b6
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2016 Freescale Semiconductor
+
+obj-y += ddr.o
+obj-y += ls1046ardb.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_NET) += eth.o
+obj-y += cpld.o
+endif
diff --git a/roms/u-boot/board/freescale/ls1046ardb/README b/roms/u-boot/board/freescale/ls1046ardb/README
new file mode 100644
index 000000000..a38c9d483
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/README
@@ -0,0 +1,76 @@
+Overview
+--------
+The LS1046A Reference Design Board (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1046A
+LayerScape Architecture processor. The LS1046ARDB provides SW development
+platform for the Freescale LS1046A processor series, with a complete
+debugging environment. The LS1046A RDB is lead-free and RoHS-compliant.
+
+LS1046A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
+SoC overview.
+
+ LS1046ARDB board Overview
+ -----------------------
+ - SERDES1 Connections, 4 lanes supporting:
+      - Lane0: XFI with x1 RJ45 connector
+      - Lane1: XFI Cage
+      - Lane2: SGMII.5
+      - Lane3: SGMII.6
+ - SERDES2 Connections, 4 lanes supporting:
+      - Lane0: PCIe1 with miniPCIe slot
+      - Lane1: PCIe2 with PCIe x2 slot
+      - Lane2: PCIe3 with PCIe x4 slot
+      - Lane3: SATA
+ - DDR Controller
+     - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
+ -IFC/Local Bus
+    - One 512 MB NAND flash with ECC support
+    - CPLD connection
+ - USB 3.0
+    - one Type A port, one Micro-AB port
+ - SDHC: connects directly to a full SD/MMC slot
+ - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
+ - 4 I2C controllers
+ - UART
+   - Two 4-pin serial ports at up to 115.2 Kbit/s
+   - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address	 End Address	 Description		Size
+0x00_0000_0000 - 0x00_000F_FFFF  Secure Boot ROM	1MB
+0x00_0100_0000 - 0x00_0FFF_FFFF  CCSRBAR		240MB
+0x00_1000_0000 - 0x00_1000_FFFF  OCRAM0 		64KB
+0x00_1001_0000 - 0x00_1001_FFFF  OCRAM1 		64KB
+0x00_2000_0000 - 0x00_20FF_FFFF  DCSR			16MB
+0x00_7E80_0000 - 0x00_7E80_FFFF  IFC - NAND Flash	64KB
+0x00_7FB0_0000 - 0x00_7FB0_0FFF  IFC - CPLD		4KB
+0x00_8000_0000 - 0x00_FFFF_FFFF  DRAM1			2GB
+0x05_0000_0000 - 0x05_07FF_FFFF  QMAN S/W Portal	128M
+0x05_0800_0000 - 0x05_0FFF_FFFF  BMAN S/W Portal	128M
+0x08_8000_0000 - 0x09_FFFF_FFFF  DRAM2			6GB
+0x40_0000_0000 - 0x47_FFFF_FFFF  PCI Express1		32G
+0x48_0000_0000 - 0x4F_FFFF_FFFF  PCI Express2		32G
+0x50_0000_0000 - 0x57_FFFF_FFFF  PCI Express3		32G
+
+QSPI flash map:
+Start Address    End Address     Description		Size
+0x00_4000_0000 - 0x00_400F_FFFF  RCW + PBI		1MB
+0x00_4010_0000 - 0x00_402F_FFFF  U-Boot 		2MB
+0x00_4030_0000 - 0x00_403F_FFFF  U-Boot Env		1MB
+0x00_4040_0000 - 0x00_405F_FFFF  PPA			2MB
+0x00_4060_0000 - 0x00_408F_FFFF  Secure boot header
+				 + bootscript		3MB
+0x00_4090_0000 - 0x00_4093_FFFF  FMan ucode		256KB
+0x00_4094_0000 - 0x00_4097_FFFF  QE/uQE firmware	256KB
+0x00_4098_0000 - 0x00_40FF_FFFF  Reserved		6MB
+0x00_4100_0000 - 0x00_43FF_FFFF  FIT Image		48MB
+
+Booting Options
+---------------
+a) QSPI boot
+b) SD boot
+c) eMMC boot
diff --git a/roms/u-boot/board/freescale/ls1046ardb/cpld.c b/roms/u-boot/board/freescale/ls1046ardb/cpld.c
new file mode 100644
index 000000000..548601a5a
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/cpld.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * Freescale LS1046ARDB board-specific CPLD controlling supports.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	out_8(p + reg, value);
+}
+
+/* Set the boot bank to the alternate bank */
+void cpld_set_altbank(void)
+{
+	u16 reg = CPLD_CFG_RCW_SRC_QSPI;
+	u8 reg4 = CPLD_READ(soft_mux_on);
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
+	u8 reg7 = CPLD_READ(vbank);
+
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
+
+	reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
+	CPLD_WRITE(vbank, reg7);
+
+	CPLD_WRITE(system_rst, 1);
+}
+
+/* Set the boot bank to the default bank */
+void cpld_set_defbank(void)
+{
+	u16 reg = CPLD_CFG_RCW_SRC_QSPI;
+	u8 reg4 = CPLD_READ(soft_mux_on);
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
+
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
+
+	CPLD_WRITE(vbank, 0);
+
+	CPLD_WRITE(system_rst, 1);
+}
+
+void cpld_set_sd(void)
+{
+	u16 reg = CPLD_CFG_RCW_SRC_SD;
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
+
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
+
+	CPLD_WRITE(system_rst, 1);
+}
+
+void cpld_select_core_volt(bool en_0v9)
+{
+	u8 reg17 = en_0v9;
+
+	CPLD_WRITE(vdd_en, 1);
+	CPLD_WRITE(vdd_sel, reg17);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+	printf("cpld_ver	= %x\n", CPLD_READ(cpld_ver));
+	printf("cpld_ver_sub	= %x\n", CPLD_READ(cpld_ver_sub));
+	printf("pcba_ver	= %x\n", CPLD_READ(pcba_ver));
+	printf("soft_mux_on	= %x\n", CPLD_READ(soft_mux_on));
+	printf("cfg_rcw_src1	= %x\n", CPLD_READ(cfg_rcw_src1));
+	printf("cfg_rcw_src2	= %x\n", CPLD_READ(cfg_rcw_src2));
+	printf("vbank		= %x\n", CPLD_READ(vbank));
+	printf("sysclk_sel	= %x\n", CPLD_READ(sysclk_sel));
+	printf("uart_sel	= %x\n", CPLD_READ(uart_sel));
+	printf("sd1refclk_sel	= %x\n", CPLD_READ(sd1refclk_sel));
+	printf("rgmii_1588_sel	= %x\n", CPLD_READ(rgmii_1588_sel));
+	printf("1588_clk_sel	= %x\n", CPLD_READ(reg_1588_clk_sel));
+	printf("status_led	= %x\n", CPLD_READ(status_led));
+	printf("sd_emmc		= %x\n", CPLD_READ(sd_emmc));
+	printf("vdd_en		= %x\n", CPLD_READ(vdd_en));
+	printf("vdd_sel		= %x\n", CPLD_READ(vdd_sel));
+	putc('\n');
+}
+#endif
+
+void cpld_rev_bit(unsigned char *value)
+{
+	u8 rev_val, val;
+	int i;
+
+	val = *value;
+	rev_val = val & 1;
+	for (i = 1; i <= 7; i++) {
+		val >>= 1;
+		rev_val <<= 1;
+		rev_val |= val & 1;
+	}
+
+	*value = rev_val;
+}
+
+int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int rc = 0;
+
+	if (argc <= 1)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		if (strcmp(argv[2], "altbank") == 0)
+			cpld_set_altbank();
+		else if (strcmp(argv[2], "sd") == 0)
+			cpld_set_sd();
+		else
+			cpld_set_defbank();
+#ifdef DEBUG
+	} else if (strcmp(argv[1], "dump") == 0) {
+		cpld_dump_regs();
+#endif
+	} else {
+		rc = cmd_usage(cmdtp);
+	}
+
+	return rc;
+}
+
+U_BOOT_CMD(
+	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+	"Reset the board or alternate bank",
+	"reset: reset to default bank\n"
+	"cpld reset altbank: reset to alternate bank\n"
+	"cpld reset sd: reset to boot from SD card\n"
+#ifdef DEBUG
+	"cpld dump - display the CPLD registers\n"
+#endif
+);
diff --git a/roms/u-boot/board/freescale/ls1046ardb/cpld.h b/roms/u-boot/board/freescale/ls1046ardb/cpld.h
new file mode 100644
index 000000000..e87044f5c
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/cpld.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor
+ */
+
+#ifndef __CPLD_H__
+#define __CPLD_H__
+
+/*
+ * CPLD register set of LS1046ARDB board-specific.
+ * CPLD Revision:  V2.1
+ */
+struct cpld_data {
+	u8 cpld_ver;		/* 0x0 - CPLD Major Revision Register */
+	u8 cpld_ver_sub;	/* 0x1 - CPLD Minor Revision Register */
+	u8 pcba_ver;		/* 0x2 - PCBA Revision Register */
+	u8 system_rst;		/* 0x3 - system reset register */
+	u8 soft_mux_on;		/* 0x4 - Switch Control Enable Register */
+	u8 cfg_rcw_src1;	/* 0x5 - RCW Source Location POR Regsiter 1 */
+	u8 cfg_rcw_src2;	/* 0x6 - RCW Source Location POR Regsiter 2 */
+	u8 vbank;		/* 0x7 - QSPI Flash Bank Setting Register */
+	u8 sysclk_sel;		/* 0x8 - System clock POR Register */
+	u8 uart_sel;		/* 0x9 - UART1 Connection Control Register */
+	u8 sd1refclk_sel;	/* 0xA - */
+	u8 rgmii_1588_sel;	/* 0xB - */
+	u8 reg_1588_clk_sel;	/* 0xC - */
+	u8 status_led;		/* 0xD - */
+	u8 global_rst;		/* 0xE - */
+	u8 sd_emmc;             /* 0xF - SD/EMMC Interface Control Regsiter */
+	u8 vdd_en;              /* 0x10 - VDD Voltage Control Enable Register */
+	u8 vdd_sel;             /* 0x11 - VDD Voltage Control Register */
+};
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+void cpld_rev_bit(unsigned char *value);
+void cpld_select_core_volt(bool en_0v9);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)  \
+	cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_SW_MUX_BANK_SEL	0x40
+#define CPLD_BANK_SEL_MASK	0x07
+#define CPLD_BANK_SEL_ALTBANK	0x04
+#define CPLD_CFG_RCW_SRC_QSPI	0x044
+#define CPLD_CFG_RCW_SRC_SD	0x040
+#endif
diff --git a/roms/u-boot/board/freescale/ls1046ardb/ddr.c b/roms/u-boot/board/freescale/ls1046ardb/ddr.c
new file mode 100644
index 000000000..befb556bd
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/ddr.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/global_data.h>
+#include "ddr.h"
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
+#include <log.h>
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[0];
+	else
+		pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for %lu MT/s\n",
+		       ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+	popts->data_bus_width = 0;	/* 64-bit data bus */
+	popts->bstopre = 0;		/* enable auto precharge */
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+			  DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x61;
+}
+
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
+#else
+int fsl_initdram(void)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+#else
+	puts("Initializing DDR....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+#endif
+
+	erratum_a008850_post();
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/ls1046ardb/ddr.h b/roms/u-boot/board/freescale/ls1046ardb/ddr.h
new file mode 100644
index 000000000..05baef232
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/ddr.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+void erratum_a008850_post(void);
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2300, 0, 8,     7, 0x08090A0E, 0x1011120C,},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1666, 0, 0x8,     0x0D, 0x0C0B0A08, 0x0A0B0C08,},
+	{2,  1900, 0, 0x8,     0x0E, 0x0D0C0B09, 0x0B0C0D09,},
+	{2,  2300, 0, 0xa,     0x12, 0x100F0D0C, 0x0E0F100C,},
+	{1,  1666, 0, 0x8,     0x0D, 0x0C0B0A08, 0x0A0B0C08,},
+	{1,  1900, 0, 0x8,     0x0E, 0x0D0C0B09, 0x0B0C0D09,},
+	{1,  2300, 0, 0xa,     0x12, 0x100F0D0C, 0x0E0F100C,},
+	{}
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+};
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls1046ardb/eth.c b/roms/u-boot/board/freescale/ls1046ardb/eth.c
new file mode 100644
index 000000000..4905302d8
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/eth.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+#include <common.h>
+#include <fdt_support.h>
+#include <net.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_dtsec.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	int i;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	struct mii_dev *dev;
+	u32 srds_s1;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	/* Set the two on-board RGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+	/* Set the two on-board SGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
+
+	/* Set the on-board AQ PHY address */
+	fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+
+	switch (srds_s1) {
+	case 0x1133:
+		break;
+	default:
+		printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
+		       srds_s1);
+		break;
+	}
+
+	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
+		fm_info_set_mdio(i, dev);
+
+	/* XFI on lane A, MAC 9 */
+	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+	fm_info_set_mdio(FM1_10GEC1, dev);
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_FMAN_ENET
+int fdt_update_ethernet_dt(void *blob)
+{
+	u32 srds_s1;
+	int i, prop;
+	int offset, nodeoff;
+	const char *path;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	/* Cycle through all aliases */
+	for (prop = 0; ; prop++) {
+		const char *name;
+
+		/* FDT might have been edited, recompute the offset */
+		offset = fdt_first_property_offset(blob,
+						   fdt_path_offset(blob,
+								   "/aliases")
+						   );
+		/* Select property number 'prop' */
+		for (i = 0; i < prop; i++)
+			offset = fdt_next_property_offset(blob, offset);
+
+		if (offset < 0)
+			break;
+
+		path = fdt_getprop_by_offset(blob, offset, &name, NULL);
+		nodeoff = fdt_path_offset(blob, path);
+
+		switch (srds_s1) {
+		case 0x1133:
+			if (!strcmp(name, "ethernet0"))
+				fdt_status_disabled(blob, nodeoff);
+
+			if (!strcmp(name, "ethernet1"))
+				fdt_status_disabled(blob, nodeoff);
+		break;
+		default:
+			printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n",
+			       __func__, srds_s1);
+		break;
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb.c b/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb.c
new file mode 100644
index 000000000..93ef903f2
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ppa.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <power/mc34vr500_pmic.h>
+#include "cpld.h"
+#include <fsl_sec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+int checkboard(void)
+{
+	static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
+	u8 cfg_rcw_src1, cfg_rcw_src2;
+	u16 cfg_rcw_src;
+	u8 sd1refclk_sel;
+
+	puts("Board: LS1046ARDB, boot from ");
+
+	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
+	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
+	cpld_rev_bit(&cfg_rcw_src1);
+	cfg_rcw_src = cfg_rcw_src1;
+	cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
+
+	if (cfg_rcw_src == 0x44)
+		printf("QSPI vBank %d\n", CPLD_READ(vbank));
+	else if (cfg_rcw_src == 0x40)
+		puts("SD\n");
+	else
+		puts("Invalid setting of SW5\n");
+
+	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
+	       CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
+
+	puts("SERDES Reference Clocks:\n");
+	sd1refclk_sel = CPLD_READ(sd1refclk_sel);
+	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_NXP_ESBC
+	/*
+	 * In case of Secure Boot, the IBR configures the SMMU
+	 * to allow only Secure transactions.
+	 * SMMU must be reset in bypass mode.
+	 * Set the ClientPD bit and Clear the USFCFG Bit
+	 */
+	u32 val;
+	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_SCR0, val);
+	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+	/* invert AQR105 IRQ pins polarity */
+	out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
+
+	return 0;
+}
+
+int board_setup_core_volt(u32 vdd)
+{
+	bool en_0v9;
+
+	en_0v9 = (vdd == 900) ? true : false;
+	cpld_select_core_volt(en_0v9);
+
+	return 0;
+}
+
+int get_serdes_volt(void)
+{
+	return mc34vr500_get_sw_volt(SW4);
+}
+
+int set_serdes_volt(int svdd)
+{
+	return mc34vr500_set_sw_volt(SW4, svdd);
+}
+
+int power_init_board(void)
+{
+	int ret;
+
+	ret = power_mc34vr500_init(0);
+	if (ret)
+		return ret;
+
+	setup_chip_volt();
+
+	return 0;
+}
+
+void config_board_mux(void)
+{
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	u32 usb_pwrfault;
+
+	/* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
+	out_be32(&scfg->rcwpmuxcr0, 0x3300);
+	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+	usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+			SCFG_USBPWRFAULT_USB3_SHIFT) |
+			(SCFG_USBPWRFAULT_DEDICATED <<
+			SCFG_USBPWRFAULT_USB2_SHIFT) |
+			(SCFG_USBPWRFAULT_SHARED <<
+			SCFG_USBPWRFAULT_USB1_SHIFT);
+	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	config_board_mux();
+	return 0;
+}
+#endif
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	/* fixup DT for the two DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
+	fdt_fixup_fman_ethernet(blob);
+#endif
+#endif
+
+	fdt_fixup_icid(blob);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg b/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
new file mode 100644
index 000000000..547821752
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
@@ -0,0 +1,22 @@
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#Serdes SATA
+09eb1300 80104e20
+09eb08dc 00502880
+#PEX gen3 link
+09570158 00000300
+89400890 01048000
+89500890 01048000
+89600890 01048000
+#Alt base register
+09570158 00001000
+#flush PBI data
+096100c0 000fffff
diff --git a/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg b/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
new file mode 100644
index 000000000..735d46c9f
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
@@ -0,0 +1,26 @@
+#QSPI clk
+0957015c 40100000
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#Serdes SATA
+09eb1300 80104e20
+09eb08dc 00502880
+#PEX gen3 link
+09570158 00000300
+89400890 01048000
+89500890 01048000
+89600890 01048000
+#Alt base register
+09570158 00001000
+#flush PBI data
+096100c0 000fffff
+#Change endianness
+09550000 000f400c
diff --git a/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
new file mode 100644
index 000000000..ccedf87e8
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+0c150012 0e000000 00000000 00000000
+11335559 40000012 60040000 c1000000
+00000000 00000000 00000000 00238800
+20124000 00003000 00000096 00000001
diff --git a/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg b/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
new file mode 100644
index 000000000..7b9be0ad3
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+0c150010 0e000000 00000000 00000000
+11335559 40005012 40025000 c1000000
+00000000 00000000 00000000 00238800
+20124000 00003101 00000096 00000001
diff --git a/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg b/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
new file mode 100644
index 000000000..d3b152282
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+0c150012 0e000000 00000000 00000000
+11335559 40005012 60040000 c1000000
+00000000 00000000 00000000 00238800
+20124000 00003101 00000096 00000001
diff --git a/roms/u-boot/board/freescale/ls1088a/Kconfig b/roms/u-boot/board/freescale/ls1088a/Kconfig
new file mode 100644
index 000000000..8bb828e3f
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1088a/Kconfig
@@ -0,0 +1,61 @@
+if TARGET_LS1088AQDS
+
+config SYS_BOARD
+	default "ls1088a"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1088aqds"
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+        hex "PPA Firmware Addr"
+	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA Firmware HDR Addr"
+	default 0x20680000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+endif
+
+if TARGET_LS1088ARDB
+
+config SYS_BOARD
+	default "ls1088a"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1088ardb"
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+        hex "PPA Firmware Addr"
+	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA Firmware HDR Addr"
+	default 0x20680000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+endif
diff --git a/roms/u-boot/board/freescale/ls1088a/MAINTAINERS b/roms/u-boot/board/freescale/ls1088a/MAINTAINERS
new file mode 100644
index 000000000..5c7925a95
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1088a/MAINTAINERS
@@ -0,0 +1,37 @@
+LS1088ARDB BOARD
+M:	Ashish Kumar <Ashish.Kumar@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1088a/
+F:	include/configs/ls1088ardb.h
+F:	configs/ls1088ardb_qspi_defconfig
+F:	configs/ls1088ardb_sdcard_qspi_defconfig
+F:	configs/ls1088ardb_tfa_defconfig
+F:	configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+
+LS1088AQDS BOARD
+M:	Ashish Kumar <Ashish.Kumar@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1088a/
+F:	include/configs/ls1088aqds.h
+F:	configs/ls1088aqds_qspi_defconfig
+F:	configs/ls1088aqds_sdcard_qspi_defconfig
+F:	configs/ls1088aqds_defconfig
+F:	configs/ls1088aqds_sdcard_ifc_defconfig
+F:	configs/ls1088aqds_tfa_defconfig
+
+LS1088AQDS_QSPI_SECURE_BOOT BOARD
+M:	Udit Agarwal <udit.agarwal@nxp.com>
+S:	Maintained
+F:	configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+
+LS1088ARDB_QSPI_SECURE_BOOT BOARD
+M:	Udit Agarwal <udit.agarwal@nxp.com>
+S:	Maintained
+F:	configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+
+LS1088ARDB_SD_SECURE_BOOT BOARD
+M:	Udit Agarwal <udit.agarwal@nxp.com>
+S:	Maintained
+F:	configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/ls1088a/Makefile b/roms/u-boot/board/freescale/ls1088a/Makefile
new file mode 100644
index 000000000..c2b0e7dc0
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1088a/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2017 NXP
+
+obj-y += ls1088a.o
+obj-y += ddr.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
+obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o
+endif
diff --git a/roms/u-boot/board/freescale/ls1088a/README b/roms/u-boot/board/freescale/ls1088a/README
new file mode 100644
index 000000000..aa0fb6ac6
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1088a/README
@@ -0,0 +1,145 @@
+Overview
+--------
+The LS1088A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports ARM SoC LS1088A and its
+derivatives.
+
+
+LS1088A SoC Overview
+--------------------------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+
+RDB Default Switch Settings (1: ON; 0: OFF)
+-------------------------------------------
+
+For QSPI Boot
+SW1 0011 0001
+SW2 x100 0000
+SW3 1111 0010
+SW4 1001 0011
+SW5 1111 0000
+
+For SD Boot
+SW1 0010 0000
+SW2 0100 0000
+SW3 1111 0010
+SW4 1001 0011
+SW5 1111 0000
+
+For eMMC Boot
+SW1 0010 0000
+SW2 1100 0000
+SW3 1111 0010
+SW4 1001 0011
+SW5 1111 0000
+
+Alternately you can use this command to switch from QSPI to SD
+
+=> i2c mw 66 0x60 0x20; i2c mw 66 10 10;i2c mw 66 10 21
+
+ LS1088ARDB board Overview
+ -------------------------
+ - SERDES Connections, 16 lanes supporting:
+      - PCI Express - 3.0
+      - SATA 3.0
+      - XFI
+      - QSGMII
+ - DDR Controller
+     - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
+       chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
+       with FSL refernce software is 2100MT/s
+ - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
+ - IFC/Local Bus
+    - One 2 GB NAND flash with ECC support, not as boot source
+    - CPLD of size 2K
+ - USB 3.0
+    - Two high speed USB 3.0 ports
+    - First USB 3.0 port configured as Host with Type-A connector
+    - Second USB 3.0 port configured as OTG with micro-AB connector
+ - SDHC/eMMC
+    - SDHC slot and onboard eMMC are muxed together
+ - 4 I2C controllers
+ - Two SATA onboard connectors
+ - 2 UART
+ - JTAG support
+ - QSPI emulator support
+ - TDM riser support
+
+QDS Default Switch Settings (1: ON; 0: OFF)
+-------------------------------------------
+
+For 16b IFC-NOR
+SW1 0001 0010
+SW2 x110 1111
+
+For QSPI Boot
+SW1 0011 0001
+SW2 0110 1111
+
+For SD Boot
+SW1 0010 0000
+SW2 0110 1111
+
+For eMMC Boot
+SW1 0010 0000
+SW2 1110 1111
+
+For I2C (ext. addr.)
+SW1 0010 0100
+SW2 1110 1111
+
+SW3 to SW12 are identical for all boot source
+
+SW3 0010 0100
+SW4 0010 0000
+SW5 1110 0111
+SW6 1110 1000
+SW7 0001 1101
+SW8 0000 1101
+SW9 1100 1010
+SW10 1110 1000
+SW11 1111 0100
+SW12 1111 1111
+
+ LS1088AQDS board Overview
+ -------------------------
+ - SERDES Connections, 16 lanes supporting:
+      - PCI Express - 3.0
+      - SATA 3.0
+      - 2 XFI
+      - QSGMII, SGMII with help for Riser card
+      - 2 RGMII
+      - 5 slot for Riser card or PCIe NIC
+ - DDR Controller
+     - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
+       chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
+       with FSL refernce software is 2100MT/s
+ - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
+ - IFC/Local Bus
+    - One 2 GB NAND flash with ECC support, not as boot source
+    - CPLD of size 2K
+ - USB 3.0
+    - Two high speed USB 3.0 ports
+    - First USB 3.0 port configured as Host with Type-A connector
+    - Second USB 3.0 port configured as OTG with micro-AB connector
+ - SDHC/eMMC
+    - SDHC/eMMC slot via adaptor
+ - 4 I2C controllers
+ - Two SATA onboard connectors
+ - 2 UART
+ - JTAG support
+ - DSPI
+ - PROMJET support
+ - QSPI emulator support
+ - TDM riser support
+
+QSPI flash memory map valid for both QDS and RDB
+  Image                               Flash Offset
+ RCW+PBI                             0x00000000
+ Boot firmware (U-Boot)              0x00100000
+ Boot firmware Environment           0x00300000
+ PPA firmware                        0x00400000
+ DPAA2 MC                            0x00A00000
+ DPAA2 DPL                           0x00D00000
+ DPAA2 DPC                           0x00E00000
+ Kernel.itb                          0x01000000
diff --git a/roms/u-boot/board/freescale/ls1088a/ddr.c b/roms/u-boot/board/freescale/ls1088a/ddr.c
new file mode 100644
index 000000000..995c42960
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1088a/ddr.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <log.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/clock.h>
+#include <asm/global_data.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts)
+{
+	int vdd;
+
+	vdd = get_core_volt_from_fuse();
+	/* Nothing to do for silicons doesn't support VID */
+	if (vdd < 0)
+		return;
+
+	if (vdd == 900) {
+		popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN;
+		debug("VID: configure DDR to support 900 mV\n");
+	}
+}
+#endif
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	/*
+	 * we use identical timing for all slots. If needed, change the code
+	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+	 */
+	pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for %lu MT/s\n",
+		       ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+
+
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* Enable DDR hashing */
+	popts->addr_hash = 1;
+
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+	fsl_ddr_setup_0v9_volt(popts);
+#endif
+
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+			  DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
+}
+
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
+#else
+int fsl_initdram(void)
+{
+	puts("Initializing DDR....using SPD\n");
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	gd->ram_size = fsl_ddr_sdram_size();
+#else
+	gd->ram_size = fsl_ddr_sdram();
+#endif
+	return 0;
+}
+#endif /* CONFIG_TFABOOT */
diff --git a/roms/u-boot/board/freescale/ls1088a/ddr.h b/roms/u-boot/board/freescale/ls1088a/ddr.h
new file mode 100644
index 000000000..b35c4ae2d
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1088a/ddr.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef __LS1088A_DDR_H__
+#define __LS1088A_DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+#if defined(CONFIG_TARGET_LS1088ARDB)
+
+	{2,  1666, 0, 8,     8, 0x090A0B0E, 0x0F10110D,},
+	{2,  1900, 0, 8,     9, 0x0A0B0C10, 0x1112140E,},
+	{2,  2300, 0, 8,     9, 0x0A0C0E11, 0x1214160F,},
+	{}
+#elif defined(CONFIG_TARGET_LS1088AQDS)
+	{2,  1666, 0, 8,     8, 0x0A0A0C0E, 0x0F10110C,},
+	{2,  1900, 0, 8,     9, 0x0A0B0C10, 0x1112140E,},
+	{2,  2300, 0, 4,     9, 0x0A0C0D11, 0x1214150E,},
+	{}
+
+#endif
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+#endif
diff --git a/roms/u-boot/board/freescale/ls1088a/eth_ls1088aqds.c b/roms/u-boot/board/freescale/ls1088a/eth_ls1088aqds.c
new file mode 100644
index 000000000..140733de6
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1088a/eth_ls1088aqds.c
@@ -0,0 +1,835 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <log.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+#include <hwconfig.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include <linux/delay.h>
+
+#include "../common/qixis.h"
+
+#include "ls1088a_qixis.h"
+
+#ifndef CONFIG_DM_ETH
+#ifdef CONFIG_FSL_MC_ENET
+
+#define SFP_TX		0
+
+ /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
+ *   Bank 1 -> Lanes A, B, C, D,
+ *   Bank 2 -> Lanes A,B, C, D,
+ */
+
+ /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
+  * means that the mapping must be determined dynamically, or that the lane
+  * maps to something other than a board slot.
+  */
+
+static u8 lane_to_slot_fsm1[] = {
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
+ * housed.
+ */
+
+static int xqsgii_riser_phy_addr[] = {
+	XQSGMII_CARD_PHY1_PORT0_ADDR,
+	XQSGMII_CARD_PHY2_PORT0_ADDR,
+	XQSGMII_CARD_PHY3_PORT0_ADDR,
+	XQSGMII_CARD_PHY4_PORT0_ADDR,
+	XQSGMII_CARD_PHY3_PORT2_ADDR,
+	XQSGMII_CARD_PHY1_PORT2_ADDR,
+	XQSGMII_CARD_PHY4_PORT2_ADDR,
+	XQSGMII_CARD_PHY2_PORT2_ADDR,
+};
+
+static int sgmii_riser_phy_addr[] = {
+	SGMII_CARD_PORT1_PHY_ADDR,
+	SGMII_CARD_PORT2_PHY_ADDR,
+	SGMII_CARD_PORT3_PHY_ADDR,
+	SGMII_CARD_PORT4_PHY_ADDR,
+};
+
+/* Slot2 does not have EMI connections */
+#define EMI_NONE	0xFF
+#define EMI1_RGMII1	0
+#define EMI1_RGMII2	1
+#define EMI1_SLOT1	2
+
+static const char * const mdio_names[] = {
+	"LS1088A_QDS_MDIO0",
+	"LS1088A_QDS_MDIO1",
+	"LS1088A_QDS_MDIO2",
+	DEFAULT_WRIOP_MDIO2_NAME,
+};
+
+struct ls1088a_qds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+struct reg_pair {
+	uint addr;
+	u8 *val;
+};
+
+static void sgmii_configure_repeater(int dpmac)
+{
+	struct mii_dev *bus;
+	uint8_t a = 0xf;
+	int i, j, k, ret;
+	unsigned short value;
+	const char *dev = "LS1088A_QDS_MDIO2";
+	int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
+	int i2c_phy_addr = 0;
+	int phy_addr = 0;
+
+	uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
+	uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
+	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+
+	u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+	struct reg_pair reg_pair[10] = {
+		{6, &reg_val[0]}, {4, &reg_val[1]},
+		{8, &reg_val[2]}, {0xf, NULL},
+		{0x11, NULL}, {0x16, NULL},
+		{0x18, NULL}, {0x23, &reg_val[3]},
+		{0x2d, &reg_val[4]}, {4, &reg_val[5]},
+	};
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *udev;
+#endif
+
+	/* Set I2c to Slot 1 */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+	ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+	if (!ret)
+		ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+	if (ret)
+		goto error;
+
+	switch (dpmac) {
+	case 1:
+		i2c_phy_addr = i2c_addr[1];
+		phy_addr = 4;
+		break;
+	case 2:
+		i2c_phy_addr = i2c_addr[0];
+		phy_addr = 0;
+		break;
+	case 3:
+		i2c_phy_addr = i2c_addr[3];
+		phy_addr = 0xc;
+		break;
+	case 7:
+		i2c_phy_addr = i2c_addr[2];
+		phy_addr = 8;
+		break;
+	}
+
+	/* Check the PHY status */
+	ret = miiphy_set_current_dev(dev);
+	if (ret > 0)
+		goto error;
+
+	bus = mdio_get_current_dev();
+	debug("Reading from bus %s\n", bus->name);
+
+	ret = miiphy_write(dev, phy_addr, 0x1f, 3);
+	if (ret > 0)
+		goto error;
+
+	mdelay(10);
+	ret = miiphy_read(dev, phy_addr, 0x11, &value);
+	if (ret > 0)
+			goto error;
+
+	mdelay(10);
+
+	if ((value & 0xfff) == 0x401) {
+		miiphy_write(dev, phy_addr, 0x1f, 0);
+		printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
+		return;
+	}
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
+#endif
+
+	for (i = 0; i < 4; i++) {
+		for (j = 0; j < 4; j++) {
+			reg_pair[3].val = &ch_a_eq[i];
+			reg_pair[4].val = &ch_a_ctl2[j];
+			reg_pair[5].val = &ch_b_eq[i];
+			reg_pair[6].val = &ch_b_ctl2[j];
+			for (k = 0; k < 10; k++) {
+#if !CONFIG_IS_ENABLED(DM_I2C)
+				ret = i2c_write(i2c_phy_addr,
+						reg_pair[k].addr,
+						1, reg_pair[k].val, 1);
+#else
+				ret = i2c_get_chip_for_busnum(0,
+							      i2c_phy_addr,
+							      1, &udev);
+				if (!ret)
+					ret = dm_i2c_write(udev,
+							   reg_pair[k].addr,
+							   reg_pair[k].val, 1);
+#endif
+				if (ret)
+					goto error;
+			}
+
+			mdelay(100);
+			ret = miiphy_read(dev, phy_addr, 0x11, &value);
+			if (ret > 0)
+				goto error;
+
+			mdelay(100);
+			ret = miiphy_read(dev, phy_addr, 0x11, &value);
+			if (ret > 0)
+				goto error;
+
+			if ((value & 0xfff) == 0x401) {
+				printf("DPMAC %d :PHY is configured ",
+				       dpmac);
+				printf("after setting repeater 0x%x\n",
+				       value);
+				i = 5;
+				j = 5;
+			} else {
+				printf("DPMAC %d :PHY is failed to ",
+				       dpmac);
+				printf("configure the repeater 0x%x\n", value);
+			}
+		}
+	}
+	miiphy_write(dev, phy_addr, 0x1f, 0);
+error:
+	if (ret)
+		printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
+	return;
+}
+
+static void qsgmii_configure_repeater(int dpmac)
+{
+	uint8_t a = 0xf;
+	int i, j, k;
+	int i2c_phy_addr = 0;
+	int phy_addr = 0;
+	int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
+
+	uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
+	uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
+	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+
+	u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+	struct reg_pair reg_pair[10] = {
+		{6, &reg_val[0]}, {4, &reg_val[1]},
+		{8, &reg_val[2]}, {0xf, NULL},
+		{0x11, NULL}, {0x16, NULL},
+		{0x18, NULL}, {0x23, &reg_val[3]},
+		{0x2d, &reg_val[4]}, {4, &reg_val[5]},
+	};
+
+	const char *dev = mdio_names[EMI1_SLOT1];
+	int ret = 0;
+	unsigned short value;
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *udev;
+#endif
+
+	/* Set I2c to Slot 1 */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+	ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+	if (!ret)
+		ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+	if (ret)
+		goto error;
+
+	switch (dpmac) {
+	case 7:
+	case 8:
+	case 9:
+	case 10:
+		i2c_phy_addr = i2c_addr[2];
+		phy_addr = 8;
+		break;
+
+	case 3:
+	case 4:
+	case 5:
+	case 6:
+		i2c_phy_addr = i2c_addr[3];
+		phy_addr = 0xc;
+		break;
+	}
+
+	/* Check the PHY status */
+	ret = miiphy_set_current_dev(dev);
+	ret = miiphy_write(dev, phy_addr, 0x1f, 3);
+	mdelay(10);
+	ret = miiphy_read(dev, phy_addr, 0x11, &value);
+	mdelay(10);
+	ret = miiphy_read(dev, phy_addr, 0x11, &value);
+	mdelay(10);
+	if ((value & 0xf) == 0xf) {
+		miiphy_write(dev, phy_addr, 0x1f, 0);
+		printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
+		return;
+	}
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
+#endif
+
+	for (i = 0; i < 4; i++) {
+		for (j = 0; j < 4; j++) {
+			reg_pair[3].val = &ch_a_eq[i];
+			reg_pair[4].val = &ch_a_ctl2[j];
+			reg_pair[5].val = &ch_b_eq[i];
+			reg_pair[6].val = &ch_b_ctl2[j];
+
+			for (k = 0; k < 10; k++) {
+#if !CONFIG_IS_ENABLED(DM_I2C)
+				ret = i2c_write(i2c_phy_addr,
+						reg_pair[k].addr,
+						1, reg_pair[k].val, 1);
+#else
+				ret = i2c_get_chip_for_busnum(0,
+							      i2c_addr[dpmac],
+							      1, &udev);
+				if (!ret)
+					ret = dm_i2c_write(udev,
+							   reg_pair[k].addr,
+							   reg_pair[k].val, 1);
+#endif
+				if (ret)
+					goto error;
+			}
+
+			ret = miiphy_read(dev, phy_addr, 0x11, &value);
+			if (ret > 0)
+				goto error;
+			mdelay(1);
+			ret = miiphy_read(dev, phy_addr, 0x11, &value);
+			if (ret > 0)
+				goto error;
+			mdelay(10);
+			if ((value & 0xf) == 0xf) {
+				miiphy_write(dev, phy_addr, 0x1f, 0);
+				printf("DPMAC %d :PHY is ..... Configured\n",
+				       dpmac);
+				return;
+			}
+		}
+	}
+error:
+	printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
+	return;
+}
+
+static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+	struct mii_dev *bus;
+	const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+static void ls1088a_qds_enable_SFP_TX(u8 muxval)
+{
+	u8 brdcfg9;
+
+	brdcfg9 = QIXIS_READ(brdcfg[9]);
+	brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
+	brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
+	QIXIS_WRITE(brdcfg[9], brdcfg9);
+}
+
+static void ls1088a_qds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+
+	if (muxval <= 5) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
+				 int devad, int regnum)
+{
+	struct ls1088a_qds_mdio *priv = bus->priv;
+
+	ls1088a_qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				  int regnum, u16 value)
+{
+	struct ls1088a_qds_mdio *priv = bus->priv;
+
+	ls1088a_qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
+{
+	struct ls1088a_qds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct ls1088a_qds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate ls1088a_qds MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate ls1088a_qds private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = ls1088a_qds_mdio_read;
+	bus->write = ls1088a_qds_mdio_write;
+	bus->reset = ls1088a_qds_mdio_reset;
+	sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+
+	return mdio_register(bus);
+}
+
+/*
+ * Initialize the dpmac_info array.
+ *
+ */
+static void initialize_dpmac_to_slot(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 serdes1_prtcl, cfg;
+
+	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+				FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
+
+	switch (serdes1_prtcl) {
+	case 0x12:
+		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
+		lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
+		lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
+		lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
+		break;
+	case 0x15:
+	case 0x1D:
+		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
+		lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
+		lane_to_slot_fsm1[2] = EMI_NONE;
+		lane_to_slot_fsm1[3] = EMI_NONE;
+		break;
+	case 0x1E:
+		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
+		lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
+		lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
+		lane_to_slot_fsm1[3] = EMI_NONE;
+		break;
+	case 0x3A:
+		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
+		lane_to_slot_fsm1[1] = EMI_NONE;
+		lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
+		lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
+		break;
+
+	default:
+		printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+		       __func__, serdes1_prtcl);
+		break;
+	}
+}
+
+void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
+{
+	struct mii_dev *bus;
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 serdes1_prtcl, cfg;
+
+	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+				FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
+
+	int *riser_phy_addr;
+	char *env_hwconfig = env_get("hwconfig");
+
+	if (hwconfig_f("xqsgmii", env_hwconfig))
+		riser_phy_addr = &xqsgii_riser_phy_addr[0];
+	else
+		riser_phy_addr = &sgmii_riser_phy_addr[0];
+
+	switch (serdes1_prtcl) {
+	case 0x12:
+	case 0x15:
+	case 0x1E:
+	case 0x3A:
+		switch (dpmac_id) {
+		case 1:
+			wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[1]);
+			break;
+		case 2:
+			wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[0]);
+			break;
+		case 3:
+			wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[3]);
+			break;
+		case 7:
+			wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[2]);
+			break;
+		default:
+			printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
+			break;
+		}
+		break;
+	default:
+		printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+		       __func__, serdes1_prtcl);
+		return;
+	}
+	dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
+	bus = mii_dev_for_muxval(EMI1_SLOT1);
+	wriop_set_mdio(dpmac_id, bus);
+}
+
+void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
+{
+	struct mii_dev *bus;
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 serdes1_prtcl, cfg;
+
+	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+				FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
+
+	switch (serdes1_prtcl) {
+	case 0x1D:
+	case 0x1E:
+		switch (dpmac_id) {
+		case 3:
+		case 4:
+		case 5:
+		case 6:
+			wriop_set_phy_address(dpmac_id, 0, dpmac_id + 9);
+			break;
+		case 7:
+		case 8:
+		case 9:
+		case 10:
+			wriop_set_phy_address(dpmac_id, 0, dpmac_id + 1);
+			break;
+		}
+
+		dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
+		bus = mii_dev_for_muxval(EMI1_SLOT1);
+		wriop_set_mdio(dpmac_id, bus);
+		break;
+	default:
+		printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		break;
+	}
+}
+
+void ls1088a_handle_phy_interface_xsgmii(int i)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 serdes1_prtcl, cfg;
+
+	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+				FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
+
+	switch (serdes1_prtcl) {
+	case 0x15:
+	case 0x1D:
+	case 0x1E:
+		wriop_set_phy_address(i, 0, i + 26);
+		ls1088a_qds_enable_SFP_TX(SFP_TX);
+		break;
+	default:
+		printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		break;
+	}
+}
+
+static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 serdes1_prtcl, cfg;
+	struct mii_dev *bus;
+
+	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+				FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
+
+	switch (dpmac_id) {
+	case 4:
+		wriop_set_phy_address(dpmac_id, 0, RGMII_PHY1_ADDR);
+		dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
+		bus = mii_dev_for_muxval(EMI1_RGMII1);
+		wriop_set_mdio(dpmac_id, bus);
+		break;
+	case 5:
+		wriop_set_phy_address(dpmac_id, 0, RGMII_PHY2_ADDR);
+		dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
+		bus = mii_dev_for_muxval(EMI1_RGMII2);
+		wriop_set_mdio(dpmac_id, bus);
+		break;
+	default:
+		printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		break;
+	}
+}
+#endif
+
+int board_eth_init(struct bd_info *bis)
+{
+	int error = 0, i;
+#ifdef CONFIG_FSL_MC_ENET
+	struct memac_mdio_info *memac_mdio0_info;
+	char *env_hwconfig = env_get("hwconfig");
+
+	initialize_dpmac_to_slot();
+
+	memac_mdio0_info = (struct memac_mdio_info *)malloc(
+					sizeof(struct memac_mdio_info));
+	memac_mdio0_info->regs =
+		(struct memac_mdio_controller *)
+					CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
+
+	/* Register the real MDIO1 bus */
+	fm_memac_mdio_init(bis, memac_mdio0_info);
+	/* Register the muxing front-ends to the MDIO buses */
+	ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
+	ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
+	ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
+
+	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+		switch (wriop_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			ls1088a_handle_phy_interface_rgmii(i);
+			break;
+		case PHY_INTERFACE_MODE_QSGMII:
+			ls1088a_handle_phy_interface_qsgmii(i);
+			break;
+		case PHY_INTERFACE_MODE_SGMII:
+			ls1088a_handle_phy_interface_sgmii(i);
+			break;
+		case PHY_INTERFACE_MODE_XGMII:
+			ls1088a_handle_phy_interface_xsgmii(i);
+			break;
+		default:
+			break;
+
+		if (i == 16)
+			i = NUM_WRIOP_PORTS;
+		}
+	}
+
+	error = cpu_eth_init(bis);
+
+	if (hwconfig_f("xqsgmii", env_hwconfig)) {
+		for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+			switch (wriop_get_enet_if(i)) {
+			case PHY_INTERFACE_MODE_QSGMII:
+				qsgmii_configure_repeater(i);
+				break;
+			case PHY_INTERFACE_MODE_SGMII:
+				sgmii_configure_repeater(i);
+				break;
+			default:
+				break;
+			}
+
+			if (i == 16)
+				i = NUM_WRIOP_PORTS;
+		}
+	}
+#endif
+	error = pci_eth_init(bis);
+	return error;
+}
+#endif // !CONFIG_DM_ETH
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+	mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+
+/* Structure to hold SERDES protocols supported in case of
+ * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+ *
+ * @serdes_block: the index of the SERDES block
+ * @serdes_protocol: the decimal value of the protocol supported
+ * @dts_needed: DTS notes describing the current configuration are needed
+ *
+ * When dts_needed is true, the board_fit_config_name_match() function
+ * will try to exactly match the current configuration of the block with a DTS
+ * name provided.
+ */
+static struct serdes_configuration {
+	u8 serdes_block;
+	u32 serdes_protocol;
+	bool dts_needed;
+} supported_protocols[] = {
+	/* Serdes block #1 */
+	{1, 21, true},
+	{1, 29, true},
+};
+
+#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
+
+static bool protocol_supported(u8 serdes_block, u32 protocol)
+{
+	struct serdes_configuration serdes_conf;
+	int i;
+
+	for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+		serdes_conf = supported_protocols[i];
+		if (serdes_conf.serdes_block == serdes_block &&
+		    serdes_conf.serdes_protocol == protocol)
+			return true;
+	}
+
+	return false;
+}
+
+static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
+{
+	struct serdes_configuration serdes_conf;
+	int i;
+
+	for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+		serdes_conf = supported_protocols[i];
+		if (serdes_conf.serdes_block == serdes_block &&
+		    serdes_conf.serdes_protocol == protocol) {
+			if (serdes_conf.dts_needed == true)
+				sprintf(str, "%u", protocol);
+			else
+				sprintf(str, "x");
+			return;
+		}
+	}
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	char expected_dts[100];
+	char srds_s1_str[2];
+	u32 srds_s1, cfg;
+
+	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+		      FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+	srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
+
+	/* Check for supported protocols. The default DTS will be used
+	 * in this case
+	 */
+	if (!protocol_supported(1, srds_s1))
+		return -1;
+
+	get_str_protocol(1, srds_s1, srds_s1_str);
+
+	sprintf(expected_dts, "fsl-ls1088a-qds-%s-x", srds_s1_str);
+
+	if (!strcmp(name, expected_dts))
+		return 0;
+
+	return -1;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/ls1088a/eth_ls1088ardb.c b/roms/u-boot/board/freescale/ls1088a/eth_ls1088ardb.c
new file mode 100644
index 000000000..a8e9ef15d
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1088a/eth_ls1088ardb.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+#ifndef CONFIG_DM_ETH
+int board_eth_init(struct bd_info *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+	int i, interface;
+	struct memac_mdio_info mdio_info;
+	struct mii_dev *dev;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct memac_mdio_controller *reg;
+	u32 srds_s1, cfg;
+
+	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+				FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+
+	srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
+
+	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	mdio_info.regs = reg;
+	mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+	/* Register the EMI 1 */
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+	mdio_info.regs = reg;
+	mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+	/* Register the EMI 2 */
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	switch (srds_s1) {
+	case 0x1D:
+		/*
+		 * XFI does not need a PHY to work, but to avoid U-boot use
+		 * default PHY address which is zero to a MAC when it found
+		 * a MAC has no PHY address, we give a PHY address to XFI
+		 * MAC error.
+		 */
+		wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a);
+		wriop_set_phy_address(WRIOP1_DPMAC2, 0, AQ_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC3, 0, QSGMII1_PORT1_PHY_ADDR);
+		wriop_set_phy_address(WRIOP1_DPMAC4, 0, QSGMII1_PORT2_PHY_ADDR);
+		wriop_set_phy_address(WRIOP1_DPMAC5, 0, QSGMII1_PORT3_PHY_ADDR);
+		wriop_set_phy_address(WRIOP1_DPMAC6, 0, QSGMII1_PORT4_PHY_ADDR);
+		wriop_set_phy_address(WRIOP1_DPMAC7, 0, QSGMII2_PORT1_PHY_ADDR);
+		wriop_set_phy_address(WRIOP1_DPMAC8, 0, QSGMII2_PORT2_PHY_ADDR);
+		wriop_set_phy_address(WRIOP1_DPMAC9, 0, QSGMII2_PORT3_PHY_ADDR);
+		wriop_set_phy_address(WRIOP1_DPMAC10, 0,
+				      QSGMII2_PORT4_PHY_ADDR);
+
+		break;
+	default:
+		printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n",
+		       srds_s1);
+		break;
+	}
+
+	for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) {
+		interface = wriop_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_QSGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+			wriop_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+	wriop_set_mdio(WRIOP1_DPMAC2, dev);
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+	mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/roms/u-boot/board/freescale/ls1088a/ls1088a.c b/roms/u-boot/board/freescale/ls1088a/ls1088a.c
new file mode 100644
index 000000000..f5dc449d8
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1088a/ls1088a.c
@@ -0,0 +1,1059 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ */
+#include <common.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <log.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <fsl_sec.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fsl-mc/fsl_mc.h>
+#include <env_internal.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch/ppa.h>
+#include <hwconfig.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+
+#include "../common/qixis.h"
+#include "ls1088a_qixis.h"
+#include "../common/vid.h"
+#include <fsl_immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+#ifdef CONFIG_TFABOOT
+struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"nor0",
+		CONFIG_SYS_NOR0_CSPR_EARLY,
+		CONFIG_SYS_NOR0_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+		0,
+		CONFIG_SYS_NOR0_CSPR,
+		0,
+	},
+	{
+		"nor1",
+		CONFIG_SYS_NOR1_CSPR_EARLY,
+		CONFIG_SYS_NOR0_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK_EARLY,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+		0,
+		CONFIG_SYS_NOR1_CSPR,
+		CONFIG_SYS_NOR_AMASK,
+	},
+	{
+		"nand",
+		CONFIG_SYS_NAND_CSPR,
+		CONFIG_SYS_NAND_CSPR_EXT,
+		CONFIG_SYS_NAND_AMASK,
+		CONFIG_SYS_NAND_CSOR,
+		{
+			CONFIG_SYS_NAND_FTIM0,
+			CONFIG_SYS_NAND_FTIM1,
+			CONFIG_SYS_NAND_FTIM2,
+			CONFIG_SYS_NAND_FTIM3
+		},
+	},
+	{
+		"fpga",
+		CONFIG_SYS_FPGA_CSPR,
+		CONFIG_SYS_FPGA_CSPR_EXT,
+		SYS_FPGA_AMASK,
+		CONFIG_SYS_FPGA_CSOR,
+		{
+			SYS_FPGA_CS_FTIM0,
+			SYS_FPGA_CS_FTIM1,
+			SYS_FPGA_CS_FTIM2,
+			SYS_FPGA_CS_FTIM3
+		},
+		0,
+		SYS_FPGA_CSPR_FINAL,
+		0,
+	}
+};
+
+struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"nand",
+		CONFIG_SYS_NAND_CSPR,
+		CONFIG_SYS_NAND_CSPR_EXT,
+		CONFIG_SYS_NAND_AMASK,
+		CONFIG_SYS_NAND_CSOR,
+		{
+			CONFIG_SYS_NAND_FTIM0,
+			CONFIG_SYS_NAND_FTIM1,
+			CONFIG_SYS_NAND_FTIM2,
+			CONFIG_SYS_NAND_FTIM3
+		},
+	},
+	{
+		"reserved",
+	},
+	{
+		"fpga",
+		CONFIG_SYS_FPGA_CSPR,
+		CONFIG_SYS_FPGA_CSPR_EXT,
+		SYS_FPGA_AMASK,
+		CONFIG_SYS_FPGA_CSOR,
+		{
+			SYS_FPGA_CS_FTIM0,
+			SYS_FPGA_CS_FTIM1,
+			SYS_FPGA_CS_FTIM2,
+			SYS_FPGA_CS_FTIM3
+		},
+		0,
+		SYS_FPGA_CSPR_FINAL,
+		0,
+	}
+};
+
+void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
+{
+	enum boot_src src = get_boot_src();
+
+	if (src == BOOT_SOURCE_QSPI_NOR)
+		regs_info->regs = ifc_cfg_qspi_nor_boot;
+	else
+		regs_info->regs = ifc_cfg_ifc_nor_boot;
+
+	regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
+}
+#endif /* CONFIG_TFABOOT */
+#endif /* CONFIG_TARGET_LS1088AQDS */
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
+	i2c_early_init_f();
+#endif
+	fsl_lsch3_early_init_f();
+	return 0;
+}
+
+#ifdef CONFIG_FSL_QIXIS
+unsigned long long get_qixis_addr(void)
+{
+	unsigned long long addr;
+
+	if (gd->flags & GD_FLG_RELOC)
+		addr = QIXIS_BASE_PHYS;
+	else
+		addr = QIXIS_BASE_PHYS_EARLY;
+
+	/*
+	 * IFC address under 256MB is mapped to 0x30000000, any address above
+	 * is mapped to 0x5_10000000 up to 4GB.
+	 */
+	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
+
+	return addr;
+}
+#endif
+
+#if defined(CONFIG_VID)
+int init_func_vid(void)
+{
+	if (adjust_vdd(0) < 0)
+		printf("core voltage not adjusted\n");
+
+	return 0;
+}
+
+u16 soc_get_fuse_vid(int vid_index)
+{
+	static const u16 vdd[32] = {
+		10250,
+		9875,
+		9750,
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		9000,
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		10000,  /* 1.0000V */
+		10125,
+		10250,
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+	};
+
+	return vdd[vid_index];
+};
+#endif
+
+int is_pb_board(void)
+{
+	u8 board_id;
+
+	board_id = QIXIS_READ(id);
+	if (board_id == LS1088ARDB_PB_BOARD)
+		return 1;
+	else
+		return 0;
+}
+
+int fixup_ls1088ardb_pb_banner(void *fdt)
+{
+	fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
+
+	return 0;
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+int checkboard(void)
+{
+#ifdef CONFIG_TFABOOT
+	enum boot_src src = get_boot_src();
+#endif
+	char buf[64];
+	u8 sw;
+	static const char *const freq[] = {"100", "125", "156.25",
+					    "100 separate SSCG"};
+	int clock;
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+	printf("Board: LS1088A-QDS, ");
+#else
+	if (is_pb_board())
+		printf("Board: LS1088ARDB-PB, ");
+	else
+		printf("Board: LS1088A-RDB, ");
+#endif
+
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+#else
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
+#endif
+
+	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+#ifdef CONFIG_TFABOOT
+	if (src == BOOT_SOURCE_SD_MMC)
+		puts("SD card\n");
+#else
+#ifdef CONFIG_SD_BOOT
+	puts("SD card\n");
+#endif
+#endif /* CONFIG_TFABOOT */
+	switch (sw) {
+#ifdef CONFIG_TARGET_LS1088AQDS
+	case 0:
+	case 1:
+	case 2:
+	case 3:
+	case 4:
+	case 5:
+	case 6:
+	case 7:
+		printf("vBank: %d\n", sw);
+		break;
+	case 8:
+		puts("PromJet\n");
+		break;
+	case 15:
+		puts("IFCCard\n");
+		break;
+	case 14:
+#else
+	case 0:
+#endif
+		puts("QSPI:");
+		sw = QIXIS_READ(brdcfg[0]);
+		sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
+		if (sw == 0 || sw == 4)
+			puts("0\n");
+		else if (sw == 1)
+			puts("1\n");
+		else
+			puts("EMU\n");
+		break;
+
+	default:
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+		break;
+	}
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+	printf("FPGA: v%d (%s), build %d",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+#else
+	printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
+#endif
+
+	/*
+	 * Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES1 Reference : ");
+	sw = QIXIS_READ(brdcfg[2]);
+	clock = (sw >> 6) & 3;
+	printf("Clock1 = %sMHz ", freq[clock]);
+	clock = (sw >> 4) & 3;
+	printf("Clock2 = %sMHz", freq[clock]);
+
+	puts("\nSERDES2 Reference : ");
+	clock = (sw >> 2) & 3;
+	printf("Clock1 = %sMHz ", freq[clock]);
+	clock = (sw >> 0) & 3;
+	printf("Clock2 = %sMHz\n", freq[clock]);
+
+	return 0;
+}
+#endif
+
+bool if_board_diff_clk(void)
+{
+#ifdef CONFIG_TARGET_LS1088AQDS
+	u8 diff_conf = QIXIS_READ(brdcfg[11]);
+	return diff_conf & 0x40;
+#else
+	u8 diff_conf = QIXIS_READ(dutcfg[11]);
+	return diff_conf & 0x80;
+#endif
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0f) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	if (if_board_diff_clk())
+		return get_board_sys_clk();
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+
+	return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+void board_retimer_init(void)
+{
+	u8 reg;
+
+	/* Retimer is connected to I2C1_CH5 */
+	select_i2c_ch_pca9547(I2C_MUX_CH5);
+
+	/* Access to Control/Shared register */
+	reg = 0x0;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
+#else
+	struct udevice *dev;
+
+	i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
+	dm_i2c_write(dev, 0xff, &reg, 1);
+#endif
+
+	/* Read device revision and ID */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 1, &reg, 1);
+#endif
+	debug("Retimer version id = 0x%x\n", reg);
+
+	/* Enable Broadcast. All writes target all channel register sets */
+	reg = 0x0c;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0xff, &reg, 1);
+#endif
+
+	/* Reset Channel Registers */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 0, &reg, 1);
+#endif
+	reg |= 0x4;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0, &reg, 1);
+#endif
+
+	/* Set data rate as 10.3125 Gbps */
+	reg = 0x90;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x60, &reg, 1);
+#endif
+	reg = 0xb3;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x61, &reg, 1);
+#endif
+	reg = 0x90;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x62, &reg, 1);
+#endif
+	reg = 0xb3;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x63, &reg, 1);
+#endif
+	reg = 0xcd;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x64, &reg, 1);
+#endif
+
+	/* Select VCO Divider to full rate (000) */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 0x2F, &reg, 1);
+#endif
+	reg &= 0x0f;
+	reg |= 0x70;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x2F, &reg, 1);
+#endif
+
+#ifdef	CONFIG_TARGET_LS1088AQDS
+	/* Retimer is connected to I2C1_CH5 */
+	select_i2c_ch_pca9547(I2C_MUX_CH5);
+
+	/* Access to Control/Shared register */
+	reg = 0x0;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
+#else
+	i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
+	dm_i2c_write(dev, 0xff, &reg, 1);
+#endif
+
+	/* Read device revision and ID */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 1, &reg, 1);
+#endif
+	debug("Retimer version id = 0x%x\n", reg);
+
+	/* Enable Broadcast. All writes target all channel register sets */
+	reg = 0x0c;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0xff, &reg, 1);
+#endif
+
+	/* Reset Channel Registers */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 0, &reg, 1);
+#endif
+	reg |= 0x4;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0, &reg, 1);
+#endif
+
+	/* Set data rate as 10.3125 Gbps */
+	reg = 0x90;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x60, &reg, 1);
+#endif
+	reg = 0xb3;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x61, &reg, 1);
+#endif
+	reg = 0x90;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x62, &reg, 1);
+#endif
+	reg = 0xb3;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x63, &reg, 1);
+#endif
+	reg = 0xcd;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x64, &reg, 1);
+#endif
+
+	/* Select VCO Divider to full rate (000) */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 0x2F, &reg, 1);
+#endif
+	reg &= 0x0f;
+	reg |= 0x70;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x2F, &reg, 1);
+#endif
+
+#endif
+	/*return the default channel*/
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_TARGET_LS1088ARDB
+	u8 brdcfg5;
+
+	if (hwconfig("esdhc-force-sd")) {
+		brdcfg5 = QIXIS_READ(brdcfg[5]);
+		brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
+		brdcfg5 |= BRDCFG5_FORCE_SD;
+		QIXIS_WRITE(brdcfg[5], brdcfg5);
+	}
+#endif
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+	 u8 brdcfg4, brdcfg5;
+
+	if (hwconfig("dspi-on-board")) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
+		brdcfg4 |= BRDCFG4_SPI;
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+
+		brdcfg5 = QIXIS_READ(brdcfg[5]);
+		brdcfg5 &= ~BRDCFG5_SPR_MASK;
+		brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
+		QIXIS_WRITE(brdcfg[5], brdcfg5);
+	} else if (hwconfig("dspi-off-board")) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
+		brdcfg4 |= BRDCFG4_SPI;
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+
+		brdcfg5 = QIXIS_READ(brdcfg[5]);
+		brdcfg5 &= ~BRDCFG5_SPR_MASK;
+		brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
+		QIXIS_WRITE(brdcfg[5], brdcfg5);
+	}
+#endif
+	return 0;
+}
+#endif
+#endif
+
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+	return select_i2c_ch_pca9547(channel);
+}
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+/* read the current value(SVDD) of the LTM Regulator Voltage */
+int get_serdes_volt(void)
+{
+	int  ret, vcode = 0;
+	u8 chan = PWM_CHANNEL0;
+
+	/* Select the PAGE 0 using PMBus commands PAGE for VDD */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
+			PMBUS_CMD_PAGE, 1, &chan, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
+				   &chan, 1);
+#endif
+
+	if (ret) {
+		printf("VID: failed to select VDD Page 0\n");
+		return ret;
+	}
+
+	/* Read the output voltage using PMBus command READ_VOUT */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
+		       PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+#else
+	dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
+#endif
+	if (ret) {
+		printf("VID: failed to read the volatge\n");
+		return ret;
+	}
+
+	return vcode;
+}
+
+int set_serdes_volt(int svdd)
+{
+	int ret, vdd_last;
+	u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
+			svdd & 0xFF, (svdd & 0xFF00) >> 8};
+
+	/* Write the desired voltage code to the SVDD regulator */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
+			PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
+				   (void *)&buff, 5);
+#endif
+	if (ret) {
+		printf("VID: I2C failed to write to the volatge regulator\n");
+		return -1;
+	}
+
+	/* Wait for the volatge to get to the desired value */
+	do {
+		vdd_last = get_serdes_volt();
+		if (vdd_last < 0) {
+			printf("VID: Couldn't read sensor abort VID adjust\n");
+			return -1;
+		}
+	} while (vdd_last != svdd);
+
+	return 1;
+}
+#else
+int get_serdes_volt(void)
+{
+	return 0;
+}
+
+int set_serdes_volt(int svdd)
+{
+	int ret;
+	u8 brdcfg4;
+
+	printf("SVDD changing of RDB\n");
+
+	/* Read the BRDCFG54 via CLPD */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
+		       QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
+				  (void *)&brdcfg4, 1);
+#endif
+
+	if (ret) {
+		printf("VID: I2C failed to read the CPLD BRDCFG4\n");
+		return -1;
+	}
+
+	brdcfg4 = brdcfg4 | 0x08;
+
+	/* Write to the BRDCFG4 */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
+			QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+#else
+	ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
+			   (void *)&brdcfg4, 1);
+#endif
+
+	if (ret) {
+		debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
+		return -1;
+	}
+
+	/* Wait for the volatge to get to the desired value */
+	udelay(10000);
+
+	return 1;
+}
+#endif
+
+/* this function disables the SERDES, changes the SVDD Voltage and enables it*/
+int board_adjust_vdd(int vdd)
+{
+	int ret = 0;
+
+	debug("%s: vdd = %d\n", __func__, vdd);
+
+	/* Special settings to be performed when voltage is 900mV */
+	if (vdd == 900) {
+		ret = setup_serdes_volt(vdd);
+		if (ret < 0) {
+			ret = -1;
+			goto exit;
+		}
+	}
+exit:
+	return ret;
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+int board_init(void)
+{
+	init_final_memctl_regs();
+#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
+	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
+
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	board_retimer_init();
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
+	/* invert AQR105 IRQ pins polarity */
+	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+	pci_init();
+#endif
+
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_ddr_info(0);
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+void board_quiesce_devices(void)
+{
+	fsl_mc_ldpaa_exit(gd->bd);
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	int offset;
+
+	offset = fdt_path_offset(fdt, "/fsl-mc");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/soc/fsl-mc");
+
+	if (offset < 0) {
+		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
+		       __func__, offset);
+		return;
+	}
+
+	if (get_mc_boot_status() == 0 &&
+	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
+		fdt_status_okay(fdt, offset);
+	else
+		fdt_status_fail(fdt, offset);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void fsl_fdt_fixup_flash(void *fdt)
+{
+	int offset;
+#ifdef CONFIG_TFABOOT
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 val;
+#endif
+
+/*
+ * IFC-NOR and QSPI are muxed on SoC.
+ * So disable IFC node in dts if QSPI is enabled or
+ * disable QSPI node in dts in case QSPI is not enabled.
+ */
+
+#ifdef CONFIG_TFABOOT
+	enum boot_src src = get_boot_src();
+	bool disable_ifc = false;
+
+	switch (src) {
+	case BOOT_SOURCE_IFC_NOR:
+		disable_ifc = false;
+		break;
+	case BOOT_SOURCE_QSPI_NOR:
+		disable_ifc = true;
+		break;
+	default:
+		val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+		if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+			disable_ifc = true;
+		break;
+	}
+
+	if (disable_ifc) {
+		offset = fdt_path_offset(fdt, "/soc/ifc/nor");
+
+		if (offset < 0)
+			offset = fdt_path_offset(fdt, "/ifc/nor");
+	} else {
+		offset = fdt_path_offset(fdt, "/soc/quadspi");
+
+		if (offset < 0)
+			offset = fdt_path_offset(fdt, "/quadspi");
+	}
+
+#else
+#ifdef CONFIG_FSL_QSPI
+	offset = fdt_path_offset(fdt, "/soc/ifc/nor");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/ifc/nor");
+#else
+	offset = fdt_path_offset(fdt, "/soc/quadspi");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/quadspi");
+#endif
+#endif
+	if (offset < 0)
+		return;
+
+	fdt_status_disabled(fdt, offset);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int i;
+	u16 mc_memory_bank = 0;
+
+	u64 *base;
+	u64 *size;
+	u64 mc_memory_base = 0;
+	u64 mc_memory_size = 0;
+	u16 total_memory_banks;
+
+	ft_cpu_setup(blob, bd);
+
+	fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+	if (mc_memory_base != 0)
+		mc_memory_bank++;
+
+	total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+	base = calloc(total_memory_banks, sizeof(u64));
+	size = calloc(total_memory_banks, sizeof(u64));
+
+	/* fixup DT for the two GPP DDR banks */
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		base[i] = gd->bd->bi_dram[i].start;
+		size[i] = gd->bd->bi_dram[i].size;
+	}
+
+#ifdef CONFIG_RESV_RAM
+	/* reduce size if reserved memory is within this bank */
+	if (gd->arch.resv_ram >= base[0] &&
+	    gd->arch.resv_ram < base[0] + size[0])
+		size[0] = gd->arch.resv_ram - base[0];
+	else if (gd->arch.resv_ram >= base[1] &&
+		 gd->arch.resv_ram < base[1] + size[1])
+		size[1] = gd->arch.resv_ram - base[1];
+#endif
+
+	if (mc_memory_base != 0) {
+		for (i = 0; i <= total_memory_banks; i++) {
+			if (base[i] == 0 && size[i] == 0) {
+				base[i] = mc_memory_base;
+				size[i] = mc_memory_size;
+				break;
+			}
+		}
+	}
+
+	fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
+
+	fdt_fsl_mc_fixup_iommu_map_entry(blob);
+
+	fsl_fdt_fixup_flash(blob);
+
+#ifdef CONFIG_FSL_MC_ENET
+	fdt_fixup_board_enet(blob);
+#endif
+
+	fdt_fixup_icid(blob);
+
+	if (is_pb_board())
+		fixup_ls1088ardb_pb_banner(blob);
+
+	return 0;
+}
+#endif
+#endif /* defined(CONFIG_SPL_BUILD) */
+
+#ifdef CONFIG_TFABOOT
+#ifdef CONFIG_MTD_NOR_FLASH
+int is_flash_available(void)
+{
+	char *env_hwconfig = env_get("hwconfig");
+	enum boot_src src = get_boot_src();
+	int is_nor_flash_available = 1;
+
+	switch (src) {
+	case BOOT_SOURCE_IFC_NOR:
+		is_nor_flash_available = 1;
+		break;
+	case BOOT_SOURCE_QSPI_NOR:
+		is_nor_flash_available = 0;
+		break;
+	/*
+	 * In Case of SD boot,if qspi is defined in env_hwconfig
+	 * disable nor flash probe.
+	 */
+	default:
+		if (hwconfig_f("qspi", env_hwconfig))
+			is_nor_flash_available = 0;
+		break;
+	}
+	return is_nor_flash_available;
+}
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+void *env_sf_get_env_addr(void)
+{
+	return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+}
+#endif
+#endif
diff --git a/roms/u-boot/board/freescale/ls1088a/ls1088a_qixis.h b/roms/u-boot/board/freescale/ls1088a/ls1088a_qixis.h
new file mode 100644
index 000000000..e3502eb1d
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls1088a/ls1088a_qixis.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef __LS1088AQDS_QIXIS_H__
+#define __LS1088AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1088AQDS */
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#define BRDCFG4_EMISEL_MASK		0xE0
+#define BRDCFG4_EMISEL_SHIFT		5
+#define BRDCFG9_SFPTX_MASK		0x10
+#define BRDCFG9_SFPTX_SHIFT		4
+
+/* Definitions of QIXIS Registers for LS1088ARDB */
+
+/* BRDCFG5 */
+#define BRDCFG5_SPISDHC_MASK		0x0C
+#define BRDCFG5_FORCE_SD		0x08
+
+/* Definitions of QIXIS Registers for LS1088AQDS */
+
+/* BRDCFG4 */
+#define BRDCFG4_USBOSC_MASK   0x01
+#define BRDCFG4_SPI 0x01
+
+/* BRDCFG5 */
+#define BRDCFG5_SPR_MASK 0x0f
+#define BRDCFG5_SPI_ON_BOARD 0x0a
+#define BRDCFG5_SPI_OFF_BOARD 0x0f
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls2080aqds/Kconfig b/roms/u-boot/board/freescale/ls2080aqds/Kconfig
new file mode 100644
index 000000000..6b2b64581
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080aqds/Kconfig
@@ -0,0 +1,34 @@
+
+if TARGET_LS2080AQDS
+
+config SYS_BOARD
+	default "ls2080aqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls2080aqds"
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+	hex "PPA Firmware Addr"
+	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x580400000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA Firmware HDR Addr"
+	default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x580680000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/ls2080aqds/MAINTAINERS b/roms/u-boot/board/freescale/ls2080aqds/MAINTAINERS
new file mode 100644
index 000000000..84735dce2
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080aqds/MAINTAINERS
@@ -0,0 +1,13 @@
+LS2080A BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+S:	Maintained
+F:	board/freescale/ls2080aqds/
+F:	board/freescale/ls2080a/ls2080aqds.c
+F:	include/configs/ls2080aqds.h
+F:	configs/ls2080aqds_defconfig
+F:	configs/ls2080aqds_nand_defconfig
+F:	configs/ls2080aqds_qspi_defconfig
+F:	configs/ls2080aqds_sdcard_defconfig
+F:	configs/ls2088aqds_tfa_defconfig
+F:	configs/ls2080aqds_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/ls2080aqds/Makefile b/roms/u-boot/board/freescale/ls2080aqds/Makefile
new file mode 100644
index 000000000..efc51b4a3
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080aqds/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2015 Freescale Semiconductor
+
+obj-y += ls2080aqds.o
+obj-y += ddr.o
+obj-y += eth.o
diff --git a/roms/u-boot/board/freescale/ls2080aqds/README b/roms/u-boot/board/freescale/ls2080aqds/README
new file mode 100644
index 000000000..8e31e9e41
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080aqds/README
@@ -0,0 +1,216 @@
+Overview
+--------
+The LS2080A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
+and LS2088A Layerscape Architecture processor. The LS2080AQDS provides
+validation and SW development platform for the Freescale LS2080A, LS2088A
+processor series, with a complete debugging environment.
+
+LS2080A, LS2088A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
+LS2088A SoC overview.
+
+ LS2080AQDS board Overview
+ -----------------------
+ - SERDES Connections, 16 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - QSGMII
+      - SATA 3.0
+      - XAUI
+      - XFI
+ - DDR Controller
+     - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
+       chip-selects and two DIMM connectors. Support is up to 2133MT/s.
+     - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
+       and two DIMM connectors. Support is up to 1600MT/s.
+ -IFC/Local Bus
+    - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
+    - One in-socket 128 MB NOR flash 16-bit data bus
+    - One 512 MB NAND flash with ECC support
+    - IFC Test Port
+    - PromJet Port
+    - FPGA connection
+ - USB 3.0
+    - Two high speed USB 3.0 ports
+    - First USB 3.0 port configured as Host with Type-A connector
+    - Second USB 3.0 port configured as OTG with micro-AB connector
+ - SDHC: PCIe x1 Right Angle connector for supporting following cards
+    - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only
+    - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only
+    - 4-bit eMMC Card Rev 4.4 (1.8V only)
+    - 8-bit eMMC Card Rev 4.5 (1.8V only)
+    - SD Card Rev 2.0 and Rev 3.0
+ - DSPI: 3 high-speed flash Memory for storage
+    - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
+    - 8 MB high-speed flash Memory (up to 104 MHz)
+    - 512 MB low-speed flash Memory (up to 40 MHz)
+ - QSPI: via NAND/QSPI Card
+ - 4 I2C controllers
+ - Two SATA onboard connectors
+ - UART
+   - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
+   - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
+0x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
+0x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
+0x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
+0x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
+0x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
+0x80_8000_0000 .. 0xFF_FFFF_FFFF	DDR region #2
+
+Other addresses are either reserved, or not used directly by U-Boot.
+This list should be updated when more addresses are used.
+
+IFC region map from core's view
+-------------------------------
+During boot i.e. IFC Region #1:-
+  0x30000000 - 0x37ffffff : 128MB : NOR flash
+  0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
+  0x3C000000 - 0x40000000 : 64MB  : FPGA etc
+
+After relocate to DDR i.e. IFC Region #2:-
+  0x5_1000_0000..0x5_1fff_ffff	Memory Hole
+  0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
+  0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
+  0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
+  0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
+
+Booting Options
+---------------
+a) Promjet Boot
+b) NOR boot
+c) NAND boot
+d) SD boot
+e) QSPI boot
+
+Memory map for NOR boot
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Secure Headers			0x00600000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
+
+Memory map for SD boot
+-------------------------
+Image				Flash Offset	SD Card
+						Start Block No.
+RCW+PBI				0x00000000	0x00008
+Boot firmware (U-Boot)		0x00100000	0x00800
+Boot firmware Environment	0x00300000	0x01800
+PPA firmware			0x00400000	0x02000
+DPAA2 MC			0x00A00000	0x05000
+DPAA2 DPL			0x00D00000	0x06800
+DPAA2 DPC			0x00E00000	0x07000
+Kernel.itb			0x01000000	0x08000
+
+Environment Variables
+---------------------
+- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
+  the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+
+- mcmemsize: MC DRAM block size. If this variable is not defined
+  the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+
+Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
+-------------------------------------------------------------------
+One needs to use appropriate bootargs to boot Linux flavors which do
+not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
+below:
+
+=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
+   earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
+   hugepages=16 mem=2048M'
+
+
+X-QSGMII-16PORT riser card
+----------------------------
+The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
+interfaces implemented in PCIe form factor board.
+It supports following:
+ - Card can operate with up to 4 QSGMII lane simultaneously
+ - Card can operate with up to 8 SGMII lane simultaneously
+
+Supported card configuration
+	- CSEL  : ON ON ON ON
+	- MSEL1 : ON ON ON ON OFF OFF OFF OFF
+	- MSEL2 : OFF OFF OFF OFF ON ON ON ON
+
+To enable this card: modify hwconfig to add "xqsgmii" variable.
+
+Supported PHY addresses during SGMII:
+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
+
+Mapping DPMACx to PHY during SGMII
+DPMAC1 -> PHY1-P0
+DPMAC2 -> PHY2-P0
+DPMAC3 -> PHY3-P0
+DPMAC4 -> PHY4-P0
+DPMAC5 -> PHY3-P2
+DPMAC6 -> PHY1-P2
+DPMAC7 -> PHY4-P1
+DPMAC8 -> PHY2-P2
+DPMAC9 -> PHY1-P0
+DPMAC10 -> PHY2-P0
+DPMAC11 -> PHY3-P0
+DPMAC12 -> PHY4-P0
+DPMAC13 -> PHY3-P2
+DPMAC14 -> PHY1-P2
+DPMAC15 -> PHY4-P1
+DPMAC16 -> PHY2-P2
+
+
+Supported PHY address during QSGMII
+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
+#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
+#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
+#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
+#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
+#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
+#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
+#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
+#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
+
+Mapping DPMACx to PHY during QSGMII
+DPMAC1 -> PHY1-P3
+DPMAC2 -> PHY1-P2
+DPMAC3 -> PHY1-P1
+DPMAC4 -> PHY1-P0
+DPMAC5 -> PHY2-P3
+DPMAC6 -> PHY2-P2
+DPMAC7 -> PHY2-P1
+DPMAC8 -> PHY2-P0
+DPMAC9 -> PHY3-P0
+DPMAC10 -> PHY3-P1
+DPMAC11 -> PHY3-P2
+DPMAC12 -> PHY3-P3
+DPMAC13 -> PHY4-P0
+DPMAC14 -> PHY4-P1
+DPMAC15 -> PHY4-P2
+DPMAC16 -> PHY4-P3
+
diff --git a/roms/u-boot/board/freescale/ls2080aqds/ddr.c b/roms/u-boot/board/freescale/ls2080aqds/ddr.c
new file mode 100644
index 000000000..2767d058c
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080aqds/ddr.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <log.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/clock.h>
+#include <asm/global_data.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+	u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+	int slot;
+
+	if (ctrl_num > 2) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+
+	for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
+		if (pdimm[slot].n_ranks)
+			break;
+	}
+
+	if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
+		return;
+
+	/*
+	 * we use identical timing for all slots. If needed, change the code
+	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+	 */
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[ctrl_num];
+	else
+		pbsp = udimms[ctrl_num];
+
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm[slot].n_ranks &&
+		    (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for data rate %lu MT/s\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
+		/* force DDR bus width to 32 bits */
+		popts->data_bus_width = 1;
+		popts->otf_burst_chop_en = 0;
+		popts->burst_length = DDR_BL8;
+		popts->bstopre = 0;	/* enable auto precharge */
+		/*
+		 * Layout optimization results byte mapping
+		 * Byte 0 -> Byte ECC
+		 * Byte 1 -> Byte 3
+		 * Byte 2 -> Byte 2
+		 * Byte 3 -> Byte 1
+		 * Byte ECC -> Byte 0
+		 */
+		dq_mapping_0 = pdimm[slot].dq_mapping[0];
+		dq_mapping_2 = pdimm[slot].dq_mapping[2];
+		dq_mapping_3 = pdimm[slot].dq_mapping[3];
+		pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
+		pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
+		pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
+		pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
+		pdimm[slot].dq_mapping[6] = dq_mapping_2;
+		pdimm[slot].dq_mapping[7] = dq_mapping_3;
+		pdimm[slot].dq_mapping[8] = dq_mapping_0;
+		pdimm[slot].dq_mapping[9] = 0;
+		pdimm[slot].dq_mapping[10] = 0;
+		pdimm[slot].dq_mapping[11] = 0;
+		pdimm[slot].dq_mapping[12] = 0;
+		pdimm[slot].dq_mapping[13] = 0;
+		pdimm[slot].dq_mapping[14] = 0;
+		pdimm[slot].dq_mapping[15] = 0;
+		pdimm[slot].dq_mapping[16] = 0;
+		pdimm[slot].dq_mapping[17] = 0;
+	}
+#endif
+	/* To work at higher than 1333MT/s */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0x0;	/* 32 clocks */
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	if (ddr_freq < 2350) {
+		if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
+			/* four chip-selects */
+			popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+					  DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+			popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
+			popts->twot_en = 1; /* enable 2T timing */
+		} else {
+			popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+					  DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+			popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+					  DDR_CDR2_VREF_RANGE_2;
+		}
+	} else {
+		popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+				  DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
+		popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
+				  DDR_CDR2_VREF_RANGE_2;
+	}
+}
+
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
+#else
+int fsl_initdram(void)
+{
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	gd->ram_size = fsl_ddr_sdram_size();
+#else
+	puts("Initializing DDR....using SPD\n");
+
+	gd->ram_size = fsl_ddr_sdram();
+#endif
+
+	return 0;
+}
+#endif /* CONFIG_TFABOOT */
diff --git a/roms/u-boot/board/freescale/ls2080aqds/ddr.h b/roms/u-boot/board/freescale/ls2080aqds/ddr.h
new file mode 100644
index 000000000..b5d790a4a
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080aqds/ddr.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2300, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
+	{}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters udimm2[] = {
+	/*
+	 * memory controller 2
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1666, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1900, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  2200, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
+	{}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters rdimm2[] = {
+	/*
+	 * memory controller 2
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x0B0A090C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+	udimm0,
+	udimm2,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+	rdimm0,
+	rdimm2,
+};
+
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls2080aqds/eth.c b/roms/u-boot/board/freescale/ls2080aqds/eth.c
new file mode 100644
index 000000000..914cd0a9a
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080aqds/eth.c
@@ -0,0 +1,1090 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <env.h>
+#include <log.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+#include <hwconfig.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include <linux/delay.h>
+
+#include "../common/qixis.h"
+
+#include "ls2080aqds_qixis.h"
+
+#define MC_BOOT_ENV_VAR "mcinitcmd"
+
+#ifndef CONFIG_DM_ETH
+
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+ /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
+ *   Bank 1 -> Lanes A, B, C, D, E, F, G, H
+ *   Bank 2 -> Lanes A,B, C, D, E, F, G, H
+ */
+
+ /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
+  * means that the mapping must be determined dynamically, or that the lane
+  * maps to something other than a board slot.
+  */
+
+static u8 lane_to_slot_fsm1[] = {
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 lane_to_slot_fsm2[] = {
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
+ * housed.
+ */
+
+static int xqsgii_riser_phy_addr[] = {
+	XQSGMII_CARD_PHY1_PORT0_ADDR,
+	XQSGMII_CARD_PHY2_PORT0_ADDR,
+	XQSGMII_CARD_PHY3_PORT0_ADDR,
+	XQSGMII_CARD_PHY4_PORT0_ADDR,
+	XQSGMII_CARD_PHY3_PORT2_ADDR,
+	XQSGMII_CARD_PHY1_PORT2_ADDR,
+	XQSGMII_CARD_PHY4_PORT2_ADDR,
+	XQSGMII_CARD_PHY2_PORT2_ADDR,
+};
+
+static int sgmii_riser_phy_addr[] = {
+	SGMII_CARD_PORT1_PHY_ADDR,
+	SGMII_CARD_PORT2_PHY_ADDR,
+	SGMII_CARD_PORT3_PHY_ADDR,
+	SGMII_CARD_PORT4_PHY_ADDR,
+};
+
+/* Slot2 does not have EMI connections */
+#define EMI_NONE	0xFF
+#define EMI1_SLOT1	0
+#define EMI1_SLOT2	1
+#define EMI1_SLOT3	2
+#define EMI1_SLOT4	3
+#define EMI1_SLOT5	4
+#define EMI1_SLOT6	5
+#define EMI2		6
+#define SFP_TX		0
+
+static const char * const mdio_names[] = {
+	"LS2080A_QDS_MDIO0",
+	"LS2080A_QDS_MDIO1",
+	"LS2080A_QDS_MDIO2",
+	"LS2080A_QDS_MDIO3",
+	"LS2080A_QDS_MDIO4",
+	"LS2080A_QDS_MDIO5",
+	DEFAULT_WRIOP_MDIO2_NAME,
+};
+
+struct ls2080a_qds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+struct reg_pair {
+	uint addr;
+	u8 *val;
+};
+
+static void sgmii_configure_repeater(int serdes_port)
+{
+	struct mii_dev *bus;
+	uint8_t a = 0xf;
+	int i, j, k, ret;
+	int dpmac_id = 0, dpmac, mii_bus = 0;
+	unsigned short value;
+	char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
+	uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
+
+	uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
+	uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
+	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+
+	u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+	struct reg_pair reg_pair[10] = {
+			{6, &reg_val[0]}, {4, &reg_val[1]},
+			{8, &reg_val[2]}, {0xf, NULL},
+			{0x11, NULL}, {0x16, NULL},
+			{0x18, NULL}, {0x23, &reg_val[3]},
+			{0x2d, &reg_val[4]}, {4, &reg_val[5]},
+	};
+
+	int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *udev;
+#endif
+
+	/* Set I2c to Slot 1 */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+	ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+	if (!ret)
+		ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+	if (ret)
+		goto error;
+
+	for (dpmac = 0; dpmac < 8; dpmac++) {
+		/* Check the PHY status */
+		switch (serdes_port) {
+		case 1:
+			mii_bus = 0;
+			dpmac_id = dpmac + 1;
+			break;
+		case 2:
+			mii_bus = 1;
+			dpmac_id = dpmac + 9;
+			a = 0xb;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+			ret = i2c_write(0x76, 0, 0, &a, 1);
+#else
+			ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
+			if (!ret)
+				ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+			if (ret)
+				goto error;
+			break;
+		}
+
+		ret = miiphy_set_current_dev(dev[mii_bus]);
+		if (ret > 0)
+			goto error;
+
+		bus = mdio_get_current_dev();
+		debug("Reading from bus %s\n", bus->name);
+
+		ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
+				   3);
+		if (ret > 0)
+			goto error;
+
+		mdelay(10);
+		ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
+				  &value);
+		if (ret > 0)
+			goto error;
+
+		mdelay(10);
+
+		if ((value & 0xfff) == 0x401) {
+			printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
+			miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
+				     0x1f, 0);
+			continue;
+		}
+
+		for (i = 0; i < 4; i++) {
+			for (j = 0; j < 4; j++) {
+				reg_pair[3].val = &ch_a_eq[i];
+				reg_pair[4].val = &ch_a_ctl2[j];
+				reg_pair[5].val = &ch_b_eq[i];
+				reg_pair[6].val = &ch_b_ctl2[j];
+
+				for (k = 0; k < 10; k++) {
+#if !CONFIG_IS_ENABLED(DM_I2C)
+					ret = i2c_write(i2c_addr[dpmac],
+							reg_pair[k].addr,
+							1, reg_pair[k].val, 1);
+#else
+					ret = i2c_get_chip_for_busnum(0,
+							    i2c_addr[dpmac],
+							    1, &udev);
+					if (!ret)
+						ret = dm_i2c_write(udev,
+							  reg_pair[k].addr,
+							  reg_pair[k].val, 1);
+#endif
+					if (ret)
+						goto error;
+				}
+
+				mdelay(100);
+				ret = miiphy_read(dev[mii_bus],
+						  riser_phy_addr[dpmac],
+						  0x11, &value);
+				if (ret > 0)
+					goto error;
+
+				mdelay(100);
+				ret = miiphy_read(dev[mii_bus],
+						  riser_phy_addr[dpmac],
+						  0x11, &value);
+				if (ret > 0)
+					goto error;
+
+				if ((value & 0xfff) == 0x401) {
+					printf("DPMAC %d :PHY is configured ",
+					       dpmac_id);
+					printf("after setting repeater 0x%x\n",
+					       value);
+					i = 5;
+					j = 5;
+				} else {
+					printf("DPMAC %d :PHY is failed to ",
+					       dpmac_id);
+					printf("configure the repeater 0x%x\n",
+					       value);
+				}
+			}
+		}
+		miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
+	}
+error:
+	if (ret)
+		printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
+	return;
+}
+
+static void qsgmii_configure_repeater(int dpmac)
+{
+	uint8_t a = 0xf;
+	int i, j, k;
+	int i2c_phy_addr = 0;
+	int phy_addr = 0;
+	int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
+
+	uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
+	uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
+	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+
+	u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+	struct reg_pair reg_pair[10] = {
+		{6, &reg_val[0]}, {4, &reg_val[1]},
+		{8, &reg_val[2]}, {0xf, NULL},
+		{0x11, NULL}, {0x16, NULL},
+		{0x18, NULL}, {0x23, &reg_val[3]},
+		{0x2d, &reg_val[4]}, {4, &reg_val[5]},
+	};
+
+	const char *dev = "LS2080A_QDS_MDIO0";
+	int ret = 0;
+	unsigned short value;
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *udev;
+#endif
+
+	/* Set I2c to Slot 1 */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+	ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+	if (!ret)
+		ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+	if (ret)
+		goto error;
+
+	switch (dpmac) {
+	case 1:
+	case 2:
+	case 3:
+	case 4:
+		i2c_phy_addr = i2c_addr[0];
+		phy_addr = 0;
+		break;
+
+	case 5:
+	case 6:
+	case 7:
+	case 8:
+		i2c_phy_addr = i2c_addr[1];
+		phy_addr = 4;
+		break;
+
+	case 9:
+	case 10:
+	case 11:
+	case 12:
+		i2c_phy_addr = i2c_addr[2];
+		phy_addr = 8;
+		break;
+
+	case 13:
+	case 14:
+	case 15:
+	case 16:
+		i2c_phy_addr = i2c_addr[3];
+		phy_addr = 0xc;
+		break;
+	}
+
+	/* Check the PHY status */
+	ret = miiphy_set_current_dev(dev);
+	ret = miiphy_write(dev, phy_addr, 0x1f, 3);
+	mdelay(10);
+	ret = miiphy_read(dev, phy_addr, 0x11, &value);
+	mdelay(10);
+	ret = miiphy_read(dev, phy_addr, 0x11, &value);
+	mdelay(10);
+	if ((value & 0xf) == 0xf) {
+		printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
+		return;
+	}
+
+	for (i = 0; i < 4; i++) {
+		for (j = 0; j < 4; j++) {
+			reg_pair[3].val = &ch_a_eq[i];
+			reg_pair[4].val = &ch_a_ctl2[j];
+			reg_pair[5].val = &ch_b_eq[i];
+			reg_pair[6].val = &ch_b_ctl2[j];
+
+			for (k = 0; k < 10; k++) {
+#if !CONFIG_IS_ENABLED(DM_I2C)
+				ret = i2c_write(i2c_phy_addr,
+						reg_pair[k].addr,
+						1, reg_pair[k].val, 1);
+#else
+				ret = i2c_get_chip_for_busnum(0,
+							      i2c_phy_addr,
+							      1, &udev);
+				if (!ret)
+					ret = dm_i2c_write(udev,
+							   reg_pair[k].addr,
+							   reg_pair[k].val, 1);
+#endif
+				if (ret)
+					goto error;
+			}
+
+			mdelay(100);
+			ret = miiphy_read(dev, phy_addr, 0x11, &value);
+			if (ret > 0)
+				goto error;
+			mdelay(1);
+			ret = miiphy_read(dev, phy_addr, 0x11, &value);
+			if (ret > 0)
+				goto error;
+			mdelay(10);
+			if ((value & 0xf) == 0xf) {
+				printf("DPMAC %d :PHY is ..... Configured\n",
+				       dpmac);
+				return;
+			}
+		}
+	}
+error:
+	printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
+	return;
+}
+
+static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+	struct mii_dev *bus;
+	const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+static void ls2080a_qds_enable_SFP_TX(u8 muxval)
+{
+	u8 brdcfg9;
+
+	brdcfg9 = QIXIS_READ(brdcfg[9]);
+	brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
+	brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
+	QIXIS_WRITE(brdcfg[9], brdcfg9);
+}
+
+static void ls2080a_qds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+
+	if (muxval <= 5) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
+				 int devad, int regnum)
+{
+	struct ls2080a_qds_mdio *priv = bus->priv;
+
+	ls2080a_qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				  int regnum, u16 value)
+{
+	struct ls2080a_qds_mdio *priv = bus->priv;
+
+	ls2080a_qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
+{
+	struct ls2080a_qds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct ls2080a_qds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate ls2080a_qds MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate ls2080a_qds private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = ls2080a_qds_mdio_read;
+	bus->write = ls2080a_qds_mdio_write;
+	bus->reset = ls2080a_qds_mdio_reset;
+	strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+
+	return mdio_register(bus);
+}
+
+/*
+ * Initialize the dpmac_info array.
+ *
+ */
+static void initialize_dpmac_to_slot(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+	int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+	char *env_hwconfig;
+	env_hwconfig = env_get("hwconfig");
+
+	switch (serdes1_prtcl) {
+	case 0x07:
+	case 0x09:
+	case 0x33:
+		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		lane_to_slot_fsm1[0] = EMI1_SLOT1;
+		lane_to_slot_fsm1[1] = EMI1_SLOT1;
+		lane_to_slot_fsm1[2] = EMI1_SLOT1;
+		lane_to_slot_fsm1[3] = EMI1_SLOT1;
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm1[4] = EMI1_SLOT1;
+			lane_to_slot_fsm1[5] = EMI1_SLOT1;
+			lane_to_slot_fsm1[6] = EMI1_SLOT1;
+			lane_to_slot_fsm1[7] = EMI1_SLOT1;
+		} else {
+			lane_to_slot_fsm1[4] = EMI1_SLOT2;
+			lane_to_slot_fsm1[5] = EMI1_SLOT2;
+			lane_to_slot_fsm1[6] = EMI1_SLOT2;
+			lane_to_slot_fsm1[7] = EMI1_SLOT2;
+		}
+		break;
+
+	case 0x39:
+		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm1[0] = EMI1_SLOT3;
+			lane_to_slot_fsm1[1] = EMI1_SLOT3;
+			lane_to_slot_fsm1[2] = EMI1_SLOT3;
+			lane_to_slot_fsm1[3] = EMI_NONE;
+		} else {
+			lane_to_slot_fsm1[0] = EMI_NONE;
+			lane_to_slot_fsm1[1] = EMI_NONE;
+			lane_to_slot_fsm1[2] = EMI_NONE;
+			lane_to_slot_fsm1[3] = EMI_NONE;
+		}
+		lane_to_slot_fsm1[4] = EMI1_SLOT3;
+		lane_to_slot_fsm1[5] = EMI1_SLOT3;
+		lane_to_slot_fsm1[6] = EMI1_SLOT3;
+		lane_to_slot_fsm1[7] = EMI_NONE;
+		break;
+
+	case 0x4D:
+		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm1[0] = EMI1_SLOT3;
+			lane_to_slot_fsm1[1] = EMI1_SLOT3;
+			lane_to_slot_fsm1[2] = EMI_NONE;
+			lane_to_slot_fsm1[3] = EMI_NONE;
+		} else {
+			lane_to_slot_fsm1[0] = EMI_NONE;
+			lane_to_slot_fsm1[1] = EMI_NONE;
+			lane_to_slot_fsm1[2] = EMI_NONE;
+			lane_to_slot_fsm1[3] = EMI_NONE;
+		}
+		lane_to_slot_fsm1[4] = EMI1_SLOT3;
+		lane_to_slot_fsm1[5] = EMI1_SLOT3;
+		lane_to_slot_fsm1[6] = EMI_NONE;
+		lane_to_slot_fsm1[7] = EMI_NONE;
+		break;
+
+	case 0x2A:
+	case 0x4B:
+	case 0x4C:
+		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		break;
+	default:
+		printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+		       __func__, serdes1_prtcl);
+		break;
+	}
+
+	switch (serdes2_prtcl) {
+	case 0x07:
+	case 0x08:
+	case 0x09:
+	case 0x49:
+		printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+		       serdes2_prtcl);
+		lane_to_slot_fsm2[0] = EMI1_SLOT4;
+		lane_to_slot_fsm2[1] = EMI1_SLOT4;
+		lane_to_slot_fsm2[2] = EMI1_SLOT4;
+		lane_to_slot_fsm2[3] = EMI1_SLOT4;
+
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm2[4] = EMI1_SLOT4;
+			lane_to_slot_fsm2[5] = EMI1_SLOT4;
+			lane_to_slot_fsm2[6] = EMI1_SLOT4;
+			lane_to_slot_fsm2[7] = EMI1_SLOT4;
+		} else {
+			/* No MDIO physical connection */
+			lane_to_slot_fsm2[4] = EMI1_SLOT6;
+			lane_to_slot_fsm2[5] = EMI1_SLOT6;
+			lane_to_slot_fsm2[6] = EMI1_SLOT6;
+			lane_to_slot_fsm2[7] = EMI1_SLOT6;
+		}
+		break;
+
+	case 0x47:
+		printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+		       serdes2_prtcl);
+		lane_to_slot_fsm2[0] = EMI_NONE;
+		lane_to_slot_fsm2[1] = EMI1_SLOT5;
+		lane_to_slot_fsm2[2] = EMI1_SLOT5;
+		lane_to_slot_fsm2[3] = EMI1_SLOT5;
+
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm2[4] = EMI_NONE;
+			lane_to_slot_fsm2[5] = EMI1_SLOT5;
+			lane_to_slot_fsm2[6] = EMI1_SLOT5;
+			lane_to_slot_fsm2[7] = EMI1_SLOT5;
+		}
+		break;
+
+	case 0x57:
+		printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+		       serdes2_prtcl);
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm2[0] = EMI_NONE;
+			lane_to_slot_fsm2[1] = EMI_NONE;
+			lane_to_slot_fsm2[2] = EMI_NONE;
+			lane_to_slot_fsm2[3] = EMI_NONE;
+		}
+		lane_to_slot_fsm2[4] = EMI_NONE;
+		lane_to_slot_fsm2[5] = EMI_NONE;
+		lane_to_slot_fsm2[6] = EMI1_SLOT5;
+		lane_to_slot_fsm2[7] = EMI1_SLOT5;
+		break;
+
+	default:
+		printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
+		       __func__ , serdes2_prtcl);
+		break;
+	}
+}
+
+void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
+{
+	int lane, slot;
+	struct mii_dev *bus;
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+	int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+	int *riser_phy_addr;
+	char *env_hwconfig = env_get("hwconfig");
+
+	if (hwconfig_f("xqsgmii", env_hwconfig))
+		riser_phy_addr = &xqsgii_riser_phy_addr[0];
+	else
+		riser_phy_addr = &sgmii_riser_phy_addr[0];
+
+	if (dpmac_id > WRIOP1_DPMAC9)
+		goto serdes2;
+
+	switch (serdes1_prtcl) {
+	case 0x07:
+	case 0x39:
+	case 0x4D:
+		lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
+
+		slot = lane_to_slot_fsm1[lane];
+
+		switch (++slot) {
+		case 1:
+			/* Slot housing a SGMII riser card? */
+			wriop_set_phy_address(dpmac_id, 0,
+					      riser_phy_addr[dpmac_id - 1]);
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
+			bus = mii_dev_for_muxval(EMI1_SLOT1);
+			wriop_set_mdio(dpmac_id, bus);
+			break;
+		case 2:
+			/* Slot housing a SGMII riser card? */
+			wriop_set_phy_address(dpmac_id, 0,
+					      riser_phy_addr[dpmac_id - 1]);
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
+			bus = mii_dev_for_muxval(EMI1_SLOT2);
+			wriop_set_mdio(dpmac_id, bus);
+			break;
+		case 3:
+			if (slot == EMI_NONE)
+				return;
+			if (serdes1_prtcl == 0x39) {
+				wriop_set_phy_address(dpmac_id, 0,
+					riser_phy_addr[dpmac_id - 2]);
+				if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
+								env_hwconfig))
+					wriop_set_phy_address(dpmac_id, 0,
+						riser_phy_addr[dpmac_id - 3]);
+			} else {
+				wriop_set_phy_address(dpmac_id, 0,
+					riser_phy_addr[dpmac_id - 2]);
+				if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
+								env_hwconfig))
+					wriop_set_phy_address(dpmac_id, 0,
+						riser_phy_addr[dpmac_id - 3]);
+			}
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
+			bus = mii_dev_for_muxval(EMI1_SLOT3);
+			wriop_set_mdio(dpmac_id, bus);
+			break;
+		case 4:
+			break;
+		case 5:
+			break;
+		case 6:
+			break;
+		}
+	break;
+	default:
+		printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+		       __func__ , serdes1_prtcl);
+	break;
+	}
+
+serdes2:
+	switch (serdes2_prtcl) {
+	case 0x07:
+	case 0x08:
+	case 0x49:
+	case 0x47:
+	case 0x57:
+		lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
+							(dpmac_id - 9));
+		slot = lane_to_slot_fsm2[lane];
+
+		switch (++slot) {
+		case 1:
+			break;
+		case 3:
+			break;
+		case 4:
+			/* Slot housing a SGMII riser card? */
+			wriop_set_phy_address(dpmac_id, 0,
+					      riser_phy_addr[dpmac_id - 9]);
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
+			bus = mii_dev_for_muxval(EMI1_SLOT4);
+			wriop_set_mdio(dpmac_id, bus);
+		break;
+		case 5:
+			if (slot == EMI_NONE)
+				return;
+			if (serdes2_prtcl == 0x47) {
+				wriop_set_phy_address(dpmac_id, 0,
+					      riser_phy_addr[dpmac_id - 10]);
+				if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
+								 env_hwconfig))
+					wriop_set_phy_address(dpmac_id, 0,
+						riser_phy_addr[dpmac_id - 11]);
+			} else {
+				wriop_set_phy_address(dpmac_id, 0,
+					riser_phy_addr[dpmac_id - 11]);
+			}
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
+			bus = mii_dev_for_muxval(EMI1_SLOT5);
+			wriop_set_mdio(dpmac_id, bus);
+			break;
+		case 6:
+			/* Slot housing a SGMII riser card? */
+			wriop_set_phy_address(dpmac_id, 0,
+					      riser_phy_addr[dpmac_id - 13]);
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
+			bus = mii_dev_for_muxval(EMI1_SLOT6);
+			wriop_set_mdio(dpmac_id, bus);
+		break;
+	}
+	break;
+	default:
+		printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
+		       __func__, serdes2_prtcl);
+	break;
+	}
+}
+
+void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
+{
+	int lane = 0, slot;
+	struct mii_dev *bus;
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	switch (serdes1_prtcl) {
+	case 0x33:
+		switch (dpmac_id) {
+		case 1:
+		case 2:
+		case 3:
+		case 4:
+			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
+		break;
+		case 5:
+		case 6:
+		case 7:
+		case 8:
+			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
+		break;
+		case 9:
+		case 10:
+		case 11:
+		case 12:
+			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
+		break;
+		case 13:
+		case 14:
+		case 15:
+		case 16:
+			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
+		break;
+	}
+
+		slot = lane_to_slot_fsm1[lane];
+
+		switch (++slot) {
+		case 1:
+			/* Slot housing a QSGMII riser card? */
+			wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
+			bus = mii_dev_for_muxval(EMI1_SLOT1);
+			wriop_set_mdio(dpmac_id, bus);
+			break;
+		case 3:
+			break;
+		case 4:
+			break;
+		case 5:
+		break;
+		case 6:
+			break;
+	}
+	break;
+	default:
+		printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+		       serdes1_prtcl);
+	break;
+	}
+
+	qsgmii_configure_repeater(dpmac_id);
+}
+
+void ls2080a_handle_phy_interface_xsgmii(int i)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	switch (serdes1_prtcl) {
+	case 0x2A:
+	case 0x4B:
+	case 0x4C:
+		/*
+		 * XFI does not need a PHY to work, but to avoid U-Boot use
+		 * default PHY address which is zero to a MAC when it found
+		 * a MAC has no PHY address, we give a PHY address to XFI
+		 * MAC, and should not use a real XAUI PHY address, since
+		 * MDIO can access it successfully, and then MDIO thinks
+		 * the XAUI card is used for the XFI MAC, which will cause
+		 * error.
+		 */
+		wriop_set_phy_address(i, 0, i + 4);
+		ls2080a_qds_enable_SFP_TX(SFP_TX);
+
+		break;
+	default:
+		printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		break;
+	}
+}
+#endif
+#endif // !CONFIG_DM_ETH
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifndef CONFIG_DM_ETH
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+	int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
+		>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+	struct memac_mdio_info *memac_mdio0_info;
+	struct memac_mdio_info *memac_mdio1_info;
+	unsigned int i;
+	char *env_hwconfig;
+	int error;
+
+	env_hwconfig = env_get("hwconfig");
+
+	initialize_dpmac_to_slot();
+
+	memac_mdio0_info = (struct memac_mdio_info *)malloc(
+					sizeof(struct memac_mdio_info));
+	memac_mdio0_info->regs =
+		(struct memac_mdio_controller *)
+					CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
+
+	/* Register the real MDIO1 bus */
+	fm_memac_mdio_init(bis, memac_mdio0_info);
+
+	memac_mdio1_info = (struct memac_mdio_info *)malloc(
+					sizeof(struct memac_mdio_info));
+	memac_mdio1_info->regs =
+		(struct memac_mdio_controller *)
+					CONFIG_SYS_FSL_WRIOP1_MDIO2;
+	memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
+
+	/* Register the real MDIO2 bus */
+	fm_memac_mdio_init(bis, memac_mdio1_info);
+
+	/* Register the muxing front-ends to the MDIO buses */
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
+
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
+
+	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+		switch (wriop_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_QSGMII:
+			ls2080a_handle_phy_interface_qsgmii(i);
+			break;
+		case PHY_INTERFACE_MODE_SGMII:
+			ls2080a_handle_phy_interface_sgmii(i);
+			break;
+		case PHY_INTERFACE_MODE_XGMII:
+			ls2080a_handle_phy_interface_xsgmii(i);
+			break;
+		default:
+			break;
+
+		if (i == 16)
+			i = NUM_WRIOP_PORTS;
+		}
+	}
+
+	error = cpu_eth_init(bis);
+
+	if (hwconfig_f("xqsgmii", env_hwconfig)) {
+		if (serdes1_prtcl == 0x7)
+			sgmii_configure_repeater(1);
+		if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
+		    serdes2_prtcl == 0x49)
+			sgmii_configure_repeater(2);
+	}
+#endif
+#endif // !CONFIG_DM_ETH
+
+#ifdef CONFIG_DM_ETH
+	return 0;
+#else
+	return pci_eth_init(bis);
+#endif
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+	mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+
+/* Structure to hold SERDES protocols supported in case of
+ * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+ *
+ * @serdes_block: the index of the SERDES block
+ * @serdes_protocol: the decimal value of the protocol supported
+ * @dts_needed: DTS notes describing the current configuration are needed
+ *
+ * When dts_needed is true, the board_fit_config_name_match() function
+ * will try to exactly match the current configuration of the block with a DTS
+ * name provided.
+ */
+static struct serdes_configuration {
+	u8 serdes_block;
+	u32 serdes_protocol;
+	bool dts_needed;
+} supported_protocols[] = {
+	/* Serdes block #1 */
+	{1, 42, true},
+
+	/* Serdes block #2 */
+	{2, 65, false},
+};
+
+#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
+
+static bool protocol_supported(u8 serdes_block, u32 protocol)
+{
+	struct serdes_configuration serdes_conf;
+	int i;
+
+	for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+		serdes_conf = supported_protocols[i];
+		if (serdes_conf.serdes_block == serdes_block &&
+		    serdes_conf.serdes_protocol == protocol)
+			return true;
+	}
+
+	return false;
+}
+
+static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
+{
+	struct serdes_configuration serdes_conf;
+	int i;
+
+	for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+		serdes_conf = supported_protocols[i];
+		if (serdes_conf.serdes_block == serdes_block &&
+		    serdes_conf.serdes_protocol == protocol) {
+			if (serdes_conf.dts_needed == true)
+				sprintf(str, "%u", protocol);
+			else
+				sprintf(str, "x");
+			return;
+		}
+	}
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 rcw_status = in_le32(&gur->rcwsr[28]);
+	char srds_s1_str[2], srds_s2_str[2];
+	u32 srds_s1, srds_s2;
+	char expected_dts[100];
+
+	srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+	srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+	/* Check for supported protocols. The default DTS will be used
+	 * in this case
+	 */
+	if (!protocol_supported(1, srds_s1) ||
+	    !protocol_supported(2, srds_s2))
+		return -1;
+
+	get_str_protocol(1, srds_s1, srds_s1_str);
+	get_str_protocol(2, srds_s2, srds_s2_str);
+
+	printf("expected_dts %s\n", expected_dts);
+	sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s",
+		srds_s1_str, srds_s2_str);
+
+	if (!strcmp(name, expected_dts))
+		return 0;
+
+	printf("this is not!\n");
+	return -1;
+}
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls2080aqds/ls2080aqds.c b/roms/u-boot/board/freescale/ls2080aqds/ls2080aqds.c
new file mode 100644
index 000000000..957231923
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080aqds/ls2080aqds.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor
+ */
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <fsl-mc/fsl_mc.h>
+#include <env_internal.h>
+#include <i2c.h>
+#include <rtc.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <fsl_sec.h>
+#include <asm/arch/ppa.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+
+
+#include "../common/qixis.h"
+#include "ls2080aqds_qixis.h"
+#include "../common/vid.h"
+
+#define PIN_MUX_SEL_SDHC	0x00
+#define PIN_MUX_SEL_DSPI	0x0a
+#define SCFG_QSPICLKCTRL_DIV_20	(5 << 27)
+
+#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	MUX_TYPE_SDHC,
+	MUX_TYPE_DSPI,
+};
+
+unsigned long long get_qixis_addr(void)
+{
+	unsigned long long addr;
+
+	if (gd->flags & GD_FLG_RELOC)
+		addr = QIXIS_BASE_PHYS;
+	else
+		addr = QIXIS_BASE_PHYS_EARLY;
+
+	/*
+	 * IFC address under 256MB is mapped to 0x30000000, any address above
+	 * is mapped to 0x5_10000000 up to 4GB.
+	 */
+	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
+
+	return addr;
+}
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+	static const char *const freq[] = {"100", "125", "156.25",
+					    "100 separate SSCG"};
+	int clock;
+
+	cpu_name(buf);
+	printf("Board: %s-QDS, ", buf);
+
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("PromJet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else if (sw == 0xf)
+		puts("QSPI\n");
+	else if (sw == 0x15)
+		printf("IFCCard\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+	printf("FPGA: v%d (%s), build %d",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+
+	/*
+	 * Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES1 Reference : ");
+	sw = QIXIS_READ(brdcfg[2]);
+	clock = (sw >> 6) & 3;
+	printf("Clock1 = %sMHz ", freq[clock]);
+	clock = (sw >> 4) & 3;
+	printf("Clock2 = %sMHz", freq[clock]);
+
+	puts("\nSERDES2 Reference : ");
+	clock = (sw >> 2) & 3;
+	printf("Clock1 = %sMHz ", freq[clock]);
+	clock = (sw >> 0) & 3;
+	printf("Clock2 = %sMHz\n", freq[clock]);
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, 0, &ch, 1);
+
+#else
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int config_board_mux(int ctrl_type)
+{
+	u8 reg5;
+
+	reg5 = QIXIS_READ(brdcfg[5]);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_SDHC:
+		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
+		break;
+	case MUX_TYPE_DSPI:
+		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
+		break;
+	default:
+		printf("Wrong mux interface type\n");
+		return -1;
+	}
+
+	QIXIS_WRITE(brdcfg[5], reg5);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	char *env_hwconfig;
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 val;
+
+	init_final_memctl_regs();
+
+	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
+
+	env_hwconfig = env_get("hwconfig");
+
+	if (hwconfig_f("dspi", env_hwconfig) &&
+	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
+		config_board_mux(MUX_TYPE_DSPI);
+	else
+		config_board_mux(MUX_TYPE_SDHC);
+
+#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
+	val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+	if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+		QIXIS_WRITE(brdcfg[9],
+			    (QIXIS_READ(brdcfg[9]) & 0xf8) |
+			     FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
+#if CONFIG_IS_ENABLED(DM_I2C)
+	rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
+#else
+	rtc_enable_32khz_output();
+#endif
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+	pci_init();
+#endif
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
+	fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+	/* input clk: 1/2 platform clk, output: input/20 */
+	out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	if (adjust_vdd(0))
+		printf("Warning: Adjusting core voltage failed.\n");
+
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
+		puts("\nDP-DDR ");
+		print_size(gd->bd->bi_dram[2].size, "");
+		print_ddr_info(CONFIG_DP_DDR_CTRL);
+	}
+#endif
+}
+
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+void fdt_fixup_board_enet(void *fdt)
+{
+	int offset;
+
+	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/fsl-mc");
+
+	if (offset < 0) {
+		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
+		       __func__, offset);
+		return;
+	}
+
+	if (get_mc_boot_status() == 0 &&
+	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
+		fdt_status_okay(fdt, offset);
+	else
+		fdt_status_fail(fdt, offset);
+}
+
+void board_quiesce_devices(void)
+{
+	fsl_mc_ldpaa_exit(gd->bd);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	ft_cpu_setup(blob, bd);
+
+	/* fixup DT for the two GPP DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+#ifdef CONFIG_RESV_RAM
+	/* reduce size if reserved memory is within this bank */
+	if (gd->arch.resv_ram >= base[0] &&
+	    gd->arch.resv_ram < base[0] + size[0])
+		size[0] = gd->arch.resv_ram - base[0];
+	else if (gd->arch.resv_ram >= base[1] &&
+		 gd->arch.resv_ram < base[1] + size[1])
+		size[1] = gd->arch.resv_ram - base[1];
+#endif
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
+
+	fdt_fsl_mc_fixup_iommu_map_entry(blob);
+
+	fsl_fdt_fixup_dr_usb(blob, bd);
+
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+	fdt_fixup_board_enet(blob);
+#endif
+
+	fdt_fixup_icid(blob);
+
+	return 0;
+}
+#endif
+
+void qixis_dump_switch(void)
+{
+	int i, nr_of_cfgsw;
+
+	QIXIS_WRITE(cms[0], 0x00);
+	nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+	puts("DIP switch settings dump:\n");
+	for (i = 1; i <= nr_of_cfgsw; i++) {
+		QIXIS_WRITE(cms[0], i);
+		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+	}
+}
diff --git a/roms/u-boot/board/freescale/ls2080aqds/ls2080aqds_qixis.h b/roms/u-boot/board/freescale/ls2080aqds/ls2080aqds_qixis.h
new file mode 100644
index 000000000..7b2607b8d
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080aqds/ls2080aqds_qixis.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __LS2_QDS_QIXIS_H__
+#define __LS2_QDS_QIXIS_H__
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+#define BRDCFG4_EMISEL_MASK		0xE0
+#define BRDCFG4_EMISEL_SHIFT		5
+#define BRDCFG9_SFPTX_MASK		0x10
+#define BRDCFG9_SFPTX_SHIFT		4
+#endif /*__LS2_QDS_QIXIS_H__*/
diff --git a/roms/u-boot/board/freescale/ls2080ardb/Kconfig b/roms/u-boot/board/freescale/ls2080ardb/Kconfig
new file mode 100644
index 000000000..678d58257
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080ardb/Kconfig
@@ -0,0 +1,35 @@
+if TARGET_LS2080ARDB || TARGET_LS2081ARDB
+
+config SYS_BOARD
+	default "ls2080ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls2080ardb"
+
+source "board/freescale/common/Kconfig"
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+	hex "PPA Firmware Addr"
+	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x580400000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA Firmware HDR Addr"
+	default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x580680000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/ls2080ardb/MAINTAINERS b/roms/u-boot/board/freescale/ls2080ardb/MAINTAINERS
new file mode 100644
index 000000000..6e25b82db
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080ardb/MAINTAINERS
@@ -0,0 +1,31 @@
+LS2080A BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	board/freescale/ls2080ardb/
+F:	board/freescale/ls2080a/ls2080ardb.c
+F:	include/configs/ls2080ardb.h
+F:	configs/ls2080ardb_defconfig
+F:	configs/ls2080ardb_nand_defconfig
+
+LS2088A_QSPI-boot BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat@nxp.com>
+S:	Maintained
+F:	configs/ls2088ardb_qspi_defconfig
+F:	configs/ls2088ardb_tfa_defconfig
+F:	configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+
+LS2081ARDB BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	configs/ls2081ardb_defconfig
+
+LS2080A_SECURE_BOOT BOARD
+M:	Udit Agarwal <udit.agarwal@nxp.com>
+S:	Maintained
+F:	configs/ls2080ardb_SECURE_BOOT_defconfig
+
+LS2088A_QSPI_SECURE_BOOT BOARD
+M:	Udit Agarwal <udit.agarwal@nxp.com>
+S:	Maintained
+F:	configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/ls2080ardb/Makefile b/roms/u-boot/board/freescale/ls2080ardb/Makefile
new file mode 100644
index 000000000..ed44d459f
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080ardb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2015 Freescale Semiconductor
+
+obj-y += ls2080ardb.o eth_ls2080rdb.o
+obj-y += ddr.o
diff --git a/roms/u-boot/board/freescale/ls2080ardb/README b/roms/u-boot/board/freescale/ls2080ardb/README
new file mode 100644
index 000000000..205c45cb2
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080ardb/README
@@ -0,0 +1,135 @@
+Overview
+--------
+The LS2080A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
+Layerscape Architecture processor.
+
+The LS2081A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2081A
+Layerscape Architecture processor.More details in below sections
+
+LS2080A, LS2088A, LS2081A SoC Overview
+--------------------------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
+LS2081A, LS2088A SoC overview.
+
+ LS2080ARDB board Overview
+ -----------------------
+ - SERDES Connections, 16 lanes supporting:
+      - PCI Express - 3.0
+      - SATA 3.0
+      - XFI
+ - DDR Controller
+     - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
+       chip-selects and two DIMM connectors. Support is up to 2133MT/s.
+     - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
+       and two DIMM connectors. Support is up to 1600MT/s.
+ -IFC/Local Bus
+    - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
+    - 128 MB NOR flash 16-bit data bus
+    - One 2 GB NAND flash with ECC support
+    - CPLD connection
+ - USB 3.0
+    - Two high speed USB 3.0 ports
+    - First USB 3.0 port configured as Host with Type-A connector
+    - Second USB 3.0 port configured as OTG with micro-AB connector
+ - SDHC adapter
+    - SD Card Rev 2.0 and Rev 3.0
+ - DSPI
+    - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz)
+ - 4 I2C controllers
+ - Two SATA onboard connectors
+ - UART
+ - ARM JTAG support
+
+ LS2081ARDB board Overview
+ -------------------------
+ LS2081ARDB board is similar to LS2080ARDB board
+ with few differences like
+  - Hosts LS2081A SoC
+  - Default boot source is QSPI-boot
+  - Does not have IFC interface
+  - RTC and QSPI flash devices are different
+  - Provides QIXIS access via I2C
+
+Memory map from core's view
+----------------------------
+0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
+0x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
+0x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
+0x00_2000_0000 .. 0x00_2FFF_FFFF	QSPI region #1
+0x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
+0x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
+0x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
+0x80_8000_0000 .. 0xFF_FFFF_FFFF	DDR region #2
+
+Other addresses are either reserved, or not used directly by U-Boot.
+This list should be updated when more addresses are used.
+
+IFC region map from core's view
+-------------------------------
+During boot i.e. IFC Region #1:-
+  0x30000000 - 0x37ffffff : 128MB : NOR flash
+  0x3C000000 - 0x40000000 : 64MB  : CPLD
+
+After relocate to DDR i.e. IFC Region #2:-
+  0x5_1000_0000..0x5_1fff_ffff	Memory Hole
+  0x5_2000_0000..0x5_3fff_ffff	IFC CSx (CPLD, NAND and others 512MB)
+  0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
+  0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
+  0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
+
+Booting Options
+---------------
+a) NOR boot
+b) NAND boot
+c) QSPI boot
+
+Memory map for NOR boot
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Secure Headers			0x00600000
+Cortina PHY firmware		0x00980000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
+
+cfg_rcw_src switches needs to be changed for booting from different option.
+Refer to board documentation for correct switch setting.
+
+QSPI boot details
+===================
+Supported only for
+ LS2088ARDB RevF board with LS2088A SoC.
+
+Images needs to be copied to QSPI flash
+as per memory map given below.
+
+Memory map for QSPI flash
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Cortina PHY firmware		0x00980000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
+
+Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
+-------------------------------------------------------------------
+One needs to use appropriate bootargs to boot Linux flavors which do
+not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
+below:
+
+=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
+   earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
+   hugepages=16 mem=2048M'
+
diff --git a/roms/u-boot/board/freescale/ls2080ardb/ddr.c b/roms/u-boot/board/freescale/ls2080ardb/ddr.c
new file mode 100644
index 000000000..07fa84733
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080ardb/ddr.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <log.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/clock.h>
+#include <asm/global_data.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+	u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+	int slot;
+
+	if (ctrl_num > 2) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+
+	for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
+		if (pdimm[slot].n_ranks)
+			break;
+	}
+
+	if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
+		return;
+
+	/*
+	 * we use identical timing for all slots. If needed, change the code
+	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+	 */
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[ctrl_num];
+	else
+		pbsp = udimms[ctrl_num];
+
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm[slot].n_ranks &&
+		    (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for data rate %lu MT/s\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
+		if (popts->registered_dimm_en)
+			printf("WARN: RDIMM not supported.\n");
+		/* force DDR bus width to 32 bits */
+		popts->data_bus_width = 1;
+		popts->otf_burst_chop_en = 0;
+		popts->burst_length = DDR_BL8;
+		popts->bstopre = 0;	/* enable auto precharge */
+		/*
+		 * Layout optimization results byte mapping
+		 * Byte 0 -> Byte ECC
+		 * Byte 1 -> Byte 3
+		 * Byte 2 -> Byte 2
+		 * Byte 3 -> Byte 1
+		 * Byte ECC -> Byte 0
+		 */
+		dq_mapping_0 = pdimm[slot].dq_mapping[0];
+		dq_mapping_2 = pdimm[slot].dq_mapping[2];
+		dq_mapping_3 = pdimm[slot].dq_mapping[3];
+		pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
+		pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
+		pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
+		pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
+		pdimm[slot].dq_mapping[6] = dq_mapping_2;
+		pdimm[slot].dq_mapping[7] = dq_mapping_3;
+		pdimm[slot].dq_mapping[8] = dq_mapping_0;
+		pdimm[slot].dq_mapping[9] = 0;
+		pdimm[slot].dq_mapping[10] = 0;
+		pdimm[slot].dq_mapping[11] = 0;
+		pdimm[slot].dq_mapping[12] = 0;
+		pdimm[slot].dq_mapping[13] = 0;
+		pdimm[slot].dq_mapping[14] = 0;
+		pdimm[slot].dq_mapping[15] = 0;
+		pdimm[slot].dq_mapping[16] = 0;
+		pdimm[slot].dq_mapping[17] = 0;
+	}
+#endif
+	/* To work at higher than 1333MT/s */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0x0;	/* 32 clocks */
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x6e;
+
+	if (ddr_freq < 2350) {
+		if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
+			/* four chip-selects */
+			popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+					  DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+			popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
+			popts->twot_en = 1;	/* enable 2T timing */
+		} else {
+			popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+					  DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+			popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+					  DDR_CDR2_VREF_RANGE_2;
+		}
+	} else {
+		popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+				  DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
+		popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
+				  DDR_CDR2_VREF_RANGE_2;
+	}
+}
+
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
+#else
+int fsl_initdram(void)
+{
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	gd->ram_size = fsl_ddr_sdram_size();
+#else
+	puts("Initializing DDR....using SPD\n");
+
+	gd->ram_size = fsl_ddr_sdram();
+#endif
+
+	return 0;
+}
+#endif /* CONFIG_TFABOOT */
diff --git a/roms/u-boot/board/freescale/ls2080ardb/ddr.h b/roms/u-boot/board/freescale/ls2080ardb/ddr.h
new file mode 100644
index 000000000..c5f2a9521
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080ardb/ddr.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 10,    9, 0x090A0B0E, 0x0F11110C,},
+	{2,  1900, 0, 12,  0xA, 0x0B0C0E11, 0x1214140F,},
+	{2,  2300, 0, 12,  0xB, 0x0C0D0F12, 0x14161610,},
+	{}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters udimm2[] = {
+	/*
+	 * memory controller 2
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1666, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1900, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  2200, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1666, 0, 8,     0x0F, 0x0D0C0A09, 0x0B0C0E08,},
+	{2,  1900, 0, 8,     0x10, 0x0F0D0B0A, 0x0B0E0F09,},
+	{2,  2200, 0, 8,     0x13, 0x120F0E0B, 0x0D10110B,},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+	udimm0,
+	udimm2,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+	rdimm0,
+	udimm2,	/* DP-DDR doesn't support RDIMM */
+};
+
+
+#endif
diff --git a/roms/u-boot/board/freescale/ls2080ardb/eth_ls2080rdb.c b/roms/u-boot/board/freescale/ls2080ardb/eth_ls2080rdb.c
new file mode 100644
index 000000000..21b4c16ff
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifndef CONFIG_DM_ETH
+#if defined(CONFIG_FSL_MC_ENET)
+	int i, interface;
+	struct memac_mdio_info mdio_info;
+	struct mii_dev *dev;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 srds_s1;
+	struct memac_mdio_controller *reg;
+
+	srds_s1 = in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	mdio_info.regs = reg;
+	mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+	/* Register the EMI 1 */
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+	mdio_info.regs = reg;
+	mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+	/* Register the EMI 2 */
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	switch (srds_s1) {
+	case 0x2A:
+		wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
+		wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
+		wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
+		wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2);
+		wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3);
+		wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4);
+
+		break;
+	case 0x4B:
+		wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
+		wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
+		wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
+
+		break;
+	default:
+		printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
+		       srds_s1);
+		break;
+	}
+
+	for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
+		interface = wriop_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_XGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+			wriop_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
+		switch (wriop_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+			wriop_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FSL_MC_ENET */
+#endif /* !CONFIG_DM_ETH */
+
+#ifdef CONFIG_PHY_AQUANTIA
+	/*
+	 * Export functions to be used by AQ firmware
+	 * upload application
+	 */
+	gd->jt->strcpy = strcpy;
+	gd->jt->mdelay = mdelay;
+	gd->jt->mdio_get_current_dev = mdio_get_current_dev;
+	gd->jt->phy_find_by_mask = phy_find_by_mask;
+	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
+	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
+#endif
+
+#ifdef CONFIG_DM_ETH
+	return 0;
+#else
+	return pci_eth_init(bis);
+#endif
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+	mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/roms/u-boot/board/freescale/ls2080ardb/ls2080ardb.c b/roms/u-boot/board/freescale/ls2080ardb/ls2080ardb.c
new file mode 100644
index 000000000..3a026b082
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080ardb/ls2080ardb.c
@@ -0,0 +1,566 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor
+ * Copyright 2017 NXP
+ */
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <hwconfig.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <fsl-mc/fsl_mc.h>
+#include <env_internal.h>
+#include <efi_loader.h>
+#include <i2c.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/ppa.h>
+#include <fsl_sec.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+
+#ifdef CONFIG_FSL_QIXIS
+#include "../common/qixis.h"
+#include "ls2080ardb_qixis.h"
+#endif
+#include "../common/vid.h"
+
+#define PIN_MUX_SEL_SDHC	0x00
+#define PIN_MUX_SEL_DSPI	0x0a
+
+#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	MUX_TYPE_SDHC,
+	MUX_TYPE_DSPI,
+};
+
+#ifdef CONFIG_VID
+u16 soc_get_fuse_vid(int vid_index)
+{
+	static const u16 vdd[32] = {
+		10500,
+		0,      /* reserved */
+		9750,
+		0,      /* reserved */
+		9500,
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		9000,   /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		10000,  /* 1.0000V */
+		0,      /* reserved */
+		10250,
+		0,      /* reserved */
+		10500,
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+	};
+
+	return vdd[vid_index];
+};
+#endif
+
+unsigned long long get_qixis_addr(void)
+{
+	unsigned long long addr;
+
+	if (gd->flags & GD_FLG_RELOC)
+		addr = QIXIS_BASE_PHYS;
+	else
+		addr = QIXIS_BASE_PHYS_EARLY;
+
+	/*
+	 * IFC address under 256MB is mapped to 0x30000000, any address above
+	 * is mapped to 0x5_10000000 up to 4GB.
+	 */
+	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
+
+	return addr;
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_FSL_QIXIS
+	u8 sw;
+#endif
+	char buf[15];
+
+	cpu_name(buf);
+	printf("Board: %s-RDB, ", buf);
+
+#ifdef CONFIG_TARGET_LS2081ARDB
+#ifdef CONFIG_FSL_QIXIS
+	sw = QIXIS_READ(arch);
+	printf("Board version: %c, ", (sw & 0xf) + 'A');
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
+	switch (sw) {
+	case 0:
+		puts("boot from QSPI DEV#0\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
+		break;
+	case 1:
+		puts("boot from QSPI DEV#1\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
+		break;
+	case 2:
+		puts("boot from QSPI EMU\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
+		break;
+	case 3:
+		puts("boot from QSPI EMU\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
+		break;
+	case 4:
+		puts("boot from QSPI DEV#0\n");
+		puts("QSPI_CSA_1 mapped to QSPI EMU\n");
+		break;
+	default:
+		printf("invalid setting of SW%u\n", sw);
+		break;
+	}
+	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
+#endif
+	puts("SERDES1 Reference : ");
+	printf("Clock1 = 100MHz ");
+	printf("Clock2 = 161.13MHz");
+#else
+#ifdef CONFIG_FSL_QIXIS
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
+#endif
+	puts("SERDES1 Reference : ");
+	printf("Clock1 = 156.25MHz ");
+	printf("Clock2 = 156.25MHz");
+#endif
+
+	puts("\nSERDES2 Reference : ");
+	printf("Clock1 = 100MHz ");
+	printf("Clock2 = 100MHz\n");
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+#ifdef CONFIG_FSL_QIXIS
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+#endif
+	return 100000000;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
+
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+	return select_i2c_ch_pca9547(channel);
+}
+
+int config_board_mux(int ctrl_type)
+{
+#ifdef CONFIG_FSL_QIXIS
+	u8 reg5;
+
+	reg5 = QIXIS_READ(brdcfg[5]);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_SDHC:
+		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
+		break;
+	case MUX_TYPE_DSPI:
+		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
+		break;
+	default:
+		printf("Wrong mux interface type\n");
+		return -1;
+	}
+
+	QIXIS_WRITE(brdcfg[5], reg5);
+#endif
+	return 0;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_FSL_MC_ENET
+	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
+
+	init_final_memctl_regs();
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+#ifdef CONFIG_FSL_QIXIS
+	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+	/* invert AQR405 IRQ pins polarity */
+	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+#endif
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+	pci_init();
+#endif
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
+	fsl_lsch3_early_init_f();
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	char *env_hwconfig;
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 val;
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 svr = gur_in32(&gur->svr);
+
+	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
+
+	env_hwconfig = env_get("hwconfig");
+
+	if (hwconfig_f("dspi", env_hwconfig) &&
+	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
+		config_board_mux(MUX_TYPE_DSPI);
+	else
+		config_board_mux(MUX_TYPE_SDHC);
+
+	/*
+	 * LS2081ARDB RevF board has smart voltage translator
+	 * which needs to be programmed to enable high speed SD interface
+	 * by setting GPIO4_10 output to zero
+	 */
+#ifdef CONFIG_TARGET_LS2081ARDB
+		out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
+					    in_le32(GPIO4_GPDIR_ADDR)));
+		out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
+					    in_le32(GPIO4_GPDAT_ADDR)));
+#endif
+	if (hwconfig("sdhc"))
+		config_board_mux(MUX_TYPE_SDHC);
+
+	if (adjust_vdd(0))
+		printf("Warning: Adjusting core voltage failed.\n");
+	/*
+	 * Default value of board env is based on filename which is
+	 * ls2080ardb. Modify board env for other supported SoCs
+	 */
+	if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
+	    (SVR_SOC_VER(svr) == SVR_LS2048A))
+		env_set("board", "ls2088ardb");
+	else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
+	    (SVR_SOC_VER(svr) == SVR_LS2041A))
+		env_set("board", "ls2081ardb");
+
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
+		puts("\nDP-DDR ");
+		print_size(gd->bd->bi_dram[2].size, "");
+		print_ddr_info(CONFIG_DP_DDR_CTRL);
+	}
+#endif
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *fdt)
+{
+	int offset;
+
+	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/fsl-mc");
+
+	if (offset < 0) {
+		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
+		       __func__, offset);
+		return;
+	}
+
+	if (get_mc_boot_status() == 0 &&
+	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
+		fdt_status_okay(fdt, offset);
+	else
+		fdt_status_fail(fdt, offset);
+}
+
+void board_quiesce_devices(void)
+{
+	fsl_mc_ldpaa_exit(gd->bd);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void fsl_fdt_fixup_flash(void *fdt)
+{
+	int offset;
+#ifdef CONFIG_TFABOOT
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 val;
+#endif
+
+/*
+ * IFC and QSPI are muxed on board.
+ * So disable IFC node in dts if QSPI is enabled or
+ * disable QSPI node in dts in case QSPI is not enabled.
+ */
+#ifdef CONFIG_TFABOOT
+	enum boot_src src = get_boot_src();
+	bool disable_ifc = false;
+
+	switch (src) {
+	case BOOT_SOURCE_IFC_NOR:
+		disable_ifc = false;
+		break;
+	case BOOT_SOURCE_QSPI_NOR:
+		disable_ifc = true;
+		break;
+	default:
+		val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+		if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+			disable_ifc = true;
+		break;
+	}
+
+	if (disable_ifc) {
+		offset = fdt_path_offset(fdt, "/soc/ifc");
+
+		if (offset < 0)
+			offset = fdt_path_offset(fdt, "/ifc");
+	} else {
+		offset = fdt_path_offset(fdt, "/soc/quadspi");
+
+		if (offset < 0)
+			offset = fdt_path_offset(fdt, "/quadspi");
+	}
+
+#else
+#ifdef CONFIG_FSL_QSPI
+	offset = fdt_path_offset(fdt, "/soc/ifc");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/ifc");
+#else
+	offset = fdt_path_offset(fdt, "/soc/quadspi");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/quadspi");
+#endif
+#endif
+
+	if (offset < 0)
+		return;
+
+	fdt_status_disabled(fdt, offset);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int i;
+	u16 mc_memory_bank = 0;
+
+	u64 *base;
+	u64 *size;
+	u64 mc_memory_base = 0;
+	u64 mc_memory_size = 0;
+	u16 total_memory_banks;
+
+	ft_cpu_setup(blob, bd);
+
+	fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+	if (mc_memory_base != 0)
+		mc_memory_bank++;
+
+	total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+	base = calloc(total_memory_banks, sizeof(u64));
+	size = calloc(total_memory_banks, sizeof(u64));
+
+	/* fixup DT for the two GPP DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+#ifdef CONFIG_RESV_RAM
+	/* reduce size if reserved memory is within this bank */
+	if (gd->arch.resv_ram >= base[0] &&
+	    gd->arch.resv_ram < base[0] + size[0])
+		size[0] = gd->arch.resv_ram - base[0];
+	else if (gd->arch.resv_ram >= base[1] &&
+		 gd->arch.resv_ram < base[1] + size[1])
+		size[1] = gd->arch.resv_ram - base[1];
+#endif
+
+	if (mc_memory_base != 0) {
+		for (i = 0; i <= total_memory_banks; i++) {
+			if (base[i] == 0 && size[i] == 0) {
+				base[i] = mc_memory_base;
+				size[i] = mc_memory_size;
+				break;
+			}
+		}
+	}
+
+	fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
+
+	fdt_fsl_mc_fixup_iommu_map_entry(blob);
+
+	fsl_fdt_fixup_dr_usb(blob, bd);
+
+	fsl_fdt_fixup_flash(blob);
+
+#ifdef CONFIG_FSL_MC_ENET
+	fdt_fixup_board_enet(blob);
+#endif
+
+	fdt_fixup_icid(blob);
+
+	return 0;
+}
+#endif
+
+void qixis_dump_switch(void)
+{
+#ifdef CONFIG_FSL_QIXIS
+	int i, nr_of_cfgsw;
+
+	QIXIS_WRITE(cms[0], 0x00);
+	nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+	puts("DIP switch settings dump:\n");
+	for (i = 1; i <= nr_of_cfgsw; i++) {
+		QIXIS_WRITE(cms[0], i);
+		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+	}
+#endif
+}
+
+/*
+ * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
+ * Both slots has 0x54, resulting 2nd slot unusable.
+ */
+void update_spd_address(unsigned int ctrl_num,
+			unsigned int slot,
+			unsigned int *addr)
+{
+#ifndef CONFIG_TARGET_LS2081ARDB
+#ifdef CONFIG_FSL_QIXIS
+	u8 sw;
+
+	sw = QIXIS_READ(arch);
+	if ((sw & 0xf) < 0x3) {
+		if (ctrl_num == 1 && slot == 0)
+			*addr = SPD_EEPROM_ADDRESS4;
+		else if (ctrl_num == 1 && slot == 1)
+			*addr = SPD_EEPROM_ADDRESS3;
+	}
+#endif
+#endif
+}
diff --git a/roms/u-boot/board/freescale/ls2080ardb/ls2080ardb_qixis.h b/roms/u-boot/board/freescale/ls2080ardb/ls2080ardb_qixis.h
new file mode 100644
index 000000000..db3c6dc2a
--- /dev/null
+++ b/roms/u-boot/board/freescale/ls2080ardb/ls2080ardb_qixis.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __LS2_RDB_QIXIS_H__
+#define __LS2_RDB_QIXIS_H__
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+
+#endif /*__LS2_RDB_QIXIS_H__*/
diff --git a/roms/u-boot/board/freescale/lx2160a/Kconfig b/roms/u-boot/board/freescale/lx2160a/Kconfig
new file mode 100644
index 000000000..7556f7dd2
--- /dev/null
+++ b/roms/u-boot/board/freescale/lx2160a/Kconfig
@@ -0,0 +1,50 @@
+if TARGET_LX2160ARDB
+
+config SYS_BOARD
+	default "lx2160a"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "lx2160ardb"
+
+source "board/freescale/common/Kconfig"
+endif
+
+if TARGET_LX2160AQDS
+
+config SYS_BOARD
+	default "lx2160a"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "lx2160aqds"
+
+source "board/freescale/common/Kconfig"
+endif
+
+if TARGET_LX2162AQDS
+
+config SYS_BOARD
+	default "lx2160a"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "lx2162aqds"
+
+source "board/freescale/common/Kconfig"
+endif
diff --git a/roms/u-boot/board/freescale/lx2160a/MAINTAINERS b/roms/u-boot/board/freescale/lx2160a/MAINTAINERS
new file mode 100644
index 000000000..cc69de297
--- /dev/null
+++ b/roms/u-boot/board/freescale/lx2160a/MAINTAINERS
@@ -0,0 +1,52 @@
+LX2160ARDB BOARD
+M:	Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	board/freescale/lx2160a/
+F:	include/configs/lx2160a_common.h
+F:	include/configs/lx2160ardb.h
+F:	configs/lx2160ardb_tfa_defconfig
+F:	configs/lx2160ardb_tfa_stmm_defconfig
+F:	arch/arm/dts/fsl-lx2160a-rdb.dts
+
+LX2160ARDB_SECURE_BOOT BOARD
+M:	Udit Agarwal <udit.agarwal@nxp.com>
+S:	Maintained
+F:	configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+
+LX2160AQDS BOARD
+M:	Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
+S:	Maintained
+F:	board/freescale/lx2160a/eth_lx2160aqds.h
+F:	include/configs/lx2160aqds.h
+F:	configs/lx2160aqds_tfa_defconfig
+F:	arch/arm/dts/fsl-lx2160a-qds.dts
+
+LX2160AQDS_SECURE_BOOT BOARD
+M:	Udit Agarwal <udit.agarwal@nxp.com>
+S:	Maintained
+F:	configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+
+LX2162AQDS BOARD
+M:	Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
+S:	Maintained
+F:	board/freescale/lx2160a/eth_lx2162aqds.h
+F:	include/configs/lx2162aqds.h
+F:	configs/lx2162aqds_tfa_defconfig
+F:	arch/arm/dts/fsl-lx2162a-qds.dts
+F:	arch/arm/dts/fsl-lx2162a-qds-17-x.dts
+F:	arch/arm/dts/fsl-lx2162a-qds-18-x.dts
+F:	arch/arm/dts/fsl-lx2162a-qds-20-x.dts
+F:	arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
+F:	arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
+F:	arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
+
+LX2162AQDS_SECURE_BOOT BOARD
+M:	Manish Tomar <Manish.Tomar@nxp.com>
+S:	Maintained
+F:	configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
+
+LX2162AQDS_VERIFIED_BOOT BOARD
+M:	Manish Tomar <Manish.Tomar@nxp.com>
+S:	Maintained
+F:	configs/lx2162aqds_tfa_verified_boot_defconfig
diff --git a/roms/u-boot/board/freescale/lx2160a/Makefile b/roms/u-boot/board/freescale/lx2160a/Makefile
new file mode 100644
index 000000000..c9561bfad
--- /dev/null
+++ b/roms/u-boot/board/freescale/lx2160a/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2018 Freescale Semiconductor
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += lx2160a.o
+obj-y += ddr.o
+obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o
+obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o
+obj-$(CONFIG_TARGET_LX2162AQDS) += eth_lx2162aqds.o
diff --git a/roms/u-boot/board/freescale/lx2160a/README b/roms/u-boot/board/freescale/lx2160a/README
new file mode 100644
index 000000000..7bca98dd3
--- /dev/null
+++ b/roms/u-boot/board/freescale/lx2160a/README
@@ -0,0 +1,329 @@
+Overview
+--------
+The LX2160A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LX2160A
+Layerscape Architecture processor and its personalities.
+
+LX2160A SoC Overview
+--------------------------------------
+For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+
+LX2160ARDB board Overview
+----------------------
+DDR Memory
+	Two ports of 72-bits (8-bits ECC) DDR4.
+	Each port supports four chip-selects and two DIMM
+	connectors. Data rate upto 3.2 GT/s.
+
+SERDES ports
+	Thress serdes controllers (24 lanes)
+	Serdes1: Supports two USXGMII connectors, each connected through
+	Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi
+	IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi
+	CS4223 phy.
+
+	Serdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0
+	connectors
+
+	Serdes3: Supports one PCIe x8 (Gen1/2/3/4) connector
+
+eSDHC
+	eSDHC1: Supports a SD connector for connecting SD cards
+	eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC
+
+Octal SPI (XSPI)
+	Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator
+	for off-board emulation
+
+I2C	All system devices on I2C1 multiplexed using PCA9547 multiplexer
+	Serial Ports
+
+USB 3.0
+	Two high speed USB 3.0 ports. First USB 3.0 port configured as
+	Host with Type-A connector, second USB 3.0 port configured as OTG
+	with micro-AB connector
+
+Serial Ports	Two UART ports
+Ethernet	Two RGMII interfaces
+Debug		ARM JTAG support
+
+Booting Options
+---------------
+a) Flexspi boot
+b) SD boot
+
+Memory map for Flexspi flash
+----------------------------
+Image							Flash Offset
+bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl)			0x00000000
+fip.bin (bl31 + bl33(u-boot) +
+	 header for Secure-boot(secure-boot only))	0x00100000
+Boot firmware Environment				0x00500000
+DDR PHY Firmware (fip_ddr_all.bin)			0x00800000
+DPAA2 MC Firmware					0x00A00000
+DPAA2 DPL						0x00D00000
+DPAA2 DPC						0x00E00000
+Kernel.itb						0x01000000
+
+Memory map for sd card
+----------------------------
+Image							SD card Offset
+bl2_sd.pbl (RCW+PBI+bl2.pbl)				0x00008
+fip.bin (bl31 + bl33(u-boot) +
+	 header for Secure-boot(secure-boot only))	0x00800
+Boot firmware Environment				0x02800
+DDR PHY Firmware (fip_ddr_all.bin)			0x04000
+DPAA2 MC Firmware					0x05000
+DPAA2 DPL						0x06800
+DPAA2 DPC						0x07000
+Kernel.itb						0x08000
+
+LX2160AQDS board Overview
+----------------------
+Various Mezzanine cards and their connection for different SERDES protocols is
+as below:
+
+SERDES1	|CARDS
+-----------------------------------------------------------------------
+1	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
+	|Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+3	|Mezzanine:X-M11-USXGMII (29828)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
+	|Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+7	|Mezzanine:X-M11-USXGMII (29828)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
+	|Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+8	|Mezzanine:X-M12-XFI (29829)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+	|Mezzanine:X-M12-XFI (29829)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
+	|Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+13	|Mezzanine:X-M8-100G (29734)
+	|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+	|Mezzanine:X-M8-100G (29734)
+	|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT2(J111)
+	|Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+15	|Mezzanine:X-M8-100G (29734)
+	|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
+	|Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+17	|Mezzanine:X-M13-25G  (32133)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
+	|Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+19	|Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125)
+	|Mezzanine:X-M7-40G (29738)
+	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111)
+	|Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+20	|Mezzanine:X-M7-40G (29738)
+	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
+	|Connect  I/O cable to IO_SLOT1(J108)
+	|Mezzanine:X-M7-40G (29738)
+	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111)
+	|Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+
+
+SERDES2	|CARDS
+-----------------------------------------------------------------------
+2	|Mezzanine:X-M6-PCIE-X8 (29737) *
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117)
+	|Connect I/O cable to IO_SLOT3(J116)
+------------------------------------------------------------------------
+3	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+	|Connect I/O cable to IO_SLOT3(J116)
+	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
+	|Connect I/O cable to IO_SLOT4(J119)
+------------------------------------------------------------------------
+5	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+	|Connect I/O cable to IO_SLOT3(J116)
+	|Mezzanine:X-M5-SATA (29687)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
+	|Connect I/O cable to IO_SLOT4(J119)
+------------------------------------------------------------------------
+11	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+	|Connect I/O cable to IO_SLOT7(J127)
+	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
+	|Connect I/O cable to IO_SLOT8(J131)
+------------------------------------------------------------------------
+
+
+SERDES3	|CARDS
+-----------------------------------------------------------------------
+2	|Mezzanine:X-M6-PCIE-X8 (29737) *
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120)
+	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT6 (J123)
+	|Connect I/O cable to IO_SLOT5(J122)
+-------------------------------------------------------------------------
+3	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120)
+	|Connect I/O cable to IO_SLOT5(J122)
+	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT6 (J123)
+	|Connect I/O cable to IO_SLOT6(J125)
+-------------------------------------------------------------------------
+
+LX2162A SoC Overview
+--------------------------------------
+For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+
+LX2162AQDS board Overview
+----------------------
+DDR Memory
+	One ports of 72-bits (8-bits ECC) DDR4.
+	Each port supports four chip-selects and two DIMM
+	connectors. Data rate upto 2.9 GT/s.
+
+SERDES ports
+	Two serdes controllers (12 lanes)
+	Serdes1: Supports two USXGMII connectors, each connected through
+	Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi
+	IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi
+	CS4223 phy.
+
+	Serdes2: Supports two PCIe x4 (Gen3) and one PCIe x8 (Gen3) connector,
+	four SATA 3.0 connectors
+
+eSDHC
+	eSDHC1: Supports a SD connector for connecting SD cards
+	eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC
+
+Octal SPI (XSPI)
+	Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator
+	for off-board emulation
+
+I2C	All system devices on I2C1 multiplexed using PCA9547 multiplexer
+	Serial Ports
+
+USB 3.0
+	One high speed USB 3.0 ports. First USB 3.0 port configured as Host
+	with Type-A connector, second USB 3.0 port configured as OTG with
+	micro-AB connector
+
+Serial Ports	Two UART ports
+Ethernet	Two RGMII interfaces
+Debug		ARM JTAG support
+
+Booting Options
+---------------
+a) Flexspi boot
+b) SD boot
+c) eMMC boot
+
+Memory map for Flexspi flash
+----------------------------
+Image							Flash Offset
+bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl)			0x00000000
+fip.bin (bl31 + bl33(u-boot) +
+	 header for Secure-boot(secure-boot only))	0x00100000
+Boot firmware Environment				0x00500000
+DDR PHY Firmware (fip_ddr_all.bin)			0x00800000
+DPAA2 MC Firmware					0x00A00000
+DPAA2 DPL						0x00D00000
+DPAA2 DPC						0x00E00000
+Kernel.itb						0x01000000
+
+Memory map for sd/eMMC card
+----------------------------
+Image							SD/eMMC card Offset
+bl2_sd.pbl (RCW+PBI+bl2.pbl)				0x00008
+fip.bin (bl31 + bl33(u-boot) +
+	 header for Secure-boot(secure-boot only))	0x00800
+Boot firmware Environment				0x02800
+DDR PHY Firmware (fip_ddr_all.bin)			0x04000
+DPAA2 MC Firmware					0x05000
+DPAA2 DPL						0x06800
+DPAA2 DPC						0x07000
+Kernel.itb						0x08000
+
+Various Mezzanine cards and their connection for different SERDES protocols is
+as below:
+
+SERDES1	|CARDS
+-----------------------------------------------------------------------
+1	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+------------------------------------------------------------------------
+3	|Mezzanine:X-M11-USXGMII (29828)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+------------------------------------------------------------------------
+15	|Mezzanine:X-M8-50G (29734)
+	|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+------------------------------------------------------------------------
+17	|Mezzanine:X-M13-25G  (32133)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+------------------------------------------------------------------------
+18	|Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125)
+------------------------------------------------------------------------
+20	|Mezzanine:X-M7-40G (29738)
+	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
+	|Connect  I/O cable to IO_SLOT1(J108)
+------------------------------------------------------------------------
+
+
+SERDES2	|CARDS
+-----------------------------------------------------------------------
+2	|Mezzanine:X-M6-PCIE-X8 (29737) *
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117)
+	|Connect I/O cable to IO_SLOT3(J116)
+------------------------------------------------------------------------
+3	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+	|Connect I/O cable to IO_SLOT3(J116)
+	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
+	|Connect I/O cable to IO_SLOT4(J119)
+------------------------------------------------------------------------
+5	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+	|Connect I/O cable to IO_SLOT3(J116)
+	|Mezzanine:X-M5-SATA (29687)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
+	|Connect I/O cable to IO_SLOT4(J119)
+------------------------------------------------------------------------
+11	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+	|Connect I/O cable to IO_SLOT7(J127)
+	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
+	|Connect I/O cable to IO_SLOT8(J131)
+------------------------------------------------------------------------
diff --git a/roms/u-boot/board/freescale/lx2160a/ddr.c b/roms/u-boot/board/freescale/lx2160a/ddr.c
new file mode 100644
index 000000000..7ab7a9e6c
--- /dev/null
+++ b/roms/u-boot/board/freescale/lx2160a/ddr.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/lx2160a/eth_lx2160aqds.c b/roms/u-boot/board/freescale/lx2160a/eth_lx2160aqds.c
new file mode 100644
index 000000000..437f0bc4c
--- /dev/null
+++ b/roms/u-boot/board/freescale/lx2160a/eth_lx2160aqds.c
@@ -0,0 +1,963 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2020 NXP
+ *
+ */
+
+#include <common.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <hwconfig.h>
+#include <command.h>
+#include <log.h>
+#include <net.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include <linux/libfdt.h>
+
+#include "../common/qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_DM_ETH
+#define EMI_NONE	0
+#define EMI1		1 /* Mdio Bus 1 */
+#define EMI2		2 /* Mdio Bus 2 */
+
+#if defined(CONFIG_FSL_MC_ENET)
+enum io_slot {
+	IO_SLOT_NONE = 0,
+	IO_SLOT_1,
+	IO_SLOT_2,
+	IO_SLOT_3,
+	IO_SLOT_4,
+	IO_SLOT_5,
+	IO_SLOT_6,
+	IO_SLOT_7,
+	IO_SLOT_8,
+	EMI1_RGMII1,
+	EMI1_RGMII2,
+	IO_SLOT_MAX
+};
+
+struct lx2160a_qds_mdio {
+	enum io_slot ioslot : 4;
+	u8 realbusnum : 4;
+	struct mii_dev *realbus;
+};
+
+/* structure explaining the phy configuration on 8 lanes of a serdes*/
+struct serdes_phy_config {
+	u8 serdes; /* serdes protocol */
+	struct phy_config {
+		u8 dpmacid;
+		/* -1 terminated array */
+		int phy_address[WRIOP_MAX_PHY_NUM + 1];
+		u8 mdio_bus;
+		enum io_slot ioslot;
+	} phy_config[SRDS_MAX_LANES];
+};
+
+/* Table defining the phy configuration on 8 lanes of a serdes.
+ * Various assumptions have been made while defining this table.
+ * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
+ * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
+ * And also that this card is connected to IO Slot 1 (could have been connected
+ * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
+ * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
+ * used in serdes1 protocol 19 (could have selected MDIO 2)
+ * To override these settings "dpmac" environment variable can be used after
+ * defining "dpmac_override" in hwconfig environment variable.
+ * This table has limited serdes protocol entries. It can be expanded as per
+ * requirement.
+ */
+static const struct serdes_phy_config serdes1_phy_config[] = {
+	{3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
+	      EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
+	     EMI1, IO_SLOT_1} } },
+	{7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
+	      EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
+	     EMI1, IO_SLOT_2},
+	    {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	     EMI1, IO_SLOT_2},
+	    {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	     EMI1, IO_SLOT_2},
+	    {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	     EMI1, IO_SLOT_2} } },
+	{8, {} },
+	{13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	       EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_2} } },
+	{14, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	       EMI1, IO_SLOT_1} } },
+	{15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	       EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1} } },
+	{17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	       EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1} } },
+	{19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
+	       EMI1, IO_SLOT_2},
+	     {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
+	      EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_6},
+	     {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_6} } },
+	{20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
+	       EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
+	      EMI1, IO_SLOT_2} } }
+};
+
+static const struct serdes_phy_config serdes2_phy_config[] = {
+	{2, {} },
+	{3, {} },
+	{5, {} },
+	{11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	       EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_8},
+	     {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_8},
+	     {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_8} } },
+};
+
+static const struct serdes_phy_config serdes3_phy_config[] = {
+	{2, {} },
+	{3, {} }
+};
+
+static inline
+const struct phy_config *get_phy_config(u8 serdes,
+					const struct serdes_phy_config *table,
+					u8 table_size)
+{
+	int i;
+
+	for (i = 0; i < table_size; i++) {
+		if (table[i].serdes == serdes)
+			return table[i].phy_config;
+	}
+
+	return NULL;
+}
+
+/* BRDCFG4 controls EMI routing for the board.
+ * Bits    Function
+ * 7-6     EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
+ * EMI1    00= On-board PHY #1
+ *         01= On-board PHY #2
+ *         10= (reserved)
+ *         11= Slots 1..8 multiplexer and translator.
+ * 5-3     EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
+ * EMI1X   000= Slot #1
+ *         001= Slot #2
+ *         010= Slot #3
+ *         011= Slot #4
+ *         100= Slot #5
+ *         101= Slot #6
+ *         110= Slot #7
+ *         111= Slot #8
+ * 2-0     EMI Interface #2 Routing (CFG_MUX_EMI2):
+ * EMI2    000= Slot #1 (secondary EMI)
+ *         001= Slot #2 (secondary EMI)
+ *         010= Slot #3 (secondary EMI)
+ *         011= Slot #4 (secondary EMI)
+ *         100= Slot #5 (secondary EMI)
+ *         101= Slot #6 (secondary EMI)
+ *         110= Slot #7 (secondary EMI)
+ *         111= Slot #8 (secondary EMI)
+ */
+static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
+{
+	switch (realbusnum) {
+	case EMI1:
+		switch (ioslot) {
+		case EMI1_RGMII1:
+			return 0;
+		case EMI1_RGMII2:
+			return 0x40;
+		default:
+			return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
+		}
+		break;
+	case EMI2:
+		return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
+	default:
+		return -1;
+	}
+}
+
+static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
+{
+	u8 brdcfg4, mux_val, reg;
+
+	brdcfg4 = QIXIS_READ(brdcfg[4]);
+	reg = brdcfg4;
+	mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
+
+	switch (priv->realbusnum) {
+	case EMI1:
+		brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
+		brdcfg4 |= mux_val;
+		break;
+	case EMI2:
+		brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
+		brdcfg4 |= mux_val;
+		break;
+	}
+
+	if (brdcfg4 ^ reg)
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+}
+
+static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
+				 int devad, int regnum)
+{
+	struct lx2160a_qds_mdio *priv = bus->priv;
+
+	lx2160a_qds_mux_mdio(priv);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				  int regnum, u16 value)
+{
+	struct lx2160a_qds_mdio *priv = bus->priv;
+
+	lx2160a_qds_mux_mdio(priv);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
+{
+	struct lx2160a_qds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
+{
+	struct lx2160a_qds_mdio *pmdio;
+	struct mii_dev *bus;
+	/*should be within MDIO_NAME_LEN*/
+	char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
+
+	if (realbusnum == EMI2) {
+		if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
+			printf("invalid ioslot %d\n", ioslot);
+			return NULL;
+		}
+	} else if (realbusnum == EMI1) {
+		if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
+			printf("invalid ioslot %d\n", ioslot);
+			return NULL;
+		}
+	} else {
+		printf("not supported real mdio bus %d\n", realbusnum);
+		return NULL;
+	}
+
+	if (ioslot == EMI1_RGMII1)
+		strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
+	else if (ioslot == EMI1_RGMII2)
+		strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
+	else
+		sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
+			realbusnum, ioslot);
+	bus = miiphy_get_dev_by_name(dummy_mdio_name);
+
+	if (bus)
+		return bus;
+
+	bus = mdio_alloc();
+	if (!bus) {
+		printf("Failed to allocate %s bus\n", dummy_mdio_name);
+		return NULL;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate %s private data\n", dummy_mdio_name);
+		free(bus);
+		return NULL;
+	}
+
+	switch (realbusnum) {
+	case EMI1:
+		pmdio->realbus =
+		  miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+		break;
+	case EMI2:
+		pmdio->realbus =
+		  miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+		break;
+	}
+
+	if (!pmdio->realbus) {
+		printf("No real mdio bus num %d found\n", realbusnum);
+		free(bus);
+		free(pmdio);
+		return NULL;
+	}
+
+	pmdio->realbusnum = realbusnum;
+	pmdio->ioslot = ioslot;
+	bus->read = lx2160a_qds_mdio_read;
+	bus->write = lx2160a_qds_mdio_write;
+	bus->reset = lx2160a_qds_mdio_reset;
+	strcpy(bus->name, dummy_mdio_name);
+	bus->priv = pmdio;
+
+	if (!mdio_register(bus))
+		return bus;
+
+	printf("No bus with name %s\n", dummy_mdio_name);
+	free(bus);
+	free(pmdio);
+	return NULL;
+}
+
+static inline void do_phy_config(const struct phy_config *phy_config)
+{
+	struct mii_dev *bus;
+	int i, phy_num, phy_address;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (!phy_config[i].dpmacid)
+			continue;
+
+		for (phy_num = 0;
+		     phy_num < ARRAY_SIZE(phy_config[i].phy_address);
+		     phy_num++) {
+			phy_address = phy_config[i].phy_address[phy_num];
+			if (phy_address == -1)
+				break;
+			wriop_set_phy_address(phy_config[i].dpmacid,
+					      phy_num, phy_address);
+		}
+		/*Register the muxing front-ends to the MDIO buses*/
+		bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
+					    phy_config[i].ioslot);
+		if (!bus)
+			printf("could not get bus for mdio %d ioslot %d\n",
+			       phy_config[i].mdio_bus,
+			       phy_config[i].ioslot);
+		else
+			wriop_set_mdio(phy_config[i].dpmacid, bus);
+	}
+}
+
+static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
+				   char *env_dpmac)
+{
+	const char *ret;
+	size_t len;
+	u8 realbusnum, ioslot;
+	struct mii_dev *bus;
+	int phy_num;
+	char *phystr = "phy00";
+
+	/*search phy in dpmac arg*/
+	for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+		sprintf(phystr, "phy%d", phy_num + 1);
+		ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
+		if (!ret) {
+			/*look for phy instead of phy1*/
+			if (!phy_num)
+				ret = hwconfig_subarg_f(arg_dpmacid, "phy",
+							&len, env_dpmac);
+			if (!ret)
+				continue;
+		}
+
+		if (len != 4 || strncmp(ret, "0x", 2))
+			printf("invalid phy format in %s variable.\n"
+			       "specify phy%d for %s in hex format e.g. 0x12\n",
+			       env_dpmac, phy_num + 1, arg_dpmacid);
+		else
+			wriop_set_phy_address(dpmac, phy_num,
+					      simple_strtoul(ret, NULL, 16));
+	}
+
+	/*search mdio in dpmac arg*/
+	ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
+	if (ret)
+		realbusnum = *ret - '0';
+	else
+		realbusnum = EMI_NONE;
+
+	if (realbusnum) {
+		/*search io in dpmac arg*/
+		ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
+		if (ret)
+			ioslot = *ret - '0';
+		else
+			ioslot = IO_SLOT_NONE;
+		/*Register the muxing front-ends to the MDIO buses*/
+		bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
+		if (!bus)
+			printf("could not get bus for mdio %d ioslot %d\n",
+			       realbusnum, ioslot);
+		else
+			wriop_set_mdio(dpmac, bus);
+	}
+}
+
+#endif
+#endif /* !CONFIG_DM_ETH */
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifndef CONFIG_DM_ETH
+#if defined(CONFIG_FSL_MC_ENET)
+	struct memac_mdio_info mdio_info;
+	struct memac_mdio_controller *regs;
+	int i;
+	const char *ret;
+	char *env_dpmac;
+	char dpmacid[] = "dpmac00", srds[] = "00_00_00";
+	size_t len;
+	struct mii_dev *bus;
+	const struct phy_config *phy_config;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 srds_s1, srds_s2, srds_s3;
+
+	srds_s1 = in_le32(&gur->rcwsr[28]) &
+		  FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	srds_s2 = in_le32(&gur->rcwsr[28]) &
+		  FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+	srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+	srds_s3 = in_le32(&gur->rcwsr[28]) &
+		  FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
+	srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
+
+	sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
+
+	regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	mdio_info.regs = regs;
+	mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+	/*Register the EMI 1*/
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+	mdio_info.regs = regs;
+	mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+	/*Register the EMI 2*/
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	/* "dpmac" environment variable can be used after
+	 * defining "dpmac_override" in hwconfig environment variable.
+	 */
+	if (hwconfig("dpmac_override")) {
+		env_dpmac = env_get("dpmac");
+		if (env_dpmac) {
+			ret = hwconfig_arg_f("srds", &len, env_dpmac);
+			if (ret) {
+				if (strncmp(ret, srds, strlen(srds))) {
+					printf("SERDES configuration changed.\n"
+					       "previous: %.*s, current: %s.\n"
+					       "update dpmac variable.\n",
+					       (int)len, ret, srds);
+				}
+			} else {
+				printf("SERDES configuration not found.\n"
+				       "Please add srds:%s in dpmac variable\n",
+				       srds);
+			}
+
+			for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+				/* Look for dpmac1 to dpmac24(current max) arg
+				 * in dpmac environment variable
+				 */
+				sprintf(dpmacid, "dpmac%d", i);
+				ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
+				if (ret)
+					do_dpmac_config(i, dpmacid, env_dpmac);
+			}
+		} else {
+			printf("Warning: environment dpmac not found.\n"
+			       "DPAA network interfaces may not work\n");
+		}
+	} else {
+		/*Look for phy config for serdes1 in phy config table*/
+		phy_config = get_phy_config(srds_s1, serdes1_phy_config,
+					    ARRAY_SIZE(serdes1_phy_config));
+		if (!phy_config) {
+			printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
+			       __func__, srds_s1);
+		} else {
+			do_phy_config(phy_config);
+		}
+		phy_config = get_phy_config(srds_s2, serdes2_phy_config,
+					    ARRAY_SIZE(serdes2_phy_config));
+		if (!phy_config) {
+			printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
+			       __func__, srds_s2);
+		} else {
+			do_phy_config(phy_config);
+		}
+		phy_config = get_phy_config(srds_s3, serdes3_phy_config,
+					    ARRAY_SIZE(serdes3_phy_config));
+		if (!phy_config) {
+			printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
+			       __func__, srds_s3);
+		} else {
+			do_phy_config(phy_config);
+		}
+	}
+
+	if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
+		wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
+		bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
+		if (!bus)
+			printf("could not get bus for RGMII1\n");
+		else
+			wriop_set_mdio(WRIOP1_DPMAC17, bus);
+	}
+
+	if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
+		wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
+		bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
+		if (!bus)
+			printf("could not get bus for RGMII2\n");
+		else
+			wriop_set_mdio(WRIOP1_DPMAC18, bus);
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+#endif /* !CONFIG_DM_ETH */
+
+#ifdef CONFIG_PHY_AQUANTIA
+	/*
+	 * Export functions to be used by AQ firmware
+	 * upload application
+	 */
+	gd->jt->strcpy = strcpy;
+	gd->jt->mdelay = mdelay;
+	gd->jt->mdio_get_current_dev = mdio_get_current_dev;
+	gd->jt->phy_find_by_mask = phy_find_by_mask;
+	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
+	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
+#endif
+
+#ifdef CONFIG_DM_ETH
+	return 0;
+#else
+	return pci_eth_init(bis);
+#endif
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+	mc_env_boot();
+#endif
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#ifndef CONFIG_DM_ETH
+#if defined(CONFIG_FSL_MC_ENET)
+int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
+{
+	int offset;
+	int ret;
+	char dpmac_str[] = "dpmacs@00";
+	const char *phy_string;
+
+	offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
+
+	if (offset < 0) {
+		printf("dpmacs node not found in device tree\n");
+		return offset;
+	}
+
+	sprintf(dpmac_str, "dpmac@%x", dpmac_id);
+	debug("dpmac_str = %s\n", dpmac_str);
+
+	offset = fdt_subnode_offset(fdt, offset, dpmac_str);
+	if (offset < 0) {
+		printf("%s node not found in device tree\n", dpmac_str);
+		return offset;
+	}
+
+	phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
+	if (is_backplane_mode(phy_string)) {
+		/* Backplane KR mode: skip fixups */
+		printf("Interface %d in backplane KR mode\n", dpmac_id);
+		return 0;
+	}
+
+	ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
+	if (ret)
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+
+	phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
+	ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
+				 phy_string);
+	if (ret)
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+
+	return ret;
+}
+
+int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
+{
+	char mdio_ioslot_str[] = "mdio@00";
+	struct lx2160a_qds_mdio *priv;
+	u64 reg;
+	u32 phandle;
+	int offset, mux_val;
+
+	/*Test if the MDIO bus is real mdio bus or muxing front end ?*/
+	if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
+		    strlen("LX2160A_QDS_MDIO")))
+		return -1;
+
+	/*Get the real MDIO bus num and ioslot info from bus's priv data*/
+	priv = mii_dev->priv;
+
+	debug("real_bus_num = %d, ioslot = %d\n",
+	      priv->realbusnum, priv->ioslot);
+
+	if (priv->realbusnum == EMI1)
+		reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	else
+		reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
+
+	offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
+	if (offset < 0) {
+		printf("mdio@%llx node not found in device tree\n", reg);
+		return offset;
+	}
+
+	phandle = fdt_get_phandle(fdt, offset);
+	phandle = cpu_to_fdt32(phandle);
+	offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
+					       &phandle, 4);
+	if (offset < 0) {
+		printf("mdio-mux-%d node not found in device tree\n",
+		       priv->realbusnum == EMI1 ? 1 : 2);
+		return offset;
+	}
+
+	mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
+	if (priv->realbusnum == EMI1)
+		mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
+	else
+		mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
+	sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
+
+	offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
+	if (offset < 0) {
+		printf("%s node not found in device tree\n", mdio_ioslot_str);
+		return offset;
+	}
+
+	return offset;
+}
+
+int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
+			struct phy_device *phy_dev, int phandle)
+{
+	char phy_node_name[] = "ethernet-phy@00";
+	char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
+	int ret;
+
+	sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
+	debug("phy_node_name = %s\n", phy_node_name);
+
+	*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
+	if (*subnodeoffset <= 0) {
+		printf("Could not add subnode %s inside node %s err = %s\n",
+		       phy_node_name, fdt_get_name(fdt, offset, NULL),
+		       fdt_strerror(*subnodeoffset));
+		return *subnodeoffset;
+	}
+
+	sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
+		phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
+	debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
+
+	ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
+				 phy_id_compatible_str);
+	if (ret) {
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+		goto out;
+	}
+
+	if (phy_dev->is_c45) {
+		ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
+					    "ethernet-phy-ieee802.3-c45");
+		if (ret) {
+			printf("%d@%s %d\n", __LINE__, __func__, ret);
+			goto out;
+		}
+	} else {
+		ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
+					    "ethernet-phy-ieee802.3-c22");
+		if (ret) {
+			printf("%d@%s %d\n", __LINE__, __func__, ret);
+			goto out;
+		}
+	}
+
+	ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
+	if (ret) {
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+		goto out;
+	}
+
+	ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
+	if (ret) {
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+		goto out;
+	}
+
+out:
+	if (ret)
+		fdt_del_node(fdt, *subnodeoffset);
+
+	return ret;
+}
+
+int fdt_fixup_board_phy(void *fdt)
+{
+	int fpga_offset, offset, subnodeoffset;
+	struct mii_dev *mii_dev;
+	struct list_head *mii_devs, *entry;
+	int ret, dpmac_id, phandle, i;
+	struct phy_device *phy_dev;
+	char ethname[ETH_NAME_LEN];
+	phy_interface_t	phy_iface;
+
+	ret = 0;
+	/* we know FPGA is connected to i2c0, therefore search path directly,
+	 * instead of compatible property, as it saves time
+	 */
+	fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
+
+	if (fpga_offset < 0)
+		fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
+
+	if (fpga_offset < 0) {
+		printf("i2c@2000000/fpga node not found in device tree\n");
+		return fpga_offset;
+	}
+
+	phandle = fdt_alloc_phandle(fdt);
+	mii_devs = mdio_get_list_head();
+
+	list_for_each(entry, mii_devs) {
+		mii_dev = list_entry(entry, struct mii_dev, link);
+		debug("mii_dev name : %s\n", mii_dev->name);
+		offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
+		if (offset < 0)
+			continue;
+
+		// Look for phy devices attached to MDIO bus muxing front end
+		// and create their entries with compatible being the device id
+		for (i = 0; i < PHY_MAX_ADDR; i++) {
+			phy_dev = mii_dev->phymap[i];
+			if (!phy_dev)
+				continue;
+
+			// TODO: use sscanf instead of loop
+			dpmac_id = WRIOP1_DPMAC1;
+			while (dpmac_id < NUM_WRIOP_PORTS) {
+				phy_iface = wriop_get_enet_if(dpmac_id);
+				snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
+					 dpmac_id,
+					 phy_string_for_interface(phy_iface));
+				if (strcmp(ethname, phy_dev->dev->name) == 0)
+					break;
+				dpmac_id++;
+			}
+			if (dpmac_id == NUM_WRIOP_PORTS)
+				continue;
+			ret = fdt_create_phy_node(fdt, offset, i,
+						  &subnodeoffset,
+						  phy_dev, phandle);
+			if (ret)
+				break;
+
+			ret = fdt_fixup_dpmac_phy_handle(fdt,
+							 dpmac_id, phandle);
+			if (ret) {
+				fdt_del_node(fdt, subnodeoffset);
+				break;
+			}
+			/* calculate offset again as new node addition may have
+			 * changed offset;
+			 */
+			offset = fdt_get_ioslot_offset(fdt, mii_dev,
+						       fpga_offset);
+			phandle++;
+		}
+
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+#endif // CONFIG_FSL_MC_ENET
+#endif
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+
+/* Structure to hold SERDES protocols supported in case of
+ * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+ *
+ * @serdes_block: the index of the SERDES block
+ * @serdes_protocol: the decimal value of the protocol supported
+ * @dts_needed: DTS notes describing the current configuration are needed
+ *
+ * When dts_needed is true, the board_fit_config_name_match() function
+ * will try to exactly match the current configuration of the block with a DTS
+ * name provided.
+ */
+static struct serdes_configuration {
+	u8 serdes_block;
+	u32 serdes_protocol;
+	bool dts_needed;
+} supported_protocols[] = {
+	/* Serdes block #1 */
+	{1, 3, true},
+	{1, 7, true},
+	{1, 19, true},
+	{1, 20, true},
+
+	/* Serdes block #2 */
+	{2, 2, false},
+	{2, 3, false},
+	{2, 5, false},
+	{2, 11, true},
+
+	/* Serdes block #3 */
+	{3, 2, false},
+	{3, 3, false},
+};
+
+#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
+
+static bool protocol_supported(u8 serdes_block, u32 protocol)
+{
+	struct serdes_configuration serdes_conf;
+	int i;
+
+	for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+		serdes_conf = supported_protocols[i];
+		if (serdes_conf.serdes_block == serdes_block &&
+		    serdes_conf.serdes_protocol == protocol)
+			return true;
+	}
+
+	return false;
+}
+
+static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
+{
+	struct serdes_configuration serdes_conf;
+	int i;
+
+	for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+		serdes_conf = supported_protocols[i];
+		if (serdes_conf.serdes_block == serdes_block &&
+		    serdes_conf.serdes_protocol == protocol) {
+			if (serdes_conf.dts_needed == true)
+				sprintf(str, "%u", protocol);
+			else
+				sprintf(str, "x");
+			return;
+		}
+	}
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 rcw_status = in_le32(&gur->rcwsr[28]);
+	char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2];
+	u32 srds_s1, srds_s2, srds_s3;
+	char expected_dts[100];
+
+	srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+	srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+	srds_s3 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
+	srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
+
+	/* Check for supported protocols. The default DTS will be used
+	 * in this case
+	 */
+	if (!protocol_supported(1, srds_s1) ||
+	    !protocol_supported(2, srds_s2) ||
+	    !protocol_supported(3, srds_s3))
+		return -1;
+
+	get_str_protocol(1, srds_s1, srds_s1_str);
+	get_str_protocol(2, srds_s2, srds_s2_str);
+	get_str_protocol(3, srds_s3, srds_s3_str);
+
+	sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s-%s",
+		srds_s1_str, srds_s2_str, srds_s3_str);
+
+	if (!strcmp(name, expected_dts))
+		return 0;
+
+	return -1;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/lx2160a/eth_lx2160ardb.c b/roms/u-boot/board/freescale/lx2160a/eth_lx2160ardb.c
new file mode 100644
index 000000000..15cbc58d5
--- /dev/null
+++ b/roms/u-boot/board/freescale/lx2160a/eth_lx2160ardb.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018, 2020 NXP
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fdt_support.h>
+#include <net.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include "lx2160a.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
+{
+	int phy_reg;
+	u32 phy_id;
+
+	phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
+	phy_id = (phy_reg & 0xffff) << 16;
+
+	phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
+	phy_id |= (phy_reg & 0xffff);
+
+	if (phy_id == PHY_UID_IN112525_S03)
+		return true;
+	else
+		return false;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+	struct memac_mdio_info mdio_info;
+	struct memac_mdio_controller *reg;
+	int i, interface;
+	struct mii_dev *dev;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	mdio_info.regs = reg;
+	mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+	/* Register the EMI 1 */
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+	mdio_info.regs = reg;
+	mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+	/* Register the EMI 2 */
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+	switch (srds_s1) {
+	case 19:
+		wriop_set_phy_address(WRIOP1_DPMAC2, 0,
+				      CORTINA_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC3, 0,
+				      AQR107_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC4, 0,
+				      AQR107_PHY_ADDR2);
+		if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
+			wriop_set_phy_address(WRIOP1_DPMAC5, 0,
+					      INPHI_PHY_ADDR1);
+			wriop_set_phy_address(WRIOP1_DPMAC6, 0,
+					      INPHI_PHY_ADDR1);
+		}
+		wriop_set_phy_address(WRIOP1_DPMAC17, 0,
+				      RGMII_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC18, 0,
+				      RGMII_PHY_ADDR2);
+		break;
+
+	case 18:
+		wriop_set_phy_address(WRIOP1_DPMAC7, 0,
+				      CORTINA_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC8, 0,
+				      CORTINA_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC9, 0,
+				      CORTINA_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC10, 0,
+				      CORTINA_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC3, 0,
+				      AQR107_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC4, 0,
+				      AQR107_PHY_ADDR2);
+		if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
+			wriop_set_phy_address(WRIOP1_DPMAC5, 0,
+					      INPHI_PHY_ADDR1);
+			wriop_set_phy_address(WRIOP1_DPMAC6, 0,
+					      INPHI_PHY_ADDR1);
+		}
+		wriop_set_phy_address(WRIOP1_DPMAC17, 0,
+				      RGMII_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC18, 0,
+				      RGMII_PHY_ADDR2);
+		break;
+
+	default:
+		printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
+		       srds_s1);
+		goto next;
+	}
+
+	for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
+		interface = wriop_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_XGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+			wriop_set_mdio(i, dev);
+			break;
+		case PHY_INTERFACE_MODE_25G_AUI:
+			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+			wriop_set_mdio(i, dev);
+			break;
+		case PHY_INTERFACE_MODE_XLAUI:
+			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+			wriop_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+	for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
+		interface = wriop_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+			wriop_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+next:
+	cpu_eth_init(bis);
+#endif /* CONFIG_FSL_MC_ENET */
+
+#ifdef CONFIG_PHY_AQUANTIA
+	/*
+	 * Export functions to be used by AQ firmware
+	 * upload application
+	 */
+	gd->jt->strcpy = strcpy;
+	gd->jt->mdelay = mdelay;
+	gd->jt->mdio_get_current_dev = mdio_get_current_dev;
+	gd->jt->phy_find_by_mask = phy_find_by_mask;
+	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
+	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
+#endif
+	return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+	mc_env_boot();
+#endif
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+int fdt_fixup_board_phy(void *fdt)
+{
+	int mdio_offset;
+	int ret;
+	struct mii_dev *dev;
+
+	ret = 0;
+
+	dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+	if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
+		mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
+
+		if (mdio_offset < 0)
+			mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
+
+		if (mdio_offset < 0) {
+			printf("mdio@0x8B9700 node not found in dts\n");
+			return mdio_offset;
+		}
+
+		ret = fdt_setprop_string(fdt, mdio_offset, "status",
+					 "disabled");
+		if (ret) {
+			printf("Could not set disable mdio@0x8B97000 %s\n",
+			       fdt_strerror(ret));
+			return ret;
+		}
+	}
+
+	return ret;
+}
diff --git a/roms/u-boot/board/freescale/lx2160a/eth_lx2162aqds.c b/roms/u-boot/board/freescale/lx2160a/eth_lx2162aqds.c
new file mode 100644
index 000000000..b742c1ff5
--- /dev/null
+++ b/roms/u-boot/board/freescale/lx2160a/eth_lx2162aqds.c
@@ -0,0 +1,975 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ *
+ */
+
+#include <common.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <hwconfig.h>
+#include <command.h>
+#include <log.h>
+#include <net.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/global_data.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include <linux/libfdt.h>
+
+#include "../common/qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_DM_ETH
+#define EMI_NONE	0
+#define EMI1		1 /* Mdio Bus 1 */
+#define EMI2		2 /* Mdio Bus 2 */
+
+#if defined(CONFIG_FSL_MC_ENET)
+enum io_slot {
+	IO_SLOT_NONE = 0,
+	IO_SLOT_1,
+	IO_SLOT_2,
+	IO_SLOT_3,
+	IO_SLOT_4,
+	IO_SLOT_5,
+	IO_SLOT_6,
+	IO_SLOT_7,
+	IO_SLOT_8,
+	EMI1_RGMII1,
+	EMI1_RGMII2,
+	IO_SLOT_MAX
+};
+
+struct lx2162a_qds_mdio {
+	enum io_slot ioslot : 4;
+	u8 realbusnum : 4;
+	struct mii_dev *realbus;
+};
+
+/* structure explaining the phy configuration on 8 lanes of a serdes*/
+struct serdes_phy_config {
+	u8 serdes; /* serdes protocol */
+	struct phy_config {
+		u8 dpmacid;
+		/* -1 terminated array */
+		int phy_address[WRIOP_MAX_PHY_NUM + 1];
+		u8 mdio_bus;
+		enum io_slot ioslot;
+	} phy_config[SRDS_MAX_LANES];
+};
+
+/* Table defining the phy configuration on 8 lanes of a serdes.
+ * Various assumptions have been made while defining this table.
+ * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
+ * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
+ * And also that this card is connected to IO Slot 1 (could have been connected
+ * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
+ * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
+ * used in serdes1 protocol 19 (could have selected MDIO 2)
+ * To override these settings "dpmac" environment variable can be used after
+ * defining "dpmac_override" in hwconfig environment variable.
+ * This table has limited serdes protocol entries. It can be expanded as per
+ * requirement.
+ */
+/*****************************************************************
+ *|   SERDES_1 PROTOCOL   |      IO_SLOT         |       CARD     |
+ ******************************************************************
+ *|      2                |      IO_SLOT_1       |  M4-PCIE-SGMII |
+ *|      3                |      IO_SLOT_1       |  M11-USXGMII   |
+ *|      15               |      IO_SLOT_1       |  M13-25G       |
+ *|      17               |      IO_SLOT_1       |  M13-25G       |
+ *|      18               |      IO_SLOT_1       |  M11-USXGMII   |
+ *|                       |      IO_SLOT_6       |  M13-25G       |
+ *|      20               |      IO_SLOT_1       |  M7-40G        |
+ *****************************************************************
+ */
+static const struct serdes_phy_config serdes1_phy_config[] = {
+	{1, {} },
+	{2, {{WRIOP1_DPMAC3, {SGMII_CARD_PORT1_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC4, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC5, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC6, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	     EMI1, IO_SLOT_1} } },
+	{3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
+	      EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
+	     EMI1, IO_SLOT_1} } },
+	{15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	       EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1} } },
+	{17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	       EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1} } },
+	{18, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
+	      EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_6},
+	     {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_6} } },
+	{20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
+	       EMI1, IO_SLOT_1} } }
+};
+
+/*****************************************************************
+ *|   SERDES_2 PROTOCOL   |      IO_SLOT         |       CARD     |
+ ******************************************************************
+ *|      2                |      IO_SLOT_7       |  M4-PCIE-SGMII |
+ *|                       |      IO_SLOT_8       |  M4-PCIE-SGMII |
+ *|      3                |      IO_SLOT_7       |  M4-PCIE-SGMII |
+ *|                       |      IO_SLOT_8       |  M4-PCIE-SGMII |
+ *|      5                |      IO_SLOT_7       |  M4-PCIE-SGMII |
+ *|      10               |      IO_SLOT_7       |  M4-PCIE-SGMII |
+ *|                       |      IO_SLOT_8       |  M4-PCIE-SGMII |
+ *|      11               |      IO_SLOT_7       |  M4-PCIE-SGMII |
+ *|                       |      IO_SLOT_8       |  M4-PCIE-SGMII |
+ *|      12               |      IO_SLOT_7       |  M4-PCIE-SGMII |
+ *|                       |      IO_SLOT_8       |  M4-PCIE-SGMII |
+ ******************************************************************
+ */
+static const struct serdes_phy_config serdes2_phy_config[] = {
+	{2, {} },
+	{3, {} },
+	{5, {} },
+	{10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
+	       EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7} } },
+	{11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	       EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_8},
+	     {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_8},
+	     {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_8} } },
+	{12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
+	       EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7} } }
+};
+
+static inline
+const struct phy_config *get_phy_config(u8 serdes,
+					const struct serdes_phy_config *table,
+					u8 table_size)
+{
+	int i;
+
+	for (i = 0; i < table_size; i++) {
+		if (table[i].serdes == serdes)
+			return table[i].phy_config;
+	}
+
+	return NULL;
+}
+
+/* BRDCFG4 controls EMI routing for the board.
+ * Bits    Function
+ * 7-6     EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
+ * EMI1    00= On-board PHY #1
+ *         01= On-board PHY #2
+ *         10= (reserved)
+ *         11= Slots 1..8 multiplexer and translator.
+ * 5-3     EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
+ * EMI1X   000= Slot #1
+ *         001= Slot #2
+ *         010= Slot #3
+ *         011= Slot #4
+ *         100= Slot #5
+ *         101= Slot #6
+ *         110= Slot #7
+ *         111= Slot #8
+ * 2-0     EMI Interface #2 Routing (CFG_MUX_EMI2):
+ * EMI2    000= Slot #1 (secondary EMI)
+ *         001= Slot #2 (secondary EMI)
+ *         010= Slot #3 (secondary EMI)
+ *         011= Slot #4 (secondary EMI)
+ *         100= Slot #5 (secondary EMI)
+ *         101= Slot #6 (secondary EMI)
+ *         110= Slot #7 (secondary EMI)
+ *         111= Slot #8 (secondary EMI)
+ */
+static int lx2162a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
+{
+	switch (realbusnum) {
+	case EMI1:
+		switch (ioslot) {
+		case EMI1_RGMII1:
+			return 0;
+		case EMI1_RGMII2:
+			return 0x40;
+		default:
+			return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
+		}
+		break;
+	case EMI2:
+		return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
+	default:
+		return -1;
+	}
+}
+
+static void lx2162a_qds_mux_mdio(struct lx2162a_qds_mdio *priv)
+{
+	u8 brdcfg4, mux_val, reg;
+
+	brdcfg4 = QIXIS_READ(brdcfg[4]);
+	reg = brdcfg4;
+	mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
+
+	switch (priv->realbusnum) {
+	case EMI1:
+		brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
+		brdcfg4 |= mux_val;
+		break;
+	case EMI2:
+		brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
+		brdcfg4 |= mux_val;
+		break;
+	}
+
+	if (brdcfg4 ^ reg)
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+}
+
+static int lx2162a_qds_mdio_read(struct mii_dev *bus, int addr,
+				 int devad, int regnum)
+{
+	struct lx2162a_qds_mdio *priv = bus->priv;
+
+	lx2162a_qds_mux_mdio(priv);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int lx2162a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				  int regnum, u16 value)
+{
+	struct lx2162a_qds_mdio *priv = bus->priv;
+
+	lx2162a_qds_mux_mdio(priv);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int lx2162a_qds_mdio_reset(struct mii_dev *bus)
+{
+	struct lx2162a_qds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static struct mii_dev *lx2162a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
+{
+	struct lx2162a_qds_mdio *pmdio;
+	struct mii_dev *bus;
+	/*should be within MDIO_NAME_LEN*/
+	char dummy_mdio_name[] = "LX2162A_QDS_MDIO1_IOSLOT1";
+
+	if (realbusnum == EMI2) {
+		if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
+			printf("invalid ioslot %d\n", ioslot);
+			return NULL;
+		}
+	} else if (realbusnum == EMI1) {
+		if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
+			printf("invalid ioslot %d\n", ioslot);
+			return NULL;
+		}
+	} else {
+		printf("not supported real mdio bus %d\n", realbusnum);
+		return NULL;
+	}
+
+	if (ioslot == EMI1_RGMII1)
+		strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII1");
+	else if (ioslot == EMI1_RGMII2)
+		strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII2");
+	else
+		sprintf(dummy_mdio_name, "LX2162A_QDS_MDIO%d_IOSLOT%d",
+			realbusnum, ioslot);
+	bus = miiphy_get_dev_by_name(dummy_mdio_name);
+
+	if (bus)
+		return bus;
+
+	bus = mdio_alloc();
+	if (!bus) {
+		printf("Failed to allocate %s bus\n", dummy_mdio_name);
+		return NULL;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate %s private data\n", dummy_mdio_name);
+		free(bus);
+		return NULL;
+	}
+
+	switch (realbusnum) {
+	case EMI1:
+		pmdio->realbus =
+		  miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+		break;
+	case EMI2:
+		pmdio->realbus =
+		  miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+		break;
+	}
+
+	if (!pmdio->realbus) {
+		printf("No real mdio bus num %d found\n", realbusnum);
+		free(bus);
+		free(pmdio);
+		return NULL;
+	}
+
+	pmdio->realbusnum = realbusnum;
+	pmdio->ioslot = ioslot;
+	bus->read = lx2162a_qds_mdio_read;
+	bus->write = lx2162a_qds_mdio_write;
+	bus->reset = lx2162a_qds_mdio_reset;
+	strcpy(bus->name, dummy_mdio_name);
+	bus->priv = pmdio;
+
+	if (!mdio_register(bus))
+		return bus;
+
+	printf("No bus with name %s\n", dummy_mdio_name);
+	free(bus);
+	free(pmdio);
+	return NULL;
+}
+
+static inline void do_phy_config(const struct phy_config *phy_config)
+{
+	struct mii_dev *bus;
+	int i, phy_num, phy_address;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (!phy_config[i].dpmacid)
+			continue;
+
+		for (phy_num = 0;
+		     phy_num < ARRAY_SIZE(phy_config[i].phy_address);
+		     phy_num++) {
+			phy_address = phy_config[i].phy_address[phy_num];
+			if (phy_address == -1)
+				break;
+			wriop_set_phy_address(phy_config[i].dpmacid,
+					      phy_num, phy_address);
+		}
+		/*Register the muxing front-ends to the MDIO buses*/
+		bus = lx2162a_qds_mdio_init(phy_config[i].mdio_bus,
+					    phy_config[i].ioslot);
+		if (!bus)
+			printf("could not get bus for mdio %d ioslot %d\n",
+			       phy_config[i].mdio_bus,
+			       phy_config[i].ioslot);
+		else
+			wriop_set_mdio(phy_config[i].dpmacid, bus);
+	}
+}
+
+static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
+				   char *env_dpmac)
+{
+	const char *ret;
+	size_t len;
+	u8 realbusnum, ioslot;
+	struct mii_dev *bus;
+	int phy_num;
+	char *phystr = "phy00";
+
+	/*search phy in dpmac arg*/
+	for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+		sprintf(phystr, "phy%d", phy_num + 1);
+		ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
+		if (!ret) {
+			/*look for phy instead of phy1*/
+			if (!phy_num)
+				ret = hwconfig_subarg_f(arg_dpmacid, "phy",
+							&len, env_dpmac);
+			if (!ret)
+				continue;
+		}
+
+		if (len != 4 || strncmp(ret, "0x", 2))
+			printf("invalid phy format in %s variable.\n"
+			       "specify phy%d for %s in hex format e.g. 0x12\n",
+			       env_dpmac, phy_num + 1, arg_dpmacid);
+		else
+			wriop_set_phy_address(dpmac, phy_num,
+					      simple_strtoul(ret, NULL, 16));
+	}
+
+	/*search mdio in dpmac arg*/
+	ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
+	if (ret)
+		realbusnum = *ret - '0';
+	else
+		realbusnum = EMI_NONE;
+
+	if (realbusnum) {
+		/*search io in dpmac arg*/
+		ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
+		if (ret)
+			ioslot = *ret - '0';
+		else
+			ioslot = IO_SLOT_NONE;
+		/*Register the muxing front-ends to the MDIO buses*/
+		bus = lx2162a_qds_mdio_init(realbusnum, ioslot);
+		if (!bus)
+			printf("could not get bus for mdio %d ioslot %d\n",
+			       realbusnum, ioslot);
+		else
+			wriop_set_mdio(dpmac, bus);
+	}
+}
+
+#endif
+#endif /* !CONFIG_DM_ETH */
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifndef CONFIG_DM_ETH
+#if defined(CONFIG_FSL_MC_ENET)
+	struct memac_mdio_info mdio_info;
+	struct memac_mdio_controller *regs;
+	int i;
+	const char *ret;
+	char *env_dpmac;
+	char dpmacid[] = "dpmac00", srds[] = "00_00_00";
+	size_t len;
+	struct mii_dev *bus;
+	const struct phy_config *phy_config;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 srds_s1, srds_s2;
+
+	srds_s1 = in_le32(&gur->rcwsr[28]) &
+		  FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	srds_s2 = in_le32(&gur->rcwsr[28]) &
+		  FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+	srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+	sprintf(srds, "%d_%d", srds_s1, srds_s2);
+
+	regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	mdio_info.regs = regs;
+	mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+	/*Register the EMI 1*/
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+	mdio_info.regs = regs;
+	mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+	/*Register the EMI 2*/
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	/* "dpmac" environment variable can be used after
+	 * defining "dpmac_override" in hwconfig environment variable.
+	 */
+	if (hwconfig("dpmac_override")) {
+		env_dpmac = env_get("dpmac");
+		if (env_dpmac) {
+			ret = hwconfig_arg_f("srds", &len, env_dpmac);
+			if (ret) {
+				if (strncmp(ret, srds, strlen(srds))) {
+					printf("SERDES configuration changed.\n"
+					       "previous: %.*s, current: %s.\n"
+					       "update dpmac variable.\n",
+					       (int)len, ret, srds);
+				}
+			} else {
+				printf("SERDES configuration not found.\n"
+				       "Please add srds:%s in dpmac variable\n",
+				       srds);
+			}
+
+			for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+				/* Look for dpmac1 to dpmac24(current max) arg
+				 * in dpmac environment variable
+				 */
+				sprintf(dpmacid, "dpmac%d", i);
+				ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
+				if (ret)
+					do_dpmac_config(i, dpmacid, env_dpmac);
+			}
+		} else {
+			printf("Warning: environment dpmac not found.\n"
+			       "DPAA network interfaces may not work\n");
+		}
+	} else {
+		/*Look for phy config for serdes1 in phy config table*/
+		phy_config = get_phy_config(srds_s1, serdes1_phy_config,
+					    ARRAY_SIZE(serdes1_phy_config));
+		if (!phy_config) {
+			printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
+			       __func__, srds_s1);
+		} else {
+			do_phy_config(phy_config);
+		}
+		phy_config = get_phy_config(srds_s2, serdes2_phy_config,
+					    ARRAY_SIZE(serdes2_phy_config));
+		if (!phy_config) {
+			printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
+			       __func__, srds_s2);
+		} else {
+			do_phy_config(phy_config);
+		}
+	}
+
+	if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
+		wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
+		bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII1);
+		if (!bus)
+			printf("could not get bus for RGMII1\n");
+		else
+			wriop_set_mdio(WRIOP1_DPMAC17, bus);
+	}
+
+	if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
+		wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
+		bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII2);
+		if (!bus)
+			printf("could not get bus for RGMII2\n");
+		else
+			wriop_set_mdio(WRIOP1_DPMAC18, bus);
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+#endif /* !CONFIG_DM_ETH */
+
+#ifdef CONFIG_PHY_AQUANTIA
+	/*
+	 * Export functions to be used by AQ firmware
+	 * upload application
+	 */
+	gd->jt->strcpy = strcpy;
+	gd->jt->mdelay = mdelay;
+	gd->jt->mdio_get_current_dev = mdio_get_current_dev;
+	gd->jt->phy_find_by_mask = phy_find_by_mask;
+	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
+	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
+#endif
+
+#ifdef CONFIG_DM_ETH
+	return 0;
+#else
+	return pci_eth_init(bis);
+#endif
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+	mc_env_boot();
+#endif
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#ifndef CONFIG_DM_ETH
+#if defined(CONFIG_FSL_MC_ENET)
+int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
+{
+	int offset;
+	int ret;
+	char dpmac_str[] = "dpmacs@00";
+	const char *phy_string;
+
+	offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
+
+	if (offset < 0) {
+		printf("dpmacs node not found in device tree\n");
+		return offset;
+	}
+
+	sprintf(dpmac_str, "dpmac@%x", dpmac_id);
+	debug("dpmac_str = %s\n", dpmac_str);
+
+	offset = fdt_subnode_offset(fdt, offset, dpmac_str);
+	if (offset < 0) {
+		printf("%s node not found in device tree\n", dpmac_str);
+		return offset;
+	}
+
+	phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
+	if (is_backplane_mode(phy_string)) {
+		/* Backplane KR mode: skip fixups */
+		printf("Interface %d in backplane KR mode\n", dpmac_id);
+		return 0;
+	}
+
+	ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
+	if (ret)
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+
+	phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
+	ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
+				 phy_string);
+	if (ret)
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+
+	return ret;
+}
+
+int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
+{
+	char mdio_ioslot_str[] = "mdio@00";
+	struct lx2162a_qds_mdio *priv;
+	u64 reg;
+	u32 phandle;
+	int offset, mux_val;
+
+	/*Test if the MDIO bus is real mdio bus or muxing front end ?*/
+	if (strncmp(mii_dev->name, "LX2162A_QDS_MDIO",
+		    strlen("LX2162A_QDS_MDIO")))
+		return -1;
+
+	/*Get the real MDIO bus num and ioslot info from bus's priv data*/
+	priv = mii_dev->priv;
+
+	debug("real_bus_num = %d, ioslot = %d\n",
+	      priv->realbusnum, priv->ioslot);
+
+	if (priv->realbusnum == EMI1)
+		reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	else
+		reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
+
+	offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
+	if (offset < 0) {
+		printf("mdio@%llx node not found in device tree\n", reg);
+		return offset;
+	}
+
+	phandle = fdt_get_phandle(fdt, offset);
+	phandle = cpu_to_fdt32(phandle);
+	offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
+					       &phandle, 4);
+	if (offset < 0) {
+		printf("mdio-mux-%d node not found in device tree\n",
+		       priv->realbusnum == EMI1 ? 1 : 2);
+		return offset;
+	}
+
+	mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
+	if (priv->realbusnum == EMI1)
+		mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
+	else
+		mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
+	sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
+
+	offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
+	if (offset < 0) {
+		printf("%s node not found in device tree\n", mdio_ioslot_str);
+		return offset;
+	}
+
+	return offset;
+}
+
+int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
+			struct phy_device *phy_dev, int phandle)
+{
+	char phy_node_name[] = "ethernet-phy@00";
+	char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
+	int ret;
+
+	sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
+	debug("phy_node_name = %s\n", phy_node_name);
+
+	*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
+	if (*subnodeoffset <= 0) {
+		printf("Could not add subnode %s inside node %s err = %s\n",
+		       phy_node_name, fdt_get_name(fdt, offset, NULL),
+		       fdt_strerror(*subnodeoffset));
+		return *subnodeoffset;
+	}
+
+	sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
+		phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
+	debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
+
+	ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
+				 phy_id_compatible_str);
+	if (ret) {
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+		goto out;
+	}
+
+	if (phy_dev->is_c45) {
+		ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
+					    "ethernet-phy-ieee802.3-c45");
+		if (ret) {
+			printf("%d@%s %d\n", __LINE__, __func__, ret);
+			goto out;
+		}
+	} else {
+		ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
+					    "ethernet-phy-ieee802.3-c22");
+		if (ret) {
+			printf("%d@%s %d\n", __LINE__, __func__, ret);
+			goto out;
+		}
+	}
+
+	ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
+	if (ret) {
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+		goto out;
+	}
+
+	ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
+	if (ret) {
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+		goto out;
+	}
+
+out:
+	if (ret)
+		fdt_del_node(fdt, *subnodeoffset);
+
+	return ret;
+}
+
+#define is_rgmii(dpmac_id) \
+	wriop_get_enet_if((dpmac_id)) == PHY_INTERFACE_MODE_RGMII_ID
+
+int fdt_fixup_board_phy(void *fdt)
+{
+	int fpga_offset, offset, subnodeoffset;
+	struct mii_dev *mii_dev;
+	struct list_head *mii_devs, *entry;
+	int ret, dpmac_id, phandle, i;
+	struct phy_device *phy_dev;
+	char ethname[ETH_NAME_LEN];
+	phy_interface_t	phy_iface;
+
+	ret = 0;
+	/* we know FPGA is connected to i2c0, therefore search path directly,
+	 * instead of compatible property, as it saves time
+	 */
+	fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
+
+	if (fpga_offset < 0)
+		fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
+
+	if (fpga_offset < 0) {
+		printf("i2c@2000000/fpga node not found in device tree\n");
+		return fpga_offset;
+	}
+
+	phandle = fdt_alloc_phandle(fdt);
+	mii_devs = mdio_get_list_head();
+
+	list_for_each(entry, mii_devs) {
+		mii_dev = list_entry(entry, struct mii_dev, link);
+		debug("mii_dev name : %s\n", mii_dev->name);
+		offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
+		if (offset < 0)
+			continue;
+
+		// Look for phy devices attached to MDIO bus muxing front end
+		// and create their entries with compatible being the device id
+		for (i = 0; i < PHY_MAX_ADDR; i++) {
+			phy_dev = mii_dev->phymap[i];
+			if (!phy_dev)
+				continue;
+
+			// TODO: use sscanf instead of loop
+			dpmac_id = WRIOP1_DPMAC1;
+			while (dpmac_id < NUM_WRIOP_PORTS) {
+				phy_iface = wriop_get_enet_if(dpmac_id);
+				snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
+					 dpmac_id,
+					 phy_string_for_interface(phy_iface));
+				if (strcmp(ethname, phy_dev->dev->name) == 0)
+					break;
+				dpmac_id++;
+			}
+			if (dpmac_id == NUM_WRIOP_PORTS)
+				continue;
+
+			if ((dpmac_id == 17 || dpmac_id == 18) &&
+			    is_rgmii(dpmac_id))
+				continue;
+
+			ret = fdt_create_phy_node(fdt, offset, i,
+						  &subnodeoffset,
+						  phy_dev, phandle);
+			if (ret)
+				break;
+
+			ret = fdt_fixup_dpmac_phy_handle(fdt,
+							 dpmac_id, phandle);
+			if (ret) {
+				fdt_del_node(fdt, subnodeoffset);
+				break;
+			}
+			/* calculate offset again as new node addition may have
+			 * changed offset;
+			 */
+			offset = fdt_get_ioslot_offset(fdt, mii_dev,
+						       fpga_offset);
+			phandle++;
+		}
+
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+#endif // CONFIG_FSL_MC_ENET
+#endif
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+
+/* Structure to hold SERDES protocols supported in case of
+ * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+ *
+ * @serdes_block: the index of the SERDES block
+ * @serdes_protocol: the decimal value of the protocol supported
+ * @dts_needed: DTS notes describing the current configuration are needed
+ *
+ * When dts_needed is true, the board_fit_config_name_match() function
+ * will try to exactly match the current configuration of the block with a DTS
+ * name provided.
+ */
+static struct serdes_configuration {
+	u8 serdes_block;
+	u32 serdes_protocol;
+	bool dts_needed;
+} supported_protocols[] = {
+	/* Serdes block #1 */
+	{1, 2, true},
+	{1, 3, true},
+	{1, 15, true},
+	{1, 17, true},
+	{1, 18, true},
+	{1, 20, true},
+
+	/* Serdes block #2 */
+	{2, 2, false},
+	{2, 3, false},
+	{2, 5, false},
+	{2, 10, false},
+	{2, 11, true},
+	{2, 12, true},
+};
+
+#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
+
+static bool protocol_supported(u8 serdes_block, u32 protocol)
+{
+	struct serdes_configuration serdes_conf;
+	int i;
+
+	for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+		serdes_conf = supported_protocols[i];
+		if (serdes_conf.serdes_block == serdes_block &&
+		    serdes_conf.serdes_protocol == protocol)
+			return true;
+	}
+
+	return false;
+}
+
+static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
+{
+	struct serdes_configuration serdes_conf;
+	int i;
+
+	for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+		serdes_conf = supported_protocols[i];
+		if (serdes_conf.serdes_block == serdes_block &&
+		    serdes_conf.serdes_protocol == protocol) {
+			if (serdes_conf.dts_needed == true)
+				sprintf(str, "%u", protocol);
+			else
+				sprintf(str, "x");
+			return;
+		}
+	}
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 rcw_status = in_le32(&gur->rcwsr[28]);
+	char srds_s1_str[2], srds_s2_str[2];
+	u32 srds_s1, srds_s2;
+	char expected_dts[100];
+
+	srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+	srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+	/* Check for supported protocols. The default DTS will be used
+	 * in this case
+	 */
+	if (!protocol_supported(1, srds_s1) ||
+	    !protocol_supported(2, srds_s2))
+		return -1;
+
+	get_str_protocol(1, srds_s1, srds_s1_str);
+	get_str_protocol(2, srds_s2, srds_s2_str);
+
+	sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s",
+		srds_s1_str, srds_s2_str);
+
+	if (!strcmp(name, expected_dts))
+		return 0;
+
+	return -1;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/lx2160a/lx2160a.c b/roms/u-boot/board/freescale/lx2160a/lx2160a.c
new file mode 100644
index 000000000..47a7024f3
--- /dev/null
+++ b/roms/u-boot/board/freescale/lx2160a/lx2160a.c
@@ -0,0 +1,810 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2020 NXP
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <dm.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ddr.h>
+#include <fsl_sec.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <linux/bitops.h>
+#include <linux/libfdt.h>
+#include <linux/delay.h>
+#include <fsl-mc/fsl_mc.h>
+#include <env_internal.h>
+#include <efi_loader.h>
+#include <asm/arch/mmu.h>
+#include <hwconfig.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/config.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include "../common/qixis.h"
+#include "../common/vid.h"
+#include <fsl_immap.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include "lx2160a.h"
+
+#ifdef CONFIG_EMC2305
+#include "../common/emc2305.h"
+#endif
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+#define CFG_MUX_I2C_SDHC(reg, value)		((reg & 0x3f) | value)
+#define SET_CFG_MUX1_SDHC1_SDHC(reg)		(reg & 0x3f)
+#define SET_CFG_MUX2_SDHC1_SPI(reg, value)	((reg & 0xcf) | value)
+#define SET_CFG_MUX3_SDHC1_SPI(reg, value)	((reg & 0xf8) | value)
+#define SET_CFG_MUX_SDHC2_DSPI(reg, value)	((reg & 0xf8) | value)
+#define SET_CFG_MUX1_SDHC1_DSPI(reg, value)	((reg & 0x3f) | value)
+#define SDHC1_BASE_PMUX_DSPI			2
+#define SDHC2_BASE_PMUX_DSPI			2
+#define IIC5_PMUX_SPI3				3
+#endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pl01x_serial_plat serial0 = {
+#if CONFIG_CONS_INDEX == 0
+	.base = CONFIG_SYS_SERIAL0,
+#elif CONFIG_CONS_INDEX == 1
+	.base = CONFIG_SYS_SERIAL1,
+#else
+#error "Unsupported console index value."
+#endif
+	.type = TYPE_PL011,
+};
+
+U_BOOT_DRVINFO(nxp_serial0) = {
+	.name = "serial_pl01x",
+	.plat = &serial0,
+};
+
+static struct pl01x_serial_plat serial1 = {
+	.base = CONFIG_SYS_SERIAL1,
+	.type = TYPE_PL011,
+};
+
+U_BOOT_DRVINFO(nxp_serial1) = {
+	.name = "serial_pl01x",
+	.plat = &serial1,
+};
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void uart_get_clock(void)
+{
+	serial0.clock = get_serial_clock();
+	serial1.clock = get_serial_clock();
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
+	/* get required clock for UART IP */
+	uart_get_clock();
+
+#ifdef CONFIG_EMC2305
+	select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
+	emc2305_init(I2C_EMC2305_ADDR);
+	set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+#endif
+
+	fsl_lsch3_early_init_f();
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_FIXUP
+int board_fix_fdt(void *fdt)
+{
+	char *reg_names, *reg_name;
+	int names_len, old_name_len, new_name_len, remaining_names_len;
+	struct str_map {
+		char *old_str;
+		char *new_str;
+	} reg_names_map[] = {
+		{ "ccsr", "dbi" },
+		{ "pf_ctrl", "ctrl" }
+	};
+	int off = -1, i = 0;
+
+	if (IS_SVR_REV(get_svr(), 1, 0))
+		return 0;
+
+	off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
+	while (off != -FDT_ERR_NOTFOUND) {
+		fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
+			    strlen("fsl,ls-pcie") + 1);
+
+		reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
+						&names_len);
+		if (!reg_names)
+			continue;
+
+		reg_name = reg_names;
+		remaining_names_len = names_len - (reg_name - reg_names);
+		i = 0;
+		while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
+			old_name_len = strlen(reg_names_map[i].old_str);
+			new_name_len = strlen(reg_names_map[i].new_str);
+			if (memcmp(reg_name, reg_names_map[i].old_str,
+				   old_name_len) == 0) {
+				/* first only leave required bytes for new_str
+				 * and copy rest of the string after it
+				 */
+				memcpy(reg_name + new_name_len,
+				       reg_name + old_name_len,
+				       remaining_names_len - old_name_len);
+				/* Now copy new_str */
+				memcpy(reg_name, reg_names_map[i].new_str,
+				       new_name_len);
+				names_len -= old_name_len;
+				names_len += new_name_len;
+				i++;
+			}
+
+			reg_name = memchr(reg_name, '\0', remaining_names_len);
+			if (!reg_name)
+				break;
+
+			reg_name += 1;
+
+			remaining_names_len = names_len -
+					      (reg_name - reg_names);
+		}
+
+		fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
+		off = fdt_node_offset_by_compatible(fdt, off,
+						    "fsl,lx2160a-pcie");
+	}
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+void esdhc_dspi_status_fixup(void *blob)
+{
+	const char esdhc0_path[] = "/soc/esdhc@2140000";
+	const char esdhc1_path[] = "/soc/esdhc@2150000";
+	const char dspi0_path[] = "/soc/spi@2100000";
+	const char dspi1_path[] = "/soc/spi@2110000";
+	const char dspi2_path[] = "/soc/spi@2120000";
+
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 sdhc1_base_pmux;
+	u32 sdhc2_base_pmux;
+	u32 iic5_pmux;
+
+	/* Check RCW field sdhc1_base_pmux to enable/disable
+	 * esdhc0/dspi0 DT node
+	 */
+	sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
+		& FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
+	sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
+
+	if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
+		do_fixup_by_path(blob, dspi0_path, "status", "okay",
+				 sizeof("okay"), 1);
+		do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
+				 sizeof("disabled"), 1);
+	} else {
+		do_fixup_by_path(blob, esdhc0_path, "status", "okay",
+				 sizeof("okay"), 1);
+		do_fixup_by_path(blob, dspi0_path, "status", "disabled",
+				 sizeof("disabled"), 1);
+	}
+
+	/* Check RCW field sdhc2_base_pmux to enable/disable
+	 * esdhc1/dspi1 DT node
+	 */
+	sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
+		& FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
+	sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
+
+	if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
+		do_fixup_by_path(blob, dspi1_path, "status", "okay",
+				 sizeof("okay"), 1);
+		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+				 sizeof("disabled"), 1);
+	} else {
+		do_fixup_by_path(blob, esdhc1_path, "status", "okay",
+				 sizeof("okay"), 1);
+		do_fixup_by_path(blob, dspi1_path, "status", "disabled",
+				 sizeof("disabled"), 1);
+	}
+
+	/* Check RCW field IIC5 to enable dspi2 DT node */
+	iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
+		& FSL_CHASSIS3_IIC5_PMUX_MASK;
+	iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
+
+	if (iic5_pmux == IIC5_PMUX_SPI3)
+		do_fixup_by_path(blob, dspi2_path, "status", "okay",
+				 sizeof("okay"), 1);
+	else
+		do_fixup_by_path(blob, dspi2_path, "status", "disabled",
+				 sizeof("disabled"), 1);
+}
+#endif
+
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+	/* Enable esdhc and dspi DT nodes based on RCW fields */
+	esdhc_dspi_status_fixup(blob);
+#else
+	/* Enable both esdhc DT nodes for LX2160ARDB */
+	do_fixup_by_compat(blob, compat, "status", "okay",
+			   sizeof("okay"), 1);
+#endif
+	return 0;
+}
+
+#if defined(CONFIG_VID)
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+	return select_i2c_ch_pca9547(channel);
+}
+
+int init_func_vid(void)
+{
+	int set_vid;
+
+	if (IS_SVR_REV(get_svr(), 1, 0))
+		set_vid = adjust_vdd(800);
+	else
+		set_vid = adjust_vdd(0);
+
+	if (set_vid < 0)
+		printf("core voltage not adjusted\n");
+
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	enum boot_src src = get_boot_src();
+	char buf[64];
+	u8 sw;
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+	int clock;
+	static const char *const freq[] = {"100", "125", "156.25",
+					   "161.13", "322.26", "", "", "",
+					   "", "", "", "", "", "", "",
+					   "100 separate SSCG"};
+#endif
+
+	cpu_name(buf);
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+	printf("Board: %s-QDS, ", buf);
+#else
+	printf("Board: %s-RDB, ", buf);
+#endif
+
+	sw = QIXIS_READ(arch);
+	printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
+
+	if (src == BOOT_SOURCE_SD_MMC) {
+		puts("SD\n");
+	} else if (src == BOOT_SOURCE_SD_MMC2) {
+		puts("eMMC\n");
+	} else {
+		sw = QIXIS_READ(brdcfg[0]);
+		sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
+		switch (sw) {
+		case 0:
+		case 4:
+			puts("FlexSPI DEV#0\n");
+			break;
+		case 1:
+			puts("FlexSPI DEV#1\n");
+			break;
+		case 2:
+		case 3:
+			puts("FlexSPI EMU\n");
+			break;
+		default:
+			printf("invalid setting, xmap: %d\n", sw);
+			break;
+		}
+	}
+#if defined(CONFIG_TARGET_LX2160ARDB)
+	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
+
+	puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
+	puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+	puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+#else
+	printf("FPGA: v%d (%s), build %d",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+
+	puts("SERDES1 Reference : ");
+	sw = QIXIS_READ(brdcfg[2]);
+	clock = sw >> 4;
+	printf("Clock1 = %sMHz ", freq[clock]);
+#if defined(CONFIG_TARGET_LX2160AQDS)
+	clock = sw & 0x0f;
+	printf("Clock2 = %sMHz", freq[clock]);
+#endif
+	sw = QIXIS_READ(brdcfg[3]);
+	puts("\nSERDES2 Reference : ");
+	clock = sw >> 4;
+	printf("Clock1 = %sMHz ", freq[clock]);
+	clock = sw & 0x0f;
+	printf("Clock2 = %sMHz\n", freq[clock]);
+#if defined(CONFIG_TARGET_LX2160AQDS)
+	sw = QIXIS_READ(brdcfg[12]);
+	puts("SERDES3 Reference : ");
+	clock = sw >> 4;
+	printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
+#endif
+#endif
+	return 0;
+}
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+/*
+ * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
+ */
+u8 qixis_esdhc_detect_quirk(void)
+{
+	/*
+	 * SDHC1 Card ID:
+	 * Specifies the type of card installed in the SDHC1 adapter slot.
+	 * 000= (reserved)
+	 * 001= eMMC V4.5 adapter is installed.
+	 * 010= SD/MMC 3.3V adapter is installed.
+	 * 011= eMMC V4.4 adapter is installed.
+	 * 100= eMMC V5.0 adapter is installed.
+	 * 101= MMC card/Legacy (3.3V) adapter is installed.
+	 * 110= SDCard V2/V3 adapter installed.
+	 * 111= no adapter is installed.
+	 */
+	return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
+		 QIXIS_ESDHC_NO_ADAPTER);
+}
+
+static void esdhc_adapter_card_ident(void)
+{
+	u8 card_id, val;
+
+	val = QIXIS_READ(sdhc1);
+	card_id = val & QIXIS_SDID_MASK;
+
+	switch (card_id) {
+	case QIXIS_ESDHC_ADAPTER_TYPE_SD:
+		/* Power cycle to card */
+		val &= ~QIXIS_SDHC1_S1V3;
+		QIXIS_WRITE(sdhc1, val);
+		mdelay(1);
+		val |= QIXIS_SDHC1_S1V3;
+		QIXIS_WRITE(sdhc1, val);
+		/* Route to SDHC1_VS */
+		val = QIXIS_READ(brdcfg[11]);
+		val |= QIXIS_SDHC1_VS;
+		QIXIS_WRITE(brdcfg[11], val);
+		break;
+	default:
+		break;
+	}
+}
+
+int config_board_mux(void)
+{
+	u8 reg11, reg5, reg13;
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 sdhc1_base_pmux;
+	u32 sdhc2_base_pmux;
+	u32 iic5_pmux;
+
+	/* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
+	 * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
+	 * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
+	 * Qixis and remote systems are isolated from the I2C1 bus.
+	 * Processor connections are still available.
+	 * SPI2 CS2_B controls EN25S64 SPI memory device.
+	 * SPI3 CS2_B controls EN25S64 SPI memory device.
+	 * EC2 connects to PHY #2 using RGMII protocol.
+	 * CLK_OUT connects to FPGA for clock measurement.
+	 */
+
+	reg5 = QIXIS_READ(brdcfg[5]);
+	reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
+	QIXIS_WRITE(brdcfg[5], reg5);
+
+	/* Check RCW field sdhc1_base_pmux
+	 * esdhc0 : sdhc1_base_pmux = 0
+	 * dspi0  : sdhc1_base_pmux = 2
+	 */
+	sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
+		& FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
+	sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
+
+	if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
+		reg11 = QIXIS_READ(brdcfg[11]);
+		reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
+		QIXIS_WRITE(brdcfg[11], reg11);
+	} else {
+		/* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
+		 *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
+		 *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
+		 */
+		reg11 = QIXIS_READ(brdcfg[11]);
+		reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
+		QIXIS_WRITE(brdcfg[11], reg11);
+	}
+
+	/* Check RCW field sdhc2_base_pmux
+	 * esdhc1 : sdhc2_base_pmux = 0 (default)
+	 * dspi1  : sdhc2_base_pmux = 2
+	 */
+	sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
+		& FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
+	sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
+
+	if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
+		reg13 = QIXIS_READ(brdcfg[13]);
+		reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
+		QIXIS_WRITE(brdcfg[13], reg13);
+	} else {
+		reg13 = QIXIS_READ(brdcfg[13]);
+		reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
+		QIXIS_WRITE(brdcfg[13], reg13);
+	}
+
+	/* Check RCW field IIC5 to enable dspi2 DT nodei
+	 * dspi2: IIC5 = 3
+	 */
+	iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
+		& FSL_CHASSIS3_IIC5_PMUX_MASK;
+	iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
+
+	if (iic5_pmux == IIC5_PMUX_SPI3) {
+		/* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
+		reg11 = QIXIS_READ(brdcfg[11]);
+		reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
+		QIXIS_WRITE(brdcfg[11], reg11);
+
+		/* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
+		 * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
+		 * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
+		 */
+		reg11 = QIXIS_READ(brdcfg[11]);
+		reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
+		QIXIS_WRITE(brdcfg[11], reg11);
+	} else {
+		/*
+		 * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
+		 * do not change it.
+		 * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
+		 */
+		reg11 = QIXIS_READ(brdcfg[11]);
+		if ((reg11 & 0x30) != 0x30) {
+			reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
+			QIXIS_WRITE(brdcfg[11], reg11);
+		}
+
+		/* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
+		 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
+		 * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
+		 */
+		reg11 = QIXIS_READ(brdcfg[11]);
+		reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
+		QIXIS_WRITE(brdcfg[11], reg11);
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	esdhc_adapter_card_ident();
+	return 0;
+}
+#elif defined(CONFIG_TARGET_LX2160ARDB)
+int config_board_mux(void)
+{
+	u8 brdcfg;
+
+	brdcfg = QIXIS_READ(brdcfg[4]);
+	/* The BRDCFG4 register controls general board configuration.
+	 *|-------------------------------------------|
+	 *|Field  | Function                          |
+	 *|-------------------------------------------|
+	 *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
+	 *|CAN_EN | 0= CAN transceivers are disabled. |
+	 *|       | 1= CAN transceivers are enabled.  |
+	 *|-------------------------------------------|
+	 */
+	brdcfg |= BIT_MASK(5);
+	QIXIS_WRITE(brdcfg[4], brdcfg);
+
+	return 0;
+}
+#else
+int config_board_mux(void)
+{
+	return 0;
+}
+#endif
+
+unsigned long get_board_sys_clk(void)
+{
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x03) {
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	}
+	return 100000000;
+#else
+	return 100000000;
+#endif
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 100000000;
+#else
+	return 100000000;
+#endif
+}
+
+int board_init(void)
+{
+#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
+	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
+	/* invert AQR107 IRQ pins polarity */
+	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+	pci_init();
+#endif
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	int i;
+	u64 ddr_size = 0;
+
+	puts("\nDDR    ");
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		ddr_size += gd->bd->bi_dram[i].size;
+	print_size(ddr_size, "");
+	print_ddr_info(0);
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	config_board_mux();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_VID
+u16 soc_get_fuse_vid(int vid_index)
+{
+	static const u16 vdd[32] = {
+		8250,
+		7875,
+		7750,
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		8000,
+		8125,
+		8250,
+		0,      /* reserved */
+		8500,
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+	};
+
+	return vdd[vid_index];
+};
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+extern int fdt_fixup_board_phy(void *fdt);
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	int offset;
+
+	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/fsl-mc");
+
+	if (offset < 0) {
+		printf("%s: fsl-mc node not found in device tree (error %d)\n",
+		       __func__, offset);
+		return;
+	}
+
+	if (get_mc_boot_status() == 0 &&
+	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
+		fdt_status_okay(fdt, offset);
+#ifndef CONFIG_DM_ETH
+		fdt_fixup_board_phy(fdt);
+#endif
+	} else {
+		fdt_status_fail(fdt, offset);
+	}
+}
+
+void board_quiesce_devices(void)
+{
+	fsl_mc_ldpaa_exit(gd->bd);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int i;
+	u16 mc_memory_bank = 0;
+
+	u64 *base;
+	u64 *size;
+	u64 mc_memory_base = 0;
+	u64 mc_memory_size = 0;
+	u16 total_memory_banks;
+
+	ft_cpu_setup(blob, bd);
+
+	fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+	if (mc_memory_base != 0)
+		mc_memory_bank++;
+
+	total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+	base = calloc(total_memory_banks, sizeof(u64));
+	size = calloc(total_memory_banks, sizeof(u64));
+
+	/* fixup DT for the three GPP DDR banks */
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		base[i] = gd->bd->bi_dram[i].start;
+		size[i] = gd->bd->bi_dram[i].size;
+	}
+
+#ifdef CONFIG_RESV_RAM
+	/* reduce size if reserved memory is within this bank */
+	if (gd->arch.resv_ram >= base[0] &&
+	    gd->arch.resv_ram < base[0] + size[0])
+		size[0] = gd->arch.resv_ram - base[0];
+	else if (gd->arch.resv_ram >= base[1] &&
+		 gd->arch.resv_ram < base[1] + size[1])
+		size[1] = gd->arch.resv_ram - base[1];
+	else if (gd->arch.resv_ram >= base[2] &&
+		 gd->arch.resv_ram < base[2] + size[2])
+		size[2] = gd->arch.resv_ram - base[2];
+#endif
+
+	if (mc_memory_base != 0) {
+		for (i = 0; i <= total_memory_banks; i++) {
+			if (base[i] == 0 && size[i] == 0) {
+				base[i] = mc_memory_base;
+				size[i] = mc_memory_size;
+				break;
+			}
+		}
+	}
+
+	fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
+
+#ifdef CONFIG_USB
+	fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+	fdt_fsl_mc_fixup_iommu_map_entry(blob);
+	fdt_fixup_board_enet(blob);
+#endif
+	fdt_fixup_icid(blob);
+
+	return 0;
+}
+#endif
+
+void qixis_dump_switch(void)
+{
+	int i, nr_of_cfgsw;
+
+	QIXIS_WRITE(cms[0], 0x00);
+	nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+	puts("DIP switch settings dump:\n");
+	for (i = 1; i <= nr_of_cfgsw; i++) {
+		QIXIS_WRITE(cms[0], i);
+		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+	}
+}
diff --git a/roms/u-boot/board/freescale/lx2160a/lx2160a.h b/roms/u-boot/board/freescale/lx2160a/lx2160a.h
new file mode 100644
index 000000000..52b020765
--- /dev/null
+++ b/roms/u-boot/board/freescale/lx2160a/lx2160a.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __LX2160_H
+#define __LX2160_H
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+/* SYSCLK */
+#define QIXIS_SYSCLK_100		0x0
+#define QIXIS_SYSCLK_125		0x1
+#define QIXIS_SYSCLK_133		0x2
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_100		0x0
+#define QIXIS_DDRCLK_125		0x1
+#define QIXIS_DDRCLK_133		0x2
+
+#define BRDCFG4_EMI1SEL_MASK		0xF8
+#define BRDCFG4_EMI1SEL_SHIFT		3
+#define BRDCFG4_EMI2SEL_MASK		0x07
+#define BRDCFG4_EMI2SEL_SHIFT		0
+#endif
+
+#define QIXIS_XMAP_SHIFT		5
+
+/* RTC */
+#define I2C_MUX_CH_RTC			0xB
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+#define AQ_PHY_ADDR1			0x00
+#define AQ_PHY_ADDR2			0x01
+#define AQ_PHY_ADDR3			0x02
+#define AQ_PHY_ADDR4			0x03
+#endif
+
+#ifdef CONFIG_TARGET_LX2160ARDB
+#define AQR107_PHY_ADDR1		0x04
+#define AQR107_PHY_ADDR2		0x05
+#define AQR107_IRQ_MASK			0x0C
+#endif
+
+#define CORTINA_PHY_ADDR1		0x0
+#define INPHI_PHY_ADDR1			0x0
+
+#define RGMII_PHY_ADDR1			0x01
+#define RGMII_PHY_ADDR2			0x02
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+#define INPHI_PHY_ADDR2			0x1
+#define SGMII_CARD_PORT1_PHY_ADDR	0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR	0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR	0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR	0x1F
+#endif
+#endif
+
+#endif /* __LX2160_H */
diff --git a/roms/u-boot/board/freescale/m5208evbe/Kconfig b/roms/u-boot/board/freescale/m5208evbe/Kconfig
new file mode 100644
index 000000000..9b416afbd
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5208evbe/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5208EVBE
+
+config SYS_CPU
+	default "mcf52x2"
+
+config SYS_BOARD
+	default "m5208evbe"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M5208EVBE"
+
+endif
diff --git a/roms/u-boot/board/freescale/m5208evbe/MAINTAINERS b/roms/u-boot/board/freescale/m5208evbe/MAINTAINERS
new file mode 100644
index 000000000..c9c3c882e
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5208evbe/MAINTAINERS
@@ -0,0 +1,6 @@
+M5208EVBE BOARD
+#M:	-
+S:	Maintained
+F:	board/freescale/m5208evbe/
+F:	include/configs/M5208EVBE.h
+F:	configs/M5208EVBE_defconfig
diff --git a/roms/u-boot/board/freescale/m5208evbe/Makefile b/roms/u-boot/board/freescale/m5208evbe/Makefile
new file mode 100644
index 000000000..b7a7c3e64
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5208evbe/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m5208evbe.o
diff --git a/roms/u-boot/board/freescale/m5208evbe/m5208evbe.c b/roms/u-boot/board/freescale/m5208evbe/m5208evbe.c
new file mode 100644
index 000000000..7bfb4557d
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5208evbe/m5208evbe.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M5208EVBe\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
+#endif
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+	udelay(500);
+
+	/* Issue PALL */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+	asm("nop");
+
+	/* Perform two refresh cycles */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	asm("nop");
+
+	/* Issue LEMR */
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+	asm("nop");
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	asm("nop");
+
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+	asm("nop");
+
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
+	asm("nop");
+
+	udelay(100);
+
+	gd->ram_size = dramsize;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/roms/u-boot/board/freescale/m52277evb/Kconfig b/roms/u-boot/board/freescale/m52277evb/Kconfig
new file mode 100644
index 000000000..c4278926a
--- /dev/null
+++ b/roms/u-boot/board/freescale/m52277evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M52277EVB
+
+config SYS_CPU
+	default "mcf5227x"
+
+config SYS_BOARD
+	default "m52277evb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M52277EVB"
+
+endif
diff --git a/roms/u-boot/board/freescale/m52277evb/MAINTAINERS b/roms/u-boot/board/freescale/m52277evb/MAINTAINERS
new file mode 100644
index 000000000..a2a2176f6
--- /dev/null
+++ b/roms/u-boot/board/freescale/m52277evb/MAINTAINERS
@@ -0,0 +1,7 @@
+M52277EVB BOARD
+M:	TsiChung Liew <Tsi-Chung.Liew@nxp.com>
+S:	Maintained
+F:	board/freescale/m52277evb/
+F:	include/configs/M52277EVB.h
+F:	configs/M52277EVB_defconfig
+F:	configs/M52277EVB_stmicro_defconfig
diff --git a/roms/u-boot/board/freescale/m52277evb/Makefile b/roms/u-boot/board/freescale/m52277evb/Makefile
new file mode 100644
index 000000000..f98b0c937
--- /dev/null
+++ b/roms/u-boot/board/freescale/m52277evb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m52277evb.o
diff --git a/roms/u-boot/board/freescale/m52277evb/README b/roms/u-boot/board/freescale/m52277evb/README
new file mode 100644
index 000000000..8bfd8122d
--- /dev/null
+++ b/roms/u-boot/board/freescale/m52277evb/README
@@ -0,0 +1,228 @@
+Freescale MCF52277EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created Jan 8, 2008
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m52277evb/m52277evb.c	Dram setup
+- board/freescale/m52277evb/Makefile	Makefile
+- board/freescale/m52277evb/config.mk	config make
+- board/freescale/m52277evb/u-boot.lds	Linker description
+
+- arch/m68k/cpu/mcf5227x/cpu.c		cpu specific code
+- arch/m68k/cpu/mcf5227x/cpu_init.c	FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf5227x/interrupts.c	cpu specific interrupt support
+- arch/m68k/cpu/mcf5227x/speed.c		system, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5227x/Makefile		Makefile
+- arch/m68k/cpu/mcf5227x/config.mk	config make
+- arch/m68k/cpu/mcf5227x/start.S		start up assembly code
+
+- board/freescale/m52277evb/README	This readme file
+
+- drivers/serial/mcfuart.c	ColdFire common UART driver
+- drivers/rtc/mcfrtc.c		Realtime clock Driver
+
+- include/asm-m68k/bitops.h		Bit operation function export
+- include/asm-m68k/byteorder.h		Byte order functions
+- include/asm-m68k/crossbar.h		CrossBar structure and definition
+- include/asm-m68k/dspi.h		DSPI structure and definition
+- include/asm-m68k/edma.h		eDMA structure and definition
+- include/asm-m68k/flexbus.h		FlexBus structure and definition
+- include/asm-m68k/fsl_i2c.h		I2C structure and definition
+- include/asm-m68k/global_data.h	Global data structure
+- include/asm-m68k/immap.h		ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5227x.h	mcf5227x specific header file
+- include/asm-m68k/io.h			io functions
+- include/asm-m68k/lcd.h		LCD structure and definition
+- include/asm-m68k/m5227x.h		mcf5227x specific header file
+- include/asm-m68k/posix_types.h	Posix
+- include/asm-m68k/processor.h		header file
+- include/asm-m68k/ptrace.h		Exception structure
+- include/asm-m68k/rtc.h		Realtime clock header file
+- include/asm-m68k/ssi.h		SSI structure and definition
+- include/asm-m68k/string.h		String function export
+- include/asm-m68k/timer.h		Timer structure and definition
+- include/asm-m68k/types.h		Data types definition
+- include/asm-m68k/uart.h		Uart structure and definition
+- include/asm-m68k/u-boot.h		U-Boot structure
+
+- include/configs/M52277EVB.h		Board specific configuration file
+
+- arch/m68k/lib/board.c			board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts			Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c			Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c			Exception init code
+
+1 MCF52277 specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in this coldfire family
+
+1.2 Configuration settings for M52277EVB Development Board
+CONFIG_MCF5227x		-- define for all MCF5227x CPUs
+CONFIG_M52277		-- define for all Freescale MCF52277 CPUs
+
+CONFIG_MCFUART		-- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE		-- define UART baudrate
+
+CONFIG_MCFRTC		-- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE		-- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR	-- define RTC clock frequency
+RTC_DEBUG		-- define to show RTC debug message
+CONFIG_CMD_DATE		-- enable to use date feature in U-Boot
+
+CONFIG_MCFTMR		-- define to use DMA timer
+
+CONFIG_SYS_I2C_FSL	-- define to use FSL common I2C driver
+CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED		-- define for I2C speed
+CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
+CONFIG_SYS_IMMR		-- define for MBAR offset
+
+CONFIG_SYS_MBAR		-- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF52277 internal SRAM
+
+CONFIG_SYS_CSn_BASE	-- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK	-- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL	-- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE	-- defines the DRAM Base
+
+CONFIG_LCD and CONFIG_CMD_USB are not supported in this current U-Boot,
+update will be provided at later time
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+	Flash:		0x00000000-0x3FFFFFFF (1024MB)
+	DDR:		0x40000000-0x7FFFFFFF (1024MB)
+	SRAM:		0x80000000-0x8FFFFFFF (256MB)
+	IP:		0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and
+	linux kernel, you can customize it based on your system requirements:
+	Flash0:		0x00000000-0x00FFFFFF (16MB)
+
+	DDR:		0x40000000-0x4FFFFFFF (64MB)
+	SRAM:		0x80000000-0x80007FFF (32KB)
+	IP:		0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1	To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+   export CROSS_COMPILE=cross-compile-prefix
+   cd u-boot-1.x.x
+   make distclean
+   make M52277EVB_config
+   make
+
+4. SCREEN DUMP
+==============
+4.1 M52277EVB Development board
+    (NOTE: May not show exactly the same)
+
+U-Boot 1.3.1 (Jan 8 2008 - 12:44:08)
+
+CPU:   Freescale MCF52277 (Mask:6c Version:0)
+       CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ
+       INP CLK 16 Mhz VCO CLK 480 Mhz
+Board: Freescale 52277 EVB
+I2C:   ready
+DRAM:  64 MB
+FLASH: 16 MB
+In:    serial
+Out:   serial
+Err:   serial
+-> print
+baudrate=115200
+hostname=M52277EVB
+inpclk=16000000
+loadaddr=(0x40000000 + 0x10000)
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save
+u-boot=u-boot.bin
+stdin=serial
+stdout=serial
+stderr=serial
+mem=65024k
+
+Environment size: 280/32764 bytes
+-> bdinfo
+memstart    = 0x40000000
+memsize     = 0x04000000
+flashstart  = 0x00000000
+flashsize   = 0x01000000
+flashoffset = 0x00000000
+sramstart   = 0x80000000
+sramsize    = 0x00008000
+mbar        = 0xFC000000
+busfreq     =     80 MHz
+flbfreq     =     80 Mhz
+inpfreq     =     16 Mhz
+vcofreq     =    480 Mhz
+
+baudrate    = 115200 bps
+->
+-> help
+?       - alias for 'help'
+base    - print or set address offset
+bdinfo  - print Board Info structure
+boot    - boot default, i.e., run 'bootcmd'
+bootd   - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm   - boot application image from memory
+bootp	- boot image via network using BootP/TFTP protocol
+bootvx  - Boot vxWorks from an ELF image
+cmp     - memory compare
+coninfo - print console devices and information
+cp      - memory copy
+crc32   - checksum calculation
+date    - get/set/reset date & time
+dcache  - enable or disable data cache
+echo    - echo args to console
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+go      - start application at address 'addr'
+help    - print online help
+i2c     - I2C sub-system
+icache  - enable or disable instruction cache
+iminfo  - print header information for application image
+imls    - list all images found in flash
+itest	- return true/false on integer compare
+loadb   - load binary file over serial line (kermit mode)
+loads   - load S-Record file over serial line
+loady   - load binary file over serial line (ymodem mode)
+loop    - infinite loop on address range
+ls	- list files in a directory (default /)
+md      - memory display
+mm      - memory modify (auto-incrementing)
+mtest   - simple RAM test
+mw      - memory write (fill)
+nm      - memory modify (constant address)
+ping	- send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+sleep   - delay execution for some time
+source  - run script from memory
+version - print monitor version
+->
diff --git a/roms/u-boot/board/freescale/m52277evb/m52277evb.c b/roms/u-boot/board/freescale/m52277evb/m52277evb.c
new file mode 100644
index 000000000..510af33e4
--- /dev/null
+++ b/roms/u-boot/board/freescale/m52277evb/m52277evb.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M52277 EVB\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	u32 dramsize;
+
+#ifdef CONFIG_CF_SBF
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
+	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+	u32 i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
+
+	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
+
+	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
+
+	/* Issue PALL */
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
+	__asm__("nop");
+
+	/* Issue LEMR */
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
+	__asm__("nop");
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD);
+	__asm__("nop");
+
+	udelay(1000);
+
+	/* Issue PALL */
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
+	__asm__("nop");
+
+	/* Perform two refresh cycles */
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+	__asm__("nop");
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+	__asm__("nop");
+
+	out_be32(&sdram->sdcr,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+
+	udelay(100);
+#endif
+	gd->ram_size = dramsize;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/roms/u-boot/board/freescale/m5235evb/Kconfig b/roms/u-boot/board/freescale/m5235evb/Kconfig
new file mode 100644
index 000000000..fc8341999
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5235evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5235EVB
+
+config SYS_CPU
+	default "mcf523x"
+
+config SYS_BOARD
+	default "m5235evb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M5235EVB"
+
+endif
diff --git a/roms/u-boot/board/freescale/m5235evb/MAINTAINERS b/roms/u-boot/board/freescale/m5235evb/MAINTAINERS
new file mode 100644
index 000000000..b15ac5f14
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5235evb/MAINTAINERS
@@ -0,0 +1,7 @@
+M5235EVB BOARD
+M:	TsiChung Liew <Tsi-Chung.Liew@nxp.com>
+S:	Maintained
+F:	board/freescale/m5235evb/
+F:	include/configs/M5235EVB.h
+F:	configs/M5235EVB_defconfig
+F:	configs/M5235EVB_Flash32_defconfig
diff --git a/roms/u-boot/board/freescale/m5235evb/Makefile b/roms/u-boot/board/freescale/m5235evb/Makefile
new file mode 100644
index 000000000..b7067e458
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5235evb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m5235evb.o
diff --git a/roms/u-boot/board/freescale/m5235evb/m5235evb.c b/roms/u-boot/board/freescale/m5235evb/m5235evb.c
new file mode 100644
index 000000000..e7c7a9403
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5235evb/m5235evb.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M5235 EVB\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+	u32 dramsize, i, dramclk;
+
+	/*
+	 * When booting from external Flash, the port-size is less than
+	 * the port-size of SDRAM.  In this case it is necessary to enable
+	 * Data[15:0] on Port Address/Data.
+	 */
+	out_8(&gpio->par_ad,
+		GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
+		GPIO_PAR_AD_DATAL);
+
+	/* Initialize PAR to enable SDRAM signals */
+	out_8(&gpio->par_sdram,
+		GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
+		GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
+		GPIO_PAR_SDRAM_SDCS(3));
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
+		dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
+
+		/* Initialize DRAM Control Register: DCR */
+		out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
+			SDRAMC_DCR_RTIM_6CLKS |
+			SDRAMC_DCR_RC((15 * dramclk) >> 4));
+
+		/* Initialize DACR0 */
+		out_be32(&sdram->dacr0,
+			SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
+			SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
+			SDRAMC_DARCn_PS_32);
+		asm("nop");
+
+		/* Initialize DMR0 */
+		out_be32(&sdram->dmr0,
+			((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
+		asm("nop");
+
+		/* Set IP (bit 3) in DACR */
+		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
+
+		/* Wait 30ns to allow banks to precharge */
+		for (i = 0; i < 5; i++) {
+			asm("nop");
+		}
+
+		/* Write to this block to initiate precharge */
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+
+		/*  Set RE (bit 15) in DACR */
+		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
+
+		/* Wait for at least 8 auto refresh cycles to occur */
+		for (i = 0; i < 0x2000; i++) {
+			asm("nop");
+		}
+
+		/* Finish the configuration by issuing the MRS. */
+		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
+		asm("nop");
+
+		/* Write to the SDRAM Mode Register */
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+	}
+
+	gd->ram_size = dramsize;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/roms/u-boot/board/freescale/m5249evb/Kconfig b/roms/u-boot/board/freescale/m5249evb/Kconfig
new file mode 100644
index 000000000..0f624776b
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5249evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5249EVB
+
+config SYS_CPU
+	default "mcf52x2"
+
+config SYS_BOARD
+	default "m5249evb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M5249EVB"
+
+endif
diff --git a/roms/u-boot/board/freescale/m5249evb/MAINTAINERS b/roms/u-boot/board/freescale/m5249evb/MAINTAINERS
new file mode 100644
index 000000000..c2273c35e
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5249evb/MAINTAINERS
@@ -0,0 +1,6 @@
+M5249EVB BOARD
+#M:	-
+S:	Maintained
+F:	board/freescale/m5249evb/
+F:	include/configs/M5249EVB.h
+F:	configs/M5249EVB_defconfig
diff --git a/roms/u-boot/board/freescale/m5249evb/Makefile b/roms/u-boot/board/freescale/m5249evb/Makefile
new file mode 100644
index 000000000..497bc7229
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5249evb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m5249evb.o
diff --git a/roms/u-boot/board/freescale/m5249evb/m5249evb.c b/roms/u-boot/board/freescale/m5249evb/m5249evb.c
new file mode 100644
index 000000000..48c007911
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5249evb/m5249evb.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard (void) {
+	ulong val;
+	uchar val8;
+
+	puts ("Board: ");
+	puts("Freescale M5249EVB");
+	val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
+	printf(" (Switch=%1X)\n", val8);
+
+	/*
+	 * Set LED on
+	 */
+	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
+	mbar2_writeLong(MCFSIM_GPIO1_OUT, val);   /* Set LED on */
+
+	return 0;
+};
+
+
+int dram_init(void)
+{
+	unsigned long	junk = 0xa5a59696;
+
+	/*
+	 *  Note:
+	 *	RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
+	 */
+
+#ifdef CONFIG_SYS_FAST_CLK
+	/*
+	 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8239);
+#elif CONFIG_SYS_PLL_BYPASS
+	/*
+	 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8202);
+#else
+	/*
+	 * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8222);
+#endif
+
+	/*
+	 * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
+	 * PM=1 (continuous page mode)
+	 */
+
+	/* RE=0 (keep auto-refresh disabled while setting up registers) */
+	mbar_writeLong(MCFSIM_DACR0, 0x00003324);
+
+	/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
+	mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
+
+	/** Precharge sequence **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
+	*((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
+	udelay(0x10); /* Allow several Precharge cycles */
+
+	/** Refresh Sequence **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
+	udelay(0x7d0); /* Allow gobs of refresh cycles */
+
+	/** Mode Register initialization **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
+	*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
+};
+
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/roms/u-boot/board/freescale/m5253demo/Kconfig b/roms/u-boot/board/freescale/m5253demo/Kconfig
new file mode 100644
index 000000000..303d29bc2
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5253demo/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5253DEMO
+
+config SYS_CPU
+	default "mcf52x2"
+
+config SYS_BOARD
+	default "m5253demo"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M5253DEMO"
+
+endif
diff --git a/roms/u-boot/board/freescale/m5253demo/MAINTAINERS b/roms/u-boot/board/freescale/m5253demo/MAINTAINERS
new file mode 100644
index 000000000..9b27f4382
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5253demo/MAINTAINERS
@@ -0,0 +1,6 @@
+M5253DEMO BOARD
+M:	TsiChung Liew <Tsi-Chung.Liew@nxp.com>
+S:	Maintained
+F:	board/freescale/m5253demo/
+F:	include/configs/M5253DEMO.h
+F:	configs/M5253DEMO_defconfig
diff --git a/roms/u-boot/board/freescale/m5253demo/Makefile b/roms/u-boot/board/freescale/m5253demo/Makefile
new file mode 100644
index 000000000..00d395d1a
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5253demo/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m5253demo.o flash.o
diff --git a/roms/u-boot/board/freescale/m5253demo/flash.c b/roms/u-boot/board/freescale/m5253demo/flash.c
new file mode 100644
index 000000000..319742178
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5253demo/flash.c
@@ -0,0 +1,453 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <flash.h>
+#include <init.h>
+#include <irq_func.h>
+
+#include <asm/immap.h>
+
+#ifndef CONFIG_SYS_FLASH_CFI
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FPW             FLASH_PORT_WIDTH
+#define FPWV            FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1    0x5555
+#define FLASH_CYCLE2    0x2aaa
+
+#define SYNC			__asm__("nop")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info);
+int flash_get_offsets(ulong base, flash_info_t * info);
+int write_word(flash_info_t * info, FPWV * dest, u16 data);
+static inline void spin_wheel(void);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+ulong flash_init(void)
+{
+	ulong size = 0;
+	ulong fbase = 0;
+
+	fbase = (ulong) CONFIG_SYS_FLASH_BASE;
+	flash_get_size((FPWV *) fbase, &flash_info[0]);
+	flash_get_offsets((ulong) fbase, &flash_info[0]);
+	fbase += flash_info[0].size;
+	size += flash_info[0].size;
+
+	/* Protect monitor and environment sectors */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	return size;
+}
+
+int flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+
+		info->start[0] = base;
+		info->protect[0] = 0;
+		for (i = 1; i < CONFIG_SYS_SST_SECT; i++) {
+			info->start[i] = info->start[i - 1]
+						+ CONFIG_SYS_SST_SECTSZ;
+			info->protect[i] = 0;
+		}
+	}
+
+	return ERR_OK;
+}
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_SST6401B:
+		printf("SST39VF6401B\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		return;
+	}
+
+	if (info->size > 0x100000) {
+		int remainder;
+
+		printf("  Size: %ld", info->size >> 20);
+
+		remainder = (info->size % 0x100000);
+		if (remainder) {
+			remainder >>= 10;
+			remainder = (int)((float)
+					  (((float)remainder / (float)1024) *
+					   10000));
+			printf(".%d ", remainder);
+		}
+
+		printf("MB in %d Sectors\n", info->sector_count);
+	} else
+		printf("  Size: %ld KB in %d Sectors\n",
+		       info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size(FPWV * addr, flash_info_t * info)
+{
+	u16 value;
+
+	addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA;	/* for Atmel, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPWV) 0x00550055;	/* for Atmel, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPWV) 0x00900090;	/* selects Intel or Atmel */
+
+	switch (addr[0] & 0xffff) {
+	case (u8) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		value = addr[1];
+		break;
+	default:
+		printf("Unknown Flash\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+
+		*addr = (FPW) 0x00F000F0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	switch (value) {
+	case (u16) SST_ID_xF6401B:
+		info->flash_id += FLASH_SST6401B;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	info->sector_count = 0;
+	info->size = 0;
+	info->sector_count = CONFIG_SYS_SST_SECT;
+	info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ;
+
+	/* reset ID mode */
+	*addr = (FPWV) 0x00F000F0;
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf("** ERROR: sector count %d > max (%d) **\n",
+		       info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	return (info->size);
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect, count;
+	ulong type, start;
+	int rcode = 0, flashtype = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+
+	switch (type) {
+	case FLASH_MAN_SST:
+		flashtype = 1;
+		break;
+	default:
+		type = (info->flash_id & FLASH_VENDMASK);
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	else
+		printf("\n");
+
+	flag = disable_interrupts();
+
+	start = get_timer(0);
+
+	if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) {
+		if (prot == 0) {
+			addr = (FPWV *) info->start[0];
+
+			addr[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+			addr[FLASH_CYCLE2] = 0x0055;	/* unlock */
+			addr[FLASH_CYCLE1] = 0x0080;	/* erase mode */
+			addr[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+			addr[FLASH_CYCLE2] = 0x0055;	/* unlock */
+			*addr = 0x0030;	/* erase chip */
+
+			count = 0;
+			start = get_timer(0);
+
+			while ((*addr & 0x0080) != 0x0080) {
+				if (count++ > 0x10000) {
+					spin_wheel();
+					count = 0;
+				}
+
+				if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf("Timeout\n");
+					*addr = 0x00F0;	/* reset to read mode */
+
+					return 1;
+				}
+			}
+
+			*addr = 0x00F0;	/* reset to read mode */
+
+			printf("\b. done\n");
+
+			if (flag)
+				enable_interrupts();
+
+			return 0;
+		} else if (prot == CONFIG_SYS_SST_SECT) {
+			return 1;
+		}
+	}
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+
+			addr = (FPWV *) (info->start[sect]);
+
+			printf(".");
+
+			/* arm simple, non interrupt dependent timer */
+			start = get_timer(0);
+
+			switch (flashtype) {
+			case 1:
+				{
+					FPWV *base;	/* first address in bank */
+
+					flag = disable_interrupts();
+
+					base = (FPWV *) (CONFIG_SYS_FLASH_BASE);	/* First sector */
+
+					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+					base[FLASH_CYCLE2] = 0x0055;	/* unlock */
+					base[FLASH_CYCLE1] = 0x0080;	/* erase mode */
+					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+					base[FLASH_CYCLE2] = 0x0055;	/* unlock */
+					*addr = 0x0050;	/* erase sector */
+
+					if (flag)
+						enable_interrupts();
+
+					while ((*addr & 0x0080) != 0x0080) {
+						if (get_timer(start) >
+						    CONFIG_SYS_FLASH_ERASE_TOUT) {
+							printf("Timeout\n");
+							*addr = 0x00F0;	/* reset to read mode */
+
+							rcode = 1;
+							break;
+						}
+					}
+
+					*addr = 0x00F0;	/* reset to read mode */
+					break;
+				}
+			}	/* switch (flashtype) */
+		}
+	}
+	printf(" done\n");
+
+	if (flag)
+		enable_interrupts();
+
+	return rcode;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, count;
+	u16 data;
+	int rc;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	/* get lower word aligned address */
+	wp = addr;
+
+	/* handle unaligned start bytes */
+	if (wp & 1) {
+		data = *((FPWV *) wp);
+		data = (data << 8) | *src;
+
+		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+			return (rc);
+
+		wp++;
+		cnt -= 1;
+		src++;
+	}
+
+	while (cnt >= 2) {
+		/*
+		 * handle word aligned part
+		 */
+		count = 0;
+		data = *((FPWV *) src);
+
+		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+			return (rc);
+
+		wp += 2;
+		src += 2;
+		cnt -= 2;
+
+		if (count++ > 0x800) {
+			spin_wheel();
+			count = 0;
+		}
+	}
+	/* handle word aligned part */
+	if (cnt) {
+		/* handle word aligned part */
+		count = 0;
+		data = *((FPWV *) wp);
+
+		data = (data & 0x00FF) | (*src << 8);
+
+		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+			return (rc);
+
+		wp++;
+		src++;
+		cnt -= 1;
+		if (count++ > 0x800) {
+			spin_wheel();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0)
+		return ERR_OK;
+
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash
+ * A word is 16 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_word(flash_info_t * info, FPWV * dest, u16 data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success */
+	FPWV *base;		/* first address in flash bank */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & (u8) data) != (u8) data) {
+		return (2);
+	}
+
+	base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (u8) 0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (u8) 0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (u8) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (u8) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	*dest++ = (u8) 0x00F000F0;	/* reset bank */
+
+	return (res);
+}
+
+static inline void spin_wheel(void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+#endif
diff --git a/roms/u-boot/board/freescale/m5253demo/m5253demo.c b/roms/u-boot/board/freescale/m5253demo/m5253demo.c
new file mode 100644
index 000000000..2a4703579
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5253demo/m5253demo.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale MCF5253 DEMO\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	u32 dramsize = 0;
+
+	/*
+	 * Check to see if the SDRAM has already been initialized
+	 * by a run control tool
+	 */
+	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
+		u32 RC, temp;
+
+		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
+		RC = (RC * 15) >> 4;
+
+		/* Initialize DRAM Control Register: DCR */
+		mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
+		__asm__("nop");
+
+		mbar_writeLong(MCFSIM_DACR0, 0x00003224);
+		__asm__("nop");
+
+		/* Initialize DMR0 */
+		dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
+		temp = (dramsize - 1) & 0xFFFC0000;
+		mbar_writeLong(MCFSIM_DMR0, temp | 1);
+		__asm__("nop");
+
+		mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
+		mb();
+		__asm__("nop");
+
+		/* Write to this block to initiate precharge */
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+		mb();
+		__asm__("nop");
+
+		/* Set RE bit in DACR */
+		mbar_writeLong(MCFSIM_DACR0,
+			       mbar_readLong(MCFSIM_DACR0) | 0x8000);
+		__asm__("nop");
+
+		/* Wait for at least 8 auto refresh cycles to occur */
+		udelay(500);
+
+		/* Finish the configuration by issuing the MRS */
+		mbar_writeLong(MCFSIM_DACR0,
+			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
+		__asm__("nop");
+
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+		mb();
+	}
+
+	gd->ram_size = dramsize;
+
+	return 0;
+}
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#ifdef CONFIG_IDE
+#include <ata.h>
+int ide_preinit(void)
+{
+	return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+	atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+	long period;
+	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
+	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
+	{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
+	{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
+	{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
+	{25, 70, 20, 10, 20, 5, 10, 0, 35}	/* PIO 4 */
+	};
+
+	if (idereset) {
+		/* control reset */
+		out_8(&ata->cr, 0);
+		udelay(100);
+	} else {
+		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
+
+#define CALC_TIMING(t) (t + period - 1) / period
+		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
+
+		/*ata->ton = CALC_TIMING (180); */
+		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+		/* IORDY enable */
+		out_8(&ata->cr, 0x40);
+		udelay(2000);
+		/* IORDY enable */
+		setbits_8(&ata->cr, 0x01);
+	}
+}
+#endif				/* CONFIG_IDE */
+
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(struct bd_info *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
diff --git a/roms/u-boot/board/freescale/m5272c3/Kconfig b/roms/u-boot/board/freescale/m5272c3/Kconfig
new file mode 100644
index 000000000..aee0b239b
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5272c3/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5272C3
+
+config SYS_CPU
+	default "mcf52x2"
+
+config SYS_BOARD
+	default "m5272c3"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M5272C3"
+
+endif
diff --git a/roms/u-boot/board/freescale/m5272c3/MAINTAINERS b/roms/u-boot/board/freescale/m5272c3/MAINTAINERS
new file mode 100644
index 000000000..e58663096
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5272c3/MAINTAINERS
@@ -0,0 +1,6 @@
+M5272C3 BOARD
+#M:	-
+S:	Maintained
+F:	board/freescale/m5272c3/
+F:	include/configs/M5272C3.h
+F:	configs/M5272C3_defconfig
diff --git a/roms/u-boot/board/freescale/m5272c3/Makefile b/roms/u-boot/board/freescale/m5272c3/Makefile
new file mode 100644
index 000000000..1df8f7003
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5272c3/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m5272c3.o
diff --git a/roms/u-boot/board/freescale/m5272c3/m5272c3.c b/roms/u-boot/board/freescale/m5272c3/m5272c3.c
new file mode 100644
index 000000000..9580cf2a0
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5272c3/m5272c3.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard (void) {
+	puts ("Board: ");
+	puts ("Freescale MCF5272C3 EVB\n");
+	return 0;
+	};
+
+int dram_init(void)
+{
+	sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
+
+	out_be16(&sdp->sdram_sdtr, 0xf539);
+	out_be16(&sdp->sdram_sdcr, 0x4211);
+
+	/* Dummy write to start SDRAM */
+	*((volatile unsigned long *)0) = 0;
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
+	};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/roms/u-boot/board/freescale/m5275evb/Kconfig b/roms/u-boot/board/freescale/m5275evb/Kconfig
new file mode 100644
index 000000000..5a6de9c1c
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5275evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5275EVB
+
+config SYS_CPU
+	default "mcf52x2"
+
+config SYS_BOARD
+	default "m5275evb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M5275EVB"
+
+endif
diff --git a/roms/u-boot/board/freescale/m5275evb/MAINTAINERS b/roms/u-boot/board/freescale/m5275evb/MAINTAINERS
new file mode 100644
index 000000000..4e6dbb12d
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5275evb/MAINTAINERS
@@ -0,0 +1,6 @@
+M5275EVB BOARD
+#M:	-
+S:	Maintained
+F:	board/freescale/m5275evb/
+F:	include/configs/M5275EVB.h
+F:	configs/M5275EVB_defconfig
diff --git a/roms/u-boot/board/freescale/m5275evb/Makefile b/roms/u-boot/board/freescale/m5275evb/Makefile
new file mode 100644
index 000000000..83e3b10f0
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5275evb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m5275evb.o
diff --git a/roms/u-boot/board/freescale/m5275evb/m5275evb.c b/roms/u-boot/board/freescale/m5275evb/m5275evb.c
new file mode 100644
index 000000000..1c4fb7232
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5275evb/m5275evb.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PERIOD		13	/* system bus period in ns */
+#define SDRAM_TREFI	7800	/* in ns */
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale MCF5275 EVB\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
+	gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+
+	/* Enable SDRAM */
+	out_be16(&gpio_reg->par_sdram, 0x3FF);
+
+	/* Set up chip select */
+	out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
+	out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
+
+	/* Set up timing */
+	out_be32(&sdp->sdcfg1, 0x83711630);
+	out_be32(&sdp->sdcfg2, 0x46770000);
+
+	/* Enable clock */
+	out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
+
+	/* Set precharge */
+	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+
+	/* Dummy write to start SDRAM */
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+	/* Send LEMR */
+	setbits_be32(&sdp->sdmr,
+		MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
+		MCF_SDRAMC_SDMR_CMD);
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+	/* Send LMR */
+	out_be32(&sdp->sdmr, 0x058d0000);
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+	/* Stop sending commands */
+	clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
+
+	/* Set precharge */
+	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+	/* Stop manual precharge, send 2 IREF */
+	clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+
+	out_be32(&sdp->sdmr, 0x018d0000);
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+	/* Stop sending commands */
+	clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
+	clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
+
+	/* Turn on auto refresh, lock SDMR */
+	out_be32(&sdp->sdcr,
+		MCF_SDRAMC_SDCR_CKE
+		| MCF_SDRAMC_SDCR_REF
+		| MCF_SDRAMC_SDCR_MUX(1)
+		/* 1 added to round up */
+		| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
+		| MCF_SDRAMC_SDCR_DQS_OE(0x3));
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/roms/u-boot/board/freescale/m5282evb/Kconfig b/roms/u-boot/board/freescale/m5282evb/Kconfig
new file mode 100644
index 000000000..2ffdd528f
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5282evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5282EVB
+
+config SYS_CPU
+	default "mcf52x2"
+
+config SYS_BOARD
+	default "m5282evb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M5282EVB"
+
+endif
diff --git a/roms/u-boot/board/freescale/m5282evb/MAINTAINERS b/roms/u-boot/board/freescale/m5282evb/MAINTAINERS
new file mode 100644
index 000000000..305e748e7
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5282evb/MAINTAINERS
@@ -0,0 +1,6 @@
+M5282EVB BOARD
+#M:	-
+S:	Maintained
+F:	board/freescale/m5282evb/
+F:	include/configs/M5282EVB.h
+F:	configs/M5282EVB_defconfig
diff --git a/roms/u-boot/board/freescale/m5282evb/Makefile b/roms/u-boot/board/freescale/m5282evb/Makefile
new file mode 100644
index 000000000..e898f3933
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5282evb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m5282evb.o
diff --git a/roms/u-boot/board/freescale/m5282evb/m5282evb.c b/roms/u-boot/board/freescale/m5282evb/m5282evb.c
new file mode 100644
index 000000000..e1ea9b3a5
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5282evb/m5282evb.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard (void)
+{
+	puts ("Board: Freescale M5282EVB Evaluation Board\n");
+	return 0;
+}
+
+int dram_init(void)
+{
+	u32 dramsize, i, dramclk;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
+	{
+		dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
+
+		/* Initialize DRAM Control Register: DCR */
+		MCFSDRAMC_DCR = (0
+			| MCFSDRAMC_DCR_RTIM_6
+			| MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
+		asm("nop");
+
+		/* Initialize DACR0 */
+		MCFSDRAMC_DACR0 = (0
+			| MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
+			| MCFSDRAMC_DACR_CASL(1)
+			| MCFSDRAMC_DACR_CBM(3)
+			| MCFSDRAMC_DACR_PS_32);
+		asm("nop");
+
+		/* Initialize DMR0 */
+		MCFSDRAMC_DMR0 = (0
+			| ((dramsize - 1) & 0xFFFC0000)
+			| MCFSDRAMC_DMR_V);
+		asm("nop");
+
+		/* Set IP (bit 3) in DACR */
+		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
+		asm("nop");
+
+		/* Wait 30ns to allow banks to precharge */
+		for (i = 0; i < 5; i++) {
+			asm ("nop");
+		}
+
+		/* Write to this block to initiate precharge */
+		*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+		asm("nop");
+
+		/* Set RE (bit 15) in DACR */
+		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
+		asm("nop");
+
+		/* Wait for at least 8 auto refresh cycles to occur */
+		for (i = 0; i < 2000; i++) {
+			asm(" nop");
+		}
+
+		/* Finish the configuration by issuing the IMRS. */
+		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
+		asm("nop");
+
+		/* Write to the SDRAM Mode Register */
+		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+	}
+	gd->ram_size = dramsize;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/m53017evb/Kconfig b/roms/u-boot/board/freescale/m53017evb/Kconfig
new file mode 100644
index 000000000..8ab89e52b
--- /dev/null
+++ b/roms/u-boot/board/freescale/m53017evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M53017EVB
+
+config SYS_CPU
+	default "mcf532x"
+
+config SYS_BOARD
+	default "m53017evb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M53017EVB"
+
+endif
diff --git a/roms/u-boot/board/freescale/m53017evb/MAINTAINERS b/roms/u-boot/board/freescale/m53017evb/MAINTAINERS
new file mode 100644
index 000000000..ad5f0cea6
--- /dev/null
+++ b/roms/u-boot/board/freescale/m53017evb/MAINTAINERS
@@ -0,0 +1,6 @@
+M53017EVB BOARD
+M:	TsiChung Liew <Tsi-Chung.Liew@nxp.com>
+S:	Maintained
+F:	board/freescale/m53017evb/
+F:	include/configs/M53017EVB.h
+F:	configs/M53017EVB_defconfig
diff --git a/roms/u-boot/board/freescale/m53017evb/Makefile b/roms/u-boot/board/freescale/m53017evb/Makefile
new file mode 100644
index 000000000..4eeb3a860
--- /dev/null
+++ b/roms/u-boot/board/freescale/m53017evb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m53017evb.o
diff --git a/roms/u-boot/board/freescale/m53017evb/README b/roms/u-boot/board/freescale/m53017evb/README
new file mode 100644
index 000000000..c4b019e2a
--- /dev/null
+++ b/roms/u-boot/board/freescale/m53017evb/README
@@ -0,0 +1,178 @@
+Freescale MCF53017EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 10/22/08
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m53017evb/m53017evb.c	Dram setup
+- board/freescale/m53017evb/mii.c	Mii access
+- board/freescale/m53017evb/Makefile	Makefile
+- board/freescale/m53017evb/config.mk	config make
+- board/freescale/m53017evb/u-boot.lds	Linker description
+
+- arch/m68k/cpu/mcf532x/cpu.c			cpu specific code
+- arch/m68k/cpu/mcf532x/cpu_init.c		FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf532x/interrupts.c		cpu specific interrupt support
+- arch/m68k/cpu/mcf532x/speed.c			system, flexbus, and cpu clock
+- arch/m68k/cpu/mcf532x/Makefile			Makefile
+- arch/m68k/cpu/mcf532x/config.mk			config make
+- arch/m68k/cpu/mcf532x/start.S			start up assembly code
+
+- board/freescale/m53017evb/README	his readme file
+
+- drivers/net/mcffec.c			ColdFire common FEC driver
+- drivers/net/mcfmii.c			ColdFire common Mii driver
+- drivers/serial/mcfuart.c		ColdFire common UART driver
+- drivers/rtc/mcfrtc.c			Realtime clock Driver
+
+- include/asm-m68k/bitops.h		Bit operation function export
+- include/asm-m68k/byteorder.h		Byte order functions
+- include/asm-m68k/fec.h		FEC structure and definition
+- include/asm-m68k/fsl_i2c.h		I2C structure and definition
+- include/asm-m68k/global_data.h	Global data structure
+- include/asm-m68k/immap.h		ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5301x.h	mcf5301x specific header file
+- include/asm-m68k/io.h			io functions
+- include/asm-m68k/m532x.h		mcf5301x specific header file
+- include/asm-m68k/posix_types.h	Posix
+- include/asm-m68k/processor.h		header file
+- include/asm-m68k/ptrace.h		Exception structure
+- include/asm-m68k/rtc.h		Realtime clock header file
+- include/asm-m68k/string.h		String function export
+- include/asm-m68k/timer.h		Timer structure and definition
+- include/asm-m68k/types.h		Data types definition
+- include/asm-m68k/uart.h		Uart structure and definition
+- include/asm-m68k/u-boot.h		U-Boot structure
+
+- include/configs/M53017EVB.h		Board specific configuration file
+
+- arch/m68k/lib/board.c			board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts			Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c			Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c			Exception init code
+
+1 MCF5301x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M53017EVB Development Board
+CONFIG_MCF5301x			-- define for all MCF5301x CPUs
+CONFIG_M53015			-- define for MCF53015 CPUs
+CONFIG_M53017EVB		-- define for M53017EVB board
+
+CONFIG_MCFUART			-- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE			-- define UART baudrate
+
+CONFIG_MCFRTC			-- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE		-- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR	-- define RTC clock frequency
+RTC_DEBUG			-- define to show RTC debug message
+CONFIG_CMD_DATE			-- enable to use date feature in U-Boot
+
+CONFIG_MCFFEC			-- define to use common CF FEC driver
+CONFIG_MII			-- enable to use MII driver
+CONFIG_CF_DOMII			-- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY		-- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER	-- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN	--
+CONFIG_SYS_FEC0_PINMUX		-- Set FEC0 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE		-- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP		-- set FEC timeout loop
+
+CONFIG_MCFTMR			-- define to use DMA timer
+
+CONFIG_SYS_I2C_FSL		-- define to use FSL common I2C driver
+CONFIG_SYS_I2C_SOFT		-- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED		-- define for I2C speed
+CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
+CONFIG_SYS_IMMR			-- define for MBAR offset
+
+CONFIG_SYS_MBAR			-- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM 	-- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF5301x internal SRAM
+
+CONFIG_SYS_CSn_BASE		-- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK		-- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL		-- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE		-- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+	Flash:		0x00000000-0x3FFFFFFF (1024MB)
+	DDR:		0x40000000-0x7FFFFFFF (1024MB)
+	SRAM:		0x80000000-0x8FFFFFFF (256MB)
+	IP:		0xFC000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and
+	linux kernel, you can customize it based on your system requirements:
+	Flash0:		0x00000000-0x00FFFFFF (16MB)
+	DDR:		0x40000000-0x4FFFFFFF (256MB)
+	SRAM:		0x80000000-0x80007FFF (32KB)
+	IP:		0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1	To create U-Boot the gcc-4.x-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+   export CROSS_COMPILE=cross-compile-prefix
+   cd u-boot
+   make distclean
+   make M53017EVB_config
+   make
+
+4. SCREEN DUMP
+==============
+4.1 M53017EVB Development board
+    (NOTE: May not show exactly the same)
+
+U-Boot 2008.10 (Oct 22 2007 - 11:07:57)
+
+CPU:   Freescale MCF53015 (Mask:76 Version:0)
+       CPU CLK 240 Mhz BUS CLK 80 Mhz
+Board: Freescale M53017EVB
+I2C:   ready
+DRAM:  64 MB
+FLASH: 16 MB
+In:    serial
+Out:   serial
+Err:   serial
+NAND:  16 MiB
+Net:   FEC0, FEC1
+-> print
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+hostname=M53017EVB
+netdev=eth0
+loadaddr=40010000
+u-boot=u-boot.bin
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=65024k
+
+Environment size: 437/4092 bytes
+->
diff --git a/roms/u-boot/board/freescale/m53017evb/m53017evb.c b/roms/u-boot/board/freescale/m53017evb/m53017evb.c
new file mode 100644
index 000000000..c9f89353c
--- /dev/null
+++ b/roms/u-boot/board/freescale/m53017evb/m53017evb.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M53017EVB\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
+#endif
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+	udelay(500);
+
+	/* Issue PALL */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+	asm("nop");
+
+	/* Perform two refresh cycles */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	asm("nop");
+
+	/* Issue LEMR */
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+	asm("nop");
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	asm("nop");
+
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+	asm("nop");
+
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+	asm("nop");
+
+	udelay(100);
+
+	gd->ram_size = dramsize;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/roms/u-boot/board/freescale/m5329evb/Kconfig b/roms/u-boot/board/freescale/m5329evb/Kconfig
new file mode 100644
index 000000000..930fbba24
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5329evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5329EVB
+
+config SYS_CPU
+	default "mcf532x"
+
+config SYS_BOARD
+	default "m5329evb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M5329EVB"
+
+endif
diff --git a/roms/u-boot/board/freescale/m5329evb/MAINTAINERS b/roms/u-boot/board/freescale/m5329evb/MAINTAINERS
new file mode 100644
index 000000000..2f7dd2d45
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5329evb/MAINTAINERS
@@ -0,0 +1,7 @@
+M5329EVB BOARD
+M:	TsiChung Liew <Tsi-Chung.Liew@nxp.com>
+S:	Maintained
+F:	board/freescale/m5329evb/
+F:	include/configs/M5329EVB.h
+F:	configs/M5329AFEE_defconfig
+F:	configs/M5329BFEE_defconfig
diff --git a/roms/u-boot/board/freescale/m5329evb/Makefile b/roms/u-boot/board/freescale/m5329evb/Makefile
new file mode 100644
index 000000000..19796c213
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5329evb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m5329evb.o nand.o
diff --git a/roms/u-boot/board/freescale/m5329evb/m5329evb.c b/roms/u-boot/board/freescale/m5329evb/m5329evb.c
new file mode 100644
index 000000000..7a75b04dd
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5329evb/m5329evb.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5329 EVB\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+	/* Issue PALL */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Issue LEMR */
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+
+	udelay(100);
+
+	gd->ram_size = dramsize;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/roms/u-boot/board/freescale/m5329evb/nand.c b/roms/u-boot/board/freescale/m5329evb/nand.c
new file mode 100644
index 000000000..58b8ee51d
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5329evb/nand.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+#define SET_CLE		0x10
+#define SET_ALE		0x08
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
+	volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+		IO_ADDR_W &= ~(SET_ALE | SET_CLE);
+
+		if (ctrl & NAND_NCE)
+			*nCE &= 0xFFFB;
+		else
+			*nCE |= 0x0004;
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= SET_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= SET_ALE;
+
+		this->IO_ADDR_W = (void *)IO_ADDR_W;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/*
+	 * set up pin configuration - enabled 2nd output buffer's signals
+	 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+	 * to use nCE signal
+	 */
+	clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+	setbits_8(&gpio->pddr_timer, 0x08);
+	setbits_8(&gpio->ppd_timer, 0x08);
+	out_8(&gpio->pclrr_timer, 0);
+	out_8(&gpio->podr_timer, 0);
+
+	nand->chip_delay = 60;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = nand_hwcontrol;
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/m5373evb/Kconfig b/roms/u-boot/board/freescale/m5373evb/Kconfig
new file mode 100644
index 000000000..67d049d79
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5373evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5373EVB
+
+config SYS_CPU
+	default "mcf532x"
+
+config SYS_BOARD
+	default "m5373evb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M5373EVB"
+
+endif
diff --git a/roms/u-boot/board/freescale/m5373evb/MAINTAINERS b/roms/u-boot/board/freescale/m5373evb/MAINTAINERS
new file mode 100644
index 000000000..acb7a43ed
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5373evb/MAINTAINERS
@@ -0,0 +1,6 @@
+M5373EVB BOARD
+M:	TsiChung Liew <Tsi-Chung.Liew@nxp.com>
+S:	Maintained
+F:	board/freescale/m5373evb/
+F:	include/configs/M5373EVB.h
+F:	configs/M5373EVB_defconfig
diff --git a/roms/u-boot/board/freescale/m5373evb/Makefile b/roms/u-boot/board/freescale/m5373evb/Makefile
new file mode 100644
index 000000000..20efa7b84
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5373evb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m5373evb.o nand.o
diff --git a/roms/u-boot/board/freescale/m5373evb/README b/roms/u-boot/board/freescale/m5373evb/README
new file mode 100644
index 000000000..bba542021
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5373evb/README
@@ -0,0 +1,324 @@
+Freescale MCF5373EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 11/08/07
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m5373evb/m5373evb.c	Dram setup
+- board/freescale/m5373evb/mii.c	Mii access
+- board/freescale/m5373evb/Makefile	Makefile
+- board/freescale/m5373evb/config.mk	config make
+- board/freescale/m5373evb/u-boot.lds	Linker description
+
+- arch/m68k/cpu/mcf532x/cpu.c		cpu specific code
+- arch/m68k/cpu/mcf532x/cpu_init.c	FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf532x/interrupts.c	cpu specific interrupt support
+- arch/m68k/cpu/mcf532x/speed.c		system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf532x/Makefile		Makefile
+- arch/m68k/cpu/mcf532x/config.mk		config make
+- arch/m68k/cpu/mcf532x/start.S		start up assembly code
+
+- board/freescale/m5373evb/README	This readme file
+
+- drivers/net/mcffec.c		ColdFire common FEC driver
+- drivers/serial/mcfuart.c	ColdFire common UART driver
+- drivers/rtc/mcfrtc.c		Realtime clock Driver
+
+- include/asm-m68k/bitops.h		Bit operation function export
+- include/asm-m68k/byteorder.h		Byte order functions
+- include/asm-m68k/fec.h		FEC structure and definition
+- include/asm-m68k/fsl_i2c.h		I2C structure and definition
+- include/asm-m68k/global_data.h	Global data structure
+- include/asm-m68k/immap.h		ColdFire specific header file and driver macros
+- include/asm-m68k/immap_532x.h		mcf532x specific header file
+- include/asm-m68k/io.h			io functions
+- include/asm-m68k/m532x.h		mcf532x specific header file
+- include/asm-m68k/posix_types.h	Posix
+- include/asm-m68k/processor.h		header file
+- include/asm-m68k/ptrace.h		Exception structure
+- include/asm-m68k/rtc.h		Realtime clock header file
+- include/asm-m68k/string.h		String function export
+- include/asm-m68k/timer.h		Timer structure and definition
+- include/asm-m68k/types.h		Data types definition
+- include/asm-m68k/uart.h		Uart structure and definition
+- include/asm-m68k/u-boot.h		U-Boot structure
+
+- include/configs/M5373EVB.h		Board specific configuration file
+
+- arch/m68k/lib/board.c			board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts			Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c			Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c			Exception init code
+
+1 MCF5373 specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M5373EVB Development Board
+CONFIG_MCF532x		-- define for all MCF532x CPUs
+CONFIG_M5373		-- define for all Freescale MCF5373 CPUs
+CONFIG_M5373EVB		-- define for M5373EVB board
+
+CONFIG_MCFUART		-- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE		-- define UART baudrate
+
+CONFIG_MCFRTC		-- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE		-- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR	-- define RTC clock frequency
+RTC_DEBUG		-- define to show RTC debug message
+CONFIG_CMD_DATE		-- enable to use date feature in U-Boot
+
+CONFIG_MCFFEC		-- define to use common CF FEC driver
+CONFIG_MII		-- enable to use MII driver
+CONFIG_CF_DOMII		-- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY	-- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER	-- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
+CONFIG_SYS_FEC0_PINMUX		-- Set FEC0 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE	-- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP	-- set FEC timeout loop
+
+CONFIG_MCFTMR		-- define to use DMA timer
+
+CONFIG_SYS_I2C_FSL	-- define to use FSL common I2C driver
+CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED		-- define for I2C speed
+CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
+CONFIG_SYS_IMMR		-- define for MBAR offset
+
+CONFIG_SYS_MBAR		-- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF5373 internal SRAM
+
+CONFIG_SYS_CSn_BASE	-- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK	-- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL	-- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE	-- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+	Flash:		0x00000000-0x3FFFFFFF (1024MB)
+	DDR:		0x40000000-0x7FFFFFFF (1024MB)
+	SRAM:		0x80000000-0x8FFFFFFF (256MB)
+	IP:		0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and
+	linux kernel, you can customize it based on your system requirements:
+	Flash0:		0x00000000-0x00FFFFFF (16MB)
+
+	DDR:		0x40000000-0x4FFFFFFF (256MB)
+	SRAM:		0x80000000-0x80007FFF (32KB)
+	IP:		0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1	To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+   export CROSS_COMPILE=cross-compile-prefix
+   cd u-boot-1.x.x
+   make distclean
+   make M5373EVB_config
+   make
+
+4. SCREEN DUMP
+==============
+4.1 M5373EVB Development board
+    (NOTE: May not show exactly the same)
+
+U-Boot 1.3.0 (Nov 8 2007 - 12:44:08)
+
+CPU:   Freescale MCF5373 (Mask:65 Version:1)
+       CPU CLK 240 Mhz BUS CLK 80 Mhz
+Board: Freescale FireEngine 5373 EVB
+I2C:   ready
+DRAM:  32 MB
+FLASH: 2 MB
+In:    serial
+Out:   serial
+Err:   serial
+NAND:  16 MiB
+Net:   FEC0
+-> print
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+hostname=M5373EVB
+netdev=eth0
+loadaddr=40010000
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
+ethact=FEC0
+u-boot=u-boot.bin
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=261632k
+
+Environment size: 401/8188 bytes
+-> bdinfo
+memstart    = 0x40000000
+memsize     = 0x02000000
+flashstart  = 0x00000000
+flashsize   = 0x00200000
+flashoffset = 0x00000000
+sramstart   = 0x80000000
+sramsize    = 0x00008000
+mbar	    = 0xFC000000
+busfreq     =	  80 MHz
+ethaddr     = 00:E0:0C:BC:E5:60
+ip_addr     = 192.168.1.3
+baudrate    = 115200 bps
+->
+-> help
+?	- alias for 'help'
+base	- print or set address offset
+bdinfo	- print Board Info structure
+boot	- boot default, i.e., run 'bootcmd'
+bootd	- boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm	- boot application image from memory
+bootp	- boot image via network using BootP/TFTP protocol
+bootvx	- Boot vxWorks from an ELF image
+cmp	- memory compare
+coninfo - print console devices and information
+cp	- memory copy
+crc32	- checksum calculation
+date	- get/set/reset date & time
+dcache	- enable or disable data cache
+echo	- echo args to console
+erase	- erase FLASH memory
+flinfo	- print FLASH memory information
+go	- start application at address 'addr'
+help	- print online help
+i2c	- I2C sub-system
+icache	- enable or disable instruction cache
+iminfo	- print header information for application image
+imls	- list all images found in flash
+itest	- return true/false on integer compare
+loadb	- load binary file over serial line (kermit mode)
+loads	- load S-Record file over serial line
+loady	- load binary file over serial line (ymodem mode)
+loop	- infinite loop on address range
+ls	- list files in a directory (default /)
+md	- memory display
+mii	- MII utility commands
+mm	- memory modify (auto-incrementing)
+mtest	- simple RAM test
+mw	- memory write (fill)
+nand	- NAND sub-system
+nboot	- boot from NAND device
+nfs	- boot image via network using NFS protocol
+nm	- memory modify (constant address)
+ping	- send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset	- Perform RESET of the CPU
+run	- run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv	- set environment variables
+sleep	- delay execution for some time
+source	- run script from memory
+tftpboot- boot image via network using TFTP protocol
+version - print monitor version
+-> tftp 0x40800000 uImage
+Using FEC0 device
+TFTP from server 192.168.1.3; our IP address is 192.168.1.3 Filename 'uImage'.
+Load address: 0x40800000
+Loading: #################################################################
+	  #################################################################
+	  ##########
+done
+Bytes transferred = 2053270 (1f5496 hex)
+-> bootm 0x40800000
+## Booting image at 40800000 ...
+    Image Name:   Linux Kernel Image
+    Created:	  2007-11-07  20:33:08 UTC
+    Image Type:   M68K Linux Kernel Image (gzip compressed)
+    Data Size:	  2053206 Bytes =  2 MB
+    Load Address: 40020000
+    Entry Point:  40020000
+    Verifying Checksum ... OK
+    Uncompressing Kernel Image ... OK
+Linux version 2.6.22-uc1 (mattw@loa) (gcc version 4.2.1 (Sourcery G++ Lite 4.2-7
+
+
+uClinux/COLDFIRE(m537x)
+COLDFIRE port done by Greg Ungerer, gerg@snapgear.com Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne Built 1 zonelists.  Total pages: 8128 Kernel command line: rootfstype=romfs PID hash table entries: 128 (order: 7, 512 bytes) Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory available: 28092k/32768k RAM, (1788k kernel code, 244k data) Mount-cache hash table entries: 512
+NET: Registered protocol family 16
+USB-MCF537x: (HOST module) EHCI device is registered
+USB-MCF537x: (OTG module) EHCI device is registered
+USB-MCF537x: (OTG module) UDC device is registered
+usbcore: registered new interface driver usbfs
+usbcore: registered new interface driver hub
+usbcore: registered new device driver usb
+NET: Registered protocol family 2
+IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
+TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered
+JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
+io scheduler noop registered
+io scheduler cfq registered (default)
+ColdFire internal UART serial driver version 1.00 ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
+ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
+ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+loop: module loaded
+nbd: registered device at major 43
+usbcore: registered new interface driver ub FEC ENET Version 0.2
+fec: PHY @ 0x1, ID 0x20005c90 -- DP83848
+eth0: ethernet 00:e0:0c:bc:e5:60
+uclinux[mtd]: RAM probe address=0x4021c22c size=0x22b000 Creating 1 MTD partitions on "RAM":
+0x00000000-0x0022b000 : "ROMfs"
+uclinux[mtd]: set ROMfs to be root filesystem NAND device: Manufacturer ID: 0x20, Chip ID: 0x73 (ST Micro NAND 16MiB 3,3V 8-b) Scanning device for bad blocks Creating 1 MTD partitions on "NAND 16MiB 3,3V 8-bit":
+0x00000000-0x01000000 : "M53xx flash partition 1"
+QSPI: spi->max_speed_hz 300000
+QSPI: Baud set to 255
+SPI: Coldfire master initialized
+M537x - Disable UART1 when using Audio
+udc: Freescale MCF53xx UDC driver version 27 October 2006 init
+udc: MCF53xx USB Device is found. ID=0x5 Rev=0x41 i2c /dev entries driver
+usbcore: registered new interface driver usbhid
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 17
+VFS: Mounted root (romfs filesystem) readonly.
+Freeing unused kernel memory: 64k freed (0x401f5000 - 0x40204000) init started:  BusyBox v1.00 (2007.11.07-19:57+0000) multi-call binary?Setting e Mounting filesystems
+mount: Mounting devpts on /dev/pts failed: No such device
+mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory Starting syslogd and klogd Setting up networking on loopback device:
+Setting up networking on eth0:
+info, udhcpc (v0.9.9-pre) started
+eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
+debug, Sending discover...
+debug, Sending discover...
+debug, Sending select for 172.27.0.130...
+info, Lease of 172.27.0.130 obtained, lease time 43200 deleting routers
+route: SIOC[ADD|DEL]RT: No such process
+adding dns 172.27.0.1
+Starting the boa webserver:
+Setting time from ntp server: ntp.cs.strath.ac.uk
+ntp.cs.strath.ac.uk: Unknown host
+
+
+BusyBox v1.00 (2007.11.07-19:57+0000) Built-in shell (msh) Enter 'help' for a list of built-in commands.
+
+#
diff --git a/roms/u-boot/board/freescale/m5373evb/m5373evb.c b/roms/u-boot/board/freescale/m5373evb/m5373evb.c
new file mode 100644
index 000000000..cfa5ca4a4
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5373evb/m5373evb.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5373 EVB\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+	/* Issue PALL */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Issue LEMR */
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+
+	udelay(100);
+
+	gd->ram_size = dramsize;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/roms/u-boot/board/freescale/m5373evb/nand.c b/roms/u-boot/board/freescale/m5373evb/nand.c
new file mode 100644
index 000000000..4c30d5100
--- /dev/null
+++ b/roms/u-boot/board/freescale/m5373evb/nand.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+#define SET_CLE		0x10
+#define SET_ALE		0x08
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
+	volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+		IO_ADDR_W &= ~(SET_ALE | SET_CLE);
+
+		if (ctrl & NAND_NCE)
+			*nCE &= 0xFFFB;
+		else
+			*nCE |= 0x0004;
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= SET_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= SET_ALE;
+
+		this->IO_ADDR_W = (void *)IO_ADDR_W;
+
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+	clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
+
+	/*
+	 * set up pin configuration - enabled 2nd output buffer's signals
+	 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+	 * to use nCE signal
+	 */
+	clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+	setbits_8(&gpio->pddr_timer, 0x08);
+	setbits_8(&gpio->ppd_timer, 0x08);
+	out_8(&gpio->pclrr_timer, 0);
+	out_8(&gpio->podr_timer, 0);
+
+	nand->chip_delay = 60;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = nand_hwcontrol;
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/m54418twr/Kconfig b/roms/u-boot/board/freescale/m54418twr/Kconfig
new file mode 100644
index 000000000..4199a3f54
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54418twr/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M54418TWR
+
+config SYS_CPU
+	default "mcf5445x"
+
+config SYS_BOARD
+	default "m54418twr"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M54418TWR"
+
+endif
diff --git a/roms/u-boot/board/freescale/m54418twr/MAINTAINERS b/roms/u-boot/board/freescale/m54418twr/MAINTAINERS
new file mode 100644
index 000000000..f88aed99d
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54418twr/MAINTAINERS
@@ -0,0 +1,11 @@
+M54418TWR BOARD
+#M:	-
+S:	Maintained
+F:	board/freescale/m54418twr/
+F:	include/configs/M54418TWR.h
+F:	configs/M54418TWR_defconfig
+F:	configs/M54418TWR_nand_mii_defconfig
+F:	configs/M54418TWR_nand_rmii_defconfig
+F:	configs/M54418TWR_nand_rmii_lowfreq_defconfig
+F:	configs/M54418TWR_serial_mii_defconfig
+F:	configs/M54418TWR_serial_rmii_defconfig
diff --git a/roms/u-boot/board/freescale/m54418twr/Makefile b/roms/u-boot/board/freescale/m54418twr/Makefile
new file mode 100644
index 000000000..aa53874cc
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54418twr/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2010-2012 Freescale Semiconductor, Inc.
+# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+
+obj-y	= m54418twr.o
+extra-y	+= sbf_dram_init.o
+
diff --git a/roms/u-boot/board/freescale/m54418twr/m54418twr.c b/roms/u-boot/board/freescale/m54418twr/m54418twr.c
new file mode 100644
index 000000000..ca8993197
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54418twr/m54418twr.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spi.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	/*
+	 * need to to:
+	 * Check serial flash size. if 2mb evb, else 8mb demo
+	 */
+	puts("Board: ");
+	puts("Freescale MCF54418 Tower System\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	u32 dramsize;
+
+#if defined(CONFIG_SERIAL_BOOT)
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
+	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	pm_t *pm = (pm_t *) MMAP_PM;
+	u32 i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+
+	out_8(&pm->pmcr0, 0x2E);
+	out_8(&gpio->mscr_sdram, 1);
+
+	clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF);
+	setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK);
+
+	out_be32(&sdram->rcrcr, 0x40000000);
+	out_be32(&sdram->padcr, 0x01030203);
+
+	out_be32(&sdram->cr00, 0x01010101);
+	out_be32(&sdram->cr01, 0x00000101);
+	out_be32(&sdram->cr02, 0x01010100);
+	out_be32(&sdram->cr03, 0x01010000);
+	out_be32(&sdram->cr04, 0x00010101);
+	out_be32(&sdram->cr06, 0x00010100);
+	out_be32(&sdram->cr07, 0x00000001);
+	out_be32(&sdram->cr08, 0x01000001);
+	out_be32(&sdram->cr09, 0x00000100);
+	out_be32(&sdram->cr10, 0x00010001);
+	out_be32(&sdram->cr11, 0x00000200);
+	out_be32(&sdram->cr12, 0x01000002);
+	out_be32(&sdram->cr13, 0x00000000);
+	out_be32(&sdram->cr14, 0x00000100);
+	out_be32(&sdram->cr15, 0x02000100);
+	out_be32(&sdram->cr16, 0x02000407);
+	out_be32(&sdram->cr17, 0x02030007);
+	out_be32(&sdram->cr18, 0x02000100);
+	out_be32(&sdram->cr19, 0x0A030203);
+	out_be32(&sdram->cr20, 0x00020708);
+	out_be32(&sdram->cr21, 0x00050008);
+	out_be32(&sdram->cr22, 0x04030002);
+	out_be32(&sdram->cr23, 0x00000004);
+	out_be32(&sdram->cr24, 0x020A0000);
+	out_be32(&sdram->cr25, 0x0C00000E);
+	out_be32(&sdram->cr26, 0x00002004);
+	out_be32(&sdram->cr28, 0x00100010);
+	out_be32(&sdram->cr29, 0x00100010);
+	out_be32(&sdram->cr31, 0x07990000);
+	out_be32(&sdram->cr40, 0x00000000);
+	out_be32(&sdram->cr41, 0x00C80064);
+	out_be32(&sdram->cr42, 0x44520002);
+	out_be32(&sdram->cr43, 0x00C80023);
+	out_be32(&sdram->cr45, 0x0000C350);
+	out_be32(&sdram->cr56, 0x04000000);
+	out_be32(&sdram->cr57, 0x03000304);
+	out_be32(&sdram->cr58, 0x40040000);
+	out_be32(&sdram->cr59, 0xC0004004);
+	out_be32(&sdram->cr60, 0x0642C000);
+	out_be32(&sdram->cr61, 0x00000642);
+	asm("tpf");
+
+	out_be32(&sdram->cr09, 0x01000100);
+
+	udelay(100);
+#endif
+	gd->ram_size = dramsize;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/m54418twr/sbf_dram_init.S b/roms/u-boot/board/freescale/m54418twr/sbf_dram_init.S
new file mode 100644
index 000000000..5a70fb918
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54418twr/sbf_dram_init.S
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board-specific sbf ddr/sdram init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ */
+
+.global sbf_dram_init
+.text
+
+sbf_dram_init:
+	move.l	#0xFC04002D, %a1
+	move.b	#46, (%a1)		/* DDR */
+
+	/* slew settings */
+	move.l	#0xEC094060, %a1
+	move.b	#0, (%a1)
+
+	/* use vco instead of cpu*2 clock for ddr clock */
+	move.l	#0xEC09001A, %a1
+	move.w	#0xE01D, (%a1)
+
+	/* DDR settings */
+	move.l	#0xFC0B8180, %a1
+	move.l	#0x00000000, (%a1)
+	move.l	#0x40000000, (%a1)
+
+	move.l	#0xFC0B81AC, %a1
+	move.l	#0x01030203, (%a1)
+
+	move.l	#0xFC0B8000, %a1
+	move.l	#0x01010101, (%a1)+	/* 0x00 */
+	move.l	#0x00000101, (%a1)+	/* 0x04 */
+	move.l	#0x01010100, (%a1)+	/* 0x08 */
+	move.l	#0x01010000, (%a1)+	/* 0x0C */
+	move.l	#0x00010101, (%a1)+	/* 0x10 */
+	move.l	#0xFC0B8018, %a1
+	move.l	#0x00010100, (%a1)+	/* 0x18 */
+	move.l	#0x00000001, (%a1)+	/* 0x1C */
+	move.l	#0x01000001, (%a1)+	/* 0x20 */
+	move.l	#0x00000100, (%a1)+	/* 0x24 */
+	move.l	#0x00010001, (%a1)+	/* 0x28 */
+	move.l	#0x00000200, (%a1)+	/* 0x2C */
+	move.l	#0x01000002, (%a1)+	/* 0x30 */
+	move.l	#0x00000000, (%a1)+	/* 0x34 */
+	move.l	#0x00000100, (%a1)+	/* 0x38 */
+	move.l	#0x02000100, (%a1)+	/* 0x3C */
+	move.l	#0x02000407, (%a1)+	/* 0x40 */
+	move.l	#0x02030007, (%a1)+	/* 0x44 */
+	move.l	#0x02000100, (%a1)+	/* 0x48 */
+	move.l	#0x0A030203, (%a1)+	/* 0x4C */
+	move.l	#0x00020708, (%a1)+	/* 0x50 */
+	move.l	#0x00050008, (%a1)+	/* 0x54 */
+	move.l	#0x04030002, (%a1)+	/* 0x58 */
+	move.l	#0x00000004, (%a1)+	/* 0x5C */
+	move.l	#0x020A0000, (%a1)+	/* 0x60 */
+	move.l	#0x0C00000E, (%a1)+	/* 0x64 */
+	move.l	#0x00002004, (%a1)+	/* 0x68 */
+	move.l	#0x00000000, (%a1)+	/* 0x6C */
+	move.l	#0x00100010, (%a1)+	/* 0x70 */
+	move.l	#0x00100010, (%a1)+	/* 0x74 */
+	move.l	#0x00000000, (%a1)+	/* 0x78 */
+	move.l	#0x07990000, (%a1)+	/* 0x7C */
+	move.l	#0xFC0B80A0, %a1
+	move.l	#0x00000000, (%a1)+	/* 0xA0 */
+	move.l	#0x00C80064, (%a1)+	/* 0xA4 */
+	move.l	#0x44520002, (%a1)+	/* 0xA8 */
+	move.l	#0x00C80023, (%a1)+	/* 0xAC */
+	move.l	#0xFC0B80B4, %a1
+	move.l	#0x0000C350, (%a1)	/* 0xB4 */
+	move.l	#0xFC0B80E0, %a1
+	move.l	#0x04000000, (%a1)+	/* 0xE0 */
+	move.l	#0x03000304, (%a1)+	/* 0xE4 */
+	move.l	#0x40040000, (%a1)+	/* 0xE8 */
+	move.l	#0xC0004004, (%a1)+	/* 0xEC */
+	move.l	#0x0642C000, (%a1)+	/* 0xF0 */
+	move.l	#0x00000642, (%a1)+	/* 0xF4 */
+	move.l	#0xFC0B8024, %a1
+	tpf
+	move.l	#0x01000100, (%a1)	/* 0x24 */
+
+	move.l	#0x2000, %d1
+	bsr	asm_delay
+
+	rts
diff --git a/roms/u-boot/board/freescale/m54451evb/Kconfig b/roms/u-boot/board/freescale/m54451evb/Kconfig
new file mode 100644
index 000000000..f460e51c9
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54451evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M54451EVB
+
+config SYS_CPU
+	default "mcf5445x"
+
+config SYS_BOARD
+	default "m54451evb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M54451EVB"
+
+endif
diff --git a/roms/u-boot/board/freescale/m54451evb/MAINTAINERS b/roms/u-boot/board/freescale/m54451evb/MAINTAINERS
new file mode 100644
index 000000000..52a268108
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54451evb/MAINTAINERS
@@ -0,0 +1,7 @@
+M54451EVB BOARD
+#M:	-
+S:	Maintained
+F:	board/freescale/m54451evb/
+F:	include/configs/M54451EVB.h
+F:	configs/M54451EVB_defconfig
+F:	configs/M54451EVB_stmicro_defconfig
diff --git a/roms/u-boot/board/freescale/m54451evb/Makefile b/roms/u-boot/board/freescale/m54451evb/Makefile
new file mode 100644
index 000000000..8c2c6a9eb
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54451evb/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m54451evb.o
+extra-y	+= sbf_dram_init.o
diff --git a/roms/u-boot/board/freescale/m54451evb/m54451evb.c b/roms/u-boot/board/freescale/m54451evb/m54451evb.c
new file mode 100644
index 000000000..a4ddc6916
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54451evb/m54451evb.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spi.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	/*
+	 * need to to:
+	 * Check serial flash size. if 2mb evb, else 8mb demo
+	 */
+	puts("Board: ");
+	puts("Freescale M54451 EVB\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	u32 dramsize;
+#ifdef CONFIG_CF_SBF
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
+	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+	u32 i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
+	    (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
+		return dramsize;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
+
+	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
+
+	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
+
+	udelay(200);
+
+	/* Issue PALL */
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
+	__asm__("nop");
+
+	/* Perform two refresh cycles */
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+	__asm__("nop");
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+	__asm__("nop");
+
+	/* Issue LEMR */
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
+	__asm__("nop");
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
+	__asm__("nop");
+
+	out_be32(&sdram->sdcr,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
+
+	udelay(100);
+#endif
+	gd->ram_size = dramsize;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/roms/u-boot/board/freescale/m54451evb/sbf_dram_init.S b/roms/u-boot/board/freescale/m54451evb/sbf_dram_init.S
new file mode 100644
index 000000000..ee08cd1ec
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54451evb/sbf_dram_init.S
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board-specific sbf ddr/sdram init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ */
+
+ #include <config.h>
+
+.global sbf_dram_init
+.text
+
+sbf_dram_init:
+	/* Dram Initialization a1, a2, and d0 */
+	/* mscr sdram */
+	move.l	#0xFC0A4074, %a1
+	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
+	nop
+
+	/* SDRAM Chip 0 and 1 */
+	move.l	#0xFC0B8110, %a1
+	move.l	#0xFC0B8114, %a2
+
+	/* calculate the size */
+	move.l	#0x13, %d1
+	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	lsr.l	#1, %d2
+#endif
+
+dramsz_loop:
+	lsr.l	#1, %d2
+	add.l	#1, %d1
+	cmp.l	#1, %d2
+	bne	dramsz_loop
+#ifdef CONFIG_SYS_NAND_BOOT
+	beq	asm_nand_chk_status
+#endif
+	/* SDRAM Chip 0 and 1 */
+	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
+	or.l	%d1, (%a1)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
+	or.l	%d1, (%a2)
+#endif
+	nop
+
+	/* dram cfg1 and cfg2 */
+	move.l	#0xFC0B8008, %a1
+	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
+	nop
+	move.l	#0xFC0B800C, %a2
+	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
+	nop
+
+	move.l	#0xFC0B8000, %a1	/* Mode */
+	move.l	#0xFC0B8004, %a2	/* Ctrl */
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	move.l	#1000, %d1
+	bsr	asm_delay
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Perform two refresh cycles */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
+	nop
+	move.l	%d0, (%a2)
+	move.l	%d0, (%a2)
+	nop
+
+	/* Issue LEMR */
+	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
+	nop
+	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
+
+	move.l	#500, %d1
+	bsr	asm_delay
+
+	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d1
+	and.l	#0x7FFFFFFF, %d1
+
+	or.l	#0x10000C00, %d1
+
+	move.l	%d1, (%a2)
+	nop
+
+	move.l	#2000, %d1
+	bsr	asm_delay
+
+	rts
diff --git a/roms/u-boot/board/freescale/m54455evb/Kconfig b/roms/u-boot/board/freescale/m54455evb/Kconfig
new file mode 100644
index 000000000..096bce831
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54455evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M54455EVB
+
+config SYS_CPU
+	default "mcf5445x"
+
+config SYS_BOARD
+	default "m54455evb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M54455EVB"
+
+endif
diff --git a/roms/u-boot/board/freescale/m54455evb/MAINTAINERS b/roms/u-boot/board/freescale/m54455evb/MAINTAINERS
new file mode 100644
index 000000000..27ced3c7b
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54455evb/MAINTAINERS
@@ -0,0 +1,10 @@
+M54455EVB BOARD
+M:	TsiChung Liew <Tsi-Chung.Liew@nxp.com>
+S:	Maintained
+F:	board/freescale/m54455evb/
+F:	include/configs/M54455EVB.h
+F:	configs/M54455EVB_defconfig
+F:	configs/M54455EVB_a66_defconfig
+F:	configs/M54455EVB_i66_defconfig
+F:	configs/M54455EVB_intel_defconfig
+F:	configs/M54455EVB_stm33_defconfig
diff --git a/roms/u-boot/board/freescale/m54455evb/Makefile b/roms/u-boot/board/freescale/m54455evb/Makefile
new file mode 100644
index 000000000..eff8ab066
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54455evb/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m54455evb.o
+extra-y	+= sbf_dram_init.o
diff --git a/roms/u-boot/board/freescale/m54455evb/README b/roms/u-boot/board/freescale/m54455evb/README
new file mode 100644
index 000000000..26d3cc81f
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54455evb/README
@@ -0,0 +1,407 @@
+Freescale MCF54455EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 4/08/07
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m54455evb/m54455evb.c	Dram setup, IDE pre init, and PCI init
+- board/freescale/m54455evb/flash.c		Atmel and INTEL flash support
+- board/freescale/m54455evb/Makefile		Makefile
+- board/freescale/m54455evb/config.mk	config make
+- board/freescale/m54455evb/u-boot.lds	Linker description
+
+- common/cmd_bdinfo.c		Clock frequencies output
+- common/cmd_mii.c		mii support
+
+- arch/m68k/cpu/mcf5445x/cpu.c		cpu specific code
+- arch/m68k/cpu/mcf5445x/cpu_init.c	Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- arch/m68k/cpu/mcf5445x/interrupts.c	cpu specific interrupt support
+- arch/m68k/cpu/mcf5445x/speed.c		system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5445x/Makefile		Makefile
+- arch/m68k/cpu/mcf5445x/config.mk	config make
+- arch/m68k/cpu/mcf5445x/start.S		start up assembly code
+
+- board/freescale/m54455evb/README	This readme file
+
+- drivers/net/mcffec.c		ColdFire common FEC driver
+- drivers/serial/mcfuart.c	ColdFire common UART driver
+
+- include/asm-m68k/bitops.h		Bit operation function export
+- include/asm-m68k/byteorder.h		Byte order functions
+- include/asm-m68k/fec.h		FEC structure and definition
+- include/asm-m68k/fsl_i2c.h		I2C structure and definition
+- include/asm-m68k/global_data.h	Global data structure
+- include/asm-m68k/immap.h		ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5445x.h	mcf5445x specific header file
+- include/asm-m68k/io.h			io functions
+- include/asm-m68k/m5445x.h		mcf5445x specific header file
+- include/asm-m68k/posix_types.h	Posix
+- include/asm-m68k/processor.h		header file
+- include/asm-m68k/ptrace.h		Exception structure
+- include/asm-m68k/rtc.h		Realtime clock header file
+- include/asm-m68k/string.h		String function export
+- include/asm-m68k/timer.h		Timer structure and definition
+- include/asm-m68k/types.h		Data types definition
+- include/asm-m68k/uart.h		Uart structure and definition
+- include/asm-m68k/u-boot.h		U-Boot structure
+
+- include/configs/M54455EVB.h	Board specific configuration file
+
+- arch/m68k/lib/board.c			board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts			Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c			Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c			Exception init code
+
+- rtc/mcfrtc.c				Realtime clock Driver
+
+1 MCF5445x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M54455EVB Development Board
+CONFIG_MCF5445x		-- define for all MCF5445x CPUs
+CONFIG_M54455		-- define for all Freescale MCF54455 CPUs
+CONFIG_M54455EVB	-- define for M54455EVB board
+
+CONFIG_MCFUART		-- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE		-- define UART baudrate
+
+CONFIG_MCFRTC		-- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE		-- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR	-- define RTC clock frequency
+RTC_DEBUG		-- define to show RTC debug message
+CONFIG_CMD_DATE		-- enable to use date feature in U-Boot
+
+CONFIG_MCFFEC		-- define to use common CF FEC driver
+CONFIG_MII		-- enable to use MII driver
+CONFIG_CF_DOMII		-- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY	-- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER	-- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
+CONFIG_SYS_FEC0_PINMUX		-- Set FEC0 Pin configuration
+CONFIG_SYS_FEC1_PINMUX		-- Set FEC1 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE	-- Set FEC0 MII base register
+CONFIG_SYS_FEC1_MIIBASE	-- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP	-- set FEC timeout loop
+CONFIG_HAS_ETH1		-- define to enable second FEC in U-Boot
+
+CONFIG_ISO_PARTITION	-- enable ISO read/write
+CONFIG_DOS_PARTITION	-- enable DOS read/write
+CONFIG_IDE_RESET	-- define ide_reset()
+CONFIG_IDE_PREINIT	-- define ide_preinit()
+CONFIG_ATAPI		-- define ATAPI support
+CONFIG_LBA48		-- define LBA48 (larger than 120GB) support
+CONFIG_SYS_IDE_MAXBUS		-- define max channel
+CONFIG_SYS_IDE_MAXDEVICE	-- define max devices per channel
+CONFIG_SYS_ATA_BASE_ADDR	-- define ATA base address
+CONFIG_SYS_ATA_IDE0_OFFSET	-- define ATA IDE0 offset
+CONFIG_SYS_ATA_DATA_OFFSET	-- define ATA data IO
+CONFIG_SYS_ATA_REG_OFFSET	-- define for normal register accesses
+CONFIG_SYS_ATA_ALT_OFFSET	-- define for alternate registers
+CONFIG_SYS_ATA_STRIDE		-- define for Interval between registers
+_IO_BASE		-- define for IO base address
+
+CONFIG_MCFTMR		-- define to use DMA timer
+
+CONFIG_SYS_FSL_I2C	-- define to use FSL common I2C driver
+CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED		-- define for I2C speed
+CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
+CONFIG_SYS_IMMR		-- define for MBAR offset
+
+CONFIG_PCI              -- define for PCI support
+CONFIG_PCI_PNP          -- define for Plug n play support
+CONFIG_SYS_PCI_MEM_BUS		-- PCI memory logical offset
+CONFIG_SYS_PCI_MEM_PHYS	-- PCI memory physical offset
+CONFIG_SYS_PCI_MEM_SIZE	-- PCI memory size
+CONFIG_SYS_PCI_IO_BUS		-- PCI IO logical offset
+CONFIG_SYS_PCI_IO_PHYS		-- PCI IO physical offset
+CONFIG_SYS_PCI_IO_SIZE		-- PCI IO size
+CONFIG_SYS_PCI_CFG_BUS		-- PCI Configuration logical offset
+CONFIG_SYS_PCI_CFG_PHYS	-- PCI Configuration physical offset
+CONFIG_SYS_PCI_CFG_SIZE	-- PCI Configuration size
+
+CONFIG_EXTRA_CLOCK	-- Enable extra clock such as vco, flexbus, pci, etc
+
+CONFIG_SYS_MBAR		-- define MBAR offset
+
+CONFIG_SYS_ATMEL_BOOT		-- To determine the U-Boot is booted from Atmel or Intel
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF54455 internal SRAM
+
+CONFIG_SYS_CSn_BASE	-- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK	-- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL	-- defines the Chip Select Control register
+
+CONFIG_SYS_ATMEL_BASE	-- defines the Atmel Flash base
+CONFIG_SYS_INTEL_BASE	-- defines the Intel Flash base
+
+CONFIG_SYS_SDRAM_BASE	-- defines the DRAM Base
+CONFIG_SYS_SDRAM_BASE1	-- defines the DRAM Base 1
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+	Flash:		0x00000000-0x3FFFFFFF (1024MB)
+	DDR:		0x40000000-0x7FFFFFFF (1024MB)
+	SRAM:		0x80000000-0x8FFFFFFF (256MB)
+	ATA:		0x90000000-0x9FFFFFFF (256MB)
+	PCI:		0xA0000000-0xBFFFFFFF (512MB)
+	FlexBus:	0xC0000000-0xDFFFFFFF (512MB)
+	IP:		0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and
+	linux kernel, you can customize it based on your system requirements:
+	Atmel boot:
+	Flash0:		0x00000000-0x0007FFFF (512KB)
+	Flash1:		0x04000000-0x05FFFFFF (32MB)
+	Intel boot:
+	Flash0:		0x00000000-0x01FFFFFF (32MB)
+	Flash1:		0x04000000-0x0407FFFF (512KB)
+
+	CPLD:		0x08000000-0x08FFFFFF (16MB)
+	FPGA:		0x09000000-0x09FFFFFF (16MB)
+	DDR:		0x40000000-0x4FFFFFFF (256MB)
+	SRAM:		0x80000000-0x80007FFF (32KB)
+	IP:		0xFC000000-0xFC0FFFFF (64KB)
+
+3. SWITCH SETTINGS
+==================
+3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
+	SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state
+	SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down
+			  1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active
+	SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down
+	SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
+
+4. COMPILATION
+==============
+4.1	To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version)
+from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+4.2 Compilation
+   export CROSS_COMPILE=cross-compile-prefix
+   cd u-boot-1.x.x
+   make distclean
+   make M54455EVB_config, or		- default to atmel 33Mhz input clock
+   make M54455EVB_atmel_config, or	- default to atmel 33Mhz input clock
+   make M54455EVB_a33_config, or	- default to atmel 33Mhz input clock
+   make M54455EVB_a66_config, or	- default to atmel 66Mhz input clock
+   make M54455EVB_intel_config, or	- default to intel 33Mhz input clock
+   make M54455EVB_i33_config, or	- default to intel 33Mhz input clock
+   make M54455EVB_i66_config, or	- default to intel 66Mhz input clock
+   make
+
+5. SCREEN DUMP
+==============
+5.1 M54455EVB Development board
+    Boot from Atmel (NOTE: May not show exactly the same)
+
+U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08)
+
+CPU:   Freescale MCF54455 (Mask:48 Version:1)
+       CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz
+       PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz
+Board: Freescale M54455 EVB
+I2C:   ready
+DRAM:  256 MB
+FLASH: 16.5 MB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   FEC0, FEC1
+IDE:   Bus 0: not available
+-> print
+bootargs=root=/dev/ram rw
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+eth1addr=00:e0:0c:bc:e5:61
+hostname=M54455EVB
+netdev=eth0
+inpclk=33333333
+loadaddr=40010000
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
+ethact=FEC0
+mtdids=nor0=M54455EVB-1
+mtdparts=M54455EVB-1:16m(user)
+u-boot=u-boot54455.bin
+filesize=292b4
+fileaddr=40010000
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=261632k
+
+Environment size: 563/8188 bytes
+-> bdinfo
+memstart    = 0x40000000
+memsize     = 0x10000000
+flashstart  = 0x00000000
+flashsize   = 0x01080000
+flashoffset = 0x00000000
+sramstart   = 0x80000000
+sramsize    = 0x00008000
+mbar        = 0xFC000000
+busfreq     = 133.333 MHz
+pcifreq     = 33.333 MHz
+flbfreq     = 66.666 MHz
+inpfreq     = 33.333 MHz
+vcofreq     = 533.333 MHz
+ethaddr     = 00:E0:0C:BC:E5:60
+eth1addr    = 00:E0:0C:BC:E5:61
+ip_addr     = 192.168.1.3
+baudrate    = 115200 bps
+->
+-> help
+?       - alias for 'help'
+base    - print or set address offset
+bdinfo  - print Board Info structure
+boot    - boot default, i.e., run 'bootcmd'
+bootd   - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm   - boot application image from memory
+bootp	- boot image via network using BootP/TFTP protocol
+bootvx  - Boot vxWorks from an ELF image
+cmp     - memory compare
+coninfo - print console devices and information
+cp      - memory copy
+crc32   - checksum calculation
+date    - get/set/reset date & time
+dcache  - enable or disable data cache
+diskboot- boot from IDE device
+echo    - echo args to console
+erase   - erase FLASH memory
+ext2load- load binary file from a Ext2 filesystem
+ext2ls  - list files in a directory (default /)
+fatinfo - print information about filesystem
+fatload - load binary file from a dos filesystem
+fatls   - list files in a directory (default /)
+flinfo  - print FLASH memory information
+fsinfo	- print information about filesystems
+fsload	- load binary file from a filesystem image
+go      - start application at address 'addr'
+help    - print online help
+i2c     - I2C sub-system
+icache  - enable or disable instruction cache
+ide     - IDE sub-system
+iminfo  - print header information for application image
+imls    - list all images found in flash
+itest	- return true/false on integer compare
+loadb   - load binary file over serial line (kermit mode)
+loads   - load S-Record file over serial line
+loady   - load binary file over serial line (ymodem mode)
+loop    - infinite loop on address range
+ls	- list files in a directory (default /)
+md      - memory display
+mii     - MII utility commands
+mm      - memory modify (auto-incrementing)
+mtest   - simple RAM test
+mw      - memory write (fill)
+nfs	- boot image via network using NFS protocol
+nm      - memory modify (constant address)
+pci     - list and access PCI Configuration Space
+ping	- send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+sleep   - delay execution for some time
+source  - run script from memory
+tftpboot- boot image via network using TFTP protocol
+version - print monitor version
+->bootm 4000000
+
+## Booting image at 04000000 ...
+   Image Name:   Linux Kernel Image
+   Created:      2007-08-14  15:13:00 UTC
+   Image Type:   M68K Linux Kernel Image (uncompressed)
+   Data Size:    2301952 Bytes =  2.2 MB
+   Load Address: 40020000
+   Entry Point:  40020000
+   Verifying Checksum ... OK
+OK
+Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr
+erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007
+starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB
+Built 1 zonelists.  Total pages: 32624
+Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph
+ysmap-flash.0:5M(kernel)ro,-(jffs2)
+PID hash table entries: 1024 (order: 10, 4096 bytes)
+Console: colour dummy device 80x25
+Dentry cache hash table entries: 32768 (order: 4, 131072 bytes)
+Inode-cache hash table entries: 16384 (order: 3, 65536 bytes)
+Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init)
+Mount-cache hash table entries: 1024
+NET: Registered protocol family 16
+SCSI subsystem initialized
+NET: Registered protocol family 2
+IP route cache hash table entries: 2048 (order: 0, 8192 bytes)
+TCP established hash table entries: 8192 (order: 2, 32768 bytes)
+TCP bind hash table entries: 4096 (order: 1, 16384 bytes)
+TCP: Hash tables configured (established 8192 bind 4096)
+TCP reno registered
+JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc.
+io scheduler noop registered
+io scheduler anticipatory registered
+io scheduler deadline registered
+io scheduler cfq registered (default)
+ColdFire internal UART serial driver version 1.00
+ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
+ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
+ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART
+RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize
+loop: loaded (max 8 devices)
+FEC ENET Version 0.2
+fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849
+eth0: ethernet 00:08:ee:00:e4:19
+physmap platform flash device: 01000000 at 04000000
+physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank
+ Intel/Sharp Extended Query Table at 0x0031
+Using buffer write method
+cfi_cmdset_0001: Erase suspend on write enabled
+2 cmdlinepart partitions found on MTD device physmap-flash.0
+Creating 2 MTD partitions on "physmap-flash.0":
+0x00000000-0x00500000 : "kernel"
+mtd: Giving out device 0 to kernel
+0x00500000-0x01000000 : "jffs2"
+mtd: Giving out device 1 to jffs2
+mice: PS/2 mouse device common for all mice
+i2c /dev entries driver
+TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 17
+NET: Registered protocol family 15
+VFS: Mounted root (jffs2 filesystem).
+Setting the hostname to freescale
+Mounting filesystems
+mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory
+Starting syslogd and klogd
+Setting up networking on loopback device:
+Setting up networking on eth0:
+eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
+Adding static route for default gateway to 172.27.255.254:
+Setting nameserver to 172.27.0.1 in /etc/resolv.conf:
+Starting inetd:
+/ #
diff --git a/roms/u-boot/board/freescale/m54455evb/m54455evb.c b/roms/u-boot/board/freescale/m54455evb/m54455evb.c
new file mode 100644
index 000000000..c749ee407
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54455evb/m54455evb.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M54455 EVB\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	u32 dramsize;
+#ifdef CONFIG_CF_SBF
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
+#else
+	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+	u32 i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
+
+	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
+
+	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
+
+	/* Issue PALL */
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Issue LEMR */
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
+
+	udelay(500);
+
+	/* Issue PALL */
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
+
+	out_be32(&sdram->sdcr,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+
+	udelay(100);
+#endif
+	gd->ram_size = dramsize << 1;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#if defined(CONFIG_IDE)
+#include <ata.h>
+
+int ide_preinit(void)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	u32 tmp;
+
+	tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
+	setbits_8(&gpio->par_fec, tmp);
+	tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
+		(GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
+	setbits_be16(&gpio->par_feci2c, tmp);
+
+	setbits_be16(&gpio->par_ata,
+		GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
+		GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
+		GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
+		GPIO_PAR_ATA_IORDY_IORDY);
+	setbits_be16(&gpio->par_pci,
+		GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
+
+	return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+	atac_t *ata = (atac_t *) MMAP_ATA;
+	long period;
+	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
+	int piotms[5][9] = {
+		{70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
+		{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
+		{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
+		{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
+		{25, 70, 20, 10, 20, 5, 10, 0, 35}
+	};			/* PIO 4 */
+
+	if (idereset) {
+		/* control reset */
+		out_8(&ata->cr, 0);
+		udelay(10000);
+	} else {
+#define CALC_TIMING(t) (t + period - 1) / period
+		period = 1000000000 / gd->bus_clk;	/* period in ns */
+
+		/*ata->ton = CALC_TIMING (180); */
+		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+		/* IORDY enable */
+		out_8(&ata->cr, 0x40);
+		udelay(200000);
+		/* IORDY enable */
+		setbits_8(&ata->cr, 0x01);
+	}
+}
+#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf5445x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+	pci_mcf5445x_init(&hose);
+}
+#endif				/* CONFIG_PCI */
+
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+	int sect[] = CONFIG_SYS_ATMEL_SECT;
+	int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
+	int i, j, k;
+
+	if (base != CONFIG_SYS_ATMEL_BASE)
+		return 0;
+
+	info->flash_id          = 0x01000000;
+	info->portwidth         = 1;
+	info->chipwidth         = 1;
+	info->buffer_size       = 1;
+	info->erase_blk_tout    = 16384;
+	info->write_tout        = 2;
+	info->buffer_write_tout = 5;
+	info->vendor            = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
+	info->cmd_reset         = 0x00F0;
+	info->interface         = FLASH_CFI_X8;
+	info->legacy_unlock     = 0;
+	info->manufacturer_id   = (u16) ATM_MANUFACT;
+	info->device_id         = ATM_ID_LV040;
+	info->device_id2        = 0;
+
+	info->ext_addr          = 0;
+	info->cfi_version       = 0x3133;
+	info->cfi_offset        = 0x0000;
+	info->addr_unlock1      = 0x00000555;
+	info->addr_unlock2      = 0x000002AA;
+	info->name              = "CFI conformant";
+
+	info->size              = 0;
+	info->sector_count      = CONFIG_SYS_ATMEL_TOTALSECT;
+	info->start[0] = base;
+	for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
+		info->size += sect[i] * sectsz[i];
+
+		for (j = 0; j < sect[i]; j++, k++) {
+			info->start[k + 1] = info->start[k] + sectsz[i];
+			info->protect[k] = 0;
+		}
+	}
+
+	return 1;
+}
+#endif				/* CONFIG_SYS_FLASH_CFI */
diff --git a/roms/u-boot/board/freescale/m54455evb/sbf_dram_init.S b/roms/u-boot/board/freescale/m54455evb/sbf_dram_init.S
new file mode 100644
index 000000000..fe5bb05dd
--- /dev/null
+++ b/roms/u-boot/board/freescale/m54455evb/sbf_dram_init.S
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board-specific sbf ddr/sdram init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ */
+
+ #include <config.h>
+
+.global sbf_dram_init
+.text
+
+sbf_dram_init:
+	/* Dram Initialization a1, a2, and d0 */
+	/* mscr sdram */
+	move.l	#0xFC0A4074, %a1
+	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
+	nop
+
+	/* SDRAM Chip 0 and 1 */
+	move.l	#0xFC0B8110, %a1
+	move.l	#0xFC0B8114, %a2
+
+	/* calculate the size */
+	move.l	#0x13, %d1
+	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	lsr.l	#1, %d2
+#endif
+
+dramsz_loop:
+	lsr.l	#1, %d2
+	add.l	#1, %d1
+	cmp.l	#1, %d2
+	bne	dramsz_loop
+#ifdef CONFIG_SYS_NAND_BOOT
+	beq	asm_nand_chk_status
+#endif
+	/* SDRAM Chip 0 and 1 */
+	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
+	or.l	%d1, (%a1)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
+	or.l	%d1, (%a2)
+#endif
+	nop
+
+	/* dram cfg1 and cfg2 */
+	move.l	#0xFC0B8008, %a1
+	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
+	nop
+	move.l	#0xFC0B800C, %a2
+	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
+	nop
+
+	move.l	#0xFC0B8000, %a1	/* Mode */
+	move.l	#0xFC0B8004, %a2	/* Ctrl */
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Issue LEMR */
+	move.l	#(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
+	nop
+	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
+	nop
+
+	move.l	#1000, %d1
+	bsr	asm_delay
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Perform two refresh cycles */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
+	nop
+	move.l	%d0, (%a2)
+	move.l	%d0, (%a2)
+	nop
+
+	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
+	nop
+
+	move.l	#500, %d1
+	bsr	asm_delay
+
+	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d1
+	and.l	#0x7FFFFFFF, %d1
+
+	or.l	#0x10000C00, %d1
+
+	move.l	%d1, (%a2)
+	nop
+
+	move.l	#2000, %d1
+	bsr	asm_delay
+
+	rts
diff --git a/roms/u-boot/board/freescale/m547xevb/Kconfig b/roms/u-boot/board/freescale/m547xevb/Kconfig
new file mode 100644
index 000000000..8cfe20ab8
--- /dev/null
+++ b/roms/u-boot/board/freescale/m547xevb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5475EVB
+
+config SYS_CPU
+	default "mcf547x_8x"
+
+config SYS_BOARD
+	default "m547xevb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M5475EVB"
+
+endif
diff --git a/roms/u-boot/board/freescale/m547xevb/MAINTAINERS b/roms/u-boot/board/freescale/m547xevb/MAINTAINERS
new file mode 100644
index 000000000..0d821eb01
--- /dev/null
+++ b/roms/u-boot/board/freescale/m547xevb/MAINTAINERS
@@ -0,0 +1,12 @@
+M547XEVB BOARD
+M:	TsiChung Liew <Tsi-Chung.Liew@nxp.com>
+S:	Maintained
+F:	board/freescale/m547xevb/
+F:	include/configs/M5475EVB.h
+F:	configs/M5475AFE_defconfig
+F:	configs/M5475BFE_defconfig
+F:	configs/M5475CFE_defconfig
+F:	configs/M5475DFE_defconfig
+F:	configs/M5475EFE_defconfig
+F:	configs/M5475FFE_defconfig
+F:	configs/M5475GFE_defconfig
diff --git a/roms/u-boot/board/freescale/m547xevb/Makefile b/roms/u-boot/board/freescale/m547xevb/Makefile
new file mode 100644
index 000000000..29fe9dad7
--- /dev/null
+++ b/roms/u-boot/board/freescale/m547xevb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m547xevb.o
diff --git a/roms/u-boot/board/freescale/m547xevb/README b/roms/u-boot/board/freescale/m547xevb/README
new file mode 100644
index 000000000..6b4fbe5c2
--- /dev/null
+++ b/roms/u-boot/board/freescale/m547xevb/README
@@ -0,0 +1,271 @@
+Freescale MCF5475EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created Jan 08, 2008
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m547xevb/m547xevb.c	Dram setup, IDE pre init, and PCI init
+- board/freescale/m547xevb/mii.c	MII init
+- board/freescale/m547xevb/Makefile	Makefile
+- board/freescale/m547xevb/config.mk	config make
+- board/freescale/m547xevb/u-boot.lds	Linker description
+
+- arch/m68k/cpu/mcf547x_8x/cpu.c			cpu specific code
+- arch/m68k/cpu/mcf547x_8x/cpu_init.c		Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- arch/m68k/cpu/mcf547x_8x/interrupts.c		cpu specific interrupt support
+- arch/m68k/cpu/mcf547x_8x/slicetimer.c		Timer support
+- arch/m68k/cpu/mcf547x_8x/speed.c		system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf547x_8x/Makefile		Makefile
+- arch/m68k/cpu/mcf547x_8x/config.mk		config make
+- arch/m68k/cpu/mcf547x_8x/start.S		start up assembly code
+
+- board/freescale/m547xevb/README	This readme file
+
+- drivers/dma/MCD_dmaApi.c		DMA API functions
+- drivers/dma/MCD_tasks.c		DMA Tasks
+- drivers/dma/MCD_tasksInit.c		DMA Tasks Init
+- drivers/net/fsl_mcdmafec.c		ColdFire common DMA FEC driver
+- drivers/serial/mcfuart.c		ColdFire common UART driver
+
+- include/MCD_dma.h			DMA header file
+- include/MCD_progCheck.h		DMA header file
+- include/MCD_tasksInit.h		DMA header file
+- include/asm-m68k/bitops.h		Bit operation function export
+- include/asm-m68k/byteorder.h		Byte order functions
+- include/asm-m68k/errno.h		Error Number definition
+- include/asm-m68k/fec.h		FEC structure and definition
+- include/asm-m68k/fsl_i2c.h		I2C structure and definition
+- include/asm-m68k/fsl_mcddmafec.h	DMA FEC structure and definition
+- include/asm-m68k/global_data.h	Global data structure
+- include/asm-m68k/immap.h		ColdFire specific header file and driver macros
+- include/asm-m68k/immap_547x_8x.h	mcf547x_8x specific header file
+- include/asm-m68k/io.h			io functions
+- include/asm-m68k/m547x_8x.h		mcf547x_8x specific header file
+- include/asm-m68k/posix_types.h	Posix
+- include/asm-m68k/processor.h		header file
+- include/asm-m68k/ptrace.h		Exception structure
+- include/asm-m68k/rtc.h		Realtime clock header file
+- include/asm-m68k/string.h		String function export
+- include/asm-m68k/timer.h		Timer structure and definition
+- include/asm-m68k/types.h		Data types definition
+- include/asm-m68k/uart.h		Uart structure and definition
+- include/asm-m68k/u-boot.h		U-Boot structure
+
+- include/configs/M5475EVB.h		Board specific configuration file
+
+- arch/m68k/lib/board.c			board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts			Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/traps.c			Exception init code
+
+1 MCF547x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M5475EVB Development Board
+CONFIG_MCF547x_8x	-- define for all MCF547x_8x CPUs
+CONFIG_M547x		-- define for all Freescale MCF547x CPUs
+CONFIG_M5475		-- define for M5475EVB board
+
+CONFIG_MCFUART		-- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE		-- define UART baudrate
+
+CONFIG_FSLDMAFEC	-- define to use common dma FEC driver
+CONFIG_MII		-- enable to use MII driver
+CONFIG_CF_DOMII		-- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY	-- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER	-- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
+CONFIG_SYS_FEC0_PINMUX		-- Set FEC0 Pin configuration
+CONFIG_SYS_FEC1_PINMUX		-- Set FEC1 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE	-- Set FEC0 MII base register
+CONFIG_SYS_FEC1_MIIBASE	-- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP	-- set FEC timeout loop
+CONFIG_HAS_ETH1		-- define to enable second FEC in U-Boot
+
+CONFIG_CMD_USB		-- enable USB commands
+CONFIG_USB_OHCI_NEW	-- enable USB OHCI driver
+CONFIG_USB_STORAGE	-- enable USB Storage device
+CONFIG_DOS_PARTITION	-- enable DOS read/write
+
+CONFIG_SLTTMR		-- define to use SLT timer
+
+CONFIG_SYS_I2C_FSL	-- define to use FSL common I2C driver
+CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED		-- define for I2C speed
+CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
+CONFIG_SYS_IMMR		-- define for MBAR offset
+
+CONFIG_PCI		-- define for PCI support
+CONFIG_PCI_PNP		-- define for Plug n play support
+CONFIG_SKIPPCI_HOSTBRIDGE	-- SKIP PCI Host bridge
+CONFIG_SYS_PCI_MEM_BUS		-- PCI memory logical offset
+CONFIG_SYS_PCI_MEM_PHYS	-- PCI memory physical offset
+CONFIG_SYS_PCI_MEM_SIZE	-- PCI memory size
+CONFIG_SYS_PCI_IO_BUS		-- PCI IO logical offset
+CONFIG_SYS_PCI_IO_PHYS		-- PCI IO physical offset
+CONFIG_SYS_PCI_IO_SIZE		-- PCI IO size
+CONFIG_SYS_PCI_CFG_BUS		-- PCI Configuration logical offset
+CONFIG_SYS_PCI_CFG_PHYS	-- PCI Configuration physical offset
+CONFIG_SYS_PCI_CFG_SIZE	-- PCI Configuration size
+
+CONFIG_SYS_MBAR		-- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF547x internal SRAM
+
+CONFIG_SYS_CSn_BASE	-- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK	-- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL	-- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE	-- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+	Flash:		0xFF800000-0xFFFFFFFF (8MB)
+	DDR:		0x00000000-0x3FFFFFFF (1024MB)
+	SRAM:		0xF2000000-0xF2000FFF (4KB)
+	PCI:		0x70000000-0x8FFFFFFF (512MB)
+	IP:		0xF0000000-0xFFFFFFFF (256MB)
+
+3. COMPILATION
+==============
+3.1	To create U-Boot the gcc-4.x compiler set (ColdFire ELF or uclinux
+	version) from codesourcery.com was used. Download it from:
+	http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+   export CROSS_COMPILE=cross-compile-prefix
+   cd u-boot-1.x.x
+   make distclean
+   make M5475AFE_config, or	- boot 2MB, RAM 64MB
+   make M5475BFE_config, or	- boot 2MB, code 16MB, RAM 64MB
+   make M5475CFE_config, or	- boot 2MB, code 16MB, Video, USB, RAM 64MB
+   make M5475DFE_config, or	- boot 2MB, USB, RAM 64MB
+   make M5475EFE_config, or	- boot 2MB, Video, USB, RAM 64MB
+   make M5475FFE_config, or	- boot 2MB, code 32MB, Video, USB, RAM 128MB
+   make M5475GFE_config, or	- boot 2MB, RAM 64MB
+   make
+
+5. SCREEN DUMP
+==============
+5.1
+
+U-Boot 1.3.1 (Jan  8 2008 - 12:47:44)
+
+CPU:   Freescale MCF5475
+       CPU CLK 266 Mhz BUS CLK 133 Mhz
+Board: Freescale FireEngine 5475 EVB
+I2C:   ready
+DRAM:  64 MB
+FLASH: 18 MB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   FEC0, FEC1
+-> pri
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+eth1addr=00:e0:0c:bc:e5:61
+ipaddr=192.162.1.2
+serverip=192.162.1.1
+gatewayip=192.162.1.1
+netmask=255.255.255.0
+hostname=M547xEVB
+netdev=eth0
+loadaddr=10000
+u-boot=u-boot.bin
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off bank 1;era ff800000 ff82ffff;cp.b ${loadaddr} ff800000 ${filesize};save
+stdin=serial
+stdout=serial
+stderr=serial
+ethact=FEC0
+mem=65024k
+
+Environment size: 433/8188 bytes
+-> bdin
+memstart    = 0x00000000
+memsize     = 0x04000000
+flashstart  = 0xFF800000
+flashsize   = 0x01200000
+flashoffset = 0x00000000
+sramstart   = 0xF2000000
+sramsize    = 0x00001000
+mbar	    = 0xF0000000
+busfreq     = 133.333 MHz
+pcifreq     =	   0 MHz
+ethaddr     = 00:E0:0C:BC:E5:60
+eth1addr    = 00:E0:0C:BC:E5:61
+ip_addr     = 192.162.1.2
+baudrate    = 115200 bps
+-> ?
+?	- alias for 'help'
+base	- print or set address offset
+bdinfo	- print Board Info structure
+boot	- boot default, i.e., run 'bootcmd'
+bootd	- boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm	- boot application image from memory
+bootp	- boot image via network using BootP/TFTP protocol
+bootvx	- Boot vxWorks from an ELF image
+cmp	- memory compare
+coninfo - print console devices and information
+cp	- memory copy
+crc32	- checksum calculation
+dcache	- enable or disable data cache
+echo	- echo args to console
+erase	- erase FLASH memory
+flinfo	- print FLASH memory information
+go	- start application at address 'addr'
+help	- print online help
+i2c	- I2C sub-system
+icache	- enable or disable instruction cache
+iminfo	- print header information for application image
+imls	- list all images found in flash
+itest	- return true/false on integer compare
+loadb	- load binary file over serial line (kermit mode)
+loads	- load S-Record file over serial line
+loady	- load binary file over serial line (ymodem mode)
+loop	- infinite loop on address range
+md	- memory display
+mii	- MII utility commands
+mm	- memory modify (auto-incrementing)
+mtest	- simple RAM test
+mw	- memory write (fill)
+nfs	- boot image via network using NFS protocol
+nm	- memory modify (constant address)
+pci	- list and access PCI Configuration Space
+ping	- send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset	- Perform RESET of the CPU
+run	- run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv	- set environment variables
+sleep	- delay execution for some time
+source	- run script from memory
+tftpboot- boot image via network using TFTP protocol
+usb	- USB sub-system
+usbboot - boot from USB device
+version - print monitor version
+-> usb start
+(Re)start USB...
+USB:   OHCI pci controller (1131, 1561) found @(0:17:0)
+OHCI regs address 0x80000000
+scanning bus for devices... 2 USB Device(s) found
+       scanning bus for storage devices... 1 Storage Device(s) found
+->
diff --git a/roms/u-boot/board/freescale/m547xevb/m547xevb.c b/roms/u-boot/board/freescale/m547xevb/m547xevb.c
new file mode 100644
index 000000000..1568f455e
--- /dev/null
+++ b/roms/u-boot/board/freescale/m547xevb/m547xevb.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5475 EVB\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	siu_t *siu = (siu_t *) (MMAP_SIU);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+#ifdef CONFIG_SYS_DRAMSZ1
+	u32 temp;
+#endif
+
+	out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
+
+	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+	out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
+
+#ifdef CONFIG_SYS_DRAMSZ1
+	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (temp == (1 << i))
+			break;
+	}
+	i--;
+	dramsize += temp;
+	out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
+#endif
+
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+	/* Issue PALL */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Issue LEMR */
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
+
+	udelay(100);
+
+	gd->ram_size = dramsize;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf547x_8x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+	pci_mcf547x_8x_init(&hose);
+}
+#endif				/* CONFIG_PCI */
diff --git a/roms/u-boot/board/freescale/m548xevb/Kconfig b/roms/u-boot/board/freescale/m548xevb/Kconfig
new file mode 100644
index 000000000..da924e3ce
--- /dev/null
+++ b/roms/u-boot/board/freescale/m548xevb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5485EVB
+
+config SYS_CPU
+	default "mcf547x_8x"
+
+config SYS_BOARD
+	default "m548xevb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M5485EVB"
+
+endif
diff --git a/roms/u-boot/board/freescale/m548xevb/MAINTAINERS b/roms/u-boot/board/freescale/m548xevb/MAINTAINERS
new file mode 100644
index 000000000..4e642e69d
--- /dev/null
+++ b/roms/u-boot/board/freescale/m548xevb/MAINTAINERS
@@ -0,0 +1,13 @@
+M548XEVB BOARD
+M:	TsiChung Liew <Tsi-Chung.Liew@nxp.com>
+S:	Maintained
+F:	board/freescale/m548xevb/
+F:	include/configs/M5485EVB.h
+F:	configs/M5485AFE_defconfig
+F:	configs/M5485BFE_defconfig
+F:	configs/M5485CFE_defconfig
+F:	configs/M5485DFE_defconfig
+F:	configs/M5485EFE_defconfig
+F:	configs/M5485FFE_defconfig
+F:	configs/M5485GFE_defconfig
+F:	configs/M5485HFE_defconfig
diff --git a/roms/u-boot/board/freescale/m548xevb/Makefile b/roms/u-boot/board/freescale/m548xevb/Makefile
new file mode 100644
index 000000000..05bfaa337
--- /dev/null
+++ b/roms/u-boot/board/freescale/m548xevb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m548xevb.o
diff --git a/roms/u-boot/board/freescale/m548xevb/m548xevb.c b/roms/u-boot/board/freescale/m548xevb/m548xevb.c
new file mode 100644
index 000000000..b62355a7a
--- /dev/null
+++ b/roms/u-boot/board/freescale/m548xevb/m548xevb.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5485 EVB\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	siu_t *siu = (siu_t *) (MMAP_SIU);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+#ifdef CONFIG_SYS_DRAMSZ1
+	u32 temp;
+#endif
+
+	out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
+
+	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+	out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
+
+#ifdef CONFIG_SYS_DRAMSZ1
+	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (temp == (1 << i))
+			break;
+	}
+	i--;
+	dramsize += temp;
+	out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
+#endif
+
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+	/* Issue PALL */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Issue LEMR */
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
+
+	udelay(100);
+
+	gd->ram_size = dramsize;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf547x_8x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+	pci_mcf547x_8x_init(&hose);
+}
+#endif				/* CONFIG_PCI */
diff --git a/roms/u-boot/board/freescale/mpc8313erdb/Kconfig b/roms/u-boot/board/freescale/mpc8313erdb/Kconfig
new file mode 100644
index 000000000..b6332a136
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8313erdb/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_MPC8313ERDB_NOR
+
+config SYS_BOARD
+	default "mpc8313erdb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "MPC8313ERDB_NOR"
+
+endif
+
+if TARGET_MPC8313ERDB_NAND
+
+config SYS_BOARD
+	default "mpc8313erdb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "MPC8313ERDB_NAND"
+
+endif
diff --git a/roms/u-boot/board/freescale/mpc8313erdb/MAINTAINERS b/roms/u-boot/board/freescale/mpc8313erdb/MAINTAINERS
new file mode 100644
index 000000000..807fb0b6e
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8313erdb/MAINTAINERS
@@ -0,0 +1,9 @@
+MPC8313ERDB BOARD
+#M:	-
+S:	Maintained
+F:	board/freescale/mpc8313erdb/
+F:	include/configs/MPC8313ERDB.h
+F:	configs/MPC8313ERDB_33_defconfig
+F:	configs/MPC8313ERDB_66_defconfig
+F:	configs/MPC8313ERDB_NAND_33_defconfig
+F:	configs/MPC8313ERDB_NAND_66_defconfig
diff --git a/roms/u-boot/board/freescale/mpc8313erdb/Makefile b/roms/u-boot/board/freescale/mpc8313erdb/Makefile
new file mode 100644
index 000000000..af600ccdb
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8313erdb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= mpc8313erdb.o sdram.o
diff --git a/roms/u-boot/board/freescale/mpc8313erdb/README b/roms/u-boot/board/freescale/mpc8313erdb/README
new file mode 100644
index 000000000..697cee4c4
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8313erdb/README
@@ -0,0 +1,111 @@
+Freescale MPC8313ERDB Board
+-----------------------------------------
+
+1.	Board Switches and Jumpers
+
+	S3 is used to set CONFIG_SYS_RESET_SOURCE.
+
+	To boot the image at 0xFE000000 in NOR flash, use these DIP
+	switch settings for S3 S4:
+
+	+------+	+------+
+	|      |	| **** |
+	| **** |	|      |
+	+------+ ON	+------+ ON
+	  4321		  4321
+	(where the '*' indicates the position of the tab of the switch.)
+
+	To boot the image at the beginning of NAND flash, use these
+	DIP switch settings for S3 S4:
+
+	+------+	+------+
+	| *    |	|  *** |
+	|  *** |	| *    |
+	+------+ ON	+------+ ON
+	  4321		  4321
+	(where the '*' indicates the position of the tab of the switch.)
+
+	When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
+
+2.	Memory Map
+	The memory map looks like this:
+
+	0x0000_0000	0x07ff_ffff	DDR		 128M
+	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
+	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
+	0xe000_0000	0xe00f_ffff	IMMR		 1M
+	0xe200_0000	0xe20f_ffff	PCI IO		 16M
+	0xe280_0000	0xe280_7fff	NAND FLASH (CS1) 32K
+	0xf000_0000	0xf001_ffff	VSC7385 (CS2)	 128K
+	0xfa00_0000	0xfa00_7fff	Board Status/	 32K
+					LED Control (CS3)
+	0xfe00_0000	0xfe7f_ffff	NOR FLASH (CS0)	 8M
+
+	When booting from NAND, NAND flash is CS0 and NOR flash
+	is CS1.
+
+3.	Definitions
+
+3.1	Explanation of NEW definitions in:
+
+	include/configs/MPC8313ERDB.h
+
+	CONFIG_MPC83xx		MPC83xx family
+	CONFIG_MPC831x		MPC831x specific
+	CONFIG_MPC8313ERDB	MPC8313ERDB board specific
+
+4.	Compilation
+
+	Assuming you're using BASH (or similar) as your shell:
+
+	export CROSS_COMPILE=your-cross-compiler-prefix-
+	make distclean
+	make MPC8313ERDB_XXX_config
+	(where XXX is:
+	   33 - 33 MHz oscillator, boot from NOR flash
+	   66 - 66 MHz oscillator, boot from NOR flash
+	   NAND_33 - 33 MHz oscillator, boot from NAND flash
+	   NAND_66 - 66 MHz oscillator, boot from NAND flash)
+	make
+
+5.	Downloading and Flashing Images
+
+5.1	Reflash U-Boot Image using U-Boot
+
+	NOR flash:
+
+	=>run tftpflash
+
+	You may want to try
+	=>tftpboot $loadaddr $uboot
+	first, to make sure that the TFTP load will succeed before it
+	goes ahead and wipes out your current firmware.  And of course,
+	have an alternate means of programming the flash available
+	if the new U-Boot doesn't boot.
+
+	NAND flash:
+
+	=>tftpboot $loadaddr <filename>
+	=>nand erase 0 0x80000
+	=>nand write $loadaddr 0 0x80000
+
+	...where 0x80000 is the filesize rounded up to
+	the next 0x20000 increment.
+
+5.2	Downloading and Booting Linux Kernel
+
+	Ensure that all networking-related environment variables are set
+	properly (including ipaddr, serverip, gatewayip (if needed),
+	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
+	fdtfile, and bootfile).
+
+	Then, do one of the following, depending on whether you
+	want an NFS root or a ramdisk root:
+
+	=>run nfsboot
+	or
+	=>run ramboot
+
+6	Notes
+
+	The console baudrate for MPC8313ERDB is 115200bps.
diff --git a/roms/u-boot/board/freescale/mpc8313erdb/mpc8313erdb.c b/roms/u-boot/board/freescale/mpc8313erdb/mpc8313erdb.c
new file mode 100644
index 000000000..3bf5cff1e
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <fdt_support.h>
+#include <init.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <linux/libfdt.h>
+#endif
+#include <pci.h>
+#include <mpc83xx.h>
+#include <vsc7385.h>
+#include <ns16550.h>
+#include <nand.h>
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
+#include <asm/gpio.h>
+#endif
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		gd->flags |= GD_FLG_SILENT;
+#endif
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
+	mpc83xx_gpio_init_f();
+#endif
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
+	mpc83xx_gpio_init_r();
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC8313ERDB\n");
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static struct pci_region pci_regions[] = {
+	{
+		.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
+		.size = CONFIG_SYS_PCI1_MEM_SIZE,
+		.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		.bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
+		.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
+		.size = CONFIG_SYS_PCI1_MMIO_SIZE,
+		.flags = PCI_REGION_MEM
+	},
+	{
+		.bus_start = CONFIG_SYS_PCI1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCI1_IO_PHYS,
+		.size = CONFIG_SYS_PCI1_IO_SIZE,
+		.flags = PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci_regions };
+
+	/* Enable all 3 PCI_CLK_OUTPUTs. */
+	clk->occr |= 0xe0000000;
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	mpc83xx_pci_init(1, reg);
+}
+
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+	int rc = 0;
+
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		rc = 1;
+	}
+#endif
+
+	return rc;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
+#endif
+#else /* CONFIG_SPL_BUILD */
+void board_init_f(ulong bootflag)
+{
+	board_early_init_f();
+	ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500),
+		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+	puts("NAND boot... ");
+	timer_init();
+	dram_init();
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
+		      CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+
+	if (c == '\n')
+		ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r');
+
+	ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c);
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mpc8313erdb/sdram.c b/roms/u-boot/board/freescale/mpc8313erdb/sdram.c
new file mode 100644
index 000000000..f146ae5d4
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8313erdb/sdram.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Authors: Nick.Spence@freescale.com
+ *          Wilson.Lo@freescale.com
+ *          scottwood@freescale.com
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+static void resume_from_sleep(void)
+{
+	u32 magic = *(u32 *)0;
+
+	typedef void (*func_t)(void);
+	func_t resume = *(func_t *)4;
+
+	if (magic == 0xf5153ae5)
+		resume();
+
+	gd->flags &= ~GD_FLG_SILENT;
+	puts("\nResume from sleep failed: bad magic word\n");
+}
+#endif
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	u32 msize_log2 = __ilog2(msize);
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	__udelay(50000);
+
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+	im->ddr.csbnds[0].csbnds =
+		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+			CSBNDS_EA);
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+	/* Currently we use only one CS, so disable the other bank. */
+	im->ddr.cs_config[1] = 0;
+
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
+	else
+#endif
+		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
+
+	im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
+
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	sync();
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+#endif
+
+	return msize;
+}
+
+int dram_init(void)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile fsl_lbc_t *lbc = &im->im_lbc;
+	u32 msize;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -ENXIO;
+
+	/* DDR SDRAM - Main SODIMM */
+	msize = fixed_sdram();
+
+	/* Local Bus setup lbcr and mrtpr */
+	lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
+	/* LB refresh timer prescal, 266MHz/32 */
+	lbc->mrtpr = 0x20000000;
+	sync();
+
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		resume_from_sleep();
+#endif
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/mpc8315erdb/Kconfig b/roms/u-boot/board/freescale/mpc8315erdb/Kconfig
new file mode 100644
index 000000000..f76b0d1d6
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8315erdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8315ERDB
+
+config SYS_BOARD
+	default "mpc8315erdb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "MPC8315ERDB"
+
+endif
diff --git a/roms/u-boot/board/freescale/mpc8315erdb/MAINTAINERS b/roms/u-boot/board/freescale/mpc8315erdb/MAINTAINERS
new file mode 100644
index 000000000..cdac1ac2e
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8315erdb/MAINTAINERS
@@ -0,0 +1,7 @@
+MPC8315ERDB BOARD
+#M:	Dave Liu <daveliu@freescale.com>
+S:	Orphan (since 2018-05)
+F:	board/freescale/mpc8315erdb/
+F:	include/configs/MPC8315ERDB.h
+F:	configs/MPC8315ERDB_defconfig
+F:	configs/MPC8315ERDB_NANDSPL_defconfig
diff --git a/roms/u-boot/board/freescale/mpc8315erdb/Makefile b/roms/u-boot/board/freescale/mpc8315erdb/Makefile
new file mode 100644
index 000000000..579181999
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8315erdb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= mpc8315erdb.o sdram.o
diff --git a/roms/u-boot/board/freescale/mpc8315erdb/README b/roms/u-boot/board/freescale/mpc8315erdb/README
new file mode 100644
index 000000000..8ad6d810c
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8315erdb/README
@@ -0,0 +1,105 @@
+Freescale MPC8315ERDB Board
+-----------------------------------------
+
+1.	Board Switches and Jumpers
+
+	S3 is used to set CONFIG_SYS_RESET_SOURCE.
+
+	To boot the image at 0xFE000000 in NOR flash, use these DIP
+	switch settings for S3 S4:
+
+	+------+	+------+
+	|      |	| **** |
+	| **** |	|      |
+	+------+ ON	+------+ ON
+	  4321		  4321
+	(where the '*' indicates the position of the tab of the switch.)
+
+	To boot the image at the beginning of NAND flash, use these
+	DIP switch settings for S3 S4:
+
+	+------+	+------+
+	| *    |	|  *** |
+	|  *** |	| *    |
+	+------+ ON	+------+ ON
+	  4321		  4321
+	(where the '*' indicates the position of the tab of the switch.)
+
+	When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
+
+2.	Memory Map
+	The memory map looks like this:
+
+	0x0000_0000	0x07ff_ffff	DDR		 128M
+	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
+	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
+	0xe000_0000	0xe00f_ffff	IMMR		 1M
+	0xe030_0000	0xe03f_ffff	PCI IO		 1M
+	0xe060_0000	0xe060_7fff	NAND FLASH (CS1) 32K
+	0xfe00_0000	0xfe7f_ffff	NOR FLASH (CS0)	 8M
+
+	When booting from NAND, NAND flash is CS0 and NOR flash
+	is CS1.
+
+3.	Definitions
+
+3.1	Explanation of NEW definitions in:
+
+	include/configs/MPC8315ERDB.h
+
+	CONFIG_MPC83xx		MPC83xx family
+	CONFIG_MPC831x		MPC831x specific
+	CONFIG_MPC8315		MPC8315 specific
+	CONFIG_MPC8315ERDB	MPC8315ERDB board specific
+
+4.	Compilation
+
+	Assuming you're using BASH (or similar) as your shell:
+
+	export CROSS_COMPILE=your-cross-compiler-prefix-
+	make distclean
+	make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
+	make all
+
+5.	Downloading and Flashing Images
+
+5.1	Reflash U-Boot Image using U-Boot
+
+	NOR flash:
+
+	tftp 40000 u-boot.bin
+	protect off all
+	erase fe000000 fe1fffff
+
+	cp.b 40000 fe000000 xxxx
+	protect on all
+
+	You have to supply the correct byte count with 'xxxx'
+	from the TFTP result log.
+
+	NAND flash:
+
+	=>tftpboot $loadaddr <filename>
+	=>nand erase 0 0x80000
+	=>nand write $loadaddr 0 0x80000
+
+	...where 0x80000 is the filesize rounded up to
+	the next 0x20000 increment.
+
+5.2	Downloading and Booting Linux Kernel
+
+	Ensure that all networking-related environment variables are set
+	properly (including ipaddr, serverip, gatewayip (if needed),
+	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
+	fdtfile, and bootfile).
+
+	Then, do one of the following, depending on whether you
+	want an NFS root or a ramdisk root:
+
+	=>run nfsboot
+	or
+	=>run ramboot
+
+6	Notes
+
+	The console baudrate for MPC8315ERDB is 115200bps.
diff --git a/roms/u-boot/board/freescale/mpc8315erdb/mpc8315erdb.c b/roms/u-boot/board/freescale/mpc8315erdb/mpc8315erdb.c
new file mode 100644
index 000000000..e89d5d495
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *         Dave Liu <daveliu@freescale.com>
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		gd->flags |= GD_FLG_SILENT;
+
+	return 0;
+}
+
+#ifndef CONFIG_NAND_SPL
+
+static u8 read_board_info(void)
+{
+	u8 val8;
+	i2c_set_bus_num(0);
+
+	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
+		return val8;
+	else
+		return 0;
+}
+
+int checkboard(void)
+{
+	static const char * const rev_str[] = {
+		"0.0",
+		"0.1",
+		"1.0",
+		"1.1",
+		"<unknown>",
+	};
+	u8 info;
+	int i;
+
+	info = read_board_info();
+	i = (!info) ? 4: info & 0x03;
+
+	printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
+
+	return 0;
+}
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+		size: CONFIG_SYS_PCI_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+		size: CONFIG_SYS_PCI_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI_IO_BASE,
+		phys_start: CONFIG_SYS_PCI_IO_PHYS,
+		size: CONFIG_SYS_PCI_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+static struct pci_region pcie_regions_1[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+		.size = CONFIG_SYS_PCIE2_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile sysconf83xx_t *sysconf = &immr->sysconf;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *reg[] = { pci_regions };
+	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+
+	/* Enable all 3 PCI_CLK_OUTPUTs. */
+	clk->occr |= 0xe0000000;
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	mpc83xx_pci_init(1, reg);
+
+	/* Configure the clock for PCIE controller */
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	out_be32(&sysconf->pecr2, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(2, pcie_reg);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_tsec1_fixup(void *fdt, struct bd_info *bd)
+{
+	const char disabled[] = "disabled";
+	const char *path;
+	int ret;
+
+	if (hwconfig_arg_cmp("board_type", "tsec1")) {
+		return;
+	} else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
+		printf("NOTICE: No or unknown board_type hwconfig specified.\n"
+		       "        Assuming board with TSEC1.\n");
+		return;
+	}
+
+	ret = fdt_path_offset(fdt, "/aliases");
+	if (ret < 0) {
+		printf("WARNING: can't find /aliases node\n");
+		return;
+	}
+
+	path = fdt_getprop(fdt, ret, "ethernet0", NULL);
+	if (!path) {
+		printf("WARNING: can't find ethernet0 alias\n");
+		return;
+	}
+
+	do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+	fsl_fdt_fixup_dr_usb(blob, bd);
+	fdt_tsec1_fixup(blob, bd);
+
+	return 0;
+}
+#endif
+
+int board_eth_init(struct bd_info *bis)
+{
+	cpu_eth_init(bis);	/* Initialize TSECs first */
+	return pci_eth_init(bis);
+}
+
+#else /* CONFIG_NAND_SPL */
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC8315ERDB\n");
+	return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+	board_early_init_f();
+	ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500),
+		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+	puts("NAND boot... ");
+	timer_init();
+	dram_init();
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+		      CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+
+	if (c == '\n')
+		ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r');
+
+	ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c);
+}
+
+#endif /* CONFIG_NAND_SPL */
diff --git a/roms/u-boot/board/freescale/mpc8315erdb/sdram.c b/roms/u-boot/board/freescale/mpc8315erdb/sdram.c
new file mode 100644
index 000000000..ffbb79aae
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8315erdb/sdram.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Authors: Nick.Spence@freescale.com
+ *          Wilson.Lo@freescale.com
+ *          scottwood@freescale.com
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void resume_from_sleep(void)
+{
+	u32 magic = *(u32 *)0;
+
+	typedef void (*func_t)(void);
+	func_t resume = *(func_t *)4;
+
+	if (magic == 0xf5153ae5)
+		resume();
+
+	gd->flags &= ~GD_FLG_SILENT;
+	puts("\nResume from sleep failed: bad magic word\n");
+}
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+static long fixed_sdram(void)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE  & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	__udelay(50000);
+
+	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+	/* Currently we use only one CS, so disable the other bank. */
+	im->ddr.cs_config[1] = 0;
+
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
+	else
+		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	sync();
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	sync();
+
+	return msize;
+}
+#else
+static long fixed_sdram(void)
+{
+	return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+}
+#endif /* CONFIG_SYS_RAMBOOT */
+
+int dram_init(void)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -ENXIO;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		resume_from_sleep();
+
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/mpc8323erdb/Kconfig b/roms/u-boot/board/freescale/mpc8323erdb/Kconfig
new file mode 100644
index 000000000..acf812219
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8323erdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8323ERDB
+
+config SYS_BOARD
+	default "mpc8323erdb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "MPC8323ERDB"
+
+endif
diff --git a/roms/u-boot/board/freescale/mpc8323erdb/MAINTAINERS b/roms/u-boot/board/freescale/mpc8323erdb/MAINTAINERS
new file mode 100644
index 000000000..496ab2af2
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8323erdb/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8323ERDB BOARD
+#M:	Michael Barkowski <michael.barkowski@freescale.com>
+S:	Orphan (since 2018-05)
+F:	board/freescale/mpc8323erdb/
+F:	include/configs/MPC8323ERDB.h
+F:	configs/MPC8323ERDB_defconfig
diff --git a/roms/u-boot/board/freescale/mpc8323erdb/Makefile b/roms/u-boot/board/freescale/mpc8323erdb/Makefile
new file mode 100644
index 000000000..e6f61891d
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8323erdb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= mpc8323erdb.o
diff --git a/roms/u-boot/board/freescale/mpc8323erdb/README b/roms/u-boot/board/freescale/mpc8323erdb/README
new file mode 100644
index 000000000..9a46da078
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8323erdb/README
@@ -0,0 +1,71 @@
+Freescale MPC8323ERDB Board
+-----------------------------------------
+
+1.	Memory Map
+	The memory map looks like this:
+
+	0x0000_0000	0x03ff_ffff	DDR		 64M
+	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
+	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
+	0xe000_0000	0xe00f_ffff	IMMR		 1M
+	0xd000_0000	0xd3ff_ffff	PCI IO		 64M
+	0xfe00_0000	0xfeff_ffff	NOR FLASH (CS0)	 16M
+
+2.	Compilation
+
+	Assuming you're using BASH (or similar) as your shell:
+
+	export CROSS_COMPILE=your-cross-compiler-prefix-
+	make distclean
+	make MPC8323ERDB_config
+	make
+
+3.	Downloading and Flashing Images
+
+3.1	Reflash U-Boot Image using U-Boot
+
+	N.b, have an alternate means of programming
+	the flash available if the new U-Boot doesn't boot.
+
+	First try a:
+
+	tftpboot $loadaddr $uboot
+
+	to make sure that the TFTP load will succeed before
+	an erase goes ahead and wipes out your current firmware.
+	Then do a:
+
+	run tftpflash
+
+	which is a shorter version of the manual sequence:
+
+	tftp $loadaddr u-boot.bin
+	protect off fe000000 +$filesize
+	erase fe000000 +$filesize
+	cp.b $loadaddr fe000000 $filesize
+
+	To keep your old U-Boot's environment variables, do a:
+
+	saveenv
+
+	prior to resetting the board.
+
+3.2	Downloading and Booting Linux Kernel
+
+	Ensure that all networking-related environment variables are set
+	properly (including ipaddr, serverip, gatewayip (if needed),
+	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
+	fdtfile, and bootfile).
+
+	Then, do one of the following, depending on whether you
+	want an NFS root or a ramdisk root:
+
+	run nfsboot
+
+	or
+
+	run ramboot
+
+4	Notes
+
+	The console baudrate for MPC8323ERDB is 115200bps.
diff --git a/roms/u-boot/board/freescale/mpc8323erdb/mpc8323erdb.c b/roms/u-boot/board/freescale/mpc8323erdb/mpc8323erdb.c
new file mode 100644
index 000000000..cef3216a6
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Michael Barkowski <michael.barkowski@freescale.com>
+ * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <eeprom.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <command.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <u-boot/crc.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* UCC3 */
+	{1,  0, 1, 0, 1}, /* TxD0 */
+	{1,  1, 1, 0, 1}, /* TxD1 */
+	{1,  2, 1, 0, 1}, /* TxD2 */
+	{1,  3, 1, 0, 1}, /* TxD3 */
+	{1,  9, 1, 0, 1}, /* TxER */
+	{1, 12, 1, 0, 1}, /* TxEN */
+	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
+
+	{1,  4, 2, 0, 1}, /* RxD0 */
+	{1,  5, 2, 0, 1}, /* RxD1 */
+	{1,  6, 2, 0, 1}, /* RxD2 */
+	{1,  7, 2, 0, 1}, /* RxD3 */
+	{1,  8, 2, 0, 1}, /* RxER */
+	{1, 10, 2, 0, 1}, /* RxDV */
+	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
+	{1, 11, 2, 0, 1}, /* COL */
+	{1, 13, 2, 0, 1}, /* CRS */
+
+	/* UCC2 */
+	{0, 18, 1, 0, 1}, /* TxD0 */
+	{0, 19, 1, 0, 1}, /* TxD1 */
+	{0, 20, 1, 0, 1}, /* TxD2 */
+	{0, 21, 1, 0, 1}, /* TxD3 */
+	{0, 27, 1, 0, 1}, /* TxER */
+	{0, 30, 1, 0, 1}, /* TxEN */
+	{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
+
+	{0, 22, 2, 0, 1}, /* RxD0 */
+	{0, 23, 2, 0, 1}, /* RxD1 */
+	{0, 24, 2, 0, 1}, /* RxD2 */
+	{0, 25, 2, 0, 1}, /* RxD3 */
+	{0, 26, 1, 0, 1}, /* RxER */
+	{0, 28, 2, 0, 1}, /* Rx_DV */
+	{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
+	{0, 29, 2, 0, 1}, /* COL */
+	{0, 31, 2, 0, 1}, /* CRS */
+
+	{3,  4, 3, 0, 2}, /* MDIO */
+	{3,  5, 1, 0, 2}, /* MDC */
+
+	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+int fixed_sdram(void);
+
+int dram_init(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -ENXIO;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
+
+	msize = fixed_sdram();
+
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
+}
+
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].ar =
+	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	__asm__ __volatile__ ("sync");
+	udelay(200);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	__asm__ __volatile__ ("sync");
+	return msize;
+}
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC8323ERDB\n");
+	return 0;
+}
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci_regions };
+
+	/* Enable all 3 PCI_CLK_OUTPUTs. */
+	clk->occr |= 0xe0000000;
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	mpc83xx_pci_init(1, reg);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
+int mac_read_from_eeprom(void)
+{
+	uchar buf[28];
+	char str[18];
+	int i = 0;
+	unsigned int crc = 0;
+	unsigned char enetvar[32];
+
+	/* Read MAC addresses from EEPROM */
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
+		printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
+		       CONFIG_SYS_I2C_EEPROM_ADDR);
+	} else {
+		uint32_t crc_buf;
+
+		memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
+
+		if (crc32(crc, buf, 24) == crc_buf) {
+			printf("Reading MAC from EEPROM\n");
+			for (i = 0; i < 4; i++) {
+				if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
+					sprintf(str,
+						"%02X:%02X:%02X:%02X:%02X:%02X",
+						buf[i * 6], buf[i * 6 + 1],
+						buf[i * 6 + 2], buf[i * 6 + 3],
+						buf[i * 6 + 4], buf[i * 6 + 5]);
+					sprintf((char *)enetvar,
+						i ? "eth%daddr" : "ethaddr", i);
+					env_set((char *)enetvar, str);
+				}
+			}
+		}
+	}
+	return 0;
+}
+#endif				/* CONFIG_I2C_MAC_OFFSET */
diff --git a/roms/u-boot/board/freescale/mpc832xemds/Kconfig b/roms/u-boot/board/freescale/mpc832xemds/Kconfig
new file mode 100644
index 000000000..e4cfa15a6
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc832xemds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC832XEMDS
+
+config SYS_BOARD
+	default "mpc832xemds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "MPC832XEMDS"
+
+endif
diff --git a/roms/u-boot/board/freescale/mpc832xemds/MAINTAINERS b/roms/u-boot/board/freescale/mpc832xemds/MAINTAINERS
new file mode 100644
index 000000000..232658a20
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc832xemds/MAINTAINERS
@@ -0,0 +1,10 @@
+MPC832XEMDS BOARD
+#M:	Dave Liu <daveliu@freescale.com>
+S:	Orphan (since 2018-05)
+F:	board/freescale/mpc832xemds/
+F:	include/configs/MPC832XEMDS.h
+F:	configs/MPC832XEMDS_defconfig
+F:	configs/MPC832XEMDS_ATM_defconfig
+F:	configs/MPC832XEMDS_HOST_33_defconfig
+F:	configs/MPC832XEMDS_HOST_66_defconfig
+F:	configs/MPC832XEMDS_SLAVE_defconfig
diff --git a/roms/u-boot/board/freescale/mpc832xemds/Makefile b/roms/u-boot/board/freescale/mpc832xemds/Makefile
new file mode 100644
index 000000000..b1551bf47
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc832xemds/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y += mpc832xemds.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/roms/u-boot/board/freescale/mpc832xemds/README b/roms/u-boot/board/freescale/mpc832xemds/README
new file mode 100644
index 000000000..d141cd33e
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc832xemds/README
@@ -0,0 +1,128 @@
+Freescale MPC832XEMDS Board
+-----------------------------------------
+1. Board Switches and Jumpers
+1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
+	For some reason, the HW designers describe the switch settings
+	in terms of 0 and 1, and then map that to physical switches where
+	the label "On" refers to logic 0 and "Off" is logic 1.
+
+	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
+	bits may contribute to signals that are numbered based at 0,
+	and some of those signals may be high-bit-number-0 too.  Heed
+	well the names and labels and do not get confused.
+
+		"Off" == 1
+		"On"  == 0
+
+	SW3 is switch 18 as silk-screened onto the board.
+	SW4[8] is the bit labeled 8 on Switch 4.
+	SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
+	SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
+	SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
+		and bits labeled 8 is set as "Off".
+
+1.1 For the MPC832XEMDS PROTO Board
+
+	First, make sure the board default setting is consistent with the document
+		 shipped with your board. Then apply the following setting:
+	SW3[1-8]= 0000_1000  (core PLL setting, core enable)
+	SW4[1-8]= 0001_0010  (Flash boot on local bus, system PLL setting)
+	SW5[1-8]= 0010_0110  (Boot from high end)
+	SW6[1-8]= 0011_0100  (Flash boot on 16 bit local bus)
+	SW7[1-8]= 1000_0011  (QE PLL setting)
+
+	ENET3/4 MII mode settings:
+	J1 1-2 (ETH3_TXER)
+	J2 2-3 (MII mode)
+	J3 2-3 (MII mode)
+	J4 2-3 (ADSL clockOscillator)
+	J5 1-2 (ETH4_TXER)
+	J6 2-3 (ClockOscillator)
+	JP1 removed (don't force PORESET)
+	JP2 mounted (ETH4/2 MII)
+	JP3 mounted (ETH3 MII)
+	JP4 mounted (HRCW from BCSR)
+
+	ENET3/4 RMII mode settings:
+	J1 1-2 (ETH3_TXER)
+	J2 1-2 (RMII mode)
+	J3 1-2 (RMII mode)
+	J4 2-3 (ADSL clockOscillator)
+	J5 1-2 (ETH4_TXER)
+	J6 2-3 (ClockOscillator)
+	JP1 removed (don't force PORESET)
+	JP2 removed (ETH4/2 RMII)
+	JP3 removed (ETH3 RMII)
+	JP4 removed (HRCW from FLASH)
+
+	on board Oscillator: 66M
+
+
+2. Memory Map
+
+2.1 The memory map should look pretty much like this:
+
+	0x0000_0000	0x7fff_ffff	DDR			2G
+	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M
+	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M
+	0xc000_0000	0xdfff_ffff	Empty			512M
+	0xe000_0000	0xe01f_ffff	Int Mem Reg Space	2M
+	0xe020_0000	0xe02f_ffff	Empty			1M
+	0xe030_0000	0xe03f_ffff	PCI IO			1M
+	0xe040_0000	0xefff_ffff	Empty			252M
+	0xf400_0000	0xf7ff_ffff	Empty			64M
+	0xf800_0000	0xf800_7fff	BCSR on CS1		32K
+	0xf800_8000	0xf800_ffff	PIB CS2			32K
+	0xf801_0000	0xf801_7fff	PIB CS3			32K
+	0xfe00_0000	0xfeff_ffff	FLASH on CS0		16M
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+	include/configs/MPC832XEPB.h
+
+    CONFIG_MPC83xx	MPC83xx family for MPC8349, MPC8360 and MPC832x
+    CONFIG_MPC832x	MPC832x specific
+    CONFIG_MPC832XEMDS	MPC832XEMDS board specific
+
+4. Compilation
+
+	Assuming you're using BASH shell:
+
+		export CROSS_COMPILE=your-cross-compile-prefix
+		cd u-boot
+		make distclean
+		make MPC832XEMDS_config
+		make
+
+	MPC832x support PCI 33MHz and PCI 66MHz, to make U-Boot support PCI:
+
+		1)Make sure the DIP SW support PCI mode as described in Section 1.1.
+
+		2)To Make U-Boot image support PCI 33MHz, use
+			Make MPC832XEMDS_HOST_33_config
+
+		3)To Make U-Boot image support PCI 66MHz, use
+			Make MPC832XEMDS_HOST_66M_config
+
+5. Downloading and Flashing Images
+
+5.0 Download over network:
+
+	tftp 10000 u-boot.bin
+
+5.1 Reflash U-Boot Image using U-Boot
+
+	tftp 20000 u-boot.bin
+	protect off fe000000 fe0fffff
+	erase fe000000 fe0fffff
+	cp.b 20000 fe000000 xxxx
+
+You have to supply the correct byte count with 'xxxx' from the TFTP result log.
+Maybe 3ffff will work too, that corresponds to the erased sectors.
+
+
+6. Notes
+	1) The console baudrate for MPC832XEMDS is 115200bps.
diff --git a/roms/u-boot/board/freescale/mpc832xemds/mpc832xemds.c b/roms/u-boot/board/freescale/mpc832xemds/mpc832xemds.c
new file mode 100644
index 000000000..f34758a94
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc832xemds/mpc832xemds.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <command.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#include <asm/global_data.h>
+#include <asm/mmu.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <linux/libfdt.h>
+#endif
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
+#endif
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* ETH3 */
+	{1,  0, 1, 0, 1}, /* TxD0 */
+	{1,  1, 1, 0, 1}, /* TxD1 */
+	{1,  2, 1, 0, 1}, /* TxD2 */
+	{1,  3, 1, 0, 1}, /* TxD3 */
+	{1,  9, 1, 0, 1}, /* TxER */
+	{1, 12, 1, 0, 1}, /* TxEN */
+	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
+
+	{1,  4, 2, 0, 1}, /* RxD0 */
+	{1,  5, 2, 0, 1}, /* RxD1 */
+	{1,  6, 2, 0, 1}, /* RxD2 */
+	{1,  7, 2, 0, 1}, /* RxD3 */
+	{1,  8, 2, 0, 1}, /* RxER */
+	{1, 10, 2, 0, 1}, /* RxDV */
+	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
+	{1, 11, 2, 0, 1}, /* COL */
+	{1, 13, 2, 0, 1}, /* CRS */
+
+	/* ETH4 */
+	{1, 18, 1, 0, 1}, /* TxD0 */
+	{1, 19, 1, 0, 1}, /* TxD1 */
+	{1, 20, 1, 0, 1}, /* TxD2 */
+	{1, 21, 1, 0, 1}, /* TxD3 */
+	{1, 27, 1, 0, 1}, /* TxER */
+	{1, 30, 1, 0, 1}, /* TxEN */
+	{3,  6, 2, 0, 1}, /* TxCLK->CLK8 */
+
+	{1, 22, 2, 0, 1}, /* RxD0 */
+	{1, 23, 2, 0, 1}, /* RxD1 */
+	{1, 24, 2, 0, 1}, /* RxD2 */
+	{1, 25, 2, 0, 1}, /* RxD3 */
+	{1, 26, 1, 0, 1}, /* RxER */
+	{1, 28, 2, 0, 1}, /* Rx_DV */
+	{3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
+	{1, 29, 2, 0, 1}, /* COL */
+	{1, 31, 2, 0, 1}, /* CRS */
+
+	{3,  4, 3, 0, 2}, /* MDIO */
+	{3,  5, 1, 0, 2}, /* MDC */
+
+	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+int board_early_init_f(void)
+{
+	volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
+
+	/* Enable flash write */
+	bcsr[9] &= ~0x08;
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_PQ_MDS_PIB
+	pib_init();
+#endif
+	return 0;
+}
+
+int fixed_sdram(void);
+
+int dram_init(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -ENXIO;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
+
+	msize = fixed_sdram();
+
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
+}
+
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].ar =
+	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+#if (CONFIG_SYS_DDR_SIZE != 128)
+#warning Currenly any ddr size other than 128 is not supported
+#endif
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	__asm__ __volatile__ ("sync");
+	udelay(200);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	__asm__ __volatile__ ("sync");
+	return msize;
+}
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC832XEMDS\n");
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mpc832xemds/pci.c b/roms/u-boot/board/freescale/mpc832xemds/pci.c
new file mode 100644
index 000000000..944108f63
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc832xemds/pci.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * PCI Configuration space access support for MPC83xx PCI Bridge
+ */
+#include <init.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+#include <linux/delay.h>
+#include "../common/pq-mds-pib.h"
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+		size: CONFIG_SYS_PCI2_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI2_IO_BASE,
+		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+		size: CONFIG_SYS_PCI2_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+		size: CONFIG_SYS_PCI2_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+#endif
+
+void pci_init_board(void)
+#ifdef CONFIG_PCISLAVE
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+	struct pci_region *reg[] = { pci1_regions };
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	mpc83xx_pci_init(1, reg);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+	pci_ctrl[0].pitar0 = 0x0;
+	pci_ctrl[0].pibar0 = 0x0;
+	pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
+	    PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
+
+	pci_ctrl[0].pitar1 = 0x0;
+	pci_ctrl[0].pibar1 = 0x0;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 &= ~PIWAR_EN;
+
+	pci_ctrl[0].pitar2 = 0x0;
+	pci_ctrl[0].pibar2 = 0x0;
+	pci_ctrl[0].piebar2 = 0x0;
+	pci_ctrl[0].piwar2 &= ~PIWAR_EN;
+
+	/* Unlock the configuration bit */
+	mpc83xx_pcislave_unlock(0);
+	printf("PCI:   Agent mode enabled\n");
+}
+#else
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+	struct pci_region *reg[] = { pci1_regions };
+#else
+	struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
+
+	/* initialize the PCA9555PW IO expander on the PIB board */
+	pib_init();
+
+#if defined(CONFIG_PCI_66M)
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+	printf("PCI clock is 66MHz\n");
+#elif defined(CONFIG_PCI_33M)
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
+	    OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
+	printf("PCI clock is 33MHz\n");
+#else
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+	printf("PCI clock is 66MHz\n");
+#endif
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
+
+	udelay(2000);
+
+#ifndef CONFIG_MPC83XX_PCI2
+	mpc83xx_pci_init(1, reg);
+#else
+	mpc83xx_pci_init(2, reg);
+#endif
+}
+#endif				/* CONFIG_PCISLAVE */
diff --git a/roms/u-boot/board/freescale/mpc8349emds/Kconfig b/roms/u-boot/board/freescale/mpc8349emds/Kconfig
new file mode 100644
index 000000000..d15411807
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8349emds/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_MPC8349EMDS
+
+config SYS_BOARD
+	default "mpc8349emds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "MPC8349EMDS"
+
+endif
+
+if TARGET_MPC8349EMDS_SDRAM
+
+config SYS_BOARD
+	default "mpc8349emds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "MPC8349EMDS_SDRAM"
+
+endif
diff --git a/roms/u-boot/board/freescale/mpc8349emds/MAINTAINERS b/roms/u-boot/board/freescale/mpc8349emds/MAINTAINERS
new file mode 100644
index 000000000..a8f26a9a3
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8349emds/MAINTAINERS
@@ -0,0 +1,9 @@
+MPC8349EMDS BOARD
+#M:	Kim Phillips <kim.phillips@freescale.com>
+S:	Orphan (since 2018-05)
+F:	board/freescale/mpc8349emds/
+F:	include/configs/MPC8349EMDS.h
+F:	configs/MPC8349EMDS_defconfig
+F:	configs/MPC8349EMDS_SDRAM_defconfig
+F:	configs/MPC8349EMDS_PCI64_defconfig
+F:	configs/MPC8349EMDS_SLAVE_defconfig
diff --git a/roms/u-boot/board/freescale/mpc8349emds/Makefile b/roms/u-boot/board/freescale/mpc8349emds/Makefile
new file mode 100644
index 000000000..af02f65cb
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8349emds/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y += mpc8349emds.o
+obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/roms/u-boot/board/freescale/mpc8349emds/ddr.c b/roms/u-boot/board/freescale/mpc8349emds/ddr.c
new file mode 100644
index 000000000..ac5ddc6d9
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8349emds/ddr.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 clk_adjust;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2t;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi|  clk| cpo|wrdata|2T
+	 * ranks| mhz|adjst|    | delay|
+	 */
+	{2,  300,    4,   4,    2,  0},
+	{2,  365,    4,   6,    2,  0},
+	{2,  450,    4,   7,    2,  0},
+	{2,  850,    4,  31,    2,  0},
+	{1,  300,    4,   4,    2,  0},
+	{1,  365,    4,   6,    2,  0},
+	{1,  450,    4,   7,    2,  0},
+	{1,  850,    4,  31,    2,  0},
+	{}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	unsigned int i;
+	ulong ddr_freq;
+
+	if (ctrl_num != 0)	/* we have only one controller */
+		return;
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (pdimm[i].n_ranks)
+			break;
+	}
+	if (i >= CONFIG_DIMM_SLOTS_PER_CTLR)	/* no DIMM */
+		return;
+
+	pbsp = udimm0;
+
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks ==  pdimm[i].n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->cpo_override = pbsp->cpo;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				popts->twot_en = pbsp->force_2t;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found "
+			"for data rate %lu MT/s!\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->cpo_override = pbsp_highest->cpo;
+		popts->write_data_delay = pbsp_highest->write_data_delay;
+		popts->twot_en = pbsp_highest->force_2t;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+
+found:
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	popts->dqs_config = 0;	/* only true DQS signal is used on board */
+}
diff --git a/roms/u-boot/board/freescale/mpc8349emds/mpc8349emds.c b/roms/u-boot/board/freescale/mpc8349emds/mpc8349emds.c
new file mode 100644
index 000000000..5f38639af
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8349emds/mpc8349emds.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/bitops.h>
+#include <asm/global_data.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spi.h>
+#include <miiphy.h>
+#ifdef CONFIG_SYS_FSL_DDR2
+#include <fsl_ddr_sdram.h>
+#else
+#include <spd_sdram.h>
+#endif
+#include <linux/delay.h>
+
+#if defined(CONFIG_OF_LIBFDT)
+#include <linux/libfdt.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fixed_sdram(void);
+void sdram_init(void);
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+int board_early_init_f (void)
+{
+	volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
+
+	/* Enable flash write */
+	bcsr[1] &= ~0x01;
+
+#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
+	/* Use USB PHY on SYS board */
+	bcsr[5] |= 0x02;
+#endif
+
+	return 0;
+}
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+int dram_init(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	phys_size_t msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -ENXIO;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+#ifndef CONFIG_SYS_FSL_DDR2
+	msize = spd_sdram() * 1024 * 1024;
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	ddr_enable_ecc(msize);
+#endif
+#else
+	msize = fsl_ddr_sdram();
+#endif
+#else
+	msize = fixed_sdram() * 1024 * 1024;
+#endif
+	/*
+	 * Initialize SDRAM if it is on local bus.
+	 */
+	sdram_init();
+
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE;
+	u32 ddr_size = msize << 20;	/* DDR size in bytes */
+	u32 ddr_size_log2 = __ilog2(ddr_size);
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+#if (CONFIG_SYS_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+#ifdef CONFIG_DDR_II
+	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+#else
+
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+	im->ddr.csbnds[2].csbnds =
+		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
+				CSBNDS_EA_SHIFT) & CSBNDS_EA);
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
+
+	/* currently we use only one CS, so disable the other banks */
+	im->ddr.cs_config[0] = 0;
+	im->ddr.cs_config[1] = 0;
+	im->ddr.cs_config[3] = 0;
+
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+
+	im->ddr.sdram_cfg =
+		SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+		| SDRAM_CFG_2T_EN
+#endif
+		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+#if defined (CONFIG_DDR_32BIT)
+	/* for 32-bit mode burst length is 8 */
+	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+#endif
+	udelay(200);
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	return msize;
+}
+#endif/*!CONFIG_SYS_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+	/*
+	 * Warning: do not read the BCSR registers here
+	 *
+	 * There is a timing bug in the 8349E and 8349EA BCSR code
+	 * version 1.2 (read from BCSR 11) that will cause the CFI
+	 * flash initialization code to overwrite BCSR 0, disabling
+	 * the serial ports and gigabit ethernet
+	 */
+
+	puts("Board: Freescale MPC8349EMDS\n");
+	return 0;
+}
+
+/*
+ * if MPC8349EMDS is soldered with SDRAM
+ */
+#if defined(CONFIG_SYS_BR2_PRELIM)  \
+	&& defined(CONFIG_SYS_OR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+				 LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+				 LSDMR_WRC3 | LSDMR_CL3;
+	/*
+	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+	 */
+
+	/* setup mtrpt, lsrt and lbcr for LB bus */
+	lbc->lbcr = 0x00000000;
+	/* LB refresh timer prescal, 266MHz/32 */
+	lbc->mrtpr = 0x20000000;
+	/* LB sdram refresh timer, about 6us */
+	lbc->lsrt = 0x32000000;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller Machine Mode Register.
+	 */
+
+	/* 0x40636733; normal operation */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+
+	/* 0x68636733; precharge all the banks */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/* 0x48636733; auto refresh */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+	asm("sync");
+	/*1 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*2 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*3 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*4 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*5 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*6 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*7 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*8 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/* 0x58636733; mode register write operation */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/* 0x40636733; normal operation */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+}
+#else
+void sdram_init(void)
+{
+}
+#endif
+
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+
+#define SPI_CS_MASK	0x80000000
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+
+	iopd->dat &= ~SPI_CS_MASK;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+
+	iopd->dat |=  SPI_CS_MASK;
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mpc8349emds/pci.c b/roms/u-boot/board/freescale/mpc8349emds/pci.c
new file mode 100644
index 000000000..3ddbe7177
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8349emds/pci.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ */
+
+#include <init.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+#include <linux/delay.h>
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+		size: CONFIG_SYS_PCI2_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI2_IO_BASE,
+		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+		size: CONFIG_SYS_PCI2_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+		size: CONFIG_SYS_PCI2_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+#endif
+
+#ifndef CONFIG_PCISLAVE
+void pib_init(void)
+{
+	u8 val8, orig_i2c_bus;
+	/*
+	 * Assign PIB PMC slot to desired PCI bus
+	 */
+	/* Switch temporarily to I2C bus #2 */
+	orig_i2c_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	val8 = 0;
+	i2c_write(0x23, 0x6, 1, &val8, 1);
+	i2c_write(0x23, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x23, 0x2, 1, &val8, 1);
+	i2c_write(0x23, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x26, 0x6, 1, &val8, 1);
+	val8 = 0x34;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+#if defined(CONFIG_PCI_64BIT)
+	val8 = 0xf4;	/* PMC2:PCI1/64-bit */
+#elif defined(CONFIG_PCI_ALL_PCI1)
+	val8 = 0xf3;	/* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
+#elif defined(CONFIG_PCI_ONE_PCI1)
+	val8 = 0xf9;	/* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
+#else
+	val8 = 0xf5;	/* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
+#endif
+	i2c_write(0x26, 0x2, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+	val8 = 0;
+	i2c_write(0x27, 0x6, 1, &val8, 1);
+	i2c_write(0x27, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x27, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x27, 0x3, 1, &val8, 1);
+	asm("eieio");
+
+#if defined(CONFIG_PCI_64BIT)
+	printf("PCI1: 64-bit on PMC2\n");
+#elif defined(CONFIG_PCI_ALL_PCI1)
+	printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
+#elif defined(CONFIG_PCI_ONE_PCI1)
+	printf("PCI1: 32-bit on PMC1\n");
+	printf("PCI2: 32-bit on PMC2, PMC3\n");
+#else
+	printf("PCI1: 32-bit on PMC1, PMC2\n");
+	printf("PCI2: 32-bit on PMC3\n");
+#endif
+	/* Reset to original I2C bus */
+	i2c_set_bus_num(orig_i2c_bus);
+}
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+	struct pci_region *reg[] = { pci1_regions };
+#else
+	struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
+
+	/* initialize the PCA9555PW IO expander on the PIB board */
+	pib_init();
+
+	/* Enable all 8 PCI_CLK_OUTPUTS */
+	clk->occr = 0xff000000;
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	udelay(2000);
+
+#ifndef CONFIG_MPC83XX_PCI2
+	mpc83xx_pci_init(1, reg);
+#else
+	mpc83xx_pci_init(2, reg);
+#endif
+}
+
+#else
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+	struct pci_region *reg[] = { pci1_regions };
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	mpc83xx_pci_init(1, reg);
+
+	/* Configure PCI Inbound Translation Windows (3 1MB windows) */
+	pci_ctrl->pitar0 = 0x0;
+	pci_ctrl->pibar0 = 0x0;
+	pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+			   PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
+
+	pci_ctrl->pitar1  = 0x0;
+	pci_ctrl->pibar1  = 0x0;
+	pci_ctrl->piebar1 = 0x0;
+	pci_ctrl->piwar1  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
+
+	pci_ctrl->pitar2  = 0x0;
+	pci_ctrl->pibar2  = 0x0;
+	pci_ctrl->piebar2 = 0x0;
+	pci_ctrl->piwar2  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
+
+	/* Unlock the configuration bit */
+	mpc83xx_pcislave_unlock(0);
+	printf("PCI:   Agent mode enabled\n");
+}
+#endif /* CONFIG_PCISLAVE */
diff --git a/roms/u-boot/board/freescale/mpc837xerdb/Kconfig b/roms/u-boot/board/freescale/mpc837xerdb/Kconfig
new file mode 100644
index 000000000..03415f9fc
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc837xerdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC837XERDB
+
+config SYS_BOARD
+	default "mpc837xerdb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "MPC837XERDB"
+
+endif
diff --git a/roms/u-boot/board/freescale/mpc837xerdb/MAINTAINERS b/roms/u-boot/board/freescale/mpc837xerdb/MAINTAINERS
new file mode 100644
index 000000000..9f44a37a0
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc837xerdb/MAINTAINERS
@@ -0,0 +1,7 @@
+MPC837XERDB BOARD
+M:	Sinan Akman <sinan@writeme.com>
+S:	Maintained
+F:	board/freescale/mpc837xerdb/
+F:	include/configs/MPC837XERDB.h
+F:	configs/MPC837XERDB_defconfig
+F:	configs/MPC837XERDB_SLAVE_defconfig
diff --git a/roms/u-boot/board/freescale/mpc837xerdb/Makefile b/roms/u-boot/board/freescale/mpc837xerdb/Makefile
new file mode 100644
index 000000000..c683b017b
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc837xerdb/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y += mpc837xerdb.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/roms/u-boot/board/freescale/mpc837xerdb/README b/roms/u-boot/board/freescale/mpc837xerdb/README
new file mode 100644
index 000000000..12df2f2e7
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc837xerdb/README
@@ -0,0 +1,97 @@
+Freescale MPC837xE-RDB Board
+-----------------------------------------
+
+1.	Board Description
+
+	The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E,
+	MPC8378E, and the MPC8379E processors in a Mini-ITX form factor.
+
+	The MPC837xE-RDB's have the following common features:
+
+	A) 256-MBytes on-board DDR2 unbuffered SDRAM
+	B) 8-Mbytes NOR Flash
+	C) 32-MBytes NAND Flash
+	D) 1 Secure Digital High Speed Card (SDHC) Interface
+	E) 1 Gigabit Ethernet
+	F) 5-port Ethernet switch (Vitesse 7385)
+	G) 1 32-bit, 3.3 V, PCI slot
+	H) 1 32-bit, 3.3 V, Mini-PCI slot
+	I) 4-port USB 2.0 Hub
+	J) 1-port OTG USB
+	K) 2 serial ports (top main console)
+	L) on board Oscillator: 66M
+
+	The MPC837xE-RDB's have the following differences:
+
+			    MPC8377E-RDB    MPC8378E-RDB    MPC8379E-RDB
+	SATA controllers	2		0		4
+	PCI-Express (mini)	2		2		0
+	SGMII Ports		0		2		0
+
+
+2.	Memory Map
+
+2.1.	The memory map should look pretty much like this:
+
+	Address Range			Device			Size		Port Size
+								(Bytes)		(Bits)
+	===========================	=================	=======		=========
+	0x0000_0000	0x0fff_ffff	DDR			256M		64
+	0x1000_0000	0x7fff_ffff	Empty			1.75G		-
+	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M		32
+	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M		32
+	0xe030_0000	0xe03f_ffff	PCI I/O space		1M		32
+	0xe000_0000	0xe00f_ffff	Int Mem Reg Space	1M		-
+	0xe060_0000	0xe060_7fff	NAND Flash		32K		8
+	0xfe00_0000	0xfe7f_ffff	NOR Flash on CS0	8M		16
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+	include/configs/MPC837XERDB.h
+
+    CONFIG_MPC83xx	    MPC83xx family for both MPC8349 and MPC8360
+    CONFIG_MPC837x	    MPC837x specific
+    CONFIG_MPC837XERDB	    MPC837xE-RDB board specific
+
+
+4. Compilation
+
+	Assuming you're using BASH shell:
+
+		export CROSS_COMPILE=your-cross-compile-prefix
+		cd u-boot
+		make distclean
+		make MPC837XERDB_config
+		make
+
+
+5. Downloading and Flashing Images
+
+5.0 Download over serial line using Kermit:
+
+	loadb $loadaddr
+	[Drop to kermit:
+	    ^\c
+	    send <u-boot-bin-image>
+	    c
+	]
+
+
+	Or via tftp:
+
+	tftp $loadaddr u-boot.bin
+
+5.1 Reflash U-Boot Image using U-Boot
+
+	tftp $loadaddr u-boot.bin
+	protect off fe000000 fe0fffff
+	erase fe000000 fe0fffff
+	cp.b $loadaddr fe000000 $filesize
+
+
+6. Additional Notes:
+	1) The console is connected to the top RS-232 connector and the
+	   baudrate for MPC837XE-RDB is 115200bps.
diff --git a/roms/u-boot/board/freescale/mpc837xerdb/mpc837xerdb.c b/roms/u-boot/board/freescale/mpc837xerdb/mpc837xerdb.c
new file mode 100644
index 000000000..624e92ef9
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Kevin Lam <kevin.lam@freescale.com>
+ * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <init.h>
+#include <asm/bitops.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+#include <fdt_support.h>
+#include <spd_sdram.h>
+#include <vsc7385.h>
+#include <fsl_esdhc.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CONFIG_SYS_MEMTEST_START,
+	       CONFIG_SYS_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+int fixed_sdram(void);
+
+int dram_init(void)
+{
+	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -ENXIO;
+
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/* Initialize DDR ECC byte */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+	/* return total bus DDR size(bytes) */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+	udelay(50000);
+
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+	udelay(1000);
+
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	udelay(1000);
+
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	sync();
+	udelay(1000);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	udelay(2000);
+	return CONFIG_SYS_DDR_SIZE;
+}
+#endif	/*!CONFIG_SYS_SPD_EEPROM */
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC837xERDB\n");
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+#ifdef CONFIG_FSL_SERDES
+	u32 spridr = in_be32(&immr->sysconf.spridr);
+
+	/* we check only part num, and don't look for CPU revisions */
+	switch (PARTID_NO_E(spridr)) {
+	case SPR_8377:
+		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		break;
+	case SPR_8378:
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		break;
+	case SPR_8379:
+		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+		break;
+	default:
+		printf("serdes not configured: unknown CPU part number: "
+		       "%04x\n", spridr >> 16);
+		break;
+	}
+#endif /* CONFIG_FSL_SERDES */
+
+#ifdef CONFIG_FSL_ESDHC
+	clrsetbits_be32(&immr->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
+	clrsetbits_be32(&immr->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+#if !(CONFIG_IS_ENABLED(DM_MMC))
+int board_mmc_init(struct bd_info *bd)
+{
+	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+	char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+	int esdhc_hwconfig_enabled = 0;
+
+	if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
+		esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
+
+	if (esdhc_hwconfig_enabled == 0)
+		return 0;
+
+	clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
+	clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
+
+	return fsl_esdhc_mmc_init(bd);
+}
+#endif
+#endif
+
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+	int rc = 0;
+
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		rc = 1;
+	}
+#endif
+
+	return rc;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
+	fdt_fixup_esdhc(blob, bd);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/roms/u-boot/board/freescale/mpc837xerdb/pci.c b/roms/u-boot/board/freescale/mpc837xerdb/pci.c
new file mode 100644
index 000000000..dccf8c555
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc837xerdb/pci.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+		size: CONFIG_SYS_PCI_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+		size: CONFIG_SYS_PCI_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI_IO_BASE,
+		phys_start: CONFIG_SYS_PCI_IO_PHYS,
+		size: CONFIG_SYS_PCI_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+static struct pci_region pcie_regions_1[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+		.size = CONFIG_SYS_PCIE2_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile sysconf83xx_t *sysconf = &immr->sysconf;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *reg[] = { pci_regions };
+	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+	u32 spridr = in_be32(&immr->sysconf.spridr);
+
+	/* Enable all 5 PCI_CLK_OUTPUTS */
+	clk->occr |= 0xf8000000;
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	mpc83xx_pci_init(1, reg);
+
+	/* There is no PEX in MPC8379 parts. */
+	if (PARTID_NO_E(spridr) == SPR_8379)
+		return;
+
+	/* Configure the clock for PCIE controller */
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	out_be32(&sysconf->pecr2, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(2, pcie_reg);
+}
diff --git a/roms/u-boot/board/freescale/mpc8541cds/Kconfig b/roms/u-boot/board/freescale/mpc8541cds/Kconfig
new file mode 100644
index 000000000..034eab254
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8541cds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8541CDS
+
+config SYS_BOARD
+	default "mpc8541cds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "MPC8541CDS"
+
+endif
diff --git a/roms/u-boot/board/freescale/mpc8541cds/MAINTAINERS b/roms/u-boot/board/freescale/mpc8541cds/MAINTAINERS
new file mode 100644
index 000000000..cf3b9cf5f
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8541cds/MAINTAINERS
@@ -0,0 +1,7 @@
+MPC8541CDS BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	board/freescale/mpc8541cds/
+F:	include/configs/MPC8541CDS.h
+F:	configs/MPC8541CDS_defconfig
+F:	configs/MPC8541CDS_legacy_defconfig
diff --git a/roms/u-boot/board/freescale/mpc8541cds/Makefile b/roms/u-boot/board/freescale/mpc8541cds/Makefile
new file mode 100644
index 000000000..b2b721ac9
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8541cds/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= mpc8541cds.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/roms/u-boot/board/freescale/mpc8541cds/ddr.c b/roms/u-boot/board/freescale/mpc8541cds/ddr.c
new file mode 100644
index 000000000..05c56a85d
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8541cds/ddr.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 6;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/roms/u-boot/board/freescale/mpc8541cds/law.c b/roms/u-boot/board/freescale/mpc8541cds/law.c
new file mode 100644
index 000000000..69f151b61
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8541cds/law.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
+ * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/mpc8541cds/mpc8541cds.c b/roms/u-boot/board/freescale/mpc8541cds/mpc8541cds.c
new file mode 100644
index 000000000..5b4fbd5e3
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8541cds/mpc8541cds.c
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <pci.h>
+#include <vsprintf.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <spd_sdram.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+void local_bus_init(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	char buf[32];
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
+	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+
+	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+	printf("PCI1: %d bit, %s MHz, %s\n",
+		(pci1_32) ? 32 : 64,
+		strmhz(buf, pci1_speed),
+		pci1_clk_sel ? "sync" : "async");
+
+	if (pci_dual) {
+		printf("PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf("PCI2: disabled\n");
+	}
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+	uint temp_lbcdll;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
+	 * If localbus freq is > 133MHz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
+	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr |= LCRR_DBYP;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr &= (~LCRR_DBYP);		/* DLL Enabled */
+
+	} else {
+		lbc->lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+
+	uint idx;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("LBC SDRAM: ");
+	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+		   "\n       ");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * Determine which address lines to use baed on CPU board rev.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+		lsdmr_common |= LSDMR_BSMA1617;
+	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+		lsdmr_common |= LSDMR_BSMA1516;
+	} else {
+		/*
+		 * Assume something unable to identify itself is
+		 * really old, and likely has lines 16/17 mapped.
+		 */
+		lsdmr_common |= LSDMR_BSMA1617;
+	}
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CONFIG_PCI)
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device.  Work around that by refusing to configure it.
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+		mpc85xx_config_via_usbide, {0,0,0}},
+	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+		mpc85xx_config_via_usb, {0,0,0}},
+	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+		mpc85xx_config_via_usb2, {0,0,0}},
+	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+		mpc85xx_config_via_power, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+		mpc85xx_config_via_ac97, {0,0,0}},
+	{},
+};
+
+static struct pci_controller hose[] = {
+	{ config_table: pci_mpc85xxcds_config_table,},
+#ifdef CONFIG_MPC85XX_PCI2
+	{},
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	pci_mpc85xx_init(hose);
+#endif
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, struct bd_info *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI1
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose[0].last_busno - hose[0].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = hose[1].last_busno - hose[1].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mpc8541cds/tlb.c b/roms/u-boot/board/freescale/mpc8541cds/tlb.c
new file mode 100644
index 000000000..d4ed51c54
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8541cds/tlb.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/freescale/mpc8548cds/Kconfig b/roms/u-boot/board/freescale/mpc8548cds/Kconfig
new file mode 100644
index 000000000..09f3b0b76
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8548cds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8548CDS
+
+config SYS_BOARD
+	default "mpc8548cds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "MPC8548CDS"
+
+endif
diff --git a/roms/u-boot/board/freescale/mpc8548cds/MAINTAINERS b/roms/u-boot/board/freescale/mpc8548cds/MAINTAINERS
new file mode 100644
index 000000000..fbbedb1d1
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8548cds/MAINTAINERS
@@ -0,0 +1,8 @@
+MPC8548CDS BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	board/freescale/mpc8548cds/
+F:	include/configs/MPC8548CDS.h
+F:	configs/MPC8548CDS_defconfig
+F:	configs/MPC8548CDS_36BIT_defconfig
+F:	configs/MPC8548CDS_legacy_defconfig
diff --git a/roms/u-boot/board/freescale/mpc8548cds/Makefile b/roms/u-boot/board/freescale/mpc8548cds/Makefile
new file mode 100644
index 000000000..5ed40e92e
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8548cds/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= mpc8548cds.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/roms/u-boot/board/freescale/mpc8548cds/ddr.c b/roms/u-boot/board/freescale/mpc8548cds/ddr.c
new file mode 100644
index 000000000..b6c1847b1
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8548cds/ddr.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/roms/u-boot/board/freescale/mpc8548cds/law.c b/roms/u-boot/board/freescale/mpc8548cds/law.c
new file mode 100644
index 000000000..d19438899
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8548cds/law.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	/* LBC window - maps 256M */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/mpc8548cds/mpc8548cds.c b/roms/u-boot/board/freescale/mpc8548cds/mpc8548cds.c
new file mode 100644
index 000000000..a1a9742bf
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8548cds/mpc8548cds.c
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <pci.h>
+#include <vsprintf.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <miiphy.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <fsl_mdio.h>
+#include <netdev.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+void local_bus_init(void);
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	puts("Board: MPC8548CDS");
+	printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
+			get_board_version(), pci_slot);
+	printf("       Daughtercard Rev: %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */
+
+	ecm->eedr = 0xffffffff;		/* clear ecm errors */
+	ecm->eeer = 0xffffffff;		/* enable ecm errors */
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+
+	gur->lbiuiplldcr1 = 0x00078080;
+	if (clkdiv == 16) {
+		gur->lbiuiplldcr0 = 0x7c0f1bf0;
+	} else if (clkdiv == 8) {
+		gur->lbiuiplldcr0 = 0x6c0f1bf0;
+	} else if (clkdiv == 4) {
+		gur->lbiuiplldcr0 = 0x5c0f1bf0;
+	}
+
+	lbc->lcrr |= 0x00030000;
+
+	asm("sync;isync;msync");
+
+	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
+	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+
+	uint idx;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	uint lsdmr_common;
+
+	puts("LBC SDRAM: ");
+	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+		   "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * MPC8548 uses "new" 15-16 style addressing.
+	 */
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	lsdmr_common |= LSDMR_BSMA1516;
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI)
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device.  Work around that by refusing to configure it.
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+		mpc85xx_config_via_usbide, {0,0,0}},
+	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+		mpc85xx_config_via_usb, {0,0,0}},
+	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+		mpc85xx_config_via_usb2, {0,0,0}},
+	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+		mpc85xx_config_via_power, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+		mpc85xx_config_via_ac97, {0,0,0}},
+	{},
+};
+
+static struct pci_controller pci1_hose;
+#endif	/* CONFIG_PCI */
+
+#if !defined(CONFIG_DM_PCI)
+void pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct fsl_pci_info pci_info;
+	u32 devdisr, pordevsr, io_sel;
+	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+	int first_free_busno = 0;
+	char buf[32];
+
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	porpllsr = in_be32(&gur->porpllsr);
+	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+
+	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+
+#ifdef CONFIG_PCI1
+	pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+	pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
+	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+		printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+			(pci_32) ? 32 : 64,
+			strmhz(buf, pci_speed),
+			pci_clk_sel ? "sync" : "async",
+			pci_agent ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter",
+			pci_info.regs);
+
+		pci1_hose.config_table = pci_mpc85xxcds_config_table;
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+
+#ifdef CONFIG_PCIX_CHECK
+		if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
+			/* PCI-X init */
+			if (CONFIG_SYS_CLK_FREQ < 66000000)
+				printf("PCI-X will only work at 66 MHz\n");
+
+			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
+		}
+#endif
+	} else {
+		printf("PCI1: disabled\n");
+	}
+
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+
+#ifdef CONFIG_PCI2
+{
+	uint pci2_clk_sel = porpllsr & 0x4000;	/* PORPLLSR[17] */
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	if (pci_dual) {
+		printf("PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf("PCI2: disabled\n");
+	}
+}
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
+#endif /* CONFIG_PCI2 */
+
+	fsl_pcie_init_board(first_free_busno);
+}
+#endif
+
+void configure_rgmii(void)
+{
+	unsigned short temp;
+
+	/* Change the resistors for the PHY */
+	/* This is needed to get the RGMII working for the 1.3+
+	 * CDS cards */
+	if (get_board_version() ==  0x13) {
+		miiphy_write(DEFAULT_MII_NAME,
+				TSEC1_PHY_ADDR, 29, 18);
+
+		miiphy_read(DEFAULT_MII_NAME,
+				TSEC1_PHY_ADDR, 30, &temp);
+
+		temp = (temp & 0xf03f);
+		temp |= 2 << 9;		/* 36 ohm */
+		temp |= 2 << 6;		/* 39 ohm */
+
+		miiphy_write(DEFAULT_MII_NAME,
+				TSEC1_PHY_ADDR, 30, temp);
+
+		miiphy_write(DEFAULT_MII_NAME,
+				TSEC1_PHY_ADDR, 29, 3);
+
+		miiphy_write(DEFAULT_MII_NAME,
+				TSEC1_PHY_ADDR, 30, 0x8000);
+	}
+
+	return;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_TSEC_ENET
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	/* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
+	if (get_board_version() >= 0x13) {
+		SET_STD_TSEC_INFO(tsec_info[num], 3);
+		tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
+		num++;
+	}
+#endif
+#ifdef CONFIG_TSEC4
+	/* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
+	if (get_board_version() >= 0x13) {
+		SET_STD_TSEC_INFO(tsec_info[num], 4);
+		tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
+		num++;
+	}
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+
+		return 0;
+	}
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+	configure_rgmii();
+#endif
+
+	return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI)
+void ft_pci_setup(void *blob, struct bd_info *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mpc8548cds/tlb.c b/roms/u-boot/board/freescale/mpc8548cds/tlb.c
new file mode 100644
index 000000000..8d1e5fee9
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8548cds/tlb.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/*
+	 * Entry 0:
+	 * FLASH(cover boot page)	16M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * Entry 1:
+	 * CCSRBAR	1M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/*
+	 * Entry 2:
+	 * LBC SDRAM	64M	Cacheable, non-guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
+		      CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 2, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * Entry 3:
+	 * CADMUS registers	1M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1M, 1),
+
+	/*
+	 * Entry 4:
+	 * PCI and PCIe MEM	1G	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_1G, 1),
+
+	/*
+	 * Entry 5:
+	 * PCI1 IO	1M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_1M, 1),
+
+	/*
+	 * Entry 6:
+	 * PCIe IO	1M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/freescale/mpc8555cds/Kconfig b/roms/u-boot/board/freescale/mpc8555cds/Kconfig
new file mode 100644
index 000000000..04bd57221
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8555cds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8555CDS
+
+config SYS_BOARD
+	default "mpc8555cds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "MPC8555CDS"
+
+endif
diff --git a/roms/u-boot/board/freescale/mpc8555cds/MAINTAINERS b/roms/u-boot/board/freescale/mpc8555cds/MAINTAINERS
new file mode 100644
index 000000000..8f32febd9
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8555cds/MAINTAINERS
@@ -0,0 +1,7 @@
+MPC8555CDS BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	board/freescale/mpc8555cds/
+F:	include/configs/MPC8555CDS.h
+F:	configs/MPC8555CDS_defconfig
+F:	configs/MPC8555CDS_legacy_defconfig
diff --git a/roms/u-boot/board/freescale/mpc8555cds/Makefile b/roms/u-boot/board/freescale/mpc8555cds/Makefile
new file mode 100644
index 000000000..f121c2fa6
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8555cds/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= mpc8555cds.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/roms/u-boot/board/freescale/mpc8555cds/ddr.c b/roms/u-boot/board/freescale/mpc8555cds/ddr.c
new file mode 100644
index 000000000..05c56a85d
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8555cds/ddr.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 6;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/roms/u-boot/board/freescale/mpc8555cds/law.c b/roms/u-boot/board/freescale/mpc8555cds/law.c
new file mode 100644
index 000000000..69f151b61
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8555cds/law.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
+ * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/mpc8555cds/mpc8555cds.c b/roms/u-boot/board/freescale/mpc8555cds/mpc8555cds.c
new file mode 100644
index 000000000..3bb8e769c
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8555cds/mpc8555cds.c
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <pci.h>
+#include <vsprintf.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <spd_sdram.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+void local_bus_init(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	char buf[32];
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
+	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+
+	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+	printf("PCI1: %d bit, %s MHz, %s\n",
+		(pci1_32) ? 32 : 64,
+		strmhz(buf, pci1_speed),
+		pci1_clk_sel ? "sync" : "async");
+
+	if (pci_dual) {
+		printf("PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf("PCI2: disabled\n");
+	}
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+	uint temp_lbcdll;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
+	 * If localbus freq is > 133MHz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
+	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr |= LCRR_DBYP;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr &= (~LCRR_DBYP);		/* DLL Enabled */
+
+	} else {
+		lbc->lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+
+	uint idx;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("LBC SDRAM: ");
+	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+		   "\n       ");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * Determine which address lines to use baed on CPU board rev.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+		lsdmr_common |= LSDMR_BSMA1617;
+	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+		lsdmr_common |= LSDMR_BSMA1516;
+	} else {
+		/*
+		 * Assume something unable to identify itself is
+		 * really old, and likely has lines 16/17 mapped.
+		 */
+		lsdmr_common |= LSDMR_BSMA1617;
+	}
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#ifdef CONFIG_PCI
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device.  Work around that by refusing to configure it
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+		mpc85xx_config_via_usbide, {0,0,0}},
+	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+		mpc85xx_config_via_usb, {0,0,0}},
+	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+		mpc85xx_config_via_usb2, {0,0,0}},
+	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+		mpc85xx_config_via_power, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+		mpc85xx_config_via_ac97, {0,0,0}},
+	{},
+};
+
+
+static struct pci_controller hose[] = {
+	{
+	config_table: pci_mpc85xxcds_config_table,
+	},
+#ifdef CONFIG_MPC85XX_PCI2
+	{},
+#endif
+};
+
+#endif
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	pci_mpc85xx_init(hose);
+#endif
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, struct bd_info *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI1
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose[0].last_busno - hose[0].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = hose[1].last_busno - hose[1].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mpc8555cds/tlb.c b/roms/u-boot/board/freescale/mpc8555cds/tlb.c
new file mode 100644
index 000000000..4a18f05af
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8555cds/tlb.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/freescale/mpc8568mds/Kconfig b/roms/u-boot/board/freescale/mpc8568mds/Kconfig
new file mode 100644
index 000000000..4e178c503
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8568mds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8568MDS
+
+config SYS_BOARD
+	default "mpc8568mds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "MPC8568MDS"
+
+endif
diff --git a/roms/u-boot/board/freescale/mpc8568mds/MAINTAINERS b/roms/u-boot/board/freescale/mpc8568mds/MAINTAINERS
new file mode 100644
index 000000000..f4747866d
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8568mds/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8568MDS BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	board/freescale/mpc8568mds/
+F:	include/configs/MPC8568MDS.h
+F:	configs/MPC8568MDS_defconfig
diff --git a/roms/u-boot/board/freescale/mpc8568mds/Makefile b/roms/u-boot/board/freescale/mpc8568mds/Makefile
new file mode 100644
index 000000000..1e9095bdd
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8568mds/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2004-2007 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= mpc8568mds.o
+obj-y	+= bcsr.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/roms/u-boot/board/freescale/mpc8568mds/bcsr.c b/roms/u-boot/board/freescale/mpc8568mds/bcsr.c
new file mode 100644
index 000000000..b1e638af5
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8568mds/bcsr.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ */
+
+#include <common.h>
+#include <flash.h>
+#include <asm/io.h>
+
+#include "bcsr.h"
+
+void enable_8568mds_duart(void)
+{
+	volatile uint* duart_mux	= (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
+	volatile uint* devices		= (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
+	volatile u8 *bcsr		= (u8 *)(CONFIG_SYS_BCSR);
+
+	*duart_mux = 0x80000000;	/* Set the mux to Duart on PMUXCR */
+	*devices  = 0;			/* Enable all peripheral devices */
+	bcsr[5] |= 0x01;		/* Enable Duart in BCSR*/
+}
+
+void enable_8568mds_flash_write(void)
+{
+	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+	bcsr[9] |= 0x01;
+}
+
+void disable_8568mds_flash_write(void)
+{
+	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+	bcsr[9] &= ~(0x01);
+}
+
+void enable_8568mds_qe_mdio(void)
+{
+	u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+	bcsr[7] |= 0x01;
+}
+
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+void reset_8568mds_uccs(void)
+{
+	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+	/* Turn off UCC1 & UCC2 */
+	out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN);
+	out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN);
+
+	/* Mode is RGMII, all bits clear */
+	out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK |
+					     BCSR_UCC2_MODE_MSK));
+
+	/* Turn UCC1 & UCC2 on */
+	out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN);
+	out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN);
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mpc8568mds/bcsr.h b/roms/u-boot/board/freescale/mpc8568mds/bcsr.h
new file mode 100644
index 000000000..a8e13a2a5
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8568mds/bcsr.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ */
+
+#ifndef __BCSR_H_
+#define __BCSR_H_
+
+#include <common.h>
+
+/* BCSR Bit definitions
+	* BCSR 0 *
+	0:3	ccb sys pll
+	4:6	cfg core pll
+	7	cfg boot seq
+
+	* BCSR 1 *
+	0:2	cfg rom lock
+	3:5	cfg host agent
+	6	PCI IO
+	7	cfg RIO size
+
+	* BCSR 2 *
+	0:4	QE PLL
+	5	QE clock
+	6	cfg PCI arbiter
+
+	* BCSR 3 *
+	0	TSEC1 reduce
+	1	TSEC2 reduce
+	2:3	TSEC1 protocol
+	4:5	TSEC2 protocol
+	6	PHY1 slave
+	7	PHY2 slave
+
+	* BCSR 4 *
+	4	clock enable
+	5	boot EPROM
+	6	GETH transactive reset
+	7	BRD write potect
+
+	* BCSR 5 *
+	1:3	Leds 1-3
+	4	UPC1 enable
+	5	UPC2 enable
+	6	UPC2 pos
+	7	RS232 enable
+
+	* BCSR 6 *
+	0	CFG ver 0
+	1	CFG ver 1
+	6	Register config led
+	7	Power on reset
+
+	* BCSR 7 *
+	2	board host mode indication
+	5	enable TSEC1 PHY
+	6	enable TSEC2 PHY
+
+	* BCSR 8 *
+	0	UCC GETH1 enable
+	1	UCC GMII enable
+	3	UCC TBI enable
+	5	UCC MII enable
+	7	Real time clock reset
+
+	* BCSR 9 *
+	0	UCC2 GETH enable
+	1	UCC2 GMII enable
+	3	UCC2 TBI enable
+	5	UCC2 MII enable
+	6	Ready only - indicate flash ready after burning
+	7	Flash write protect
+*/
+
+#define BCSR_UCC1_GETH_EN	(0x1 << 7)
+#define BCSR_UCC2_GETH_EN	(0x1 << 7)
+#define BCSR_UCC1_MODE_MSK	(0x3 << 4)
+#define BCSR_UCC2_MODE_MSK	(0x3 << 0)
+
+/*BCSR Utils functions*/
+
+void enable_8568mds_duart(void);
+void enable_8568mds_flash_write(void);
+void disable_8568mds_flash_write(void);
+void enable_8568mds_qe_mdio(void);
+
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+void reset_8568mds_uccs(void);
+#endif
+
+#endif	/* __BCSR_H_ */
diff --git a/roms/u-boot/board/freescale/mpc8568mds/ddr.c b/roms/u-boot/board/freescale/mpc8568mds/ddr.c
new file mode 100644
index 000000000..58a979dbc
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8568mds/ddr.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 6;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/roms/u-boot/board/freescale/mpc8568mds/law.c b/roms/u-boot/board/freescale/mpc8568mds/law.c
new file mode 100644
index 000000000..c04c36b5d
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8568mds/law.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
+ *1)   0x8000_0000   0x9fff_ffff     PCI1 MEM                512MB
+ *2)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
+ *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
+ *3)   0xe200_0000   0xe27f_ffff     PCI1 I/O                8M
+ *4)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
+ *5)   0xc000_0000   0xdfff_ffff     SRIO                    512MB
+ *6.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
+ *6.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
+ *6.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
+ *6.d) 0xf801_0000   0xf801_7fff     PIB (CS5)		     32KB
+ *6.e) 0xfe00_0000   0xffff_ffff     Flash                   32MB
+ *
+ *Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ */
+
+struct law_entry law_table[] = {
+	/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/mpc8568mds/mpc8568mds.c b/roms/u-boot/board/freescale/mpc8568mds/mpc8568mds.c
new file mode 100644
index 000000000..7b379464c
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8568mds/mpc8568mds.c
@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ */
+
+#include <common.h>
+#include <flash.h>
+#include <init.h>
+#include <log.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+#include "bcsr.h"
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* GETH1 */
+	{4, 10, 1, 0, 2}, /* TxD0 */
+	{4,  9, 1, 0, 2}, /* TxD1 */
+	{4,  8, 1, 0, 2}, /* TxD2 */
+	{4,  7, 1, 0, 2}, /* TxD3 */
+	{4, 23, 1, 0, 2}, /* TxD4 */
+	{4, 22, 1, 0, 2}, /* TxD5 */
+	{4, 21, 1, 0, 2}, /* TxD6 */
+	{4, 20, 1, 0, 2}, /* TxD7 */
+	{4, 15, 2, 0, 2}, /* RxD0 */
+	{4, 14, 2, 0, 2}, /* RxD1 */
+	{4, 13, 2, 0, 2}, /* RxD2 */
+	{4, 12, 2, 0, 2}, /* RxD3 */
+	{4, 29, 2, 0, 2}, /* RxD4 */
+	{4, 28, 2, 0, 2}, /* RxD5 */
+	{4, 27, 2, 0, 2}, /* RxD6 */
+	{4, 26, 2, 0, 2}, /* RxD7 */
+	{4, 11, 1, 0, 2}, /* TX_EN */
+	{4, 24, 1, 0, 2}, /* TX_ER */
+	{4, 16, 2, 0, 2}, /* RX_DV */
+	{4, 30, 2, 0, 2}, /* RX_ER */
+	{4, 17, 2, 0, 2}, /* RX_CLK */
+	{4, 19, 1, 0, 2}, /* GTX_CLK */
+	{1, 31, 2, 0, 3}, /* GTX125 */
+
+	/* GETH2 */
+	{5, 10, 1, 0, 2}, /* TxD0 */
+	{5,  9, 1, 0, 2}, /* TxD1 */
+	{5,  8, 1, 0, 2}, /* TxD2 */
+	{5,  7, 1, 0, 2}, /* TxD3 */
+	{5, 23, 1, 0, 2}, /* TxD4 */
+	{5, 22, 1, 0, 2}, /* TxD5 */
+	{5, 21, 1, 0, 2}, /* TxD6 */
+	{5, 20, 1, 0, 2}, /* TxD7 */
+	{5, 15, 2, 0, 2}, /* RxD0 */
+	{5, 14, 2, 0, 2}, /* RxD1 */
+	{5, 13, 2, 0, 2}, /* RxD2 */
+	{5, 12, 2, 0, 2}, /* RxD3 */
+	{5, 29, 2, 0, 2}, /* RxD4 */
+	{5, 28, 2, 0, 2}, /* RxD5 */
+	{5, 27, 2, 0, 3}, /* RxD6 */
+	{5, 26, 2, 0, 2}, /* RxD7 */
+	{5, 11, 1, 0, 2}, /* TX_EN */
+	{5, 24, 1, 0, 2}, /* TX_ER */
+	{5, 16, 2, 0, 2}, /* RX_DV */
+	{5, 30, 2, 0, 2}, /* RX_ER */
+	{5, 17, 2, 0, 2}, /* RX_CLK */
+	{5, 19, 1, 0, 2}, /* GTX_CLK */
+	{1, 31, 2, 0, 3}, /* GTX125 */
+	{4,  6, 3, 0, 2}, /* MDIO */
+	{4,  5, 1, 0, 2}, /* MDC */
+
+	/* UART1 */
+	{2, 0, 1, 0, 2}, /* UART_SOUT1 */
+	{2, 1, 1, 0, 2}, /* UART_RTS1 */
+	{2, 2, 2, 0, 2}, /* UART_CTS1 */
+	{2, 3, 2, 0, 2}, /* UART_SIN1 */
+
+	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+void local_bus_init(void);
+
+int board_early_init_f (void)
+{
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	enable_8568mds_duart();
+	enable_8568mds_flash_write();
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+	reset_8568mds_uccs();
+#endif
+#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
+	enable_8568mds_qe_mdio();
+#endif
+
+#ifdef CONFIG_SYS_I2C2_OFFSET
+	/* Enable I2C2_SCL and I2C2_SDA */
+	volatile struct par_io *port_c;
+	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
+	port_c->cpdir2 |= 0x0f000000;
+	port_c->cppar2 &= ~0x0f000000;
+	port_c->cppar2 |= 0x0a000000;
+#endif
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf ("Board: 8568 MDS\n");
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+
+	gur->lbiuiplldcr1 = 0x00078080;
+	if (clkdiv == 16) {
+		gur->lbiuiplldcr0 = 0x7c0f1bf0;
+	} else if (clkdiv == 8) {
+		gur->lbiuiplldcr0 = 0x6c0f1bf0;
+	} else if (clkdiv == 4) {
+		gur->lbiuiplldcr0 = 0x5c0f1bf0;
+	}
+
+	lbc->lcrr |= 0x00030000;
+
+	asm("sync;isync;msync");
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+
+	uint idx;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	uint lsdmr_common;
+
+	puts("LBC SDRAM: ");
+	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+		   "\n       ");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+	asm("msync");
+
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * MPC8568 uses "new" 15-16 style addressing.
+	 */
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	lsdmr_common |= LSDMR_BSMA1516;
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CONFIG_PCI)
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc8568mds_config_table[] = {
+	{
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 pci_cfgfunc_config_device,
+	 {PCI_ENET0_IOADDR,
+	  PCI_ENET0_MEMADDR,
+	  PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
+	 },
+	{}
+};
+#endif
+
+static struct pci_controller pci1_hose;
+#endif	/* CONFIG_PCI */
+
+/*
+ * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
+ */
+void
+pib_init(void)
+{
+	u8 val8, orig_i2c_bus;
+	/*
+	 * Assign PIB PMC2/3 to PCI bus
+	 */
+
+	/*switch temporarily to I2C bus #2 */
+	orig_i2c_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	val8 = 0x00;
+	i2c_write(0x23, 0x6, 1, &val8, 1);
+	i2c_write(0x23, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x23, 0x2, 1, &val8, 1);
+	i2c_write(0x23, 0x3, 1, &val8, 1);
+
+	val8 = 0x00;
+	i2c_write(0x26, 0x6, 1, &val8, 1);
+	val8 = 0x34;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+	val8 = 0xf9;
+	i2c_write(0x26, 0x2, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+
+	val8 = 0x00;
+	i2c_write(0x27, 0x6, 1, &val8, 1);
+	i2c_write(0x27, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x27, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x27, 0x3, 1, &val8, 1);
+
+	asm("eieio");
+	i2c_set_bus_num(orig_i2c_bus);
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int first_free_busno = 0;
+#ifdef CONFIG_PCI1
+	struct fsl_pci_info pci_info;
+	u32 devdisr, pordevsr, io_sel;
+	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	porpllsr = in_be32(&gur->porpllsr);
+	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+
+	debug("   %s: devdisr=%x, io_sel=%x\n", __func__, devdisr, io_sel);
+
+	pci_speed = 66666000;
+	pci_32 = 1;
+	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+			(pci_32) ? 32 : 64,
+			(pci_speed == 33333000) ? "33" :
+			(pci_speed == 66666000) ? "66" : "unknown",
+			pci_clk_sel ? "sync" : "async",
+			pci_agent ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter",
+			pci_info.regs);
+
+#ifndef CONFIG_PCI_PNP
+		pci1_hose.config_table = pci_mpc8568mds_config_table;
+#endif
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+	} else {
+		printf("PCI: disabled\n");
+	}
+
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+
+	fsl_pcie_init_board(first_free_busno);
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	FT_FSL_PCI_SETUP;
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mpc8568mds/tlb.c b/roms/u-boot/board/freescale/mpc8568mds/tlb.c
new file mode 100644
index 000000000..fea1606a1
--- /dev/null
+++ b/roms/u-boot/board/freescale/mpc8568mds/tlb.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 Initializations */
+	/*
+	 * TLBe 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH (upper half)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLBe 1:	16M	Non-cacheable, guarded
+	 * 0xfe000000	16M	FLASH (lower half)
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLBe 2:	1G	Non-cacheable, guarded
+	 * 0x80000000	512M	PCI1 MEM
+	 * 0xa0000000	512M	PCIe MEM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_1G, 1),
+
+	/*
+	 * TLBe 3:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	8M	PCI1 IO
+	 * 0xe280_0000	8M	PCIe IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLBe 4:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 4, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLBe 5:	256K	Non-cacheable, guarded
+	 * 0xf8000000	32K BCSR
+	 * 0xf8008000	32K PIB (CS4)
+	 * 0xf8010000	32K PIB (CS5)
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/freescale/mx23evk/Kconfig b/roms/u-boot/board/freescale/mx23evk/Kconfig
new file mode 100644
index 000000000..51a8f9f77
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx23evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX23EVK
+
+config SYS_BOARD
+	default "mx23evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "mxs"
+
+config SYS_CONFIG_NAME
+	default "mx23evk"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx23evk/MAINTAINERS b/roms/u-boot/board/freescale/mx23evk/MAINTAINERS
new file mode 100644
index 000000000..122b70cd7
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx23evk/MAINTAINERS
@@ -0,0 +1,8 @@
+MX23EVK BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+M:	Otavio Salvador <otavio@ossystems.com.br>
+S:	Maintained
+F:	board/freescale/mx23evk/
+F:	arch/arm/dts/imx23-evk.dts
+F:	include/configs/mx23evk.h
+F:	configs/mx23evk_defconfig
diff --git a/roms/u-boot/board/freescale/mx23evk/Makefile b/roms/u-boot/board/freescale/mx23evk/Makefile
new file mode 100644
index 000000000..6fe6992a5
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx23evk/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ifndef	CONFIG_SPL_BUILD
+obj-y	:= mx23evk.o
+else
+obj-y	:= spl_boot.o
+endif
diff --git a/roms/u-boot/board/freescale/mx23evk/mx23evk.c b/roms/u-boot/board/freescale/mx23evk/mx23evk.c
new file mode 100644
index 000000000..df4fb3912
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx23evk/mx23evk.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Freescale MX23EVK board
+ *
+ * (C) Copyright 2013 O.S. Systems Software LTDA.
+ *
+ * Author: Otavio Salvador <otavio@ossystems.com.br>
+ *
+ * Based on m28evk.c:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+
+	/* SSP0 clock at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+	/* Power on LCD */
+	gpio_direction_output(MX23_PAD_LCD_RESET__GPIO_1_18, 1);
+
+	/* Set contrast to maximum */
+	gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/mx23evk/spl_boot.c b/roms/u-boot/board/freescale/mx23evk/spl_boot.c
new file mode 100644
index 000000000..14e9b4a86
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx23evk/spl_boot.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Freescale MX23EVK Boot setup
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_SSP1	(MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_LCD	(MXS_PAD_4MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* DUART */
+	MX23_PAD_PWM0__DUART_RX,
+	MX23_PAD_PWM1__DUART_TX,
+
+	/* EMI */
+	MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
+
+	MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+
+	MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+
+	/* MMC 0 */
+	MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP1,
+	MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP1,
+	MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP1,
+	MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP1,
+	MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP1,
+	MX23_PAD_SSP1_DETECT__SSP1_DETECT | MUX_CONFIG_SSP1,
+		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	MX23_PAD_SSP1_SCK__SSP1_SCK |
+		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	/* Write Protect Pin */
+	MX23_PAD_PWM4__GPIO_1_30 |
+		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	/* Slot Power Enable */
+	MX23_PAD_PWM3__GPIO_1_29 |
+		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	/* LCD */
+	MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D08__LCD_D18 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D09__LCD_D19 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D10__LCD_D20 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D11__LCD_D21 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D12__LCD_D22 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D13__LCD_D23 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_DOTCK__LCD_DOTCK | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, /* LCD power */
+	MX23_PAD_PWM2__GPIO_1_28 | MUX_CONFIG_LCD, /* LCD contrast */
+};
+
+#define HW_DRAM_CTL14	(0x38 >> 2)
+#define CS_MAP		0x3
+#define INTAREF		0x2
+#define HW_DRAM_CTL14_CONFIG	(INTAREF << 8 | CS_MAP)
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+	dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG;
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/roms/u-boot/board/freescale/mx28evk/Kconfig b/roms/u-boot/board/freescale/mx28evk/Kconfig
new file mode 100644
index 000000000..39777bd70
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx28evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX28EVK
+
+config SYS_BOARD
+	default "mx28evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "mxs"
+
+config SYS_CONFIG_NAME
+	default "mx28evk"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx28evk/MAINTAINERS b/roms/u-boot/board/freescale/mx28evk/MAINTAINERS
new file mode 100644
index 000000000..597118d3f
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx28evk/MAINTAINERS
@@ -0,0 +1,9 @@
+MX28EVK BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/freescale/mx28evk/
+F:	include/configs/mx28evk.h
+F:	configs/mx28evk_defconfig
+F:	configs/mx28evk_auart_console_defconfig
+F:	configs/mx28evk_nand_defconfig
+F:	configs/mx28evk_spi_defconfig
diff --git a/roms/u-boot/board/freescale/mx28evk/Makefile b/roms/u-boot/board/freescale/mx28evk/Makefile
new file mode 100644
index 000000000..057760433
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx28evk/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ifndef	CONFIG_SPL_BUILD
+obj-y	:= mx28evk.o
+else
+obj-y	:= iomux.o
+endif
diff --git a/roms/u-boot/board/freescale/mx28evk/README b/roms/u-boot/board/freescale/mx28evk/README
new file mode 100644
index 000000000..d32f0efb3
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx28evk/README
@@ -0,0 +1,62 @@
+FREESCALE MX28EVK
+==================
+
+Supported hardware: MX28EVK rev C and D are supported in U-Boot.
+
+Files of the MX28EVK port
+--------------------------
+
+arch/arm/cpu/arm926ejs/mxs/	- The CPU support code for the Freescale i.MX28
+arch/arm/include/asm/arch-mxs/	- Header files for the Freescale i.MX28
+board/freescale/mx28evk/	- MX28EVK board specific files
+include/configs/mx28evk.h	- MX28EVK configuration file
+
+Jumper configuration
+---------------------
+
+To boot MX28EVK from an SD card, set the boot mode DIP switches as:
+
+   * Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42)
+   * JTAG PSWITCH RESET: To the right (reset disabled)
+   * Battery Source: Down
+   * Wall 5V: Up
+   * VDD 5V: To the left (off)
+   * Hold Button: Down (off)
+
+To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as:
+
+   * Boot Mode Select: 0 0 1 0 (Boot from SSP2)
+   * JTAG PSWITCH RESET: To the right (reset disabled)
+   * Battery Source: Down
+   * Wall 5V: Up
+   * VDD 5V: To the left (off)
+   * Hold Button: Down (off)
+
+Environment Storage
+-------------------
+
+There are three targets for mx28evk:
+
+"make mx28evk_config"		- store environment variables into MMC
+
+or
+
+"make mx28evk_nand_config"	- store environment variables into NAND flash
+
+or
+
+"make mx28evk_spi_config"       - store environment variables into SPI NOR flash
+
+Choose the target accordingly.
+
+Note: The mx28evk board does not come with a NAND flash populated from the
+factory. It comes with an empty slot (U23), which allows the insertion of a
+48-pin TSOP flash device.
+
+mx28evk does not come with SPI NOR flash populated from the factory either.
+It is possible to solder a SOIC memory on U49 or use a DIP8 on J89.
+To get SPI communication to work R320, R321,R322 and C178 need to be populated.
+Look in the schematics for the proper component values.
+
+Follow the instructions from doc/imx/common/mxs.txt to generate a bootable
+SD card or to generate a binary to be flashed into SPI NOR.
diff --git a/roms/u-boot/board/freescale/mx28evk/iomux.c b/roms/u-boot/board/freescale/mx28evk/iomux.c
new file mode 100644
index 000000000..cc0c85885
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx28evk/iomux.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Freescale MX28EVK IOMUX setup
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_GPMI	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* DUART */
+	MX28_PAD_PWM0__DUART_RX,
+	MX28_PAD_PWM1__DUART_TX,
+
+	/* MMC0 */
+	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	MX28_PAD_SSP0_SCK__SSP0_SCK |
+		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	/* write protect */
+	MX28_PAD_SSP1_SCK__GPIO_2_12,
+	/* MMC0 slot power enable */
+	MX28_PAD_PWM3__GPIO_3_28 |
+		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+#ifdef CONFIG_NAND_MXS
+	/* GPMI NAND */
+	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RDN__GPMI_RDN |
+		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+#endif
+
+	/* FEC0 */
+	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+	/* FEC0 Enable */
+	MX28_PAD_SSP1_DATA3__GPIO_2_15 |
+		(MXS_PAD_12MA | MXS_PAD_3V3),
+	/* FEC0 Reset */
+	MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
+		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+	/* FEC1 */
+	MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+
+	/* EMI */
+	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+	/* SPI2 (for SPI flash) */
+	MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_SS0__SSP2_D3 |
+		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+	/* I2C */
+	MX28_PAD_I2C0_SCL__I2C0_SCL,
+	MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+	/* LCD */
+	MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */
+	MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */
+};
+
+#define HW_DRAM_CTL29	(0x74 >> 2)
+#define CS_MAP		0xf
+#define COLUMN_SIZE	0x2
+#define ADDR_PINS	0x1
+#define APREBIT		0xa
+
+#define HW_DRAM_CTL29_CONFIG	(CS_MAP << 24 | COLUMN_SIZE << 16 | \
+					ADDR_PINS << 8 | APREBIT)
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+	dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/roms/u-boot/board/freescale/mx28evk/mx28evk.c b/roms/u-boot/board/freescale/mx28evk/mx28evk.c
new file mode 100644
index 000000000..21c9cb112
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx28evk/mx28evk.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Freescale MX28EVK board
+ *
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Based on m28evk.c:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/delay.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+	/* IO1 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+	/* SSP0 clock at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+	/* SSP2 clock at 160MHz */
+	mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
+
+#ifdef	CONFIG_CMD_USB
+	mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
+	mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
+			MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
+	gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
+#endif
+
+	/* Power on LCD */
+	gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1);
+
+	/* Set contrast to maximum */
+	gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef	CONFIG_CMD_MMC
+static int mx28evk_mmc_wp(int id)
+{
+	if (id != 0) {
+		printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
+		return 1;
+	}
+
+	return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12);
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	/* Configure WP as input */
+	gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12);
+
+	/* Configure MMC0 Power Enable */
+	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+
+	return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL);
+}
+#endif
+
+#ifdef	CONFIG_CMD_NET
+
+int board_eth_init(struct bd_info *bis)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct eth_device *dev;
+	int ret;
+
+	ret = cpu_eth_init(bis);
+	if (ret)
+		return ret;
+
+	/* MX28EVK uses ENET_CLK PAD to drive FEC clock */
+	writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
+	       &clkctrl_regs->hw_clkctrl_enet);
+
+	/* Power-on FECs */
+	gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
+
+	/* Reset FEC PHYs */
+	gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
+	udelay(200);
+	gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
+
+	ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+	if (ret) {
+		puts("FEC MXS: Unable to init FEC0\n");
+		return ret;
+	}
+
+	ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
+	if (ret) {
+		puts("FEC MXS: Unable to init FEC1\n");
+		return ret;
+	}
+
+	dev = eth_get_dev_by_name("FEC0");
+	if (!dev) {
+		puts("FEC MXS: Unable to get FEC0 device entry\n");
+		return -EINVAL;
+	}
+
+	dev = eth_get_dev_by_name("FEC1");
+	if (!dev) {
+		puts("FEC MXS: Unable to get FEC1 device entry\n");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+#endif
diff --git a/roms/u-boot/board/freescale/mx51evk/Kconfig b/roms/u-boot/board/freescale/mx51evk/Kconfig
new file mode 100644
index 000000000..f9b69cbd6
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx51evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX51EVK
+
+config SYS_BOARD
+	default "mx51evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "mx5"
+
+config SYS_CONFIG_NAME
+	default "mx51evk"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx51evk/MAINTAINERS b/roms/u-boot/board/freescale/mx51evk/MAINTAINERS
new file mode 100644
index 000000000..1ca55f7d1
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx51evk/MAINTAINERS
@@ -0,0 +1,7 @@
+MX51EVK BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+M:	Stefano Babic <sbabic@denx.de>
+S:	Maintained
+F:	board/freescale/mx51evk/
+F:	include/configs/mx51evk.h
+F:	configs/mx51evk_defconfig
diff --git a/roms/u-boot/board/freescale/mx51evk/Makefile b/roms/u-boot/board/freescale/mx51evk/Makefile
new file mode 100644
index 000000000..1a9581cab
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx51evk/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+
+obj-y			+= mx51evk.o
+obj-$(CONFIG_VIDEO)	+= mx51evk_video.o
diff --git a/roms/u-boot/board/freescale/mx51evk/imximage.cfg b/roms/u-boot/board/freescale/mx51evk/imximage.cfg
new file mode 100644
index 000000000..ff2ec4aa2
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx51evk/imximage.cfg
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM	spi
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Setting IOMUXC */
+DATA 4 0x73FA88a0 0x200
+DATA 4 0x73FA850c 0x20c5
+DATA 4 0x73FA8510 0x20c5
+DATA 4 0x73FA883c 0x2
+DATA 4 0x73FA8848 0x2
+DATA 4 0x73FA84b8 0xe7
+DATA 4 0x73FA84bc 0x45
+DATA 4 0x73FA84c0 0x45
+DATA 4 0x73FA84c4 0x45
+DATA 4 0x73FA84c8 0x45
+DATA 4 0x73FA8820 0x0
+DATA 4 0x73FA84a4 0x3
+DATA 4 0x73FA84a8 0x3
+DATA 4 0x73FA84ac 0xe3
+DATA 4 0x73FA84b0 0xe3
+DATA 4 0x73FA84b4 0xe3
+DATA 4 0x73FA84cc 0xe3
+DATA 4 0x73FA84d0 0xe2
+
+DATA 4 0x73FA882c 0x6
+DATA 4 0x73FA88a4 0x6
+DATA 4 0x73FA88ac 0x6
+DATA 4 0x73FA88b8 0x6
+
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
+DATA 4 0x83FD9000 0x82a20000
+/* ESDCTL_ESDCTL1 */
+DATA 4 0x83FD9008 0x82a20000
+/* ESDCTL_ESDMISC */
+DATA 4 0x83FD9010 0x000ad0d0
+/* ESDCTL_ESDCFG0 */
+DATA 4 0x83FD9004 0x333574aa
+/* ESDCTL_ESDCFG1 */
+DATA 4 0x83FD900C 0x333574aa
+
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
+DATA 4 0x83FD9014 0x04008008
+DATA 4 0x83FD9014 0x0000801a
+DATA 4 0x83FD9014 0x0000801b
+DATA 4 0x83FD9014 0x00448019
+DATA 4 0x83FD9014 0x07328018
+DATA 4 0x83FD9014 0x04008008
+DATA 4 0x83FD9014 0x00008010
+DATA 4 0x83FD9014 0x00008010
+DATA 4 0x83FD9014 0x06328018
+DATA 4 0x83FD9014 0x03808019
+DATA 4 0x83FD9014 0x00408019
+DATA 4 0x83FD9014 0x00008000
+
+/* Init DRAM on CS1 */
+DATA 4 0x83FD9014 0x0400800c
+DATA 4 0x83FD9014 0x0000801e
+DATA 4 0x83FD9014 0x0000801f
+DATA 4 0x83FD9014 0x0000801d
+DATA 4 0x83FD9014 0x0732801c
+DATA 4 0x83FD9014 0x0400800c
+DATA 4 0x83FD9014 0x00008014
+DATA 4 0x83FD9014 0x00008014
+DATA 4 0x83FD9014 0x0632801c
+DATA 4 0x83FD9014 0x0380801d
+DATA 4 0x83FD9014 0x0040801d
+DATA 4 0x83FD9014 0x00008004
+
+/* Write to CTL0 */
+DATA 4 0x83FD9000 0xb2a20000
+/* Write to CTL1 */
+DATA 4 0x83FD9008 0xb2a20000
+/* ESDMISC */
+DATA 4 0x83FD9010 0x000ad6d0
+/* ESDCTL_ESDCDLYGD */
+DATA 4 0x83FD9034 0x90000000
+DATA 4 0x83FD9014 0x00000000
diff --git a/roms/u-boot/board/freescale/mx51evk/mx51evk.c b/roms/u-boot/board/freescale/mx51evk/mx51evk.c
new file mode 100644
index 000000000..c8439a634
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx51evk/mx51evk.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx51.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/mx5_video.h>
+#include <i2c.h>
+#include <input.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	u32 rev = get_cpu_rev();
+	if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
+		rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
+	return rev;
+}
+
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
+
+static void setup_iomux_uart(void)
+{
+	static const iomux_v3_cfg_t uart_pads[] = {
+		MX51_PAD_UART1_RXD__UART1_RXD,
+		MX51_PAD_UART1_TXD__UART1_TXD,
+		NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#ifdef CONFIG_MXC_SPI
+static void setup_iomux_spi(void)
+{
+	static const iomux_v3_cfg_t spi_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
+				MX51_GPIO_PAD_CTRL),
+		MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+}
+#endif
+
+static void power_init(void)
+{
+	unsigned int val;
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+	struct pmic *p;
+	int ret;
+
+	ret = pmic_init(CONFIG_FSL_PMIC_BUS);
+	if (ret)
+		return;
+
+	p = pmic_get("FSL_PMIC");
+	if (!p)
+		return;
+
+	/* Write needed to Power Gate 2 register */
+	pmic_reg_read(p, REG_POWER_MISC, &val);
+	val &= ~PWGT2SPIEN;
+	pmic_reg_write(p, REG_POWER_MISC, val);
+
+	/* Externally powered */
+	pmic_reg_read(p, REG_CHARGE, &val);
+	val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+	pmic_reg_write(p, REG_CHARGE, val);
+
+	/* power up the system first */
+	pmic_reg_write(p, REG_POWER_MISC, PWUP);
+
+	/* Set core voltage to 1.1V */
+	pmic_reg_read(p, REG_SW_0, &val);
+	val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
+	pmic_reg_write(p, REG_SW_0, val);
+
+	/* Setup VCC (SW2) to 1.25 */
+	pmic_reg_read(p, REG_SW_1, &val);
+	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+	pmic_reg_write(p, REG_SW_1, val);
+
+	/* Setup 1V2_DIG1 (SW3) to 1.25 */
+	pmic_reg_read(p, REG_SW_2, &val);
+	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+	pmic_reg_write(p, REG_SW_2, val);
+	udelay(50);
+
+	/* Raise the core frequency to 800MHz */
+	writel(0x0, &mxc_ccm->cacrr);
+
+	/* Set switchers in Auto in NORMAL mode & STANDBY mode */
+	/* Setup the switcher mode for SW1 & SW2*/
+	pmic_reg_read(p, REG_SW_4, &val);
+	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+		(SWMODE_MASK << SWMODE2_SHIFT)));
+	val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+	pmic_reg_write(p, REG_SW_4, val);
+
+	/* Setup the switcher mode for SW3 & SW4 */
+	pmic_reg_read(p, REG_SW_5, &val);
+	val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
+		(SWMODE_MASK << SWMODE4_SHIFT)));
+	val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
+	pmic_reg_write(p, REG_SW_5, val);
+
+	/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
+	pmic_reg_read(p, REG_SETTING_0, &val);
+	val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
+	val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
+	pmic_reg_write(p, REG_SETTING_0, val);
+
+	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+	pmic_reg_read(p, REG_SETTING_1, &val);
+	val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+	val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
+	pmic_reg_write(p, REG_SETTING_1, val);
+
+	/* Configure VGEN3 and VCAM regulators to use external PNP */
+	val = VGEN3CONFIG | VCAMCONFIG;
+	pmic_reg_write(p, REG_MODE_1, val);
+	udelay(200);
+
+	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+	val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+		VVIDEOEN | VAUDIOEN  | VSDEN;
+	pmic_reg_write(p, REG_MODE_1, val);
+
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
+						NO_PAD_CTRL));
+	gpio_request(IMX_GPIO_NR(2, 14), "gpio2_14");
+	gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
+
+	udelay(500);
+
+	gpio_set_value(IMX_GPIO_NR(2, 14), 1);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_iomux_lcd();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_MXC_SPI
+	setup_iomux_spi();
+	power_init();
+#endif
+
+	return 0;
+}
+#endif
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX51EVK\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/mx51evk/mx51evk_video.c b/roms/u-boot/board/freescale/mx51evk/mx51evk_video.c
new file mode 100644
index 000000000..3715c5d73
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx51evk/mx51evk_video.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <linux/list.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx51.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+#define MX51EVK_LCD_3V3		IMX_GPIO_NR(4, 9)
+#define MX51EVK_LCD_5V		IMX_GPIO_NR(4, 10)
+#define MX51EVK_LCD_BACKLIGHT	IMX_GPIO_NR(3, 4)
+
+static struct fb_videomode const claa_wvga = {
+	.name		= "CLAA07LC0ACW",
+	.refresh	= 57,
+	.xres		= 800,
+	.yres		= 480,
+	.pixclock	= 37037,
+	.left_margin	= 40,
+	.right_margin	= 60,
+	.upper_margin	= 10,
+	.lower_margin	= 10,
+	.hsync_len	= 20,
+	.vsync_len	= 10,
+	.sync		= 0,
+	.vmode		= FB_VMODE_NONINTERLACED
+};
+
+static struct fb_videomode const dvi = {
+	.name		= "DVI panel",
+	.refresh	= 60,
+	.xres		= 1024,
+	.yres		= 768,
+	.pixclock	= 15385,
+	.left_margin	= 220,
+	.right_margin	= 40,
+	.upper_margin	= 21,
+	.lower_margin	= 7,
+	.hsync_len	= 60,
+	.vsync_len	= 10,
+	.sync		= 0,
+	.vmode		= FB_VMODE_NONINTERLACED
+};
+
+void setup_iomux_lcd(void)
+{
+	/* DI2_PIN15 */
+	imx_iomux_v3_setup_pad(MX51_PAD_DI_GP4__DI2_PIN15);
+
+	/* Pad settings for DI2_DISP_CLK */
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK,
+			    PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW));
+
+	/* Turn on 3.3V voltage for LCD */
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D12__GPIO4_9,
+						NO_PAD_CTRL));
+	gpio_direction_output(MX51EVK_LCD_3V3, 1);
+
+	/* Turn on 5V voltage for LCD */
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D13__GPIO4_10,
+						NO_PAD_CTRL));
+	gpio_direction_output(MX51EVK_LCD_5V, 1);
+
+	/* Turn on GPIO backlight */
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4,
+						NO_PAD_CTRL));
+	gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
+}
+
+int board_video_skip(void)
+{
+	int ret;
+	char const *e = env_get("panel");
+
+	if (e) {
+		if (strcmp(e, "claa") == 0) {
+			ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
+			if (ret)
+				printf("claa cannot be configured: %d\n", ret);
+			return ret;
+		}
+	}
+
+	/*
+	 * 'panel' env variable not found or has different value than 'claa'
+	 *  Defaulting to dvi output.
+	 */
+	ret = ipuv3_fb_init(&dvi, 0, IPU_PIX_FMT_RGB24);
+	if (ret)
+		printf("dvi cannot be configured: %d\n", ret);
+	return ret;
+}
diff --git a/roms/u-boot/board/freescale/mx53loco/Kconfig b/roms/u-boot/board/freescale/mx53loco/Kconfig
new file mode 100644
index 000000000..5ca1672bf
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx53loco/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX53LOCO
+
+config SYS_BOARD
+	default "mx53loco"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "mx5"
+
+config SYS_CONFIG_NAME
+	default "mx53loco"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx53loco/MAINTAINERS b/roms/u-boot/board/freescale/mx53loco/MAINTAINERS
new file mode 100644
index 000000000..6c2375187
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx53loco/MAINTAINERS
@@ -0,0 +1,7 @@
+MX53LOCO BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+M:	Jason Liu <jason.hui.liu@nxp.com>
+S:	Maintained
+F:	board/freescale/mx53loco/
+F:	include/configs/mx53loco.h
+F:	configs/mx53loco_defconfig
diff --git a/roms/u-boot/board/freescale/mx53loco/Makefile b/roms/u-boot/board/freescale/mx53loco/Makefile
new file mode 100644
index 000000000..d2ebd94dc
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx53loco/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# Jason Liu <r64343@freescale.com>
+
+obj-y			+= mx53loco.o
+obj-$(CONFIG_VIDEO)	+= mx53loco_video.o
diff --git a/roms/u-boot/board/freescale/mx53loco/imximage.cfg b/roms/u-boot/board/freescale/mx53loco/imximage.cfg
new file mode 100644
index 000000000..d12801d19
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx53loco/imximage.cfg
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8724 0x04000000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0x83190000
+DATA 4 0x63fd900c 0x9f5152e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9040 0x05380003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
diff --git a/roms/u-boot/board/freescale/mx53loco/mx53loco.c b/roms/u-boot/board/freescale/mx53loco/mx53loco.c
new file mode 100644
index 000000000..088863056
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx53loco/mx53loco.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <env.h>
+#include <linux/errno.h>
+#include <asm/mach-imx/mx5_video.h>
+#include <i2c.h>
+#include <input.h>
+#include <fsl_esdhc_imx.h>
+#include <asm/gpio.h>
+#include <power/pmic.h>
+#include <dialog_pmic.h>
+#include <fsl_pmic.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+#define MX53LOCO_LCD_POWER		IMX_GPIO_NR(3, 24)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_board_rev(void)
+{
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+		(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	int rev = readl(&fuse->gp[6]);
+
+	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
+		rev = 0;
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_uart(void)
+{
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+	static const iomux_v3_cfg_t i2c1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
+}
+
+static int power_init(void)
+{
+	unsigned int val;
+	int ret;
+	struct pmic *p;
+
+	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
+		ret = pmic_dialog_init(I2C_PMIC);
+		if (ret)
+			return ret;
+
+		p = pmic_get("DIALOG_PMIC");
+		if (!p)
+			return -ENODEV;
+
+		env_set("fdt_file", "imx53-qsb.dtb");
+
+		/* Set VDDA to 1.25V */
+		val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
+		ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
+		if (ret) {
+			printf("Writing to BUCKCORE_REG failed: %d\n", ret);
+			return ret;
+		}
+
+		pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+		val |= DA9052_SUPPLY_VBCOREGO;
+		ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+		if (ret) {
+			printf("Writing to SUPPLY_REG failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Set Vcc peripheral to 1.30V */
+		ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
+		if (ret) {
+			printf("Writing to BUCKPRO_REG failed: %d\n", ret);
+			return ret;
+		}
+
+		ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+		if (ret) {
+			printf("Writing to SUPPLY_REG failed: %d\n", ret);
+			return ret;
+		}
+
+		return ret;
+	}
+
+	if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
+		ret = pmic_init(I2C_0);
+		if (ret)
+			return ret;
+
+		p = pmic_get("FSL_PMIC");
+		if (!p)
+			return -ENODEV;
+
+		env_set("fdt_file", "imx53-qsrb.dtb");
+
+		/* Set VDDGP to 1.25V for 1GHz on SW1 */
+		pmic_reg_read(p, REG_SW_0, &val);
+		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
+		ret = pmic_reg_write(p, REG_SW_0, val);
+		if (ret) {
+			printf("Writing to REG_SW_0 failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Set VCC as 1.30V on SW2 */
+		pmic_reg_read(p, REG_SW_1, &val);
+		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
+		ret = pmic_reg_write(p, REG_SW_1, val);
+		if (ret) {
+			printf("Writing to REG_SW_1 failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Set global reset timer to 4s */
+		pmic_reg_read(p, REG_POWER_CTL2, &val);
+		val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
+		ret = pmic_reg_write(p, REG_POWER_CTL2, val);
+		if (ret) {
+			printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Set VUSBSEL and VUSBEN for USB PHY supply*/
+		pmic_reg_read(p, REG_MODE_0, &val);
+		val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
+		ret = pmic_reg_write(p, REG_MODE_0, val);
+		if (ret) {
+			printf("Writing to REG_MODE_0 failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Set SWBST to 5V in auto mode */
+		val = SWBST_AUTO;
+		ret = pmic_reg_write(p, SWBST_CTRL, val);
+		if (ret) {
+			printf("Writing to SWBST_CTRL failed: %d\n", ret);
+			return ret;
+		}
+
+		return ret;
+	}
+
+	return -1;
+}
+
+static void clock_1GHz(void)
+{
+	int ret;
+	u32 ref_clk = MXC_HCLK;
+	/*
+	 * After increasing voltage to 1.25V, we can switch
+	 * CPU clock to 1GHz and DDR to 400MHz safely
+	 */
+	ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to 1GHZ failed\n");
+
+	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to 400MHz failed\n");
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_iomux_lcd();
+
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	mxc_set_sata_internal_clock();
+	setup_iomux_i2c();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	if (!power_init())
+		clock_1GHz();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX53 LOCO\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/mx53loco/mx53loco_video.c b/roms/u-boot/board/freescale/mx53loco/mx53loco_video.c
new file mode 100644
index 000000000..ff3fc8ce3
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx53loco/mx53loco_video.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <linux/list.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx53.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+#define MX53LOCO_LCD_POWER		IMX_GPIO_NR(3, 24)
+
+static struct fb_videomode const claa_wvga = {
+	.name		= "CLAA07LC0ACW",
+	.refresh	= 57,
+	.xres		= 800,
+	.yres		= 480,
+	.pixclock	= 37037,
+	.left_margin	= 40,
+	.right_margin	= 60,
+	.upper_margin	= 10,
+	.lower_margin	= 10,
+	.hsync_len	= 20,
+	.vsync_len	= 10,
+	.sync		= 0,
+	.vmode		= FB_VMODE_NONINTERLACED
+};
+
+static struct fb_videomode const seiko_wvga = {
+	.name		= "Seiko-43WVF1G",
+	.refresh	= 60,
+	.xres		= 800,
+	.yres		= 480,
+	.pixclock	= 29851, /* picosecond (33.5 MHz) */
+	.left_margin	= 89,
+	.right_margin	= 164,
+	.upper_margin	= 23,
+	.lower_margin	= 10,
+	.hsync_len	= 10,
+	.vsync_len	= 10,
+	.sync		= 0,
+};
+
+void setup_iomux_lcd(void)
+{
+	static const iomux_v3_cfg_t lcd_pads[] = {
+		MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+		MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+		MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+		MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+		MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+		MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+		MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+		MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+		MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+		MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+		MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+		MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+		MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+		MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+		MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+		MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+		MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+		MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+		MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+		MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+		MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+		MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+		MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+		MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+		MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+		MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+		MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+		MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	/* Turn on GPIO backlight */
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_D24__GPIO3_24);
+	gpio_direction_output(MX53LOCO_LCD_POWER, 1);
+
+	/* Turn on display contrast */
+	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+	gpio_direction_output(IMX_GPIO_NR(1, 1), 1);
+}
+
+int board_video_skip(void)
+{
+	int ret;
+	char const *e = env_get("panel");
+
+	if (e) {
+		if (strcmp(e, "seiko") == 0) {
+			ret = ipuv3_fb_init(&seiko_wvga, 0, IPU_PIX_FMT_RGB24);
+			if (ret)
+				printf("Seiko cannot be configured: %d\n", ret);
+			return ret;
+		}
+	}
+
+	/*
+	 * 'panel' env variable not found or has different value than 'seiko'
+	 *  Defaulting to claa lcd.
+	 */
+	ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
+	if (ret)
+		printf("CLAA cannot be configured: %d\n", ret);
+	return ret;
+}
diff --git a/roms/u-boot/board/freescale/mx6memcal/Kconfig b/roms/u-boot/board/freescale/mx6memcal/Kconfig
new file mode 100644
index 000000000..9987cba5d
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6memcal/Kconfig
@@ -0,0 +1,227 @@
+if TARGET_MX6MEMCAL
+
+config SYS_BOARD
+	default "mx6memcal"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6memcal"
+
+menu "mx6memcal specifics"
+choice
+	prompt "Serial console"
+	help
+	  Either UART1 or UART2 will be used as the console for
+	  displaying the calibration values or errors.
+
+config SERIAL_CONSOLE_UART1
+	bool "UART1"
+	help
+	  Select this if your board uses UART1 for its' console.
+
+config SERIAL_CONSOLE_UART2
+	bool "UART2"
+	help
+	  Select this if your board uses UART2 for its' console.
+
+endchoice
+
+choice
+	prompt "UART pads"
+	help
+	  Select the RX and TX pads used for your serial console.
+	  The choices below reflect the most commonly used options
+	  for your UART.
+
+	config UART2_EIM_D26_27
+		bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)"
+		depends on SERIAL_CONSOLE_UART2
+		help
+		  Choose this configuration if you're using pads
+		  EIM_D26 and D27 for a console on UART2.
+		  This is typical for designs that are based on the
+		  NXP SABRELite.
+
+	config UART1_CSI0_DAT10_11
+		bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)"
+		depends on SERIAL_CONSOLE_UART1
+		help
+		  Choose this configuration if you're using pads
+		  CSI0_DAT10 and DAT11 for a console on UART1 as
+		  is done on the i.MX6 Wand board and i.MX6 SabreSD.
+
+	config UART1_UART1
+		bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
+		depends on SERIAL_CONSOLE_UART1
+		help
+		  Choose this configuration if you're using pads
+		  UART1_TXD/RXD for a console on UART1 as is done
+		  on most i.MX6SL designs.
+
+endchoice
+
+config IMXIMAGE_OUTPUT
+	bool "Include output for imximage .cfg files"
+	default y
+	help
+	  Say "Y" if you want output formatted for use in non-SPL
+	  (DCD-style) configuration files.
+
+config DDRWIDTH
+	int "DDR bus width"
+	default 64
+	help
+	  Select either 32 or 64 to reflect the DDR bus width.
+
+config DDRCS
+	int "DDR chip selects"
+	default 2
+	range 1 2
+	help
+	  Select the number of chip selects used in your board design
+
+choice
+	prompt "Memory type"
+	help
+	  Select the type of DDR (DDR3 or LPDDR2) used on your design
+
+config	DDR3
+	bool "DDR3"
+	help
+	  Select this if your board design uses DDR3.
+
+config	LPDDR2
+	bool "LPDDR2"
+	help
+	  Select this if your board design uses LPDDR2.
+
+endchoice
+
+choice
+	prompt "Memory device"
+
+config MT41K512M16TNA
+	bool "Micron MT41K512M16TNA 512Mx16 (1GiB/chip)"
+	depends on DDR3
+
+config MT41K128M16JT
+	bool "Micron MT41K128M16JT 128Mx16 (256 MiB/chip)"
+	depends on DDR3
+
+config H5TQ4G63AFR
+	bool "Hynix H5TQ4G63AFR 256Mx16 (512 MiB/chip)"
+	depends on DDR3
+
+config H5TQ2G63DFR
+	bool "Hynix H5TQ2G63DFR 128Mx16 (256 MiB/chip)"
+	depends on DDR3
+
+config MT42L256M32D2LG
+	bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)"
+	depends on LPDDR2
+
+config MT29PZZZ4D4BKESK
+	bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC"
+	depends on LPDDR2
+
+endchoice
+
+config DDR_ODT
+	int "DDR On-die-termination"
+	default 2
+	range 0 7
+	help
+	  Enter the on-die termination value as an index defined for
+	  IOMUX settings for PAD_DRAM_SDCLK0_P and others.
+	  0 == Disabled
+	  1 == 120 Ohm
+	  2 == 60 Ohm
+	  3 == 40 Ohm
+	  4 == 30 Ohm
+	  5 == 24 Ohm
+	  6 == 20 Ohm
+	  7 == 17 Ohm
+	  Value will be applied to all clock and data lines
+
+
+config DRAM_DRIVE_STRENGTH
+	int "DRAM Drive strength"
+	default 6
+	range 0 7
+	help
+	  Enter drive strength as an index defined for IOMUX settings
+	  for GRP_B1DS and others.
+	  0 == Hi Z
+	  6 == 40 Ohm (default)
+	  7 == 34 Ohm
+	  Value will be applied to all clock and data lines
+
+config RTT_NOM
+	int "RTT_NOM"
+	default 1
+	range 1 2
+	help
+	  Enter the RTT_NOM selector
+	  1 == RZQ/4 (60ohm)
+	  2 == RZQ/2 (120ohm)
+
+config RTT_WR
+	int "RTT_WR"
+	default 1
+	range 0 2
+	help
+	  Enter the RTT_WR selector for MR2
+	  0 == Dynamic ODT disabled
+	  1 == RZQ/4 (60ohm)
+	  2 == RZQ/2 (120ohm)
+
+config RALAT
+	int "Read additional latency"
+	default 5
+	range 0 7
+	help
+	  Enter a latency in number of cycles. This will be added to
+	  CAS and internal delays for which the MMDC will retrieve the
+	  read data from the internal FIFO.
+	  This is used to compensate for board/chip delays.
+
+config WALAT
+	int "Write additional latency"
+	default 0
+	range 0 7
+	help
+	  Enter a latency in number of cycles. This will be added to
+	  CAS and internal delays for which the MMDC will retrieve the
+	  read data from the internal FIFO
+	  This is used to compensate for board/chip delays.
+
+config REFSEL
+	int "Refresh period"
+	range 0 3
+	default 1
+	help
+	  Select the DDR refresh period.
+	  See the description of bitfield REF_SEL in the reference manual
+	  for details.
+	  0 == disabled
+	  1 == 32 kHz
+	  2 == 64 kHz
+	  3 == fast counter
+
+config REFR
+	int "Number of refreshes"
+	range 0 7
+	default 7
+	help
+	   This selects the number of refreshes (-1) during each period.
+	   i.e.:
+	   0 == 1 refresh (tRFC)
+	   7 == 8 refreshes (tRFC*8)
+	   See the description of MDREF[REFR] in the reference manual for
+	   details.
+
+endmenu
+endif
+
diff --git a/roms/u-boot/board/freescale/mx6memcal/MAINTAINERS b/roms/u-boot/board/freescale/mx6memcal/MAINTAINERS
new file mode 100644
index 000000000..5da38f710
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6memcal/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6MEMCAL BOARD
+M:	Eric Nelson <eric@nelint.com>
+S:	Maintained
+F:	board/freescale/mx6memcal/
+F:	include/configs/mx6memcal.h
+F:	configs/mx6memcal_defconfig
+
diff --git a/roms/u-boot/board/freescale/mx6memcal/Makefile b/roms/u-boot/board/freescale/mx6memcal/Makefile
new file mode 100644
index 000000000..fc2d3eb9e
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6memcal/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= spl.o
+else
+obj-y	:= mx6memcal.o
+endif
diff --git a/roms/u-boot/board/freescale/mx6memcal/README b/roms/u-boot/board/freescale/mx6memcal/README
new file mode 100644
index 000000000..9fe2fe2d0
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6memcal/README
@@ -0,0 +1,49 @@
+mx6memcal - a tool for calibrating DDR on i.MX6 boards.
+
+The mx6memcal board isn't a real board, but a tool for use in bring-up of
+new i.MX6 board designs.
+
+It provides a similar function to the tool from NXP([1]) with a number
+of advantages:
+
+1. It's open-source, so it's easier to change if needed.
+   Typical reasons for needing to change include the use of alternate
+   UARTs and PMIC initialization.
+2. It produces an image that's directly loadable with imx_usb [2] or
+   SB_LOADER.exe [3].
+   The NXP tool requires either a cumbersome JTAG connection that
+   makes running the DDR very slow or a working U-Boot image that
+   suffers from a chicken-and-egg problem (i.e. where do you get the
+   DDR parameters for U-Boot?).
+3. It doesn't prompt for parameters, so it's much faster to gather
+   data from multiple boards.
+4. Parameters to the calibration process can be chosen through
+   'make menuconfig'.
+
+When booted, the mx6memcal board will run the DDR calibration
+routines and display the result in a form suitable for cut and
+paste into struct mx6_mmdc_calibration. It can also optionally
+produce output in a form usable in a DCD-style .cfg file.
+
+Selections in Kconfig allow most system design settings to be chosen:
+
+1. The UART number and pad configuration for the UART. Options
+   include support for the most frequent reference designs on
+   i.MX6DQ/SDL (SABRE Lite and SABRESD designs).
+2. The memory bus width (64 and 32-bit)
+3. The number of chip-selects in use
+4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support
+   is incomplete as of this writing.
+5. The type of DDR chips in use. This selection allows re-use of common
+   parts and four DDR3 and two LPDDR2 parts are currently defined
+6. The On-die termination value for the DRAM lines
+7. The DRAM drive strength
+8. The RTT_NOM and RTT_WR termination settings
+9. RALAT/WALAT latency values
+
+References:
+[1] - NXP DDR Stress Test Tool - https://community.nxp.com/docs/DOC-105652
+[2] - Boundary Devices imx_usb_loader
+      https://github.com/boundarydevices/imx_usb_loader
+[3] - Use of SB_Loader.exe
+      https://boundarydevices.com/windows-users-and-unbricking
diff --git a/roms/u-boot/board/freescale/mx6memcal/mx6memcal.c b/roms/u-boot/board/freescale/mx6memcal/mx6memcal.c
new file mode 100644
index 000000000..1cc744fa9
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6memcal/mx6memcal.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mx6memcal board support - provides a minimal, UART-only
+ * U-Boot that's capable of running a memory test.
+ *
+ * Copyright (C) 2016 Nelson Integration, LLC
+ * Author: Eric Nelson <eric@nelint.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: mx6memcal\n");
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
diff --git a/roms/u-boot/board/freescale/mx6memcal/spl.c b/roms/u-boot/board/freescale/mx6memcal/spl.c
new file mode 100644
index 000000000..61d0ca340
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6memcal/spl.c
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Nelson Integration, LLC
+ * Author: Eric Nelson <eric@nelint.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+#ifdef CONFIG_UART2_EIM_D26_27
+	IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif defined(CONFIG_UART1_CSI0_DAT10_11)
+	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif defined(CONFIG_UART1_SD3_DAT6_7)
+	IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif defined(CONFIG_UART1_UART1)
+	MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+#else
+#error select UART console pads
+#endif
+};
+
+#ifdef CONFIG_DDR3
+#define GRP_DDRTYPE	0x000C0000
+#else
+#define GRP_DDRTYPE	0x00080000
+#endif
+
+/* all existing designs have this disabled */
+#define DDR_PKE		0
+
+/* use Kconfig for ODT and DRIVE_STRENGTH */
+#define DDR_ODT	\
+	(CONFIG_DDR_ODT << 8)
+#define DRAM_DRIVE_STRENGTH \
+	(CONFIG_DRAM_DRIVE_STRENGTH << 3)
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs const mx6dq_ddr_ioregs = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+	.dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2 = 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 40 ohm */
+	.dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH,
+	.dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.dram_sdqs0 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs1 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs2 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs3 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs4 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs5 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs6 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs7 = DRAM_DRIVE_STRENGTH,
+
+	/* DQM[0:7]: Differential input, 40 ohm */
+	.dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs const mx6dq_grp_ioregs = {
+	/* DDR3 */
+	.grp_ddr_type = GRP_DDRTYPE,
+	.grp_ddrmode_ctl = DDR_ODT,
+	/* disable DDR pullups */
+	.grp_ddrpke = DDR_PKE,
+	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
+	.grp_addds = DRAM_DRIVE_STRENGTH,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+	.grp_ctlds = DRAM_DRIVE_STRENGTH,
+	/* DATA[00:63]: Differential input, 40 ohm */
+	.grp_ddrmode = DDR_ODT,
+	.grp_b0ds = DRAM_DRIVE_STRENGTH,
+	.grp_b1ds = DRAM_DRIVE_STRENGTH,
+	.grp_b2ds = DRAM_DRIVE_STRENGTH,
+	.grp_b3ds = DRAM_DRIVE_STRENGTH,
+	.grp_b4ds = DRAM_DRIVE_STRENGTH,
+	.grp_b5ds = DRAM_DRIVE_STRENGTH,
+	.grp_b6ds = DRAM_DRIVE_STRENGTH,
+	.grp_b7ds = DRAM_DRIVE_STRENGTH,
+};
+
+static struct mx6sdl_iomux_ddr_regs const mx6sdl_ddr_ioregs = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+	.dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2 = 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 40 ohm */
+	.dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH,
+	.dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.dram_sdqs0 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs1 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs2 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs3 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs4 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs5 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs6 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs7 = DRAM_DRIVE_STRENGTH,
+
+	/* DQM[0:7]: Differential input, 40 ohm */
+	.dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+static struct mx6sdl_iomux_grp_regs const mx6sdl_grp_ioregs = {
+	/* DDR3 */
+	.grp_ddr_type = GRP_DDRTYPE,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.grp_ddrmode_ctl = DDR_ODT,
+	/* disable DDR pullups */
+	.grp_ddrpke = DDR_PKE,
+	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
+	.grp_addds = DRAM_DRIVE_STRENGTH,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+	.grp_ctlds = DRAM_DRIVE_STRENGTH,
+	/* DATA[00:63]: Differential input, 40 ohm */
+	.grp_ddrmode = DDR_ODT,
+	.grp_b0ds = DRAM_DRIVE_STRENGTH,
+	.grp_b1ds = DRAM_DRIVE_STRENGTH,
+	.grp_b2ds = DRAM_DRIVE_STRENGTH,
+	.grp_b3ds = DRAM_DRIVE_STRENGTH,
+	.grp_b4ds = DRAM_DRIVE_STRENGTH,
+	.grp_b5ds = DRAM_DRIVE_STRENGTH,
+	.grp_b6ds = DRAM_DRIVE_STRENGTH,
+	.grp_b7ds = DRAM_DRIVE_STRENGTH,
+};
+
+const struct mx6sl_iomux_ddr_regs mx6sl_ddr_ioregs = {
+	.dram_sdqs0 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs1 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs2 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs3 = DRAM_DRIVE_STRENGTH,
+	.dram_dqm0 = DRAM_DRIVE_STRENGTH,
+	.dram_dqm1 = DRAM_DRIVE_STRENGTH,
+	.dram_dqm2 = DRAM_DRIVE_STRENGTH,
+	.dram_dqm3 = DRAM_DRIVE_STRENGTH,
+	.dram_cas  = DRAM_DRIVE_STRENGTH,
+	.dram_ras  = DRAM_DRIVE_STRENGTH,
+	.dram_sdclk_0 = DRAM_DRIVE_STRENGTH,
+	.dram_reset = DRAM_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00020000,
+	.dram_odt0 = 0x00030000 + DRAM_DRIVE_STRENGTH,
+	.dram_odt1 = 0x00030000 + DRAM_DRIVE_STRENGTH,
+};
+
+const struct mx6sl_iomux_grp_regs mx6sl_grp_ioregs = {
+	.grp_b0ds = DRAM_DRIVE_STRENGTH,
+	.grp_b1ds = DRAM_DRIVE_STRENGTH,
+	.grp_b2ds = DRAM_DRIVE_STRENGTH,
+	.grp_b3ds = DRAM_DRIVE_STRENGTH,
+	.grp_addds = DRAM_DRIVE_STRENGTH,
+	.grp_ctlds = DRAM_DRIVE_STRENGTH,
+	.grp_ddrmode_ctl = DDR_ODT,
+	.grp_ddrpke = DDR_PKE,
+	.grp_ddrmode = DDR_ODT,
+	.grp_ddr_type = GRP_DDRTYPE,
+};
+
+static struct mx6_ddr_sysinfo const sysinfo = {
+	/* width of data bus:0=16,1=32,2=64 */
+#if CONFIG_DDRWIDTH == 32
+	.dsize = 1,
+#elif CONFIG_DDRWIDTH == 64
+	.dsize = 2,
+#else
+#error missing CONFIG_DDRWIDTH
+#endif
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density = 32, /* 32Gb per CS */
+
+	/* # of chip selects */
+	.ncs = CONFIG_DDRCS,
+	.cs1_mirror = 0,
+	.bi_on = 1,	/* Bank interleaving enabled */
+	.rtt_nom = CONFIG_RTT_NOM,
+	.rtt_wr = CONFIG_RTT_WR,
+	.ralat = CONFIG_RALAT,	/* Read additional latency */
+	.walat = CONFIG_WALAT,	/* Write additional latency */
+	.mif3_mode = 3,	/* Command prediction working mode */
+#ifdef CONFIG_DDR3
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.sde_to_rst = 0x10,	/* JEDEC value for LPDDR2 - 200us */
+	.pd_fast_exit = 0,	/* immaterial for calibration */
+	.ddr_type = DDR_TYPE_DDR3,
+#else
+	.rst_to_cke = 0x10,	/* JEDEC value for LPDDR2: 200us */
+	.sde_to_rst = 0,	/* LPDDR2 does not need this field */
+	.pd_fast_exit = 0,	/* immaterial for calibration */
+	.ddr_type = DDR_TYPE_LPDDR2,
+#endif
+	.refsel = CONFIG_REFSEL,
+	.refr = CONFIG_REFR,
+};
+
+#ifdef CONFIG_MT41K512M16TNA
+/* Micron MT41K512M16TNA-125 */
+static struct mx6_ddr3_cfg const ddrtype = {
+	.mem_speed = 1600,
+	.density = 8,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 1,
+	.trcd = 1375,
+	.trcmin = 5062,
+	.trasmin = 3750,
+};
+#elif defined(CONFIG_MT41K128M16JT)
+/* Micron MT41K128M16JT-125 */
+static struct mx6_ddr3_cfg const ddrtype = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+#elif defined(CONFIG_H5TQ4G63AFR)
+/* Hynix H5TQ4G63AFR */
+static struct mx6_ddr3_cfg const ddrtype = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+#elif defined CONFIG_H5TQ2G63DFR
+/* Hynix H5TQ2G63DFR */
+static struct mx6_ddr3_cfg const ddrtype = {
+	.mem_speed = 1333,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1350,
+	.trcmin = 4950,
+	.trasmin = 3600,
+};
+#elif defined(CONFIG_MT42L256M32D2LG)
+/* Micron MT42L256M32D2LG */
+static struct mx6_lpddr2_cfg ddrtype = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 32,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.trcd_lp = 2000,
+	.trppb_lp = 2000,
+	.trpab_lp = 2250,
+	.trasmin = 4200,
+};
+#elif defined(CONFIG_MT29PZZZ4D4BKESK)
+/* Micron MT29PZZZ4D4BKESK */
+static struct mx6_lpddr2_cfg ddrtype = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 32,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.trcd_lp = 2000,
+	.trppb_lp = 2000,
+	.trpab_lp = 2250,
+	.trasmin = 4200,
+};
+#else
+#error please select DDR type using menuconfig
+#endif
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* FIXME: these should probably be checked, especially
+	 * for i.MX6SL, UL, ULL
+	 */
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void display_calibration(struct mx6_mmdc_calibration *calib)
+{
+	printf(".p0_mpdgctrl0\t= 0x%08X\n", calib->p0_mpdgctrl0);
+	printf(".p0_mpdgctrl1\t= 0x%08X\n", calib->p0_mpdgctrl1);
+	printf(".p0_mprddlctl\t= 0x%08X\n", calib->p0_mprddlctl);
+	printf(".p0_mpwrdlctl\t= 0x%08X\n", calib->p0_mpwrdlctl);
+	printf(".p0_mpwldectrl0\t= 0x%08X\n", calib->p0_mpwldectrl0);
+	printf(".p0_mpwldectrl1\t= 0x%08X\n", calib->p0_mpwldectrl1);
+	if (sysinfo.dsize == 2) {
+		printf(".p1_mpdgctrl0\t= 0x%08X\n", calib->p1_mpdgctrl0);
+		printf(".p1_mpdgctrl1\t= 0x%08X\n", calib->p1_mpdgctrl1);
+		printf(".p1_mprddlctl\t= 0x%08X\n", calib->p1_mprddlctl);
+		printf(".p1_mpwrdlctl\t= 0x%08X\n", calib->p1_mpwrdlctl);
+		printf(".p1_mpwldectrl0\t= 0x%08X\n", calib->p1_mpwldectrl0);
+		printf(".p1_mpwldectrl1\t= 0x%08X\n", calib->p1_mpwldectrl1);
+	}
+#ifdef CONFIG_IMXIMAGE_OUTPUT
+	printf("DATA 4 MX6_MMDC_P0_MPDGCTRL0\t= 0x%08X\n", calib->p0_mpdgctrl0);
+	printf("DATA 4 MX6_MMDC_P0_MPDGCTRL1\t= 0x%08X\n", calib->p0_mpdgctrl1);
+	printf("DATA 4 MX6_MMDC_P0_MPRDDLCTL\t= 0x%08X\n", calib->p0_mprddlctl);
+	printf("DATA 4 MX6_MMDC_P0_MPWRDLCTL\t= 0x%08X\n", calib->p0_mpwrdlctl);
+	printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL0\t= 0x%08X\n",
+	       calib->p0_mpwldectrl0);
+	printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL1\t= 0x%08X\n",
+	       calib->p0_mpwldectrl1);
+	if (sysinfo.dsize == 2) {
+		printf("DATA 4 MX6_MMDC_P1_MPDGCTRL0\t= 0x%08X\n",
+		       calib->p1_mpdgctrl0);
+		printf("DATA 4 MX6_MMDC_P1_MPDGCTRL1\t= 0x%08X\n",
+		       calib->p1_mpdgctrl1);
+		printf("DATA 4 MX6_MMDC_P1_MPRDDLCTL\t= 0x%08X\n",
+		       calib->p1_mprddlctl);
+		printf("DATA 4 MX6_MMDC_P1_MPWRDLCTL\t= 0x%08X\n",
+		       calib->p1_mpwrdlctl);
+		printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL0\t= 0x%08X\n",
+		       calib->p1_mpwldectrl0);
+		printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL1\t= 0x%08X\n",
+		       calib->p1_mpwldectrl1);
+	}
+#endif
+}
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+	int errs;
+	struct mx6_mmdc_calibration calibration = {0};
+
+	memset((void *)gd, 0, sizeof(struct global_data));
+
+	/* write leveling calibration defaults */
+	calibration.p0_mpwrdlctl = 0x40404040;
+	calibration.p1_mpwrdlctl = 0x40404040;
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+
+	SETUP_IOMUX_PADS(uart_pads);
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	if (sysinfo.dsize != 1) {
+		if (is_cpu_type(MXC_CPU_MX6SX) ||
+		    is_cpu_type(MXC_CPU_MX6UL) ||
+		    is_cpu_type(MXC_CPU_MX6ULL) ||
+		    is_cpu_type(MXC_CPU_MX6SL)) {
+			printf("cpu type 0x%x doesn't support 64-bit bus\n",
+			       get_cpu_type());
+			reset_cpu();
+		}
+	}
+#ifdef CONFIG_MX6SL
+	mx6sl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sl_ddr_ioregs,
+			 &mx6sl_grp_ioregs);
+#else
+	if (is_cpu_type(MXC_CPU_MX6Q)) {
+		mx6dq_dram_iocfg(CONFIG_DDRWIDTH, &mx6dq_ddr_ioregs,
+				 &mx6dq_grp_ioregs);
+	} else {
+		mx6sdl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sdl_ddr_ioregs,
+				  &mx6sdl_grp_ioregs);
+	}
+#endif
+	mx6_dram_cfg(&sysinfo, &calibration, &ddrtype);
+
+	errs = mmdc_do_write_level_calibration(&sysinfo);
+	if (errs) {
+		printf("error %d from write level calibration\n", errs);
+	} else {
+		errs = mmdc_do_dqs_calibration(&sysinfo);
+		if (errs) {
+			printf("error %d from dqs calibration\n", errs);
+		} else {
+			printf("completed successfully\n");
+			mmdc_read_calibration(&sysinfo, &calibration);
+			display_calibration(&calibration);
+		}
+	}
+}
diff --git a/roms/u-boot/board/freescale/mx6sabreauto/Kconfig b/roms/u-boot/board/freescale/mx6sabreauto/Kconfig
new file mode 100644
index 000000000..5b4faf6d5
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sabreauto/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6SABREAUTO
+
+config SYS_BOARD
+	default "mx6sabreauto"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6sabreauto"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx6sabreauto/MAINTAINERS b/roms/u-boot/board/freescale/mx6sabreauto/MAINTAINERS
new file mode 100644
index 000000000..6179d672c
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sabreauto/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6SABREAUTO BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/mx6sabreauto/
+F:	include/configs/mx6sabreauto.h
+F:	configs/mx6sabreauto_defconfig
diff --git a/roms/u-boot/board/freescale/mx6sabreauto/Makefile b/roms/u-boot/board/freescale/mx6sabreauto/Makefile
new file mode 100644
index 000000000..7ecdb6b4a
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sabreauto/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+
+obj-y  := mx6sabreauto.o
diff --git a/roms/u-boot/board/freescale/mx6sabreauto/mx6sabreauto.c b/roms/u-boot/board/freescale/mx6sabreauto/mx6sabreauto.c
new file mode 100644
index 000000000..e92ef26d0
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -0,0 +1,1013 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <env.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <miiphy.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <input.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/mach-imx/video.h>
+#include <asm/arch/crm_regs.h>
+#include <pca953x.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC	1
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+
+/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
+static struct i2c_pads_info mx6q_i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.gp = IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.gp = IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+		.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+#ifndef CONFIG_SYS_FLASH_CFI
+/*
+ * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
+ * Compass Sensor, Accelerometer, Res Touch
+ */
+static struct i2c_pads_info mx6q_i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
+		.gp = IMX_GPIO_NR(3, 18)
+	}
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		.i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
+		.gp = IMX_GPIO_NR(3, 18)
+	}
+};
+#endif
+
+static iomux_v3_cfg_t const i2c3_pads[] = {
+	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const port_exp[] = {
+	IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+#ifdef CONFIG_MTD_NOR_FLASH
+static iomux_v3_cfg_t const eimnor_pads[] = {
+	IOMUX_PADS(PAD_EIM_D16__EIM_DATA16	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__EIM_DATA17	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__EIM_DATA18	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__EIM_DATA19	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D20__EIM_DATA20	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D21__EIM_DATA21	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D22__EIM_DATA22	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D23__EIM_DATA23	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D24__EIM_DATA24	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D25__EIM_DATA25	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D26__EIM_DATA26	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__EIM_DATA27	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D28__EIM_DATA28	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D29__EIM_DATA29	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D30__EIM_DATA30	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D31__EIM_DATA31	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA0__EIM_AD00	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA1__EIM_AD01	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA2__EIM_AD02	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA3__EIM_AD03	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA4__EIM_AD04	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA5__EIM_AD05	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA6__EIM_AD06	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA7__EIM_AD07	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA8__EIM_AD08	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA9__EIM_AD09	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA10__EIM_AD10	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA11__EIM_AD11	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA12__EIM_AD12	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA13__EIM_AD13	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA14__EIM_AD14	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA15__EIM_AD15	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_OE__EIM_OE_B		| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_RW__EIM_RW		| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void eimnor_cs_setup(void)
+{
+	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+	writel(0x00020181, &weim_regs->cs0gcr1);
+	writel(0x00000001, &weim_regs->cs0gcr2);
+	writel(0x0a020000, &weim_regs->cs0rcr1);
+	writel(0x0000c000, &weim_regs->cs0rcr2);
+	writel(0x0804a240, &weim_regs->cs0wcr1);
+	writel(0x00000120, &weim_regs->wcr);
+
+	set_chipselect_size(CS0_128);
+}
+
+static void eim_clk_setup(void)
+{
+	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int cscmr1, ccgr6;
+
+
+	/* Turn off EIM clock */
+	ccgr6 = readl(&imx_ccm->CCGR6);
+	ccgr6 &= ~(0x3 << 10);
+	writel(ccgr6, &imx_ccm->CCGR6);
+
+	/*
+	 * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
+	 * and aclk_eim_slow_podf = 01 --> divide by 2
+	 * so that we can have EIM at the maximum clock of 132MHz
+	 */
+	cscmr1 = readl(&imx_ccm->cscmr1);
+	cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
+		    MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
+	cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
+	writel(cscmr1, &imx_ccm->cscmr1);
+
+	/* Turn on EIM clock */
+	ccgr6 |= (0x3 << 10);
+	writel(ccgr6, &imx_ccm->CCGR6);
+}
+
+static void setup_iomux_eimnor(void)
+{
+	SETUP_IOMUX_PADS(eimnor_pads);
+
+	gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+
+	eimnor_cs_setup();
+}
+#endif
+
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart4_pads);
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	gpio_direction_input(IMX_GPIO_NR(6, 15));
+	return !gpio_get_value(IMX_GPIO_NR(6, 15));
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	SETUP_IOMUX_PADS(usdhc3_pads);
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t gpmi_pads[] = {
+	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
+	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS	| MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	SETUP_IOMUX_PADS(gpmi_pads);
+
+	setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+u32 get_board_rev(void)
+{
+	int rev = nxp_board_rev();
+
+	return (get_cpu_rev() & ~(0xF << 8)) | rev;
+}
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8031_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static void disable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	clrbits_le32(&iomux->gpr[2],
+		     IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+		     IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	disable_lvds(dev);
+	imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= NULL,
+	.enable	= NULL,
+	.mode	= {
+		.name           = "Hannstar-XGA",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED,
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+iomux_v3_cfg_t const backlight_pads[] = {
+	IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+};
+
+static void setup_iomux_backlight(void)
+{
+	gpio_request(IMX_GPIO_NR(2, 9), "backlight");
+	gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+	SETUP_IOMUX_PADS(backlight_pads);
+}
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	setup_iomux_backlight();
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	/* Turn on LDB_DI0 and LDB_DI1 clocks */
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+		 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+	       (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+		MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
+	      IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+	      IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+	      IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+	      IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+	      IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+	      IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
+	      IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+		 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
+	reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+		IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
+	       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+		IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+	eim_clk_setup();
+#endif
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
+	if (is_mx6dq() || is_mx6dqp())
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
+	else
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
+	/* I2C 3 Steer */
+	gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
+	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
+	SETUP_IOMUX_PADS(i2c3_pads);
+#ifndef CONFIG_SYS_FLASH_CFI
+	if (is_mx6dq() || is_mx6dqp())
+		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
+	else
+		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
+#endif
+	gpio_request(IMX_GPIO_NR(1, 15), "expander en");
+	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+	SETUP_IOMUX_PADS(port_exp);
+
+#ifdef CONFIG_VIDEO_IPUV3
+	setup_display();
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+	setup_iomux_eimnor();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	unsigned int value;
+
+	p = pfuze_common_init(I2C_PMIC);
+	if (!p)
+		return -ENODEV;
+
+	if (is_mx6dqp()) {
+		/* set SW2 staby volatage 0.975V*/
+		pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+		value &= ~0x3f;
+		value |= 0x17;
+		pmic_reg_write(p, PFUZE100_SW2STBY, value);
+	}
+
+	return pfuze_mode_init(p, APS_PFM);
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{NULL,   0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "SABREAUTO");
+
+	if (is_mx6dqp())
+		env_set("board_rev", "MX6QP");
+	else if (is_mx6dq())
+		env_set("board_rev", "MX6Q");
+	else if (is_mx6sdl())
+		env_set("board_rev", "MX6DL");
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	switch (port) {
+	case 0:
+		/*
+		  * Set daisy chain for otg_pin_id on 6q.
+		 *  For 6dl, this bit is reserved.
+		 */
+		imx_iomux_set_gpr_register(1, 13, 1, 0);
+		break;
+	case 1:
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <asm/arch/mx6-ddr.h>
+#include <spl.h>
+#include <linux/libfdt.h>
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	return 0;
+}
+#endif
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static int mx6q_dcd_table[] = {
+	0x020e0798, 0x000C0000,
+	0x020e0758, 0x00000000,
+	0x020e0588, 0x00000030,
+	0x020e0594, 0x00000030,
+	0x020e056c, 0x00000030,
+	0x020e0578, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e057c, 0x00000030,
+	0x020e058c, 0x00000000,
+	0x020e059c, 0x00000030,
+	0x020e05a0, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e05a8, 0x00000028,
+	0x020e05b0, 0x00000028,
+	0x020e0524, 0x00000028,
+	0x020e051c, 0x00000028,
+	0x020e0518, 0x00000028,
+	0x020e050c, 0x00000028,
+	0x020e05b8, 0x00000028,
+	0x020e05c0, 0x00000028,
+	0x020e0774, 0x00020000,
+	0x020e0784, 0x00000028,
+	0x020e0788, 0x00000028,
+	0x020e0794, 0x00000028,
+	0x020e079c, 0x00000028,
+	0x020e07a0, 0x00000028,
+	0x020e07a4, 0x00000028,
+	0x020e07a8, 0x00000028,
+	0x020e0748, 0x00000028,
+	0x020e05ac, 0x00000028,
+	0x020e05b4, 0x00000028,
+	0x020e0528, 0x00000028,
+	0x020e0520, 0x00000028,
+	0x020e0514, 0x00000028,
+	0x020e0510, 0x00000028,
+	0x020e05bc, 0x00000028,
+	0x020e05c4, 0x00000028,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001F001F,
+	0x021b0810, 0x001F001F,
+	0x021b480c, 0x001F001F,
+	0x021b4810, 0x001F001F,
+	0x021b083c, 0x43260335,
+	0x021b0840, 0x031A030B,
+	0x021b483c, 0x4323033B,
+	0x021b4840, 0x0323026F,
+	0x021b0848, 0x483D4545,
+	0x021b4848, 0x44433E48,
+	0x021b0850, 0x41444840,
+	0x021b4850, 0x4835483E,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020036,
+	0x021b0008, 0x09444040,
+	0x021b000c, 0x8A8F7955,
+	0x021b0010, 0xFF328F64,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x008F1023,
+	0x021b0040, 0x00000047,
+	0x021b0000, 0x841A0000,
+	0x021b001c, 0x04088032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x09408030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025576,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+	0x020c4068, 0x00C03F3F,
+	0x020c406c, 0x0030FC03,
+	0x020c4070, 0x0FFFC000,
+	0x020c4074, 0x3FF00000,
+	0x020c4078, 0xFFFFF300,
+	0x020c407c, 0x0F0000F3,
+	0x020c4080, 0x00000FFF,
+	0x020e0010, 0xF00000CF,
+	0x020e0018, 0x007F007F,
+	0x020e001c, 0x007F007F,
+};
+
+static int mx6qp_dcd_table[] = {
+	0x020e0798, 0x000C0000,
+	0x020e0758, 0x00000000,
+	0x020e0588, 0x00000030,
+	0x020e0594, 0x00000030,
+	0x020e056c, 0x00000030,
+	0x020e0578, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e057c, 0x00000030,
+	0x020e058c, 0x00000000,
+	0x020e059c, 0x00000030,
+	0x020e05a0, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e05a8, 0x00000030,
+	0x020e05b0, 0x00000030,
+	0x020e0524, 0x00000030,
+	0x020e051c, 0x00000030,
+	0x020e0518, 0x00000030,
+	0x020e050c, 0x00000030,
+	0x020e05b8, 0x00000030,
+	0x020e05c0, 0x00000030,
+	0x020e0774, 0x00020000,
+	0x020e0784, 0x00000030,
+	0x020e0788, 0x00000030,
+	0x020e0794, 0x00000030,
+	0x020e079c, 0x00000030,
+	0x020e07a0, 0x00000030,
+	0x020e07a4, 0x00000030,
+	0x020e07a8, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e05ac, 0x00000030,
+	0x020e05b4, 0x00000030,
+	0x020e0528, 0x00000030,
+	0x020e0520, 0x00000030,
+	0x020e0514, 0x00000030,
+	0x020e0510, 0x00000030,
+	0x020e05bc, 0x00000030,
+	0x020e05c4, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001b001e,
+	0x021b0810, 0x002e0029,
+	0x021b480c, 0x001b002a,
+	0x021b4810, 0x0019002c,
+	0x021b083c, 0x43240334,
+	0x021b0840, 0x0324031a,
+	0x021b483c, 0x43340344,
+	0x021b4840, 0x03280276,
+	0x021b0848, 0x44383A3E,
+	0x021b4848, 0x3C3C3846,
+	0x021b0850, 0x2e303230,
+	0x021b4850, 0x38283E34,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08c0, 0x24912492,
+	0x021b48c0, 0x24912492,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020036,
+	0x021b0008, 0x09444040,
+	0x021b000c, 0x898E7955,
+	0x021b0010, 0xFF328F64,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x008E1023,
+	0x021b0040, 0x00000047,
+	0x021b0400, 0x14420000,
+	0x021b0000, 0x841A0000,
+	0x00bb0008, 0x00000004,
+	0x00bb000c, 0x2891E41A,
+	0x00bb0038, 0x00000564,
+	0x00bb0014, 0x00000040,
+	0x00bb0028, 0x00000020,
+	0x00bb002c, 0x00000020,
+	0x021b001c, 0x04088032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x09408030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025576,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+	0x020c4068, 0x00C03F3F,
+	0x020c406c, 0x0030FC03,
+	0x020c4070, 0x0FFFC000,
+	0x020c4074, 0x3FF00000,
+	0x020c4078, 0xFFFFF300,
+	0x020c407c, 0x0F0000F3,
+	0x020c4080, 0x00000FFF,
+	0x020e0010, 0xF00000CF,
+	0x020e0018, 0x77177717,
+	0x020e001c, 0x77177717,
+};
+
+static int mx6dl_dcd_table[] = {
+	0x020e0774, 0x000C0000,
+	0x020e0754, 0x00000000,
+	0x020e04ac, 0x00000030,
+	0x020e04b0, 0x00000030,
+	0x020e0464, 0x00000030,
+	0x020e0490, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e0494, 0x00000030,
+	0x020e04a0, 0x00000000,
+	0x020e04b4, 0x00000030,
+	0x020e04b8, 0x00000030,
+	0x020e076c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e04bc, 0x00000028,
+	0x020e04c0, 0x00000028,
+	0x020e04c4, 0x00000028,
+	0x020e04c8, 0x00000028,
+	0x020e04cc, 0x00000028,
+	0x020e04d0, 0x00000028,
+	0x020e04d4, 0x00000028,
+	0x020e04d8, 0x00000028,
+	0x020e0760, 0x00020000,
+	0x020e0764, 0x00000028,
+	0x020e0770, 0x00000028,
+	0x020e0778, 0x00000028,
+	0x020e077c, 0x00000028,
+	0x020e0780, 0x00000028,
+	0x020e0784, 0x00000028,
+	0x020e078c, 0x00000028,
+	0x020e0748, 0x00000028,
+	0x020e0470, 0x00000028,
+	0x020e0474, 0x00000028,
+	0x020e0478, 0x00000028,
+	0x020e047c, 0x00000028,
+	0x020e0480, 0x00000028,
+	0x020e0484, 0x00000028,
+	0x020e0488, 0x00000028,
+	0x020e048c, 0x00000028,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001F001F,
+	0x021b0810, 0x001F001F,
+	0x021b480c, 0x001F001F,
+	0x021b4810, 0x001F001F,
+	0x021b083c, 0x42190217,
+	0x021b0840, 0x017B017B,
+	0x021b483c, 0x4176017B,
+	0x021b4840, 0x015F016C,
+	0x021b0848, 0x4C4C4D4C,
+	0x021b4848, 0x4A4D4C48,
+	0x021b0850, 0x3F3F3F40,
+	0x021b4850, 0x3538382E,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020025,
+	0x021b0008, 0x00333030,
+	0x021b000c, 0x676B5313,
+	0x021b0010, 0xB66E8B63,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x006B1023,
+	0x021b0040, 0x00000047,
+	0x021b0000, 0x841A0000,
+	0x021b001c, 0x04008032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x05208030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025565,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+	0x020c4068, 0x00C03F3F,
+	0x020c406c, 0x0030FC03,
+	0x020c4070, 0x0FFFC000,
+	0x020c4074, 0x3FF00000,
+	0x020c4078, 0xFFFFF300,
+	0x020c407c, 0x0F0000C3,
+	0x020c4080, 0x00000FFF,
+	0x020e0010, 0xF00000CF,
+	0x020e0018, 0x007F007F,
+	0x020e001c, 0x007F007F,
+};
+
+static void ddr_init(int *table, int size)
+{
+	int i;
+
+	for (i = 0; i < size / 2 ; i++)
+		writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_mx6dq())
+		ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
+	else if (is_mx6dqp())
+		ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
+	else if (is_mx6sdl())
+		ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+}
+
+void board_init_f(ulong dummy)
+{
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_mx6dq()) {
+		if (!strcmp(name, "imx6q-sabreauto"))
+			return 0;
+	} else if (is_mx6dqp()) {
+		if (!strcmp(name, "imx6qp-sabreauto"))
+			return 0;
+	} else if (is_mx6dl()) {
+		if (!strcmp(name, "imx6dl-sabreauto"))
+			return 0;
+	}
+
+	return -1;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mx6sabresd/Kconfig b/roms/u-boot/board/freescale/mx6sabresd/Kconfig
new file mode 100644
index 000000000..e87dea0d7
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sabresd/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6SABRESD
+
+config SYS_BOARD
+	default "mx6sabresd"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6sabresd"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx6sabresd/MAINTAINERS b/roms/u-boot/board/freescale/mx6sabresd/MAINTAINERS
new file mode 100644
index 000000000..5e256ef16
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sabresd/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6SABRESD BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/freescale/mx6sabresd/
+F:	include/configs/mx6sabresd.h
+F:	configs/mx6sabresd_defconfig
diff --git a/roms/u-boot/board/freescale/mx6sabresd/Makefile b/roms/u-boot/board/freescale/mx6sabresd/Makefile
new file mode 100644
index 000000000..92e1ff72a
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sabresd/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+
+obj-y  := mx6sabresd.o
diff --git a/roms/u-boot/board/freescale/mx6sabresd/mx6sabresd.c b/roms/u-boot/board/freescale/mx6sabresd/mx6sabresd.c
new file mode 100644
index 000000000..8c3523085
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sabresd/mx6sabresd.c
@@ -0,0 +1,938 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <image.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/spi.h>
+#include <env.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <miiphy.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <input.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC	1
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define DISP0_PWR_EN	IMX_GPIO_NR(1, 21)
+
+#define KEY_VOL_UP	IMX_GPIO_NR(1, 4)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const bl_pads[] = {
+	IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void enable_backlight(void)
+{
+	SETUP_IOMUX_PADS(bl_pads);
+	gpio_request(DISP0_PWR_EN, "Display Power Enable");
+	gpio_direction_output(DISP0_PWR_EN, 1);
+}
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+	SETUP_IOMUX_PADS(rgb_pads);
+	enable_backlight();
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	enable_backlight();
+}
+
+static struct i2c_pads_info mx6q_i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+		.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+		.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+static void setup_spi(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+}
+
+iomux_v3_cfg_t const di0_pads[] = {
+	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),	/* DISP0_CLK */
+	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),		/* DISP0_HSYNC */
+	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),		/* DISP0_VSYNC */
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC2_BASE_ADDR},
+	{USDHC3_BASE_ADDR},
+	{USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 2)
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 0)
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno - 1;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	case USDHC4_BASE_ADDR:
+		ret = 1; /* eMMC/uSDHC4 is always present */
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned reg = readl(&psrc->sbmr1) >> 11;
+	/*
+	 * Upon reading BOOT_CFG register the following map is done:
+	 * Bit 11 and 12 of BOOT_CFG register can determine the current
+	 * mmc port
+	 * 0x1                  SD1
+	 * 0x2                  SD2
+	 * 0x3                  SD4
+	 */
+
+	switch (reg & 0x3) {
+	case 0x1:
+		SETUP_IOMUX_PADS(usdhc2_pads);
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x2:
+		SETUP_IOMUX_PADS(usdhc3_pads);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x3:
+		SETUP_IOMUX_PADS(usdhc4_pads);
+		usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	}
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8031_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static void disable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	int reg = readl(&iomux->gpr[2]);
+
+	reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+		 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+
+	writel(reg, &iomux->gpr[2]);
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	disable_lvds(dev);
+	imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= NULL,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "Hannstar-XGA",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15384,
+		.left_margin    = 160,
+		.right_margin   = 24,
+		.upper_margin   = 29,
+		.lower_margin   = 3,
+		.hsync_len      = 136,
+		.vsync_len      = 6,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15384,
+		.left_margin    = 160,
+		.right_margin   = 24,
+		.upper_margin   = 29,
+		.lower_margin   = 3,
+		.hsync_len      = 136,
+		.vsync_len      = 6,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 0,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= NULL,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "SEIKO-WVGA",
+		.refresh        = 60,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 29850,
+		.left_margin    = 89,
+		.right_margin   = 164,
+		.upper_margin   = 23,
+		.lower_margin   = 10,
+		.hsync_len      = 10,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
+	SETUP_IOMUX_PADS(di0_pads);
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+	      | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
+	     | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+	     | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+	     | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
+	     | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
+			| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+static void setup_usb(void)
+{
+	/*
+	 * set daisy chain for otg_pin_id on 6q.
+	 * for 6dl, this bit is reserved
+	 */
+	imx_iomux_set_gpr_register(1, 13, 1, 0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
+	if (is_mx6dq() || is_mx6dqp())
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
+	else
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+#ifdef CONFIG_USB_EHCI_MX6
+	setup_usb();
+#endif
+
+	return 0;
+}
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	unsigned int reg;
+	int ret;
+
+	p = pfuze_common_init(I2C_PMIC);
+	if (!p)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* Increase VGEN3 from 2.5 to 2.8V */
+	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
+	reg &= ~LDO_VOL_MASK;
+	reg |= LDOB_2_80V;
+	pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
+
+	/* Increase VGEN5 from 2.8 to 3V */
+	pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
+	reg &= ~LDO_VOL_MASK;
+	reg |= LDOB_3_00V;
+	pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+
+	return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "SABRESD");
+
+	if (is_mx6dqp())
+		env_set("board_rev", "MX6QP");
+	else if (is_mx6dq())
+		env_set("board_rev", "MX6Q");
+	else if (is_mx6sdl())
+		env_set("board_rev", "MX6DL");
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <asm/arch/mx6-ddr.h>
+#include <spl.h>
+#include <linux/libfdt.h>
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	gpio_request(KEY_VOL_UP, "KEY Volume UP");
+	gpio_direction_input(KEY_VOL_UP);
+
+	/* Only enter in Falcon mode if KEY_VOL_UP is pressed */
+	return gpio_get_value(KEY_VOL_UP);
+}
+#endif
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static int mx6q_dcd_table[] = {
+	0x020e0798, 0x000C0000,
+	0x020e0758, 0x00000000,
+	0x020e0588, 0x00000030,
+	0x020e0594, 0x00000030,
+	0x020e056c, 0x00000030,
+	0x020e0578, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e057c, 0x00000030,
+	0x020e058c, 0x00000000,
+	0x020e059c, 0x00000030,
+	0x020e05a0, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e05a8, 0x00000030,
+	0x020e05b0, 0x00000030,
+	0x020e0524, 0x00000030,
+	0x020e051c, 0x00000030,
+	0x020e0518, 0x00000030,
+	0x020e050c, 0x00000030,
+	0x020e05b8, 0x00000030,
+	0x020e05c0, 0x00000030,
+	0x020e0774, 0x00020000,
+	0x020e0784, 0x00000030,
+	0x020e0788, 0x00000030,
+	0x020e0794, 0x00000030,
+	0x020e079c, 0x00000030,
+	0x020e07a0, 0x00000030,
+	0x020e07a4, 0x00000030,
+	0x020e07a8, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e05ac, 0x00000030,
+	0x020e05b4, 0x00000030,
+	0x020e0528, 0x00000030,
+	0x020e0520, 0x00000030,
+	0x020e0514, 0x00000030,
+	0x020e0510, 0x00000030,
+	0x020e05bc, 0x00000030,
+	0x020e05c4, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001F001F,
+	0x021b0810, 0x001F001F,
+	0x021b480c, 0x001F001F,
+	0x021b4810, 0x001F001F,
+	0x021b083c, 0x43270338,
+	0x021b0840, 0x03200314,
+	0x021b483c, 0x431A032F,
+	0x021b4840, 0x03200263,
+	0x021b0848, 0x4B434748,
+	0x021b4848, 0x4445404C,
+	0x021b0850, 0x38444542,
+	0x021b4850, 0x4935493A,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020036,
+	0x021b0008, 0x09444040,
+	0x021b000c, 0x555A7975,
+	0x021b0010, 0xFF538F64,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x005A1023,
+	0x021b0040, 0x00000027,
+	0x021b0000, 0x831A0000,
+	0x021b001c, 0x04088032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x09408030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025576,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+};
+
+static int mx6qp_dcd_table[] = {
+	0x020e0798, 0x000c0000,
+	0x020e0758, 0x00000000,
+	0x020e0588, 0x00000030,
+	0x020e0594, 0x00000030,
+	0x020e056c, 0x00000030,
+	0x020e0578, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e057c, 0x00000030,
+	0x020e058c, 0x00000000,
+	0x020e059c, 0x00000030,
+	0x020e05a0, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e05a8, 0x00000030,
+	0x020e05b0, 0x00000030,
+	0x020e0524, 0x00000030,
+	0x020e051c, 0x00000030,
+	0x020e0518, 0x00000030,
+	0x020e050c, 0x00000030,
+	0x020e05b8, 0x00000030,
+	0x020e05c0, 0x00000030,
+	0x020e0774, 0x00020000,
+	0x020e0784, 0x00000030,
+	0x020e0788, 0x00000030,
+	0x020e0794, 0x00000030,
+	0x020e079c, 0x00000030,
+	0x020e07a0, 0x00000030,
+	0x020e07a4, 0x00000030,
+	0x020e07a8, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e05ac, 0x00000030,
+	0x020e05b4, 0x00000030,
+	0x020e0528, 0x00000030,
+	0x020e0520, 0x00000030,
+	0x020e0514, 0x00000030,
+	0x020e0510, 0x00000030,
+	0x020e05bc, 0x00000030,
+	0x020e05c4, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001b001e,
+	0x021b0810, 0x002e0029,
+	0x021b480c, 0x001b002a,
+	0x021b4810, 0x0019002c,
+	0x021b083c, 0x43240334,
+	0x021b0840, 0x0324031a,
+	0x021b483c, 0x43340344,
+	0x021b4840, 0x03280276,
+	0x021b0848, 0x44383A3E,
+	0x021b4848, 0x3C3C3846,
+	0x021b0850, 0x2e303230,
+	0x021b4850, 0x38283E34,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08c0, 0x24912249,
+	0x021b48c0, 0x24914289,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020036,
+	0x021b0008, 0x24444040,
+	0x021b000c, 0x555A7955,
+	0x021b0010, 0xFF320F64,
+	0x021b0014, 0x01ff00db,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x005A1023,
+	0x021b0040, 0x00000027,
+	0x021b0400, 0x14420000,
+	0x021b0000, 0x831A0000,
+	0x021b0890, 0x00400C58,
+	0x00bb0008, 0x00000000,
+	0x00bb000c, 0x2891E41A,
+	0x00bb0038, 0x00000564,
+	0x00bb0014, 0x00000040,
+	0x00bb0028, 0x00000020,
+	0x00bb002c, 0x00000020,
+	0x021b001c, 0x04088032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x09408030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025576,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+};
+
+static int mx6dl_dcd_table[] = {
+	0x020e0774, 0x000C0000,
+	0x020e0754, 0x00000000,
+	0x020e04ac, 0x00000030,
+	0x020e04b0, 0x00000030,
+	0x020e0464, 0x00000030,
+	0x020e0490, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e0494, 0x00000030,
+	0x020e04a0, 0x00000000,
+	0x020e04b4, 0x00000030,
+	0x020e04b8, 0x00000030,
+	0x020e076c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e04bc, 0x00000030,
+	0x020e04c0, 0x00000030,
+	0x020e04c4, 0x00000030,
+	0x020e04c8, 0x00000030,
+	0x020e04cc, 0x00000030,
+	0x020e04d0, 0x00000030,
+	0x020e04d4, 0x00000030,
+	0x020e04d8, 0x00000030,
+	0x020e0760, 0x00020000,
+	0x020e0764, 0x00000030,
+	0x020e0770, 0x00000030,
+	0x020e0778, 0x00000030,
+	0x020e077c, 0x00000030,
+	0x020e0780, 0x00000030,
+	0x020e0784, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e0470, 0x00000030,
+	0x020e0474, 0x00000030,
+	0x020e0478, 0x00000030,
+	0x020e047c, 0x00000030,
+	0x020e0480, 0x00000030,
+	0x020e0484, 0x00000030,
+	0x020e0488, 0x00000030,
+	0x020e048c, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001F001F,
+	0x021b0810, 0x001F001F,
+	0x021b480c, 0x001F001F,
+	0x021b4810, 0x001F001F,
+	0x021b083c, 0x4220021F,
+	0x021b0840, 0x0207017E,
+	0x021b483c, 0x4201020C,
+	0x021b4840, 0x01660172,
+	0x021b0848, 0x4A4D4E4D,
+	0x021b4848, 0x4A4F5049,
+	0x021b0850, 0x3F3C3D31,
+	0x021b4850, 0x3238372B,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x0002002D,
+	0x021b0008, 0x00333030,
+	0x021b000c, 0x3F435313,
+	0x021b0010, 0xB66E8B63,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x00431023,
+	0x021b0040, 0x00000027,
+	0x021b0000, 0x831A0000,
+	0x021b001c, 0x04008032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x05208030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x0002556D,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+};
+
+static void ddr_init(int *table, int size)
+{
+	int i;
+
+	for (i = 0; i < size / 2 ; i++)
+		writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_mx6dq())
+		ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
+	else if (is_mx6dqp())
+		ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
+	else if (is_mx6sdl())
+		ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+}
+
+void board_init_f(ulong dummy)
+{
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_mx6dq()) {
+		if (!strcmp(name, "imx6q-sabresd"))
+			return 0;
+	} else if (is_mx6dqp()) {
+		if (!strcmp(name, "imx6qp-sabresd"))
+			return 0;
+	} else if (is_mx6dl()) {
+		if (!strcmp(name, "imx6dl-sabresd"))
+			return 0;
+	}
+
+	return -1;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mx6slevk/Kconfig b/roms/u-boot/board/freescale/mx6slevk/Kconfig
new file mode 100644
index 000000000..18482b551
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6slevk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6SLEVK
+
+config SYS_BOARD
+	default "mx6slevk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6slevk"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx6slevk/MAINTAINERS b/roms/u-boot/board/freescale/mx6slevk/MAINTAINERS
new file mode 100644
index 000000000..ae87fe472
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6slevk/MAINTAINERS
@@ -0,0 +1,9 @@
+MX6SLEVK BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/mx6slevk/
+F:	include/configs/mx6slevk.h
+F:	configs/mx6slevk_defconfig
+F:	configs/mx6slevk_spl_defconfig
+F:	configs/mx6slevk_spinor_defconfig
diff --git a/roms/u-boot/board/freescale/mx6slevk/Makefile b/roms/u-boot/board/freescale/mx6slevk/Makefile
new file mode 100644
index 000000000..770f7aac6
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6slevk/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+
+obj-y  := mx6slevk.o
diff --git a/roms/u-boot/board/freescale/mx6slevk/imximage.cfg b/roms/u-boot/board/freescale/mx6slevk/imximage.cfg
new file mode 100644
index 000000000..b97761a51
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6slevk/imximage.cfg
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x020c4018 0x00260324
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020e0344 0x00003030
+DATA 4 0x020e0348 0x00003030
+DATA 4 0x020e034c 0x00003030
+DATA 4 0x020e0350 0x00003030
+DATA 4 0x020e030c 0x00000030
+DATA 4 0x020e0310 0x00000030
+DATA 4 0x020e0314 0x00000030
+DATA 4 0x020e0318 0x00000030
+DATA 4 0x020e0300 0x00000030
+DATA 4 0x020e031c 0x00000030
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e0320 0x00000030
+DATA 4 0x020e032c 0x00000000
+DATA 4 0x020e033c 0x00000008
+DATA 4 0x020e0340 0x00000008
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x020e05cc 0x00000030
+DATA 4 0x020e05d4 0x00000030
+DATA 4 0x020e05d8 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05c8 0x00000030
+DATA 4 0x020e05b0 0x00020000
+DATA 4 0x020e05b4 0x00000000
+DATA 4 0x020e05c0 0x00020000
+DATA 4 0x020e05d0 0x00080000
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b085c 0x1b4700c7
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b0890 0x00400000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b0834 0xf3333333
+DATA 4 0x021b0838 0xf3333333
+DATA 4 0x021b0848 0x4241444a
+DATA 4 0x021b0850 0x3030312b
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x00000000
+DATA 4 0x021b08c0 0x24911492
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b000c 0x33374133
+DATA 4 0x021b0004 0x00020024
+DATA 4 0x021b0010 0x00100A82
+DATA 4 0x021b0014 0x00000093
+DATA 4 0x021b0018 0x00001688
+DATA 4 0x021b002c 0x0f9f26d2
+DATA 4 0x021b0030 0x009f0e10
+DATA 4 0x021b0038 0x00190778
+DATA 4 0x021b0008 0x00000000
+DATA 4 0x021b0040 0x0000004f
+DATA 4 0x021b0000 0xc3110000
+DATA 4 0x021b001c 0x003f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0x82018030
+DATA 4 0x021b001c 0x04028030
+DATA 4 0x021b001c 0x02038030
+DATA 4 0x021b001c 0xff0a8038
+DATA 4 0x021b001c 0x82018038
+DATA 4 0x021b001c 0x04028038
+DATA 4 0x021b001c 0x02038038
+DATA 4 0x021b0800 0xa1310003
+DATA 4 0x021b0020 0x00001800
+DATA 4 0x021b0818 0x00000000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b0004 0x00025564
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
diff --git a/roms/u-boot/board/freescale/mx6slevk/mx6slevk.c b/roms/u-boot/board/freescale/mx6slevk/mx6slevk.c
new file mode 100644
index 000000000..2c90a35e2
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6slevk/mx6slevk.c
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+			PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
+			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
+			PAD_CTL_SRE_FAST)
+
+#define ETH_PHY_POWER	IMX_GPIO_NR(4, 21)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#ifdef CONFIG_SPL_BUILD
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	/* 8 bit SD */
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/*CD pin*/
+	MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/*CD pin*/
+	MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/*CD pin*/
+	MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+#ifdef CONFIG_DM_PMIC_PFUZE100
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+	u32 dev_id, rev_id, i;
+	u32 switch_num = 6;
+	u32 offset = PFUZE100_SW1CMODE;
+
+	ret = pmic_get("pfuze100@08", &dev);
+	if (ret == -ENODEV)
+		return 0;
+
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/* set SW1AB staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
+
+	/* set SW1C staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
+
+	/* Init mode to APS_PFM */
+	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
+
+	for (i = 0; i < switch_num - 1; i++)
+		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+
+static int setup_fec(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
+
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef	CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6SLEVK\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <linux/libfdt.h>
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(5, 0)
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(3, 22)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC1_BASE_ADDR},
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC2_BASE_ADDR:
+		gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+	u32 val;
+	u32 port;
+
+	val = readl(&src_regs->sbmr1);
+
+	/* Boot from USDHC */
+	port = (val >> 11) & 0x3;
+	switch (port) {
+	case 0:
+		imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+						 ARRAY_SIZE(usdhc1_pads));
+		gpio_direction_input(USDHC1_CD_GPIO);
+		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+		break;
+	case 1:
+		imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+						 ARRAY_SIZE(usdhc2_pads));
+		gpio_direction_input(USDHC2_CD_GPIO);
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[0].max_bus_width = 4;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		break;
+	case 2:
+		imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
+						 ARRAY_SIZE(usdhc3_pads));
+		gpio_direction_input(USDHC3_CD_GPIO);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].max_bus_width = 4;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		break;
+	}
+
+	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_sdqs0 = 0x00003030,
+	.dram_sdqs1 = 0x00003030,
+	.dram_sdqs2 = 0x00003030,
+	.dram_sdqs3 = 0x00003030,
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_dqm2 = 0x00000030,
+	.dram_dqm3 = 0x00000030,
+	.dram_cas  = 0x00000030,
+	.dram_ras  = 0x00000030,
+	.dram_sdclk_0 = 0x00000028,
+	.dram_reset = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_odt0 = 0x00000008,
+	.dram_odt1 = 0x00000008,
+};
+
+const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_b0ds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_b2ds = 0x00000030,
+	.grp_b3ds = 0x00000030,
+	.grp_addds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x00080000,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpdgctrl0 =  0x20000000,
+	.p0_mpdgctrl1 =  0x00000000,
+	.p0_mprddlctl =  0x4241444a,
+	.p0_mpwrdlctl =  0x3030312b,
+	.mpzqlp2ctl = 0x1b4700c7,
+};
+
+static struct mx6_lpddr2_cfg mem_ddr = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 32,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.trcd_lp = 2000,
+	.trppb_lp = 2000,
+	.trpab_lp = 2250,
+	.trasmin = 4200,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+
+	writel(0x00260324, &ccm->cbcmr);
+}
+
+static void spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		.dsize = mem_ddr.width / 32,
+		.cs_density = 20,
+		.ncs = 2,
+		.cs1_mirror = 0,
+		.walat = 0,
+		.ralat = 2,
+		.mif3_mode = 3,
+		.bi_on = 1,
+		.rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
+		.rtt_nom = 0,
+		.sde_to_rst = 0,    /* LPDDR2 does not need this field */
+		.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
+		.ddr_type = DDR_TYPE_LPDDR2,
+		.refsel = 0,	/* Refresh cycles at 64KHz */
+		.refr = 3,	/* 4 refresh commands per refresh cycle */
+	};
+	mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mx6sllevk/Kconfig b/roms/u-boot/board/freescale/mx6sllevk/Kconfig
new file mode 100644
index 000000000..4ba9bbf14
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sllevk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6SLLEVK
+
+config SYS_BOARD
+	default "mx6sllevk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6sllevk"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx6sllevk/MAINTAINERS b/roms/u-boot/board/freescale/mx6sllevk/MAINTAINERS
new file mode 100644
index 000000000..b82273c01
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sllevk/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6SLLEVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/mx6sllevk/
+F:	include/configs/mx6sllevk.h
+F:	configs/mx6sllevk_defconfig
+F:	configs/mx6sllevk_plugin_defconfig
diff --git a/roms/u-boot/board/freescale/mx6sllevk/Makefile b/roms/u-boot/board/freescale/mx6sllevk/Makefile
new file mode 100644
index 000000000..8f724ccfc
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sllevk/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+
+obj-y  := mx6sllevk.o
diff --git a/roms/u-boot/board/freescale/mx6sllevk/imximage.cfg b/roms/u-boot/board/freescale/mx6sllevk/imximage.cfg
new file mode 100644
index 000000000..74b3a907b
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sllevk/imximage.cfg
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sllevk/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E0550 0x00080000
+DATA 4 0x020E0534 0x00000000
+DATA 4 0x020E02AC 0x00000030
+DATA 4 0x020E0548 0x00000030
+DATA 4 0x020E052C 0x00000030
+DATA 4 0x020E0530 0x00020000
+DATA 4 0x020E02B0 0x00003030
+DATA 4 0x020E02B4 0x00003030
+DATA 4 0x020E02B8 0x00003030
+DATA 4 0x020E02BC 0x00003030
+DATA 4 0x020E0540 0x00020000
+DATA 4 0x020E0544 0x00000030
+DATA 4 0x020E054C 0x00000030
+DATA 4 0x020E0554 0x00000030
+DATA 4 0x020E0558 0x00000030
+DATA 4 0x020E0294 0x00000030
+DATA 4 0x020E0298 0x00000030
+DATA 4 0x020E029C 0x00000030
+DATA 4 0x020E02A0 0x00000030
+DATA 4 0x020E02C0 0x00082030
+
+DATA 4 0x021B001C 0x00008000
+
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B085c 0x084700C7
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B0848 0x3F393B3C
+DATA 4 0x021B0850 0x262C3826
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B0824 0x33333333
+DATA 4 0x021B0828 0x33333333
+
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B0834 0xf3333333
+DATA 4 0x021B0838 0xf3333333
+DATA 4 0x021B08C0 0x24922492
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B000C 0x53574333
+DATA 4 0x021B0010 0x00100B22
+DATA 4 0x021B0038 0x00170778
+DATA 4 0x021B0014 0x00C700DB
+DATA 4 0x021B0018 0x00201718
+DATA 4 0x021B002C 0x0F9F26D2
+DATA 4 0x021B0030 0x009F0E10
+DATA 4 0x021B0040 0x0000005F
+DATA 4 0x021B0000 0xC4190000
+
+DATA 4 0x021B083C 0x20000000
+
+DATA 4 0x021B001C 0x00008050
+DATA 4 0x021B001C 0x00008058
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0x003F8038
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0xFF0A8038
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x04028038
+DATA 4 0x021B001C 0x83018030
+DATA 4 0x021B001C 0x83018038
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B001C 0x01038038
+
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/roms/u-boot/board/freescale/mx6sllevk/mx6sllevk.c b/roms/u-boot/board/freescale/mx6sllevk/mx6sllevk.c
new file mode 100644
index 000000000..b4fddafe6
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sllevk/mx6sllevk.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_DM_PMIC_PFUZE100
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+	u32 dev_id, rev_id, i;
+	u32 switch_num = 6;
+	u32 offset = PFUZE100_SW1CMODE;
+
+	ret = pmic_get("pfuze100@08", &dev);
+	if (ret == -ENODEV)
+		return 0;
+
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+
+	/* Init mode to APS_PFM */
+	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
+
+	for (i = 0; i < switch_num - 1; i++)
+		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
+
+	/* set SW1AB staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
+
+	/* set SW1C staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6SLL EVK\n");
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+	return devno;
+}
diff --git a/roms/u-boot/board/freescale/mx6sllevk/plugin.S b/roms/u-boot/board/freescale/mx6sllevk/plugin.S
new file mode 100644
index 000000000..dcf5e14d4
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sllevk/plugin.S
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6sll_evk_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x550]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x534]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x2AC]
+	str r1, [r0, #0x548]
+	str r1, [r0, #0x52C]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x530]
+	ldr r1, =0x00003030
+	str r1, [r0, #0x2B0]
+	str r1, [r0, #0x2B4]
+	str r1, [r0, #0x2B8]
+	str r1, [r0, #0x2BC]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x540]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x544]
+	str r1, [r0, #0x54C]
+	str r1, [r0, #0x554]
+	str r1, [r0, #0x558]
+	str r1, [r0, #0x294]
+	str r1, [r0, #0x298]
+	str r1, [r0, #0x29C]
+	str r1, [r0, #0x2A0]
+
+	ldr r1, =0x00082030
+	str r1, [r0, #0x2C0]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x084700C7
+	str r1, [r0, #0x85C]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x3F393B3C
+	str r1, [r0, #0x848]
+	ldr r1, =0x262C3826
+	str r1, [r0, #0x850]
+
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	str r1, [r0, #0x824]
+	str r1, [r0, #0x828]
+
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	str r1, [r0, #0x834]
+	str r1, [r0, #0x838]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x53574333
+	str r1, [r0, #0x00C]
+	ldr r1, =0x00100B22
+	str r1, [r0, #0x010]
+	ldr r1, =0x00170778
+	str r1, [r0, #0x038]
+	ldr r1, =0x00C700DB
+	str r1, [r0, #0x014]
+	ldr r1, =0x00201718
+	str r1, [r0, #0x018]
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000005F
+	str r1, [r0, #0x040]
+	ldr r1, =0xC4190000
+	str r1, [r0, #0x000]
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83C]
+
+	ldr r1, =0x00008050
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008058
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x83018030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x83018038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038038
+	str r1, [r0, #0x01C]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x020]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	str r1, [r0, #0x06c]
+	str r1, [r0, #0x070]
+	str r1, [r0, #0x074]
+	str r1, [r0, #0x078]
+	str r1, [r0, #0x07c]
+	str r1, [r0, #0x080]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+	imx6sll_evk_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/roms/u-boot/board/freescale/mx6sxsabreauto/Kconfig b/roms/u-boot/board/freescale/mx6sxsabreauto/Kconfig
new file mode 100644
index 000000000..ae2ea0243
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sxsabreauto/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6SXSABREAUTO
+
+config SYS_BOARD
+	default "mx6sxsabreauto"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6sxsabreauto"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx6sxsabreauto/MAINTAINERS b/roms/u-boot/board/freescale/mx6sxsabreauto/MAINTAINERS
new file mode 100644
index 000000000..692bbd976
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sxsabreauto/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6SXSABREAUTO BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/freescale/mx6sxsabreauto/
+F:	include/configs/mx6sxsabreauto.h
+F:	configs/mx6sxsabreauto_defconfig
diff --git a/roms/u-boot/board/freescale/mx6sxsabreauto/Makefile b/roms/u-boot/board/freescale/mx6sxsabreauto/Makefile
new file mode 100644
index 000000000..50f29a9dd
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sxsabreauto/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+
+obj-y  := mx6sxsabreauto.o
diff --git a/roms/u-boot/board/freescale/mx6sxsabreauto/imximage.cfg b/roms/u-boot/board/freescale/mx6sxsabreauto/imximage.cfg
new file mode 100644
index 000000000..4a0bcc5f7
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sxsabreauto/imximage.cfg
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000030
+DATA 4 0x020e02fc 0x00000030
+DATA 4 0x020e05f4 0x00000030
+
+/* Control */
+DATA 4 0x020e0340 0x00000030
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000030
+DATA 4 0x020e0314 0x00000030
+DATA 4 0x020e0614 0x00000030
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000030
+DATA 4 0x020e0334 0x00000030
+DATA 4 0x020e0338 0x00000030
+DATA 4 0x020e033c 0x00000030
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000030
+DATA 4 0x020e0610 0x00000030
+DATA 4 0x020e061c 0x00000030
+DATA 4 0x020e0620 0x00000030
+DATA 4 0x020e02ec 0x00000030
+DATA 4 0x020e02f0 0x00000030
+DATA 4 0x020e02f4 0x00000030
+DATA 4 0x020e02f8 0x00000030
+
+/* Calibrations - ZQ */
+DATA 4 0x021b0800 0xa1390003
+
+/* Write leveling */
+DATA 4 0x021b080c 0x002C003D
+DATA 4 0x021b0810 0x00110046
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x4160016C
+DATA 4 0x021b0840 0x013C016C
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x46424446
+DATA 4 0x021b0850 0x3A3C3C3A
+
+DATA 4 0x021b08c0 0x2492244A
+
+/* read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676b52f3
+DATA 4 0x021b0010 0xb66d8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000007f
+DATA 4 0x021b0000 0x85190000
+
+/* Initialize MT41K256M16HA-125 - MR2 */
+DATA 4 0x021b001c 0x04008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00068031
+/* MR0 */
+DATA 4 0x021b001c 0x05208030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00000800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b0004 0x0002556d
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
diff --git a/roms/u-boot/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/roms/u-boot/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
new file mode 100644
index 000000000..7340a3440
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * Author: Ye Li <ye.li@nxp.com>
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                   \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_pads[] = {
+	MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
+
+	return enable_fec_anatop_clock(1, ENET_125MHZ);
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
+	setup_fec();
+
+	ret = fecmxc_initialize_multi(bis, 1,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC%d MXC: %s:failed\n", 1, __func__);
+
+	return ret;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/*
+	 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+	 * Phy control debug reg 0
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	/* rgmii tx clock delay enable */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+	u32 dev_id, rev_id, i;
+	u32 switch_num = 6;
+	u32 offset = PFUZE100_SW1CMODE;
+
+	ret = pmic_get("pfuze100", &dev);
+	if (ret == -ENODEV)
+		return 0;
+
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+
+	/* Init mode to APS_PFM */
+	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
+
+	for (i = 0; i < switch_num - 1; i++)
+		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
+
+	/* set SW1AB staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
+
+	/* set SW1C staby volatage 1.10V */
+	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	/* OGT1 */
+	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* OTG2 */
+	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_QSPI
+int board_qspi_init(void)
+{
+	/* Set the clock */
+	enable_qspi_clk(0);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+iomux_v3_cfg_t gpmi_pads[] = {
+	MX6_PAD_NAND_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WP_B__RAWNAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0),
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+	setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+int board_init(void)
+{
+	struct gpio_desc desc;
+	int ret;
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	ret = dm_gpio_lookup_name("gpio@30_4", &desc);
+	if (ret)
+		return ret;
+
+	ret = dm_gpio_request(&desc, "cpu_per_rst_b");
+	if (ret)
+		return ret;
+	/* Reset CPU_PER_RST_B signal for enet phy and PCIE */
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	udelay(500);
+	dm_gpio_set_value(&desc, 1);
+
+	ret = dm_gpio_lookup_name("gpio@32_2", &desc);
+	if (ret)
+		return ret;
+
+	ret = dm_gpio_request(&desc, "steer_enet");
+	if (ret)
+		return ret;
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	udelay(500);
+	/* Set steering signal to L for selecting B0 */
+	dm_gpio_set_value(&desc, 0);
+
+#ifdef CONFIG_USB_EHCI_MX6
+	setup_usb();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	{"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
+	{"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6SX SABRE AUTO\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/mx6sxsabresd/Kconfig b/roms/u-boot/board/freescale/mx6sxsabresd/Kconfig
new file mode 100644
index 000000000..fcfac0aae
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sxsabresd/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6SXSABRESD
+
+config SYS_BOARD
+	default "mx6sxsabresd"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6sxsabresd"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx6sxsabresd/MAINTAINERS b/roms/u-boot/board/freescale/mx6sxsabresd/MAINTAINERS
new file mode 100644
index 000000000..b3c8b56f1
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sxsabresd/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6SXSABRESD BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/freescale/mx6sxsabresd/
+F:	include/configs/mx6sxsabresd.h
+F:	configs/mx6sxsabresd_defconfig
diff --git a/roms/u-boot/board/freescale/mx6sxsabresd/Makefile b/roms/u-boot/board/freescale/mx6sxsabresd/Makefile
new file mode 100644
index 000000000..266bd4ac4
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sxsabresd/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+
+obj-y  := mx6sxsabresd.o
diff --git a/roms/u-boot/board/freescale/mx6sxsabresd/imximage.cfg b/roms/u-boot/board/freescale/mx6sxsabresd/imximage.cfg
new file mode 100644
index 000000000..28ffb2f8b
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sxsabresd/imximage.cfg
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000020
+DATA 4 0x020e02fc 0x00000020
+DATA 4 0x020e05f4 0x00000020
+
+/* Control */
+DATA 4 0x020e0340 0x00000020
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000020
+DATA 4 0x020e0314 0x00000020
+DATA 4 0x020e0614 0x00000020
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000028
+DATA 4 0x020e0334 0x00000028
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e033c 0x00000028
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+/* Calibrations - ZQ */
+DATA 4 0x021b0800 0xa1390003
+
+/* Write leveling */
+DATA 4 0x021b080c 0x00290025
+DATA 4 0x021b0810 0x00220022
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x41480144
+DATA 4 0x021b0840 0x01340130
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x3C3E4244
+DATA 4 0x021b0850 0x34363638
+
+/* Read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676b52f3
+DATA 4 0x021b0010 0xb66d8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000005f
+DATA 4 0x021b0000 0x84190000
+
+/* Initialize MT41K256M16HA-125 - MR2 */
+DATA 4 0x021b001c 0x04008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00048031
+/* MR0 */
+DATA 4 0x021b001c 0x05208030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00000800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b001c 0x00000000
diff --git a/roms/u-boot/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/roms/u-boot/board/freescale/mx6sxsabresd/mx6sxsabresd.c
new file mode 100644
index 000000000..57fab2386
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <env.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                   \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_b_pad = {
+	MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const peri_3v3_pads[] = {
+	MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const phy_control_pads[] = {
+	/* 25MHz Ethernet PHY Clock */
+	MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+
+	/* ENET PHY Power */
+	MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* AR8031 PHY Reset */
+	MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	int reg, ret;
+
+	/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
+
+	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+	if (ret)
+		return ret;
+
+	imx_iomux_v3_setup_multiple_pads(phy_control_pads,
+					 ARRAY_SIZE(phy_control_pads));
+
+	/* Enable the ENET power, active low */
+	gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
+	gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
+
+	/* Reset AR8031 PHY */
+	gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
+	gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
+	mdelay(10);
+	gpio_set_value(IMX_GPIO_NR(2, 7), 1);
+
+	reg = readl(&anatop->pll_enet);
+	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
+	writel(reg, &anatop->pll_enet);
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+	setup_fec();
+
+	return cpu_eth_init(bis);
+}
+
+int power_init_board(void)
+{
+	struct udevice *dev;
+	unsigned int reg;
+	int ret;
+
+	dev = pfuze_common_init();
+	if (!dev)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* Enable power of VGEN5 3V3, needed for SD3 */
+	reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
+	reg &= ~LDO_VOL_MASK;
+	reg |= (LDOB_3_30V | (1 << LDO_EN));
+	pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/*
+	 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+	 * Phy control debug reg 0
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	/* rgmii tx clock delay enable */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
+	imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
+					 ARRAY_SIZE(peri_3v3_pads));
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+#ifdef CONFIG_FSL_QSPI
+
+int board_qspi_init(void)
+{
+	/* Set the clock */
+	enable_qspi_clk(1);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* Use GPIO for Brightness adjustment, duty cycle = period */
+	MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static int setup_lcd(void)
+{
+	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	/* Reset the LCD */
+	gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst");
+	gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
+	udelay(500);
+	gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
+
+	/* Set Brightness to high */
+	gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
+	gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/*
+	 * Because kernel set WDOG_B mux before pad with the common pinctrl
+	 * framwork now and wdog reset will be triggered once set WDOG_B mux
+	 * with default pad setting, we set pad setting here to workaround this.
+	 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
+	 * as GPIO mux firstly here to workaround it.
+	 */
+	imx_iomux_v3_setup_pad(wdog_b_pad);
+
+	/* Active high for ncp692 */
+	gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
+	gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+	setup_lcd();
+#endif
+
+	return 0;
+}
+
+static bool is_reva(void)
+{
+	return (nxp_board_rev() == 1);
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (is_reva())
+		env_set("board_rev", "REVA");
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/mx6ul_14x14_evk/Kconfig b/roms/u-boot/board/freescale/mx6ul_14x14_evk/Kconfig
new file mode 100644
index 000000000..8210cd3cb
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6ul_14x14_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6UL_14X14_EVK || TARGET_MX6UL_9X9_EVK
+
+config SYS_BOARD
+	default "mx6ul_14x14_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6ul_14x14_evk"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx6ul_14x14_evk/MAINTAINERS b/roms/u-boot/board/freescale/mx6ul_14x14_evk/MAINTAINERS
new file mode 100644
index 000000000..7c7a196d2
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6ul_14x14_evk/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6ULEVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/mx6ul_14x14_evk/
+F:	include/configs/mx6ul_14x14_evk.h
+F:	configs/mx6ul_14x14_evk_defconfig
+F:	configs/mx6ul_9x9_evk_defconfig
diff --git a/roms/u-boot/board/freescale/mx6ul_14x14_evk/Makefile b/roms/u-boot/board/freescale/mx6ul_14x14_evk/Makefile
new file mode 100644
index 000000000..272ada720
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6ul_14x14_evk/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+
+obj-y  := mx6ul_14x14_evk.o
diff --git a/roms/u-boot/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/roms/u-boot/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
new file mode 100644
index 000000000..b916ea010
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -0,0 +1,523 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                  \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret, dev_id, rev_id;
+	unsigned int reg;
+
+	ret = pmic_get("pfuze3000", &dev);
+	if (ret == -ENODEV)
+		return 0;
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
+	reg |= 0x1;
+	pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
+
+	/* SW1B step ramp up time from 2us to 4us/25mV */
+	pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
+
+	/* SW1B mode to APS/PFM */
+	pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
+
+	/* SW1B standby voltage set to 0.975V */
+	pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
+
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_QSPI
+static int board_qspi_init(void)
+{
+	/* Set the clock */
+	enable_qspi_clk(0);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+/* At default the 3v3 enables the MIC2026 for VBUS power */
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(int fec_id)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	if (fec_id == 0) {
+		/*
+		 * Use 50M anatop loopback REF_CLK1 for ENET1,
+		 * clear gpr1[13], set gpr1[17].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+	} else {
+		/*
+		 * Use 50M anatop loopback REF_CLK2 for ENET2,
+		 * clear gpr1[14], set gpr1[18].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+	}
+
+	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+static iomux_v3_cfg_t const lcd_pads[] = {
+	/* Use GPIO for Brightness adjustment, duty cycle = period. */
+	MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static int setup_lcd(void)
+{
+	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	/* Reset the LCD */
+	gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
+	gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
+	udelay(500);
+	gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
+
+	/* Set Brightness to high */
+	gpio_request(IMX_GPIO_NR(1, 8), "backlight");
+	gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
+
+	return 0;
+}
+#else
+static inline int setup_lcd(void) { return 0; }
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef	CONFIG_FEC_MXC
+	setup_fec(CONFIG_FEC_ENET_DEV);
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+	setup_usb();
+#endif
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "EVK");
+
+	if (is_mx6ul_9x9_evk())
+		env_set("board_rev", "9X9");
+	else
+		env_set("board_rev", "14X14");
+#endif
+
+	setup_lcd();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	if (is_mx6ul_9x9_evk())
+		puts("Board: MX6UL 9x9 EVK\n");
+	else
+		puts("Board: MX6UL 14x14 EVK\n");
+
+	return 0;
+}
+
+/*
+ * Backlight off and reset LCD before OS handover
+ */
+void board_preboot_os(void)
+{
+	gpio_set_value(IMX_GPIO_NR(1, 8), 0);
+	gpio_set_value(IMX_GPIO_NR(5, 9), 0);
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <linux/libfdt.h>
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
+	.grp_ddr_type = 0x00080000,
+#else
+	.grp_ddr_type = 0x000c0000,
+#endif
+};
+
+#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000000,
+	.dram_odt1 = 0x00000000,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00003030,
+	.dram_sdqs1 = 0x00003030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x20000000,
+	.p0_mprddlctl = 0x4040484f,
+	.p0_mpwrdlctl = 0x40405247,
+	.mpzqlp2ctl = 0x1b4700c7,
+};
+
+static struct mx6_lpddr2_cfg mem_ddr = {
+	.mem_speed = 800,
+	.density = 2,
+	.width = 16,
+	.banks = 4,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.trcd_lp = 1500,
+	.trppb_lp = 1500,
+	.trpab_lp = 2000,
+	.trasmin = 4250,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,
+	.cs_density = 18,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.walat = 0,
+	.ralat = 5,
+	.mif3_mode = 3,
+	.bi_on = 1,
+	.rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
+	.rtt_nom = 0,
+	.sde_to_rst = 0,    /* LPDDR2 does not need this field */
+	.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
+	.ddr_type = DDR_TYPE_LPDDR2,
+	.refsel = 0,	/* Refresh cycles at 64KHz */
+	.refr = 3,	/* 4 refresh commands per refresh cycle */
+};
+
+#else
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x41570155,
+	.p0_mprddlctl = 0x4040474A,
+	.p0_mpwrdlctl = 0x40405550,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,
+	.cs_density = 20,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 2,
+	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
+	.walat = 0,		/* Write additional latency */
+	.ralat = 5,		/* Read additional latency */
+	.mif3_mode = 3,		/* Command prediction working mode */
+	.bi_on = 1,		/* Bank interleaving enabled */
+	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 0,	/* Refresh cycles at 64KHz */
+	.refr = 1,	/* 2 refresh commands per refresh cycle */
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+#endif
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+	writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mx6ullevk/Kconfig b/roms/u-boot/board/freescale/mx6ullevk/Kconfig
new file mode 100644
index 000000000..7eec497e3
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6ullevk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6ULL_14X14_EVK
+
+config SYS_BOARD
+	default "mx6ullevk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6ullevk"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx6ullevk/MAINTAINERS b/roms/u-boot/board/freescale/mx6ullevk/MAINTAINERS
new file mode 100644
index 000000000..3d1b25603
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6ullevk/MAINTAINERS
@@ -0,0 +1,8 @@
+MX6ULLEVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/mx6ullevk/
+F:	include/configs/mx6ullevk.h
+F:	configs/mx6ull_14x14_evk_defconfig
+F:	configs/mx6ull_14x14_evk_plugin_defconfig
+F:	configs/mx6ulz_14x14_evk_defconfig
diff --git a/roms/u-boot/board/freescale/mx6ullevk/Makefile b/roms/u-boot/board/freescale/mx6ullevk/Makefile
new file mode 100644
index 000000000..1ff03b5f1
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6ullevk/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+
+obj-y  := mx6ullevk.o
diff --git a/roms/u-boot/board/freescale/mx6ullevk/imximage.cfg b/roms/u-boot/board/freescale/mx6ullevk/imximage.cfg
new file mode 100644
index 000000000..155503997
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6ullevk/imximage.cfg
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6ullevk/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x000C0030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000004
+DATA 4 0x021B083C 0x41640158
+DATA 4 0x021B0848 0x40403237
+DATA 4 0x021B0850 0x40403C33
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00944009
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D0B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0x84180000
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+
+#endif
diff --git a/roms/u-boot/board/freescale/mx6ullevk/mx6ullevk.c b/roms/u-boot/board/freescale/mx6ullevk/mx6ullevk.c
new file mode 100644
index 000000000..86c11c7bd
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6ullevk/mx6ullevk.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+	return devno;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(int fec_id)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	if (fec_id == 0) {
+		/*
+		 * Use 50MHz anatop loopback REF_CLK1 for ENET1,
+		 * clear gpr1[13], set gpr1[17].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+	} else {
+		/*
+		 * Use 50MHz anatop loopback REF_CLK2 for ENET2,
+		 * clear gpr1[14], set gpr1[18].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+	}
+
+	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef	CONFIG_FEC_MXC
+	setup_fec(CONFIG_FEC_ENET_DEV);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (is_cpu_type(MXC_CPU_MX6ULZ))
+		env_set("board_name", "ULZ-EVK");
+	else
+		env_set("board_name", "EVK");
+	env_set("board_rev", "14X14");
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	if (is_cpu_type(MXC_CPU_MX6ULZ))
+		puts("Board: MX6ULZ 14x14 EVK\n");
+	else
+		puts("Board: MX6ULL 14x14 EVK\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/mx6ullevk/plugin.S b/roms/u-boot/board/freescale/mx6ullevk/plugin.S
new file mode 100644
index 000000000..1f631ff5e
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx6ullevk/plugin.S
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6ull_ddr3_evk_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000C0000
+	str r1, [r0, #0x4B4]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4AC]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x27C]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x250]
+	str r1, [r0, #0x24C]
+	str r1, [r0, #0x490]
+	ldr r1, =0x000C0030
+	str r1, [r0, #0x288]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x270]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x260]
+	str r1, [r0, #0x264]
+	str r1, [r0, #0x4A0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x280]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x284]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x4B0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x498]
+	str r1, [r0, #0x4A4]
+	str r1, [r0, #0x244]
+	str r1, [r0, #0x248]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00000004
+	str r1, [r0, #0x80C]
+	ldr r1, =0x41640158
+	str r1, [r0, #0x83C]
+	ldr r1, =0x40403237
+	str r1, [r0, #0x848]
+	ldr r1, =0x40403C33
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	ldr r1, =0xF3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	ldr r1, =0x00944009
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+	ldr r1, =0x0002002D
+	str r1, [r0, #0x004]
+	ldr r1, =0x1B333030
+	str r1, [r0, #0x008]
+	ldr r1, =0x676B52F3
+	str r1, [r0, #0x00C]
+	ldr r1, =0xB66D0B63
+	str r1, [r0, #0x010]
+	ldr r1, =0x01FF00DB
+	str r1, [r0, #0x014]
+	ldr r1, =0x00201740
+	str r1, [r0, #0x018]
+	ldr r1, =0x00008000
+	str r1, [r0, #0x01C]
+	ldr r1, =0x000026D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x006B1023
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000004F
+	str r1, [r0, #0x040]
+	ldr r1, =0x84180000
+	str r1, [r0, #0x000]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+	ldr r1, =0x02008032
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008033
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00048031
+	str r1, [r0, #0x01C]
+	ldr r1, =0x15208030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04008040
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x020]
+	ldr r1, =0x00000227
+	str r1, [r0, #0x818]
+	ldr r1, =0x0002552D
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #0x68]
+	str r1, [r0, #0x6C]
+	str r1, [r0, #0x70]
+	str r1, [r0, #0x74]
+	str r1, [r0, #0x78]
+	str r1, [r0, #0x7C]
+	str r1, [r0, #0x80]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+	imx6ull_ddr3_evk_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/roms/u-boot/board/freescale/mx7dsabresd/Kconfig b/roms/u-boot/board/freescale/mx7dsabresd/Kconfig
new file mode 100644
index 000000000..c6a969ca6
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx7dsabresd/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX7DSABRESD
+
+config SYS_BOARD
+	default "mx7dsabresd"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx7dsabresd"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx7dsabresd/MAINTAINERS b/roms/u-boot/board/freescale/mx7dsabresd/MAINTAINERS
new file mode 100644
index 000000000..721321c9c
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx7dsabresd/MAINTAINERS
@@ -0,0 +1,8 @@
+MX7DSABRESD BOARD
+M:	Adrian Alonso <adrian.alonso@nxp.com>
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/freescale/mx7dsabresd
+F:	include/configs/mx7dsabresd.h
+F:	configs/mx7dsabresd_defconfig
+F:	configs/mx7dsabresd_qspi_defconfig
diff --git a/roms/u-boot/board/freescale/mx7dsabresd/Makefile b/roms/u-boot/board/freescale/mx7dsabresd/Makefile
new file mode 100644
index 000000000..852b3d87a
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx7dsabresd/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+
+obj-y  := mx7dsabresd.o
diff --git a/roms/u-boot/board/freescale/mx7dsabresd/imximage.cfg b/roms/u-boot/board/freescale/mx7dsabresd/imximage.cfg
new file mode 100644
index 000000000..05446ac83
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx7dsabresd/imximage.cfg
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : sd
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00400046
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x09081109
+DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0184 0x02000100
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00171717
+DATA 4 0x307a0214 0x04040404
+DATA 4 0x307a0218 0x0f040404
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000d6e
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e407304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
diff --git a/roms/u-boot/board/freescale/mx7dsabresd/mx7dsabresd.c b/roms/u-boot/board/freescale/mx7dsabresd/mx7dsabresd.c
new file mode 100644
index 000000000..2777ae13b
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
+#include <i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/crm_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
+	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
+	PAD_CTL_DSE_3P3V_49OHM)
+
+#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL \
+  (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
+
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
+
+#ifdef CONFIG_MXC_SPI
+static iomux_v3_cfg_t const ecspi3_pads[] = {
+    MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+    MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+    MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+    MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+         return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1;
+}
+
+static void setup_spi(void)
+{
+         imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_CLK__NAND_CLE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_CMD__NAND_ALE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_STROBE__NAND_RE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_RESET_B__NAND_WE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_MCLK__NAND_WP_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_TX_SYNC__NAND_DQS	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+	/* NAND_USDHC_BUS_CLK is set in rom */
+	set_clk_nand();
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+
+	MX7D_PAD_LCD_RESET__GPIO3_IO4	| MUX_PAD_CTRL(LCD_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwm_pads[] = {
+	/* Use GPIO for Brightness adjustment, duty cycle = period */
+	MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static int setup_lcd(void)
+{
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
+
+	/* Reset LCD */
+	gpio_request(IMX_GPIO_NR(3, 4), "lcd reset");
+	gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
+	udelay(500);
+	gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
+
+	/* Set Brightness to high */
+	gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight");
+	gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
+
+	return 0;
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	if (devno == 2)
+		devno--;
+
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int dev_no)
+{
+	if (dev_no == 1)
+		dev_no++;
+
+	return dev_no;
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+		(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
+		 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
+
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+int board_qspi_init(void)
+{
+	/* Set the clock */
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+	setup_lcd();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+#ifdef CONFIG_MXC_SPI
+       setup_spi();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret, dev_id, rev_id;
+
+	ret = pmic_get("pfuze3000@8", &dev);
+	if (ret == -ENODEV)
+		return 0;
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
+
+	/*
+	 * Set the voltage of VLDO4 output to 2.8V which feeds
+	 * the MIPI DSI and MIPI CSI inputs.
+	 */
+	pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
+
+	return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	/*
+	 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+	 * since we use PMIC_PWRON to reset the board.
+	 */
+	clrsetbits_le16(&wdog->wcr, 0, 0x10);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *mode;
+
+	if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
+		mode = "secure";
+	else
+		mode = "non-secure";
+
+	printf("Board: i.MX7D SABRESD in %s mode\n", mode);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/mx7ulp_evk/Kconfig b/roms/u-boot/board/freescale/mx7ulp_evk/Kconfig
new file mode 100644
index 000000000..ff448311f
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx7ulp_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX7ULP_EVK
+
+config SYS_BOARD
+	default "mx7ulp_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx7ulp_evk"
+
+endif
diff --git a/roms/u-boot/board/freescale/mx7ulp_evk/MAINTAINERS b/roms/u-boot/board/freescale/mx7ulp_evk/MAINTAINERS
new file mode 100644
index 000000000..1aa264456
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx7ulp_evk/MAINTAINERS
@@ -0,0 +1,7 @@
+MX7ULPEVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/mx7ulp_evk/
+F:	include/configs/mx7ulp_evk.h
+F:	configs/mx7ulp_evk_defconfig
+F:	configs/mx7ulp_evk_plugin_defconfig
diff --git a/roms/u-boot/board/freescale/mx7ulp_evk/Makefile b/roms/u-boot/board/freescale/mx7ulp_evk/Makefile
new file mode 100644
index 000000000..686763d67
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx7ulp_evk/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+
+obj-y  := mx7ulp_evk.o
+
+extra-$(CONFIG_USE_PLUGIN) :=  plugin.bin
+$(obj)/plugin.bin: $(obj)/plugin.o
+	$(OBJCOPY) -O binary --gap-fill 0xff $< $@
diff --git a/roms/u-boot/board/freescale/mx7ulp_evk/imximage.cfg b/roms/u-boot/board/freescale/mx7ulp_evk/imximage.cfg
new file mode 100644
index 000000000..ec3673040
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx7ulp_evk/imximage.cfg
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00dc 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e0508 0x00160002
+DATA 4   0x403E0510 0x00000001
+DATA 4   0x403E0514 0x00000014
+DATA 4   0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+DATA 4   0x403e050c 0x8080801B
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00dc 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x00000180
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0890 0x00400000
+
+DATA 4   0x40AB0848 0x40404040
+DATA 4   0x40AB0850 0x40404040
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB08B8 0x00000800
+
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB000C 0x292C42F3
+DATA 4   0x40AB0010 0x00100A22
+DATA 4   0x40AB0038 0x00120556
+DATA 4   0x40AB0014 0x00C700DB
+DATA 4   0x40AB0018 0x00211718
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0040 0x0000003F
+DATA 4   0x40AB0000 0xC3190000
+
+DATA 4   0x40AB001C 0x00008010
+DATA 4   0x40AB001C 0x00008018
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0x003F8038
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0xFF0A8038
+DATA 4   0x40AB001C 0x04028030
+DATA 4   0x40AB001C 0x04028038
+DATA 4   0x40AB001C 0x83018030
+DATA 4   0x40AB001C 0x83018038
+DATA 4   0x40AB001C 0x01038030
+DATA 4   0x40AB001C 0x01038038
+
+DATA 4   0x40AB083C 0x20000000
+
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1310000
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB0404 0x00011006
+DATA 4   0x40AB001C 0x00000000
+#endif
diff --git a/roms/u-boot/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/roms/u-boot/board/freescale/mx7ulp_evk/mx7ulp_evk.c
new file mode 100644
index 000000000..01e321365
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx7ulp_evk/mx7ulp_evk.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx7ulp-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/mach-imx/boot_mode.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_UP)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_cfg_t const lpuart4_pads[] = {
+	MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
+					 ARRAY_SIZE(lpuart4_pads));
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	const char *path;
+	int rc, nodeoff;
+
+	if (get_boot_device() == USB_BOOT) {
+		path = fdt_get_alias(blob, "mmc0");
+		if (!path) {
+			puts("Not found mmc0\n");
+			return 0;
+		}
+
+		nodeoff = fdt_path_offset(blob, path);
+		if (nodeoff < 0)
+			return 0;
+
+		printf("Found usdhc0 node\n");
+		if (fdt_get_property(blob, nodeoff, "vqmmc-supply",
+		    NULL) != NULL) {
+			rc = fdt_delprop(blob, nodeoff, "vqmmc-supply");
+			if (!rc) {
+				puts("Removed vqmmc-supply property\n");
+add:
+				rc = fdt_setprop(blob, nodeoff,
+						 "no-1-8-v", NULL, 0);
+				if (rc == -FDT_ERR_NOSPACE) {
+					rc = fdt_increase_size(blob, 32);
+					if (!rc)
+						goto add;
+				} else if (rc) {
+					printf("Failed to add no-1-8-v property, %d\n", rc);
+				} else {
+					puts("Added no-1-8-v property\n");
+				}
+			} else {
+				printf("Failed to remove vqmmc-supply property, %d\n", rc);
+			}
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/mx7ulp_evk/plugin.S b/roms/u-boot/board/freescale/mx7ulp_evk/plugin.S
new file mode 100644
index 000000000..2cc93dbdd
--- /dev/null
+++ b/roms/u-boot/board/freescale/mx7ulp_evk/plugin.S
@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
+ */
+
+#include <config.h>
+
+.macro imx7ulp_ddr_freq_decrease
+	ldr r2, =0x403f0000
+	ldr r3, =0x00000000
+	str r3, [r2, #0xdc]
+
+	ldr r2, =0x403e0000
+	ldr r3, =0x01000020
+	str r3, [r2, #0x40]
+	ldr r3, =0x01000000
+	str r3, [r2, #0x500]
+
+	ldr r3, =0x80808080
+	str r3, [r2, #0x50c]
+	ldr r3, =0x00160002
+	str r3, [r2, #0x508]
+	ldr r3, =0x00000001
+	str r3, [r2, #0x510]
+	ldr r3, =0x00000014
+	str r3, [r2, #0x514]
+	ldr r3, =0x00000001
+	str r3, [r2, #0x500]
+
+	ldr r3, =0x01000000
+wait1:
+	ldr r4, [r2, #0x500]
+	and r4, r3
+	cmp r4, r3
+	bne wait1
+
+	ldr r3, =0x8080801B
+	str r3, [r2, #0x50c]
+
+	ldr r3, =0x00000040
+wait2:
+	ldr r4, [r2, #0x50c]
+	and r4, r3
+	cmp r4, r3
+	bne wait2
+
+	ldr r3, =0x00000001
+	str r3, [r2, #0x30]
+	ldr r3, =0x11000020
+	str r3, [r2, #0x40]
+
+	ldr r2, =0x403f0000
+	ldr r3, =0x42000000
+	str r3, [r2, #0xdc]
+
+.endm
+
+.macro imx7ulp_evk_ddr_setting
+
+	imx7ulp_ddr_freq_decrease
+
+	/* Enable MMDC PCC clock */
+	ldr r2, =0x40b30000
+	ldr r3, =0x40000000
+	str r3, [r2, #0xac]
+
+	/* Configure DDR pad */
+	ldr r0, =0x40ad0000
+	ldr r1, =0x00040000
+	str r1, [r0, #0x128]
+	ldr r1, =0x0
+	str r1, [r0, #0xf8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0xd8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x108]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x104]
+	ldr r1, =0x00010000
+	str r1, [r0, #0x124]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x80]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x84]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x88]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x8c]
+
+	ldr r1, =0x00010000
+	str r1, [r0, #0x120]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x10c]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x110]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x114]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x118]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x90]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x94]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x98]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x9c]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe4]
+
+	ldr r0, =0x40ab0000
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1c]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x0D3900A0
+	str r1, [r0, #0x85c]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x40404040
+	str r1, [r0, #0x848]
+	ldr r1, =0x40404040
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81c]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x820]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x824]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x828]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8c0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x292C42F3
+	str r1, [r0, #0xc]
+	ldr r1, =0x00100A22
+	str r1, [r0, #0x10]
+	ldr r1, =0x00120556
+	str r1, [r0, #0x38]
+	ldr r1, =0x00C700DB
+	str r1, [r0, #0x14]
+	ldr r1, =0x00211718
+	str r1, [r0, #0x18]
+
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x2c]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x30]
+	ldr r1, =0x0000003F
+	str r1, [r0, #0x40]
+	ldr r1, =0xC3190000
+	str r1, [r0, #0x0]
+
+	ldr r1, =0x00008010
+	str r1, [r0, #0x1c]
+	ldr r1, =0x00008018
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x83018030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x83018038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038038
+	str r1, [r0, #0x1c]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83c]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x20]
+	ldr r1, =0xA1310000
+	str r1, [r0, #0x800]
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x1c]
+
+.endm
+
+.macro imx7ulp_clock_gating
+.endm
+
+.macro imx7ulp_qos_setting
+.endm
+
+.macro imx7ulp_ddr_setting
+	imx7ulp_evk_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7ulp_plugin.S>
diff --git a/roms/u-boot/board/freescale/p1010rdb/Kconfig b/roms/u-boot/board/freescale/p1010rdb/Kconfig
new file mode 100644
index 000000000..3adac4af1
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1010rdb/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB
+
+config SYS_BOARD
+	default "p1010rdb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "P1010RDB"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/p1010rdb/MAINTAINERS b/roms/u-boot/board/freescale/p1010rdb/MAINTAINERS
new file mode 100644
index 000000000..6e940dd87
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1010rdb/MAINTAINERS
@@ -0,0 +1,21 @@
+P1010RDB BOARD
+M:	Qiang Zhao <qiang.zhao@nxp.com>
+S:	Maintained
+F:	board/freescale/p1010rdb/
+F:	include/configs/P1010RDB.h
+F:	configs/P1010RDB-PA_36BIT_NAND_defconfig
+F:	configs/P1010RDB-PA_36BIT_NOR_defconfig
+F:	configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+F:	configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+F:	configs/P1010RDB-PA_NAND_defconfig
+F:	configs/P1010RDB-PA_NOR_defconfig
+F:	configs/P1010RDB-PA_SDCARD_defconfig
+F:	configs/P1010RDB-PA_SPIFLASH_defconfig
+F:	configs/P1010RDB-PB_36BIT_NAND_defconfig
+F:	configs/P1010RDB-PB_36BIT_NOR_defconfig
+F:	configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+F:	configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+F:	configs/P1010RDB-PB_NAND_defconfig
+F:	configs/P1010RDB-PB_NOR_defconfig
+F:	configs/P1010RDB-PB_SDCARD_defconfig
+F:	configs/P1010RDB-PB_SPIFLASH_defconfig
diff --git a/roms/u-boot/board/freescale/p1010rdb/Makefile b/roms/u-boot/board/freescale/p1010rdb/Makefile
new file mode 100644
index 000000000..36b34c70a
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1010rdb/Makefile
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2010-2011 Freescale Semiconductor, Inc.
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y	+= spl_minimal.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o
+endif
+obj-y	+= p1010rdb.o
+obj-y	+= ddr.o
+endif
+
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PA b/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PA
new file mode 100644
index 000000000..0cb950d84
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PA
@@ -0,0 +1,207 @@
+Overview
+=========
+The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
+
+The P1010 is a cost-effective, low-power, highly integrated host processor
+based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
+that addresses the requirements of several routing, gateways, storage, consumer,
+and industrial applications. Applications of interest include the main CPUs and
+I/O processors in network attached storage (NAS), the voice over IP (VoIP)
+router/gateway, and wireless LAN (WLAN) and industrial controllers.
+
+The P1010RDB board features are as follows:
+Memory subsystem:
+	- 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+	- 32 Mbyte NOR flash single-chip memory
+	- 32 Mbyte NAND flash memory
+	- 256 Kbit M24256 I2C EEPROM
+	- 16 Mbyte SPI memory
+	- I2C Board EEPROM 128x8 bit memory
+	- SD/MMC connector to interface with the SD memory card
+Interfaces:
+	- PCIe:
+		- Lane0: x1 mini-PCIe slot
+		- Lane1: x1 PCIe standard slot
+	- SATA:
+		- 1 internal SATA connector to 2.5” 160G SATA2 HDD
+		- 1 eSATA connector to rear panel
+	- 10/100/1000 BaseT Ethernet ports:
+		- eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
+		- eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
+		- eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
+	- USB 2.0 port:
+		- x1 USB2.0 port via an external ULPI PHY to micro-AB connector
+		- x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
+	- FlexCAN ports:
+		- 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
+		  interface;
+	- DUART interface:
+		- DUART interface: supports two UARTs up to 115200 bps for
+		   console display
+		- RJ45 connectors are used for these 2 UART ports.
+	- TDM
+		- 2 FXS ports connected via an external SLIC to the TDM interface.
+		  SLIC is controllled via SPI.
+		- 1 FXO port connected via a relay to FXS for switchover to POTS
+Board connectors:
+	- Mini-ITX power supply connector
+	- JTAG/COP for debugging
+IEEE Std. 1588 signals for test and measurement
+Real-time clock on I2C bus
+POR
+	- support critical POR setting changed via switch on board
+PCB
+	- 6-layer routing (4-layer signals, 2-layer power and ground)
+
+
+Physical Memory Map on P1010RDB
+===============================
+Address Start   Address End   Memory type	Attributes
+0x0000_0000	0x3fff_ffff   DDR		1G Cacheable
+0xa000_0000	0xdfff_ffff   PCI Express Mem	1G non-cacheable
+0xee00_0000	0xefff_ffff   NOR Flash		32M non-cacheable
+0xffc2_0000	0xffc5_ffff   PCI IO range	256K non-cacheable
+0xffa0_0000	0xffaf_ffff   NAND Flash	1M cacheable
+0xffb0_0000	0xffbf_ffff   Board CPLD	1M non-cacheable
+0xffd0_0000	0xffd0_3fff   L1 for Stack	16K Cacheable TLB0
+0xffe0_0000	0xffef_ffff   CCSR		1M non-cacheable
+
+
+Serial Port Configuration on P1010RDB
+=====================================
+Configure the serial port of the attached computer with the following values:
+	-Data rate: 115200 bps
+	-Number of data bits: 8
+	-Parity: None
+	-Number of Stop bits: 1
+	-Flow Control: Hardware/None
+
+
+Settings of DIP-switch
+======================
+  SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
+  SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
+  SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
+Note: 1 stands for 'on', 0 stands for 'off'
+
+
+Setting of hwconfig
+===================
+If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
+"fsl_p1010mux:tdm_can=tdm" explicitly in u-boot prompt as below for example:
+setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
+By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
+is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
+instead of to CAN/UART1.
+
+
+Build and burn U-Boot to NOR flash
+==================================
+1. Build u-boot.bin image
+	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+	make P1010RDB_NOR
+
+2. Burn u-boot.bin into NOR flash
+	=> tftp $loadaddr $uboot
+	=> protect off eff40000 +$filesize
+	=> erase eff40000 +$filesize
+	=> cp.b $loadaddr eff40000 $filesize
+
+3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
+
+
+Alternate NOR bank
+==================
+1. Burn u-boot.bin into alternate NOR bank
+	=> tftp $loadaddr $uboot
+	=> protect off eef40000 +$filesize
+	=> erase eef40000 +$filesize
+	=> cp.b $loadaddr eef40000 $filesize
+
+2. Switch to alternate NOR bank
+	=> mw.b ffb00009 1
+	=> reset
+	or set SW1[8]= ON
+
+SW1[8]= OFF: Upper bank used for booting start
+SW1[8]= ON:  Lower bank used for booting start
+CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
+0 - boot from upper 4 sectors
+1 - boot from lower 4 sectors
+
+
+Build and burn U-Boot to NAND flash
+===================================
+1. Build u-boot.bin image
+	export ARCH=powerpc
+	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+	make P1010RDB_NAND
+
+2. Burn u-boot-nand.bin into NAND flash
+	=> tftp $loadaddr $uboot-nand
+	=> nand erase 0 $filesize
+	=> nand write $loadaddr 0 $filesize
+
+3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
+
+
+Build and burn U-Boot to SPI flash
+==================================
+1. Build u-boot-spi.bin image
+	make P1010RDB_SPIFLASH_config; make
+	Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
+	Download u-boot.bin to linux and you can find some config files
+	under /usr/share such as config_xx.dat. Do below command:
+	boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
+			u-boot-spi.bin
+	to generate u-boot-spi.bin.
+
+2. Burn u-boot-spi.bin into SPI flash
+	=> tftp $loadaddr $uboot-spi
+	=> sf erase 0 100000
+	=> sf write $loadaddr 0 $filesize
+
+3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
+
+
+CPLD POR setting registers
+==========================
+1. Set POR switch selection register (addr 0xFFB00011) to 0.
+2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
+   proper values.
+   If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
+   switch command by I2C.
+3. Send reset command.
+   After reset, the new POR setting will be implemented.
+
+Two examples are given in below:
+Switch from NOR to NAND boot with default frequency:
+	=> i2c dev 0
+	=> i2c mw 18 1 f9
+	=> i2c mw 18 3 f0
+	=> mw.b ffb00011 0
+	=> mw.b ffb00017 1
+	=> reset
+Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
+	=> i2c dev 0
+	=> i2c mw 18 1 f1
+	=> i2c mw 18 3 f0
+	=> mw.b ffb00011 0
+	=> mw.b ffb00014 2
+	=> mw.b ffb00015 5
+	=> mw.b ffb00016 3
+	=> mw.b ffb00017 f
+	=> reset
+
+
+Boot Linux from network using TFTP on P1010RDB
+==============================================
+Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
+	=> tftp 1000000 uImage
+	=> tftp 2000000 p1010rdb.dtb
+	=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
+	=> bootm 1000000 3000000 2000000
+
+
+For more details, please refer to P1010RDB User Guide and access website
+www.freescale.com
diff --git a/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PB b/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PB
new file mode 100644
index 000000000..4a3b38987
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PB
@@ -0,0 +1,187 @@
+Overview
+=========
+The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
+P1010RDB-PB is a variation of previous P1010RDB-PA board.
+
+The P1010 is a cost-effective, low-power, highly integrated host processor
+based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
+addresses the requirements of several routing, gateways, storage, consumer,
+and industrial applications. Applications of interest include the main CPUs and
+I/O processors in network attached storage (NAS), the voice over IP (VoIP)
+router/gateway, and wireless LAN (WLAN) and industrial controllers.
+
+The P1010RDB-PB board features are as following:
+Memory subsystem:
+	- 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+	- 32M bytes NOR flash single-chip memory
+	- 2G bytes NAND flash memory
+	- 16M bytes SPI memory
+	- 256K bit M24256 I2C EEPROM
+	- I2C Board EEPROM 128x8 bit memory
+	- SD/MMC connector to interface with the SD memory card
+Interfaces:
+	- Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
+	- PCIe 2.0: two x1 mini-PCIe slots
+	- SATA 2.0: two SATA interfaces
+	- USB 2.0: one USB interface
+	- FlexCAN: two FlexCAN interfaces (revision 2.0B)
+	- UART: one USB-to-Serial interface
+	- TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
+	       1 FXO port connected via a relay to FXS for switchover to POTS
+
+Board connectors:
+	- Mini-ITX power supply connector
+	- JTAG/COP for debugging
+
+POR: support critical POR setting changed via switch on board
+PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
+
+Physical Memory Map on P1010RDB
+===============================
+Address Start   Address End   Memory type	Attributes
+0x0000_0000	0x3fff_ffff   DDR		1G Cacheable
+0xa000_0000	0xdfff_ffff   PCI Express Mem	1G non-cacheable
+0xee00_0000	0xefff_ffff   NOR Flash		32M non-cacheable
+0xffc2_0000	0xffc5_ffff   PCI IO range	256K non-cacheable
+0xffa0_0000	0xffaf_ffff   NAND Flash	1M cacheable
+0xffb0_0000	0xffbf_ffff   Board CPLD	1M non-cacheable
+0xffd0_0000	0xffd0_3fff   L1 for Stack	16K Cacheable TLB0
+0xffe0_0000	0xffef_ffff   CCSR		1M non-cacheable
+
+
+Serial Port Configuration on P1010RDB
+=====================================
+Configure the serial port of the attached computer with the following values:
+	-Data rate: 115200 bps
+	-Number of data bits: 8
+	-Parity: None
+	-Number of Stop bits: 1
+	-Flow Control: Hardware/None
+
+
+P1010RDB-PB default DIP-switch settings
+=======================================
+SW1[1:8]= 10101010
+SW2[1:8]= 11011000
+SW3[1:8]= 10010000
+SW4[1:4]= 1010
+SW5[1:8]= 11111010
+
+
+P1010RDB-PB boot mode settings via DIP-switch
+=============================================
+SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
+SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
+SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
+SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
+Note: 1 stands for 'on', 0 stands for 'off'
+
+
+Switch P1010RDB-PB boot mode via software without setting DIP-switch
+====================================================================
+=> run boot_bank0    (boot from NOR bank0)
+=> run boot_bank1    (boot from NOR bank1)
+=> run boot_nand     (boot from NAND flash)
+=> run boot_spi      (boot from SPI flash)
+=> run boot_sd       (boot from SD card)
+
+
+Frequency combination support on P1010RDB-PB
+=============================================
+SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
+0101      1      1010     0       800       400		800
+1001      1      1010     0       800       400		667
+1010      1      1100     0       667       333		667
+1000      0      1010     0       533       266		667
+0101      1      1010     1       1000      400		800
+1001      1      1010     1       1000      400		667
+
+
+Setting of pin mux
+==================
+Since pins multiplexing, TDM and CAN are muxed with SPI flash.
+SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
+
+To enable TDM:
+=> setenv hwconfig fsl_p1010mux:tdm_can=tdm
+=> save;reset
+
+To enable FlexCAN:
+=> setenv hwconfig fsl_p1010mux:tdm_can=can
+=> save;reset
+
+To enable SDHC in case of NOR/NAND/SPI boot
+   a) For temporary use case in runtime without reboot system
+      run 'mux sdhc' in U-Boot to validate SDHC with invalidating IFC.
+
+   b) For long-term use case
+      set 'esdhc' in hwconfig and save it.
+
+To enable IFC in case of SD boot
+   a) For temporary use case in runtime without reboot system
+      run 'mux ifc' in U-Boot to validate IFC with invalidating SDHC.
+
+   b) For long-term use case
+      set 'ifc' in hwconfig and save it.
+
+
+Build images for different boot mode
+====================================
+First setup cross compile environment on build host
+   $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
+
+1. For NOR boot
+   $ make P1010RDB-PB_NOR
+
+2. For NAND boot
+   $ make P1010RDB-PB_NAND
+
+3. For SPI boot
+   $ make P1010RDB-PB_SPIFLASH
+
+4. For SD boot
+   $ make P1010RDB-PB_SDCARD
+
+
+Steps to program images to flash for different boot mode
+========================================================
+1. NOR boot
+   => tftp 1000000 u-boot.bin
+   For bank0
+   => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+   set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
+
+   For bank1
+   => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize
+   set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
+
+2. NAND boot
+   => tftp 1000000 u-boot-nand.bin
+   => nand erase 0 $filesize; nand write $loadaddr 0 $filesize
+   Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
+
+3. SPI boot
+   1)  cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
+   2)  =>  tftp 1000000 u-boot-spi-combined.bin
+   3)  =>  sf probe 0; sf erase 0 100000; sf write 1000000 0 100000
+   set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
+
+4. SD boot
+   1)	cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
+   2)	=> tftp 1000000 u-boot-sd-combined.bin
+   3)	=> mux sdhc
+   4)	=> mmc write 1000000 0 1050
+   set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
+
+
+Boot Linux from network using TFTP on P1010RDB-PB
+=================================================
+Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path.
+	=> tftp 1000000 uImage
+	=> tftp 2000000 p1010rdb.dtb
+	=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
+	=> bootm 1000000 3000000 2000000
+
+
+For more details, please refer to P1010RDB-PB User Guide and access website
+www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/roms/u-boot/board/freescale/p1010rdb/ddr.c b/roms/u-boot/board/freescale/p1010rdb/ddr.c
new file mode 100644
index 000000000..2625195f8
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1010rdb/ddr.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_DRAM_SIZE	1024
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{750, 850, &ddr_cfg_regs_800},
+	{607, 749, &ddr_cfg_regs_667},
+	{0, 0, NULL}
+};
+
+unsigned long get_sdram_size(void)
+{
+	struct cpu_type *cpu;
+	phys_size_t ddr_size;
+
+	cpu = gd->arch.cpu;
+	/* P1014 and it's derivatives support max 16it DDR width */
+	if (cpu->soc_ver == SVR_P1014)
+		ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
+	else
+		ddr_size = CONFIG_SYS_DRAM_SIZE;
+
+	return ddr_size;
+}
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+phys_size_t fixed_sdram(void)
+{
+	int i;
+	char buf[32];
+	fsl_ddr_cfg_regs_t ddr_cfg_regs;
+	phys_size_t ddr_size;
+	ulong ddr_freq, ddr_freq_mhz;
+	struct cpu_type *cpu;
+
+#if defined(CONFIG_SYS_RAMBOOT)
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+#endif
+
+	ddr_freq = get_ddr_freq(0);
+	ddr_freq_mhz = ddr_freq / 1000000;
+
+	printf("Configuring DDR for %s MT/s data rate\n",
+				strmhz(buf, ddr_freq));
+
+	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+			memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
+							sizeof(ddr_cfg_regs));
+			break;
+		}
+	}
+
+	if (fixed_ddr_parm_0[i].max_freq == 0)
+		panic("Unsupported DDR data rate %s MT/s data rate\n",
+					strmhz(buf, ddr_freq));
+
+	cpu = gd->arch.cpu;
+	/* P1014 and it's derivatives support max 16bit DDR width */
+	if (cpu->soc_ver == SVR_P1014) {
+		ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
+		ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
+		/* divide SA and EA by two and then mask the rest so we don't
+		 * write to reserved fields */
+		ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff;
+	}
+
+	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
+					LAW_TRGT_IF_DDR_1) < 0) {
+		printf("ERROR setting Local Access Windows for DDR\n");
+		return 0;
+	}
+
+	return ddr_size;
+}
+
+#else /* CONFIG_SYS_DDR_RAW_TIMING */
+/*
+ * Samsung K4B2G0846C-HCF8
+ * The following timing are for "downshift"
+ * i.e. to use CL9 part as CL7
+ * otherwise, tAA, tRCD, tRP will be 13500ps
+ * and tRC will be 49500ps
+ */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 1875,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR on board";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	struct cpu_type *cpu;
+	int i;
+	popts->clk_adjust = 6;
+	popts->cpo_override = 0x1f;
+	popts->write_data_delay = 2;
+	popts->half_strength_driver_enable = 1;
+	/* Write leveling override */
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x8;
+	popts->trwt_override = 1;
+	popts->trwt = 0;
+
+	cpu = gd->arch.cpu;
+	/* P1014 and it's derivatives support max 16it DDR width */
+	if (cpu->soc_ver == SVR_P1014)
+		popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+	}
+}
+
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/roms/u-boot/board/freescale/p1010rdb/law.c b/roms/u-boot/board/freescale/p1010rdb/law.c
new file mode 100644
index 000000000..debf57148
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1010rdb/law.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/p1010rdb/p1010rdb.c b/roms/u-boot/board/freescale/p1010rdb/p1010rdb.c
new file mode 100644
index 000000000..90436337d
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1010rdb/p1010rdb.c
@@ -0,0 +1,734 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <env.h>
+#include <miiphy.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <pci.h>
+#include <asm/fsl_serdes.h>
+#include <fsl_ifc.h>
+#include <asm/fsl_pci.h>
+#include <hwconfig.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO4_PCIE_RESET_SET		0x08000000
+#define MUX_CPLD_CAN_UART		0x00
+#define MUX_CPLD_TDM			0x01
+#define MUX_CPLD_SPICS0_FLASH		0x00
+#define MUX_CPLD_SPICS0_SLIC		0x02
+#define PMUXCR1_IFC_MASK       0x00ffff00
+#define PMUXCR1_SDHC_MASK      0x00fff000
+#define PMUXCR1_SDHC_ENABLE    0x00555000
+
+enum {
+	MUX_TYPE_IFC,
+	MUX_TYPE_SDHC,
+	MUX_TYPE_SPIFLASH,
+	MUX_TYPE_TDM,
+	MUX_TYPE_CAN,
+	MUX_TYPE_CS0_NOR,
+	MUX_TYPE_CS0_NAND,
+};
+
+enum {
+	I2C_READ_BANK,
+	I2C_READ_PCB_VER,
+};
+
+static uint sd_ifc_mux;
+
+struct cpld_data {
+	u8 cpld_ver; /* cpld revision */
+#if defined(CONFIG_TARGET_P1010RDB_PA)
+	u8 pcba_ver; /* pcb revision number */
+	u8 twindie_ddr3;
+	u8 res1[6];
+	u8 bank_sel; /* NOR Flash bank */
+	u8 res2[5];
+	u8 usb2_sel;
+	u8 res3[1];
+	u8 porsw_sel;
+	u8 tdm_can_sel;
+	u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
+	u8 por0; /* POR Options */
+	u8 por1; /* POR Options */
+	u8 por2; /* POR Options */
+	u8 por3; /* POR Options */
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
+	u8 rom_loc;
+#endif
+};
+
+int board_early_init_f(void)
+{
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	/* Clock configuration to access CPLD using IFC(GPCM) */
+	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+	/*
+	* Reset PCIe slots via GPIO4
+	*/
+	setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
+	setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 2;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash */
+		disable_tlb(flash_esel);
+	}
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_16M, 1);
+
+	set_tlb(1, flashbase + 0x1000000,
+			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
+	return 0;
+}
+
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif /* ifdef CONFIG_PCI */
+
+int config_board_mux(int ctrl_type)
+{
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u8 tmp;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+	int ret;
+#if defined(CONFIG_TARGET_P1010RDB_PA)
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
+				      I2C_PCA9557_ADDR1, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n",
+		       __func__, I2C_PCA9557_BUS_NUM);
+		return ret;
+	}
+	switch (ctrl_type) {
+	case MUX_TYPE_IFC:
+		tmp = 0xf0;
+		dm_i2c_write(dev, 3, &tmp, 1);
+		tmp = 0x01;
+		dm_i2c_write(dev, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_IFC;
+		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+		break;
+	case MUX_TYPE_SDHC:
+		tmp = 0xf0;
+		dm_i2c_write(dev, 3, &tmp, 1);
+		tmp = 0x05;
+		dm_i2c_write(dev, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_SDHC;
+		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+				PMUXCR1_SDHC_ENABLE);
+		break;
+	case MUX_TYPE_SPIFLASH:
+		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
+		break;
+	case MUX_TYPE_TDM:
+		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
+		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
+		break;
+	case MUX_TYPE_CAN:
+		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
+		break;
+	default:
+		break;
+	}
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
+	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
+				      I2C_PCA9557_ADDR2, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n",
+		       __func__, I2C_PCA9557_BUS_NUM);
+		return ret;
+	}
+	switch (ctrl_type) {
+	case MUX_TYPE_IFC:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_IFC;
+		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+		break;
+	case MUX_TYPE_SDHC:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		setbits_8(&tmp, 0x04);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_SDHC;
+		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+				PMUXCR1_SDHC_ENABLE);
+		break;
+	case MUX_TYPE_SPIFLASH:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		clrbits_8(&tmp, 0x80);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x80);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		break;
+	case MUX_TYPE_TDM:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		setbits_8(&tmp, 0x82);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x82);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		break;
+	case MUX_TYPE_CAN:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		clrbits_8(&tmp, 0x02);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x02);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		break;
+	case MUX_TYPE_CS0_NOR:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		break;
+	case MUX_TYPE_CS0_NAND:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		setbits_8(&tmp, 0x08);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		break;
+	default:
+		break;
+	}
+#endif
+#else
+#if defined(CONFIG_TARGET_P1010RDB_PA)
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_IFC:
+		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+		tmp = 0xf0;
+		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
+		tmp = 0x01;
+		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_IFC;
+		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+		break;
+	case MUX_TYPE_SDHC:
+		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+		tmp = 0xf0;
+		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
+		tmp = 0x05;
+		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_SDHC;
+		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+				PMUXCR1_SDHC_ENABLE);
+		break;
+	case MUX_TYPE_SPIFLASH:
+		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
+		break;
+	case MUX_TYPE_TDM:
+		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
+		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
+		break;
+	case MUX_TYPE_CAN:
+		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
+		break;
+	default:
+		break;
+	}
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
+	uint orig_bus = i2c_get_bus_num();
+	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_IFC:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_IFC;
+		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+		break;
+	case MUX_TYPE_SDHC:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		setbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_SDHC;
+		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+				PMUXCR1_SDHC_ENABLE);
+		break;
+	case MUX_TYPE_SPIFLASH:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x80);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x80);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_TDM:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		setbits_8(&tmp, 0x82);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x82);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_CAN:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x02);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x02);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_CS0_NOR:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_CS0_NAND:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		setbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	default:
+		break;
+	}
+	i2c_set_bus_num(orig_bus);
+#endif
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_TARGET_P1010RDB_PB
+int i2c_pca9557_read(int type)
+{
+	u8 val;
+	int bus_num = I2C_PCA9557_BUS_NUM;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n",
+		       __func__, bus_num);
+		return ret;
+	}
+	dm_i2c_read(dev, 0, &val, 1);
+#else
+	i2c_set_bus_num(bus_num);
+	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
+#endif
+
+	switch (type) {
+	case I2C_READ_BANK:
+		val = (val & 0x10) >> 4;
+		break;
+	case I2C_READ_PCB_VER:
+		val = ((val & 0x60) >> 5) + 1;
+		break;
+	default:
+		break;
+	}
+
+	return val;
+}
+#endif
+
+int checkboard(void)
+{
+	struct cpu_type *cpu;
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	u8 val;
+
+	cpu = gd->arch.cpu;
+#if defined(CONFIG_TARGET_P1010RDB_PA)
+	printf("Board: %sRDB-PA, ", cpu->name);
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
+	printf("Board: %sRDB-PB, ", cpu->name);
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       I2C_PCA9557_BUS_NUM);
+		return ret;
+	}
+	val = 0x0;  /* no polarity inversion */
+	dm_i2c_write(dev, 2, &val, 1);
+#else
+	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
+	val = 0x0;  /* no polarity inversion */
+	i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
+#endif
+#endif
+
+#ifdef CONFIG_SDCARD
+	/* switch to IFC to read info from CPLD */
+	config_board_mux(MUX_TYPE_IFC);
+#endif
+
+#if defined(CONFIG_TARGET_P1010RDB_PA)
+	val = (in_8(&cpld_data->pcba_ver) & 0xf);
+	printf("PCB: v%x.0\n", val);
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
+	val = in_8(&cpld_data->cpld_ver);
+	printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
+	printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
+	val = in_8(&cpld_data->rom_loc) & 0xf;
+	puts("Boot from: ");
+	switch (val) {
+	case 0xf:
+		config_board_mux(MUX_TYPE_CS0_NOR);
+		printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
+		break;
+	case 0xe:
+		puts("SDHC\n");
+		val = 0x60; /* set pca9557 pin input/output */
+#if CONFIG_IS_ENABLED(DM_I2C)
+		dm_i2c_write(dev, 3, &val, 1);
+#else
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
+#endif
+		break;
+	case 0x5:
+		config_board_mux(MUX_TYPE_IFC);
+		config_board_mux(MUX_TYPE_CS0_NAND);
+		puts("NAND\n");
+		break;
+	case 0x6:
+		config_board_mux(MUX_TYPE_IFC);
+		puts("SPI\n");
+		break;
+	default:
+		puts("unknown\n");
+		break;
+	}
+#endif
+	return 0;
+}
+
+#ifndef CONFIG_DM_ETH
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_TSEC_ENET
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	struct cpu_type *cpu;
+	int num = 0;
+
+	cpu = gd->arch.cpu;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	/* P1014 and it's derivatives do not support eTSEC3 */
+	if (cpu->soc_ver != SVR_P1014) {
+		SET_STD_TSEC_INFO(tsec_info[num], 3);
+		num++;
+	}
+#endif
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+#endif
+
+	return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_del_flexcan(void *blob)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+				"fsl,p1010-flexcan")) >= 0) {
+		fdt_del_node(blob, nodeoff);
+	}
+}
+
+void fdt_del_spi_flash(void *blob)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+				"spansion,s25sl12801")) >= 0) {
+		fdt_del_node(blob, nodeoff);
+	}
+}
+
+void fdt_del_spi_slic(void *blob)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+				"zarlink,le88266")) >= 0) {
+		fdt_del_node(blob, nodeoff);
+	}
+}
+
+void fdt_del_tdm(void *blob)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+				"fsl,starlite-tdm")) >= 0) {
+		fdt_del_node(blob, nodeoff);
+	}
+}
+
+void fdt_del_sdhc(void *blob)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+			"fsl,esdhc")) >= 0) {
+		fdt_del_node(blob, nodeoff);
+	}
+}
+
+void fdt_del_ifc(void *blob)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+				"fsl,ifc")) >= 0) {
+		fdt_del_node(blob, nodeoff);
+	}
+}
+
+void fdt_disable_uart1(void *blob)
+{
+	int nodeoff;
+
+	nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
+					CONFIG_SYS_NS16550_COM2);
+
+	if (nodeoff > 0) {
+		fdt_status_disabled(blob, nodeoff);
+	} else {
+		printf("WARNING unable to set status for fsl,ns16550 "
+			"uart1: %s\n", fdt_strerror(nodeoff));
+	}
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+	struct cpu_type *cpu;
+
+	cpu = gd->arch.cpu;
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
+	FT_FSL_PCI_SETUP;
+#endif
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+	fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+       /* P1014 and it's derivatives don't support CAN and eTSEC3 */
+	if (cpu->soc_ver == SVR_P1014) {
+		fdt_del_flexcan(blob);
+		fdt_del_node_and_alias(blob, "ethernet2");
+	}
+
+	/* Delete IFC node as IFC pins are multiplexing with SDHC */
+	if (sd_ifc_mux != MUX_TYPE_IFC)
+		fdt_del_ifc(blob);
+	else
+		fdt_del_sdhc(blob);
+
+	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
+		fdt_del_tdm(blob);
+		fdt_del_spi_slic(blob);
+	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
+		fdt_del_flexcan(blob);
+		fdt_del_spi_flash(blob);
+		fdt_disable_uart1(blob);
+	} else {
+		/*
+		 * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
+		 * explicitly, defaultly spi_cs_sel to spi-flash instead of
+		 * to tdm/slic.
+		 */
+		fdt_del_tdm(blob);
+		fdt_del_flexcan(blob);
+		fdt_disable_uart1(blob);
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SDCARD
+int board_mmc_init(struct bd_info *bis)
+{
+	config_board_mux(MUX_TYPE_SDHC);
+		return -1;
+}
+#else
+void board_reset(void)
+{
+	/* mux to IFC to enable CPLD for reset */
+	if (sd_ifc_mux != MUX_TYPE_IFC)
+		config_board_mux(MUX_TYPE_IFC);
+}
+#endif
+
+
+int misc_init_r(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
+		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
+				MPC85xx_PMUXCR_CAN1_UART |
+				MPC85xx_PMUXCR_CAN2_TDM |
+				MPC85xx_PMUXCR_CAN2_UART);
+		config_board_mux(MUX_TYPE_CAN);
+	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
+		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
+				MPC85xx_PMUXCR_CAN1_UART);
+		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
+				MPC85xx_PMUXCR_CAN1_TDM);
+		clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
+		setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
+		config_board_mux(MUX_TYPE_TDM);
+	} else {
+		/* defaultly spi_cs_sel to flash */
+		config_board_mux(MUX_TYPE_SPIFLASH);
+	}
+
+	if (hwconfig("esdhc"))
+		config_board_mux(MUX_TYPE_SDHC);
+	else if (hwconfig("ifc"))
+		config_board_mux(MUX_TYPE_IFC);
+
+#ifdef CONFIG_TARGET_P1010RDB_PB
+	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+#endif
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	if (strcmp(argv[1], "ifc") == 0)
+		config_board_mux(MUX_TYPE_IFC);
+	else if (strcmp(argv[1], "sdhc") == 0)
+		config_board_mux(MUX_TYPE_SDHC);
+	else
+		return CMD_RET_USAGE;
+	return 0;
+}
+
+U_BOOT_CMD(
+	mux, 2, 0, pin_mux_cmd,
+	"configure multiplexing pin for IFC/SDHC bus in runtime",
+	"bus_type (e.g. mux sdhc)"
+);
+#endif
diff --git a/roms/u-boot/board/freescale/p1010rdb/spl.c b/roms/u-boot/board/freescale/p1010rdb/spl.c
new file mode 100644
index 000000000..6c84eef39
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1010rdb/spl.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <console.h>
+#include <env.h>
+#include <env_internal.h>
+#include <init.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include <asm/global_data.h>
+#include "../common/spl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+
+	console_init_f();
+
+	/* Clock configuration to access CPLD using IFC(GPCM) */
+	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+#ifdef CONFIG_TARGET_P1010RDB_PB
+	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
+#endif
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	*/
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	struct bd_info *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(struct bd_info));
+	gd->bd = bd;
+
+	arch_cpu_init();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+
+#ifndef CONFIG_SPL_NAND_BOOT
+	env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+
+	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)SPL_ENV_ADDR);
+			    gd->env_addr  = (ulong)(SPL_ENV_ADDR);
+	gd->env_valid = ENV_VALID;
+#else
+	env_relocate();
+#endif
+
+	i2c_init_all();
+
+	dram_init();
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("\nTertiary program loader running in sram...");
+#else
+	puts("\nSecond program loader running in sram...");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	fsl_spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/roms/u-boot/board/freescale/p1010rdb/spl_minimal.c b/roms/u-boot/board/freescale/p1010rdb/spl_minimal.c
new file mode 100644
index 000000000..989c5b139
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1010rdb/spl_minimal.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+#include <common.h>
+#include <init.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	puts("\nSecond program loader running in sram...");
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r');
+
+	ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
diff --git a/roms/u-boot/board/freescale/p1010rdb/tlb.c b/roms/u-boot/board/freescale/p1010rdb/tlb.c
new file mode 100644
index 000000000..04faefe99
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1010rdb/tlb.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_BOOT
+	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+			0, 2, BOOKE_PAGESZ_16M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
+			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+			0, 3, BOOKE_PAGESZ_16M, 1),
+
+#ifdef CONFIG_PCI
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 4, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_256K, 1),
+#endif
+#endif
+
+	/* *I*G - Board CPLD  */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 6, BOOKE_PAGESZ_256K, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 7, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+			0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/freescale/p1_p2_rdb_pc/Kconfig b/roms/u-boot/board/freescale/p1_p2_rdb_pc/Kconfig
new file mode 100644
index 000000000..cd36150f6
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1_p2_rdb_pc/Kconfig
@@ -0,0 +1,14 @@
+if	TARGET_P1020RDB_PC	|| \
+	TARGET_P1020RDB_PD	|| \
+	TARGET_P2020RDB
+
+config SYS_BOARD
+	default "p1_p2_rdb_pc"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "p1_p2_rdb_pc"
+
+endif
diff --git a/roms/u-boot/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/roms/u-boot/board/freescale/p1_p2_rdb_pc/MAINTAINERS
new file mode 100644
index 000000000..0004d717d
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1_p2_rdb_pc/MAINTAINERS
@@ -0,0 +1,25 @@
+P1_P2_RDB_PC BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	board/freescale/p1_p2_rdb_pc/
+F:	include/configs/p1_p2_rdb_pc.h
+F:	configs/P1020RDB-PC_defconfig
+F:	configs/P1020RDB-PC_36BIT_defconfig
+F:	configs/P1020RDB-PC_36BIT_NAND_defconfig
+F:	configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+F:	configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+F:	configs/P1020RDB-PC_NAND_defconfig
+F:	configs/P1020RDB-PC_SDCARD_defconfig
+F:	configs/P1020RDB-PC_SPIFLASH_defconfig
+F:	configs/P1020RDB-PD_defconfig
+F:	configs/P1020RDB-PD_NAND_defconfig
+F:	configs/P1020RDB-PD_SDCARD_defconfig
+F:	configs/P1020RDB-PD_SPIFLASH_defconfig
+F:	configs/P2020RDB-PC_defconfig
+F:	configs/P2020RDB-PC_36BIT_defconfig
+F:	configs/P2020RDB-PC_36BIT_NAND_defconfig
+F:	configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+F:	configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+F:	configs/P2020RDB-PC_NAND_defconfig
+F:	configs/P2020RDB-PC_SDCARD_defconfig
+F:	configs/P2020RDB-PC_SPIFLASH_defconfig
diff --git a/roms/u-boot/board/freescale/p1_p2_rdb_pc/Makefile b/roms/u-boot/board/freescale/p1_p2_rdb_pc/Makefile
new file mode 100644
index 000000000..a7736d833
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1_p2_rdb_pc/Makefile
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2010-2011 Freescale Semiconductor, Inc.
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y	+= spl_minimal.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o
+endif
+obj-y	+= p1_p2_rdb_pc.o
+obj-y	+= ddr.o
+endif
+
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/roms/u-boot/board/freescale/p1_p2_rdb_pc/README b/roms/u-boot/board/freescale/p1_p2_rdb_pc/README
new file mode 100644
index 000000000..86ff04e69
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1_p2_rdb_pc/README
@@ -0,0 +1,64 @@
+Overview
+--------
+P1_P2_RDB_PC represents a set of boards including
+    P1020MSBG-PC
+    P1020RDB-PC
+    P1020RDB-PD
+    P1021RDB-PC
+    P1024RDB
+    P2020RDB-PC
+
+They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
+has 64-bit DDR. All others have 32-bit DDR.
+
+Key features on these boards include:
+    * DDR3
+    * NOR flash
+    * NAND flash (on RDB's only)
+    * SPI flash (on RDB's only)
+    * SDHC/MMC card slot
+    * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
+    * PCIE slot and mini-PCIE slots
+
+As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
+is used to store SPD data. In case of absent or corrupted SPD, falling back
+to timing data embedded in the source code will be used. Raw timing data is
+extracted from DDR chip datasheet. Different speeds of DDR are supported with
+this approach. ODT option is forced to fit this set of boards, again because
+they don't have regular DIMMs.
+
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification
+for writing timing.
+
+VSC firmware Address is defined by default in config file for eTSEC1.
+
+SD width is based off DIP switch. DIP switch is detected on the
+board by reading i2c bus and setting the appropriate mux values.
+
+Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have
+pins multiplexing. QE function needs to be disabled to access Nor Flash and
+CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
+in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
+enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below
+
+'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
+'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for p1020rdb and p2020rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl.bin' for other boot.
diff --git a/roms/u-boot/board/freescale/p1_p2_rdb_pc/ddr.c b/roms/u-boot/board/freescale/p1_p2_rdb_pc/ddr.c
new file mode 100644
index 000000000..be803ddf9
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+#if	defined(CONFIG_P1020RDB_PROTO)
+/* Micron MT41J256M8_187E */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 1870,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 37500,
+};
+#elif defined(CONFIG_TARGET_P2020RDB)
+/* Micron MT41J128M16_15E */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.primary_sdram_width = 64,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 14,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 1500,
+	.caslat_x = 0x7e << 4,	/* 5,6,7,8,9,10 */
+	.taa_ps = 13500,
+	.twr_ps = 15000,
+	.trcd_ps = 13500,
+	.trrd_ps = 6000,
+	.trp_ps = 13500,
+	.tras_ps = 36000,
+	.trc_ps = 49500,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 30000,
+};
+#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
+/* Micron MT41J512M8_187E */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 2,
+	.rank_density = 1073741824u,
+	.capacity = 2147483648u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 1870,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 37500,
+};
+#elif defined(CONFIG_TARGET_P1020RDB_PC)
+/*
+ * Samsung K4B2G0846C-HCF8
+ * The following timing are for "downshift"
+ * i.e. to use CL9 part as CL7
+ * otherwise, tAA, tRCD, tRP will be 13500ps
+ * and tRC will be 49500ps
+ */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 1875,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 37500,
+};
+#elif	defined(CONFIG_TARGET_P1024RDB)
+/*
+ * Samsung K4B2G0846C-HCH9
+ * The following timing are for "downshift"
+ * i.e. to use CL9 part as CL7
+ * otherwise, tAA, tRCD, tRP will be 13500ps
+ * and tRC will be 49500ps
+ */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 1500,
+	.caslat_x = 0x3e << 4,	/* 5,6,7,8,9 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 6000,
+	.trp_ps = 13125,
+	.tras_ps = 36000,
+	.trc_ps = 49125,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 30000,
+};
+#else
+#error Missing raw timing data for this board
+#endif
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR on board";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
+
+#ifdef CONFIG_SYS_DDR_CS0_BNDS
+/* Fixed sdram init -- doesn't use serial presence detect. */
+phys_size_t fixed_sdram(void)
+{
+	sys_info_t sysinfo;
+	char buf[32];
+	size_t ddr_size;
+	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
+		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+#endif
+		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
+		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
+		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
+		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
+		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
+		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
+		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+		.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
+		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
+		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+	};
+
+	get_sys_info(&sysinfo);
+	printf("Configuring DDR for %s MT/s data rate\n",
+			strmhz(buf, sysinfo.freq_ddrbus));
+
+	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
+		printf("ERROR setting Local Access Windows for DDR\n");
+		return 0;
+	};
+
+	return ddr_size;
+}
+#endif
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	int i;
+	popts->clk_adjust = 6;
+	popts->cpo_override = 0x1f;
+	popts->write_data_delay = 2;
+	popts->half_strength_driver_enable = 1;
+	/* Write leveling override */
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x8;
+	popts->trwt_override = 1;
+	popts->trwt = 0;
+
+	if (pdimm->primary_sdram_width == 64)
+		popts->data_bus_width = 0;
+	else if (pdimm->primary_sdram_width == 32)
+		popts->data_bus_width = 1;
+	else
+		printf("Error in DDR bus width configuration!\n");
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+	}
+}
diff --git a/roms/u-boot/board/freescale/p1_p2_rdb_pc/law.c b/roms/u-boot/board/freescale/p1_p2_rdb_pc/law.c
new file mode 100644
index 000000000..5f4d713ca
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1_p2_rdb_pc/law.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_VSC7385_ENET
+	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/roms/u-boot/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
new file mode 100644
index 000000000..8273384f2
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <hang.h>
+#include <hwconfig.h>
+#include <image.h>
+#include <init.h>
+#include <net.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_lbc.h>
+#include <asm/mp.h>
+#include <miiphy.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <vsc7385.h>
+#include <ioports.h>
+#include <asm/fsl_serdes.h>
+#include <netdev.h>
+
+#ifdef CONFIG_QE
+
+#define GPIO_GETH_SW_PORT	1
+#define GPIO_GETH_SW_PIN	29
+#define GPIO_GETH_SW_DATA	(1 << (31 - GPIO_GETH_SW_PIN))
+
+#define GPIO_SLIC_PORT		1
+#define GPIO_SLIC_PIN		30
+#define GPIO_SLIC_DATA		(1 << (31 - GPIO_SLIC_PIN))
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* GPIO */
+	{1,   1, 2, 0, 0}, /* GPIO7/PB1   - LOAD_DEFAULT_N */
+	{0,  15, 1, 0, 0}, /* GPIO11/A15  - WDI */
+	{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0},	/* RST_GETH_SW_N */
+	{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0},	/* RST_SLIC_N */
+	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
+struct cpld_data {
+	u8 cpld_rev_major;
+	u8 pcba_rev;
+	u8 wd_cfg;
+	u8 rst_bps_sw;
+	u8 load_default_n;
+	u8 rst_bps_wd;
+	u8 bypass_enable;
+	u8 bps_led;
+	u8 status_led;                  /* offset: 0x8 */
+	u8 fxo_led;                     /* offset: 0x9 */
+	u8 fxs_led;                     /* offset: 0xa */
+	u8 rev4[2];
+	u8 system_rst;                  /* offset: 0xd */
+	u8 bps_out;
+	u8 rev5[3];
+	u8 cpld_rev_minor;
+};
+
+#define CPLD_WD_CFG	0x03
+#define CPLD_RST_BSW	0x00
+#define CPLD_RST_BWD	0x00
+#define CPLD_BYPASS_EN	0x03
+#define CPLD_STATUS_LED	0x01
+#define CPLD_FXO_LED	0x01
+#define CPLD_FXS_LED	0x0F
+#define CPLD_SYS_RST	0x00
+
+void board_cpld_init(void)
+{
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
+	out_8(&cpld_data->status_led, CPLD_STATUS_LED);
+	out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
+	out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
+	out_8(&cpld_data->system_rst, CPLD_SYS_RST);
+}
+
+void board_gpio_init(void)
+{
+#ifdef CONFIG_QE
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
+
+	/* Enable VSC7385 switch */
+	setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
+
+	/* Enable SLIC */
+	setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
+#else
+
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+
+	/*
+	 * GPIO10 DDR Reset, open drain
+	 * GPIO7  LOAD_DEFAULT_N          Input
+	 * GPIO11  WDI (watchdog input)
+	 * GPIO12  Ethernet Switch Reset
+	 * GPIO13  SLIC Reset
+	 */
+
+	setbits_be32(&pgpio->gpdir, 0x02130000);
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
+	/* init DDR3 reset signal */
+	setbits_be32(&pgpio->gpdir, 0x00200000);
+	setbits_be32(&pgpio->gpodr, 0x00200000);
+	clrbits_be32(&pgpio->gpdat, 0x00200000);
+	udelay(1000);
+	setbits_be32(&pgpio->gpdat, 0x00200000);
+	udelay(1000);
+	clrbits_be32(&pgpio->gpdir, 0x00200000);
+#endif
+
+#ifdef CONFIG_VSC7385_ENET
+	/* reset VSC7385 Switch */
+	setbits_be32(&pgpio->gpdir, 0x00080000);
+	setbits_be32(&pgpio->gpdat, 0x00080000);
+#endif
+
+#ifdef CONFIG_SLIC
+	/* reset SLIC */
+	setbits_be32(&pgpio->gpdir, 0x00040000);
+	setbits_be32(&pgpio->gpdat, 0x00040000);
+#endif
+#endif
+}
+
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	setbits_be32(&gur->pmuxcr,
+			(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+	clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
+
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
+
+	board_gpio_init();
+	board_cpld_init();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u8 in, out, io_config, val;
+	int bus_num = CONFIG_SYS_SPD_BUS_NUM;
+
+	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
+		in_8(&cpld_data->cpld_rev_major) & 0x0F,
+		in_8(&cpld_data->cpld_rev_minor) & 0x0F,
+		in_8(&cpld_data->pcba_rev) & 0x0F);
+
+	/* Initialize i2c early for rom_loc and flash bank information */
+	#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return -ENXIO;
+	}
+
+	if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
+	    dm_i2c_read(dev, 1, &out, 1) < 0 ||
+	    dm_i2c_read(dev, 3, &io_config, 1) < 0) {
+		printf("Error reading i2c boot information!\n");
+		return 0; /* Don't want to hang() on this error */
+	}
+	#else /* Non DM I2C support - will be removed */
+	i2c_set_bus_num(bus_num);
+
+	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
+	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
+	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
+		printf("Error reading i2c boot information!\n");
+		return 0; /* Don't want to hang() on this error */
+	}
+	#endif
+
+	val = (in & io_config) | (out & (~io_config));
+
+	puts("rom_loc: ");
+	if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
+		puts("sd");
+#ifdef __SW_BOOT_SPI
+	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
+		puts("spi");
+#endif
+#ifdef __SW_BOOT_NAND
+	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
+		puts("nand");
+#endif
+#ifdef __SW_BOOT_PCIE
+	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
+		puts("pcie");
+#endif
+	} else {
+		if (val & 0x2)
+			puts("nor lower bank");
+		else
+			puts("nor upper bank");
+	}
+	puts("\n");
+
+	if (val & 0x1) {
+		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+		puts("SD/MMC : 8-bit Mode\n");
+		puts("eSPI : Disabled\n");
+	} else {
+		puts("SD/MMC : 4-bit Mode\n");
+		puts("eSPI : Enabled\n");
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+#ifdef CONFIG_VSC7385_ENET
+	unsigned int vscfw_addr;
+	char *tmp;
+#endif
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 2;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash */
+		disable_tlb(flash_esel);
+	}
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
+		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+#ifdef CONFIG_VSC7385_ENET
+	/* If a VSC7385 microcode image is present, then upload it. */
+	tmp = env_get("vscfw_addr");
+	if (tmp) {
+		vscfw_addr = simple_strtoul(tmp, NULL, 16);
+		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+		if (vsc7385_upload_firmware((void *)vscfw_addr,
+					    CONFIG_VSC7385_IMAGE_SIZE))
+			puts("Failure uploading VSC7385 microcode.\n");
+	} else {
+		puts("No address specified for VSC7385 microcode.\n");
+	}
+#endif
+	return 0;
+}
+
+#ifndef CONFIG_DM_ETH
+int board_eth_init(struct bd_info *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	ccsr_gur_t *gur __attribute__((unused)) =
+		(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (is_serdes_configured(SGMII_TSEC2)) {
+		printf("eTSEC2 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
+	mdio_info.name = DEFAULT_MII_NAME;
+
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+
+#if defined(CONFIG_UEC_ETH)
+	/*  QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
+
+	uec_standard_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
+	const char *soc_usb_compat = "fsl-usb2-dr";
+	int usb_err, usb1_off, usb2_off;
+#endif
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+	int err;
+#endif
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#if !defined(CONFIG_DM_PCI)
+	FT_FSL_PCI_SETUP;
+#endif
+
+#ifdef CONFIG_QE
+	do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
+			sizeof("okay"), 0);
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+	fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+	/* Delete eLBC node as it is muxed with USB2 controller */
+	if (hwconfig("usb2")) {
+		const char *soc_elbc_compat = "fsl,p1020-elbc";
+		int off = fdt_node_offset_by_compatible(blob, -1,
+				soc_elbc_compat);
+		if (off < 0) {
+			printf("WARNING: could not find compatible node %s\n",
+			       soc_elbc_compat);
+			return off;
+		}
+		err = fdt_del_node(blob, off);
+		if (err < 0) {
+			printf("WARNING: could not remove %s\n",
+			       soc_elbc_compat);
+			return err;
+		}
+		return 0;
+	}
+#endif
+
+#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
+/* Delete USB2 node as it is muxed with eLBC */
+	usb1_off = fdt_node_offset_by_compatible(blob, -1,
+		soc_usb_compat);
+	if (usb1_off < 0) {
+		printf("WARNING: could not find compatible node %s\n",
+		       soc_usb_compat);
+		return usb1_off;
+	}
+	usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
+			soc_usb_compat);
+	if (usb2_off < 0) {
+		printf("WARNING: could not find compatible node %s\n",
+		       soc_usb_compat);
+		return usb2_off;
+	}
+	usb_err = fdt_del_node(blob, usb2_off);
+	if (usb_err < 0) {
+		printf("WARNING: could not remove %s\n", soc_usb_compat);
+		return usb_err;
+	}
+#endif
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/p1_p2_rdb_pc/spl.c b/roms/u-boot/board/freescale/p1_p2_rdb_pc/spl.c
new file mode 100644
index 000000000..010f4639e
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1_p2_rdb_pc/spl.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <console.h>
+#include <env.h>
+#include <env_internal.h>
+#include <init.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include <asm/global_data.h>
+#include "../common/spl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, bus_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+	setbits_be32(&gur->pmuxcr,
+		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+	/* Read back the register to synchronize the write. */
+	in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	gd->bus_clk = bus_clk;
+
+	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+		     bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
+#endif
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	struct bd_info *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(struct bd_info));
+	gd->bd = bd;
+
+	arch_cpu_init();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+
+#ifndef CONFIG_SPL_NAND_BOOT
+	env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)SPL_ENV_ADDR);
+	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
+	gd->env_valid = ENV_VALID;
+#else
+	env_relocate();
+#endif
+
+#ifdef CONFIG_SYS_I2C
+	i2c_init_all();
+#else
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	dram_init();
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("Tertiary program loader running in sram...");
+#else
+	puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	fsl_spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/roms/u-boot/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/roms/u-boot/board/freescale/p1_p2_rdb_pc/spl_minimal.c
new file mode 100644
index 000000000..eb3f2c83f
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	puts("\nSecond program loader running in sram...");
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r');
+
+	ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
diff --git a/roms/u-boot/board/freescale/p1_p2_rdb_pc/tlb.c b/roms/u-boot/board/freescale/p1_p2_rdb_pc/tlb.c
new file mode 100644
index 000000000..fcd7a5519
--- /dev/null
+++ b/roms/u-boot/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+			0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+			0, 2, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_PCI
+	/* *I*G* - PCI memory 1.5G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O effective: 192K  */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#ifdef CONFIG_VSC7385_ENET
+	/* *I*G - VSC7385 Switch */
+	SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_1M, 1),
+#endif
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 6, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 10, BOOKE_PAGESZ_64K, 1),
+#endif /* not SPL */
+
+#ifdef CONFIG_SYS_NAND_BASE
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 7, BOOKE_PAGESZ_1M, 1),
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+	/* *I*G - eSDHC/eSPI/NAND boot */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+			0, 8, BOOKE_PAGESZ_1G, 1),
+
+#if defined(CONFIG_TARGET_P1020RDB_PD)
+	/* 2G DDR on P1020MBG, map the second 1G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 9, BOOKE_PAGESZ_1G, 1),
+#endif
+#endif /* RAMBOOT/SPL */
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/freescale/p2041rdb/Kconfig b/roms/u-boot/board/freescale/p2041rdb/Kconfig
new file mode 100644
index 000000000..7e187dde7
--- /dev/null
+++ b/roms/u-boot/board/freescale/p2041rdb/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_P2041RDB
+
+config SYS_BOARD
+	default "p2041rdb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "P2041RDB"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/p2041rdb/MAINTAINERS b/roms/u-boot/board/freescale/p2041rdb/MAINTAINERS
new file mode 100644
index 000000000..2121243e1
--- /dev/null
+++ b/roms/u-boot/board/freescale/p2041rdb/MAINTAINERS
@@ -0,0 +1,11 @@
+P2041RDB BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	board/freescale/p2041rdb/
+F:	include/configs/P2041RDB.h
+F:	configs/P2041RDB_defconfig
+F:	configs/P2041RDB_NAND_defconfig
+F:	configs/P2041RDB_SDCARD_defconfig
+F:	configs/P2041RDB_SECURE_BOOT_defconfig
+F:	configs/P2041RDB_SPIFLASH_defconfig
+F:	configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/p2041rdb/Makefile b/roms/u-boot/board/freescale/p2041rdb/Makefile
new file mode 100644
index 000000000..ebd0982b5
--- /dev/null
+++ b/roms/u-boot/board/freescale/p2041rdb/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2011 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= p2041rdb.o
+obj-y	+= cpld.o
+obj-y	+= ddr.o
+obj-y	+= eth.o
diff --git a/roms/u-boot/board/freescale/p2041rdb/README b/roms/u-boot/board/freescale/p2041rdb/README
new file mode 100644
index 000000000..79f77e496
--- /dev/null
+++ b/roms/u-boot/board/freescale/p2041rdb/README
@@ -0,0 +1,141 @@
+Overview
+=========
+The P2041 Processor combines four Power Architecture processor cores
+with high-performance datapath acceleration architecture(DPAA), CoreNet
+fabric infrastructure, as well as network and peripheral bus interfaces
+required for networking, telecom/datacom, wireless infrastructure, and
+military/aerospace applications.
+
+P2041RDB board is a quad core platform supporting the P2041 processor
+of QorIQ DPAA series.
+
+Boot from NOR flash
+===================
+1. Build image
+	make P2041RDB_config
+	make all
+
+2. Program image
+	=> tftp 1000000 u-boot.bin
+	=> protect off all
+	=> erase eff40000 efffffff
+	=> cp.b 1000000 eff40000 c0000
+
+3. Program RCW
+	=> tftp 1000000 rcw.bin
+	=> protect off all
+	=> erase e8000000 e801ffff
+	=> cp.b 1000000 e8000000 50
+
+4. Program FMAN Firmware ucode
+	=> tftp 1000000 ucode.bin
+	=> protect off all
+	=> erase eff00000 eff3ffff
+	=> cp.b 1000000 eff00000 2000
+
+5. Change DIP-switch
+	SW1[1-5] = 10110
+	Note: 1 stands for 'on', 0 stands for 'off'
+
+Boot from SDCard
+===================
+1. Build image
+	make P2041RDB_SDCARD_config
+	make all
+
+2. Generate PBL imge
+   Use PE tool to produce a image used to be programed to
+   SDCard which contains RCW and U-Boot image.
+
+3. Program the PBL image to SDCard
+	=> tftp 1000000 pbl_sd.bin
+	=> mmcinfo
+	=> mmc write 1000000 8 672
+
+4. Program FMAN Firmware ucode
+	=> tftp 1000000 ucode.bin
+	=> mmc write 1000000 690 10
+
+5. Change DIP-switch
+	SW1[1-5] = 01100
+	Note: 1 stands for 'on', 0 stands for 'off'
+
+Boot from SPI flash
+===================
+1. Build image
+	make P2041RDB_SPIFLASH_config
+	make all
+
+2. Generate PBL imge
+   Use PE tool to produce a image used to be programed to
+   SPI flash which contains RCW and U-Boot image.
+
+3. Program the PBL image to SPI flash
+	=> tftp 1000000 pbl_spi.bin
+	=> spi probe 0
+	=> sf erase 0 100000
+	=> sf write 1000000 0 $filesize
+
+4. Program FMAN Firmware ucode
+	=> tftp 1000000 ucode.bin
+	=> sf erase 110000 10000
+	=> sf write 1000000 110000 $filesize
+
+5. Change DIP-switch
+	SW1[1-5] = 10100
+	Note: 1 stands for 'on', 0 stands for 'off'
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for p2041rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin'
+instead of u-boot.bin for all boot.
+
+CPLD command
+============
+The CPLD is used to control the power sequence and some serdes lane
+mux function.
+
+cpld reset			 - hard reset to default bank
+cpld reset altbank		 - reset to alternate bank
+cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
+		lane 6: 0 -> slot1 (Default)
+			1 -> SGMII
+		lane a: 0 -> slot2 (Default)
+			1 -> AURORA
+		lane c: 0 -> slot2 (Default)
+			1 -> SATA0
+		lane d: 0 -> slot2 (Default)
+			1 -> SATA1
+
+Using the Device Tree Source File
+=================================
+To create the DTB (Device Tree Binary) image file, use a command
+similar to this:
+	dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
+
+Or use the following command:
+	{linux-2.6}/make p2041rdb.dtb ARCH=powerpc
+
+then the dtb file will be generated under the following directory:
+	{linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
+
+Booting Linux
+=============
+Place a linux uImage in the TFTP disk area.
+	tftp 1000000 uImage
+	tftp 2000000 rootfs.ext2.gz.uboot
+	tftp 3000000 p2041rdb.dtb
+	bootm 1000000 2000000 3000000
diff --git a/roms/u-boot/board/freescale/p2041rdb/cpld.c b/roms/u-boot/board/freescale/p2041rdb/cpld.c
new file mode 100644
index 000000000..b042fe3bc
--- /dev/null
+++ b/roms/u-boot/board/freescale/p2041rdb/cpld.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * Copyright 2011 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CPLD_BASE - The virtual address of the base of the CPLD register map
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+
+static u8 __cpld_read(unsigned int reg)
+{
+	void *p = (void *)CPLD_BASE;
+
+	return in_8(p + reg);
+}
+u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
+
+static void __cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CPLD_BASE;
+
+	out_8(p + reg, value);
+}
+void cpld_write(unsigned int reg, u8 value)
+	__attribute__((weak, alias("__cpld_write")));
+
+/*
+ * Reset the board. This honors the por_cfg registers.
+ */
+void __cpld_reset(void)
+{
+	CPLD_WRITE(system_rst, 1);
+}
+void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void __cpld_set_altbank(void)
+{
+	u8 reg5 = CPLD_READ(sw_ctl_on);
+
+	CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
+	CPLD_WRITE(fbank_sel, 1);
+	CPLD_WRITE(system_rst, 1);
+}
+void cpld_set_altbank(void)
+	__attribute__((weak, alias("__cpld_set_altbank")));
+
+/**
+ * Set the boot bank to the default bank
+ */
+void __cpld_set_defbank(void)
+{
+	CPLD_WRITE(system_rst_default, 1);
+}
+void cpld_set_defbank(void)
+	__attribute__((weak, alias("__cpld_set_defbank")));
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+	printf("cpld_ver	= 0x%02x\n", CPLD_READ(cpld_ver));
+	printf("cpld_ver_sub	= 0x%02x\n", CPLD_READ(cpld_ver_sub));
+	printf("pcba_ver	= 0x%02x\n", CPLD_READ(pcba_ver));
+	printf("system_rst	= 0x%02x\n", CPLD_READ(system_rst));
+	printf("sw_ctl_on	= 0x%02x\n", CPLD_READ(sw_ctl_on));
+	printf("por_cfg		= 0x%02x\n", CPLD_READ(por_cfg));
+	printf("switch_strobe	= 0x%02x\n", CPLD_READ(switch_strobe));
+	printf("jtag_sel	= 0x%02x\n", CPLD_READ(jtag_sel));
+	printf("sdbank1_clk	= 0x%02x\n", CPLD_READ(sdbank1_clk));
+	printf("sdbank2_clk	= 0x%02x\n", CPLD_READ(sdbank2_clk));
+	printf("fbank_sel	= 0x%02x\n", CPLD_READ(fbank_sel));
+	printf("serdes_mux	= 0x%02x\n", CPLD_READ(serdes_mux));
+	printf("SW[2]		= 0x%02x\n", in_8(&CPLD_SW(2)));
+	putc('\n');
+}
+#endif
+
+int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int rc = 0;
+
+	if (argc <= 1)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		if (strcmp(argv[2], "altbank") == 0)
+			cpld_set_altbank();
+		else
+			cpld_set_defbank();
+	} else if (strcmp(argv[1], "lane_mux") == 0) {
+		u32 lane = simple_strtoul(argv[2], NULL, 16);
+		u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
+		u8 reg = CPLD_READ(serdes_mux);
+
+		switch (lane) {
+		case 0x6:
+			reg &= ~SERDES_MUX_LANE_6_MASK;
+			reg |= val << SERDES_MUX_LANE_6_SHIFT;
+			break;
+		case 0xa:
+			reg &= ~SERDES_MUX_LANE_A_MASK;
+			reg |= val << SERDES_MUX_LANE_A_SHIFT;
+			break;
+		case 0xc:
+			reg &= ~SERDES_MUX_LANE_C_MASK;
+			reg |= val << SERDES_MUX_LANE_C_SHIFT;
+			break;
+		case 0xd:
+			reg &= ~SERDES_MUX_LANE_D_MASK;
+			reg |= val << SERDES_MUX_LANE_D_SHIFT;
+			break;
+		default:
+			printf("Invalid value\n");
+			break;
+		}
+
+		CPLD_WRITE(serdes_mux, reg);
+#ifdef DEBUG
+	} else if (strcmp(argv[1], "dump") == 0) {
+		cpld_dump_regs();
+#endif
+	} else
+		rc = cmd_usage(cmdtp);
+
+	return rc;
+}
+
+U_BOOT_CMD(
+	cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
+	"Reset the board or pin mulexing selection using the CPLD sequencer",
+	"reset - hard reset to default bank\n"
+	"cpld_cmd reset altbank - reset to alternate bank\n"
+	"cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
+	"	lane 6: 0 -> slot1\n"
+	"		1 -> SGMII (Default)\n"
+	"	lane a: 0 -> slot2\n"
+	"		1 -> AURORA (Default)\n"
+	"	lane c: 0 -> slot2\n"
+	"		1 -> SATA0 (Default)\n"
+	"	lane d: 0 -> slot2\n"
+	"		1 -> SATA1 (Default)\n"
+#ifdef DEBUG
+	"cpld_cmd dump - display the CPLD registers\n"
+#endif
+	);
diff --git a/roms/u-boot/board/freescale/p2041rdb/cpld.h b/roms/u-boot/board/freescale/p2041rdb/cpld.h
new file mode 100644
index 000000000..8c90c1ccf
--- /dev/null
+++ b/roms/u-boot/board/freescale/p2041rdb/cpld.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/**
+ * Copyright 2011 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+typedef struct cpld_data {
+	u8 cpld_ver;		/* 0x0 - CPLD Major Revision Register */
+	u8 cpld_ver_sub;	/* 0x1 - CPLD Minor Revision Register */
+	u8 pcba_ver;		/* 0x2 - PCBA Revision Register */
+	u8 system_rst;		/* 0x3 - system reset register */
+	u8 res0;		/* 0x4 - not used */
+	u8 sw_ctl_on;		/* 0x5 - Switch Control Enable Register */
+	u8 por_cfg;		/* 0x6 - POR Control Register */
+	u8 switch_strobe;	/* 0x7 - Multiplexed pin Select Register */
+	u8 jtag_sel;		/* 0x8 - JTAG or AURORA Selection */
+	u8 sdbank1_clk;		/* 0x9 - SerDes Bank1 Reference clock */
+	u8 sdbank2_clk;		/* 0xa - SerDes Bank2 Reference clock */
+	u8 fbank_sel;		/* 0xb - Flash bank selection */
+	u8 serdes_mux;		/* 0xc - Multiplexed pin Select Register */
+	u8 sw[1];		/* 0xd - SW2 Status */
+	u8 system_rst_default;	/* 0xe - system reset to default register */
+	u8 sysclk_sw1;		/* 0xf - sysclk configuration register */
+} __attribute__ ((packed)) cpld_data_t;
+
+#define SERDES_MUX_LANE_6_MASK	0x2
+#define SERDES_MUX_LANE_6_SHIFT	1
+#define SERDES_MUX_LANE_A_MASK	0x1
+#define SERDES_MUX_LANE_A_SHIFT	0
+#define SERDES_MUX_LANE_C_MASK	0x4
+#define SERDES_MUX_LANE_C_SHIFT	2
+#define SERDES_MUX_LANE_D_MASK	0x8
+#define SERDES_MUX_LANE_D_SHIFT	3
+#define CPLD_SWITCH_BANK_ENABLE	0x40
+#define CPLD_SYSCLK_83		0x1	/* system clock 83.3MHz */
+#define CPLD_SYSCLK_100		0x2	/* system clock 100MHz */
+
+/* Pointer to the CPLD register set */
+#define cpld ((cpld_data_t *)CPLD_BASE)
+
+/* The CPLD SW register that corresponds to board switch X, where x >= 1 */
+#define CPLD_SW(x)		(cpld->sw[(x) - 2])
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg))
+#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value)
diff --git a/roms/u-boot/board/freescale/p2041rdb/ddr.c b/roms/u-boot/board/freescale/p2041rdb/ddr.c
new file mode 100644
index 000000000..910058cef
--- /dev/null
+++ b/roms/u-boot/board/freescale/p2041rdb/ddr.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2t;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ *
+ * ranges for parameters:
+ *  wr_data_delay = 0-6
+ *  clk adjust = 0-8
+ *  cpo 2-0x1E (30)
+ */
+static const struct board_specific_parameters dimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz|adjst| start | delay|
+	 */
+	{2,   750,    3,     5,   0xff,    2,  0},
+	{2,  1250,    4,     6,   0xff,    2,  0},
+	{2,  1350,    5,     7,   0xff,    2,  0},
+	{2,  1666,    5,     8,   0xff,    2,  0},
+	{}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num) {
+		printf("Wrong parameter for controller number %d", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = dimm0;
+
+	/*
+	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->cpo_override = pbsp->cpo;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->twot_en = pbsp->force_2t;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found "
+			"for data rate %lu MT/s!\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->cpo_override = pbsp_highest->cpo;
+		popts->write_data_delay = pbsp_highest->write_data_delay;
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->twot_en = pbsp_highest->force_2t;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+
+found:
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/* Write leveling override */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/* Rtt and Rtt_WR override */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 60 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
+}
+
+int dram_init(void)
+{
+	phys_size_t dram_size = 0;
+
+	puts("Initializing....");
+
+	if (fsl_use_spd()) {
+		puts("using SPD\n");
+		dram_size = fsl_ddr_sdram();
+	} else {
+		puts("no SPD and fixed parameters\n");
+		return -ENXIO;
+	}
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	debug("    DDR: ");
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/p2041rdb/eth.c b/roms/u-boot/board/freescale/p2041rdb/eth.c
new file mode 100644
index 000000000..23fd619ce
--- /dev/null
+++ b/roms/u-boot/board/freescale/p2041rdb/eth.c
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Author: Mingkai Hu <Mingkai.hu@freescale.com>
+ */
+
+/*
+ * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
+ * are provided by the three on-board PHY or by the standard Freescale
+ * four-port SGMII riser card. We need to change the phy-handle in the
+ * kernel dts file to point to the correct PHY according to serdes mux
+ * and serdes protocol selection.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fsl_dtsec.h>
+
+#include "cpld.h"
+#include "../common/fman.h"
+
+#ifdef CONFIG_FMAN_ENET
+/*
+ * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot
+ */
+static u8 lane_to_slot[] = {
+	0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
+};
+
+static int riser_phy_addr[] = {
+	CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
+	CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
+	CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
+	CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
+};
+
+/*
+ * Initialize the lane_to_slot[] array.
+ *
+ * On the P2040RDB board the mapping is controlled by CPLD register.
+ */
+static void initialize_lane_to_slot(void)
+{
+	u8 mux = CPLD_READ(serdes_mux);
+
+	lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1;
+	lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;
+	lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;
+	lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;
+}
+
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) An Fman port
+ *
+ * ... update the phy-handle property of the Ethernet node to point to the
+ * right PHY.  This assumes that we already know the PHY for each port.
+ *
+ * The offset of the Fman Ethernet node is also passed in for convenience, but
+ * it is not used, and we recalculate the offset anyway.
+ *
+ * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
+ * Inside the Fman, "ports" are things that connect to MACs.  We only call them
+ * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
+ * and ports are the same thing.
+ *
+ */
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+			      enum fm_port port, int offset)
+{
+	phy_interface_t intf = fm_info_get_enet_if(port);
+	char phy[16];
+	int lane;
+	u8 slot;
+
+	switch (intf) {
+	/* The RGMII PHY is identified by the MAC connected to it */
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+		sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
+		fdt_set_phy_handle(fdt, compat, addr, phy);
+		break;
+	/* The SGMII PHY is identified by the MAC connected to it */
+	case PHY_INTERFACE_MODE_SGMII:
+		lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
+		if (lane < 0)
+			return;
+		slot = lane_to_slot[lane];
+		if (slot) {
+			sprintf(phy, "phy_sgmii_%x",
+					CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+					+ (port - FM1_DTSEC1));
+			fdt_set_phy_handle(fdt, compat, addr, phy);
+		} else {
+			sprintf(phy, "phy_sgmii_%x",
+					CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
+					+ (port - FM1_DTSEC1));
+			fdt_set_phy_handle(fdt, compat, addr, phy);
+		}
+		break;
+	case PHY_INTERFACE_MODE_XGMII:
+		/* XAUI */
+		lane = serdes_get_first_lane(XAUI_FM1);
+		if (lane >= 0) {
+			/* The XAUI PHY is identified by the slot */
+			sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
+			fdt_set_phy_handle(fdt, compat, addr, phy);
+		}
+		break;
+	default:
+		break;
+	}
+}
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct fsl_pq_mdio_info dtsec_mdio_info;
+	struct tgec_mdio_info tgec_mdio_info;
+	unsigned int i, slot;
+	int lane;
+
+	printf("Initializing Fman\n");
+
+	initialize_lane_to_slot();
+
+	dtsec_mdio_info.regs =
+		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the real 10G MDIO bus */
+	fm_tgec_mdio_init(bis, &tgec_mdio_info);
+
+	/*
+	 * Program the three on-board SGMII PHY addresses. If the SGMII Riser
+	 * card used, we'll override the PHY address later. For any DTSEC that
+	 * is RGMII, we'll also override its PHY address later. We assume that
+	 * DTSEC4 and DTSEC5 are used for RGMII.
+	 */
+	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			if (slot)
+				fm_info_set_phy_address(i, riser_phy_addr[i]);
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
+			fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
+					CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
+					CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+			break;
+		default:
+			printf("Fman1: DTSEC%u set to unknown interface %i\n",
+			       idx + 1, fm_info_get_enet_if(i));
+			break;
+		}
+
+		fm_info_set_mdio(i,
+			miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+	}
+
+	lane = serdes_get_first_lane(XAUI_FM1);
+	if (lane >= 0) {
+		slot = lane_to_slot[lane];
+		if (slot)
+			fm_info_set_phy_address(FM1_10GEC1,
+					CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+	}
+
+	fm_info_set_mdio(FM1_10GEC1,
+			miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/freescale/p2041rdb/p2041rdb.c b/roms/u-boot/board/freescale/p2041rdb/p2041rdb.c
new file mode 100644
index 000000000..4ece1e6ea
--- /dev/null
+++ b/roms/u-boot/board/freescale/p2041rdb/p2041rdb.c
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2011,2012 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <image.h>
+#include <init.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+extern void pci_of_setup(void *blob, struct bd_info *bd);
+
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	u8 sw;
+	struct cpu_type *cpu = gd->arch.cpu;
+	unsigned int i;
+
+	printf("Board: %sRDB, ", cpu->name);
+	printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
+			CPLD_READ(cpld_ver_sub));
+
+	sw = CPLD_READ(fbank_sel);
+	printf("vBank: %d\n", sw & 0x1);
+
+	/*
+	 * Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES Reference Clocks: ");
+	sw = in_8(&CPLD_SW(2)) >> 2;
+	for (i = 0; i < 2; i++) {
+		static const char * const freq[][3] = {{"0", "100", "125"},
+						{"100", "156.25", "125"}
+		};
+		unsigned int clock = (sw >> (2 * i)) & 3;
+
+		printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
+	}
+	puts("\n");
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
+	setbits_be32(&gur->ddrclkdr, 0x000f000f);
+
+	return 0;
+}
+
+#define CPLD_LANE_A_SEL	0x1
+#define CPLD_LANE_G_SEL	0x2
+#define CPLD_LANE_C_SEL	0x4
+#define CPLD_LANE_D_SEL	0x8
+
+void board_config_lanes_mux(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+	u8 mux = 0;
+	switch (srds_prtcl) {
+	case 0x2:
+	case 0x5:
+	case 0x9:
+	case 0xa:
+	case 0xf:
+		break;
+	case 0x8:
+		mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+		break;
+	case 0x14:
+		mux |= CPLD_LANE_A_SEL;
+		break;
+	case 0x17:
+		mux |= CPLD_LANE_G_SEL;
+		break;
+	case 0x16:
+	case 0x19:
+	case 0x1a:
+		mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+		break;
+	case 0x1c:
+		mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
+		break;
+	default:
+		printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
+		break;
+	}
+	CPLD_WRITE(serdes_mux, mux);
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 2;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash + promjet */
+		disable_tlb(flash_esel);
+	}
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	board_config_lanes_mux();
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(unsigned long dummy)
+{
+	u8 sysclk_conf = CPLD_READ(sysclk_sw1);
+
+	switch (sysclk_conf & 0x7) {
+	case CPLD_SYSCLK_83:
+		return 83333333;
+	case CPLD_SYSCLK_100:
+		return 100000000;
+	default:
+		return 66666666;
+	}
+}
+
+#define NUM_SRDS_BANKS	2
+
+int misc_init_r(void)
+{
+	serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 actual[NUM_SRDS_BANKS];
+	unsigned int i;
+	u8 sw;
+	static const int freq[][3] = {
+		{0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
+		{SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
+			SRDS_PLLCR0_RFCK_SEL_125}
+	};
+
+	sw = in_8(&CPLD_SW(2)) >> 2;
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		unsigned int clock = (sw >> (2 * i)) & 3;
+		if (clock == 0x3) {
+			printf("Warning: SDREFCLK%u switch setting of '11' is "
+			       "unsupported\n", i + 1);
+			break;
+		}
+		if (i == 0 && clock == 0)
+			puts("Warning: SDREFCLK1 switch setting of"
+				"'00' is unsupported\n");
+		else
+			actual[i] = freq[i][clock];
+
+		/*
+		 * PC board uses a different CPLD with PB board, this CPLD
+		 * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
+		 * board has cpld_ver_sub = 0, and pcba_ver = 4.
+		 */
+		if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
+		    (CPLD_READ(pcba_ver) == 5)) {
+			/* PC board bank2 frequency */
+			actual[i] = freq[i-1][clock];
+		}
+	}
+
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		u32 expected = in_be32(&regs->bank[i].pllcr0);
+		expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (expected != actual[i]) {
+			printf("Warning: SERDES bank %u expects reference clock"
+			       " %sMHz, but actual is %sMHz\n", i + 1,
+			       serdes_clock_to_string(expected),
+			       serdes_clock_to_string(actual[i]));
+		}
+	}
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+	fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+#ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
+	fdt_fixup_fman_ethernet(blob);
+#endif
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/t102xrdb/Kconfig b/roms/u-boot/board/freescale/t102xrdb/Kconfig
new file mode 100644
index 000000000..6deeb248a
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_T1023RDB || TARGET_T1024RDB
+
+config SYS_BOARD
+	default "t102xrdb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "T102xRDB"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/t102xrdb/MAINTAINERS b/roms/u-boot/board/freescale/t102xrdb/MAINTAINERS
new file mode 100644
index 000000000..471ea07d3
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/MAINTAINERS
@@ -0,0 +1,14 @@
+T102XRDB BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	board/freescale/t102xrdb/
+F:	include/configs/T102xRDB.h
+F:	configs/T1024RDB_defconfig
+F:	configs/T1024RDB_NAND_defconfig
+F:	configs/T1024RDB_SDCARD_defconfig
+F:	configs/T1024RDB_SPIFLASH_defconfig
+F:	configs/T1024RDB_SECURE_BOOT_defconfig
+F:	configs/T1023RDB_defconfig
+F:	configs/T1023RDB_NAND_defconfig
+F:	configs/T1023RDB_SDCARD_defconfig
+F:	configs/T1023RDB_SPIFLASH_defconfig
diff --git a/roms/u-boot/board/freescale/t102xrdb/Makefile b/roms/u-boot/board/freescale/t102xrdb/Makefile
new file mode 100644
index 000000000..ddeb44f36
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o
+else
+obj-y   += t102xrdb.o
+obj-$(CONFIG_TARGET_T1024RDB)   += cpld.o
+obj-y   += eth_t102xrdb.o
+obj-$(CONFIG_PCI)       += pci.o
+endif
+obj-y   += ddr.o
+obj-y   += law.o
+obj-y   += tlb.o
diff --git a/roms/u-boot/board/freescale/t102xrdb/README b/roms/u-boot/board/freescale/t102xrdb/README
new file mode 100644
index 000000000..dde3f8ca3
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/README
@@ -0,0 +1,340 @@
+T1024 SoC Overview
+------------------
+The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
+combines two or one 64-bit Power Architecture e5500 core respectively with high
+performance datapath acceleration logic, and network peripheral bus interfaces
+required for networking and telecommunications. This processor can be used in
+applications such as enterprise WLAN access points, routers, switches, firewall
+and other packet processing intensive small enterprise and branch office appliances,
+and general-purpose embedded computing. Its high level of integration offers
+significant performance benefits and greatly helps to simplify board design.
+
+
+The T1024 SoC includes the following function and features:
+- two e5500 cores, each with a private 256 KB L2 cache
+  - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
+  - Three levels of instructions: User, supervisor, and hypervisor
+  - Independent boot and reset
+  - Secure boot capability
+- 256 KB shared L3 CoreNet platform cache (CPC)
+- Interconnect CoreNet platform
+  - CoreNet coherency manager supporting coherent and noncoherent transactions
+    with prioritization and bandwidth allocation amongst CoreNet endpoints
+  - 150 Gbps coherent read bandwidth
+- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
+- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
+  - Packet parsing, classification, and distribution
+  - Queue management for scheduling, packet sequencing, and congestion management
+  - Cryptography Acceleration (SEC 5.x)
+  - IEEE 1588 support
+  - Hardware buffer management for buffer allocation and deallocation
+  - MACSEC on DPAA-based Ethernet ports
+- Ethernet interfaces
+  - Four 1 Gbps Ethernet controllers
+- Parallel Ethernet interfaces
+  - Two RGMII interfaces
+- High speed peripheral interfaces
+  - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
+  - One SATA controller supporting 1.5 and 3.0 Gb/s operation
+  - One QSGMII interface
+  - Four SGMII interface supporting 1000 Mbps
+  - Three SGMII interfaces supporting up to 2500 Mbps
+  - 10GbE XFI or 10Base-KR interface
+- Additional peripheral interfaces
+  - Two USB 2.0 controllers with integrated PHY
+  - SD/eSDHC/eMMC
+  - eSPI controller
+  - Four I2C controllers
+  - Four UARTs
+  - Four GPIO controllers
+  - Integrated flash controller (IFC)
+  - LCD interface (DIU) with 12 bit dual data rate
+- Multicore programmable interrupt controller (PIC)
+- Two 8-channel DMA engines
+- Single source clocking implementation
+- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+- QUICC Engine block
+  - 32-bit RISC controller for flexible support of the communications peripherals
+  - Serial DMA channel for receive and transmit on all serial channels
+  - Two universal communication controllers, supporting TDM, HDLC, and UART
+
+T1023 Personality
+------------------
+T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
+unavailable deep sleep. Rest of the blocks are almost same as T1024.
+Differences between T1024 and T1023
+Feature		T1024  T1023
+QUICC Engine:	yes    no
+DIU:		yes    no
+Deep Sleep:	yes    no
+I2C controller: 4      3
+DDR:		64-bit 32-bit
+IFC:		32-bit 28-bit
+Package:	23x23  19x19
+
+
+T1024RDB board Overview
+-----------------------
+ - Ethernet
+     - Two on-board 10M/100M/1G bps RGMII ethernet ports
+     - One on-board 10G bps Base-T port.
+ - DDR Memory
+     - Supports 64-bit 4GB DDR3L DIMM
+ - PCIe
+     - One on-board PCIe slot.
+     - Two on-board PCIe Mini-PCIe connectors.
+ - IFC/Local Bus
+     - NOR:  128MB 16-bit NOR Flash
+     - NAND: 1GB 8-bit NAND flash
+     - CPLD: for system controlling with programable header on-board
+ - USB
+     - Supports two USB 2.0 ports with integrated PHYs
+     - Two type A ports with 5V@1.5A per port.
+ - SDHC
+     - one SD connector supporting 1.8V/3.3V via J53.
+ - SPI
+     -  On-board 64MB SPI flash
+ - Other
+     - Two Serial ports
+     - Four I2C ports
+
+
+T1023RDB board Overview
+-----------------------
+- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
+- CoreNet fabric supporting coherent and noncoherent transactions with
+  prioritization and bandwidth allocation
+- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
+- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
+- Ethernet interfaces:
+  - one 1G RGMII port on-board(RTL8211FS PHY)
+  - one 1G SGMII port on-board(RTL8211FS PHY)
+  - one 2.5G SGMII port on-board(AQR105 PHY)
+- PCIe: Two Mini-PCIe connectors on-board.
+- SerDes: 4 lanes up to 10.3125GHz
+- NOR:  128MB S29GL01GS110TFIV10 Spansion NOR Flash
+- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
+- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
+- USB: one Type-A USB 2.0 port with internal PHY
+- eSDHC: support SD/MMC and eMMC card
+- 256Kbit M24256 I2C EEPROM
+- RTC: Real-time clock DS1339U on I2C bus
+- UART: one serial port on-board with RJ45 connector
+- Debugging: JTAG/COP for T1023 debugging
+
+
+Memory map on T1024RDB
+----------------------
+Start Address  End Address      Description			Size
+0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - CPLD			4KB
+0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash		64KB
+0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR				16MB
+0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space		64KB
+0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space		64KB
+0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space		64KB
+0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
+0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
+0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash			128MB
+0xF_0000_0000  0xF_003F_FFFF    DCSR				4MB
+0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space		256MB
+0xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space		256MB
+0xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space		256MB
+0x0_0000_0000  0x0_ffff_ffff    DDR				4GB
+
+
+128MB NOR Flash Memory Layout
+-----------------------------
+Start Address   End Address     Definition			Max size
+0xEFF40000      0xEFFFFFFF      U-Boot (current bank)		768KB
+0xEFF20000      0xEFF3FFFF      U-Boot env (current bank)	128KB
+0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)	128KB
+0xEFE00000      0xEFE3FFFF      QE firmware (current bank)	256KB
+0xED300000      0xEFDFFFFF      rootfs (alt bank)		44MB
+0xED000000      0xED2FFFFF      Guest image #3 (alternate bank) 3MB
+0xECD00000      0xECFFFFFF      Guest image #2 (alternate bank) 3MB
+0xECA00000	0xECCFFFFF	Guest image #1 (alternate bank) 3MB
+0xEC900000	0xEC9FFFFF	HV config device tree(alt bank)	1MB
+0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank) 1MB
+0xEC700000	0xEC7FFFFF	HV.uImage (alternate bank)	1MB
+0xEC020000      0xEC6FFFFF      Linux.uImage (alt bank)		~7MB
+0xEC000000      0xEC01FFFF      RCW (alt bank)			128KB
+0xEBF40000      0xEBFFFFFF      U-Boot (alt bank)		768KB
+0xEBF20000      0xEBF3FFFF      U-Boot env (alt bank)		128KB
+0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)		128KB
+0xEBE00000      0xEBE3FFFF      QE firmware (alt bank)		256KB
+0xE9300000      0xEBDFFFFF      rootfs (current bank)		44MB
+0xE9000000      0xE92FFFFF      Guest image #3 (current bank)   3MB
+0xE8D00000      0xE8FFFFFF      Guest image #2 (current bank)   3MB
+0xE8A00000	0xE8CFFFFF	Guest image #1 (current bank)	3MB
+0xE8900000	0xE89FFFFF	HV config device tree(cur bank) 1MB
+0xE8800000      0xE88FFFFF      Hardware device tree (cur bank) 1MB
+0xE8700000	0xE87FFFFF	HV.uImage (current bank)	1MB
+0xE8020000      0xE86FFFFF      Linux.uImage (current bank)	~7MB
+0xE8000000      0xE801FFFF      RCW (current bank)		128KB
+
+
+T1024/T1023 Clock frequency
+---------------------------
+BIN   Core     DDR       Platform  FMan
+Bin1: 1400MHz  1600MT/s  400MHz    700MHz
+Bin2: 1200MHz  1600MT/s  400MHz    600MHz
+Bin3: 1000MHz  1600MT/s  400MHz    500MHz
+
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+   a. build NOR boot image
+	$  make T1024RDB_defconfig
+	$  make
+   b. program u-boot.bin image to NOR flash
+	=> tftp 1000000 u-boot.bin
+	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+	on T1024RDB:
+	   set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+	on T1023RDB:
+	   set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
+
+   Switching between default bank0 and alternate bank4 on NOR flash
+   To change boot source to vbank4:
+   on T1024RDB:
+	via software:   run command 'cpld reset altbank' in U-Boot.
+	via DIP-switch: set SW3[5:7] = '100'
+   on T1023RDB:
+	via software:   run command 'switch bank4' in U-Boot.
+	via DIP-switch: set SW3[5:7] = '100'
+
+   To change boot source to vbank0:
+   on T1024RDB:
+	via software:   run command 'cpld reset' in U-Boot.
+	via DIP-Switch: set SW3[5:7] = '000'
+   on T1023RDB:
+	via software:   run command 'switch bank0' in U-Boot.
+	via DIP-switch: set SW3[5:7] = '000'
+
+2. NAND Boot:
+   a. build PBL image for NAND boot
+	$ make T1024RDB_NAND_defconfig
+	$ make
+   b. program u-boot-with-spl-pbl.bin to NAND flash
+	=> tftp 1000000 u-boot-with-spl-pbl.bin
+	=> nand erase 0 $filesize
+	=> nand write 1000000 0 $filesize
+	set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
+
+3. SPI Boot:
+   a. build PBL image for SPI boot
+	$ make T1024RDB_SPIFLASH_defconfig
+	$ make
+   b. program u-boot-with-spl-pbl.bin to SPI flash
+	=> tftp 1000000 u-boot-with-spl-pbl.bin
+	=> sf probe 0
+	=> sf erase 0 100000
+	=> sf write 1000000 0 $filesize
+	=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
+	=> sf erase 100000 100000
+	=> sf write 1000000 110000 20000
+	set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+   a. build PBL image for SD boot
+	$ make T1024RDB_SDCARD_defconfig
+	$ make
+   b. program u-boot-with-spl-pbl.bin to SD/MMC card
+	=> tftp 1000000 u-boot-with-spl-pbl.bin
+	=> mmc write 1000000 8 0x7f0
+	=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
+	=> mmc write 1000000 0x820 80
+	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+   SW3[3] = '1' for SD card(or 'switch sd' by software)
+   SW3[3] = '0' for eMMC (or 'switch emmc' by software)
+
+
+device tree support and how to enable it for different configs
+--------------------------------------------------------------
+device tree support is available for t1024rdb for below mentioned boot,
+1. nor boot
+2. nand boot
+3. sd boot
+4. spiflash boot
+
+to enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. config_default_device_tree="t1024rdb" (change default device tree name if required)
+2. config_of_control
+3. config_mpc85xx_have_reset_vector if reset vector is located at
+   config_reset_vector_address - 0xffc
+
+if device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for nor boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to U-Boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area		   | Address			|
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB)		|
+-------------------------------------------------
+|GD, BD		   | 0xFFFC8000 (4KB)		|
+-------------------------------------------------
+|ENV		   | 0xFFFC9000 (8KB)		|
+-------------------------------------------------
+|HEAP		   | 0xFFFCB000 (30KB)		|
+-------------------------------------------------
+|STACK		   | 0xFFFD8000 (22KB)		|
+-------------------------------------------------
+|U-Boot SPL	   | 0xFFFD8000 (160KB)		|
+-------------------------------------------------
+
+NAND Flash memory Map on T1024RDB
+-------------------------------------------------------------
+Start		End		Definition	Size
+0x000000	0x0FFFFF	U-Boot		1MB(2 block)
+0x100000	0x17FFFF	U-Boot env	512KB(1 block)
+0x180000	0x1FFFFF	FMAN Ucode	512KB(1 block)
+0x200000	0x27FFFF	QE Firmware	512KB(1 block)
+
+
+NAND Flash memory Map on T1023RDB
+----------------------------------------------------
+Start		End		Definition	Size
+0x000000	0x0FFFFF	U-Boot		1MB
+0x100000	0x15FFFF	U-Boot env	8KB
+0x160000	0x17FFFF	FMAN Ucode	128KB
+
+
+SD Card memory Map on T102xRDB
+----------------------------------------------------
+Block		#blocks		Definition	Size
+0x008		2048		U-Boot img	1MB
+0x800		0016		U-Boot env	8KB
+0x820		0256		FMAN Ucode	128KB
+0x920		0256		QE Firmware	128KB(only T1024RDB)
+
+
+64MB SPI Flash memory Map on T102xRDB
+----------------------------------------------------
+Start		End		Definition	Size
+0x000000	0x0FFFFF	U-Boot img	1MB
+0x100000	0x101FFF	U-Boot env	8KB
+0x110000	0x12FFFF	FMAN Ucode	128KB
+0x130000	0x14FFFF	QE Firmware	128KB(only T1024RDB)
+0x300000	0x3FFFFF	device tree	128KB
+0x400000	0x9FFFFF	Linux kernel    6MB
+0xa00000	0x3FFFFFF	rootfs		54MB
+
+
+For more details, please refer to T1024RDB/T1023RDB User Guide
+and Freescale QorIQ SDK Infocenter document.
diff --git a/roms/u-boot/board/freescale/t102xrdb/cpld.c b/roms/u-boot/board/freescale/t102xrdb/cpld.c
new file mode 100644
index 000000000..47c3b1627
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/cpld.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * Freescale T1024RDB board-specific CPLD controlling supports.
+ *
+ * The following macros need to be defined:
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	out_8(p + reg, value);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(void)
+{
+	u8 reg = CPLD_READ(flash_csr);
+
+	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+
+	CPLD_WRITE(flash_csr, reg);
+	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+	u8 reg = CPLD_READ(flash_csr);
+
+	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+
+	CPLD_WRITE(flash_csr, reg);
+	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+static void cpld_dump_regs(void)
+{
+	printf("cpld_ver	 = 0x%02x\n", CPLD_READ(cpld_ver));
+	printf("cpld_ver_sub	 = 0x%02x\n", CPLD_READ(cpld_ver_sub));
+	printf("hw_ver		 = 0x%02x\n", CPLD_READ(hw_ver));
+	printf("sw_ver		 = 0x%02x\n", CPLD_READ(sw_ver));
+	printf("reset_ctl1	 = 0x%02x\n", CPLD_READ(reset_ctl1));
+	printf("reset_ctl2	 = 0x%02x\n", CPLD_READ(reset_ctl2));
+	printf("int_status	 = 0x%02x\n", CPLD_READ(int_status));
+	printf("flash_csr	 = 0x%02x\n", CPLD_READ(flash_csr));
+	printf("fan_ctl_status	 = 0x%02x\n", CPLD_READ(fan_ctl_status));
+	printf("led_ctl_status	 = 0x%02x\n", CPLD_READ(led_ctl_status));
+	printf("sfp_ctl_status	 = 0x%02x\n", CPLD_READ(sfp_ctl_status));
+	printf("misc_ctl_status	 = 0x%02x\n", CPLD_READ(misc_ctl_status));
+	printf("boot_override	 = 0x%02x\n", CPLD_READ(boot_override));
+	printf("boot_config1	 = 0x%02x\n", CPLD_READ(boot_config1));
+	printf("boot_config2	 = 0x%02x\n", CPLD_READ(boot_config2));
+	putc('\n');
+}
+
+int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int rc = 0;
+
+	if (argc <= 1)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		if (strcmp(argv[2], "altbank") == 0)
+			cpld_set_altbank();
+		else
+			cpld_set_defbank();
+	} else if (strcmp(argv[1], "dump") == 0) {
+		cpld_dump_regs();
+	} else {
+		rc = cmd_usage(cmdtp);
+	}
+
+	return rc;
+}
+
+U_BOOT_CMD(
+	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+	"Reset the board or alternate bank",
+	"reset - hard reset to default bank\n"
+	"cpld reset altbank - reset to alternate bank\n"
+	"cpld dump - display the CPLD registers\n"
+	);
diff --git a/roms/u-boot/board/freescale/t102xrdb/cpld.h b/roms/u-boot/board/freescale/t102xrdb/cpld.h
new file mode 100644
index 000000000..c05f53680
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/cpld.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ */
+
+struct cpld_data {
+	u8 cpld_ver;		/* 0x00 - CPLD Major Revision Register */
+	u8 cpld_ver_sub;	/* 0x01 - CPLD Minor Revision Register */
+	u8 hw_ver;		/* 0x02 - Hardware Revision Register */
+	u8 sw_ver;		/* 0x03 - Software Revision register */
+	u8 res0[12];		/* 0x04 - 0x0F - not used */
+	u8 reset_ctl1;		/* 0x10 - Reset control Register1 */
+	u8 reset_ctl2;		/* 0x11 - Reset control Register2 */
+	u8 int_status;		/* 0x12 - Interrupt status Register */
+	u8 flash_csr;		/* 0x13 - Flash control and status register */
+	u8 fan_ctl_status;	/* 0x14 - Fan control and status register  */
+	u8 led_ctl_status;	/* 0x15 - LED control and status register */
+	u8 sfp_ctl_status;	/* 0x16 - SFP control and status register  */
+	u8 misc_ctl_status;	/* 0x17 - Miscellanies ctrl & status register*/
+	u8 boot_override;	/* 0x18 - Boot override register */
+	u8 boot_config1;	/* 0x19 - Boot config override register*/
+	u8 boot_config2;	/* 0x1A - Boot config override register*/
+} cpld_data_t;
+
+
+/* Pointer to the CPLD register set */
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)\
+		cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_LBMAP_MASK	 0x3F
+#define CPLD_BANK_SEL_MASK      0x07
+#define CPLD_BANK_OVERRIDE      0x40
+#define CPLD_LBMAP_ALTBANK      0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK     0x40 /* BANK OR | BANK 0 */
+#define CPLD_LBMAP_RESET	0xFF
+#define CPLD_LBMAP_SHIFT	0x03
+#define CPLD_BOOT_SEL	   0x80
+
+#define CPLD_PCIE_SGMII_MUX	0x80
+#define CPLD_OVERRIDE_BOOT_EN	0x01
+#define CPLD_OVERRIDE_MUX_EN	0x02 /* PCIE/2.5G-SGMII mux override enable */
diff --git a/roms/u-boot/board/freescale/t102xrdb/ddr.c b/roms/u-boot/board/freescale/t102xrdb/ddr.c
new file mode 100644
index 000000000..818c20cf1
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/ddr.c
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * datarate_mhz_high values need to be in ascending order
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 */
+	{2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+	{1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+	struct cpu_type *cpu = gd->arch.cpu;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust according to the board ddr freqency and n_banks
+	 * specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found\n");
+		printf("for data rate %lu MT/s\n", ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+	debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
+	      pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
+	debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * rtt and rtt_wr override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
+
+	/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
+	 * force DDR bus width to 32bit for T1023
+	 */
+	if (cpu->soc_ver == SVR_T1023)
+		popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
+
+#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
+	/* for DDR bus 32bit test on T1024 */
+	popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
+#endif
+
+#ifdef CONFIG_TARGET_T1023RDB
+	popts->wrlvl_ctl_2 = 0x07070606;
+	popts->half_strength_driver_enable = 1;
+	popts->cpo_sample = 0x43;
+#elif defined(CONFIG_TARGET_T1024RDB)
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x52;
+#endif
+}
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 0x80000000,
+	.capacity = 0x80000000,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.bank_addr_bits = 2,
+	.bank_group_bits = 2,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+	.tckmin_x_ps = 938,
+	.tckmax_ps = 1500,
+	.caslat_x = 0x000DFA00,
+	.taa_ps = 13500,
+	.trcd_ps = 13500,
+	.trp_ps = 13500,
+	.tras_ps = 33000,
+	.trc_ps = 46500,
+	.trfc1_ps = 260000,
+	.trfc2_ps = 160000,
+	.trfc4_ps = 110000,
+	.tfaw_ps = 25000,
+	.trrds_ps = 3700,
+	.trrdl_ps = 5300,
+	.tccdl_ps = 5355,
+	.refresh_rate_ps = 7800000,
+	.dq_mapping[0] = 0x0,
+	.dq_mapping[1] = 0x0,
+	.dq_mapping[2] = 0x0,
+	.dq_mapping[3] = 0x0,
+	.dq_mapping[4] = 0x0,
+	.dq_mapping[5] = 0x0,
+	.dq_mapping[6] = 0x0,
+	.dq_mapping[7] = 0x0,
+	.dq_mapping[8] = 0x0,
+	.dq_mapping[9] = 0x0,
+	.dq_mapping[10] = 0x0,
+	.dq_mapping[11] = 0x0,
+	.dq_mapping[12] = 0x0,
+	.dq_mapping[13] = 0x0,
+	.dq_mapping[14] = 0x0,
+	.dq_mapping[15] = 0x0,
+	.dq_mapping[16] = 0x0,
+	.dq_mapping[17] = 0x0,
+	.dq_mapping_ors = 1,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR4 on board";
+
+	if (((controller_number == 0) && (dimm_number == 0)) ||
+	    ((controller_number == 1) && (dimm_number == 0))) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+	void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+	/* does not provide HW signals for power management */
+	clrbits_8(cpld_base + 0x17, 0x40);
+	/* Disable MCKE isolation */
+	gpio_set_value(2, 0);
+	udelay(1);
+}
+#endif
+
+int dram_init(void)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
+	puts("Initializing....using SPD\n");
+#endif
+	dram_size = fsl_ddr_sdram();
+#else
+	/* DDR has been initialised by first stage boot loader */
+	dram_size =  fsl_ddr_sdram_size();
+#endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+	fsl_dp_resume();
+#endif
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/t102xrdb/eth_t102xrdb.c b/roms/u-boot/board/freescale/t102xrdb/eth_t102xrdb.c
new file mode 100644
index 000000000..56e610928
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fdt_support.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include "../common/fman.h"
+
+int board_eth_init(struct bd_info *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+	int i, interface;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	struct mii_dev *dev;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	/* Set the on-board RGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
+
+	switch (srds_s1) {
+#ifdef CONFIG_TARGET_T1024RDB
+	case 0x95:
+		/* set the on-board RGMII2  PHY */
+		fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+
+		/* set 10G XFI with Aquantia AQR105 PHY */
+		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+		break;
+#endif
+	case 0x6a:
+	case 0x6b:
+	case 0x77:
+	case 0x135:
+		/* set the on-board 2.5G SGMII AQR105 PHY */
+		fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
+#ifdef CONFIG_TARGET_T1023RDB
+		/* set the on-board 1G SGMII RTL8211F PHY */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
+#endif
+		break;
+	default:
+		printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
+		       srds_s1);
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
+		case PHY_INTERFACE_MODE_SGMII:
+#if defined(CONFIG_TARGET_T1023RDB)
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+#elif defined(CONFIG_TARGET_T1024RDB)
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+#endif
+			fm_info_set_mdio(i, dev);
+			break;
+		case PHY_INTERFACE_MODE_SGMII_2500:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+			      enum fm_port port, int offset)
+{
+#if defined(CONFIG_TARGET_T1024RDB)
+	if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
+	     (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
+			(port == FM1_DTSEC3)) {
+		fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
+		fdt_setprop_string(fdt, offset, "phy-connection-type",
+				   "sgmii-2500");
+		fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
+	}
+#endif
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+}
diff --git a/roms/u-boot/board/freescale/t102xrdb/law.c b/roms/u-boot/board/freescale/t102xrdb/law.c
new file mode 100644
index 000000000..04a423979
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/law.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_MTD_NOR_FLASH
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/t102xrdb/pci.c b/roms/u-boot/board/freescale/t102xrdb/pci.c
new file mode 100644
index 000000000..45ab9223a
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/pci.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007-2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+#if !defined(CONFIG_DM_PCI)
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, struct bd_info *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/t102xrdb/spl.c b/roms/u-boot/board/freescale/t102xrdb/spl.c
new file mode 100644
index 000000000..71566851d
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/spl.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <console.h>
+#include <env_internal.h>
+#include <init.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include <asm/global_data.h>
+#include "../common/sleep.h"
+#include "../common/spl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return CONFIG_DDR_CLK_FREQ;
+}
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+#define GPIO1_SD_SEL 0x00020000
+int board_mmc_getcd(struct mmc *mmc)
+{
+	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val = in_be32(&pgpio->gpdat);
+
+	/* GPIO1_14, 0: eMMC, 1: SD */
+	val &= GPIO1_SD_SEL;
+
+	return val ? -1 : 1;
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val = in_be32(&pgpio->gpdat);
+
+	val &= GPIO1_SD_SEL;
+
+	return val ? -1 : 0;
+}
+#endif
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, sys_clk, ccb_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+	/* Update GD pointer */
+	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+	console_init_f();
+
+#ifdef CONFIG_DEEP_SLEEP
+	/* disable the console if boot from deep sleep */
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	sys_clk = get_board_sys_clk();
+	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+	ccb_clk = sys_clk * plat_ratio / 2;
+
+	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+		     ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	puts("\nNAND boot...\n");
+#endif
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	struct bd_info *bd;
+
+	bd = (struct bd_info *)(gd + sizeof(gd_t));
+	memset(bd, 0, sizeof(struct bd_info));
+	gd->bd = bd;
+
+	arch_cpu_init();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)SPL_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)SPL_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+	fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			       (uchar *)SPL_ENV_ADDR);
+#endif
+
+	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
+	gd->env_valid = ENV_VALID;
+
+	i2c_init_all();
+
+	dram_init();
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	fsl_spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/roms/u-boot/board/freescale/t102xrdb/t1023_nand_rcw.cfg b/roms/u-boot/board/freescale/t102xrdb/t1023_nand_rcw.cfg
new file mode 100644
index 000000000..f8f72826b
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/t1023_nand_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1023RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x77
+#Default Core=1200MHz, DDR=1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+3b800003 00000012 e8104000 21000000
+00000000 00000000 00000000 00022800
+00000130 04020200 00000000 00000006
diff --git a/roms/u-boot/board/freescale/t102xrdb/t1023_sd_rcw.cfg b/roms/u-boot/board/freescale/t102xrdb/t1023_sd_rcw.cfg
new file mode 100644
index 000000000..dbf8fba55
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/t1023_sd_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1023RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x77
+#Default Core=1200MHz, DDR=1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+3b800003 00000012 68104000 21000000
+00000000 00000000 00000000 00022800
+00000130 04020200 00000000 00000006
diff --git a/roms/u-boot/board/freescale/t102xrdb/t1023_spi_rcw.cfg b/roms/u-boot/board/freescale/t102xrdb/t1023_spi_rcw.cfg
new file mode 100644
index 000000000..5edcdb50e
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/t1023_spi_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1023RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x77
+#Default Core=1200MHz, DDR=1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+3b800003 00000012 58104000 21000000
+00000000 00000000 00000000 00022800
+00000130 04020200 00000000 00000006
diff --git a/roms/u-boot/board/freescale/t102xrdb/t1024_nand_rcw.cfg b/roms/u-boot/board/freescale/t102xrdb/t1024_nand_rcw.cfg
new file mode 100644
index 000000000..cd6f90639
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/t1024_nand_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1024RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x95
+#Core/DDR: 1400Mhz/1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+4a800003 80000012 ec027000 21000000
+00000000 00000000 00000000 00030810
+00000000 0b005a08 00000000 00000006
diff --git a/roms/u-boot/board/freescale/t102xrdb/t1024_pbi.cfg b/roms/u-boot/board/freescale/t102xrdb/t1024_pbi.cfg
new file mode 100644
index 000000000..98efca25a
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/t1024_pbi.cfg
@@ -0,0 +1,26 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 081e000d
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
diff --git a/roms/u-boot/board/freescale/t102xrdb/t1024_sd_rcw.cfg b/roms/u-boot/board/freescale/t102xrdb/t1024_sd_rcw.cfg
new file mode 100644
index 000000000..05b3f3776
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/t1024_sd_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1024RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x95
+#Core/DDR: 1400Mhz/1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+4a800003 80000012 6c027000 21000000
+00000000 00000000 00000000 00030810
+00000000 0b005a08 00000000 00000006
diff --git a/roms/u-boot/board/freescale/t102xrdb/t1024_spi_rcw.cfg b/roms/u-boot/board/freescale/t102xrdb/t1024_spi_rcw.cfg
new file mode 100644
index 000000000..8b695b4ab
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/t1024_spi_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1024RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x95
+#Core/DDR: 1400Mhz/1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+4a800003 80000012 5c027000 21000000
+00000000 00000000 00000000 00030810
+00000000 0b005a08 00000000 00000006
diff --git a/roms/u-boot/board/freescale/t102xrdb/t102xrdb.c b/roms/u-boot/board/freescale/t102xrdb/t102xrdb.c
new file mode 100644
index 000000000..51a36abe3
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/t102xrdb.c
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <image.h>
+#include <init.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include "t102xrdb.h"
+#ifdef CONFIG_TARGET_T1024RDB
+#include "cpld.h"
+#elif defined(CONFIG_TARGET_T1023RDB)
+#include <i2c.h>
+#include <mmc.h>
+#endif
+#include "../common/sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_TARGET_T1023RDB
+enum {
+	GPIO1_SD_SEL    = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
+	GPIO1_EMMC_SEL,
+	GPIO3_GET_VERSION,	       /* GPIO3_4/5, 00:RevB, 01: RevC */
+	GPIO3_BRD_VER_MASK = 0x0c000000,
+	GPIO3_OFFSET = 0x2000,
+	I2C_GET_BANK,
+	I2C_SET_BANK0,
+	I2C_SET_BANK4,
+};
+#endif
+
+int checkboard(void)
+{
+	struct cpu_type *cpu = gd->arch.cpu;
+	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	printf("Board: %sRDB, ", cpu->name);
+#if defined(CONFIG_TARGET_T1024RDB)
+	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
+	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+#elif defined(CONFIG_TARGET_T1023RDB)
+	printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
+#endif
+	printf("boot from ");
+
+#ifdef CONFIG_SDCARD
+	puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+	puts("SPI\n");
+#elif defined(CONFIG_TARGET_T1024RDB)
+	u8 reg;
+
+	reg = CPLD_READ(flash_csr);
+
+	if (reg & CPLD_BOOT_SEL) {
+		puts("NAND\n");
+	} else {
+		reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+		printf("NOR vBank%d\n", reg);
+	}
+#elif defined(CONFIG_TARGET_T1023RDB)
+#ifdef CONFIG_MTD_RAW_NAND
+	puts("NAND\n");
+#else
+	printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
+#endif
+#endif
+
+	puts("SERDES Reference Clocks:\n");
+	if (srds_s1 == 0x95)
+		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+	else
+		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
+
+	return 0;
+}
+
+#ifdef CONFIG_TARGET_T1024RDB
+static void board_mux_lane(void)
+{
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_prtcl_s1;
+	u8 reg = CPLD_READ(misc_ctl_status);
+
+	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	if (srds_prtcl_s1 == 0x95) {
+		/* Route Lane B to PCIE */
+		CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
+	} else {
+		/* Route Lane B to SGMII */
+		CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
+	}
+	CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 2;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash + promjet */
+		disable_tlb(flash_esel);
+	}
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+
+#ifdef CONFIG_TARGET_T1024RDB
+	board_mux_lane();
+#endif
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return CONFIG_DDR_CLK_FREQ;
+}
+
+#ifdef CONFIG_TARGET_T1024RDB
+void board_reset(void)
+{
+	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+#endif
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+	fsl_fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
+	fdt_fixup_fman_ethernet(blob);
+#endif
+	fdt_fixup_board_enet(blob);
+#endif
+
+#ifdef CONFIG_TARGET_T1023RDB
+	if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
+		fdt_enable_nor(blob);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_TARGET_T1023RDB
+/* Enable NOR flash for RevC */
+static void fdt_enable_nor(void *blob)
+{
+	int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
+
+	if (nodeoff >= 0)
+		fdt_status_okay(blob, nodeoff);
+	else
+		printf("WARNING unable to set status for NOR\n");
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val = in_be32(&pgpio->gpdat);
+
+	/* GPIO1_14, 0: eMMC, 1: SD/MMC */
+	val &= GPIO1_SD_SEL;
+
+	return val ? -1 : 1;
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val = in_be32(&pgpio->gpdat);
+
+	val &= GPIO1_SD_SEL;
+
+	return val ? -1 : 0;
+}
+
+static u32 t1023rdb_ctrl(u32 ctrl_type)
+{
+	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gur_t __iomem  *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 val;
+	u8 tmp;
+	int bus_num = I2C_PCA6408_BUS_NUM;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	switch (ctrl_type) {
+	case GPIO1_SD_SEL:
+		val = in_be32(&pgpio->gpdat);
+		val |= GPIO1_SD_SEL;
+		out_be32(&pgpio->gpdat, val);
+		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
+		break;
+	case GPIO1_EMMC_SEL:
+		val = in_be32(&pgpio->gpdat);
+		val &= ~GPIO1_SD_SEL;
+		out_be32(&pgpio->gpdat, val);
+		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
+		break;
+	case GPIO3_GET_VERSION:
+		pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
+			 + GPIO3_OFFSET);
+		val = in_be32(&pgpio->gpdat);
+		val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
+		if (val == 0x3) /* GPIO3_4/5 not used on RevB */
+			val = 0;
+		return val;
+	case I2C_GET_BANK:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		tmp &= 0x7;
+		tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
+		return tmp;
+	case I2C_SET_BANK0:
+		tmp = 0x0;
+		dm_i2c_write(dev, 1, &tmp, 1);
+		tmp = 0xf8;
+		dm_i2c_write(dev, 3, &tmp, 1);
+		/* asserting HRESET_REQ */
+		out_be32(&gur->rstcr, 0x2);
+		break;
+	case I2C_SET_BANK4:
+		tmp = 0x1;
+		dm_i2c_write(dev, 1, &tmp, 1);
+		tmp = 0xf8;
+		dm_i2c_write(dev, 3, &tmp, 1);
+		out_be32(&gur->rstcr, 0x2);
+		break;
+	default:
+		break;
+	}
+#else
+	u32 orig_bus;
+
+	orig_bus = i2c_get_bus_num();
+
+	switch (ctrl_type) {
+	case GPIO1_SD_SEL:
+		val = in_be32(&pgpio->gpdat);
+		val |= GPIO1_SD_SEL;
+		out_be32(&pgpio->gpdat, val);
+		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
+		break;
+	case GPIO1_EMMC_SEL:
+		val = in_be32(&pgpio->gpdat);
+		val &= ~GPIO1_SD_SEL;
+		out_be32(&pgpio->gpdat, val);
+		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
+		break;
+	case GPIO3_GET_VERSION:
+		pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
+			 + GPIO3_OFFSET);
+		val = in_be32(&pgpio->gpdat);
+		val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
+		if (val == 0x3) /* GPIO3_4/5 not used on RevB */
+			val = 0;
+		return val;
+	case I2C_GET_BANK:
+		i2c_set_bus_num(bus_num);
+		i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
+		tmp &= 0x7;
+		tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
+		i2c_set_bus_num(orig_bus);
+		return tmp;
+	case I2C_SET_BANK0:
+		i2c_set_bus_num(bus_num);
+		tmp = 0x0;
+		i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
+		tmp = 0xf8;
+		i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
+		/* asserting HRESET_REQ */
+		out_be32(&gur->rstcr, 0x2);
+		break;
+	case I2C_SET_BANK4:
+		i2c_set_bus_num(bus_num);
+		tmp = 0x1;
+		i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
+		tmp = 0xf8;
+		i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
+		out_be32(&gur->rstcr, 0x2);
+		break;
+	default:
+		break;
+	}
+#endif
+	return 0;
+}
+
+static int switch_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+		      char *const argv[])
+{
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	if (!strcmp(argv[1], "bank0"))
+		t1023rdb_ctrl(I2C_SET_BANK0);
+	else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
+		t1023rdb_ctrl(I2C_SET_BANK4);
+	else if (!strcmp(argv[1], "sd"))
+		t1023rdb_ctrl(GPIO1_SD_SEL);
+	else if (!strcmp(argv[1], "emmc"))
+		t1023rdb_ctrl(GPIO1_EMMC_SEL);
+	else
+		return CMD_RET_USAGE;
+	return 0;
+}
+
+U_BOOT_CMD(
+	switch, 2, 0, switch_cmd,
+	"for bank0/bank4/sd/emmc switch control in runtime",
+	"command (e.g. switch bank4)"
+);
+#endif
diff --git a/roms/u-boot/board/freescale/t102xrdb/t102xrdb.h b/roms/u-boot/board/freescale/t102xrdb/t102xrdb.h
new file mode 100644
index 000000000..33df0f24d
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/t102xrdb.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __T1024_RDB_H__
+#define __T1024_RDB_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, struct bd_info *bd);
+#ifdef CONFIG_TARGET_T1023RDB
+static u32 t1023rdb_ctrl(u32 ctrl_type);
+static void fdt_enable_nor(void *blob);
+#endif
+#endif
diff --git a/roms/u-boot/board/freescale/t102xrdb/tlb.c b/roms/u-boot/board/freescale/t102xrdb/tlb.c
new file mode 100644
index 000000000..97080eb95
--- /dev/null
+++ b/roms/u-boot/board/freescale/t102xrdb/tlb.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 5, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 7, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 12, BOOKE_PAGESZ_1G, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 13, BOOKE_PAGESZ_1G, 1)
+#endif
+	/* entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so if needed more, will use entry 16 later.
+	 */
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/freescale/t104xrdb/Kconfig b/roms/u-boot/board/freescale/t104xrdb/Kconfig
new file mode 100644
index 000000000..e6e46fa12
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_T1040RDB || TARGET_T1040D4RDB || \
+	TARGET_T1042RDB || TARGET_T1042D4RDB || \
+	TARGET_T1042RDB_PI
+
+config SYS_BOARD
+	default "t104xrdb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "T104xRDB"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/t104xrdb/MAINTAINERS b/roms/u-boot/board/freescale/t104xrdb/MAINTAINERS
new file mode 100644
index 000000000..4e82f7f2e
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/MAINTAINERS
@@ -0,0 +1,31 @@
+T104XRDB BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	board/freescale/t104xrdb/
+F:	include/configs/T104xRDB.h
+F:	configs/T1040RDB_defconfig
+F:	configs/T1040RDB_NAND_defconfig
+F:	configs/T1040RDB_SPIFLASH_defconfig
+F:	configs/T1040D4RDB_defconfig
+F:	configs/T1040D4RDB_NAND_defconfig
+F:	configs/T1040D4RDB_SPIFLASH_defconfig
+F:	configs/T1042RDB_defconfig
+F:	configs/T1042D4RDB_defconfig
+F:	configs/T1042D4RDB_NAND_defconfig
+F:	configs/T1042D4RDB_SPIFLASH_defconfig
+F:	configs/T1042RDB_PI_defconfig
+F:	configs/T1042RDB_PI_NAND_defconfig
+F:	configs/T1042RDB_PI_SPIFLASH_defconfig
+
+T1040RDB_SDCARD BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	configs/T1040RDB_SDCARD_defconfig
+F:	configs/T1040D4RDB_SDCARD_defconfig
+F:	configs/T1042D4RDB_SDCARD_defconfig
+F:	configs/T1042RDB_PI_SDCARD_defconfig
+
+T1042D4RDB_SECURE_BOOT BOARD
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
+S:	Maintained
+F:	configs/T1042D4RDB_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/t104xrdb/Makefile b/roms/u-boot/board/freescale/t104xrdb/Makefile
new file mode 100644
index 000000000..31abbd9ac
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y	+= t104xrdb.o
+obj-y	+= cpld.o
+obj-y	+= eth.o
+obj-$(CONFIG_PCI)	+= pci.o
+obj-$(CONFIG_FSL_DIU_FB)+= diu.o
+endif
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/roms/u-boot/board/freescale/t104xrdb/README b/roms/u-boot/board/freescale/t104xrdb/README
new file mode 100644
index 000000000..09cb98e33
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/README
@@ -0,0 +1,386 @@
+Overview
+--------
+The T1040RDB is a Freescale reference board that hosts the T1040 SoC
+(and variants). Variants inclued T1042 presonality of T1040, in which
+case T1040RDB can also be called T1042RDB.
+
+The T1042RDB is a Freescale reference board that hosts the T1042 SoC
+(and variants). The board is similar to T1040RDB, T1040 is a reduced
+personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
+
+The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
+(a personality of T1040 SoC). The board is similar to T1040RDB but is
+designed specially with low power features targeted for Printing Image Market.
+
+The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
+The board is re-designed T1040RDB board with following changes :
+    - Support of DDR4 memory and some enhancements
+
+The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC.
+The board is re-designed T1040RDB board with following changes :
+    - Support of DDR4 memory
+    - Support for 0x86 serdes protocol which can support following interfaces
+        - 2 RGMII's on DTSEC4, DTSEC5
+        - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
+
+Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
+-------------------------------------------------------------------------
+Board		Si		Protocol		Targeted Market
+-------------------------------------------------------------------------
+T1040RDB	T1040		0x66                    Networking
+T1040RDB	T1042		0x86                    Networking
+T1042RDB_PI	T1042		0x06                    Printing & Imaging
+T1040D4RDB	T1040		0x66                    Networking
+T1042D4RDB	T1042		0x86                    Networking
+
+
+T1040 SoC Overview
+------------------
+The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
+processor cores with high-performance data path acceleration architecture
+and network peripheral interfaces required for networking & telecommunications.
+
+The T1040/T1042 SoC includes the following function and features:
+
+ - Four e5500 cores, each with a private 256 KB L2 cache
+ - 256 KB shared L3 CoreNet platform cache (CPC)
+ - Interconnect CoreNet platform
+ - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ for the following functions:
+    -  Packet parsing, classification, and distribution
+    -  Queue management for scheduling, packet sequencing, and congestion
+       management
+    -  Cryptography Acceleration (SEC 5.0)
+    - RegEx Pattern Matching Acceleration (PME 2.2)
+    - IEEE Std 1588 support
+    - Hardware buffer management for buffer allocation and deallocation
+ - Ethernet interfaces
+    - Integrated 8-port Gigabit Ethernet switch (T1040 only)
+    - Four 1 Gbps Ethernet controllers
+ - Two RGMII interfaces or one RGMII and one MII interfaces
+ - High speed peripheral interfaces
+   - Four PCI Express 2.0 controllers running at up to 5 GHz
+   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
+   - Upto two QSGMII interface
+   - Upto six SGMII interface supporting 1000 Mbps
+   - One SGMII interface supporting upto 2500 Mbps
+ - Additional peripheral interfaces
+   - Two USB 2.0 controllers with integrated PHY
+   - SD/eSDHC/eMMC
+   - eSPI controller
+   - Four I2C controllers
+   - Four UARTs
+   - Four GPIO controllers
+   - Integrated flash controller (IFC)
+   - LCD and HDMI interface (DIU) with 12 bit dual data rate
+   - TDM interface
+ - Multicore programmable interrupt controller (PIC)
+ - Two 8-channel DMA engines
+ - Single source clocking implementation
+ - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+
+T1040 SoC Personalities
+-------------------------
+T1022 Personality:
+T1022 is a reduced personality of T1040 with less core/clusters.
+
+T1042 Personality:
+T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
+Ethernet switch. Rest of the blocks are same as T1040
+
+
+T1040RDB board Overview
+-------------------------
+ - SERDES Connections, 8 lanes information:
+	1: None
+	2: SGMII
+	3: QSGMII
+	4: QSGMII
+	5: PCIe1 x1 slot
+	6: mini PCIe connector
+	7: mini PCIe connector
+	8: SATA connector
+ - DDR Controller
+     - Supports rates of up to 1600 MHz data-rate
+     - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ - IFC/Local Bus
+     - NAND flash: 1GB 8-bit NAND flash
+     - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+     - Two on-board RGMII 10/100/1G ethernet ports.
+ - CPLD
+ - Clocks
+     - System and DDR clock (SYSCLK, “DDRCLK”)
+     - SERDES clocks
+ - Power Supplies
+ - USB
+     - Supports two USB 2.0 ports with integrated PHYs
+     - Two type A ports with 5V@1.5A per port.
+ - SDHC
+     - SDHC/SDXC connector
+ - SPI
+    -  On-board 64MB SPI flash
+ - Other IO
+    - Two Serial ports
+    - Four I2C ports
+
+T1042RDB_PI board Overview
+-------------------------
+ - SERDES Connections, 8 lanes information:
+	1, 2, 3, 4 : PCIe x4 slot
+	5: mini PCIe connector
+	6: mini PCIe connector
+	7: NA
+	8: SATA connector
+ - DDR Controller
+     - Supports rates of up to 1600 MHz data-rate
+     - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ - IFC/Local Bus
+     - NAND flash: 1GB 8-bit NAND flash
+     - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+     - Two on-board RGMII 10/100/1G ethernet ports.
+ - CPLD
+ - Clocks
+     - System and DDR clock (SYSCLK, “DDRCLK”)
+     - SERDES clocks
+ - Video
+     - DIU supports video at up to 1280x1024x32bpp
+ - Power Supplies
+ - USB
+     - Supports two USB 2.0 ports with integrated PHYs
+     - Two type A ports with 5V@1.5A per port.
+ - SDHC
+     - SDHC/SDXC connector
+ - SPI
+    -  On-board 64MB SPI flash
+ - Other IO
+    - Two Serial ports
+    - Four I2C ports
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address  End Address      Description                     Size
+0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - CPLD                      4KB
+0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash                64KB
+0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR                         16MB
+0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space         64KB
+0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space	        64KB
+0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space         64KB
+0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space	        64KB
+0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
+0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
+0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash                 128MB
+0xF_0000_0000  0xF_003F_FFFF    DCSR                            4MB
+0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 4 Mem Space         256MB
+0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space         256MB
+0xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space         256MB
+0xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space         256MB
+0x0_0000_0000  0x0_ffff_ffff    DDR                             2GB
+
+
+NOR Flash memory Map
+---------------------
+ Start          End             Definition                       Size
+0xEFF40000      0xEFFFFFFF      U-Boot (current bank)            768KB
+0xEFF20000      0xEFF3FFFF      U-Boot env (current bank)        128KB
+0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)        128KB
+0xED300000      0xEFEFFFFF      rootfs (alt bank)                44MB
+0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank)  1MB
+0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)          7MB + 875KB
+0xEC000000      0xEC01FFFF      RCW (alt bank)                   128KB
+0xEBF40000      0xEBFFFFFF      U-Boot (alt bank)                768KB
+0xEBF20000      0xEBF3FFFF      U-Boot env (alt bank)            128KB
+0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)            128KB
+0xE9300000      0xEBEFFFFF      rootfs (current bank)            44MB
+0xE8800000      0xE88FFFFF      Hardware device tree (cur bank)  11MB + 512KB
+0xE8020000      0xE86FFFFF      Linux.uImage (current bank)      7MB + 875KB
+0xE8000000      0xE801FFFF      RCW (current bank)               128KB
+
+
+Various Software configurations/environment variables/commands
+--------------------------------------------------------------
+The below commands apply to the board
+
+1. U-Boot environment variable hwconfig
+   The default hwconfig is:
+	hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
+					dr_mode=host,phy_type=utmi
+   Note: For USB gadget set "dr_mode=peripheral"
+
+2. FMAN Ucode versions
+   fsl_fman_ucode_t1040.bin
+
+3. Switching to alternate bank
+   Commands for switching to alternate bank.
+
+	1. To change from vbank0 to vbank4
+		=> cpld reset altbank (it will boot using vbank4)
+
+	2.To change from vbank4 to vbank0
+		=> cpld reset (it will boot using vbank0)
+
+NAND boot with 2 Stage boot loader
+----------------------------------
+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
+SPL further initialise DDR using SPD and environment variables and copy
+U-Boot(768 KB) from flash to DDR.
+Finally SPL transer control to U-Boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+ Run time view of SPL framework during  boot :-
+ -----------------------------------------------
+ Area        | Address                         |
+-----------------------------------------------
+ Secure boot | 0xFFFC0000 (32KB)               |
+ headers     |                                 |
+ -----------------------------------------------
+ GD, BD      | 0xFFFC8000 (4KB)                |
+ -----------------------------------------------
+ ENV         | 0xFFFC9000 (8KB)                |
+ -----------------------------------------------
+ HEAP        | 0xFFFCB000 (30KB)               |
+ -----------------------------------------------
+ STACK       | 0xFFFD8000 (22KB)               |
+ -----------------------------------------------
+ U-Boot SPL  | 0xFFFD8000 (160KB)              |
+ -----------------------------------------------
+
+NAND Flash memory Map on T104xRDB
+------------------------------------------
+ Start		 End		Definition			Size
+0x000000	0x0FFFFF	U-Boot                          1MB
+0x180000	0x19FFFF	U-Boot env                      128KB
+0x280000	0x29FFFF	FMAN Ucode                      128KB
+0x380000	0x39FFFF	QE Firmware                     128KB
+
+SD Card memory Map on T104xRDB
+------------------------------------------
+ Block		#blocks		Definition			Size
+0x008		2048		U-Boot                          1MB
+0x800		0024		U-Boot env                      8KB
+0x820		0256		FMAN Ucode                      128KB
+0x920		0256		QE Firmware                     128KB
+
+SPI Flash memory Map on T104xRDB
+------------------------------------------
+ Start		 End		Definition			Size
+0x000000	0x0FFFFF	U-Boot                          1MB
+0x100000	0x101FFF	U-Boot env                      8KB
+0x110000	0x12FFFF	FMAN Ucode                      128KB
+0x130000	0x14FFFF	QE Firmware                     128KB
+
+Please note QE Firmware is only valid for T1040RDB
+
+
+Switch Settings for T104xRDB boards: (ON is 0, OFF is 1)
+==========================================================
+NOR boot SW setting:
+SW1: 00010011
+SW2: 10111011
+SW3: 11100001
+
+NAND boot SW setting:
+SW1: 10001000
+SW2: 00111011
+SW3: 11110001
+
+SPI boot SW setting:
+SW1: 00100010
+SW2: 10111011
+SW3: 11100001
+
+SD boot SW setting:
+SW1: 00100000
+SW2: 00111011
+SW3: 11100001
+
+Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1)
+=============================================================
+NOR boot SW setting:
+SW1: 00010011
+SW2: 10111001
+SW3: 11100001
+
+NAND boot SW setting:
+SW1: 10001000
+SW2: 00111001
+SW3: 11110001
+
+SPI boot SW setting:
+SW1: 00100010
+SW2: 10111001
+SW3: 11100001
+
+SD boot SW setting:
+SW1: 00100000
+SW2: 00111001
+SW3: 11100001
+
+PBL-based image generation
+==========================
+Changes only the required register bit in in PBI commands.
+
+Provides reference code which might needs some
+modification as per requirement.
+example:
+By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file
+which needs to be changed for SPI and SD.
+
+For SD-boot
+==============
+1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files)
+
+example:
+ RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
+
+Change
+66000002 40000002 ec027000 01000000
+to
+66000002 40000002 6c027000 01000000
+
+2. SD does not support flush so remove flush from pbl, make changes in
+   tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
+   with 0x091380c0
+
+For SPI-boot
+==============
+1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files)
+
+example:
+ RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
+
+Change
+66000002 40000002 ec027000 01000000
+to
+66000002 40000002 5c027000 01000000
+
+2. SPI does not support flush so remove flush from pbl, make changes in
+   tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
+   with 0x091380c0
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for t1042d4rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/roms/u-boot/board/freescale/t104xrdb/cpld.c b/roms/u-boot/board/freescale/t104xrdb/cpld.c
new file mode 100644
index 000000000..ac34095f3
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/cpld.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	out_8(p + reg, value);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(void)
+{
+	u8 reg = CPLD_READ(flash_ctl_status);
+
+	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+
+	CPLD_WRITE(flash_ctl_status, reg);
+	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+	u8 reg = CPLD_READ(flash_ctl_status);
+
+	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+
+	CPLD_WRITE(flash_ctl_status, reg);
+	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+	printf("cpld_ver	 = 0x%02x\n", CPLD_READ(cpld_ver));
+	printf("cpld_ver_sub	 = 0x%02x\n", CPLD_READ(cpld_ver_sub));
+	printf("hw_ver		 = 0x%02x\n", CPLD_READ(hw_ver));
+	printf("sw_ver		 = 0x%02x\n", CPLD_READ(sw_ver));
+	printf("reset_ctl1	 = 0x%02x\n", CPLD_READ(reset_ctl1));
+	printf("reset_ctl2	 = 0x%02x\n", CPLD_READ(reset_ctl2));
+	printf("int_status	 = 0x%02x\n", CPLD_READ(int_status));
+	printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
+	printf("fan_ctl_status	 = 0x%02x\n", CPLD_READ(fan_ctl_status));
+#if defined(CONFIG_TARGET_T1040D4D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
+	printf("int_mask	 = 0x%02x\n", CPLD_READ(int_mask));
+#else
+	printf("led_ctl_status	 = 0x%02x\n", CPLD_READ(led_ctl_status));
+#endif
+	printf("sfp_ctl_status	 = 0x%02x\n", CPLD_READ(sfp_ctl_status));
+	printf("misc_ctl_status	 = 0x%02x\n", CPLD_READ(misc_ctl_status));
+	printf("boot_override	 = 0x%02x\n", CPLD_READ(boot_override));
+	printf("boot_config1	 = 0x%02x\n", CPLD_READ(boot_config1));
+	printf("boot_config2	 = 0x%02x\n", CPLD_READ(boot_config2));
+	putc('\n');
+}
+#endif
+
+int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int rc = 0;
+
+	if (argc <= 1)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		if (strcmp(argv[2], "altbank") == 0)
+			cpld_set_altbank();
+		else
+			cpld_set_defbank();
+#ifdef DEBUG
+	} else if (strcmp(argv[1], "dump") == 0) {
+		cpld_dump_regs();
+#endif
+	} else
+		rc = cmd_usage(cmdtp);
+
+	return rc;
+}
+
+U_BOOT_CMD(
+	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+	"Reset the board or alternate bank",
+	"reset - hard reset to default bank\n"
+	"cpld reset altbank - reset to alternate bank\n"
+#ifdef DEBUG
+	"cpld dump - display the CPLD registers\n"
+#endif
+	);
diff --git a/roms/u-boot/board/freescale/t104xrdb/cpld.h b/roms/u-boot/board/freescale/t104xrdb/cpld.h
new file mode 100644
index 000000000..a816aef10
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/cpld.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/**
+ * Copyright 2013 Freescale Semiconductor
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+struct cpld_data {
+	u8 cpld_ver;		/* 0x00 - CPLD Major Revision Register */
+	u8 cpld_ver_sub;	/* 0x01 - CPLD Minor Revision Register */
+	u8 hw_ver;		/* 0x02 - Hardware Revision Register */
+	u8 sw_ver;		/* 0x03 - Software Revision register */
+	u8 res0[12];		/* 0x04 - 0x0F - not used */
+	u8 reset_ctl1;		/* 0x10 - Reset control Register1 */
+	u8 reset_ctl2;		/* 0x11 - Reset control Register2 */
+	u8 int_status;		/* 0x12 - Interrupt status Register */
+	u8 flash_ctl_status;	/* 0x13 - Flash control and status register */
+	u8 fan_ctl_status;	/* 0x14 - Fan control and status register  */
+#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
+	u8 int_mask;		/* 0x15 - Interrupt mask Register */
+#else
+	u8 led_ctl_status;	/* 0x15 - LED control and status register */
+#endif
+	u8 sfp_ctl_status;	/* 0x16 - SFP control and status register  */
+	u8 misc_ctl_status;	/* 0x17 - Miscellanies ctrl & status register*/
+	u8 boot_override;	/* 0x18 - Boot override register */
+	u8 boot_config1;	/* 0x19 - Boot config override register*/
+	u8 boot_config2;	/* 0x1A - Boot config override register*/
+} cpld_data_t;
+
+
+/* Pointer to the CPLD register set */
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)\
+		cpld_write(offsetof(struct cpld_data, reg), value)
+#define MISC_CTL_SG_SEL		0x80
+#define MISC_CTL_AURORA_SEL	0x02
+#define MISC_MUX_QE_TDM		0xc0
diff --git a/roms/u-boot/board/freescale/t104xrdb/ddr.c b/roms/u-boot/board/freescale/t104xrdb/ddr.c
new file mode 100644
index 000000000..8351f7ce9
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/ddr.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
+#include <linux/delay.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found\n");
+		printf("for data rate %lu MT/s\n", ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+		"wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	popts->half_strength_driver_enable = 1;
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x59;
+#else
+	popts->half_strength_driver_enable = 0;
+#endif
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * rtt and rtt_wr override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
+		DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
+#else
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+	void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+	/* does not provide HW signals for power management */
+	clrbits_8(cpld_base + 0x17, 0x40);
+	/* Disable MCKE isolation */
+	gpio_set_value(2, 0);
+	udelay(1);
+}
+#endif
+
+int dram_init(void)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+	puts("Initializing....using SPD\n");
+	dram_size = fsl_ddr_sdram();
+#else
+	dram_size =  fsl_ddr_sdram_size();
+#endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+	fsl_dp_resume();
+#endif
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/t104xrdb/ddr.h b/roms/u-boot/board/freescale/t104xrdb/ddr.h
new file mode 100644
index 000000000..f9d667f61
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/ddr.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2
+	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	{2,  1600, 4, 8,     6, 0x07090A0c, 0x0e0f100a},
+	{1,  1600, 4, 8,     5, 0x0607080B, 0x0C0C0D09},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+	{2,  833,  4, 8,     6, 0x06060607, 0x08080807},
+	{2,  833,  0, 8,     6, 0x06060607, 0x08080807},
+	{2,  1350, 4, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{2,  1666, 4, 8,     7, 0x0808090B, 0x0C0D0E0A},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  833,  4, 8,     6, 0x06060607, 0x08080807},
+	{1,  833,  0, 8,     6, 0x06060607, 0x08080807},
+	{1,  1350, 4, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1666, 4, 8,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A},
+#else
+#error DDR type not defined
+#endif
+	{}
+};
+
+#endif
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
diff --git a/roms/u-boot/board/freescale/t104xrdb/diu.c b/roms/u-boot/board/freescale/t104xrdb/diu.c
new file mode 100644
index 000000000..25c859720
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/diu.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
+ */
+
+#include <clock_legacy.h>
+#include <asm/io.h>
+#include <common.h>
+#include <command.h>
+#include <fsl_diu_fb.h>
+#include <linux/ctype.h>
+#include <video_fb.h>
+
+#include "../common/diu_ch7301.h"
+
+#include "cpld.h"
+#include "t104xrdb.h"
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F		0x10000000
+#define AD_ALPHA_C_SHIFT	25
+#define AD_BLUE_C_SHIFT		23
+#define AD_GREEN_C_SHIFT	21
+#define AD_RED_C_SHIFT		19
+#define AD_PIXEL_S_SHIFT	16
+#define AD_COMP_3_SHIFT		12
+#define AD_COMP_2_SHIFT		8
+#define AD_COMP_1_SHIFT		4
+#define AD_COMP_0_SHIFT		0
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+	unsigned long speed_ccb, temp;
+	u32 pixval;
+	int ret;
+
+	speed_ccb = get_bus_freq(0);
+	temp = 1000000000 / pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+
+	/* Program HDMI encoder */
+	ret = diu_set_dvi_encoder(temp);
+	if (ret) {
+		puts("Failed to set DVI encoder\n");
+		return;
+	}
+
+	/* Program pixel clock */
+	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
+		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
+
+	/* enable clock*/
+	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
+		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+	u32 pixel_format;
+	u8 sw;
+
+	/*Configure Display ouput port as HDMI*/
+	sw = CPLD_READ(sfp_ctl_status);
+	CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
+
+	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+	printf("DIU: Switching to monitor DVI @ %ux%u\n",  xres, yres);
+
+	return fsl_diu_init(xres, yres, pixel_format, 0);
+}
diff --git a/roms/u-boot/board/freescale/t104xrdb/eth.c b/roms/u-boot/board/freescale/t104xrdb/eth.c
new file mode 100644
index 000000000..b034f11d6
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/eth.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fsl_dtsec.h>
+#include <vsc9953.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct memac_mdio_info memac_mdio_info;
+	unsigned int i;
+	int phy_addr = 0;
+#ifdef CONFIG_VSC9953
+	phy_interface_t phy_int;
+	struct mii_dev *bus;
+#endif
+
+	printf("Initializing Fman\n");
+
+	memac_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fm_memac_mdio_init(bis, &memac_mdio_info);
+
+	/*
+	 * Program on board RGMII, SGMII PHY addresses.
+	 */
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
+		case PHY_INTERFACE_MODE_SGMII:
+			/* T1040RDB & T1040D4RDB only supports SGMII on
+			 * DTSEC3
+			 */
+			fm_info_set_phy_address(FM1_DTSEC3,
+						CONFIG_SYS_SGMII1_PHY_ADDR);
+			break;
+#endif
+#ifdef CONFIG_TARGET_T1042RDB
+		case PHY_INTERFACE_MODE_SGMII:
+			/* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
+			if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
+				fm_info_set_phy_address(i, 0);
+			/* T1042RDB only supports SGMII on DTSEC3 */
+			fm_info_set_phy_address(FM1_DTSEC3,
+						CONFIG_SYS_SGMII1_PHY_ADDR);
+			break;
+#endif
+#ifdef CONFIG_TARGET_T1042D4RDB
+		case PHY_INTERFACE_MODE_SGMII:
+			/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
+			 *  & DTSEC3
+			 */
+			if (FM1_DTSEC1 == i)
+				phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
+			if (FM1_DTSEC2 == i)
+				phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
+			if (FM1_DTSEC3 == i)
+				phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
+			fm_info_set_phy_address(i, phy_addr);
+			break;
+#endif
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			if (FM1_DTSEC4 == i)
+				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
+			if (FM1_DTSEC5 == i)
+				phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
+			fm_info_set_phy_address(i, phy_addr);
+			break;
+		case PHY_INTERFACE_MODE_QSGMII:
+			fm_info_set_phy_address(i, 0);
+			break;
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
+			break;
+		default:
+			printf("Fman1: DTSEC%u set to unknown interface %i\n",
+			       idx + 1, fm_info_get_enet_if(i));
+			fm_info_set_phy_address(i, 0);
+			break;
+		}
+		if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
+		    fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
+			fm_info_set_mdio(i, NULL);
+		else
+			fm_info_set_mdio(i,
+					 miiphy_get_dev_by_name(
+							DEFAULT_FM_MDIO_NAME));
+	}
+
+#ifdef CONFIG_VSC9953
+	/* SerDes configured for QSGMII */
+	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
+		for (i = 0; i < 4; i++) {
+			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
+			phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+			vsc9953_port_info_set_mdio(i, bus);
+			vsc9953_port_info_set_phy_address(i, phy_addr);
+			vsc9953_port_info_set_phy_int(i, phy_int);
+			vsc9953_port_enable(i);
+		}
+	}
+	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
+		for (i = 4; i < 8; i++) {
+			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
+			phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+			vsc9953_port_info_set_mdio(i, bus);
+			vsc9953_port_info_set_phy_address(i, phy_addr);
+			vsc9953_port_info_set_phy_int(i, phy_int);
+			vsc9953_port_enable(i);
+		}
+	}
+
+	/* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
+	if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
+		vsc9953_port_enable(8);
+
+	/* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
+	if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
+		/* Enable L2 On MAC2 using SCFG */
+		struct ccsr_scfg *scfg = (struct ccsr_scfg *)
+				CONFIG_SYS_MPC85xx_SCFG;
+
+		out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
+			 (0x80000000));
+		vsc9953_port_enable(9);
+	}
+#endif
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/freescale/t104xrdb/law.c b/roms/u-boot/board/freescale/t104xrdb/law.c
new file mode 100644
index 000000000..0f6b71a8c
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/law.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_MTD_NOR_FLASH
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/t104xrdb/pci.c b/roms/u-boot/board/freescale/t104xrdb/pci.c
new file mode 100644
index 000000000..1fd240270
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/pci.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+#if !defined(CONFIG_DM_PCI)
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, struct bd_info *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/t104xrdb/spl.c b/roms/u-boot/board/freescale/t104xrdb/spl.c
new file mode 100644
index 000000000..f5fe73e62
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/spl.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <console.h>
+#include <env_internal.h>
+#include <init.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include <asm/global_data.h>
+#include "../common/sleep.h"
+#include "../common/spl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return CONFIG_DDR_CLK_FREQ;
+}
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK	0xFF800000
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, sys_clk, uart_clk;
+#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
+	u32 porsr1, pinctl;
+	u32 svr = get_svr();
+#endif
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
+	if (IS_SVR_REV(svr, 1, 0)) {
+		/*
+		 * There is T1040 SoC issue where NOR, FPGA are inaccessible
+		 * during NAND boot because IFC signals > IFC_AD7 are not
+		 * enabled. This workaround changes RCW source to make all
+		 * signals enabled.
+		 */
+		porsr1 = in_be32(&gur->porsr1);
+		pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
+			  | 0x24800000);
+		out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
+			 pinctl);
+	}
+#endif
+
+	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+	/* Update GD pointer */
+	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+#ifdef CONFIG_DEEP_SLEEP
+	/* disable the console if boot from deep sleep */
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+	/* compiler optimization barrier needed for GCC >= 3.4 */
+	__asm__ __volatile__("" : : : "memory");
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	sys_clk = get_board_sys_clk();
+	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+	uart_clk = sys_clk * plat_ratio / 2;
+
+	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+		     uart_clk / 16 / CONFIG_BAUDRATE);
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	struct bd_info *bd;
+
+	bd = (struct bd_info *)(gd + sizeof(gd_t));
+	memset(bd, 0, sizeof(struct bd_info));
+	gd->bd = bd;
+
+	arch_cpu_init();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+
+	/* relocate environment function pointers etc. */
+#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_MMC) || \
+	defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)SPL_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)SPL_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+	fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			       (uchar *)SPL_ENV_ADDR);
+#endif
+	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
+	gd->env_valid = ENV_VALID;
+#endif
+
+	i2c_init_all();
+
+	puts("\n\n");
+
+	dram_init();
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	fsl_spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1040_nand_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1040_nand_rcw.cfg
new file mode 100644
index 000000000..3300c184a
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1040_nand_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 80000002 e8106000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1040_sd_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1040_sd_rcw.cfg
new file mode 100644
index 000000000..fd3e8c5bb
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1040_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 80000002 68106000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1040_spi_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1040_spi_rcw.cfg
new file mode 100644
index 000000000..fccde5e01
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1040_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 80000002 58106000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
new file mode 100644
index 000000000..c1034b3df
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 40000002 ec027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342580f 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
new file mode 100644
index 000000000..e6f7585bb
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 40000002 6c027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342580f 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
new file mode 100644
index 000000000..cde862dff
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 40000002 5c027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342580f 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1042_nand_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1042_nand_rcw.cfg
new file mode 100644
index 000000000..db4d52f39
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1042_nand_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 80000002 ec027000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
new file mode 100644
index 000000000..57de89ad0
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x06
+0c18000e 0e000000 00000000 00000000
+06000002 00400002 e8106000 01000000
+00000000 00000000 00000000 00030810
+00000000 01fe0a06 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
new file mode 100644
index 000000000..bbce9a369
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x06
+0c18000e 0e000000 00000000 00000000
+06000002 00400002 68106000 01000000
+00000000 00000000 00000000 00030810
+00000000 01fe0a06 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
new file mode 100644
index 000000000..b1d8b4c65
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x06
+0c18000e 0e000000 00000000 00000000
+06000002 00400002 58106000 01000000
+00000000 00000000 00000000 00030810
+00000000 01fe0a06 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1042_sd_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1042_sd_rcw.cfg
new file mode 100644
index 000000000..d77bf189b
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1042_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 80000002 6c027000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1042_spi_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1042_spi_rcw.cfg
new file mode 100644
index 000000000..e8a3ad128
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1042_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 80000002 5c027000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
new file mode 100644
index 000000000..9e0ee2795
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 40000002 ec027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342500f 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
new file mode 100644
index 000000000..9d9046d65
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 40000002 6c027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342500f 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg b/roms/u-boot/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
new file mode 100644
index 000000000..f1ec98932
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 40000002 5c027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342500f 00000000 00000000
diff --git a/roms/u-boot/board/freescale/t104xrdb/t104x_pbi.cfg b/roms/u-boot/board/freescale/t104xrdb/t104x_pbi.cfg
new file mode 100644
index 000000000..51945b474
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t104x_pbi.cfg
@@ -0,0 +1,36 @@
+#PBI commands
+#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
+09250100 00000400
+09250108 00002000
+#Software Workaround for errata A-008007 to reset PVR register
+09000010 0000000b
+09000014 c0000000
+09000018 81d00017
+89020400 a1000000
+091380c0 000f0000
+89020400 00000000
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 081e000d
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
diff --git a/roms/u-boot/board/freescale/t104xrdb/t104x_pbi_sb.cfg b/roms/u-boot/board/freescale/t104xrdb/t104x_pbi_sb.cfg
new file mode 100644
index 000000000..98dc8e4c2
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t104x_pbi_sb.cfg
@@ -0,0 +1,38 @@
+#PBI commands
+#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
+09250100 00000400
+09250108 00002000
+#Software Workaround for errata A-008007 to reset PVR register
+09000010 0000000b
+09000014 c0000000
+09000018 81d00017
+89020400 a1000000
+091380c0 000f0000
+89020400 00000000
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 bffc0007
+09010f00 081e000d
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 bffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 bf000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
+090e0200 bffd0000
+091380c0 000FFFFF
diff --git a/roms/u-boot/board/freescale/t104xrdb/t104xrdb.c b/roms/u-boot/board/freescale/t104xrdb/t104xrdb.c
new file mode 100644
index 000000000..780043483
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t104xrdb.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <hwconfig.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_fdt.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include "../common/sleep.h"
+#include "t104xrdb.h"
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	struct cpu_type *cpu = gd->arch.cpu;
+	u8 sw;
+
+#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
+	printf("Board: %sD4RDB\n", cpu->name);
+#else
+	printf("Board: %sRDB\n", cpu->name);
+#endif
+	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
+	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+
+	sw = CPLD_READ(flash_ctl_status);
+	sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+
+	printf("vBank: %d\n", sw);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 2;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash */
+		disable_tlb(flash_esel);
+	}
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
+
+	printf("SERDES Reference : 0x%X\n", srds_s1);
+
+	/* select SGMII*/
+	if (srds_s1 == 0x86)
+		CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+					 MISC_CTL_SG_SEL);
+
+	/* select SGMII and Aurora*/
+	if (srds_s1 == 0x8E)
+		CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+					 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
+
+#if defined(CONFIG_TARGET_T1040D4RDB)
+	if (hwconfig("qe-tdm")) {
+		CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
+			   MISC_MUX_QE_TDM);
+		printf("QECSR : 0x%02x, mux to qe-tdm\n",
+		       CPLD_READ(sfp_ctl_status));
+	}
+	/* Mask all CPLD interrupt sources, except QSGMII interrupts */
+	if (CPLD_READ(sw_ver) < 0x03) {
+		debug("CPLD SW version 0x%02x doesn't support int_mask\n",
+		      CPLD_READ(sw_ver));
+	} else {
+		CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
+			   ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
+	}
+#endif
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+	fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
+	fdt_fixup_fman_ethernet(blob);
+#endif
+#endif
+
+	if (hwconfig("qe-tdm"))
+		fdt_del_diu(blob);
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/t104xrdb/t104xrdb.h b/roms/u-boot/board/freescale/t104xrdb/t104xrdb.h
new file mode 100644
index 000000000..678724c7e
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/t104xrdb.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __T104x_RDB_H__
+#define __T104x_RDB_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, struct bd_info *bd);
+
+#endif
diff --git a/roms/u-boot/board/freescale/t104xrdb/tlb.c b/roms/u-boot/board/freescale/t104xrdb/tlb.c
new file mode 100644
index 000000000..9dcba7933
--- /dev/null
+++ b/roms/u-boot/board/freescale/t104xrdb/tlb.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
+	!defined(CONFIG_NXP_ESBC)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256K, 1),
+
+#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_SPL_BUILD)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
+	 * the physical address of the SRAM is at 0xbffc0000,
+	 * and virtual address is 0xfffc0000
+	 */
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
+		      CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 5, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 7, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 12, BOOKE_PAGESZ_1G, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 13, BOOKE_PAGESZ_1G, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/freescale/t208xqds/Kconfig b/roms/u-boot/board/freescale/t208xqds/Kconfig
new file mode 100644
index 000000000..f65d8eed5
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_T2080QDS
+
+config SYS_BOARD
+	default "t208xqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "T208xQDS"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/t208xqds/MAINTAINERS b/roms/u-boot/board/freescale/t208xqds/MAINTAINERS
new file mode 100644
index 000000000..790b009c5
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/MAINTAINERS
@@ -0,0 +1,20 @@
+T208XQDS BOARD
+M:	Shengzhou Liu <Shengzhou.Liu@nxp.com>
+S:	Maintained
+F:	board/freescale/t208xqds/
+F:	include/configs/T208xQDS.h
+F:	configs/T2080QDS_defconfig
+F:	configs/T2080QDS_NAND_defconfig
+F:	configs/T2080QDS_SDCARD_defconfig
+F:	configs/T2080QDS_SPIFLASH_defconfig
+F:	configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+F:	configs/T2081QDS_defconfig
+F:	configs/T2081QDS_NAND_defconfig
+F:	configs/T2081QDS_SDCARD_defconfig
+F:	configs/T2081QDS_SPIFLASH_defconfig
+F:	configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+
+T2080QDS_SECURE_BOOT BOARD
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
+S:	Maintained
+F:	configs/T2080QDS_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/t208xqds/Makefile b/roms/u-boot/board/freescale/t208xqds/Makefile
new file mode 100644
index 000000000..55b1e7390
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_PCI)      += pci.o
+endif
+
+obj-y   += ddr.o
+obj-y   += law.o
+obj-y   += tlb.o
diff --git a/roms/u-boot/board/freescale/t208xqds/README b/roms/u-boot/board/freescale/t208xqds/README
new file mode 100755
index 000000000..d690857f2
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/README
@@ -0,0 +1,293 @@
+The T2080QDS is a high-performance computing evaluation, development and
+test platform supporting the T2080 QorIQ Power Architecture processor.
+
+T2080 SoC Overview
+------------------
+The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
+Architecture processor cores with high-performance datapath acceleration
+logic and network and peripheral bus interfaces required for networking,
+telecom/datacom, wireless infrastructure, and mil/aerospace applications.
+
+T2080 includes the following functions and features:
+ - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
+ - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
+ - Hierarchical interconnect fabric
+ - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ - 16 SerDes lanes up to 10.3125 GHz
+ - 8 Ethernet interfaces, supporting combinations of the following:
+   - Up to four 10 Gbps Ethernet MACs
+   - Up to eight 1 Gbps Ethernet MACs
+   - Up to four 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+   - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
+ - Additional peripheral interfaces
+   - Two serial ATA (SATA 2.0) controllers
+   - Two high-speed USB 2.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
+   - Enhanced serial peripheral interface (eSPI)
+   - Four I2C controllers
+   - Four 2-pin UARTs or two 4-pin UARTs
+   - Integrated Flash Controller supporting NAND and NOR flash
+ - Three eight-channel DMA engines
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ Platform's Trust Architecture 2.0
+
+Differences between T2080 and T2081
+-----------------------------------
+  Feature		T2080	 T2081
+  1G Ethernet numbers:  8	 6
+  10G Ethernet numbers: 4	 2
+  SerDes lanes:		16	 8
+  Serial RapidIO,RMan:  2	 no
+  SATA Controller:	2	 no
+  Aurora:		yes	 no
+  SoC Package:		896-pins 780-pins
+
+
+T2080QDS feature overview
+-------------------------
+Processor:
+ - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
+Memory:
+ - Single memory controller capable of supporting DDR3 and DDR3-LV devices
+ - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
+Ethernet interfaces:
+ - Two 1Gbps RGMII on-board ports
+ - Four 10Gbps XFI on-board cages
+ - 1Gbps/2.5Gbps SGMII Riser card
+ - 10Gbps XAUI Riser card
+Accelerator:
+ - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
+SerDes:
+ - 16 lanes up to 10.3125GHz
+ - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
+IFC:
+ - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
+eSPI:
+ - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
+USB:
+ - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
+PCIE:
+ - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+SATA:
+ - Two SATA 2.0 ports on-board
+SRIO:
+ - Two Serial RapidIO 2.0 ports up to 5 GHz
+eSDHC:
+ - Supports SD/SDHC/SDXC/eMMC Card
+I2C:
+ - Four I2C controllers.
+UART:
+ - Dual 4-pins UART serial ports
+System Logic:
+ - QIXIS-II FPGA system controll
+Debug Features:
+ - Support Legacy, COP/JTAG, Aurora, Event and EVT
+XFI:
+ - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
+ a on-board SFP+ cages, which to house optical module (fiber cable) or
+ direct attach cable(copper), the copper cable is used to emulate
+ 10GBASE-KR scenario.
+ So, for XFI usage, there are two scenarios, one will use fiber cable,
+ another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
+ introduced to indicate a XFI port will use copper cable, and U-Boot
+ will fixup the dtb accordingly.
+ It's used as: fsl_10gkr_copper:<10g_mac_name>
+ The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
+ do not have to be coexist in hwconfig. If a MAC is listed in the env
+ "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
+ will be used by default.
+ for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
+ hwconfig, then both four XFI ports will use copper cable.
+ set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
+ XFI ports will use copper cable, the other two XFI ports will use fiber
+ cable.
+1000BASE-KX(1G-KX):
+ - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
+ runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
+ in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
+ Register 1 (PCCR1), and U-Boot fixup the dtb for kernel to do proper
+ initialization.
+ Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
+ 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
+ MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
+ stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
+ For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
+ hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
+
+System Memory map
+----------------
+
+Start Address  End Address      Description			Size
+0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - CPLD			4KB
+0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash		64KB
+0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR				16MB
+0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space		64KB
+0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space		64KB
+0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space		64KB
+0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space		64KB
+0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal	32MB
+0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal	32MB
+0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash			128MB
+0xF_0000_0000  0xF_003F_FFFF    DCSR				4MB
+0xC_4000_0000  0xC_4FFF_FFFF    PCI Express 4 Mem Space		256MB
+0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 3 Mem Space		256MB
+0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 2 Mem Space		256MB
+0xC_0000_0000  0xC_1FFF_FFFF    PCI Express 1 Mem Space		512MB
+0x0_0000_0000  0x0_ffff_ffff    DDR				4GB
+
+
+128M NOR Flash memory Map
+-------------------------
+Start Address   End Address	Definition			Max size
+0xEFF40000	0xEFFFFFFF	U-Boot (current bank)		768KB
+0xEFF20000	0xEFF3FFFF	U-Boot env (current bank)	128KB
+0xEFF00000	0xEFF1FFFF	FMAN Ucode (current bank)	128KB
+0xED300000	0xEFEFFFFF	rootfs (alt bank)		44MB
+0xEC800000	0xEC8FFFFF	Hardware device tree (alt bank)	1MB
+0xEC020000	0xEC7FFFFF	Linux.uImage (alt bank)		7MB + 875KB
+0xEC000000	0xEC01FFFF	RCW (alt bank)			128KB
+0xEBF40000	0xEBFFFFFF	U-Boot (alt bank)		768KB
+0xEBF20000	0xEBF3FFFF	U-Boot env (alt bank)		128KB
+0xEBF00000	0xEBF1FFFF	FMAN ucode (alt bank)		128KB
+0xE9300000	0xEBEFFFFF	rootfs (current bank)		44MB
+0xE8800000	0xE88FFFFF	Hardware device tree (cur bank)	1MB
+0xE8020000	0xE86FFFFF	Linux.uImage (current bank)	7MB + 875KB
+0xE8000000	0xE801FFFF	RCW (current bank)		128KB
+
+
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+   a. build NOR boot image
+	$  make T2080QDS_config
+	$  make
+   b. program u-boot.bin image to NOR flash
+	=> tftp 1000000 u-boot.bin
+	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+	set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
+
+   Switching between default bank0 and alternate bank4 on NOR flash
+   To change boot source to vbank4:
+	by software:   run command 'qixis_reset altbank' in U-Boot.
+	by DIP-switch: set SW6[1:4] = '0100'
+
+   To change boot source to vbank0:
+	by software:   run command 'qixis_reset' in U-Boot.
+	by DIP-Switch: set SW6[1:4] = '0000'
+
+2. NAND Boot:
+   a. build PBL image for NAND boot
+	$ make T2080QDS_NAND_config
+	$ make
+   b. program u-boot-with-spl-pbl.bin to NAND flash
+	=> tftp 1000000 u-boot-with-spl-pbl.bin
+	=> nand erase 0 $filesize
+	=> nand write 1000000 0 $filesize
+	set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
+
+3. SPI Boot:
+   a. build PBL image for SPI boot
+	$ make T2080QDS_SPIFLASH_config
+	$ make
+   b. program u-boot-with-spl-pbl.bin to SPI flash
+	=> tftp 1000000 u-boot-with-spl-pbl.bin
+	=> sf probe 0
+	=> sf erase 0 f0000
+	=> sf write 1000000 0 $filesize
+	set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+   a. build PBL image for SD boot
+	$ make T2080QDS_SDCARD_config
+	$ make
+   b. program u-boot-with-spl-pbl.bin to SD/MMC card
+	=> tftp 1000000 u-boot-with-spl-pbl.bin
+	=> mmc write 1000000 8 0x800
+	=> tftp 1000000 fsl_fman_ucode_T2080_xx.bin
+	=> mmc write 1000000 0x820 80
+	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to U-Boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area		   | Address			|
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB)		|
+-------------------------------------------------
+|GD, BD		   | 0xFFFC8000 (4KB)		|
+-------------------------------------------------
+|ENV		   | 0xFFFC9000 (8KB)		|
+-------------------------------------------------
+|HEAP		   | 0xFFFCB000 (50KB)		|
+-------------------------------------------------
+|STACK		   | 0xFFFD8000 (22KB)		|
+-------------------------------------------------
+|U-Boot SPL	   | 0xFFFD8000 (160KB)		|
+-------------------------------------------------
+
+NAND Flash memory Map on T2080QDS
+--------------------------------------------------------------
+Start		End		Definition	Size
+0x000000	0x0FFFFF	U-Boot img	1MB  (2 blocks)
+0x100000	0x17FFFF	U-Boot env	512KB (1 block)
+0x180000	0x1FFFFF	FMAN ucode	512KB (1 block)
+
+
+Micro SD Card memory Map on T2080QDS
+----------------------------------------------------
+Block		#blocks		Definition	Size
+0x008		2048		U-Boot img	1MB
+0x800		0016		U-Boot env	8KB
+0x820		0128		FMAN ucode	64KB
+
+
+SPI Flash memory Map on T2080QDS
+----------------------------------------------------
+Start		End		Definition	Size
+0x000000	0x0FFFFF	U-Boot img	1MB
+0x100000	0x101FFF	U-Boot env	8KB
+0x110000	0x11FFFF	FMAN ucode	64KB
+
+
+How to update the ucode of Freescale FMAN
+-----------------------------------------
+=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin
+=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
+
+
+For more details, please refer to T2080QDS User Guide and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for t2080qds for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/roms/u-boot/board/freescale/t208xqds/ddr.c b/roms/u-boot/board/freescale/t208xqds/ddr.c
new file mode 100644
index 000000000..56471b398
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/ddr.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	/*
+	 * we use identical timing for all slots. If needed, change the code
+	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+	 */
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[0];
+	else
+		pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found");
+		printf("for data rate %lu MT/s\n", ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+		"wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x64;
+}
+
+int dram_init(void)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+	puts("Initializing....using SPD\n");
+	dram_size = fsl_ddr_sdram();
+#else
+	/* DDR has been initialised by first stage boot loader */
+	dram_size =  fsl_ddr_sdram_size();
+#endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/t208xqds/ddr.h b/roms/u-boot/board/freescale/t208xqds/ddr.h
new file mode 100644
index 000000000..9dd39813b
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/ddr.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl | wrlvl | wrlvl |
+	 * ranks| mhz| GB  |adjst| start | ctl2  | ctl3  |
+	 */
+	{2,  1200,  0, 10,  7,  0x0708090a,  0x0b0c0d09},
+	{2,  1400,  0, 10,  7,  0x08090a0c,  0x0d0e0f0a},
+	{2,  1700,  0, 10,  8,  0x090a0b0c,  0x0e10110c},
+	{2,  1900,  0, 10,  8,  0x090b0c0f,  0x1012130d},
+	{2,  2140,  0, 10,  8,  0x090b0c0f,  0x1012130d},
+	{1,  1200,  0, 10,  7,  0x0808090a,  0x0b0c0c0a},
+	{1,  1500,  0, 10,  6,  0x07070809,  0x0a0b0b09},
+	{1,  1600,  0, 10,  8,  0x090b0b0d,  0x0d0e0f0b},
+	{1,  1700,  0,  8,  8,  0x080a0a0c,  0x0c0d0e0a},
+	{1,  1900,  0, 10,  8,  0x090a0c0d,  0x0e0f110c},
+	{1,  2140,  0,  8,  8,  0x090a0b0d,  0x0e0f110b},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 */
+	/* TODO: need tuning these parameters if RDIMM is used */
+	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
+	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+};
+#endif
diff --git a/roms/u-boot/board/freescale/t208xqds/eth_t208xqds.c b/roms/u-boot/board/freescale/t208xqds/eth_t208xqds.c
new file mode 100644
index 000000000..705387af3
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/eth_t208xqds.c
@@ -0,0 +1,723 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fdt_support.h>
+#include <log.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include <hwconfig.h>
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "t208xqds_qixis.h"
+#include <linux/libfdt.h>
+
+#define EMI_NONE	0xFFFFFFFF
+#define EMI1_RGMII1	0
+#define EMI1_RGMII2     1
+#define EMI1_SLOT1	2
+#if defined(CONFIG_TARGET_T2080QDS)
+#define EMI1_SLOT2	6
+#define EMI1_SLOT3	3
+#define EMI1_SLOT4	4
+#define EMI1_SLOT5	5
+#define EMI2            7
+#endif
+
+#define PCCR1_SGMIIA_KX_MASK		0x00008000
+#define PCCR1_SGMIIB_KX_MASK		0x00004000
+#define PCCR1_SGMIIC_KX_MASK		0x00002000
+#define PCCR1_SGMIID_KX_MASK		0x00001000
+#define PCCR1_SGMIIE_KX_MASK		0x00000800
+#define PCCR1_SGMIIF_KX_MASK		0x00000400
+#define PCCR1_SGMIIG_KX_MASK		0x00000200
+#define PCCR1_SGMIIH_KX_MASK		0x00000100
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+#if defined(CONFIG_TARGET_T2080QDS)
+	"T2080QDS_MDIO_RGMII1",
+	"T2080QDS_MDIO_RGMII2",
+	"T2080QDS_MDIO_SLOT1",
+	"T2080QDS_MDIO_SLOT3",
+	"T2080QDS_MDIO_SLOT4",
+	"T2080QDS_MDIO_SLOT5",
+	"T2080QDS_MDIO_SLOT2",
+	"T2080QDS_MDIO_10GC",
+#endif
+};
+
+/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
+#if defined(CONFIG_TARGET_T2080QDS)
+static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
+#endif
+
+static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+	struct mii_dev *bus;
+	const char *name = t208xqds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+struct t208xqds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+static void t208xqds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+	if (muxval < 8) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+				int regnum)
+{
+	struct t208xqds_mdio *priv = bus->priv;
+
+	t208xqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				int regnum, u16 value)
+{
+	struct t208xqds_mdio *priv = bus->priv;
+
+	t208xqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t208xqds_mdio_reset(struct mii_dev *bus)
+{
+	struct t208xqds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int t208xqds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct t208xqds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate t208xqds MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate t208xqds private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = t208xqds_mdio_read;
+	bus->write = t208xqds_mdio_write;
+	bus->reset = t208xqds_mdio_reset;
+	strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+	return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+				enum fm_port port, int offset)
+{
+	int phy;
+	char alias[20];
+	char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
+	char buf[32] = "serdes-1,";
+	struct fixed_link f_link;
+	int media_type = 0;
+	const char *phyconn;
+	int off;
+
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_TARGET_T2080QDS
+	serdes_corenet_t *srds_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
+#endif
+	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+		phy = fm_info_get_phy_address(port);
+		switch (port) {
+#if defined(CONFIG_TARGET_T2080QDS)
+		case FM1_DTSEC1:
+			if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
+				media_type = 1;
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "phy_1gkx1");
+				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
+				sprintf(buf, "%s%s%s", buf, "lane-c,",
+						(char *)lane_mode[0]);
+				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+					 PCCR1_SGMIIH_KX_MASK);
+				break;
+			}
+		case FM1_DTSEC2:
+			if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
+				media_type = 1;
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "phy_1gkx2");
+				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
+				sprintf(buf, "%s%s%s", buf, "lane-d,",
+						(char *)lane_mode[0]);
+				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+					 PCCR1_SGMIIG_KX_MASK);
+				break;
+			}
+		case FM1_DTSEC9:
+			if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
+				media_type = 1;
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "phy_1gkx9");
+				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
+				sprintf(buf, "%s%s%s", buf, "lane-a,",
+						(char *)lane_mode[0]);
+				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+					 PCCR1_SGMIIE_KX_MASK);
+				break;
+			}
+		case FM1_DTSEC10:
+			if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
+				media_type = 1;
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "phy_1gkx10");
+				fdt_status_okay_by_alias(fdt,
+							 "1gkx_pcs_mdio10");
+				sprintf(buf, "%s%s%s", buf, "lane-b,",
+						(char *)lane_mode[0]);
+				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+					 PCCR1_SGMIIF_KX_MASK);
+				break;
+			}
+			if (mdio_mux[port] == EMI1_SLOT2) {
+				sprintf(alias, "phy_sgmii_s2_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+			} else if (mdio_mux[port] == EMI1_SLOT3) {
+				sprintf(alias, "phy_sgmii_s3_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+			}
+			break;
+		case FM1_DTSEC5:
+			if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
+				media_type = 1;
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "phy_1gkx5");
+				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
+				sprintf(buf, "%s%s%s", buf, "lane-g,",
+						(char *)lane_mode[0]);
+				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+					 PCCR1_SGMIIC_KX_MASK);
+				break;
+			}
+		case FM1_DTSEC6:
+			if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
+				media_type = 1;
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "phy_1gkx6");
+				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
+				sprintf(buf, "%s%s%s", buf, "lane-h,",
+						(char *)lane_mode[0]);
+				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+					 PCCR1_SGMIID_KX_MASK);
+				break;
+			}
+			if (mdio_mux[port] == EMI1_SLOT1) {
+				sprintf(alias, "phy_sgmii_s1_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot1");
+			} else if (mdio_mux[port] == EMI1_SLOT2) {
+				sprintf(alias, "phy_sgmii_s2_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+			}
+			break;
+#endif
+		default:
+			break;
+		}
+		if (media_type) {
+			/* set property for 1000BASE-KX in dtb */
+			off = fdt_node_offset_by_compat_reg(fdt,
+					"fsl,fman-memac-mdio", addr + 0x1000);
+			fdt_setprop_string(fdt, off, "lane-instance", buf);
+		}
+
+	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+		switch (srds_s1) {
+		case 0x66: /* XFI interface */
+		case 0x6b:
+		case 0x6c:
+		case 0x6d:
+		case 0x71:
+			/*
+			* if the 10G is XFI, check hwconfig to see what is the
+			* media type, there are two types, fiber or copper,
+			* fix the dtb accordingly.
+			*/
+			switch (port) {
+			case FM1_10GEC1:
+			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
+				/* it's MAC9 */
+				media_type = 1;
+				fdt_set_phy_handle(fdt, compat, addr,
+						"phy_xfi9");
+				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
+				sprintf(buf, "%s%s%s", buf, "lane-a,",
+						(char *)lane_mode[1]);
+			}
+				break;
+			case FM1_10GEC2:
+			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
+				/* it's MAC10 */
+				media_type = 1;
+				fdt_set_phy_handle(fdt, compat, addr,
+						"phy_xfi10");
+				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
+				sprintf(buf, "%s%s%s", buf, "lane-b,",
+						(char *)lane_mode[1]);
+			}
+				break;
+			case FM1_10GEC3:
+			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
+				/* it's MAC1 */
+				media_type = 1;
+				fdt_set_phy_handle(fdt, compat, addr,
+						"phy_xfi1");
+				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
+				sprintf(buf, "%s%s%s", buf, "lane-c,",
+						(char *)lane_mode[1]);
+			}
+				break;
+			case FM1_10GEC4:
+			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
+				/* it's MAC2 */
+				media_type = 1;
+				fdt_set_phy_handle(fdt, compat, addr,
+						"phy_xfi2");
+				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
+				sprintf(buf, "%s%s%s", buf, "lane-d,",
+						(char *)lane_mode[1]);
+			}
+				break;
+			default:
+				return;
+			}
+
+			if (!media_type) {
+				phyconn = fdt_getprop(fdt, offset,
+						      "phy-connection-type",
+						      NULL);
+				if (is_backplane_mode(phyconn)) {
+					/* Backplane KR mode: skip fixups */
+					printf("Interface %d in backplane KR mode\n",
+					       port);
+				} else {
+					/* fixed-link for XFI fiber cable */
+					f_link.phy_id = port;
+					f_link.duplex = 1;
+					f_link.link_speed = 10000;
+					f_link.pause = 0;
+					f_link.asym_pause = 0;
+					fdt_delprop(fdt, offset, "phy-handle");
+					fdt_setprop(fdt, offset, "fixed-link",
+						    &f_link, sizeof(f_link));
+				}
+			} else {
+				/* set property for copper cable */
+				off = fdt_node_offset_by_compat_reg(fdt,
+					"fsl,fman-memac-mdio", addr + 0x1000);
+				fdt_setprop_string(fdt, off,
+					"lane-instance", buf);
+			}
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	return;
+}
+
+/*
+ * This function reads RCW to check if Serdes1{A:H} is configured
+ * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	switch (srds_s1) {
+#if defined(CONFIG_TARGET_T2080QDS)
+	case 0x51:
+	case 0x5f:
+	case 0x65:
+	case 0x6b:
+	case 0x71:
+		lane_to_slot[5] = 2;
+		lane_to_slot[6] = 2;
+		lane_to_slot[7] = 2;
+		break;
+	case 0xa6:
+	case 0x8e:
+	case 0x8f:
+	case 0x82:
+	case 0x83:
+	case 0xd3:
+	case 0xd9:
+	case 0xcb:
+		lane_to_slot[6] = 2;
+		lane_to_slot[7] = 2;
+		break;
+	case 0xda:
+		lane_to_slot[4] = 3;
+		lane_to_slot[5] = 3;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+	int i, idx, lane, slot, interface;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	initialize_lane_to_slot();
+
+	/* Initialize the mdio_mux array so we can recognize empty elements */
+	for (i = 0; i < NUM_FM_PORTS; i++)
+		mdio_mux[i] = EMI_NONE;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	/* Register the muxing front-ends to the MDIO buses */
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+#if defined(CONFIG_TARGET_T2080QDS)
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+#endif
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+	t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+	/* Set the two on-board RGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+	if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+			FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
+		fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+	else
+		fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
+
+	switch (srds_s1) {
+	case 0x1b:
+	case 0x1c:
+	case 0x95:
+	case 0xa2:
+	case 0x94:
+		/* T2080QDS: SGMII in Slot3;  T2081QDS: SGMII in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		/* T2080QDS: SGMII in Slot2;  T2081QDS: SGMII in Slot1 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	case 0x50:
+	case 0x51:
+	case 0x5e:
+	case 0x5f:
+	case 0x64:
+	case 0x65:
+		/* T2080QDS: XAUI/HiGig in Slot3;  T2081QDS: in Slot2 */
+		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+		/* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	case 0x66:
+	case 0x67:
+		/*
+		 * XFI does not need a PHY to work, but to avoid U-Boot use
+		 * default PHY address which is zero to a MAC when it found
+		 * a MAC has no PHY address, we give a PHY address to XFI
+		 * MAC, and should not use a real XAUI PHY address, since
+		 * MDIO can access it successfully, and then MDIO thinks
+		 * the XAUI card is used for the XFI MAC, which will cause
+		 * error.
+		 */
+		fm_info_set_phy_address(FM1_10GEC1, 4);
+		fm_info_set_phy_address(FM1_10GEC2, 5);
+		fm_info_set_phy_address(FM1_10GEC3, 6);
+		fm_info_set_phy_address(FM1_10GEC4, 7);
+		break;
+	case 0x6a:
+	case 0x6b:
+		fm_info_set_phy_address(FM1_10GEC1, 4);
+		fm_info_set_phy_address(FM1_10GEC2, 5);
+		fm_info_set_phy_address(FM1_10GEC3, 6);
+		fm_info_set_phy_address(FM1_10GEC4, 7);
+		/* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+	case 0x6c:
+	case 0x6d:
+		fm_info_set_phy_address(FM1_10GEC1, 4);
+		fm_info_set_phy_address(FM1_10GEC2, 5);
+		/* T2080QDS: SGMII in Slot3;  T2081QDS: in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	case 0x70:
+	case 0x71:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		/* SGMII in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+	case 0xa6:
+	case 0x8e:
+	case 0x8f:
+	case 0x82:
+	case 0x83:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		/* SGMII in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+	case 0xa4:
+	case 0x96:
+	case 0x8a:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+#if defined(CONFIG_TARGET_T2080QDS)
+	case 0xd9:
+	case 0xd3:
+	case 0xcb:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		/* SGMII in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+#endif
+	case 0xf2:
+		/* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	default:
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		idx = i - FM1_DTSEC1;
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(FSL_SRDS_1,
+					SGMII_FM1_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+			      idx + 1, slot);
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
+
+			switch (slot) {
+			case 1:
+				mdio_mux[i] = EMI1_SLOT1;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 2:
+				mdio_mux[i] = EMI1_SLOT2;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 3:
+				mdio_mux[i] = EMI1_SLOT3;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			}
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+			if (i == FM1_DTSEC3)
+				mdio_mux[i] = EMI1_RGMII1;
+			else if (i == FM1_DTSEC4 || FM1_DTSEC10)
+				mdio_mux[i] = EMI1_RGMII2;
+			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		idx = i - FM1_10GEC1;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			if (srds_s1 == 0x51) {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						XAUI_FM1_MAC9 + idx);
+			} else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						HIGIG_FM1_MAC9 + idx);
+			} else {
+				if (i == FM1_10GEC1 || i == FM1_10GEC2)
+					lane = serdes_get_first_lane(FSL_SRDS_1,
+						XFI_FM1_MAC9 + idx);
+				else
+					lane = serdes_get_first_lane(FSL_SRDS_1,
+						XFI_FM1_MAC1 + idx);
+			}
+
+			if (lane < 0)
+				break;
+			mdio_mux[i] = EMI2;
+			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+
+			if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
+			    (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
+			    (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
+			    (srds_s1 == 0x71)) {
+				/* As XFI is in cage intead of a slot, so
+				 * ensure doesn't disable the corresponding port
+				 */
+				break;
+			}
+
+			slot = lane_to_slot[lane];
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
+			break;
+		default:
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/freescale/t208xqds/law.c b/roms/u-boot/board/freescale/t208xqds/law.c
new file mode 100644
index 000000000..40fdcf61c
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/law.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/t208xqds/pci.c b/roms/u-boot/board/freescale/t208xqds/pci.c
new file mode 100644
index 000000000..a03b11ccb
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/pci.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007-2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+#if !defined(CONFIG_DM_PCI)
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, struct bd_info *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/t208xqds/spl.c b/roms/u-boot/board/freescale/t208xqds/spl.c
new file mode 100644
index 000000000..e934a3ca6
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/spl.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <console.h>
+#include <env_internal.h>
+#include <init.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include <asm/global_data.h>
+#include "../common/qixis.h"
+#include "t208xqds_qixis.h"
+#include "../common/spl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, sys_clk, ccb_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+	/* Update GD pointer */
+	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	sys_clk = get_board_sys_clk();
+	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+	ccb_clk = sys_clk * plat_ratio / 2;
+
+	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+		     ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	puts("\nNAND boot...\n");
+#endif
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	struct bd_info *bd;
+
+	bd = (struct bd_info *)(gd + sizeof(gd_t));
+	memset(bd, 0, sizeof(struct bd_info));
+	gd->bd = bd;
+
+	arch_cpu_init();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)SPL_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)SPL_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+	fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			       (uchar *)SPL_ENV_ADDR);
+#endif
+
+	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
+	gd->env_valid = ENV_VALID;
+
+	i2c_init_all();
+
+	dram_init();
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	fsl_spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/roms/u-boot/board/freescale/t208xqds/t2080_nand_rcw.cfg b/roms/u-boot/board/freescale/t208xqds/t2080_nand_rcw.cfg
new file mode 100644
index 000000000..52a1652a2
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/t2080_nand_rcw.cfg
@@ -0,0 +1,16 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
+#12100017 15000000 00000000 00000000
+#66150002 00008400 e8104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
+0c070012 0e000000 00000000 00000000
+66150002 00000000 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/roms/u-boot/board/freescale/t208xqds/t2080_sd_rcw.cfg b/roms/u-boot/board/freescale/t208xqds/t2080_sd_rcw.cfg
new file mode 100644
index 000000000..73f53faa2
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/t2080_sd_rcw.cfg
@@ -0,0 +1,16 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
+#12100017 15000000 00000000 00000000
+#66150002 00008400 e8104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
+0c070012 0e000000 00000000 00000000
+66150002 00000000 68104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/roms/u-boot/board/freescale/t208xqds/t2080_spi_rcw.cfg b/roms/u-boot/board/freescale/t208xqds/t2080_spi_rcw.cfg
new file mode 100644
index 000000000..8474c8ef7
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/t2080_spi_rcw.cfg
@@ -0,0 +1,16 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
+#12100017 15000000 00000000 00000000
+#66150002 00008400 e8104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
+0c070012 0e000000 00000000 00000000
+66150002 00000000 58104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/roms/u-boot/board/freescale/t208xqds/t2081_nand_rcw.cfg b/roms/u-boot/board/freescale/t208xqds/t2081_nand_rcw.cfg
new file mode 100644
index 000000000..a2d5ecf4a
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/t2081_nand_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/roms/u-boot/board/freescale/t208xqds/t2081_sd_rcw.cfg b/roms/u-boot/board/freescale/t208xqds/t2081_sd_rcw.cfg
new file mode 100644
index 000000000..daced6796
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/t2081_sd_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 68104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/roms/u-boot/board/freescale/t208xqds/t2081_spi_rcw.cfg b/roms/u-boot/board/freescale/t208xqds/t2081_spi_rcw.cfg
new file mode 100644
index 000000000..79ba1f1ab
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/t2081_spi_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 58104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/roms/u-boot/board/freescale/t208xqds/t208x_pbi.cfg b/roms/u-boot/board/freescale/t208xqds/t208x_pbi.cfg
new file mode 100644
index 000000000..43be8a864
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/t208x_pbi.cfg
@@ -0,0 +1,40 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+091380c0 00100000
diff --git a/roms/u-boot/board/freescale/t208xqds/t208xqds.c b/roms/u-boot/board/freescale/t208xqds/t208xqds.c
new file mode 100644
index 000000000..fd3217f24
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/t208xqds.c
@@ -0,0 +1,449 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "../common/vid.h"
+#include "t208xqds.h"
+#include "t208xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+	struct cpu_type *cpu = gd->arch.cpu;
+	static const char *freq[4] = {
+		"100.00MHZ(from 8T49N222A)", "125.00MHz",
+		"156.25MHZ", "100.00MHz"
+	};
+
+	printf("Board: %sQDS, ", cpu->name);
+	sw = QIXIS_READ(arch);
+	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
+	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+#ifdef CONFIG_SDCARD
+	puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+	puts("SPI\n");
+#else
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank%d\n", sw);
+	else if (sw == 0x8)
+		puts("Promjet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+	printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
+	       qixis_read_tag(buf), (int)qixis_read_minor());
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+
+	puts("SERDES Reference Clocks:\n");
+	sw = QIXIS_READ(brdcfg[2]);
+	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
+	       freq[(sw >> 4) & 0x3]);
+	printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
+	       freq[sw & 0x3]);
+
+	return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
+{
+	int ret;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+	return select_i2c_ch_pca9547(channel, 0);
+}
+
+int brd_mux_lane_to_slot(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_prtcl_s1;
+
+	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+#if defined(CONFIG_TARGET_T2080QDS)
+	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+#endif
+
+	switch (srds_prtcl_s1) {
+	case 0:
+		/* SerDes1 is not enabled */
+		break;
+#if defined(CONFIG_TARGET_T2080QDS)
+	case 0x1b:
+	case 0x1c:
+	case 0xa2:
+		/* SD1(A:D) => SLOT3 SGMII
+		 * SD1(G:H) => SLOT1 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x1a);
+		break;
+	case 0x94:
+	case 0x95:
+		/* SD1(A:B) => SLOT3 SGMII@1.25bps
+		 * SD1(C:D) => SFP Module, SGMII@3.125bps
+		 * SD1(E:H) => SLOT1 SGMII@1.25bps
+		 */
+	case 0x96:
+		/* SD1(A:B) => SLOT3 SGMII@1.25bps
+		 * SD1(C)   => SFP Module, SGMII@3.125bps
+		 * SD1(D)   => SFP Module, SGMII@1.25bps
+		 * SD1(E:H) => SLOT1 PCIe4 x4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x3a);
+		break;
+	case 0x50:
+	case 0x51:
+		/* SD1(A:D) => SLOT3 XAUI
+		 * SD1(E)   => SLOT1 PCIe4
+		 * SD1(F:H) => SLOT2 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x15);
+		break;
+	case 0x66:
+	case 0x67:
+		/* SD1(A:D) => XFI cage
+		 * SD1(E:H) => SLOT1 PCIe4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xfe);
+		break;
+	case 0x6a:
+	case 0x6b:
+		/* SD1(A:D) => XFI cage
+		 * SD1(E)   => SLOT1 PCIe4
+		 * SD1(F:H) => SLOT2 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xf1);
+		break;
+	case 0x6c:
+	case 0x6d:
+		/* SD1(A:B) => XFI cage
+		 * SD1(C:D) => SLOT3 SGMII
+		 * SD1(E:H) => SLOT1 PCIe4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xda);
+		break;
+	case 0x6e:
+		/* SD1(A:B) => SFP Module, XFI
+		 * SD1(C:D) => SLOT3 SGMII
+		 * SD1(E:F) => SLOT1 PCIe4 x2
+		 * SD1(G:H) => SLOT2 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xd9);
+		break;
+	case 0xda:
+		/* SD1(A:H) => SLOT3 PCIe3 x8
+		 */
+		 QIXIS_WRITE(brdcfg[12], 0x0);
+		 break;
+	case 0xc8:
+		/* SD1(A)   => SLOT3 PCIe3 x1
+		 * SD1(B)   => SFP Module, SGMII@1.25bps
+		 * SD1(C:D) => SFP Module, SGMII@3.125bps
+		 * SD1(E:F) => SLOT1 PCIe4 x2
+		 * SD1(G:H) => SLOT2 SGMII
+		 */
+		 QIXIS_WRITE(brdcfg[12], 0x79);
+		 break;
+	case 0xab:
+		/* SD1(A:D) => SLOT3 PCIe3 x4
+		 * SD1(E:H) => SLOT1 PCIe4 x4
+		 */
+		 QIXIS_WRITE(brdcfg[12], 0x1a);
+		 break;
+#endif
+	default:
+		printf("WARNING: unsupported for SerDes1 Protocol %d\n",
+		       srds_prtcl_s1);
+		return -1;
+	}
+
+#ifdef CONFIG_TARGET_T2080QDS
+	switch (srds_prtcl_s2) {
+	case 0:
+		/* SerDes2 is not enabled */
+		break;
+	case 0x01:
+	case 0x02:
+		/* SD2(A:H) => SLOT4 PCIe1 */
+		QIXIS_WRITE(brdcfg[13], 0x10);
+		break;
+	case 0x15:
+	case 0x16:
+		/*
+		 * SD2(A:D) => SLOT4 PCIe1
+		 * SD2(E:F) => SLOT5 PCIe2
+		 * SD2(G:H) => SATA1,SATA2
+		 */
+		QIXIS_WRITE(brdcfg[13], 0xb0);
+		break;
+	case 0x18:
+		/*
+		 * SD2(A:D) => SLOT4 PCIe1
+		 * SD2(E:F) => SLOT5 Aurora
+		 * SD2(G:H) => SATA1,SATA2
+		 */
+		QIXIS_WRITE(brdcfg[13], 0x78);
+		break;
+	case 0x1f:
+		/*
+		 * SD2(A:D) => SLOT4 PCIe1
+		 * SD2(E:H) => SLOT5 PCIe2
+		 */
+		QIXIS_WRITE(brdcfg[13], 0xa0);
+		break;
+	case 0x29:
+	case 0x2d:
+	case 0x2e:
+		/*
+		 * SD2(A:D) => SLOT4 SRIO2
+		 * SD2(E:H) => SLOT5 SRIO1
+		 */
+		QIXIS_WRITE(brdcfg[13], 0xa0);
+		break;
+	case 0x36:
+		/*
+		 * SD2(A:D) => SLOT4 SRIO2
+		 * SD2(E:F) => Aurora
+		 * SD2(G:H) => SATA1,SATA2
+		 */
+		QIXIS_WRITE(brdcfg[13], 0x78);
+		break;
+	default:
+		printf("WARNING: unsupported for SerDes2 Protocol %d\n",
+		       srds_prtcl_s2);
+		return -1;
+	}
+#endif
+	return 0;
+}
+
+static void esdhc_adapter_card_ident(void)
+{
+	u8 card_id, value;
+
+	card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
+
+	switch (card_id) {
+	case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
+		value = QIXIS_READ(brdcfg[5]);
+		value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
+		QIXIS_WRITE(brdcfg[5], value);
+		break;
+	case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
+		value = QIXIS_READ(pwr_ctl[1]);
+		value |= QIXIS_EVDD_BY_SDHC_VS;
+		QIXIS_WRITE(pwr_ctl[1], value);
+		break;
+	case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
+		value = QIXIS_READ(brdcfg[5]);
+		value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
+		QIXIS_WRITE(brdcfg[5], value);
+		break;
+	default:
+		break;
+	}
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 2;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash + promjet */
+		disable_tlb(flash_esel);
+	}
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	/* Disable remote I2C connection to qixis fpga */
+	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
+
+	/*
+	 * Adjust core voltage according to voltage ID
+	 * This function changes I2C mux to channel 2.
+	 */
+	if (adjust_vdd(0))
+		printf("Warning: Adjusting core voltage failed.\n");
+
+	brd_mux_lane_to_slot();
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
+	esdhc_adapter_card_ident();
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+	/* use accurate clock measurement */
+	int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
+	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+	u32 val;
+
+	val =  freq * base;
+	if (val) {
+		debug("SYS Clock measurement is: %d\n", val);
+		return val;
+	} else {
+		printf("Warning: SYS clock measurement is invalid, ");
+		printf("using value from brdcfg1.\n");
+	}
+#endif
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+	/* use accurate clock measurement */
+	int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
+	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+	u32 val;
+
+	val =  freq * base;
+	if (val) {
+		debug("DDR Clock measurement is: %d\n", val);
+		return val;
+	} else {
+		printf("Warning: DDR clock measurement is invalid, ");
+		printf("using value from brdcfg1.\n");
+	}
+#endif
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+	fsl_fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
+	fdt_fixup_fman_ethernet(blob);
+#endif
+	fdt_fixup_board_enet(blob);
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/t208xqds/t208xqds.h b/roms/u-boot/board/freescale/t208xqds/t208xqds.h
new file mode 100644
index 000000000..50ebb6f6f
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/t208xqds.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, struct bd_info *bd);
+
+#endif
diff --git a/roms/u-boot/board/freescale/t208xqds/t208xqds_qixis.h b/roms/u-boot/board/freescale/t208xqds/t208xqds_qixis.h
new file mode 100644
index 000000000..0f9a45a6f
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/t208xqds_qixis.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __T208xQDS_QIXIS_H__
+#define __T208xQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T208xQDS */
+
+#define QIXIS_SRDS1CLK_122		0x5a
+#define QIXIS_SRDS1CLK_125		0x5e
+
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK             0xE0
+#define BRDCFG4_EMISEL_SHIFT            5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66                 0x0
+#define QIXIS_SYSCLK_83                 0x1
+#define QIXIS_SYSCLK_100                0x2
+#define QIXIS_SYSCLK_125                0x3
+#define QIXIS_SYSCLK_133                0x4
+#define QIXIS_SYSCLK_150                0x5
+#define QIXIS_SYSCLK_160                0x6
+#define QIXIS_SYSCLK_166                0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66                 0x0
+#define QIXIS_DDRCLK_100                0x1
+#define QIXIS_DDRCLK_125                0x2
+#define QIXIS_DDRCLK_133                0x3
+
+#define BRDCFG5_IRE                     0x20    /* i2c Remote i2c1 enable */
+
+#define BRDCFG9_SFP_TX_EN		0x10
+
+#define BRDCFG12_SD3EN_MASK             0x20
+#define BRDCFG12_SD3MX_MASK             0x08
+#define BRDCFG12_SD3MX_SLOT5            0x08
+#define BRDCFG12_SD3MX_SLOT6            0x00
+#define BRDCFG12_SD4EN_MASK             0x04
+#define BRDCFG12_SD4MX_MASK             0x03
+#define BRDCFG12_SD4MX_SLOT7            0x02
+#define BRDCFG12_SD4MX_SLOT8            0x01
+#define BRDCFG12_SD4MX_AURO_SATA        0x00
+#endif
diff --git a/roms/u-boot/board/freescale/t208xqds/tlb.c b/roms/u-boot/board/freescale/t208xqds/tlb.c
new file mode 100644
index 000000000..1e501da36
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xqds/tlb.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008-2013 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+	 * space is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	/* *I*G* - PCIe 1, 0x80000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_512M, 1),
+
+	/* *I*G* - PCIe 2, 0xa0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIe 3, 0xb0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+
+	/* *I*G* - PCIe 4, 0xc0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE_PHYS
+	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+	 * fetching ucode and ENV from master
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/freescale/t208xrdb/Kconfig b/roms/u-boot/board/freescale/t208xrdb/Kconfig
new file mode 100644
index 000000000..8249c5df9
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_T2080RDB
+
+config SYS_BOARD
+	default "t208xrdb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "T208xRDB"
+
+config T2080RDB_REV_D
+	bool "Support for T2080RDB revisions D and up"
+	default n
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/t208xrdb/MAINTAINERS b/roms/u-boot/board/freescale/t208xrdb/MAINTAINERS
new file mode 100644
index 000000000..6e9b25fa0
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/MAINTAINERS
@@ -0,0 +1,19 @@
+T208XRDB BOARD
+M:	Shengzhou Liu <Shengzhou.Liu@nxp.com>
+S:	Maintained
+F:	board/freescale/t208xrdb/
+F:	include/configs/T208xRDB.h
+F:	configs/T2080RDB_defconfig
+F:	configs/T2080RDB_NAND_defconfig
+F:	configs/T2080RDB_SDCARD_defconfig
+F:	configs/T2080RDB_SPIFLASH_defconfig
+F:	configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+F:	configs/T2080RDB_revD_defconfig
+F:	configs/T2080RDB_revD_NAND_defconfig
+F:	configs/T2080RDB_revD_SDCARD_defconfig
+F:	configs/T2080RDB_revD_SPIFLASH_defconfig
+
+T2080RDB_SECURE_BOOT BOARD
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
+S:	Maintained
+F:	configs/T2080RDB_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/t208xrdb/Makefile b/roms/u-boot/board/freescale/t208xrdb/Makefile
new file mode 100644
index 000000000..25ea66a02
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o
+else
+obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
+obj-$(CONFIG_PCI)      += pci.o
+endif
+
+obj-y   += ddr.o
+obj-y   += law.o
+obj-y   += tlb.o
diff --git a/roms/u-boot/board/freescale/t208xrdb/README b/roms/u-boot/board/freescale/t208xrdb/README
new file mode 100644
index 000000000..ec47c96f2
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/README
@@ -0,0 +1,288 @@
+T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
+It can work in two mode: standalone mode and PCIe endpoint mode.
+
+T2080 SoC Overview
+------------------
+The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
+Architecture processor cores with high-performance datapath acceleration
+logic and network and peripheral bus interfaces required for networking,
+telecom/datacom, wireless infrastructure, and mil/aerospace applications.
+
+T2080 includes the following functions and features:
+ - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
+ - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
+ - Hierarchical interconnect fabric
+ - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ - 16 SerDes lanes up to 10.3125 GHz
+ - 8 Ethernet interfaces, supporting combinations of the following:
+   - Up to four 10 Gbps Ethernet MACs
+   - Up to eight 1 Gbps Ethernet MACs
+   - Up to four 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+   - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
+ - Additional peripheral interfaces
+   - Two serial ATA (SATA 2.0) controllers
+   - Two high-speed USB 2.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
+   - Enhanced serial peripheral interface (eSPI)
+   - Four I2C controllers
+   - Four 2-pin UARTs or two 4-pin UARTs
+   - Integrated Flash Controller supporting NAND and NOR flash
+ - Three eight-channel DMA engines
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ Platform's Trust Architecture 2.0
+
+User Guide
+----------
+The T2080RDB User Guide is available on the web at
+https://www.nxp.com/docs/en/user-guide/T2080RDBPCUG.pdf
+
+Differences between T2080 and T2081
+-----------------------------------
+  Feature		T2080	 T2081
+  1G Ethernet numbers:  8	 6
+  10G Ethernet numbers: 4	 2
+  SerDes lanes:		16	 8
+  Serial RapidIO,RMan:  2	 no
+  SATA Controller:	2	 no
+  Aurora:		yes	 no
+  SoC Package:		896-pins 780-pins
+
+
+T2080PCIe-RDB board Overview
+----------------------------
+ - SERDES Configuration
+     - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
+     - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
+     - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
+     - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
+     - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
+     - SerDes-2 Lane G-H: to SATA1 & SATA2
+ - Ethernet
+     - Two on-board 10M/100M/1G RGMII ethernet ports
+     - Two on-board 10Gbps XFI fiber ports
+     - Two on-board 10Gbps Base-T copper ports
+ - DDR Memory
+     - Supports 72bit 4GB DDR3-LP SODIMM
+ - PCIe
+     - One PCIe x4 gold-finger
+     - One PCIe x4 connector
+     - One PCIe x2 end-point device (C293 Crypto co-processor)
+ - IFC/Local Bus
+     - NOR:  128MB 16-bit NOR Flash
+     - NAND: 1GB 8-bit NAND flash
+     - CPLD: for system controlling with programable header on-board
+ - SATA
+     - Two SATA 2.0 onnectors on-board
+ - USB
+     - Supports two USB 2.0 ports with integrated PHYs
+     - Two type A ports with 5V@1.5A per port.
+ - SDHC
+     - one TF-card connector on-board
+ - SPI
+     -  On-board 64MB SPI flash
+ - Other
+     - Two Serial ports
+     - Four I2C ports
+
+
+System Memory map
+-----------------
+Start Address  End Address      Description			Size
+0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - CPLD			4KB
+0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash		64KB
+0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR				16MB
+0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space		64KB
+0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space		64KB
+0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space		64KB
+0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space		64KB
+0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal	32MB
+0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal	32MB
+0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash			128MB
+0xF_0000_0000  0xF_003F_FFFF    DCSR				4MB
+0xC_4000_0000  0xC_4FFF_FFFF    PCI Express 4 Mem Space		256MB
+0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 3 Mem Space		256MB
+0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 2 Mem Space		256MB
+0xC_0000_0000  0xC_1FFF_FFFF    PCI Express 1 Mem Space		512MB
+0x0_0000_0000  0x0_ffff_ffff    DDR				4GB
+
+
+128M NOR Flash memory Map
+-------------------------
+Start Address   End Address	Definition			Max size
+0xEFF40000	0xEFFFFFFF	U-Boot (current bank)		768KB
+0xEFF20000	0xEFF3FFFF	U-Boot env (current bank)	128KB
+0xEFF00000	0xEFF1FFFF	FMAN Ucode (current bank)	128KB
+0xEFE00000	0xEFE3FFFF	PHY CS4315 firmware		256KB
+0xED300000	0xEFEFFFFF	rootfs (alt bank)		44MB
+0xEC800000	0xEC8FFFFF	Hardware device tree (alt bank)	1MB
+0xEC020000	0xEC7FFFFF	Linux.uImage (alt bank)		7MB + 875KB
+0xEC000000	0xEC01FFFF	RCW (alt bank)			128KB
+0xEBF40000	0xEBFFFFFF	U-Boot (alt bank)		768KB
+0xEBF20000	0xEBF3FFFF	U-Boot env (alt bank)		128KB
+0xEBF00000	0xEBF1FFFF	FMAN ucode (alt bank)		128KB
+0xEBE00000	0xEBE3FFFF	PHY CS4315 firmware (alt bank)	256KB
+0xE9300000	0xEBEFFFFF	rootfs (current bank)		44MB
+0xE8800000	0xE88FFFFF	Hardware device tree (cur bank)	1MB
+0xE8020000	0xE86FFFFF	Linux.uImage (current bank)	7MB + 875KB
+0xE8000000	0xE801FFFF	RCW (current bank)		128KB
+
+
+T2080PCIe-RDB Ethernet Port Map
+-------------------------------
+Label    In Uboot      In Linux     FMan Address   Comments    PHY
+ETH0     FM1@GTEC1     fm1-mac9     0xfe4f0000     10G SFP+   (CS4315)
+ETH1     FM1@GTEC2     fm1-mac10    0xfe4f2000     10G SFP+   (CS4315)
+ETH2     FM1@GTEC3     fm1-mac1     0xfe4e0000     10G Base-T (AQ1202)
+ETH3     FM1@GTEC4     fm1-mac2     0xfe4e2000     10G Base-T (AQ1202)
+ETH4     FM1@DTSEC3    fm1-mac3     0xfe4e4000     1G  RGMII  (RTL8211E)
+ETH5     FM1@DTSEC4    fm1-mac4     0xfe4e6000     1G  RGMII  (RTL8211E)
+
+
+T2080PCIe-RDB Default DIP-Switch setting
+----------------------------------------
+SW1[1:8] = '00010011'
+SW2[1:8] = '10111111'
+SW3[1:8] = '11100001'
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+   a. build NOR boot image
+	$ make T2080RDB_config
+	$ make
+   b. program u-boot.bin image to NOR flash
+	=> tftp 1000000 u-boot.bin
+	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+	set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+
+   Switching between default bank and alternate bank on NOR flash
+   To change boot source to vbank4:
+	via software:   run command 'cpld reset altbank' in U-Boot.
+	via DIP-switch: set SW3[5:7] = '100'
+
+   To change boot source to vbank0:
+	via software:   run command 'cpld reset' in U-Boot.
+	via DIP-Switch: set SW3[5:7] = '000'
+
+2. NAND Boot:
+   a. build PBL image for NAND boot
+	$ make T2080RDB_NAND_config
+	$ make
+   b. program u-boot-with-spl-pbl.bin to NAND flash
+	=> tftp 1000000 u-boot-with-spl-pbl.bin
+	=> nand erase 0 d0000
+	=> nand write 1000000 0 $filesize
+	set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
+
+3. SPI Boot:
+   a. build PBL image for SPI boot
+	$ make T2080RDB_SPIFLASH_config
+	$ make
+   b. program u-boot-with-spl-pbl.bin to SPI flash
+	=> tftp 1000000 u-boot-with-spl-pbl.bin
+	=> sf probe 0
+	=> sf erase 0 d0000
+	=> sf write 1000000 0 $filesize
+	set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+   a. build PBL image for SD boot
+	$ make T2080RDB_SDCARD_config
+	$ make
+   b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
+	=> tftp 1000000 u-boot-with-spl-pbl.bin
+	=> mmc write 1000000 8 0x800
+	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to U-Boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area		   | Address			|
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB)		|
+-------------------------------------------------
+|GD, BD		   | 0xFFFC8000 (4KB)		|
+-------------------------------------------------
+|ENV		   | 0xFFFC9000 (8KB)		|
+-------------------------------------------------
+|HEAP		   | 0xFFFCB000 (50KB)		|
+-------------------------------------------------
+|STACK		   | 0xFFFD8000 (22KB)		|
+-------------------------------------------------
+|U-Boot SPL	   | 0xFFFD8000 (160KB)		|
+-------------------------------------------------
+
+NAND Flash memory Map on T2080RDB
+--------------------------------------------------------------
+Start		End		Definition	Size
+0x000000	0x0FFFFF	U-Boot img	1MB  (2 blocks)
+0x100000	0x17FFFF	U-Boot env	512KB (1 block)
+0x180000	0x1FFFFF	FMAN ucode	512KB (1 block)
+0x200000	0x27FFFF	CS4315 ucode	512KB (1 block)
+
+
+Micro SD Card memory Map on T2080RDB
+----------------------------------------------------
+Block		#blocks		Definition	Size
+0x008		2048		U-Boot img	1MB
+0x800		0016		U-Boot env	8KB
+0x820		0128		FMAN ucode	64KB
+0x8a0		0512		CS4315 ucode	256KB
+
+
+SPI Flash memory Map on T2080RDB
+----------------------------------------------------
+Start		End		Definition	Size
+0x000000	0x0FFFFF	U-Boot img	1MB
+0x100000	0x101FFF	U-Boot env	8KB
+0x110000	0x11FFFF	FMAN ucode	64KB
+0x120000        0x15FFFF        CS4315 ucode	256KB
+
+
+How to update the ucode of Cortina CS4315/CS4340 10G PHY
+--------------------------------------------------------
+=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt
+=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize
+
+
+How to update the ucode of Freescale FMAN
+-----------------------------------------
+=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin
+=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
+
+
+For more details, please refer to T2080PCIe-RDB User Guide and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for t2080rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/roms/u-boot/board/freescale/t208xrdb/cpld.c b/roms/u-boot/board/freescale/t208xrdb/cpld.c
new file mode 100644
index 000000000..b9ba62adf
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/cpld.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * Freescale T2080RDB board-specific CPLD controlling supports.
+ */
+
+#include <common.h>
+#include <command.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	out_8(p + reg, value);
+}
+
+/* Set the boot bank to the alternate bank */
+void cpld_set_altbank(void)
+{
+	u8 reg = CPLD_READ(flash_csr);
+
+	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+	CPLD_WRITE(flash_csr, reg);
+	CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
+}
+
+/* Set the boot bank to the default bank */
+void cpld_set_defbank(void)
+{
+	u8 reg = CPLD_READ(flash_csr);
+
+	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+	CPLD_WRITE(flash_csr, reg);
+	CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
+}
+
+int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int rc = 0;
+
+	if (argc <= 1)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		if (strcmp(argv[2], "altbank") == 0)
+			cpld_set_altbank();
+		else
+			cpld_set_defbank();
+	} else {
+		rc = cmd_usage(cmdtp);
+	}
+
+	return rc;
+}
+
+U_BOOT_CMD(
+	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+	"Reset the board or alternate bank",
+	"reset: reset to default bank\n"
+	"cpld reset altbank: reset to alternate bank\n"
+);
diff --git a/roms/u-boot/board/freescale/t208xrdb/cpld.h b/roms/u-boot/board/freescale/t208xrdb/cpld.h
new file mode 100644
index 000000000..bd6c20374
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/cpld.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor
+ */
+
+/*
+ * CPLD register set of T2080RDB board-specific.
+ */
+struct cpld_data {
+	u8 chip_id1;		/* 0x00 - Chip ID1 register */
+	u8 chip_id2;		/* 0x01 - Chip ID2 register */
+	u8 hw_ver;		/* 0x02 - Hardware Revision Register */
+	u8 sw_ver;		/* 0x03 - Software Revision register */
+	u8 res0[12];		/* 0x04 - 0x0F - not used */
+	u8 reset_ctl;		/* 0x10 - Reset control Register */
+	u8 flash_csr;		/* 0x11 - Flash control and status register */
+	u8 thermal_csr;		/* 0x12 - Thermal control and status register */
+	u8 led_csr;		/* 0x13 - LED control and status register */
+	u8 sfp_csr;		/* 0x14 - SFP+ control and status register */
+	u8 misc_csr;		/* 0x15 - Misc control and status register */
+	u8 boot_or;		/* 0x16 - Boot config override register */
+	u8 boot_cfg1;		/* 0x17 - Boot configuration register 1 */
+	u8 boot_cfg2;		/* 0x18 - Boot configuration register 2 */
+} cpld_data_t;
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)  \
+	cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_LBMAP_MASK		0x3F
+#define CPLD_BANK_SEL_MASK	0x07
+#define CPLD_BANK_OVERRIDE	0x40
+#define CPLD_LBMAP_ALTBANK	0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK	0x40 /* BANK OR | BANK 0 */
+#define CPLD_LBMAP_RESET	0xFF
+#define CPLD_LBMAP_SHIFT	0x03
+#define CPLD_BOOT_SEL		0x80
+
+/* RSTCON Register */
+#define CPLD_RSTCON_EDC_RST	0x04
diff --git a/roms/u-boot/board/freescale/t208xrdb/ddr.c b/roms/u-boot/board/freescale/t208xrdb/ddr.c
new file mode 100644
index 000000000..1fbab36e1
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/ddr.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found");
+		printf("for data rate %lu MT/s\n", ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+		"wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x54;
+}
+
+int dram_init(void)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+	puts("Initializing....using SPD\n");
+	dram_size = fsl_ddr_sdram();
+#else
+	/* DDR has been initialised by first stage boot loader */
+	dram_size = fsl_ddr_sdram_size();
+#endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/t208xrdb/ddr.h b/roms/u-boot/board/freescale/t208xrdb/ddr.h
new file mode 100644
index 000000000..c00f17816
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/ddr.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 */
+	{2,  1200, 2, 10,     7, 0x0808090a, 0x0b0c0c0a},
+	{2,  1500, 2, 10,     6, 0x07070809, 0x0a0b0b09},
+	{2,  1600, 2, 10,     8, 0x0808070b, 0x0c0d0e0a},
+	{2,  1700, 2,  8,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{2,  1900, 0, 10,     7, 0x0808080c, 0x0b0c0c09},
+	{1,  1200, 2, 10,     7, 0x0808090a, 0x0b0c0c0a},
+	{1,  1500, 2, 10,     6, 0x07070809, 0x0a0b0b09},
+	{1,  1600, 2, 10,     8, 0x0808070b, 0x0c0d0e0a},
+	{1,  1700, 2,  8,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 0, 10,     7, 0x0808080c, 0x0b0c0c09},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+#endif
diff --git a/roms/u-boot/board/freescale/t208xrdb/eth_t208xrdb.c b/roms/u-boot/board/freescale/t208xrdb/eth_t208xrdb.c
new file mode 100644
index 000000000..e4592eac1
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/eth_t208xrdb.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fdt_support.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+
+extern u8 get_hw_revision(void);
+
+/* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two
+ * "fsl,dpa-ethernet" nodes that reference them.
+ */
+void fdt_fixup_board_fman_ethernet(void *fdt)
+{
+	int mac_off, eth_off, i;
+	char mac_path[2][42] = {
+		"/soc@ffe000000/fman@400000/ethernet@e8000",
+		"/soc@ffe000000/fman@400000/ethernet@ea000",
+	};
+	u32 eth_ph;
+
+	for (i = 0; i < 2; i++) {
+		/* Disable the MAC node */
+		mac_off = fdt_path_offset(fdt, mac_path[i]);
+		if (mac_off < 0)
+			continue;
+		fdt_status_disabled(fdt, mac_off);
+
+		/* Disable the fsl,dpa-ethernet node that points to the MAC.
+		 * The fsl,fman-mac property refers to the MAC's phandle.
+		 */
+		eth_ph = fdt_get_phandle(fdt, mac_off);
+		if (eth_ph <= 0)
+			continue;
+
+		eth_off = fdt_node_offset_by_prop_value(fdt, -1, "fsl,fman-mac",
+							&eth_ph,
+							sizeof(eth_ph));
+		if (eth_off >= 0)
+			fdt_status_disabled(fdt, eth_off);
+	}
+}
+
+/* Update the address of the second Aquantia PHY on boards revision D and up.
+ * Also rename the PHY node to align with the address change.
+ */
+void fdt_fixup_board_phy(void *fdt)
+{
+	const char phy_path[] =
+		"/soc@ffe000000/fman@400000/mdio@fd000/ethernet-phy@1";
+	int ret, offset, new_addr = AQR113C_PHY_ADDR2;
+	char new_name[] = "ethernet-phy@00";
+
+	if (get_hw_revision() == 'C')
+		return;
+
+	offset = fdt_path_offset(fdt, phy_path);
+	if (offset < 0) {
+		printf("ethernet-phy@1 node not found in the dts\n");
+		return;
+	}
+
+	ret = fdt_setprop(fdt, offset, "reg", &new_addr, sizeof(new_addr));
+	if (ret < 0) {
+		printf("Unable to set 'reg' for node ethernet-phy@1: %s\n",
+		       fdt_strerror(ret));
+		return;
+	}
+
+	sprintf(new_name, "ethernet-phy@%x", new_addr);
+	ret = fdt_set_name(fdt, offset, new_name);
+	if (ret < 0)
+		printf("Unable to rename node ethernet-phy@1: %s\n",
+		       fdt_strerror(ret));
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	return;
+}
diff --git a/roms/u-boot/board/freescale/t208xrdb/law.c b/roms/u-boot/board/freescale/t208xrdb/law.c
new file mode 100644
index 000000000..d3b263f59
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/law.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/t208xrdb/pci.c b/roms/u-boot/board/freescale/t208xrdb/pci.c
new file mode 100644
index 000000000..45ab9223a
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/pci.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007-2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+#if !defined(CONFIG_DM_PCI)
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, struct bd_info *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/t208xrdb/spl.c b/roms/u-boot/board/freescale/t208xrdb/spl.c
new file mode 100644
index 000000000..b0ce9af00
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/spl.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <console.h>
+#include <env_internal.h>
+#include <init.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include <asm/global_data.h>
+#include "../common/spl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, sys_clk, ccb_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+	/* Update GD pointer */
+	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	sys_clk = get_board_sys_clk();
+	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+	ccb_clk = sys_clk * plat_ratio / 2;
+
+	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+		     ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	puts("\nNAND boot...\n");
+#endif
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	struct bd_info *bd;
+
+	bd = (struct bd_info *)(gd + sizeof(gd_t));
+	memset(bd, 0, sizeof(struct bd_info));
+	gd->bd = bd;
+
+	arch_cpu_init();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)SPL_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)SPL_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+	fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			       (uchar *)SPL_ENV_ADDR);
+#endif
+
+	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
+	gd->env_valid = ENV_VALID;
+
+	i2c_init_all();
+
+	dram_init();
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	fsl_spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/roms/u-boot/board/freescale/t208xrdb/t2080_nand_rcw.cfg b/roms/u-boot/board/freescale/t208xrdb/t2080_nand_rcw.cfg
new file mode 100644
index 000000000..8096ff9f3
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/t2080_nand_rcw.cfg
@@ -0,0 +1,19 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
+#120c0017 15000000 00000000 00000000
+#66150002 00008400 ec104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
+#1206001b 15000000 00000000 00000000
+
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 15000000 00000000 00000000
+66150002 00000000 e8104000 c1000000
+00800000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/roms/u-boot/board/freescale/t208xrdb/t2080_pbi.cfg b/roms/u-boot/board/freescale/t208xrdb/t2080_pbi.cfg
new file mode 100644
index 000000000..43be8a864
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/t2080_pbi.cfg
@@ -0,0 +1,40 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+091380c0 00100000
diff --git a/roms/u-boot/board/freescale/t208xrdb/t2080_sd_rcw.cfg b/roms/u-boot/board/freescale/t208xrdb/t2080_sd_rcw.cfg
new file mode 100644
index 000000000..6309b1d22
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/t2080_sd_rcw.cfg
@@ -0,0 +1,19 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
+#120c0017 15000000 00000000 00000000
+#66150002 00008400 ec104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
+#1206001b 15000000 00000000 00000000
+
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 15000000 00000000 00000000
+66150002 00000000 68104000 c1000000
+00800000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/roms/u-boot/board/freescale/t208xrdb/t2080_spi_rcw.cfg b/roms/u-boot/board/freescale/t208xrdb/t2080_spi_rcw.cfg
new file mode 100644
index 000000000..f16749588
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/t2080_spi_rcw.cfg
@@ -0,0 +1,19 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
+#120c0017 15000000 00000000 00000000
+#66150002 00008400 ec104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
+#1206001b 15000000 00000000 00000000
+
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 15000000 00000000 00000000
+66150002 00000000 58104000 c1000000
+00800000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/roms/u-boot/board/freescale/t208xrdb/t208xrdb.c b/roms/u-boot/board/freescale/t208xrdb/t208xrdb.c
new file mode 100644
index 000000000..1f0cdee0b
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/t208xrdb.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <image.h>
+#include <init.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include "t208xrdb.h"
+#include "cpld.h"
+#include "../common/vid.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u8 get_hw_revision(void)
+{
+	u8 ver = CPLD_READ(hw_ver);
+
+	switch (ver) {
+	default:
+	case 0x1:
+		return 'C';
+	case 0x0:
+		return 'D';
+	case 0x2:
+		return 'E';
+	}
+}
+
+int checkboard(void)
+{
+	struct cpu_type *cpu = gd->arch.cpu;
+	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+
+	printf("Board: %sRDB, ", cpu->name);
+	printf("Board rev: %c CPLD ver: 0x%02x, boot from ",
+	       get_hw_revision(), CPLD_READ(sw_ver));
+
+#ifdef CONFIG_SDCARD
+	puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+	puts("SPI\n");
+#else
+	u8 reg;
+
+	reg = CPLD_READ(flash_csr);
+
+	if (reg & CPLD_BOOT_SEL) {
+		puts("NAND\n");
+	} else {
+		reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+		printf("NOR vBank%d\n", reg);
+	}
+#endif
+
+	puts("SERDES Reference Clocks:\n");
+	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+	printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 2;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash + promjet */
+		disable_tlb(flash_esel);
+	}
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	/*
+	 * Adjust core voltage according to voltage ID
+	 * This function changes I2C mux to channel 2.
+	 */
+	if (adjust_vdd(0))
+		printf("Warning: Adjusting core voltage failed.\n");
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return CONFIG_DDR_CLK_FREQ;
+}
+
+int misc_init_r(void)
+{
+	u8 reg;
+
+	/* Reset CS4315 PHY */
+	reg = CPLD_READ(reset_ctl);
+	reg |= CPLD_RSTCON_EDC_RST;
+	CPLD_WRITE(reset_ctl, reg);
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+	fsl_fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_board_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
+	fdt_fixup_board_phy(blob);
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/t208xrdb/t208xrdb.h b/roms/u-boot/board/freescale/t208xrdb/t208xrdb.h
new file mode 100644
index 000000000..edbc860c9
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/t208xrdb.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, struct bd_info *bd);
+void fdt_fixup_board_fman_ethernet(void *blob);
+void fdt_fixup_board_phy(void *blob);
+
+#endif
diff --git a/roms/u-boot/board/freescale/t208xrdb/tlb.c b/roms/u-boot/board/freescale/t208xrdb/tlb.c
new file mode 100644
index 000000000..542ab1e03
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/tlb.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+	 * space is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	/* *I*G* - PCIe 1, 0x80000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_512M, 1),
+
+	/* *I*G* - PCIe 2, 0xa0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIe 3, 0xb0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+
+	/* *I*G* - PCIe 4, 0xc0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+	 * fetching ucode and ENV from master
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/freescale/t4rdb/Kconfig b/roms/u-boot/board/freescale/t4rdb/Kconfig
new file mode 100644
index 000000000..a94a57e7f
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_T4160RDB || TARGET_T4240RDB
+
+config SYS_BOARD
+	default "t4rdb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "T4240RDB"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/t4rdb/MAINTAINERS b/roms/u-boot/board/freescale/t4rdb/MAINTAINERS
new file mode 100644
index 000000000..7380408aa
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/MAINTAINERS
@@ -0,0 +1,8 @@
+T4RDB BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	board/freescale/t4rdb/
+F:	include/configs/T4240RDB.h
+F:	configs/T4160RDB_defconfig
+F:	configs/T4240RDB_defconfig
+F:	configs/T4240RDB_SDCARD_defconfig
diff --git a/roms/u-boot/board/freescale/t4rdb/Makefile b/roms/u-boot/board/freescale/t4rdb/Makefile
new file mode 100644
index 000000000..209983a24
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/Makefile
@@ -0,0 +1,19 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o
+else
+obj-$(CONFIG_TARGET_T4160RDB)	+= t4240rdb.o
+obj-$(CONFIG_TARGET_T4240RDB)	+= t4240rdb.o
+obj-y			+= cpld.o
+obj-y			+= eth.o
+obj-$(CONFIG_PCI)	+= pci.o
+endif
+
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/roms/u-boot/board/freescale/t4rdb/cpld.c b/roms/u-boot/board/freescale/t4rdb/cpld.c
new file mode 100644
index 000000000..d484509bc
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/cpld.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
+ * CPLD register map
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	out_8(p + reg, value);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(void)
+{
+	u8 val, curbank, altbank, override;
+
+	val = CPLD_READ(vbank);
+	curbank = val & CPLD_BANK_SEL_MASK;
+
+	switch (curbank) {
+	case CPLD_SELECT_BANK0:
+	case CPLD_SELECT_BANK4:
+		altbank = CPLD_SELECT_BANK4;
+		CPLD_WRITE(vbank, altbank);
+		override = CPLD_READ(software_on);
+		CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
+		CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
+		break;
+	default:
+		printf("CPLD Altbank Fail: Invalid value!\n");
+		return;
+	}
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+	u8 val;
+
+	val = CPLD_DEFAULT_BANK;
+
+	CPLD_WRITE(global_reset, val);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+	printf("chip_id1	= 0x%02x\n", CPLD_READ(chip_id1));
+	printf("chip_id2	= 0x%02x\n", CPLD_READ(chip_id2));
+	printf("sw_maj_ver	= 0x%02x\n", CPLD_READ(sw_maj_ver));
+	printf("sw_min_ver	= 0x%02x\n", CPLD_READ(sw_min_ver));
+	printf("hw_ver		= 0x%02x\n", CPLD_READ(hw_ver));
+	printf("software_on	= 0x%02x\n", CPLD_READ(software_on));
+	printf("cfg_rcw_src	= 0x%02x\n", CPLD_READ(cfg_rcw_src));
+	printf("res0		= 0x%02x\n", CPLD_READ(res0));
+	printf("vbank		= 0x%02x\n", CPLD_READ(vbank));
+	printf("sw1_sysclk	= 0x%02x\n", CPLD_READ(sw1_sysclk));
+	printf("sw2_status	= 0x%02x\n", CPLD_READ(sw2_status));
+	printf("sw3_status	= 0x%02x\n", CPLD_READ(sw3_status));
+	printf("sw4_status	= 0x%02x\n", CPLD_READ(sw4_status));
+	printf("sys_reset	= 0x%02x\n", CPLD_READ(sys_reset));
+	printf("global_reset	= 0x%02x\n", CPLD_READ(global_reset));
+	printf("res1		= 0x%02x\n", CPLD_READ(res1));
+	putc('\n');
+}
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int rc = 0;
+
+	if (argc <= 1)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		if (strcmp(argv[2], "altbank") == 0)
+			cpld_set_altbank();
+		else
+			cpld_set_defbank();
+#ifdef DEBUG
+	} else if (strcmp(argv[1], "dump") == 0) {
+		cpld_dump_regs();
+#endif
+	} else
+		rc = cmd_usage(cmdtp);
+
+	return rc;
+}
+
+U_BOOT_CMD(
+	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+	"Reset the board or alternate bank",
+	"reset - reset to default bank\n"
+	"cpld reset altbank - reset to alternate bank\n"
+#ifdef DEBUG
+	"cpld dump - display the CPLD registers\n"
+#endif
+	);
+#endif
diff --git a/roms/u-boot/board/freescale/t4rdb/cpld.h b/roms/u-boot/board/freescale/t4rdb/cpld.h
new file mode 100644
index 000000000..dc3f9f3c2
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/cpld.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+struct cpld_data {
+	u8 chip_id1;	/* 0x00 - CPLD Chip ID1 Register */
+	u8 chip_id2;	/* 0x01 - CPLD Chip ID2 Register */
+	u8 sw_maj_ver;	/* 0x02 - CPLD Code Major Version Register */
+	u8 sw_min_ver;	/* 0x03 - CPLD Code Minor Version Register */
+	u8 hw_ver;	/* 0x04 - PCBA Version Register */
+	u8 software_on;	/* 0x05 - Override Physical Switch Enable Register */
+	u8 cfg_rcw_src;	/* 0x06 - RCW Source Location Control Register */
+	u8 res0;	/* 0x07 - not used */
+	u8 vbank;	/* 0x08 - Flash Bank Selection Control Register */
+	u8 sw1_sysclk;	/* 0x09 - SW1 Status Read Back Register */
+	u8 sw2_status;	/* 0x0a - SW2 Status Read Back Register */
+	u8 sw3_status;	/* 0x0b - SW3 Status Read Back Register */
+	u8 sw4_status;	/* 0x0c - SW4 Status Read Back Register */
+	u8 sys_reset;	/* 0x0d - Reset System With Reserving Registers Value*/
+	u8 global_reset;/* 0x0e - Reset System With Default Registers Value */
+	u8 res1;	/* 0x0f - not used */
+};
+
+#define CPLD_BANK_SEL_MASK	0x07
+#define CPLD_BANK_SEL_EN	0x04
+#define CPLD_SYSTEM_RESET	0x01
+#define CPLD_SELECT_BANK0	0x00
+#define CPLD_SELECT_BANK4	0x04
+#define CPLD_DEFAULT_BANK	0x01
+
+/* Pointer to the CPLD register set */
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value) \
+		cpld_write(offsetof(struct cpld_data, reg), value)
+
diff --git a/roms/u-boot/board/freescale/t4rdb/ddr.c b/roms/u-boot/board/freescale/t4rdb/ddr.c
new file mode 100644
index 000000000..57cbde154
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/ddr.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 2) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	/*
+	 * we use identical timing for all slots. If needed, change the code
+	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+	 */
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[0];
+	else
+		pbsp = udimms[0];
+
+
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for data\n"
+			"rate %lu MT/s\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
+		"wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x64;
+}
+
+int dram_init(void)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....using SPD\n");
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+	dram_size = fsl_ddr_sdram();
+#else
+	/* DDR has been initialised by first stage boot loader */
+	dram_size = fsl_ddr_sdram_size();
+#endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/freescale/t4rdb/ddr.h b/roms/u-boot/board/freescale/t4rdb/ddr.h
new file mode 100644
index 000000000..74a277961
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/ddr.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a},
+	{2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09},
+	{2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b},
+	{2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a},
+	{2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
+	{2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
+	{1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a},
+	{1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a},
+	{1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
+	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
+	{}
+};
+
+/*
+ * The three slots have slightly different timing. The center values are good
+ * for all slots. We use identical speed tables for them. In future use, if
+ * DIMMs require separated tables, make more entries as needed.
+ */
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+/*
+ * The three slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+};
+
+
+#endif
diff --git a/roms/u-boot/board/freescale/t4rdb/eth.c b/roms/u-boot/board/freescale/t4rdb/eth.c
new file mode 100644
index 000000000..c815a3a4f
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/eth.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Chunhe Lan <Chunhe.Lan@freescale.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fdt_support.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include <hwconfig.h>
+
+#include "../common/fman.h"
+#include "t4rdb.h"
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	return;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+	int i, interface;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	struct mii_dev *dev;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_prtcl_s1, srds_prtcl_s2;
+
+	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
+		/* SGMII */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
+		fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
+		fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
+	} else {
+		puts("Invalid SerDes1 protocol for T4240RDB\n");
+	}
+
+	fm_disable_port(FM1_DTSEC5);
+	fm_disable_port(FM1_DTSEC6);
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_SGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
+		/* SGMII && XFI */
+		fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
+		fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
+		fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
+		fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
+		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
+		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
+		fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
+	} else {
+		puts("Invalid SerDes2 protocol for T4240RDB\n");
+	}
+
+	fm_disable_port(FM2_DTSEC5);
+	fm_disable_port(FM2_DTSEC6);
+	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_SGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+#endif /* CONFIG_SYS_NUM_FMAN */
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/freescale/t4rdb/law.c b/roms/u-boot/board/freescale/t4rdb/law.c
new file mode 100644
index 000000000..038f60565
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/law.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/t4rdb/pci.c b/roms/u-boot/board/freescale/t4rdb/pci.c
new file mode 100644
index 000000000..c2bc05164
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/pci.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+#if !defined(CONFIG_DM_PCI)
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, struct bd_info *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/t4rdb/spl.c b/roms/u-boot/board/freescale/t4rdb/spl.c
new file mode 100644
index 000000000..e2f9c9b3d
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/spl.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <console.h>
+#include <env_internal.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/spl.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+
+#include "t4rdb.h"
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK	0xFF800000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, sys_clk, ccb_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+	/* Update GD pointer */
+	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+	/* compiler optimization barrier needed for GCC >= 3.4 */
+	__asm__ __volatile__("" : : : "memory");
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	sys_clk = get_board_sys_clk();
+	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+	ccb_clk = sys_clk * plat_ratio / 2;
+
+	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+		     ccb_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nSD boot...\n");
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	struct bd_info *bd;
+
+	bd = (struct bd_info *)(gd + sizeof(gd_t));
+	memset(bd, 0, sizeof(struct bd_info));
+	gd->bd = bd;
+
+	arch_cpu_init();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+
+	mmc_initialize(bd);
+	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)SPL_ENV_ADDR);
+
+	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
+	gd->env_valid = ENV_VALID;
+
+	i2c_init_all();
+
+	dram_init();
+
+	mmc_boot();
+}
diff --git a/roms/u-boot/board/freescale/t4rdb/t4240rdb.c b/roms/u-boot/board/freescale/t4rdb/t4240rdb.c
new file mode 100644
index 000000000..6ab35ca91
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/t4240rdb.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <image.h>
+#include <init.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "t4rdb.h"
+#include "cpld.h"
+#include "../common/vid.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	struct cpu_type *cpu = gd->arch.cpu;
+	u8 sw;
+
+	printf("Board: %sRDB, ", cpu->name);
+	printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
+	       CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver));
+
+	sw = CPLD_READ(vbank);
+	sw = sw & CPLD_BANK_SEL_MASK;
+
+	if (sw <= 7)
+		printf("vBank: %d\n", sw);
+	else
+		printf("Unsupported Bank=%x\n", sw);
+
+	puts("SERDES Reference Clocks:\n");
+	printf("       SERDES1=100MHz SERDES2=156.25MHz\n"
+	       "       SERDES3=100MHz SERDES4=100MHz\n");
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 2;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash + promjet */
+		disable_tlb(flash_esel);
+	}
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	/*
+	 * Adjust core voltage according to voltage ID
+	 * This function changes I2C mux to channel 2.
+	*/
+	if (adjust_vdd(0))
+		printf("Warning: Adjusting core voltage failed.\n");
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+	fsl_fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
+	fdt_fixup_fman_ethernet(blob);
+#endif
+	fdt_fixup_board_enet(blob);
+#endif
+
+	return 0;
+}
+
+/*
+ * This function is called by bdinfo to print detail board information.
+ * As an exmaple for future board, we organize the messages into
+ * several sections. If applicable, the message is in the format of
+ * <name>      = <value>
+ * It should aligned with normal output of bdinfo command.
+ *
+ * Voltage: Core, DDR and another configurable voltages
+ * Clock  : Critical clocks which are not printed already
+ * RCW    : RCW source if not printed already
+ * Misc   : Other important information not in above catagories
+ */
+void board_detail(void)
+{
+	int rcwsrc;
+
+	/* RCW section SW3[4] */
+	rcwsrc = 0x0;
+	puts("RCW source  = ");
+	switch (rcwsrc & 0x1) {
+	case 0x1:
+		puts("SDHC/eMMC\n");
+		break;
+	default:
+		puts("I2C normal addressing\n");
+		break;
+	}
+}
diff --git a/roms/u-boot/board/freescale/t4rdb/t4_pbi.cfg b/roms/u-boot/board/freescale/t4rdb/t4_pbi.cfg
new file mode 100644
index 000000000..0b326fa16
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/t4_pbi.cfg
@@ -0,0 +1,27 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+091380c0 00100000
diff --git a/roms/u-boot/board/freescale/t4rdb/t4_sd_rcw.cfg b/roms/u-boot/board/freescale/t4rdb/t4_sd_rcw.cfg
new file mode 100644
index 000000000..cc2bff682
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/t4_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol  27_55_1_9
+16070019 18101916 00000000 00000000
+6c6e0848 00448c00 6c020000 f5000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000028
diff --git a/roms/u-boot/board/freescale/t4rdb/t4rdb.h b/roms/u-boot/board/freescale/t4rdb/t4rdb.h
new file mode 100644
index 000000000..3f1fa7bbd
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/t4rdb.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __T4RDB_H__
+#define __T4RDB_H__
+
+#undef CONFIG_SYS_NUM_FM1_DTSEC
+#undef CONFIG_SYS_NUM_FM2_DTSEC
+#define CONFIG_SYS_NUM_FM1_DTSEC	4
+#define CONFIG_SYS_NUM_FM2_DTSEC	4
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, struct bd_info *bd);
+
+#endif
diff --git a/roms/u-boot/board/freescale/t4rdb/tlb.c b/roms/u-boot/board/freescale/t4rdb/tlb.c
new file mode 100644
index 000000000..b927dd848
--- /dev/null
+++ b/roms/u-boot/board/freescale/t4rdb/tlb.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 512K SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_512K, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+		      MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 18, BOOKE_PAGESZ_2G, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/freescale/vf610twr/Kconfig b/roms/u-boot/board/freescale/vf610twr/Kconfig
new file mode 100644
index 000000000..3b90ed67f
--- /dev/null
+++ b/roms/u-boot/board/freescale/vf610twr/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VF610TWR
+
+config SYS_BOARD
+	default "vf610twr"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "vf610twr"
+
+endif
diff --git a/roms/u-boot/board/freescale/vf610twr/MAINTAINERS b/roms/u-boot/board/freescale/vf610twr/MAINTAINERS
new file mode 100644
index 000000000..b2eef8e24
--- /dev/null
+++ b/roms/u-boot/board/freescale/vf610twr/MAINTAINERS
@@ -0,0 +1,7 @@
+VF610TWR BOARD
+M:	Alison Wang <alison.wang@nxp.com>
+S:	Maintained
+F:	board/freescale/vf610twr/
+F:	include/configs/vf610twr.h
+F:	configs/vf610twr_defconfig
+F:	configs/vf610twr_nand_defconfig
diff --git a/roms/u-boot/board/freescale/vf610twr/Makefile b/roms/u-boot/board/freescale/vf610twr/Makefile
new file mode 100644
index 000000000..43934e8b2
--- /dev/null
+++ b/roms/u-boot/board/freescale/vf610twr/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+
+obj-y	:= vf610twr.o
diff --git a/roms/u-boot/board/freescale/vf610twr/imximage.cfg b/roms/u-boot/board/freescale/vf610twr/imximage.cfg
new file mode 100644
index 000000000..e2fa1a582
--- /dev/null
+++ b/roms/u-boot/board/freescale/vf610twr/imximage.cfg
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/mach-imx/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET	FLASH_OFFSET_STANDARD
diff --git a/roms/u-boot/board/freescale/vf610twr/vf610twr.c b/roms/u-boot/board/freescale/vf610twr/vf610twr.c
new file mode 100644
index 000000000..98cb0140a
--- /dev/null
+++ b/roms/u-boot/board/freescale/vf610twr/vf610twr.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/ddrmc-vf610.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+			PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+static struct ddrmc_cr_setting vf610twr_cr_settings[] = {
+	/* levelling */
+	{ DDRMC_CR97_WRLVL_EN, 97 },
+	{ DDRMC_CR98_WRLVL_DL_0(0), 98 },
+	{ DDRMC_CR99_WRLVL_DL_1(0), 99 },
+	{ DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
+	{ DDRMC_CR105_RDLVL_DL_0(0), 105 },
+	{ DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
+	{ DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
+	/* AXI */
+	{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
+	{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
+	{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
+		   DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
+	{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
+		   DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
+	{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+		   DDRMC_CR122_AXI0_PRIRLX(100), 122 },
+	{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
+		   DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
+	{ DDRMC_CR124_AXI1_PRIRLX(100), 124 },
+	{ DDRMC_CR126_PHY_RDLAT(8), 126 },
+	{ DDRMC_CR132_WRLAT_ADJ(5) |
+		   DDRMC_CR132_RDLAT_ADJ(6), 132 },
+	{ DDRMC_CR137_PHYCTL_DL(2), 137 },
+	{ DDRMC_CR138_PHY_WRLV_MXDL(256) |
+		   DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
+	{ DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+		   DDRMC_CR139_PHY_WRLV_DLL(3) |
+		   DDRMC_CR139_PHY_WRLV_EN(3), 139 },
+	{ DDRMC_CR140_PHY_WRLV_WW(64), 140 },
+	{ DDRMC_CR143_RDLV_GAT_MXDL(1536) |
+		   DDRMC_CR143_RDLV_MXDL(128), 143 },
+	{ DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
+		   DDRMC_CR144_PHY_RDLV_DLL(3) |
+		   DDRMC_CR144_PHY_RDLV_EN(3), 144 },
+	{ DDRMC_CR145_PHY_RDLV_RR(64), 145 },
+	{ DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
+	{ DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
+	{ DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
+	{ DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
+		   DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
+
+	{ DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+		   DDRMC_CR154_PAD_ZQ_MODE(1) |
+		   DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
+		   DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
+	{ DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
+	{ DDRMC_CR158_TWR(6), 158 },
+	{ DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
+		   DDRMC_CR161_TODTH_WR(2), 161 },
+	/* end marker */
+	{ 0, -1 }
+};
+
+int dram_init(void)
+{
+	static const struct ddr3_jedec_timings timings = {
+		.tinit             = 5,
+		.trst_pwron        = 80000,
+		.cke_inactive      = 200000,
+		.wrlat             = 5,
+		.caslat_lin        = 12,
+		.trc               = 21,
+		.trrd              = 4,
+		.tccd              = 4,
+		.tbst_int_interval = 0,
+		.tfaw              = 20,
+		.trp               = 6,
+		.twtr              = 4,
+		.tras_min          = 15,
+		.tmrd              = 4,
+		.trtp              = 4,
+		.tras_max          = 28080,
+		.tmod              = 12,
+		.tckesr            = 4,
+		.tcke              = 3,
+		.trcd_int          = 6,
+		.tras_lockout      = 0,
+		.tdal              = 12,
+		.bstlen            = 3,
+		.tdll              = 512,
+		.trp_ab            = 6,
+		.tref              = 3120,
+		.trfc              = 44,
+		.tref_int          = 0,
+		.tpdex             = 3,
+		.txpdll            = 10,
+		.txsnr             = 48,
+		.txsr              = 468,
+		.cksrx             = 5,
+		.cksre             = 5,
+		.freq_chg_en       = 0,
+		.zqcl              = 256,
+		.zqinit            = 512,
+		.zqcs              = 64,
+		.ref_per_zq        = 64,
+		.zqcs_rotate       = 0,
+		.aprebit           = 10,
+		.cmd_age_cnt       = 64,
+		.age_cnt           = 64,
+		.q_fullness        = 7,
+		.odt_rd_mapcs0     = 0,
+		.odt_wr_mapcs0     = 1,
+		.wlmrd             = 40,
+		.wldqsen           = 25,
+	};
+
+	ddrmc_setup_iomux(NULL, 0);
+
+	ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3);
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	static const iomux_v3_cfg_t uart1_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+	static const iomux_v3_cfg_t enet0_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
+}
+
+static void setup_iomux_i2c(void)
+{
+	static const iomux_v3_cfg_t i2c0_pads[] = {
+		VF610_PAD_PTB14__I2C0_SCL,
+		VF610_PAD_PTB15__I2C0_SDA,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
+}
+
+#ifdef CONFIG_NAND_VF610_NFC
+static void setup_iomux_nfc(void)
+{
+	static const iomux_v3_cfg_t nfc_pads[] = {
+		VF610_PAD_PTD31__NF_IO15,
+		VF610_PAD_PTD30__NF_IO14,
+		VF610_PAD_PTD29__NF_IO13,
+		VF610_PAD_PTD28__NF_IO12,
+		VF610_PAD_PTD27__NF_IO11,
+		VF610_PAD_PTD26__NF_IO10,
+		VF610_PAD_PTD25__NF_IO9,
+		VF610_PAD_PTD24__NF_IO8,
+		VF610_PAD_PTD23__NF_IO7,
+		VF610_PAD_PTD22__NF_IO6,
+		VF610_PAD_PTD21__NF_IO5,
+		VF610_PAD_PTD20__NF_IO4,
+		VF610_PAD_PTD19__NF_IO3,
+		VF610_PAD_PTD18__NF_IO2,
+		VF610_PAD_PTD17__NF_IO1,
+		VF610_PAD_PTD16__NF_IO0,
+		VF610_PAD_PTB24__NF_WE_B,
+		VF610_PAD_PTB25__NF_CE0_B,
+		VF610_PAD_PTB27__NF_RE_B,
+		VF610_PAD_PTC26__NF_RB_B,
+		VF610_PAD_PTC27__NF_ALE,
+		VF610_PAD_PTC28__NF_CLE
+	};
+
+	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+}
+#endif
+
+
+static void setup_iomux_qspi(void)
+{
+	static const iomux_v3_cfg_t qspi0_pads[] = {
+		VF610_PAD_PTD0__QSPI0_A_QSCK,
+		VF610_PAD_PTD1__QSPI0_A_CS0,
+		VF610_PAD_PTD2__QSPI0_A_DATA3,
+		VF610_PAD_PTD3__QSPI0_A_DATA2,
+		VF610_PAD_PTD4__QSPI0_A_DATA1,
+		VF610_PAD_PTD5__QSPI0_A_DATA0,
+		VF610_PAD_PTD7__QSPI0_B_QSCK,
+		VF610_PAD_PTD8__QSPI0_B_CS0,
+		VF610_PAD_PTD9__QSPI0_B_DATA3,
+		VF610_PAD_PTD10__QSPI0_B_DATA2,
+		VF610_PAD_PTD11__QSPI0_B_DATA1,
+		VF610_PAD_PTD12__QSPI0_B_DATA0,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{ESDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* eSDHC1 is always present */
+	return 1;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	static const iomux_v3_cfg_t esdhc1_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
+	};
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(
+		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+static void clock_init(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+
+	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+		CCM_CCGR0_UART1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+		CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+		CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+		CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+		CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
+		CCM_CCGR2_QSPI0_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+		CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+		CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+		CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+		CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+		CCM_CCGR7_SDHC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+		CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+		CCM_CCGR10_NFC_CTRL_MASK);
+
+	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
+		ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+		ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+		CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
+		CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
+		CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
+		CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
+		CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
+		CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
+		CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
+	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+		CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+		CCM_CACRR_ARM_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+		CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
+		CCM_CSCMR1_NFC_CLK_SEL(0));
+	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+		CCM_CSCDR1_RMII_CLK_EN);
+	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+		CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
+		CCM_CSCDR2_NFC_EN);
+	clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
+		CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
+		CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
+		CCM_CSCDR3_NFC_PRE_DIV(5));
+	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+		CCM_CSCMR2_RMII_CLK_SEL(0));
+}
+
+static void mscm_init(void)
+{
+	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+	int i;
+
+	for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	clock_init();
+	mscm_init();
+
+	setup_iomux_uart();
+	setup_iomux_enet();
+	setup_iomux_i2c();
+	setup_iomux_qspi();
+#ifdef CONFIG_NAND_VF610_NFC
+	setup_iomux_nfc();
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/*
+	 * Enable external 32K Oscillator
+	 *
+	 * The internal clock experiences significant drift
+	 * so we must use the external oscillator in order
+	 * to maintain correct time in the hwclock
+	 */
+	setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: vf610twr\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/friendlyarm/Kconfig b/roms/u-boot/board/friendlyarm/Kconfig
new file mode 100644
index 000000000..f8f9cfd87
--- /dev/null
+++ b/roms/u-boot/board/friendlyarm/Kconfig
@@ -0,0 +1,37 @@
+choice
+	prompt "LCD backlight control"
+	optional
+	default S5P4418_ONEWIRE
+
+config S5P4418_ONEWIRE
+	bool "I2C / 1-Wire"
+	help
+	  This enables LCD-Backlight control for FriendlyARM LCD-panels.
+	  I2C is used if available, otherwise 1-Wire is used.
+
+config PWM_NX
+	bool "PWM"
+	help
+	  This enables LCD-Backlight control via PWM.
+endchoice
+
+config ROOT_DEV
+	int "ROOT_DEV"
+	help
+	  Environment variable rootdev is set to this value if env. var. firstboot
+	  does not exist. Otherwise rootdev is set to the MMC boot device. rootdev
+	  determines (together with env. var. bootpart) where the OS (linux) is
+	  booted from.
+
+config BOOT_PART
+	int "BOOT_PART"
+	help
+	  Environment variable bootpart is set to this value. bootpart determines
+	  (together with env. var. rootdev) where the OS (linux) is booted from.
+
+config ROOT_PART
+	int "ROOT_PART"
+	help
+	  Environment variable rootpart is set to this value.
+
+source "board/friendlyarm/nanopi2/Kconfig"
diff --git a/roms/u-boot/board/friendlyarm/nanopi2/Kconfig b/roms/u-boot/board/friendlyarm/nanopi2/Kconfig
new file mode 100644
index 000000000..0f684229e
--- /dev/null
+++ b/roms/u-boot/board/friendlyarm/nanopi2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NANOPI2
+
+config SYS_BOARD
+	default "nanopi2"
+
+config SYS_VENDOR
+	default "friendlyarm"
+
+config SYS_CONFIG_NAME
+	default "s5p4418_nanopi2"
+
+endif
diff --git a/roms/u-boot/board/friendlyarm/nanopi2/MAINTAINERS b/roms/u-boot/board/friendlyarm/nanopi2/MAINTAINERS
new file mode 100644
index 000000000..c8e2ce7b7
--- /dev/null
+++ b/roms/u-boot/board/friendlyarm/nanopi2/MAINTAINERS
@@ -0,0 +1,7 @@
+NANOPI2 BOARD
+NANOPC-T2 BOARD
+M:  Stefan Bosch <stefan_b@posteo.net>
+S:  Maintained
+F:  board/s5p4418/nanopi2/
+F:  include/configs/s5p4418_nanopi2.h
+F:  configs/s5p4418_nanopi2_defconfig
diff --git a/roms/u-boot/board/friendlyarm/nanopi2/Makefile b/roms/u-boot/board/friendlyarm/nanopi2/Makefile
new file mode 100644
index 000000000..5c8b3b77f
--- /dev/null
+++ b/roms/u-boot/board/friendlyarm/nanopi2/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 Nexell
+# Hyunseok, Jung <hsjung@nexell.co.kr>
+
+obj-y	:= board.o hwrev.o lcds.o
+obj-$(CONFIG_S5P4418_ONEWIRE) += onewire.o
diff --git a/roms/u-boot/board/friendlyarm/nanopi2/board.c b/roms/u-boot/board/friendlyarm/nanopi2/board.c
new file mode 100644
index 000000000..c0fe2d546
--- /dev/null
+++ b/roms/u-boot/board/friendlyarm/nanopi2/board.c
@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Guangzhou FriendlyARM Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <fdt_support.h>
+#include <log.h>
+#ifdef CONFIG_PWM_NX
+#include <pwm.h>
+#endif
+#include <asm/global_data.h>
+#include <asm/io.h>
+
+#include <asm/arch/nexell.h>
+#include <asm/arch/nx_gpio.h>
+#include <asm/arch/display.h>
+#include <asm/arch/display_dev.h>
+
+#include <u-boot/md5.h>
+
+#include <linux/stringify.h>
+
+#include "hwrev.h"
+#include "onewire.h"
+#include "nxp-fb.h"
+
+#include <env_internal.h>	/* for env_save() */
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum gpio_group {
+	gpio_a, gpio_b, gpio_c, gpio_d, gpio_e,
+};
+
+#ifdef CONFIG_PWM_NX
+struct pwm_device {
+	int grp;
+	int bit;
+	int io_fn;
+};
+
+static inline void bd_pwm_config_gpio(int ch)
+{
+	struct pwm_device pwm_dev[] = {
+		[0] = { .grp = gpio_d, .bit = 1,  .io_fn = 0 },
+		[1] = { .grp = gpio_c, .bit = 13, .io_fn = 1 },
+		[2] = { .grp = gpio_c, .bit = 14, .io_fn = 1 },
+		[3] = { .grp = gpio_d, .bit = 0,  .io_fn = 0 },
+	};
+
+	int gp = pwm_dev[ch].grp;
+	int io = pwm_dev[ch].bit;
+
+	/* pwm backlight OFF: HIGH, ON: LOW */
+	nx_gpio_set_pad_function(gp, io, pwm_dev[ch].io_fn);
+	nx_gpio_set_output_value(gp, io, 1);
+	nx_gpio_set_output_enable(gp, io, 1);
+}
+#endif
+
+static void bd_backlight_off(void)
+{
+#ifdef CONFIG_S5P4418_ONEWIRE
+	onewire_set_backlight(0);
+
+#elif defined(BACKLIGHT_CH)
+	bd_pwm_config_gpio(BACKLIGHT_CH);
+#endif
+}
+
+static void bd_backlight_on(void)
+{
+#ifdef CONFIG_S5P4418_ONEWIRE
+	onewire_set_backlight(127);
+
+#elif defined(BACKLIGHT_CH)
+	/* pwm backlight ON: HIGH, ON: LOW */
+	pwm_init(BACKLIGHT_CH,
+		 BACKLIGHT_DIV, BACKLIGHT_INV);
+	pwm_config(BACKLIGHT_CH,
+		   TO_DUTY_NS(BACKLIGHT_DUTY, BACKLIGHT_HZ),
+		   TO_PERIOD_NS(BACKLIGHT_HZ));
+#endif
+}
+
+static void bd_lcd_config_gpio(void)
+{
+	int i;
+
+	for (i = 0; i < 28; i++) {
+		nx_gpio_set_pad_function(gpio_a, i, 1);
+		nx_gpio_set_drive_strength(gpio_a, i, 0);
+		nx_gpio_set_pull_mode(gpio_a, i, 2);
+	}
+
+	nx_gpio_set_drive_strength(gpio_a, 0, 1);
+}
+
+/* DEFAULT mmc dev for eMMC boot (dwmmc.2) */
+static int mmc_boot_dev;
+
+int board_mmc_bootdev(void)
+{
+	return mmc_boot_dev;
+}
+
+/* call from common/env_mmc.c */
+int mmc_get_env_dev(void)
+{
+	return mmc_boot_dev;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("Board: %s\n", get_board_name());
+
+	return 0;
+}
+#endif
+
+int nx_display_fixup_dp(struct nx_display_dev *dp)
+{
+	struct nxp_lcd *lcd = bd_get_lcd();
+	enum lcd_format fmt = bd_get_lcd_format();
+	struct nxp_lcd_timing *timing = &lcd->timing;
+	struct dp_sync_info *sync = &dp->sync;
+	struct dp_plane_info *plane = &dp->planes[0];
+	int i;
+	u32 clk = 800000000;
+	u32 div;
+
+	sync->h_active_len = lcd->width;
+	sync->h_sync_width = timing->h_sw;
+	sync->h_back_porch = timing->h_bp;
+	sync->h_front_porch = timing->h_fp;
+	sync->h_sync_invert = !lcd->polarity.inv_hsync;
+
+	sync->v_active_len = lcd->height;
+	sync->v_sync_width = timing->v_sw;
+	sync->v_back_porch = timing->v_bp;
+	sync->v_front_porch = timing->v_fp;
+	sync->v_sync_invert = !lcd->polarity.inv_vsync;
+
+	/* calculates pixel clock */
+	div  = timing->h_sw + timing->h_bp + timing->h_fp + lcd->width;
+	div *= timing->v_sw + timing->v_bp + timing->v_fp + lcd->height;
+	div *= lcd->freq ? : 60;
+	clk /= div;
+
+	dp->ctrl.clk_div_lv0 = clk;
+	dp->ctrl.clk_inv_lv0 = lcd->polarity.rise_vclk;
+
+	dp->top.screen_width = lcd->width;
+	dp->top.screen_height = lcd->height;
+
+	for (i = 0; i < dp->top.plane_num; i++, plane++) {
+		if (plane->enable) {
+			plane->width = lcd->width;
+			plane->height = lcd->height;
+		}
+	}
+
+	/* initialize display device type */
+	if (fmt == LCD_RGB) {
+		dp->dev_type = DP_DEVICE_RGBLCD;
+
+	} else if (fmt == LCD_HDMI) {
+		struct dp_hdmi_dev *dev = (struct dp_hdmi_dev *)dp->device;
+
+		dp->dev_type = DP_DEVICE_HDMI;
+		if (lcd->width == 1920 && lcd->height == 1080)
+			dev->preset = 1;
+		else
+			dev->preset = 0;
+
+	} else {
+		struct dp_lvds_dev *dev = (struct dp_lvds_dev *)dp->device;
+
+		dp->dev_type = DP_DEVICE_LVDS;
+		dev->lvds_format = (fmt & 0x3);
+	}
+
+	return 0;
+}
+
+/* --------------------------------------------------------------------------
+ * initialize board status.
+ */
+
+#define	MMC_BOOT_CH0		(0)
+#define	MMC_BOOT_CH1		(1 <<  3)
+#define	MMC_BOOT_CH2		(1 << 19)
+
+static void bd_bootdev_init(void)
+{
+	unsigned int rst = readl(PHY_BASEADDR_CLKPWR + SYSRSTCONFIG);
+
+	rst &= (1 << 19) | (1 << 3);
+	if (rst == MMC_BOOT_CH0) {
+		/* mmc dev 1 for SD boot */
+		mmc_boot_dev = 1;
+	}
+}
+
+#ifdef CONFIG_S5P4418_ONEWIRE
+static void bd_onewire_init(void)
+{
+	unsigned char lcd;
+	unsigned short fw_ver;
+
+	onewire_init();
+	onewire_get_info(&lcd, &fw_ver);
+}
+#endif
+
+static void bd_lcd_init(void)
+{
+	struct nxp_lcd *cfg;
+	int id = -1;
+	int ret;
+
+#ifdef CONFIG_S5P4418_ONEWIRE
+	id = onewire_get_lcd_id();
+	/* -1: onwire probe failed
+	 *  0: bad
+	 * >0: identified
+	 */
+#endif
+	ret = bd_setup_lcd_by_id(id);
+	if (id <= 0 || ret != id) {
+		printf("Panel: N/A (%d)\n", id);
+		bd_setup_lcd_by_name("HDMI720P60");
+
+	} else {
+		printf("Panel: %s\n", bd_get_lcd_name());
+
+		cfg = bd_get_lcd();
+		if (cfg->gpio_init)
+			cfg->gpio_init();
+	}
+}
+
+static int mac_read_from_generic_eeprom(u8 *addr)
+{
+	return -1;
+}
+
+static void make_ether_addr(u8 *addr)
+{
+	u32 hash[20];
+
+#define ETHER_MAC_TAG  "ethmac"
+	memset(hash, 0, sizeof(hash));
+	memcpy(hash + 12, ETHER_MAC_TAG, sizeof(ETHER_MAC_TAG));
+
+	hash[4] = readl(PHY_BASEADDR_ECID + 0x00);
+	hash[5] = readl(PHY_BASEADDR_ECID + 0x04);
+	hash[6] = readl(PHY_BASEADDR_ECID + 0x08);
+	hash[7] = readl(PHY_BASEADDR_ECID + 0x0c);
+
+	md5((unsigned char *)&hash[4], 64, (unsigned char *)hash);
+
+	hash[0] ^= hash[2];
+	hash[1] ^= hash[3];
+
+	memcpy(addr, (char *)hash, 6);
+	addr[0] &= 0xfe;	/* clear multicast bit */
+	addr[0] |= 0x02;
+}
+
+static void set_ether_addr(void)
+{
+	unsigned char mac[6];
+	char ethaddr[20];
+	int ret;
+
+	if (env_get("ethaddr"))
+		return;
+
+	ret = mac_read_from_generic_eeprom(mac);
+	if (ret < 0)
+		make_ether_addr(mac);
+
+	sprintf(ethaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
+		mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+	if (!ret)
+		printf("MAC:  [%s]\n", ethaddr);
+
+	env_set("ethaddr", ethaddr);
+}
+
+#ifdef CONFIG_REVISION_TAG
+static void set_board_rev(void)
+{
+	char info[64] = {0, };
+
+	snprintf(info, ARRAY_SIZE(info), "%02x", get_board_rev());
+	env_set("board_rev", info);
+}
+#endif
+
+static void set_dtb_name(void)
+{
+	char info[64] = {0, };
+
+	snprintf(info, ARRAY_SIZE(info),
+		 "s5p4418-nanopi2-rev%02x.dtb", get_board_rev());
+	env_set("dtb_name", info);
+}
+
+static void bd_update_env(void)
+{
+	char *lcdtype = env_get("lcdtype");
+	char *lcddpi = env_get("lcddpi");
+	char *bootargs = env_get("bootargs");
+	const char *name;
+	char *p = NULL;
+	int rootdev = board_mmc_bootdev();
+	int need_save = 0;
+
+#define CMDLINE_LCD		" lcd="
+	char cmdline[CONFIG_SYS_CBSIZE];
+	int n = 1;
+
+	if (rootdev != CONFIG_ROOT_DEV && !env_get("firstboot")) {
+		env_set_ulong("rootdev", rootdev);
+		env_set("firstboot", "0");
+		need_save = 1;
+	}
+
+	if (lcdtype) {
+		/* Setup again as user specified LCD in env */
+		bd_setup_lcd_by_name(lcdtype);
+	}
+
+	name = bd_get_lcd_name();
+
+	if (bootargs)
+		n = strlen(bootargs);	/* isn't 0 for NULL */
+	else
+		cmdline[0] = '\0';
+
+	if ((n + strlen(name) + sizeof(CMDLINE_LCD)) > sizeof(cmdline)) {
+		printf("Error: `bootargs' is too large (%d)\n", n);
+		goto __exit;
+	}
+
+	if (bootargs) {
+		p = strstr(bootargs, CMDLINE_LCD);
+		if (p) {
+			n = (p - bootargs);
+			p += strlen(CMDLINE_LCD);
+		}
+		strncpy(cmdline, bootargs, n);
+	}
+
+	/* add `lcd=NAME,NUMdpi' */
+	strncpy(cmdline + n, CMDLINE_LCD, strlen(CMDLINE_LCD));
+	n += strlen(CMDLINE_LCD);
+
+	strcpy(cmdline + n, name);
+	n += strlen(name);
+
+	if (lcddpi) {
+		n += sprintf(cmdline + n, ",%sdpi", lcddpi);
+	} else {
+		int dpi = bd_get_lcd_density();
+
+		if (dpi > 0 && dpi < 600)
+			n += sprintf(cmdline + n, ",%ddpi", dpi);
+	}
+
+	/* copy remaining of bootargs */
+	if (p) {
+		p = strstr(p, " ");
+		if (p) {
+			strcpy(cmdline + n, p);
+			n += strlen(p);
+		}
+	}
+
+	/* append `bootdev=2' */
+#define CMDLINE_BDEV	" bootdev="
+	if (rootdev > 0 && !strstr(cmdline, CMDLINE_BDEV))
+		n += sprintf(cmdline + n, "%s2", CMDLINE_BDEV);
+
+	/* finally, let's update uboot env & save it */
+	if (bootargs && strncmp(cmdline, bootargs, sizeof(cmdline))) {
+		env_set("bootargs", cmdline);
+		need_save = 1;
+	}
+
+__exit:
+	if (need_save)
+		env_save();
+}
+
+/* --------------------------------------------------------------------------
+ * call from u-boot
+ */
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	bd_hwrev_init();
+	bd_base_rev_init();
+
+	bd_bootdev_init();
+#ifdef CONFIG_S5P4418_ONEWIRE
+	bd_onewire_init();
+#endif
+
+	bd_backlight_off();
+
+	bd_lcd_config_gpio();
+	bd_lcd_init();
+
+	if (IS_ENABLED(CONFIG_SILENT_CONSOLE))
+		gd->flags |= GD_FLG_SILENT;
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	bd_update_env();
+
+#ifdef CONFIG_REVISION_TAG
+	set_board_rev();
+#endif
+	set_dtb_name();
+
+	set_ether_addr();
+
+	if (IS_ENABLED(CONFIG_SILENT_CONSOLE))
+		gd->flags &= ~GD_FLG_SILENT;
+
+	bd_backlight_on();
+	printf("\n");
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPLASH_SOURCE
+#include <splash.h>
+static struct splash_location splash_locations[] = {
+	{
+	.name = "mmc_fs",
+	.storage = SPLASH_STORAGE_MMC,
+	.flags = SPLASH_STORAGE_FS,
+	.devpart = __stringify(CONFIG_ROOT_DEV) ":"
+		   __stringify(CONFIG_BOOT_PART),
+	},
+};
+
+int splash_screen_prepare(void)
+{
+	int err;
+	char *env_cmd = env_get("load_splash");
+
+	debug("%s()\n", __func__);
+
+	if (env_cmd) {
+		err = run_command(env_cmd, 0);
+
+	} else {
+		char devpart[64] = { 0, };
+		int bootpart = env_get_ulong("bootpart", 0, CONFIG_BOOT_PART);
+		int rootdev;
+
+		if (env_get("firstboot"))
+			rootdev = env_get_ulong("rootdev", 0, CONFIG_ROOT_DEV);
+		else
+			rootdev = board_mmc_bootdev();
+
+		snprintf(devpart, ARRAY_SIZE(devpart), "%d:%d", rootdev,
+			 bootpart);
+		splash_locations[0].devpart = devpart;
+
+		err = splash_source_load(splash_locations,
+					 ARRAY_SIZE(splash_locations));
+	}
+
+	if (!err) {
+		char addr[64];
+
+		sprintf(addr, "0x%lx", gd->fb_base);
+		env_set("fb_addr", addr);
+	}
+
+	return err;
+}
+#endif
+
+/* u-boot dram initialize */
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
+}
+
+/* u-boot dram board specific */
+int dram_init_banksize(void)
+{
+#define SCR_USER_SIG6_READ		(SCR_ALIVE_BASE + 0x0F0)
+	unsigned int reg_val = readl(SCR_USER_SIG6_READ);
+
+	/* set global data memory */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x00000100;
+
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size  = CONFIG_SYS_SDRAM_SIZE;
+
+	/* Number of Row: 14 bits */
+	if ((reg_val >> 28) == 14)
+		gd->bd->bi_dram[0].size -= 0x20000000;
+
+	/* Number of Memory Chips */
+	if ((reg_val & 0x3) > 1) {
+		gd->bd->bi_dram[1].start = 0x80000000;
+		gd->bd->bi_dram[1].size  = 0x40000000;
+	}
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int nodeoff;
+	unsigned int rootdev;
+	unsigned int fb_addr;
+
+	if (board_mmc_bootdev() > 0) {
+		rootdev = fdt_getprop_u32_default(blob, "/board", "sdidx", 2);
+		if (rootdev) {
+			/* find or create "/chosen" node. */
+			nodeoff = fdt_find_or_add_subnode(blob, 0, "chosen");
+			if (nodeoff >= 0)
+				fdt_setprop_u32(blob, nodeoff, "linux,rootdev",
+						rootdev);
+		}
+	}
+
+	fb_addr = env_get_ulong("fb_addr", 0, 0);
+	if (fb_addr) {
+		nodeoff = fdt_path_offset(blob, "/reserved-memory");
+		if (nodeoff < 0)
+			return nodeoff;
+
+		nodeoff = fdt_add_subnode(blob, nodeoff, "display_reserved");
+		if (nodeoff >= 0) {
+			fdt32_t cells[2];
+
+			cells[0] = cpu_to_fdt32(fb_addr);
+			cells[1] = cpu_to_fdt32(0x800000);
+
+			fdt_setprop(blob, nodeoff, "reg", cells,
+				    sizeof(cells[0]) * 2);
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/friendlyarm/nanopi2/hwrev.c b/roms/u-boot/board/friendlyarm/nanopi2/hwrev.c
new file mode 100644
index 000000000..b1e23a48a
--- /dev/null
+++ b/roms/u-boot/board/friendlyarm/nanopi2/hwrev.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Guangzhou FriendlyARM Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#include <asm/arch/nexell.h>
+#include <asm/arch/nx_gpio.h>
+
+/* Board revision list: <PCB3 | PCB2 | PCB1>
+ *  0b000 - NanoPi 2
+ *  0b001 - NanoPC-T2
+ *  0b010 - NanoPi S2
+ *  0b011 - Smart4418
+ *  0b100 - NanoPi Fire 2A
+ *  0b111 - NanoPi M2A
+ *
+ * Extented revision:
+ *  0b001 - Smart4418-SDK
+ */
+#define __IO_GRP		2	/* GPIO_C */
+#define __IO_PCB1		26
+#define __IO_PCB2		27
+#define __IO_PCB3		25
+
+static int pcb_rev = -1;
+static int base_rev;
+
+static void bd_hwrev_config_gpio(void)
+{
+	int gpios[3][2] = {
+		{ __IO_PCB1, 1 },
+		{ __IO_PCB2, 1 },
+		{ __IO_PCB3, 1 },
+	};
+	int i;
+
+	/* gpio input mode, pull-down */
+	for (i = 0; i < 3; i++) {
+		nx_gpio_set_pad_function(__IO_GRP, gpios[i][0], gpios[i][1]);
+		nx_gpio_set_output_enable(__IO_GRP, gpios[i][0], 0);
+		nx_gpio_set_pull_mode(__IO_GRP, gpios[i][0], 0);
+	}
+}
+
+void bd_hwrev_init(void)
+{
+	if (pcb_rev >= 0)
+		return;
+
+	bd_hwrev_config_gpio();
+
+	pcb_rev  = nx_gpio_get_input_value(__IO_GRP, __IO_PCB1);
+	pcb_rev |= nx_gpio_get_input_value(__IO_GRP, __IO_PCB2) << 1;
+	pcb_rev |= nx_gpio_get_input_value(__IO_GRP, __IO_PCB3) << 2;
+}
+
+/* Get extended revision for SmartXX18 */
+void bd_base_rev_init(void)
+{
+	struct udevice *dev;
+	u8 val = 0;
+
+	if (pcb_rev != 0x3)
+		return;
+
+#define PCA9536_I2C_BUS     2
+#define PCA9636_I2C_ADDR    0x41
+	if (i2c_get_chip_for_busnum
+				(PCA9536_I2C_BUS, PCA9636_I2C_ADDR, 1, &dev))
+		return;
+
+	if (!dm_i2c_read(dev, 0, &val, 1))
+		base_rev = (val & 0xf);
+}
+
+/* To override __weak symbols */
+u32 get_board_rev(void)
+{
+	return (base_rev << 8) | pcb_rev;
+}
+
+const char *get_board_name(void)
+{
+	bd_hwrev_init();
+
+	switch (pcb_rev) {
+	case 0:
+		return "NanoPi 2";
+	case 1:
+		return "NanoPC-T2";
+	case 2:
+		return "NanoPi S2";
+	case 3:
+		return "Smart4418";
+	case 4:
+		return "NanoPi Fire 2A";
+	case 7:
+		return "NanoPi M2A";
+	default:
+		return "s5p4418-X";
+	}
+}
diff --git a/roms/u-boot/board/friendlyarm/nanopi2/hwrev.h b/roms/u-boot/board/friendlyarm/nanopi2/hwrev.h
new file mode 100644
index 000000000..1b1a828af
--- /dev/null
+++ b/roms/u-boot/board/friendlyarm/nanopi2/hwrev.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) Guangzhou FriendlyARM Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+#ifndef __BD_HW_REV_H__
+#define __BD_HW_REV_H__
+
+extern void bd_hwrev_init(void);
+extern void bd_base_rev_init(void);
+extern u32 get_board_rev(void);
+extern const char *get_board_name(void);
+
+#endif /* __BD_HW_REV_H__ */
diff --git a/roms/u-boot/board/friendlyarm/nanopi2/lcds.c b/roms/u-boot/board/friendlyarm/nanopi2/lcds.c
new file mode 100644
index 000000000..7303e53af
--- /dev/null
+++ b/roms/u-boot/board/friendlyarm/nanopi2/lcds.c
@@ -0,0 +1,697 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 FriendlyARM (www.arm9.net)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+
+#include <asm/arch/nexell.h>
+#include <asm/arch/display.h>
+#include <asm/arch/nx_gpio.h>
+
+#include "nxp-fb.h"
+
+/*
+ * param @module_index for nx_gpio APIs and will be removed
+ * after support pinctrl
+ */
+#ifndef PAD_GPIO_A
+#define PAD_GPIO_A	0
+#endif
+
+static inline void common_gpio_init(void)
+{
+	/* PVCLK */
+	nx_gpio_set_fast_slew(PAD_GPIO_A, 0, 1);
+}
+
+static void s70_gpio_init(void)
+{
+	int i;
+
+	/* PVCLK */
+	nx_gpio_set_drive_strength(PAD_GPIO_A, 0, 1);
+
+	/* RGB24 */
+	for (i = 1; i < 25; i++)
+		nx_gpio_set_drive_strength(PAD_GPIO_A, i, 2);
+
+	/* HS/VS/DE */
+	for (; i < 28; i++)
+		nx_gpio_set_drive_strength(PAD_GPIO_A, i, 1);
+}
+
+static void s702_gpio_init(void)
+{
+	int i;
+
+	common_gpio_init();
+
+	nx_gpio_set_drive_strength(PAD_GPIO_A, 0, 2);
+
+	for (i = 1; i < 25; i++)
+		nx_gpio_set_drive_strength(PAD_GPIO_A, i, 0);
+
+	for (; i < 28; i++)
+		nx_gpio_set_drive_strength(PAD_GPIO_A, i, 1);
+}
+
+static void s430_gpio_init(void)
+{
+	int  i;
+
+	for (i = 0; i < 28; i++)
+		nx_gpio_set_drive_strength(PAD_GPIO_A, i, 1);
+}
+
+static void hd101_gpio_init(void)
+{
+	int i;
+
+	common_gpio_init();
+
+	nx_gpio_set_drive_strength(PAD_GPIO_A, 0, 2);
+
+	for (i = 1; i < 25; i++)
+		nx_gpio_set_drive_strength(PAD_GPIO_A, i, 1);
+
+	nx_gpio_set_drive_strength(PAD_GPIO_A, 27, 1);
+}
+
+static void hd700_gpio_init(void)
+{
+	hd101_gpio_init();
+}
+
+/* NXP display configs for supported LCD */
+
+static struct nxp_lcd wxga_hd700 = {
+	.width = 800,
+	.height = 1280,
+	.p_width = 94,
+	.p_height = 151,
+	.bpp = 24,
+	.freq = 60,
+
+	.timing = {
+		.h_fp = 20,
+		.h_bp = 20,
+		.h_sw = 24,
+		.v_fp =  4,
+		.v_fpe = 1,
+		.v_bp =  4,
+		.v_bpe = 1,
+		.v_sw =  8,
+	},
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 0,
+		.inv_vsync = 0,
+		.inv_vden = 0,
+	},
+	.gpio_init = hd700_gpio_init,
+};
+
+static struct nxp_lcd wvga_s70 = {
+	.width = 800,
+	.height = 480,
+	.p_width = 155,
+	.p_height = 93,
+	.bpp = 24,
+	.freq = 61,
+
+	.timing = {
+		.h_fp = 48,
+		.h_bp = 36,
+		.h_sw = 10,
+		.v_fp = 22,
+		.v_fpe = 1,
+		.v_bp = 15,
+		.v_bpe = 1,
+		.v_sw = 8,
+	},
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+	.gpio_init = s70_gpio_init,
+};
+
+static struct nxp_lcd wvga_s702 = {
+	.width = 800,
+	.height = 480,
+	.p_width = 155,
+	.p_height = 93,
+	.bpp = 24,
+	.freq = 61,
+
+	.timing = {
+		.h_fp = 44,
+		.h_bp = 26,
+		.h_sw = 20,
+		.v_fp = 22,
+		.v_fpe = 1,
+		.v_bp = 15,
+		.v_bpe = 1,
+		.v_sw = 8,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+	.gpio_init = s702_gpio_init,
+};
+
+static struct nxp_lcd wvga_s70d = {
+	.width = 800,
+	.height = 480,
+	.p_width = 155,
+	.p_height = 93,
+	.bpp = 24,
+	.freq = 61,
+
+	.timing = {
+		.h_fp = 80,
+		.h_bp = 78,
+		.h_sw = 10,
+		.v_fp = 22,
+		.v_fpe = 1,
+		.v_bp = 24,
+		.v_bpe = 1,
+		.v_sw = 8,
+	},
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+	.gpio_init = s702_gpio_init,
+};
+
+static struct nxp_lcd wvga_w50 = {
+	.width = 800,
+	.height = 480,
+	.p_width = 108,
+	.p_height = 64,
+	.bpp = 24,
+	.freq = 61,
+
+	.timing = {
+		.h_fp = 40,
+		.h_bp = 40,
+		.h_sw = 48,
+		.v_fp = 20,
+		.v_fpe = 1,
+		.v_bp = 20,
+		.v_bpe = 1,
+		.v_sw = 12,
+	},
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+	.gpio_init = s70_gpio_init,
+};
+
+static struct nxp_lcd wvga_s430 = {
+	.width = 480,
+	.height = 800,
+	.p_width = 108,
+	.p_height = 64,
+	.bpp = 24,
+	.freq = 60,
+
+	.timing = {
+		.h_fp = 64,
+		.h_bp = 0,
+		.h_sw = 16,
+		.v_fp = 32,
+		.v_fpe = 1,
+		.v_bp = 0,
+		.v_bpe = 1,
+		.v_sw = 16,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+	.gpio_init = s430_gpio_init,
+};
+
+static struct nxp_lcd wsvga_w101 = {
+	.width = 1024,
+	.height = 600,
+	.p_width = 204,
+	.p_height = 120,
+	.bpp = 24,
+	.freq = 60,
+
+	.timing = {
+		.h_fp = 40,
+		.h_bp = 40,
+		.h_sw = 200,
+		.v_fp =  8,
+		.v_fpe = 1,
+		.v_bp =  8,
+		.v_bpe = 1,
+		.v_sw = 16,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+};
+
+static struct nxp_lcd wsvga_x710 = {
+	.width = 1024,
+	.height = 600,
+	.p_width = 154,
+	.p_height = 90,
+	.bpp = 24,
+	.freq = 61,
+
+	.timing = {
+		.h_fp = 84,
+		.h_bp = 84,
+		.h_sw = 88,
+		.v_fp = 10,
+		.v_fpe = 1,
+		.v_bp = 10,
+		.v_bpe = 1,
+		.v_sw = 20,
+	},
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+	.gpio_init = hd101_gpio_init,
+};
+
+static struct nxp_lcd xga_a97 = {
+	.width = 1024,
+	.height = 768,
+	.p_width = 200,
+	.p_height = 150,
+	.bpp = 24,
+	.freq = 61,
+
+	.timing = {
+		.h_fp = 12,
+		.h_bp = 12,
+		.h_sw = 4,
+		.v_fp = 8,
+		.v_fpe = 1,
+		.v_bp = 8,
+		.v_bpe = 1,
+		.v_sw =  4,
+	},
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+};
+
+static struct nxp_lcd xga_lq150 = {
+	.width = 1024,
+	.height = 768,
+	.p_width = 304,
+	.p_height = 228,
+	.bpp = 24,
+	.freq = 60,
+
+	.timing = {
+		.h_fp = 12,
+		.h_bp = 12,
+		.h_sw = 40,
+		.v_fp = 8,
+		.v_fpe = 1,
+		.v_bp = 8,
+		.v_bpe = 1,
+		.v_sw = 40,
+	},
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+};
+
+static struct nxp_lcd vga_l80 = {
+	.width = 640,
+	.height = 480,
+	.p_width = 160,
+	.p_height = 120,
+	.bpp = 32,
+	.freq = 60,
+
+	.timing = {
+		.h_fp = 35,
+		.h_bp = 53,
+		.h_sw = 73,
+		.v_fp = 3,
+		.v_fpe = 1,
+		.v_bp = 29,
+		.v_bpe = 1,
+		.v_sw = 6,
+	},
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+};
+
+static struct nxp_lcd wxga_bp101 = {
+	.width = 1280,
+	.height = 800,
+	.p_width = 218,
+	.p_height = 136,
+	.bpp = 24,
+	.freq = 60,
+
+	.timing = {
+		.h_fp = 20,
+		.h_bp = 20,
+		.h_sw = 24,
+		.v_fp =  4,
+		.v_fpe = 1,
+		.v_bp =  4,
+		.v_bpe = 1,
+		.v_sw =  8,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+};
+
+static struct nxp_lcd wxga_hd101 = {
+	.width = 1280,
+	.height = 800,
+	.p_width = 218,
+	.p_height = 136,
+	.bpp = 24,
+	.freq = 60,
+
+	.timing = {
+		.h_fp = 16,
+		.h_bp = 16,
+		.h_sw = 30,
+		.v_fp =  8,
+		.v_fpe = 1,
+		.v_bp =  8,
+		.v_bpe = 1,
+		.v_sw = 12,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 0,
+		.inv_vsync = 0,
+		.inv_vden = 0,
+	},
+	.gpio_init = hd101_gpio_init,
+};
+
+static struct nxp_lcd hvga_h43 = {
+	.width = 480,
+	.height = 272,
+	.p_width = 96,
+	.p_height = 54,
+	.bpp = 32,
+	.freq = 65,
+
+	.timing = {
+		.h_fp =  5,
+		.h_bp = 40,
+		.h_sw =  2,
+		.v_fp =  8,
+		.v_fpe = 1,
+		.v_bp =  8,
+		.v_bpe = 1,
+		.v_sw =  2,
+	},
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+};
+
+static struct nxp_lcd hvga_p43 = {
+	.width = 480,
+	.height = 272,
+	.p_width = 96,
+	.p_height = 54,
+	.bpp = 32,
+	.freq = 65,
+
+	.timing = {
+		.h_fp =  5,
+		.h_bp = 40,
+		.h_sw =  2,
+		.v_fp =  8,
+		.v_fpe = 1,
+		.v_bp =  9,
+		.v_bpe = 1,
+		.v_sw =  2,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+};
+
+static struct nxp_lcd qvga_w35 = {
+	.width = 320,
+	.height = 240,
+	.p_width = 70,
+	.p_height = 52,
+	.bpp = 16,
+	.freq = 65,
+
+	.timing = {
+		.h_fp =  4,
+		.h_bp = 70,
+		.h_sw =  4,
+		.v_fp =  4,
+		.v_fpe = 1,
+		.v_bp = 12,
+		.v_bpe = 1,
+		.v_sw =  4,
+	},
+	.polarity = {
+		.rise_vclk = 1,
+		.inv_hsync = 0,
+		.inv_vsync = 0,
+		.inv_vden = 0,
+	},
+};
+
+/* HDMI */
+static struct nxp_lcd hdmi_def = {
+	.width = 1920,
+	.height = 1080,
+	.p_width = 480,
+	.p_height = 320,
+	.bpp = 24,
+	.freq = 60,
+
+	.timing = {
+		.h_fp = 12,
+		.h_bp = 12,
+		.h_sw = 4,
+		.v_fp = 8,
+		.v_fpe = 1,
+		.v_bp = 8,
+		.v_bpe = 1,
+		.v_sw =  4,
+	},
+	.polarity = {
+		.rise_vclk = 0,
+		.inv_hsync = 1,
+		.inv_vsync = 1,
+		.inv_vden = 0,
+	},
+};
+
+static struct hdmi_config {
+	char *name;
+	int width;
+	int height;
+} bd_hdmi_config[] = {
+	{ "HDMI1080P60",	1920, 1080 },
+	{ "HDMI1080I60",	1920, 1080 },
+	{ "HDMI1080P30",	1920, 1080 },
+	{ "HDMI1080P50",	1920, 1080 },
+	{ "HDMI1080I50",	1920, 1080 },
+
+	{ "HDMI1080P60D",	 960,  536 },
+	{ "HDMI1080I60D",	 960,  536 },
+	{ "HDMI1080P30D",	 960,  536 },
+	{ "HDMI1080P50D",	 960,  536 },
+	{ "HDMI1080I50D",	 960,  536 },
+
+	{ "HDMI720P60",		1280,  720 },
+	{ "HDMI720P60D",	 640,  360 },
+	{ "HDMI720P50",		1280,  720 },
+	{ "HDMI720P50D",	 640,  360 },
+
+	{ "HDMI576P16X9",	 720,  576 },
+	{ "HDMI576P16X9D",	 720,  576 },
+	{ "HDMI576P4X3",	 720,  576 },
+	{ "HDMI576P4X3D",	 720,  576 },
+
+	{ "HDMI480P16X9",	 720,  480 },
+	{ "HDMI480P16X9D",	 720,  480 },
+	{ "HDMI480P4X3",	 720,  480 },
+	{ "HDMI480P4X3D",	 720,  480 },
+};
+
+/* Try to guess LCD panel by kernel command line, or
+ * using *HD101* as default
+ */
+static struct {
+	int id;
+	char *name;
+	struct nxp_lcd *lcd;
+	int dpi;
+	int ctp;
+	enum lcd_format fmt;
+} bd_lcd_config[] = {
+	{  25, "HD101",	 &wxga_hd101,   0, 1, LCD_RGB  },
+	{  32, "HD101B", &wxga_hd101,   0, 1, LCD_RGB  },
+	{  18, "HD700",	 &wxga_hd700, 213, 1, LCD_RGB  },
+	{  30, "HD702",	 &wxga_hd700, 213, 1, LCD_RGB  },
+	{  33, "H70",	 &wxga_hd700, 213, 0, LCD_VESA },
+	{   3, "S70",	 &wvga_s70,   128, 1, LCD_RGB  },
+	{  36, "S701",	 &wvga_s70,   128, 1, LCD_RGB  },
+	{  24, "S702",	 &wvga_s702,  128, 3, LCD_RGB  },
+	{  26, "S70D",	 &wvga_s70d,  128, 0, LCD_RGB  },
+	{  14, "H43",	 &hvga_h43,     0, 0, LCD_RGB  },
+	{  19, "P43",	 &hvga_p43,     0, 0, LCD_RGB  },
+	{   8, "W35",	 &qvga_w35,     0, 0, LCD_RGB  },
+	{  28, "X710",	 &wsvga_x710,   0, 1, LCD_RGB  },
+	{  31, "S430",	 &wvga_s430,  180, 1, LCD_RGB  },
+	{   4, "W50",	 &wvga_w50,     0, 0, LCD_RGB  },
+
+	/* TODO: Testing */
+	{  15, "W101",	 &wsvga_w101,   0, 1, LCD_RGB  },
+	{   5, "L80",	 &vga_l80,      0, 1, LCD_RGB  },
+	{  -1, "A97",	 &xga_a97,      0, 0, LCD_RGB  },
+	{  -1, "LQ150",	 &xga_lq150,    0, 1, LCD_RGB  },
+	{  -1, "BP101",	 &wxga_bp101,   0, 1, LCD_RGB  },
+	/* Pls keep it at last */
+	{ 128, "HDMI",	 &hdmi_def,     0, 0, LCD_HDMI },
+};
+
+static int lcd_idx;
+
+int bd_setup_lcd_by_id(int id)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(bd_lcd_config); i++) {
+		if (bd_lcd_config[i].id == id) {
+			lcd_idx = i;
+			break;
+		}
+	}
+
+	if (i >= ARRAY_SIZE(bd_lcd_config)) {
+		/* NOT found */
+		return -19;
+	}
+
+	return bd_lcd_config[i].id;
+}
+
+int bd_setup_lcd_by_name(char *str)
+{
+	char *delim;
+	int i;
+
+	delim = strchr(str, ',');
+	if (delim)
+		*delim++ = '\0';
+
+	if (!strncasecmp("HDMI", str, 4)) {
+		struct hdmi_config *cfg = &bd_hdmi_config[0];
+		struct nxp_lcd *lcd;
+
+		lcd_idx = ARRAY_SIZE(bd_lcd_config) - 1;
+		lcd = bd_lcd_config[lcd_idx].lcd;
+
+		for (i = 0; i < ARRAY_SIZE(bd_hdmi_config); i++, cfg++) {
+			if (!strcasecmp(cfg->name, str)) {
+				lcd->width = cfg->width;
+				lcd->height = cfg->height;
+				bd_lcd_config[lcd_idx].name = cfg->name;
+				goto __ret;
+			}
+		}
+	}
+
+	for (i = 0; i < ARRAY_SIZE(bd_lcd_config); i++) {
+		if (!strcasecmp(bd_lcd_config[i].name, str)) {
+			lcd_idx = i;
+			break;
+		}
+	}
+
+__ret:
+	return 0;
+}
+
+struct nxp_lcd *bd_get_lcd(void)
+{
+	return bd_lcd_config[lcd_idx].lcd;
+}
+
+const char *bd_get_lcd_name(void)
+{
+	return bd_lcd_config[lcd_idx].name;
+}
+
+enum lcd_format bd_get_lcd_format(void)
+{
+	return bd_lcd_config[lcd_idx].fmt;
+}
+
+int bd_get_lcd_density(void)
+{
+	return bd_lcd_config[lcd_idx].dpi;
+}
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+int bd_fixup_lcd_fdt(void *blob, struct nxp_lcd *lcd)
+{
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/friendlyarm/nanopi2/nxp-fb.h b/roms/u-boot/board/friendlyarm/nanopi2/nxp-fb.h
new file mode 100644
index 000000000..d31a03d7c
--- /dev/null
+++ b/roms/u-boot/board/friendlyarm/nanopi2/nxp-fb.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (c) 2017 FriendlyARM (www.arm9.net)
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Header file for NXP Display Driver
+ */
+
+#ifndef __MACH_NXP_FB_H__
+#define __MACH_NXP_FB_H__
+
+/*
+ * struct nxp_lcd_polarity
+ * @rise_vclk:	if 1, video data is fetched at rising edge
+ * @inv_hsync:	if HSYNC polarity is inversed
+ * @inv_vsync:	if VSYNC polarity is inversed
+ * @inv_vden:	if VDEN polarity is inversed
+ */
+struct nxp_lcd_polarity {
+	int	rise_vclk;
+	int	inv_hsync;
+	int	inv_vsync;
+	int	inv_vden;
+};
+
+/*
+ * struct nxp_lcd_timing
+ * @h_fp:	horizontal front porch
+ * @h_bp:	horizontal back porch
+ * @h_sw:	horizontal sync width
+ * @v_fp:	vertical front porch
+ * @v_fpe:	vertical front porch for even field
+ * @v_bp:	vertical back porch
+ * @v_bpe:	vertical back porch for even field
+ */
+struct nxp_lcd_timing {
+	int	h_fp;
+	int	h_bp;
+	int	h_sw;
+	int	v_fp;
+	int	v_fpe;
+	int	v_bp;
+	int	v_bpe;
+	int	v_sw;
+};
+
+/*
+ * struct nxp_lcd
+ * @width:		horizontal resolution
+ * @height:		vertical resolution
+ * @p_width:	width of lcd in mm
+ * @p_height:	height of lcd in mm
+ * @bpp:		bits per pixel
+ * @freq:		vframe frequency
+ * @timing:		timing values
+ * @polarity:	polarity settings
+ * @gpio_init:	pointer to GPIO init function
+ *
+ */
+struct nxp_lcd {
+	int	width;
+	int	height;
+	int	p_width;
+	int	p_height;
+	int	bpp;
+	int	freq;
+	struct	nxp_lcd_timing timing;
+	struct	nxp_lcd_polarity polarity;
+	void	(*gpio_init)(void);
+};
+
+/**
+ * Public interfaces
+ */
+enum lcd_format {
+	LCD_VESA	= 0,
+	LCD_JEIDA	= 1,
+	LCD_LOC		= 2,
+
+	LCD_RGB		= 4,
+	LCD_HDMI	= 5,
+};
+
+extern int bd_setup_lcd_by_id(int id);
+extern int bd_setup_lcd_by_name(char *name);
+extern struct nxp_lcd *bd_get_lcd(void);
+extern const char *bd_get_lcd_name(void);
+extern int bd_get_lcd_density(void);
+extern enum lcd_format bd_get_lcd_format(void);
+extern int bd_fixup_lcd_fdt(void *blob, struct nxp_lcd *cfg);
+
+#endif /* __MACH_NXP_FB_H__ */
diff --git a/roms/u-boot/board/friendlyarm/nanopi2/onewire.c b/roms/u-boot/board/friendlyarm/nanopi2/onewire.c
new file mode 100644
index 000000000..fb356639b
--- /dev/null
+++ b/roms/u-boot/board/friendlyarm/nanopi2/onewire.c
@@ -0,0 +1,307 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Guangzhou FriendlyARM Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <i2c.h>
+#include <pwm.h>
+
+#include <irq_func.h>
+
+#include <asm/arch/nexell.h>
+#include <asm/arch/nx_gpio.h>
+
+#ifndef NSEC_PER_SEC
+#define NSEC_PER_SEC	1000000000L
+#endif
+
+#define SAMPLE_BPS		9600
+#define SAMPLE_IN_US	101		/* (1000000 / BPS) */
+
+#define REQ_INFO		0x60U
+#define REQ_BL			0x80U
+
+#define BUS_I2C			0x18
+#define ONEWIRE_I2C_BUS		2
+#define ONEWIRE_I2C_ADDR	0x2f
+
+static int bus_type = -1;
+static int lcd_id = -1;
+static unsigned short lcd_fwrev;
+static int current_brightness = -1;
+#if CONFIG_IS_ENABLED(DM_I2C)
+static struct udevice *i2c_dev;
+#endif
+
+/* debug */
+#if (0)
+#define DBGOUT(msg...)	do { printf("onewire: " msg); } while (0)
+#else
+#define DBGOUT(msg...)	do {} while (0)
+#endif
+
+/* based on web page from http://lfh1986.blogspot.com */
+static unsigned char crc8_ow(unsigned int v, unsigned int len)
+{
+	unsigned char crc = 0xACU;
+
+	while (len--) {
+		if ((crc & 0x80U) != 0) {
+			crc <<= 1;
+			crc ^= 0x7U;
+		} else {
+			crc <<= 1;
+		}
+		if ((v & (1U << 31)) != 0)
+			crc ^= 0x7U;
+		v <<= 1;
+	}
+	return crc;
+}
+
+/* GPIO helpers */
+#define __IO_GRP		2	/* GPIOC15 */
+#define __IO_IDX		15
+
+static inline void set_pin_as_input(void)
+{
+	nx_gpio_set_output_enable(__IO_GRP, __IO_IDX, 0);
+}
+
+static inline void set_pin_as_output(void)
+{
+	nx_gpio_set_output_enable(__IO_GRP, __IO_IDX, 1);
+}
+
+static inline void set_pin_value(int v)
+{
+	nx_gpio_set_output_value(__IO_GRP, __IO_IDX, !!v);
+}
+
+static inline int get_pin_value(void)
+{
+	return nx_gpio_get_input_value(__IO_GRP, __IO_IDX);
+}
+
+/* Timer helpers */
+#define PWM_CH				3
+#define PWM_TCON			(PHY_BASEADDR_PWM + 0x08)
+#define PWM_TCON_START		(1 << 16)
+#define PWM_TINT_CSTAT		(PHY_BASEADDR_PWM + 0x44)
+
+static int onewire_init_timer(void)
+{
+	int period_ns = NSEC_PER_SEC / SAMPLE_BPS;
+
+	/* range: 1080~1970 */
+	period_ns -= 1525;
+
+	return pwm_config(PWM_CH, period_ns >> 1, period_ns);
+}
+
+static void wait_one_tick(void)
+{
+	unsigned int tcon;
+
+	tcon = readl(PWM_TCON);
+	tcon |= PWM_TCON_START;
+	writel(tcon, PWM_TCON);
+
+	while (1) {
+		if (readl(PWM_TINT_CSTAT) & (1 << (5 + PWM_CH)))
+			break;
+	}
+
+	writel((1 << (5 + PWM_CH)), PWM_TINT_CSTAT);
+
+	tcon &= ~PWM_TCON_START;
+	writel(tcon, PWM_TCON);
+}
+
+/* Session handler */
+static int onewire_session(unsigned char req, unsigned char res[])
+{
+	unsigned int Req;
+	unsigned int *Res;
+	int ints = disable_interrupts();
+	int i;
+	int ret;
+
+	Req = (req << 24) | (crc8_ow(req << 24, 8) << 16);
+	Res = (unsigned int *)res;
+
+	set_pin_value(1);
+	set_pin_as_output();
+	for (i = 0; i < 60; i++)
+		wait_one_tick();
+
+	set_pin_value(0);
+	for (i = 0; i < 2; i++)
+		wait_one_tick();
+
+	for (i = 0; i < 16; i++) {
+		int v = !!(Req & (1U << 31));
+
+		Req <<= 1;
+		set_pin_value(v);
+		wait_one_tick();
+	}
+
+	wait_one_tick();
+	set_pin_as_input();
+	wait_one_tick();
+	for (i = 0; i < 32; i++) {
+		(*Res) <<= 1;
+		(*Res) |= get_pin_value();
+		wait_one_tick();
+	}
+	set_pin_value(1);
+	set_pin_as_output();
+
+	if (ints)
+		enable_interrupts();
+
+	ret = crc8_ow(*Res, 24) == res[0];
+	DBGOUT("req = %02X, res = %02X%02X%02X%02X, ret = %d\n",
+	       req, res[3], res[2], res[1], res[0], ret);
+
+	return ret;
+}
+
+static int onewire_i2c_do_request(unsigned char req, unsigned char *buf)
+{
+	unsigned char tx[4];
+	int ret;
+
+	tx[0] = req;
+	tx[1] = crc8_ow(req << 24, 8);
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	if (dm_i2c_write(i2c_dev, 0, tx, 2))
+		return -EIO;
+
+	if (!buf)
+		return 0;
+
+	if (dm_i2c_read(i2c_dev, 0, buf, 4))
+		return -EIO;
+#else
+	if (i2c_write(ONEWIRE_I2C_ADDR, 0, 0, tx, 2))
+		return -EIO;
+
+	if (!buf) /* NO READ */
+		return 0;
+
+	if (i2c_read(ONEWIRE_I2C_ADDR, 0, 0, buf, 4))
+		return -EIO;
+#endif
+
+	ret = crc8_ow((buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8), 24);
+	DBGOUT("req = %02X, res = %02X%02X%02X%02X, ret = %02x\n",
+	       req, buf[0], buf[1], buf[2], buf[3], ret);
+
+	return (ret == buf[3]) ? 0 : -EIO;
+}
+
+static void onewire_i2c_init(void)
+{
+	unsigned char buf[4];
+	int ret;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	ret = i2c_get_chip_for_busnum(ONEWIRE_I2C_BUS,
+				      ONEWIRE_I2C_ADDR, 0, &i2c_dev);
+#else
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_set_bus_num(ONEWIRE_I2C_BUS);
+
+	ret = i2c_probe(ONEWIRE_I2C_ADDR);
+#endif
+	if (ret)
+		return;
+
+	ret = onewire_i2c_do_request(REQ_INFO, buf);
+	if (!ret) {
+		lcd_id = buf[0];
+		lcd_fwrev = buf[1] * 0x100 + buf[2];
+		bus_type = BUS_I2C;
+	}
+}
+
+void onewire_init(void)
+{
+	/* GPIO, Pull-off */
+	nx_gpio_set_pad_function(__IO_GRP, __IO_IDX, 1);
+	nx_gpio_set_pull_mode(__IO_GRP, __IO_IDX, 2);
+
+	onewire_init_timer();
+	onewire_i2c_init();
+}
+
+int onewire_get_info(unsigned char *lcd, unsigned short *fw_ver)
+{
+	unsigned char res[4];
+	int i;
+
+	if (bus_type == BUS_I2C && lcd_id > 0) {
+		*lcd = lcd_id;
+		*fw_ver = lcd_fwrev;
+		return 0;
+	}
+
+	for (i = 0; i < 3; i++) {
+		if (onewire_session(REQ_INFO, res)) {
+			*lcd = res[3];
+			*fw_ver = res[2] * 0x100 + res[1];
+			lcd_id = *lcd;
+			DBGOUT("lcd = %d, fw_ver = %x\n", *lcd, *fw_ver);
+			return 0;
+		}
+	}
+
+	/* LCD unknown or not connected */
+	*lcd = 0;
+	*fw_ver = -1;
+
+	return -1;
+}
+
+int onewire_get_lcd_id(void)
+{
+	return lcd_id;
+}
+
+int onewire_set_backlight(int brightness)
+{
+	unsigned char res[4];
+	int i;
+
+	if (brightness == current_brightness)
+		return 0;
+
+	if (brightness > 127)
+		brightness = 127;
+	else if (brightness < 0)
+		brightness = 0;
+
+	if (bus_type == BUS_I2C) {
+		onewire_i2c_do_request((REQ_BL | brightness), NULL);
+		current_brightness = brightness;
+		return 0;
+	}
+
+	for (i = 0; i < 3; i++) {
+		if (onewire_session((REQ_BL | brightness), res)) {
+			current_brightness = brightness;
+			return 0;
+		}
+	}
+
+	return -1;
+}
diff --git a/roms/u-boot/board/friendlyarm/nanopi2/onewire.h b/roms/u-boot/board/friendlyarm/nanopi2/onewire.h
new file mode 100644
index 000000000..9f6d7cfe5
--- /dev/null
+++ b/roms/u-boot/board/friendlyarm/nanopi2/onewire.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) Guangzhou FriendlyARM Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+#ifndef __ONE_WIRE_H__
+#define __ONE_WIRE_H__
+
+extern void onewire_init(void);
+extern int  onewire_get_info(unsigned char *lcd, unsigned short *fw_ver);
+extern int  onewire_get_lcd_id(void);
+extern int  onewire_set_backlight(int brightness);
+
+#endif /* __ONE_WIRE_H__ */
diff --git a/roms/u-boot/board/gardena/smart-gateway-at91sam/Kconfig b/roms/u-boot/board/gardena/smart-gateway-at91sam/Kconfig
new file mode 100644
index 000000000..ea2b5ff4e
--- /dev/null
+++ b/roms/u-boot/board/gardena/smart-gateway-at91sam/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GARDENA_SMART_GATEWAY_AT91SAM
+
+config SYS_BOARD
+	default "smart-gateway-at91sam"
+
+config SYS_VENDOR
+	default "gardena"
+
+config SYS_CONFIG_NAME
+	default "gardena-smart-gateway-at91sam"
+
+endif
diff --git a/roms/u-boot/board/gardena/smart-gateway-at91sam/MAINTAINERS b/roms/u-boot/board/gardena/smart-gateway-at91sam/MAINTAINERS
new file mode 100644
index 000000000..a5e4c71b8
--- /dev/null
+++ b/roms/u-boot/board/gardena/smart-gateway-at91sam/MAINTAINERS
@@ -0,0 +1,7 @@
+GARDENA_SMART_GATEWAY_AT91SAM BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/gardena/smart-gateway-at91sam/
+F:	include/configs/gardena-smart-gateway-at91sam.h
+F:	configs/gardena-smart-gateway-at91sam_defconfig
+F:	arch/arm/dts/gardena-smart-gateway-at91sam.dts
diff --git a/roms/u-boot/board/gardena/smart-gateway-at91sam/Makefile b/roms/u-boot/board/gardena/smart-gateway-at91sam/Makefile
new file mode 100644
index 000000000..a2ed79fd0
--- /dev/null
+++ b/roms/u-boot/board/gardena/smart-gateway-at91sam/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += board.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/roms/u-boot/board/gardena/smart-gateway-at91sam/board.c b/roms/u-boot/board/gardena/smart-gateway-at91sam/board.c
new file mode 100644
index 000000000..3f402cfee
--- /dev/null
+++ b/roms/u-boot/board/gardena/smart-gateway-at91sam/board.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ * Copyright (C) 2019 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <env.h>
+#include <init.h>
+#include <led.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/clk.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void at91_prepare_cpu_var(void)
+{
+	env_set("cpu", get_cpu_name());
+}
+
+int board_late_init(void)
+{
+	at91_prepare_cpu_var();
+
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	return 0;
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	at91_seriald_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/gardena/smart-gateway-at91sam/spl.c b/roms/u-boot/board/gardena/smart-gateway-at91sam/spl.c
new file mode 100644
index 000000000..3ab6760df
--- /dev/null
+++ b/roms/u-boot/board/gardena/smart-gateway-at91sam/spl.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ * Copyright (C) 2019 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <spl.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+
+static void at91sam9x5ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+
+	/* NAND flash on D16 */
+	csa |= AT91_MATRIX_NFD0_ON_D16;
+
+	/* Configure IO drive */
+	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(1),
+	       &smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOCD);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* NAND ALE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);	/* NAND CLE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
+}
+
+void at91_spl_board_init(void)
+{
+	at91sam9x5ek_nand_hw_init();
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_13 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct atmel_mpddrc_config ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* Enable DDR2 clock */
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+	csa |= AT91_MATRIX_EBI_DBPD_OFF;
+	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+	writel(csa, &matrix->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
+}
diff --git a/roms/u-boot/board/gardena/smart-gateway-mt7688/Kconfig b/roms/u-boot/board/gardena/smart-gateway-mt7688/Kconfig
new file mode 100644
index 000000000..3653f8aad
--- /dev/null
+++ b/roms/u-boot/board/gardena/smart-gateway-mt7688/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_GARDENA_SMART_GATEWAY_MT7688
+
+config SYS_BOARD
+	default "smart-gateway-mt7688"
+
+config SYS_VENDOR
+	default "gardena"
+
+config SYS_CONFIG_NAME
+	default "gardena-smart-gateway-mt7688"
+
+endif
diff --git a/roms/u-boot/board/gardena/smart-gateway-mt7688/MAINTAINERS b/roms/u-boot/board/gardena/smart-gateway-mt7688/MAINTAINERS
new file mode 100644
index 000000000..bbb491c1c
--- /dev/null
+++ b/roms/u-boot/board/gardena/smart-gateway-mt7688/MAINTAINERS
@@ -0,0 +1,8 @@
+GARDENA_SMART_GATEWAY_MT7688 BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/gardena/smart-gateway-mt7688
+F:	include/configs/gardena-smart-gateway-mt7688.h
+F:	configs/gardena-smart-gateway-mt7688_defconfig
+F:	configs/gardena-smart-gateway-mt7688-ram_defconfig
+F:	arch/mips/dts/gardena-smart-gateway-mt7688.dts
diff --git a/roms/u-boot/board/gardena/smart-gateway-mt7688/Makefile b/roms/u-boot/board/gardena/smart-gateway-mt7688/Makefile
new file mode 100644
index 000000000..70cd7a8e5
--- /dev/null
+++ b/roms/u-boot/board/gardena/smart-gateway-mt7688/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += board.o
diff --git a/roms/u-boot/board/gardena/smart-gateway-mt7688/board.c b/roms/u-boot/board/gardena/smart-gateway-mt7688/board.c
new file mode 100644
index 000000000..8a3a6e348
--- /dev/null
+++ b/roms/u-boot/board/gardena/smart-gateway-mt7688/board.c
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <env_internal.h>
+#include <flash.h>
+#include <init.h>
+#include <led.h>
+#include <log.h>
+#include <malloc.h>
+#include <net.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <linux/delay.h>
+#include <linux/stringify.h>
+#include <u-boot/crc.h>
+#include <uuid.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+
+#define MT76XX_AGPIO_CFG	0x1000003c
+
+#define FACTORY_DATA_OFFS	0xc0000
+#define FACTORY_DATA_SECT_SIZE	0x10000
+#if ((CONFIG_ENV_OFFSET_REDUND + CONFIG_ENV_SIZE) > FACTORY_DATA_OFFS)
+#error "U-Boot image with environment too big (overlapping with factory-data)!"
+#endif
+#define FACTORY_DATA_USER_OFFS	0x140
+#define FACTORY_DATA_SIZE	0x1f0
+#define FACTORY_DATA_CRC_LEN	(FACTORY_DATA_SIZE -			\
+				 FACTORY_DATA_USER_OFFS - sizeof(u32))
+
+#define FACTORY_DATA_MAGIC	0xCAFEBABE
+
+struct factory_data_values {
+	u8 pad_1[4];
+	u8 wifi_mac[6];		/* offs: 0x004: binary value */
+	u8 pad_2[30];
+	u8 eth_mac[6];		/* offs: 0x028: binary value */
+	u8 pad_3[FACTORY_DATA_USER_OFFS - 4 - 6 - 30 - 6];
+	/* User values start here at offset 0x140 */
+	u32 crc;
+	u32 magic;
+	u32 version;
+	char ipr_id[UUID_STR_LEN];	/* UUID as string w/o ending \0 */
+	char hqv_id[UUID_STR_LEN];	/* UUID as string w/o ending \0 */
+	char unielec_id[UUID_STR_LEN];	/* UUID as string w/o ending \0 */
+};
+
+int board_early_init_f(void)
+{
+	void __iomem *gpio_mode;
+
+	/* Configure digital vs analog GPIOs */
+	gpio_mode = ioremap_nocache(MT76XX_AGPIO_CFG, 0x100);
+	iowrite32(0x00fe01ff, gpio_mode);
+
+	return 0;
+}
+
+static bool prepare_uuid_var(const char *fd_ptr, const char *env_var_name,
+			     char errorchar)
+{
+	char str[UUID_STR_LEN + 1] = { 0 };	/* Enough for UUID stuff */
+	bool env_updated = false;
+	char *env;
+	int i;
+
+	memcpy(str, fd_ptr, UUID_STR_LEN);
+
+	/* Convert non-ascii character to 'X' */
+	for (i = 0; i < UUID_STR_LEN; i++) {
+		if (!(isascii(str[i]) && isprint(str[i])))
+			str[i] = errorchar;
+	}
+
+	env = env_get(env_var_name);
+	if (strcmp(env, str)) {
+		env_set(env_var_name, str);
+		env_updated = true;
+	}
+
+	return env_updated;
+}
+
+static void factory_data_env_config(void)
+{
+	struct factory_data_values *fd;
+	struct spi_flash *sf;
+	int env_updated = 0;
+	char str[UUID_STR_LEN + 1];	/* Enough for UUID stuff */
+	char *env;
+	u8 *buf;
+	u32 crc;
+	int ret;
+	u8 *ptr;
+
+	buf = malloc(FACTORY_DATA_SIZE);
+	if (!buf) {
+		printf("F-Data:Unable to allocate buffer\n");
+		return;
+	}
+
+	/*
+	 * Get values from factory-data area in SPI NOR
+	 */
+	sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
+			     CONFIG_SF_DEFAULT_CS,
+			     CONFIG_SF_DEFAULT_SPEED,
+			     CONFIG_SF_DEFAULT_MODE);
+	if (!sf) {
+		printf("F-Data:Unable to access SPI NOR flash\n");
+		goto err_free;
+	}
+
+	ret = spi_flash_read(sf, FACTORY_DATA_OFFS, FACTORY_DATA_SIZE,
+			     (void *)buf);
+	if (ret) {
+		printf("F-Data:Unable to read factory-data from SPI NOR\n");
+		goto err_spi_flash;
+	}
+
+	fd = (struct factory_data_values *)buf;
+
+	if (fd->magic != FACTORY_DATA_MAGIC)
+		printf("F-Data:Magic value not correct\n");
+
+	crc = crc32(0, (u8 *)&fd->magic, FACTORY_DATA_CRC_LEN);
+	if (crc != fd->crc)
+		printf("F-Data:CRC not correct\n");
+	else
+		printf("F-Data:factory-data version %x detected\n",
+		       fd->version);
+
+	/* Handle wifi_mac env variable */
+	ptr = fd->wifi_mac;
+	sprintf(str, "%pM", ptr);
+	if (!is_valid_ethaddr(ptr))
+		printf("F-Data:Invalid MAC addr: wifi_mac %s\n", str);
+
+	env = env_get("wifiaddr");
+	if (strcmp(env, str)) {
+		env_set("wifiaddr", str);
+		env_updated = 1;
+	}
+
+	/* Handle eth_mac env variable */
+	ptr = fd->eth_mac;
+	sprintf(str, "%pM", ptr);
+	if (!is_valid_ethaddr(ptr))
+		printf("F-Data:Invalid MAC addr: eth_mac %s\n", str);
+
+	env = env_get("ethaddr");
+	if (strcmp(env, str)) {
+		env_set("ethaddr", str);
+		env_updated = 1;
+	}
+
+	/* Handle UUID env variables */
+	env_updated |= prepare_uuid_var(fd->ipr_id, "linuxmoduleid", 'X');
+	env_updated |= prepare_uuid_var(fd->hqv_id, "linuxmodulehqvid", '\0');
+	env_updated |= prepare_uuid_var(fd->unielec_id,
+					"linuxmoduleunielecid", '\0');
+
+	/* Check if the environment was updated and needs to get stored */
+	if (env_updated != 0) {
+		printf("F-Data:Values don't match env values -> saving\n");
+		env_save();
+	} else {
+		debug("F-Data:Values match current env values\n");
+	}
+
+err_spi_flash:
+	spi_flash_free(sf);
+
+err_free:
+	free(buf);
+}
+
+int board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	factory_data_env_config();
+
+	return 0;
+}
+
+static void copy_or_generate_uuid(char *fd_ptr, const char *env_var_name)
+{
+	char str[UUID_STR_LEN + 1] = { 0 };	/* Enough for UUID stuff */
+	char *env;
+
+	/* Don't use the UUID dest place, as the \0 char won't fit */
+	env = env_get(env_var_name);
+	if (env)
+		strncpy(str, env, UUID_STR_LEN);
+	else
+		gen_rand_uuid_str(str, UUID_STR_FORMAT_STD);
+
+	memcpy(fd_ptr, str, UUID_STR_LEN);
+}
+
+/*
+ * Helper function to provide some sane factory-data values for testing
+ * purpose, when these values are not programmed correctly
+ */
+int do_fd_write(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	struct factory_data_values *fd;
+	struct spi_flash *sf;
+	u8 *buf;
+	int ret = CMD_RET_FAILURE;
+
+	buf = malloc(FACTORY_DATA_SECT_SIZE);
+	if (!buf) {
+		printf("F-Data:Unable to allocate buffer\n");
+		return CMD_RET_FAILURE;
+	}
+
+	sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
+			     CONFIG_SF_DEFAULT_CS,
+			     CONFIG_SF_DEFAULT_SPEED,
+			     CONFIG_SF_DEFAULT_MODE);
+	if (!sf) {
+		printf("F-Data:Unable to access SPI NOR flash\n");
+		goto err_free;
+	}
+
+	/* Generate the factory-data struct */
+
+	/* Fist read complete sector into buffer */
+	ret = spi_flash_read(sf, FACTORY_DATA_OFFS, FACTORY_DATA_SECT_SIZE,
+			     (void *)buf);
+	if (ret) {
+		printf("F-Data:spi_flash_read failed (%d)\n", ret);
+		goto err_spi_flash;
+	}
+
+	fd = (struct factory_data_values *)buf;
+	fd->magic = FACTORY_DATA_MAGIC;
+	fd->version = 0x1;
+
+	/* Use existing MAC and UUID values or generate some random ones */
+	if (!eth_env_get_enetaddr("wifiaddr", fd->wifi_mac)) {
+		net_random_ethaddr(fd->wifi_mac);
+		/* to get a different seed value for the MAC address */
+		mdelay(10);
+	}
+
+	if (!eth_env_get_enetaddr("ethaddr", fd->eth_mac))
+		net_random_ethaddr(fd->eth_mac);
+
+	copy_or_generate_uuid(fd->ipr_id, "linuxmoduleid");
+	copy_or_generate_uuid(fd->hqv_id, "linuxmodulehqvid");
+	copy_or_generate_uuid(fd->unielec_id, "linuxmoduleunielecid");
+
+	printf("New factory-data values:\n");
+	printf("wifiaddr=%pM\n", fd->wifi_mac);
+	printf("ethaddr=%pM\n", fd->eth_mac);
+
+	/*
+	 * We don't have the \0 char at the end, so we need to specify the
+	 * length in the printf format instead
+	 */
+	printf("linuxmoduleid=%." __stringify(UUID_STR_LEN) "s\n", fd->ipr_id);
+	printf("linuxmodulehqvid=%." __stringify(UUID_STR_LEN) "s\n",
+	       fd->hqv_id);
+	printf("linuxmoduleunielecid=%." __stringify(UUID_STR_LEN) "s\n",
+	       fd->unielec_id);
+
+	fd->crc = crc32(0, (u8 *)&fd->magic, FACTORY_DATA_CRC_LEN);
+
+	ret = spi_flash_erase(sf, FACTORY_DATA_OFFS, FACTORY_DATA_SECT_SIZE);
+	if (ret) {
+		printf("F-Data:spi_flash_erase failed (%d)\n", ret);
+		goto err_spi_flash;
+	}
+
+	ret = spi_flash_write(sf, FACTORY_DATA_OFFS, FACTORY_DATA_SECT_SIZE,
+			      buf);
+	if (ret) {
+		printf("F-Data:spi_flash_write failed (%d)\n", ret);
+		goto err_spi_flash;
+	}
+
+	printf("F-Data:factory-data values written to SPI NOR flash\n");
+
+err_spi_flash:
+	spi_flash_free(sf);
+
+err_free:
+	free(buf);
+
+	return ret;
+}
+
+#ifndef CONFIG_SPL_BUILD
+U_BOOT_CMD(
+	fd_write,	1,	0,	do_fd_write,
+	"Write test factory-data values to SPI NOR",
+	"\n"
+);
+#endif
diff --git a/roms/u-boot/board/gateworks/gw_ventana/Kconfig b/roms/u-boot/board/gateworks/gw_ventana/Kconfig
new file mode 100644
index 000000000..fee910ca8
--- /dev/null
+++ b/roms/u-boot/board/gateworks/gw_ventana/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_GW_VENTANA
+
+config DM_GPIO
+	default y
+
+config SYS_BOARD
+	default "gw_ventana"
+
+config SYS_VENDOR
+	default "gateworks"
+
+config SYS_CONFIG_NAME
+	default "gw_ventana"
+
+config CMD_EECONFIG
+	bool "Enable the 'econfig' command"
+	help
+	  Provides access to EEPROM configuration on Gateworks Ventana
+
+config CMD_GSC
+	bool "Enable the 'gsc' command"
+	help
+	  Provides access to the GSC configuration:
+
+	     gsc sleep - sleeps for a period of seconds
+	     gsc wd - enables / disables the watchdog
+
+endif
diff --git a/roms/u-boot/board/gateworks/gw_ventana/MAINTAINERS b/roms/u-boot/board/gateworks/gw_ventana/MAINTAINERS
new file mode 100644
index 000000000..1619d23c8
--- /dev/null
+++ b/roms/u-boot/board/gateworks/gw_ventana/MAINTAINERS
@@ -0,0 +1,56 @@
+GW_VENTANA BOARD
+M:	Tim Harvey <tharvey@gateworks.com>
+S:	Maintained
+F:	board/gateworks/gw_ventana/
+F:	include/configs/gw_ventana.h
+F:	configs/gwventana_nand_defconfig
+F:	configs/gwventana_emmc_defconfig
+F:	configs/gwventana_gw5904_defconfig
+F:	arch/arm/dts/imx6dl-gw51xx.dts
+F:	arch/arm/dts/imx6dl-gw52xx.dts
+F:	arch/arm/dts/imx6dl-gw53xx.dts
+F:	arch/arm/dts/imx6dl-gw54xx.dts
+F:	arch/arm/dts/imx6dl-gw551x.dts
+F:	arch/arm/dts/imx6dl-gw552x.dts
+F:	arch/arm/dts/imx6dl-gw553x.dts
+F:	arch/arm/dts/imx6dl-gw560x.dts
+F:	arch/arm/dts/imx6dl-gw5903.dts
+F:	arch/arm/dts/imx6dl-gw5904.dts
+F:	arch/arm/dts/imx6dl-gw5905.dts
+F:	arch/arm/dts/imx6dl-gw5907.dts
+F:	arch/arm/dts/imx6dl-gw5910.dts
+F:	arch/arm/dts/imx6dl-gw5912.dts
+F:	arch/arm/dts/imx6dl-gw5913.dts
+F:	arch/arm/dts/imx6qdl-gw51xx.dtsi
+F:	arch/arm/dts/imx6qdl-gw52xx.dtsi
+F:	arch/arm/dts/imx6qdl-gw53xx.dtsi
+F:	arch/arm/dts/imx6qdl-gw54xx.dtsi
+F:	arch/arm/dts/imx6qdl-gw551x.dtsi
+F:	arch/arm/dts/imx6qdl-gw552x.dtsi
+F:	arch/arm/dts/imx6qdl-gw553x.dtsi
+F:	arch/arm/dts/imx6qdl-gw560x.dtsi
+F:	arch/arm/dts/imx6qdl-gw5903.dtsi
+F:	arch/arm/dts/imx6qdl-gw5904.dtsi
+F:	arch/arm/dts/imx6qdl-gw5905.dtsi
+F:	arch/arm/dts/imx6qdl-gw5907.dtsi
+F:	arch/arm/dts/imx6qdl-gw5910.dtsi
+F:	arch/arm/dts/imx6qdl-gw5912.dtsi
+F:	arch/arm/dts/imx6qdl-gw5913.dtsi
+F:	arch/arm/dts/imx6q-gw51xx.dts
+F:	arch/arm/dts/imx6q-gw52xx.dts
+F:	arch/arm/dts/imx6q-gw53xx.dts
+F:	arch/arm/dts/imx6q-gw5400-a.dts
+F:	arch/arm/dts/imx6q-gw54xx.dts
+F:	arch/arm/dts/imx6q-gw551x.dts
+F:	arch/arm/dts/imx6q-gw552x.dts
+F:	arch/arm/dts/imx6q-gw553x.dts
+F:	arch/arm/dts/imx6q-gw560x.dts
+F:	arch/arm/dts/imx6q-gw5901.dts
+F:	arch/arm/dts/imx6q-gw5902.dts
+F:	arch/arm/dts/imx6q-gw5903.dts
+F:	arch/arm/dts/imx6q-gw5904.dts
+F:	arch/arm/dts/imx6q-gw5905.dts
+F:	arch/arm/dts/imx6q-gw5907.dts
+F:	arch/arm/dts/imx6q-gw5910.dts
+F:	arch/arm/dts/imx6q-gw5912.dts
+F:	arch/arm/dts/imx6q-gw5913.dts
diff --git a/roms/u-boot/board/gateworks/gw_ventana/Makefile b/roms/u-boot/board/gateworks/gw_ventana/Makefile
new file mode 100644
index 000000000..8fa691aef
--- /dev/null
+++ b/roms/u-boot/board/gateworks/gw_ventana/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Gateworks Corporation
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+obj-y  := gw_ventana.o gsc.o eeprom.o common.o
+obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o
+
diff --git a/roms/u-boot/board/gateworks/gw_ventana/README b/roms/u-boot/board/gateworks/gw_ventana/README
new file mode 100644
index 000000000..57c64a1b2
--- /dev/null
+++ b/roms/u-boot/board/gateworks/gw_ventana/README
@@ -0,0 +1,320 @@
+U-Boot for the Gateworks Ventana Product Family boards
+
+This file contains information for the port of U-Boot to the Gateworks
+Ventana Product family boards.
+
+The entire Ventana product family (http://www.gateworks.com/product#ventana)
+is supported by a single bootloader build by using a common SPL and U-Boot
+that dynamically determines the characterstics of the board at runtime via
+information from an EEPROM on the board programmed at the factory and supports
+all of the various boot mediums available.
+
+1. Secondary Program Loader (SPL)
+---------------------------------
+
+The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading
+an executable image from various boot devices.
+
+The Gateworks Ventana board config uses an SPL build configuration. This
+will build the following artifacts from U-Boot source:
+ - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program
+         Loader) boots.  This detects CPU/DRAM configuration, configures
+         The DRAM controller, loads u-boot.img from the detected boot device,
+         and jumps to it.  As this is booted from the PPL, it has an IVT/DCD
+         table.
+ - u-boot.img - The main U-Boot core which is u-boot.bin with a image header.
+
+
+2. Build
+--------
+
+To build U-Boot for the Gateworks Ventana product family:
+
+For NAND FLASH based boards:
+ make gwventana_nand_config
+ make
+
+For EMMC FLASH based boards:
+ make gwventana_emmc_config
+ make
+
+
+3. Boot source:
+---------------
+
+The Gateworks Ventana boards support booting from NAND or micro-SD depending
+on the board model. The IMX6 BOOT ROM will choose a boot media based on eFUSE
+settings programmed at the factory.
+
+Boards with NAND flash will always boot from NAND, and NAND-less boards will
+always boot from micro-SD. However, it is possible to use the U-Boot bmode
+command (or the technique it uses) to essentially bootstrap to another boot
+media at runtime.
+
+3.1. boot from NAND
+-------------------
+
+The i.MX6 BOOT ROM expects some structures that provide details of NAND layout
+and bad block information (referred to as 'bootstreams') which are replicated
+multiple times in NAND. The number of replications and their spacing (referred
+to as search stride) is configurable through board strapping options and/or
+eFUSE settings (BOOT_SEARCH_COUNT / Pages in block from BOOT_CFG2). In
+addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two
+copies of a bootloader in flash in the case that a bad block has corrupted one.
+The Freescale 'kobs-ng' application from the Freescale LTIB BSP, which runs
+under Linux and operates on an MTD partition, must be used to program the
+bootstream in order to setup this flash structure correctly.
+
+The Gateworks Ventana boards with NAND flash have been factory programmed
+such that their eFUSE settings expect 2 copies of the boostream (this is
+specified by providing kobs-ng with the --search_exponent=1 argument). Once in
+Linux with MTD support for the NAND on /dev/mtd0 you can program the SPL
+with:
+
+kobs-ng init -v -x --search_exponent=1 SPL
+
+The kobs-ng application uses an imximage which contains the Image Vector Table
+(IVT) and Device Configuration Data (DCD) structures that the i.MX6 BOOT ROM
+requires to boot.  The kobs-ng adds the Firmware Configuration Block (FCB) and
+Discovered Bad Block Table (DBBT).  The SPL build artifact from U-Boot is
+an imximage.
+
+The u-boot.img, which is the non SPL U-Boot binary appended to a U-Boot image
+header must be programmed in the NAND flash boot device at an offset hard
+coded in the SPL. For the Ventana boards, this has been chosen to be 14MB.
+The image can be programmed from either U-Boot or Linux:
+
+U-Boot:
+Ventana > setenv mtdparts mtdparts=nand:14m(spl),2m(uboot),1m(env),-(rootfs)
+Ventana > tftp ${loadaddr} u-boot.img && nand erase.part uboot && \
+          nand write ${loadaddr} uboot ${filesize}
+
+Linux:
+nandwrite /dev/mtd1 u-boot.img
+
+The above assumes the default Ventana partitioning scheme which is configured
+via the mtdparts env var:
+ - spl: 14MB
+ - uboot: 2M
+ - env: 1M
+ - rootfs: the rest
+
+This information is taken from:
+  http://trac.gateworks.com/wiki/ventana/bootloader#nand
+
+More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
+
+3.1. boot from MMC (eMMC/microSD)
+---------------------------------
+
+When the IMX6 eFUSE settings have been factory programmed to boot from
+MMC the SPL will be loaded from offset 0x400 (1KB). Once the SPL is
+booted, it will load and execute U-Boot (u-boot.img) from offset 69KB
+on the micro-SD (defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR).
+
+While it is technically possible to enable the SPL to be able to load
+U-Boot from a file on a FAT/EXT filesystem on the micro-SD, we chose to
+use raw micro-SD access to keep the code-size and boot time of the SPL down.
+
+For these reasons an MMC device that will be used as an IMX6 primary boot
+device must be carefully partitioned and prepared.
+
+The following shell commands are executed on a Linux host (adjust DEV to the
+block storage device of your MMC, ie /dev/mmcblk0):
+
+ DEV=/dev/sdc
+ # zero out 1MB of device
+ sudo dd if=/dev/zero of=$DEV count=1 bs=1M oflag=sync status=none && sync
+ # copy SPL to 1KB offset
+ sudo dd if=SPL of=$DEV bs=1K seek=1 oflag=sync status=none && sync
+ # copy U-Boot to 69KB offset
+ sudo dd if=u-boot.img of=$DEV bs=1K seek=69 oflag=sync status=none && sync
+ # create a partition table with a single rootfs partition starting at 1MB
+ printf "1,,L\n" | sudo sfdisk --in-order --no-reread -L -uM $DEV && sync
+ # format partition
+ sudo mkfs.ext4 -L root ${DEV}1
+ # mount the partition
+ sudo udisks --mount ${DEV}1
+ # extract filesystem
+ sudo tar xvf rootfs.tar.gz -C /media/root
+ # flush and unmount
+ sync && sudo umount /media/root
+
+The above assumes the default Ventana micro-SD partitioning scheme
+ - spl    :   1KB-69KB  (68KB)  required by IMX6 BOOT ROM
+ - uboot  :  69KB-709KB (640KB) defined by
+                                CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+ - env    : 709KB-965KB (256KB) defined by
+                                CONFIG_ENV_MMC_SIZE
+                                CONFIG_ENV_MMC_OFFSET_REDUND
+ - rootfs :   1MB-
+
+This information is taken from:
+  http://trac.gateworks.com/wiki/ventana/bootloader#microsd
+
+More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
+
+4. Falcon Mode
+------------------------------
+
+The Gateworks Ventana board config enables Falcon mode (CONFIG_SPL_OS_BOOT)
+which allows the SPL to boot directly to an OS instead of to U-Boot
+(u-boot.img) thus acheiving a faster overall boot time. The time savings
+depends on your boot medium (ie NAND Flash vs micro-SD) and size/storage
+of the OS. The time savings can be anywhere from 2 seconds (256MB NAND Flash
+with ~1MB kernel) to 6 seconds or more (2GB NAND Flash with ~6 kernel)
+
+The Gateworks Ventana board supports Falcon mode for the following boot
+medium:
+ - NAND flash
+ - micro-SD
+
+For all boot mediums, raw mode is used. While support of more complex storage
+such as files on top of FAT/EXT filesystem is possible but not practical
+as the size of the SPL is fairly limitted (to 64KB based on the smallest
+size of available IMX6 iRAM) as well as the fact that this would increase
+OS load time which defeats the purpose of Falcon mode in the first place.
+
+The SPL decides to boot either U-Boot (u-boot.img) or the OS (args + kernel)
+based on the return value of the spl_start_uboot() function. While often
+this can simply be the state of a GPIO based pushbutton or DIP switch, for
+Gateworks Ventana, we use an EEPROM register on i2c-0 at 0x50:0x00:
+set to '0' will choose to boot to U-Boot and otherwise it will boot to OS.
+
+To use Falcon mode it is required that you first 'prepare' the 'args' data
+that is stored on your boot medium along with the kernel (which can be any
+OS or bare-metal application). In the case of the Linux kernel the 'args'
+is the flatenned device-tree which normally gets altered prior to booting linux
+by U-Boot's 'bootm' command. To achieve this for SPL we use the
+'spl export fdt' command in U-Boot after loading the kernel and dtb which
+will go through the same process of modifying the device-tree for the board
+being executed on but not jump to the kernel. This allows you to save the
+args data to the location the SPL expects it and then enable Falcon mode.
+
+It is important to realize that there are certain values in the dtb that
+are board model specific (IMX6Q vs IMX6DL for example) and board specific
+(board serial number, MAC addrs) so you do not want to use the 'args'
+data prepared from one board on another board.
+
+4.1. Falcon Mode on NAND flash
+------------------------------
+To prepare a Gateworks Ventana board that boots from NAND flash for Falcon
+mode you must program your flash such that the 'args' and 'kernel' are
+located where defined at compile time by the following:
+   CONFIG_CMD_SPL_NAND_OFS         17MB - offset of 'args'
+   CONFIG_SYS_NAND_SPL_KERNEL_OFFS 18MB - offset of 'kernel'
+
+The location offsets defined above are defaults chosen by Gateworks and are
+flexible if you want to re-define them.
+
+The following steps executed in U-Boot will configure Falcon mode for NAND
+using rootfs (ubi), kernel (uImage), and dtb from the network:
+
+ # change mtd partitions to the above mapping
+ Ventana > setenv mtdparts 'mtdparts=nand:14m(spl),2m(uboot),1m(env),1m(args),10m(kernel),-(rootfs)'
+
+ # flash rootfs (at 28MB)
+ Ventana > tftp ${loadaddr} rootfs_${flash_layout}.ubi && \
+   nand erase.part rootfs && nand write ${loadaddr} rootfs ${filesize}
+
+ # load the device-tree
+ Ventana > tftp ${fdt_addr} ventana/${fdt_file2}
+
+ # load the kernel
+ Ventana > tftp ${loadaddr} ventana/uImage
+
+ # flash kernel (at 18MB)
+ Ventana > nand erase.part kernel && nand write ${loadaddr} kernel ${filesize}
+
+ # set kernel args for the console and rootfs (used by spl export)
+ Ventana > setenv bootargs 'console=ttymxc1,115200 root=ubi0:rootfs ubi.mtd=5 rootfstype=ubifs quiet'
+
+ # create args based on env, board, EEPROM, and dtb
+ Ventana > spl export fdt ${loadaddr} - ${fdt_addr}
+
+ # flash args (at 17MB)
+ Ventana > nand erase.part args && nand write 18000000 args 100000
+
+ # set i2c register 0x50:0x00=0 to boot to Linux
+ Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
+
+Be sure to adjust 'bootargs' above to your OS needs (this will be different
+for various distros such as OpenWrt, Yocto, Android, etc). You can use the
+value obtained from 'cat /proc/cmdline' when booted to Linux.
+
+This information is taken from:
+  http://trac.gateworks.com/wiki/ventana/bootloader/falcon-mode#nand
+
+
+4.2. Falcon Mode on micro-SD card
+---------------------------------
+
+To prepare a Gateworks Ventana board with a primary boot device of micro-SD
+you first need to make sure you build U-Boot with CONFIG_ENV_IS_IN_MMC
+instead of CONFIG_ENV_IS_IN_NAND.
+
+For micro-SD based Falcon mode you must program your micro-SD such that
+the 'args' and 'kernel' are located where defined at compile time
+by the following:
+   CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 (1MB) - offset of 'args'
+   CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 (2MB) - offset of 'kernel'
+
+The location offsets defined above are defaults chosen by Gateworks and are
+flexible if you want to re-define them.
+
+First you must prepare a micro-SD such that the SPL can be loaded by the
+IMX6 BOOT ROM (fixed offset of 1KB), and U-Boot can be loaded by the SPL
+(fixed offset of 69KB defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR).
+
+The following shell commands are executed on a Linux host (adjust DEV to the
+block storage device of your micro-SD):
+
+ DEV=/dev/sdc
+ # zero out 1MB of device
+ sudo dd if=/dev/zero of=$DEV count=1 bs=1M oflag=sync status=none && sync
+ # copy SPL to 1KB offset
+ sudo dd if=SPL of=$DEV bs=1K seek=1 oflag=sync status=none && sync
+ # copy U-Boot to 69KB offset
+ sudo dd if=u-boot.img of=$DEV bs=1K seek=69 oflag=sync status=none && sync
+ # create a partition table with a single rootfs partition starting at 10MB
+ printf "10,,L\n" | sudo sfdisk --in-order --no-reread -L -uM $DEV && sync
+ # format partition
+ sudo mkfs.ext4 -L root ${DEV}1
+ # mount the partition
+ sudo udisks --mount ${DEV}1
+ # extract filesystem
+ sudo tar xvf rootfs.tar.gz -C /media/root
+ # flush and unmount
+ sync && sudo umount /media/root
+
+Now that your micro-SD partitioning has been adjusted to leave room for the
+raw 'args' and 'kernel' data boot the board with the prepared micro-SD, break
+out in U-Boot and use the following to enable Falcon mode:
+
+ # load device-tree from rootfs
+ Ventana > ext2load mmc 0:1 ${fdt_addr} boot/${fdt_file2}
+
+ # load kernel from rootfs
+ Ventana > ext2load mmc 0:1 ${loadaddr} boot/uImage
+
+ # write kernel at 2MB offset
+ Ventana > mmc write ${loadaddr} 0x1000 0x4000
+
+ # setup kernel bootargs
+ Ventana > setenv bootargs 'console=ttymxc1,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw'
+
+ # prepare args
+ Ventana > spl export fdt ${loadaddr} - ${fdt_addr}
+
+ # write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
+ Ventana > mmc write 18000000 0x800 0x800
+
+ # set i2c register 0x50:0x00=0 to boot to Linux
+ Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
+
+Be sure to adjust 'bootargs' above to your OS needs (this will be different
+for various distros such as OpenWrt, Yocto, Android, etc). You can use the
+value obtained from 'cat /proc/cmdline' when booted to Linux.
+
+This information is taken from:
+  http://trac.gateworks.com/wiki/ventana/bootloader/falcon-mode#microsd
diff --git a/roms/u-boot/board/gateworks/gw_ventana/common.c b/roms/u-boot/board/gateworks/gw_ventana/common.c
new file mode 100644
index 000000000..4627a156f
--- /dev/null
+++ b/roms/u-boot/board/gateworks/gw_ventana/common.c
@@ -0,0 +1,1743 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
+#include <hwconfig.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/ltc3676_pmic.h>
+#include <power/pfuze100_pmic.h>
+
+#include "common.h"
+
+/* UART2: Serial Console */
+static iomux_v3_cfg_t const uart2_pads[] = {
+	IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart2_pads);
+}
+
+/* MMC */
+static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+/* 4-bit microSD on SD2 */
+static iomux_v3_cfg_t const gw5904_mmc_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* CD */
+	IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+/* 8-bit eMMC on SD2/NAND */
+static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+/*
+ * I2C pad configs:
+ * I2C1: GSC
+ * I2C2: PMIC,PCIe Switch,Clock,Mezz
+ * I2C3: Multimedia/Expansion
+ */
+static struct i2c_pads_info mx6q_i2c_pad_info[] = {
+	{
+		.scl = {
+			.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
+			.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
+			.gp = IMX_GPIO_NR(3, 21)
+		},
+		.sda = {
+			.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
+			.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
+			.gp = IMX_GPIO_NR(3, 28)
+		}
+	}, {
+		.scl = {
+			.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
+			.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
+			.gp = IMX_GPIO_NR(4, 12)
+		},
+		.sda = {
+			.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+			.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+			.gp = IMX_GPIO_NR(4, 13)
+		}
+	}, {
+		.scl = {
+			.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+			.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+			.gp = IMX_GPIO_NR(1, 3)
+		},
+		.sda = {
+			.i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
+			.gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
+			.gp = IMX_GPIO_NR(1, 6)
+		}
+	}
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info[] = {
+	{
+		.scl = {
+			.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
+			.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
+			.gp = IMX_GPIO_NR(3, 21)
+		},
+		.sda = {
+			.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
+			.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
+			.gp = IMX_GPIO_NR(3, 28)
+		}
+	}, {
+		.scl = {
+			.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
+			.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
+			.gp = IMX_GPIO_NR(4, 12)
+		},
+		.sda = {
+			.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+			.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+			.gp = IMX_GPIO_NR(4, 13)
+		}
+	}, {
+		.scl = {
+			.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+			.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
+			.gp = IMX_GPIO_NR(1, 3)
+		},
+		.sda = {
+			.i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
+			.gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
+			.gp = IMX_GPIO_NR(1, 6)
+		}
+	}
+};
+
+void setup_ventana_i2c(int i2c)
+{
+	struct i2c_pads_info *p;
+
+	if (is_cpu_type(MXC_CPU_MX6Q))
+		p = &mx6q_i2c_pad_info[i2c];
+	else
+		p = &mx6dl_i2c_pad_info[i2c];
+
+	setup_i2c(i2c, CONFIG_SYS_I2C_SPEED, 0x7f, p);
+}
+
+/*
+ * Baseboard specific GPIO
+ */
+static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* IOEXP_PWREN# */
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+	/* IOEXP_IRQ# */
+	IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+
+	/* GPS_SHDN */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+	/* VID_PWR */
+	IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
+	/* SD3_VSELECT */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+	/* RS232_EN# */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+	/* MSATA_EN */
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* IOEXP_PWREN# */
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+	/* IOEXP_IRQ# */
+	IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+	/* CAN_STBY */
+	IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* GPS_SHDN */
+	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
+	/* USBOTG_SEL */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+	/* VID_PWR */
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+	/* PCI_RST# (GW522x) */
+	IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG),
+	/* RS485_EN */
+	IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
+	/* SD3_VSELECT */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+	/* RS232_EN# */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+	/* MSATA_EN */
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
+	/* CAN_STBY */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+	/* USB_HUBRST# */
+	IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* IOEXP_PWREN# */
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+	/* IOEXP_IRQ# */
+	IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+	/* DIOI2C_DIS# */
+	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+	/* GPS_SHDN */
+	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
+	/* VID_EN */
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+	/* RS485_EN */
+	IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
+	/* SD3_VSELECT */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+	/* RS232_EN# */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+	/* MSATA_EN */
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
+	/* CAN_STBY */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* USB_HUBRST# */
+	IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG),
+	/* MIPI_DIO */
+	IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
+	/* RS485_EN */
+	IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
+	/* IOEXP_PWREN# */
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+	/* IOEXP_IRQ# */
+	IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+	/* DIOI2C_DIS# */
+	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+	/* VID_EN */
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+	/* RS485_EN */
+	IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
+	/* CAN_STBY */
+	IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+	/* PANLED# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
+	/* MSATA_EN */
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
+	/* USBOTG_SEL */
+	IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
+	/* USB_HUBRST# */
+	IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+	/* MX6_DIO[4:9] */
+	IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
+	/* PCIEGBE1_OFF# */
+	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
+	/* PCIEGBE2_OFF# */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
+	/* SD3_VSELECT */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG),
+	/* VID_PWR */
+	IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
+	/* RS232_EN# */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+	/* CAN_STBY */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+	/* USB_HUBRST# */
+	IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* IOEXP_PWREN# */
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+	/* IOEXP_IRQ# */
+	IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+	/* DIOI2C_DIS# */
+	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+	/* VID_EN */
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG),
+	/* RS485_EN */
+	IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+	/* USBH2_PEN (OTG) */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* 12V0_PWR_EN */
+	IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw5901_gpio_pads[] = {
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* ETH1_EN */
+	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
+	/* CAN_STBY */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+	/* PMIC reset */
+	IOMUX_PADS(PAD_DISP0_DAT8__WDOG1_B | DIO_PAD_CFG),
+	/* COM_CFGA/B/C/D */
+	IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
+	/* ETI_IRQ# */
+	IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
+	/* DIO_IRQ# */
+	IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
+	/* FIBER_SIGDET */
+	IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw5902_gpio_pads[] = {
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* CAN1_STBY */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+	/* CAN2_STBY */
+	IOMUX_PADS(PAD_SD3_CLK__GPIO7_IO03 | DIO_PAD_CFG),
+	/* UART1_EN# */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+	/* 5V_UVLO */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+	/* ETI_IRQ# */
+	IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
+	/* DIO_IRQ# */
+	IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
+	/* USBOTG_PEN */
+	IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
+	/* BKLT_12VEN */
+	IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
+	/* EMMY_PDN# */
+	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG),
+	/* EMMY_CFG1# */
+	IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
+	/* EMMY_CFG1# */
+	IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
+	/* USBH1_PEN (EHCI) */
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+	/* USBH2_PEN (OTG) */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* USBDPC_PEN */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* TOUCH_RST */
+	IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
+	/* AUDIO_RST# */
+	IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
+	/* UART1_TEN# */
+	IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+	/* LVDS_BKLEN # */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+	/* RGMII_PDWN# */
+	IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG),
+	/* TOUCH_IRQ# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* TOUCH_RST# */
+	IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
+	/* USB_HUBRST# */
+	IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* IOEXP_PWREN# */
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+	/* IOEXP_IRQ# */
+	IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+	/* DIOI2C_DIS# */
+	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+	/* UART_RS485 */
+	IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG),
+	/* UART_HALF */
+	IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG),
+	/* SKT1_WDIS# */
+	IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG),
+	/* SKT1_RST# */
+	IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG),
+	/* SKT2_WDIS# */
+	IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG),
+	/* SKT2_RST# */
+	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+	/* M2_OFF# */
+	IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
+	/* M2_WDIS# */
+	IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
+	/* M2_RST# */
+	IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
+	/* RS232_EN# */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw5905_gpio_pads[] = {
+	/* EMMY_PDN# */
+	IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+	/* MIPI_RST */
+	IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
+	/* MIPI_PWDN */
+	IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
+	/* USBEHCI_SEL */
+	IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_GPIO_16__GPIO7_IO11 | DIO_PAD_CFG),
+	/* LVDS_BKLEN # */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | DIO_PAD_CFG),
+	/* SPK_SHDN# */
+	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+	/* LOCLED# */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+	/* FLASH LED1 */
+	IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | DIO_PAD_CFG),
+	/* FLASH LED2 */
+	IOMUX_PADS(PAD_DISP0_DAT12__GPIO5_IO06 | DIO_PAD_CFG),
+	/* DECT_RST# */
+	IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
+	/* USBH1_PEN (EHCI) */
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+	/* LVDS_PWM */
+	IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+	/* CODEC_RST */
+	IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
+	/* GYRO_CONTROL/DATA_EN */
+	IOMUX_PADS(PAD_CSI0_DAT8__GPIO5_IO26 | DIO_PAD_CFG),
+	/* TOUCH_RST */
+	IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
+	/* TOUCH_IRQ */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+};
+
+/* Digital I/O */
+struct dio_cfg gw51xx_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
+		IMX_GPIO_NR(1, 18),
+		{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
+		4
+	},
+};
+
+struct dio_cfg gw52xx_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+};
+
+struct dio_cfg gw53xx_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+};
+
+struct dio_cfg gw54xx_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
+		IMX_GPIO_NR(1, 9),
+		{ IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
+		1
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
+		IMX_GPIO_NR(2, 9),
+		{ IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
+		IMX_GPIO_NR(2, 10),
+		{ IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
+		4
+	},
+};
+
+struct dio_cfg gw551x_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+};
+
+struct dio_cfg gw552x_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18) },
+		IMX_GPIO_NR(5, 18),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20) },
+		IMX_GPIO_NR(5, 20),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21) },
+		IMX_GPIO_NR(5, 21),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22) },
+		IMX_GPIO_NR(5, 22),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23) },
+		IMX_GPIO_NR(5, 23),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25) },
+		IMX_GPIO_NR(5, 25),
+		{ 0, 0 },
+		0
+	},
+};
+
+struct dio_cfg gw553x_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
+		IMX_GPIO_NR(1, 18),
+		{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
+		4
+	},
+};
+
+struct dio_cfg gw560x_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+};
+
+struct dio_cfg gw5901_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
+		IMX_GPIO_NR(5, 14),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
+		IMX_GPIO_NR(5, 15),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
+		IMX_GPIO_NR(5, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
+		IMX_GPIO_NR(5, 17),
+		{ 0, 0 },
+		0
+	},
+};
+
+struct dio_cfg gw5902_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
+		IMX_GPIO_NR(5, 14),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
+		IMX_GPIO_NR(5, 15),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
+		IMX_GPIO_NR(5, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
+		IMX_GPIO_NR(5, 17),
+		{ 0, 0 },
+		0
+	},
+};
+
+struct dio_cfg gw5903_dio[] = {
+};
+
+struct dio_cfg gw5904_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) },
+		IMX_GPIO_NR(2, 0),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) },
+		IMX_GPIO_NR(2, 1),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) },
+		IMX_GPIO_NR(2, 2),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) },
+		IMX_GPIO_NR(2, 3),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) },
+		IMX_GPIO_NR(2, 4),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) },
+		IMX_GPIO_NR(2, 5),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) },
+		IMX_GPIO_NR(2, 6),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) },
+		IMX_GPIO_NR(2, 7),
+		{ 0, 0 },
+		0
+	},
+};
+
+struct dio_cfg gw5906_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+};
+
+/*
+ * Board Specific GPIO
+ */
+struct ventana gpio_cfg[GW_UNKNOWN] = {
+	/* GW5400proto */
+	{
+		.gpio_pads = gw54xx_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
+		.dio_cfg = gw54xx_dio,
+		.dio_num = ARRAY_SIZE(gw54xx_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 10),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+		.mezz_pwren = IMX_GPIO_NR(4, 7),
+		.mezz_irq = IMX_GPIO_NR(4, 9),
+		.rs485en = IMX_GPIO_NR(3, 24),
+		.dioi2c_en = IMX_GPIO_NR(4,  5),
+		.pcie_sson = IMX_GPIO_NR(1, 20),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
+	},
+
+	/* GW51xx */
+	{
+		.gpio_pads = gw51xx_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
+		.dio_cfg = gw51xx_dio,
+		.dio_num = ARRAY_SIZE(gw51xx_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 10),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 0),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.gps_shdn = IMX_GPIO_NR(1, 2),
+		.vidin_en = IMX_GPIO_NR(5, 20),
+		.wdis = IMX_GPIO_NR(7, 12),
+		.nand = true,
+	},
+
+	/* GW52xx */
+	{
+		.gpio_pads = gw52xx_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
+		.dio_cfg = gw52xx_dio,
+		.dio_num = ARRAY_SIZE(gw52xx_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.gps_shdn = IMX_GPIO_NR(1, 27),
+		.vidin_en = IMX_GPIO_NR(3, 31),
+		.usb_sel = IMX_GPIO_NR(1, 2),
+		.wdis = IMX_GPIO_NR(7, 12),
+		.msata_en = GP_MSATA_SEL,
+		.rs232_en = GP_RS232_EN,
+		.vsel_pin = IMX_GPIO_NR(6, 14),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
+		.nand = true,
+	},
+
+	/* GW53xx */
+	{
+		.gpio_pads = gw53xx_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
+		.dio_cfg = gw53xx_dio,
+		.dio_num = ARRAY_SIZE(gw53xx_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.gps_shdn = IMX_GPIO_NR(1, 27),
+		.vidin_en = IMX_GPIO_NR(3, 31),
+		.wdis = IMX_GPIO_NR(7, 12),
+		.msata_en = GP_MSATA_SEL,
+		.rs232_en = GP_RS232_EN,
+		.vsel_pin = IMX_GPIO_NR(6, 14),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
+		.nand = true,
+	},
+
+	/* GW54xx */
+	{
+		.gpio_pads = gw54xx_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
+		.dio_cfg = gw54xx_dio,
+		.dio_num = ARRAY_SIZE(gw54xx_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.rs485en = IMX_GPIO_NR(7, 1),
+		.vidin_en = IMX_GPIO_NR(3, 31),
+		.dioi2c_en = IMX_GPIO_NR(4,  5),
+		.pcie_sson = IMX_GPIO_NR(1, 20),
+		.wdis = IMX_GPIO_NR(5, 17),
+		.msata_en = GP_MSATA_SEL,
+		.rs232_en = GP_RS232_EN,
+		.vsel_pin = IMX_GPIO_NR(6, 14),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
+		.nand = true,
+	},
+
+	/* GW551x */
+	{
+		.gpio_pads = gw551x_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
+		.dio_cfg = gw551x_dio,
+		.dio_num = ARRAY_SIZE(gw551x_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 7),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 0),
+		.wdis = IMX_GPIO_NR(7, 12),
+		.nand = true,
+	},
+
+	/* GW552x */
+	{
+		.gpio_pads = gw552x_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
+		.dio_cfg = gw552x_dio,
+		.dio_num = ARRAY_SIZE(gw552x_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+		.usb_sel = IMX_GPIO_NR(1, 7),
+		.wdis = IMX_GPIO_NR(7, 12),
+		.msata_en = GP_MSATA_SEL,
+		.nand = true,
+	},
+
+	/* GW553x */
+	{
+		.gpio_pads = gw553x_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
+		.dio_cfg = gw553x_dio,
+		.dio_num = ARRAY_SIZE(gw553x_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 10),
+			IMX_GPIO_NR(4, 11),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 0),
+		.vidin_en = IMX_GPIO_NR(5, 20),
+		.wdis = IMX_GPIO_NR(7, 12),
+		.vsel_pin = IMX_GPIO_NR(6, 14),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
+		.nand = true,
+	},
+
+	/* GW560x */
+	{
+		.gpio_pads = gw560x_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
+		.dio_cfg = gw560x_dio,
+		.dio_num = ARRAY_SIZE(gw560x_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(4, 31),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.rs232_en = GP_RS232_EN,
+		.vidin_en = IMX_GPIO_NR(3, 31),
+		.wdis = IMX_GPIO_NR(7, 12),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
+	},
+
+	/* GW5901 */
+	{
+		.gpio_pads = gw5901_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw5901_gpio_pads)/2,
+		.dio_cfg = gw5901_dio,
+		.leds = {
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+		.nand = true,
+	},
+
+	/* GW5902 */
+	{
+		.gpio_pads = gw5902_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw5902_gpio_pads)/2,
+		.dio_cfg = gw5902_dio,
+		.leds = {
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 0),
+		.rs232_en = GP_RS232_EN,
+		.nand = true,
+	},
+
+	/* GW5903 */
+	{
+		.gpio_pads = gw5903_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
+		.dio_cfg = gw5903_dio,
+		.dio_num = ARRAY_SIZE(gw5903_dio),
+		.leds = {
+			IMX_GPIO_NR(6, 14),
+		},
+		.mmc_cd = IMX_GPIO_NR(6, 11),
+	},
+
+	/* GW5904 */
+	{
+		.gpio_pads = gw5904_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
+		.dio_cfg = gw5904_dio,
+		.dio_num = ARRAY_SIZE(gw5904_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 0),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+	},
+
+	/* GW5905 */
+	{
+		.gpio_pads = gw5905_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw5905_gpio_pads)/2,
+		.leds = {
+			IMX_GPIO_NR(6, 14),
+		},
+		.pcie_rst = IMX_GPIO_NR(7, 11),
+		.wdis = IMX_GPIO_NR(7, 13),
+	},
+
+	/* GW5906 */
+	{
+		.gpio_pads = gw552x_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
+		.dio_cfg = gw5906_dio,
+		.dio_num = ARRAY_SIZE(gw5906_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+		.usb_sel = IMX_GPIO_NR(1, 7),
+		.wdis = IMX_GPIO_NR(7, 12),
+		.msata_en = GP_MSATA_SEL,
+		.nand = true,
+	},
+
+	/* GW5907 */
+	{
+		.gpio_pads = gw51xx_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
+		.dio_cfg = gw51xx_dio,
+		.dio_num = ARRAY_SIZE(gw51xx_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 10),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 0),
+		.wdis = IMX_GPIO_NR(7, 12),
+		.nand = true,
+	},
+
+	/* GW5908 */
+	{
+		.gpio_pads = gw53xx_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
+		.dio_cfg = gw53xx_dio,
+		.dio_num = ARRAY_SIZE(gw53xx_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.gps_shdn = IMX_GPIO_NR(1, 27),
+		.vidin_en = IMX_GPIO_NR(3, 31),
+		.wdis = IMX_GPIO_NR(7, 12),
+		.msata_en = GP_MSATA_SEL,
+		.rs232_en = GP_RS232_EN,
+	},
+
+	/* GW5909 */
+	{
+		.gpio_pads = gw5904_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
+		.dio_cfg = gw5904_dio,
+		.dio_num = ARRAY_SIZE(gw5904_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 0),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+	},
+};
+
+#define SETUP_GPIO_OUTPUT(gpio, name, level) \
+	gpio_request(gpio, name); \
+	gpio_direction_output(gpio, level);
+#define SETUP_GPIO_INPUT(gpio, name) \
+	gpio_request(gpio, name); \
+	gpio_direction_input(gpio);
+void setup_iomux_gpio(int board, struct ventana_board_info *info)
+{
+	int i;
+
+	if (board >= GW_UNKNOWN)
+		return;
+
+	/* board specific iomux */
+	imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads,
+					 gpio_cfg[board].num_pads);
+
+	/* RS232_EN# */
+	if (gpio_cfg[board].rs232_en) {
+		gpio_request(gpio_cfg[board].rs232_en, "rs232_en#");
+		gpio_direction_output(gpio_cfg[board].rs232_en, 0);
+	}
+
+	/* GW522x Uses GPIO3_IO23 for PCIE_RST# */
+	if (board == GW52xx && info->model[4] == '2')
+		gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23);
+
+	/* assert PCI_RST# */
+	gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#");
+	gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
+
+	/* turn off (active-high) user LED's */
+	for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
+		char name[16];
+		if (gpio_cfg[board].leds[i]) {
+			sprintf(name, "led_user%d", i);
+			gpio_request(gpio_cfg[board].leds[i], name);
+			gpio_direction_output(gpio_cfg[board].leds[i], 1);
+		}
+	}
+
+	/* MSATA Enable - default to PCI */
+	if (gpio_cfg[board].msata_en) {
+		gpio_request(gpio_cfg[board].msata_en, "msata_en");
+		gpio_direction_output(gpio_cfg[board].msata_en, 0);
+	}
+
+	/* Expansion Mezzanine IO */
+	if (gpio_cfg[board].mezz_pwren) {
+		gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr");
+		gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
+	}
+	if (gpio_cfg[board].mezz_irq) {
+		gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#");
+		gpio_direction_input(gpio_cfg[board].mezz_irq);
+	}
+
+	/* RS485 Transmit Enable */
+	if (gpio_cfg[board].rs485en) {
+		gpio_request(gpio_cfg[board].rs485en, "rs485_en");
+		gpio_direction_output(gpio_cfg[board].rs485en, 0);
+	}
+
+	/* GPS_SHDN */
+	if (gpio_cfg[board].gps_shdn) {
+		gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn");
+		gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
+	}
+
+	/* Analog video codec power enable */
+	if (gpio_cfg[board].vidin_en) {
+		gpio_request(gpio_cfg[board].vidin_en, "anavidin_en");
+		gpio_direction_output(gpio_cfg[board].vidin_en, 1);
+	}
+
+	/* DIOI2C_DIS# */
+	if (gpio_cfg[board].dioi2c_en) {
+		gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#");
+		gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
+	}
+
+	/* PCICK_SSON: disable spread-spectrum clock */
+	if (gpio_cfg[board].pcie_sson) {
+		gpio_request(gpio_cfg[board].pcie_sson, "pci_sson");
+		gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
+	}
+
+	/* USBOTG mux routing */
+	if (gpio_cfg[board].usb_sel) {
+		gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel");
+		gpio_direction_output(gpio_cfg[board].usb_sel, 0);
+	}
+
+	/* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
+	if (gpio_cfg[board].wdis) {
+		gpio_request(gpio_cfg[board].wdis, "wlan_dis");
+		gpio_direction_output(gpio_cfg[board].wdis, 1);
+	}
+
+	/* sense vselect pin to see if we support uhs-i */
+	if (gpio_cfg[board].vsel_pin) {
+		gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect");
+		gpio_direction_input(gpio_cfg[board].vsel_pin);
+		gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin);
+	}
+
+	/* microSD CD */
+	if (gpio_cfg[board].mmc_cd) {
+		gpio_request(gpio_cfg[board].mmc_cd, "sd_cd");
+		gpio_direction_input(gpio_cfg[board].mmc_cd);
+	}
+
+	/* Anything else board specific */
+	switch(board) {
+	case GW560x:
+		gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
+		gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
+		break;
+	case GW5901:
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can_stby", 0);
+		break;
+	case GW5902:
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can1_stby", 0);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 3), "can2_stby", 0);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "5P0V_EN", 1);
+		break;
+	case GW5903:
+		gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
+		gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
+		gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
+		gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
+		gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
+		gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
+		gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
+		gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
+		gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#");
+		gpio_direction_input(IMX_GPIO_NR(4, 6));
+		gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst");
+		gpio_direction_output(IMX_GPIO_NR(4, 8), 1);
+		gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
+		gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
+		break;
+	case GW5909:
+	case GW5904:
+		gpio_request(IMX_GPIO_NR(4, 23), "rs485_en");
+		gpio_direction_output(IMX_GPIO_NR(4, 23), 0);
+		gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
+		gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
+		gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
+		gpio_direction_output(IMX_GPIO_NR(5, 12), 1);
+		gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#");
+		gpio_direction_output(IMX_GPIO_NR(5, 13), 1);
+		gpio_request(IMX_GPIO_NR(1, 15), "m2_off#");
+		gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+		gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#");
+		gpio_direction_output(IMX_GPIO_NR(1, 14), 1);
+		gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
+		gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
+		break;
+	case GW5905:
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 7), "usb_pcisel", 0);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 9), "lvds_cabc", 1);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 14), "mipi_pdwn", 1);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 15), "mipi_rst#", 0);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(2, 3), "emmy_pdwn#", 1);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 5), "spk_shdn#", 0);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 0);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 6), "touch_irq", 0);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 5), "flash_en1", 0);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 6), "flash_en2", 0);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 14), "dect_rst#", 1);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 17), "codec_rst#", 0);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 26), "imu_den", 1);
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "lvds_cabc", 0);
+		mdelay(100);
+		/*
+		 * gauruntee touch controller comes out of reset with INT
+		 * low for address
+		 */
+		SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 1);
+		break;
+	}
+}
+
+/* setup GPIO pinmux and default configuration per baseboard and env */
+void setup_board_gpio(int board, struct ventana_board_info *info)
+{
+	const char *s;
+	char arg[10];
+	size_t len;
+	int i;
+	int quiet = simple_strtol(env_get("quiet"), NULL, 10);
+
+	if (board >= GW_UNKNOWN)
+		return;
+
+	/* RS232_EN# */
+	if (gpio_cfg[board].rs232_en) {
+		gpio_direction_output(gpio_cfg[board].rs232_en,
+				      (hwconfig("rs232")) ? 0 : 1);
+	}
+
+	/* MSATA Enable */
+	if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
+		gpio_direction_output(GP_MSATA_SEL,
+				      (hwconfig("msata")) ? 1 : 0);
+	}
+
+	/* USBOTG Select (PCISKT or FrontPanel) */
+	if (gpio_cfg[board].usb_sel) {
+		gpio_direction_output(gpio_cfg[board].usb_sel,
+				      (hwconfig("usb_pcisel")) ? 1 : 0);
+	}
+
+	/*
+	 * Configure DIO pinmux/padctl registers
+	 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
+	 */
+	for (i = 0; i < gpio_cfg[board].dio_num; i++) {
+		struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
+		iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
+		unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
+
+		if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
+			continue;
+		sprintf(arg, "dio%d", i);
+		if (!hwconfig(arg))
+			continue;
+		s = hwconfig_subarg(arg, "padctrl", &len);
+		if (s) {
+			ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
+					    & 0x1ffff) | MUX_MODE_SION;
+		}
+		if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
+			if (!quiet) {
+				printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
+				       (cfg->gpio_param/32)+1,
+				       cfg->gpio_param%32,
+				       cfg->gpio_param);
+			}
+			imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
+					       ctrl);
+			gpio_requestf(cfg->gpio_param, "dio%d", i);
+			gpio_direction_input(cfg->gpio_param);
+		} else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
+			   cfg->pwm_padmux) {
+			if (!cfg->pwm_param) {
+				printf("DIO%d:  Error: pwm config invalid\n",
+					i);
+				continue;
+			}
+			if (!quiet)
+				printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
+			imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
+					       MUX_PAD_CTRL(ctrl));
+		}
+	}
+
+	if (!quiet) {
+		if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
+			printf("MSATA: %s\n", (hwconfig("msata") ?
+			       "enabled" : "disabled"));
+		}
+		if (gpio_cfg[board].rs232_en) {
+			printf("RS232: %s\n", (hwconfig("rs232")) ?
+			       "enabled" : "disabled");
+		}
+	}
+}
+
+/* setup board specific PMIC */
+void setup_pmic(void)
+{
+	struct pmic *p;
+	struct ventana_board_info ventana_info;
+	int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+	const int i2c_pmic = 1;
+	u32 reg;
+
+	i2c_set_bus_num(i2c_pmic);
+
+	/* configure PFUZE100 PMIC */
+	if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) {
+		debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR);
+		power_pfuze100_init(i2c_pmic);
+		p = pmic_get("PFUZE100");
+		if (p && !pmic_probe(p)) {
+			pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+			printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+			/* Set VGEN1 to 1.5V and enable */
+			pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
+			reg &= ~(LDO_VOL_MASK);
+			reg |= (LDOA_1_50V | LDO_EN);
+			pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
+
+			/* Set SWBST to 5.0V and enable */
+			pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
+			reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
+			reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
+			pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+		}
+	}
+
+	/* configure LTC3676 PMIC */
+	else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) {
+		debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
+		power_ltc3676_init(i2c_pmic);
+		p = pmic_get("LTC3676_PMIC");
+		if (!p || pmic_probe(p))
+			return;
+		puts("PMIC:  LTC3676\n");
+		/*
+		 * set board-specific scalar for max CPU frequency
+		 * per CPU based on the LDO enabled Operating Ranges
+		 * defined in the respective IMX6DQ and IMX6SDL
+		 * datasheets. The voltage resulting from the R1/R2
+		 * feedback inputs on Ventana is 1308mV. Note that this
+		 * is a bit shy of the Vmin of 1350mV in the datasheet
+		 * for LDO enabled mode but is as high as we can go.
+		 */
+		switch (board) {
+		case GW560x:
+			/* mask PGOOD during SW3 transition */
+			pmic_reg_write(p, LTC3676_DVB3B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW3 (VDD_ARM) */
+			pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+			break;
+		case GW5903:
+			/* mask PGOOD during SW3 transition */
+			pmic_reg_write(p, LTC3676_DVB3B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW3 (VDD_ARM) */
+			pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+
+			/* mask PGOOD during SW4 transition */
+			pmic_reg_write(p, LTC3676_DVB4B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW4 (VDD_SOC) */
+			pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
+			break;
+		case GW5905:
+			/* mask PGOOD during SW1 transition */
+			pmic_reg_write(p, LTC3676_DVB1B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW1 (VDD_ARM) */
+			pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
+
+			/* mask PGOOD during SW3 transition */
+			pmic_reg_write(p, LTC3676_DVB3B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW3 (VDD_SOC) */
+			pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+			break;
+		default:
+			/* mask PGOOD during SW1 transition */
+			pmic_reg_write(p, LTC3676_DVB1B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW1 (VDD_SOC) */
+			pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
+
+			/* mask PGOOD during SW3 transition */
+			pmic_reg_write(p, LTC3676_DVB3B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW3 (VDD_ARM) */
+			pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+		}
+	}
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+static struct fsl_esdhc_cfg usdhc_cfg[2];
+
+int board_mmc_init(struct bd_info *bis)
+{
+	struct ventana_board_info ventana_info;
+	int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+	int ret;
+
+	switch (board_type) {
+	case GW52xx:
+	case GW53xx:
+	case GW54xx:
+	case GW553x:
+		/* usdhc3: 4bit microSD */
+		SETUP_IOMUX_PADS(usdhc3_pads);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[0].max_bus_width = 4;
+		return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	case GW560x:
+		/* usdhc2: 8-bit eMMC */
+		SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads);
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		usdhc_cfg[0].max_bus_width = 8;
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+		if (ret)
+			return ret;
+		/* usdhc3: 4-bit microSD */
+		SETUP_IOMUX_PADS(usdhc3_pads);
+		usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[1].max_bus_width = 4;
+		return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+	case GW5903:
+		/* usdhc3: 8-bit eMMC */
+		SETUP_IOMUX_PADS(gw5904_emmc_pads);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[0].max_bus_width = 8;
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+		if (ret)
+			return ret;
+		/* usdhc2: 4-bit microSD */
+		SETUP_IOMUX_PADS(gw5904_mmc_pads);
+		usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		usdhc_cfg[1].max_bus_width = 4;
+		return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+	case GW5904:
+	case GW5905:
+	case GW5909:
+		/* usdhc3: 8bit eMMC */
+		SETUP_IOMUX_PADS(gw5904_emmc_pads);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[0].max_bus_width = 8;
+		return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	default:
+		/* doesn't have MMC */
+		return -1;
+	}
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct ventana_board_info ventana_info;
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+	int gpio = gpio_cfg[board].mmc_cd;
+
+	/* Card Detect */
+	switch (board) {
+	case GW560x:
+		/* emmc is always present */
+		if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+			return 1;
+		break;
+	case GW5903:
+	case GW5904:
+	case GW5905:
+	case GW5909:
+		/* emmc is always present */
+		if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+			return 1;
+		break;
+	}
+
+	if (gpio) {
+		debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio));
+		return !gpio_get_value(gpio);
+	}
+
+	return -1;
+}
+
+#endif /* CONFIG_FSL_ESDHC_IMX */
diff --git a/roms/u-boot/board/gateworks/gw_ventana/common.h b/roms/u-boot/board/gateworks/gw_ventana/common.h
new file mode 100644
index 000000000..813f7d9f5
--- /dev/null
+++ b/roms/u-boot/board/gateworks/gw_ventana/common.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ */
+
+#ifndef _GWVENTANA_COMMON_H_
+#define _GWVENTANA_COMMON_H_
+
+#include "ventana_eeprom.h"
+
+/* GPIO's common to all baseboards */
+#define GP_RS232_EN	IMX_GPIO_NR(2, 11)
+#define GP_MSATA_SEL	IMX_GPIO_NR(2, 8)
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define IRQ_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define DIO_PAD_CFG   (MUX_PAD_CTRL(IRQ_PAD_CTRL) | MUX_MODE_SION)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/*
+ * each baseboard has an optional set user configurable Digital IO lines which
+ * can be pinmuxed as a GPIO or in some cases a PWM
+ */
+struct dio_cfg {
+	iomux_v3_cfg_t gpio_padmux[2];
+	unsigned gpio_param;
+	iomux_v3_cfg_t pwm_padmux[2];
+	unsigned pwm_param;
+};
+
+struct ventana {
+	/* pinmux */
+	iomux_v3_cfg_t const *gpio_pads;
+	int num_pads;
+	/* DIO pinmux/val */
+	struct dio_cfg *dio_cfg;
+	int dio_num;
+	/* various gpios (0 if non-existent) */
+	int leds[3];
+	int pcie_rst;
+	int mezz_pwren;
+	int mezz_irq;
+	int rs485en;
+	int gps_shdn;
+	int vidin_en;
+	int dioi2c_en;
+	int pcie_sson;
+	int usb_sel;
+	int wdis;
+	int msata_en;
+	int rs232_en;
+	int vsel_pin;
+	int mmc_cd;
+	/* various features */
+	bool usd_vsel;
+	bool nand;
+};
+
+extern struct ventana gpio_cfg[GW_UNKNOWN];
+
+/* configure i2c iomux */
+void setup_ventana_i2c(int);
+/* configure uart iomux */
+void setup_iomux_uart(void);
+/* conifgure PMIC */
+void setup_pmic(void);
+/* configure gpio iomux/defaults */
+void setup_iomux_gpio(int board, struct ventana_board_info *);
+/* late setup of GPIO (configuration per baseboard and env) */
+void setup_board_gpio(int board, struct ventana_board_info *);
+
+#endif /* #ifndef _GWVENTANA_COMMON_H_ */
diff --git a/roms/u-boot/board/gateworks/gw_ventana/eeprom.c b/roms/u-boot/board/gateworks/gw_ventana/eeprom.c
new file mode 100644
index 000000000..b9862c7df
--- /dev/null
+++ b/roms/u-boot/board/gateworks/gw_ventana/eeprom.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <hexdump.h>
+#include <i2c.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/bitops.h>
+#include <linux/delay.h>
+
+#include "gsc.h"
+#include "ventana_eeprom.h"
+
+/* read ventana EEPROM, check for validity, and return baseboard type */
+int
+read_eeprom(int bus, struct ventana_board_info *info)
+{
+	int i;
+	int chksum;
+	char baseboard;
+	int type;
+	unsigned char *buf = (unsigned char *)info;
+
+	memset(info, 0, sizeof(*info));
+
+	/*
+	 * On a board with a missing/depleted backup battery for GSC, the
+	 * board may be ready to probe the GSC before its firmware is
+	 * running.  We will wait here indefinately for the GSC/EEPROM.
+	 */
+	while (1) {
+		if (0 == i2c_set_bus_num(bus) &&
+		    0 == i2c_probe(GSC_EEPROM_ADDR))
+			break;
+		mdelay(1);
+	}
+
+	/* read eeprom config section */
+	mdelay(10);
+	if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) {
+		puts("EEPROM: Failed to read EEPROM\n");
+		return GW_UNKNOWN;
+	}
+
+	/* sanity checks */
+	if (info->model[0] != 'G' || info->model[1] != 'W') {
+		puts("EEPROM: Invalid Model in EEPROM\n");
+		print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf,
+				     sizeof(*info));
+		return GW_UNKNOWN;
+	}
+
+	/* validate checksum */
+	for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
+		chksum += buf[i];
+	if ((info->chksum[0] != chksum>>8) ||
+	    (info->chksum[1] != (chksum&0xff))) {
+		puts("EEPROM: Failed EEPROM checksum\n");
+		print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf,
+				     sizeof(*info));
+		return GW_UNKNOWN;
+	}
+
+	/* original GW5400-A prototype */
+	baseboard = info->model[3];
+	if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
+		baseboard = '0';
+
+	type = GW_UNKNOWN;
+	switch (baseboard) {
+	case '0': /* original GW5400-A prototype */
+		type = GW54proto;
+		break;
+	case '1':
+		type = GW51xx;
+		break;
+	case '2':
+		type = GW52xx;
+		break;
+	case '3':
+		type = GW53xx;
+		break;
+	case '4':
+		type = GW54xx;
+		break;
+	case '5':
+		if (info->model[4] == '1') {
+			type = GW551x;
+			break;
+		} else if (info->model[4] == '2') {
+			type = GW552x;
+			break;
+		} else if (info->model[4] == '3') {
+			type = GW553x;
+			break;
+		}
+		break;
+	case '6':
+		if (info->model[4] == '0')
+			type = GW560x;
+		break;
+	case '9':
+		if (info->model[4] == '0' && info->model[5] == '1')
+			type = GW5901;
+		else if (info->model[4] == '0' && info->model[5] == '2')
+			type = GW5902;
+		else if (info->model[4] == '0' && info->model[5] == '3')
+			type = GW5903;
+		else if (info->model[4] == '0' && info->model[5] == '4')
+			type = GW5904;
+		else if (info->model[4] == '0' && info->model[5] == '5')
+			type = GW5905;
+		else if (info->model[4] == '0' && info->model[5] == '6')
+			type = GW5906;
+		else if (info->model[4] == '0' && info->model[5] == '7')
+			type = GW5907;
+		else if (info->model[4] == '0' && info->model[5] == '8')
+			type = GW5908;
+		else if (info->model[4] == '0' && info->model[5] == '9')
+			type = GW5909;
+		break;
+	default:
+		printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
+		print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf,
+				     sizeof(*info));
+		break;
+	}
+	return type;
+}
+
+/* list of config bits that the bootloader will remove from dtb if not set */
+struct ventana_eeprom_config econfig[] = {
+	{ "eth0", "ethernet0", EECONFIG_ETH0 },
+	{ "usb0", NULL, EECONFIG_USB0 },
+	{ "usb1", NULL, EECONFIG_USB1 },
+	{ "mmc0", NULL, EECONFIG_SD0 },
+	{ "mmc1", NULL, EECONFIG_SD1 },
+	{ "mmc2", NULL, EECONFIG_SD2 },
+	{ "mmc3", NULL, EECONFIG_SD3 },
+	{ /* Sentinel */ }
+};
+
+#if defined(CONFIG_CMD_EECONFIG) && !defined(CONFIG_SPL_BUILD)
+static struct ventana_eeprom_config *get_config(const char *name)
+{
+	struct ventana_eeprom_config *cfg = econfig;
+
+	while (cfg->name) {
+		if (0 == strcmp(name, cfg->name))
+			return cfg;
+		cfg++;
+	}
+	return NULL;
+}
+
+static u8 econfig_bytes[sizeof(ventana_info.config)];
+static int econfig_init = -1;
+
+static int do_econfig(struct cmd_tbl *cmdtp, int flag, int argc,
+		      char *const argv[])
+{
+	struct ventana_eeprom_config *cfg;
+	struct ventana_board_info *info = &ventana_info;
+	int i;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	/* initialize */
+	if (econfig_init != 1) {
+		memcpy(econfig_bytes, info->config, sizeof(econfig_bytes));
+		econfig_init = 1;
+	}
+
+	/* list configs */
+	if ((strncmp(argv[1], "list", 4) == 0)) {
+		cfg = econfig;
+		while (cfg->name) {
+			printf("%s: %d\n", cfg->name,
+			       test_bit(cfg->bit, econfig_bytes) ?  1 : 0);
+			cfg++;
+		}
+	}
+
+	/* save */
+	else if ((strncmp(argv[1], "save", 4) == 0)) {
+		unsigned char *buf = (unsigned char *)info;
+		int chksum;
+
+		/* calculate new checksum */
+		memcpy(info->config, econfig_bytes, sizeof(econfig_bytes));
+		for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
+			chksum += buf[i];
+		debug("old chksum:0x%04x\n",
+		      (info->chksum[0] << 8) | info->chksum[1]);
+		debug("new chksum:0x%04x\n", chksum);
+		info->chksum[0] = chksum >> 8;
+		info->chksum[1] = chksum & 0xff;
+
+		/* write new config data */
+		if (gsc_i2c_write(GSC_EEPROM_ADDR, info->config - (u8 *)info,
+				  1, econfig_bytes, sizeof(econfig_bytes))) {
+			printf("EEPROM: Failed updating config\n");
+			return CMD_RET_FAILURE;
+		}
+
+		/* write new config data */
+		if (gsc_i2c_write(GSC_EEPROM_ADDR, info->chksum - (u8 *)info,
+				  1, info->chksum, 2)) {
+			printf("EEPROM: Failed updating checksum\n");
+			return CMD_RET_FAILURE;
+		}
+
+		printf("Config saved to EEPROM\n");
+	}
+
+	/* get config */
+	else if (argc == 2) {
+		cfg = get_config(argv[1]);
+		if (cfg) {
+			printf("%s: %d\n", cfg->name,
+			       test_bit(cfg->bit, econfig_bytes) ? 1 : 0);
+		} else {
+			printf("invalid config: %s\n", argv[1]);
+			return CMD_RET_FAILURE;
+		}
+	}
+
+	/* set config */
+	else if (argc == 3) {
+		cfg = get_config(argv[1]);
+		if (cfg) {
+			if (simple_strtol(argv[2], NULL, 10)) {
+				test_and_set_bit(cfg->bit, econfig_bytes);
+				printf("Enabled %s\n", cfg->name);
+			} else {
+				test_and_clear_bit(cfg->bit, econfig_bytes);
+				printf("Disabled %s\n", cfg->name);
+			}
+		} else {
+			printf("invalid config: %s\n", argv[1]);
+			return CMD_RET_FAILURE;
+		}
+	}
+
+	else
+		return CMD_RET_USAGE;
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	econfig, 3, 0, do_econfig,
+	"EEPROM configuration",
+	"list - list config\n"
+	"save - save config to EEPROM\n"
+	"<name> - get config 'name'\n"
+	"<name> [0|1] - set config 'name' to value\n"
+);
+
+#endif /* CONFIG_CMD_EECONFIG */
diff --git a/roms/u-boot/board/gateworks/gw_ventana/gsc.c b/roms/u-boot/board/gateworks/gw_ventana/gsc.c
new file mode 100644
index 000000000..ffed6b5fc
--- /dev/null
+++ b/roms/u-boot/board/gateworks/gw_ventana/gsc.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <common.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#include <asm/arch/sys_proto.h>
+
+#include "ventana_eeprom.h"
+#include "gsc.h"
+
+/*
+ * The Gateworks System Controller will fail to ACK a master transaction if
+ * it is busy, which can occur during its 1HZ timer tick while reading ADC's.
+ * When this does occur, it will never be busy long enough to fail more than
+ * 2 back-to-back transfers.  Thus we wrap i2c_read and i2c_write with
+ * 3 retries.
+ */
+int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+	int retry = 3;
+	int n = 0;
+	int ret;
+
+	while (n++ < retry) {
+		ret = i2c_read(chip, addr, alen, buf, len);
+		if (!ret)
+			break;
+		debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
+		      n, ret);
+		if (ret != -ENODEV)
+			break;
+		mdelay(10);
+	}
+	return ret;
+}
+
+int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+	int retry = 3;
+	int n = 0;
+	int ret;
+
+	while (n++ < retry) {
+		ret = i2c_write(chip, addr, alen, buf, len);
+		if (!ret)
+			break;
+		debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
+		      n, ret);
+		if (ret != -ENODEV)
+			break;
+		mdelay(10);
+	}
+	mdelay(100);
+	return ret;
+}
+
+static void read_hwmon(const char *name, uint reg, uint size)
+{
+	unsigned char buf[3];
+	uint ui;
+
+	printf("%-8s:", name);
+	memset(buf, 0, sizeof(buf));
+	if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
+		puts("fRD\n");
+	} else {
+		ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
+		if (size == 2 && ui > 0x8000)
+			ui -= 0xffff;
+		if (ui == 0xffffff)
+			puts("invalid\n");
+		else
+			printf("%d\n", ui);
+	}
+}
+
+int gsc_info(int verbose)
+{
+	unsigned char buf[16];
+
+	i2c_set_bus_num(0);
+	if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16))
+		return CMD_RET_FAILURE;
+
+	printf("GSC:   v%d", buf[GSC_SC_FWVER]);
+	printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8);
+	printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN))
+		? "en" : "dis");
+	if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) {
+		buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG);
+		puts(" WDT_RESET");
+		gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
+			      &buf[GSC_SC_STATUS], 1);
+	}
+	if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) {
+		int ui = buf[0] | buf[1]<<8;
+		if (ui > 0x8000)
+			ui -= 0xffff;
+		printf(" board temp at %dC", ui / 10);
+	}
+	puts("\n");
+	if (!verbose)
+		return CMD_RET_SUCCESS;
+
+	read_hwmon("Temp",     GSC_HWMON_TEMP, 2);
+	read_hwmon("VIN",      GSC_HWMON_VIN, 3);
+	read_hwmon("VBATT",    GSC_HWMON_VBATT, 3);
+	read_hwmon("VDD_3P3",  GSC_HWMON_VDD_3P3, 3);
+	read_hwmon("VDD_ARM",  GSC_HWMON_VDD_CORE, 3);
+	read_hwmon("VDD_SOC",  GSC_HWMON_VDD_SOC, 3);
+	read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
+	read_hwmon("VDD_DDR",  GSC_HWMON_VDD_DDR, 3);
+	read_hwmon("VDD_5P0",  GSC_HWMON_VDD_5P0, 3);
+	if (strncasecmp((const char*) ventana_info.model, "GW553", 5))
+		read_hwmon("VDD_2P5",  GSC_HWMON_VDD_2P5, 3);
+	read_hwmon("VDD_1P8",  GSC_HWMON_VDD_1P8, 3);
+	read_hwmon("VDD_IO2",  GSC_HWMON_VDD_IO2, 3);
+	switch (ventana_info.model[3]) {
+	case '1': /* GW51xx */
+		read_hwmon("VDD_IO3",  GSC_HWMON_VDD_IO4, 3); /* -C rev */
+		break;
+	case '2': /* GW52xx */
+		break;
+	case '3': /* GW53xx */
+		read_hwmon("VDD_IO4",  GSC_HWMON_VDD_IO4, 3); /* -C rev */
+		read_hwmon("VDD_GPS",  GSC_HWMON_VDD_IO3, 3);
+		break;
+	case '4': /* GW54xx */
+		read_hwmon("VDD_IO3",  GSC_HWMON_VDD_IO4, 3); /* -C rev */
+		read_hwmon("VDD_GPS",  GSC_HWMON_VDD_IO3, 3);
+		break;
+	case '5': /* GW55xx */
+		break;
+	case '6': /* GW560x */
+		read_hwmon("VDD_IO4",  GSC_HWMON_VDD_IO4, 3);
+		read_hwmon("VDD_GPS",  GSC_HWMON_VDD_IO3, 3);
+		break;
+	case '9': /* GW590x */
+		read_hwmon("AMONBMON",  GSC_HWMON_VDD_IO3, 3);
+		read_hwmon("BAT_VOLT",  GSC_HWMON_VDD_EXT, 3);
+		read_hwmon("BAT_TEMP",  GSC_HWMON_VDD_IO4, 2);
+	}
+	return 0;
+}
+
+/*
+ *  The Gateworks System Controller implements a boot
+ *  watchdog (always enabled) as a workaround for IMX6 boot related
+ *  errata such as:
+ *    ERR005768 - no fix scheduled
+ *    ERR006282 - fixed in silicon r1.2
+ *    ERR007117 - fixed in silicon r1.3
+ *    ERR007220 - fixed in silicon r1.3
+ *    ERR007926 - no fix scheduled
+ *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
+ *
+ * Disable the boot watchdog
+ */
+int gsc_boot_wd_disable(void)
+{
+	u8 reg;
+
+	i2c_set_bus_num(CONFIG_I2C_GSC);
+	if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
+		reg |= (1 << GSC_SC_CTRL1_WDDIS);
+		if (!gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+			return 0;
+	}
+	puts("Error: could not disable GSC Watchdog\n");
+	return 1;
+}
+
+/* determine BOM revision from model */
+int get_bom_rev(const char *str)
+{
+	int  rev_bom = 0;
+	int i;
+
+	for (i = strlen(str) - 1; i > 0; i--) {
+		if (str[i] == '-')
+			break;
+		if (str[i] >= '1' && str[i] <= '9') {
+			rev_bom = str[i] - '0';
+			break;
+		}
+	}
+	return rev_bom;
+}
+
+/* determine PCB revision from model */
+char get_pcb_rev(const char *str)
+{
+	char rev_pcb = 'A';
+	int i;
+
+	for (i = strlen(str) - 1; i > 0; i--) {
+		if (str[i] == '-')
+			break;
+		if (str[i] >= 'A') {
+			rev_pcb = str[i];
+			break;
+		}
+	}
+	return rev_pcb;
+}
+
+/*
+ * get dt name based on model and detail level:
+ */
+const char *gsc_get_dtb_name(int level, char *buf, int sz)
+{
+	const char *model = (const char *)ventana_info.model;
+	const char *pre = is_mx6dq() ? "imx6q-" : "imx6dl-";
+	int modelno, rev_pcb, rev_bom;
+
+	/* a few board models are dt equivalents to other models */
+	if (strncasecmp(model, "gw5906", 6) == 0)
+		model = "gw552x-d";
+	else if (strncasecmp(model, "gw5908", 6) == 0)
+		model = "gw53xx-f";
+	else if (strncasecmp(model, "gw5905", 6) == 0)
+		model = "gw5904-a";
+
+	modelno = ((model[2] - '0') * 1000)
+		  + ((model[3] - '0') * 100)
+		  + ((model[4] - '0') * 10)
+		  + (model[5] - '0');
+	rev_pcb = tolower(get_pcb_rev(model));
+	rev_bom = get_bom_rev(model);
+
+	/* compare model/rev/bom in order of most specific to least */
+	snprintf(buf, sz, "%s%04d", pre, modelno);
+	switch (level) {
+	case 0: /* full model first (ie gw5400-a1) */
+		if (rev_bom) {
+			snprintf(buf, sz, "%sgw%04d-%c%d", pre, modelno, rev_pcb, rev_bom);
+			break;
+		}
+		fallthrough;
+	case 1: /* don't care about bom rev (ie gw5400-a) */
+		snprintf(buf, sz, "%sgw%04d-%c", pre, modelno, rev_pcb);
+		break;
+	case 2: /* don't care about the pcb rev (ie gw5400) */
+		snprintf(buf, sz, "%sgw%04d", pre, modelno);
+		break;
+	case 3: /* look for generic model (ie gw540x) */
+		snprintf(buf, sz, "%sgw%03dx", pre, modelno / 10);
+		break;
+	case 4: /* look for more generic model (ie gw54xx) */
+		snprintf(buf, sz, "%sgw%02dxx", pre, modelno / 100);
+		break;
+	default: /* give up */
+		return NULL;
+	}
+
+	return buf;
+}
+
+#if defined(CONFIG_CMD_GSC) && !defined(CONFIG_SPL_BUILD)
+static int do_gsc_sleep(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	unsigned char reg;
+	unsigned long secs = 0;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	secs = simple_strtoul(argv[1], NULL, 10);
+	printf("GSC Sleeping for %ld seconds\n", secs);
+
+	i2c_set_bus_num(0);
+	reg = (secs >> 24) & 0xff;
+	if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, &reg, 1))
+		goto error;
+	reg = (secs >> 16) & 0xff;
+	if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, &reg, 1))
+		goto error;
+	reg = (secs >> 8) & 0xff;
+	if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, &reg, 1))
+		goto error;
+	reg = secs & 0xff;
+	if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, &reg, 1))
+		goto error;
+	if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+		goto error;
+	reg |= (1 << 2);
+	if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+		goto error;
+	reg &= ~(1 << 2);
+	reg |= 0x3;
+	if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+		goto error;
+
+	return CMD_RET_SUCCESS;
+
+error:
+	printf("i2c error\n");
+	return CMD_RET_FAILURE;
+}
+
+static int do_gsc_wd(struct cmd_tbl *cmdtp, int flag, int argc,
+		     char *const argv[])
+{
+	unsigned char reg;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	if (strcasecmp(argv[1], "enable") == 0) {
+		int timeout = 0;
+
+		if (argc > 2)
+			timeout = simple_strtoul(argv[2], NULL, 10);
+		i2c_set_bus_num(0);
+		if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+			return CMD_RET_FAILURE;
+		reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
+		if (timeout == 60)
+			reg |= (1 << GSC_SC_CTRL1_WDTIME);
+		else
+			timeout = 30;
+		reg |= (1 << GSC_SC_CTRL1_WDEN);
+		if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+			return CMD_RET_FAILURE;
+		printf("GSC Watchdog enabled with timeout=%d seconds\n",
+		       timeout);
+	} else if (strcasecmp(argv[1], "disable") == 0) {
+		i2c_set_bus_num(0);
+		if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+			return CMD_RET_FAILURE;
+		reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
+		if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+			return CMD_RET_FAILURE;
+		printf("GSC Watchdog disabled\n");
+	} else {
+		return CMD_RET_USAGE;
+	}
+	return CMD_RET_SUCCESS;
+}
+
+static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	if (argc < 2)
+		return gsc_info(1);
+
+	if (strcasecmp(argv[1], "wd") == 0)
+		return do_gsc_wd(cmdtp, flag, --argc, ++argv);
+	else if (strcasecmp(argv[1], "sleep") == 0)
+		return do_gsc_sleep(cmdtp, flag, --argc, ++argv);
+
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+	gsc, 4, 1, do_gsc, "GSC configuration",
+	"[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n"
+	);
+
+#endif /* CONFIG_CMD_GSC */
diff --git a/roms/u-boot/board/gateworks/gw_ventana/gsc.h b/roms/u-boot/board/gateworks/gw_ventana/gsc.h
new file mode 100644
index 000000000..29d375b3a
--- /dev/null
+++ b/roms/u-boot/board/gateworks/gw_ventana/gsc.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ */
+
+#ifndef __ASSEMBLY__
+
+/* i2c slave addresses */
+#define GSC_SC_ADDR		0x20
+#define GSC_RTC_ADDR		0x68
+#define GSC_HWMON_ADDR		0x29
+#define GSC_EEPROM_ADDR		0x51
+
+/* System Controller registers */
+enum {
+	GSC_SC_CTRL0		= 0x00,
+	GSC_SC_CTRL1		= 0x01,
+	GSC_SC_STATUS		= 0x0a,
+	GSC_SC_FWCRC		= 0x0c,
+	GSC_SC_FWVER		= 0x0e,
+};
+
+/* System Controller Control1 bits */
+enum {
+	GSC_SC_CTRL1_WDTIME	= 4, /* 1 = 60s timeout, 0 = 30s timeout */
+	GSC_SC_CTRL1_WDEN	= 5, /* 1 = enable, 0 = disable */
+	GSC_SC_CTRL1_WDDIS	= 7, /* 1 = disable boot watchdog */
+};
+
+/* System Controller Interrupt bits */
+enum {
+	GSC_SC_IRQ_PB		= 0, /* Pushbutton switch */
+	GSC_SC_IRQ_SECURE	= 1, /* Secure Key erase operation complete */
+	GSC_SC_IRQ_EEPROM_WP	= 2, /* EEPROM write violation */
+	GSC_SC_IRQ_GPIO		= 4, /* GPIO change */
+	GSC_SC_IRQ_TAMPER	= 5, /* Tamper detect */
+	GSC_SC_IRQ_WATCHDOG	= 6, /* Watchdog trip */
+	GSC_SC_IRQ_PBLONG	= 7, /* Pushbutton long hold */
+};
+
+/* Hardware Monitor registers */
+enum {
+	GSC_HWMON_TEMP		= 0x00,
+	GSC_HWMON_VIN		= 0x02,
+	GSC_HWMON_VDD_3P3	= 0x05,
+	GSC_HWMON_VBATT		= 0x08,
+	GSC_HWMON_VDD_5P0	= 0x0b,
+	GSC_HWMON_VDD_CORE	= 0x0e,
+	GSC_HWMON_VDD_SOC	= 0x11,
+	GSC_HWMON_VDD_HIGH	= 0x14,
+	GSC_HWMON_VDD_DDR	= 0x17,
+	GSC_HWMON_VDD_EXT	= 0x1a,
+	GSC_HWMON_VDD_1P8	= 0x1d,
+	GSC_HWMON_VDD_IO2	= 0x20,
+	GSC_HWMON_VDD_2P5	= 0x23,
+	GSC_HWMON_VDD_IO3	= 0x26,
+	GSC_HWMON_VDD_IO4	= 0x29,
+};
+
+/*
+ * I2C transactions to the GSC are done via these functions which
+ * perform retries in the case of a busy GSC NAK'ing the transaction
+ */
+int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len);
+int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len);
+int gsc_info(int verbose);
+int gsc_boot_wd_disable(void);
+const char *gsc_get_dtb_name(int level, char *buf, int sz);
+#endif
+
diff --git a/roms/u-boot/board/gateworks/gw_ventana/gw_ventana.c b/roms/u-boot/board/gateworks/gw_ventana/gw_ventana.c
new file mode 100644
index 000000000..1ed9c1a39
--- /dev/null
+++ b/roms/u-boot/board/gateworks/gw_ventana/gw_ventana.c
@@ -0,0 +1,1223 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <dm.h>
+#include <env.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <jffs2/load_kernel.h>
+#include <linux/ctype.h>
+#include <miiphy.h>
+#include <mtd_node.h>
+#include <pci.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <power/pmic.h>
+#include <power/ltc3676_pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <fdt_support.h>
+#include <jffs2/load_kernel.h>
+
+#include "gsc.h"
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+/*
+ * EEPROM board info struct populated by read_eeprom so that we only have to
+ * read it once.
+ */
+struct ventana_board_info ventana_info;
+static int board_type;
+
+#ifdef CONFIG_USB_EHCI_MX6
+/* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
+int board_ehci_hcd_init(int port)
+{
+	int gpio;
+
+	/* USB HUB is always on P1 */
+	if (port == 0)
+		return 0;
+
+	/* Reset USB HUB */
+	switch (board_type) {
+	case GW53xx:
+	case GW552x:
+	case GW5906:
+		gpio = (IMX_GPIO_NR(1, 9));
+		break;
+	case GW54proto:
+	case GW54xx:
+		gpio = (IMX_GPIO_NR(1, 16));
+		break;
+	default:
+		return 0;
+	}
+
+	/* request and toggle hub rst */
+	gpio_request(gpio, "usb_hub_rst#");
+	gpio_direction_output(gpio, 0);
+	mdelay(2);
+	gpio_set_value(gpio, 1);
+
+	return 0;
+}
+#endif /* CONFIG_USB_EHCI_MX6 */
+
+/* configure eth0 PHY board-specific LED behavior */
+int board_phy_config(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* Marvel 88E1510 */
+	if (phydev->phy_id == 0x1410dd1) {
+		/*
+		 * Page 3, Register 16: LED[2:0] Function Control Register
+		 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
+		 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
+		 */
+		phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
+		val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
+		val &= 0xff00;
+		val |= 0x0017;
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
+		phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
+	}
+
+	/* TI DP83867 */
+	else if (phydev->phy_id == 0x2000a231) {
+		/* configure register 0x170 for ref CLKOUT */
+		phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
+		phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
+		phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
+		val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
+		val &= ~0x1f00;
+		val |= 0x0b00; /* chD tx clock*/
+		phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
+	}
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+	struct mii_dev *bus = phydev->bus;
+
+	/* GPIO[0] output, CLK125 */
+	debug("enabling RGMII_REFCLK\n");
+	bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
+		   0x1a /*MV_SCRATCH_MISC*/,
+		   (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
+	bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
+		   0x1a /*MV_SCRATCH_MISC*/,
+		   (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
+
+	/* RGMII delay - Physical Control register bit[15:14] */
+	debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
+	/* forced 1000mbps full-duplex link */
+	bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
+	phydev->autoneg = AUTONEG_DISABLE;
+	phydev->speed = SPEED_1000;
+	phydev->duplex = DUPLEX_FULL;
+
+	/* LED configuration: 7:4-green (8=Activity)  3:0 amber (8=Link) */
+	bus->write(bus, 0x10, 0, 0x16, 0x8088);
+	bus->write(bus, 0x11, 0, 0x16, 0x8088);
+	bus->write(bus, 0x12, 0, 0x16, 0x8088);
+	bus->write(bus, 0x13, 0, 0x16, 0x8088);
+
+	return 0;
+}
+#endif // CONFIG_MV88E61XX_SWITCH
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static void enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+	return i2c_set_bus_num(dev->bus) == 0 &&
+		i2c_probe(dev->addr) == 0;
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)
+				IOMUXC_BASE_ADDR;
+
+	/* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
+	u32 reg = readl(&iomux->gpr[2]);
+	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+	writel(reg, &iomux->gpr[2]);
+
+	/* Enable Backlight */
+	gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
+	gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
+	gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
+	SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
+	gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
+}
+
+struct display_info_t const displays[] = {{
+	/* HDMI Output */
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	/* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
+	.bus	= 2,
+	.addr	= 0x4,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.detect	= detect_i2c,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "Hannstar-XGA",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	/* DLC700JMG-T-4 */
+	.bus	= 2,
+	.addr	= 0x38,
+	.detect	= NULL,
+	.enable	= enable_lvds,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.mode	= {
+		.name           = "DLC700JMGT4",
+		.refresh        = 60,
+		.xres           = 1024,		/* 1024x600active pixels */
+		.yres           = 600,
+		.pixclock       = 15385,	/* 64MHz */
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	/* DLC800FIG-T-3 */
+	.bus	= 2,
+	.addr	= 0x14,
+	.detect	= NULL,
+	.enable	= enable_lvds,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.mode	= {
+		.name           = "DLC800FIGT3",
+		.refresh        = 60,
+		.xres           = 1024,		/* 1024x768 active pixels */
+		.yres           = 768,
+		.pixclock       = 15385,	/* 64MHz */
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 2,
+	.addr	= 0x5d,
+	.detect	= detect_i2c,
+	.enable	= enable_lvds,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.mode	= {
+		.name           = "Z101WX01",
+		.refresh        = 60,
+		.xres           = 1280,
+		.yres           = 800,
+		.pixclock       = 15385,	/* 64MHz */
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+	}
+},
+};
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+	/* Turn on LDB0,IPU,IPU DI0 clocks */
+	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+	      |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	     |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+	     |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+	     |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+	     |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+
+	/* LVDS Backlight GPIO on LVDS connector - output low */
+	SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
+	gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	setup_pmic();
+	return 0;
+}
+
+int imx6_pcie_toggle_reset(void)
+{
+	if (board_type < GW_UNKNOWN) {
+		uint pin = gpio_cfg[board_type].pcie_rst;
+		gpio_request(pin, "pci_rst#");
+		gpio_direction_output(pin, 0);
+		mdelay(50);
+		gpio_direction_output(pin, 1);
+	}
+	return 0;
+}
+
+/*
+ * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
+ * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
+ * properly and assert reset for 100ms.
+ */
+#define MAX_PCI_DEVS	32
+struct pci_dev {
+	pci_dev_t devfn;
+	struct udevice *dev;
+	unsigned short vendor;
+	unsigned short device;
+	unsigned short class;
+	unsigned short busno; /* subbordinate busno */
+	struct pci_dev *ppar;
+};
+struct pci_dev pci_devs[MAX_PCI_DEVS];
+int pci_devno;
+int pci_bridgeno;
+
+void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev)
+{
+	struct pci_child_plat *pdata = dev_get_parent_plat(udev);
+	struct pci_dev *pdev = &pci_devs[pci_devno++];
+	unsigned short vendor = pdata->vendor;
+	unsigned short device = pdata->device;
+	unsigned int class = pdata->class;
+	pci_dev_t dev = dm_pci_get_bdf(udev);
+	int i;
+
+	debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
+	      PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
+
+	/* store array of devs for later use in device-tree fixup */
+	pdev->dev = udev;
+	pdev->devfn = dev;
+	pdev->vendor = vendor;
+	pdev->device = device;
+	pdev->class = class;
+	pdev->ppar = NULL;
+	if (class == PCI_CLASS_BRIDGE_PCI)
+		pdev->busno = ++pci_bridgeno;
+	else
+		pdev->busno = 0;
+
+	/* fixup RC - it should be 00:00.0 not 00:01.0 */
+	if (PCI_BUS(dev) == 0)
+		pdev->devfn = 0;
+
+	/* find dev's parent */
+	for (i = 0; i < pci_devno; i++) {
+		if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
+			pdev->ppar = &pci_devs[i];
+			break;
+		}
+	}
+
+	/* assert downstream PERST# */
+	if (vendor == PCI_VENDOR_ID_PLX &&
+	    (device & 0xfff0) == 0x8600 &&
+	    PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
+		ulong val;
+		debug("configuring PLX 860X downstream PERST#\n");
+		pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32);
+		val |= 0xaaa8; /* GPIO1-7 outputs */
+		pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32);
+
+		pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32);
+		val |= 0xfe;   /* GPIO1-7 output high */
+		pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32);
+
+		mdelay(100);
+	}
+}
+
+#ifdef CONFIG_SERIAL_TAG
+/*
+ * called when setting up ATAGS before booting kernel
+ * populate serialnum from the following (in order of priority):
+ *   serial# env var
+ *   eeprom
+ */
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *serial = env_get("serial#");
+
+	if (serial) {
+		serialnr->high = 0;
+		serialnr->low = simple_strtoul(serial, NULL, 10);
+	} else if (ventana_info.model[0]) {
+		serialnr->high = 0;
+		serialnr->low = ventana_info.serial;
+	} else {
+		serialnr->high = 0;
+		serialnr->low = 0;
+	}
+}
+#endif
+
+/*
+ * Board Support
+ */
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+int board_init(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[1],
+			IOMUXC_GPR1_OTG_ID_MASK,
+			IOMUXC_GPR1_OTG_ID_GPIO1);
+
+	/* address of linux boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* read Gateworks EEPROM into global struct (used later) */
+	setup_ventana_i2c(0);
+	board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+
+	setup_ventana_i2c(1);
+	setup_ventana_i2c(2);
+
+	setup_iomux_gpio(board_type, &ventana_info);
+
+	return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	static char init;
+	const char *dtb;
+	char buf[32];
+	int i = 0;
+
+	do {
+		dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
+		if (dtb && !strcmp(dtb, name)) {
+			if (!init++)
+				printf("DTB:   %s\n", name);
+			return 0;
+		}
+	} while (dtb);
+
+	return -1;
+}
+
+#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
+/*
+ * called during late init (after relocation and after board_init())
+ * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
+ * EEPROM read.
+ */
+int checkboard(void)
+{
+	struct ventana_board_info *info = &ventana_info;
+	unsigned char buf[4];
+	const char *p;
+	int quiet; /* Quiet or minimal output mode */
+
+	quiet = 0;
+	p = env_get("quiet");
+	if (p)
+		quiet = simple_strtol(p, NULL, 10);
+	else
+		env_set("quiet", "0");
+
+	puts("\nGateworks Corporation Copyright 2014\n");
+	if (info->model[0]) {
+		printf("Model: %s\n", info->model);
+		printf("MFGDate: %02x-%02x-%02x%02x\n",
+		       info->mfgdate[0], info->mfgdate[1],
+		       info->mfgdate[2], info->mfgdate[3]);
+		printf("Serial:%d\n", info->serial);
+	} else {
+		puts("Invalid EEPROM - board will not function fully\n");
+	}
+	if (quiet)
+		return 0;
+
+	/* Display GSC firmware revision/CRC/status */
+	gsc_info(0);
+
+	/* Display RTC */
+	if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
+		printf("RTC:   %d\n",
+		       buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+/*
+ * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
+ * see Table 8-11 and Table 5-9
+ *  BOOT_CFG1[7] = 1 (boot from NAND)
+ *  BOOT_CFG1[5] = 0 - raw NAND
+ *  BOOT_CFG1[4] = 0 - default pad settings
+ *  BOOT_CFG1[3:2] = 00 - devices = 1
+ *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
+ *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
+ *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
+ *  BOOT_CFG2[0] = 0 - Reset time 12ms
+ */
+static const struct boot_mode board_boot_modes[] = {
+	/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
+	{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
+	{ "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
+	{ "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
+	{ NULL, 0 },
+};
+#endif
+
+/* late init */
+int misc_init_r(void)
+{
+	struct ventana_board_info *info = &ventana_info;
+	char buf[256];
+	int i;
+
+	/* set env vars based on EEPROM data */
+	if (ventana_info.model[0]) {
+		char str[16], fdt[36];
+		char *p;
+		const char *cputype = "";
+
+		/*
+		 * FDT name will be prefixed with CPU type.  Three versions
+		 * will be created each increasingly generic and bootloader
+		 * env scripts will try loading each from most specific to
+		 * least.
+		 */
+		if (is_cpu_type(MXC_CPU_MX6Q) ||
+		    is_cpu_type(MXC_CPU_MX6D))
+			cputype = "imx6q";
+		else if (is_cpu_type(MXC_CPU_MX6DL) ||
+			 is_cpu_type(MXC_CPU_MX6SOLO))
+			cputype = "imx6dl";
+		env_set("soctype", cputype);
+		if (8 << (ventana_info.nand_flash_size-1) >= 2048)
+			env_set("flash_layout", "large");
+		else
+			env_set("flash_layout", "normal");
+		memset(str, 0, sizeof(str));
+		for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
+			str[i] = tolower(info->model[i]);
+		env_set("model", str);
+		if (!env_get("fdt_file")) {
+			sprintf(fdt, "%s-%s.dtb", cputype, str);
+			env_set("fdt_file", fdt);
+		}
+		p = strchr(str, '-');
+		if (p) {
+			*p++ = 0;
+
+			env_set("model_base", str);
+			sprintf(fdt, "%s-%s.dtb", cputype, str);
+			env_set("fdt_file1", fdt);
+			if (board_type != GW551x &&
+			    board_type != GW552x &&
+			    board_type != GW553x &&
+			    board_type != GW560x)
+				str[4] = 'x';
+			str[5] = 'x';
+			str[6] = 0;
+			sprintf(fdt, "%s-%s.dtb", cputype, str);
+			env_set("fdt_file2", fdt);
+		}
+
+		/* initialize env from EEPROM */
+		if (test_bit(EECONFIG_ETH0, info->config) &&
+		    !env_get("ethaddr")) {
+			eth_env_set_enetaddr("ethaddr", info->mac0);
+		}
+		if (test_bit(EECONFIG_ETH1, info->config) &&
+		    !env_get("eth1addr")) {
+			eth_env_set_enetaddr("eth1addr", info->mac1);
+		}
+
+		/* board serial-number */
+		sprintf(str, "%6d", info->serial);
+		env_set("serial#", str);
+
+		/* memory MB */
+		sprintf(str, "%d", (int) (gd->ram_size >> 20));
+		env_set("mem_mb", str);
+	}
+
+	/* Set a non-initialized hwconfig based on board configuration */
+	if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
+		buf[0] = 0;
+		if (gpio_cfg[board_type].rs232_en)
+			strcat(buf, "rs232;");
+		for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
+			char buf1[32];
+			sprintf(buf1, "dio%d:mode=gpio;", i);
+			if (strlen(buf) + strlen(buf1) < sizeof(buf))
+				strcat(buf, buf1);
+		}
+		env_set("hwconfig", buf);
+	}
+
+	/* setup baseboard specific GPIO based on board and env */
+	setup_board_gpio(board_type, info);
+
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	/* disable boot watchdog */
+	gsc_boot_wd_disable();
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+
+static int ft_sethdmiinfmt(void *blob, char *mode)
+{
+	int off;
+
+	if (!mode)
+		return -EINVAL;
+
+	off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
+	if (off < 0)
+		return off;
+
+	if (0 == strcasecmp(mode, "yuv422bt656")) {
+		u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
+			     0x00, 0x00, 0x00 };
+		mode = "422_ccir";
+		fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
+		fdt_setprop_u32(blob, off, "vidout_trc", 1);
+		fdt_setprop_u32(blob, off, "vidout_blc", 1);
+		fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
+		printf("   set HDMI input mode to %s\n", mode);
+	} else if (0 == strcasecmp(mode, "yuv422smp")) {
+		u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
+			     0x82, 0x81, 0x00 };
+		mode = "422_smp";
+		fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
+		fdt_setprop_u32(blob, off, "vidout_trc", 0);
+		fdt_setprop_u32(blob, off, "vidout_blc", 0);
+		fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
+		printf("   set HDMI input mode to %s\n", mode);
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_CMD_PCI)
+#define PCI_ID(x) ( \
+	(PCI_BUS(x->devfn)<<16)| \
+	(PCI_DEV(x->devfn)<<11)| \
+	(PCI_FUNC(x->devfn)<<8) \
+	)
+int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
+{
+	uint32_t reg[5];
+	char node[32];
+	int np;
+
+	sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
+		PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
+
+	np = fdt_subnode_offset(blob, par, node);
+	if (np >= 0)
+		return np;
+	np = fdt_add_subnode(blob, par, node);
+	if (np < 0) {
+		printf("   %s failed: no space\n", __func__);
+		return np;
+	}
+
+	memset(reg, 0, sizeof(reg));
+	reg[0] = cpu_to_fdt32(PCI_ID(dev));
+	fdt_setprop(blob, np, "reg", reg, sizeof(reg));
+
+	return np;
+}
+
+/* build a path of nested PCI devs for all bridges passed through */
+int fdt_add_pci_path(void *blob, struct pci_dev *dev)
+{
+	struct pci_dev *bridges[MAX_PCI_DEVS];
+	int k, np;
+
+	/* build list of parents */
+	np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
+	if (np < 0)
+		return np;
+
+	k = 0;
+	while (dev) {
+		bridges[k++] = dev;
+		dev = dev->ppar;
+	};
+
+	/* now add them the to DT in reverse order */
+	while (k--) {
+		np = fdt_add_pci_node(blob, np, bridges[k]);
+		if (np < 0)
+			break;
+	}
+
+	return np;
+}
+
+/*
+ * The GW16082 has a hardware errata errata such that it's
+ * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
+ * of this normal PCI interrupt swizzling will not work so we will
+ * provide an irq-map via device-tree.
+ */
+int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
+{
+	int len;
+	int host;
+	uint32_t imap_new[8*4*4];
+	const uint32_t *imap;
+	uint32_t irq[4];
+	uint32_t reg[4];
+	int i;
+
+	/* build irq-map based on host controllers map */
+	host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
+	if (host < 0) {
+		printf("   %s failed: missing host\n", __func__);
+		return host;
+	}
+
+	/* use interrupt data from root complex's node */
+	imap = fdt_getprop(blob, host, "interrupt-map", &len);
+	if (!imap || len != 128) {
+		printf("   %s failed: invalid interrupt-map\n",
+		       __func__);
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	/* obtain irq's of host controller in pin order */
+	for (i = 0; i < 4; i++)
+		irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
+
+	/*
+	 * determine number of swizzles necessary:
+	 *   For each bridge we pass through we need to swizzle
+	 *   the number of the slot we are on.
+	 */
+	struct pci_dev *d;
+	int b;
+	b = 0;
+	d = dev->ppar;
+	while(d && d->ppar) {
+		b += PCI_DEV(d->devfn);
+		d = d->ppar;
+	}
+
+	/* create new irq mappings for slots12-15
+	 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
+	 * J3    AD28    12     INTD      INTA
+	 * J4    AD29    13     INTC      INTD
+	 * J5    AD30    14     INTB      INTC
+	 * J2    AD31    15     INTA      INTB
+	 */
+	for (i = 0; i < 4; i++) {
+		/* addr matches bus:dev:func */
+		u32 addr = dev->busno << 16 | (12+i) << 11;
+
+		/* default cells from root complex */
+		memcpy(&imap_new[i*32], imap, 128);
+		/* first cell is PCI device address (BDF) */
+		imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
+		imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
+		imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
+		imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
+		/* third cell is pin */
+		imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
+		imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
+		imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
+		imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
+		/* sixth cell is relative interrupt */
+		imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
+		imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
+		imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
+		imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
+	}
+	fdt_setprop(blob, np, "interrupt-map", imap_new,
+		    sizeof(imap_new));
+	reg[0] = cpu_to_fdt32(0xfff00);
+	reg[1] = 0;
+	reg[2] = 0;
+	reg[3] = cpu_to_fdt32(0x7);
+	fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
+	fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
+	fdt_setprop_string(blob, np, "device_type", "pci");
+	fdt_setprop_cell(blob, np, "#address-cells", 3);
+	fdt_setprop_cell(blob, np, "#size-cells", 2);
+	printf("   Added custom interrupt-map for GW16082\n");
+
+	return 0;
+}
+
+/* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
+int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
+{
+	char *tmp, *end;
+	char mac[16];
+	unsigned char mac_addr[6];
+	int j;
+
+	sprintf(mac, "eth1addr");
+	tmp = env_get(mac);
+	if (tmp) {
+		for (j = 0; j < 6; j++) {
+			mac_addr[j] = tmp ?
+				      simple_strtoul(tmp, &end,16) : 0;
+			if (tmp)
+				tmp = (*end) ? end+1 : end;
+		}
+		fdt_setprop(blob, np, "local-mac-address", mac_addr,
+			    sizeof(mac_addr));
+		printf("   Added mac addr for eth1\n");
+		return 0;
+	}
+
+	return -1;
+}
+
+/*
+ * PCI DT nodes must be nested therefore if we need to apply a DT fixup
+ * we will walk the PCI bus and add bridge nodes up to the device receiving
+ * the fixup.
+ */
+void ft_board_pci_fixup(void *blob, struct bd_info *bd)
+{
+	int i, np;
+	struct pci_dev *dev;
+
+	for (i = 0; i < pci_devno; i++) {
+		dev = &pci_devs[i];
+
+		/*
+		 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
+		 * an EEPROM at i2c1-0x50.
+		 */
+		if ((dev->vendor == PCI_VENDOR_ID_TI) &&
+		    (dev->device == 0x8240) &&
+		    (i2c_set_bus_num(1) == 0) &&
+		    (i2c_probe(0x50) == 0))
+		{
+			np = fdt_add_pci_path(blob, dev);
+			if (np > 0)
+				fdt_fixup_gw16082(blob, np, dev);
+		}
+
+		/* ethernet1 mac address */
+		else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
+		         (dev->device == 0x4380))
+		{
+			np = fdt_add_pci_path(blob, dev);
+			if (np > 0)
+				fdt_fixup_sky2(blob, np, dev);
+		}
+	}
+}
+#endif /* if defined(CONFIG_CMD_PCI) */
+
+void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
+{
+	int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
+
+	if (off) {
+		fdt_delprop(blob, off, "ext-reset-output");
+		fdt_delprop(blob, off, "fsl,ext-reset-output");
+	}
+}
+
+/*
+ * called prior to booting kernel or by 'fdt boardsetup' command
+ *
+ * unless 'fdt_noauto' env var is set we will update the following in the DTB:
+ *  - mtd partitions based on mtdparts/mtdids env
+ *  - system-serial (board serial num from EEPROM)
+ *  - board (full model from EEPROM)
+ *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
+ */
+#define WDOG1_ADDR	0x20bc000
+#define WDOG2_ADDR	0x20c0000
+#define GPIO3_ADDR	0x20a4000
+#define USDHC3_ADDR	0x2198000
+#define PWM0_ADDR	0x2080000
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	struct ventana_board_info *info = &ventana_info;
+	struct ventana_eeprom_config *cfg;
+	static const struct node_info nodes[] = {
+		{ "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
+		{ "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
+	};
+	const char *model = env_get("model");
+	const char *display = env_get("display");
+	int i;
+	char rev = 0;
+
+	/* determine board revision */
+	for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
+		if (ventana_info.model[i] >= 'A') {
+			rev = ventana_info.model[i];
+			break;
+		}
+	}
+
+	if (env_get("fdt_noauto")) {
+		puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
+		return 0;
+	}
+
+	if (test_bit(EECONFIG_NAND, info->config)) {
+		/* Update partition nodes using info from mtdparts env var */
+		puts("   Updating MTD partitions...\n");
+		fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+	}
+
+	/* Update display timings from display env var */
+	if (display) {
+		if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
+				      display) >= 0)
+			printf("   Set display timings for %s...\n", display);
+	}
+
+	printf("   Adjusting FDT per EEPROM for %s...\n", model);
+
+	/* board serial number */
+	fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
+		    strlen(env_get("serial#")) + 1);
+
+	/* board (model contains model from device-tree) */
+	fdt_setprop(blob, 0, "board", info->model,
+		    strlen((const char *)info->model) + 1);
+
+	/* set desired digital video capture format */
+	ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
+
+	/*
+	 * Board model specific fixups
+	 */
+	switch (board_type) {
+	case GW51xx:
+		/*
+		 * disable wdog node for GW51xx-A/B to work around
+		 * errata causing wdog timer to be unreliable.
+		 */
+		if (rev >= 'A' && rev < 'C') {
+			i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
+							  WDOG1_ADDR);
+			if (i)
+				fdt_status_disabled(blob, i);
+		}
+
+		/* GW51xx-E adds WDOG1_B external reset */
+		if (rev < 'E')
+			ft_board_wdog_fixup(blob, WDOG1_ADDR);
+		break;
+
+	case GW52xx:
+		/* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
+		if (info->model[4] == '2') {
+			u32 handle = 0;
+			u32 *range = NULL;
+
+			i = fdt_node_offset_by_compatible(blob, -1,
+							  "fsl,imx6q-pcie");
+			if (i)
+				range = (u32 *)fdt_getprop(blob, i,
+							   "reset-gpio", NULL);
+
+			if (range) {
+				i = fdt_node_offset_by_compat_reg(blob,
+					"fsl,imx6q-gpio", GPIO3_ADDR);
+				if (i)
+					handle = fdt_get_phandle(blob, i);
+				if (handle) {
+					range[0] = cpu_to_fdt32(handle);
+					range[1] = cpu_to_fdt32(23);
+				}
+			}
+
+			/* these have broken usd_vsel */
+			if (strstr((const char *)info->model, "SP318-B") ||
+			    strstr((const char *)info->model, "SP331-B"))
+				gpio_cfg[board_type].usd_vsel = 0;
+
+			/* GW522x-B adds WDOG1_B external reset */
+			if (rev < 'B')
+				ft_board_wdog_fixup(blob, WDOG1_ADDR);
+		}
+
+		/* GW520x-E adds WDOG1_B external reset */
+		else if (info->model[4] == '0' && rev < 'E')
+			ft_board_wdog_fixup(blob, WDOG1_ADDR);
+		break;
+
+	case GW53xx:
+		/* GW53xx-E adds WDOG1_B external reset */
+		if (rev < 'E')
+			ft_board_wdog_fixup(blob, WDOG1_ADDR);
+		break;
+
+	case GW54xx:
+		/*
+		 * disable serial2 node for GW54xx for compatibility with older
+		 * 3.10.x kernel that improperly had this node enabled in the DT
+		 */
+		fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
+					0);
+
+		/* GW54xx-E adds WDOG2_B external reset */
+		if (rev < 'E')
+			ft_board_wdog_fixup(blob, WDOG2_ADDR);
+		break;
+
+	case GW551x:
+		/*
+		 * isolate CSI0_DATA_EN for GW551x-A to work around errata
+		 * causing non functional digital video in (it is not hooked up)
+		 */
+		if (rev == 'A') {
+			u32 *range = NULL;
+			int len;
+			const u32 *handle = NULL;
+
+			i = fdt_node_offset_by_compatible(blob, -1,
+						"fsl,imx-tda1997x-video");
+			if (i)
+				handle = fdt_getprop(blob, i, "pinctrl-0",
+						     NULL);
+			if (handle)
+				i = fdt_node_offset_by_phandle(blob,
+							fdt32_to_cpu(*handle));
+			if (i)
+				range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
+							   &len);
+			if (range) {
+				len /= sizeof(u32);
+				for (i = 0; i < len; i += 6) {
+					u32 mux_reg = fdt32_to_cpu(range[i+0]);
+					u32 conf_reg = fdt32_to_cpu(range[i+1]);
+					/* mux PAD_CSI0_DATA_EN to GPIO */
+					if (is_cpu_type(MXC_CPU_MX6Q) &&
+					    mux_reg == 0x260 &&
+					    conf_reg == 0x630)
+						range[i+3] = cpu_to_fdt32(0x5);
+					else if (!is_cpu_type(MXC_CPU_MX6Q) &&
+						 mux_reg == 0x08c &&
+						 conf_reg == 0x3a0)
+						range[i+3] = cpu_to_fdt32(0x5);
+				}
+				fdt_setprop_inplace(blob, i, "fsl,pins", range,
+						    len);
+			}
+
+			/* set BT656 video format */
+			ft_sethdmiinfmt(blob, "yuv422bt656");
+		}
+
+		/* GW551x-C adds WDOG1_B external reset */
+		if (rev < 'C')
+			ft_board_wdog_fixup(blob, WDOG1_ADDR);
+		break;
+	case GW5901:
+	case GW5902:
+		/* GW5901/GW5901 revB adds WDOG1_B as an external reset */
+		if (rev < 'B')
+			ft_board_wdog_fixup(blob, WDOG1_ADDR);
+		break;
+	}
+
+	/* Configure DIO */
+	for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
+		struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
+		char arg[10];
+
+		sprintf(arg, "dio%d", i);
+		if (!hwconfig(arg))
+			continue;
+		if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
+		{
+			phys_addr_t addr;
+			int off;
+
+			printf("   Enabling pwm%d for DIO%d\n",
+			       cfg->pwm_param, i);
+			addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
+			off = fdt_node_offset_by_compat_reg(blob,
+							    "fsl,imx6q-pwm",
+							    addr);
+			if (off)
+				fdt_status_okay(blob, off);
+		}
+	}
+
+	/* remove no-1-8-v if UHS-I support is present */
+	if (gpio_cfg[board_type].usd_vsel) {
+		debug("Enabling UHS-I support\n");
+		i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
+						  USDHC3_ADDR);
+		if (i)
+			fdt_delprop(blob, i, "no-1-8-v");
+	}
+
+#if defined(CONFIG_CMD_PCI)
+	if (!env_get("nopcifixup"))
+		ft_board_pci_fixup(blob, bd);
+#endif
+
+	/*
+	 * Peripheral Config:
+	 *  remove nodes by alias path if EEPROM config tells us the
+	 *  peripheral is not loaded on the board.
+	 */
+	if (env_get("fdt_noconfig")) {
+		puts("   Skiping periperhal config (fdt_noconfig defined)\n");
+		return 0;
+	}
+	cfg = econfig;
+	while (cfg->name) {
+		if (!test_bit(cfg->bit, info->config)) {
+			fdt_del_node_and_alias(blob, cfg->dtalias ?
+					       cfg->dtalias : cfg->name);
+		}
+		cfg++;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/roms/u-boot/board/gateworks/gw_ventana/gw_ventana_spl.c b/roms/u-boot/board/gateworks/gw_ventana/gw_ventana_spl.c
new file mode 100644
index 000000000..a4f64395a
--- /dev/null
+++ b/roms/u-boot/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -0,0 +1,787 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <env.h>
+#include <i2c.h>
+#include <spl.h>
+
+#include "gsc.h"
+#include "common.h"
+
+#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
+#define GSC_EEPROM_DDR_SIZE	0x2B	/* enum (512,1024,2048) MB */
+#define GSC_EEPROM_DDR_WIDTH	0x2D	/* enum (32,64) bit */
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+	.dram_sdclk_0 = 0x00020030,
+	.dram_sdclk_1 = 0x00020030,
+	.dram_cas = 0x00020030,
+	.dram_ras = 0x00020030,
+	.dram_reset = 0x00020030,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2 = 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 40 ohm */
+	.dram_sdodt0 = 0x00003030,
+	.dram_sdodt1 = 0x00003030,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_sdqs2 = 0x00000030,
+	.dram_sdqs3 = 0x00000030,
+	.dram_sdqs4 = 0x00000030,
+	.dram_sdqs5 = 0x00000030,
+	.dram_sdqs6 = 0x00000030,
+	.dram_sdqs7 = 0x00000030,
+
+	/* DQM[0:7]: Differential input, 40 ohm */
+	.dram_dqm0 = 0x00020030,
+	.dram_dqm1 = 0x00020030,
+	.dram_dqm2 = 0x00020030,
+	.dram_dqm3 = 0x00020030,
+	.dram_dqm4 = 0x00020030,
+	.dram_dqm5 = 0x00020030,
+	.dram_dqm6 = 0x00020030,
+	.dram_dqm7 = 0x00020030,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+	/* DDR3 */
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	/* disable DDR pullups */
+	.grp_ddrpke = 0x00000000,
+	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
+	.grp_addds = 0x00000030,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+	.grp_ctlds = 0x00000030,
+	/* DATA[00:63]: Differential input, 40 ohm */
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_b2ds = 0x00000030,
+	.grp_b3ds = 0x00000030,
+	.grp_b4ds = 0x00000030,
+	.grp_b5ds = 0x00000030,
+	.grp_b6ds = 0x00000030,
+	.grp_b7ds = 0x00000030,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+	.dram_sdclk_0 = 0x00020030,
+	.dram_sdclk_1 = 0x00020030,
+	.dram_cas = 0x00020030,
+	.dram_ras = 0x00020030,
+	.dram_reset = 0x00020030,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2 = 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 40 ohm */
+	.dram_sdodt0 = 0x00003030,
+	.dram_sdodt1 = 0x00003030,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_sdqs2 = 0x00000030,
+	.dram_sdqs3 = 0x00000030,
+	.dram_sdqs4 = 0x00000030,
+	.dram_sdqs5 = 0x00000030,
+	.dram_sdqs6 = 0x00000030,
+	.dram_sdqs7 = 0x00000030,
+
+	/* DQM[0:7]: Differential input, 40 ohm */
+	.dram_dqm0 = 0x00020030,
+	.dram_dqm1 = 0x00020030,
+	.dram_dqm2 = 0x00020030,
+	.dram_dqm3 = 0x00020030,
+	.dram_dqm4 = 0x00020030,
+	.dram_dqm5 = 0x00020030,
+	.dram_dqm6 = 0x00020030,
+	.dram_dqm7 = 0x00020030,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	/* DDR3 */
+	.grp_ddr_type = 0x000c0000,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.grp_ddrmode_ctl = 0x00020000,
+	/* disable DDR pullups */
+	.grp_ddrpke = 0x00000000,
+	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
+	.grp_addds = 0x00000030,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+	.grp_ctlds = 0x00000030,
+	/* DATA[00:63]: Differential input, 40 ohm */
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_b2ds = 0x00000030,
+	.grp_b3ds = 0x00000030,
+	.grp_b4ds = 0x00000030,
+	.grp_b5ds = 0x00000030,
+	.grp_b6ds = 0x00000030,
+	.grp_b7ds = 0x00000030,
+};
+
+/* MT41K64M16JT-125 (1Gb density) */
+static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
+	.mem_speed = 1600,
+	.density = 1,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 13,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+/* MT41K128M16JT-125 (2Gb density) */
+static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+/* MT41K256M16HA-125 (4Gb density) */
+static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+/* MT41K512M16HA-125 (8Gb density) */
+static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
+	.mem_speed = 1600,
+	.density = 8,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 16,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+/*
+ * calibration - these are the various CPU/DDR3 combinations we support
+ */
+static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x004C004E,
+	.p0_mpwldectrl1 = 0x00440044,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x42440247,
+	.p0_mpdgctrl1 = 0x02310232,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x45424746,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x33382C31,
+};
+
+/* TODO: update with calibrated values */
+static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x00190017,
+	.p0_mpwldectrl1 = 0x00140026,
+	.p1_mpwldectrl0 = 0x0021001C,
+	.p1_mpwldectrl1 = 0x0011001D,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x43380347,
+	.p0_mpdgctrl1 = 0x433C034D,
+	.p1_mpdgctrl0 = 0x032C0324,
+	.p1_mpdgctrl1 = 0x03310232,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x3C313539,
+	.p1_mprddlctl = 0x37343141,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x36393C39,
+	.p1_mpwrdlctl = 0x42344438,
+};
+
+/* TODO: update with calibrated values */
+static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x003C003C,
+	.p0_mpwldectrl1 = 0x001F002A,
+	.p1_mpwldectrl0 = 0x00330038,
+	.p1_mpwldectrl1 = 0x0022003F,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x42410244,
+	.p0_mpdgctrl1 = 0x4234023A,
+	.p1_mpdgctrl0 = 0x022D022D,
+	.p1_mpdgctrl1 = 0x021C0228,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x484A4C4B,
+	.p1_mprddlctl = 0x4B4D4E4B,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x33342B32,
+	.p1_mpwrdlctl = 0x3933332B,
+};
+
+static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x001B0016,
+	.p0_mpwldectrl1 = 0x000C000E,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x4324033A,
+	.p0_mpdgctrl1 = 0x00000000,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x40403438,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x40403D36,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x00420043,
+	.p0_mpwldectrl1 = 0x0016001A,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x4238023B,
+	.p0_mpdgctrl1 = 0x00000000,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x40404849,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x40402E2F,
+};
+
+static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x00190017,
+	.p0_mpwldectrl1 = 0x00140026,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x43380347,
+	.p0_mpdgctrl1 = 0x433C034D,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x3C313539,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x36393C39,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x003C003C,
+	.p0_mpwldectrl1 = 0x001F002A,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x42410244,
+	.p0_mpdgctrl1 = 0x4234023A,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x484A4C4B,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x33342B32,
+};
+
+static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x00190017,
+	.p0_mpwldectrl1 = 0x00140026,
+	.p1_mpwldectrl0 = 0x0021001C,
+	.p1_mpwldectrl1 = 0x0011001D,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x43380347,
+	.p0_mpdgctrl1 = 0x433C034D,
+	.p1_mpdgctrl0 = 0x032C0324,
+	.p1_mpdgctrl1 = 0x03310232,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x3C313539,
+	.p1_mprddlctl = 0x37343141,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x36393C39,
+	.p1_mpwrdlctl = 0x42344438,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x003C003C,
+	.p0_mpwldectrl1 = 0x001F002A,
+	.p1_mpwldectrl0 = 0x00330038,
+	.p1_mpwldectrl1 = 0x0022003F,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x42410244,
+	.p0_mpdgctrl1 = 0x4234023A,
+	.p1_mpdgctrl0 = 0x022D022D,
+	.p1_mpdgctrl1 = 0x021C0228,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x484A4C4B,
+	.p1_mprddlctl = 0x4B4D4E4B,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x33342B32,
+	.p1_mpwrdlctl = 0x3933332B,
+};
+
+static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x001E001A,
+	.p0_mpwldectrl1 = 0x0026001F,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x43370349,
+	.p0_mpdgctrl1 = 0x032D0327,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x3D303639,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x32363934,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0X00480047,
+	.p0_mpwldectrl1 = 0X003D003F,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0X423E0241,
+	.p0_mpdgctrl1 = 0X022B022C,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0X49454A4A,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0X2E372C32,
+};
+
+static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0X00220021,
+	.p0_mpwldectrl1 = 0X00200030,
+	.p1_mpwldectrl0 = 0X002D0027,
+	.p1_mpwldectrl1 = 0X00150026,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x43330342,
+	.p0_mpdgctrl1 = 0x0339034A,
+	.p1_mpdgctrl0 = 0x032F0325,
+	.p1_mpdgctrl1 = 0x032F022E,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0X3A2E3437,
+	.p1_mprddlctl = 0X35312F3F,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0X33363B37,
+	.p1_mpwrdlctl = 0X40304239,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x0048004A,
+	.p0_mpwldectrl1 = 0x003F004A,
+	.p1_mpwldectrl0 = 0x001E0028,
+	.p1_mpwldectrl1 = 0x002C0043,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x02250219,
+	.p0_mpdgctrl1 = 0x01790202,
+	.p1_mpdgctrl0 = 0x02080208,
+	.p1_mpdgctrl1 = 0x016C0175,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x4A4C4D4C,
+	.p1_mprddlctl = 0x494C4A48,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x403F3437,
+	.p1_mpwrdlctl = 0x383A3930,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x001F003F,
+	.p0_mpwldectrl1 = 0x001F001F,
+	.p1_mpwldectrl0 = 0x001F004E,
+	.p1_mpwldectrl1 = 0x0059001F,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0   = 0x42220225,
+	.p0_mpdgctrl1   = 0x0213021F,
+	.p1_mpdgctrl0   = 0x022C0242,
+	.p1_mpdgctrl1   = 0x022C0244,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl   = 0x474A4C4A,
+	.p1_mprddlctl   = 0x48494C45,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl   = 0x3F3F3F36,
+	.p1_mpwrdlctl   = 0x3F36363F,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_128x64x2_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x001F003F,
+	.p0_mpwldectrl1 = 0x001F001F,
+	.p1_mpwldectrl0 = 0x001F004E,
+	.p1_mpwldectrl1 = 0x0059001F,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0   = 0x42220225,
+	.p0_mpdgctrl1   = 0x0213021F,
+	.p1_mpdgctrl0   = 0x022C0242,
+	.p1_mpdgctrl1   = 0x022C0244,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl   = 0x474A4C4A,
+	.p1_mprddlctl   = 0x48494C45,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl   = 0x3F3F3F36,
+	.p1_mpwrdlctl   = 0x3F36363F,
+};
+
+static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x002A0025,
+	.p0_mpwldectrl1 = 0x003A002A,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x43430356,
+	.p0_mpdgctrl1 = 0x033C0335,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x4B373F42,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x303E3C36,
+};
+
+static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x00230020,
+	.p0_mpwldectrl1 = 0x002F002A,
+	.p1_mpwldectrl0 = 0x001D0027,
+	.p1_mpwldectrl1 = 0x00100023,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x03250339,
+	.p0_mpdgctrl1 = 0x031C0316,
+	.p1_mpdgctrl0 = 0x03210331,
+	.p1_mpdgctrl1 = 0x031C025A,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x40373C40,
+	.p1_mprddlctl = 0x3A373646,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x2E353933,
+	.p1_mpwrdlctl = 0x3C2F3F35,
+};
+
+static void spl_dram_init(int width, int size_mb, int board_model)
+{
+	struct mx6_ddr3_cfg *mem = NULL;
+	struct mx6_mmdc_calibration *calib = NULL;
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize = width/32,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density = 32, /* 32Gb per CS */
+		/* single chip select */
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
+#ifdef RTT_NOM_120OHM
+		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
+#else
+		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
+#endif
+		.walat = 1,	/* Write additional latency */
+		.ralat = 5,	/* Read additional latency */
+		.mif3_mode = 3,	/* Command prediction working mode */
+		.bi_on = 1,	/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
+		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
+	};
+
+	/*
+	 * MMDC Calibration requires the following data:
+	 *   mx6_mmdc_calibration - board-specific calibration (routing delays)
+	 *      these calibration values depend on board routing, SoC, and DDR
+	 *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
+	 *   mx6_ddr_cfg - chip specific timing/layout details
+	 */
+	if (width == 16 && size_mb == 128) {
+		mem = &mt41k64m16jt_125;
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			;
+		else
+			calib = &mx6sdl_64x16_mmdc_calib;
+		debug("1gB density\n");
+	} else if (width == 16 && size_mb == 256) {
+		/* 1x 2Gb density chip - same calib as 2x 2Gb */
+		mem = &mt41k128m16jt_125;
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			calib = &mx6dq_128x32_mmdc_calib;
+		else
+			calib = &mx6sdl_128x32_mmdc_calib;
+		debug("2gB density\n");
+	} else if (width == 16 && size_mb == 512) {
+		mem = &mt41k256m16ha_125;
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			calib = &mx6dq_256x16_mmdc_calib;
+		else
+			calib = &mx6sdl_256x16_mmdc_calib;
+		debug("4gB density\n");
+	} else if (width == 16 && size_mb == 1024) {
+		mem = &mt41k512m16ha_125;
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			calib = &mx6dq_512x32_mmdc_calib;
+		debug("8gB density\n");
+	} else if (width == 32 && size_mb == 256) {
+		/* Same calib as width==16, size==128 */
+		mem = &mt41k64m16jt_125;
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			;
+		else
+			calib = &mx6sdl_64x16_mmdc_calib;
+		debug("1gB density\n");
+	} else if (width == 32 && size_mb == 512) {
+		mem = &mt41k128m16jt_125;
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			calib = &mx6dq_128x32_mmdc_calib;
+		else
+			calib = &mx6sdl_128x32_mmdc_calib;
+		debug("2gB density\n");
+	}  else if (width == 32 && size_mb == 1024) {
+		mem = &mt41k256m16ha_125;
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			calib = &mx6dq_256x32_mmdc_calib;
+		else
+			calib = &mx6sdl_256x32_mmdc_calib;
+		debug("4gB density\n");
+	} else if (width == 32 && size_mb == 2048) {
+		mem = &mt41k512m16ha_125;
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			calib = &mx6dq_512x32_mmdc_calib;
+		debug("8gB density\n");
+	} else if (width == 64 && size_mb == 512) {
+		mem = &mt41k64m16jt_125;
+		debug("1gB density\n");
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			calib = &mx6dq_64x64_mmdc_calib;
+		else
+			calib = &mx6sdl_64x64_mmdc_calib;
+	} else if (width == 64 && size_mb == 1024) {
+		mem = &mt41k128m16jt_125;
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			calib = &mx6dq_128x64_mmdc_calib;
+		else
+			calib = &mx6sdl_128x64_mmdc_calib;
+		debug("2gB density\n");
+	} else if (width == 64 && size_mb == 2048) {
+		switch(board_model) {
+		case GW5905:
+			/* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */
+			mem = &mt41k128m16jt_125;
+			debug("2gB density - 2 chipsel\n");
+			if (!is_cpu_type(MXC_CPU_MX6Q)) {
+				calib = &mx6sdl_128x64x2_mmdc_calib;
+				sysinfo.ncs = 2;
+				sysinfo.cs_density = 10; /* CS0_END=39 */
+				sysinfo.cs1_mirror = 1; /* mirror enabled */
+			}
+			break;
+		default:
+			mem = &mt41k256m16ha_125;
+			if (is_cpu_type(MXC_CPU_MX6Q))
+				calib = &mx6dq_256x64_mmdc_calib;
+			else
+				calib = &mx6sdl_256x64_mmdc_calib;
+			debug("4gB density\n");
+			break;
+		}
+	} else if (width == 64 && size_mb == 4096) {
+		switch(board_model) {
+		case GW5903:
+			/* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
+			mem = &mt41k256m16ha_125;
+			debug("4gB density - 2 chipsel\n");
+			if (!is_cpu_type(MXC_CPU_MX6Q)) {
+				calib = &mx6sdl_256x64x2_mmdc_calib;
+				sysinfo.ncs = 2;
+				sysinfo.cs_density = 18; /* CS0_END=71 */
+				sysinfo.cs1_mirror = 1; /* mirror enabled */
+			}
+			break;
+		default:
+			mem = &mt41k512m16ha_125;
+			if (is_cpu_type(MXC_CPU_MX6Q))
+				calib = &mx6dq_512x64_mmdc_calib;
+			debug("8gB density\n");
+			break;
+		}
+	}
+
+	if (!(mem && calib)) {
+		puts("Error: Invalid Calibration/Board Configuration\n");
+		printf("MEM    : %s\n", mem ? "OKAY" : "NULL");
+		printf("CALIB  : %s\n", calib ? "OKAY" : "NULL");
+		printf("CPUTYPE: %s\n",
+		       is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
+		printf("SIZE_MB: %d\n", size_mb);
+		printf("WIDTH  : %d\n", width);
+		hang();
+	}
+
+	if (is_cpu_type(MXC_CPU_MX6Q))
+		mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
+				 &mx6dq_grp_ioregs);
+	else
+		mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
+				  &mx6sdl_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, calib, mem);
+}
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0xFFFFF300, &ccm->CCGR4);	/* enable NAND/GPMI/BCH clks */
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+	struct ventana_board_info ventana_info;
+	int board_model;
+
+	/* setup clock gating */
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* setup AXI */
+	gpr_init();
+
+	/* iomux and setup of uart/i2c */
+	setup_iomux_uart();
+	setup_ventana_i2c(0);
+	setup_ventana_i2c(1);
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* read/validate EEPROM info to determine board model and SDRAM cfg */
+	board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+
+	/* configure model-specific gpio */
+	setup_iomux_gpio(board_model, &ventana_info);
+
+	/* provide some some default: 32bit 128MB */
+	if (GW_UNKNOWN == board_model)
+		hang();
+
+	/* configure MMDC for SDRAM width/size and per-model calibration */
+	spl_dram_init(8 << ventana_info.sdram_width,
+		      16 << ventana_info.sdram_size,
+		      board_model);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+	switch (spl_boot_list[0]) {
+	case BOOT_DEVICE_NAND:
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+		spl_boot_list[2] = BOOT_DEVICE_UART;
+		break;
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[1] = BOOT_DEVICE_UART;
+		break;
+	}
+}
+
+/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
+/* its our chance to print info about boot device */
+void spl_board_init(void)
+{
+	u32 boot_device;
+	int board_type;
+
+	/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
+	boot_device = spl_boot_device();
+
+	/* read eeprom again now that we have gd */
+	board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+	if (board_type == GW_UNKNOWN)
+		hang();
+
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+		puts("Booting from MMC\n");
+		break;
+	case BOOT_DEVICE_NAND:
+		puts("Booting from NAND\n");
+		break;
+	case BOOT_DEVICE_SATA:
+		puts("Booting from SATA\n");
+		break;
+	default:
+		puts("Unknown boot device\n");
+	}
+
+	/* PMIC init */
+	setup_pmic();
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* return 1 if we wish to boot to uboot vs os (falcon mode) */
+int spl_start_uboot(void)
+{
+	unsigned char ret = 1;
+
+	debug("%s\n", __func__);
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	env_init();
+	env_load();
+	debug("boot_os=%s\n", env_get("boot_os"));
+	if (env_get_yesno("boot_os") == 1)
+		ret = 0;
+#else
+	/* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
+	i2c_set_bus_num(0);
+	gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
+#endif
+	if (!ret)
+		gsc_boot_wd_disable();
+
+	debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
+	return ret;
+}
+#endif
diff --git a/roms/u-boot/board/gateworks/gw_ventana/ventana_eeprom.h b/roms/u-boot/board/gateworks/gw_ventana/ventana_eeprom.h
new file mode 100644
index 000000000..4fa085b32
--- /dev/null
+++ b/roms/u-boot/board/gateworks/gw_ventana/ventana_eeprom.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ */
+
+#ifndef _VENTANA_EEPROM_
+#define _VENTANA_EEPROM_
+
+struct ventana_board_info {
+	u8 mac0[6];          /* 0x00: MAC1 */
+	u8 mac1[6];          /* 0x06: MAC2 */
+	u8 res0[12];         /* 0x0C: reserved */
+	u32 serial;          /* 0x18: Serial Number (read only) */
+	u8 res1[4];          /* 0x1C: reserved */
+	u8 mfgdate[4];       /* 0x20: MFG date (read only) */
+	u8 res2[7];          /* 0x24 */
+	/* sdram config */
+	u8 sdram_size;       /* 0x2B: (16 << n) MB */
+	u8 sdram_speed;      /* 0x2C: (33.333 * n) MHz */
+	u8 sdram_width;      /* 0x2D: (8 << n) bit */
+	/* cpu config */
+	u8 cpu_speed;        /* 0x2E: (33.333 * n) MHz */
+	u8 cpu_type;         /* 0x2F: 7=imx6q, 8=imx6dl */
+	u8 model[16];        /* 0x30: model string */
+	/* FLASH config */
+	u8 nand_flash_size;  /* 0x40: (8 << (n-1)) MB */
+	u8 spi_flash_size;   /* 0x41: (4 << (n-1)) MB */
+
+	/* Config1: SoC Peripherals */
+	u8 config[8];        /* 0x42: loading options */
+
+	u8 res3[4];          /* 0x4A */
+
+	u8 chksum[2];        /* 0x4E */
+};
+
+/* config bits */
+enum {
+	EECONFIG_ETH0,
+	EECONFIG_ETH1,
+	EECONFIG_HDMI_OUT,
+	EECONFIG_SATA,
+	EECONFIG_PCIE,
+	EECONFIG_SSI0,
+	EECONFIG_SSI1,
+	EECONFIG_LCD,
+	EECONFIG_LVDS0,
+	EECONFIG_LVDS1,
+	EECONFIG_USB0,
+	EECONFIG_USB1,
+	EECONFIG_SD0,
+	EECONFIG_SD1,
+	EECONFIG_SD2,
+	EECONFIG_SD3,
+	EECONFIG_UART0,
+	EECONFIG_UART1,
+	EECONFIG_UART2,
+	EECONFIG_UART3,
+	EECONFIG_UART4,
+	EECONFIG_IPU0,
+	EECONFIG_IPU1,
+	EECONFIG_FLEXCAN,
+	EECONFIG_MIPI_DSI,
+	EECONFIG_MIPI_CSI,
+	EECONFIG_TZASC0,
+	EECONFIG_TZASC1,
+	EECONFIG_I2C0,
+	EECONFIG_I2C1,
+	EECONFIG_I2C2,
+	EECONFIG_VPU,
+	EECONFIG_CSI0,
+	EECONFIG_CSI1,
+	EECONFIG_CAAM,
+	EECONFIG_MEZZ,
+	EECONFIG_RES1,
+	EECONFIG_RES2,
+	EECONFIG_RES3,
+	EECONFIG_RES4,
+	EECONFIG_ESPCI0,
+	EECONFIG_ESPCI1,
+	EECONFIG_ESPCI2,
+	EECONFIG_ESPCI3,
+	EECONFIG_ESPCI4,
+	EECONFIG_ESPCI5,
+	EECONFIG_RES5,
+	EECONFIG_RES6,
+	EECONFIG_GPS,
+	EECONFIG_SPIFL0,
+	EECONFIG_SPIFL1,
+	EECONFIG_GSPBATT,
+	EECONFIG_HDMI_IN,
+	EECONFIG_VID_OUT,
+	EECONFIG_VID_IN,
+	EECONFIG_NAND,
+	EECONFIG_RES8,
+	EECONFIG_RES9,
+	EECONFIG_RES10,
+	EECONFIG_RES11,
+	EECONFIG_RES12,
+	EECONFIG_RES13,
+	EECONFIG_RES14,
+	EECONFIG_RES15,
+};
+
+enum {
+	GW54proto, /* original GW5400-A prototype */
+	GW51xx,
+	GW52xx,
+	GW53xx,
+	GW54xx,
+	GW551x,
+	GW552x,
+	GW553x,
+	GW560x,
+	GW5901,
+	GW5902,
+	GW5903,
+	GW5904,
+	GW5905,
+	GW5906,
+	GW5907,
+	GW5908,
+	GW5909,
+	GW_UNKNOWN,
+	GW_BADCRC,
+};
+
+/* config items */
+struct ventana_eeprom_config {
+	const char *name;	/* name of item */
+	const char *dtalias;	/* name of dt node to remove if not set */
+	int bit;		/* bit within config */
+};
+
+extern struct ventana_eeprom_config econfig[];
+extern struct ventana_board_info ventana_info;
+
+int read_eeprom(int bus, struct ventana_board_info *);
+
+#endif
diff --git a/roms/u-boot/board/gateworks/venice/Kconfig b/roms/u-boot/board/gateworks/venice/Kconfig
new file mode 100644
index 000000000..64cb97c1e
--- /dev/null
+++ b/roms/u-boot/board/gateworks/venice/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MM_VENICE
+
+config SYS_BOARD
+	default "venice"
+
+config SYS_VENDOR
+	default "gateworks"
+
+config SYS_CONFIG_NAME
+	default "imx8mm_venice"
+
+endif
diff --git a/roms/u-boot/board/gateworks/venice/MAINTAINERS b/roms/u-boot/board/gateworks/venice/MAINTAINERS
new file mode 100644
index 000000000..07b9e2a60
--- /dev/null
+++ b/roms/u-boot/board/gateworks/venice/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX8MM Venice
+M:	Tim Harvey <tharvey@gateworks.com>
+S:	Maintained
+F:	arch/arm/dts/imx8mm-venice*
+F:	board/gateworks/venice/
+F:	include/configs/venice.h
+F:	configs/imx8mm_venice_defconfig
diff --git a/roms/u-boot/board/gateworks/venice/Makefile b/roms/u-boot/board/gateworks/venice/Makefile
new file mode 100644
index 000000000..08f5c62db
--- /dev/null
+++ b/roms/u-boot/board/gateworks/venice/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2021 Gateworks Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mm_venice.o gsc.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/roms/u-boot/board/gateworks/venice/README b/roms/u-boot/board/gateworks/venice/README
new file mode 100644
index 000000000..6a0ab1ef1
--- /dev/null
+++ b/roms/u-boot/board/gateworks/venice/README
@@ -0,0 +1,34 @@
+U-Boot for the Gateworks i.MX8M Mini Venice Development Kit boards
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Flash to eMMC
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ git checkout imx_5.4.47_2.2.0
+$ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- bl31
+$ cp build/imx8mm/release/bl31.bin .
+
+Get the DDR Firmware
+====================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+$ chmod +x firmware-imx-8.9.bin
+$ ./firmware-imx-8.9.bin
+$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin .
+
+Build U-Boot
+============
+$ make imx8mm_venice_defconfig
+$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x920000
+
+Update eMMC
+===========
+=> tftpboot $loadaddr flash.bin
+=> setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200
+=> mmc dev 2 && mmc write $loadaddr 0x42 $blkcnt
diff --git a/roms/u-boot/board/gateworks/venice/gsc.c b/roms/u-boot/board/gateworks/venice/gsc.c
new file mode 100644
index 000000000..d2490e606
--- /dev/null
+++ b/roms/u-boot/board/gateworks/venice/gsc.c
@@ -0,0 +1,676 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hang.h>
+#include <hexdump.h>
+#include <i2c.h>
+#include <linux/delay.h>
+#include <dm/uclass.h>
+
+#include "gsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct venice_board_info som_info;
+struct venice_board_info base_info;
+char venice_model[32];
+
+/* return a mac address from EEPROM info */
+int gsc_getmac(int index, uint8_t *address)
+{
+	int i, j;
+	u32 maclow, machigh;
+	u64 mac;
+
+	j = 0;
+	if (som_info.macno) {
+		maclow = som_info.mac[5];
+		maclow |= som_info.mac[4] << 8;
+		maclow |= som_info.mac[3] << 16;
+		maclow |= som_info.mac[2] << 24;
+		machigh = som_info.mac[1];
+		machigh |= som_info.mac[0] << 8;
+		mac = machigh;
+		mac <<= 32;
+		mac |= maclow;
+		for (i = 0; i < som_info.macno; i++, j++) {
+			if (index == j)
+				goto out;
+		}
+	}
+
+	maclow = base_info.mac[5];
+	maclow |= base_info.mac[4] << 8;
+	maclow |= base_info.mac[3] << 16;
+	maclow |= base_info.mac[2] << 24;
+	machigh = base_info.mac[1];
+	machigh |= base_info.mac[0] << 8;
+	mac = machigh;
+	mac <<= 32;
+	mac |= maclow;
+	for (i = 0; i < base_info.macno; i++, j++) {
+		if (index == j)
+			goto out;
+	}
+
+	return -EINVAL;
+
+out:
+	mac += i;
+	address[0] = (mac >> 40) & 0xff;
+	address[1] = (mac >> 32) & 0xff;
+	address[2] = (mac >> 24) & 0xff;
+	address[3] = (mac >> 16) & 0xff;
+	address[4] = (mac >> 8) & 0xff;
+	address[5] = (mac >> 0) & 0xff;
+
+	return 0;
+}
+
+/* System Controller registers */
+enum {
+	GSC_SC_CTRL0		= 0,
+	GSC_SC_CTRL1		= 1,
+	GSC_SC_STATUS		= 10,
+	GSC_SC_FWCRC		= 12,
+	GSC_SC_FWVER		= 14,
+	GSC_SC_WP		= 15,
+	GSC_SC_RST_CAUSE	= 16,
+	GSC_SC_THERM_PROTECT	= 19,
+};
+
+/* System Controller Control1 bits */
+enum {
+	GSC_SC_CTRL1_WDTIME	= 4, /* 1 = 60s timeout, 0 = 30s timeout */
+	GSC_SC_CTRL1_WDEN	= 5, /* 1 = enable, 0 = disable */
+	GSC_SC_CTRL1_BOOT_CHK   = 6, /* 1 = enable alt boot check */
+	GSC_SC_CTRL1_WDDIS	= 7, /* 1 = disable boot watchdog */
+};
+
+/* System Controller Interrupt bits */
+enum {
+	GSC_SC_IRQ_PB		= 0, /* Pushbutton switch */
+	GSC_SC_IRQ_SECURE	= 1, /* Secure Key erase operation complete */
+	GSC_SC_IRQ_EEPROM_WP	= 2, /* EEPROM write violation */
+	GSC_SC_IRQ_GPIO		= 4, /* GPIO change */
+	GSC_SC_IRQ_TAMPER	= 5, /* Tamper detect */
+	GSC_SC_IRQ_WATCHDOG	= 6, /* Watchdog trip */
+	GSC_SC_IRQ_PBLONG	= 7, /* Pushbutton long hold */
+};
+
+/* System Controller WP bits */
+enum {
+	GSC_SC_WP_ALL		= 0, /* Write Protect All EEPROM regions */
+	GSC_SC_WP_BOARDINFO	= 1, /* Write Protect Board Info region */
+};
+
+/* System Controller Reset Cause */
+enum {
+	GSC_SC_RST_CAUSE_VIN		= 0,
+	GSC_SC_RST_CAUSE_PB		= 1,
+	GSC_SC_RST_CAUSE_WDT		= 2,
+	GSC_SC_RST_CAUSE_CPU		= 3,
+	GSC_SC_RST_CAUSE_TEMP_LOCAL	= 4,
+	GSC_SC_RST_CAUSE_TEMP_REMOTE	= 5,
+	GSC_SC_RST_CAUSE_SLEEP		= 6,
+	GSC_SC_RST_CAUSE_BOOT_WDT	= 7,
+	GSC_SC_RST_CAUSE_BOOT_WDT_MAN	= 8,
+	GSC_SC_RST_CAUSE_SOFT_PWR	= 9,
+	GSC_SC_RST_CAUSE_MAX		= 10,
+};
+
+static struct udevice *gsc_get_dev(int busno, int slave)
+{
+	static const char * const i2c[] = { "i2c@30a20000", "i2c@30a30000" };
+	struct udevice *dev, *bus;
+	int ret;
+
+	ret = uclass_get_device_by_name(UCLASS_I2C, i2c[busno - 1], &bus);
+	if (ret) {
+		printf("GSC     : failed I2C%d probe: %d\n", busno, ret);
+		return NULL;
+	}
+	ret = dm_i2c_probe(bus, slave, 0, &dev);
+	if (ret)
+		return NULL;
+
+	return dev;
+}
+
+static int gsc_read_eeprom(int bus, int slave, int alen, struct venice_board_info *info)
+{
+	int i;
+	int chksum;
+	unsigned char *buf = (unsigned char *)info;
+	struct udevice *dev;
+	int ret;
+
+	/* probe device */
+	dev = gsc_get_dev(bus, slave);
+	if (!dev) {
+		if (slave == GSC_EEPROM_ADDR)
+			puts("ERROR: Failed to probe EEPROM\n");
+		return -ENODEV;
+	}
+
+	/* read eeprom config section */
+	memset(info, 0, sizeof(*info));
+	ret = i2c_set_chip_offset_len(dev, alen);
+	if (ret) {
+		puts("EEPROM: Failed to set alen\n");
+		return ret;
+	}
+	ret = dm_i2c_read(dev, 0x00, buf, sizeof(*info));
+	if (ret) {
+		if (slave == GSC_EEPROM_ADDR)
+			printf("EEPROM: Failed to read EEPROM\n");
+		return ret;
+	}
+
+	/* validate checksum */
+	for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++)
+		chksum += buf[i];
+	if ((info->chksum[0] != chksum >> 8) ||
+	    (info->chksum[1] != (chksum & 0xff))) {
+		printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", bus, slave);
+		print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info));
+		memset(info, 0, sizeof(*info));
+		return -EINVAL;
+	}
+
+	/* sanity check valid model */
+	if (info->model[0] != 'G' || info->model[1] != 'W') {
+		printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", bus, slave);
+		print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info));
+		memset(info, 0, sizeof(*info));
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const char *gsc_get_rst_cause(struct udevice *dev)
+{
+	static char str[64];
+	static const char * const names[] = {
+		"VIN",
+		"PB",
+		"WDT",
+		"CPU",
+		"TEMP_L",
+		"TEMP_R",
+		"SLEEP",
+		"BOOT_WDT1",
+		"BOOT_WDT2",
+		"SOFT_PWR",
+	};
+	unsigned char reg;
+
+	/* reset cause */
+	str[0] = 0;
+	if (!dm_i2c_read(dev, GSC_SC_RST_CAUSE, &reg, 1)) {
+		if (reg < ARRAY_SIZE(names))
+			sprintf(str, "%s", names[reg]);
+		else
+			sprintf(str, "0x%02x", reg);
+	}
+
+	/* thermal protection */
+	if (!dm_i2c_read(dev, GSC_SC_THERM_PROTECT, &reg, 1)) {
+		reg |= 1;
+		dm_i2c_write(dev, GSC_SC_THERM_PROTECT, &reg, 1);
+		strcat(str, " Thermal Protection Enabled");
+	}
+
+	return str;
+}
+
+/* display hardware monitor ADC channels */
+int gsc_hwmon(void)
+{
+	const void *fdt = gd->fdt_blob;
+	struct udevice *dev;
+	int node, reg, mode, len, val, offset;
+	const char *label;
+	u8 buf[2];
+	int ret;
+
+	node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
+	if (node <= 0)
+		return node;
+
+	/* probe device */
+	dev = gsc_get_dev(1, GSC_HWMON_ADDR);
+	if (!dev) {
+		puts("ERROR: Failed to probe GSC HWMON\n");
+		return -ENODEV;
+	}
+
+	/* iterate over hwmon nodes */
+	node = fdt_first_subnode(fdt, node);
+	while (node > 0) {
+		reg = fdtdec_get_int(fdt, node, "reg", -1);
+		mode = fdtdec_get_int(fdt, node, "gw,mode", -1);
+		offset = fdtdec_get_int(fdt, node, "gw,voltage-offset-microvolt", 0);
+		label = fdt_stringlist_get(fdt, node, "label", 0, NULL);
+
+		if ((reg == -1) || (mode == -1) || !label)
+			printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL));
+
+		memset(buf, 0, sizeof(buf));
+		ret = dm_i2c_read(dev, reg, buf, sizeof(buf));
+		if (ret) {
+			printf("i2c error: %d\n", ret);
+			continue;
+		}
+		val = buf[0] | buf[1] << 8;
+		if (val >= 0) {
+			const u32 *div;
+			int r[2];
+
+			switch (mode) {
+			case 0: /* temperature (C*10) */
+				if (val > 0x8000)
+					val -= 0xffff;
+				printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10));
+				break;
+			case 1: /* prescaled voltage */
+				if (val != 0xffff)
+					printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
+				break;
+			case 2: /* scaled based on ref volt and resolution */
+				val *= 2500;
+				val /= 1 << 12;
+
+				/* apply pre-scaler voltage divider */
+				div  = fdt_getprop(fdt, node, "gw,voltage-divider-ohms", &len);
+				if (div && (len == sizeof(uint32_t) * 2)) {
+					r[0] = fdt32_to_cpu(div[0]);
+					r[1] = fdt32_to_cpu(div[1]);
+					if (r[0] && r[1]) {
+						val *= (r[0] + r[1]);
+						val /= r[1];
+					}
+				}
+
+				/* adjust by offset */
+				val += offset;
+
+				printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
+				break;
+			}
+		}
+		node = fdt_next_subnode(fdt, node);
+	}
+
+	return 0;
+}
+
+/* determine BOM revision from model */
+int get_bom_rev(const char *str)
+{
+	int  rev_bom = 0;
+	int i;
+
+	for (i = strlen(str) - 1; i > 0; i--) {
+		if (str[i] == '-')
+			break;
+		if (str[i] >= '1' && str[i] <= '9') {
+			rev_bom = str[i] - '0';
+			break;
+		}
+	}
+	return rev_bom;
+}
+
+/* determine PCB revision from model */
+char get_pcb_rev(const char *str)
+{
+	char rev_pcb = 'A';
+	int i;
+
+	for (i = strlen(str) - 1; i > 0; i--) {
+		if (str[i] == '-')
+			break;
+		if (str[i] >= 'A') {
+			rev_pcb = str[i];
+			break;
+		}
+	}
+	return rev_pcb;
+}
+
+/*
+ * get dt name based on model and detail level:
+ *
+ * For boards that are a combination of a SoM plus a Baseboard:
+ *   Venice SoM part numbers are GW70xx where xx is:
+ *    7000-7019: same PCB with som dt of '0x'
+ *    7020-7039: same PCB with som dt of '2x'
+ *    7040-7059: same PCB with som dt of '4x'
+ *    7060-7079: same PCB with som dt of '6x'
+ *    7080-7099: same PCB with som dt of '8x'
+ *   Venice Baseboard part numbers are GW7xxx where xxx is:
+ *    7100-7199: same PCB with base dt of '71xx'
+ *    7200-7299: same PCB with base dt of '72xx'
+ *    7300-7399: same PCB with base dt of '73xx'
+ *    7400-7499: same PCB with base dt of '74xx'
+ *    7500-7599: same PCB with base dt of '75xx'
+ *    7600-7699: same PCB with base dt of '76xx'
+ *    7700-7799: same PCB with base dt of '77xx'
+ *    7800-7899: same PCB with base dt of '78xx'
+ *   DT name is comprised of:
+ *    gw<base dt>-<som dt>-[base-pcb-rev][base-bom-rev][som-pcb-rev][som-bom-rev]
+ *
+ * For board models from 7900-7999 each PCB is unique with its own dt:
+ *   DT name is comprised:
+ *    gw<model>-[pcb-rev][bom-rev]
+ *
+ */
+#define snprintfcat(dest, sz, fmt, ...) \
+	snprintf((dest) + strlen(dest), (sz) - strlen(dest), fmt, ##__VA_ARGS__)
+const char *gsc_get_dtb_name(int level, char *buf, int sz)
+{
+	const char *pre = "imx8mm-venice-gw";
+	int model, rev_pcb, rev_bom;
+
+	model = ((som_info.model[2] - '0') * 1000)
+		+ ((som_info.model[3] - '0') * 100)
+		+ ((som_info.model[4] - '0') * 10)
+		+ (som_info.model[5] - '0');
+	rev_pcb = tolower(get_pcb_rev(som_info.model));
+	rev_bom = get_bom_rev(som_info.model);
+
+	/* som + baseboard*/
+	if (base_info.model[0]) {
+		/* baseboard id: 7100-7199->71; 7200-7299->72; etc */
+		int base = ((base_info.model[2] - '0') * 10) + (base_info.model[3] - '0');
+		/* som id: 7000-7019->1; 7020-7039->2; etc */
+		int som = ((model % 100) / 20) * 2;
+		int rev_base_pcb = tolower(get_pcb_rev(base_info.model));
+		int rev_base_bom = get_bom_rev(base_info.model);
+
+		snprintf(buf, sz, "%s%2dxx-%dx", pre, base, som);
+		switch (level) {
+		case 0: /* full model (ie gw73xx-0x-a1a1) */
+			if (rev_base_bom)
+				snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom);
+			else
+				snprintfcat(buf, sz, "-%c", rev_base_pcb);
+			if (rev_bom)
+				snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom);
+			else
+				snprintfcat(buf, sz, "%c", rev_pcb);
+			break;
+		case 1: /* don't care about SoM revision */
+			if (rev_base_bom)
+				snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom);
+			else
+				snprintfcat(buf, sz, "-%c", rev_base_pcb);
+			snprintfcat(buf, sz, "xx");
+			break;
+		case 2: /* don't care about baseboard revision */
+			snprintfcat(buf, sz, "-xx");
+			if (rev_bom)
+				snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom);
+			else
+				snprintfcat(buf, sz, "%c", rev_pcb);
+			break;
+		case 3: /* don't care about SoM/baseboard revision */
+			break;
+		default:
+			return NULL;
+		}
+	} else {
+		snprintf(buf, sz, "%s%04d", pre, model);
+		switch (level) {
+		case 0: /* full model wth PCB and BOM revision first (ie gw7901-a1) */
+			if (rev_bom)
+				snprintfcat(buf, sz, "-%c%d", rev_pcb, rev_bom);
+			else
+				snprintfcat(buf, sz, "-%c", rev_pcb);
+			break;
+		case 1: /* don't care about BOM revision */
+			snprintfcat(buf, sz, "-%c", rev_pcb);
+			break;
+		case 2: /* don't care about PCB or BOM revision */
+			break;
+		default:
+			return NULL;
+		}
+	}
+
+	return buf;
+}
+
+static int gsc_read(void)
+{
+	int ret;
+
+	ret = gsc_read_eeprom(1, GSC_EEPROM_ADDR, 1, &som_info);
+	if (ret) {
+		memset(&som_info, 0, sizeof(som_info));
+		return ret;
+	}
+
+	/* read optional baseboard EEPROM */
+	return gsc_read_eeprom(2, 0x52, 2, &base_info);
+}
+
+static int gsc_info(int verbose)
+{
+	struct udevice *dev;
+	unsigned char buf[16];
+	char rev_pcb;
+	int rev_bom;
+
+	if (!base_info.model[0]) {
+		strcpy(venice_model, som_info.model);
+		printf("Model   : %s\n", som_info.model);
+		printf("Serial  : %d\n", som_info.serial);
+		printf("MFGDate : %02x-%02x-%02x%02x\n",
+		       som_info.mfgdate[0], som_info.mfgdate[1],
+		       som_info.mfgdate[2], som_info.mfgdate[3]);
+	} else {
+		sprintf(venice_model, "GW%c%c%c%c-%c%c-",
+			som_info.model[2], /* family */
+			base_info.model[3], /* baseboard */
+			base_info.model[4], base_info.model[5], /* subload of baseboard */
+			som_info.model[4], som_info.model[5]); /* last 2digits of SOM */
+
+		/* baseboard revision */
+		rev_pcb = get_pcb_rev(base_info.model);
+		rev_bom = get_bom_rev(base_info.model);
+		if (rev_bom)
+			sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom);
+		else
+			sprintf(venice_model + strlen(venice_model), "%c", rev_pcb);
+		/* som revision */
+		rev_pcb = get_pcb_rev(som_info.model);
+		rev_bom = get_bom_rev(som_info.model);
+		if (rev_bom)
+			sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom);
+		else
+			sprintf(venice_model + strlen(venice_model), "%c", rev_pcb);
+
+		if (verbose > 1) {
+			printf("SOM     : %s %d %02x-%02x-%02x%02x\n",
+			       som_info.model, som_info.serial,
+			       som_info.mfgdate[0], som_info.mfgdate[1],
+			       som_info.mfgdate[2], som_info.mfgdate[3]);
+			printf("BASE    : %s %d %02x-%02x-%02x%02x\n",
+			       base_info.model, base_info.serial,
+			       base_info.mfgdate[0], base_info.mfgdate[1],
+			       base_info.mfgdate[2], base_info.mfgdate[3]);
+		}
+		printf("Model   : %s\n", venice_model);
+		printf("Serial  : %d\n", som_info.serial);
+		printf("MFGDate : %02x-%02x-%02x%02x\n",
+		       som_info.mfgdate[0], som_info.mfgdate[1],
+		       som_info.mfgdate[2], som_info.mfgdate[3]);
+	}
+
+	/* Display RTC */
+	puts("RTC     : ");
+	dev = gsc_get_dev(1, GSC_RTC_ADDR);
+	if (!dev) {
+		puts("Failed to probe GSC RTC\n");
+	} else {
+		dm_i2c_read(dev, 0, buf, 6);
+		printf("%d\n", buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24);
+	}
+
+	return 0;
+}
+
+int gsc_init(int quiet)
+{
+	unsigned char buf[16];
+	struct udevice *dev;
+	int ret;
+
+	/*
+	 * On a board with a missing/depleted backup battery for GSC, the
+	 * board may be ready to probe the GSC before its firmware is
+	 * running.  We will wait here indefinately for the GSC/EEPROM.
+	 */
+	while (1) {
+		/* probe device */
+		dev = gsc_get_dev(1, GSC_SC_ADDR);
+		if (dev)
+			break;
+		mdelay(1);
+	}
+
+	ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
+	if (ret) {
+		puts("ERROR: Failed reading GSC\n");
+		return ret;
+	}
+	gsc_read();
+
+	/* banner */
+	if (!quiet) {
+		printf("GSC     : v%d 0x%04x", buf[GSC_SC_FWVER],
+		       buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC + 1] << 8);
+		printf(" RST:%s", gsc_get_rst_cause(dev));
+		printf("\n");
+		gsc_info(1);
+	}
+
+	if (ret)
+		hang();
+
+	return ((16 << som_info.sdram_size) / 1024);
+}
+
+const char *gsc_get_model(void)
+{
+	return venice_model;
+}
+
+#if !(IS_ENABLED(CONFIG_SPL_BUILD))
+static int gsc_sleep(unsigned long secs)
+{
+	unsigned char reg;
+	struct udevice *dev;
+	int ret;
+
+	/* probe device */
+	dev = gsc_get_dev(1, GSC_SC_ADDR);
+	if (!dev)
+		return -ENODEV;
+
+	printf("GSC Sleeping for %ld seconds\n", secs);
+	reg = (secs >> 24) & 0xff;
+	ret = dm_i2c_write(dev, 9, &reg, 1);
+	if (ret)
+		goto err;
+	reg = (secs >> 16) & 0xff;
+	ret = dm_i2c_write(dev, 8, &reg, 1);
+	if (ret)
+		goto err;
+	reg = (secs >> 8) & 0xff;
+	ret = dm_i2c_write(dev, 7, &reg, 1);
+	if (ret)
+		goto err;
+	reg = secs & 0xff;
+	ret = dm_i2c_write(dev, 6, &reg, 1);
+	if (ret)
+		goto err;
+	ret = dm_i2c_read(dev, GSC_SC_CTRL1, &reg, 1);
+	if (ret)
+		goto err;
+	reg |= (1 << 2);
+	ret = dm_i2c_write(dev, GSC_SC_CTRL1, &reg, 1);
+	if (ret)
+		goto err;
+	reg &= ~(1 << 2);
+	reg |= 0x3;
+	ret = dm_i2c_write(dev, GSC_SC_CTRL1, &reg, 1);
+	if (ret)
+		goto err;
+
+	return 0;
+
+err:
+	printf("i2c error\n");
+	return ret;
+}
+
+static int gsc_boot_wd_disable(void)
+{
+	u8 reg;
+	struct udevice *dev;
+	int ret;
+
+	/* probe device */
+	dev = gsc_get_dev(1, GSC_SC_ADDR);
+	if (!dev)
+		return -ENODEV;
+
+	ret = dm_i2c_read(dev, GSC_SC_CTRL1, &reg, 1);
+	if (ret)
+		goto err;
+	reg |= (1 << GSC_SC_CTRL1_WDDIS);
+	reg &= ~(1 << GSC_SC_CTRL1_BOOT_CHK);
+	ret = dm_i2c_write(dev, GSC_SC_CTRL1, &reg, 1);
+	if (ret)
+		goto err;
+	puts("GSC     : boot watchdog disabled\n");
+
+	return 0;
+
+err:
+	printf("i2c error");
+	return ret;
+}
+
+static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2)
+		return gsc_info(2);
+
+	if (strcasecmp(argv[1], "sleep") == 0) {
+		if (argc < 3)
+			return CMD_RET_USAGE;
+		if (!gsc_sleep(simple_strtoul(argv[2], NULL, 10)))
+			return CMD_RET_SUCCESS;
+	} else if (strcasecmp(argv[1], "hwmon") == 0) {
+		if (!gsc_hwmon())
+			return CMD_RET_SUCCESS;
+	} else if (strcasecmp(argv[1], "wd-disable") == 0) {
+		if (!gsc_boot_wd_disable())
+			return CMD_RET_SUCCESS;
+	}
+
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(gsc, 4, 1, do_gsc, "Gateworks System Controller",
+	   "[sleep <secs>]|[hwmon]|[wd-disable]\n");
+#endif
diff --git a/roms/u-boot/board/gateworks/venice/gsc.h b/roms/u-boot/board/gateworks/venice/gsc.h
new file mode 100644
index 000000000..27b02117b
--- /dev/null
+++ b/roms/u-boot/board/gateworks/venice/gsc.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#ifndef _GSC_H_
+#define _GSC_H_
+
+/* I2C slave addresses */
+#define GSC_SC_ADDR             0x20
+#define GSC_RTC_ADDR            0x68
+#define GSC_HWMON_ADDR          0x29
+#define GSC_EEPROM_ADDR         0x51
+
+struct venice_board_info {
+	u8 mac[6];		/* 0x00: MAC base */
+	char equiv_dts[16];	/* 0x06: equivalent device-tree */
+	u8 res0[2];	/* 0x16: reserved */
+	u32 serial;	/* 0x18: Serial Number */
+	u8 res1[4];	/* 0x1C: reserved */
+	u8 mfgdate[4];	/* 0x20: MFG date */
+	u8 macno;		/* 0x24: number of mac addrs */
+	u8 res2[6];	/* 0x25 */
+	u8 sdram_size;	/* 0x2B: (16 << n) MB */
+	u8 sdram_speed;	/* 0x2C: (33.333 * n) MHz */
+	u8 sdram_width;	/* 0x2D: (8 << n) bit */
+	u8 res3[2];	/* 0x2E */
+	char model[16];		/* 0x30: model string */
+	u8 res4[14];	/* 0x40 */
+	u8 chksum[2];	/* 0x4E */
+};
+
+int gsc_init(int quiet);
+int gsc_hwmon(void);
+const char *gsc_get_model(void);
+const char *gsc_get_dtb_name(int level, char *buf, int len);
+int gsc_getmac(int index, uint8_t *enetaddr);
+
+#endif
diff --git a/roms/u-boot/board/gateworks/venice/imx8mm_venice.c b/roms/u-boot/board/gateworks/venice/imx8mm_venice.c
new file mode 100644
index 000000000..1d51b6ea9
--- /dev/null
+++ b/roms/u-boot/board/gateworks/venice/imx8mm_venice.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include <common.h>
+#include <init.h>
+#include <led.h>
+#include <linux/delay.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+#include "gsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+	int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
+
+	if (ddr_size == 0x4) {
+		*size = 0x100000000;
+	} else if (ddr_size == 0x3) {
+		*size = 0xc0000000;
+	} else if (ddr_size == 0x2) {
+		*size = 0x80000000;
+	} else if (ddr_size == 0x1) {
+		*size = 0x40000000;
+	} else {
+		printf("Unknown DDR type!!!\n");
+		*size = 0x40000000;
+	}
+
+	return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	int i  = 0;
+	const char *dtb;
+	char buf[32];
+
+	do {
+		dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
+		if (!strcmp(dtb, name))
+			return 0;
+	} while (dtb);
+
+	return -1;
+}
+
+#if (IS_ENABLED(CONFIG_FEC_MXC))
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	switch (phydev->phy_id) {
+	case 0x2000a231: /* TI DP83867 GbE PHY */
+		puts("DP83867 ");
+		/* LED configuration */
+		val = 0;
+		val |= 0x5 << 4; /* LED1(Amber;Speed)   : 1000BT link */
+		val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
+		phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
+		break;
+	}
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif // IS_ENABLED(CONFIG_FEC_MXC)
+
+int board_init(void)
+{
+	gsc_init(1);
+
+	if (IS_ENABLED(CONFIG_FEC_MXC))
+		setup_fec();
+
+	gsc_hwmon();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	const char *ethmac;
+	char env[32];
+	int ret, i;
+	u8 enetaddr[6];
+
+	led_default_state();
+
+	/* Set mac addrs */
+	i = 0;
+	do {
+		if (i)
+			sprintf(env, "eth%daddr", i);
+		else
+			sprintf(env, "ethaddr");
+		ethmac = env_get(env);
+		if (!ethmac) {
+			ret = gsc_getmac(i, enetaddr);
+			if (!ret)
+				eth_env_set_enetaddr(env, enetaddr);
+		}
+		i++;
+	} while (!ret);
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
diff --git a/roms/u-boot/board/gateworks/venice/lpddr4_timing.c b/roms/u-boot/board/gateworks/venice/lpddr4_timing.c
new file mode 100644
index 000000000..47e93e123
--- /dev/null
+++ b/roms/u-boot/board/gateworks/venice/lpddr4_timing.c
@@ -0,0 +1,2505 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param lpddr4_ddrc_cfg_1gb[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400020, 0x223 },
+	{ 0x3d400024, 0x3a980 },
+	{ 0x3d400064, 0x5b0087 },
+	{ 0x3d4000d0, 0xc00305ba },
+	{ 0x3d4000d4, 0x940000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000ec, 0x16004d },
+	{ 0x3d400100, 0x191e1920 },
+	{ 0x3d400104, 0x60630 },
+	{ 0x3d40010c, 0xb0b000 },
+	{ 0x3d400110, 0xe04080e },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x401 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0x8d },
+	{ 0x3d400144, 0x96004b },
+	{ 0x3d400180, 0x2ee0017 },
+	{ 0x3d400184, 0x2605b8e },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0xf070707 },
+	{ 0x3d400250, 0x29001701 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x21 },
+	{ 0x3d402024, 0x7d00 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0xc0012 },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020ec, 0x16004d },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x13 },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x21 },
+	{ 0x3d403024, 0x1f40 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30005 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x310000 },
+	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030ec, 0x16004d },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x5 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg_1gb[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x220024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x2ee },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x2200c7, 0x21 },
+	{ 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
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+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x110 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, 0x16 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x110 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, 0x16 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x110 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, 0x16 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x110 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, 0x16 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xf },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a7, 0x0 },
+	{ 0x900a8, 0x790 },
+	{ 0x900a9, 0x11a },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x7b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x0 },
+	{ 0x900b1, 0x7c8 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xc },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x0 },
+	{ 0x90169, 0x8 },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x448 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
+	{ 0x9016e, 0x7c0 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x7c8 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x5d },
+	{ 0x2000c, 0xbb },
+	{ 0x2000d, 0x753 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x2003a, 0x2 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg_1gb[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg_1gb,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg_1gb),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg_1gb,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg_1gb),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp2_cfg_1gb,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg_1gb),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg_1gb,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg_1gb),
+	},
+};
+
+/* lpddr4 timing config params */
+struct dram_timing_info dram_timing_1gb = {
+	.ddrc_cfg = lpddr4_ddrc_cfg_1gb,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_1gb),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg_1gb,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg_1gb),
+	.fsp_msg = lpddr4_dram_fsp_msg_1gb,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg_1gb),
+	.ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
+
+static struct dram_cfg_param lpddr4_ddrc_cfg_4gb[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa3080020 },
+	{ 0x3d400020, 0x223 },
+	{ 0x3d400024, 0x3a980 },
+	{ 0x3d400064, 0x5b00d2 },
+	{ 0x3d4000d0, 0xc00305ba },
+	{ 0x3d4000d4, 0x940000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000ec, 0x16004d },
+	{ 0x3d400100, 0x191e1920 },
+	{ 0x3d400104, 0x60630 },
+	{ 0x3d40010c, 0xb0b000 },
+	{ 0x3d400110, 0xe04080e },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x401 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0xd8 },
+	{ 0x3d400144, 0x96004b },
+	{ 0x3d400180, 0x2ee0017 },
+	{ 0x3d400184, 0x2605b8e },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x17 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d400250, 0x29001701 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x21 },
+	{ 0x3d402024, 0x7d00 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020ec, 0x16004d },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x21 },
+	{ 0x3d403024, 0x1f40 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x310000 },
+	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030ec, 0x16004d },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg_4gb[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x220024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x2ee },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x1200c7, 0x21 },
+	{ 0x2200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200ca, 0x24 },
+	{ 0x2200ca, 0x24 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg_4gb[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg_4gb[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp2_cfg_4gb[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg_4gb[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg_4gb[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg_4gb,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg_4gb),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg_4gb,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg_4gb),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp2_cfg_4gb,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg_4gb),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg_4gb,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg_4gb),
+	},
+};
+
+/* lpddr4 timing config params */
+struct dram_timing_info dram_timing_4gb = {
+	.ddrc_cfg = lpddr4_ddrc_cfg_4gb,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_4gb),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg_4gb,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg_4gb),
+	.fsp_msg = lpddr4_dram_fsp_msg_4gb,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg_4gb),
+	.ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
diff --git a/roms/u-boot/board/gateworks/venice/lpddr4_timing.h b/roms/u-boot/board/gateworks/venice/lpddr4_timing.h
new file mode 100644
index 000000000..94445f86a
--- /dev/null
+++ b/roms/u-boot/board/gateworks/venice/lpddr4_timing.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+extern struct dram_timing_info dram_timing_1gb;
+extern struct dram_timing_info dram_timing_4gb;
+
+#endif /* __LPDDR4_TIMING_H__ */
diff --git a/roms/u-boot/board/gateworks/venice/spl.c b/roms/u-boot/board/gateworks/venice/spl.c
new file mode 100644
index 000000000..ea500d4f8
--- /dev/null
+++ b/roms/u-boot/board/gateworks/venice/spl.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <i2c.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+#include <asm-generic/gpio.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/mp5416.h>
+
+#include "gsc.h"
+#include "lpddr4_timing.h"
+
+#define PCIE_RSTN IMX_GPIO_NR(4, 6)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void spl_dram_init(int size)
+{
+	struct dram_timing_info *dram_timing;
+
+	switch (size) {
+	case 1:
+		dram_timing = &dram_timing_1gb;
+		break;
+	case 4:
+		dram_timing = &dram_timing_4gb;
+		break;
+	default:
+		printf("Unknown DDR configuration: %d GiB\n", size);
+		dram_timing = &dram_timing_1gb;
+		size = 1;
+	}
+
+	printf("DRAM    : LPDDR4 %d GiB\n", size);
+	ddr_init(dram_timing);
+	writel(size, M4_BOOTROM_BASE_ADDR);
+}
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+/*
+ * Model specific PMIC adjustments necessary prior to DRAM init
+ *
+ * Note that we can not use pmic dm drivers here as we have a generic
+ * venice dt that does not have board-specific pmic's defined.
+ *
+ * Instead we must use dm_i2c.
+ */
+static int power_init_board(void)
+{
+	const char *model = gsc_get_model();
+	struct udevice *bus;
+	struct udevice *dev;
+	int ret;
+
+	if ((!strncmp(model, "GW71", 4)) ||
+	    (!strncmp(model, "GW72", 4)) ||
+	    (!strncmp(model, "GW73", 4))) {
+		ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@30a20000", &bus);
+		if (ret) {
+			printf("PMIC    : failed I2C1 probe: %d\n", ret);
+			return ret;
+		}
+		ret = dm_i2c_probe(bus, 0x69, 0, &dev);
+		if (ret) {
+			printf("PMIC    : failed probe: %d\n", ret);
+			return ret;
+		}
+		puts("PMIC    : MP5416\n");
+
+		/* set VDD_ARM SW3 to 0.92V for 1.6GHz */
+		dm_i2c_reg_write(dev, MP5416_VSET_SW3,
+				 BIT(7) | MP5416_VSET_SW3_SVAL(920000));
+	}
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+	int dram_sz;
+
+	arch_cpu_init();
+
+	init_uart_clk(1);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0) {
+		printf("Failed to find clock node. Check device tree\n");
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
+	gpio_request(PCIE_RSTN, "perst#");
+	gpio_direction_output(PCIE_RSTN, 0);
+
+	/* GSC */
+	dram_sz = gsc_init(0);
+
+	/* PMIC */
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init(dram_sz);
+
+	board_init_r(NULL, 0);
+}
+
+/* determine prioritized order of boot devices to load U-Boot from */
+void board_boot_order(u32 *spl_boot_list)
+{
+	/*
+	 * If the SPL was loaded via serial loader, we try to get
+	 * U-Boot proper via USB SDP.
+	 */
+	if (spl_boot_device() == BOOT_DEVICE_BOARD)
+		spl_boot_list[0] = BOOT_DEVICE_BOARD;
+
+	/* we have only eMMC in default venice dt */
+	spl_boot_list[0] = BOOT_DEVICE_MMC1;
+}
+
+/* return boot device based on where the SPL was loaded from */
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	/* SDHC2 */
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	/* SDHC3 */
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
diff --git a/roms/u-boot/board/gdsys/a38x/MAINTAINERS b/roms/u-boot/board/gdsys/a38x/MAINTAINERS
new file mode 100644
index 000000000..d31e675dd
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/MAINTAINERS
@@ -0,0 +1,7 @@
+A38X BOARD
+M:	Dirk Eibach <dirk.eibach@gdsys.cc>
+M:	Mario Six <mario.six@gdsys.cc>
+S:	Maintained
+F:	board/gdsys/a38x/
+F:	include/configs/controlcenterdc.h
+F:	configs/controlcenterdc_defconfig
diff --git a/roms/u-boot/board/gdsys/a38x/Makefile b/roms/u-boot/board/gdsys/a38x/Makefile
new file mode 100644
index 000000000..32fffab46
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+# Copyright (C) 2015 Reinhard Pfau <reinhard.pfau@gdsys.cc>
+# Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
+
+obj-$(CONFIG_TARGET_CONTROLCENTERDC) += controlcenterdc.o hre.o spl.o keyprogram.o dt_helpers.o
+
+ifeq ($(CONFIG_SPL_BUILD),)
+obj-$(CONFIG_TARGET_CONTROLCENTERDC) += hydra.o ihs_phys.o
+endif
diff --git a/roms/u-boot/board/gdsys/a38x/controlcenterdc.c b/roms/u-boot/board/gdsys/a38x/controlcenterdc.c
new file mode 100644
index 000000000..dc424f271
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/controlcenterdc.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <tpm-v1.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm-generic/gpio.h>
+#include <linux/delay.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
+
+#include "keyprogram.h"
+#include "dt_helpers.h"
+#include "hydra.h"
+#include "ihs_phys.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DB_GP_88F68XX_GPP_OUT_ENA_LOW	0x7fffffff
+#define DB_GP_88F68XX_GPP_OUT_ENA_MID	0xffffefff
+
+#define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
+#define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x00001000
+#define DB_GP_88F68XX_GPP_POL_LOW	0x0
+#define DB_GP_88F68XX_GPP_POL_MID	0x0
+
+static int get_tpm(struct udevice **devp)
+{
+	int rc;
+
+	rc = uclass_first_device_err(UCLASS_TPM, devp);
+	if (rc) {
+		printf("Could not find TPM (ret=%d)\n", rc);
+		return CMD_RET_FAILURE;
+	}
+
+	return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct mv_ddr_topology_map ddr_topology_map = {
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1600K,	/* speed_bin */
+	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
+	    MV_DDR_DIE_CAP_4GBIT,	/* mem_size */
+	    MV_DDR_FREQ_533,		/* frequency */
+	    0, 0,			/* cas_wl cas_l */
+	    MV_DDR_TEMP_LOW,		/* temperature */
+	    MV_DDR_TIM_DEFAULT} },	/* timing */
+	BUS_MASK_32BIT,			/* Busses mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+
+};
+
+static struct serdes_map serdes_topology_map[] = {
+	{SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	/* SATA tx polarity is inverted */
+	{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
+	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	*serdes_map_array = serdes_topology_map;
+	*count = ARRAY_SIZE(serdes_topology_map);
+	return 0;
+}
+
+void board_pex_config(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	uint k;
+	struct gpio_desc gpio = {};
+
+	if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
+		/* prepare FPGA reconfiguration */
+		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
+		dm_gpio_set_value(&gpio, 0);
+
+		/* give lunatic PCIe clock some time to stabilize */
+		mdelay(500);
+
+		/* start FPGA reconfiguration */
+		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
+	}
+
+	/* wait for FPGA done */
+	if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
+		for (k = 0; k < 20; ++k) {
+			if (dm_gpio_get_value(&gpio)) {
+				printf("FPGA done after %u rounds\n", k);
+				break;
+			}
+			mdelay(100);
+		}
+	}
+
+	/* disable FPGA reset */
+	if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
+		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
+		dm_gpio_set_value(&gpio, 1);
+	}
+
+	/* wait for FPGA ready */
+	if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
+		for (k = 0; k < 2; ++k) {
+			if (!dm_gpio_get_value(&gpio))
+				break;
+			mdelay(100);
+		}
+	}
+#endif
+}
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	return &ddr_topology_map;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	/* Configure MPP */
+	writel(0x00111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x40040000, MVEBU_MPP_BASE + 0x04);
+	writel(0x00466444, MVEBU_MPP_BASE + 0x08);
+	writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
+	writel(0x44400000, MVEBU_MPP_BASE + 0x10);
+	writel(0x20000334, MVEBU_MPP_BASE + 0x14);
+	writel(0x40000000, MVEBU_MPP_BASE + 0x18);
+	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+void init_host_phys(struct mii_dev *bus)
+{
+	uint k;
+
+	for (k = 0; k < 2; ++k) {
+		struct phy_device *phydev;
+
+		phydev = phy_find_by_mask(bus, 1 << k,
+					  PHY_INTERFACE_MODE_SGMII);
+
+		if (phydev)
+			phy_config(phydev);
+	}
+}
+
+int ccdc_eth_init(void)
+{
+	uint k;
+	uint octo_phy_mask = 0;
+	int ret;
+	struct mii_dev *bus;
+
+	/* Init SoC's phys */
+	bus = miiphy_get_dev_by_name("ethernet@34000");
+
+	if (bus)
+		init_host_phys(bus);
+
+	bus = miiphy_get_dev_by_name("ethernet@70000");
+
+	if (bus)
+		init_host_phys(bus);
+
+	/* Init octo phys */
+	octo_phy_mask = calculate_octo_phy_mask();
+
+	printf("IHS PHYS: %08x", octo_phy_mask);
+
+	ret = init_octo_phys(octo_phy_mask);
+
+	if (ret)
+		return ret;
+
+	printf("\n");
+
+	if (!get_fpga()) {
+		puts("fpga was NULL\n");
+		return 1;
+	}
+
+	/* reset all FPGA-QSGMII instances */
+	for (k = 0; k < 80; ++k)
+		writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
+
+	udelay(100);
+
+	for (k = 0; k < 80; ++k)
+		writel(0, get_fpga()->qsgmii_port_state[k]);
+	return 0;
+}
+
+#endif
+
+int board_late_init(void)
+{
+#ifndef CONFIG_SPL_BUILD
+	hydra_initialize();
+#endif
+	return 0;
+}
+
+int board_fix_fdt(void *rw_fdt_blob)
+{
+	struct udevice *bus = NULL;
+	uint k;
+	char name[64];
+	int err;
+
+	err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
+
+	if (err) {
+		printf("Could not get I2C bus.\n");
+		return err;
+	}
+
+	for (k = 0x21; k <= 0x26; k++) {
+		snprintf(name, 64,
+			 "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
+
+		if (!dm_i2c_simple_probe(bus, k))
+			fdt_disable_by_ofname(rw_fdt_blob, name);
+	}
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	struct udevice *tpm;
+	int ret;
+
+#ifndef CONFIG_SPL_BUILD
+	ccdc_eth_init();
+#endif
+	ret = get_tpm(&tpm);
+	if (ret || tpm_init(tpm) || tpm1_startup(tpm, TPM_ST_CLEAR) ||
+	    tpm1_continue_self_test(tpm)) {
+		return 1;
+	}
+
+	mdelay(37);
+
+	flush_keys(tpm);
+	load_and_run_keyprog(tpm);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/gdsys/a38x/dt_helpers.c b/roms/u-boot/board/gdsys/a38x/dt_helpers.c
new file mode 100644
index 000000000..c859024a2
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/dt_helpers.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+
+int fdt_disable_by_ofname(void *rw_fdt_blob, char *ofname)
+{
+	int offset = fdt_path_offset(rw_fdt_blob, ofname);
+
+	return fdt_status_disabled(rw_fdt_blob, offset);
+}
+
+bool dm_i2c_simple_probe(struct udevice *bus, uint chip_addr)
+{
+	struct udevice *dev;
+
+	return !dm_i2c_probe(bus, chip_addr, DM_I2C_CHIP_RD_ADDRESS |
+			     DM_I2C_CHIP_WR_ADDRESS, &dev);
+}
+
+int request_gpio_by_name(struct gpio_desc *gpio, const char *gpio_dev_name,
+			 uint offset, char *gpio_name)
+{
+	struct udevice *gpio_dev = NULL;
+
+	if (uclass_get_device_by_name(UCLASS_GPIO, gpio_dev_name, &gpio_dev))
+		return 1;
+
+	gpio->dev = gpio_dev;
+	gpio->offset = offset;
+	gpio->flags = 0;
+
+	return dm_gpio_request(gpio, gpio_name);
+}
+
diff --git a/roms/u-boot/board/gdsys/a38x/dt_helpers.h b/roms/u-boot/board/gdsys/a38x/dt_helpers.h
new file mode 100644
index 000000000..245fadd0d
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/dt_helpers.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef __DT_HELPERS_H
+#define __DT_HELPERS_H
+
+int fdt_disable_by_ofname(void *rw_fdt_blob, char *ofname);
+bool dm_i2c_simple_probe(struct udevice *bus, uint chip_addr);
+int request_gpio_by_name(struct gpio_desc *gpio, const char *gpio_dev_name,
+			 uint offset, char *gpio_name);
+
+#endif /* __DT_HELPERS_H */
diff --git a/roms/u-boot/board/gdsys/a38x/hre.c b/roms/u-boot/board/gdsys/a38x/hre.c
new file mode 100644
index 000000000..de5411a6b
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/hre.c
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013
+ * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
+ */
+
+#include <common.h>
+#include <log.h>
+#include <malloc.h>
+#include <fs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <tpm-v1.h>
+#include <u-boot/crc.h>
+#include <u-boot/sha1.h>
+#include <asm/byteorder.h>
+#include <asm/unaligned.h>
+#include <pca9698.h>
+
+#include "hre.h"
+
+/* other constants */
+enum {
+	ESDHC_BOOT_IMAGE_SIG_OFS	= 0x40,
+	ESDHC_BOOT_IMAGE_SIZE_OFS	= 0x48,
+	ESDHC_BOOT_IMAGE_ADDR_OFS	= 0x50,
+	ESDHC_BOOT_IMAGE_TARGET_OFS	= 0x58,
+	ESDHC_BOOT_IMAGE_ENTRY_OFS	= 0x60,
+};
+
+enum {
+	I2C_SOC_0 = 0,
+	I2C_SOC_1 = 1,
+};
+
+enum access_mode {
+	HREG_NONE	= 0,
+	HREG_RD		= 1,
+	HREG_WR		= 2,
+	HREG_RDWR	= 3,
+};
+
+/* register constants */
+enum {
+	FIX_HREG_DEVICE_ID_HASH	= 0,
+	FIX_HREG_UNUSED1	= 1,
+	FIX_HREG_UNUSED2	= 2,
+	FIX_HREG_VENDOR		= 3,
+	COUNT_FIX_HREGS
+};
+
+static struct h_reg pcr_hregs[24];
+static struct h_reg fix_hregs[COUNT_FIX_HREGS];
+static struct h_reg var_hregs[8];
+
+/* hre opcodes */
+enum {
+	/* opcodes w/o data */
+	HRE_NOP		= 0x00,
+	HRE_SYNC	= HRE_NOP,
+	HRE_CHECK0	= 0x01,
+	/* opcodes w/o data, w/ sync dst */
+	/* opcodes w/ data */
+	HRE_LOAD	= 0x81,
+	/* opcodes w/data, w/sync dst */
+	HRE_XOR		= 0xC1,
+	HRE_AND		= 0xC2,
+	HRE_OR		= 0xC3,
+	HRE_EXTEND	= 0xC4,
+	HRE_LOADKEY	= 0xC5,
+};
+
+/* hre errors */
+enum {
+	HRE_E_OK	= 0,
+	HRE_E_TPM_FAILURE,
+	HRE_E_INVALID_HREG,
+};
+
+static uint64_t device_id;
+static uint64_t device_cl;
+static uint64_t device_type;
+
+static uint32_t platform_key_handle;
+
+static uint32_t hre_tpm_err;
+static int hre_err = HRE_E_OK;
+
+#define IS_PCR_HREG(spec) ((spec) & 0x20)
+#define IS_FIX_HREG(spec) (((spec) & 0x38) == 0x08)
+#define IS_VAR_HREG(spec) (((spec) & 0x38) == 0x10)
+#define HREG_IDX(spec) ((spec) & (IS_PCR_HREG(spec) ? 0x1f : 0x7))
+
+static const uint8_t vendor[] = "Guntermann & Drunck";
+
+/**
+ * @brief get the size of a given (TPM) NV area
+ * @param tpm		TPM device
+ * @param index	NV index of the area to get size for
+ * @param size	pointer to the size
+ * @return 0 on success, != 0 on error
+ */
+static int get_tpm_nv_size(struct udevice *tpm, uint32_t index, uint32_t *size)
+{
+	uint32_t err;
+	uint8_t info[72];
+	uint8_t *ptr;
+	uint16_t v16;
+
+	err = tpm1_get_capability(tpm, TPM_CAP_NV_INDEX, index, info,
+				  sizeof(info));
+	if (err) {
+		printf("tpm_get_capability(CAP_NV_INDEX, %08x) failed: %u\n",
+		       index, err);
+		return 1;
+	}
+
+	/* skip tag and nvIndex */
+	ptr = info + 6;
+	/* skip 2 pcr info fields */
+	v16 = get_unaligned_be16(ptr);
+	ptr += 2 + v16 + 1 + 20;
+	v16 = get_unaligned_be16(ptr);
+	ptr += 2 + v16 + 1 + 20;
+	/* skip permission and flags */
+	ptr += 6 + 3;
+
+	*size = get_unaligned_be32(ptr);
+	return 0;
+}
+
+/**
+ * @brief search for a key by usage auth and pub key hash.
+ * @param tpm		TPM device
+ * @param auth	usage auth of the key to search for
+ * @param pubkey_digest	(SHA1) hash of the pub key structure of the key
+ * @param[out] handle	the handle of the key iff found
+ * @return 0 if key was found in TPM; != 0 if not.
+ */
+static int find_key(struct udevice *tpm, const uint8_t auth[20],
+		    const uint8_t pubkey_digest[20], uint32_t *handle)
+{
+	uint16_t key_count;
+	uint32_t key_handles[10];
+	uint8_t buf[288];
+	uint8_t *ptr;
+	uint32_t err;
+	uint8_t digest[20];
+	size_t buf_len;
+	unsigned int i;
+
+	/* fetch list of already loaded keys in the TPM */
+	err = tpm1_get_capability(tpm, TPM_CAP_HANDLE, TPM_RT_KEY, buf,
+				  sizeof(buf));
+	if (err)
+		return -1;
+	key_count = get_unaligned_be16(buf);
+	ptr = buf + 2;
+	for (i = 0; i < key_count; ++i, ptr += 4)
+		key_handles[i] = get_unaligned_be32(ptr);
+
+	/* now search a(/ the) key which we can access with the given auth */
+	for (i = 0; i < key_count; ++i) {
+		buf_len = sizeof(buf);
+		err = tpm1_get_pub_key_oiap(tpm, key_handles[i], auth, buf,
+					    &buf_len);
+		if (err && err != TPM_AUTHFAIL)
+			return -1;
+		if (err)
+			continue;
+		sha1_csum(buf, buf_len, digest);
+		if (!memcmp(digest, pubkey_digest, 20)) {
+			*handle = key_handles[i];
+			return 0;
+		}
+	}
+	return 1;
+}
+
+/**
+ * @brief read CCDM common data from TPM NV
+ * @param tpm		TPM device
+ * @return 0 if CCDM common data was found and read, !=0 if something failed.
+ */
+static int read_common_data(struct udevice *tpm)
+{
+	uint32_t size = 0;
+	uint32_t err;
+	uint8_t buf[256];
+	sha1_context ctx;
+
+	if (get_tpm_nv_size(tpm, NV_COMMON_DATA_INDEX, &size) ||
+	    size < NV_COMMON_DATA_MIN_SIZE)
+		return 1;
+	err = tpm1_nv_read_value(tpm, NV_COMMON_DATA_INDEX, buf,
+				 min(sizeof(buf), size));
+	if (err) {
+		printf("tpm_nv_read_value() failed: %u\n", err);
+		return 1;
+	}
+
+	device_id = get_unaligned_be64(buf);
+	device_cl = get_unaligned_be64(buf + 8);
+	device_type = get_unaligned_be64(buf + 16);
+
+	sha1_starts(&ctx);
+	sha1_update(&ctx, buf, 24);
+	sha1_finish(&ctx, fix_hregs[FIX_HREG_DEVICE_ID_HASH].digest);
+	fix_hregs[FIX_HREG_DEVICE_ID_HASH].valid = true;
+
+	platform_key_handle = get_unaligned_be32(buf + 24);
+
+	return 0;
+}
+
+/**
+ * @brief get pointer to  hash register by specification
+ * @param spec	specification of a hash register
+ * @return pointer to hash register or NULL if @a spec does not qualify a
+ * valid hash register; NULL else.
+ */
+static struct h_reg *get_hreg(uint8_t spec)
+{
+	uint8_t idx;
+
+	idx = HREG_IDX(spec);
+	if (IS_FIX_HREG(spec)) {
+		if (idx < ARRAY_SIZE(fix_hregs))
+			return fix_hregs + idx;
+		hre_err = HRE_E_INVALID_HREG;
+	} else if (IS_PCR_HREG(spec)) {
+		if (idx < ARRAY_SIZE(pcr_hregs))
+			return pcr_hregs + idx;
+		hre_err = HRE_E_INVALID_HREG;
+	} else if (IS_VAR_HREG(spec)) {
+		if (idx < ARRAY_SIZE(var_hregs))
+			return var_hregs + idx;
+		hre_err = HRE_E_INVALID_HREG;
+	}
+	return NULL;
+}
+
+/**
+ * @brief get pointer of a hash register by specification and usage.
+ * @param tpm		TPM device
+ * @param spec	specification of a hash register
+ * @param mode	access mode (read or write or read/write)
+ * @return pointer to hash register if found and valid; NULL else.
+ *
+ * This func uses @a get_reg() to determine the hash register for a given spec.
+ * If a register is found it is validated according to the desired access mode.
+ * The value of automatic registers (PCR register and fixed registers) is
+ * loaded or computed on read access.
+ */
+static struct h_reg *access_hreg(struct udevice *tpm, uint8_t spec,
+				 enum access_mode mode)
+{
+	struct h_reg *result;
+
+	result = get_hreg(spec);
+	if (!result)
+		return NULL;
+
+	if (mode & HREG_WR) {
+		if (IS_FIX_HREG(spec)) {
+			hre_err = HRE_E_INVALID_HREG;
+			return NULL;
+		}
+	}
+	if (mode & HREG_RD) {
+		if (!result->valid) {
+			if (IS_PCR_HREG(spec)) {
+				hre_tpm_err = tpm1_pcr_read(tpm, HREG_IDX(spec),
+							    result->digest, 20);
+				result->valid = (hre_tpm_err == TPM_SUCCESS);
+			} else if (IS_FIX_HREG(spec)) {
+				switch (HREG_IDX(spec)) {
+				case FIX_HREG_DEVICE_ID_HASH:
+					read_common_data(tpm);
+					break;
+				case FIX_HREG_VENDOR:
+					memcpy(result->digest, vendor, 20);
+					result->valid = true;
+					break;
+				}
+			} else {
+				result->valid = true;
+			}
+		}
+		if (!result->valid) {
+			hre_err = HRE_E_INVALID_HREG;
+			return NULL;
+		}
+	}
+
+	return result;
+}
+
+static void *compute_and(void *_dst, const void *_src, size_t n)
+{
+	uint8_t *dst = _dst;
+	const uint8_t *src = _src;
+	size_t i;
+
+	for (i = n; i-- > 0; )
+		*dst++ &= *src++;
+
+	return _dst;
+}
+
+static void *compute_or(void *_dst, const void *_src, size_t n)
+{
+	uint8_t *dst = _dst;
+	const uint8_t *src = _src;
+	size_t i;
+
+	for (i = n; i-- > 0; )
+		*dst++ |= *src++;
+
+	return _dst;
+}
+
+static void *compute_xor(void *_dst, const void *_src, size_t n)
+{
+	uint8_t *dst = _dst;
+	const uint8_t *src = _src;
+	size_t i;
+
+	for (i = n; i-- > 0; )
+		*dst++ ^= *src++;
+
+	return _dst;
+}
+
+static void *compute_extend(void *_dst, const void *_src, size_t n)
+{
+	uint8_t digest[20];
+	sha1_context ctx;
+
+	sha1_starts(&ctx);
+	sha1_update(&ctx, _dst, n);
+	sha1_update(&ctx, _src, n);
+	sha1_finish(&ctx, digest);
+	memcpy(_dst, digest, min(n, sizeof(digest)));
+
+	return _dst;
+}
+
+static int hre_op_loadkey(struct udevice *tpm, struct h_reg *src_reg,
+			  struct h_reg *dst_reg, const void *key,
+			  size_t key_size)
+{
+	uint32_t parent_handle;
+	uint32_t key_handle;
+
+	if (!src_reg || !dst_reg || !src_reg->valid || !dst_reg->valid)
+		return -1;
+	if (find_key(tpm, src_reg->digest, dst_reg->digest, &parent_handle))
+		return -1;
+	hre_tpm_err = tpm1_load_key2_oiap(tpm, parent_handle, key, key_size,
+					  src_reg->digest, &key_handle);
+	if (hre_tpm_err) {
+		hre_err = HRE_E_TPM_FAILURE;
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief executes the next opcode on the hash register engine.
+ * @param tpm		TPM device
+ * @param[in,out] ip	pointer to the opcode (instruction pointer)
+ * @param[in,out] code_size	(remaining) size of the code
+ * @return new instruction pointer on success, NULL on error.
+ */
+static const uint8_t *hre_execute_op(struct udevice *tpm, const uint8_t **ip,
+				     size_t *code_size)
+{
+	bool dst_modified = false;
+	uint32_t ins;
+	uint8_t opcode;
+	uint8_t src_spec;
+	uint8_t dst_spec;
+	uint16_t data_size;
+	struct h_reg *src_reg, *dst_reg;
+	uint8_t buf[20];
+	const uint8_t *src_buf, *data;
+	uint8_t *ptr;
+	int i;
+	void * (*bin_func)(void *, const void *, size_t);
+
+	if (*code_size < 4)
+		return NULL;
+
+	ins = get_unaligned_be32(*ip);
+	opcode = **ip;
+	data = *ip + 4;
+	src_spec = (ins >> 18) & 0x3f;
+	dst_spec = (ins >> 12) & 0x3f;
+	data_size = (ins & 0x7ff);
+
+	debug("HRE: ins=%08x (op=%02x, s=%02x, d=%02x, L=%d)\n", ins,
+	      opcode, src_spec, dst_spec, data_size);
+
+	if ((opcode & 0x80) && (data_size + 4) > *code_size)
+		return NULL;
+
+	src_reg = access_hreg(tpm, src_spec, HREG_RD);
+	if (hre_err || hre_tpm_err)
+		return NULL;
+	dst_reg = access_hreg(tpm, dst_spec,
+			      (opcode & 0x40) ? HREG_RDWR : HREG_WR);
+	if (hre_err || hre_tpm_err)
+		return NULL;
+
+	switch (opcode) {
+	case HRE_NOP:
+		goto end;
+	case HRE_CHECK0:
+		if (src_reg) {
+			for (i = 0; i < 20; ++i) {
+				if (src_reg->digest[i])
+					return NULL;
+			}
+		}
+		break;
+	case HRE_LOAD:
+		bin_func = memcpy;
+		goto do_bin_func;
+	case HRE_XOR:
+		bin_func = compute_xor;
+		goto do_bin_func;
+	case HRE_AND:
+		bin_func = compute_and;
+		goto do_bin_func;
+	case HRE_OR:
+		bin_func = compute_or;
+		goto do_bin_func;
+	case HRE_EXTEND:
+		bin_func = compute_extend;
+do_bin_func:
+		if (!dst_reg)
+			return NULL;
+		if (src_reg) {
+			src_buf = src_reg->digest;
+		} else {
+			if (!data_size) {
+				memset(buf, 0, 20);
+				src_buf = buf;
+			} else if (data_size == 1) {
+				memset(buf, *data, 20);
+				src_buf = buf;
+			} else if (data_size >= 20) {
+				src_buf = data;
+			} else {
+				src_buf = buf;
+				for (ptr = (uint8_t *)src_buf, i = 20; i > 0;
+					i -= data_size, ptr += data_size)
+					memcpy(ptr, data,
+					       min_t(size_t, i, data_size));
+			}
+		}
+		bin_func(dst_reg->digest, src_buf, 20);
+		dst_reg->valid = true;
+		dst_modified = true;
+		break;
+	case HRE_LOADKEY:
+		if (hre_op_loadkey(tpm, src_reg, dst_reg, data, data_size))
+			return NULL;
+		break;
+	default:
+		return NULL;
+	}
+
+	if (dst_reg && dst_modified && IS_PCR_HREG(dst_spec)) {
+		hre_tpm_err = tpm1_extend(tpm, HREG_IDX(dst_spec),
+					  dst_reg->digest, dst_reg->digest);
+		if (hre_tpm_err) {
+			hre_err = HRE_E_TPM_FAILURE;
+			return NULL;
+		}
+	}
+end:
+	*ip += 4;
+	*code_size -= 4;
+	if (opcode & 0x80) {
+		*ip += data_size;
+		*code_size -= data_size;
+	}
+
+	return *ip;
+}
+
+/**
+ * @brief runs a program on the hash register engine.
+ * @param tpm		TPM device
+ * @param code		pointer to the (HRE) code.
+ * @param code_size	size of the code (in bytes).
+ * @return 0 on success, != 0 on failure.
+ */
+int hre_run_program(struct udevice *tpm, const uint8_t *code, size_t code_size)
+{
+	size_t code_left;
+	const uint8_t *ip = code;
+
+	code_left = code_size;
+	hre_tpm_err = 0;
+	hre_err = HRE_E_OK;
+	while (code_left > 0)
+		if (!hre_execute_op(tpm, &ip, &code_left))
+			return -1;
+
+	return hre_err;
+}
+
+int hre_verify_program(struct key_program *prg)
+{
+	uint32_t crc;
+
+	crc = crc32(0, prg->code, prg->code_size);
+
+	if (crc != prg->code_crc) {
+		printf("HRC crc mismatch: %08x != %08x\n",
+		       crc, prg->code_crc);
+		return 1;
+	}
+	return 0;
+}
diff --git a/roms/u-boot/board/gdsys/a38x/hre.h b/roms/u-boot/board/gdsys/a38x/hre.h
new file mode 100644
index 000000000..da983aa45
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/hre.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
+ */
+
+#ifndef __HRE_H
+#define __HRE_H
+
+struct key_program {
+	uint32_t magic;
+	uint32_t code_crc;
+	uint32_t code_size;
+	uint8_t code[];
+};
+
+struct h_reg {
+	bool valid;
+	uint8_t digest[20];
+};
+
+/* CCDM specific contants */
+enum {
+	/* NV indices */
+	NV_COMMON_DATA_INDEX	= 0x40000001,
+	/* magics for key blob chains */
+	MAGIC_KEY_PROGRAM	= 0x68726500,
+	MAGIC_HMAC		= 0x68616300,
+	MAGIC_END_OF_CHAIN	= 0x00000000,
+	/* sizes */
+	NV_COMMON_DATA_MIN_SIZE	= 3 * sizeof(uint64_t) + 2 * sizeof(uint16_t),
+};
+
+int hre_verify_program(struct key_program *prg);
+int hre_run_program(struct udevice *tpm, const uint8_t *code, size_t code_size);
+
+#endif /* __HRE_H */
diff --git a/roms/u-boot/board/gdsys/a38x/hydra.c b/roms/u-boot/board/gdsys/a38x/hydra.c
new file mode 100644
index 000000000..495a97691
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/hydra.c
@@ -0,0 +1,140 @@
+#include <common.h>
+#include <command.h>
+#include <console.h> /* ctrlc */
+#include <pci.h>
+#include <asm/io.h>
+
+#include "hydra.h"
+
+enum {
+	HWVER_100 = 0,
+	HWVER_110 = 1,
+	HWVER_120 = 2,
+};
+
+static struct pci_device_id hydra_supported[] = {
+	{ 0x6d5e, 0xcdc1 },
+	{}
+};
+
+static struct ihs_fpga *fpga;
+
+struct ihs_fpga *get_fpga(void)
+{
+	return fpga;
+}
+
+void print_hydra_version(uint index)
+{
+	u32 versions = readl(&fpga->versions);
+	u32 fpga_version = readl(&fpga->fpga_version);
+
+	uint hardware_version = versions & 0xf;
+
+	printf("FPGA%u: mapped to %p\n       ", index, fpga);
+
+	switch (hardware_version) {
+	case HWVER_100:
+		printf("HW-Ver 1.00\n");
+		break;
+
+	case HWVER_110:
+		printf("HW-Ver 1.10\n");
+		break;
+
+	case HWVER_120:
+		printf("HW-Ver 1.20\n");
+		break;
+
+	default:
+		printf("HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d\n",
+	       fpga_version / 100, fpga_version % 100);
+}
+
+void hydra_initialize(void)
+{
+	uint i;
+	pci_dev_t devno;
+
+	/* Find and probe all the matching PCI devices */
+	for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
+		u32 val;
+
+		/* Try to enable I/O accesses and bus-mastering */
+		val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+		pci_write_config_dword(devno, PCI_COMMAND, val);
+
+		/* Make sure it worked */
+		pci_read_config_dword(devno, PCI_COMMAND, &val);
+		if (!(val & PCI_COMMAND_MEMORY)) {
+			puts("Can't enable I/O memory\n");
+			continue;
+		}
+		if (!(val & PCI_COMMAND_MASTER)) {
+			puts("Can't enable bus-mastering\n");
+			continue;
+		}
+
+		/* read FPGA details */
+		fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
+				   PCI_REGION_MEM);
+
+		print_hydra_version(i);
+	}
+}
+
+#define REFL_PATTERN (0xdededede)
+#define REFL_PATTERN_INV (~REFL_PATTERN)
+
+int do_hydrate(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	uint k = 0;
+	void __iomem *pcie2_base = (void __iomem *)(MVEBU_REG_PCIE_BASE +
+						    0x4000);
+
+	if (!fpga)
+		return -1;
+
+	while (1) {
+		u32 res;
+
+		writel(REFL_PATTERN, &fpga->reflection_low);
+		res = readl(&fpga->reflection_low);
+		if (res != REFL_PATTERN_INV)
+			printf("round %u: read %08x, expected %08x\n",
+			       k, res, REFL_PATTERN_INV);
+		writel(REFL_PATTERN_INV, &fpga->reflection_low);
+		res = readl(&fpga->reflection_low);
+		if (res != REFL_PATTERN)
+			printf("round %u: read %08x, expected %08x\n",
+			       k, res, REFL_PATTERN);
+
+		res = readl(pcie2_base + 0x118) & 0x1f;
+		if (res)
+			printf("FrstErrPtr %u\n", res);
+		res = readl(pcie2_base + 0x104);
+		if (res) {
+			printf("Uncorrectable Error Status 0x%08x\n", res);
+			writel(res, pcie2_base + 0x104);
+		}
+
+		if (!(++k % 10000))
+			printf("round %u\n", k);
+
+		if (ctrlc())
+			break;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	hydrate,	1,	0,	do_hydrate,
+	"hydra reflection test",
+	"hydra reflection test"
+);
diff --git a/roms/u-boot/board/gdsys/a38x/hydra.h b/roms/u-boot/board/gdsys/a38x/hydra.h
new file mode 100644
index 000000000..26562a560
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/hydra.h
@@ -0,0 +1,14 @@
+struct ihs_fpga {
+	u32 reflection_low;		/* 0x0000 */
+	u32 versions;			/* 0x0004 */
+	u32 fpga_version;		/* 0x0008 */
+	u32 fpga_features;		/* 0x000c */
+	u32 reserved0[4];		/* 0x0010 */
+	u32 control;			/* 0x0020 */
+	u32 reserved1[375];		/* 0x0024 */
+	u32 qsgmii_port_state[80];	/* 0x0600 */
+};
+
+void print_hydra_version(uint index);
+void hydra_initialize(void);
+struct ihs_fpga *get_fpga(void);
diff --git a/roms/u-boot/board/gdsys/a38x/ihs_phys.c b/roms/u-boot/board/gdsys/a38x/ihs_phys.c
new file mode 100644
index 000000000..c23d15092
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/ihs_phys.c
@@ -0,0 +1,357 @@
+#include <common.h>
+#include <dm.h>
+#include <miiphy.h>
+#include <asm-generic/gpio.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+#include "ihs_phys.h"
+#include "dt_helpers.h"
+
+enum {
+	PORTTYPE_MAIN_CAT,
+	PORTTYPE_TOP_CAT,
+	PORTTYPE_16C_16F,
+	PORTTYPE_UNKNOWN
+};
+
+static struct porttype {
+	bool phy_invert_in_pol;
+	bool phy_invert_out_pol;
+} porttypes[] = {
+	{ true, false },
+	{ false, true },
+	{ false, false },
+};
+
+static void ihs_phy_config(struct phy_device *phydev, bool qinpn, bool qoutpn)
+{
+	u16 reg;
+
+	phy_config(phydev);
+
+	/* enable QSGMII autonegotiation with flow control */
+	phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0004);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 16);
+	reg |= (3 << 6);
+	phy_write(phydev, MDIO_DEVAD_NONE, 16, reg);
+
+	/*
+	 * invert QSGMII Q_INP/N and Q_OUTP/N if required
+	 * and perform global reset
+	 */
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 26);
+	if (qinpn)
+		reg |= (1 << 13);
+	if (qoutpn)
+		reg |= (1 << 12);
+	reg |= (1 << 15);
+	phy_write(phydev, MDIO_DEVAD_NONE, 26, reg);
+
+	/* advertise 1000BASE-T full-duplex only  */
+	phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 4);
+	reg &= ~0x1e0;
+	phy_write(phydev, MDIO_DEVAD_NONE, 4, reg);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 9);
+	reg = (reg & ~0x300) | 0x200;
+	phy_write(phydev, MDIO_DEVAD_NONE, 9, reg);
+
+	/* copper power up */
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 16);
+	reg &= ~0x0004;
+	phy_write(phydev, MDIO_DEVAD_NONE, 16, reg);
+}
+
+uint calculate_octo_phy_mask(void)
+{
+	uint k;
+	uint octo_phy_mask = 0;
+	struct gpio_desc gpio = {};
+	char gpio_name[64];
+	static const char * const dev_name[] = {"pca9698@23", "pca9698@21",
+						"pca9698@24", "pca9698@25",
+						"pca9698@26"};
+
+	/* mark all octo phys that should be present */
+	for (k = 0; k < 5; ++k) {
+		snprintf(gpio_name, 64, "cat-gpio-%u", k);
+
+		if (request_gpio_by_name(&gpio, dev_name[k], 0x20, gpio_name))
+			continue;
+
+		/* check CAT flag */
+		if (dm_gpio_get_value(&gpio))
+			octo_phy_mask |= (1 << (k * 2));
+		else
+			/* If CAT == 0, there's no second octo phy -> skip */
+			continue;
+
+		snprintf(gpio_name, 64, "second-octo-gpio-%u", k);
+
+		if (request_gpio_by_name(&gpio, dev_name[k], 0x27, gpio_name)) {
+			/* default: second octo phy is present */
+			octo_phy_mask |= (1 << (k * 2 + 1));
+			continue;
+		}
+
+		if (dm_gpio_get_value(&gpio) == 0)
+			octo_phy_mask |= (1 << (k * 2 + 1));
+	}
+
+	return octo_phy_mask;
+}
+
+int register_miiphy_bus(uint k, struct mii_dev **bus)
+{
+	int retval;
+	struct mii_dev *mdiodev = mdio_alloc();
+	char *name = bb_miiphy_buses[k].name;
+
+	if (!mdiodev)
+		return -ENOMEM;
+	strncpy(mdiodev->name,
+		name,
+		MDIO_NAME_LEN);
+	mdiodev->read = bb_miiphy_read;
+	mdiodev->write = bb_miiphy_write;
+
+	retval = mdio_register(mdiodev);
+	if (retval < 0)
+		return retval;
+	*bus = miiphy_get_dev_by_name(name);
+
+	return 0;
+}
+
+struct porttype *get_porttype(uint octo_phy_mask, uint k)
+{
+	uint octo_index = k * 4;
+
+	if (!k) {
+		if (octo_phy_mask & 0x01)
+			return &porttypes[PORTTYPE_MAIN_CAT];
+		else if (!(octo_phy_mask & 0x03))
+			return &porttypes[PORTTYPE_16C_16F];
+	} else {
+		if (octo_phy_mask & (1 << octo_index))
+			return &porttypes[PORTTYPE_TOP_CAT];
+	}
+
+	return NULL;
+}
+
+int init_single_phy(struct porttype *porttype, struct mii_dev *bus,
+		    uint bus_idx, uint m, uint phy_idx)
+{
+	struct phy_device *phydev = phy_find_by_mask(
+		bus, 1 << (m * 8 + phy_idx),
+		PHY_INTERFACE_MODE_MII);
+
+	printf(" %u", bus_idx * 32 + m * 8 + phy_idx);
+
+	if (!phydev)
+		puts("!");
+	else
+		ihs_phy_config(phydev, porttype->phy_invert_in_pol,
+			       porttype->phy_invert_out_pol);
+
+	return 0;
+}
+
+int init_octo_phys(uint octo_phy_mask)
+{
+	uint bus_idx;
+
+	/* there are up to four octo-phys on each mdio bus */
+	for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; ++bus_idx) {
+		uint m;
+		uint octo_index = bus_idx * 4;
+		struct mii_dev *bus = NULL;
+		struct porttype *porttype = NULL;
+		int ret;
+
+		porttype = get_porttype(octo_phy_mask, bus_idx);
+
+		if (!porttype)
+			continue;
+
+		for (m = 0; m < 4; ++m) {
+			uint phy_idx;
+
+			/**
+			 * Register a bus device if there is at least one phy
+			 * on the current bus
+			 */
+			if (!m && octo_phy_mask & (0xf << octo_index)) {
+				ret = register_miiphy_bus(bus_idx, &bus);
+				if (ret)
+					return ret;
+			}
+
+			if (!(octo_phy_mask & BIT(octo_index + m)))
+				continue;
+
+			for (phy_idx = 0; phy_idx < 8; ++phy_idx)
+				init_single_phy(porttype, bus, bus_idx, m,
+						phy_idx);
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * MII GPIO bitbang implementation
+ * MDC MDIO bus
+ * 13  14   PHY1-4
+ * 25  45   PHY5-8
+ * 46  24   PHY9-10
+ */
+
+struct gpio_mii {
+	int index;
+	struct gpio_desc mdc_gpio;
+	struct gpio_desc mdio_gpio;
+	int mdc_num;
+	int mdio_num;
+	int mdio_value;
+} gpio_mii_set[] = {
+	{ 0, {}, {}, 13, 14, 1 },
+	{ 1, {}, {}, 25, 45, 1 },
+	{ 2, {}, {}, 46, 24, 1 },
+};
+
+static int mii_mdio_init(struct bb_miiphy_bus *bus)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+	char name[32] = {};
+	struct udevice *gpio_dev1 = NULL;
+	struct udevice *gpio_dev2 = NULL;
+
+	if (uclass_get_device_by_name(UCLASS_GPIO, "gpio@18100", &gpio_dev1) ||
+	    uclass_get_device_by_name(UCLASS_GPIO, "gpio@18140", &gpio_dev2)) {
+		printf("Could not get GPIO device.\n");
+		return 1;
+	}
+
+	if (gpio_mii->mdc_num > 31) {
+		gpio_mii->mdc_gpio.dev = gpio_dev2;
+		gpio_mii->mdc_gpio.offset = gpio_mii->mdc_num - 32;
+	} else {
+		gpio_mii->mdc_gpio.dev = gpio_dev1;
+		gpio_mii->mdc_gpio.offset = gpio_mii->mdc_num;
+	}
+	gpio_mii->mdc_gpio.flags = 0;
+	snprintf(name, 32, "bb_miiphy_bus-%d-mdc", gpio_mii->index);
+	dm_gpio_request(&gpio_mii->mdc_gpio, name);
+
+	if (gpio_mii->mdio_num > 31) {
+		gpio_mii->mdio_gpio.dev = gpio_dev2;
+		gpio_mii->mdio_gpio.offset = gpio_mii->mdio_num - 32;
+	} else {
+		gpio_mii->mdio_gpio.dev = gpio_dev1;
+		gpio_mii->mdio_gpio.offset = gpio_mii->mdio_num;
+	}
+	gpio_mii->mdio_gpio.flags = 0;
+	snprintf(name, 32, "bb_miiphy_bus-%d-mdio", gpio_mii->index);
+	dm_gpio_request(&gpio_mii->mdio_gpio, name);
+
+	dm_gpio_set_dir_flags(&gpio_mii->mdc_gpio, GPIOD_IS_OUT);
+	dm_gpio_set_value(&gpio_mii->mdc_gpio, 1);
+
+	return 0;
+}
+
+static int mii_mdio_active(struct bb_miiphy_bus *bus)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_value(&gpio_mii->mdc_gpio, gpio_mii->mdio_value);
+
+	return 0;
+}
+
+static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_IN);
+
+	return 0;
+}
+
+static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_OUT);
+	dm_gpio_set_value(&gpio_mii->mdio_gpio, v);
+	gpio_mii->mdio_value = v;
+
+	return 0;
+}
+
+static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_IN);
+	*v = (dm_gpio_get_value(&gpio_mii->mdio_gpio));
+
+	return 0;
+}
+
+static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_value(&gpio_mii->mdc_gpio, v);
+
+	return 0;
+}
+
+static int mii_delay(struct bb_miiphy_bus *bus)
+{
+	udelay(1);
+
+	return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+	{
+		.name = "ihs0",
+		.init = mii_mdio_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &gpio_mii_set[0],
+	},
+	{
+		.name = "ihs1",
+		.init = mii_mdio_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &gpio_mii_set[1],
+	},
+	{
+		.name = "ihs2",
+		.init = mii_mdio_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &gpio_mii_set[2],
+	},
+};
+
+int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
diff --git a/roms/u-boot/board/gdsys/a38x/ihs_phys.h b/roms/u-boot/board/gdsys/a38x/ihs_phys.h
new file mode 100644
index 000000000..c4bec4d46
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/ihs_phys.h
@@ -0,0 +1,2 @@
+uint calculate_octo_phy_mask(void);
+int init_octo_phys(uint octo_phy_mask);
diff --git a/roms/u-boot/board/gdsys/a38x/keyprogram.c b/roms/u-boot/board/gdsys/a38x/keyprogram.c
new file mode 100644
index 000000000..7020fae18
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/keyprogram.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <tpm-v1.h>
+#include <malloc.h>
+#include <linux/ctype.h>
+#include <asm/unaligned.h>
+
+#include "hre.h"
+
+int flush_keys(struct udevice *tpm)
+{
+	u16 key_count;
+	u8 buf[288];
+	u8 *ptr;
+	u32 err;
+	uint i;
+
+	/* fetch list of already loaded keys in the TPM */
+	err = tpm1_get_capability(tpm, TPM_CAP_HANDLE, TPM_RT_KEY, buf,
+				  sizeof(buf));
+	if (err)
+		return -1;
+	key_count = get_unaligned_be16(buf);
+	ptr = buf + 2;
+	for (i = 0; i < key_count; ++i, ptr += 4) {
+		err = tpm1_flush_specific(tpm, get_unaligned_be32(ptr),
+					  TPM_RT_KEY);
+		if (err && err != TPM_KEY_OWNER_CONTROL)
+			return err;
+	}
+
+	return 0;
+}
+
+int decode_hexstr(char *hexstr, u8 **result)
+{
+	int len = strlen(hexstr);
+	int bytes = len / 2;
+	int i;
+	u8 acc = 0;
+
+	if (len % 2 == 1)
+		return 1;
+
+	*result = (u8 *)malloc(bytes);
+
+	for (i = 0; i < len; i++) {
+		char cur = tolower(hexstr[i]);
+		u8 val;
+
+		if ((cur >= 'a' && cur <= 'f') || (cur >= '0' && cur <= '9')) {
+			val = cur - (cur > '9' ? 87 : 48);
+
+			if (i % 2 == 0)
+				acc = 16 * val;
+			else
+				(*result)[i / 2] = acc + val;
+		} else {
+			free(*result);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+int extract_subprogram(u8 **progdata, u32 expected_magic,
+		       struct key_program **result)
+{
+	struct key_program *prog = *result;
+	u32 magic, code_crc, code_size;
+
+	magic = get_unaligned_be32(*progdata);
+	code_crc = get_unaligned_be32(*progdata + 4);
+	code_size = get_unaligned_be32(*progdata + 8);
+
+	*progdata += 12;
+
+	if (magic != expected_magic)
+		return -1;
+
+	*result = malloc(sizeof(struct key_program) + code_size);
+
+	if (!*result)
+		return -1;
+
+	prog->magic = magic;
+	prog->code_crc = code_crc;
+	prog->code_size = code_size;
+	memcpy(prog->code, *progdata, code_size);
+
+	*progdata += code_size;
+
+	if (hre_verify_program(prog)) {
+		free(prog);
+		return -1;
+	}
+
+	return 0;
+}
+
+struct key_program *parse_and_check_keyprog(u8 *progdata)
+{
+	struct key_program *result = NULL, *hmac = NULL;
+
+	/* Part 1: Load key program */
+
+	if (extract_subprogram(&progdata, MAGIC_KEY_PROGRAM, &result))
+		return NULL;
+
+	/* Part 2: Load hmac program */
+
+	if (extract_subprogram(&progdata, MAGIC_HMAC, &hmac))
+		return NULL;
+
+	free(hmac);
+
+	return result;
+}
+
+int load_and_run_keyprog(struct udevice *tpm)
+{
+	char *cmd = NULL;
+	u8 *binprog = NULL;
+	char *hexprog;
+	struct key_program *prog;
+
+	cmd = env_get("loadkeyprogram");
+
+	if (!cmd || run_command(cmd, 0))
+		return 1;
+
+	hexprog = env_get("keyprogram");
+
+	if (decode_hexstr(hexprog, &binprog))
+		return 1;
+
+	prog = parse_and_check_keyprog(binprog);
+	free(binprog);
+
+	if (!prog)
+		return 1;
+
+	if (hre_run_program(tpm, prog->code, prog->code_size)) {
+		free(prog);
+		return 1;
+	}
+
+	printf("\nSD code ran successfully\n");
+
+	free(prog);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/gdsys/a38x/keyprogram.h b/roms/u-boot/board/gdsys/a38x/keyprogram.h
new file mode 100644
index 000000000..06889c67e
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/keyprogram.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef __KEYPROGRAM_H
+#define __KEYPROGRAM_H
+
+int load_and_run_keyprog(struct udevice *tpm);
+int flush_keys(struct udevice *tpm);
+
+#endif /* __KEYPROGRAM_H */
diff --git a/roms/u-boot/board/gdsys/a38x/spl.c b/roms/u-boot/board/gdsys/a38x/spl.c
new file mode 100644
index 000000000..84864d197
--- /dev/null
+++ b/roms/u-boot/board/gdsys/a38x/spl.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/cpu.h>
+
+void spl_board_init(void)
+{
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+	u32 *bootrom_save = (u32 *)CONFIG_SPL_BOOTROM_SAVE;
+	u32 *regs = (u32 *)(*bootrom_save);
+
+	printf("Returning to BootROM (return address %08x)...\n", regs[13]);
+	return_to_bootrom();
+#endif
+}
diff --git a/roms/u-boot/board/gdsys/common/Makefile b/roms/u-boot/board/gdsys/common/Makefile
new file mode 100644
index 000000000..dd6d5e69d
--- /dev/null
+++ b/roms/u-boot/board/gdsys/common/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+
+obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
+obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
+obj-$(CONFIG_CONTROLCENTERD) += dp501.o
+obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o
+
+ifdef CONFIG_OSD
+obj-$(CONFIG_GDSYS_LEGACY_OSD_CMDS) += osd_cmd.o
+endif
diff --git a/roms/u-boot/board/gdsys/common/cmd_ioloop.c b/roms/u-boot/board/gdsys/common/cmd_ioloop.c
new file mode 100644
index 000000000..658756d98
--- /dev/null
+++ b/roms/u-boot/board/gdsys/common/cmd_ioloop.c
@@ -0,0 +1,585 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+#include <gdsys_fpga.h>
+
+#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
+#include <dm.h>
+#include <misc.h>
+#include <regmap.h>
+#include <sysinfo.h>
+
+#include "../../../drivers/misc/gdsys_soc.h"
+#include "../../../drivers/misc/gdsys_ioep.h"
+#include "../../../drivers/misc/ihs_fpga.h"
+
+const int HEADER_WORDS = sizeof(struct io_generic_packet) / 2;
+#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
+
+enum status_print_type {
+	STATUS_LOUD = 0,
+	STATUS_SILENT = 1,
+};
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+enum {
+	STATE_TX_PACKET_BUILDING = BIT(0),
+	STATE_TX_TRANSMITTING = BIT(1),
+	STATE_TX_BUFFER_FULL = BIT(2),
+	STATE_TX_ERR = BIT(3),
+	STATE_RECEIVE_TIMEOUT = BIT(4),
+	STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
+	STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
+	STATE_RX_DIST_ERR = BIT(7),
+	STATE_RX_LENGTH_ERR = BIT(8),
+	STATE_RX_FRAME_CTR_ERR = BIT(9),
+	STATE_RX_FCS_ERR = BIT(10),
+	STATE_RX_PACKET_DROPPED = BIT(11),
+	STATE_RX_DATA_LAST = BIT(12),
+	STATE_RX_DATA_FIRST = BIT(13),
+	STATE_RX_DATA_AVAILABLE = BIT(15),
+};
+
+enum {
+	IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
+	IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
+	IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
+	IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
+};
+
+enum {
+	CTRL_PROC_RECEIVE_ENABLE = BIT(12),
+	CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
+};
+
+struct io_generic_packet {
+	u16 target_address;
+	u16 source_address;
+	u8 packet_type;
+	u8 bc;
+	u16 packet_length;
+} __attribute__((__packed__));
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+unsigned long long rx_ctr;
+unsigned long long tx_ctr;
+unsigned long long err_ctr;
+#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
+struct udevice *dev;
+#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+static void io_check_status(uint fpga, u16 status, enum status_print_type type)
+{
+	u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
+		   STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
+		   STATE_RX_PACKET_DROPPED | STATE_TX_ERR;
+
+	if (!(status & mask)) {
+		FPGA_SET_REG(fpga, ep.rx_tx_status, status);
+		return;
+	}
+
+	err_ctr++;
+	FPGA_SET_REG(fpga, ep.rx_tx_status, status);
+
+	if (type == STATUS_SILENT)
+		return;
+
+	if (status & STATE_RX_PACKET_DROPPED)
+		printf("RX_PACKET_DROPPED, status %04x\n", status);
+
+	if (status & STATE_RX_DIST_ERR)
+		printf("RX_DIST_ERR\n");
+	if (status & STATE_RX_LENGTH_ERR)
+		printf("RX_LENGTH_ERR\n");
+	if (status & STATE_RX_FRAME_CTR_ERR)
+		printf("RX_FRAME_CTR_ERR\n");
+	if (status & STATE_RX_FCS_ERR)
+		printf("RX_FCS_ERR\n");
+
+	if (status & STATE_TX_ERR)
+		printf("TX_ERR\n");
+}
+#else
+static void io_check_status(struct udevice *dev, enum status_print_type type)
+{
+	u16 status = 0;
+	int ret;
+
+	ret = misc_call(dev, 0, NULL, 0, &status, 0);
+	if (!ret)
+		return;
+
+	err_ctr++;
+
+	if (type != STATUS_LOUD)
+		return;
+
+	if (status & STATE_RX_PACKET_DROPPED)
+		printf("RX_PACKET_DROPPED, status %04x\n", status);
+
+	if (status & STATE_RX_DIST_ERR)
+		printf("RX_DIST_ERR\n");
+	if (status & STATE_RX_LENGTH_ERR)
+		printf("RX_LENGTH_ERR\n");
+	if (status & STATE_RX_FRAME_CTR_ERR)
+		printf("RX_FRAME_CTR_ERR\n");
+	if (status & STATE_RX_FCS_ERR)
+		printf("RX_FCS_ERR\n");
+
+	if (status & STATE_TX_ERR)
+		printf("TX_ERR\n");
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+static void io_send(uint fpga, uint size)
+{
+	uint k;
+	struct io_generic_packet packet = {
+		.source_address = 1,
+		.packet_type = 1,
+		.packet_length = size,
+	};
+	u16 *p = (u16 *)&packet;
+
+	for (k = 0; k < sizeof(packet) / 2; ++k)
+		FPGA_SET_REG(fpga, ep.transmit_data, *p++);
+
+	for (k = 0; k < (size + 1) / 2; ++k)
+		FPGA_SET_REG(fpga, ep.transmit_data, k);
+
+	FPGA_SET_REG(fpga, ep.rx_tx_control,
+		     CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
+
+	tx_ctr++;
+}
+#else
+static void io_send(struct udevice *dev, uint size)
+{
+	uint k;
+	u16 buffer[HEADER_WORDS + 128];
+	struct io_generic_packet header = {
+		.source_address = 1,
+		.packet_type = 1,
+		.packet_length = size,
+	};
+	const uint words = (size + 1) / 2;
+
+	memcpy(buffer, &header, 2 * HEADER_WORDS);
+	for (k = 0; k < words; ++k)
+		buffer[k + HEADER_WORDS] = (2 * k + 1) + ((2 * k) << 8);
+
+	misc_write(dev, 0, buffer, HEADER_WORDS + words);
+
+	tx_ctr++;
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+static void io_receive(uint fpga)
+{
+	u16 rx_tx_status;
+
+	FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+	while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
+		u16 rx;
+
+		if (rx_tx_status & STATE_RX_DATA_LAST)
+			rx_ctr++;
+
+		FPGA_GET_REG(fpga, ep.receive_data, &rx);
+
+		FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+	}
+}
+#else
+static void io_receive(struct udevice *dev)
+{
+	u16 buffer[HEADER_WORDS + 128];
+
+	if (!misc_read(dev, 0, buffer, 0))
+		rx_ctr++;
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+static void io_reflect(uint fpga)
+{
+	u16 buffer[128];
+
+	uint k = 0;
+	uint n;
+	u16 rx_tx_status;
+
+	FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+	while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
+		FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]);
+		if (rx_tx_status & STATE_RX_DATA_LAST)
+			break;
+
+		FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+	}
+
+	if (!k)
+		return;
+
+	for (n = 0; n < k; ++n)
+		FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]);
+
+	FPGA_SET_REG(fpga, ep.rx_tx_control,
+		     CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
+
+	tx_ctr++;
+}
+#else
+static void io_reflect(struct udevice *dev)
+{
+	u16 buffer[HEADER_WORDS + 128];
+	struct io_generic_packet *header;
+
+	if (misc_read(dev, 0, buffer, 0))
+		return;
+
+	header = (struct io_generic_packet *)&buffer;
+
+	misc_write(dev, 0, buffer, HEADER_WORDS + header->packet_length);
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+/*
+ * FPGA io-endpoint reflector
+ *
+ * Syntax:
+ *	ioreflect {fpga} {reportrate}
+ */
+int do_ioreflect(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	uint fpga;
+	uint rate = 0;
+	unsigned long long last_seen = 0;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	fpga = simple_strtoul(argv[1], NULL, 10);
+
+	/*
+	 * If another parameter, it is the report rate in packets.
+	 */
+	if (argc > 2)
+		rate = simple_strtoul(argv[2], NULL, 10);
+
+	/* Enable receive path */
+	FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
+
+	/* Set device address to dummy 1*/
+	FPGA_SET_REG(fpga, ep.device_address, 1);
+
+	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+	while (1) {
+		u16 top_int;
+		u16 rx_tx_status;
+
+		FPGA_GET_REG(fpga, top_interrupt, &top_int);
+		FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+		io_check_status(fpga, rx_tx_status, STATUS_SILENT);
+		if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
+		    (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
+			io_reflect(fpga);
+
+		if (rate) {
+			if (!(tx_ctr % rate) && (tx_ctr != last_seen))
+				printf("refl %llu, err %llu\n", tx_ctr,
+				       err_ctr);
+			last_seen = tx_ctr;
+		}
+
+		if (ctrlc())
+			break;
+	}
+
+	return 0;
+}
+#else
+/*
+ * FPGA io-endpoint reflector
+ *
+ * Syntax:
+ *	ioreflect {reportrate}
+ */
+int do_ioreflect(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	struct udevice *fpga;
+	struct regmap *map;
+	uint rate = 0;
+	unsigned long long last_seen = 0;
+
+	if (!dev) {
+		printf("No device selected\n");
+		return 1;
+	}
+
+	gdsys_soc_get_fpga(dev, &fpga);
+	regmap_init_mem(dev_ofnode(dev), &map);
+
+	/* Enable receive path */
+	misc_set_enabled(dev, true);
+
+	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+	while (1) {
+		uint top_int;
+
+		ihs_fpga_get(map, top_interrupt, &top_int);
+		io_check_status(dev, STATUS_SILENT);
+		if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
+		    (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
+			io_reflect(dev);
+
+		if (rate) {
+			if (!(tx_ctr % rate) && (tx_ctr != last_seen))
+				printf("refl %llu, err %llu\n", tx_ctr,
+				       err_ctr);
+			last_seen = tx_ctr;
+		}
+
+		if (ctrlc())
+			break;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#define DISP_LINE_LEN	16
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+/*
+ * FPGA io-endpoint looptest
+ *
+ * Syntax:
+ *	ioloop {fpga} {size} {rate}
+ */
+int do_ioloop(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	uint fpga;
+	uint size;
+	uint rate = 0;
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	/*
+	 * FPGA is specified since argc > 2
+	 */
+	fpga = simple_strtoul(argv[1], NULL, 10);
+
+	/*
+	 * packet size is specified since argc > 2
+	 */
+	size = simple_strtoul(argv[2], NULL, 10);
+
+	/*
+	 * If another parameter, it is the test rate in packets per second.
+	 */
+	if (argc > 3)
+		rate = simple_strtoul(argv[3], NULL, 10);
+
+	/* enable receive path */
+	FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
+
+	/* set device address to dummy 1*/
+	FPGA_SET_REG(fpga, ep.device_address, 1);
+
+	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+	while (1) {
+		u16 top_int;
+		u16 rx_tx_status;
+
+		FPGA_GET_REG(fpga, top_interrupt, &top_int);
+		FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+		io_check_status(fpga, rx_tx_status, STATUS_LOUD);
+		if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
+			io_send(fpga, size);
+		if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
+			io_receive(fpga);
+
+		if (rate) {
+			if (ctrlc())
+				break;
+			udelay(1000000 / rate);
+			if (!(tx_ctr % rate))
+				printf("d %llu, tx %llu, rx %llu, err %llu\n",
+				       tx_ctr - rx_ctr, tx_ctr, rx_ctr,
+				       err_ctr);
+		}
+	}
+
+	return 0;
+}
+#else
+/*
+ * FPGA io-endpoint looptest
+ *
+ * Syntax:
+ *	ioloop {size} {rate}
+ */
+int do_ioloop(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	uint size;
+	uint rate = 0;
+	struct udevice *fpga;
+	struct regmap *map;
+
+	if (!dev) {
+		printf("No device selected\n");
+		return 1;
+	}
+
+	gdsys_soc_get_fpga(dev, &fpga);
+	regmap_init_mem(dev_ofnode(dev), &map);
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	/*
+	 * packet size is specified since argc > 1
+	 */
+	size = simple_strtoul(argv[2], NULL, 10);
+
+	/*
+	 * If another parameter, it is the test rate in packets per second.
+	 */
+	if (argc > 2)
+		rate = simple_strtoul(argv[3], NULL, 10);
+
+	/* Enable receive path */
+	misc_set_enabled(dev, true);
+
+	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+	while (1) {
+		uint top_int;
+
+		if (ctrlc())
+			break;
+
+		ihs_fpga_get(map, top_interrupt, &top_int);
+
+		io_check_status(dev, STATUS_LOUD);
+		if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
+			io_send(dev, size);
+		if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
+			io_receive(dev);
+
+		if (rate) {
+			udelay(1000000 / rate);
+			if (!(tx_ctr % rate))
+				printf("d %llu, tx %llu, rx %llu, err %llu\n",
+				       tx_ctr - rx_ctr, tx_ctr, rx_ctr,
+				       err_ctr);
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
+int do_iodev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	struct udevice *ioep = NULL;
+	struct udevice *sysinfo;
+	char name[8];
+	int ret;
+
+	if (sysinfo_get(&sysinfo))
+		return CMD_RET_FAILURE;
+
+	if (argc > 1) {
+		int i = simple_strtoul(argv[1], NULL, 10);
+
+		snprintf(name, sizeof(name), "ioep%d", i);
+
+		ret = uclass_get_device_by_phandle(UCLASS_MISC, sysinfo, name,
+						   &ioep);
+
+		if (ret || !ioep) {
+			printf("Invalid IOEP %d\n", i);
+			return CMD_RET_FAILURE;
+		}
+
+		dev = ioep;
+	} else {
+		int i = 0;
+
+		while (1) {
+			snprintf(name, sizeof(name), "ioep%d", i);
+
+			ret = uclass_get_device_by_phandle(UCLASS_MISC, sysinfo,
+							   name, &ioep);
+
+			if (ret || !ioep)
+				break;
+
+			printf("IOEP %d:\t%s\n", i++, ioep->name);
+		}
+
+		if (dev)
+			printf("\nSelected IOEP: %s\n", dev->name);
+		else
+			puts("\nNo IOEP selected.\n");
+	}
+
+	return 0;
+}
+#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+U_BOOT_CMD(
+	ioloop,	4,	0,	do_ioloop,
+	"fpga io-endpoint looptest",
+	"fpga packetsize [packets/sec]"
+);
+
+U_BOOT_CMD(
+	ioreflect, 3,	0,	do_ioreflect,
+	"fpga io-endpoint reflector",
+	"fpga reportrate"
+);
+#else
+U_BOOT_CMD(
+	ioloop,	3,	0,	do_ioloop,
+	"fpga io-endpoint looptest",
+	"packetsize [packets/sec]"
+);
+
+U_BOOT_CMD(
+	ioreflect, 2,	0,	do_ioreflect,
+	"fpga io-endpoint reflector",
+	"reportrate"
+);
+
+U_BOOT_CMD(
+	iodev, 2,	0,	do_iodev,
+	"fpga io-endpoint listing/selection",
+	"[ioep device to select]"
+);
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/roms/u-boot/board/gdsys/common/dp501.c b/roms/u-boot/board/gdsys/common/dp501.c
new file mode 100644
index 000000000..9ca69ebcb
--- /dev/null
+++ b/roms/u-boot/board/gdsys/common/dp501.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+
+#define DP501_I2C_ADDR 0x08
+
+#ifdef CONFIG_SYS_DP501_I2C
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
+#endif
+
+#ifdef CONFIG_SYS_DP501_BASE
+int dp501_base[] = CONFIG_SYS_DP501_BASE;
+#endif
+
+static void dp501_setbits(u8 addr, u8 reg, u8 mask)
+{
+	u8 val;
+
+	val = i2c_reg_read(addr, reg);
+	setbits_8(&val, mask);
+	i2c_reg_write(addr, reg, val);
+}
+
+static void dp501_clrbits(u8 addr, u8 reg, u8 mask)
+{
+	u8 val;
+
+	val = i2c_reg_read(addr, reg);
+	clrbits_8(&val, mask);
+	i2c_reg_write(addr, reg, val);
+}
+
+static int dp501_detect_cable_adapter(u8 addr)
+{
+	u8 val = i2c_reg_read(addr, 0x00);
+
+	return !(val & 0x04);
+}
+
+static void dp501_link_training(u8 addr)
+{
+	u8 val;
+	u8 link_bw;
+	u8 max_lane_cnt;
+	u8 lane_cnt;
+
+	val = i2c_reg_read(addr, 0x51);
+	if (val >= 0x0a)
+		link_bw = 0x0a;
+	else
+		link_bw = 0x06;
+	if (link_bw != val)
+		printf("DP sink supports %d Mbps link rate, set to %d Mbps\n",
+		       val * 270, link_bw * 270);
+	i2c_reg_write(addr, 0x5d, link_bw); /* set link_bw */
+	val = i2c_reg_read(addr, 0x52);
+	max_lane_cnt = val & 0x1f;
+	if (max_lane_cnt >= 4)
+		lane_cnt = 4;
+	else
+		lane_cnt = max_lane_cnt;
+	if (lane_cnt != max_lane_cnt)
+		printf("DP sink supports %d lanes, set to %d lanes\n",
+		       max_lane_cnt, lane_cnt);
+	i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */
+	val = i2c_reg_read(addr, 0x53);
+	i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */
+
+	i2c_reg_write(addr, 0x5f, 0x0d); /* start training */
+}
+
+void dp501_powerup(u8 addr)
+{
+	dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
+	dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
+	i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
+	dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
+	dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
+	i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
+	dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
+	dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
+	dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */
+
+#ifdef CONFIG_SYS_DP501_VCAPCTRL0
+	i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
+#else
+	i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
+#endif
+
+#ifdef CONFIG_SYS_DP501_DIFFERENTIAL
+	i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */
+	i2c_reg_write(addr + 2, 0x25, 0x04);
+	i2c_reg_write(addr + 2, 0x26, 0x10);
+#else
+	i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
+#endif
+
+	i2c_reg_write(addr + 2, 0x1a, 0x04); /* SPDIF input method TTL */
+
+	i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
+	i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
+	i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
+	i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
+	i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
+	i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
+	dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
+	i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
+	i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
+	i2c_reg_write(addr, 0x87, 0x7f); /* set retry counter as 7
+					    retry interval 400us */
+
+	if (dp501_detect_cable_adapter(addr)) {
+		printf("DVI/HDMI cable adapter detected\n");
+		i2c_reg_write(addr, 0x5e, 0x04); /* enable 4 channel */
+		dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
+	} else {
+		printf("no DVI/HDMI cable adapter detected\n");
+		dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
+
+		dp501_link_training(addr);
+	}
+}
+
+void dp501_powerdown(u8 addr)
+{
+	dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
+}
+
+
+int dp501_probe(unsigned screen, bool power)
+{
+#ifdef CONFIG_SYS_DP501_BASE
+	uint8_t dp501_addr = dp501_base[screen];
+#else
+	uint8_t dp501_addr = DP501_I2C_ADDR;
+#endif
+
+#ifdef CONFIG_SYS_DP501_I2C
+	i2c_set_bus_num(dp501_i2c[screen]);
+#endif
+
+	if (i2c_probe(dp501_addr))
+		return -1;
+
+	dp501_powerup(dp501_addr);
+
+	return 0;
+}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/roms/u-boot/board/gdsys/common/dp501.h b/roms/u-boot/board/gdsys/common/dp501.h
new file mode 100644
index 000000000..b98b54edc
--- /dev/null
+++ b/roms/u-boot/board/gdsys/common/dp501.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DP501_H_
+#define _DP501_H_
+
+void dp501_powerup(u8 addr);
+void dp501_powerdown(u8 addr);
+int dp501_probe(unsigned screen, bool power);
+
+#endif
diff --git a/roms/u-boot/board/gdsys/common/fpga.c b/roms/u-boot/board/gdsys/common/fpga.c
new file mode 100644
index 000000000..5ba6613ed
--- /dev/null
+++ b/roms/u-boot/board/gdsys/common/fpga.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
+#include <common.h>
+#include <gdsys_fpga.h>
+
+#include <asm/io.h>
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+	out_le16(reg, data);
+
+	return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+	*data = in_le16(reg);
+
+	return 0;
+}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/roms/u-boot/board/gdsys/common/ihs_mdio.c b/roms/u-boot/board/gdsys/common/ihs_mdio.c
new file mode 100644
index 000000000..5f1215e9e
--- /dev/null
+++ b/roms/u-boot/board/gdsys/common/ihs_mdio.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#include <common.h>
+#include <linux/delay.h>
+
+#include <miiphy.h>
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+#include <gdsys_fpga.h>
+#else
+#include <fdtdec.h>
+#include <dm.h>
+#include <regmap.h>
+#endif
+
+#include "ihs_mdio.h"
+
+#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
+enum {
+	REG_MDIO_CONTROL = 0x0,
+	REG_MDIO_ADDR_DATA = 0x2,
+	REG_MDIO_RX_DATA = 0x4,
+};
+
+static inline u16 read_reg(struct udevice *fpga, uint base, uint addr)
+{
+	struct regmap *map;
+	u8 *ptr;
+
+	regmap_init_mem(dev_ofnode(fpga), &map);
+	ptr = regmap_get_range(map, 0);
+
+	return in_le16((u16 *)(ptr + base + addr));
+}
+
+static inline void write_reg(struct udevice *fpga, uint base, uint addr,
+			     u16 val)
+{
+	struct regmap *map;
+	u8 *ptr;
+
+	regmap_init_mem(dev_ofnode(fpga), &map);
+	ptr = regmap_get_range(map, 0);
+
+	out_le16((u16 *)(ptr + base + addr), val);
+}
+#endif
+
+static inline u16 read_control(struct ihs_mdio_info *info)
+{
+	u16 val;
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+	FPGA_GET_REG(info->fpga, mdio.control, &val);
+#else
+	val = read_reg(info->fpga, info->base, REG_MDIO_CONTROL);
+#endif
+	return val;
+}
+
+static inline void write_control(struct ihs_mdio_info *info, u16 val)
+{
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+	FPGA_SET_REG(info->fpga, mdio.control, val);
+#else
+	write_reg(info->fpga, info->base, REG_MDIO_CONTROL, val);
+#endif
+}
+
+static inline void write_addr_data(struct ihs_mdio_info *info, u16 val)
+{
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+	FPGA_SET_REG(info->fpga, mdio.address_data, val);
+#else
+	write_reg(info->fpga, info->base, REG_MDIO_ADDR_DATA, val);
+#endif
+}
+
+static inline u16 read_rx_data(struct ihs_mdio_info *info)
+{
+	u16 val;
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+	FPGA_GET_REG(info->fpga, mdio.rx_data, &val);
+#else
+	val = read_reg(info->fpga, info->base, REG_MDIO_RX_DATA);
+#endif
+	return val;
+}
+
+static int ihs_mdio_idle(struct mii_dev *bus)
+{
+	struct ihs_mdio_info *info = bus->priv;
+	u16 val;
+	unsigned int ctr = 0;
+
+	do {
+		val = read_control(info);
+		udelay(100);
+		if (ctr++ > 10)
+			return -1;
+	} while (!(val & (1 << 12)));
+
+	return 0;
+}
+
+static int ihs_mdio_reset(struct mii_dev *bus)
+{
+	ihs_mdio_idle(bus);
+
+	return 0;
+}
+
+static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr,
+			 int regnum)
+{
+	struct ihs_mdio_info *info = bus->priv;
+	u16 val;
+
+	ihs_mdio_idle(bus);
+
+	write_control(info,
+		      ((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10));
+
+	/* wait for rx data available */
+	udelay(100);
+
+	val = read_rx_data(info);
+
+	return val;
+}
+
+static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
+			  int regnum, u16 value)
+{
+	struct ihs_mdio_info *info = bus->priv;
+
+	ihs_mdio_idle(bus);
+
+	write_addr_data(info, value);
+	write_control(info, ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10));
+
+	return 0;
+}
+
+int ihs_mdio_init(struct ihs_mdio_info *info)
+{
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate FSL MDIO bus\n");
+		return -1;
+	}
+
+	bus->read = ihs_mdio_read;
+	bus->write = ihs_mdio_write;
+	bus->reset = ihs_mdio_reset;
+	strcpy(bus->name, info->name);
+
+	bus->priv = info;
+
+	return mdio_register(bus);
+}
diff --git a/roms/u-boot/board/gdsys/common/ihs_mdio.h b/roms/u-boot/board/gdsys/common/ihs_mdio.h
new file mode 100644
index 000000000..d0a4b0d7a
--- /dev/null
+++ b/roms/u-boot/board/gdsys/common/ihs_mdio.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#ifndef _IHS_MDIO_H_
+#define _IHS_MDIO_H_
+
+struct ihs_mdio_info {
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+	u32 fpga;
+#else
+	struct udevice *fpga;
+	int base;
+#endif
+	char *name;
+};
+
+int ihs_mdio_init(struct ihs_mdio_info *info);
+
+#endif
diff --git a/roms/u-boot/board/gdsys/common/ioep-fpga.c b/roms/u-boot/board/gdsys/common/ioep-fpga.c
new file mode 100644
index 000000000..7292d7ab5
--- /dev/null
+++ b/roms/u-boot/board/gdsys/common/ioep-fpga.c
@@ -0,0 +1,591 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
+#include <common.h>
+
+#include <gdsys_fpga.h>
+#include <linux/bitops.h>
+
+enum pcb_video_type {
+	PCB_DVI_SL,
+	PCB_DP_165MPIX,
+	PCB_DP_300MPIX,
+	PCB_HDMI,
+	PCB_DP_1_2,
+	PCB_HDMI_2_0,
+};
+
+enum pcb_transmission_type {
+	PCB_CAT_1G,
+	PCB_FIBER_3G,
+	PCB_CAT_10G,
+	PCB_FIBER_10G,
+};
+
+enum carrier_speed {
+	CARRIER_SPEED_1G,
+	CARRIER_SPEED_3G,
+	CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
+	CARRIER_SPEED_10G,
+};
+
+enum ram_config {
+	RAM_DDR2_32BIT_295MBPS,
+	RAM_DDR3_32BIT_590MBPS,
+	RAM_DDR3_48BIT_590MBPS,
+	RAM_DDR3_64BIT_1800MBPS,
+	RAM_DDR3_48BIT_1800MBPS,
+};
+
+enum sysclock {
+	SYSCLK_147456,
+};
+
+struct fpga_versions {
+	bool video_channel;
+	bool con_side;
+	enum pcb_video_type pcb_video_type;
+	enum pcb_transmission_type pcb_transmission_type;
+	unsigned int hw_version;
+};
+
+struct fpga_features {
+	u8 video_channels;
+	u8 carriers;
+	enum carrier_speed carrier_speed;
+	enum ram_config ram_config;
+	enum sysclock sysclock;
+
+	bool pcm_tx;
+	bool pcm_rx;
+	bool spdif_tx;
+	bool spdif_rx;
+	bool usb2;
+	bool rs232;
+	bool compression_type1;
+	bool compression_type2;
+	bool compression_type3;
+	bool interlace;
+	bool osd;
+	bool compression_pipes;
+};
+
+#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
+
+static int get_versions(unsigned int fpga, struct fpga_versions *versions)
+{
+	enum {
+		VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
+		VERSIONS_FPGA_CON_SIDE = BIT(13),
+		VERSIONS_FPGA_SC = BIT(14),
+		VERSIONS_PCB_CON = BIT(9),
+		VERSIONS_PCB_SC = BIT(8),
+		VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
+		VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
+		VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
+		VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
+		VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
+		VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
+		VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
+		VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
+		VERSIONS_HW_VER_MASK = 0xf << 0,
+	};
+	u16 raw_versions;
+
+	memset(versions, 0, sizeof(struct fpga_versions));
+
+	FPGA_GET_REG(fpga, versions, &raw_versions);
+
+	versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
+	versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
+
+	switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
+	case VERSIONS_PCB_VIDEO_DP_1_2:
+		versions->pcb_video_type = PCB_DP_1_2;
+		break;
+
+	case VERSIONS_PCB_VIDEO_HDMI_2_0:
+		versions->pcb_video_type = PCB_HDMI_2_0;
+		break;
+	}
+
+	switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
+	case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
+		versions->pcb_transmission_type = PCB_FIBER_10G;
+		break;
+
+	case VERSIONS_PCB_TRANSMISSION_CAT_10G:
+		versions->pcb_transmission_type = PCB_CAT_10G;
+		break;
+
+	case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
+		versions->pcb_transmission_type = PCB_FIBER_3G;
+		break;
+
+	case VERSIONS_PCB_TRANSMISSION_CAT_1G:
+		versions->pcb_transmission_type = PCB_CAT_1G;
+		break;
+
+	}
+
+	versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
+
+	return 0;
+}
+
+static int get_features(unsigned int fpga, struct fpga_features *features)
+{
+	enum {
+		FEATURE_SPDIF_RX = BIT(15),
+		FEATURE_SPDIF_TX = BIT(14),
+		FEATURE_PCM_RX = BIT(13),
+		FEATURE_PCM_TX = BIT(12),
+		FEATURE_RAM_MASK = GENMASK(11, 8),
+		FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
+		FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
+		FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
+		FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
+		FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
+		FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
+		FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
+		FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
+		FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
+		FEATURE_CARRIERS_MASK = GENMASK(5, 4),
+		FEATURE_CARRIERS_0 = 0x0 << 4,
+		FEATURE_CARRIERS_1 = 0x1 << 4,
+		FEATURE_CARRIERS_2 = 0x2 << 4,
+		FEATURE_CARRIERS_4 = 0x3 << 4,
+		FEATURE_USB2 = BIT(3),
+		FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
+		FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
+		FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
+		FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
+		FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
+	};
+
+	enum {
+		EXT_FEATURE_OSD = BIT(15),
+		EXT_FEATURE_ETHERNET = BIT(9),
+		EXT_FEATURE_INTERLACE = BIT(8),
+		EXT_FEATURE_RS232 = BIT(7),
+		EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
+		EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
+		EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
+		EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
+		EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
+		EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
+		EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
+	};
+
+	u16 raw_features;
+	u16 raw_extended_features;
+
+	memset(features, 0, sizeof(struct fpga_features));
+
+	FPGA_GET_REG(fpga, fpga_features, &raw_features);
+	FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
+
+	switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
+	case FEATURE_VIDEOCHANNELS_0:
+		features->video_channels = 0;
+		break;
+
+	case FEATURE_VIDEOCHANNELS_1:
+		features->video_channels = 1;
+		break;
+
+	case FEATURE_VIDEOCHANNELS_1_1:
+	case FEATURE_VIDEOCHANNELS_2:
+		features->video_channels = 2;
+		break;
+	};
+
+	switch (raw_features & FEATURE_CARRIERS_MASK) {
+	case FEATURE_CARRIERS_0:
+		features->carriers = 0;
+		break;
+
+	case FEATURE_CARRIERS_1:
+		features->carriers = 1;
+		break;
+
+	case FEATURE_CARRIERS_2:
+		features->carriers = 2;
+		break;
+
+	case FEATURE_CARRIERS_4:
+		features->carriers = 4;
+		break;
+	}
+
+	switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
+	case FEATURE_CARRIER_SPEED_1G:
+		features->carrier_speed = CARRIER_SPEED_1G;
+		break;
+	case FEATURE_CARRIER_SPEED_2_5G:
+		features->carrier_speed = CARRIER_SPEED_2_5G;
+		break;
+	case FEATURE_CARRIER_SPEED_10G:
+		features->carrier_speed = CARRIER_SPEED_10G;
+		break;
+	}
+
+	switch (raw_features & FEATURE_RAM_MASK) {
+	case FEATURE_RAM_DDR2_32BIT_295MBPS:
+		features->ram_config = RAM_DDR2_32BIT_295MBPS;
+		break;
+
+	case FEATURE_RAM_DDR3_32BIT_590MBPS:
+		features->ram_config = RAM_DDR3_32BIT_590MBPS;
+		break;
+
+	case FEATURE_RAM_DDR3_48BIT_590MBPS:
+		features->ram_config = RAM_DDR3_48BIT_590MBPS;
+		break;
+
+	case FEATURE_RAM_DDR3_64BIT_1800MBPS:
+		features->ram_config = RAM_DDR3_64BIT_1800MBPS;
+		break;
+
+	case FEATURE_RAM_DDR3_48BIT_1800MBPS:
+		features->ram_config = RAM_DDR3_48BIT_1800MBPS;
+		break;
+	}
+
+	features->pcm_tx = raw_features & FEATURE_PCM_TX;
+	features->pcm_rx = raw_features & FEATURE_PCM_RX;
+	features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
+	features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
+	features->usb2 = raw_features & FEATURE_USB2;
+	features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
+	features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1;
+	features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2;
+	features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3;
+	features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
+	features->osd = raw_extended_features & EXT_FEATURE_OSD;
+	features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK;
+
+	return 0;
+}
+
+#else
+
+static int get_versions(unsigned int fpga, struct fpga_versions *versions)
+{
+	enum {
+		/* HW version encoding is a mess, leave it for the moment */
+		VERSIONS_HW_VER_MASK = 0xf << 0,
+		VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
+		VERSIONS_SFP = BIT(5),
+		VERSIONS_VIDEO_MASK = 0x7 << 6,
+		VERSIONS_VIDEO_DVI = 0x0 << 6,
+		VERSIONS_VIDEO_DP_165 = 0x1 << 6,
+		VERSIONS_VIDEO_DP_300 = 0x2 << 6,
+		VERSIONS_VIDEO_HDMI = 0x3 << 6,
+		VERSIONS_UT_MASK = 0xf << 12,
+		VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
+		VERSIONS_UT_MAIN_USER = 0x1 << 12,
+		VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
+		VERSIONS_UT_VIDEO_USER = 0x3 << 12,
+	};
+	u16 raw_versions;
+
+	memset(versions, 0, sizeof(struct fpga_versions));
+
+	FPGA_GET_REG(fpga, versions, &raw_versions);
+
+	switch (raw_versions & VERSIONS_UT_MASK) {
+	case VERSIONS_UT_MAIN_SERVER:
+		versions->video_channel = false;
+		versions->con_side = false;
+		break;
+
+	case VERSIONS_UT_MAIN_USER:
+		versions->video_channel = false;
+		versions->con_side = true;
+		break;
+
+	case VERSIONS_UT_VIDEO_SERVER:
+		versions->video_channel = true;
+		versions->con_side = false;
+		break;
+
+	case VERSIONS_UT_VIDEO_USER:
+		versions->video_channel = true;
+		versions->con_side = true;
+		break;
+
+	}
+
+	switch (raw_versions & VERSIONS_VIDEO_MASK) {
+	case VERSIONS_VIDEO_DVI:
+		versions->pcb_video_type = PCB_DVI_SL;
+		break;
+
+	case VERSIONS_VIDEO_DP_165:
+		versions->pcb_video_type = PCB_DP_165MPIX;
+		break;
+
+	case VERSIONS_VIDEO_DP_300:
+		versions->pcb_video_type = PCB_DP_300MPIX;
+		break;
+
+	case VERSIONS_VIDEO_HDMI:
+		versions->pcb_video_type = PCB_HDMI;
+		break;
+	}
+
+	versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
+
+	if (raw_versions & VERSIONS_SFP)
+		versions->pcb_transmission_type = PCB_FIBER_3G;
+	else
+		versions->pcb_transmission_type = PCB_CAT_1G;
+
+	return 0;
+}
+
+static int get_features(unsigned int fpga, struct fpga_features *features)
+{
+	enum {
+		FEATURE_CARRIER_SPEED_2_5 = BIT(4),
+		FEATURE_RAM_MASK = 0x7 << 5,
+		FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
+		FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
+		FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
+		FEATURE_PCM_AUDIO_TX = BIT(9),
+		FEATURE_PCM_AUDIO_RX = BIT(10),
+		FEATURE_OSD = BIT(11),
+		FEATURE_USB20 = BIT(12),
+		FEATURE_COMPRESSION_MASK = 7 << 13,
+		FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
+		FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
+		FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
+	};
+
+	enum {
+		EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
+		EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
+		EXTENDED_FEATURE_RS232 = BIT(2),
+		EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
+		EXTENDED_FEATURE_INTERLACE = BIT(4),
+	};
+
+	u16 raw_features;
+#ifdef GDSYS_LEGACY_DRIVERS
+	u16 raw_extended_features;
+#endif
+
+	memset(features, 0, sizeof(struct fpga_features));
+
+	FPGA_GET_REG(fpga, fpga_features, &raw_features);
+#ifdef GDSYS_LEGACY_DRIVERS
+	FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
+#endif
+
+	features->video_channels = raw_features & 0x3;
+	features->carriers = (raw_features >> 2) & 0x3;
+
+	features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
+		? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
+
+	switch (raw_features & FEATURE_RAM_MASK) {
+	case FEATURE_RAM_DDR2_32BIT:
+		features->ram_config = RAM_DDR2_32BIT_295MBPS;
+		break;
+
+	case FEATURE_RAM_DDR3_32BIT:
+		features->ram_config = RAM_DDR3_32BIT_590MBPS;
+		break;
+
+	case FEATURE_RAM_DDR3_48BIT:
+		features->ram_config = RAM_DDR3_48BIT_590MBPS;
+		break;
+	}
+
+	features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
+	features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
+#ifdef GDSYS_LEGACY_DRIVERS
+	features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX;
+	features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX;
+#endif
+
+	features->usb2 = raw_features & FEATURE_USB20;
+#ifdef GDSYS_LEGACY_DRIVERS
+	features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
+#endif
+
+	features->compression_type1 = false;
+	features->compression_type2 = false;
+	features->compression_type3 = false;
+	switch (raw_features & FEATURE_COMPRESSION_MASK) {
+	case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
+		features->compression_type3 = true;
+	case FEATURE_COMPRESSION_TYPE1_TYPE2:
+		features->compression_type2 = true;
+	case FEATURE_COMPRESSION_TYPE1:
+		features->compression_type1 = true;
+		break;
+	}
+
+#ifdef GDSYS_LEGACY_DRIVERS
+	features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE;
+#endif
+	features->osd = raw_features & FEATURE_OSD;
+#ifdef GDSYS_LEGACY_DRIVERS
+	features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES;
+#endif
+
+	return 0;
+}
+
+#include <linux/bitops.h>
+#endif
+
+bool ioep_fpga_has_osd(unsigned int fpga)
+{
+	struct fpga_features features;
+
+	get_features(fpga, &features);
+
+	return features.osd;
+}
+
+void ioep_fpga_print_info(unsigned int fpga)
+{
+	u16 fpga_version;
+	struct fpga_versions versions;
+	struct fpga_features features;
+
+	FPGA_GET_REG(fpga, fpga_version, &fpga_version);
+	get_versions(fpga, &versions);
+	get_features(fpga, &features);
+
+	if (versions.video_channel)
+		printf("Videochannel");
+	else
+		printf("Mainchannel");
+
+	if (versions.con_side)
+		printf(" User");
+	else
+		printf(" Server");
+
+// FIXME
+#if 0
+		if (versions & (1<<4))
+			printf(" UC");
+#endif
+
+	switch(versions.pcb_transmission_type) {
+	case PCB_CAT_1G:
+	case PCB_CAT_10G:
+		printf(" CAT");
+		break;
+	case PCB_FIBER_3G:
+	case PCB_FIBER_10G:
+		printf(" Fiber");
+		break;
+	};
+
+	switch (versions.pcb_video_type) {
+	case PCB_DVI_SL:
+		printf(" DVI,");
+		break;
+	case PCB_DP_165MPIX:
+		printf(" DP 165MPix/s,");
+		break;
+	case PCB_DP_300MPIX:
+		printf(" DP 300MPix/s,");
+		break;
+	case PCB_HDMI:
+		printf(" HDMI,");
+		break;
+	case PCB_DP_1_2:
+		printf(" DP 1.2,");
+		break;
+	case PCB_HDMI_2_0:
+		printf(" HDMI 2.0,");
+		break;
+	}
+
+	printf(" FPGA V %d.%02d\n       features: ",
+	       fpga_version / 100, fpga_version % 100);
+
+	if (!features.compression_type1 &&
+	    !features.compression_type2 &&
+	    !features.compression_type3)
+		printf("no compression, ");
+
+	if (features.compression_type1)
+		printf("type1, ");
+
+	if (features.compression_type2)
+		printf("type2, ");
+
+	if (features.compression_type3)
+		printf("type3, ");
+
+	printf("%sosd", features.osd ? "" : "no ");
+
+	if (features.pcm_rx && features.pcm_tx)
+		printf(", pcm rx+tx");
+	else if(features.pcm_rx)
+		printf(", pcm rx");
+	else if(features.pcm_tx)
+		printf(", pcm tx");
+
+	if (features.spdif_rx && features.spdif_tx)
+		printf(", spdif rx+tx");
+	else if(features.spdif_rx)
+		printf(", spdif rx");
+	else if(features.spdif_tx)
+		printf(", spdif tx");
+
+	puts(",\n       ");
+
+	switch (features.sysclock) {
+	case SYSCLK_147456:
+		printf("clock 147.456 MHz");
+		break;
+	}
+
+	switch (features.ram_config) {
+	case RAM_DDR2_32BIT_295MBPS:
+		printf(", RAM 32 bit DDR2");
+		break;
+	case RAM_DDR3_32BIT_590MBPS:
+		printf(", RAM 32 bit DDR3");
+		break;
+	case RAM_DDR3_48BIT_590MBPS:
+	case RAM_DDR3_48BIT_1800MBPS:
+		printf(", RAM 48 bit DDR3");
+		break;
+	case RAM_DDR3_64BIT_1800MBPS:
+		printf(", RAM 64 bit DDR3");
+		break;
+	}
+
+	printf(", %d carrier(s)", features.carriers);
+
+	switch(features.carrier_speed) {
+	case CARRIER_SPEED_1G:
+		printf(", 1Gbit/s");
+		break;
+	case CARRIER_SPEED_3G:
+		printf(", 3Gbit/s");
+		break;
+	case CARRIER_SPEED_10G:
+		printf(", 10Gbit/s");
+		break;
+	}
+
+	printf(", %d video channel(s)\n", features.video_channels);
+}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/roms/u-boot/board/gdsys/common/ioep-fpga.h b/roms/u-boot/board/gdsys/common/ioep-fpga.h
new file mode 100644
index 000000000..53570b936
--- /dev/null
+++ b/roms/u-boot/board/gdsys/common/ioep-fpga.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#ifndef _IOEP_FPGA_H_
+#define _IOEP_FPGA_H_
+
+void ioep_fpga_print_info(unsigned int fpga);
+bool ioep_fpga_has_osd(unsigned int fpga);
+
+#endif
diff --git a/roms/u-boot/board/gdsys/common/osd.c b/roms/u-boot/board/gdsys/common/osd.c
new file mode 100644
index 000000000..679f8f301
--- /dev/null
+++ b/roms/u-boot/board/gdsys/common/osd.c
@@ -0,0 +1,506 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <linux/stringify.h>
+
+#include "ch7301.h"
+#include "dp501.h"
+#include <gdsys_fpga.h>
+
+#define ICS8N3QV01_I2C_ADDR 0x6E
+#define ICS8N3QV01_FREF 114285000
+#define ICS8N3QV01_FREF_LL 114285000LL
+#define ICS8N3QV01_F_DEFAULT_0 156250000LL
+#define ICS8N3QV01_F_DEFAULT_1 125000000LL
+#define ICS8N3QV01_F_DEFAULT_2 100000000LL
+#define ICS8N3QV01_F_DEFAULT_3  25175000LL
+
+#define SIL1178_MASTER_I2C_ADDRESS 0x38
+#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+
+#define PIXCLK_640_480_60 25180000
+#define MAX_X_CHARS 53
+#define MAX_Y_CHARS 26
+
+#ifdef CONFIG_SYS_OSD_DH
+#define MAX_OSD_SCREEN 8
+#define OSD_DH_BASE 4
+#else
+#define MAX_OSD_SCREEN 4
+#endif
+
+#ifdef CONFIG_SYS_OSD_DH
+#define OSD_SET_REG(screen, fld, val) \
+	do { \
+		if (screen >= OSD_DH_BASE) \
+			FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
+		else \
+			FPGA_SET_REG(screen, osd0.fld, val); \
+	} while (0)
+#else
+#define OSD_SET_REG(screen, fld, val) \
+		FPGA_SET_REG(screen, osd0.fld, val)
+#endif
+
+#ifdef CONFIG_SYS_OSD_DH
+#define OSD_GET_REG(screen, fld, val) \
+	do {					\
+		if (screen >= OSD_DH_BASE) \
+			FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
+		else \
+			FPGA_GET_REG(screen, osd0.fld, val); \
+	} while (0)
+#else
+#define OSD_GET_REG(screen, fld, val) \
+		FPGA_GET_REG(screen, osd0.fld, val)
+#endif
+
+unsigned int base_width;
+unsigned int base_height;
+size_t bufsize;
+u16 *buf;
+
+unsigned int osd_screen_mask = 0;
+
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
+#endif
+
+#ifdef CONFIG_SYS_SIL1178_I2C
+int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
+static void mpc92469ac_calc_parameters(unsigned int fout,
+	unsigned int *post_div, unsigned int *feedback_div)
+{
+	unsigned int n = *post_div;
+	unsigned int m = *feedback_div;
+	unsigned int a;
+	unsigned int b = 14745600 / 16;
+
+	if (fout < 50169600)
+		n = 8;
+	else if (fout < 100339199)
+		n = 4;
+	else if (fout < 200678399)
+		n = 2;
+	else
+		n = 1;
+
+	a = fout * n + (b / 2); /* add b/2 for proper rounding */
+
+	m = a / b;
+
+	*post_div = n;
+	*feedback_div = m;
+}
+
+static void mpc92469ac_set(unsigned screen, unsigned int fout)
+{
+	unsigned int n;
+	unsigned int m;
+	unsigned int bitval = 0;
+	mpc92469ac_calc_parameters(fout, &n, &m);
+
+	switch (n) {
+	case 1:
+		bitval = 0x00;
+		break;
+	case 2:
+		bitval = 0x01;
+		break;
+	case 4:
+		bitval = 0x02;
+		break;
+	case 8:
+		bitval = 0x03;
+		break;
+	}
+
+	FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
+}
+#endif
+
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+
+static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
+{
+	unsigned long long n;
+	unsigned long long mint;
+	unsigned long long mfrac;
+	u8 reg_a, reg_b, reg_c, reg_d, reg_f;
+	unsigned long long fout_calc;
+
+	if (index > 3)
+		return 0;
+
+	reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
+	reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
+	reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
+	reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
+	reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);
+
+	mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
+	mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
+		| (reg_d >> 7);
+	n = reg_d & 0x7f;
+
+	fout_calc = (mint * ICS8N3QV01_FREF_LL
+		     + mfrac * ICS8N3QV01_FREF_LL / 262144LL
+		     + ICS8N3QV01_FREF_LL / 524288LL
+		     + n / 2)
+		    / n
+		    * 1000000
+		    / (1000000 - 100);
+
+	return fout_calc;
+}
+
+
+static void ics8n3qv01_calc_parameters(unsigned int fout,
+	unsigned int *_mint, unsigned int *_mfrac,
+	unsigned int *_n)
+{
+	unsigned int n;
+	unsigned int foutiic;
+	unsigned int fvcoiic;
+	unsigned int mint;
+	unsigned long long mfrac;
+
+	n = (2215000000U + fout / 2) / fout;
+	if ((n & 1) && (n > 5))
+		n -= 1;
+
+	foutiic = fout - (fout / 10000);
+	fvcoiic = foutiic * n;
+
+	mint = fvcoiic / 114285000;
+	if ((mint < 17) || (mint > 63))
+		printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
+
+	mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
+		/ 114285000LL;
+
+	*_mint = mint;
+	*_mfrac = mfrac;
+	*_n = n;
+}
+
+static void ics8n3qv01_set(unsigned int fout)
+{
+	unsigned int n;
+	unsigned int mint;
+	unsigned int mfrac;
+	unsigned int fout_calc;
+	unsigned long long fout_prog;
+	long long off_ppm;
+	u8 reg0, reg4, reg8, reg12, reg18, reg20;
+
+	fout_calc = ics8n3qv01_get_fout_calc(1);
+	off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
+		  / ICS8N3QV01_F_DEFAULT_1;
+	printf("       PLL is off by %lld ppm\n", off_ppm);
+	fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
+		    / ICS8N3QV01_F_DEFAULT_1;
+	ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
+
+	reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+	reg0 |= (mint & 0x1f) << 1;
+	reg0 |= (mfrac >> 17) & 0x01;
+	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);
+
+	reg4 = mfrac >> 9;
+	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);
+
+	reg8 = mfrac >> 1;
+	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);
+
+	reg12 = mfrac << 7;
+	reg12 |= n & 0x7f;
+	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);
+
+	reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+	reg18 |= 0x20;
+	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);
+
+	reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+	reg20 |= mint & (1 << 5);
+	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
+}
+#endif
+
+static int osd_write_videomem(unsigned screen, unsigned offset,
+	u16 *data, size_t charcount)
+{
+	unsigned int k;
+
+	for (k = 0; k < charcount; ++k) {
+		if (offset + k >= bufsize)
+			return -1;
+#ifdef CONFIG_SYS_OSD_DH
+		if (screen >= OSD_DH_BASE)
+			FPGA_SET_REG(screen - OSD_DH_BASE,
+				     videomem1[offset + k], data[k]);
+		else
+			FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
+#else
+		FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
+#endif
+	}
+
+	return charcount;
+}
+
+static int osd_print(struct cmd_tbl *cmdtp, int flag, int argc,
+		     char *const argv[])
+{
+	unsigned screen;
+
+	if (argc < 5) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
+		unsigned x;
+		unsigned y;
+		unsigned charcount;
+		unsigned len;
+		u8 color;
+		unsigned int k;
+		char *text;
+		int res;
+
+		if (!(osd_screen_mask & (1 << screen)))
+			continue;
+
+		x = simple_strtoul(argv[1], NULL, 16);
+		y = simple_strtoul(argv[2], NULL, 16);
+		color = simple_strtoul(argv[3], NULL, 16);
+		text = argv[4];
+		charcount = strlen(text);
+		len = (charcount > bufsize) ? bufsize : charcount;
+
+		for (k = 0; k < len; ++k)
+			buf[k] = (text[k] << 8) | color;
+
+		res = osd_write_videomem(screen, y * base_width + x, buf, len);
+		if (res < 0)
+			return res;
+
+		OSD_SET_REG(screen, control, 0x0049);
+	}
+
+	return 0;
+}
+
+int osd_probe(unsigned screen)
+{
+	u16 version;
+	u16 features;
+	int old_bus = i2c_get_bus_num();
+	bool pixclock_present = false;
+	bool output_driver_present = false;
+
+	OSD_GET_REG(0, version, &version);
+	OSD_GET_REG(0, features, &features);
+
+	base_width = ((features & 0x3f00) >> 8) + 1;
+	base_height = (features & 0x001f) + 1;
+	bufsize = base_width * base_height;
+	buf = malloc(sizeof(u16) * bufsize);
+	if (!buf)
+		return -1;
+
+#ifdef CONFIG_SYS_OSD_DH
+	printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+	       (screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen,
+	       (screen > 3) ? 1 : 0, version/100, version%100, base_width,
+	       base_height);
+#else
+	printf("OSD%d:  Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+	       screen, version/100, version%100, base_width, base_height);
+#endif
+	/* setup pixclock */
+
+#ifdef CONFIG_SYS_MPC92469AC
+	pixclock_present = true;
+	mpc92469ac_set(screen, PIXCLK_640_480_60);
+#endif
+
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+	i2c_set_bus_num(ics8n3qv01_i2c[screen]);
+	if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
+		ics8n3qv01_set(PIXCLK_640_480_60);
+		pixclock_present = true;
+	}
+#endif
+
+	if (!pixclock_present)
+		printf("       no pixelclock found\n");
+
+	/* setup output driver */
+
+#ifdef CONFIG_SYS_CH7301_I2C
+	if (!ch7301_probe(screen, true))
+		output_driver_present = true;
+#endif
+
+#ifdef CONFIG_SYS_SIL1178_I2C
+	i2c_set_bus_num(sil1178_i2c[screen]);
+	if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
+		if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) {
+			/*
+			 * magic initialization sequence,
+			 * adapted from datasheet
+			 */
+			i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+			output_driver_present = true;
+		}
+	}
+#endif
+
+#ifdef CONFIG_SYS_DP501_I2C
+	if (!dp501_probe(screen, true))
+		output_driver_present = true;
+#endif
+
+	if (!output_driver_present)
+		printf("       no output driver found\n");
+
+	OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1));
+	OSD_SET_REG(screen, x_pos, 0x007f);
+	OSD_SET_REG(screen, y_pos, 0x005f);
+
+	if (pixclock_present && output_driver_present)
+		osd_screen_mask |= 1 << screen;
+
+	i2c_set_bus_num(old_bus);
+
+	return 0;
+}
+
+int osd_write(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	unsigned screen;
+
+	if ((argc < 4) || (strlen(argv[3]) % 4)) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
+		unsigned x;
+		unsigned y;
+		unsigned k;
+		u16 buffer[base_width];
+		char *rp;
+		u16 *wp = buffer;
+		unsigned count = (argc > 4) ?
+			simple_strtoul(argv[4], NULL, 16) : 1;
+
+		if (!(osd_screen_mask & (1 << screen)))
+			continue;
+
+		x = simple_strtoul(argv[1], NULL, 16);
+		y = simple_strtoul(argv[2], NULL, 16);
+		rp = argv[3];
+
+
+		while (*rp) {
+			char substr[5];
+
+			memcpy(substr, rp, 4);
+			substr[4] = 0;
+			*wp = simple_strtoul(substr, NULL, 16);
+
+			rp += 4;
+			wp++;
+			if (wp - buffer > base_width)
+				break;
+		}
+
+		for (k = 0; k < count; ++k) {
+			unsigned offset =
+				y * base_width + x + k * (wp - buffer);
+			osd_write_videomem(screen, offset, buffer,
+				wp - buffer);
+		}
+
+		OSD_SET_REG(screen, control, 0x0049);
+	}
+
+	return 0;
+}
+
+int osd_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	unsigned screen;
+	unsigned x;
+	unsigned y;
+
+	if (argc < 3) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	x = simple_strtoul(argv[1], NULL, 16);
+	y = simple_strtoul(argv[2], NULL, 16);
+
+	if (!x || (x > 64) || (x > MAX_X_CHARS) ||
+	    !y || (y > 32) || (y > MAX_Y_CHARS)) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
+		if (!(osd_screen_mask & (1 << screen)))
+			continue;
+
+		OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1));
+		OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
+		OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	osdw, 5, 0, osd_write,
+	"write 16-bit hex encoded buffer to osd memory",
+	"pos_x pos_y buffer count\n"
+);
+
+U_BOOT_CMD(
+	osdp, 5, 0, osd_print,
+	"write ASCII buffer to osd memory",
+	"pos_x pos_y color text\n"
+);
+
+U_BOOT_CMD(
+	osdsize, 3, 0, osd_size,
+	"set OSD XY size in characters",
+	"size_x(max. " __stringify(MAX_X_CHARS)
+	") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
+);
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/roms/u-boot/board/gdsys/common/osd.h b/roms/u-boot/board/gdsys/common/osd.h
new file mode 100644
index 000000000..4e8e53ab4
--- /dev/null
+++ b/roms/u-boot/board/gdsys/common/osd.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#ifndef _OSD_H_
+#define _OSD_H_
+
+int ch7301_probe(unsigned screen, bool power);
+int osd_probe(unsigned screen);
+
+#endif
diff --git a/roms/u-boot/board/gdsys/common/osd_cmd.c b/roms/u-boot/board/gdsys/common/osd_cmd.c
new file mode 100644
index 000000000..fe6249794
--- /dev/null
+++ b/roms/u-boot/board/gdsys/common/osd_cmd.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017
+ * Mario Six,  Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * based on the gdsys osd driver, which is
+ *
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <hexdump.h>
+#include <video_osd.h>
+#include <malloc.h>
+
+static int do_osd_write(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	struct udevice *dev;
+	uint x, y;
+	uint count;
+	char *hexstr;
+	u8 *buffer;
+	size_t buflen;
+	int res;
+
+	if (argc < 4 || (strlen(argv[3])) % 2)
+		return CMD_RET_USAGE;
+
+	x = simple_strtoul(argv[1], NULL, 16);
+	y = simple_strtoul(argv[2], NULL, 16);
+	hexstr = argv[3];
+	count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1;
+
+	buflen = strlen(hexstr) / 2;
+
+	buffer = malloc(buflen);
+	if (!buffer) {
+		puts("Memory allocation failure\n");
+		return CMD_RET_FAILURE;
+	}
+
+	res = hex2bin(buffer, hexstr, buflen);
+	if (res) {
+		free(buffer);
+		puts("Hexadecimal input contained invalid characters\n");
+		return CMD_RET_FAILURE;
+	}
+
+	for (uclass_first_device(UCLASS_VIDEO_OSD, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		int res;
+
+		res = video_osd_set_mem(dev, x, y, buffer, buflen, count);
+		if (res) {
+			free(buffer);
+			printf("Could not write to video mem on osd %s\n",
+			       dev->name);
+			return CMD_RET_FAILURE;
+		}
+	}
+
+	free(buffer);
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_osd_print(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	struct udevice *dev;
+	uint x, y;
+	u8 color;
+	char *text;
+
+	if (argc < 5)
+		return CMD_RET_USAGE;
+
+	x = simple_strtoul(argv[1], NULL, 16);
+	y = simple_strtoul(argv[2], NULL, 16);
+	color = simple_strtoul(argv[3], NULL, 16);
+	text = argv[4];
+
+	for (uclass_first_device(UCLASS_VIDEO_OSD, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		int res;
+
+		res = video_osd_print(dev, x, y, color, text);
+		if (res) {
+			printf("Could not print string to osd %s\n", dev->name);
+			return CMD_RET_FAILURE;
+		}
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_osd_size(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	struct udevice *dev;
+	uint x, y;
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	x = simple_strtoul(argv[1], NULL, 16);
+	y = simple_strtoul(argv[2], NULL, 16);
+
+	for (uclass_first_device(UCLASS_VIDEO_OSD, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		int res;
+
+		res = video_osd_set_size(dev, x, y);
+
+		if (res) {
+			printf("Could not set size on osd %s\n", dev->name);
+			return CMD_RET_FAILURE;
+		}
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	osdw, 5, 0, do_osd_write,
+	"write 16-bit hex encoded buffer to osd memory",
+	"osdw [pos_x] [pos_y] [buffer] [count] - write 8-bit hex encoded buffer to osd memory\n"
+);
+
+U_BOOT_CMD(
+	osdp, 5, 0, do_osd_print,
+	"write ASCII buffer to osd memory",
+	"osdp [pos_x] [pos_y] [color] [text] - write ASCII buffer to osd memory\n"
+);
+
+U_BOOT_CMD(
+	osdsize, 3, 0, do_osd_size,
+	"set OSD XY size in characters",
+	"osdsize [size_x] [size_y] - set OSD XY size in characters\n"
+);
diff --git a/roms/u-boot/board/gdsys/mpc8308/Kconfig b/roms/u-boot/board/gdsys/mpc8308/Kconfig
new file mode 100644
index 000000000..c3fd0518b
--- /dev/null
+++ b/roms/u-boot/board/gdsys/mpc8308/Kconfig
@@ -0,0 +1,83 @@
+if TARGET_GAZERBEAM
+
+config GDSYS_LEGACY_OSD_CMDS
+	bool
+	help
+	  Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by
+	  gdsys devices.
+
+config GDSYS_LEGACY_DRIVERS
+	bool
+	help
+	  Enable the gdsys legacy drivers under board/gdsys/common. If this
+	  option is not set, all relevant DM drivers must be configured for the
+	  device in question.
+
+config SYS_FPGA0_BASE
+	hex
+	default E0600000
+	help
+	  The base address of the first FPGA's register map.
+
+config SYS_FPGA0_SIZE
+	hex
+	default 1
+	help
+	  The base address of the first FPGA's register map.
+
+config SYS_FPGA1_BASE
+	hex
+	help
+	  The base address of the second FPGA's register map.
+
+config SYS_FPGA1_SIZE
+	hex
+	help
+	  The base address of the second FPGA's register map.
+
+config SYS_BOARD
+	default "mpc8308"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_CONFIG_NAME
+	default "gazerbeam"
+
+config SYS_FPGA1_BASE
+	default E0700000
+
+config SYS_FPGA1_SIZE
+	default 1
+
+config GDSYS_LEGACY_OSD_CMDS
+	default y
+
+choice
+	prompt "FPGA flavor selection"
+
+config SYS_FPGA_FLAVOR_LEGACY
+	bool "Legacy flavor"
+	help
+	  This enables support for the gdsys pre-Gazerbeam FPGA memory layout.
+
+config SYS_FPGA_FLAVOR_GAZERBEAM
+	bool "Gazerbeam flavor"
+	help
+	  This enables support for the gdsys FPGA memory layout of the
+	  Gazerbeam board.
+
+endchoice
+
+config EXTENDED_FEATURES
+	bool "FPGA extended features"
+	depends on GDSYS_LEGACY_DRIVERS
+	help
+	  Enable support for the extended features field of the IHS FPGA.
+
+config CMD_IOLOOP
+	bool "Enable 'ioloop' and 'ioreflect' commands"
+	help
+	  These commands provide FPGA tests.
+
+endif
diff --git a/roms/u-boot/board/gdsys/mpc8308/MAINTAINERS b/roms/u-boot/board/gdsys/mpc8308/MAINTAINERS
new file mode 100644
index 000000000..dc0b389f7
--- /dev/null
+++ b/roms/u-boot/board/gdsys/mpc8308/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8308 BOARD
+M:	Dirk Eibach <dirk.eibach@gdsys.cc>
+S:	Maintained
+F:	board/gdsys/mpc8308/
+F:	include/configs/gazerbeam.h
+F:	configs/gazerbeam_defconfig
diff --git a/roms/u-boot/board/gdsys/mpc8308/Makefile b/roms/u-boot/board/gdsys/mpc8308/Makefile
new file mode 100644
index 000000000..f86d997bc
--- /dev/null
+++ b/roms/u-boot/board/gdsys/mpc8308/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2014
+# Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+
+obj-y := mpc8308.o sdram.o
+obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o
diff --git a/roms/u-boot/board/gdsys/mpc8308/gazerbeam.c b/roms/u-boot/board/gdsys/mpc8308/gazerbeam.c
new file mode 100644
index 000000000..3d4a7e57f
--- /dev/null
+++ b/roms/u-boot/board/gdsys/mpc8308/gazerbeam.c
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <init.h>
+#include <miiphy.h>
+#include <misc.h>
+#include <sysinfo.h>
+#include <tpm-v1.h>
+#include <video_osd.h>
+#include <asm/global_data.h>
+
+#include "../common/ihs_mdio.h"
+#include "../../../drivers/sysinfo/gazerbeam.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ihs_mdio_info ihs_mdio_info[] = {
+	{ .fpga = NULL, .name = "ihs0", .base = 0x58 },
+	{ .fpga = NULL, .name = "ihs1", .base = 0x58 },
+};
+
+static int get_tpm(struct udevice **devp)
+{
+	int rc;
+
+	rc = uclass_first_device_err(UCLASS_TPM, devp);
+	if (rc) {
+		printf("Could not find TPM (ret=%d)\n", rc);
+		return CMD_RET_FAILURE;
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	struct udevice *sysinfo;
+	struct udevice *serdes;
+	int mc = 0;
+	int con = 0;
+
+	if (sysinfo_get(&sysinfo))
+		puts("Could not find sysinfo information device.\n");
+
+	/* Initialize serdes */
+	uclass_get_device_by_phandle(UCLASS_MISC, sysinfo, "serdes", &serdes);
+
+	if (sysinfo_detect(sysinfo))
+		puts("Device information detection failed.\n");
+
+	sysinfo_get_int(sysinfo, BOARD_MULTICHANNEL, &mc);
+	sysinfo_get_int(sysinfo, BOARD_VARIANT, &con);
+
+	if (mc == 2 || mc == 1)
+		dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@22");
+
+	if (mc == 4) {
+		dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@20");
+		dev_enable_by_path("/localbus@e0005000/iocon_uart@2,0");
+		dev_enable_by_path("/fpga1bus");
+	}
+
+	if (mc == 2 || con == VAR_CON) {
+		dev_enable_by_path("/fpga0bus/fpga0_video1");
+		dev_enable_by_path("/fpga0bus/fpga0_iic_video1");
+		dev_enable_by_path("/fpga0bus/fpga0_axi_video1");
+	}
+
+	if (con == VAR_CON) {
+		dev_enable_by_path("/fpga0bus/fpga0_video0");
+		dev_enable_by_path("/fpga0bus/fpga0_iic_video0");
+		dev_enable_by_path("/fpga0bus/fpga0_axi_video0");
+	}
+
+	return 0;
+}
+
+int checksysinfo(void)
+{
+	struct udevice *sysinfo;
+	char *s = env_get("serial#");
+	int mc = 0;
+	int con = 0;
+
+	if (sysinfo_get(&sysinfo))
+		puts("Could not find sysinfo information device.\n");
+
+	sysinfo_get_int(sysinfo, BOARD_MULTICHANNEL, &mc);
+	sysinfo_get_int(sysinfo, BOARD_VARIANT, &con);
+
+	puts("Board: Gazerbeam ");
+	printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC");
+	printf("%s", con == VAR_CON ? "CON" : "CPU");
+
+	if (s) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+static void display_osd_info(struct udevice *osd,
+			     struct video_osd_info *osd_info)
+{
+	printf("OSD-%s: Digital-OSD version %01d.%02d, %d x %d characters\n",
+	       osd->name, osd_info->major_version, osd_info->minor_version,
+	       osd_info->width, osd_info->height);
+}
+
+int last_stage_init(void)
+{
+	int fpga_hw_rev = 0;
+	int i;
+	struct udevice *sysinfo;
+	struct udevice *osd;
+	struct video_osd_info osd_info;
+	struct udevice *tpm;
+	int ret;
+
+	if (sysinfo_get(&sysinfo))
+		puts("Could not find sysinfo information device.\n");
+
+	if (sysinfo) {
+		int res = sysinfo_get_int(sysinfo, BOARD_HWVERSION,
+					  &fpga_hw_rev);
+
+		if (res)
+			printf("Could not determind FPGA HW revision (res = %d)\n",
+			       res);
+	}
+
+	env_set_ulong("fpga_hw_rev", fpga_hw_rev);
+
+	ret = get_tpm(&tpm);
+	if (ret || tpm_init(tpm) || tpm1_startup(tpm, TPM_ST_CLEAR) ||
+	    tpm1_continue_self_test(tpm)) {
+		printf("TPM init failed\n");
+	}
+
+	if (fpga_hw_rev >= 4) {
+		for (i = 0; i < 4; i++) {
+			struct udevice *rxaui;
+			char name[8];
+
+			snprintf(name, sizeof(name), "rxaui%d", i);
+			/* Disable RXAUI polarity inversion */
+			ret = uclass_get_device_by_phandle(UCLASS_MISC, sysinfo,
+							   name, &rxaui);
+			if (!ret)
+				misc_set_enabled(rxaui, false);
+		}
+	}
+
+	for (uclass_first_device(UCLASS_VIDEO_OSD, &osd);
+	     osd;
+	     uclass_next_device(&osd)) {
+		video_osd_get_info(osd, &osd_info);
+		display_osd_info(osd, &osd_info);
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
+	fdt_fixup_esdhc(blob, bd);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/gdsys/mpc8308/mpc8308.c b/roms/u-boot/board/gdsys/mpc8308/mpc8308.c
new file mode 100644
index 000000000..0f90f8ad3
--- /dev/null
+++ b/roms/u-boot/board/gdsys/mpc8308/mpc8308.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#include "mpc8308.h"
+#include <gdsys_fpga.h>
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+/* as gpio output status cannot be read back, we have to buffer it locally */
+u32 gpio0_out;
+
+void setbits_gpio0_out(u32 mask)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	gpio0_out |= mask;
+	out_be32(&immr->gpio[0].dat, gpio0_out);
+}
+
+void clrbits_gpio0_out(u32 mask)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	gpio0_out &= ~mask;
+	out_be32(&immr->gpio[0].dat, gpio0_out);
+}
+
+int get_fpga_state(uint dev)
+{
+	return gd->arch.fpga_state[dev];
+}
+
+int board_early_init_f(void)
+{
+	uint k;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->arch.fpga_state[k] = 0;
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	uint k;
+	uint ctr;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->arch.fpga_state[k] = 0;
+
+	/*
+	 * reset FPGA
+	 */
+	mpc8308_init();
+
+	mpc8308_set_fpga_reset(1);
+
+	mpc8308_setup_hw();
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ctr = 0;
+		while (!mpc8308_get_fpga_done(k)) {
+			mdelay(100);
+			if (ctr++ > 5) {
+				gd->arch.fpga_state[k] |=
+					FPGA_STATE_DONE_FAILED;
+				break;
+			}
+		}
+	}
+
+	udelay(10);
+
+	mpc8308_set_fpga_reset(0);
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		/*
+		 * wait for fpga out of reset
+		 */
+		ctr = 0;
+		while (1) {
+			u16 val;
+
+			FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
+
+			FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+			if (val == REFLECTION_TESTPATTERN_INV)
+				break;
+
+			mdelay(100);
+			if (ctr++ > 5) {
+				gd->arch.fpga_state[k] |=
+					FPGA_STATE_REFLECTION_FAILED;
+				break;
+			}
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/gdsys/mpc8308/mpc8308.h b/roms/u-boot/board/gdsys/mpc8308/mpc8308.h
new file mode 100644
index 000000000..1e4f24fb2
--- /dev/null
+++ b/roms/u-boot/board/gdsys/mpc8308/mpc8308.h
@@ -0,0 +1,13 @@
+#ifndef __MPC8308_H_
+#define __MPC8308_H_
+
+void setbits_gpio0_out(u32 mask);
+void clrbits_gpio0_out(u32 mask);
+
+/* functions to be provided by board implementation */
+void mpc8308_init(void);
+void mpc8308_set_fpga_reset(unsigned state);
+void mpc8308_setup_hw(void);
+int mpc8308_get_fpga_done(unsigned fpga);
+
+#endif /* __MPC8308_H_ */
diff --git a/roms/u-boot/board/gdsys/mpc8308/sdram.c b/roms/u-boot/board/gdsys/mpc8308/sdram.c
new file mode 100644
index 000000000..bfd55f54e
--- /dev/null
+++ b/roms/u-boot/board/gdsys/mpc8308/sdram.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * Authors: Nick.Spence@freescale.com
+ *          Wilson.Lo@freescale.com
+ *          scottwood@freescale.com
+ *
+ * This files is  mostly identical to the original from
+ * board\freescale\mpc8315erdb\sdram.c
+ */
+
+#ifndef CONFIG_MPC83XX_SDRAM
+
+#include <common.h>
+#include <init.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+
+#include <asm/bitops.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+		 CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	sync();
+
+	return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
+}
+
+int dram_init(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -ENXIO;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
+}
+
+#endif /* !CONFIG_MPC83XX_SDRAM */
diff --git a/roms/u-boot/board/ge/b1x5v2/Kconfig b/roms/u-boot/board/ge/b1x5v2/Kconfig
new file mode 100644
index 000000000..80a5bcae7
--- /dev/null
+++ b/roms/u-boot/board/ge/b1x5v2/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_GE_B1X5V2
+
+config SYS_BOARD
+	default "b1x5v2"
+
+config SYS_VENDOR
+	default "ge"
+
+config SYS_CONFIG_NAME
+	default "ge_b1x5v2"
+
+source "board/ge/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/ge/b1x5v2/MAINTAINERS b/roms/u-boot/board/ge/b1x5v2/MAINTAINERS
new file mode 100644
index 000000000..f22d49283
--- /dev/null
+++ b/roms/u-boot/board/ge/b1x5v2/MAINTAINERS
@@ -0,0 +1,9 @@
+GE B1X5V2 BOARD
+M:	Huan 'Kitty' Wang <HuanWang@ge.com>
+M:	Ian Ray <ian.ray@ge.com>
+M:	Sebastian Reichel <sebastian.reichel@collabora.com>
+S:	Maintained
+F:	arch/arm/dts/imx6dl-b1x5v2.dts
+F:	board/ge/b1x5v2/
+F:	configs/ge_b1x5v2_defconfig
+F:	include/configs/ge_b1x5v2.h
diff --git a/roms/u-boot/board/ge/b1x5v2/Makefile b/roms/u-boot/board/ge/b1x5v2/Makefile
new file mode 100644
index 000000000..8a27af52e
--- /dev/null
+++ b/roms/u-boot/board/ge/b1x5v2/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2018-2020 Collabora
+# Copyright 2018-2020 GE
+
+obj-y :=  b1x5v2.o spl.o
diff --git a/roms/u-boot/board/ge/b1x5v2/b1x5v2.c b/roms/u-boot/board/ge/b1x5v2/b1x5v2.c
new file mode 100644
index 000000000..de4cb0d5a
--- /dev/null
+++ b/roms/u-boot/board/ge/b1x5v2/b1x5v2.c
@@ -0,0 +1,699 @@
+/*
+ * GE B105v2, B125v2, B155v2
+ *
+ * Copyright 2018-2020 GE Inc.
+ * Copyright 2018-2020 Collabora Ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/video.h>
+#include <command.h>
+#include <common.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <micrel.h>
+#include <netdev.h>
+#include <panel.h>
+#include <rtc.h>
+#include <spi_flash.h>
+#include <version.h>
+
+#include "../common/vpd_reader.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SPL_BUILD
+
+#define B1X5V2_GE_VPD_OFFSET	0x0100000
+#define B1X5V2_GE_VPD_SIZE	1022
+
+#define VPD_TYPE_INVALID	0x00
+#define VPD_BLOCK_NETWORK	0x20
+#define VPD_BLOCK_HWID		0x44
+#define VPD_MAC_ADDRESS_LENGTH	6
+
+#define VPD_FLAG_VALID_MAC	BIT(1)
+
+#define AR8035_PHY_ID			0x004dd072
+#define AR8035_PHY_DEBUG_ADDR_REG	0x1d
+#define AR8035_PHY_DEBUG_DATA_REG	0x1e
+#define AR8035_HIB_CTRL_REG		0xb
+#define AR8035_HIBERNATE_EN		(1 << 15)
+
+static struct vpd_cache {
+	bool is_read;
+	u8 product_id;
+	unsigned char mac[VPD_MAC_ADDRESS_LENGTH];
+	u32 flags;
+} vpd;
+
+enum product_type {
+	PRODUCT_TYPE_B105V2 = 6,
+	PRODUCT_TYPE_B105PV2 = 7,
+	PRODUCT_TYPE_B125V2 = 8,
+	PRODUCT_TYPE_B125PV2 = 9,
+	PRODUCT_TYPE_B155V2 = 10,
+
+	PRODUCT_TYPE_INVALID = 0,
+};
+
+int dram_init(void) {
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+int power_init_board(void)
+{
+	/* all required PMIC configuration happens via DT */
+	return 0;
+}
+
+static int disable_phy_hibernation(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	if (phydev->drv->uid == AR8035_PHY_ID) {
+		/* Disable hibernation, other configuration has been done by PHY driver */
+		phy_write(phydev, MDIO_DEVAD_NONE, AR8035_PHY_DEBUG_ADDR_REG, AR8035_HIB_CTRL_REG);
+		val = phy_read(phydev, MDIO_DEVAD_NONE, AR8035_PHY_DEBUG_DATA_REG);
+		val &= ~AR8035_HIBERNATE_EN;
+		phy_write(phydev, MDIO_DEVAD_NONE, AR8035_PHY_DEBUG_DATA_REG, val);
+	} else {
+		printf("Unknown PHY: %08x\n", phydev->drv->uid);
+	}
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	disable_phy_hibernation(phydev);
+
+	return 0;
+}
+
+static int auo_g101evn01_detect(const struct display_info_t *info)
+{
+	char *dev = env_get("devicetype");
+	return !strcmp(dev, "B105v2") || !strcmp(dev, "B105Pv2");
+}
+
+static int auo_g121ean01_detect(const struct display_info_t *info)
+{
+	char *dev = env_get("devicetype");
+	return !strcmp(dev, "B125v2") || !strcmp(dev, "B125Pv2");;
+}
+
+static int auo_g156xtn01_detect(const struct display_info_t *info)
+{
+	char *dev = env_get("devicetype");
+	return !strcmp(dev, "B155v2");
+}
+
+static void b1x5v2_backlight_enable(int percent)
+{
+	struct udevice *panel;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
+	if (ret) {
+		printf("Could not find panel: %d\n", ret);
+		return;
+	}
+
+	panel_set_backlight(panel, percent);
+	panel_enable_backlight(panel);
+
+}
+
+static void lcd_enable(const struct display_info_t *info)
+{
+	printf("Enable backlight...\n");
+	b1x5v2_backlight_enable(100);
+}
+
+struct display_info_t const displays[] = {
+{
+	.di = 0,
+	.bus = -1,
+	.addr = -1,
+	.pixfmt = IPU_PIX_FMT_RGB24,
+	.detect = auo_g156xtn01_detect,
+	.enable = lcd_enable,
+	.mode = {
+		.name = "AUO G156XTN01",
+		.refresh = 60,
+		.xres = 1368, /* because of i.MX6 limitation, actually 1366 */
+		.yres = 768,
+		.pixclock = 13158, /* 76 MHz in ps */
+		.left_margin = 33,
+		.right_margin = 67,
+		.upper_margin = 4,
+		.lower_margin = 4,
+		.hsync_len = 94,
+		.vsync_len = 30,
+		.sync = FB_SYNC_EXT,
+		.vmode = FB_VMODE_NONINTERLACED
+	}
+},
+{
+	.di = 0,
+	.bus = -1,
+	.addr = -1,
+	.pixfmt = IPU_PIX_FMT_RGB24,
+	.detect = auo_g121ean01_detect,
+	.enable = lcd_enable,
+	.mode = {
+		.name = "AUO G121EAN01.4",
+		.refresh = 60,
+		.xres = 1280,
+		.yres = 800,
+		.pixclock = 14992, /* 66.7 MHz in ps */
+		.left_margin = 8,
+		.right_margin = 58,
+		.upper_margin = 6,
+		.lower_margin = 4,
+		.hsync_len = 70,
+		.vsync_len = 10,
+		.sync = FB_SYNC_EXT,
+		.vmode = FB_VMODE_NONINTERLACED
+	}
+},
+{
+	.di = 0,
+	.bus = -1,
+	.addr = -1,
+	.pixfmt = IPU_PIX_FMT_RGB24,
+	.detect = auo_g101evn01_detect,
+	.enable = lcd_enable,
+	.mode = {
+		.name = "AUO G101EVN01.3",
+		.refresh = 60,
+		.xres = 1280,
+		.yres = 800,
+		.pixclock = 14992, /* 66.7 MHz in ps */
+		.left_margin = 8,
+		.right_margin = 58,
+		.upper_margin = 6,
+		.lower_margin = 4,
+		.hsync_len = 70,
+		.vsync_len = 10,
+		.sync = FB_SYNC_EXT,
+		.vmode = FB_VMODE_NONINTERLACED
+	}
+}
+};
+size_t display_count = ARRAY_SIZE(displays);
+
+static void enable_videopll(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	s32 timeout = 100000;
+
+	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	/* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
+	 *   |
+	 * PLL5
+	 *   |
+	 * CS2CDR[LDB_DI0_CLK_SEL]
+	 *   |
+	 *   +----> LDB_DI0_SERIAL_CLK_ROOT
+	 *   |
+	 *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
+	 */
+
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+			BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+			BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
+			BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+	clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	while (timeout--)
+		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+			break;
+
+	if (timeout < 0)
+		printf("Warning: video pll lock timeout!\n");
+
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_BYPASS,
+			BM_ANADIG_PLL_VIDEO_ENABLE);
+}
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	enable_videopll();
+
+	/* When a reset/reboot is performed the display power needs to be turned
+	 * off for atleast 500ms. The boot time is ~300ms, we need to wait for
+	 * an additional 200ms here. Unfortunately we use external PMIC for
+	 * doing the reset, so can not differentiate between POR vs soft reset
+	 */
+	mdelay(200);
+
+	/* CCM_CSCMR2 -> ldb_di0_ipu_div [IMX6SDLRM page 839] */
+	/* divide IPU clock by 7 */
+	setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+	/* CCM_CHSCCDR -> ipu1_di0_clk_sel [IMX6SDLRM page 849] */
+	/* Set LDB_DI0 as clock source for IPU_DI0 */
+	clrsetbits_le32(&mxc_ccm->chsccdr,
+			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+			(CHSCCDR_CLK_SEL_LDB_DI0 <<
+			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+	/* Turn on IPU LDB DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+	enable_ipu_clock();
+
+	/* IOMUXC_GPR2 [IMX6SDLRM page 2049] */
+	/* Set LDB Channel 0 in SPWG 24 Bit mode */
+	writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
+	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+	       &iomux->gpr[2]);
+
+	/* IOMUXC_GPR3 [IMX6SDLRM page 2051] */
+	/* LVDS0 is connected to IPU DI0 */
+	clrsetbits_le32(&iomux->gpr[3],
+			IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
+		       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+			IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_early_init_f(void)
+{
+	select_ldb_di_clock_source(MXC_PLL5_CLK);
+
+	return 0;
+}
+
+static int eeti_touch_get_model(struct udevice *dev, char *result) {
+	u8 query[68] = {0x67, 0x00, 0x42, 0x00, 0x03, 0x01, 'E', 0x00, 0x00, 0x00};
+	struct i2c_msg qmsg = {
+		.addr = 0x2a,
+		.flags = 0,
+		.len = sizeof(query),
+		.buf = query,
+	};
+	u8 reply[66] = {0};
+	struct i2c_msg rmsg = {
+		.addr = 0x2a,
+		.flags = I2C_M_RD,
+		.len = sizeof(reply),
+		.buf = reply,
+	};
+	int err;
+
+	err = dm_i2c_xfer(dev, &qmsg, 1);
+	if (err)
+		return err;
+
+	/*
+	 * device sends IRQ when its ok to read. To keep the code
+	 * simple we just wait an arbitrary, long enough time period.
+	 */
+	mdelay(10);
+
+	err = dm_i2c_xfer(dev, &rmsg, 1);
+	if (err)
+		return err;
+
+	if (reply[0] != 0x42 || reply[1] != 0x00 ||
+	    reply[2] != 0x03 || reply[4] != 'E')
+		return -EPROTO;
+
+	memcpy(result, reply+5, 10);
+	return 0;
+}
+
+static bool b1x5v2_board_is_p_model(void)
+{
+	struct udevice *bus = NULL;
+	struct udevice *dev = NULL;
+	int err;
+
+	err = uclass_get_device_by_name(UCLASS_I2C, "i2c@21a0000", &bus);
+	if (err || !bus) {
+		printf("Could not get I2C bus: %d\n", err);
+		return true;
+	}
+
+	/* The P models do not have this port expander */
+	err = dm_i2c_probe(bus, 0x21, 0, &dev);
+	if (err || !dev) {
+		return true;
+	}
+
+	return false;
+}
+
+static enum product_type b1x5v2_board_type(void)
+{
+	struct udevice *bus = NULL;
+	struct udevice *dev = NULL;
+	char model[11] = {0};
+	int err;
+	int retry;
+
+	err = uclass_get_device_by_name(UCLASS_I2C, "i2c@21a8000", &bus);
+	if (err) {
+		printf("Could not get I2C bus: %d\n", err);
+		return PRODUCT_TYPE_INVALID;
+	}
+
+	err = dm_i2c_probe(bus, 0x41, 0, &dev);
+	if (!err && dev) { /* Ilitek Touchscreen */
+		if (b1x5v2_board_is_p_model()) {
+			return PRODUCT_TYPE_B105PV2;
+		} else {
+			return PRODUCT_TYPE_B105V2;
+		}
+	}
+
+	err = dm_i2c_probe(bus, 0x2a, 0, &dev);
+	if (err || !dev) {
+		printf("Could not find touchscreen: %d\n", err);
+		return PRODUCT_TYPE_INVALID;
+	}
+
+	for (retry = 0; retry < 3; ++retry) {
+		err = eeti_touch_get_model(dev, model);
+		if (!err)
+			break;
+		printf("Retry %d read EETI touchscreen model: %d\n", retry + 1, err);
+	}
+	if (err) {
+		printf("Could not read EETI touchscreen model: %d\n", err);
+		return PRODUCT_TYPE_INVALID;
+	}
+
+	if (!strcmp(model, "Orion_1320")) { /* EETI EXC80H60 */
+		if (b1x5v2_board_is_p_model()) {
+			return PRODUCT_TYPE_B125PV2;
+		} else {
+			return PRODUCT_TYPE_B125V2;
+		}
+	} else if (!strcmp(model, "Orion_1343")) { /* EETI EXC80H84 */
+		return PRODUCT_TYPE_B155V2;
+	}
+
+	printf("Unknown EETI touchscreen model: %s\n", model);
+	return PRODUCT_TYPE_INVALID;
+}
+
+static void set_env_per_board_type(enum product_type type)
+{
+	switch (type) {
+	case PRODUCT_TYPE_B105V2:
+		env_set("resolution", "1280x800");
+		env_set("devicetype", "B105v2");
+		env_set("fdtfile", "imx6dl-b105v2.dtb");
+		break;
+	case PRODUCT_TYPE_B105PV2:
+		env_set("resolution", "1280x800");
+		env_set("devicetype", "B105Pv2");
+		env_set("fdtfile", "imx6dl-b105pv2.dtb");
+		break;
+	case PRODUCT_TYPE_B125V2:
+		env_set("resolution", "1280x800");
+		env_set("devicetype", "B125v2");
+		env_set("fdtfile", "imx6dl-b125v2.dtb");
+		break;
+	case PRODUCT_TYPE_B125PV2:
+		env_set("resolution", "1280x800");
+		env_set("devicetype", "B125Pv2");
+		env_set("fdtfile", "imx6dl-b125pv2.dtb");
+		break;
+	case PRODUCT_TYPE_B155V2:
+		env_set("resolution", "1366x768");
+		env_set("devicetype", "B155v2");
+		env_set("fdtfile", "imx6dl-b155v2.dtb");
+		break;
+	default:
+		break;
+	}
+}
+
+static int b1x5v2_board_type_autodetect(void)
+{
+	enum product_type product = b1x5v2_board_type();
+	if (product != PRODUCT_TYPE_INVALID) {
+		set_env_per_board_type(product);
+		return 0;
+	}
+	return -1;
+}
+
+/*
+ * Extracts MAC and product information from the VPD.
+ */
+static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
+			size_t size, u8 const *data)
+{
+	if (type == VPD_TYPE_INVALID)
+		return 0;
+
+	if (id == VPD_BLOCK_HWID && version == 1 && size >= 1) {
+		vpd->product_id = data[0];
+	} else if (id == VPD_BLOCK_NETWORK && version == 1) {
+		if (size >= VPD_MAC_ADDRESS_LENGTH) {
+			memcpy(vpd->mac, data, VPD_MAC_ADDRESS_LENGTH);
+			vpd->flags |= VPD_FLAG_VALID_MAC;
+		}
+	}
+
+	return 0;
+}
+
+static int read_spi_vpd(struct vpd_cache *cache,
+		 int (*process_block)(struct vpd_cache *, u8 id, u8 version,
+				      u8 type, size_t size, u8 const *data))
+{
+	static const int size = B1X5V2_GE_VPD_SIZE;
+	struct udevice *dev;
+	int ret;
+	u8 *data;
+
+	ret = uclass_get_device_by_name(UCLASS_SPI_FLASH, "m25p80@0", &dev);
+	if (ret)
+		return ret;
+
+	data = malloc(size);
+	if (!data)
+		return -ENOMEM;
+
+	ret = spi_flash_read_dm(dev, B1X5V2_GE_VPD_OFFSET, size, data);
+	if (ret) {
+		free(data);
+		return ret;
+	}
+
+	ret = vpd_reader(size, data, cache, process_block);
+
+	free(data);
+
+	return ret;
+}
+
+int board_init(void)
+{
+	if (!read_spi_vpd(&vpd, vpd_callback)) {
+		vpd.is_read = true;
+	}
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	setup_display();
+
+	return 0;
+}
+
+static void init_bootcause(void)
+{
+	const char *cause;
+
+	/* We care about WDOG only, treating everything else as
+	 * a power-on-reset.
+	 */
+	if (get_imx_reset_cause() & 0x0010)
+		cause = "WDOG";
+	else
+		cause = "POR";
+
+	env_set("bootcause", cause);
+}
+
+int misc_init_r(void)
+{
+	init_bootcause();
+
+	return 0;
+}
+
+#define M41T62_REG_FLAGS	0xf
+#define M41T62_FLAGS_OF		(1 << 2)
+static void check_time(void)
+{
+	struct udevice *rtc = NULL;
+	struct rtc_time tm;
+	u8 val;
+	int ret;
+
+	ret = uclass_get_device_by_name(UCLASS_RTC, "m41t62@68", &rtc);
+	if (ret) {
+		printf("Could not get RTC: %d\n", ret);
+		env_set("rtc_status", "FAIL");
+		return;
+	}
+
+	ret = dm_i2c_read(rtc, M41T62_REG_FLAGS, &val, sizeof(val));
+	if (ret) {
+		printf("Could not read RTC register: %d\n", ret);
+		env_set("rtc_status", "FAIL");
+		return;
+	}
+
+	ret = dm_rtc_reset(rtc);
+	if (ret) {
+		printf("Could not reset RTC: %d\n", ret);
+		env_set("rtc_status", "FAIL");
+		return;
+	}
+
+	if (val & M41T62_FLAGS_OF) {
+		env_set("rtc_status", "STOP");
+		return;
+	}
+
+	ret = dm_rtc_get(rtc, &tm);
+	if (ret) {
+		printf("Could not read RTC: %d\n", ret);
+		env_set("rtc_status", "FAIL");
+		return;
+	}
+
+	if (tm.tm_year > 2037) {
+		tm.tm_sec  = 0;
+		tm.tm_min  = 0;
+		tm.tm_hour = 0;
+		tm.tm_mday = 1;
+		tm.tm_wday = 2;
+		tm.tm_mon  = 1;
+		tm.tm_year = 2036;
+
+		ret = dm_rtc_set(rtc, &tm);
+		if (ret) {
+			printf("Could not update RTC: %d\n", ret);
+			env_set("rtc_status", "FAIL");
+			return;
+		}
+
+		printf("RTC behind 2037, capped to 2036 for userspace handling\n");
+		env_set("rtc_status", "2038");
+		return;
+	}
+
+	env_set("rtc_status", "OK");
+}
+
+static void process_vpd(struct vpd_cache *vpd)
+{
+	if (!vpd->is_read) {
+		printf("VPD wasn't read\n");
+		return;
+	}
+
+	if (vpd->flags & VPD_FLAG_VALID_MAC) {
+		eth_env_set_enetaddr_by_index("eth", 0, vpd->mac);
+		env_set("ethact", "eth0");
+	}
+}
+
+int board_late_init(void)
+{
+	process_vpd(&vpd);
+
+	if (vpd.product_id >= PRODUCT_TYPE_B105V2 &&
+	    vpd.product_id <= PRODUCT_TYPE_B155V2) {
+		set_env_per_board_type((enum product_type)vpd.product_id);
+	} else {
+		b1x5v2_board_type_autodetect();
+	}
+
+	printf("Board: GE %s\n", env_get("devicetype"));
+
+	check_time();
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	char *rtc_status = env_get("rtc_status");
+
+	fdt_setprop(blob, 0, "ge,boot-ver", version_string,
+	                                    strlen(version_string) + 1);
+	fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
+	                                    strlen(rtc_status) + 1);
+
+	return 0;
+}
+#endif
+
+static int do_b1x5v2_autodetect(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	int err;
+
+	err = b1x5v2_board_type_autodetect();
+	if (!err)
+		printf("Identified %s\n", env_get("devicetype"));
+
+	return 0;
+}
+
+U_BOOT_CMD(
+       autodetect_devtype, 1,      1,      do_b1x5v2_autodetect,
+       "autodetect b1x5v2 device type",
+       ""
+);
+
+#endif // CONFIG_SPL_BUILD
diff --git a/roms/u-boot/board/ge/b1x5v2/spl.c b/roms/u-boot/board/ge/b1x5v2/spl.c
new file mode 100644
index 000000000..52c80f792
--- /dev/null
+++ b/roms/u-boot/board/ge/b1x5v2/spl.c
@@ -0,0 +1,587 @@
+/*
+ * GE b1x5v2 - QMX6 SPL
+ *
+ * Copyright 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Copyright 2018-2020 GE Inc.
+ * Copyright 2018-2020 Collabora Ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <init.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <spl.h>
+
+#if defined(CONFIG_SPL_BUILD)
+
+#include <asm/arch/mx6-ddr.h>
+
+#define IMX6DQ_DRIVE_STRENGTH_40_OHM		0x30
+#define IMX6DQ_DRIVE_STRENGTH_48_OHM		0x28
+#define IMX6DQ_DRIVE_STRENGTH			IMX6DQ_DRIVE_STRENGTH_40_OHM
+
+#define QMX6_DDR_PKE_DISABLED			0x00000000
+#define QMX6_DDR_ODT_60_OHM			(2 << 16)
+#define QMX6_DDR_TYPE_DDR3			0x000c0000
+
+#define QMX6_DRAM_SDCKE_PULLUP_100K		0x00003000
+#define QMX6_DRAM_SDBA2_PULLUP_NONE		0x00000000
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define SPI1_CS0 IMX_GPIO_NR(3, 19)
+#define POWEROFF IMX_GPIO_NR(4, 25)
+
+static iomux_v3_cfg_t const poweroff_pads[] = {
+	IOMUX_PADS(PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+	IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+	IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
+	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
+	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke0 = QMX6_DRAM_SDCKE_PULLUP_100K,
+	.dram_sdcke1 = QMX6_DRAM_SDCKE_PULLUP_100K,
+	.dram_sdba2 = QMX6_DRAM_SDBA2_PULLUP_NONE,
+	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
+	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
+	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke0 = QMX6_DRAM_SDCKE_PULLUP_100K,
+	.dram_sdcke1 = QMX6_DRAM_SDCKE_PULLUP_100K,
+	.dram_sdba2 = QMX6_DRAM_SDBA2_PULLUP_NONE,
+	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+static struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
+	.grp_ddr_type = QMX6_DDR_TYPE_DDR3,
+	.grp_ddrmode_ctl = QMX6_DDR_ODT_60_OHM,
+	.grp_ddrpke = QMX6_DDR_PKE_DISABLED,
+	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddrmode = QMX6_DDR_ODT_60_OHM,
+	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = QMX6_DDR_TYPE_DDR3,
+	.grp_ddrmode_ctl = QMX6_DDR_ODT_60_OHM,
+	.grp_ddrpke = QMX6_DDR_PKE_DISABLED,
+	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddrmode = QMX6_DDR_ODT_60_OHM,
+	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+const struct mx6_mmdc_calibration mx6q_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x0016001A,
+	.p0_mpwldectrl1 =  0x0023001C,
+	.p1_mpwldectrl0 =  0x0028003A,
+	.p1_mpwldectrl1 =  0x001F002C,
+	.p0_mpdgctrl0 =  0x43440354,
+	.p0_mpdgctrl1 =  0x033C033C,
+	.p1_mpdgctrl0 =  0x43300368,
+	.p1_mpdgctrl1 =  0x03500330,
+	.p0_mprddlctl =  0x3228242E,
+	.p1_mprddlctl =  0x2C2C2636,
+	.p0_mpwrdlctl =  0x36323A38,
+	.p1_mpwrdlctl =  0x42324440,
+};
+
+const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x00080016,
+	.p0_mpwldectrl1 =  0x001D0016,
+	.p1_mpwldectrl0 =  0x0018002C,
+	.p1_mpwldectrl1 =  0x000D001D,
+	.p0_mpdgctrl0 =    0x43200334,
+	.p0_mpdgctrl1 =    0x0320031C,
+	.p1_mpdgctrl0 =    0x0344034C,
+	.p1_mpdgctrl1 =    0x03380314,
+	.p0_mprddlctl =    0x3E36383A,
+	.p1_mprddlctl =    0x38363240,
+	.p0_mpwrdlctl =	   0x36364238,
+	.p1_mpwrdlctl =    0x4230423E,
+};
+
+const struct mx6_mmdc_calibration mx6q_4g_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x00180018,
+	.p0_mpwldectrl1 =  0x00220018,
+	.p1_mpwldectrl0 =  0x00330046,
+	.p1_mpwldectrl1 =  0x002B003D,
+	.p0_mpdgctrl0 =    0x4344034C,
+	.p0_mpdgctrl1 =    0x033C033C,
+	.p1_mpdgctrl0 =    0x03700374,
+	.p1_mpdgctrl1 =    0x03600338,
+	.p0_mprddlctl =    0x443E3E40,
+	.p1_mprddlctl =    0x423E3E48,
+	.p0_mpwrdlctl =	   0x3C3C4442,
+	.p1_mpwrdlctl =    0x46384C46,
+};
+
+static const struct mx6_mmdc_calibration mx6s_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x00480049,
+	.p0_mpwldectrl1 =  0x00410044,
+	.p0_mpdgctrl0 =    0x42480248,
+	.p0_mpdgctrl1 =    0x023C023C,
+	.p0_mprddlctl =    0x40424644,
+	.p0_mpwrdlctl =    0x34323034,
+};
+
+static const struct mx6_mmdc_calibration mx6s_2g_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x00450048,
+	.p0_mpwldectrl1 =  0x003B003F,
+	.p0_mpdgctrl0 =    0x424C0248,
+	.p0_mpdgctrl1 =    0x0234023C,
+	.p0_mprddlctl =    0x40444848,
+	.p0_mpwrdlctl =    0x38363232,
+};
+
+static const struct mx6_mmdc_calibration mx6dl_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x0043004B,
+	.p0_mpwldectrl1 =  0x003A003E,
+	.p1_mpwldectrl0 =  0x0047004F,
+	.p1_mpwldectrl1 =  0x004E0061,
+	.p0_mpdgctrl0 =    0x42500250,
+	.p0_mpdgctrl1 =	   0x0238023C,
+	.p1_mpdgctrl0 =    0x42640264,
+	.p1_mpdgctrl1 =    0x02500258,
+	.p0_mprddlctl =    0x40424846,
+	.p1_mprddlctl =    0x46484842,
+	.p0_mpwrdlctl =    0x38382C30,
+	.p1_mpwrdlctl =    0x34343430,
+};
+
+static const struct mx6_mmdc_calibration mx6dl_2g_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x00450045,
+	.p0_mpwldectrl1 =  0x00390043,
+	.p1_mpwldectrl0 =  0x0049004D,
+	.p1_mpwldectrl1 =  0x004E0061,
+	.p0_mpdgctrl0 =    0x4240023C,
+	.p0_mpdgctrl1 =	   0x0228022C,
+	.p1_mpdgctrl0 =    0x02400244,
+	.p1_mpdgctrl1 =    0x02340238,
+	.p0_mprddlctl =    0x42464648,
+	.p1_mprddlctl =    0x4446463C,
+	.p0_mpwrdlctl =    0x3C38323A,
+	.p1_mpwrdlctl =    0x34323430,
+};
+
+static struct mx6_ddr3_cfg mem_ddr_2g = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1310,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static struct mx6_ddr3_cfg mem_ddr_4g = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1310,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static struct mx6_ddr3_cfg mem_ddr_8g = {
+	.mem_speed = 1600,
+	.density = 8,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 16,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1310,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void spl_dram_init(u8 width, u32 memsize) {
+	struct mx6_ddr_sysinfo sysinfo = {
+		 /* width of data bus: 0=16, 1=32, 2=64 */
+		.dsize		= width / 32,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density	= 32,	/* 32Gb per CS */
+
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 2,
+		.rtt_nom = 2,
+		.walat = 0,
+		.ralat = 5,
+		.mif3_mode = 3,
+		.bi_on = 1,
+		.sde_to_rst = 0x0d,
+		.rst_to_cke = 0x20,
+	};
+
+	if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+		sysinfo.walat = 1;
+		mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
+
+		switch(memsize) {
+		case 512:
+			mx6_dram_cfg(&sysinfo, &mx6s_2g_mmcd_calib, &mem_ddr_2g);
+			break;
+		default:
+			mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g);
+			break;
+		}
+	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
+		sysinfo.walat = 1;
+		mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
+
+		switch(memsize) {
+		case 2048:
+			mx6_dram_cfg(&sysinfo, &mx6dl_2g_mmcd_calib, &mem_ddr_4g);
+			break;
+		default:
+			mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g);
+			break;
+		}
+	} else if (is_cpu_type(MXC_CPU_MX6Q)) {
+		mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
+
+		switch(memsize) {
+		case 4096:
+			sysinfo.cs_density = 16;
+			sysinfo.ncs = 2;
+			mx6_dram_cfg(&sysinfo, &mx6q_4g_mmcd_calib, &mem_ddr_8g);
+			break;
+		case 2048:
+			mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
+			break;
+		default:
+			mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
+			break;
+		}
+	}
+}
+
+/* Define a minimal structure so that the part number can be read via SPL */
+#define CFG_MFG_ADDR_OFFSET	(spi->size - SZ_16K)
+struct mfgdata {
+	unsigned char tsize;
+	/* size of checksummed part in bytes */
+	unsigned char ckcnt;
+	/* checksum corrected byte */
+	unsigned char cksum;
+	/* decimal serial number, packed BCD */
+	unsigned char serial[6];
+	 /* part number, right justified, ASCII */
+	unsigned char pn[16];
+};
+
+static void conv_ascii(unsigned char *dst, unsigned char *src, int len)
+{
+	int remain = len;
+	unsigned char *sptr = src;
+	unsigned char *dptr = dst;
+
+	while (remain) {
+		if (*sptr) {
+			*dptr = *sptr;
+			dptr++;
+		}
+		sptr++;
+		remain--;
+	}
+	*dptr = 0x0;
+}
+
+/*
+ * Returns the total size of the memory [in MB] the board is equipped with
+ *
+ * This is determined via the partnumber which is stored in the
+ * congatec manufacturing area
+ */
+static int get_boardmem_size(struct spi_flash *spi)
+{
+	int ret;
+	int i;
+	int arraysize;
+	char buf[sizeof(struct mfgdata)];
+	struct mfgdata *data = (struct mfgdata *)buf;
+	unsigned char outbuf[32];
+	char partnumbers_2g[4][7] = { "016104", "016105", "016304", "016305" };
+	char partnumbers_4g[2][7] = { "016308", "016318" };
+	char partnumbers_512m[2][7] = { "016203", "616300" };
+
+	ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata),
+			     buf);
+	if (ret)
+		return 1024; /* default to 1GByte in case of error */
+
+	conv_ascii(outbuf, data->pn, sizeof(data->pn));
+
+	printf("Detected Congatec QMX6 SOM: %s\n", outbuf);
+
+	/* congatec PN 016104, 016105, 016304, 016305 have 2GiB of RAM */
+	arraysize = sizeof(partnumbers_2g) / sizeof(partnumbers_2g[0]);
+	for (i=0; i < arraysize; i++) {
+		if (!memcmp(outbuf,partnumbers_2g[i],6))
+			return 2048;
+	}
+
+	/* congatec PN 016308, 016318 have 4GiB of RAM */
+	arraysize = sizeof(partnumbers_4g) / sizeof(partnumbers_4g[0]);
+	for (i=0; i < arraysize; i++) {
+		if (!memcmp(outbuf,partnumbers_4g[i],6))
+			return 4096;
+	}
+
+	/* congatec PN 016203, 616300 has 512MiB of RAM */
+	arraysize = sizeof(partnumbers_512m) / sizeof(partnumbers_512m[0]);
+	for (i=0; i < arraysize; i++) {
+		if (!memcmp(outbuf,partnumbers_512m[i],6))
+			return 512;
+	}
+
+	/* default to 1GByte */
+	return 1024;
+}
+
+void reset_cpu(void)
+{
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	if (bus == 0 && cs == 0)
+		return (SPI1_CS0);
+	else
+		return -1;
+}
+
+static void memory_init(void) {
+	struct spi_flash *spi;
+	u8 width;
+	u32 size;
+
+	SETUP_IOMUX_PADS(ecspi1_pads);
+	gpio_direction_output(SPI1_CS0, 0);
+
+	spi = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+			      CONFIG_ENV_SPI_CS,
+			      CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+	if (!spi)
+		panic("Cannot identify board type: SPI-NOR flash module not detected\n");
+
+	/* lock manufacturer area */
+	spi_flash_protect(spi, CFG_MFG_ADDR_OFFSET, SZ_16K, true);
+
+	width = is_cpu_type(MXC_CPU_MX6SOLO) ? 32 : 64;
+	size = get_boardmem_size(spi);
+	printf("Detected Memory Size: %u\n", size);
+
+	spl_dram_init(width, size);
+}
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	static const uint32_t ccgr0 =
+		MXC_CCM_CCGR0_AIPS_TZ1_MASK |
+		MXC_CCM_CCGR0_AIPS_TZ2_MASK |
+		MXC_CCM_CCGR0_APBHDMA_MASK |
+		MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK |
+		MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+		MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+		MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK;
+
+	static const uint32_t ccgr1 =
+		MXC_CCM_CCGR1_ECSPI1S_MASK |
+		MXC_CCM_CCGR1_ENET_MASK |
+		MXC_CCM_CCGR1_EPIT1S_MASK |
+		MXC_CCM_CCGR1_EPIT2S_MASK |
+		MXC_CCM_CCGR1_GPT_BUS_MASK;
+
+	static const uint32_t ccgr2 =
+		MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK |
+		MXC_CCM_CCGR2_IPMUX1_MASK |
+		MXC_CCM_CCGR2_IPMUX2_MASK |
+		MXC_CCM_CCGR2_IPMUX3_MASK |
+		MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK |
+		MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK |
+		MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK;
+
+	static const uint32_t ccgr3 =
+		MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK |
+		MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK |
+		MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK |
+		MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK |
+		MXC_CCM_CCGR3_OCRAM_MASK;
+
+	static const uint32_t ccgr4 =
+		MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK |
+		MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK |
+		MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK |
+		MXC_CCM_CCGR4_PWM1_MASK |
+		MXC_CCM_CCGR4_PWM2_MASK |
+		MXC_CCM_CCGR4_PWM3_MASK |
+		MXC_CCM_CCGR4_PWM4_MASK;
+
+	static const uint32_t ccgr5 =
+		MXC_CCM_CCGR5_ROM_MASK |
+		MXC_CCM_CCGR5_SDMA_MASK |
+		MXC_CCM_CCGR5_UART_MASK |
+		MXC_CCM_CCGR5_UART_SERIAL_MASK;
+
+	static const uint32_t ccgr6 =
+		MXC_CCM_CCGR6_USBOH3_MASK |
+		MXC_CCM_CCGR6_USDHC1_MASK |
+		MXC_CCM_CCGR6_USDHC2_MASK |
+		MXC_CCM_CCGR6_SIM1_CLK_MASK |
+		MXC_CCM_CCGR6_SIM2_CLK_MASK;
+
+	writel(ccgr0, &ccm->CCGR0);
+	writel(ccgr1, &ccm->CCGR1);
+	writel(ccgr2, &ccm->CCGR2);
+	writel(ccgr3, &ccm->CCGR3);
+	writel(ccgr4, &ccm->CCGR4);
+	writel(ccgr5, &ccm->CCGR5);
+	writel(ccgr6, &ccm->CCGR6);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup clock gating */
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* setup AXI */
+	gpr_init();
+
+	/*
+	 * setup poweroff GPIO. This controls system power regulator. Once
+	 * the power button is released this must be enabled to keep system
+	 * running. Not enabling it (or disabling it later) will turn off
+	 * the main system regulator and instantly poweroff the system. We
+	 * do this very early, to reduce the time users have to press the
+	 * power button.
+	 */
+	SETUP_IOMUX_PADS(poweroff_pads);
+	gpio_direction_output(POWEROFF, 1);
+
+	/* setup GP timer */
+	timer_init();
+
+	/* iomux */
+	if (CONFIG_MXC_UART_BASE == UART2_BASE)
+		SETUP_IOMUX_PADS(uart2_pads);
+	else if (CONFIG_MXC_UART_BASE == UART3_BASE)
+		SETUP_IOMUX_PADS(uart3_pads);
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* Needed for malloc() [used by SPI] to work in SPL prior to board_init_r() */
+	spl_init();
+
+	/* DDR initialization */
+	memory_init();
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	printf("Load normal U-Boot...\n");
+}
+#endif
diff --git a/roms/u-boot/board/ge/bx50v3/Kconfig b/roms/u-boot/board/ge/bx50v3/Kconfig
new file mode 100644
index 000000000..05938560a
--- /dev/null
+++ b/roms/u-boot/board/ge/bx50v3/Kconfig
@@ -0,0 +1,20 @@
+if TARGET_GE_BX50V3
+
+config IMX_CONFIG
+	default "board/ge/bx50v3/bx50v3.cfg"
+
+config SYS_BOARD
+	default "bx50v3"
+
+config SYS_VENDOR
+	default "ge"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "ge_bx50v3"
+
+source "board/ge/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/ge/bx50v3/MAINTAINERS b/roms/u-boot/board/ge/bx50v3/MAINTAINERS
new file mode 100644
index 000000000..fafbd78c2
--- /dev/null
+++ b/roms/u-boot/board/ge/bx50v3/MAINTAINERS
@@ -0,0 +1,14 @@
+GE BX50V3 BOARD
+M:	Ian Ray <ian.ray@ge.com>
+M:	Sebastian Reichel <sebastian.reichel@collabora.com>
+S:	Maintained
+F:	arch/arm/dts/imx6q-b450v3.dts
+F:	arch/arm/dts/imx6q-b650v3.dts
+F:	arch/arm/dts/imx6q-b850v3.dts
+F:	arch/arm/dts/imx6q-bx50v3*
+F:	board/ge/bx50v3/
+F:	configs/ge_b450v3_defconfig
+F:	configs/ge_b650v3_defconfig
+F:	configs/ge_b850v3_defconfig
+F:	configs/ge_bx50v3_defconfig
+F:	include/configs/ge_bx50v3.h
diff --git a/roms/u-boot/board/ge/bx50v3/Makefile b/roms/u-boot/board/ge/bx50v3/Makefile
new file mode 100644
index 000000000..9b80e7c24
--- /dev/null
+++ b/roms/u-boot/board/ge/bx50v3/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2015 Timesys Corporation
+# Copyright 2015 General Electric Company
+
+obj-y  := bx50v3.o
diff --git a/roms/u-boot/board/ge/bx50v3/bx50v3.c b/roms/u-boot/board/ge/bx50v3/bx50v3.c
new file mode 100644
index 000000000..7fcebba02
--- /dev/null
+++ b/roms/u-boot/board/ge/bx50v3/bx50v3.c
@@ -0,0 +1,596 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015 Timesys Corporation
+ * Copyright 2015 General Electric Company
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ */
+
+#include <image.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <env.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/libfdt.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <power/regulator.h>
+#include <power/da9063_pmic.h>
+#include <power/pmic.h>
+#include <input.h>
+#include <pwm.h>
+#include <version.h>
+#include <stdlib.h>
+#include <dm/root.h>
+#include "../common/ge_rtc.h"
+#include "../common/vpd_reader.h"
+#include "../../../drivers/net/e1000.h"
+#include <pci.h>
+#include <panel.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define VPD_PRODUCT_B850 1
+#define VPD_PRODUCT_B650 2
+#define VPD_PRODUCT_B450 3
+
+#define AR8033_DBG_REG_ADDR		0x1d
+#define AR8033_DBG_REG_DATA		0x1e
+#define AR8033_SERDES_REG		0x5
+
+static int productid;  /* Default to generic. */
+static struct vpd_cache vpd;
+
+#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/*
+	 * Set reserved bits to avoid board specific voltage peak issue. The
+	 * value is a magic number provided directly by Qualcomm. Note, that
+	 * PHY driver will take control of BIT(8) in this register to control
+	 * TX clock delay, so we do not initialize that bit here.
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_ADDR, AR8033_SERDES_REG);
+	phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_DATA, 0x3c47);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static void do_enable_backlight(struct display_info_t const *dev)
+{
+	struct udevice *panel;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
+	if (ret) {
+		printf("Could not find panel: %d\n", ret);
+		return;
+	}
+
+	panel_set_backlight(panel, 100);
+	panel_enable_backlight(panel);
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static int is_b850v3(void)
+{
+	return productid == VPD_PRODUCT_B850;
+}
+
+static int detect_lcd(struct display_info_t const *dev)
+{
+	return !is_b850v3();
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= -1,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_lcd,
+	.enable	= do_enable_backlight,
+	.mode	= {
+		.name           = "G121X1-L03",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 20,
+		.right_margin   = 300,
+		.upper_margin   = 30,
+		.lower_margin   = 8,
+		.hsync_len      = 1,
+		.vsync_len      = 1,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 3,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void enable_videopll(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	s32 timeout = 100000;
+
+	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	/* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
+	 *   |
+	 * PLL5
+	 *   |
+	 * CS2CDR[LDB_DI0_CLK_SEL]
+	 *   |
+	 *   +----> LDB_DI0_SERIAL_CLK_ROOT
+	 *   |
+	 *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
+	 */
+
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+			BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+			BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
+			BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+	clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	while (timeout--)
+		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+			break;
+
+	if (timeout < 0)
+		printf("Warning: video pll lock timeout!\n");
+
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_BYPASS,
+			BM_ANADIG_PLL_VIDEO_ENABLE);
+}
+
+static void setup_display_b850v3(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	enable_videopll();
+
+	/* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
+	setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+	imx_setup_hdmi();
+
+	/* Set LDB_DI0 as clock source for IPU_DI0 */
+	clrsetbits_le32(&mxc_ccm->chsccdr,
+			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+			(CHSCCDR_CLK_SEL_LDB_DI0 <<
+			 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+	/* Turn on IPU LDB DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+	enable_ipu_clock();
+
+	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+	       IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
+	       IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+	       IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+	       IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
+	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+	       IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
+	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
+	       IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
+	       &iomux->gpr[2]);
+
+	clrbits_le32(&iomux->gpr[3],
+		     IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+		     IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
+		     IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
+}
+
+static void setup_display_bx50v3(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	enable_videopll();
+
+	/* When a reset/reboot is performed the display power needs to be turned
+	 * off for atleast 500ms. The boot time is ~300ms, we need to wait for
+	 * an additional 200ms here. Unfortunately we use external PMIC for
+	 * doing the reset, so can not differentiate between POR vs soft reset
+	 */
+	mdelay(200);
+
+	/* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
+	setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+	/* Set LDB_DI0 as clock source for IPU_DI0 */
+	clrsetbits_le32(&mxc_ccm->chsccdr,
+			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+			(CHSCCDR_CLK_SEL_LDB_DI0 <<
+			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+	/* Turn on IPU LDB DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+	enable_ipu_clock();
+
+	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+	       IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+	       &iomux->gpr[2]);
+
+	clrsetbits_le32(&iomux->gpr[3],
+			IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
+		       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+			IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#define VPD_TYPE_INVALID 0x00
+#define VPD_BLOCK_NETWORK 0x20
+#define VPD_BLOCK_HWID 0x44
+#define VPD_HAS_MAC1 0x1
+#define VPD_HAS_MAC2 0x2
+#define VPD_MAC_ADDRESS_LENGTH 6
+
+struct vpd_cache {
+	bool is_read;
+	u8 product_id;
+	u8 has;
+	unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
+	unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
+};
+
+/*
+ * Extracts MAC and product information from the VPD.
+ */
+static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
+			size_t size, u8 const *data)
+{
+	if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
+	    size >= 1) {
+		vpd->product_id = data[0];
+	} else if (id == VPD_BLOCK_NETWORK && version == 1 &&
+		   type != VPD_TYPE_INVALID) {
+		if (size >= 6) {
+			vpd->has |= VPD_HAS_MAC1;
+			memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
+		}
+		if (size >= 12) {
+			vpd->has |= VPD_HAS_MAC2;
+			memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
+		}
+	}
+
+	return 0;
+}
+
+static void process_vpd(struct vpd_cache *vpd)
+{
+	int fec_index = 0;
+	int i210_index = -1;
+
+	if (!vpd->is_read) {
+		printf("VPD wasn't read");
+		return;
+	}
+
+	if (vpd->has & VPD_HAS_MAC1)
+		eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
+
+	env_set("ethact", "eth0");
+
+	switch (vpd->product_id) {
+	case VPD_PRODUCT_B450:
+		i210_index = 1;
+		break;
+	case VPD_PRODUCT_B650:
+		i210_index = 1;
+		break;
+	case VPD_PRODUCT_B850:
+		i210_index = 2;
+		break;
+	}
+
+	if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
+		eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
+}
+
+static iomux_v3_cfg_t const misc_pads[] = {
+	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_A25__GPIO5_IO02	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_CS0__GPIO2_IO23	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_CS1__GPIO2_IO24	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_OE__GPIO2_IO25	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
+};
+#define SUS_S3_OUT	IMX_GPIO_NR(4, 11)
+#define PWGIN_IN	IMX_GPIO_NR(4, 14)
+#define WIFI_EN	IMX_GPIO_NR(6, 14)
+
+int board_early_init_f(void)
+{
+	imx_iomux_v3_setup_multiple_pads(misc_pads,
+					 ARRAY_SIZE(misc_pads));
+
+#if defined(CONFIG_VIDEO_IPUV3)
+	/* Set LDB clock to Video PLL */
+	select_ldb_di_clock_source(MXC_PLL5_CLK);
+#endif
+	return 0;
+}
+
+int board_init(void)
+{
+	if (!read_i2c_vpd(&vpd, vpd_callback)) {
+		int ret, rescan;
+
+		vpd.is_read = true;
+		productid = vpd.product_id;
+
+		ret = fdtdec_resetup(&rescan);
+		if (!ret && rescan) {
+			dm_uninit();
+			dm_init_and_scan(false);
+		}
+	}
+
+	gpio_request(SUS_S3_OUT, "sus_s3_out");
+	gpio_direction_output(SUS_S3_OUT, 1);
+
+	gpio_request(PWGIN_IN, "pwgin_in");
+	gpio_direction_input(PWGIN_IN);
+
+	gpio_request(WIFI_EN, "wifi_en");
+	gpio_direction_output(WIFI_EN, 1);
+
+#if defined(CONFIG_VIDEO_IPUV3)
+	if (is_b850v3())
+		setup_display_b850v3();
+	else
+		setup_display_bx50v3();
+#endif
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+
+/*
+ * The SoM used by these boards has XTAL not connected despite datasheet
+ * suggesting connecting unused XTAL pins to ground. Without explicitly
+ * clearing the CRYSTAL bit the system runs unstable and sometimes reboots
+ * unexpectedly.
+ */
+static void pmic_crystal_fix(void)
+{
+	struct udevice *pmic;
+	static const uint EN_32K_CRYSTAL = (1 << 3);
+
+	if (pmic_get("pmic@58", &pmic)) {
+		puts("failed to get device for PMIC\n");
+		return;
+	}
+
+	if (pmic_clrsetbits(pmic, DA9063_REG_EN_32K, EN_32K_CRYSTAL, 0) < 0) {
+		puts("failed to clear CRYSTAL bit\n");
+		return;
+	}
+}
+
+void pmic_init(void)
+{
+	struct udevice *reg;
+	int ret, i;
+	static const char * const bucks[] = {
+		"bcore1",
+		"bcore2",
+		"bpro",
+		"bmem",
+		"bio",
+		"bperi",
+	};
+
+	pmic_crystal_fix();
+
+	for (i = 0; i < ARRAY_SIZE(bucks); i++) {
+		ret = regulator_get_by_devname(bucks[i], &reg);
+		if (reg < 0) {
+			printf("%s(): Unable to get regulator %s: %d\n",
+			       __func__, bucks[i], ret);
+			continue;
+		}
+		regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
+	}
+}
+
+static void detect_boot_cause(void)
+{
+	const char *cause = "POR";
+
+	if (is_b850v3())
+		if (!gpio_get_value(PWGIN_IN))
+			cause = "PM_WDOG";
+
+	env_set("bootcause", cause);
+}
+
+int board_late_init(void)
+{
+	process_vpd(&vpd);
+
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	if (is_b850v3())
+		env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
+	else
+		env_set("videoargs", "video=LVDS-1:1024x768@65");
+
+	detect_boot_cause();
+
+	/* board specific pmic init */
+	pmic_init();
+
+	check_time();
+
+	pci_init();
+
+	return 0;
+}
+
+/*
+ * Removes the 'eth[0-9]*addr' environment variable with the given index
+ *
+ * @param index [in] the index of the eth_device whose variable is to be removed
+ */
+static void remove_ethaddr_env_var(int index)
+{
+	char env_var_name[9];
+
+	sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
+	env_set(env_var_name, NULL);
+}
+
+int last_stage_init(void)
+{
+	int i;
+
+	/*
+	 * Remove first three ethaddr which may have been created by
+	 * function process_vpd().
+	 */
+	for (i = 0; i < 3; ++i)
+		remove_ethaddr_env_var(i);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("BOARD: %s\n", CONFIG_BOARD_NAME);
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	char *rtc_status = env_get("rtc_status");
+
+	fdt_setprop(blob, 0, "ge,boot-ver", version_string,
+		    strlen(version_string) + 1);
+
+	fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
+		    strlen(rtc_status) + 1);
+	return 0;
+}
+#endif
+
+int board_fit_config_name_match(const char *name)
+{
+	const char *machine = name;
+
+	if (!vpd.is_read)
+		return strcmp(name, "imx6q-bx50v3");
+
+	if (!strncmp(machine, "Boot ", 5))
+		machine += 5;
+	if (!strncmp(machine, "imx6q-", 6))
+		machine += 6;
+
+	switch (vpd.product_id) {
+	case VPD_PRODUCT_B450:
+		return strcasecmp(machine, "b450v3");
+	case VPD_PRODUCT_B650:
+		return strcasecmp(machine, "b650v3");
+	case VPD_PRODUCT_B850:
+		return strcasecmp(machine, "b850v3");
+	default:
+		return -1;
+	}
+}
+
+int embedded_dtb_select(void)
+{
+	vpd.is_read = false;
+	return fdtdec_setup();
+}
diff --git a/roms/u-boot/board/ge/bx50v3/bx50v3.cfg b/roms/u-boot/board/ge/bx50v3/bx50v3.cfg
new file mode 100644
index 000000000..de3955a94
--- /dev/null
+++ b/roms/u-boot/board/ge/bx50v3/bx50v3.cfg
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* DDR IO */
+DATA 4, MX6_IOM_GRP_DDR_TYPE,	0x000c0000
+DATA 4, MX6_IOM_GRP_DDRPKE,	0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1,	0x00000030
+DATA 4, MX6_IOM_DRAM_CAS,	0x00000030
+DATA 4, MX6_IOM_DRAM_RAS,	0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS,	0x00000030
+DATA 4, MX6_IOM_DRAM_RESET,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDBA2,	0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDODT1,	0x00000030
+DATA 4, MX6_IOM_GRP_CTLDS,	0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL,	0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7,	0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE,	0x00020000
+DATA 4, MX6_IOM_GRP_B0DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B1DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B2DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B3DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B4DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B5DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B6DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B7DS,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7,	0x00000030
+
+/* Calibrations */
+/* ZQ */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL,  0xa1390003
+/* write leveling */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
+/* Read DQS Gating calibration */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0,	0x45380544
+DATA 4, MX6_MMDC_P0_MPDGCTRL1,	0x05280530
+DATA 4, MX6_MMDC_P1_MPDGCTRL0,	0x4530053C
+DATA 4, MX6_MMDC_P1_MPDGCTRL1,	0x0530050C
+/* Read calibration */
+DATA 4, MX6_MMDC_P0_MPRDDLCTL,	0x36303032
+DATA 4, MX6_MMDC_P1_MPRDDLCTL,	0x38363042
+/* Write calibration */
+DATA 4, MX6_MMDC_P0_MPWRDLCTL,	0x3A3A423E
+DATA 4, MX6_MMDC_P1_MPWRDLCTL,	0x4A38483E
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/* Complete calibration by forced measurment */
+DATA 4, MX6_MMDC_P0_MPMUR0,	0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0,	0x00000800
+
+/* MMDC init */
+DATA 4, MX6_MMDC_P0_MDPDC,	0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC,	0x09444040
+DATA 4, MX6_MMDC_P0_MDCFG0,	0x8A8F79A4
+DATA 4, MX6_MMDC_P0_MDCFG1,	0xDB538E64
+DATA 4, MX6_MMDC_P0_MDCFG2,	0x01ff00db
+DATA 4, MX6_MMDC_P0_MDMISC,	0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD,	0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR,	0x008F1023
+DATA 4, MX6_MMDC_P0_MDASP,	0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL,	0x841a0000
+
+/* Initialize Micron MT41J128M */
+DATA 4, MX6_MMDC_P0_MDSCR,	0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR,	0x0408803a
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR,	0x0000803b
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00408031
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00408039
+DATA 4, MX6_MMDC_P0_MDSCR,	0x09408030
+DATA 4, MX6_MMDC_P0_MDSCR,	0x09408038
+DATA 4, MX6_MMDC_P0_MDSCR,	0x04008040
+DATA 4, MX6_MMDC_P0_MDSCR,	0x04008048
+DATA 4, MX6_MMDC_P0_MDREF,	0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL,	0x00011117
+DATA 4, MX6_MMDC_P1_MPODTCTRL,	0x00011117
+DATA 4, MX6_MMDC_P0_MDPDC,	0x00025576
+DATA 4, MX6_MMDC_P0_MAPSR,	0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  1	   --> CKO1 enabled
+ * cko1_div 111  --> divide by 8
+ * cko1_sel 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/roms/u-boot/board/ge/common/Kconfig b/roms/u-boot/board/ge/common/Kconfig
new file mode 100644
index 000000000..323ed1f99
--- /dev/null
+++ b/roms/u-boot/board/ge/common/Kconfig
@@ -0,0 +1,7 @@
+config GE_VPD
+	bool "Enable GE VPD Support"
+	default y
+
+config GE_RTC
+	bool "Enable GE RTC Support"
+	default y
diff --git a/roms/u-boot/board/ge/common/Makefile b/roms/u-boot/board/ge/common/Makefile
new file mode 100644
index 000000000..8bd44e3c8
--- /dev/null
+++ b/roms/u-boot/board/ge/common/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2017 General Electric Company
+
+obj-$(CONFIG_GE_VPD)  += vpd_reader.o
+obj-$(CONFIG_GE_RTC)  += ge_rtc.o
diff --git a/roms/u-boot/board/ge/common/ge_rtc.c b/roms/u-boot/board/ge/common/ge_rtc.c
new file mode 100644
index 000000000..48c377804
--- /dev/null
+++ b/roms/u-boot/board/ge/common/ge_rtc.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 General Electric Company
+ */
+
+#include <common.h>
+#include <env.h>
+#include <dm/uclass.h>
+#include <rtc.h>
+
+void check_time(void)
+{
+	struct udevice *dev;
+	int ret, i;
+	struct rtc_time tm;
+	u8 retry = 3;
+
+	ret = uclass_get_device(UCLASS_RTC, 0, &dev);
+	if (ret) {
+		env_set("rtc_status", "FAIL");
+		return;
+	}
+
+	for (i = 0; i < retry; i++) {
+		ret = dm_rtc_get(dev, &tm);
+		if (!ret || ret == -EINVAL)
+			break;
+	}
+
+	if (!ret && tm.tm_year > 2037) {
+		tm.tm_sec  = 0;
+		tm.tm_min  = 0;
+		tm.tm_hour = 0;
+		tm.tm_mday = 1;
+		tm.tm_wday = 2;
+		tm.tm_mon  = 1;
+		tm.tm_year = 2036;
+
+		for (i = 0; i < retry; i++) {
+			ret = dm_rtc_set(dev, &tm);
+			if (!ret)
+				break;
+		}
+
+		if (ret >= 0)
+			ret = 2038;
+	}
+
+	if (ret < 0)
+		env_set("rtc_status", "FAIL");
+	else if (ret == 2038)
+		env_set("rtc_status", "2038");
+	else
+		env_set("rtc_status", "OK");
+}
+
diff --git a/roms/u-boot/board/ge/common/ge_rtc.h b/roms/u-boot/board/ge/common/ge_rtc.h
new file mode 100644
index 000000000..d33486d08
--- /dev/null
+++ b/roms/u-boot/board/ge/common/ge_rtc.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 General Electric Company
+ */
+
+void check_time(void);
diff --git a/roms/u-boot/board/ge/common/vpd_reader.c b/roms/u-boot/board/ge/common/vpd_reader.c
new file mode 100644
index 000000000..c28d2c03c
--- /dev/null
+++ b/roms/u-boot/board/ge/common/vpd_reader.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 General Electric Company
+ */
+
+#include "vpd_reader.h"
+#include <malloc.h>
+
+#include <i2c.h>
+#include <linux/bch.h>
+#include <stdlib.h>
+#include <dm/uclass.h>
+#include <i2c_eeprom.h>
+#include <hexdump.h>
+
+/* BCH configuration */
+
+const struct {
+	int header_ecc_capability_bits;
+	int data_ecc_capability_bits;
+	unsigned int prim_poly;
+	struct {
+		int min;
+		int max;
+	} galois_field_order;
+} bch_configuration = {
+	.header_ecc_capability_bits = 4,
+	.data_ecc_capability_bits = 16,
+	.prim_poly = 0,
+	.galois_field_order = {
+		.min = 5,
+		.max = 15,
+	},
+};
+
+static int calculate_galois_field_order(size_t source_length)
+{
+	int gfo = bch_configuration.galois_field_order.min;
+
+	for (; gfo < bch_configuration.galois_field_order.max &&
+	     ((((1 << gfo) - 1) - ((int)source_length * 8)) < 0);
+	     gfo++) {
+	}
+
+	if (gfo == bch_configuration.galois_field_order.max)
+		return -1;
+
+	return gfo + 1;
+}
+
+static int verify_bch(int ecc_bits, unsigned int prim_poly, u8 *data,
+		      size_t data_length, const u8 *ecc, size_t ecc_length)
+{
+	int gfo = calculate_galois_field_order(data_length);
+
+	if (gfo < 0)
+		return -1;
+
+	struct bch_control *bch = init_bch(gfo, ecc_bits, prim_poly);
+
+	if (!bch)
+		return -1;
+
+	if (bch->ecc_bytes != ecc_length) {
+		free_bch(bch);
+		return -1;
+	}
+
+	unsigned int *errloc = (unsigned int *)calloc(data_length,
+						      sizeof(unsigned int));
+	int errors = decode_bch(bch, data, data_length, ecc, NULL, NULL,
+				errloc);
+
+	free_bch(bch);
+	if (errors < 0) {
+		free(errloc);
+		return -1;
+	}
+
+	if (errors > 0) {
+		for (int n = 0; n < errors; n++) {
+			if (errloc[n] >= 8 * data_length) {
+				/*
+				 * n-th error located in ecc (no need for data
+				 * correction)
+				 */
+			} else {
+				/* n-th error located in data */
+				data[errloc[n] / 8] ^= 1 << (errloc[n] % 8);
+			}
+		}
+	}
+
+	free(errloc);
+	return 0;
+}
+
+static const int ID;
+static const int LEN = 1;
+static const int VER = 2;
+static const int TYP = 3;
+static const int BLOCK_SIZE = 4;
+
+static const u8 HEADER_BLOCK_ID;
+static const u8 HEADER_BLOCK_LEN = 18;
+static const u32 HEADER_BLOCK_MAGIC = 0xca53ca53;
+static const size_t HEADER_BLOCK_VERIFY_LEN = 14;
+static const size_t HEADER_BLOCK_ECC_OFF = 14;
+static const size_t HEADER_BLOCK_ECC_LEN = 4;
+
+static const u8 ECC_BLOCK_ID = 0xFF;
+
+int vpd_reader(size_t size, u8 *data, struct vpd_cache *userdata,
+	       int (*fn)(struct vpd_cache *, u8 id, u8 version, u8 type,
+			 size_t size, u8 const *data))
+{
+	if (size < HEADER_BLOCK_LEN || !data || !fn)
+		return -EINVAL;
+
+	/*
+	 * +--------------------+----------------+--//--+--------------------+
+	 * | header block       | data block     | ...  | ecc block          |
+	 * +--------------------+----------------+--//--+--------------------+
+	 * :                    :                       :
+	 * +------+-------+-----+                       +------+-------------+
+	 * | id   | magic | ecc |                       | ...  | ecc         |
+	 * | len  | off   |     |                       +------+-------------+
+	 * | ver  | size  |     |                       :
+	 * | type |       |     |                       :
+	 * +------+-------+-----+                       :
+	 * :              :     :                       :
+	 * <----- [1] ---->     <--------- [2] --------->
+	 *
+	 * Repair (if necessary) the contents of header block [1] by using a
+	 * 4 byte ECC located at the end of the header block.  A successful
+	 * return value means that we can trust the header.
+	 */
+	int ret = verify_bch(bch_configuration.header_ecc_capability_bits,
+			     bch_configuration.prim_poly, data,
+			     HEADER_BLOCK_VERIFY_LEN,
+			     &data[HEADER_BLOCK_ECC_OFF], HEADER_BLOCK_ECC_LEN);
+	if (ret < 0)
+		return ret;
+
+	/* Validate header block { id, length, version, type }. */
+	if (data[ID] != HEADER_BLOCK_ID || data[LEN] != HEADER_BLOCK_LEN ||
+	    data[VER] != 0 || data[TYP] != 0 ||
+	    ntohl(*(u32 *)(&data[4])) != HEADER_BLOCK_MAGIC)
+		return -EINVAL;
+
+	u32 offset = ntohl(*(u32 *)(&data[8]));
+	u16 size_bits = ntohs(*(u16 *)(&data[12]));
+
+	/* Check that ECC header fits. */
+	if (offset + 3 >= size)
+		return -EINVAL;
+
+	/* Validate ECC block. */
+	u8 *ecc = &data[offset];
+
+	if (ecc[ID] != ECC_BLOCK_ID || ecc[LEN] < BLOCK_SIZE ||
+	    ecc[LEN] + offset > size ||
+	    ecc[LEN] - BLOCK_SIZE != size_bits / 8 || ecc[VER] != 1 ||
+	    ecc[TYP] != 1)
+		return -EINVAL;
+
+	/*
+	 * Use the header block to locate the ECC block and verify the data
+	 * blocks [2] against the ecc block ECC.
+	 */
+	ret = verify_bch(bch_configuration.data_ecc_capability_bits,
+			 bch_configuration.prim_poly, &data[data[LEN]],
+			 offset - data[LEN], &data[offset + BLOCK_SIZE],
+			 ecc[LEN] - BLOCK_SIZE);
+	if (ret < 0)
+		return ret;
+
+	/* Stop after ECC.  Ignore possible zero padding. */
+	size = offset;
+
+	for (;;) {
+		/* Move to next block. */
+		size -= data[LEN];
+		data += data[LEN];
+
+		if (size == 0) {
+			/* Finished iterating through blocks. */
+			return 0;
+		}
+
+		if (size < BLOCK_SIZE || data[LEN] < BLOCK_SIZE) {
+			/* Not enough data for a header, or short header. */
+			return -EINVAL;
+		}
+
+		ret = fn(userdata, data[ID], data[VER], data[TYP],
+			 data[LEN] - BLOCK_SIZE, &data[BLOCK_SIZE]);
+		if (ret)
+			return ret;
+	}
+}
+
+int read_i2c_vpd(struct vpd_cache *cache,
+		 int (*process_block)(struct vpd_cache *, u8 id, u8 version,
+				      u8 type, size_t size, u8 const *data))
+{
+	struct udevice *dev;
+	int ret;
+	u8 *data;
+	int size;
+
+	ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd@0", &dev);
+	if (ret)
+		return ret;
+
+	size = i2c_eeprom_size(dev);
+	if (size < 0) {
+		printf("Unable to get size of eeprom: %d\n", ret);
+		return ret;
+	}
+
+	data = malloc(size);
+	if (!data)
+		return -ENOMEM;
+
+	ret = i2c_eeprom_read(dev, 0, data, size);
+	if (ret) {
+		free(data);
+		return ret;
+	}
+
+	ret = vpd_reader(size, data, cache, process_block);
+
+	free(data);
+
+	return ret;
+}
diff --git a/roms/u-boot/board/ge/common/vpd_reader.h b/roms/u-boot/board/ge/common/vpd_reader.h
new file mode 100644
index 000000000..0c51dc57e
--- /dev/null
+++ b/roms/u-boot/board/ge/common/vpd_reader.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 General Electric Company
+ */
+
+#include "common.h"
+
+struct vpd_cache;
+
+/*
+ * Read VPD from given data, verify content, call callback for each vital
+ * product data block.
+ *
+ * cache: structure used by process block to store VPD information
+ * process_block: callback called for each VPD data block
+ *
+ * Returns Non-zero on error.  Negative numbers encode errno.
+ */
+int read_i2c_vpd(struct vpd_cache *cache,
+		 int (*process_block)(struct vpd_cache *, u8 id, u8 version,
+				      u8 type, size_t size, u8 const *data));
+
+/*
+ * Read VPD from given data, verify content, call callback for each vital
+ * product data block.
+ *
+ * size: size of the raw VPD data in bytes
+ * data: raw VPD data read from device
+ * cache: structure used by process block to store VPD information
+ * process_block: callback called for each VPD data block
+ *
+ * Returns Non-zero on error.  Negative numbers encode errno.
+ */
+
+int vpd_reader(size_t size, u8 *data, struct vpd_cache *cache,
+	       int (*process_block)(struct vpd_cache *, u8 id, u8 version, u8 type,
+				    size_t size, u8 const *data));
diff --git a/roms/u-boot/board/ge/mx53ppd/Kconfig b/roms/u-boot/board/ge/mx53ppd/Kconfig
new file mode 100644
index 000000000..bebb2fab0
--- /dev/null
+++ b/roms/u-boot/board/ge/mx53ppd/Kconfig
@@ -0,0 +1,18 @@
+
+if TARGET_MX53PPD
+
+config SYS_BOARD
+	default "mx53ppd"
+
+config SYS_VENDOR
+	default "ge"
+
+config SYS_SOC
+	default "mx5"
+
+config SYS_CONFIG_NAME
+	default "mx53ppd"
+
+source "board/ge/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/ge/mx53ppd/MAINTAINERS b/roms/u-boot/board/ge/mx53ppd/MAINTAINERS
new file mode 100644
index 000000000..2c06c8ee8
--- /dev/null
+++ b/roms/u-boot/board/ge/mx53ppd/MAINTAINERS
@@ -0,0 +1,9 @@
+GE PPD BOARD
+M:	Antti Mäentausta <antti.maentausta@ge.com>
+M:	Ian Ray <ian.ray@ge.com>
+M:	Sebastian Reichel <sebastian.reichel@collabora.com>
+S:	Maintained
+F:	arch/arm/dts/imx53-ppd*
+F:	board/ge/mx53ppd/
+F:	configs/mx53ppd_defconfig
+F:	include/configs/mx53ppd.h
diff --git a/roms/u-boot/board/ge/mx53ppd/Makefile b/roms/u-boot/board/ge/mx53ppd/Makefile
new file mode 100644
index 000000000..f423e80ca
--- /dev/null
+++ b/roms/u-boot/board/ge/mx53ppd/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2017 General Electric Company
+#
+# Based on board/freescale/mx53loco/Makefile:
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# Jason Liu <r64343@freescale.com>
+
+obj-y			+= mx53ppd.o
+obj-$(CONFIG_DM_VIDEO)	+= mx53ppd_video.o
diff --git a/roms/u-boot/board/ge/mx53ppd/imximage.cfg b/roms/u-boot/board/ge/mx53ppd/imximage.cfg
new file mode 100644
index 000000000..1ee819839
--- /dev/null
+++ b/roms/u-boot/board/ge/mx53ppd/imximage.cfg
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 General Electric Company
+ *
+ * Based on board/freescale/mx53loco/imximage.cfg:
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x53fa8004 0x00194005
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00111740
+DATA 4 0x63fd9000 0x85190000
+DATA 4 0x63fd900c 0x8b8f52e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x008f0e21
+DATA 4 0x63fd9008 0x09333030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00468031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9040 0x05380003
+DATA 4 0x63fd9058 0x00011110
+DATA 4 0x63fd901c 0x00000000
diff --git a/roms/u-boot/board/ge/mx53ppd/mx53ppd.c b/roms/u-boot/board/ge/mx53ppd/mx53ppd.c
new file mode 100644
index 000000000..6174125e7
--- /dev/null
+++ b/roms/u-boot/board/ge/mx53ppd/mx53ppd.c
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 General Electric Company
+ *
+ * Based on board/freescale/mx53loco/mx53loco.c:
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <env.h>
+#include <linux/errno.h>
+#include <linux/libfdt.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/mx5_video.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <asm/gpio.h>
+#include <power/pmic.h>
+#include <dialog_pmic.h>
+#include <fsl_pmic.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <version.h>
+#include <watchdog.h>
+#include "ppd_gpio.h"
+#include <stdlib.h>
+#include "../../ge/common/ge_rtc.h"
+#include "../../ge/common/vpd_reader.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
+{
+	/*
+	 * WARNING: We must override get_effective_memsize() function here
+	 * to report only the size of the first DRAM bank. This is to make
+	 * U-Boot relocator place U-Boot into valid memory, that is, at the
+	 * end of the first DRAM bank. If we did not override this function
+	 * like so, U-Boot would be placed at the address of the first DRAM
+	 * bank + total DRAM size - sizeof(uboot), which in the setup where
+	 * each DRAM bank contains 512MiB of DRAM would result in placing
+	 * U-Boot into invalid memory area close to the end of the first
+	 * DRAM bank.
+	 */
+	return mx53_dram_size[0];
+}
+
+int dram_init(void)
+{
+	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = mx53_dram_size[0];
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev() & ~(0xF << 8);
+}
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+	/* request VBUS power enable pin, GPIO7_8 */
+	imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
+	gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
+	return 0;
+}
+#endif
+
+static int clock_1GHz(void)
+{
+	int ret;
+	u32 ref_clk = MXC_HCLK;
+	/*
+	 * After increasing voltage to 1.25V, we can switch
+	 * CPU clock to 1GHz and DDR to 400MHz safely
+	 */
+	ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+	if (ret) {
+		printf("CPU:   Switch CPU clock to 1GHZ failed\n");
+		return -1;
+	}
+
+	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+	if (ret) {
+		printf("CPU:   Switch DDR clock to 400MHz failed\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+void ppd_gpio_init(void)
+{
+	int i;
+
+	imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads));
+	for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i) {
+		gpio_request(ppd_gpios[i].gpio, "request");
+		gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value);
+	}
+}
+
+int board_early_init_f(void)
+{
+	ppd_gpio_init();
+
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#define VPD_TYPE_INVALID 0x00
+#define VPD_BLOCK_NETWORK 0x20
+#define VPD_BLOCK_HWID 0x44
+#define VPD_PRODUCT_PPD 4
+#define VPD_HAS_MAC1 0x1
+#define VPD_MAC_ADDRESS_LENGTH 6
+
+struct vpd_cache {
+	u8 product_id;
+	u8 has;
+	unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
+};
+
+/*
+ * Extracts MAC and product information from the VPD.
+ */
+static int vpd_callback(struct vpd_cache *userdata, u8 id, u8 version,
+			u8 type, size_t size, u8 const *data)
+{
+	struct vpd_cache *vpd = userdata;
+
+	if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
+	    size >= 1) {
+		vpd->product_id = data[0];
+
+	} else if (id == VPD_BLOCK_NETWORK && version == 1 &&
+		   type != VPD_TYPE_INVALID) {
+		if (size >= 6) {
+			vpd->has |= VPD_HAS_MAC1;
+			memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
+		}
+	}
+
+	return 0;
+}
+
+static void process_vpd(struct vpd_cache *vpd)
+{
+	int fec_index = -1;
+
+	if (vpd->product_id == VPD_PRODUCT_PPD)
+		fec_index = 0;
+
+	if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
+		eth_env_set_enetaddr("ethaddr", vpd->mac1);
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	mxc_set_sata_internal_clock();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	const char *cause;
+
+	/* We care about WDOG only, treating everything else as
+	 * a power-on-reset.
+	 */
+	if (get_imx_reset_cause() & 0x0010)
+		cause = "WDOG";
+	else
+		cause = "POR";
+
+	env_set("bootcause", cause);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	int res;
+	struct vpd_cache vpd;
+
+	memset(&vpd, 0, sizeof(vpd));
+	res = read_i2c_vpd(&vpd, vpd_callback);
+	if (!res)
+		process_vpd(&vpd);
+	else
+		printf("Can't read VPD");
+
+	res = clock_1GHz();
+	if (res != 0)
+		return res;
+
+	print_cpuinfo();
+
+	check_time();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: GE PPD\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	char *rtc_status = env_get("rtc_status");
+
+	fdt_setprop(blob, 0, "ge,boot-ver", version_string,
+		    strlen(version_string) + 1);
+
+	fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
+		    strlen(rtc_status) + 1);
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/ge/mx53ppd/mx53ppd_video.c b/roms/u-boot/board/ge/mx53ppd/mx53ppd_video.c
new file mode 100644
index 000000000..3240ed62a
--- /dev/null
+++ b/roms/u-boot/board/ge/mx53ppd/mx53ppd_video.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 General Electric Company
+ *
+ * Based on board/freescale/mx53loco/mx53loco_video.c:
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/list.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/mach-imx/video.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <panel.h>
+
+static int detect_lcd(struct display_info_t const *dev)
+{
+	return 1;
+}
+
+static void lcd_enable(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* Set LDB_DI0 as clock source for IPU_DI0 */
+	clrsetbits_le32(&mxc_ccm->cscmr2,
+			MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK,
+			MXC_CCM_CSCMR2_DI0_CLK_SEL(
+				MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK));
+
+	/* Turn on IPU LDB DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3));
+
+	/* Turn on IPU DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3));
+
+	/* Configure LDB */
+	writel(IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+		IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+		IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+		&iomux->gpr[2]);
+}
+
+static void do_enable_backlight(struct display_info_t const *dev)
+{
+	struct udevice *panel;
+	int ret;
+
+	lcd_enable();
+
+	ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
+	if (ret) {
+		printf("Could not find panel: %d\n", ret);
+		return;
+	}
+
+	panel_set_backlight(panel, 100);
+	panel_enable_backlight(panel);
+}
+
+struct display_info_t const displays[] = {
+	{
+		.bus	= -1,
+		.addr	= -1,
+		.pixfmt	= IPU_PIX_FMT_RGB24,
+		.detect	= detect_lcd,
+		.enable	= do_enable_backlight,
+		.mode = {
+			.name		= "NV-SPWGRGB888",
+			.refresh	= 60,
+			.xres		= 800,
+			.yres		= 480,
+			.pixclock	= 15384,
+			.left_margin	= 16,
+			.right_margin	= 210,
+			.upper_margin	= 10,
+			.lower_margin	= 22,
+			.hsync_len	= 30,
+			.vsync_len	= 13,
+			.sync		= FB_SYNC_EXT,
+			.vmode		= FB_VMODE_NONINTERLACED
+		}
+	}
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
diff --git a/roms/u-boot/board/ge/mx53ppd/ppd_gpio.h b/roms/u-boot/board/ge/mx53ppd/ppd_gpio.h
new file mode 100644
index 000000000..98c41d4d6
--- /dev/null
+++ b/roms/u-boot/board/ge/mx53ppd/ppd_gpio.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 General Electric Company
+ */
+
+#ifndef __PPD_GPIO_H_
+#define __PPD_GPIO_H_
+
+#include <asm/arch/iomux-mx53.h>
+#include <asm/gpio.h>
+
+static const iomux_v3_cfg_t ppd_pads[] = {
+	/* FEC */
+	MX53_PAD_EIM_A22__GPIO2_16,
+	/* Video */
+	MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */
+	MX53_PAD_CSI0_VSYNC__GPIO5_21,	 /* UD_SCAN_CTRL */
+	MX53_PAD_CSI0_DAT10__GPIO5_28,	 /* DATA_WIDTH_CTRL */
+	MX53_PAD_CSI0_PIXCLK__GPIO5_18,	 /* HOST_CONTROLLED_RESET_TO_LCD_N */
+	MX53_PAD_EIM_DA2__GPIO3_2,	 /* LVDS1_MUX_CTRL */
+	MX53_PAD_EIM_DA3__GPIO3_3,	 /* LVDS0_MUX_CTRL */
+	MX53_PAD_EIM_A21__GPIO2_17,	 /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */
+	MX53_PAD_CSI0_DAT11__GPIO5_29,	 /* BACKLIGHT_ENABLE */
+	MX53_PAD_DISP0_DAT9__PWM2_PWMO,	 /* IMX535_PWM2_TO_LCD_CONNECTOR */
+	/* I2C */
+	MX53_PAD_EIM_A20__GPIO2_18,	 /* RESET_I2C1_BUS_SEGMENT_MUX_N */
+
+	/* SPI */
+	MX53_PAD_DISP0_DAT23__GPIO5_17,
+	MX53_PAD_KEY_COL2__GPIO4_10,
+	MX53_PAD_KEY_ROW2__GPIO4_11,
+	MX53_PAD_KEY_COL3__GPIO4_12,
+
+	MX53_PAD_PATA_DATA7__GPIO2_7,    /* BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */
+};
+
+struct gpio_cfg {
+	unsigned int gpio;
+	int value;
+};
+
+#define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16)
+#define UD_SCAN_CTRL IMX_GPIO_NR(5, 21)
+#define LR_SCAN_CTRL IMX_GPIO_NR(5, 20)
+#define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3)
+#define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2)
+#define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18)
+#define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28)
+#define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28)
+#define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29)
+#define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22)
+#define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27)
+#define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17)
+#define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18)
+#define ECSPI1_CS0 IMX_GPIO_NR(5, 17)
+#define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
+#define ECSPI1_CS2 IMX_GPIO_NR(4, 11)
+#define ECSPI1_CS3 IMX_GPIO_NR(4, 12)
+#define BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N IMX_GPIO_NR(2, 7)
+
+static const struct gpio_cfg ppd_gpios[] = {
+	/* FEC */
+	/* Drive Low as GPIO output for 25ms per Eth Phy IX spec */
+	/* Then Drive High as GPIO output to bring Eth Phy IC out of reset */
+	{ RESET_IMX535_ETHERNET_PHY_N, 0 },
+	{ RESET_IMX535_ETHERNET_PHY_N, 1 },
+	/* Video */
+	{ UD_SCAN_CTRL, 0 },
+	{ LR_SCAN_CTRL, 1 },
+#ifdef PROPRIETARY_CHANGES
+	{ LVDS0_MUX_CTRL, 1 },
+#else
+	{ LVDS0_MUX_CTRL, 0 },
+#endif
+	{ LVDS1_MUX_CTRL, 1 },
+	{ HOST_CONTROLLED_RESET_TO_LCD_N, 1 },
+	{ DATA_WIDTH_CTRL, 0 },
+	{ RESET_DP0_TRANSMITTER_N, 1 },
+	{ RESET_DP1_TRANSMITTER_N, 1 },
+	{ POWER_DOWN_LVDS0_DESERIALIZER_N, 1 },
+	{ POWER_DOWN_LVDS1_DESERIALIZER_N, 1 },
+	{ ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 },
+	{ RESET_I2C1_BUS_SEGMENT_MUX_N, 1 },
+	{ ECSPI1_CS0, 1 },
+	{ ECSPI1_CS1, 1 },
+	{ ECSPI1_CS2, 1 },
+	{ ECSPI1_CS3, 1 },
+	{ BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N, 1 },
+};
+
+#endif /* __PPD_GPIO_H_ */
diff --git a/roms/u-boot/board/geekbuying/geekbox/Kconfig b/roms/u-boot/board/geekbuying/geekbox/Kconfig
new file mode 100644
index 000000000..41aa8fbe0
--- /dev/null
+++ b/roms/u-boot/board/geekbuying/geekbox/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_GEEKBOX
+
+config SYS_BOARD
+	default "geekbox"
+
+config SYS_VENDOR
+	default "geekbuying"
+
+config SYS_CONFIG_NAME
+	default "geekbox"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/geekbuying/geekbox/MAINTAINERS b/roms/u-boot/board/geekbuying/geekbox/MAINTAINERS
new file mode 100644
index 000000000..7a4989f94
--- /dev/null
+++ b/roms/u-boot/board/geekbuying/geekbox/MAINTAINERS
@@ -0,0 +1,6 @@
+GEEKBOX
+M:	Andreas Färber <afaerber@suse.de>
+S:	Maintained
+F:	board/geekbuying/geekbox
+F:	include/configs/geekbox.h
+F:	configs/geekbox_defconfig
diff --git a/roms/u-boot/board/geekbuying/geekbox/Makefile b/roms/u-boot/board/geekbuying/geekbox/Makefile
new file mode 100644
index 000000000..ced2ff75a
--- /dev/null
+++ b/roms/u-boot/board/geekbuying/geekbox/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2016 Andreas Färber
+
+obj-y	+= geekbox.o
diff --git a/roms/u-boot/board/geekbuying/geekbox/README b/roms/u-boot/board/geekbuying/geekbox/README
new file mode 100644
index 000000000..de980f2f2
--- /dev/null
+++ b/roms/u-boot/board/geekbuying/geekbox/README
@@ -0,0 +1 @@
+see board/rockchip/sheep_rk3368/README
diff --git a/roms/u-boot/board/geekbuying/geekbox/geekbox.c b/roms/u-boot/board/geekbuying/geekbox/geekbox.c
new file mode 100644
index 000000000..b0f9a5f9b
--- /dev/null
+++ b/roms/u-boot/board/geekbuying/geekbox/geekbox.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016 Andreas Färber
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/google/Kconfig b/roms/u-boot/board/google/Kconfig
new file mode 100644
index 000000000..22c4be392
--- /dev/null
+++ b/roms/u-boot/board/google/Kconfig
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+
+if VENDOR_GOOGLE
+
+choice
+	prompt "Mainboard model"
+	optional
+
+config TARGET_CHROMEBOOK_CORAL
+	bool "Chromebook coral"
+	help
+	  This is a range of Intel-based laptops released in 2018. They use an
+	  Intel Apollo Lake SoC. The design supports WiFi, 4GB to 16GB of
+	  LPDDR4 1600MHz SDRAM, PCIe WiFi and Bluetooth, eMMC (typically 32GB),
+	  up two cameras (front-facing 720p and another 5MP option), USB SD
+	  reader, microphone and speakers. It also includes two USB 3 Type A and
+	  two Type C ports. The latter are used as power input and can also
+	  charge external devices as well as a 4K external display. There is a
+	  Chrome OS EC connected on LPC, a Cr50 secure chip from Google and
+	  various display options. OEMs products include Acer Chromebook 11
+	  (e.g. C732, CB11, CP311) and Lenovo Chromebook (100e, 300e, 500e).
+
+config TARGET_CHROMEBOOK_LINK
+	bool "Chromebook link"
+	help
+	  This is the Chromebook Pixel released in 2013. It uses an Intel
+	  i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
+	  SDRAM. It has a Panther Point platform controller hub, PCIe
+	  WiFi and Bluetooth. It also includes a 720p webcam, USB SD
+	  reader, microphone and speakers, display port and 32GB SATA
+	  solid state drive. There is a Chrome OS EC connected on LPC,
+	  and it provides a 2560x1700 high resolution touch-enabled LCD
+	  display.
+
+config TARGET_CHROMEBOOK_LINK64
+	bool "Chromebook link 64-bit"
+	help
+	  This is the Chromebook Pixel released in 2013. With this config
+	  U-Boot is built as a 64-bit binary. This allows testing while this
+	  feature is being completed.
+
+config TARGET_CHROMEBOX_PANTHER
+	bool "Chromebox panther (not available)"
+	help
+	  Note: At present this must be used with coreboot. See README.x86
+	  for instructions.
+
+	  This is the Asus Chromebox CN60 released in 2014. It uses an Intel
+	  Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
+	  Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also
+	  includes a USB SD reader, four USB3 ports, display port and HDMI
+	  video output and a 16GB SATA solid state drive. There is no Chrome
+	  OS EC on this model.
+
+config TARGET_CHROMEBOOK_SAMUS
+	bool "Chromebook samus"
+	help
+	  This is the Chromebook Pixel released in 2015. It uses an Intel
+	  Broadwell U Core i5 or Core i7 CPU with either 8GB or 16GB of
+	  LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
+	  720p webcam, USB SD reader, microphone and speakers, 2 USB 3 Type
+	  C ports which can support charging and up to a 4K external display.
+	  There is a solid state drive, either 32GB or 64GB. There is a
+	  Chrome OS EC connected on LPC, and it provides a 2560x1700 high
+	  resolution touch-enabled LCD display.
+
+config TARGET_CHROMEBOOK_SAMUS_TPL
+	bool "Chromebook samus booting from TPL"
+	help
+	  This is a version of Samus which boots into TPL, then to SPL and
+	  U-Boot proper. This is useful where verified boot must select
+	  between different A/B versions of SPL/U-Boot, to allow upgrading of
+	  almost all U-Boot code in the field.
+
+endchoice
+
+source "board/google/chromebook_coral/Kconfig"
+source "board/google/chromebook_link/Kconfig"
+source "board/google/chromebox_panther/Kconfig"
+source "board/google/chromebook_samus/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/google/chromebook_coral/Kconfig b/roms/u-boot/board/google/chromebook_coral/Kconfig
new file mode 100644
index 000000000..53c651c3f
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/Kconfig
@@ -0,0 +1,44 @@
+if TARGET_CHROMEBOOK_CORAL
+
+config SYS_BOARD
+	default "chromebook_coral"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_SOC
+	default "apollolake"
+
+config SYS_CONFIG_NAME
+	default "chromebook_coral"
+
+config SYS_TEXT_BASE
+	default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select USE_EARLY_BOARD_INIT
+	select INTEL_APOLLOLAKE
+	select BOARD_ROMSIZE_KB_16384
+
+config PCIE_ECAM_BASE
+	default 0xe0000000
+
+config EARLY_POST_CROS_EC
+	bool "Enable early post to Chrome OS EC"
+	help
+	  Allow post codes to be sent to the Chroem OS EC early during boot,
+	  to enable monitoring of the boot and debugging when things go wrong.
+	  With this option enabled, the EC console can be used to watch post
+	  codes the first part of boot.
+
+config SYS_CAR_ADDR
+	hex
+	default 0xfef00000
+
+config SYS_CAR_SIZE
+	hex
+	default 0xc0000
+
+endif
diff --git a/roms/u-boot/board/google/chromebook_coral/MAINTAINERS b/roms/u-boot/board/google/chromebook_coral/MAINTAINERS
new file mode 100644
index 000000000..904227e2e
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOOK_CORAL_BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_coral/
+F:	include/configs/chromebook_coral.h
+F:	configs/chromebook_coral_defconfig
diff --git a/roms/u-boot/board/google/chromebook_coral/Makefile b/roms/u-boot/board/google/chromebook_coral/Makefile
new file mode 100644
index 000000000..f7a0ca6cc
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Google LLC
+
+obj-y	+= coral.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/roms/u-boot/board/google/chromebook_coral/baseboard_dptf.asl b/roms/u-boot/board/google/chromebook_coral/baseboard_dptf.asl
new file mode 100644
index 000000000..5da963a67
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/baseboard_dptf.asl
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ */
+
+#define DPTF_CPU_PASSIVE	95
+#define DPTF_CPU_CRITICAL	105
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"Battery"
+#define DPTF_TSR0_PASSIVE	120
+#define DPTF_TSR0_CRITICAL	125
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"Ambient"
+#define DPTF_TSR1_PASSIVE	46
+#define DPTF_TSR1_CRITICAL	75
+
+#define DPTF_TSR2_SENSOR_ID	2
+#define DPTF_TSR2_SENSOR_NAME	"Charger"
+#define DPTF_TSR2_PASSIVE	58
+#define DPTF_TSR2_CRITICAL	90
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 },	/* 3A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
+})
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Charger Effect on Temp Sensor 2 */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
+#endif
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		3000,	/* PowerLimitMinimum */
+		12000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
diff --git a/roms/u-boot/board/google/chromebook_coral/coral.c b/roms/u-boot/board/google/chromebook_coral/coral.c
new file mode 100644
index 000000000..3f9235c90
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/coral.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#define LOG_CATEGORY	UCLASS_SYSINFO
+
+#include <common.h>
+#include <bloblist.h>
+#include <command.h>
+#include <cros_ec.h>
+#include <dm.h>
+#include <log.h>
+#include <sysinfo.h>
+#include <acpi/acpigen.h>
+#include <asm-generic/gpio.h>
+#include <asm/acpi_nhlt.h>
+#include <asm/intel_gnvs.h>
+#include <asm/intel_pinctrl.h>
+#include <dm/acpi.h>
+#include <linux/delay.h>
+#include "variant_gpio.h"
+
+struct cros_gpio_info {
+	const char *linux_name;
+	enum cros_gpio_t type;
+	int gpio_num;
+	int flags;
+};
+
+int arch_misc_init(void)
+{
+	return 0;
+}
+
+static int get_memconfig(struct udevice *dev)
+{
+	struct gpio_desc gpios[4];
+	int cfg;
+	int ret;
+
+	ret = gpio_request_list_by_name(dev, "memconfig-gpios", gpios,
+					ARRAY_SIZE(gpios),
+					GPIOD_IS_IN | GPIOD_PULL_UP);
+	if (ret < 0) {
+		log_debug("Cannot get GPIO list '%s' (%d)\n", dev->name, ret);
+		return ret;
+	}
+
+	/* Give the lines time to settle */
+	udelay(10);
+
+	ret = dm_gpio_get_values_as_int(gpios, ARRAY_SIZE(gpios));
+	if (ret < 0)
+		return log_msg_ret("get", ret);
+	cfg = ret;
+
+	ret = gpio_free_list(dev, gpios, ARRAY_SIZE(gpios));
+	if (ret)
+		return log_msg_ret("free", ret);
+
+	return cfg;
+}
+
+/**
+ * get_skuconfig() - Get the SKU number either from pins or the EC
+ *
+ * Two options are supported:
+ *     skuconfig-gpios - two pins in the device tree (tried first)
+ *     EC              - reading from the EC (backup)
+ *
+ * @dev: sysinfo device to use
+ * @return SKU ID, or -ve error if not found
+ */
+static int get_skuconfig(struct udevice *dev)
+{
+	struct gpio_desc gpios[2];
+	int cfg;
+	int ret;
+
+	ret = gpio_request_list_by_name(dev, "skuconfig-gpios", gpios,
+					ARRAY_SIZE(gpios),
+					GPIOD_IS_IN);
+	if (ret != ARRAY_SIZE(gpios)) {
+		struct udevice *cros_ec;
+
+		log_debug("Cannot get GPIO list '%s' (%d)\n", dev->name, ret);
+
+		/* Try the EC */
+		ret = uclass_first_device_err(UCLASS_CROS_EC, &cros_ec);
+		if (ret < 0) {
+			log_err("Cannot find EC for SKU details\n");
+			return log_msg_ret("sku", ret);
+		}
+		ret = cros_ec_get_sku_id(cros_ec);
+		if (ret < 0) {
+			log_err("Cannot read SKU details\n");
+			return log_msg_ret("sku", ret);
+		}
+
+		return ret;
+	}
+
+	ret = dm_gpio_get_values_as_int_base3(gpios, ARRAY_SIZE(gpios));
+	if (ret < 0)
+		return log_msg_ret("get", ret);
+	cfg = ret;
+
+	ret = gpio_free_list(dev, gpios, ARRAY_SIZE(gpios));
+	if (ret)
+		return log_msg_ret("free", ret);
+
+	return cfg;
+}
+
+static int coral_get_str(struct udevice *dev, int id, size_t size, char *val)
+{
+	int ret;
+
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		return -ENOSYS;
+
+	switch (id) {
+	case SYSINFO_ID_SMBIOS_SYSTEM_VERSION:
+	case SYSINFO_ID_SMBIOS_BASEBOARD_VERSION: {
+		ret = get_skuconfig(dev);
+
+		if (ret < 0)
+			return ret;
+		if (size < 15)
+			return -ENOSPC;
+		sprintf(val, "rev%d", ret);
+		break;
+	}
+	case SYSINFO_ID_BOARD_MODEL: {
+		int mem_config, sku_config;
+		const char *model;
+
+		ret = get_memconfig(dev);
+		if (ret < 0)
+			log_warning("Unable to read memconfig (err=%d)\n", ret);
+		mem_config = ret;
+		ret = get_skuconfig(dev);
+		if (ret < 0)
+			log_warning("Unable to read skuconfig (err=%d)\n", ret);
+		sku_config = ret;
+		model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+		snprintf(val, size, "%s (memconfig %d, SKU %d)", model,
+			 mem_config, sku_config);
+		break;
+	}
+	default:
+		return -ENOENT;
+	}
+
+	return 0;
+}
+
+int chromeos_get_gpio(const struct udevice *dev, const char *prop,
+		      enum cros_gpio_t type, struct cros_gpio_info *info)
+{
+	struct udevice *pinctrl;
+	struct gpio_desc desc;
+	int ret;
+
+	ret = gpio_request_by_name((struct udevice *)dev, prop, 0, &desc, 0);
+	if (ret == -ENOTBLK) {
+		info->gpio_num = CROS_GPIO_VIRTUAL;
+		log_debug("GPIO '%s' is virtual\n", prop);
+	} else if (ret) {
+		return log_msg_ret("gpio", ret);
+	} else {
+		info->gpio_num = desc.offset;
+		dm_gpio_free((struct udevice *)dev, &desc);
+	}
+	info->linux_name = dev_read_string(desc.dev, "linux-name");
+	if (!info->linux_name)
+		return log_msg_ret("linux-name", -ENOENT);
+	info->type = type;
+	/* Get ACPI pin from GPIO library if available */
+	if (info->gpio_num != CROS_GPIO_VIRTUAL) {
+		pinctrl = dev_get_parent(desc.dev);
+		info->gpio_num = intel_pinctrl_get_acpi_pin(pinctrl,
+							    info->gpio_num);
+	}
+	info->flags = desc.flags & GPIOD_ACTIVE_LOW ? CROS_GPIO_ACTIVE_LOW :
+		CROS_GPIO_ACTIVE_HIGH;
+	if (!ret)
+		dm_gpio_free(desc.dev, &desc);
+
+	return 0;
+}
+
+static int chromeos_acpi_gpio_generate(const struct udevice *dev,
+				       struct acpi_ctx *ctx)
+{
+	struct cros_gpio_info info[3];
+	int count, i;
+	int ret;
+
+	count = 3;
+	ret = chromeos_get_gpio(dev, "recovery-gpios", CROS_GPIO_REC, &info[0]);
+	if (ret)
+		return log_msg_ret("rec", ret);
+	ret = chromeos_get_gpio(dev, "write-protect-gpios", CROS_GPIO_WP,
+				&info[1]);
+	if (ret)
+		return log_msg_ret("wp", ret);
+	ret = chromeos_get_gpio(dev, "phase-enforce-gpios", CROS_GPIO_PE,
+				&info[2]);
+	if (ret)
+		return log_msg_ret("phase", ret);
+	acpigen_write_scope(ctx, "\\");
+	acpigen_write_name(ctx, "OIPG");
+	acpigen_write_package(ctx, count);
+	for (i = 0; i < count; i++) {
+		acpigen_write_package(ctx, 4);
+		acpigen_write_integer(ctx, info[i].type);
+		acpigen_write_integer(ctx, info[i].flags);
+		acpigen_write_integer(ctx, info[i].gpio_num);
+		acpigen_write_string(ctx, info[i].linux_name);
+		acpigen_pop_len(ctx);
+	}
+
+	acpigen_pop_len(ctx);
+	acpigen_pop_len(ctx);
+
+	return 0;
+}
+
+static int coral_write_acpi_tables(const struct udevice *dev,
+				   struct acpi_ctx *ctx)
+{
+	struct acpi_global_nvs *gnvs;
+	struct nhlt *nhlt;
+	const char *oem_id = "coral";
+	const char *oem_table_id = "coral";
+	u32 oem_revision = 3;
+	int ret;
+
+	gnvs = bloblist_find(BLOBLISTT_ACPI_GNVS, sizeof(*gnvs));
+	if (!gnvs)
+		return log_msg_ret("bloblist", -ENOENT);
+
+	nhlt = nhlt_init();
+	if (!nhlt)
+		return -ENOMEM;
+
+	log_debug("Setting up NHLT\n");
+	ret = acpi_setup_nhlt(ctx, nhlt);
+	if (ret)
+		return log_msg_ret("setup", ret);
+
+	/* Update NHLT GNVS Data */
+	gnvs->nhla = (uintptr_t)ctx->current;
+	gnvs->nhll = nhlt_current_size(nhlt);
+
+	ret = nhlt_serialise_oem_overrides(ctx, nhlt, oem_id, oem_table_id,
+					   oem_revision);
+	if (ret)
+		return log_msg_ret("serialise", ret);
+
+	return 0;
+}
+
+struct acpi_ops coral_acpi_ops = {
+	.write_tables	= coral_write_acpi_tables,
+	.inject_dsdt	= chromeos_acpi_gpio_generate,
+};
+
+struct sysinfo_ops coral_sysinfo_ops = {
+	.get_str	= coral_get_str,
+};
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+static const struct udevice_id coral_ids[] = {
+	{ .compatible = "google,coral" },
+	{ }
+};
+#endif
+
+U_BOOT_DRIVER(coral_drv) = {
+	.name		= "coral",
+	.id		= UCLASS_SYSINFO,
+	.of_match	= of_match_ptr(coral_ids),
+	.ops		= &coral_sysinfo_ops,
+	ACPI_OPS_PTR(&coral_acpi_ops)
+};
diff --git a/roms/u-boot/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat b/roms/u-boot/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
new file mode 100644
index 000000000..46c0efbd0
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
diff --git a/roms/u-boot/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat b/roms/u-boot/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
new file mode 100644
index 000000000..6a7f2cef4
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
diff --git a/roms/u-boot/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat b/roms/u-boot/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
new file mode 100644
index 000000000..71d764820
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
diff --git a/roms/u-boot/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat b/roms/u-boot/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
new file mode 100644
index 000000000..142ab353f
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
diff --git a/roms/u-boot/board/google/chromebook_coral/dsdt.asl b/roms/u-boot/board/google/chromebook_coral/dsdt.asl
new file mode 100644
index 000000000..b51e0b050
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/dsdt.asl
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+#include "variant_ec.h"
+#include "variant_gpio.h"
+#include <acpi/acpi_table.h>
+#include <asm/acpi/global_nvs.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	OEM_TABLE_ID,
+	0x20110725	// OEM revision
+)
+{
+	/* global NVS and variables */
+	#include <asm/arch/acpi/globalnvs.asl>
+
+	/* CPU */
+	#include <asm/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <asm/arch/acpi/northbridge.asl>
+			#include <asm/arch/acpi/southbridge.asl>
+			#include <asm/arch/acpi/pch_hda.asl>
+		}
+	}
+
+	/* Chrome OS specific */
+	#include <asm/acpi/chromeos.asl>
+
+	/* Chipset specific sleep states */
+	#include <asm/acpi/sleepstates.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <asm/acpi/cros_ec/superio.asl>
+		/* ACPI code for EC functions */
+		#include <asm/acpi/cros_ec/ec.asl>
+	}
+
+	/* Dynamic Platform Thermal Framework */
+	Scope (\_SB)
+	{
+		/* Per board variant specific definitions. */
+		#include "variant_dptf.asl"
+		/* Include soc specific DPTF changes */
+		#include <asm/arch/acpi/dptf.asl>
+		/* Include common dptf ASL files */
+		#include <asm/acpi/dptf/dptf.asl>
+	}
+}
diff --git a/roms/u-boot/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat b/roms/u-boot/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
new file mode 100644
index 000000000..b0b5b9ba6
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
diff --git a/roms/u-boot/board/google/chromebook_coral/variant_dptf.asl b/roms/u-boot/board/google/chromebook_coral/variant_dptf.asl
new file mode 100644
index 000000000..943ebeaac
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/variant_dptf.asl
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+#include "baseboard_dptf.asl"
diff --git a/roms/u-boot/board/google/chromebook_coral/variant_ec.h b/roms/u-boot/board/google/chromebook_coral/variant_ec.h
new file mode 100644
index 000000000..7d5e1a674
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/variant_ec.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+/*
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include "variant_gpio.h"
+#include <ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS	(MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
+
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif
diff --git a/roms/u-boot/board/google/chromebook_coral/variant_gpio.h b/roms/u-boot/board/google/chromebook_coral/variant_gpio.h
new file mode 100644
index 000000000..403e2419a
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_coral/variant_gpio.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ *
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
+
+#include <asm/arch/gpio.h>
+#include <ec_commands.h>
+
+/*
+ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
+ * which is North community
+ */
+#define EC_SCI_GPI	GPE0_DW1_11
+
+/* EC SMI */
+#define EC_SMI_GPI	GPIO_49
+
+/*
+ * On lidopen/lidclose GPIO_22 from North Community gets toggled and
+ * is used in _PRW to wake up device from sleep. GPIO_22 maps to
+ * group GPIO_GPE_N_31_0 and the pad is configured as SCI with
+ * EDGE_SINGLE and INVERT.
+ */
+#define GPE_EC_WAKE	GPE0_DW1_22
+
+/* Write Protect and indication if EC is in RW code. */
+#define GPIO_PCH_WP	GPIO_75
+#define GPIO_EC_IN_RW	GPIO_41
+/* Determine if board is in final shipping mode. */
+#define GPIO_SHIP_MODE	GPIO_10
+
+/* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */
+#define DMIC_CONFIG_PIN	GPIO_17
+
+#ifndef __ASSEMBLY__
+
+enum cros_gpio_t {
+	CROS_GPIO_REC = 1,	 /* Recovery */
+
+	/* Developer; * deprecated (chromium:942901) */
+	CROS_GPIO_DEPRECATED_DEV = 2,
+	CROS_GPIO_WP = 3,	/* Write Protect */
+	CROS_GPIO_PE = 4,	/* Phase enforcement for final product */
+
+	CROS_GPIO_ACTIVE_LOW = 0,
+	CROS_GPIO_ACTIVE_HIGH = 1,
+
+	CROS_GPIO_VIRTUAL = -1,
+};
+#endif
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/roms/u-boot/board/google/chromebook_link/Kconfig b/roms/u-boot/board/google/chromebook_link/Kconfig
new file mode 100644
index 000000000..dd29ddf69
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_link/Kconfig
@@ -0,0 +1,43 @@
+if TARGET_CHROMEBOOK_LINK || TARGET_CHROMEBOOK_LINK64
+
+config SYS_BOARD
+	default "chromebook_link"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_SOC
+	default "ivybridge"
+
+config SYS_CONFIG_NAME
+	default "chromebook_link"
+
+config SYS_TEXT_BASE
+	default 0xfff00000 if !SUPPORT_SPL
+	default 0x10000000 if SUPPORT_SPL
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select USE_EARLY_BOARD_INIT
+	select NORTHBRIDGE_INTEL_IVYBRIDGE
+	select HAVE_INTEL_ME
+	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
+
+config PCIE_ECAM_BASE
+	default 0xf0000000
+
+config EARLY_POST_CROS_EC
+	bool "Enable early post to Chrome OS EC"
+	default y
+
+config SYS_CAR_ADDR
+	hex
+	default 0xff7e0000
+
+config SYS_CAR_SIZE
+	hex
+	default 0x20000
+
+endif
diff --git a/roms/u-boot/board/google/chromebook_link/MAINTAINERS b/roms/u-boot/board/google/chromebook_link/MAINTAINERS
new file mode 100644
index 000000000..e7aef5339
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_link/MAINTAINERS
@@ -0,0 +1,13 @@
+CHROMEBOOK LINK BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_link/
+F:	include/configs/chromebook_link.h
+F:	configs/chromebook_link_defconfig
+
+CHROMEBOOK LINK 64-bit BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_link/
+F:	include/configs/chromebook_link.h
+F:	configs/chromebook_link64_defconfig
diff --git a/roms/u-boot/board/google/chromebook_link/Makefile b/roms/u-boot/board/google/chromebook_link/Makefile
new file mode 100644
index 000000000..d84a84899
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_link/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+
+obj-y	+= link.o
diff --git a/roms/u-boot/board/google/chromebook_link/link.c b/roms/u-boot/board/google/chromebook_link/link.c
new file mode 100644
index 000000000..e357e6218
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_link/link.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Google, Inc
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/google/chromebook_samus/Kconfig b/roms/u-boot/board/google/chromebook_samus/Kconfig
new file mode 100644
index 000000000..9f66d7998
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_samus/Kconfig
@@ -0,0 +1,52 @@
+if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL
+
+config SYS_BOARD
+	default "chromebook_samus"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_SOC
+	default "broadwell"
+
+config SYS_CONFIG_NAME
+	default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS
+	default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL
+
+config SYS_TEXT_BASE
+	default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select USE_EARLY_BOARD_INIT
+	select INTEL_BROADWELL
+	select HAVE_INTEL_ME
+	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
+
+config PCIE_ECAM_BASE
+	default 0xf0000000
+
+config EARLY_POST_CROS_EC
+	bool "Enable early post to Chrome OS EC"
+	default y
+
+config SYS_CAR_ADDR
+	hex
+	default 0xff7c0000
+
+config SYS_CAR_SIZE
+	hex
+	default 0x40000
+
+endif
+
+if TARGET_CHROMEBOOK_SAMUS_TPL
+
+config BOARD_SPECIFIC_OPTIONS_TPL # dummy
+	def_bool y
+	select SPL
+	select TPL
+
+endif
diff --git a/roms/u-boot/board/google/chromebook_samus/MAINTAINERS b/roms/u-boot/board/google/chromebook_samus/MAINTAINERS
new file mode 100644
index 000000000..ca4b16500
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_samus/MAINTAINERS
@@ -0,0 +1,13 @@
+CHROMEBOOK SAMUS BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_samus/
+F:	include/configs/chromebook_samus.h
+F:	configs/chromebook_samus_defconfig
+
+CHROMEBOOK SAMUS TPL BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_samus/
+F:	include/configs/chromebook_samus.h
+F:	configs/chromebook_samus_tpl_defconfig
diff --git a/roms/u-boot/board/google/chromebook_samus/Makefile b/roms/u-boot/board/google/chromebook_samus/Makefile
new file mode 100644
index 000000000..68c9e4993
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_samus/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2016 Google, Inc
+
+obj-y	+= samus.o
diff --git a/roms/u-boot/board/google/chromebook_samus/samus.c b/roms/u-boot/board/google/chromebook_samus/samus.c
new file mode 100644
index 000000000..83edf8910
--- /dev/null
+++ b/roms/u-boot/board/google/chromebook_samus/samus.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Google, Inc
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/google/chromebox_panther/Kconfig b/roms/u-boot/board/google/chromebox_panther/Kconfig
new file mode 100644
index 000000000..875df9d59
--- /dev/null
+++ b/roms/u-boot/board/google/chromebox_panther/Kconfig
@@ -0,0 +1,35 @@
+if TARGET_CHROMEBOX_PANTHER
+
+config SYS_BOARD
+	default "chromebox_panther"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_SOC
+	default "ivybridge"
+
+config SYS_CONFIG_NAME
+	default "chromebox_panther"
+
+config SYS_TEXT_BASE
+	default 0xfff00000
+
+# Panther actually uses haswell, not ivybridge, so this is just a placeholder
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select NORTHBRIDGE_INTEL_IVYBRIDGE
+	select HAVE_INTEL_ME
+	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
+
+config SYS_CAR_ADDR
+	hex
+	default 0xff7e0000
+
+config SYS_CAR_SIZE
+	hex
+	default 0x20000
+
+endif
diff --git a/roms/u-boot/board/google/chromebox_panther/MAINTAINERS b/roms/u-boot/board/google/chromebox_panther/MAINTAINERS
new file mode 100644
index 000000000..c88774bc8
--- /dev/null
+++ b/roms/u-boot/board/google/chromebox_panther/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOX PANTHER BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_panther/
+F:	include/configs/chromebox_panther.h
+F:	configs/chromebox_panther_defconfig
diff --git a/roms/u-boot/board/google/chromebox_panther/Makefile b/roms/u-boot/board/google/chromebox_panther/Makefile
new file mode 100644
index 000000000..1a5518f13
--- /dev/null
+++ b/roms/u-boot/board/google/chromebox_panther/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2015 Google, Inc
+
+obj-y	+= panther.o
diff --git a/roms/u-boot/board/google/chromebox_panther/panther.c b/roms/u-boot/board/google/chromebox_panther/panther.c
new file mode 100644
index 000000000..da3445bb1
--- /dev/null
+++ b/roms/u-boot/board/google/chromebox_panther/panther.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Google, Inc
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/google/common/Makefile b/roms/u-boot/board/google/common/Makefile
new file mode 100644
index 000000000..d1f45c677
--- /dev/null
+++ b/roms/u-boot/board/google/common/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2014 Google, Inc
+
+obj-$(CONFIG_X86) += early_init.o
diff --git a/roms/u-boot/board/google/common/early_init.S b/roms/u-boot/board/google/common/early_init.S
new file mode 100644
index 000000000..6ac64b338
--- /dev/null
+++ b/roms/u-boot/board/google/common/early_init.S
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 Google, Inc
+ */
+
+.globl early_board_init
+early_board_init:
+	/* Enable post codes to EC */
+#ifdef CONFIG_EARLY_POST_CROS_EC
+	mov    $0x1b, %ecx
+	rdmsr
+	and    $0x100, %eax
+	test   %eax, %eax
+	je     1f
+
+	mov    $0x8000f8f0, %eax
+	mov    $0xcf8, %dx
+	out    %eax, (%dx)
+	mov    $0xfed1c001, %eax
+	mov    $0xcfc, %dx
+	out    %eax, (%dx)
+	mov    $0xfed1f410, %esp
+	mov    (%esp), %eax
+	and    $0xfffffffb, %eax
+	mov    %eax, (%esp)
+1:
+#endif
+	jmp	early_board_init_ret
diff --git a/roms/u-boot/board/google/gru/Kconfig b/roms/u-boot/board/google/gru/Kconfig
new file mode 100644
index 000000000..61f7bbca9
--- /dev/null
+++ b/roms/u-boot/board/google/gru/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CHROMEBOOK_BOB
+
+config SYS_BOARD
+	default "gru"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "gru"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/google/gru/MAINTAINERS b/roms/u-boot/board/google/gru/MAINTAINERS
new file mode 100644
index 000000000..e1cda756b
--- /dev/null
+++ b/roms/u-boot/board/google/gru/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOOK BOB BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/gru/
+F:	include/configs/gru.h
+F:	configs/chromebook_bob_defconfig
diff --git a/roms/u-boot/board/google/gru/Makefile b/roms/u-boot/board/google/gru/Makefile
new file mode 100644
index 000000000..9117534a4
--- /dev/null
+++ b/roms/u-boot/board/google/gru/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Google LLC
+
+obj-y += gru.o
diff --git a/roms/u-boot/board/google/gru/gru.c b/roms/u-boot/board/google/gru/gru.c
new file mode 100644
index 000000000..23080c179
--- /dev/null
+++ b/roms/u-boot/board/google/gru/gru.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Google
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+
+#ifdef CONFIG_SPL_BUILD
+/* provided to defeat compiler optimisation in board_init_f() */
+void gru_dummy_function(int i)
+{
+}
+
+int board_early_init_f(void)
+{
+# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
+	int sum, i;
+
+	/*
+	 * Add a delay and ensure that the compiler does not optimise this out.
+	 * This is needed since the power rails tail a while to turn on, and
+	 * we get garbage serial output otherwise.
+	 */
+	sum = 0;
+	for (i = 0; i < 150000; i++)
+		sum += i;
+	gru_dummy_function(sum);
+#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+int board_early_init_r(void)
+{
+	struct udevice *clk;
+	int ret;
+
+	/*
+	 * This init is done in SPL, but when chain-loading U-Boot SPL will
+	 * have been skipped. Allow the clock driver to check if it needs
+	 * setting up.
+	 */
+	ret = uclass_get_device_by_driver(UCLASS_CLK,
+					  DM_DRIVER_GET(clk_rk3399), &clk);
+	if (ret) {
+		debug("%s: CLK init failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/google/imx8mq_phanbell/Kconfig b/roms/u-boot/board/google/imx8mq_phanbell/Kconfig
new file mode 100644
index 000000000..fba2e9ce6
--- /dev/null
+++ b/roms/u-boot/board/google/imx8mq_phanbell/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MQ_PHANBELL
+
+config SYS_BOARD
+	default "imx8mq_phanbell"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_phanbell"
+
+endif
diff --git a/roms/u-boot/board/google/imx8mq_phanbell/MAINTAINERS b/roms/u-boot/board/google/imx8mq_phanbell/MAINTAINERS
new file mode 100644
index 000000000..b233e6b57
--- /dev/null
+++ b/roms/u-boot/board/google/imx8mq_phanbell/MAINTAINERS
@@ -0,0 +1,8 @@
+i.MX 8MQ PHANBELL BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+M:	Marco Franchi <marcofrk@gmail.com>
+M:	Alifer Moraes <alifer.wsdm@gmail.com>
+S:	Maintained
+F:	board/google/imx8mq_phanbell/
+F:	include/configs/imx8mq_phanbell.h
+F:	configs/imx8mq_phanbell_defconfig
diff --git a/roms/u-boot/board/google/imx8mq_phanbell/Makefile b/roms/u-boot/board/google/imx8mq_phanbell/Makefile
new file mode 100644
index 000000000..d6427cf8e
--- /dev/null
+++ b/roms/u-boot/board/google/imx8mq_phanbell/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 NXP
+#
+
+obj-y += imx8mq_phanbell.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_1g.o
+endif
diff --git a/roms/u-boot/board/google/imx8mq_phanbell/README b/roms/u-boot/board/google/imx8mq_phanbell/README
new file mode 100644
index 000000000..88a136b32
--- /dev/null
+++ b/roms/u-boot/board/google/imx8mq_phanbell/README
@@ -0,0 +1,37 @@
+U-Boot for Google's i.MX8MQ Phanbell board
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr and hdmi firmware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+Note: srctree is U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_4.19.35_1.0.0
+$ make PLAT=imx8mq bl31
+$ cp build/imx8mq/release/bl31.bin $(builddir)
+
+Get the ddr and hdmi firmware
+=============================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
+$ chmod +x firmware-imx-7.9.bin
+$ ./firmware-imx-7.9.bin
+$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
+$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+============
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make imx8mq_phanbell_defconfig
+$ make flash.bin
+
+Burn the flash.bin to MicroSD card offset 33KB
+$sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=33
+
+Boot
+====
+Set Boot switch SW1: 1011 to boot from Micro SD.
diff --git a/roms/u-boot/board/google/imx8mq_phanbell/imx8mq_phanbell.c b/roms/u-boot/board/google/imx8mq_phanbell/imx8mq_phanbell.c
new file mode 100644
index 000000000..d0a740dd3
--- /dev/null
+++ b/roms/u-boot/board/google/imx8mq_phanbell/imx8mq_phanbell.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
diff --git a/roms/u-boot/board/google/imx8mq_phanbell/lpddr4_timing_1g.c b/roms/u-boot/board/google/imx8mq_phanbell/lpddr4_timing_1g.c
new file mode 100644
index 000000000..7800011a0
--- /dev/null
+++ b/roms/u-boot/board/google/imx8mq_phanbell/lpddr4_timing_1g.c
@@ -0,0 +1,1731 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa1080020},
+	{0x3d400028, 0x0},
+	{0x3d400020, 0x203},
+	{0x3d400024, 0x3e800},
+	{0x3d400064, 0x610090},
+	{0x3d4000d0, 0xc003061c},
+	{0x3d4000d4, 0x9e0000},
+	{0x3d4000dc, 0xd4002d},
+	{0x3d4000e0, 0x310008},
+	{0x3d4000e8, 0x66004a},
+	{0x3d4000ec, 0x16004a},
+	{0x3d400100, 0x1a201b22},
+	{0x3d400104, 0x60633},
+	{0x3d40010c, 0xc0c000},
+	{0x3d400110, 0xf04080f},
+	{0x3d400114, 0x2040c0c},
+	{0x3d400118, 0x1010007},
+	{0x3d40011c, 0x401},
+	{0x3d400130, 0x20600},
+	{0x3d400134, 0xc100002},
+	{0x3d400138, 0x96},
+	{0x3d400144, 0xa00050},
+	{0x3d400180, 0xc3200018},
+	{0x3d400184, 0x28061a8},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x497820a},
+	{0x3d400194, 0x80303},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001b4, 0x170a},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x1},
+	{0x3d4000f4, 0x639},
+	{0x3d400108, 0x70e1617},
+	{0x3d400200, 0x1f},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0xf070707},
+	{0x3d402020, 0x1},
+	{0x3d402024, 0xd0c0},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0x14001f},
+	{0x3d4020dc, 0x940009},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004a},
+	{0x3d4020ec, 0x16004a},
+	{0x3d402100, 0xb070508},
+	{0x3d402104, 0x3040b},
+	{0x3d402108, 0x305090c},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x4040204},
+	{0x3d402114, 0x2030303},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x20},
+	{0x3d402144, 0x220011},
+	{0x3d402180, 0xc0a70006},
+	{0x3d402190, 0x3858202},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x502},
+	{0x3d400244, 0x0},
+	{0x3d400250, 0x29001505},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x5900575b},
+	{0x3d400264, 0x90000096},
+	{0x3d40026c, 0x1000012c},
+	{0x3d400300, 0x16},
+	{0x3d400304, 0x0},
+	{0x3d40030c, 0x0},
+	{0x3d400320, 0x1},
+	{0x3d40036c, 0x11},
+	{0x3d400400, 0x111},
+	{0x3d400404, 0x10f3},
+	{0x3d400408, 0x72ff},
+	{0x3d400490, 0x1},
+	{0x3d400494, 0xe00},
+	{0x3d400498, 0x62ffff},
+	{0x3d40049c, 0xe00},
+	{0x3d4004a0, 0xffff},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x2},
+	{0x110a3, 0x3},
+	{0x110a4, 0x4},
+	{0x110a5, 0x5},
+	{0x110a6, 0x6},
+	{0x110a7, 0x7},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x2},
+	{0x120a3, 0x3},
+	{0x120a4, 0x4},
+	{0x120a5, 0x5},
+	{0x120a6, 0x6},
+	{0x120a7, 0x7},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x20110, 0x2},
+	{0x20111, 0x3},
+	{0x20112, 0x4},
+	{0x20113, 0x5},
+	{0x20114, 0x0},
+	{0x20115, 0x1},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x19},
+	{0x1200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x1},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x3},
+	{0x120056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x43, 0xe7},
+	{0x1043, 0xe7},
+	{0x2043, 0xe7},
+	{0x3043, 0xe7},
+	{0x4043, 0xe7},
+	{0x5043, 0xe7},
+	{0x6043, 0xe7},
+	{0x7043, 0xe7},
+	{0x8043, 0xe7},
+	{0x9043, 0xe7},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x320},
+	{0x120008, 0xa7},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x200f0, 0x0},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5555},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x200c7, 0x80},
+	{0x1200c7, 0x80},
+	{0x200ca, 0x106},
+	{0x1200ca, 0x106},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xc80},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x1},
+	{0x54003, 0x29c},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x994},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x994},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x9400},
+	{0x54033, 0x3109},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0x9400},
+	{0x54039, 0x3109},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xc80},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x64},
+	{0x2000c, 0xc8},
+	{0x2000d, 0x7d0},
+	{0x2000e, 0x2c},
+	{0x12000b, 0x14},
+	{0x12000c, 0x29},
+	{0x12000d, 0x1a1},
+	{0x12000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
diff --git a/roms/u-boot/board/google/imx8mq_phanbell/spl.c b/roms/u-boot/board/google/imx8mq_phanbell/spl.c
new file mode 100644
index 000000000..eec3f3d93
--- /dev/null
+++ b/roms/u-boot/board/google/imx8mq_phanbell/spl.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ *
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <init.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
+#include <linux/delay.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void spl_dram_init(void)
+{
+	/* ddr init */
+	ddr_init(&dram_timing);
+}
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR},
+	{USDHC2_BASE_ADDR},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			usdhc_cfg[0].max_bus_width = 8;
+			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+							 ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			usdhc_cfg[1].max_bus_width = 4;
+			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+							 ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/google/veyron/Kconfig b/roms/u-boot/board/google/veyron/Kconfig
new file mode 100644
index 000000000..7f55d78da
--- /dev/null
+++ b/roms/u-boot/board/google/veyron/Kconfig
@@ -0,0 +1,63 @@
+if TARGET_CHROMEBOOK_JERRY
+
+config SYS_BOARD
+	default "veyron"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+
+if TARGET_CHROMEBIT_MICKEY
+
+config SYS_BOARD
+	default "veyron"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+
+if TARGET_CHROMEBOOK_MINNIE
+
+config SYS_BOARD
+	default "veyron"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+
+if TARGET_CHROMEBOOK_SPEEDY
+
+config SYS_BOARD
+	default "veyron"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/google/veyron/MAINTAINERS b/roms/u-boot/board/google/veyron/MAINTAINERS
new file mode 100644
index 000000000..d97978076
--- /dev/null
+++ b/roms/u-boot/board/google/veyron/MAINTAINERS
@@ -0,0 +1,27 @@
+CHROMEBOOK JERRY BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/veyron/
+F:	include/configs/veyron.h
+F:	configs/chromebook_jerry_defconfig
+
+CHROMEBIT MICKEY BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/veyron/
+F:	include/configs/veyron.h
+F:	configs/chromebit_mickey_defconfig
+
+CHROMEBOOK MINNIE BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/veyron/
+F:	include/configs/veyron.h
+F:	configs/chromebook_minnie_defconfig
+
+CHROMEBOOK SPEEDY BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/veyron/
+F:	include/configs/veyron.h
+F:	configs/chromebook_speedy_defconfig
diff --git a/roms/u-boot/board/google/veyron/Makefile b/roms/u-boot/board/google/veyron/Makefile
new file mode 100644
index 000000000..98683579d
--- /dev/null
+++ b/roms/u-boot/board/google/veyron/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= veyron.o
diff --git a/roms/u-boot/board/google/veyron/veyron.c b/roms/u-boot/board/google/veyron/veyron.c
new file mode 100644
index 000000000..32dbcdc4d
--- /dev/null
+++ b/roms/u-boot/board/google/veyron/veyron.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/global_data.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <power/regulator.h>
+
+/*
+ * We should increase the DDR voltage to 1.2V using the PWM regulator.
+ * There is a U-Boot driver for this but it may need to add support for the
+ * 'voltage-table' property.
+ */
+#ifndef CONFIG_SPL_BUILD
+#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
+static int veyron_init(void)
+{
+	struct udevice *dev;
+	struct clk clk;
+	int ret;
+
+	ret = regulator_get_by_platname("vdd_arm", &dev);
+	if (ret) {
+		debug("Cannot set regulator name\n");
+		return ret;
+	}
+
+	/* Slowly raise to max CPU voltage to prevent overshoot */
+	ret = regulator_set_value(dev, 1200000);
+	if (ret)
+		return ret;
+	udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
+	ret = regulator_set_value(dev, 1400000);
+	if (ret)
+		return ret;
+	udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
+
+	ret = rockchip_get_clk(&clk.dev);
+	if (ret)
+		return ret;
+	clk.id = PLL_APLL;
+	ret = clk_set_rate(&clk, 1800000000);
+	if (IS_ERR_VALUE(ret))
+		return ret;
+
+	ret = regulator_get_by_platname("vcc33_sd", &dev);
+	if (ret) {
+		debug("Cannot get regulator name\n");
+		return ret;
+	}
+
+	ret = regulator_set_value(dev, 3300000);
+	if (ret)
+		return ret;
+
+	ret = regulators_enable_boot_on(false);
+	if (ret) {
+		debug("%s: Cannot enable boot on regulators\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+#endif
+
+int board_early_init_r(void)
+{
+	struct udevice *dev;
+	int ret;
+
+#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
+	if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
+		ret = veyron_init();
+		if (ret)
+			return ret;
+	}
+#endif
+	/*
+	 * This init is done in SPL, but when chain-loading U-Boot SPL will
+	 * have been skipped. Allow the clock driver to check if it needs
+	 * setting up.
+	 */
+	ret = rockchip_get_clk(&dev);
+	if (ret) {
+		debug("CLK init failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/grinn/chiliboard/Kconfig b/roms/u-boot/board/grinn/chiliboard/Kconfig
new file mode 100644
index 000000000..20056e81a
--- /dev/null
+++ b/roms/u-boot/board/grinn/chiliboard/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CHILIBOARD
+
+config SYS_BOARD
+	default "chiliboard"
+
+config SYS_VENDOR
+	default "grinn"
+
+config SYS_CONFIG_NAME
+	default "chiliboard"
+
+config SYS_SOC
+	default "am33xx"
+
+endif
diff --git a/roms/u-boot/board/grinn/chiliboard/MAINTAINERS b/roms/u-boot/board/grinn/chiliboard/MAINTAINERS
new file mode 100644
index 000000000..5eaccb279
--- /dev/null
+++ b/roms/u-boot/board/grinn/chiliboard/MAINTAINERS
@@ -0,0 +1,8 @@
+CHILIBOARD
+M:	Marcin Niestroj <m.niestroj@grinn-global.com>
+S:	Maintained
+F:	arch/arm/include/asm/arch-am33xx/chilisom.h
+F:	arch/arm/mach-omap2/am33xx/chilisom.c
+F:	board/grinn/chiliboard/
+F:	include/configs/chiliboard.h
+F:	configs/chiliboard_defconfig
diff --git a/roms/u-boot/board/grinn/chiliboard/Makefile b/roms/u-boot/board/grinn/chiliboard/Makefile
new file mode 100644
index 000000000..2c33ccdbf
--- /dev/null
+++ b/roms/u-boot/board/grinn/chiliboard/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2017 Grinn
+
+obj-y  := board.o
diff --git a/roms/u-boot/board/grinn/chiliboard/README b/roms/u-boot/board/grinn/chiliboard/README
new file mode 100644
index 000000000..cea4c1d42
--- /dev/null
+++ b/roms/u-boot/board/grinn/chiliboard/README
@@ -0,0 +1,31 @@
+How to use U-Boot on Grinn's chiliBoard
+--------------------------------------
+
+- Build U-Boot for chiliBoard:
+
+$ make mrproper
+$ make chiliboard_defconfig
+$ make
+
+This will generate the SPL image called MLO and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=MLO of=/dev/mmcblk0 bs=128k; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=128k seek=3; sync
+
+- Jumper settings:
+
+S2: 1 1 1 0 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Insert the micro SD card in the board.
+
+- Connect USB cable between chiliBoard and the PC for the power and console.
+
+- U-Boot messages should come up.
diff --git a/roms/u-boot/board/grinn/chiliboard/board.c b/roms/u-boot/board/grinn/chiliboard/board.c
new file mode 100644
index 000000000..12480f572
--- /dev/null
+++ b/roms/u-boot/board/grinn/chiliboard/board.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2017, Grinn - http://grinn-global.com/
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch/chilisom.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/emif.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <cpsw.h>
+#include <env.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <spl.h>
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static __maybe_unused struct ctrl_dev *cdev =
+	(struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REFCLK */
+	{-1},
+};
+
+static void enable_board_pin_mux(void)
+{
+	chilisom_enable_pin_mux();
+
+	/* chiliboard pinmux */
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+}
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+void set_uart_mux_conf(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+void am33xx_spl_board_init(void)
+{
+	chilisom_spl_board_init();
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD)
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!env_get("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+	}
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!env_get("eth1addr")) {
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("eth1addr", mac_addr);
+	}
+#endif
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/grinn/liteboard/Kconfig b/roms/u-boot/board/grinn/liteboard/Kconfig
new file mode 100644
index 000000000..e035872c9
--- /dev/null
+++ b/roms/u-boot/board/grinn/liteboard/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LITEBOARD
+
+config SYS_BOARD
+	default "liteboard"
+
+config SYS_VENDOR
+	default "grinn"
+
+config SYS_CONFIG_NAME
+	default "liteboard"
+
+endif
diff --git a/roms/u-boot/board/grinn/liteboard/MAINTAINERS b/roms/u-boot/board/grinn/liteboard/MAINTAINERS
new file mode 100644
index 000000000..b4474f1b3
--- /dev/null
+++ b/roms/u-boot/board/grinn/liteboard/MAINTAINERS
@@ -0,0 +1,6 @@
+LITEBOARD
+M:	Marcin Niestroj <m.niestroj@grinn-global.com>
+S:	Maintained
+F:	board/grinn/liteboard/
+F:	include/configs/liteboard.h
+F:	configs/liteboard_defconfig
diff --git a/roms/u-boot/board/grinn/liteboard/Makefile b/roms/u-boot/board/grinn/liteboard/Makefile
new file mode 100644
index 000000000..06aa3eb56
--- /dev/null
+++ b/roms/u-boot/board/grinn/liteboard/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2016 Grinn
+
+obj-y  := board.o
diff --git a/roms/u-boot/board/grinn/liteboard/README b/roms/u-boot/board/grinn/liteboard/README
new file mode 100644
index 000000000..bee039442
--- /dev/null
+++ b/roms/u-boot/board/grinn/liteboard/README
@@ -0,0 +1,31 @@
+How to use U-Boot on Grinn's liteBoard
+--------------------------------------
+
+- Build U-Boot for liteBoard:
+
+$ make mrproper
+$ make liteboard_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+S1: 0 1 0 1 1 1
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Insert the micro SD card in the board.
+
+- Connect USB cable between liteBoard and the PC for the power and console.
+
+- U-Boot messages should come up.
diff --git a/roms/u-boot/board/grinn/liteboard/board.c b/roms/u-boot/board/grinn/liteboard/board.c
new file mode 100644
index 000000000..48392c48e
--- /dev/null
+++ b/roms/u-boot/board/grinn/liteboard/board.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Grinn
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/litesom.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/sizes.h>
+#include <linux/fb.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                   \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const sd_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* CD */
+	MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
+
+#define SD_CD_GPIO	IMX_GPIO_NR(1, 19)
+
+static int mmc_get_env_devno(void)
+{
+	u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+	int dev_no;
+	u32 bootsel;
+
+	bootsel = (soc_sbmr & 0x000000FF) >> 6;
+
+	/* If not boot from sd/mmc, use default value */
+	if (bootsel != 1)
+		return CONFIG_SYS_MMC_ENV_DEV;
+
+	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
+	dev_no = (soc_sbmr & 0x00001800) >> 11;
+
+	return dev_no;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(SD_CD_GPIO);
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = 1;
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int ret;
+
+	/* SD */
+	imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
+	gpio_direction_input(SD_CD_GPIO);
+	sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	ret = fsl_esdhc_initialize(bis, &sd_cfg);
+	if (ret) {
+		printf("Warning: failed to initialize mmc dev 0 (SD)\n");
+		return ret;
+	}
+
+	return litesom_mmc_init(bis);
+}
+
+static int check_mmc_autodetect(void)
+{
+	char *autodetect_str = env_get("mmcautodetect");
+
+	if ((autodetect_str != NULL) &&
+	    (strcmp(autodetect_str, "yes") == 0)) {
+		return 1;
+	}
+
+	return 0;
+}
+
+void board_late_mmc_init(void)
+{
+	char cmd[32];
+	char mmcblk[32];
+	u32 dev_no = mmc_get_env_devno();
+
+	if (!check_mmc_autodetect())
+		return;
+
+	env_set_ulong("mmcdev", dev_no);
+
+	/* Set mmcblk env */
+	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+		dev_no);
+	env_set("mmcroot", mmcblk);
+
+	sprintf(cmd, "mmc dev %d", dev_no);
+	run_command(cmd, 0);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
+	   set gpr1[17]*/
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef	CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd",   MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_init();
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Grinn liteBoard\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_boot_order(u32 *spl_boot_list)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
+	unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
+	unsigned port = (reg >> 11) & 0x1;
+
+	if (port == 0) {
+		spl_boot_list[0] = BOOT_DEVICE_MMC1;
+		spl_boot_list[1] = BOOT_DEVICE_MMC2;
+	} else {
+		spl_boot_list[0] = BOOT_DEVICE_MMC2;
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+	}
+}
+
+void board_init_f(ulong dummy)
+{
+	litesom_init_f();
+}
+#endif
diff --git a/roms/u-boot/board/hardkernel/odroid_go2/Kconfig b/roms/u-boot/board/hardkernel/odroid_go2/Kconfig
new file mode 100644
index 000000000..cf3f7c91d
--- /dev/null
+++ b/roms/u-boot/board/hardkernel/odroid_go2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ODROID_GO2
+
+config SYS_BOARD
+	default "odroid_go2"
+
+config SYS_VENDOR
+	default "hardkernel"
+
+config SYS_CONFIG_NAME
+	default "odroid_go2"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/hardkernel/odroid_go2/MAINTAINERS b/roms/u-boot/board/hardkernel/odroid_go2/MAINTAINERS
new file mode 100644
index 000000000..eab622a70
--- /dev/null
+++ b/roms/u-boot/board/hardkernel/odroid_go2/MAINTAINERS
@@ -0,0 +1,6 @@
+GO2
+M:      Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
+S:      Maintained
+F:      board/odroid/go2
+F:      include/configs/odroid_go2.h
+F:      configs/odroid-go2_defconfig
diff --git a/roms/u-boot/board/hardkernel/odroid_go2/Makefile b/roms/u-boot/board/hardkernel/odroid_go2/Makefile
new file mode 100644
index 000000000..51b9d24cf
--- /dev/null
+++ b/roms/u-boot/board/hardkernel/odroid_go2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= go2.o
diff --git a/roms/u-boot/board/hardkernel/odroid_go2/go2.c b/roms/u-boot/board/hardkernel/odroid_go2/go2.c
new file mode 100644
index 000000000..29464ae63
--- /dev/null
+++ b/roms/u-boot/board/hardkernel/odroid_go2/go2.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
diff --git a/roms/u-boot/board/highbank/MAINTAINERS b/roms/u-boot/board/highbank/MAINTAINERS
new file mode 100644
index 000000000..a542bd1ee
--- /dev/null
+++ b/roms/u-boot/board/highbank/MAINTAINERS
@@ -0,0 +1,6 @@
+HIGHBANK BOARD
+M:	Andre Przywara <andre.przywara@arm.com>
+S:	Maintained
+F:	board/highbank/
+F:	include/configs/highbank.h
+F:	configs/highbank_defconfig
diff --git a/roms/u-boot/board/highbank/Makefile b/roms/u-boot/board/highbank/Makefile
new file mode 100644
index 000000000..57f7f2e2a
--- /dev/null
+++ b/roms/u-boot/board/highbank/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= highbank.o ahci.o
diff --git a/roms/u-boot/board/highbank/ahci.c b/roms/u-boot/board/highbank/ahci.c
new file mode 100644
index 000000000..9c057278a
--- /dev/null
+++ b/roms/u-boot/board/highbank/ahci.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2012 Calxeda, Inc.
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
+#define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
+#define CPHY_BASE			0xfff58000
+#define CPHY_WIDTH			0x1000
+#define CPHY_DTE_XS			5
+#define CPHY_MII			31
+#define SERDES_CR_CTL			0x80a0
+#define SERDES_CR_ADDR			0x80a1
+#define SERDES_CR_DATA			0x80a2
+#define CR_BUSY				0x0001
+#define CR_START			0x0001
+#define CR_WR_RDN			0x0002
+#define CPHY_TX_INPUT_STS		0x2001
+#define CPHY_RX_INPUT_STS		0x2002
+#define CPHY_SATA_TX_OVERRIDE_BIT	0x8000
+#define CPHY_SATA_RX_OVERRIDE_BIT	0x4000
+#define CPHY_TX_INPUT_OVERRIDE		0x2004
+#define CPHY_RX_INPUT_OVERRIDE		0x2005
+#define SPHY_LANE			0x100
+#define SPHY_HALF_RATE			0x0001
+#define CPHY_SATA_DPLL_MODE		0x0700
+#define CPHY_SATA_DPLL_SHIFT		8
+#define CPHY_SATA_TX_ATTEN		0x1c00
+#define CPHY_SATA_TX_ATTEN_SHIFT	10
+
+#define HB_SREG_SATA_ATTEN		0xfff3cf24
+
+#define SATA_PORT_BASE			0xffe08000
+#define SATA_VERSIONR			0xf8
+#define SATA_HB_VERSION			0x3332302a
+
+static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr)
+{
+	u32 data;
+	writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
+	data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
+	return data;
+}
+
+static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data)
+{
+	writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
+	writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
+}
+
+static u32 combo_phy_read(u8 phy, u32 addr)
+{
+	u8 dev = CPHY_DTE_XS;
+	if (phy == 5)
+		dev = CPHY_MII;
+	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
+		udelay(5);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START);
+	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
+		udelay(5);
+	return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA);
+}
+
+static void combo_phy_write(u8 phy, u32 addr, u32 data)
+{
+	u8 dev = CPHY_DTE_XS;
+	if (phy == 5)
+		dev = CPHY_MII;
+	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
+		udelay(5);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START);
+}
+
+static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val)
+{
+	u32 tmp;
+	tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
+	tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp |= CPHY_SATA_RX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp &= ~CPHY_SATA_DPLL_MODE;
+	tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE;
+	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+static void cphy_tx_attenuation_override(u8 phy, u8 lane)
+{
+	u32 val;
+	u32 tmp;
+	u8  shift;
+
+	shift = ((phy == 5) ? 4 : lane) * 4;
+
+	val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf;
+
+	if (val & 0x8)
+		return;
+
+	tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
+	tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp |= CPHY_SATA_TX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
+	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+static void cphy_disable_port_overrides(u8 port)
+{
+	u32 tmp;
+	u8 lane = 0, phy = 0;
+
+	if (port == 0)
+		phy = 5;
+	else if (port < 5)
+		lane = port - 1;
+	else
+		return;
+	tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
+	tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE);
+	tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+void cphy_disable_overrides(void)
+{
+	int i;
+	u32 port_map;
+
+	port_map = readl(0xffe08000 + HOST_PORTS_IMPL);
+	for (i = 0; i < 5; i++) {
+		if (port_map & (1 << i))
+			cphy_disable_port_overrides(i);
+	}
+}
+
+static void cphy_override_lane(u8 port)
+{
+	u32 tmp, k = 0;
+	u8 lane = 0, phy = 0;
+
+	if (port == 0)
+		phy = 5;
+	else if (port < 5)
+		lane = port - 1;
+	else
+		return;
+
+	do {
+		tmp = combo_phy_read(0, CPHY_RX_INPUT_STS +
+					lane * SPHY_LANE);
+	} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
+	cphy_spread_spectrum_override(phy, lane, 3);
+	cphy_tx_attenuation_override(phy, lane);
+}
+
+#define WAIT_MS_LINKUP	4
+
+int ahci_link_up(struct ahci_uc_priv *probe_ent, int port)
+{
+	u32 tmp;
+	int j = 0;
+	u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
+	u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) ==
+				SATA_HB_VERSION ? 1 : 0;
+
+	/* Bring up SATA link.
+	 * SATA link bringup time is usually less than 1 ms; only very
+	 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
+	 */
+	while (j < WAIT_MS_LINKUP) {
+		if (is_highbank && (j == 0)) {
+			cphy_disable_port_overrides(port);
+			writel(0x301, port_mmio + PORT_SCR_CTL);
+			udelay(1000);
+			writel(0x300, port_mmio + PORT_SCR_CTL);
+			udelay(1000);
+			cphy_override_lane(port);
+		}
+
+		tmp = readl(port_mmio + PORT_SCR_STAT);
+		if ((tmp & 0xf) == 0x3)
+			return 0;
+		udelay(1000);
+		j++;
+
+		if ((j == WAIT_MS_LINKUP) && (tmp & 0xf))
+			j = 0;	/* retry phy reset */
+	}
+	return 1;
+}
diff --git a/roms/u-boot/board/highbank/highbank.c b/roms/u-boot/board/highbank/highbank.c
new file mode 100644
index 000000000..ffb6fd922
--- /dev/null
+++ b/roms/u-boot/board/highbank/highbank.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <net.h>
+#include <scsi.h>
+#include <asm/global_data.h>
+
+#include <linux/sizes.h>
+#include <asm/io.h>
+
+#define HB_AHCI_BASE			0xffe08000
+
+#define HB_SCU_A9_PWR_STATUS		0xfff10008
+#define HB_SREG_A9_PWR_REQ		0xfff3cf00
+#define HB_SREG_A9_BOOT_SRC_STAT	0xfff3cf04
+#define HB_SREG_A9_PWRDOM_STAT		0xfff3cf20
+#define HB_SREG_A15_PWR_CTRL		0xfff3c200
+
+#define HB_PWR_SUSPEND			0
+#define HB_PWR_SOFT_RESET		1
+#define HB_PWR_HARD_RESET		2
+#define HB_PWR_SHUTDOWN			3
+
+#define PWRDOM_STAT_SATA		0x80000000
+#define PWRDOM_STAT_PCI			0x40000000
+#define PWRDOM_STAT_EMMC		0x20000000
+
+#define HB_SCU_A9_PWR_NORMAL		0
+#define HB_SCU_A9_PWR_DORMANT		2
+#define HB_SCU_A9_PWR_OFF		3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void cphy_disable_overrides(void);
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	icache_enable();
+
+	return 0;
+}
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+void scsi_init(void)
+{
+	u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
+
+	cphy_disable_overrides();
+	if (reg & PWRDOM_STAT_SATA) {
+		ahci_init((void __iomem *)HB_AHCI_BASE);
+		scsi_scan(true);
+	}
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char envbuffer[16];
+	u32 boot_choice;
+
+	boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
+	sprintf(envbuffer, "bootcmd%d", boot_choice);
+	if (env_get(envbuffer)) {
+		sprintf(envbuffer, "run bootcmd%d", boot_choice);
+		env_set("bootcmd", envbuffer);
+	} else
+		env_set("bootcmd", "");
+
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *fdt, struct bd_info *bd)
+{
+	static const char disabled[] = "disabled";
+	u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
+
+	if (!(reg & PWRDOM_STAT_SATA))
+		do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status",
+			disabled, sizeof(disabled), 1);
+
+	if (!(reg & PWRDOM_STAT_EMMC))
+		do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status",
+			disabled, sizeof(disabled), 1);
+
+	return 0;
+}
+#endif
+
+void *board_fdt_blob_setup(void)
+{
+	/*
+	 * The ECME management processor loads the DTB from NOR flash
+	 * into DRAM (at 4KB), where it gets patched to contain the
+	 * detected memory size.
+	 */
+	return (void *)0x1000;
+}
+
+static int is_highbank(void)
+{
+	uint32_t midr;
+
+	asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
+
+	return (midr & 0xfff0) == 0xc090;
+}
+
+void reset_cpu(void)
+{
+	writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
+	if (is_highbank())
+		writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
+	else
+		writel(0x1, HB_SREG_A15_PWR_CTRL);
+
+	wfi();
+}
+
+/*
+ * turn off the override before transferring control to Linux, since Linux
+ * may not support spread spectrum.
+ */
+void arch_preboot_os(void)
+{
+	cphy_disable_overrides();
+}
diff --git a/roms/u-boot/board/hisilicon/hikey/Kconfig b/roms/u-boot/board/hisilicon/hikey/Kconfig
new file mode 100644
index 000000000..f7f1055e1
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/hikey/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HIKEY
+
+config SYS_BOARD
+	default "hikey"
+
+config SYS_VENDOR
+	default "hisilicon"
+
+config SYS_SOC
+	default "hi6220"
+
+config SYS_CONFIG_NAME
+	default "hikey"
+
+endif
diff --git a/roms/u-boot/board/hisilicon/hikey/MAINTAINERS b/roms/u-boot/board/hisilicon/hikey/MAINTAINERS
new file mode 100644
index 000000000..11088eef8
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/hikey/MAINTAINERS
@@ -0,0 +1,6 @@
+HIKEY BOARD
+M:     Peter Griffin <peter.griffin@linaro.org>
+S:     Maintained
+F:     board/hisilicon/hikey
+F:     include/configs/hikey.h
+F:     configs/hikey_defconfig
diff --git a/roms/u-boot/board/hisilicon/hikey/Makefile b/roms/u-boot/board/hisilicon/hikey/Makefile
new file mode 100644
index 000000000..5b8e76f0b
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/hikey/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= hikey.o
diff --git a/roms/u-boot/board/hisilicon/hikey/README b/roms/u-boot/board/hisilicon/hikey/README
new file mode 100644
index 000000000..94e8397e9
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/hikey/README
@@ -0,0 +1,227 @@
+Introduction
+============
+
+HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: -
+* HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz.
+* ARM Mali 450-MP4 GPU
+* 1GB 800MHz LPDDR3 DRAM
+* 4GB eMMC Flash Storage
+* microSD
+* 802.11a/b/g/n WiFi, Bluetooth
+
+The HiKey schematic can be found here: -
+https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/HiKey_schematics_LeMaker_version_Rev_A1.pdf
+
+The SoC datasheet can be found here: -
+https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
+
+Currently the u-boot port supports: -
+* USB
+* eMMC
+* SD card
+* GPIO
+
+The HiKey U-Boot port has been tested with l-loader, booting ATF, which then boots
+U-Boot as the bl33.bin executable.
+
+Compile from source
+===================
+
+First get all the sources
+
+  > mkdir -p ~/hikey/src ~/hikey/bin
+  > cd ~/hikey/src
+  > git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
+  > git clone https://github.com/ARM-software/arm-trusted-firmware
+  > git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
+  > git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
+  > git clone https://github.com/96boards-hikey/atf-fastboot
+  > wget https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/hisi-idt.py
+
+Get the BL30 mcuimage.bin binary. It is shipped as part of the UEFI source.
+The latest version can be obtained from the OpenPlatformPkg repo.
+
+  > cp OpenPlatformPkg/Platforms/Hisilicon/HiKey/Binary/mcuimage.bin ~/hikey/bin/
+
+Get nvme.img binary
+  > wget -P ~/hikey/bin https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/nvme.img
+
+Compile U-Boot
+==============
+
+  > cd ~/hikey/src/u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
+  > make CROSS_COMPILE=aarch64-linux-gnu-
+  > cp u-boot.bin ~/hikey/bin
+
+Compile ARM Trusted Firmware (ATF)
+==================================
+
+  > cd ~/hikey/src/arm-trusted-firmware
+  > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+    SCP_BL2=~/hikey/bin/mcuimage.bin \
+    BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey
+
+Copy the resulting FIP binary
+  > cp build/hikey/debug/fip.bin ~/hikey/bin
+
+Compile ATF Fastboot
+====================
+
+  > cd ~/hikey/src/atf-fastboot
+  > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=hikey DEBUG=1
+
+Compile l-loader
+================
+  > cd ~/hikey/src/l-loader
+  > ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl1.bin
+  > ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl2.bin
+  > ln -sf ~/hikey/src/atf-fastboot/build/hikey/debug/bl1.bin fastboot.bin
+  > make hikey PTABLE_LST=aosp-8g
+
+Copy the resulting binaries
+  > cp *.img ~/hikey/bin
+  > cp l-loader.bin ~/hikey/bin
+  > cp recovery.bin ~/hikey/bin
+
+These instructions are adapted from
+https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey.rst
+
+FLASHING
+========
+
+1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with
+the hisi-idt.py utility. Then connect a USB A to B mini cable from your PC to the USB OTG port of HiKey and execute the below command.
+
+The command below assumes HiKey enumerated as the first USB serial port
+
+  > sudo python ~/hikey/src/hisi-idt.py -d /dev/ttyUSB0 --img1 ~/hikey/bin/recovery.bin
+
+2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device.
+
+  > sudo fastboot devices
+
+0123456789ABCDEF	fastboot
+
+3. Flash the images
+
+  > sudo fastboot flash ptable ~/hikey/bin/prm_ptable.img
+  > sudo fastboot flash loader ~/hikey/bin/l-loader.bin
+  > sudo fastboot flash fastboot ~/hikey/bin/fip.bin
+  > sudo fastboot flash nvme ~/hikey/bin/nvme.img
+
+4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully)
+   have ATF, booting u-boot from eMMC.
+
+   Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you
+   will get 'dwc_otg_core_host_init: Timeout!' errors.
+
+See working boot trace below on UART3 available at Low Speed Expansion header: -
+
+NOTICE:  BL2: v1.5(debug):v1.5-694-g6d4f6aea
+NOTICE:  BL2: Built : 09:21:42, Aug 29 2018
+INFO:    BL2: Doing platform setup
+INFO:    ddr3 rank1 init pass
+INFO:    succeed to set ddrc 150mhz
+INFO:    ddr3 rank1 init pass
+INFO:    succeed to set ddrc 266mhz
+INFO:    ddr3 rank1 init pass
+INFO:    succeed to set ddrc 400mhz
+INFO:    ddr3 rank1 init pass
+INFO:    succeed to set ddrc 533mhz
+INFO:    ddr3 rank1 init pass
+INFO:    succeed to set ddrc 800mhz
+INFO:    Samsung DDR
+INFO:    ddr test value:0xa5a55a5a
+INFO:    BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000
+INFO:    BL2: TrustZone: protecting 4194304 bytes of memory at 0x3e800000
+INFO:    [BDID] [fff91c18] midr: 0x410fd033
+INFO:    init_acpu_dvfs: pmic version 17
+INFO:    init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00.
+INFO:    acpu_dvfs_volt_init: success!
+INFO:    acpu_dvfs_set_freq: support freq num is 5
+INFO:    acpu_dvfs_set_freq: start prof is 0x4
+INFO:    acpu_dvfs_set_freq: magic is 0x5a5ac5c5
+INFO:    acpu_dvfs_set_freq: voltage:
+INFO:      - 0: 0x49
+INFO:      - 1: 0x49
+INFO:      - 2: 0x50
+INFO:      - 3: 0x60
+INFO:      - 4: 0x78
+NOTICE:  acpu_dvfs_set_freq: set acpu freq success!INFO:    BL2: Loading image id 2
+INFO:    Loading image id=2 at address 0x1000000
+INFO:    Image id=2 loaded: 0x1000000 - 0x1023d00
+INFO:    hisi_mcu_load_image: mcu sections 0:
+INFO:    hisi_mcu_load_image:  src  = 0x1000200
+INFO:    hisi_mcu_load_image:  dst  = 0xf6000000
+INFO:    hisi_mcu_load_image:  size = 31184
+INFO:    hisi_mcu_load_image:  [SRC 0x1000200] 0x8000 0x3701 0x7695 0x7689
+INFO:    hisi_mcu_load_image:  [DST 0xf6000000] 0x8000 0x3701 0x7695 0x7689
+INFO:    hisi_mcu_load_image: mcu sections 1:
+INFO:    hisi_mcu_load_image:  src  = 0x1007bd0
+INFO:    hisi_mcu_load_image:  dst  = 0x5e00000
+INFO:    hisi_mcu_load_image:  size = 93828
+INFO:    hisi_mcu_load_image:  [SRC 0x1007bd0] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
+INFO:    hisi_mcu_load_image:  [DST 0x5e00000] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
+INFO:    hisi_mcu_load_image: mcu sections 2:
+INFO:    hisi_mcu_load_image:  src  = 0x101ea54
+INFO:    hisi_mcu_load_image:  dst  = 0x5e16e84
+INFO:    hisi_mcu_load_image:  size = 15428
+INFO:    hisi_mcu_load_image:  [SRC 0x101ea54] 0x9 0x1020640 0x10001 0x8f0d180
+INFO:    hisi_mcu_load_image:  [DST 0x5e16e84] 0x9 0x1020640 0x10001 0x8f0d180
+INFO:    hisi_mcu_load_image: mcu sections 3:
+INFO:    hisi_mcu_load_image:  src  = 0x1022698
+INFO:    hisi_mcu_load_image:  dst  = 0x5e22a10
+INFO:    hisi_mcu_load_image:  size = 3060
+INFO:    hisi_mcu_load_image:  [SRC 0x1022698] 0x0 0x0 0x0 0x0
+INFO:    hisi_mcu_load_image:  [DST 0x5e22a10] 0x0 0x0 0x0 0x0
+INFO:    hisi_mcu_load_image: mcu sections 4:
+INFO:    hisi_mcu_load_image:  src  = 0x102328c
+INFO:    hisi_mcu_load_image:  dst  = 0x5e23604
+INFO:    hisi_mcu_load_image:  size = 2616
+INFO:    hisi_mcu_load_image:  [SRC 0x102328c] 0xf80000a0 0x0 0xf80000ac 0x0
+INFO:    hisi_mcu_load_image:  [DST 0x5e23604] 0xf80000a0 0x0 0xf80000ac 0x0
+INFO:    hisi_mcu_start_run: AO_SC_SYS_CTRL2=0
+INFO:    plat_hikey_bl2_handle_scp_bl2: MCU PC is at 0x42933301
+INFO:    plat_hikey_bl2_handle_scp_bl2: AO_SC_PERIPH_CLKSTAT4 is 0x3b018f09
+WARNING: BL2: Platform setup already done!!
+INFO:    BL2: Loading image id 3
+INFO:    Loading image id=3 at address 0xf9858000
+INFO:    Image id=3 loaded: 0xf9858000 - 0xf9860058
+INFO:    BL2: Loading image id 5
+INFO:    Loading image id=5 at address 0x35000000
+INFO:    Image id=5 loaded: 0x35000000 - 0x35061cd2
+NOTICE:  BL2: Booting BL31
+INFO:    Entry point address = 0xf9858000
+INFO:    SPSR = 0x3cd
+NOTICE:  BL31: v1.5(debug):v1.5-694-g6d4f6aea
+NOTICE:  BL31: Built : 09:21:44, Aug 29 2018
+WARNING: Using deprecated integer interrupt array in gicv2_driver_data_t
+WARNING: Please migrate to using an interrupt_prop_t array
+INFO:    ARM GICv2 driver initialized
+INFO:    BL31: Initializing runtime services
+INFO:    BL31: cortex_a53: CPU workaround for disable_non_temporal_hint was applied
+INFO:    BL31: cortex_a53: CPU workaround for 843419 was applied
+INFO:    BL31: cortex_a53: CPU workaround for 855873 was applied
+INFO:    BL31: Preparing for EL3 exit to normal world
+INFO:    Entry point address = 0x35000000
+INFO:    SPSR = 0x3c9
+
+
+U-Boot 2018.09-rc1 (Aug 22 2018 - 14:55:49 +0530)hikey
+
+DRAM:  990 MiB
+HI6553 PMIC init
+MMC:   config_sd_carddetect: SD card present
+Hisilicon DWMMC: 0, Hisilicon DWMMC: 1
+Loading Environment from FAT... Unable to use mmc 1:1... Failed (-5)
+In:    uart@f7113000
+Out:   uart@f7113000
+Err:   uart@f7113000
+Net:   Net Initialization Skipped
+No ethernet found.
+Hit any key to stop autoboot:  0
+starting USB...
+USB0:   scanning bus 0 for devices... 2 USB Device(s) found
+       scanning usb for storage devices... 0 Storage Device(s) found
+       scanning usb for ethernet devices... 0 Ethernet Device(s) found
diff --git a/roms/u-boot/board/hisilicon/hikey/build-tf.mak b/roms/u-boot/board/hisilicon/hikey/build-tf.mak
new file mode 100644
index 000000000..cde04827e
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/hikey/build-tf.mak
@@ -0,0 +1,42 @@
+CROSS_COMPILE	:= aarch64-linux-gnu-
+output_dir	:= $(PWD)/../bin
+makejobs	:= $(nproc)
+makethreads	:= $(shell dc -e "$(makejobs) 1 + p")
+make_options	:= GCC49_AARCH64_PREFIX=$CROSS_COMPILE \
+		-j$(makethreads) -l$(makejobs)
+
+BL30_HIKEY	:= $(output_dir)/mcuimage.bin
+BL33_HIKEY	:= $(output_dir)/u-boot-hikey.bin
+
+.PHONY: help
+help:
+	@echo "****  Common Makefile  ****"
+	@echo "example:"
+	@echo "make -f build-tf.mak build"
+
+.PHONY: have-crosscompiler
+have-crosscompiler:
+	@echo -n "Check that $(CROSS_COMPILE)gcc is available..."
+	@which $(CROSS_COMPILE)gcc > /dev/null ; \
+	if [ ! $$? -eq 0 ] ; then \
+	   echo "ERROR: cross-compiler $(CROSS_COMPILE)gcc not in PATH=$$PATH!" ; \
+	   echo "ABORTING." ; \
+	   exit 1 ; \
+	else \
+	   echo "OK" ;\
+	fi
+
+build: have-crosscompiler FORCE
+	@echo "Build TF for Hikey..."
+	rm -rf build/
+	CROSS_COMPILE=$(CROSS_COMPILE) \
+	make all fip \
+	BL30=$(BL30_HIKEY) \
+	BL33=$(BL33_HIKEY) \
+	DEBUG=1 \
+	PLAT=hikey
+	@echo "Copy resulting binaries..."
+	cp build/hikey/debug/bl1.bin $(output_dir)/bl1-hikey.bin
+	cp build/hikey/debug/fip.bin $(output_dir)/fip-hikey.bin
+
+FORCE:
diff --git a/roms/u-boot/board/hisilicon/hikey/hikey.c b/roms/u-boot/board/hisilicon/hikey/hikey.c
new file mode 100644
index 000000000..c9a2d60ee
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/hikey/hikey.c
@@ -0,0 +1,493 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ */
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <errno.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <usb.h>
+#include <linux/delay.h>
+#include <power/hi6553_pmic.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/hi6220.h>
+#include <asm/armv8/mmu.h>
+
+/*TODO drop this table in favour of device tree */
+static const struct hikey_gpio_plat hi6220_gpio[] = {
+	{ 0, HI6220_GPIO_BASE(0)},
+	{ 1, HI6220_GPIO_BASE(1)},
+	{ 2, HI6220_GPIO_BASE(2)},
+	{ 3, HI6220_GPIO_BASE(3)},
+	{ 4, HI6220_GPIO_BASE(4)},
+	{ 5, HI6220_GPIO_BASE(5)},
+	{ 6, HI6220_GPIO_BASE(6)},
+	{ 7, HI6220_GPIO_BASE(7)},
+	{ 8, HI6220_GPIO_BASE(8)},
+	{ 9, HI6220_GPIO_BASE(9)},
+	{ 10, HI6220_GPIO_BASE(10)},
+	{ 11, HI6220_GPIO_BASE(11)},
+	{ 12, HI6220_GPIO_BASE(12)},
+	{ 13, HI6220_GPIO_BASE(13)},
+	{ 14, HI6220_GPIO_BASE(14)},
+	{ 15, HI6220_GPIO_BASE(15)},
+	{ 16, HI6220_GPIO_BASE(16)},
+	{ 17, HI6220_GPIO_BASE(17)},
+	{ 18, HI6220_GPIO_BASE(18)},
+	{ 19, HI6220_GPIO_BASE(19)},
+
+};
+
+U_BOOT_DRVINFOS(hi6220_gpios) = {
+	{ "gpio_hi6220", &hi6220_gpio[0] },
+	{ "gpio_hi6220", &hi6220_gpio[1] },
+	{ "gpio_hi6220", &hi6220_gpio[2] },
+	{ "gpio_hi6220", &hi6220_gpio[3] },
+	{ "gpio_hi6220", &hi6220_gpio[4] },
+	{ "gpio_hi6220", &hi6220_gpio[5] },
+	{ "gpio_hi6220", &hi6220_gpio[6] },
+	{ "gpio_hi6220", &hi6220_gpio[7] },
+	{ "gpio_hi6220", &hi6220_gpio[8] },
+	{ "gpio_hi6220", &hi6220_gpio[9] },
+	{ "gpio_hi6220", &hi6220_gpio[10] },
+	{ "gpio_hi6220", &hi6220_gpio[11] },
+	{ "gpio_hi6220", &hi6220_gpio[12] },
+	{ "gpio_hi6220", &hi6220_gpio[13] },
+	{ "gpio_hi6220", &hi6220_gpio[14] },
+	{ "gpio_hi6220", &hi6220_gpio[15] },
+	{ "gpio_hi6220", &hi6220_gpio[16] },
+	{ "gpio_hi6220", &hi6220_gpio[17] },
+	{ "gpio_hi6220", &hi6220_gpio[18] },
+	{ "gpio_hi6220", &hi6220_gpio[19] },
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+
+static const struct pl01x_serial_plat serial_plat = {
+#if CONFIG_CONS_INDEX == 1
+	.base = HI6220_UART0_BASE,
+#elif CONFIG_CONS_INDEX == 4
+	.base = HI6220_UART3_BASE,
+#else
+#error "Unsupported console index value."
+#endif
+	.type = TYPE_PL011,
+	.clock = 19200000
+};
+
+U_BOOT_DRVINFO(hikey_seriala) = {
+	.name = "serial_pl01x",
+	.plat = &serial_plat,
+};
+#endif
+
+static struct mm_region hikey_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = hikey_mem_map;
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_uart_init(void)
+{
+	switch (CONFIG_CONS_INDEX) {
+	case 1:
+		hi6220_pinmux_config(PERIPH_ID_UART0);
+		break;
+	case 4:
+		hi6220_pinmux_config(PERIPH_ID_UART3);
+		break;
+	default:
+		debug("%s: Unsupported UART selected\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	board_uart_init();
+	return 0;
+}
+#endif
+
+struct peri_sc_periph_regs *peri_sc =
+	(struct peri_sc_periph_regs *)HI6220_PERI_BASE;
+
+struct alwayson_sc_regs *ao_sc =
+	(struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
+
+/* status offset from enable reg */
+#define STAT_EN_OFF 0x2
+
+void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
+{
+	uint32_t data;
+
+	data = readl(clk_base);
+	data |= bitfield;
+
+	writel(bitfield, clk_base);
+	do {
+		data = readl(clk_base + STAT_EN_OFF);
+	} while ((data & bitfield) == 0);
+}
+
+/* status offset from disable reg */
+#define STAT_DIS_OFF 0x1
+
+void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
+{
+	uint32_t data;
+
+	data = readl(clk_base);
+	data |= bitfield;
+
+	writel(data, clk_base);
+	do {
+		data = readl(clk_base + STAT_DIS_OFF);
+	} while (data & bitfield);
+}
+
+#define EYE_PATTERN	0x70533483
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	unsigned int data;
+
+	/* enable USB clock */
+	hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
+
+	/* take usb IPs out of reset */
+	writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
+		PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
+		&peri_sc->rst0_dis);
+	do {
+		data = readl(&peri_sc->rst0_stat);
+		data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
+			PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
+	} while (data);
+
+	/*CTRL 5*/
+	data = readl(&peri_sc->ctrl5);
+	data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
+	data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
+	data |= 0x300;
+	writel(data, &peri_sc->ctrl5);
+
+	/*CTRL 4*/
+
+	/* configure USB PHY */
+	data = readl(&peri_sc->ctrl4);
+
+	/* make PHY out of low power mode */
+	data &= ~PERI_CTRL4_PICO_SIDDQ;
+	data &= ~PERI_CTRL4_PICO_OGDISABLE;
+	data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
+	writel(data, &peri_sc->ctrl4);
+
+	writel(EYE_PATTERN, &peri_sc->ctrl8);
+
+	mdelay(5);
+	return 0;
+}
+
+static int config_sd_carddetect(void)
+{
+	int ret;
+
+	/* configure GPIO8 as nopull */
+	writel(0, 0xf8001830);
+
+	gpio_request(8, "SD CD");
+
+	gpio_direction_input(8);
+	ret = gpio_get_value(8);
+
+	if (!ret) {
+		printf("%s: SD card present\n", __func__);
+		return 1;
+	}
+
+	printf("%s: SD card not present\n", __func__);
+	return 0;
+}
+
+
+static void mmc1_init_pll(void)
+{
+	uint32_t data;
+
+	/* select SYSPLL as the source of MMC1 */
+	/* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
+	writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
+	do {
+		data = readl(&peri_sc->clk0_sel);
+	} while (!(data & (1 << 11)));
+
+	/* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
+	writel(1 << 30, &peri_sc->clk0_sel);
+	do {
+		data = readl(&peri_sc->clk0_sel);
+	} while (data & (1 << 14));
+
+	hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
+
+	hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
+
+	do {
+		/* 1.2GHz / 50 = 24MHz */
+		writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
+		data = readl(&peri_sc->clkcfg8bit2);
+	} while ((data & 0x31) != 0x31);
+}
+
+static void mmc1_reset_clk(void)
+{
+	unsigned int data;
+
+	/* disable mmc1 bus clock */
+	hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
+
+	/* enable mmc1 bus clock */
+	hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
+
+	/* reset mmc1 clock domain */
+	writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
+
+	/* bypass mmc1 clock phase */
+	data = readl(&peri_sc->ctrl2);
+	data |= 3 << 2;
+	writel(data, &peri_sc->ctrl2);
+
+	/* disable low power */
+	data = readl(&peri_sc->ctrl13);
+	data |= 1 << 4;
+	writel(data, &peri_sc->ctrl13);
+	do {
+		data = readl(&peri_sc->rst0_stat);
+	} while (!(data & PERI_RST0_MMC1));
+
+	/* unreset mmc1 clock domain */
+	writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
+	do {
+		data = readl(&peri_sc->rst0_stat);
+	} while (data & PERI_RST0_MMC1);
+}
+
+static void mmc0_reset_clk(void)
+{
+	unsigned int data;
+
+	/* disable mmc0 bus clock */
+	hi6220_clk_disable(PERI_CLK0_MMC0, &peri_sc->clk0_dis);
+
+	/* enable mmc0 bus clock */
+	hi6220_clk_enable(PERI_CLK0_MMC0, &peri_sc->clk0_en);
+
+	/* reset mmc0 clock domain */
+	writel(PERI_RST0_MMC0, &peri_sc->rst0_en);
+
+	/* bypass mmc0 clock phase */
+	data = readl(&peri_sc->ctrl2);
+	data |= 3;
+	writel(data, &peri_sc->ctrl2);
+
+	/* disable low power */
+	data = readl(&peri_sc->ctrl13);
+	data |= 1 << 3;
+	writel(data, &peri_sc->ctrl13);
+	do {
+		data = readl(&peri_sc->rst0_stat);
+	} while (!(data & PERI_RST0_MMC0));
+
+	/* unreset mmc0 clock domain */
+	writel(PERI_RST0_MMC0, &peri_sc->rst0_dis);
+	do {
+		data = readl(&peri_sc->rst0_stat);
+	} while (data & PERI_RST0_MMC0);
+}
+
+
+/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
+static void hi6220_pmussi_init(void)
+{
+	uint32_t data;
+
+	/* Take PMUSSI out of reset */
+	writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
+	       &ao_sc->rst4_dis);
+	do {
+		data = readl(&ao_sc->rst4_stat);
+	} while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
+
+	/* set PMU SSI clock latency for read operation */
+	data = readl(&ao_sc->mcu_subsys_ctrl3);
+	data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
+	data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
+	writel(data, &ao_sc->mcu_subsys_ctrl3);
+
+	/* enable PMUSSI clock */
+	data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
+	       ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
+
+	hi6220_clk_enable(data, &ao_sc->clk5_en);
+
+	/* Output high to PMIC on PWR_HOLD_GPIO0_0 */
+	gpio_request(0, "PWR_HOLD_GPIO0_0");
+	gpio_direction_output(0, 1);
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_MMC
+
+static int init_dwmmc(void)
+{
+	int ret = 0;
+
+#ifdef CONFIG_MMC_DW
+
+	/* mmc0 pll is already configured by ATF */
+	mmc0_reset_clk();
+	ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
+	if (ret)
+		printf("%s: Error configuring pinmux for eMMC (%d)\n"
+			, __func__, ret);
+
+	ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
+	if (ret)
+		printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
+
+
+	/* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
+	mmc1_init_pll();
+	mmc1_reset_clk();
+
+	ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
+	if (ret)
+		printf("%s: Error configuring pinmux for eMMC (%d)\n"
+			, __func__, ret);
+
+	config_sd_carddetect();
+
+	ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
+	if (ret)
+		printf("%s: Error adding SD port (%d)\n", __func__, ret);
+
+#endif
+	return ret;
+}
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	/* init the hi6220 pmussi ip */
+	hi6220_pmussi_init();
+
+	power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
+
+	return 0;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int ret;
+
+	/* add the eMMC and sd ports */
+	ret = init_dwmmc();
+
+	if (ret)
+		debug("init_dwmmc failed\n");
+
+	return ret;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	/*
+	 * Reserve regions below from DT memory node (which gets generated
+	 * by U-Boot from the dram banks in arch_fixup_fdt() before booting
+	 * the kernel. This will then match the kernel hikey dts memory node.
+	 *
+	 *  0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
+	 *  0x05f0,1000 - 0x05f0,1fff: Reboot reason
+	 *  0x06df,f000 - 0x06df,ffff: Mailbox message data
+	 *  0x0740,f000 - 0x0740,ffff: MCU firmware section
+	 *  0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
+	 *  0x3e00,0000 - 0x3fff,ffff: OP-TEE
+	*/
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = 0x05e00000;
+
+	gd->bd->bi_dram[1].start = 0x05f00000;
+	gd->bd->bi_dram[1].size = 0x00001000;
+
+	gd->bd->bi_dram[2].start = 0x05f02000;
+	gd->bd->bi_dram[2].size = 0x00efd000;
+
+	gd->bd->bi_dram[3].start = 0x06e00000;
+	gd->bd->bi_dram[3].size = 0x0060f000;
+
+	gd->bd->bi_dram[4].start = 0x07410000;
+	gd->bd->bi_dram[4].size = 0x1aaf0000;
+
+	gd->bd->bi_dram[5].start = 0x22000000;
+	gd->bd->bi_dram[5].size = 0x1c000000;
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	writel(0x48698284, &ao_sc->stat0);
+	wfi();
+}
diff --git a/roms/u-boot/board/hisilicon/hikey960/Kconfig b/roms/u-boot/board/hisilicon/hikey960/Kconfig
new file mode 100644
index 000000000..89f096d64
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/hikey960/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HIKEY960
+
+config SYS_BOARD
+	default "hikey960"
+
+config SYS_VENDOR
+	default "hisilicon"
+
+config SYS_SOC
+	default "hi3660"
+
+config SYS_CONFIG_NAME
+	default "hikey960"
+
+endif
diff --git a/roms/u-boot/board/hisilicon/hikey960/MAINTAINERS b/roms/u-boot/board/hisilicon/hikey960/MAINTAINERS
new file mode 100644
index 000000000..2c9893216
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/hikey960/MAINTAINERS
@@ -0,0 +1,6 @@
+HIKEY960 BOARD
+M:     Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+S:     Maintained
+F:     board/hisilicon/hikey960
+F:     include/configs/hikey960.h
+F:     configs/hikey960_defconfig
diff --git a/roms/u-boot/board/hisilicon/hikey960/Makefile b/roms/u-boot/board/hisilicon/hikey960/Makefile
new file mode 100644
index 000000000..ea5a70921
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/hikey960/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	:= hikey960.o
diff --git a/roms/u-boot/board/hisilicon/hikey960/README b/roms/u-boot/board/hisilicon/hikey960/README
new file mode 100644
index 000000000..e1e330d53
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/hikey960/README
@@ -0,0 +1,247 @@
+Introduction
+============
+
+HiKey960 is one of the 96Boards Consumer Edition board from HiSilicon.
+The board/SoC has: -
+* HiSilicon Kirin960 (HI3660) SoC with 4xCortex-A73 and 4xCortex-A53
+* ARM Mali G71 MP8 GPU
+* 3GB LPDDR4 SDRAM
+* 32GB UFS Flash Storage
+* microSD
+* 802.11a/b/g/n WiFi, Bluetooth
+
+More information about this board can be found in 96Boards website:
+https://www.96boards.org/product/hikey960/
+
+Currently the u-boot port supports: -
+* SD card
+
+Compile from source
+===================
+
+First get all the sources
+
+  > mkdir -p ~/hikey960/src ~/hikey960/bin
+  > cd ~/hikey960/src
+  > git clone https://github.com/ARM-software/arm-trusted-firmware
+  > git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
+  > git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
+  > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/config
+  > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hisi-sec_usb_xloader.img
+  > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hisi-sec_uce_boot.img
+  > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/sec_xloader.img
+  > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/recovery.bin
+  > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hikey_idt
+
+Get the SCP_BL2 lpm3.img binary. It is shipped as part of the UEFI source.
+The latest version can be obtained from the OpenPlatformPkg repo.
+
+  > cp OpenPlatformPkg/Platforms/Hisilicon/HiKey960/Binary/lpm3.img ~/hikey960/bin/
+
+Compile U-Boot
+==============
+
+  > cd ~/hikey960/src/u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- hikey960_defconfig
+  > make CROSS_COMPILE=aarch64-linux-gnu-
+  > cp u-boot.bin ~/hikey960/bin/
+
+Compile ARM Trusted Firmware (ATF)
+==================================
+
+  > cd ~/hikey960/src/arm-trusted-firmware
+  > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+    SCP_BL2=~/hikey960/bin/lpm3.img \
+    BL33=~/hikey960/bin/u-boot.bin DEBUG=1 PLAT=hikey960
+
+Copy the resulting FIP binary
+  > cp build/hikey960/debug/fip.bin ~/hikey960/bin
+
+Compile l-loader
+================
+  > cd ~/hikey960/src/l-loader
+  > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl1.bin
+  > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl2.bin
+  > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/fip.bin
+  > ln -sf ~/hikey960/bin/u-boot.bin
+  > make hikey960 PTABLE_LST=linux-32g NS_BL1U=u-boot.bin
+
+Copy the resulting binaries
+  > cp *.img ~/hikey960/bin
+  > cp l-loader.bin ~/hikey960/bin
+
+These instructions are adapted from
+https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey960.rst
+
+Setup Console
+=============
+
+Install ser2net. Use telnet as the console since UEFI in recovery mode
+output window fails to display in minicom.
+
+  > sudo apt-get install ser2net
+
+Configure ser2net
+
+  > sudo vi /etc/ser2net.conf
+
+Append one line for serial-over-USB in #ser2net.conf
+
+  > 2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
+
+Start ser2net
+
+  > sudo killall ser2net
+  > sudo ser2net -u
+
+Open the console.
+
+  > telnet localhost 2004
+
+And you could open the console remotely, too.
+
+Flashing
+========
+
+1. Boot Hikey960 into recovery mode as per the below document:
+https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey960/installation/board-recovery.md
+
+Once Hikey960 is in recovery mode, flash the recovery binary:
+
+  > cd ~/hikey960/src
+  > chmod +x ./hikey_idt
+  > sudo ./hikey_idt -c config -p /dev/ttyUSB1
+
+Now move to the Hikey960 console and press `f` during UEFI boot. This
+will allow the board to boot into fastboot mode. Once the board is in
+fastboot mode, you should see the ID of the HiKey960 board using the
+following command
+
+  > sudo fastboot devices
+
+1ED3822A018E3372	fastboot
+
+3. Flash the images
+
+Now, the images can be flashed using fastboot:
+
+  > sudo fastboot flash ptable ~/hikey960/bin/prm_ptable.img
+  > sudo fastboot flash xloader ~/hikey960/bin/sec_xloader.img
+  > sudo fastboot flash fastboot ~/hikey960/bin/l-loader.bin
+  > sudo fastboot flash fip ~/hikey960/bin/fip.bin
+
+4. Set the "Boot Mode" switch to OFF position for normal boot mode.
+Then power on HiKey960
+
+Observe the console traces using UART6 on the Low Speed Expansion header:
+
+NOTICE:  BL2: v2.1(debug):v2.1-531-g3ee48f40
+NOTICE:  BL2: Built : 18:15:58, Aug  2 2019
+INFO:    BL2: Doing platform setup
+INFO:    UFS LUN0 contains 1024 blocks with 4096-byte size
+INFO:    UFS LUN1 contains 1024 blocks with 4096-byte size
+INFO:    UFS LUN2 contains 2048 blocks with 4096-byte size
+INFO:    UFS LUN3 contains 7805952 blocks with 4096-byte size
+INFO:    ufs: change power mode success
+INFO:    BL2: Loading image id 2
+INFO:    Loading image id=2 at address 0x89c80000
+INFO:    Image id=2 loaded: 0x89c80000 - 0x89cb5088
+INFO:    BL2: Initiating SCP_BL2 transfer to SCP
+INFO:    BL2: SCP_BL2: 0x89c80000@0x35088
+INFO:    BL2: SCP_BL2 HEAD:
+INFO:    BL2: SCP_BL2 0x7000 0x179 0x159 0x149
+INFO:    BL2: SCP_BL2 0x189 0x18b 0x18d 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x18f
+INFO:    BL2: SCP_BL2 0x191 0x0 0x193 0x195
+INFO:    BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+INFO:    BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+INFO:    BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+INFO:    BL2: SCP_BL2 0x4d454355 0x43494741 0x424d554e 0x21215245
+INFO:    BL2: SCP_BL2 0x4a054904 0x42912000 0xf841bfbc 0xe7fa0b04
+INFO:    BL2: SCP_BL2 0xb88cf000 0x3b18 0x3d1c 0x6809493e
+INFO:    BL2: SCP_BL2 0x4613680a 0x201f102 0xf0002a04 0x600a804c
+INFO:    BL2: SCP_BL2 0x204f04f 0xf203fb02 0xf102440a 0x60100204
+INFO:    BL2: SCP_BL2 0x160f04f 0xf103fb01 0x68004834 0x61044408
+INFO:    BL2: SCP_BL2 0x61866145 0xf8c061c7 0xf8c08020 0xf8c09024
+INFO:    BL2: SCP_BL2 0xf8c0a028 0xf3efb02c 0xf3ef8208 0x68118309
+INFO:    BL2: SCP_BL2 0xf1026401 0xf0110204 0xbf070f04 0x46113220
+INFO:    BL2: SCP_BL2 TAIL:
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x19cad151 0x19b80040 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 transferred to SCP
+INFO:    start fw loading
+INFO:    fw load success
+WARNING: BL2: Platform setup already done!!
+INFO:    BL2: Loading image id 3
+INFO:    Loading image id=3 at address 0x1ac58000
+INFO:    Image id=3 loaded: 0x1ac58000 - 0x1ac63024
+INFO:    BL2: Loading image id 5
+INFO:    Loading image id=5 at address 0x1ac98000
+INFO:    Image id=5 loaded: 0x1ac98000 - 0x1ad0819c
+NOTICE:  BL2: Booting BL31
+INFO:    Entry point address = 0x1ac58000
+INFO:    SPSR = 0x3cd
+NOTICE:  BL31: v2.1(debug):v2.1-531-g3ee48f40
+NOTICE:  BL31: Built : 18:16:01, Aug  2 2019
+INFO:    ARM GICv2 driver initialized
+INFO:    BL31: Initializing runtime services
+INFO:    BL31: cortex_a53: CPU workaround for 855873 was applied
+INFO:    plat_setup_psci_ops: sec_entrypoint=0x1ac580fc
+INFO:    BL31: Preparing for EL3 exit to normal world
+INFO:    Entry point address = 0x1ac98000
+INFO:    SPSR = 0x3c9
+
+
+U-Boot 2019.07-00628-g286f05a6fc-dirty (Aug 02 2019 - 17:14:05 +0530)
+Hikey960
+
+DRAM:  3 GiB
+PSCI:  v1.1
+MMC:   dwmmc1@ff37f000: 0
+Loading Environment from EXT4... ** File not found /uboot.env **
+
+** Unable to read "/uboot.env" from mmc0:2 **
+In:    serial@fff32000
+Out:   serial@fff32000
+Err:   serial@fff32000
+Net:   Net Initialization Skipped
+No ethernet found.
+Hit any key to stop autoboot:  0
+switch to partitions #0, OK
+mmc0 is current device
+Scanning mmc 0:1...
+Found /extlinux/extlinux.conf
+Retrieving file: /extlinux/extlinux.conf
+201 bytes read in 12 ms (15.6 KiB/s)
+1:      hikey960-kernel
+Retrieving file: /Image
+24689152 bytes read in 4377 ms (5.4 MiB/s)
+append: earlycon=pl011,mmio32,0xfff32000 console=ttyAMA6,115200 rw root=/dev/mmcblk0p2 rot
+Retrieving file: /hi3660-hikey960.dtb
+35047 bytes read in 14 ms (2.4 MiB/s)
+## Flattened Device Tree blob at 10000000
+   Booting using the fdt blob at 0x10000000
+   Using Device Tree in place at 0000000010000000, end 000000001000b8e6
+
+Starting kernel ...
+
+[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
+[    0.000000] Linux version 5.2.0-03138-gd75da80dce39 (mani@Mani-XPS-13-9360) (gcc versi9
+[    0.000000] Machine model: HiKey960
+[    0.000000] earlycon: pl11 at MMIO32 0x00000000fff32000 (options '')
+[    0.000000] printk: bootconsole [pl11] enabled
+[    0.000000] efi: Getting EFI parameters from FDT:
diff --git a/roms/u-boot/board/hisilicon/hikey960/hikey960.c b/roms/u-boot/board/hisilicon/hikey960/hikey960.c
new file mode 100644
index 000000000..f41fabbad
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/hikey960/hikey960.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Linaro
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/cache.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/hi3660.h>
+#include <asm/armv8/mmu.h>
+#include <asm/psci.h>
+#include <linux/arm-smccc.h>
+#include <linux/delay.h>
+#include <linux/psci.h>
+
+#define PMIC_REG_TO_BUS_ADDR(x) (x << 2)
+#define PMIC_VSEL_MASK		0x7
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#include <dm/platform_data/serial_pl01x.h>
+
+static const struct pl01x_serial_plat serial_plat = {
+	.base = HI3660_UART6_BASE,
+	.type = TYPE_PL011,
+	.clock = 19200000
+};
+
+U_BOOT_DRVINFO(hikey960_serial0) = {
+	.name = "serial_pl01x",
+	.plat = &serial_plat,
+};
+#endif
+
+static struct mm_region hikey_mem_map[] = {
+	{
+		.virt = 0x0UL, /* DDR */
+		.phys = 0x0UL,
+		.size = 0xC0000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xE0000000UL, /* Peripheral block */
+		.phys = 0xE0000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = hikey_mem_map;
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
+void hikey960_sd_init(void)
+{
+	u32 data;
+
+	/* Enable FPLL0 */
+	data = readl(SCTRL_SCFPLLCTRL0);
+	data |= SCTRL_SCFPLLCTRL0_FPLL0_EN;
+	writel(data, SCTRL_SCFPLLCTRL0);
+
+	/* Configure LDO16 */
+	data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79)) &
+		     PMIC_VSEL_MASK;
+	data |= 6;
+	writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79));
+
+	data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
+	data |= 2;
+	writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
+
+	udelay(100);
+
+	/* Configure LDO9 */
+	data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b)) &
+		     PMIC_VSEL_MASK;
+	data |= 5;
+	writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b));
+
+	data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
+	data |= 2;
+	writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
+
+	udelay(100);
+
+	/* GPIO CD */
+	writel(0, PINMUX4_SDDET);
+
+	/* SD Pinconf */
+	writel(15 << 4, PINCONF3_SDCLK);
+	writel((1 << 0) | (8 << 4), PINCONF3_SDCMD);
+	writel((1 << 0) | (8 << 4), PINCONF3_SDDATA0);
+	writel((1 << 0) | (8 << 4), PINCONF3_SDDATA1);
+	writel((1 << 0) | (8 << 4), PINCONF3_SDDATA2);
+	writel((1 << 0) | (8 << 4), PINCONF3_SDDATA3);
+
+	/* Set SD clock mux */
+	do {
+		data = readl(CRG_REG_BASE + 0xb8);
+		data |= ((1 << 6) | (1 << 6 << 16) | (0 << 4) | (3 << 4 << 16));
+		writel(data, CRG_REG_BASE + 0xb8);
+
+		data = readl(CRG_REG_BASE + 0xb8);
+	} while ((data & ((1 << 6) | (3 << 4))) != ((1 << 6) | (0 << 4)));
+
+	/* Take SD out of reset */
+	writel(1 << 18, CRG_PERRSTDIS4);
+	do {
+		data = readl(CRG_PERRSTSTAT4);
+	} while ((data & (1 << 18)) == (1 << 18));
+
+	/* Enable hclk_gate_sd */
+	data = readl(CRG_REG_BASE + 0);
+	data |= (1 << 30);
+	writel(data, CRG_REG_BASE + 0);
+
+	/* Enable clk_andgt_mmc */
+	data = readl(CRG_REG_BASE + 0xf4);
+	data |= ((1 << 3) | (1 << 3 << 16));
+	writel(data, CRG_REG_BASE + 0xf4);
+
+	/* Enable clk_gate_sd */
+	data = readl(CRG_PEREN4);
+	data |= (1 << 17);
+	writel(data, CRG_PEREN4);
+	do {
+		data = readl(CRG_PERCLKEN4);
+	} while ((data & (1 << 17)) != (1 << 17));
+}
+
+static void show_psci_version(void)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+	printf("PSCI:  v%ld.%ld\n",
+	       PSCI_VERSION_MAJOR(res.a0),
+		PSCI_VERSION_MINOR(res.a0));
+}
+
+int board_init(void)
+{
+	/* Init SD */
+	hikey960_sd_init();
+
+	show_psci_version();
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	psci_system_reset();
+}
diff --git a/roms/u-boot/board/hisilicon/poplar/Kconfig b/roms/u-boot/board/hisilicon/poplar/Kconfig
new file mode 100644
index 000000000..339729544
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/poplar/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_POPLAR
+
+config SYS_BOARD
+	default "poplar"
+
+config SYS_VENDOR
+	default "hisilicon"
+
+config SYS_SOC
+	default "hi3798cv200"
+
+config SYS_CONFIG_NAME
+	default "poplar"
+
+endif
diff --git a/roms/u-boot/board/hisilicon/poplar/MAINTAINERS b/roms/u-boot/board/hisilicon/poplar/MAINTAINERS
new file mode 100644
index 000000000..9c045eaeb
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/poplar/MAINTAINERS
@@ -0,0 +1,7 @@
+Poplar BOARD
+M:     Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
+M:     Shawn Guo <shawn.guo@linaro.org>
+S:     Maintained
+F:     board/hisilicon/poplar
+F:     include/configs/poplar.h
+F:     configs/poplar_defconfig
diff --git a/roms/u-boot/board/hisilicon/poplar/Makefile b/roms/u-boot/board/hisilicon/poplar/Makefile
new file mode 100644
index 000000000..9f2e9c4d4
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/poplar/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2017 Linaro
+# Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+obj-y	:= poplar.o
diff --git a/roms/u-boot/board/hisilicon/poplar/README b/roms/u-boot/board/hisilicon/poplar/README
new file mode 100644
index 000000000..99ed6ce29
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/poplar/README
@@ -0,0 +1,288 @@
+================================================================================
+			Board Information
+================================================================================
+
+Developed by HiSilicon, the board features the Hi3798C V200 with an
+integrated quad-core 64-bit ARM Cortex A53 processor and high
+performance Mali T720 GPU, making it capable of running any commercial
+set-top solution based on Linux or Android. Its high performance
+specification also supports a premium user experience with up to H.265
+HEVC decoding of 4K video at 60 frames per second.
+
+SOC  Hisilicon Hi3798CV200
+CPU  Quad-core ARM Cortex-A53 64 bit
+DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
+USB  Two USB 2.0 ports One USB 3.0 ports
+CONSOLE  USB-micro port for console support
+ETHERNET  1 GBe Ethernet
+PCIE  One PCIe 2.0 interfaces
+JTAG  8-Pin JTAG
+EXPANSION INTERFACE  Linaro 96Boards Low Speed Expansion slot
+DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
+WIFI  802.11AC 2*2 with Bluetooth
+CONNECTORS  One connector for Smart Card One connector for TSI
+
+
+================================================================================
+			BUILD INSTRUCTIONS
+================================================================================
+
+Note of warning:
+================
+
+U-boot has a *strong* dependency with the l-loader and the arm trusted firmware
+repositories.
+
+The boot sequence is:
+	l-loader --> arm_trusted_firmware --> u-boot
+
+U-Boot needs to be aware of the BL31 runtime location and size to avoid writing
+over it. Currently, BL31 is being placed below the kernel text offset (check
+poplar.c) but this could change in the future.
+
+The current version of u-boot has been tested with:
+ - https://github.com/Linaro/poplar-l-loader.git
+
+	commit f0988698dcc5c08bd0a8f50aa0457e138a5f438c
+	Author: Alex Elder <elder@linaro.org>
+	Date:   Fri Jun 16 08:57:59 2017 -0500
+
+    l-loader: use external memory region definitions
+
+    The ARM Trusted Firmware code now has a header file that collects
+    all the definitions for the memory regions used for its boot stages.
+    Include that file where needed, and use the definitions found therein
+
+    Signed-off-by: Alex Elder <elder@linaro.org>
+
+
+ - https://github.com/Linaro/poplar-arm-trusted-firmware.git
+
+	commit 6ac42dd3be13c99aa8ce29a15073e2f19d935f68
+	Author: Alex Elder <elder@linaro.org>
+	Date:   Fri Jun 16 09:24:50 2017 -0500
+
+    poplar: define memory regions in a separate file
+
+    Separate the definitions for memory regions used for the BL stage
+    images and FIP into a new file.  The "l-loader" image uses knowledge
+    of the sizes and locations of these memory regions, and it can now
+    include this (external) header to get these definitions, rather than
+    having to make coordinated changes to both code bases.
+
+    The new file has a complete set of definitions (more than may be
+    required by one or the other user).  It also includes a summary of
+    how the boot process works, and how it uses these regions.
+
+    It should now be relatively easy to adjust the sizes and locations
+    of these memory regions, or to add to them (e.g. for TEE).
+
+    Signed-off-by: Alex Elder <elder@linaro.org>
+
+
+Compile from source:
+====================
+
+Get all the sources
+
+  > mkdir -p ~/poplar/src ~/poplar/bin
+  > cd ~/poplar/src
+  > git clone https://github.com/Linaro/poplar-l-loader.git l-loader
+  > git clone https://github.com/Linaro/poplar-arm-trusted-firmware.git atf
+  > git clone https://github.com/Linaro/poplar-u-boot.git u-boot
+
+Make sure you are using the correct branch on each one of these repositories.
+The definition of "correct" might change over time (at this moment in time this
+would be the "latest" branch).
+
+Compile U-Boot:
+===============
+
+  Prerequisite:
+  # sudo apt-get install device-tree-compiler
+
+  > cd ~/poplar/src/u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- poplar_defconfig
+  > make CROSS_COMPILE=aarch64-linux-gnu-
+  > cp u-boot.bin ~/poplar/bin
+
+Compile ARM Trusted Firmware (ATF):
+===================================
+
+  > cd ~/poplar/src/atf
+  > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+		SPD=none BL33=~/poplar/bin/u-boot.bin DEBUG=1 PLAT=poplar
+
+Copy resulting binaries
+  > cp build/hi3798cv200/debug/bl1.bin ~/poplar/src/l-loader/atf/
+  > cp build/hi3798cv200/debug/fip.bin ~/poplar/src/l-loader/atf/
+
+Compile l-loader:
+=================
+
+  > cd ~/poplar/src/l-loader
+  > make clean
+  > make CROSS_COMPILE=arm-linux-gnueabi-
+
+   Due to BootROM requiremets, rename l-loader.bin to fastboot.bin:
+  > cp l-loader.bin ~/poplar/bin/fastboot.bin
+
+
+================================================================================
+			FLASH INSTRUCTIONS
+================================================================================
+
+Two methods:
+
+Using USB debrick support:
+	Copy fastboot.bin to a FAT partition on the USB drive and reboot the
+       poplar board while pressing S3(usb_boot).
+
+       The system will execute the new u-boot and boot into a shell which you
+       can then use to write to eMMC.
+
+Using U-BOOT from shell:
+	1) using AXIS usb ethernet dongle and tftp
+	2) using FAT formated USB drive
+
+
+1. TFTP (USB ethernet dongle)
+=============================
+
+Plug a USB AXIS ethernet dongle on any of the USB2 ports on the Poplar board.
+Copy fastboot.bin to your tftp server.
+In u-boot make sure your network is properly setup.
+
+Then
+
+=> tftp 0x30000000 fastboot.bin
+starting USB...
+USB0:   USB EHCI 1.00
+scanning bus 0 for devices... 1 USB Device(s) found
+USB1:   USB EHCI 1.00
+scanning bus 1 for devices... 3 USB Device(s) found
+       scanning usb for storage devices... 0 Storage Device(s) found
+       scanning usb for ethernet devices... 1 Ethernet Device(s) found
+Waiting for Ethernet connection... done.
+Using asx0 device
+TFTP from server 192.168.1.4; our IP address is 192.168.1.10
+Filename 'poplar/fastboot.bin'.
+Load address: 0x30000000
+Loading: #################################################################
+	 #################################################################
+	 ###############################################################
+	 2 MiB/s
+done
+Bytes transferred = 983040 (f0000 hex)
+
+=> mmc write 0x30000000 0 0x780
+
+MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
+=> reset
+
+
+2. USING USB FAT DRIVE
+=======================
+
+Copy fastboot.bin to any partition on a FAT32 formated usb flash drive.
+Enter the uboot prompt
+
+=> fatls usb 0:2
+   983040   fastboot.bin
+
+1 file(s), 0 dir(s)
+
+=> fatload usb 0:2 0x30000000 fastboot.bin
+reading fastboot.bin
+983040 bytes read in 44 ms (21.3 MiB/s)
+
+=> mmc write 0x30000000 0 0x780
+
+MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
+
+
+================================================================================
+				BOOT TRACE
+================================================================================
+
+Bootrom start
+Boot Media: eMMC
+Decrypt auxiliary code ...OK
+
+lsadc voltage min: 000000FE, max: 000000FF, aver: 000000FE, index: 00000000
+
+Entry boot auxiliary code
+
+Auxiliary code - v1.00
+DDR code - V1.1.2 20160205
+Build: Mar 24 2016 - 17:09:44
+Reg Version:  v134
+Reg Time:     2016/03/18 09:44:55
+Reg Name:     hi3798cv2dmb_hi3798cv200_ddr3_2gbyte_8bitx4_4layers.reg
+
+Boot auxiliary code success
+Bootrom success
+
+LOADER:  Switched to aarch64 mode
+LOADER:  Entering ARM TRUSTED FIRMWARE
+LOADER:  CPU0 executes at 0x000ce000
+
+INFO:    BL1: 0xe1000 - 0xe7000 [size = 24576]
+NOTICE:  Booting Trusted Firmware
+NOTICE:  BL1: v1.3(debug):v1.3-372-g1ba9c60
+NOTICE:  BL1: Built : 17:51:33, Apr 30 2017
+INFO:    BL1: RAM 0xe1000 - 0xe7000
+INFO:    BL1: Loading BL2
+INFO:    Loading image id=1 at address 0xe9000
+INFO:    Image id=1 loaded at address 0xe9000, size = 0x5008
+NOTICE:  BL1: Booting BL2
+INFO:    Entry point address = 0xe9000
+INFO:    SPSR = 0x3c5
+NOTICE:  BL2: v1.3(debug):v1.3-372-g1ba9c60
+NOTICE:  BL2: Built : 17:51:33, Apr 30 2017
+INFO:    BL2: Loading BL31
+INFO:    Loading image id=3 at address 0x129000
+INFO:    Image id=3 loaded at address 0x129000, size = 0x8038
+INFO:    BL2: Loading BL33
+INFO:    Loading image id=5 at address 0x37000000
+INFO:    Image id=5 loaded at address 0x37000000, size = 0x58f17
+NOTICE:  BL1: Booting BL31
+INFO:    Entry point address = 0x129000
+INFO:    SPSR = 0x3cd
+INFO:    Boot bl33 from 0x37000000 for 364311 Bytes
+NOTICE:  BL31: v1.3(debug):v1.3-372-g1ba9c60
+NOTICE:  BL31: Built : 17:51:33, Apr 30 2017
+INFO:    BL31: Initializing runtime services
+INFO:    BL31: Preparing for EL3 exit to normal world
+INFO:    Entry point address = 0x37000000
+INFO:    SPSR = 0x3c9
+
+
+U-Boot 2017.05-rc2-00130-gd2255b0 (Apr 30 2017 - 17:51:28 +0200)poplar
+
+Model: HiSilicon Poplar Development Board
+BOARD: Hisilicon HI3798cv200 Poplar
+DRAM:  1 GiB
+MMC:   Hisilicon DWMMC: 0
+In:    serial@f8b00000
+Out:   serial@f8b00000
+Err:   serial@f8b00000
+Net:   Net Initialization Skipped
+No ethernet found.
+
+Hit any key to stop autoboot:  0
+starting USB...
+USB0:   USB EHCI 1.00
+scanning bus 0 for devices... 1 USB Device(s) found
+USB1:   USB EHCI 1.00
+scanning bus 1 for devices... 4 USB Device(s) found
+       scanning usb for storage devices... 1 Storage Device(s) found
+       scanning usb for ethernet devices... 1 Ethernet Device(s) found
+
+USB device 0:
+    Device 0: Vendor: SanDisk Rev: 1.00 Prod: Cruzer Blade
+	    Type: Removable Hard Disk
+	    Capacity: 7632.0 MB = 7.4 GB (15630336 x 512)
+... is now current device
+Scanning usb 0:1...
+=>
diff --git a/roms/u-boot/board/hisilicon/poplar/poplar.c b/roms/u-boot/board/hisilicon/poplar/poplar.c
new file mode 100644
index 000000000..6cc79d96a
--- /dev/null
+++ b/roms/u-boot/board/hisilicon/poplar/poplar.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017 Linaro
+ * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <init.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <asm/arch/hi3798cv200.h>
+#include <asm/armv8/mmu.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region poplar_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		0,
+	}
+};
+
+struct mm_region *mem_map = poplar_mem_map;
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct pl01x_serial_plat serial_plat = {
+	.base = REG_BASE_UART0,
+	.type = TYPE_PL010,
+	.clock = 75000000,
+};
+
+U_BOOT_DRVINFO(poplar_serial) = {
+	.name = "serial_pl01x",
+	.plat = &serial_plat,
+};
+#endif
+
+int checkboard(void)
+{
+	puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	psci_system_reset();
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(NULL, 0x80000000);
+
+	return 0;
+}
+
+/*
+ * Some linux kernel versions don't use memory before its load address, so to
+ * be generic we just pretend it isn't there.  In previous uboot versions we
+ * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
+ * could persist in memory and be left alone by the kernel.
+ *
+ * That led to a problem when mapping memory in older kernels.  That PSCI code
+ * now lies in memory below the kernel load offset; it therefore won't be
+ * touched by the kernel, and by not specially reserving it we avoid the mapping
+ * problem as well.
+ *
+ */
+#define KERNEL_TEXT_OFFSET	0x00080000
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
+	gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
+
+	return 0;
+}
+
+static void usb2_phy_config(void)
+{
+	const u32 config[] = {
+		/* close EOP pre-emphasis. open data pre-emphasis */
+		0xa1001c,
+		/* Rcomp = 150mW, increase DC level */
+		0xa00607,
+		/* keep Rcomp working */
+		0xa10700,
+		/* Icomp = 212mW, increase current drive */
+		0xa00aab,
+		/* EMI fix: rx_active not stay 1 when error packets received */
+		0xa11140,
+		/* Comp mode select */
+		0xa11041,
+		/* adjust eye diagram */
+		0xa0098c,
+		/* adjust eye diagram */
+		0xa10a0a,
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(config); i++) {
+		writel(config[i], PERI_CTRL_USB0);
+		clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
+		udelay(20);
+	}
+}
+
+static void usb2_phy_init(void)
+{
+	/* reset usb2 controller bus/utmi/roothub */
+	setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
+			USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
+	udelay(200);
+
+	/* reset usb2 phy por/utmi */
+	setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
+	udelay(200);
+
+	/* open usb2 ref clk */
+	setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
+	udelay(300);
+
+	/* cancel usb2 power on reset */
+	clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
+	udelay(500);
+
+	usb2_phy_config();
+
+	/* cancel usb2 port reset, wait comp circuit stable */
+	clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
+	mdelay(10);
+
+	/* open usb2 controller clk */
+	setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
+			USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
+			USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
+	udelay(200);
+
+	/* cancel usb2 control reset */
+	clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
+			USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
+	udelay(200);
+}
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <env.h>
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+#include <g_dnl.h>
+
+static struct dwc2_plat_otg_data poplar_otg_data = {
+	.regs_otg = HIOTG_BASE_ADDR
+};
+
+static void set_usb_to_device(void)
+{
+	setbits_le32(PERI_CTRL_USB3, USB2_2P_CHIPID);
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	set_usb_to_device();
+	return dwc2_udc_probe(&poplar_otg_data);
+}
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	if (!env_get("serial#"))
+		g_dnl_set_serialnumber("0123456789POPLAR");
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	usb2_phy_init();
+
+	return 0;
+}
+
diff --git a/roms/u-boot/board/hoperun/hihope-rzg2/Kconfig b/roms/u-boot/board/hoperun/hihope-rzg2/Kconfig
new file mode 100644
index 000000000..ee422ba6c
--- /dev/null
+++ b/roms/u-boot/board/hoperun/hihope-rzg2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HIHOPE_RZG2
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "hihope-rzg2"
+
+config SYS_VENDOR
+	default "hoperun"
+
+config SYS_CONFIG_NAME
+	default "hihope-rzg2"
+
+endif
diff --git a/roms/u-boot/board/hoperun/hihope-rzg2/MAINTAINERS b/roms/u-boot/board/hoperun/hihope-rzg2/MAINTAINERS
new file mode 100644
index 000000000..e3702fd12
--- /dev/null
+++ b/roms/u-boot/board/hoperun/hihope-rzg2/MAINTAINERS
@@ -0,0 +1,6 @@
+HIHOPE_RZG2 BOARD
+M:	Biju Das <biju.das.jz@bp.renesas.com>
+S:	Maintained
+F:	board/hoperun/hihope-rzg2/
+F:	include/configs/hihope-rzg2.h
+F:	configs/hihope_rzg2_defconfig
diff --git a/roms/u-boot/board/hoperun/hihope-rzg2/Makefile b/roms/u-boot/board/hoperun/hihope-rzg2/Makefile
new file mode 100644
index 000000000..e989e7aac
--- /dev/null
+++ b/roms/u-boot/board/hoperun/hihope-rzg2/Makefile
@@ -0,0 +1,9 @@
+#
+# board/hoperun/hihope-rzg2/Makefile
+#
+# Copyright (C) 2021 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y	:= hihope-rzg2.o ../../renesas/rcar-common/common.o
diff --git a/roms/u-boot/board/hoperun/hihope-rzg2/hihope-rzg2.c b/roms/u-boot/board/hoperun/hihope-rzg2/hihope-rzg2.c
new file mode 100644
index 000000000..c1bfdcbc1
--- /dev/null
+++ b/roms/u-boot/board/hoperun/hihope-rzg2/hihope-rzg2.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/hoperun/hihope-rzg2/hihope-rzg2.c
+ *     This file is HiHope RZ/G2[HMN] board support.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+
+#define RST_BASE	0xE6160000
+#define RST_CA57RESCNT	(RST_BASE + 0x40)
+#define RST_CA53RESCNT	(RST_BASE + 0x44)
+#define RST_CA57_CODE	0xA5A5000F
+#define RST_CA53_CODE	0x5A5A000F
+
+DECLARE_GLOBAL_DATA_PTR;
+#define HSUSB_MSTP704		BIT(4)	/* HSUSB */
+
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS			0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
+#define HSUSB_REG_UGCTRL2		0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10
+#define HSUSB_REG_UGCTRL2_RESERVED_3	0x1 /* bit[3:0] should be B'0001 */
+
+#define PRR_REGISTER (0xFFF00044)
+
+int board_init(void)
+{
+	u32 i;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	/* Configure the HSUSB block */
+	mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
+	/*
+	 * We need to add a barrier instruction after HSUSB module stop release.
+	 * This barrier instruction can be either reading back the same MSTP
+	 * register or any other register in the same IP block. So like linux
+	 * adding check for MSTPSR register, which indicates the clock has been
+	 * started.
+	 */
+	for (i = 1000; i > 0; --i) {
+		if (!(readl(MSTPSR7) & HSUSB_MSTP704))
+			break;
+		cpu_relax();
+	}
+
+	/* Select EHCI/OHCI host module for USB2.0 ch0 */
+	writel(HSUSB_REG_UGCTRL2_USB0SEL_EHCI | HSUSB_REG_UGCTRL2_RESERVED_3,
+	       HSUSB_REG_UGCTRL2);
+	/* low power status */
+	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	unsigned long midr, cputype;
+
+	asm volatile("mrs %0, midr_el1" : "=r" (midr));
+	cputype = (midr >> 4) & 0xfff;
+
+	if (cputype == 0xd03)
+		writel(RST_CA53_CODE, RST_CA53RESCNT);
+	else
+		writel(RST_CA57_CODE, RST_CA57RESCNT);
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+/* If the firmware passed a device tree, use it for board identification. */
+extern u64 rcar_atf_boot_args[];
+
+static bool is_hoperun_hihope_rzg2_board(const char *board_name)
+{
+	void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+	bool ret = false;
+
+	if ((fdt_magic(atf_fdt_blob) == FDT_MAGIC) &&
+	    (fdt_node_check_compatible(atf_fdt_blob, 0, board_name) == 0))
+		ret = true;
+
+	return ret;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2m") &&
+	    !strcmp(name, "r8a774a1-hihope-rzg2m-u-boot"))
+		return 0;
+
+	if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2n") &&
+	    !strcmp(name, "r8a774b1-hihope-rzg2n-u-boot"))
+		return 0;
+
+	if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2h") &&
+	    !strcmp(name, "r8a774e1-hihope-rzg2h-u-boot"))
+		return 0;
+
+	return -1;
+}
+#endif
diff --git a/roms/u-boot/board/huawei/hg556a/Kconfig b/roms/u-boot/board/huawei/hg556a/Kconfig
new file mode 100644
index 000000000..88622d0e6
--- /dev/null
+++ b/roms/u-boot/board/huawei/hg556a/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_HUAWEI_HG556A
+
+config SYS_BOARD
+	default "hg556a"
+
+config SYS_VENDOR
+	default "huawei"
+
+config SYS_CONFIG_NAME
+	default "huawei_hg556a"
+
+endif
diff --git a/roms/u-boot/board/huawei/hg556a/MAINTAINERS b/roms/u-boot/board/huawei/hg556a/MAINTAINERS
new file mode 100644
index 000000000..3ead7e4dd
--- /dev/null
+++ b/roms/u-boot/board/huawei/hg556a/MAINTAINERS
@@ -0,0 +1,6 @@
+HUAWEI HG556A BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/huawei/hg556a/
+F:	include/configs/huawei_hg556a.h
+F:	configs/huawei_hg556a_ram_defconfig
diff --git a/roms/u-boot/board/huawei/hg556a/Makefile b/roms/u-boot/board/huawei/hg556a/Makefile
new file mode 100644
index 000000000..43e9be6bb
--- /dev/null
+++ b/roms/u-boot/board/huawei/hg556a/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += hg556a.o
diff --git a/roms/u-boot/board/huawei/hg556a/hg556a.c b/roms/u-boot/board/huawei/hg556a/hg556a.c
new file mode 100644
index 000000000..1e4b7281d
--- /dev/null
+++ b/roms/u-boot/board/huawei/hg556a/hg556a.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/ids/ids8313/Kconfig b/roms/u-boot/board/ids/ids8313/Kconfig
new file mode 100644
index 000000000..d165b4be7
--- /dev/null
+++ b/roms/u-boot/board/ids/ids8313/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IDS8313
+
+config SYS_BOARD
+	default "ids8313"
+
+config SYS_VENDOR
+	default "ids"
+
+config SYS_CONFIG_NAME
+	default "ids8313"
+
+endif
diff --git a/roms/u-boot/board/ids/ids8313/MAINTAINERS b/roms/u-boot/board/ids/ids8313/MAINTAINERS
new file mode 100644
index 000000000..c5b2f9ed0
--- /dev/null
+++ b/roms/u-boot/board/ids/ids8313/MAINTAINERS
@@ -0,0 +1,6 @@
+IDS8313 BOARD
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	board/ids/ids8313/
+F:	include/configs/ids8313.h
+F:	configs/ids8313_defconfig
diff --git a/roms/u-boot/board/ids/ids8313/Makefile b/roms/u-boot/board/ids/ids8313/Makefile
new file mode 100644
index 000000000..91e4ad6f1
--- /dev/null
+++ b/roms/u-boot/board/ids/ids8313/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2013
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+
+obj-y	= ids8313.o
diff --git a/roms/u-boot/board/ids/ids8313/ids8313.c b/roms/u-boot/board/ids/ids8313/ids8313.c
new file mode 100644
index 000000000..45c77a249
--- /dev/null
+++ b/roms/u-boot/board/ids/ids8313/ids8313.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (c) 2011 IDS GmbH, Germany
+ * ids8313.c - ids8313 board support.
+ *
+ * Sergej Stepanov <ste@ids.de>
+ * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <mpc83xx.h>
+#include <spi.h>
+#include <asm/bitops.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+/** CPLD contains the info about:
+ * - board type: *pCpld & 0xF0
+ * - hw-revision: *pCpld & 0x0F
+ * - cpld-revision: *pCpld+1
+ */
+int checkboard(void)
+{
+	char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
+	u8 u8Vers = readb(pcpld);
+	u8 u8Revs = readb(pcpld + 1);
+
+	printf("Board: ");
+	switch (u8Vers & 0xF0) {
+	case '\x40':
+		printf("CU73X");
+		break;
+	case '\x50':
+		printf("CC73X");
+		break;
+	default:
+		printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
+		return 0;
+	}
+	printf("\nInfo:  HW-Rev: %i, CPLD-Rev: %i\n",
+	       u8Vers & 0x0F, u8Revs & 0xFF);
+	return 0;
+}
+
+/*
+ *  fixed sdram init
+ */
+int fixed_sdram(unsigned long config)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE << 20;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+		 (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+	sync();
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	udelay(50000);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], config);
+
+	/* currently we use only one CS, so disable the other banks */
+	out_be32(&im->ddr.cs_config[1], 0);
+	out_be32(&im->ddr.cs_config[2], 0);
+	out_be32(&im->ddr.cs_config[3], 0);
+
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+	sync();
+	udelay(300);
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	/* now check the real size */
+	disable_addr_trans();
+	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
+	enable_addr_trans();
+#endif
+	return msize;
+}
+
+static int setup_sdram(void)
+{
+	u32 msize = CONFIG_SYS_DDR_SIZE << 20;
+	long int size_01, size_02;
+
+	size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
+	size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
+
+	if (size_01 > size_02)
+		msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
+	else
+		msize = size_02;
+
+	return msize;
+}
+
+int dram_init(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	fsl_lbc_t *lbc = &im->im_lbc;
+	u32 msize = 0;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -ENXIO;
+
+	msize = setup_sdram();
+
+	out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
+	out_be32(&lbc->mrtpr, 0x20000000);
+	sync();
+
+	gd->ram_size = msize;
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
+
+/* gpio mask for spi_cs */
+#define IDSCPLD_SPI_CS_MASK		0x00000001
+/* spi_cs multiplexed through cpld */
+#define IDSCPLD_SPI_CS_BASE		(CONFIG_SYS_CPLD_BASE + 0xf)
+
+#if defined(CONFIG_MISC_INIT_R)
+/* srp umcr mask for rts */
+#define IDSUMCR_RTS_MASK 0x04
+int misc_init_r(void)
+{
+	/*srp*/
+	duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
+	duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
+
+	gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+	u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+	/* deactivate spi_cs channels */
+	out_8(spi_base, 0);
+	/* deactivate the spi_cs */
+	setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
+	/*srp - deactivate rts*/
+	out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
+	out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
+
+
+	gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MPC8XXX_SPI
+/*
+ * The following are used to control the SPI chip selects
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && ((cs >= 0) && (cs <= 2));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+	u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+	/* select the spi_cs channel */
+	out_8(spi_base, 1 << slave->cs);
+	/* activate the spi_cs */
+	clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+	u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+	/* select the spi_cs channel */
+	out_8(spi_base, 1 << slave->cs);
+	/* deactivate the spi_cs */
+	setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
+}
+#endif
diff --git a/roms/u-boot/board/imgtec/boston/Kconfig b/roms/u-boot/board/imgtec/boston/Kconfig
new file mode 100644
index 000000000..ab76a3c62
--- /dev/null
+++ b/roms/u-boot/board/imgtec/boston/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_BOSTON
+
+config SYS_BOARD
+	default "boston"
+
+config SYS_VENDOR
+	default "imgtec"
+
+config SYS_CONFIG_NAME
+	default "boston"
+
+config SYS_TEXT_BASE
+	default 0x9fc00000 if 32BIT
+	default 0xffffffff9fc00000 if 64BIT
+
+endif
diff --git a/roms/u-boot/board/imgtec/boston/MAINTAINERS b/roms/u-boot/board/imgtec/boston/MAINTAINERS
new file mode 100644
index 000000000..07f6156ff
--- /dev/null
+++ b/roms/u-boot/board/imgtec/boston/MAINTAINERS
@@ -0,0 +1,13 @@
+BOSTON BOARD
+M:	Paul Burton <paul.burton@mips.com>
+S:	Maintained
+F:	board/imgtec/boston/
+F:	include/configs/boston.h
+F:	configs/boston32r2_defconfig
+F:	configs/boston32r2el_defconfig
+F:	configs/boston32r6_defconfig
+F:	configs/boston32r6el_defconfig
+F:	configs/boston64r2_defconfig
+F:	configs/boston64r2el_defconfig
+F:	configs/boston64r6_defconfig
+F:	configs/boston64r6el_defconfig
diff --git a/roms/u-boot/board/imgtec/boston/Makefile b/roms/u-boot/board/imgtec/boston/Makefile
new file mode 100644
index 000000000..4271a4def
--- /dev/null
+++ b/roms/u-boot/board/imgtec/boston/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2016 Imagination Technologies
+
+obj-y += checkboard.o
+obj-y += ddr.o
+obj-y += dt.o
+obj-y += lowlevel_init.o
diff --git a/roms/u-boot/board/imgtec/boston/boston-lcd.h b/roms/u-boot/board/imgtec/boston/boston-lcd.h
new file mode 100644
index 000000000..5f5cd0fe1
--- /dev/null
+++ b/roms/u-boot/board/imgtec/boston/boston-lcd.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ */
+
+#ifndef __BOARD_BOSTON_LCD_H__
+#define __BOARD_BOSTON_LCD_H__
+
+/**
+ * lowlevel_display() - Display a message on Boston's LCD
+ * @msg: The string to display
+ *
+ * Display the string @msg on the 7 character LCD display of the Boston board.
+ * This is typically used for debug or to present some form of status
+ * indication to the user, allowing faults to be identified when things go
+ * wrong early enough that the UART isn't up.
+ */
+void lowlevel_display(const char msg[static 8]);
+
+#endif /* __BOARD_BOSTON_LCD_H__ */
diff --git a/roms/u-boot/board/imgtec/boston/boston-regs.h b/roms/u-boot/board/imgtec/boston/boston-regs.h
new file mode 100644
index 000000000..673a61cfb
--- /dev/null
+++ b/roms/u-boot/board/imgtec/boston/boston-regs.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ */
+
+#ifndef __BOARD_BOSTON_REGS_H__
+#define __BOARD_BOSTON_REGS_H__
+
+#include <asm/addrspace.h>
+
+#define BOSTON_PLAT_BASE		CKSEG1ADDR(0x17ffd000)
+#define BOSTON_LCD_BASE			CKSEG1ADDR(0x17fff000)
+
+/*
+ * Platform Register Definitions
+ */
+#define BOSTON_PLAT_CORE_CL		(BOSTON_PLAT_BASE + 0x04)
+
+#define BOSTON_PLAT_DDR3STAT		(BOSTON_PLAT_BASE + 0x14)
+# define BOSTON_PLAT_DDR3STAT_CALIB	(1 << 2)
+
+#define BOSTON_PLAT_DDRCONF0		(BOSTON_PLAT_BASE + 0x38)
+# define BOSTON_PLAT_DDRCONF0_SIZE	(0xf << 0)
+
+#endif /* __BOARD_BOSTON_REGS_H__ */
diff --git a/roms/u-boot/board/imgtec/boston/checkboard.c b/roms/u-boot/board/imgtec/boston/checkboard.c
new file mode 100644
index 000000000..1b8a47d25
--- /dev/null
+++ b/roms/u-boot/board/imgtec/boston/checkboard.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+
+#include "boston-lcd.h"
+#include "boston-regs.h"
+
+int checkboard(void)
+{
+	u32 changelist;
+
+	lowlevel_display("U-boot  ");
+
+	printf("Board: MIPS Boston\n");
+
+	printf("CPU:   0x%08x", read_c0_prid());
+	changelist = __raw_readl((uint32_t *)BOSTON_PLAT_CORE_CL);
+	if (changelist > 1)
+		printf(" cl%x", changelist);
+	putc('\n');
+
+	return 0;
+}
diff --git a/roms/u-boot/board/imgtec/boston/config.mk b/roms/u-boot/board/imgtec/boston/config.mk
new file mode 100644
index 000000000..c1e242f10
--- /dev/null
+++ b/roms/u-boot/board/imgtec/boston/config.mk
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+quiet_cmd_srec_cat = SRECCAT $@
+      cmd_srec_cat = srec_cat -output $@ -$2 \
+			$< -binary \
+			-fill 0x00 -within $< -binary -range-pad 16 \
+			-offset $3
+
+u-boot.mcs: u-boot.bin
+	$(call cmd,srec_cat,intel,0x7c00000)
+
+# if srec_cat is present build u-boot.mcs by default
+has_srec_cat = $(call try-run,srec_cat -VERSion,y,n)
+INPUTS-$(has_srec_cat) += u-boot.mcs
+CLEAN_FILES += u-boot.mcs
diff --git a/roms/u-boot/board/imgtec/boston/ddr.c b/roms/u-boot/board/imgtec/boston/ddr.c
new file mode 100644
index 000000000..182f79b91
--- /dev/null
+++ b/roms/u-boot/board/imgtec/boston/ddr.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+
+#include <asm/io.h>
+
+#include "boston-regs.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0);
+
+	gd->ram_size = (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) <<
+			30;
+
+	return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) {
+		/* 2GB wrapped around to 0 */
+		return CKSEG0ADDR(256 << 20);
+	}
+
+	return min_t(unsigned long, gd->ram_top, CKSEG0ADDR(256 << 20));
+}
diff --git a/roms/u-boot/board/imgtec/boston/dt.c b/roms/u-boot/board/imgtec/boston/dt.c
new file mode 100644
index 000000000..bf772ff5d
--- /dev/null
+++ b/roms/u-boot/board/imgtec/boston/dt.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <asm/global_data.h>
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	u64 mem_start[2], mem_size[2];
+	int mem_regions;
+
+	mem_start[0] = 0;
+	mem_size[0] = min_t(u64, 256llu << 20, gd->ram_size);
+	mem_regions = 1;
+
+	if (gd->ram_size > mem_size[0]) {
+		mem_start[1] = 0x80000000 + mem_size[0];
+		mem_size[1] = gd->ram_size - mem_size[0];
+		mem_regions++;
+	}
+
+	return fdt_fixup_memory_banks(blob, mem_start, mem_size, mem_regions);
+}
diff --git a/roms/u-boot/board/imgtec/boston/lowlevel_init.S b/roms/u-boot/board/imgtec/boston/lowlevel_init.S
new file mode 100644
index 000000000..2761bf2cd
--- /dev/null
+++ b/roms/u-boot/board/imgtec/boston/lowlevel_init.S
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ */
+
+#include <config.h>
+
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+
+#include "boston-regs.h"
+
+.data
+
+msg_ddr_cal:	.ascii "DDR Cal "
+msg_ddr_ok:	.ascii "DDR OK  "
+
+.text
+
+LEAF(lowlevel_init)
+	move	s0, ra
+
+	PTR_LA	a0, msg_ddr_cal
+	bal	lowlevel_display
+
+	PTR_LI	t0, BOSTON_PLAT_DDR3STAT
+1:	lw	t1, 0(t0)
+	andi	t1, t1, BOSTON_PLAT_DDR3STAT_CALIB
+	beqz	t1, 1b
+
+	PTR_LA	a0, msg_ddr_ok
+	bal	lowlevel_display
+
+	jr	s0
+	END(lowlevel_init)
+
+LEAF(lowlevel_display)
+	.set	push
+	.set	noat
+	PTR_LI	AT, BOSTON_LCD_BASE
+#ifdef CONFIG_64BIT
+	ld	k1, 0(a0)
+	sd	k1, 0(AT)
+#else
+	lw	k1, 0(a0)
+	sw	k1, 0(AT)
+	lw	k1, 4(a0)
+	sw	k1, 4(AT)
+#endif
+	.set	pop
+	jr	ra
+	END(lowlevel_display)
diff --git a/roms/u-boot/board/imgtec/ci20/Kconfig b/roms/u-boot/board/imgtec/ci20/Kconfig
new file mode 100644
index 000000000..82bf65d64
--- /dev/null
+++ b/roms/u-boot/board/imgtec/ci20/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_JZ4780_CI20
+
+config SYS_BOARD
+	default "ci20"
+
+config SYS_VENDOR
+	default "imgtec"
+
+config SYS_CONFIG_NAME
+	default "ci20"
+
+config SYS_TEXT_BASE
+	default 0x80000000
+
+endif
diff --git a/roms/u-boot/board/imgtec/ci20/MAINTAINERS b/roms/u-boot/board/imgtec/ci20/MAINTAINERS
new file mode 100644
index 000000000..dca6bf353
--- /dev/null
+++ b/roms/u-boot/board/imgtec/ci20/MAINTAINERS
@@ -0,0 +1,6 @@
+Creator CI20 BOARD
+M:      Ezequiel Garcia <ezequiel@collabora.com>
+S:      Maintained
+F:      board/imgtec/ci20/
+F:      include/configs/ci20.h
+F:      configs/ci20_mmc_defconfig
diff --git a/roms/u-boot/board/imgtec/ci20/Makefile b/roms/u-boot/board/imgtec/ci20/Makefile
new file mode 100644
index 000000000..7843b4679
--- /dev/null
+++ b/roms/u-boot/board/imgtec/ci20/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := ci20.o
diff --git a/roms/u-boot/board/imgtec/ci20/README b/roms/u-boot/board/imgtec/ci20/README
new file mode 100644
index 000000000..07d89d7e2
--- /dev/null
+++ b/roms/u-boot/board/imgtec/ci20/README
@@ -0,0 +1,10 @@
+CI20 U-Boot
+
+Installation to an SD card:
+  Repartition your card with an MBR such that the first partition starts at an
+  offset of no less than 270KB. Then install U-Boot SPL & the full U-Boot image
+  to the card like so:
+
+    dd if=spl/u-boot-spl.bin of=/dev/sdX obs=512 seek=1
+    dd if=u-boot-dtb.img of=/dev/sdX obs=1K seek=14
+    sync
diff --git a/roms/u-boot/board/imgtec/ci20/ci20.c b/roms/u-boot/board/imgtec/ci20/ci20.c
new file mode 100644
index 000000000..7ee175d40
--- /dev/null
+++ b/roms/u-boot/board/imgtec/ci20/ci20.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CI20 setup code
+ *
+ * Copyright (c) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <mach/jz4780.h>
+#include <mach/jz4780_dram.h>
+#include <mach/jz4780_gpio.h>
+
+struct ci20_otp {
+	u32	serial_number;
+	u32	date;
+	u8	manufacturer[2];
+	u8	mac[6];
+} __packed;
+
+static void ci20_mux_mmc(void)
+{
+	void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+
+	/* setup MSC1 pins */
+	writel(0x30f00000, gpio_regs + GPIO_PXINTC(4));
+	writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4));
+	writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4));
+	writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4));
+	writel(0x30f00000, gpio_regs + GPIO_PXPENC(4));
+	jz4780_clk_ungate_mmc();
+}
+
+#ifndef CONFIG_SPL_BUILD
+
+static void ci20_mux_eth(void)
+{
+	void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+
+#ifdef CONFIG_MTD_RAW_NAND
+	/* setup pins (some already setup for NAND) */
+	writel(0x04030000, gpio_regs + GPIO_PXINTC(0));
+	writel(0x04030000, gpio_regs + GPIO_PXMASKC(0));
+	writel(0x04030000, gpio_regs + GPIO_PXPAT1C(0));
+	writel(0x04030000, gpio_regs + GPIO_PXPAT0C(0));
+	writel(0x04030000, gpio_regs + GPIO_PXPENS(0));
+#else
+	/* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */
+	writel(0x0dff00ff, gpio_regs + GPIO_PXINTC(0));
+	writel(0x0dff00ff, gpio_regs + GPIO_PXMASKC(0));
+	writel(0x0dff00ff, gpio_regs + GPIO_PXPAT1C(0));
+	writel(0x0dff00ff, gpio_regs + GPIO_PXPAT0C(0));
+	writel(0x0dff00ff, gpio_regs + GPIO_PXPENS(0));
+	writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
+	writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
+	writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
+	writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
+	writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
+#endif
+}
+
+static void ci20_mux_jtag(void)
+{
+#ifdef CONFIG_JTAG
+	void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+
+	/* enable JTAG */
+	writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
+	writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
+	writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
+	writel(3 << 30, gpio_regs + GPIO_PXPAT0C(0));
+#endif
+}
+
+static void ci20_mux_nand(void)
+{
+	void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+
+	/* setup pins */
+	writel(0x002c00ff, gpio_regs + GPIO_PXINTC(0));
+	writel(0x002c00ff, gpio_regs + GPIO_PXMASKC(0));
+	writel(0x002c00ff, gpio_regs + GPIO_PXPAT1C(0));
+	writel(0x002c00ff, gpio_regs + GPIO_PXPAT0C(0));
+	writel(0x002c00ff, gpio_regs + GPIO_PXPENS(0));
+	writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
+	writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
+	writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
+	writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
+	writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
+
+	/* FRB0_N */
+	jz47xx_gpio_direction_input(JZ_GPIO(0, 20));
+	writel(20, gpio_regs + GPIO_PXPENS(0));
+
+	/* disable write protect */
+	jz47xx_gpio_direction_output(JZ_GPIO(5, 22), 1);
+}
+
+static void ci20_mux_uart(void)
+{
+	void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+
+	/* UART0 */
+	writel(0x9, gpio_regs + GPIO_PXINTC(5));
+	writel(0x9, gpio_regs + GPIO_PXMASKC(5));
+	writel(0x9, gpio_regs + GPIO_PXPAT1C(5));
+	writel(0x9, gpio_regs + GPIO_PXPAT0C(5));
+	writel(0x9, gpio_regs + GPIO_PXPENC(5));
+	jz4780_clk_ungate_uart(0);
+
+	/* UART 1 and 2 */
+	jz4780_clk_ungate_uart(1);
+	jz4780_clk_ungate_uart(2);
+
+#ifndef CONFIG_JTAG
+	/* UART3 */
+	writel(1 << 12, gpio_regs + GPIO_PXINTC(3));
+	writel(1 << 12, gpio_regs + GPIO_PXMASKS(3));
+	writel(1 << 12, gpio_regs + GPIO_PXPAT1S(3));
+	writel(1 << 12, gpio_regs + GPIO_PXPAT0C(3));
+	writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
+	writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
+	writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
+	writel(1 << 30, gpio_regs + GPIO_PXPAT0C(0));
+	writel(1 << 31, gpio_regs + GPIO_PXPAT0S(0));
+	jz4780_clk_ungate_uart(3);
+#endif
+
+	/* UART4 */
+	writel(0x100400, gpio_regs + GPIO_PXINTC(2));
+	writel(0x100400, gpio_regs + GPIO_PXMASKC(2));
+	writel(0x100400, gpio_regs + GPIO_PXPAT1S(2));
+	writel(0x100400, gpio_regs + GPIO_PXPAT0C(2));
+	writel(0x100400, gpio_regs + GPIO_PXPENC(2));
+	jz4780_clk_ungate_uart(4);
+}
+
+int board_early_init_f(void)
+{
+	ci20_mux_jtag();
+	ci20_mux_uart();
+
+	ci20_mux_eth();
+	ci20_mux_mmc();
+	ci20_mux_nand();
+
+	/* SYS_POWER_IND high (LED blue, VBUS off) */
+	jz47xx_gpio_direction_output(JZ_GPIO(5, 15), 0);
+
+	/* LEDs off */
+	jz47xx_gpio_direction_output(JZ_GPIO(2, 0), 0);
+	jz47xx_gpio_direction_output(JZ_GPIO(2, 1), 0);
+	jz47xx_gpio_direction_output(JZ_GPIO(2, 2), 0);
+	jz47xx_gpio_direction_output(JZ_GPIO(2, 3), 0);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	const u32 efuse_clk = jz4780_clk_get_efuse_clk();
+	struct ci20_otp otp;
+	char manufacturer[3];
+
+	/* Read the board OTP data */
+	jz4780_efuse_init(efuse_clk);
+	jz4780_efuse_read(0x18, 16, (u8 *)&otp);
+
+	/* Set MAC address */
+	if (!is_valid_ethaddr(otp.mac)) {
+		/* no MAC assigned, generate one from the unique chip ID */
+		jz4780_efuse_read(0x8, 4, &otp.mac[0]);
+		jz4780_efuse_read(0x12, 2, &otp.mac[4]);
+		otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01;
+	}
+	eth_env_set_enetaddr("ethaddr", otp.mac);
+
+	/* Put other board information into the environment */
+	env_set_ulong("serial#", otp.serial_number);
+	env_set_ulong("board_date", otp.date);
+	manufacturer[0] = otp.manufacturer[0];
+	manufacturer[1] = otp.manufacturer[1];
+	manufacturer[2] = 0;
+	env_set("board_mfr", manufacturer);
+
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(struct bd_info *bis)
+{
+	/* Enable clock */
+	jz4780_clk_ungate_ethernet();
+
+	/* Enable power (PB25) */
+	jz47xx_gpio_direction_output(JZ_GPIO(1, 25), 1);
+
+	/* Reset (PF12) */
+	mdelay(10);
+	jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 0);
+	mdelay(10);
+	jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 1);
+	mdelay(10);
+
+	return dm9000_initialize(bis);
+}
+#endif /* CONFIG_DRIVER_DM9000 */
+#endif
+
+static u8 ci20_revision(void)
+{
+	void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+	int val;
+
+	jz47xx_gpio_direction_input(JZ_GPIO(2, 18));
+	jz47xx_gpio_direction_input(JZ_GPIO(2, 19));
+
+	/* Enable pullups */
+	writel(BIT(18) | BIT(19), gpio_regs + GPIO_PXPENC(2));
+
+	/* Read PC18/19 for version */
+	val = (!!jz47xx_gpio_get_value(JZ_GPIO(2, 18))) |
+	     ((!!jz47xx_gpio_get_value(JZ_GPIO(2, 19))) << 1);
+
+	if (val == 3)	/* Rev 1 boards had no pulldowns - giving 3 */
+		return 1;
+	if (val == 1)	/* Rev 2 boards pulldown port C bit 18 giving 1 */
+		return 2;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = sdram_size(0) + sdram_size(1);
+	return 0;
+}
+
+/* U-Boot common routines */
+int checkboard(void)
+{
+	printf("Board: Creator CI20 (rev.%d)\n", ci20_revision());
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+int board_mmc_init(struct bd_info *bd)
+{
+	ci20_mux_mmc();
+	return jz_mmc_init((void __iomem *)MSC0_BASE);
+}
+#endif
+
+static const struct jz4780_ddr_config K4B2G0846Q_48_config = {
+	.timing = {
+		(4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
+		(6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
+
+		(4 << DDRC_TIMING2_TCCD_BIT) | (15 << DDRC_TIMING2_TRAS_BIT) |
+		(6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
+
+		(4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
+		(6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
+		(21 << DDRC_TIMING3_TRC_BIT),
+
+		(31 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
+		(4 << DDRC_TIMING4_TCKE_BIT) | (9 << DDRC_TIMING4_TMINSR_BIT) |
+		(8 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
+
+		(8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
+		(4 << DDRC_TIMING5_TWDLAT_BIT),
+
+		(25 << DDRC_TIMING6_TXSRD_BIT) | (12 << DDRC_TIMING6_TFAW_BIT) |
+		(2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
+	},
+
+	/* PHY */
+	/* Mode Register 0 */
+	.mr0 = 0x420,
+#ifdef SDRAM_DISABLE_DLL
+	.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
+#else
+	.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
+#endif
+
+	.ptr0 = 0x002000d4,
+	.ptr1 = 0x02230d40,
+	.ptr2 = 0x04013880,
+
+	.dtpr0 = 0x2a8f6690,
+	.dtpr1 = 0x00400860,
+	.dtpr2 = 0x10042a00,
+
+	.pullup = 0x0b,
+	.pulldn = 0x0b,
+};
+
+static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = {
+	.timing = {
+		(4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
+		(6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
+
+		(4 << DDRC_TIMING2_TCCD_BIT) | (16 << DDRC_TIMING2_TRAS_BIT) |
+		(6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
+
+		(4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
+		(6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
+		(22 << DDRC_TIMING3_TRC_BIT),
+
+		(42 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
+		(4 << DDRC_TIMING4_TCKE_BIT) | (7 << DDRC_TIMING4_TMINSR_BIT) |
+		(3 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
+
+		(8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
+		(4 << DDRC_TIMING5_TWDLAT_BIT),
+
+		(25 << DDRC_TIMING6_TXSRD_BIT) | (20 << DDRC_TIMING6_TFAW_BIT) |
+		(2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
+	},
+
+	/* PHY */
+	/* Mode Register 0 */
+	.mr0 = 0x420,
+#ifdef SDRAM_DISABLE_DLL
+	.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
+#else
+	.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
+#endif
+
+	.ptr0 = 0x002000d4,
+	.ptr1 = 0x02d30d40,
+	.ptr2 = 0x04013880,
+
+	.dtpr0 = 0x2c906690,
+	.dtpr1 = 0x005608a0,
+	.dtpr2 = 0x10042a00,
+
+	.pullup = 0x0e,
+	.pulldn = 0x0e,
+};
+
+#if (CONFIG_SYS_MHZ != 1200)
+#error No DDR configuration for CPU speed
+#endif
+
+const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
+{
+	const int board_revision = ci20_revision();
+
+	if (board_revision == 2)
+		return &K4B2G0846Q_48_config;
+	else /* Fall back to H5TQ2G83CFR RAM */
+		return &H5TQ2G83CFR_48_config;
+}
+#endif
diff --git a/roms/u-boot/board/imgtec/malta/Kconfig b/roms/u-boot/board/imgtec/malta/Kconfig
new file mode 100644
index 000000000..98eb4d16c
--- /dev/null
+++ b/roms/u-boot/board/imgtec/malta/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_MALTA
+
+config SYS_BOARD
+	default "malta"
+
+config SYS_VENDOR
+	default "imgtec"
+
+config SYS_CONFIG_NAME
+	default "malta"
+
+config SYS_TEXT_BASE
+	default 0xbe000000 if 32BIT
+	default 0xffffffffbe000000 if 64BIT
+
+endif
diff --git a/roms/u-boot/board/imgtec/malta/MAINTAINERS b/roms/u-boot/board/imgtec/malta/MAINTAINERS
new file mode 100644
index 000000000..b1cf297f4
--- /dev/null
+++ b/roms/u-boot/board/imgtec/malta/MAINTAINERS
@@ -0,0 +1,9 @@
+MALTA BOARD
+M:	Paul Burton <paul.burton@mips.com>
+S:	Maintained
+F:	board/imgtec/malta/
+F:	include/configs/malta.h
+F:	configs/malta64_defconfig
+F:	configs/malta64el_defconfig
+F:	configs/malta_defconfig
+F:	configs/maltael_defconfig
diff --git a/roms/u-boot/board/imgtec/malta/Makefile b/roms/u-boot/board/imgtec/malta/Makefile
new file mode 100644
index 000000000..d0d84010f
--- /dev/null
+++ b/roms/u-boot/board/imgtec/malta/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= malta.o
+obj-y	+= lowlevel_init.o
+obj-y	+= superio.o
diff --git a/roms/u-boot/board/imgtec/malta/flash-malta-boot.tcl b/roms/u-boot/board/imgtec/malta/flash-malta-boot.tcl
new file mode 100644
index 000000000..972002a8e
--- /dev/null
+++ b/roms/u-boot/board/imgtec/malta/flash-malta-boot.tcl
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2013 Imagination Technologies
+#
+# Programs a MIPS Malta boot flash with a flat binary image.
+
+proc flash-boot { binfile } {
+  puts "flash monitor binary $binfile"
+  config Coherent on
+  config CoherencyDuringLoad on
+
+  if {[endian]=="big"} {
+    puts "CPU in BE mode"
+    flash device sharp_16x32_be;
+  } else {
+    puts "CPU in LE mode"
+    flash device sharp_16x32;
+  }
+
+  flash clear all;
+  flash set 0xBE000000..0xBE0FFFFF
+  flash erase sector 0xbe000000;
+  flash erase sector 0xbe020000;
+  flash erase sector 0xbe040000;
+  flash erase sector 0xbe060000;
+  flash erase sector 0xbe080000;
+  flash erase sector 0xbe0a0000;
+  flash erase sector 0xbe0c0000;
+  flash erase sector 0xbe0e0000;
+  puts "finished erasing boot flash";
+
+  puts "programming flash, please be patient"
+  load bin 0xbe000000 $binfile size4
+
+  flash clear all
+  config CoherencyDuringLoad off
+  puts "finished programming boot flash";
+}
diff --git a/roms/u-boot/board/imgtec/malta/lowlevel_init.S b/roms/u-boot/board/imgtec/malta/lowlevel_init.S
new file mode 100644
index 000000000..ecb4424fd
--- /dev/null
+++ b/roms/u-boot/board/imgtec/malta/lowlevel_init.S
@@ -0,0 +1,231 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ */
+
+#include <config.h>
+#include <gt64120.h>
+#include <msc01.h>
+#include <pci.h>
+
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/malta.h>
+#include <asm/mipsregs.h>
+
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CPU_TO_GT32(_x)		((_x))
+#else
+#define CPU_TO_GT32(_x) (					\
+	(((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) |	\
+	(((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
+#endif
+
+	.text
+	.set noreorder
+
+	.globl	lowlevel_init
+lowlevel_init:
+	/* detect the core card */
+	PTR_LI	t0, CKSEG1ADDR(MALTA_REVISION)
+	lw	t0, 0(t0)
+	srl	t0, t0, MALTA_REVISION_CORID_SHF
+	andi	t0, t0, (MALTA_REVISION_CORID_MSK >> \
+			 MALTA_REVISION_CORID_SHF)
+
+	/* core cards using the gt64120 system controller */
+	li	t1, MALTA_REVISION_CORID_CORE_LV
+	beq	t0, t1, _gt64120
+
+	/* core cards using the MSC01 system controller */
+	 li	t1, MALTA_REVISION_CORID_CORE_FPGA6
+	beq	t0, t1, _msc01
+	 nop
+
+	/* unknown system controller */
+	b	.
+	 nop
+
+	/*
+	 * Load BAR registers of GT64120 as done by YAMON
+	 *
+	 * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
+	 * to the barebox mailing list.
+	 * The subject of the original patch:
+	 *   'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
+	 * URL:
+	 * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
+	 *
+	 * based on write_bootloader() in qemu.git/hw/mips_malta.c
+	 * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
+	 */
+_gt64120:
+	/* move GT64120 registers from 0x14000000 to 0x1be00000 */
+	PTR_LI	t1, CKSEG1ADDR(GT_DEF_BASE)
+	li	t0, CPU_TO_GT32(0xdf000000)
+	sw	t0, GT_ISD_OFS(t1)
+
+	/* setup MEM-to-PCI0 mapping */
+	PTR_LI	t1, CKSEG1ADDR(MALTA_GT_BASE)
+
+	/* setup PCI0 io window to 0x18000000-0x181fffff */
+	li	t0, CPU_TO_GT32(0xc0000000)
+	sw	t0, GT_PCI0IOLD_OFS(t1)
+	li	t0, CPU_TO_GT32(0x40000000)
+	sw	t0, GT_PCI0IOHD_OFS(t1)
+
+	/* setup PCI0 mem windows */
+	li	t0, CPU_TO_GT32(0x80000000)
+	sw	t0, GT_PCI0M0LD_OFS(t1)
+	li	t0, CPU_TO_GT32(0x3f000000)
+	sw	t0, GT_PCI0M0HD_OFS(t1)
+
+	li	t0, CPU_TO_GT32(0xc1000000)
+	sw	t0, GT_PCI0M1LD_OFS(t1)
+	li	t0, CPU_TO_GT32(0x5e000000)
+	sw	t0, GT_PCI0M1HD_OFS(t1)
+
+	jr	ra
+	 nop
+
+	/*
+	 *
+	 */
+_msc01:
+	/* setup peripheral bus controller clock divide */
+	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
+	li	t1, 0x1 << MSC01_PBC_CLKCFG_SHF
+	sw	t1, MSC01_PBC_CLKCFG_OFS(t0)
+
+	/* tweak peripheral bus controller timings */
+	li	t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
+		    (0x1 << MSC01_PBC_CS0TIM_CAT_SHF)
+	sw	t1, MSC01_PBC_CS0TIM_OFS(t0)
+	li	t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
+		    (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \
+		    (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \
+		    (0x2 << MSC01_PBC_CS0RW_WAT_SHF)
+	sw	t1, MSC01_PBC_CS0RW_OFS(t0)
+	lw	t1, MSC01_PBC_CS0CFG_OFS(t0)
+	li	t2, MSC01_PBC_CS0CFG_DTYP_MSK
+	and	t1, t2
+	ori	t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \
+		    (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \
+		    (0x10 << MSC01_PBC_CS0CFG_WS_SHF)
+	sw	t1, MSC01_PBC_CS0CFG_OFS(t0)
+
+	/* setup basic address decode */
+	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
+	li	t1, 0x0
+	li	t2, -CONFIG_SYS_MEM_SIZE
+	sw	t1, MSC01_BIU_MCBAS1L_OFS(t0)
+	sw	t2, MSC01_BIU_MCMSK1L_OFS(t0)
+	sw	t1, MSC01_BIU_MCBAS2L_OFS(t0)
+	sw	t2, MSC01_BIU_MCMSK2L_OFS(t0)
+
+	/* initialise IP1 - unused */
+	li	t1, MALTA_MSC01_IP1_BASE
+	li	t2, -MALTA_MSC01_IP1_SIZE
+	sw	t1, MSC01_BIU_IP1BAS1L_OFS(t0)
+	sw	t2, MSC01_BIU_IP1MSK1L_OFS(t0)
+	sw	t1, MSC01_BIU_IP1BAS2L_OFS(t0)
+	sw	t2, MSC01_BIU_IP1MSK2L_OFS(t0)
+
+	/* initialise IP2 - PCI */
+	li	t1, MALTA_MSC01_IP2_BASE1
+	li	t2, -MALTA_MSC01_IP2_SIZE1
+	sw	t1, MSC01_BIU_IP2BAS1L_OFS(t0)
+	sw	t2, MSC01_BIU_IP2MSK1L_OFS(t0)
+	li	t1, MALTA_MSC01_IP2_BASE2
+	li	t2, -MALTA_MSC01_IP2_SIZE2
+	sw	t1, MSC01_BIU_IP2BAS2L_OFS(t0)
+	sw	t2, MSC01_BIU_IP2MSK2L_OFS(t0)
+
+	/* initialise IP3 - peripheral bus controller */
+	li	t1, MALTA_MSC01_IP3_BASE
+	li	t2, -MALTA_MSC01_IP3_SIZE
+	sw	t1, MSC01_BIU_IP3BAS1L_OFS(t0)
+	sw	t2, MSC01_BIU_IP3MSK1L_OFS(t0)
+	sw	t1, MSC01_BIU_IP3BAS2L_OFS(t0)
+	sw	t2, MSC01_BIU_IP3MSK2L_OFS(t0)
+
+	/* setup PCI memory */
+	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
+	li	t1, MALTA_MSC01_PCIMEM_BASE
+	li	t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
+	li	t3, MALTA_MSC01_PCIMEM_MAP
+	sw	t1, MSC01_PCI_SC2PMBASL_OFS(t0)
+	sw	t2, MSC01_PCI_SC2PMMSKL_OFS(t0)
+	sw	t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
+
+	/* setup PCI I/O */
+	li	t1, MALTA_MSC01_PCIIO_BASE
+	li	t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
+	li	t3, MALTA_MSC01_PCIIO_MAP
+	sw	t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
+	sw	t2, MSC01_PCI_SC2PIOMSKL_OFS(t0)
+	sw	t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
+
+	/* setup PCI_BAR0 memory window */
+	li	t1, -CONFIG_SYS_MEM_SIZE
+	sw	t1, MSC01_PCI_BAR0_OFS(t0)
+
+	/* setup PCI to SysCon/CPU translation */
+	sw	t1, MSC01_PCI_P2SCMSKL_OFS(t0)
+	sw	zero, MSC01_PCI_P2SCMAPL_OFS(t0)
+
+	/* setup PCI vendor & device IDs */
+	li	t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
+		    (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF)
+	sw	t1, MSC01_PCI_HEAD0_OFS(t0)
+
+	/* setup PCI subsystem vendor & device IDs */
+	sw	t1, MSC01_PCI_HEAD11_OFS(t0)
+
+	/* setup PCI class, revision */
+	li	t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
+		    (0x1 << MSC01_PCI_HEAD2_REV_SHF)
+	sw	t1, MSC01_PCI_HEAD2_OFS(t0)
+
+	/* ensure a sane setup */
+	sw	zero, MSC01_PCI_HEAD3_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD4_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD5_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD6_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD7_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD8_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD9_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD10_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD12_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD13_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD14_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD15_OFS(t0)
+
+	/* setup PCI command register */
+	li	t1, (PCI_COMMAND_FAST_BACK | \
+		     PCI_COMMAND_SERR | \
+		     PCI_COMMAND_PARITY | \
+		     PCI_COMMAND_MASTER | \
+		     PCI_COMMAND_MEMORY)
+	sw	t1, MSC01_PCI_HEAD1_OFS(t0)
+
+	/* setup PCI byte swapping */
+#ifdef CONFIG_SYS_BIG_ENDIAN
+	li	t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
+		    (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF)
+	sw	t1, MSC01_PCI_SWAP_OFS(t0)
+#else
+	sw	zero, MSC01_PCI_SWAP_OFS(t0)
+#endif
+
+	/* enable PCI host configuration cycles */
+	lw	t1, MSC01_PCI_CFG_OFS(t0)
+	li	t2, MSC01_PCI_CFG_RA_MSK | \
+		    MSC01_PCI_CFG_G_MSK | \
+		    MSC01_PCI_CFG_EN_MSK
+	or	t1, t1, t2
+	sw	t1, MSC01_PCI_CFG_OFS(t0)
+
+	jr	ra
+	 nop
diff --git a/roms/u-boot/board/imgtec/malta/malta.c b/roms/u-boot/board/imgtec/malta/malta.c
new file mode 100644
index 000000000..c04f72796
--- /dev/null
+++ b/roms/u-boot/board/imgtec/malta/malta.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 Imagination Technologies
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <pci.h>
+#include <pci_gt64120.h>
+#include <pci_msc01.h>
+#include <rtc.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/malta.h>
+
+#include "superio.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum core_card {
+	CORE_UNKNOWN,
+	CORE_LV,
+	CORE_FPGA6,
+};
+
+enum sys_con {
+	SYSCON_UNKNOWN,
+	SYSCON_GT64120,
+	SYSCON_MSC01,
+};
+
+static void malta_lcd_puts(const char *str)
+{
+	int i;
+	void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
+
+	/* print up to 8 characters of the string */
+	for (i = 0; i < min((int)strlen(str), 8); i++) {
+		__raw_writel(str[i], reg);
+		reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
+	}
+
+	/* fill the rest of the display with spaces */
+	for (; i < 8; i++) {
+		__raw_writel(' ', reg);
+		reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
+	}
+}
+
+static enum core_card malta_core_card(void)
+{
+	u32 corid, rev;
+	const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
+
+	rev = __raw_readl(reg);
+	corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
+
+	switch (corid) {
+	case MALTA_REVISION_CORID_CORE_LV:
+		return CORE_LV;
+
+	case MALTA_REVISION_CORID_CORE_FPGA6:
+		return CORE_FPGA6;
+
+	default:
+		return CORE_UNKNOWN;
+	}
+}
+
+static enum sys_con malta_sys_con(void)
+{
+	switch (malta_core_card()) {
+	case CORE_LV:
+		return SYSCON_GT64120;
+
+	case CORE_FPGA6:
+		return SYSCON_MSC01;
+
+	default:
+		return SYSCON_UNKNOWN;
+	}
+}
+
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_MEM_SIZE;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	enum core_card core;
+
+	malta_lcd_puts("U-Boot");
+	puts("Board: MIPS Malta");
+
+	core = malta_core_card();
+	switch (core) {
+	case CORE_LV:
+		puts(" CoreLV");
+		break;
+
+	case CORE_FPGA6:
+		puts(" CoreFPGA6");
+		break;
+
+	default:
+		puts(" CoreUnknown");
+	}
+
+	putc('\n');
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	return pci_eth_init(bis);
+}
+
+void _machine_restart(void)
+{
+	void __iomem *reset_base;
+
+	reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
+	__raw_writel(GORESET, reset_base);
+	mdelay(1000);
+}
+
+int board_early_init_f(void)
+{
+	ulong io_base;
+
+	/* choose correct PCI I/O base */
+	switch (malta_sys_con()) {
+	case SYSCON_GT64120:
+		io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
+		break;
+
+	case SYSCON_MSC01:
+		io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
+		break;
+
+	default:
+		return -1;
+	}
+
+	set_io_port_base(io_base);
+
+	/* setup FDC37M817 super I/O controller */
+	malta_superio_init();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	rtc_reset();
+
+	return 0;
+}
+
+void pci_init_board(void)
+{
+	pci_dev_t bdf;
+	u32 val32;
+	u8 val8;
+
+	switch (malta_sys_con()) {
+	case SYSCON_GT64120:
+		gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
+				 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+				 0x10000000, 0x10000000, 128 * 1024 * 1024,
+				 0x00000000, 0x00000000, 0x20000);
+		break;
+
+	default:
+	case SYSCON_MSC01:
+		msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
+			       0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+			       MALTA_MSC01_PCIMEM_MAP,
+			       CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
+			       MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
+			       0x00000000, MALTA_MSC01_PCIIO_SIZE);
+		break;
+	}
+
+	bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
+			      PCI_DEVICE_ID_INTEL_82371AB_0, 0);
+	if (bdf == -1)
+		panic("Failed to find PIIX4 PCI bridge\n");
+
+	/* setup PCI interrupt routing */
+	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
+	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
+	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
+	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
+
+	/* mux SERIRQ onto SERIRQ pin */
+	pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
+	val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
+	pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
+
+	/* enable SERIRQ - Linux currently depends upon this */
+	pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
+	val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
+	pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
+
+	bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
+			      PCI_DEVICE_ID_INTEL_82371AB, 0);
+	if (bdf == -1)
+		panic("Failed to find PIIX4 IDE controller\n");
+
+	/* enable bus master & IO access */
+	val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+	pci_write_config_dword(bdf, PCI_COMMAND, val32);
+
+	/* set latency */
+	pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
+
+	/* enable IDE/ATA */
+	pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
+			       PCI_CFG_PIIX4_IDETIM_IDE);
+	pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
+			       PCI_CFG_PIIX4_IDETIM_IDE);
+}
diff --git a/roms/u-boot/board/imgtec/malta/superio.c b/roms/u-boot/board/imgtec/malta/superio.c
new file mode 100644
index 000000000..aba11e25b
--- /dev/null
+++ b/roms/u-boot/board/imgtec/malta/superio.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ *
+ * Setup code for the FDC37M817 super I/O controller
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define SIO_CONF_PORT		0x3f0
+#define SIO_DATA_PORT		0x3f1
+
+enum sio_conf_key {
+	SIOCONF_DEVNUM		= 0x07,
+	SIOCONF_ACTIVATE	= 0x30,
+	SIOCONF_ENTER_SETUP	= 0x55,
+	SIOCONF_BASE_HIGH	= 0x60,
+	SIOCONF_BASE_LOW	= 0x61,
+	SIOCONF_PRIMARY_INT	= 0x70,
+	SIOCONF_EXIT_SETUP	= 0xaa,
+	SIOCONF_MODE		= 0xf0,
+};
+
+static struct {
+	u8 key;
+	u8 data;
+} sio_config[] = {
+	/* tty0 */
+	{ SIOCONF_DEVNUM,	0x04 },
+	{ SIOCONF_BASE_HIGH,	0x03 },
+	{ SIOCONF_BASE_LOW,	0xf8 },
+	{ SIOCONF_MODE,		0x02 },
+	{ SIOCONF_PRIMARY_INT,	0x04 },
+	{ SIOCONF_ACTIVATE,	0x01 },
+
+	/* tty1 */
+	{ SIOCONF_DEVNUM,	0x05 },
+	{ SIOCONF_BASE_HIGH,	0x02 },
+	{ SIOCONF_BASE_LOW,	0xf8 },
+	{ SIOCONF_MODE,		0x02 },
+	{ SIOCONF_PRIMARY_INT,	0x03 },
+	{ SIOCONF_ACTIVATE,	0x01 },
+};
+
+void malta_superio_init(void)
+{
+	unsigned i;
+
+	/* enter config state */
+	outb(SIOCONF_ENTER_SETUP, SIO_CONF_PORT);
+
+	/* configure peripherals */
+	for (i = 0; i < ARRAY_SIZE(sio_config); i++) {
+		outb(sio_config[i].key, SIO_CONF_PORT);
+		outb(sio_config[i].data, SIO_DATA_PORT);
+	}
+
+	/* exit config state */
+	outb(SIOCONF_EXIT_SETUP, SIO_CONF_PORT);
+}
diff --git a/roms/u-boot/board/imgtec/malta/superio.h b/roms/u-boot/board/imgtec/malta/superio.h
new file mode 100644
index 000000000..11e9cef97
--- /dev/null
+++ b/roms/u-boot/board/imgtec/malta/superio.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ *
+ * Setup code for the FDC37M817 super I/O controller
+ */
+
+#ifndef __BOARD_MALTA_SUPERIO_H__
+#define __BOARD_MALTA_SUPERIO_H__
+
+void malta_superio_init(void);
+
+#endif /* __BOARD_MALTA_SUPERIO_H__ */
diff --git a/roms/u-boot/board/imgtec/xilfpga/Kconfig b/roms/u-boot/board/imgtec/xilfpga/Kconfig
new file mode 100644
index 000000000..b0782780f
--- /dev/null
+++ b/roms/u-boot/board/imgtec/xilfpga/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_XILFPGA
+
+config SYS_BOARD
+	default "xilfpga"
+
+config SYS_VENDOR
+	default "imgtec"
+
+config SYS_CONFIG_NAME
+	default "imgtec_xilfpga"
+
+config SYS_TEXT_BASE
+	default 0x80C00000
+
+endif
diff --git a/roms/u-boot/board/imgtec/xilfpga/MAINTAINERS b/roms/u-boot/board/imgtec/xilfpga/MAINTAINERS
new file mode 100644
index 000000000..aa045325e
--- /dev/null
+++ b/roms/u-boot/board/imgtec/xilfpga/MAINTAINERS
@@ -0,0 +1,6 @@
+XILFPGA BOARD
+M:	Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+S:	Maintained
+F:	board/imgtec/xilfpga
+F:	include/configs/xilfpga.h
+F:	configs/imgtec_xilfpga_defconfig
diff --git a/roms/u-boot/board/imgtec/xilfpga/Makefile b/roms/u-boot/board/imgtec/xilfpga/Makefile
new file mode 100644
index 000000000..9aaf9ce26
--- /dev/null
+++ b/roms/u-boot/board/imgtec/xilfpga/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016, Imagination Technologies Ltd.
+# Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+obj-y := xilfpga.o
diff --git a/roms/u-boot/board/imgtec/xilfpga/README b/roms/u-boot/board/imgtec/xilfpga/README
new file mode 100644
index 000000000..ac19d485d
--- /dev/null
+++ b/roms/u-boot/board/imgtec/xilfpga/README
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2016, Imagination Technologies Ltd.
+ *
+ * Zubair Lutfullah Kakakhel, Zubair.Kakakhel@imgtec.com
+ */
+
+MIPSfpga
+=======================================
+
+MIPSfpga is an FPGA based development platform by Imagination Technologies
+As we are dealing with a MIPS core instantiated on an FPGA, specifications
+are fluid and can be varied in RTL.
+
+The example project provided by IMGTEC runs on the Nexys4DDR board by
+Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about
+the example project and the Nexys4DDR board:
+
+- microAptiv UP core m14Kc
+- 50MHz clock speed
+- 128Mbyte DDR RAM	at 0x0000_0000
+- 8Kbyte RAM		at 0x1000_0000
+- axi_intc		at 0x1020_0000
+- axi_uart16550		at 0x1040_0000
+- axi_gpio		at 0x1060_0000
+- axi_i2c		at 0x10A0_0000
+- custom_gpio		at 0x10C0_0000
+- axi_ethernetlite	at 0x10E0_0000
+- 8Kbyte BootRAM	at 0x1FC0_0000
+- 16Mbyte QPI		at 0x1D00_0000
+
+Boot protocol:
+--------------
+
+The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
+This is for easy reprogrammibility via JTAG.
+
+DDR initialization is already handled by a HW IP block.
+
+When the example project bitstream is loaded, the cpu_reset button
+needs to be pressed.
+
+The bootram initializes the cache and axi_uart
+Then checks if there is anything non 0xffff_ffff at location 0x1D40_0000
+
+If there is, then that is considered as u-boot. u-boot is copied from
+0x1D40_0000 to memory and the bootram jumps into u-boot code.
+
+At this point, the board is ready to load the Linux kernel + buildroot initramfs
+
+This can be done in multiple ways:
+
+1- JTAG load the binary and jump into it.
+2- Load kernel stored in the QSPI flash at 0x1D80_0000
+3- Load uImage via tftp. Ethernet works in u-boot.
+   e.g. env set server ip 192.168.154.45; dhcp uImage; bootm
diff --git a/roms/u-boot/board/imgtec/xilfpga/xilfpga.c b/roms/u-boot/board/imgtec/xilfpga/xilfpga.c
new file mode 100644
index 000000000..6a836370e
--- /dev/null
+++ b/roms/u-boot/board/imgtec/xilfpga/xilfpga.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Imagination Technologies MIPSfpga platform code
+ *
+ * Copyright (C) 2016, Imagination Technologies Ltd.
+ *
+ * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* initialize the DDR Controller and PHY */
+int dram_init(void)
+{
+	/* MIG IP block is smart and doesn't need SW
+	 * to do any init */
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;	/* in bytes */
+
+	return 0;
+}
diff --git a/roms/u-boot/board/intel/Kconfig b/roms/u-boot/board/intel/Kconfig
new file mode 100644
index 000000000..7b16ec4dc
--- /dev/null
+++ b/roms/u-boot/board/intel/Kconfig
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+
+if VENDOR_INTEL
+
+choice
+	prompt "Mainboard model"
+	optional
+
+config TARGET_BAYLEYBAY
+	bool "Bayley Bay"
+	help
+	  This is the Intel Bayley Bay Customer Reference Board. It contains an
+	  Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
+	  4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
+	  PCIe and some other sensor interfaces.
+
+config TARGET_CHERRYHILL
+	bool "Cherry Hill"
+	help
+	  This is the Intel Cherry Hill Customer Reference Board. It is in a
+	  mini-ITX form factor containing the Intel Braswell SoC, which has
+	  a 64-bit quad-core, single-thread, Intel Atom processor, along with
+	  serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,
+	  some GPIOs, one HDMI and two DP video out.
+
+config TARGET_COUGARCANYON2
+	bool "Cougar Canyon 2"
+	help
+	  This is the Intel Cougar Canyon 2 Customer Reference Board. It
+	  is built on the Chief River platform with Intel Ivybridge Processor
+	  and Panther Point chipset. The board has 4GB RAM, with some other
+	  peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI.
+
+config TARGET_CROWNBAY
+	bool "Crown Bay"
+	help
+	  This is the Intel Crown Bay Customer Reference Board. It contains
+	  the Intel Atom Processor E6xx populated on the COM Express module
+	  with 1GB DDR2 soldered down memory and a carrier board with the
+	  Intel Platform Controller Hub EG20T, other system components and
+	  peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+
+config TARGET_EDISON
+	bool "Edison"
+	help
+	  This is the Intel Edison Compute Module. It contains a dual core Intel
+	  Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB
+	  eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers.
+
+config TARGET_GALILEO
+	bool "Galileo"
+	help
+	  This is the Intel Galileo board, which is the first in a family of
+	  Arduino-certified development and prototyping boards based on Intel
+	  architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
+	  single-core, single-thread, Intel Pentium processor instrunction set
+	  architecture (ISA) compatible, operating at speeds up to 400Mhz,
+	  along with 256MB DDR3 memory. It supports a wide range of industry
+	  standard I/O interfaces, including a full-sized mini-PCIe slot,
+	  one 100Mb Ethernet port, a microSD card slot, a USB host port and
+	  a USB client port.
+
+config TARGET_MINNOWMAX
+	bool "Minnowboard MAX"
+	help
+	  This is the Intel Minnowboard MAX. It contains an Atom E3800
+	  processor in a small form factor with Ethernet, micro-SD, USB 2,
+	  USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
+	  It requires some binary blobs - see README.x86 for details.
+
+	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+	  by U-Boot matches that value.
+
+config TARGET_SLIMBOOTLOADER
+	bool "slimbootloader"
+	help
+	  This target is used for running U-Boot on top of Slim Bootloader
+	  boot firmware as a payload. Slim Bootloader does memory initialization
+	  and silicon initialization, and it passes necessary information in
+	  HOB (Hand Off Block) to a payload. The payload consumes HOB data
+	  which is generated by Slim Bootloader for its driver initialization.
+	  Slim Bootloader consumes FSP and its HOB, but FSP HOB is cleared
+	  Before launching a payload. Instead, Slim Bootloader generates its
+	  HOB data such as memory info, serial port info and so on.
+	  Refer to doc/board/intel/slimbootloader.rst for the details.
+
+endchoice
+
+source "board/intel/bayleybay/Kconfig"
+source "board/intel/cherryhill/Kconfig"
+source "board/intel/cougarcanyon2/Kconfig"
+source "board/intel/crownbay/Kconfig"
+source "board/intel/edison/Kconfig"
+source "board/intel/galileo/Kconfig"
+source "board/intel/minnowmax/Kconfig"
+source "board/intel/slimbootloader/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/intel/agilex-socdk/MAINTAINERS b/roms/u-boot/board/intel/agilex-socdk/MAINTAINERS
new file mode 100644
index 000000000..fd05e9a4a
--- /dev/null
+++ b/roms/u-boot/board/intel/agilex-socdk/MAINTAINERS
@@ -0,0 +1,13 @@
+SOCFPGA BOARD
+M:	Ley Foon Tan <ley.foon.tan@intel.com>
+M:	Chee Hong Ang <chee.hong.ang@intel.com>
+S:	Maintained
+F:	board/intel/agilex-socdk/
+F:	include/configs/socfpga_agilex_socdk.h
+F:	configs/socfpga_agilex_atf_defconfig
+F:	configs/socfpga_agilex_defconfig
+
+SOCFPGA BOARD WITH VAB
+M:	Siew Chin Lim <elly.siew.chin.lim@intel.com>
+S:	Maintained
+F:	configs/socfpga_agilex_vab_defconfig
diff --git a/roms/u-boot/board/intel/agilex-socdk/Makefile b/roms/u-boot/board/intel/agilex-socdk/Makefile
new file mode 100644
index 000000000..b86223a57
--- /dev/null
+++ b/roms/u-boot/board/intel/agilex-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2019 Intel Corporation <www.intel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0
+#
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/intel/agilex-socdk/socfpga.c b/roms/u-boot/board/intel/agilex-socdk/socfpga.c
new file mode 100644
index 000000000..72a3e0836
--- /dev/null
+++ b/roms/u-boot/board/intel/agilex-socdk/socfpga.c
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/intel/bayleybay/.gitignore b/roms/u-boot/board/intel/bayleybay/.gitignore
new file mode 100644
index 000000000..6eb8a5481
--- /dev/null
+++ b/roms/u-boot/board/intel/bayleybay/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/roms/u-boot/board/intel/bayleybay/Kconfig b/roms/u-boot/board/intel/bayleybay/Kconfig
new file mode 100644
index 000000000..a62249936
--- /dev/null
+++ b/roms/u-boot/board/intel/bayleybay/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_BAYLEYBAY
+
+config SYS_BOARD
+	default "bayleybay"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "baytrail"
+
+config SYS_CONFIG_NAME
+	default "bayleybay"
+
+config SYS_TEXT_BASE
+	default 0xfff00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
+
+config PCIE_ECAM_BASE
+	default 0xe0000000
+
+endif
diff --git a/roms/u-boot/board/intel/bayleybay/MAINTAINERS b/roms/u-boot/board/intel/bayleybay/MAINTAINERS
new file mode 100644
index 000000000..85fa51626
--- /dev/null
+++ b/roms/u-boot/board/intel/bayleybay/MAINTAINERS
@@ -0,0 +1,6 @@
+Intel Bayley Bay
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/intel/bayleybay
+F:	include/configs/bayleybay.h
+F:	configs/bayleybay_defconfig
diff --git a/roms/u-boot/board/intel/bayleybay/Makefile b/roms/u-boot/board/intel/bayleybay/Makefile
new file mode 100644
index 000000000..d19447184
--- /dev/null
+++ b/roms/u-boot/board/intel/bayleybay/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y	+= bayleybay.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/roms/u-boot/board/intel/bayleybay/acpi/mainboard.asl b/roms/u-boot/board/intel/bayleybay/acpi/mainboard.asl
new file mode 100644
index 000000000..2ab938a8d
--- /dev/null
+++ b/roms/u-boot/board/intel/bayleybay/acpi/mainboard.asl
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
+
+/* PS/2 keyboard and mouse */
+Scope (\_SB.PCI0.LPCB)
+{
+	/* 8042 Keyboard */
+	Device (PS2K)
+	{
+		Name(_HID, EISAID("PNP0303"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x60, 0x60, 0x00, 0x01)
+			IO(Decode16, 0x64, 0x64, 0x00, 0x01)
+			IRQNoFlags() { 1 }
+		})
+
+		Method(_STA, 0, Serialized)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+
+	/* 8042 Mouse */
+	Device (PS2M)
+	{
+		Name(_HID, EISAID("PNP0F03"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x60, 0x60, 0x00, 0x01)
+			IO(Decode16, 0x64, 0x64, 0x00, 0x01)
+			IRQNoFlags() { 12 }
+		})
+
+		Method(_STA, 0, Serialized)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+}
diff --git a/roms/u-boot/board/intel/bayleybay/bayleybay.c b/roms/u-boot/board/intel/bayleybay/bayleybay.c
new file mode 100644
index 000000000..4f63c23a1
--- /dev/null
+++ b/roms/u-boot/board/intel/bayleybay/bayleybay.c
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
diff --git a/roms/u-boot/board/intel/bayleybay/dsdt.asl b/roms/u-boot/board/intel/bayleybay/dsdt.asl
new file mode 100644
index 000000000..d2297ef59
--- /dev/null
+++ b/roms/u-boot/board/intel/bayleybay/dsdt.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/roms/u-boot/board/intel/cherryhill/Kconfig b/roms/u-boot/board/intel/cherryhill/Kconfig
new file mode 100644
index 000000000..a4fa004bf
--- /dev/null
+++ b/roms/u-boot/board/intel/cherryhill/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_CHERRYHILL
+
+config SYS_BOARD
+	default "cherryhill"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "braswell"
+
+config SYS_CONFIG_NAME
+	default "cherryhill"
+
+config SYS_TEXT_BASE
+	default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BRASWELL
+	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_MACRONIX
+
+endif
diff --git a/roms/u-boot/board/intel/cherryhill/MAINTAINERS b/roms/u-boot/board/intel/cherryhill/MAINTAINERS
new file mode 100644
index 000000000..6e90f6421
--- /dev/null
+++ b/roms/u-boot/board/intel/cherryhill/MAINTAINERS
@@ -0,0 +1,6 @@
+INTEL CHERRYHILL BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/intel/cherryhill/
+F:	include/configs/cherryhill.h
+F:	configs/cherryhill_defconfig
diff --git a/roms/u-boot/board/intel/cherryhill/Makefile b/roms/u-boot/board/intel/cherryhill/Makefile
new file mode 100644
index 000000000..ff6e14836
--- /dev/null
+++ b/roms/u-boot/board/intel/cherryhill/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y	+= cherryhill.o
diff --git a/roms/u-boot/board/intel/cherryhill/cherryhill.c b/roms/u-boot/board/intel/cherryhill/cherryhill.c
new file mode 100644
index 000000000..c037d5b14
--- /dev/null
+++ b/roms/u-boot/board/intel/cherryhill/cherryhill.c
@@ -0,0 +1,595 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/fsp1/fsp_support.h>
+
+static const struct gpio_family gpio_family[] = {
+	GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0,
+			 VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST),
+
+	/* end of the table */
+	GPIO_FAMILY_CONF("GPIO FAMILY TABLE END", NA, 0,
+			 VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR),
+};
+
+static const struct gpio_pad gpio_pad[] = {
+	GPIO_PAD_CONF("N37: CX_PRDY_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 29, NA, 0x4c38, NORTH),
+	GPIO_PAD_CONF("N35: CX_PRDY_B_2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 27, NA, 0x4c28, NORTH),
+	GPIO_PAD_CONF("N39: CX_PREQ_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 20, NA, 0x4858, NORTH),
+	GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 37, NA, 0x5018, NORTH),
+	GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 42, NA, 0x5040, NORTH),
+	GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 35, NA, 0x5008, NORTH),
+	GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 40, NA, 0x5030, NORTH),
+	GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 45, NA, 0x5058, NORTH),
+	GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 34, NA, 0x5000, NORTH),
+	GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 38, NA, 0x5020, NORTH),
+	GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 43, NA, 0x5048, NORTH),
+	GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 36, NA, 0x5010, NORTH),
+	GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 41, NA, 0x5038, NORTH),
+	GPIO_PAD_CONF("N50: GP_CAMERASB10", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 39, NA, 0x5028, NORTH),
+	GPIO_PAD_CONF("N55: GP_CAMERASB11", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 44, NA, 0x5050, NORTH),
+	GPIO_PAD_CONF("N00: GPIO_DFX0", NATIVE, M5, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0x4400, NORTH),
+	GPIO_PAD_CONF("N03: GPIO_DFX1", NATIVE, M5, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 3, NA, 0x4418, NORTH),
+	GPIO_PAD_CONF("N07: GPIO_DFX2", NATIVE, M5, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 2, NA, 0x4438, NORTH),
+	GPIO_PAD_CONF("N01: GPIO_DFX3", NATIVE, M5, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 1, NA, 0x4408, NORTH),
+	GPIO_PAD_CONF("N05: GPIO_DFX4", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 5, NA, 0x4428, NORTH),
+	GPIO_PAD_CONF("N04: GPIO_DFX5", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 4, NA, 0x4420, NORTH),
+	GPIO_PAD_CONF("N08: GPIO_DFX6", NATIVE, M8, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 8, NA, 0x4440, NORTH),
+	GPIO_PAD_CONF("N02: GPIO_DFX7", GPIO, M1, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 2, NA, 0x4410, NORTH),
+	GPIO_PAD_CONF("N15: GPIO_SUS0", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 9 , NA, 0x4800, NORTH),
+	GPIO_PAD_CONF("N19: GPIO_SUS1", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 13, NA, 0x4820, NORTH),
+	GPIO_PAD_CONF("N24: GPIO_SUS2", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 18, NA, 0x4848, NORTH),
+	GPIO_PAD_CONF("N17: GPIO_SUS3", NATIVE, M6, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 11, NA, 0x4810, NORTH),
+	GPIO_PAD_CONF("N22: GPIO_SUS4", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 16, NA, 0x4838, NORTH),
+	GPIO_PAD_CONF("N20: GPIO_SUS5", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 14, NA, 0x4828, NORTH),
+	GPIO_PAD_CONF("N25: GPIO_SUS6", GPIO, M1, GPI, NA, NA,
+		      TRIG_EDGE_LOW, L9, NA, NA, NA, NON_MASKABLE,
+		      EN_EDGE_RX_DATA, NO_INVERSION,
+		      NA, 19, SCI, 0x4850, NORTH),
+	GPIO_PAD_CONF("N18: GPIO_SUS7", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 12, SMI, 0x4818, NORTH),
+	GPIO_PAD_CONF("N71: HV_DDI0_DDC_SCL", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 57, NA, 0x5458, NORTH),
+	GPIO_PAD_CONF("N66: HV_DDI0_DDC_SDA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 52, NA, 0x5430, NORTH),
+	GPIO_PAD_CONF("N61: HV_DDI0_HPD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 47, NA, 0x5408, NORTH),
+	GPIO_PAD_CONF("N64: HV_DDI1_HPD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 50, NA, 0x5420, NORTH),
+	GPIO_PAD_CONF("N67: HV_DDI2_DDC_SCL", NATIVE, M3, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 53, NA, 0x5438, NORTH),
+	GPIO_PAD_CONF("N62: HV_DDI2_DDC_SDA", NATIVE, M3, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 48, NA, 0x5410, NORTH),
+	GPIO_PAD_CONF("N68: HV_DDI2_HPD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 54, NA, 0x5440, NORTH),
+	GPIO_PAD_CONF("N65: PANEL0_BKLTCTL", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 51, NA, 0x5428, NORTH),
+	GPIO_PAD_CONF("N60: PANEL0_BKLTEN", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 46, NA, 0x5400, NORTH),
+	GPIO_PAD_CONF("N72: PANEL0_VDDEN", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 58, NA, 0x5460, NORTH),
+	GPIO_PAD_CONF("N63: PANEL1_BKLTCTL", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 49, NA, 0x5418, NORTH),
+	GPIO_PAD_CONF("N70: PANEL1_BKLTEN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 56, NA, 0x5450, NORTH),
+	GPIO_PAD_CONF("N69: PANEL1_VDDEN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 55, NA, 0x5448, NORTH),
+	GPIO_PAD_CONF("N32: PROCHOT_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 24, NA, 0x4c10, NORTH),
+	GPIO_PAD_CONF("N16: SEC_GPIO_SUS10", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 10, NA, 0x4808, NORTH),
+	GPIO_PAD_CONF("N21: SEC_GPIO_SUS11", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 15, NA, 0x4830, NORTH),
+	GPIO_PAD_CONF("N23: SEC_GPIO_SUS8", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 17, NA, 0x4840, NORTH),
+	GPIO_PAD_CONF("N27: SEC_GPIO_SUS9", GPIO, M1, GPI, LOW, NA,
+		      TRIG_LEVEL, L15, NA, NA, NA, NON_MASKABLE,
+		      EN_RX_DATA, INV_RX_DATA,
+		      NA, 21, SCI, 0x4860, NORTH),
+	GPIO_PAD_CONF("N31: TCK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 23, NA, 0x4c08, NORTH),
+	GPIO_PAD_CONF("N41: TDI", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 33, NA, 0x4c58, NORTH),
+	GPIO_PAD_CONF("N39: TDO", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 31, NA, 0x4c48, NORTH),
+	GPIO_PAD_CONF("N36: TDO_2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 28, NA, 0x4c30, NORTH),
+	GPIO_PAD_CONF("N34: TMS", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 26, NA, 0x4c20, NORTH),
+	GPIO_PAD_CONF("N30: TRST_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 22, NA, 0x4c00, NORTH),
+
+	GPIO_PAD_CONF("E21: MF_ISH_GPIO_0", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 18, NA, 0x4830, EAST),
+	GPIO_PAD_CONF("E18: MF_ISH_GPIO_1", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 15, NA, 0x4818, EAST),
+	GPIO_PAD_CONF("E24: MF_ISH_GPIO_2", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 21, NA, 0x4848, EAST),
+	GPIO_PAD_CONF("E15: MF_ISH_GPIO_3", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 12, NA, 0x4800, EAST),
+	GPIO_PAD_CONF("E22: MF_ISH_GPIO_4", GPIO, M1, GPI, NA, NA,
+		      NA, L0, NA, NA, NA, NON_MASKABLE, NA, NO_INVERSION,
+		      NA, 19, NA, 0x4838, EAST),
+	GPIO_PAD_CONF("E19: MF_ISH_GPIO_5", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 16, NA, 0x4820, EAST),
+	GPIO_PAD_CONF("E25: MF_ISH_GPIO_6", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 22, NA, 0x4850, EAST),
+	GPIO_PAD_CONF("E16: MF_ISH_GPIO_7", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 13, NA, 0x4808, EAST),
+	GPIO_PAD_CONF("E23: MF_ISH_GPIO_8", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 20, NA, 0x4840, EAST),
+	GPIO_PAD_CONF("E20: MF_ISH_GPIO_9", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 17, NA, 0x4828, EAST),
+	GPIO_PAD_CONF("E26: MF_ISH_I2C1_SDA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 23, NA, 0x4858, EAST),
+	GPIO_PAD_CONF("E17: MF_ISH_I2C1_SCL", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 14, NA, 0x4810, EAST),
+	GPIO_PAD_CONF("E04: PMU_AC_PRESENT", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 4, NA, 0x4420, EAST),
+	GPIO_PAD_CONF("E01: PMU_BATLOW_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 1, NA, 0x4408, EAST),
+	GPIO_PAD_CONF("E05: PMU_PLTRST_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 5, NA, 0x4428, EAST),
+	GPIO_PAD_CONF("E07: PMU_SLP_LAN_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 7, NA, 0x4438, EAST),
+	GPIO_PAD_CONF("E03: PMU_SLP_S0IX_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 3, NA, 0x4418, EAST),
+	GPIO_PAD_CONF("E00: PMU_SLP_S3_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0x4400, EAST),
+	GPIO_PAD_CONF("E09: PMU_SLP_S4_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 9, NA, 0x4448, EAST),
+	GPIO_PAD_CONF("E06: PMU_SUSCLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 6, NA, 0x4430, EAST),
+	GPIO_PAD_CONF("E10: PMU_WAKE_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 10, NA, 0x4450, EAST),
+	GPIO_PAD_CONF("E11: PMU_WAKE_LAN_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 11, NA, 0x4458, EAST),
+	GPIO_PAD_CONF("E02: SUS_STAT_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 2, NA, 0x4410, EAST),
+
+	GPIO_PAD_CONF("SE16: SDMMC1_CLK", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 9, NA, 0x4808, SOUTHEAST),
+	GPIO_PAD_CONF("SE23: SDMMC1_CMD", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 16, NA, 0x4840, SOUTHEAST),
+	GPIO_PAD_CONF("SE17: SDMMC1_D0", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 10, NA, 0x4810, SOUTHEAST),
+	GPIO_PAD_CONF("SE24: SDMMC1_D1", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 17, NA, 0x4848, SOUTHEAST),
+	GPIO_PAD_CONF("SE20: SDMMC1_D2", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 13, NA, 0x4828, SOUTHEAST),
+	GPIO_PAD_CONF("SE26: SDMMC1_D3_CD_B", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 19, NA, 0x4858, SOUTHEAST),
+	GPIO_PAD_CONF("SE67: MMC1_D4_SD_WE", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 41, NA, 0x5438, SOUTHEAST),
+	GPIO_PAD_CONF("SE65: MMC1_D5", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 39, NA, 0x5428, SOUTHEAST),
+	GPIO_PAD_CONF("SE63: MMC1_D6", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 37, NA, 0x5418, SOUTHEAST),
+	GPIO_PAD_CONF("SE68: MMC1_D7", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 42, NA, 0x5440, SOUTHEAST),
+	GPIO_PAD_CONF("SE69: MMC1_RCLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 43, NA, 0x5448, SOUTHEAST),
+	GPIO_PAD_CONF("SE77: GPIO_ALERT", GPIO, M1, GPI, NA, NA,
+		      TRIG_LEVEL, L2, NA, NA, NA, NON_MASKABLE,
+		      EN_RX_DATA, INV_RX_DATA,
+		      NA, 46, NA, 0x5810, SOUTHEAST),
+	GPIO_PAD_CONF("SE79: ILB_SERIRQ", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 48, NA, 0x5820, SOUTHEAST),
+	GPIO_PAD_CONF("SE51: MF_LPC_CLKOUT0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 32, NA, 0x5030, SOUTHEAST),
+	GPIO_PAD_CONF("SE49: MF_LPC_CLKOUT1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 30, NA, 0x5020, SOUTHEAST),
+	GPIO_PAD_CONF("SE47: MF_LPC_AD0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 28, NA, 0x5010, SOUTHEAST),
+	GPIO_PAD_CONF("SE52: MF_LPC_AD1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 33, NA, 0x5038, SOUTHEAST),
+	GPIO_PAD_CONF("SE45: MF_LPC_AD2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 26, NA, 0x5000, SOUTHEAST),
+	GPIO_PAD_CONF("SE50: MF_LPC_AD3", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 31, NA, 0x5028, SOUTHEAST),
+	GPIO_PAD_CONF("SE46: LPC_CLKRUNB", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 27, NA, 0x5008, SOUTHEAST),
+	GPIO_PAD_CONF("SE48: LPC_FRAMEB", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 29, NA, 0x5018, SOUTHEAST),
+	GPIO_PAD_CONF("SE00: MF_PLT_CLK0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0x4400, SOUTHEAST),
+	GPIO_PAD_CONF("SE02: MF_PLT_CLK1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 1, NA, 0x4410, SOUTHEAST),
+	GPIO_PAD_CONF("SE07: MF_PLT_CLK2", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 7, NA, 0x4438, SOUTHEAST),
+	GPIO_PAD_CONF("SE04: MF_PLT_CLK3", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 4, NA, 0x4420, SOUTHEAST),
+	GPIO_PAD_CONF("SE03: MF_PLT_CLK4", GPIO, M1, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 3, NA, 0x4418, SOUTHEAST),
+	GPIO_PAD_CONF("SE06: MF_PLT_CLK5", GPIO, M3, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 6, NA, 0x4430, SOUTHEAST),
+	GPIO_PAD_CONF("SE83: SUSPWRDNACK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 52, NA, 0x5840, SOUTHEAST),
+	GPIO_PAD_CONF("SE05: PWM0", GPIO, M1, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 5, NA, 0x4428, SOUTHEAST),
+	GPIO_PAD_CONF("SE01: PWM1", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 1, NA, 0x4408, SOUTHEAST),
+	GPIO_PAD_CONF("SE85: SDMMC3_1P8_EN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 54, NA, 0x5850, SOUTHEAST),
+	GPIO_PAD_CONF("SE81: SDMMC3_CD_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 50, NA, 0x5830, SOUTHEAST),
+	GPIO_PAD_CONF("SE31: SDMMC3_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 21, NA, 0x4c08, SOUTHEAST),
+	GPIO_PAD_CONF("SE34: SDMMC3_CMD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 24, NA, 0x4c20, SOUTHEAST),
+	GPIO_PAD_CONF("SE35: SDMMC3_D0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 25, NA, 0x4c28, SOUTHEAST),
+	GPIO_PAD_CONF("SE30: SDMMC3_D1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 20, NA, 0x4c00, SOUTHEAST),
+	GPIO_PAD_CONF("SE33: SDMMC3_D2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 23, NA, 0x4c18, SOUTHEAST),
+	GPIO_PAD_CONF("SE32: SDMMC3_D3", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 22, NA, 0x4c10, SOUTHEAST),
+	GPIO_PAD_CONF("SE78: SDMMC3_PWR_EN_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 47, NA, 0x5818, SOUTHEAST),
+	GPIO_PAD_CONF("SE19: SDMMC2_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 12, NA, 0x4820, SOUTHEAST),
+	GPIO_PAD_CONF("SE22: SDMMC2_CMD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 15, NA, 0x4838, SOUTHEAST),
+	GPIO_PAD_CONF("SE25: SDMMC2_D0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 18, NA, 0x4850, SOUTHEAST),
+	GPIO_PAD_CONF("SE18: SDMMC2_D1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 11, NA, 0x4818, SOUTHEAST),
+	GPIO_PAD_CONF("SE21: SDMMC2_D2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 14, NA, 0x4830, SOUTHEAST),
+	GPIO_PAD_CONF("SE15: SDMMC2_D3_CD_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 8, NA, 0x4800, SOUTHEAST),
+	GPIO_PAD_CONF("SE62: SPI1_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 36, NA, 0x5410, SOUTHEAST),
+	GPIO_PAD_CONF("SE61: SPI1_CS0_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 35, NA, 0x5408, SOUTHEAST),
+	GPIO_PAD_CONF("SE66: SPI1_CS1_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 40, NA, 0x5430, SOUTHEAST),
+	GPIO_PAD_CONF("SE60: SPI1_MISO", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 34, NA, 0x5400, SOUTHEAST),
+	GPIO_PAD_CONF("SE64: SPI1_MOSI", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 38, NA, 0x5420, SOUTHEAST),
+	GPIO_PAD_CONF("SE80: USB_OC0_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 49, NA, 0x5828, SOUTHEAST),
+	GPIO_PAD_CONF("SE75: USB_OC1_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 44, NA, 0x5800, SOUTHEAST),
+	GPIO_PAD_CONF("SW02: FST_SPI_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 2, NA, 0x4410, SOUTHWEST),
+	GPIO_PAD_CONF("SW06: FST_SPI_CS0_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 6, NA, 0x4430, SOUTHWEST),
+	GPIO_PAD_CONF("SW04: FST_SPI_CS1_B", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 4, NA, 0x4420, SOUTHWEST),
+	GPIO_PAD_CONF("SW07: FST_SPI_CS2_B", GPIO, M1, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 7, NA, 0x4438, SOUTHWEST),
+	GPIO_PAD_CONF("SW01: FST_SPI_D0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 1, NA, 0x4408, SOUTHWEST),
+	GPIO_PAD_CONF("SW05: FST_SPI_D1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 5, NA, 0x4428, SOUTHWEST),
+	GPIO_PAD_CONF("SW00: FST_SPI_D2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0x4400, SOUTHWEST),
+	GPIO_PAD_CONF("SW03: FST_SPI_D3", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 3, NA, 0x4418, SOUTHWEST),
+	GPIO_PAD_CONF("SW30: MF_HDA_CLK", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 16, NA, 0x4c00, SOUTHWEST),
+	GPIO_PAD_CONF("SW37: MF_HDA_DOCKENB", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 23, NA, 0x4c38, SOUTHWEST),
+	GPIO_PAD_CONF("SW34: MF_HDA_DOCKRSTB", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 20, NA, 0x4c20, SOUTHWEST),
+	GPIO_PAD_CONF("SW31: MF_HDA_RSTB", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 17, NA, 0x4c08, SOUTHWEST),
+	GPIO_PAD_CONF("SW32: MF_HDA_SDI0", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 18, NA, 0x4c10, SOUTHWEST),
+	GPIO_PAD_CONF("SW36: MF_HDA_SDI1", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 22, NA, 0x4c30, SOUTHWEST),
+	GPIO_PAD_CONF("SW33: MF_HDA_SDO", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 19, NA, 0x4c18, SOUTHWEST),
+	GPIO_PAD_CONF("SW35: MF_HDA_SYNC", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 21, NA, 0x4c28, SOUTHWEST),
+	GPIO_PAD_CONF("SW18: UART1_CTS_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 11, NA, 0x4818, SOUTHWEST),
+	GPIO_PAD_CONF("SW15: UART1_RTS_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 8, NA, 0x4800, SOUTHWEST),
+	GPIO_PAD_CONF("SW16: UART1_RXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 9, NA, 0x4808, SOUTHWEST),
+	GPIO_PAD_CONF("SW20: UART1_TXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 13, NA, 0x4828, SOUTHWEST),
+	GPIO_PAD_CONF("SW22: UART2_CTS_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 15, NA, 0x4838, SOUTHWEST),
+	GPIO_PAD_CONF("SW19: UART2_RTS_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 12, NA, 0x4820, SOUTHWEST),
+	GPIO_PAD_CONF("SW17: UART2_RXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 10, NA, 0x4810, SOUTHWEST),
+	GPIO_PAD_CONF("SW21: UART2_TXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 14, NA, 0x4830, SOUTHWEST),
+	GPIO_PAD_CONF("SW50: I2C4_SCL", NATIVE, M3, NA, NA, NA,
+		      NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 29, NA, 0x5028, SOUTHWEST),
+	GPIO_PAD_CONF("SW46: I2C4_SDA", NATIVE, M3, NA, NA, NA,
+		      NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 25, NA, 0x5008, SOUTHWEST),
+	GPIO_PAD_CONF("SW49: I2C_NFC_SDA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 28, NA, 0x5020, SOUTHWEST),
+	GPIO_PAD_CONF("SW52: I2C_NFC_SCL", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 31, NA, 0x5038, SOUTHWEST),
+	GPIO_PAD_CONF("SW77: GP_SSP_2_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 50, NA, 0x5c10, SOUTHWEST),
+	GPIO_PAD_CONF("SW81: GP_SSP_2_FS", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 54, NA, 0x5c30, SOUTHWEST),
+	GPIO_PAD_CONF("SW79: GP_SSP_2_RXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 52, NA, 0x5c20, SOUTHWEST),
+	GPIO_PAD_CONF("SW82: GP_SSP_2_TXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 55, NA, 0x5C38, SOUTHWEST),
+	GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 48, NA, 0x5c00, SOUTHWEST),
+	GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 49, NA, 0x5c08, SOUTHWEST),
+	GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 51, NA, 0x5c18, SOUTHWEST),
+	GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 53, NA, 0x5c28, SOUTHWEST),
+	GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 40, NA, 0x5800, SOUTHWEST),
+	GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 41, NA, 0x5808, SOUTHWEST),
+	GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
+		      NA, 43, NA, 0x5818, SOUTHWEST),
+	GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 45, NA, 0x5828, SOUTHWEST),
+	GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
+		      NA, 42, NA, 0x5810, SOUTHWEST),
+	GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
+		      NA, NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 44, NA, 0x5820, SOUTHWEST),
+	GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 46, NA, 0x5830, SOUTHWEST),
+	GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 47, NA, 0x5838, SOUTHWEST),
+	GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 48, NA, 0x5c00, SOUTHWEST),
+	GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 49, NA, 0x5c08, SOUTHWEST),
+	GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 51, NA, 0x5c18, SOUTHWEST),
+	GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 53, NA, 0x5c28, SOUTHWEST),
+	GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA,
+		      NA, 40, NA, 0x5800, SOUTHWEST),
+	GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA,
+		      NA, 41, NA, 0x5808, SOUTHWEST),
+	GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, ENABLE, NA, NA, NA, NA,
+		      NA, 43, NA, 0x5818, SOUTHWEST),
+	GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 45, NA, 0x5828, SOUTHWEST),
+	GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, ENABLE, NA, NA, NA, NA,
+		      NA, 42, NA, 0x5810, SOUTHWEST),
+	GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
+		      NA, NA, NA, P_20K_H, NA, NA, NA, NA, NA,
+		      NA, 44, NA, 0x5820, SOUTHWEST),
+	GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NA,
+		      NA, 46, NA, 0x5830, SOUTHWEST),
+	GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NA,
+		      NA, 47, NA, 0x5838, SOUTHWEST),
+
+	/* end of the table */
+	GPIO_PAD_CONF("GPIO PAD TABLE END", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0, TERMINATOR),
+};
+
+void update_fsp_gpio_configs(const struct gpio_family **family,
+			     const struct gpio_pad **pad)
+{
+	*family = gpio_family;
+	*pad = gpio_pad;
+}
diff --git a/roms/u-boot/board/intel/cougarcanyon2/Kconfig b/roms/u-boot/board/intel/cougarcanyon2/Kconfig
new file mode 100644
index 000000000..ed764485a
--- /dev/null
+++ b/roms/u-boot/board/intel/cougarcanyon2/Kconfig
@@ -0,0 +1,27 @@
+if TARGET_COUGARCANYON2
+
+config SYS_BOARD
+	default "cougarcanyon2"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "ivybridge"
+
+config SYS_CONFIG_NAME
+	default "cougarcanyon2"
+
+config SYS_TEXT_BASE
+	default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select NORTHBRIDGE_INTEL_IVYBRIDGE
+	select HAVE_FSP
+	select BOARD_ROMSIZE_KB_2048
+	select BOARD_EARLY_INIT_F
+	select SPI_FLASH_WINBOND
+
+endif
diff --git a/roms/u-boot/board/intel/cougarcanyon2/MAINTAINERS b/roms/u-boot/board/intel/cougarcanyon2/MAINTAINERS
new file mode 100644
index 000000000..a486739b5
--- /dev/null
+++ b/roms/u-boot/board/intel/cougarcanyon2/MAINTAINERS
@@ -0,0 +1,6 @@
+INTEL COUGAR CANYON 2 BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/intel/cougarcanyon2/
+F:	include/configs/cougarcanyon2.h
+F:	configs/cougarcanyon2_defconfig
diff --git a/roms/u-boot/board/intel/cougarcanyon2/Makefile b/roms/u-boot/board/intel/cougarcanyon2/Makefile
new file mode 100644
index 000000000..13b19ae65
--- /dev/null
+++ b/roms/u-boot/board/intel/cougarcanyon2/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y	+= cougarcanyon2.o
diff --git a/roms/u-boot/board/intel/cougarcanyon2/cougarcanyon2.c b/roms/u-boot/board/intel/cougarcanyon2/cougarcanyon2.c
new file mode 100644
index 000000000..ce11eae59
--- /dev/null
+++ b/roms/u-boot/board/intel/cougarcanyon2/cougarcanyon2.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <init.h>
+#include <pci.h>
+#include <smsc_sio1007.h>
+#include <asm/ibmpc.h>
+#include <asm/lpc_common.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+#define SIO1007_RUNTIME_IOPORT	0x180
+
+int board_early_init_f(void)
+{
+	struct udevice *pch;
+	int ret;
+
+	ret = uclass_first_device(UCLASS_PCH, &pch);
+	if (ret)
+		return ret;
+	if (!pch)
+		return -ENODEV;
+
+	/* Initialize LPC interface to turn on superio chipset decode range */
+	dm_pci_write_config16(pch, LPC_IO_DEC, COMA_DEC_RANGE | COMB_DEC_RANGE);
+	dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | COMA_LPC_EN);
+	dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B |
+			      (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN);
+	dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B |
+			      SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN);
+
+	/* Enable legacy serial port at 0x3f8 */
+	sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ);
+
+	/* Enable SIO1007 runtime I/O port at 0x180 */
+	sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT);
+
+	/*
+	 * On Cougar Canyon 2 board, the RS232 transiver connected to serial
+	 * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007.
+	 * Set the pin value to 1 to enable the RS232 transiver.
+	 */
+	sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT,
+			    GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL);
+	sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/intel/crownbay/Kconfig b/roms/u-boot/board/intel/crownbay/Kconfig
new file mode 100644
index 000000000..1eed227c7
--- /dev/null
+++ b/roms/u-boot/board/intel/crownbay/Kconfig
@@ -0,0 +1,26 @@
+if TARGET_CROWNBAY
+
+config SYS_BOARD
+	default "crownbay"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "queensbay"
+
+config SYS_CONFIG_NAME
+	default "crownbay"
+
+config SYS_TEXT_BASE
+	default 0xfff00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_QUEENSBAY
+	select BOARD_ROMSIZE_KB_1024
+	select BOARD_EARLY_INIT_F
+	select SPI_FLASH_SST
+
+endif
diff --git a/roms/u-boot/board/intel/crownbay/MAINTAINERS b/roms/u-boot/board/intel/crownbay/MAINTAINERS
new file mode 100644
index 000000000..1eb68693d
--- /dev/null
+++ b/roms/u-boot/board/intel/crownbay/MAINTAINERS
@@ -0,0 +1,6 @@
+INTEL CROWNBAY BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/intel/crownbay/
+F:	include/configs/crownbay.h
+F:	configs/crownbay_defconfig
diff --git a/roms/u-boot/board/intel/crownbay/Makefile b/roms/u-boot/board/intel/crownbay/Makefile
new file mode 100644
index 000000000..6abd3eeb5
--- /dev/null
+++ b/roms/u-boot/board/intel/crownbay/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y	+= crownbay.o
diff --git a/roms/u-boot/board/intel/crownbay/crownbay.c b/roms/u-boot/board/intel/crownbay/crownbay.c
new file mode 100644
index 000000000..55095deea
--- /dev/null
+++ b/roms/u-boot/board/intel/crownbay/crownbay.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/ibmpc.h>
+#include <asm/pnp_def.h>
+#include <smsc_lpc47m.h>
+
+int board_early_init_f(void)
+{
+	lpc47m_enable_serial(PNP_DEV(LPC47M_IO_PORT, LPC47M_SP1),
+			     UART0_BASE, UART0_IRQ);
+	lpc47m_enable_kbc(PNP_DEV(LPC47M_IO_PORT, LPC47M_KBC),
+			  KBD_IRQ, MSE_IRQ);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/intel/edison/.gitignore b/roms/u-boot/board/intel/edison/.gitignore
new file mode 100644
index 000000000..6eb8a5481
--- /dev/null
+++ b/roms/u-boot/board/intel/edison/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/roms/u-boot/board/intel/edison/Kconfig b/roms/u-boot/board/intel/edison/Kconfig
new file mode 100644
index 000000000..23b2af482
--- /dev/null
+++ b/roms/u-boot/board/intel/edison/Kconfig
@@ -0,0 +1,36 @@
+if TARGET_EDISON
+
+config SYS_BOARD
+	default "edison"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "tangier"
+
+config SYS_CONFIG_NAME
+	default "edison"
+
+config SYS_MALLOC_LEN
+	default 0x08000000
+
+config SYS_TEXT_BASE
+	default 0x01101000
+
+config ROM_TABLE_ADDR
+	default 0x0e4500
+
+config ROM_TABLE_SIZE
+	default 0x007b00
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_LOAD_FROM_32_BIT
+	select INTEL_MID
+	select INTEL_TANGIER
+	select BOARD_LATE_INIT
+	select MD5
+	imply BINMAN
+
+endif
diff --git a/roms/u-boot/board/intel/edison/MAINTAINERS b/roms/u-boot/board/intel/edison/MAINTAINERS
new file mode 100644
index 000000000..4bc4a00c8
--- /dev/null
+++ b/roms/u-boot/board/intel/edison/MAINTAINERS
@@ -0,0 +1,6 @@
+Intel Edison Board
+M:	Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+S:	Maintained
+F:	board/intel/edison
+F:	include/configs/edison.h
+F:	configs/edison_defconfig
diff --git a/roms/u-boot/board/intel/edison/Makefile b/roms/u-boot/board/intel/edison/Makefile
new file mode 100644
index 000000000..1eaf7ca7f
--- /dev/null
+++ b/roms/u-boot/board/intel/edison/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= edison.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/roms/u-boot/board/intel/edison/config.mk b/roms/u-boot/board/intel/edison/config.mk
new file mode 100644
index 000000000..8c6087e29
--- /dev/null
+++ b/roms/u-boot/board/intel/edison/config.mk
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+#
+# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+# Copyright (c) 2017 Intel Corporation
+#
+
+# Add 4096 bytes of zeroes to u-boot.bin
+quiet_cmd_mkalign_eds = EDSALGN $@
+cmd_mkalign_eds =							\
+	dd if=$^ of=$@ bs=4k seek=1 2>/dev/null &&			\
+	mv $@ $^
+
+INPUTS-y += u-boot-align.bin
+u-boot-align.bin: u-boot.bin
+	$(call if_changed,mkalign_eds)
+
+HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
diff --git a/roms/u-boot/board/intel/edison/dsdt.asl b/roms/u-boot/board/intel/edison/dsdt.asl
new file mode 100644
index 000000000..3b75c4e76
--- /dev/null
+++ b/roms/u-boot/board/intel/edison/dsdt.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * Partially based on dsdt.asl for other x86 boards
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+}
diff --git a/roms/u-boot/board/intel/edison/edison-environment.txt b/roms/u-boot/board/intel/edison/edison-environment.txt
new file mode 100644
index 000000000..afe009204
--- /dev/null
+++ b/roms/u-boot/board/intel/edison/edison-environment.txt
@@ -0,0 +1,48 @@
+partitions=uuid_disk=${uuid_disk};name=u-boot0,start=1MiB,size=2MiB,uuid=${uuid_uboot0};name=u-boot-env0,size=1MiB,uuid=${uuid_uboot_env0};name=u-boot1,size=2MiB,uuid=${uuid_uboot1};name=u-boot-env1,size=1MiB,uuid=${uuid_uboot_env1};name=factory,size=1MiB,uuid=${uuid_factory};name=panic,size=24MiB,uuid=${uuid_panic};name=boot,size=32MiB,uuid=${uuid_boot};name=rootfs,size=1536MiB,uuid=${uuid_rootfs};name=update,size=768MiB,uuid=${uuid_update};name=home,size=-,uuid=${uuid_home};
+do_dfu_alt_info_mmc=setenv dfu_alt_info "ifwi${hardware_id} raw 0 8192 mmcpart 1;ifwib${hardware_id} raw 0 8192 mmcpart 2;u-boot0 part 0 1;u-boot-env0 part 0 2;u-boot1 part 0 3;u-boot-env1 part 0 4;boot part 0 7;rootfs part 0 8;update part 0 9;home part 0 10;vmlinuz fat 0 7;initrd fat 0 7"
+dfu_alt_info_ram=kernel ram ${loadaddr} 0x800000
+do_dfu_alt_info_ifwi=setenv dfu_alt_info "ifwi${hardware_id} raw 0 8192 mmcpart 1;ifwib${hardware_id} raw 0 8192 mmcpart 2"
+dfu_alt_info_reset=reset ram 0x0 0x0
+bootargs_console=console=ttyMFD2 earlyprintk=ttyMFD2,keep
+bootargs_debug=loglevel=4
+do_bootargs_rootfs=setenv bootargs_rootfs rootwait root=PARTUUID=${uuid_rootfs} rootfstype=ext4
+first_install_retry=0
+first_install_max_retries=3
+ota_update_retry=0
+ota_update_max_retries=3
+audio_codec_name=audio_codec="dummy"
+do_audio_support=setenv audio_support platform_mrfld_audio.${audio_codec_name}
+do_compute_target=if itest.b ${first_install_retry} -gt ${first_install_max_retries} || itest.b ${ota_update_retry} -gt ${ota_update_max_retries}; then echo "Switch to Rescue target"; setenv bootargs_target rescue; saveenv; fi
+mmc-bootargs=run do_bootargs_rootfs; run do_audio_support; setenv bootargs ${bootargs_rootfs} ${bootargs_console} ${bootargs_debug} g_multi.ethernet_config=${bootargs_ethconfig} systemd.unit=${bootargs_target}.target hardware_id=${hardware_id} g_multi.iSerialNumber=${serial#} g_multi.dev_addr=${usb0addr} ${audio_support}
+loadaddr=0x100000
+load_kernel=fatload mmc 0:7 ${loadaddr} vmlinuz
+do_partition_done=0
+do_partition=if itest.b ${do_partition_done} -eq 1; then echo "Partitioning already done..."; else run do_force_partition ; fi
+do_force_partition=echo "Partitioning using GPT"; gpt write mmc 0 ${partitions} ; mmc rescan; setenv do_partition_done 1 ; saveenv
+do_flash_ifwi=run do_dfu_alt_info_ifwi ; dfu 0 mmc 0 $dfu_to_sec
+do_flash_os=if itest.b ${do_flash_os_done} -eq 1 ; then echo "Flashing already done..." ; else run do_force_flash_os; fi
+do_force_flash_os=run do_dfu_alt_info_mmc ; sleep 1 ; setenv do_flash_os_done 1 ; saveenv ; dfu 0 mmc 0 $dfu_to_sec
+do_flashall=run do_partition;run do_flash_ifwi;run do_flash_os
+do_dnx=setenv dfu_alt_info ${dfu_alt_info_ram};dfu 0 ram 0 ram;run bootcmd
+init_dfu=run do_dfu_alt_info_mmc ; saveenv
+bootcmd=echo "Target:${target_name}"; run do_partition; run do_handle_bootargs_mode;
+do_handle_bootargs_mode=run do_preprocess_bootargs_mode; if itest.s $bootargs_mode == "ota" ; then run do_ota; fi; if itest.s $bootargs_mode == "boot" ; then run do_boot; fi; if itest.s $bootargs_mode == "flash"; then run do_flash; fi; run do_fallback; exit;
+do_preprocess_bootargs_mode=if env exists bootargs_mode ; then ; else setenv bootargs_mode "boot" ;fi;
+do_fallback=echo "Unknown boot mode: $bootargs_mode"; env delete -f bootargs_mode; saveenv; echo "Resetting to default boot mode and reboot..."; reset;
+do_boot=run boot_target_cmd;
+do_flash=run do_force_flash_os;
+ota_done=0
+ota_script_addr=0x100000
+do_ota_init=setenv ota_status 1 ; env delete -f bootargs_mode
+do_load_ota_scr=if fatload mmc 0:9 $ota_script_addr ota_update.scr ; then setenv ota_status 0 ; else setenv ota_status 1 ; fi
+do_source_ota_scr=if test $ota_status -eq 0 ; then if source $ota_script_addr ; then setenv ota_status 0 ; else setenv ota_status 2 ; fi ; fi
+do_ota_clean=saveenv ; reset
+do_ota=run do_ota_init ; run do_load_ota_scr ; run do_source_ota_scr ; run do_ota_clean
+target_name=blank
+bootdelay=1
+do_flash_os_done=1
+bootargs_target=multi-user
+bootargs_ethconfig=cdc
+dfu_to_sec=3
+do_probe_dfu=run do_dfu_alt_info_mmc ; dfu 0 mmc 0 $dfu_to_sec
+boot_target_cmd=run do_flash_os;run do_probe_dfu;run do_compute_target;run mmc-bootargs;run load_kernel;zboot ${loadaddr}
diff --git a/roms/u-boot/board/intel/edison/edison-osip.dat b/roms/u-boot/board/intel/edison/edison-osip.dat
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/roms/u-boot/board/intel/edison/edison-osip.dat
diff --git a/roms/u-boot/board/intel/edison/edison.c b/roms/u-boot/board/intel/edison/edison.c
new file mode 100644
index 000000000..11e7f74e4
--- /dev/null
+++ b/roms/u-boot/board/intel/edison/edison.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Intel Corporation
+ */
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <mmc.h>
+#include <u-boot/md5.h>
+
+#include <asm/cache.h>
+#include <asm/pmu.h>
+#include <asm/scu.h>
+#include <asm/u-boot-x86.h>
+
+/* List of Intel Tangier LSSs */
+#define PMU_LSS_TANGIER_SDIO0_01	1
+
+int board_early_init_r(void)
+{
+	pmu_turn_power(PMU_LSS_TANGIER_SDIO0_01, true);
+	return 0;
+}
+
+static void assign_serial(void)
+{
+	struct mmc *mmc = find_mmc_device(0);
+	unsigned char ssn[16];
+	char usb0addr[18];
+	char serial[33];
+	int i;
+
+	if (!mmc)
+		return;
+
+	md5((unsigned char *)mmc->cid, sizeof(mmc->cid), ssn);
+
+	snprintf(usb0addr, sizeof(usb0addr), "02:00:86:%02x:%02x:%02x",
+		 ssn[13], ssn[14], ssn[15]);
+	env_set("usb0addr", usb0addr);
+
+	for (i = 0; i < 16; i++)
+		snprintf(&serial[2 * i], 3, "%02x", ssn[i]);
+	env_set("serial#", serial);
+
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+	env_save();
+#endif
+}
+
+static void assign_hardware_id(void)
+{
+	struct ipc_ifwi_version v;
+	char hardware_id[4];
+	int ret;
+
+	ret = scu_ipc_command(IPCMSG_GET_FW_REVISION, 1, NULL, 0, (u32 *)&v, 4);
+	if (ret < 0)
+		printf("Can't retrieve hardware revision\n");
+
+	snprintf(hardware_id, sizeof(hardware_id), "%02X", v.hardware_id);
+	env_set("hardware_id", hardware_id);
+
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+	env_save();
+#endif
+}
+
+int board_late_init(void)
+{
+	if (!env_get("serial#"))
+		assign_serial();
+
+	if (!env_get("hardware_id"))
+		assign_hardware_id();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/intel/galileo/.gitignore b/roms/u-boot/board/intel/galileo/.gitignore
new file mode 100644
index 000000000..6eb8a5481
--- /dev/null
+++ b/roms/u-boot/board/intel/galileo/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/roms/u-boot/board/intel/galileo/Kconfig b/roms/u-boot/board/intel/galileo/Kconfig
new file mode 100644
index 000000000..fb8d94fb5
--- /dev/null
+++ b/roms/u-boot/board/intel/galileo/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_GALILEO
+
+config SYS_BOARD
+	default "galileo"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "quark"
+
+config SYS_CONFIG_NAME
+	default "galileo"
+
+config SYS_TEXT_BASE
+	default 0xfff10000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_QUARK
+	select BOARD_ROMSIZE_KB_1024
+	select SPI_FLASH_WINBOND
+
+endif
diff --git a/roms/u-boot/board/intel/galileo/MAINTAINERS b/roms/u-boot/board/intel/galileo/MAINTAINERS
new file mode 100644
index 000000000..dbbc82e8a
--- /dev/null
+++ b/roms/u-boot/board/intel/galileo/MAINTAINERS
@@ -0,0 +1,6 @@
+INTEL GALILEO BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/intel/galileo/
+F:	include/configs/galileo.h
+F:	configs/galileo_defconfig
diff --git a/roms/u-boot/board/intel/galileo/Makefile b/roms/u-boot/board/intel/galileo/Makefile
new file mode 100644
index 000000000..4130bb023
--- /dev/null
+++ b/roms/u-boot/board/intel/galileo/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y	+= galileo.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/roms/u-boot/board/intel/galileo/acpi/mainboard.asl b/roms/u-boot/board/intel/galileo/acpi/mainboard.asl
new file mode 100644
index 000000000..beb9d93ec
--- /dev/null
+++ b/roms/u-boot/board/intel/galileo/acpi/mainboard.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/roms/u-boot/board/intel/galileo/dsdt.asl b/roms/u-boot/board/intel/galileo/dsdt.asl
new file mode 100644
index 000000000..d2297ef59
--- /dev/null
+++ b/roms/u-boot/board/intel/galileo/dsdt.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/roms/u-boot/board/intel/galileo/galileo.c b/roms/u-boot/board/intel/galileo/galileo.c
new file mode 100644
index 000000000..341b627a6
--- /dev/null
+++ b/roms/u-boot/board/intel/galileo/galileo.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/device.h>
+#include <asm/arch/quark.h>
+
+/*
+ * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin.
+ *
+ * We cannot use any public GPIO APIs in <asm-generic/gpio.h> to control this
+ * pin, as these APIs will eventually call into gpio_ich6_of_to_plat()
+ * in the Intel ICH6 GPIO driver where it calls PCI configuration space access
+ * APIs which will trigger PCI enumeration process.
+ *
+ * Check <asm/arch-quark/quark.h> for more details.
+ */
+void board_assert_perst(void)
+{
+	u32 base, port, val;
+
+	/* retrieve the GPIO IO base */
+	qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
+	base = (base & 0xffff) & ~0x7f;
+
+	/* enable the pin */
+	port = base + 0x20;
+	val = inl(port);
+	val |= (1 << 0);
+	outl(val, port);
+
+	/* configure the pin as output */
+	port = base + 0x24;
+	val = inl(port);
+	val &= ~(1 << 0);
+	outl(val, port);
+
+	/* pull it down (assert) */
+	port = base + 0x28;
+	val = inl(port);
+	val &= ~(1 << 0);
+	outl(val, port);
+}
+
+void board_deassert_perst(void)
+{
+	u32 base, port, val;
+
+	/* retrieve the GPIO IO base */
+	qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
+	base = (base & 0xffff) & ~0x7f;
+
+	/* pull it up (de-assert) */
+	port = base + 0x28;
+	val = inl(port);
+	val |= (1 << 0);
+	outl(val, port);
+}
diff --git a/roms/u-boot/board/intel/minnowmax/.gitignore b/roms/u-boot/board/intel/minnowmax/.gitignore
new file mode 100644
index 000000000..6eb8a5481
--- /dev/null
+++ b/roms/u-boot/board/intel/minnowmax/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/roms/u-boot/board/intel/minnowmax/Kconfig b/roms/u-boot/board/intel/minnowmax/Kconfig
new file mode 100644
index 000000000..82a6ca904
--- /dev/null
+++ b/roms/u-boot/board/intel/minnowmax/Kconfig
@@ -0,0 +1,31 @@
+if TARGET_MINNOWMAX
+
+config SYS_BOARD
+	default "minnowmax"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "baytrail"
+
+config SYS_CONFIG_NAME
+	default "minnowmax"
+
+config SYS_TEXT_BASE
+	default 0xfff00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_STMICRO
+	# Enable Winbond so we can use Dediprog em100pro emulator which does
+	# not support N25Q064
+	select SPI_FLASH_WINBOND
+
+config PCIE_ECAM_BASE
+	default 0xe0000000
+
+endif
diff --git a/roms/u-boot/board/intel/minnowmax/MAINTAINERS b/roms/u-boot/board/intel/minnowmax/MAINTAINERS
new file mode 100644
index 000000000..d655761d5
--- /dev/null
+++ b/roms/u-boot/board/intel/minnowmax/MAINTAINERS
@@ -0,0 +1,6 @@
+CircuitCo Minnowboard Max
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/intel/minnowmax
+F:	include/configs/minnowmax.h
+F:	configs/minnowmax_defconfig
diff --git a/roms/u-boot/board/intel/minnowmax/Makefile b/roms/u-boot/board/intel/minnowmax/Makefile
new file mode 100644
index 000000000..d339b5ad0
--- /dev/null
+++ b/roms/u-boot/board/intel/minnowmax/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Google, Inc
+
+obj-y	+= minnowmax.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/roms/u-boot/board/intel/minnowmax/acpi/mainboard.asl b/roms/u-boot/board/intel/minnowmax/acpi/mainboard.asl
new file mode 100644
index 000000000..beb9d93ec
--- /dev/null
+++ b/roms/u-boot/board/intel/minnowmax/acpi/mainboard.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/roms/u-boot/board/intel/minnowmax/dsdt.asl b/roms/u-boot/board/intel/minnowmax/dsdt.asl
new file mode 100644
index 000000000..d2297ef59
--- /dev/null
+++ b/roms/u-boot/board/intel/minnowmax/dsdt.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/roms/u-boot/board/intel/minnowmax/minnowmax.c b/roms/u-boot/board/intel/minnowmax/minnowmax.c
new file mode 100644
index 000000000..b02e3f0d4
--- /dev/null
+++ b/roms/u-boot/board/intel/minnowmax/minnowmax.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015, Google, Inc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <asm/gpio.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+
+#define GPIO_BANKE_NAME		"gpioe"
+
+int misc_init_r(void)
+{
+	struct udevice *dev;
+	struct gpio_desc desc;
+	int ret;
+
+	/*
+	 * Turn on USB VBUS for the two USB ports on the board.
+	 * Each port's VBUS is controlled by a GPIO pin.
+	 */
+
+	ret = uclass_find_device_by_name(UCLASS_GPIO, GPIO_BANKE_NAME, &dev);
+	if (ret) {
+		debug("%s: GPIO %s device cannot be not found (ret=%d)\n",
+		      __func__, GPIO_BANKE_NAME, ret);
+		return ret;
+	}
+
+	ret = device_probe(dev);
+	if (ret) {
+		debug("%s: GPIO %s device probe failed (ret=%d)\n",
+		      __func__, GPIO_BANKE_NAME, ret);
+		return ret;
+	}
+
+	desc.dev = dev;
+	desc.flags = GPIOD_IS_OUT;
+
+	/* GPIO E8 controls the bottom port */
+	desc.offset = 8;
+
+	ret = dm_gpio_request(&desc, "usb_host_en0");
+	if (ret)
+		return ret;
+	dm_gpio_set_value(&desc, 1);
+
+	/* GPIO E9 controls the upper port */
+	desc.offset = 9;
+
+	ret = dm_gpio_request(&desc, "usb_host_en1");
+	if (ret)
+		return ret;
+
+	dm_gpio_set_value(&desc, 1);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/intel/slimbootloader/Kconfig b/roms/u-boot/board/intel/slimbootloader/Kconfig
new file mode 100644
index 000000000..8c7e22cc3
--- /dev/null
+++ b/roms/u-boot/board/intel/slimbootloader/Kconfig
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Intel Corporation <www.intel.com>
+
+if TARGET_SLIMBOOTLOADER
+
+config SYS_BOARD
+	default "slimbootloader"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "slimbootloader"
+
+config SYS_CONFIG_NAME
+	default "slimbootloader"
+
+config SYS_TEXT_BASE
+	default 0x00100000
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SYS_SLIMBOOTLOADER
+	select USB_STORAGE
+	select USB_KEYBOARD
+
+endif
diff --git a/roms/u-boot/board/intel/slimbootloader/MAINTAINERS b/roms/u-boot/board/intel/slimbootloader/MAINTAINERS
new file mode 100644
index 000000000..e6935517e
--- /dev/null
+++ b/roms/u-boot/board/intel/slimbootloader/MAINTAINERS
@@ -0,0 +1,6 @@
+Intel Slim Bootloader Payload
+M:	Aiden Park <aiden.park@intel.com>
+S:	Maintained
+F:	board/intel/slimbootloader
+F:	include/configs/slimbootloader.h
+F:	configs/slimbootloader_defconfig
diff --git a/roms/u-boot/board/intel/slimbootloader/Makefile b/roms/u-boot/board/intel/slimbootloader/Makefile
new file mode 100644
index 000000000..50330cc6e
--- /dev/null
+++ b/roms/u-boot/board/intel/slimbootloader/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Intel Corporation <www.intel.com>
+
+obj-y	+= slimbootloader.o
diff --git a/roms/u-boot/board/intel/slimbootloader/slimbootloader.c b/roms/u-boot/board/intel/slimbootloader/slimbootloader.c
new file mode 100644
index 000000000..b20ddf0c6
--- /dev/null
+++ b/roms/u-boot/board/intel/slimbootloader/slimbootloader.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <init.h>
+
+int board_early_init_r(void)
+{
+	/*
+	 * Make sure PCI bus is enumerated so that peripherals on the PCI bus
+	 * can be discovered by their drivers.
+	 *
+	 * Slim Bootloader has already done PCI bus enumeration before loading
+	 * U-Boot, so U-Boot needs to preserve PCI configuration.
+	 * Therefore, '# CONFIG_PCI_PNP is not set' is included in defconfig.
+	 */
+	pci_init();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/inversepath/usbarmory/Kconfig b/roms/u-boot/board/inversepath/usbarmory/Kconfig
new file mode 100644
index 000000000..c2cd54437
--- /dev/null
+++ b/roms/u-boot/board/inversepath/usbarmory/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_USBARMORY
+
+config IMX_CONFIG
+	default "board/inversepath/usbarmory/imximage.cfg"
+
+config SYS_BOARD
+	default "usbarmory"
+
+config SYS_VENDOR
+	default "inversepath"
+
+config SYS_CONFIG_NAME
+	default "usbarmory"
+
+endif
diff --git a/roms/u-boot/board/inversepath/usbarmory/MAINTAINERS b/roms/u-boot/board/inversepath/usbarmory/MAINTAINERS
new file mode 100644
index 000000000..71a3dd40f
--- /dev/null
+++ b/roms/u-boot/board/inversepath/usbarmory/MAINTAINERS
@@ -0,0 +1,6 @@
+USBARMORY BOARD
+M:	Andrej Rosano <andrej@inversepath.com>
+S:	Maintained
+F:	board/inversepath/usbarmory/
+F:	include/configs/usbarmory.h
+F:	configs/usbarmory_defconfig
diff --git a/roms/u-boot/board/inversepath/usbarmory/Makefile b/roms/u-boot/board/inversepath/usbarmory/Makefile
new file mode 100644
index 000000000..9b8bd80ab
--- /dev/null
+++ b/roms/u-boot/board/inversepath/usbarmory/Makefile
@@ -0,0 +1,10 @@
+#
+# USB armory MkI board Makefile
+# http://inversepath.com/usbarmory
+#
+# Copyright (C) 2015, Inverse Path
+# Andrej Rosano <andrej@inversepath.com>
+#
+# SPDX-License-Identifier:|____GPL-2.0+
+
+obj-y	:= usbarmory.o
diff --git a/roms/u-boot/board/inversepath/usbarmory/imximage.cfg b/roms/u-boot/board/inversepath/usbarmory/imximage.cfg
new file mode 100644
index 000000000..d23885bed
--- /dev/null
+++ b/roms/u-boot/board/inversepath/usbarmory/imximage.cfg
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * USB armory MkI board imximage configuration
+ * http://inversepath.com/usbarmory
+ *
+ * Copyright (C) 2015, Inverse Path
+ * Andrej Rosano <andrej@inversepath.com>
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM sd
+
+
+/* IOMUX */
+
+DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
+DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE     */
+DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE      */
+DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE    */
+
+DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS   */
+DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3  */
+DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
+
+DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS   */
+DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2  */
+DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
+
+DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS   */
+DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1  */
+DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
+
+DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS   */
+DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0  */
+DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
+
+DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK0 */
+DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK1 */
+
+DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS  */
+DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS  */
+DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDS  */
+DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
+
+DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */
+DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
+
+
+/* ESDCTL */
+
+DATA 4 0x63fd9000 0x84180000 /* ESDCTL_ESDCTL  */
+
+DATA 4 0x63fd9004 0x0002002d /* ESDCTL_ESDPTC  */
+DATA 4 0x63fd9008 0x12273030 /* ESDCTL_ESDOTC  */
+DATA 4 0x63fd900c 0x9f5152e3 /* ESDCTL_ESDCFG0 */
+DATA 4 0x63fd9010 0xb68e8a63 /* ESDCTL_ESDCFG1 */
+DATA 4 0x63fd9014 0x01ff00db /* ESDCTL_ESDCFG2 */
+DATA 4 0x63fd9018 0x00011740 /* ESDCTL_ESDMISC */
+
+DATA 4 0x63fd901c 0x00008032 /* ESDCTL_ESDSCR  */
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd901c 0x00000000
+
+DATA 4 0x63fd9020 0x00005800 /* ESDCTL_ESDREF   */
+DATA 4 0x63fd902c 0x000026d2 /* ESDCTL_ESDEWD   */
+DATA 4 0x63fd9030 0x009f0e21 /* ESDCTL_ESDOR    */
+DATA 4 0x63fd9040 0x05380003 /* ESDCTL_ZQHWCTRL */
+DATA 4 0x63fd9058 0x00022227 /* ESDCTL_ODTCTRL  */
+
+DATA 4 0x63fd907c 0x01370138 /* ESDCTL_DGCTRL0  */
+DATA 4 0x63fd9080 0x013b013c /* ESDCTL_DGCTRL1  */
+DATA 4 0x63fd9088 0x35343535 /* ESDCTL_RDDLCTL  */
+DATA 4 0x63fd9090 0x4d444c44 /* ESDCTL_WRDLCTL  */
diff --git a/roms/u-boot/board/inversepath/usbarmory/usbarmory.c b/roms/u-boot/board/inversepath/usbarmory/usbarmory.c
new file mode 100644
index 000000000..086d0522c
--- /dev/null
+++ b/roms/u-boot/board/inversepath/usbarmory/usbarmory.c
@@ -0,0 +1,452 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * USB armory MkI board initialization
+ * http://inversepath.com/usbarmory
+ *
+ * Copyright (C) 2015, Inverse Path
+ * Andrej Rosano <andrej@inversepath.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fs.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_board_rev(void)
+{
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+		(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	int rev = readl(&fuse->gp[6]);
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{MMC_SDHC1_BASE_ADDR}
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* CD not present */
+	return 1;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int ret = 0;
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+
+	return ret;
+}
+
+#define SD_CMD_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			PAD_CTL_PUS_100K_UP)
+#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+			PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+#define PAD_CTRL_UP	PAD_CTL_PUS_100K_UP
+#define PAD_CTRL_GND	PAD_CTL_PUS_100K_DOWN
+
+static void setup_iomux_sd(void)
+{
+	static const iomux_v3_cfg_t pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, MX53_SDHC_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+			     MX53_SDHC_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+			     MX53_SDHC_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+			     MX53_SDHC_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+			     MX53_SDHC_PAD_CTRL),
+		MX53_PAD_EIM_DA13__GPIO3_13,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
+}
+
+static void setup_iomux_led(void)
+{
+	static const iomux_v3_cfg_t pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT6__GPIO4_27,
+			     PAD_CTL_PUS_100K_DOWN),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
+}
+
+static void setup_iomux_i2c(void)
+{
+	static const iomux_v3_cfg_t pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
+}
+
+static void setup_iomux_pinheader(void)
+{
+	static const iomux_v3_cfg_t pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__GPIO5_26, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__GPIO5_27, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+			     MX53_UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
+			     MX53_UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__GPIO5_30, PAD_CTRL_UP),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
+}
+
+static void setup_iomux_unused_boot(void)
+{
+	static const iomux_v3_cfg_t pads[] = {
+		/* Pulled-up pads */
+		NEW_PAD_CTRL(MX53_PAD_EIM_A21__GPIO2_17, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA0__GPIO3_0, PAD_CTRL_UP),
+
+		/* Grounded pads */
+		NEW_PAD_CTRL(MX53_PAD_EIM_LBA__GPIO2_27, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_EB0__GPIO2_28, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_EB1__GPIO2_29, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A18__GPIO2_20, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A19__GPIO2_19, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A20__GPIO2_18, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A22__GPIO2_16, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA1__GPIO3_1, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA2__GPIO3_2, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA3__GPIO3_3, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA4__GPIO3_4, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA5__GPIO3_5, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA6__GPIO3_6, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA7__GPIO3_7, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA8__GPIO3_8, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA9__GPIO3_9, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA10__GPIO3_10, PAD_CTRL_GND),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
+}
+
+static void setup_iomux_unused_nc(void)
+{
+	/* Out of reset values define the pin values before the
+	   ROM is executed so we force all the not connected pins
+	   to a known state */
+	static const iomux_v3_cfg_t pads[] = {
+		/* CONTROL PINS block */
+		NEW_PAD_CTRL(MX53_PAD_GPIO_0__GPIO1_0, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_3__GPIO1_3, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_5__GPIO1_5, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_6__GPIO1_6, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_7__GPIO1_7, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_8__GPIO1_8, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_9__GPIO1_9, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_11__GPIO4_1, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_12__GPIO4_2, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_13__GPIO4_3, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_14__GPIO4_4, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_16__GPIO7_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_17__GPIO7_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_18__GPIO7_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_19__GPIO4_5, PAD_CTRL_UP),
+
+		/* EIM block */
+		NEW_PAD_CTRL(MX53_PAD_EIM_OE__GPIO2_25, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_WAIT__GPIO5_0, PAD_CTRL_UP),
+		/* EIM_LBA: setup_iomux_unused_boot() */
+		NEW_PAD_CTRL(MX53_PAD_EIM_RW__GPIO2_26, PAD_CTRL_UP),
+		/* EIM_EB0: setup_iomux_unused_boot() */
+		/* EIM_EB1: setup_iomux_unused_boot() */
+		NEW_PAD_CTRL(MX53_PAD_EIM_EB2__GPIO2_30, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_CS0__GPIO2_23, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_CS1__GPIO2_24, PAD_CTRL_UP),
+		/* EIM_A16: setup_iomux_unused_boot() */
+		/* EIM_A17: setup_iomux_unused_boot() */
+		/* EIM_A18: setup_iomux_unused_boot() */
+		/* EIM_A19: setup_iomux_unused_boot() */
+		/* EIM_A20: setup_iomux_unused_boot() */
+		/* EIM_A21: setup_iomux_unused_boot() */
+		/* EIM_A22: setup_iomux_unused_boot() */
+		NEW_PAD_CTRL(MX53_PAD_EIM_A23__GPIO6_6, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A24__GPIO5_4, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A25__GPIO5_2, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D16__GPIO3_16, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D17__GPIO3_17, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D18__GPIO3_18, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D19__GPIO3_19, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D20__GPIO3_20, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D21__GPIO3_21, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D22__GPIO3_22, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D23__GPIO3_23, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D27__GPIO3_27, PAD_CTRL_UP),
+		/* EIM_D28: setup_iomux_unused_boot() */
+		/* EIM_D29: setup_iomux_unused_boot() */
+		NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, PAD_CTRL_UP),
+		/* EIM_DA0: setup_iomux_unused_boot() */
+		/* EIM_DA1: setup_iomux_unused_boot() */
+		/* EIM_DA2: setup_iomux_unused_boot() */
+		/* EIM_DA3: setup_iomux_unused_boot() */
+		/* EIM_DA4: setup_iomux_unused_boot() */
+		/* EIM_DA5: setup_iomux_unused_boot() */
+		/* EIM_DA6: setup_iomux_unused_boot() */
+		/* EIM_DA7: setup_iomux_unused_boot() */
+		/* EIM_DA8: setup_iomux_unused_boot() */
+		/* EIM_DA9: setup_iomux_unused_boot() */
+		/* EIM_DA10: setup_iomux_unused_boot() */
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA11__GPIO3_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA12__GPIO3_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA13__GPIO3_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA14__GPIO3_14, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA15__GPIO3_15, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__GPIO6_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__GPIO6_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__GPIO6_8, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__GPIO6_7, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__GPIO6_9, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__GPIO6_10, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__GPIO6_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__GPIO6_14, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS3__GPIO6_16, PAD_CTRL_UP),
+
+		/* MISC block */
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__GPIO1_31, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__GPIO1_22, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__GPIO1_25, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__GPIO1_23, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__GPIO1_24, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__GPIO1_28, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__GPIO1_27, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__GPIO1_26, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__GPIO1_30, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__GPIO1_29, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__GPIO4_6, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__GPIO4_7, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__GPIO4_8, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__GPIO4_9, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__GPIO4_10, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__GPIO4_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__GPIO4_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__GPIO4_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL4__GPIO4_14, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW4__GPIO4_15, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_SD2_CMD__GPIO1_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_SD2_CLK__GPIO1_10, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__GPIO1_15, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__GPIO1_14, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__GPIO1_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__GPIO1_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_BUFFER_EN__GPIO7_1, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_CS_0__GPIO7_9, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_CS_1__GPIO7_10, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DA_0__GPIO7_6, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DA_1__GPIO7_7, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DA_2__GPIO7_8, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__GPIO2_0, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__GPIO2_1, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__GPIO2_2, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__GPIO2_3, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__GPIO2_4, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__GPIO2_5, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__GPIO2_6, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__GPIO2_7, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__GPIO2_8, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__GPIO2_9, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__GPIO2_10, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__GPIO2_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__GPIO2_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__GPIO2_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__GPIO2_14, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__GPIO2_15, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DIOR__GPIO7_3, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__GPIO6_17, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__GPIO6_18, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DMARQ__GPIO7_0, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_INTRQ__GPIO7_2, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__GPIO7_5, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__GPIO7_4, PAD_CTRL_UP),
+
+		/* IPU block */
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT4__GPIO5_22, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT5__GPIO5_23, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT6__GPIO5_24, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT7__GPIO5_25, PAD_CTRL_UP),
+		/* CSI0_DAT8: setup_iomux_pinheader() */
+		/* CSI0_DAT9: setup_iomux_pinheader() */
+		/* CSI0_DAT10: setup_iomux_pinheader() */
+		/* CSI0_DAT11: setup_iomux_pinheader() */
+		/* CSI0_DAT12: setup_iomux_pinheader() */
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__GPIO5_31, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT14__GPIO6_0, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT15__GPIO6_1, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT16__GPIO6_2, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT17__GPIO6_3, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT18__GPIO6_4, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT19__GPIO6_5, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_VSYNC__GPIO5_21, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_PIXCLK__GPIO5_18, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_MCLK__GPIO5_19, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DATA_EN__GPIO5_20, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DI0_PIN2__GPIO4_18, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DI0_PIN3__GPIO4_19, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DI0_PIN15__GPIO4_17, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT0__GPIO4_21, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT1__GPIO4_22, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT2__GPIO4_23, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT3__GPIO4_24, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT4__GPIO4_25, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT5__GPIO4_26, PAD_CTRL_UP),
+		/* DISP0_DAT6: setup_iomux_led() */
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT7__GPIO4_28, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT8__GPIO4_29, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT9__GPIO4_30, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT10__GPIO4_31, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT11__GPIO5_5, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT12__GPIO5_6, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT13__GPIO5_7, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT14__GPIO5_8, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT15__GPIO5_9, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT16__GPIO5_10, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT17__GPIO5_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT18__GPIO5_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT19__GPIO5_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT20__GPIO5_14, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT21__GPIO5_15, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT22__GPIO5_16, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT23__GPIO5_17, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DI0_DISP_CLK__GPIO4_16, PAD_CTRL_UP),
+
+		/* LVDS block */
+		NEW_PAD_CTRL(MX53_PAD_LVDS0_TX0_P__GPIO7_30, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS0_TX1_P__GPIO7_28, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS0_TX2_P__GPIO7_26, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS0_TX3_P__GPIO7_22, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS1_TX0_P__GPIO6_30, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS1_TX1_P__GPIO6_28, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS1_TX2_P__GPIO6_24, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS1_TX3_P__GPIO6_22, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS0_CLK_P__GPIO7_24, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS1_CLK_P__GPIO6_26, PAD_CTRL_UP),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
+}
+
+#define CPU_CLOCK 800
+
+static void set_clock(void)
+{
+	u32 ref_clk = MXC_HCLK;
+	const uint32_t cpuclk = CPU_CLOCK;
+	const uint32_t dramclk = 400;
+	int ret;
+
+	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to %dMHZ failed\n", cpuclk);
+
+	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
+	if (ret)
+		printf("CPU:   Switch peripheral clock to %dMHz failed\n",
+		       dramclk);
+
+	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_unused_nc();
+	setup_iomux_unused_boot();
+	setup_iomux_sd();
+	setup_iomux_led();
+	setup_iomux_pinheader();
+	set_clock();
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	setup_iomux_i2c();
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30);
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Inverse Path USB armory MkI\n");
+	return 0;
+}
+
+#ifndef CONFIG_CMDLINE
+static char *ext2_argv[] = {
+	"ext2load",
+	"mmc",
+	"0:1",
+	USBARMORY_FIT_ADDR,
+	USBARMORY_FIT_PATH
+};
+
+static char *bootm_argv[] = {
+	"bootm",
+	USBARMORY_FIT_ADDR
+};
+
+int board_run_command(const char *cmdline)
+{
+	printf("%s %s %s %s %s\n", ext2_argv[0], ext2_argv[1], ext2_argv[2],
+	       ext2_argv[3], ext2_argv[4]);
+
+	if (do_ext2load(NULL, 0, 5, ext2_argv) != 0) {
+		udelay(5*1000*1000);
+		return 1;
+	}
+
+	printf("%s %s\n", bootm_argv[0], bootm_argv[1]);
+	do_bootm(NULL, 0, 2, bootm_argv);
+
+	return 1;
+}
+#endif
diff --git a/roms/u-boot/board/iomega/iconnect/Kconfig b/roms/u-boot/board/iomega/iconnect/Kconfig
new file mode 100644
index 000000000..e56b02941
--- /dev/null
+++ b/roms/u-boot/board/iomega/iconnect/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ICONNECT
+
+config SYS_BOARD
+	default "iconnect"
+
+config SYS_VENDOR
+	default "iomega"
+
+config SYS_CONFIG_NAME
+	default "iconnect"
+
+endif
diff --git a/roms/u-boot/board/iomega/iconnect/MAINTAINERS b/roms/u-boot/board/iomega/iconnect/MAINTAINERS
new file mode 100644
index 000000000..167cf074b
--- /dev/null
+++ b/roms/u-boot/board/iomega/iconnect/MAINTAINERS
@@ -0,0 +1,6 @@
+ICONNECT BOARD
+M:	Luka Perkov <luka@openwrt.org>
+S:	Maintained
+F:	board/iomega/iconnect/
+F:	include/configs/iconnect.h
+F:	configs/iconnect_defconfig
diff --git a/roms/u-boot/board/iomega/iconnect/Makefile b/roms/u-boot/board/iomega/iconnect/Makefile
new file mode 100644
index 000000000..fd975b016
--- /dev/null
+++ b/roms/u-boot/board/iomega/iconnect/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= iconnect.o
diff --git a/roms/u-boot/board/iomega/iconnect/iconnect.c b/roms/u-boot/board/iomega/iconnect/iconnect.c
new file mode 100644
index 000000000..fe4be28b1
--- /dev/null
+++ b/roms/u-boot/board/iomega/iconnect/iconnect.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/global_data.h>
+#include "iconnect.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(ICONNECT_OE_VAL_LOW,
+			  ICONNECT_OE_VAL_HIGH,
+			  ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,	/* Reset signal */
+		MPP7_GPO,
+		MPP8_TW_SDA,		/* I2C */
+		MPP9_TW_SCK,		/* I2C */
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_GPO,		/* Reset button */
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GE1_14,
+		MPP35_GPIO,		/* OTB button */
+		MPP36_AUDIO_SPDIFI,
+		MPP37_AUDIO_SPDIFO,
+		MPP38_GPIO,
+		MPP39_TDM_SPI_CS0,
+		MPP40_TDM_SPI_SCK,
+		MPP41_GPIO,		/* LED brightness */
+		MPP42_GPIO,		/* LED power (blue) */
+		MPP43_GPIO,		/* LED power (red) */
+		MPP44_GPIO,		/* LED USB 1 */
+		MPP45_GPIO,		/* LED USB 2 */
+		MPP46_GPIO,		/* LED USB 3 */
+		MPP47_GPIO,		/* LED USB 4 */
+		MPP48_GPIO,		/* LED OTB */
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/iomega/iconnect/iconnect.h b/roms/u-boot/board/iomega/iconnect/iconnect.h
new file mode 100644
index 000000000..4f0be7191
--- /dev/null
+++ b/roms/u-boot/board/iomega/iconnect/iconnect.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ */
+
+#ifndef __ICONNECT_H
+#define __ICONNECT_H
+
+#define ICONNECT_OE_LOW			(~(1 << 7))
+#define ICONNECT_OE_HIGH		(~(1 << 10))
+#define ICONNECT_OE_VAL_LOW		(0)
+#define ICONNECT_OE_VAL_HIGH		(1 << 10)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __ICONNECT_H */
diff --git a/roms/u-boot/board/iomega/iconnect/kwbimage.cfg b/roms/u-boot/board/iomega/iconnect/kwbimage.cfg
new file mode 100644
index 000000000..ffe87d86c
--- /dev/null
+++ b/roms/u-boot/board/iomega/iconnect/kwbimage.cfg
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2009-2012
+# Wojciech Dubowik <wojciech.dubowik@neratec.com>
+# Luka Perkov <luka@openwrt.org>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xffd100e0 0x1b1b1b9b
+
+# Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xffd01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30, (3120 DDR2 clks refresh rate)
+# bit23-14: 0x0,
+# bit24:    0x1,   enable exit self refresh mode on DDR access
+# bit25:    0x1,   required
+# bit29-26: 0x0,
+# bit31-30: 0x1,
+
+DATA 0xffd01404 0x37543000	# DDR Controller Control Low
+# bit4:     0x0, addr/cmd in smame cycle
+# bit5:     0x0, clk is driven during self refresh, we don't care for APX
+# bit6:     0x0, use recommended falling edge of clk for addr/cmd
+# bit14:    0x0, input buffer always powered up
+# bit18:    0x1, cpu lock transaction enabled
+# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 0x3, required
+# bit31:    0x0, no additional STARTBURST delay
+
+DATA 0xffd01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11-8:  TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000a33	# DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: 0x0, required
+
+DATA 0xffd01410 0x000000cc	# DDR Address Control
+# bit1-0:   00,  Cs0width (x8)
+# bit3-2:   11,  Cs0size (1Gb)
+# bit5-4:   00,  Cs1width (x8)
+# bit7-6:   11,  Cs1size (1Gb)
+# bit9-8:   00,  Cs2width (nonexistent)
+# bit11-10: 00,  Cs2size (nonexistent)
+# bit13-12: 00,  Cs3width (nonexistent)
+# bit15-14: 00,  Cs3size (nonexistent)
+# bit16:    0,   Cs0AddrSel
+# bit17:    0,   Cs1AddrSel
+# bit18:    0,   Cs2AddrSel
+# bit19:    0,   Cs3AddrSel
+# bit31-20: 0x0, required
+
+DATA 0xffd01414 0x00000000	# DDR Open Pages Control
+# bit0:    0,   OpenPage enabled
+# bit31-1: 0x0, required
+
+DATA 0xffd01418 0x00000000	# DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0x0, required
+
+DATA 0xffd0141c 0x00000c52	# DDR Mode
+# bit2-0:   0x2, BurstLen=2 required
+# bit3:     0x0, BurstType=0 required
+# bit6-4:   0x4, CL=5
+# bit7:     0x0, TestMode=0 normal
+# bit8:     0x0, DLL reset=0 normal
+# bit11-9:  0x6, auto-precharge write recovery
+# bit12:    0x0, PD must be zero
+# bit31-13: 0x0, required
+
+DATA 0xffd01420 0x00000040	# DDR Extended Mode
+# bit0:     0,   DDR DLL enabled
+# bit1:     0,   DDR drive strenght normal
+# bit2:     0,   DDR ODT control lsd (disabled)
+# bit5-3:   0x0, required
+# bit6:     1,   DDR ODT control msb, (disabled)
+# bit9-7:   0x0, required
+# bit10:    0,   differential DQS enabled
+# bit11:    0,   required
+# bit12:    0,   DDR output buffer enabled
+# bit31-13: 0x0, required
+
+DATA 0xffd01424 0x0000f17f	# DDR Controller Control High
+# bit2-0:   0x7, required
+# bit3:     0x1, MBUS Burst Chop disabled
+# bit6-4:   0x7, required
+# bit7:     0x0,
+# bit8:     0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9:     0x0, no half clock cycle addition to dataout
+# bit10:    0x0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11:    0x0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf, required
+# bit31-16: 0x0, required
+
+DATA 0xffd01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xffd01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xffd01504 0x0ffffff1	# CS[0]n Size
+# bit0:     0x1,     Window enabled
+# bit1:     0x0,     Write Protect disabled
+# bit3-2:   0x0,     CS0 hit selected
+# bit23-4:  0xfffff, required
+# bit31-24: 0x0f,    Size (i.e. 256MB)
+
+DATA 0xffd01508 0x00000000	# CS[1]n Base address to 256Mb
+DATA 0xffd0150c 0x00000000	# CS[1]n Size, window disabled
+
+DATA 0xffd01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xffd0151c 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000	# DDR ODT Control (Low)
+# bit3-0:     ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4:     ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000	# DDR ODT Control (High)
+# bit1-0:  0x0, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  0x1, ODT1 active NEVER!
+# bit31-4: 0x0, required
+
+DATA 0xffd0149c 0x0000e803	# CPU ODT Control
+DATA 0xffd01480 0x00000001	# DDR Initialization Control
+# bit0: 0x1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/is1/MAINTAINERS b/roms/u-boot/board/is1/MAINTAINERS
new file mode 100644
index 000000000..a737e13f8
--- /dev/null
+++ b/roms/u-boot/board/is1/MAINTAINERS
@@ -0,0 +1,6 @@
+SOCFPGA IS1 BOARD
+M:	Pavel Machek <pavel@denx.de>
+S:	Maintained
+F:	board/is1/
+F:	include/configs/socfpga_is1.h
+F:	configs/socfpga_is1_defconfig
diff --git a/roms/u-boot/board/is1/Makefile b/roms/u-boot/board/is1/Makefile
new file mode 100644
index 000000000..e499116b6
--- /dev/null
+++ b/roms/u-boot/board/is1/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/is1/qts/iocsr_config.h b/roms/u-boot/board/is1/qts/iocsr_config.h
new file mode 100644
index 000000000..1d2774aa4
--- /dev/null
+++ b/roms/u-boot/board/is1/qts/iocsr_config.h
@@ -0,0 +1,659 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00000000,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00020000,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x000C0300,
+	0x300C0000,
+	0x30000000,
+	0x000000C0,
+	0x000300C0,
+	0x80008000,
+	0x0000007F,
+	0x0001FE00,
+	0x07F80000,
+	0xE0000000,
+	0x0000001F,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x00007F80,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x01800000,
+	0x00000006,
+	0x00601806,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x00100000,
+	0x300C0000,
+	0x0FF00000,
+	0x00000000,
+	0x00040000,
+	0x00008000,
+	0x00080000,
+	0x00000000,
+	0x18000000,
+	0x00000060,
+	0x06018060,
+	0x00004000,
+	0x0C0300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x06000018,
+	0x00006018,
+	0x01806018,
+	0x00001000,
+	0x0300C030,
+	0x0300C000,
+	0x0300000C,
+	0x0000300C,
+	0x00C0300C,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x08024001,
+	0x00100000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x00000000,
+	0x00000010,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680A28,
+	0x41034030,
+	0x02081A00,
+	0x80A280D0,
+	0x34051406,
+	0x01A02490,
+	0x280D0000,
+	0x30C0680A,
+	0x00000340,
+	0xD000001A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680A28,
+	0x49034030,
+	0x12481A02,
+	0x80A280D0,
+	0x34030C06,
+	0x01A00040,
+	0x280D0002,
+	0x30C0680A,
+	0x02490340,
+	0xD012481A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x69A47A05,
+	0xF228A3D5,
+	0xF6D1451E,
+	0x0352D348,
+	0x821A0000,
+	0x0000D000,
+	0x05140680,
+	0xD569A47A,
+	0x1E8A28A3,
+	0x48F6D145,
+	0x00035292,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x0000FF00,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0xF8482000,
+	0x00000007,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x04864000,
+	0x69A47A01,
+	0x8A28A3D5,
+	0xF4D1451E,
+	0x0352D348,
+	0x821A028A,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8A28A3,
+	0x48F6D145,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x0000FF00,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0x00040100,
+	0x00000800,
+	0x00040100,
+	0x00000800,
+	0x00040100,
+	0x00000800,
+	0x00040100,
+	0x00000800,
+	0x08000000,
+	0x00000000,
+	0xF8000020,
+	0x00000007,
+	0x02000000,
+	0x00400000,
+	0x00020080,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x00020080,
+	0x00000400,
+	0x04000000,
+	0xC8800000,
+	0x00003001,
+	0x00004000,
+	0x01000000,
+	0x00200000,
+	0x00010040,
+	0x00000200,
+	0x00010040,
+	0x00000200,
+	0x00010040,
+	0x00000200,
+	0x00010040,
+	0x00000200,
+	0x02000000,
+	0x00000000,
+	0xFE000008,
+	0x00000001,
+	0x00800000,
+	0x00100000,
+	0x00000200,
+	0x08283380,
+	0x00000000,
+	0x00122C80,
+	0x1A000008,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x6800000D,
+	0x03400000,
+	0x001A0000,
+	0x0000D000,
+	0x00000680,
+	0xA0000034,
+	0x0D000001,
+	0x00680000,
+	0x00034000,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x0000FF00,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00003FC0,
+	0x00800000,
+	0x00040100,
+	0x00000800,
+	0x00040100,
+	0x00000800,
+	0x00040100,
+	0x00000800,
+	0x00040100,
+	0x00000800,
+	0x08000000,
+	0x00000000,
+	0xF8000020,
+	0x00000007,
+	0x02000000,
+	0x00400000,
+	0x00020080,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x01000000,
+	0x00200000,
+	0x00010040,
+	0x00000200,
+	0x00010040,
+	0x00000200,
+	0x00010040,
+	0x00000200,
+	0x00010040,
+	0x00000200,
+	0x02000000,
+	0x00000004,
+	0x00001008,
+	0x00402000,
+	0x00800000,
+	0x00100001,
+	0x00000200,
+	0x08283380,
+	0x00000000,
+	0x00102C80,
+	0x1A000008,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x6800000D,
+	0x03400000,
+	0x001A0000,
+	0x0000D000,
+	0x00000680,
+	0xA0000034,
+	0x0D000001,
+	0x00680000,
+	0x00034000,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x0000FF00,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00003FC0,
+	0x00800000,
+	0x00489800,
+	0x9E1A0000,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0xC0000004,
+	0x0000003F,
+	0x0000FF00,
+	0x03FC0000,
+	0xF0000000,
+	0x0000000F,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0xE0000002,
+	0x0000001F,
+	0x00007F80,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0xF0000001,
+	0x0000000F,
+	0x00003FC0,
+	0x00FF0000,
+	0xFC000000,
+	0x00000003,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x0001FE00,
+	0x07F80000,
+	0xE0000000,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/is1/qts/pinmux_config.h b/roms/u-boot/board/is1/qts/pinmux_config.h
new file mode 100644
index 000000000..bf79975b9
--- /dev/null
+++ b/roms/u-boot/board/is1/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	0, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	0, /* FLASHIO2 */
+	0, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	0, /* FLASHIO9 */
+	0, /* FLASHIO10 */
+	0, /* FLASHIO11 */
+	3, /* GENERALIO0 */
+	3, /* GENERALIO1 */
+	3, /* GENERALIO2 */
+	3, /* GENERALIO3 */
+	3, /* GENERALIO4 */
+	3, /* GENERALIO5 */
+	3, /* GENERALIO6 */
+	3, /* GENERALIO7 */
+	3, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	3, /* GENERALIO13 */
+	3, /* GENERALIO14 */
+	0, /* GENERALIO15 */
+	0, /* GENERALIO16 */
+	0, /* GENERALIO17 */
+	0, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	2, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	0, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	0, /* GPLMUX57 */
+	0, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	0, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	0, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	1, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/is1/qts/pll_config.h b/roms/u-boot/board/is1/qts/pll_config.h
new file mode 100644
index 000000000..218ab35c0
--- /dev/null
+++ b/roms/u-boot/board/is1/qts/pll_config.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 59
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1500000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 488281
+#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
+#define CONFIG_HPS_CLK_QSPI_HZ 375000000
+#define CONFIG_HPS_CLK_SPIM_HZ 12500000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/roms/u-boot/board/is1/qts/sdram_config.h b/roms/u-boot/board/is1/qts/sdram_config.h
new file mode 100644
index 000000000..2573171ab
--- /dev/null
+++ b/roms/u-boot/board/is1/qts/sdram_config.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			64
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x777
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	8
+#define CALIB_VFIFO_OFFSET	6
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x5555048d
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	2
+#define RW_MGR_MEM_DATA_WIDTH	16
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	2
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	2
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	2
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080431,
+	0x10080530,
+	0x10090044,
+	0x100a00c8,
+	0x100b0000,
+	0x10380400,
+	0x10080449,
+	0x100804c8,
+	0x100a0024,
+	0x10090130,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/roms/u-boot/board/is1/socfpga.c b/roms/u-boot/board/is1/socfpga.c
new file mode 100644
index 000000000..2a543bf7b
--- /dev/null
+++ b/roms/u-boot/board/is1/socfpga.c
@@ -0,0 +1,4 @@
+/*
+ * Currently nothing special is needed on this board, empty file to
+ * make build scripts happy
+ */
diff --git a/roms/u-boot/board/isee/igep003x/Kconfig b/roms/u-boot/board/isee/igep003x/Kconfig
new file mode 100644
index 000000000..68a68fc52
--- /dev/null
+++ b/roms/u-boot/board/isee/igep003x/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AM335X_IGEP003X
+
+config SYS_BOARD
+	default "igep003x"
+
+config SYS_VENDOR
+	default "isee"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "am335x_igep003x"
+
+endif
diff --git a/roms/u-boot/board/isee/igep003x/MAINTAINERS b/roms/u-boot/board/isee/igep003x/MAINTAINERS
new file mode 100644
index 000000000..ba92e64e2
--- /dev/null
+++ b/roms/u-boot/board/isee/igep003x/MAINTAINERS
@@ -0,0 +1,6 @@
+IGEP003X BOARD
+M:	Javier Martínez Canillas <javier@dowhile0.org>
+S:	Maintained
+F:	board/isee/igep003x/
+F:	include/configs/am335x_igep003x.h
+F:	configs/am335x_igep003x_defconfig
diff --git a/roms/u-boot/board/isee/igep003x/Makefile b/roms/u-boot/board/isee/igep003x/Makefile
new file mode 100644
index 000000000..c3e397452
--- /dev/null
+++ b/roms/u-boot/board/isee/igep003x/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/roms/u-boot/board/isee/igep003x/board.c b/roms/u-boot/board/isee/igep003x/board.c
new file mode 100644
index 000000000..02ae7df04
--- /dev/null
+++ b/roms/u-boot/board/isee/igep003x/board.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
+ *
+ * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
+ */
+
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <malloc.h>
+#include <net.h>
+#include <serial.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <fdt_support.h>
+#include <mtd_node.h>
+#include <jffs2/load_kernel.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
+ * and control IGEP0034 green and red LEDs.
+ * U-boot configures these pins as input pullup to detect board revision:
+ * IGEP0034-LITE = 0b00
+ * IGEP0034 (FULL) = 0b01
+ * IGEP0033 = 0b1X
+ */
+#define GPIO_GREEN_REVISION	27
+#define GPIO_RED_REVISION	26
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/*
+ * Routine: get_board_revision
+ * Description: Returns the board revision
+ */
+static int get_board_revision(void)
+{
+	int revision;
+
+	gpio_request(GPIO_GREEN_REVISION, "green_revision");
+	gpio_direction_input(GPIO_GREEN_REVISION);
+	revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
+	gpio_free(GPIO_GREEN_REVISION);
+
+	gpio_request(GPIO_RED_REVISION, "red_revision");
+	gpio_direction_input(GPIO_RED_REVISION);
+	revision = revision + gpio_get_value(GPIO_RED_REVISION);
+	gpio_free(GPIO_RED_REVISION);
+
+	return revision;
+}
+
+#ifdef CONFIG_SPL_BUILD
+/* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
+static const struct ddr_data ddr3_igep0034_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct ddr_data ddr3_igep0034_lite_data = {
+	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
+	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
+	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
+	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
+	.cmd0csratio = K4B2G1646EBIH9_RATIO,
+	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+
+	.cmd1csratio = K4B2G1646EBIH9_RATIO,
+	.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+
+	.cmd2csratio = K4B2G1646EBIH9_RATIO,
+	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_igep0034_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
+	.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
+	.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
+	.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
+	.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
+	.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
+	.zq_config = K4B2G1646EBIH9_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
+};
+
+const struct ctrl_ioregs ioregs_igep0034 = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_igep0034_lite = {
+	.cm0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.cm1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.cm2ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.dt0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.dt1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+};
+
+#define OSC    (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+		400, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+	if (get_board_revision() == 1)
+		config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
+			&ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
+	else
+		config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
+			&ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	gpmc_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	switch (get_board_revision()) {
+		case 0:
+			env_set("board_name", "igep0034-lite");
+			break;
+		case 1:
+			env_set("board_name", "igep0034");
+			break;
+		default:
+			env_set("board_name", "igep0033");
+			break;
+	}
+#endif
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+	static const struct node_info nodes[] = {
+		{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+	};
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+		.phy_if		= PHY_INTERFACE_MODE_RMII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(struct bd_info *bis)
+{
+	int rv, ret = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+	}
+
+	writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
+	       &cdev->miisel);
+
+	if (get_board_revision() == 1)
+		cpsw_slaves[0].phy_addr = 1;
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		ret += rv;
+
+	return ret;
+}
+#endif
diff --git a/roms/u-boot/board/isee/igep003x/board.h b/roms/u-boot/board/isee/igep003x/board.h
new file mode 100644
index 000000000..ec54f860c
--- /dev/null
+++ b/roms/u-boot/board/isee/igep003x/board.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * IGEP COM AQUILA boards information header
+ *
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We must be able to enable uart0, for initial output. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/roms/u-boot/board/isee/igep003x/mux.c b/roms/u-boot/board/isee/igep003x/mux.c
new file mode 100644
index 000000000..550e3b319
--- /dev/null
+++ b/roms/u-boot/board/isee/igep003x/mux.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},		/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TXD0 */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TXD1 */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REF_CLK */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},	/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	{OFFSET(gpmc_ad10), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* GPIO0_26 */
+	{OFFSET(gpmc_ad11), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* GPIO0_27 */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+/*
+ * Do board-specific muxes.
+ */
+void enable_board_pin_mux(void)
+{
+	/* NAND Flash */
+	configure_module_pin_mux(nand_pin_mux);
+	/* SD Card */
+	configure_module_pin_mux(mmc0_pin_mux);
+	/* Ethernet pinmux. */
+	configure_module_pin_mux(rmii1_pin_mux);
+	/* GPIO pinmux. */
+	configure_module_pin_mux(gpio_pin_mux);
+}
diff --git a/roms/u-boot/board/isee/igep00x0/Kconfig b/roms/u-boot/board/isee/igep00x0/Kconfig
new file mode 100644
index 000000000..597d6d92c
--- /dev/null
+++ b/roms/u-boot/board/isee/igep00x0/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_OMAP3_IGEP00X0
+
+config SYS_BOARD
+	default "igep00x0"
+
+config SYS_VENDOR
+	default "isee"
+
+config SYS_CONFIG_NAME
+	default "omap3_igep00x0"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/isee/igep00x0/MAINTAINERS b/roms/u-boot/board/isee/igep00x0/MAINTAINERS
new file mode 100644
index 000000000..a07c9f49a
--- /dev/null
+++ b/roms/u-boot/board/isee/igep00x0/MAINTAINERS
@@ -0,0 +1,6 @@
+IGEP00X0 BOARD
+M:	Enric Balletbo i Serra <eballetbo@gmail.com>
+S:	Maintained
+F:	board/isee/igep00x0/
+F:	include/configs/omap3_igep00x0.h
+F:	configs/igep00x0_defconfig
diff --git a/roms/u-boot/board/isee/igep00x0/Makefile b/roms/u-boot/board/isee/igep00x0/Makefile
new file mode 100644
index 000000000..e095bcada
--- /dev/null
+++ b/roms/u-boot/board/isee/igep00x0/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= spl.o common.o
+else
+obj-y	:= igep00x0.o common.o
+endif
diff --git a/roms/u-boot/board/isee/igep00x0/common.c b/roms/u-boot/board/isee/igep00x0/common.c
new file mode 100644
index 000000000..3fdf83e84
--- /dev/null
+++ b/roms/u-boot/board/isee/igep00x0/common.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <twl4030.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/omap_mmc.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <jffs2/load_kernel.h>
+#include <linux/delay.h>
+#include <linux/mtd/rawnand.h>
+#include "igep00x0.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_DEFAULT();
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	int loops = 100;
+
+	/* find out flash memory type, assume NAND first */
+	gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
+	gpmc_init();
+
+	/* Issue a RESET and then READID */
+	writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
+	writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
+	while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
+	                                        != NAND_STATUS_READY) {
+		udelay(1);
+		if (--loops == 0) {
+			gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
+			gpmc_init();	/* reinitialize for OneNAND */
+			break;
+		}
+	}
+
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(struct bd_info *bis)
+{
+	return omap_mmc_init(0, 0, 0, -1, -1);
+}
+
+void board_mmc_power_init(void)
+{
+	twl4030_power_mmc_init(0);
+}
+#endif
diff --git a/roms/u-boot/board/isee/igep00x0/igep00x0.c b/roms/u-boot/board/isee/igep00x0/igep00x0.c
new file mode 100644
index 000000000..0932f62b9
--- /dev/null
+++ b/roms/u-boot/board/isee/igep00x0/igep00x0.c
@@ -0,0 +1,263 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ */
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <net.h>
+#include <status_led.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <twl4030.h>
+#include <netdev.h>
+#include <spl.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/delay.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/mtd/onenand.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+#include <fdt_support.h>
+#include "igep00x0.h"
+
+static const struct ns16550_plat igep_serial = {
+	.base = OMAP34XX_UART3,
+	.reg_shift = 2,
+	.clock = V_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
+};
+
+U_BOOT_DRVINFO(igep_uart) = {
+	"ns16550_serial",
+	&igep_serial
+};
+
+/*
+ * Routine: get_board_revision
+ * Description: GPIO_28 and GPIO_129 are used to read board and revision from
+ * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from
+ * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because
+ * this functionality is shared by USB HOST.
+ * Once USB reset is applied, U-boot configures these pins as input pullup to
+ * detect board and revision:
+ * IGEP0020-RF = 0b00
+ * IGEP0020-RC = 0b01
+ * IGEP0030-RG = 0b10
+ * IGEP0030-RE = 0b11
+ */
+static int get_board_revision(void)
+{
+	int revision;
+
+	gpio_request(IGEP0030_USB_TRANSCEIVER_RESET,
+				"igep0030_usb_transceiver_reset");
+	gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0);
+
+	gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection");
+	gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION);
+	revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION);
+	gpio_free(GPIO_IGEP00X0_BOARD_DETECTION);
+
+	gpio_request(GPIO_IGEP00X0_REVISION_DETECTION,
+				"igep00x0_revision_detection");
+	gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION);
+	revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION);
+	gpio_free(GPIO_IGEP00X0_REVISION_DETECTION);
+
+	gpio_free(IGEP0030_USB_TRANSCEIVER_RESET);
+
+	return revision;
+}
+
+int onenand_board_init(struct mtd_info *mtd)
+{
+	if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
+		struct onenand_chip *this = mtd->priv;
+		this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+		return 0;
+	}
+	return 1;
+}
+
+#if defined(CONFIG_CMD_NET)
+static void reset_net_chip(int gpio)
+{
+	if (!gpio_request(gpio, "eth nrst")) {
+		gpio_direction_output(gpio, 1);
+		udelay(1);
+		gpio_set_value(gpio, 0);
+		udelay(40);
+		gpio_set_value(gpio, 1);
+		mdelay(10);
+	}
+}
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *		Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+	static const u32 gpmc_lan_config[] = {
+		NET_LAN9221_GPMC_CONFIG1,
+		NET_LAN9221_GPMC_CONFIG2,
+		NET_LAN9221_GPMC_CONFIG3,
+		NET_LAN9221_GPMC_CONFIG4,
+		NET_LAN9221_GPMC_CONFIG5,
+		NET_LAN9221_GPMC_CONFIG6,
+	};
+
+	enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
+			CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+
+	reset_net_chip(64);
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_SMC911X
+	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#else
+	return 0;
+#endif
+}
+#else
+static inline void setup_net_chip(void) {}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+static int ft_enable_by_compatible(void *blob, char *compat, int enable)
+{
+	int off = fdt_node_offset_by_compatible(blob, -1, compat);
+	if (off < 0)
+		return off;
+
+	if (enable)
+		fdt_status_okay(blob, off);
+	else
+		fdt_status_disabled(blob, off);
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+	static const struct node_info nodes[] = {
+		{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+		{ "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, },
+	};
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+	ft_enable_by_compatible(blob, "ti,omap2-nand",
+				gpmc_cs0_flash == MTD_DEV_TYPE_NAND);
+	ft_enable_by_compatible(blob, "ti,omap2-onenand",
+				gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND);
+
+	return 0;
+}
+#endif
+
+void set_led(void)
+{
+	switch (get_board_revision()) {
+	case 0:
+	case 1:
+		gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led");
+		gpio_direction_output(IGEP0020_GPIO_LED, 1);
+		break;
+	case 2:
+	case 3:
+		gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led");
+		gpio_direction_output(IGEP0030_GPIO_LED, 0);
+		break;
+	default:
+		/* Should not happen... */
+		break;
+	}
+}
+
+void set_boardname(void)
+{
+	char rev[5] = { 'F','C','G','E', };
+	int i = get_board_revision();
+
+	rev[i+1] = 0;
+	env_set("board_rev", rev + i);
+	env_set("board_name", i < 2 ? "igep0020" : "igep0030");
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	t2_t *t2_base = (t2_t *)T2_BASE;
+	u32 pbias_lite;
+
+	twl4030_power_init();
+
+	/* set VSIM to 1.8V */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
+				TWL4030_PM_RECEIVER_VSIM_VSEL_18,
+				TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
+				TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+	/* set up dual-voltage GPIOs to 1.8V */
+	pbias_lite = readl(&t2_base->pbias_lite);
+	pbias_lite &= ~PBIASLITEVMODE1;
+	pbias_lite |= PBIASLITEPWRDNZ1;
+	writel(pbias_lite, &t2_base->pbias_lite);
+	if (get_cpu_family() == CPU_OMAP36XX)
+		writel(readl(OMAP34XX_CTRL_WKUP_CTRL) |
+					 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
+					 OMAP34XX_CTRL_WKUP_CTRL);
+
+	setup_net_chip();
+
+	omap_die_id_display();
+
+	set_led();
+
+	set_boardname();
+
+	return 0;
+}
+
+void board_mtdparts_default(const char **mtdids, const char **mtdparts)
+{
+	struct mtd_info *mtd = get_mtd_device(NULL, 0);
+	if (mtd) {
+		static char ids[24];
+		static char parts[48];
+		const char *linux_name = "omap2-nand";
+		if (strncmp(mtd->name, "onenand0", 8) == 0)
+			linux_name = "omap2-onenand";
+		snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
+		snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
+		         linux_name, 4 * mtd->erasesize >> 10);
+		*mtdids = ids;
+		*mtdparts = parts;
+	}
+}
diff --git a/roms/u-boot/board/isee/igep00x0/igep00x0.h b/roms/u-boot/board/isee/igep00x0/igep00x0.h
new file mode 100644
index 000000000..aa532acad
--- /dev/null
+++ b/roms/u-boot/board/isee/igep00x0/igep00x0.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ */
+#ifndef _IGEP00X0_H_
+#define _IGEP00X0_H_
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT()\
+	MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
+	MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
+	MUX_VAL(CP(SDRC_D2),        (IEN  | PTD | DIS | M0)) /* SDRC_D2 */\
+	MUX_VAL(CP(SDRC_D3),        (IEN  | PTD | DIS | M0)) /* SDRC_D3 */\
+	MUX_VAL(CP(SDRC_D4),        (IEN  | PTD | DIS | M0)) /* SDRC_D4 */\
+	MUX_VAL(CP(SDRC_D5),        (IEN  | PTD | DIS | M0)) /* SDRC_D5 */\
+	MUX_VAL(CP(SDRC_D6),        (IEN  | PTD | DIS | M0)) /* SDRC_D6 */\
+	MUX_VAL(CP(SDRC_D7),        (IEN  | PTD | DIS | M0)) /* SDRC_D7 */\
+	MUX_VAL(CP(SDRC_D8),        (IEN  | PTD | DIS | M0)) /* SDRC_D8 */\
+	MUX_VAL(CP(SDRC_D9),        (IEN  | PTD | DIS | M0)) /* SDRC_D9 */\
+	MUX_VAL(CP(SDRC_D10),       (IEN  | PTD | DIS | M0)) /* SDRC_D10 */\
+	MUX_VAL(CP(SDRC_D11),       (IEN  | PTD | DIS | M0)) /* SDRC_D11 */\
+	MUX_VAL(CP(SDRC_D12),       (IEN  | PTD | DIS | M0)) /* SDRC_D12 */\
+	MUX_VAL(CP(SDRC_D13),       (IEN  | PTD | DIS | M0)) /* SDRC_D13 */\
+	MUX_VAL(CP(SDRC_D14),       (IEN  | PTD | DIS | M0)) /* SDRC_D14 */\
+	MUX_VAL(CP(SDRC_D15),       (IEN  | PTD | DIS | M0)) /* SDRC_D15 */\
+	MUX_VAL(CP(SDRC_D16),       (IEN  | PTD | DIS | M0)) /* SDRC_D16 */\
+	MUX_VAL(CP(SDRC_D17),       (IEN  | PTD | DIS | M0)) /* SDRC_D17 */\
+	MUX_VAL(CP(SDRC_D18),       (IEN  | PTD | DIS | M0)) /* SDRC_D18 */\
+	MUX_VAL(CP(SDRC_D19),       (IEN  | PTD | DIS | M0)) /* SDRC_D19 */\
+	MUX_VAL(CP(SDRC_D20),       (IEN  | PTD | DIS | M0)) /* SDRC_D20 */\
+	MUX_VAL(CP(SDRC_D21),       (IEN  | PTD | DIS | M0)) /* SDRC_D21 */\
+	MUX_VAL(CP(SDRC_D22),       (IEN  | PTD | DIS | M0)) /* SDRC_D22 */\
+	MUX_VAL(CP(SDRC_D23),       (IEN  | PTD | DIS | M0)) /* SDRC_D23 */\
+	MUX_VAL(CP(SDRC_D24),       (IEN  | PTD | DIS | M0)) /* SDRC_D24 */\
+	MUX_VAL(CP(SDRC_D25),       (IEN  | PTD | DIS | M0)) /* SDRC_D25 */\
+	MUX_VAL(CP(SDRC_D26),       (IEN  | PTD | DIS | M0)) /* SDRC_D26 */\
+	MUX_VAL(CP(SDRC_D27),       (IEN  | PTD | DIS | M0)) /* SDRC_D27 */\
+	MUX_VAL(CP(SDRC_D28),       (IEN  | PTD | DIS | M0)) /* SDRC_D28 */\
+	MUX_VAL(CP(SDRC_D29),       (IEN  | PTD | DIS | M0)) /* SDRC_D29 */\
+	MUX_VAL(CP(SDRC_D30),       (IEN  | PTD | DIS | M0)) /* SDRC_D30 */\
+	MUX_VAL(CP(SDRC_D31),       (IEN  | PTD | DIS | M0)) /* SDRC_D31 */\
+	MUX_VAL(CP(SDRC_CLK),       (IEN  | PTD | DIS | M0)) /* SDRC_CLK */\
+	MUX_VAL(CP(SDRC_DQS0),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS0 */\
+	MUX_VAL(CP(SDRC_DQS1),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS1 */\
+	MUX_VAL(CP(SDRC_DQS2),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
+	MUX_VAL(CP(SDRC_DQS3),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */\
+	MUX_VAL(CP(GPMC_A1),        (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
+	MUX_VAL(CP(GPMC_A2),        (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
+	MUX_VAL(CP(GPMC_A3),        (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
+	MUX_VAL(CP(GPMC_A4),        (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
+	MUX_VAL(CP(GPMC_A5),        (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
+	MUX_VAL(CP(GPMC_A6),        (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
+	MUX_VAL(CP(GPMC_A7),        (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
+	MUX_VAL(CP(GPMC_A8),        (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
+	MUX_VAL(CP(GPMC_A9),        (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
+	MUX_VAL(CP(GPMC_A10),       (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
+	MUX_VAL(CP(GPMC_D0),        (IEN  | PTD | DIS | M0)) /* GPMC_D0 */\
+	MUX_VAL(CP(GPMC_D1),        (IEN  | PTD | DIS | M0)) /* GPMC_D1 */\
+	MUX_VAL(CP(GPMC_D2),        (IEN  | PTD | DIS | M0)) /* GPMC_D2 */\
+	MUX_VAL(CP(GPMC_D3),        (IEN  | PTD | DIS | M0)) /* GPMC_D3 */\
+	MUX_VAL(CP(GPMC_D4),        (IEN  | PTD | DIS | M0)) /* GPMC_D4 */\
+	MUX_VAL(CP(GPMC_D5),        (IEN  | PTD | DIS | M0)) /* GPMC_D5 */\
+	MUX_VAL(CP(GPMC_D6),        (IEN  | PTD | DIS | M0)) /* GPMC_D6 */\
+	MUX_VAL(CP(GPMC_D7),        (IEN  | PTD | DIS | M0)) /* GPMC_D7 */\
+	MUX_VAL(CP(GPMC_D8),        (IEN  | PTD | DIS | M0)) /* GPMC_D8 */\
+	MUX_VAL(CP(GPMC_D9),        (IEN  | PTD | DIS | M0)) /* GPMC_D9 */\
+	MUX_VAL(CP(GPMC_D10),       (IEN  | PTD | DIS | M0)) /* GPMC_D10 */\
+	MUX_VAL(CP(GPMC_D11),       (IEN  | PTD | DIS | M0)) /* GPMC_D11 */\
+	MUX_VAL(CP(GPMC_D12),       (IEN  | PTD | DIS | M0)) /* GPMC_D12 */\
+	MUX_VAL(CP(GPMC_D13),       (IEN  | PTD | DIS | M0)) /* GPMC_D13 */\
+	MUX_VAL(CP(GPMC_D14),       (IEN  | PTD | DIS | M0)) /* GPMC_D14 */\
+	MUX_VAL(CP(GPMC_D15),       (IEN  | PTD | DIS | M0)) /* GPMC_D15 */\
+	MUX_VAL(CP(GPMC_NCS0),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS0 */\
+	MUX_VAL(CP(GPMC_NCS1),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS1 */\
+	MUX_VAL(CP(GPMC_NCS2),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS2 */\
+	MUX_VAL(CP(GPMC_NCS3),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS3 */\
+	MUX_VAL(CP(GPMC_NCS4),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS4 */\
+	MUX_VAL(CP(GPMC_NCS5),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS5 */\
+	MUX_VAL(CP(GPMC_NCS6),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS6 */\
+	MUX_VAL(CP(GPMC_NCS7),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
+	MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
+	MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
+	MUX_VAL(CP(GPMC_NOE),       (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
+	MUX_VAL(CP(GPMC_NWE),       (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
+	MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
+	MUX_VAL(CP(GPMC_NBE1),      (IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
+	MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /* GPMC_nWP */\
+	MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /* GPMC_WAIT0 */\
+	MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /* MMC1_CLK */\
+	MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /* MMC1_CMD */\
+	MUX_VAL(CP(MMC1_DAT0),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT0 */\
+	MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT1 */\
+	MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT2 */\
+	MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT3 */\
+	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /* UART1_TX */\
+	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /* UART1_RX */\
+	MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /* UART3_TX */\
+	MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /* UART3_RX */\
+	MUX_VAL(CP(I2C1_SCL),       (IEN  | PTU | EN  | M0)) /* I2C1_SCL */\
+	MUX_VAL(CP(I2C1_SDA),       (IEN  | PTU | EN  | M0)) /* I2C1_SDA */\
+	MUX_VAL(CP(I2C4_SCL),       (IEN  | PTU | EN  | M0)) /* I2C4_SCL */\
+	MUX_VAL(CP(I2C4_SDA),       (IEN  | PTU | EN  | M0)) /* I2C4_SDA */\
+	MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /* SYS_32K */\
+	MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /* GPIO_2 */\
+	MUX_VAL(CP(SYS_BOOT1),      (IEN  | PTD | DIS | M4)) /* GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) /* GPIO_4 */\
+	MUX_VAL(CP(SYS_BOOT3),      (IEN  | PTD | DIS | M4)) /* GPIO_5 */\
+	MUX_VAL(CP(SYS_BOOT4),      (IEN  | PTD | DIS | M4)) /* GPIO_6 */\
+	MUX_VAL(CP(SYS_BOOT5),      (IEN  | PTD | DIS | M4)) /* GPIO_7 */\
+	MUX_VAL(CP(SYS_BOOT6),      (IEN  | PTD | DIS | M4)) /* GPIO_8 */\
+	MUX_VAL(CP(ETK_D14_ES2),    (IEN  | PTU | EN  | M4)) /* GPIO_28 */\
+	MUX_VAL(CP(GPMC_NCS3),      (IDIS | PTD | DIS | M4)) /* GPIO_54 */\
+	MUX_VAL(CP(GPMC_WAIT2),     (IEN  | PTU | DIS | M4)) /* GPIO_64 */\
+	MUX_VAL(CP(GPIO129),        (IEN  | PTU | EN  | M4)) /* GPIO_129 */\
+	MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE0 */\
+	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */
+#endif
diff --git a/roms/u-boot/board/isee/igep00x0/spl.c b/roms/u-boot/board/isee/igep00x0/spl.c
new file mode 100644
index 000000000..f814fe135
--- /dev/null
+++ b/roms/u-boot/board/isee/igep00x0/spl.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <jffs2/load_kernel.h>
+#include <linux/mtd/rawnand.h>
+#include "igep00x0.h"
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+	int mfr, id, err = identify_nand_chip(&mfr, &id);
+
+	timings->mr = MICRON_V_MR_165;
+	if (!err) {
+		switch (mfr) {
+		case NAND_MFR_HYNIX:
+			timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+			timings->ctrla = HYNIX_V_ACTIMA_200;
+			timings->ctrlb = HYNIX_V_ACTIMB_200;
+			break;
+		case NAND_MFR_MICRON:
+			timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+			timings->ctrla = MICRON_V_ACTIMA_200;
+			timings->ctrlb = MICRON_V_ACTIMB_200;
+			break;
+		default:
+			/* Should not happen... */
+			break;
+		}
+		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+		gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
+	} else {
+		if (get_cpu_family() == CPU_OMAP34XX) {
+			timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
+			timings->ctrla = NUMONYX_V_ACTIMA_165;
+			timings->ctrlb = NUMONYX_V_ACTIMB_165;
+			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+		} else {
+			timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
+			timings->ctrla = NUMONYX_V_ACTIMA_200;
+			timings->ctrlb = NUMONYX_V_ACTIMB_200;
+			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+		}
+		gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
+	}
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/k+p/bootscripts/tpcboot.cmd b/roms/u-boot/board/k+p/bootscripts/tpcboot.cmd
new file mode 100644
index 000000000..b81494dd1
--- /dev/null
+++ b/roms/u-boot/board/k+p/bootscripts/tpcboot.cmd
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018
+# Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d tpcboot.cmd boot.scr
+#
+
+
+# Input envs (to be set in environment)
+# Mandatory:
+# kernel_file = "fitImage"
+# boardname = "XXXX"  // set automatically in u-boot
+# boardsoc = "imx6q"  // set automatically in u-boot
+#
+# Optional:
+# bootcmd_force = "nfs" "tftp_kernel"
+# If not set - eMMC/SD boot
+
+# Generic setup
+setenv mmcroot "/dev/mmcblk${devnum}p2 rootwait rw"
+setenv displayargs ""
+setenv mmcargs "setenv bootargs console=${console} ${smp} root=${mmcroot} \
+	${displayargs}"
+setenv miscadj "
+if test '${boardsoc}' = 'imx53'; then
+       setenv bootargs '${bootargs} di=${dig_in} key1=${key1}';
+fi;"
+setenv nfsadj "
+if test '${boardsoc}' = 'imx53'; then
+   if test '${boardtype}' = 'hsc'; then
+       setenv bootargs '${bootargs} dsa_core.blacklist=yes';
+   fi;
+fi;"
+setenv boot_fitImage "
+	setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb';
+	setenv itbcfg "\"#\${fdt_conf}\"";
+	print itbcfg;
+	bootm '${loadaddr}${itbcfg}';"
+
+#------------------------------------------------------------
+#
+# Provide default 'bootcmd' command
+#------------------------------------------------------------
+setenv bootcmd "
+if test -e ${devtype} ${devnum}:${distro_bootpart} ${kernel_file}; then
+	echo Found kernel image: ${kernel_file};
+	if load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} \
+	   ${kernel_file}; then
+		run mmcargs;
+		run miscadj;
+		run boot_fitImage;
+	fi;
+fi;"
+
+#------------------------------------------------------------
+#
+# Provide 'boot_tftp_kernel' command
+#------------------------------------------------------------
+setenv download_kernel "dhcp ${loadaddr} ${kernel_file}"
+
+setenv boot_tftp_kernel "
+if run download_kernel; then
+	run mmcargs;
+	run miscadj;
+	run boot_fitImage;
+fi"
+
+#------------------------------------------------------------
+#
+# Provide 'boot_nfs' command
+#------------------------------------------------------------
+setenv nfsargs "setenv bootargs root=/dev/nfs rw nfsroot='${rootpath}',nolock,nfsvers=3"
+setenv addip "setenv bootargs '${bootargs}' ip='${ipaddr}':'${serverip}':'${gatewayip}':'${netmask}':'${hostname}':eth0:on"
+
+setenv boot_nfs "
+if run download_kernel; then
+	run nfsargs;
+	run addip;
+	run nfsadj;
+	setenv bootargs '${bootargs}' console=${console};
+
+	run boot_fitImage;
+fi"
+
+#------------------------------------------------------------
+#
+# Set correct boot flow
+#------------------------------------------------------------
+
+setenv bcmd "
+if test ! -n ${bootcmd_force}; then
+	run bootcmd;
+fi;
+if test ${bootcmd_force} = nfs; then
+	run boot_nfs;
+else if test ${bootcmd_force} = tftp_kernel; then
+	run boot_tftp_kernel;
+     fi;
+fi"
+
+run bcmd
diff --git a/roms/u-boot/board/k+p/kp_imx53/Kconfig b/roms/u-boot/board/k+p/kp_imx53/Kconfig
new file mode 100644
index 000000000..017c1e30d
--- /dev/null
+++ b/roms/u-boot/board/k+p/kp_imx53/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_KP_IMX53
+
+config SYS_BOARD
+	default "kp_imx53"
+
+config SYS_VENDOR
+	default "k+p"
+
+config SYS_SOC
+	default "mx5"
+
+config SYS_CONFIG_NAME
+	default "kp_imx53"
+
+endif
diff --git a/roms/u-boot/board/k+p/kp_imx53/MAINTAINERS b/roms/u-boot/board/k+p/kp_imx53/MAINTAINERS
new file mode 100644
index 000000000..c105a93e7
--- /dev/null
+++ b/roms/u-boot/board/k+p/kp_imx53/MAINTAINERS
@@ -0,0 +1,6 @@
+KP_IMX53_HSC BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/k+p/kp_imx53/
+F:	include/configs/kp_imx53.h
+F:	configs/kp_imx53_defconfig
diff --git a/roms/u-boot/board/k+p/kp_imx53/Makefile b/roms/u-boot/board/k+p/kp_imx53/Makefile
new file mode 100644
index 000000000..66629c98a
--- /dev/null
+++ b/roms/u-boot/board/k+p/kp_imx53/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2018, DENX Software Engineering
+# Lukasz Majewski <lukma@denx.de>
+#
+# SPDX-License-Identifier:    GPL-2.0+
+#
+
+obj-y		+= kp_imx53.o kp_id_rev.o
diff --git a/roms/u-boot/board/k+p/kp_imx53/kp_id_rev.c b/roms/u-boot/board/k+p/kp_imx53/kp_id_rev.c
new file mode 100644
index 000000000..7103a3e0f
--- /dev/null
+++ b/roms/u-boot/board/k+p/kp_imx53/kp_id_rev.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Based on code developed by:
+ *
+ * Copyright (C) 2012 TQ-Systems GmbH
+ * Daniel Gericke <daniel.gericke@tqs.de>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <i2c.h>
+#include "kp_id_rev.h"
+#include <net.h>
+
+static int eeprom_has_been_read;
+static struct id_eeprom eeprom;
+
+void show_eeprom(void)
+{
+	char safe_string[33];
+	int i;
+	u8 *p;
+
+	puts("Module EEPROM:\n");
+	/* ID */
+	for (i = 0; i <= sizeof(eeprom.id) && 0xff != eeprom.id[i]; ++i)
+		safe_string[i] = eeprom.id[i];
+	safe_string[i] = '\0';
+
+	if (!strncmp(safe_string, "TQM", 3)) {
+		printf("  ID: %s\n", safe_string);
+		env_set("boardtype", safe_string);
+	} else {
+		puts("  unknown hardware variant\n");
+	}
+
+	/* Serial number */
+	for (i = 0; (sizeof(eeprom.serial) >= i) &&
+		    (eeprom.serial[i] >= 0x30) &&
+		    (eeprom.serial[i] <= 0x39); ++i)
+		safe_string[i] = eeprom.serial[i];
+	safe_string[i] = '\0';
+
+	if (strlen(safe_string) == 8) {
+		printf("  SN: %s\n", safe_string);
+		env_set("serial#", safe_string);
+	} else {
+		puts("  unknown serial number\n");
+	}
+
+	/* MAC address  */
+	p = eeprom.mac;
+	if (!is_valid_ethaddr(p)) {
+		printf("  Not valid ETH EEPROM addr!\n");
+		return;
+	}
+
+	printf("  MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+	       p[0], p[1], p[2], p[3], p[4], p[5]);
+
+	eth_env_set_enetaddr("ethaddr", p);
+}
+
+int read_eeprom(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (eeprom_has_been_read)
+		return 0;
+
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+				      CONFIG_SYS_I2C_EEPROM_ADDR,
+				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
+	if (ret) {
+		printf("Cannot find EEPROM !\n");
+		return ret;
+	}
+
+	ret = dm_i2c_read(dev, 0x0, (uchar *)&eeprom, sizeof(eeprom));
+
+	eeprom_has_been_read = (ret == 0) ? 1 : 0;
+	return ret;
+}
+
+int read_board_id(void)
+{
+	unsigned char rev_id = 0x42;
+	char rev_str[32], buf[8];
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(2, 0x22, 1, &dev);
+	if (ret) {
+		printf("Cannot find pcf8574 IO expander !\n");
+		return ret;
+	}
+
+	dm_i2c_read(dev, 0x0, &rev_id, sizeof(rev_id));
+
+	sprintf(rev_str, "%02X", rev_id);
+	if (rev_id & 0x80) {
+		printf("BBoard:4x00 Rev:%s\n", rev_str);
+		env_set("boardtype", "ddc");
+		env_set("fit_config", "imx53_kb_conf");
+	} else {
+		printf("BBoard:40x0 Rev:%s\n", rev_str);
+		env_set("boardtype", "hsc");
+		env_set("fit_config", "imx53_kb_40x0_conf");
+	}
+
+	sprintf(buf, "kp-%s", env_get("boardtype"));
+	env_set("boardname", buf);
+	env_set("boardsoc", "imx53");
+	env_set("kb53_rev", rev_str);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/k+p/kp_imx53/kp_id_rev.h b/roms/u-boot/board/k+p/kp_imx53/kp_id_rev.h
new file mode 100644
index 000000000..aa6417392
--- /dev/null
+++ b/roms/u-boot/board/k+p/kp_imx53/kp_id_rev.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Based on code developed by:
+ *
+ * Copyright (C) 2012 TQ-Systems GmbH
+ * Daniel Gericke <daniel.gericke@tqs.de>
+ */
+
+#ifndef __KP_ID_REV_H_
+#define __KP_ID_REV_H_
+
+struct id_eeprom {
+	u8 hrcw_primary[0x20];
+	u8 mac[6];              /* 0x20 ... 0x25 */
+	u8 rsv1[10];
+	u8 serial[8];           /* 0x30 ... 0x37 */
+	u8 rsv2[8];
+	u8 id[0x40];            /* 0x40 ... 0x7f */
+} __packed;
+
+void show_eeprom(void);
+int read_eeprom(void);
+int read_board_id(void);
+#endif /* __KP_ID_REV_H_ */
diff --git a/roms/u-boot/board/k+p/kp_imx53/kp_imx53.c b/roms/u-boot/board/k+p/kp_imx53/kp_imx53.c
new file mode 100644
index 000000000..cc8118b4a
--- /dev/null
+++ b/roms/u-boot/board/k+p/kp_imx53/kp_imx53.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <asm/gpio.h>
+#include <env.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <bootstage.h>
+#include "kp_id_rev.h"
+
+#define BOOSTER_OFF IMX_GPIO_NR(2, 23)
+#define LCD_BACKLIGHT IMX_GPIO_NR(1, 1)
+#define KEY1 IMX_GPIO_NR(2, 26)
+#define LED_RED IMX_GPIO_NR(3, 28)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	u32 size;
+
+	size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	gd->ram_size = size;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+static int power_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("mc34708@8", &dev);
+	if (ret) {
+		printf("%s: mc34708 not found !\n", __func__);
+		return ret;
+	}
+
+	/* Set VDDGP to 1.110V for 800 MHz on SW1 */
+	pmic_clrsetbits(dev, REG_SW_0, SWx_VOLT_MASK_MC34708,
+			SWx_1_110V_MC34708);
+
+	/* Set VCC as 1.30V on SW2 */
+	pmic_clrsetbits(dev, REG_SW_1, SWx_VOLT_MASK_MC34708,
+			SWx_1_300V_MC34708);
+
+	/* Set global reset timer to 4s */
+	pmic_clrsetbits(dev, REG_POWER_CTL2, TIMER_MASK_MC34708,
+			TIMER_4S_MC34708);
+
+	return ret;
+}
+
+static void setup_clocks(void)
+{
+	int ret;
+	u32 ref_clk = MXC_HCLK;
+	/*
+	 * CPU clock set to 800MHz and DDR to 400MHz
+	 */
+	ret = mxc_set_clock(ref_clk, 800, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to 800MHZ failed\n");
+
+	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to 400MHz failed\n");
+}
+
+static void setup_ups(void)
+{
+	gpio_request(BOOSTER_OFF, "BOOSTER_OFF");
+	gpio_direction_output(BOOSTER_OFF, 0);
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+void board_disable_display(void)
+{
+	gpio_request(LCD_BACKLIGHT, "LCD_BACKLIGHT");
+	gpio_direction_output(LCD_BACKLIGHT, 0);
+}
+
+void board_misc_setup(void)
+{
+	gpio_request(KEY1, "KEY1_GPIO");
+	gpio_direction_input(KEY1);
+
+	if (gpio_get_value(KEY1))
+		env_set("key1", "off");
+	else
+		env_set("key1", "on");
+}
+
+int board_late_init(void)
+{
+	int ret = 0;
+
+	board_disable_display();
+	setup_ups();
+
+	if (!power_init())
+		setup_clocks();
+
+	ret = read_eeprom();
+	if (ret)
+		printf("Error %d reading EEPROM content!\n", ret);
+
+	show_eeprom();
+	read_board_id();
+
+	board_misc_setup();
+
+	return ret;
+}
+
+#define GPIO_DR 0x0
+#define GPIO_GDIR 0x4
+#define GPIO_ALT1 0x1
+#define GPIO5_BASE 0x53FDC000
+#define IOMUXC_EIM_WAIT 0x53FA81E4
+/* Green LED: GPIO5_0 */
+#define GPIO_GREEN BIT(0)
+
+void show_boot_progress(int status)
+{
+	/*
+	 * This BOOTSTAGE_ID is called at very early stage of execution. DM gpio
+	 * is not yet initialized.
+	 */
+	if (status == BOOTSTAGE_ID_START_UBOOT_F) {
+		/*
+		 * After ROM execution the EIM_WAIT PAD is set as ALT0
+		 * (according to RM it shall be ALT1 after reset). To use it as
+		 * GPIO we need to set it to ALT1.
+		 */
+		setbits_le32(((uint32_t *)(IOMUXC_EIM_WAIT)), GPIO_ALT1);
+
+		/* Configure green LED GPIO pin direction */
+		setbits_le32(((uint32_t *)(GPIO5_BASE + GPIO_GDIR)),
+			     GPIO_GREEN);
+		/* Turn on green LED */
+		setbits_le32(((uint32_t *)(GPIO5_BASE + GPIO_DR)), GPIO_GREEN);
+	}
+
+	/*
+	 * This BOOTSTAGE_ID is called just before handling execution to kernel
+	 * - i.e. gpio subsystem is already initialized
+	 */
+	if (status == BOOTSTAGE_ID_BOOTM_HANDOFF) {
+		/*
+		 * Off green LED - the same approach - i.e. non dm gpio
+		 * (*bits_le32) is used as in the very early stage.
+		 */
+		clrbits_le32(((uint32_t *)(GPIO5_BASE + GPIO_DR)),
+			     GPIO_GREEN);
+
+		/*
+		 * On red LED
+		 */
+		gpio_request(LED_RED, "LED_RED_ERROR");
+		gpio_direction_output(LED_RED, 1);
+	}
+}
diff --git a/roms/u-boot/board/k+p/kp_imx6q_tpc/Kconfig b/roms/u-boot/board/k+p/kp_imx6q_tpc/Kconfig
new file mode 100644
index 000000000..62e34978e
--- /dev/null
+++ b/roms/u-boot/board/k+p/kp_imx6q_tpc/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KP_IMX6Q_TPC
+
+config SYS_BOARD
+	default "kp_imx6q_tpc"
+
+config SYS_VENDOR
+	default "k+p"
+
+config SYS_CONFIG_NAME
+	default "kp_imx6q_tpc"
+
+endif
diff --git a/roms/u-boot/board/k+p/kp_imx6q_tpc/MAINTAINERS b/roms/u-boot/board/k+p/kp_imx6q_tpc/MAINTAINERS
new file mode 100644
index 000000000..6c4c8dd28
--- /dev/null
+++ b/roms/u-boot/board/k+p/kp_imx6q_tpc/MAINTAINERS
@@ -0,0 +1,6 @@
+KP_IMX6Q_TPC BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/k+p/kp_imx6q_tpc/
+F:	include/configs/kp_imx6q_tpc.h
+F:	configs/kp_imx6q_tpc_defconfig
diff --git a/roms/u-boot/board/k+p/kp_imx6q_tpc/Makefile b/roms/u-boot/board/k+p/kp_imx6q_tpc/Makefile
new file mode 100644
index 000000000..6551b2bfa
--- /dev/null
+++ b/roms/u-boot/board/k+p/kp_imx6q_tpc/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= kp_imx6q_tpc_spl.o
+else
+obj-y	:= kp_imx6q_tpc.o
+endif
diff --git a/roms/u-boot/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c b/roms/u-boot/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
new file mode 100644
index 000000000..110496d99
--- /dev/null
+++ b/roms/u-boot/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K+P iMX6Q KP_IMX6Q_TPC board configuration
+ *
+ * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <env.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <led.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec_clock(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* set gpr1[21] to select anatop clock */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK,
+			IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
+}
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8031 output a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8031_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+static void setup_usb(void)
+{
+	/*
+	 * Set daisy chain for otg_pin_id on MX6Q.
+	 * For MX6DL, this bit is reserved.
+	 */
+	imx_iomux_set_gpr_register(1, 13, 1, 0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_USB_EHCI_MX6
+	setup_usb();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec_clock();
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* Enable eim_slow clocks */
+	setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	env_set("boardname", "kp-tpc");
+	env_set("boardsoc", "imx6q");
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n");
+	return 0;
+}
diff --git a/roms/u-boot/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/roms/u-boot/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
new file mode 100644
index 000000000..103c4531a
--- /dev/null
+++ b/roms/u-boot/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K+P iMX6Q KP_IMX6Q_TPC board configuration
+ *
+ * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <spl.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+/* DDR3 */
+static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdclk_1 = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_reset = 0x00000030,
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = 0x00000030,
+	.dram_sdodt1 = 0x00000030,
+
+	.dram_sdqs0 = 0x00000018,
+	.dram_sdqs1 = 0x00000018,
+	.dram_sdqs2 = 0x00000018,
+	.dram_sdqs3 = 0x00000018,
+	.dram_sdqs4 = 0x00000018,
+	.dram_sdqs5 = 0x00000018,
+	.dram_sdqs6 = 0x00000018,
+	.dram_sdqs7 = 0x00000018,
+
+	.dram_dqm0 = 0x00000018,
+	.dram_dqm1 = 0x00000018,
+	.dram_dqm2 = 0x00000018,
+	.dram_dqm3 = 0x00000018,
+	.dram_dqm4 = 0x00000018,
+	.dram_dqm5 = 0x00000018,
+	.dram_dqm6 = 0x00000018,
+	.dram_dqm7 = 0x00000018,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = 0x00000018,
+	.grp_b1ds = 0x00000018,
+	.grp_b2ds = 0x00000018,
+	.grp_b3ds = 0x00000018,
+	.grp_b4ds = 0x00000018,
+	.grp_b5ds = 0x00000018,
+	.grp_b6ds = 0x00000018,
+	.grp_b7ds = 0x00000018,
+};
+
+static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x001F001F,
+	.p0_mpwldectrl1 = 0x001F001F,
+	.p1_mpwldectrl0 = 0x001F001F,
+	.p1_mpwldectrl1 = 0x001F001F,
+	.p0_mpdgctrl0 = 0x43270338,
+	.p0_mpdgctrl1 = 0x03200314,
+	.p1_mpdgctrl0 = 0x431A032F,
+	.p1_mpdgctrl1 = 0x03200263,
+	.p0_mprddlctl = 0x4B434748,
+	.p1_mprddlctl = 0x4445404C,
+	.p0_mpwrdlctl = 0x38444542,
+	.p1_mpwrdlctl = 0x4935493A,
+};
+
+/* MT41K256M16 (4Gb density) */
+static const struct mx6_ddr3_cfg mt41k256m16 = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+#ifdef CONFIG_MX6_DDRCAL
+static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+	struct mx6_mmdc_calibration calibration = {0};
+
+	mmdc_read_calibration(sysinfo, &calibration);
+
+	debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
+	debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
+	debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
+	debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
+	debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
+	debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
+	debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
+	debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
+	debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
+	debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
+	debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
+	debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
+}
+
+static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+	int ret;
+
+	/* Perform DDR DRAM calibration */
+	udelay(100);
+	ret = mmdc_do_write_level_calibration(sysinfo);
+	if (ret) {
+		printf("DDR: Write level calibration error [%d]\n", ret);
+		return;
+	}
+
+	ret = mmdc_do_dqs_calibration(sysinfo);
+	if (ret) {
+		printf("DDR: DQS calibration error [%d]\n", ret);
+		return;
+	}
+
+	spl_dram_print_cal(sysinfo);
+}
+#endif /* CONFIG_MX6_DDRCAL */
+
+static void spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize = 2,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density = 32, /* 32Gb per CS */
+		/* single chip select */
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
+		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
+		.walat = 1,	/* Write additional latency */
+		.ralat = 5,	/* Read additional latency */
+		.mif3_mode = 3,	/* Command prediction working mode */
+		.bi_on = 1,	/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
+		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
+	};
+
+	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
+
+#ifdef CONFIG_MX6_DDRCAL
+	spl_dram_perform_cal(&sysinfo);
+#endif
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	u32 boot_device = spl_boot_device();
+	u32 reg = imx6_src_get_boot_mode();
+
+	reg = (reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
+
+	debug("%s: boot device: 0x%x (0x4 SD, 0x6 eMMC)\n", __func__, reg);
+	if (boot_device == BOOT_DEVICE_MMC1)
+		if (reg == IMX6_BMODE_MMC || reg == IMX6_BMODE_EMMC)
+			boot_device = BOOT_DEVICE_MMC2;
+
+	spl_boot_list[0] = boot_device;
+	/*
+	 * Below boot device is a 'fallback' - it shall always be possible to
+	 * boot from SD card
+	 */
+	spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* Early - pre reloc - driver model setup */
+	spl_early_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+}
diff --git a/roms/u-boot/board/keymile/Kconfig b/roms/u-boot/board/keymile/Kconfig
new file mode 100644
index 000000000..3a6c63b77
--- /dev/null
+++ b/roms/u-boot/board/keymile/Kconfig
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019, Pascal Linder <pascal.linder@edu.hefr.ch>
+
+config VENDOR_KM
+	bool
+	help
+	  Selected by any KM board to have additional configurations.
+
+if VENDOR_KM
+
+menu "KM Board Setup"
+
+config KM_PNVRAM
+	hex "Pseudo RAM"
+	default 0x80000
+	depends on !ARCH_SOCFPGA
+	help
+	  Start address of the pseudo non-volatile RAM for application.
+
+config KM_PHRAM
+	hex "Physical RAM"
+	default 0x17F000 if ARM && !ARCH_LS1021A
+	default 0x100000 if PPC || ARCH_LS1021A
+	depends on !ARCH_SOCFPGA
+	help
+	  Start address of the physical RAM, which is the mounted /var folder.
+
+config KM_RESERVED_PRAM
+	hex "Reserved RAM"
+	default 0x801000 if ARCH_KIRKWOOD
+	default 0x0 if MPC83xx
+	default 0x1000 if MPC85xx || ARCH_LS1021A
+	depends on !ARCH_SOCFPGA
+	help
+	  Reserved physical RAM area at the end of memory for special purposes.
+
+config KM_CRAMFS_ADDR
+	hex "CRAMFS Address"
+	default 0x83000000 if ARCH_LS1021A
+	default 0x3000000
+	depends on !ARCH_SOCFPGA
+	help
+	  Start address of the CRAMFS containing the Linux kernel.
+
+config KM_KERNEL_ADDR
+	hex "Kernel Load Address"
+	default 0x82000000 if ARCH_LS1021A
+	default 0x2000000
+	help
+	  Address where to load Linux kernel in RAM.
+
+config KM_FDT_ADDR
+	hex "FDT Load Address"
+	default 0x82FC0000 if ARCH_LS1021A
+	default 0x2FC0000
+	help
+	  Address where to load flattened device tree in RAM.
+
+config SYS_PAX_BASE
+	hex "PAX IFC Base Address"
+	default 0x78000000
+	depends on ARCH_LS1021A
+	help
+	  IFC Base Address for PAXx FPGA.
+
+config SYS_CLIPS_BASE
+	hex "CLIPS IFC Base Address"
+	default 0x78000000
+	depends on ARCH_LS1021A
+	help
+	  IFC Base Address for CLIPS FPGA.
+
+config KM_CONSOLE_TTY
+	string "KM Console"
+	default "ttyS0"
+	help
+	  TTY console to use on board.
+
+config KM_DEF_NETDEV
+	string "Default Netdevice"
+	default "eth0"
+	help
+	  Default netdevice for debug interface
+
+config KM_COMMON_ETH_INIT
+	bool "Common Ethernet Initialization"
+	default y if ARCH_KIRKWOOD || MPC83xx
+	default n if MPC85xx || ARCH_SOCFPGA || ARCH_LS1021A
+	help
+	  Use the Ethernet initialization implemented in common code that
+	  detects if a Piggy board is present.
+
+config PIGGY_MAC_ADDRESS_OFFSET
+	int "Piggy Address Offset"
+	default 0
+	help
+	  MAC address offset for the Piggy board.
+
+config KM_MVEXTSW_ADDR
+	hex "Marvell Switch Address"
+	depends on MV88E6352_SWITCH
+	default 0x10
+	help
+	  Address of external Marvell switch.
+
+config KM_IVM_BUS
+	int "IVM I2C Bus"
+	default 0 if ARCH_SOCFPGA
+	default 1 if ARCH_KIRKWOOD || MPC85xx || ARCH_LS1021A
+	default 2 if MPC83xx
+	help
+	  Identifier number of I2C bus, where the inventory EEPROM is connected to.
+
+config SYS_IVM_EEPROM_ADR
+	hex "IVM I2C Address"
+	default 0x50
+	help
+	  I2C address of the EEPROM containing the inventory.
+
+config SYS_IVM_EEPROM_MAX_LEN
+	hex "IVM Length"
+	default 0x400
+	help
+	  Maximum length of inventory in EEPROM.
+
+config SYS_IVM_EEPROM_PAGE_LEN
+	hex "IVM Page Size"
+	default 0x100
+	help
+	  Page size of inventory in EEPROM.
+
+source "board/keymile/km83xx/Kconfig"
+source "board/keymile/kmcent2/Kconfig"
+source "board/keymile/kmp204x/Kconfig"
+source "board/keymile/km_arm/Kconfig"
+source "board/keymile/pg-wcom-ls102xa/Kconfig"
+
+endmenu
+
+endif
diff --git a/roms/u-boot/board/keymile/common/common.c b/roms/u-boot/board/keymile/common/common.c
new file mode 100644
index 000000000..016806a2a
--- /dev/null
+++ b/roms/u-boot/board/keymile/common/common.c
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2011
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ */
+
+#include <common.h>
+#include <env.h>
+#include <ioports.h>
+#include <command.h>
+#include <malloc.h>
+#include <cli_hush.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <linux/ctype.h>
+#include <linux/delay.h>
+
+#if defined(CONFIG_POST)
+#include "post.h"
+#endif
+#include "common.h"
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Set Keymile specific environment variables
+ * Currently only some memory layout variables are calculated here
+ * ... ------------------------------------------------
+ * ... |@rootfsaddr |@pnvramaddr |@varaddr |@reserved |@END_OF_RAM
+ * ... |<------------------- pram ------------------->|
+ * ... ------------------------------------------------
+ * @END_OF_RAM: denotes the RAM size
+ * @pnvramaddr: Startadress of pseudo non volatile RAM in hex
+ * @pram      : preserved ram size in k
+ * @varaddr   : startadress for /var mounted into RAM
+ */
+int set_km_env(void)
+{
+	unsigned int pnvramaddr;
+	unsigned int pram;
+	unsigned int varaddr;
+	unsigned int kernelmem;
+	unsigned long rootfssize = 0;
+	char envval[16];
+	char *p;
+
+	pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
+		CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM;
+	sprintf(envval, "0x%x", pnvramaddr);
+	env_set("pnvramaddr", envval);
+
+	/* try to read rootfssize (ram image) from environment */
+	p = env_get("rootfssize");
+	if (p)
+		strict_strtoul(p, 16, &rootfssize);
+	pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM +
+		CONFIG_KM_PNVRAM) / 0x400;
+	env_set_ulong("pram", pram);
+
+	varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
+		CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
+	env_set_hex("varaddr", varaddr);
+	sprintf(envval, "0x%x", varaddr);
+	env_set("varaddr", envval);
+
+	kernelmem = gd->ram_size - 0x400 * pram;
+	sprintf(envval, "0x%x", kernelmem);
+	env_set("kernelmem", envval);
+
+	return 0;
+}
+
+#if defined(CONFIG_SYS_I2C_INIT_BOARD)
+static void i2c_write_start_seq(void)
+{
+	set_sda(1);
+	udelay(DELAY_HALF_PERIOD);
+	set_scl(1);
+	udelay(DELAY_HALF_PERIOD);
+	set_sda(0);
+	udelay(DELAY_HALF_PERIOD);
+	set_scl(0);
+	udelay(DELAY_HALF_PERIOD);
+}
+
+/*
+ * I2C is a synchronous protocol and resets of the processor in the middle
+ * of an access can block the I2C Bus until a powerdown of the full unit is
+ * done. This function toggles the SCL until the SCL and SCA line are
+ * released, but max. 16 times, after this a I2C start-sequence is sent.
+ * This I2C Deblocking mechanism was developed by Keymile in association
+ * with Anatech and Atmel in 1998.
+ */
+int i2c_make_abort(void)
+{
+	int	scl_state = 0;
+	int	sda_state = 0;
+	int	i = 0;
+	int	ret = 0;
+
+	if (!get_sda()) {
+		ret = -1;
+		while (i < 16) {
+			i++;
+			set_scl(0);
+			udelay(DELAY_ABORT_SEQ);
+			set_scl(1);
+			udelay(DELAY_ABORT_SEQ);
+			scl_state = get_scl();
+			sda_state = get_sda();
+			if (scl_state && sda_state) {
+				ret = 0;
+				break;
+			}
+		}
+	}
+	if (ret == 0)
+		for (i = 0; i < 5; i++)
+			i2c_write_start_seq();
+
+	/* respect stop setup time */
+	udelay(DELAY_ABORT_SEQ);
+	set_scl(1);
+	udelay(DELAY_ABORT_SEQ);
+	set_sda(1);
+	get_sda();
+
+	return ret;
+}
+
+/**
+ * i2c_init_board - reset i2c bus. When the board is powercycled during a
+ * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
+ */
+void i2c_init_board(void)
+{
+	/* Now run the AbortSequence() */
+	i2c_make_abort();
+}
+#endif
+
+#if defined(CONFIG_KM_COMMON_ETH_INIT)
+int board_eth_init(struct bd_info *bis)
+{
+	if (ethernet_present())
+		return cpu_eth_init(bis);
+
+	return -1;
+}
+#endif
+
+/*
+ * do_setboardid command
+ * read out the board id and the hw key from the intventory EEPROM and set
+ * this values as environment variables.
+ */
+static int do_setboardid(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	unsigned char buf[32];
+	char *p;
+
+	p = get_local_var("IVM_BoardId");
+	if (!p) {
+		printf("can't get the IVM_Boardid\n");
+		return 1;
+	}
+	strcpy((char *)buf, p);
+	env_set("boardid", (char *)buf);
+	printf("set boardid=%s\n", buf);
+
+	p = get_local_var("IVM_HWKey");
+	if (!p) {
+		printf("can't get the IVM_HWKey\n");
+		return 1;
+	}
+	strcpy((char *)buf, p);
+	env_set("hwkey", (char *)buf);
+	printf("set hwkey=%s\n", buf);
+	printf("Execute manually saveenv for persistent storage.\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(km_setboardid, 1, 0, do_setboardid, "setboardid",
+	   "read out bid and hwkey from IVM and set in environment");
+
+/*
+ * command km_checkbidhwk
+ *	if "boardid" and "hwkey" are not already set in the environment, do:
+ *		if a "boardIdListHex" exists in the environment:
+ *			- read ivm data for boardid and hwkey
+ *			- compare each entry of the boardIdListHex with the
+ *				IVM data:
+ *			if match:
+ *				set environment variables boardid, boardId,
+ *				hwkey, hwKey to	the found values
+ *				both (boardid and boardId) are set because
+ *				they might be used differently in the
+ *				application and in the init scripts (?)
+ *	return 0 in case of match, 1 if not match or error
+ */
+static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int flag, int argc,
+			      char *const argv[])
+{
+	unsigned long ivmbid = 0, ivmhwkey = 0;
+	unsigned long envbid = 0, envhwkey = 0;
+	char *p;
+	int verbose = argc > 1 && *argv[1] == 'v';
+	int rc = 0;
+
+	/*
+	 * first read out the real inventory values, these values are
+	 * already stored in the local hush variables
+	 */
+	p = get_local_var("IVM_BoardId");
+	if (!p) {
+		printf("can't get the IVM_Boardid\n");
+		return 1;
+	}
+	rc = strict_strtoul(p, 16, &ivmbid);
+
+	p = get_local_var("IVM_HWKey");
+	if (!p) {
+		printf("can't get the IVM_HWKey\n");
+		return 1;
+	}
+	rc = strict_strtoul(p, 16, &ivmhwkey);
+
+	if (!ivmbid || !ivmhwkey) {
+		printf("Error: IVM_BoardId and/or IVM_HWKey not set!\n");
+		return rc;
+	}
+
+	/* now try to read values from environment if available */
+	p = env_get("boardid");
+	if (p)
+		rc = strict_strtoul(p, 16, &envbid);
+	p = env_get("hwkey");
+	if (p)
+		rc = strict_strtoul(p, 16, &envhwkey);
+	if (rc != 0) {
+		printf("strict_strtoul returns error: %d", rc);
+		return rc;
+	}
+
+	if (!envbid || !envhwkey) {
+		/*
+		 * BoardId/HWkey not available in the environment, so try the
+		 * environment variable for BoardId/HWkey list
+		 */
+		char *bidhwklist = env_get("boardIdListHex");
+
+		if (bidhwklist) {
+			int found = 0;
+			char *rest = bidhwklist;
+			char *endp;
+
+			if (verbose) {
+				printf("IVM_BoardId: %ld, IVM_HWKey=%ld\n",
+				       ivmbid, ivmhwkey);
+				printf("boardIdHwKeyList: %s\n", bidhwklist);
+			}
+			while (!found) {
+				/* loop over each bid/hwkey pair in the list */
+				unsigned long bid   = 0;
+				unsigned long hwkey = 0;
+
+				while (*rest && !isxdigit(*rest))
+					rest++;
+				/*
+				 * use simple_strtoul because we need &end and
+				 * we know we got non numeric char at the end
+				 */
+				bid = simple_strtoul(rest, &endp, 16);
+				/* BoardId and HWkey are separated with a "_" */
+				if (*endp == '_') {
+					rest  = endp + 1;
+					/*
+					 * use simple_strtoul because we need
+					 * &end
+					 */
+					hwkey = simple_strtoul(rest, &endp, 16);
+					rest  = endp;
+					while (*rest && !isxdigit(*rest))
+						rest++;
+				}
+				if (!bid || !hwkey) {
+					/* end of list */
+					break;
+				}
+				if (verbose) {
+					printf("trying bid=0x%lX, hwkey=%ld\n",
+					       bid, hwkey);
+				}
+				/*
+				 * Compare the values of the found entry in the
+				 * list with the valid values which are stored
+				 * in the inventory eeprom. If they are equal
+				 * set the values in environment variables.
+				 */
+				if (bid == ivmbid && hwkey == ivmhwkey) {
+					found = 1;
+					envbid   = bid;
+					envhwkey = hwkey;
+					env_set_hex("boardid", bid);
+					env_set_hex("hwkey", hwkey);
+				}
+			} /* end while( ! found ) */
+		}
+	}
+
+	/* compare now the values */
+	if (ivmbid == envbid && ivmhwkey == envhwkey) {
+		printf("boardid=0x%3lX, hwkey=%ld\n", envbid, envhwkey);
+		rc = 0; /* match */
+	} else {
+		printf("Error: env boardid=0x%3lX, hwkey=%ld\n", envbid,
+		       envhwkey);
+		printf("       IVM bId=0x%3lX, hwKey=%ld\n", ivmbid, ivmhwkey);
+		rc = 1; /* don't match */
+	}
+	return rc;
+}
+
+U_BOOT_CMD(km_checkbidhwk, 2, 0, do_checkboardidhwk,
+	   "check boardid and hwkey",
+	   "[v]\n  - check environment parameter \"boardIdListHex\" against stored boardid and hwkey from the IVM\n    v: verbose output"
+);
+
+/*
+ * command km_checktestboot
+ *  if the testpin of the board is asserted, return 1
+ *  *	else return 0
+ */
+static int do_checktestboot(struct cmd_tbl *cmdtp, int flag, int argc,
+			    char *const argv[])
+{
+	int testpin = 0;
+	char *s = NULL;
+	int testboot = 0;
+	int verbose = argc > 1 && *argv[1] == 'v';
+
+#if defined(CONFIG_POST)
+	testpin = post_hotkeys_pressed();
+#endif
+
+	s = env_get("test_bank");
+	/* when test_bank is not set, act as if testpin is not asserted */
+	testboot = (testpin != 0) && (s);
+	if (verbose) {
+		printf("testpin   = %d\n", testpin);
+		/* cppcheck-suppress nullPointer */
+		printf("test_bank = %s\n", s ? s : "not set");
+		printf("boot test app : %s\n", (testboot) ? "yes" : "no");
+	}
+	/* return 0 means: testboot, therefore we need the inversion */
+	return !testboot;
+}
+
+U_BOOT_CMD(km_checktestboot, 2, 0, do_checktestboot,
+	   "check if testpin is asserted",
+	   "[v]\n  v - verbose output"
+);
diff --git a/roms/u-boot/board/keymile/common/common.h b/roms/u-boot/board/keymile/common/common.h
new file mode 100644
index 000000000..15a3c3797
--- /dev/null
+++ b/roms/u-boot/board/keymile/common/common.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#ifndef __KEYMILE_COMMON_H
+#define __KEYMILE_COMMON_H
+
+#define WRG_RESET	0x80
+#define H_OPORTS_14	0x40
+#define WRG_LED		0x02
+#define WRL_BOOT	0x01
+
+#define OPRTL_XBUFENA	0x20
+
+#define H_OPORTS_SCC4_ENA	0x10
+#define H_OPORTS_SCC4_FD_ENA	0x04
+#define H_OPORTS_FCC1_PW_DWN	0x01
+
+#define PIGGY_PRESENT	0x80
+
+struct km_bec_fpga {
+	unsigned char	id;
+	unsigned char	rev;
+	unsigned char	oprth;
+	unsigned char	oprtl;
+	unsigned char	res1[3];
+	unsigned char	bprth;
+	unsigned char	bprtl;
+	unsigned char	gprt3;
+	unsigned char	gprt2;
+	unsigned char	gprt1;
+	unsigned char	gprt0;
+	unsigned char	res2[2];
+	unsigned char	prst;
+	unsigned char	res3[0xfff0];
+	unsigned char	pgy_id;
+	unsigned char	pgy_rev;
+	unsigned char	pgy_outputs;
+	unsigned char	pgy_eth;
+};
+
+#define BFTICU_DIPSWITCH_MASK   0x0f
+
+/*
+ * BFTICU FPGA iomap
+ * BFTICU is used on mgcoge and mgocge3ne
+ */
+struct bfticu_iomap {
+	u8	xi_ena;		/* General defect enable */
+	u8	pack1[3];
+	u8	en_csn;
+	u8	pack2;
+	u8	safe_mem;
+	u8	pack3;
+	u8	id;
+	u8	pack4;
+	u8	rev;
+	u8	build;
+	u8	p_frc;
+	u8	p_msk;
+	u8	pack5[2];
+	u8	xg_int;
+	u8	pack6[15];
+	u8	s_conf;
+	u8	pack7;
+	u8	dmx_conf12;
+	u8	pack8;
+	u8	s_clkslv;
+	u8	pack9[11];
+	u8	d_conf;
+	u8	d_mask_ca;
+	u8	d_pll_del;
+	u8	pack10[16];
+	u8	t_conf_ca;
+	u8	t_mask_ca;
+	u8	pack11[13];
+	u8	m_def0;
+	u8	m_def1;
+	u8	m_def2;
+	u8	m_def3;
+	u8	m_def4;
+	u8	m_def5;
+	u8	m_def_trap0;
+	u8	m_def_trap1;
+	u8	m_def_trap2;
+	u8	m_def_trap3;
+	u8	m_def_trap4;
+	u8	m_def_trap5;
+	u8	m_mask_def0;
+	u8	m_mask_def1;
+	u8	m_mask_def2;
+	u8	m_mask_def3;
+	u8	m_mask_def4;
+	u8	m_mask_def5;
+	u8	m_def_mask0;
+	u8	m_def_mask1;
+	u8	m_def_mask2;
+	u8	m_def_mask3;
+	u8	m_def_mask4;
+	u8	m_def_mask5;
+	u8	m_def_pri;
+	u8	pack12[11];
+	u8	hw_status;
+	u8	pack13;
+	u8	hw_control1;
+	u8	hw_control2;
+	u8	hw_control3;
+	u8	pack14[7];
+	u8	led_on;		/* Leds */
+	u8	pack15;
+	u8	sfp_control;	/* SFP modules */
+	u8	pack16;
+	u8	alarm_control;	/* Alarm output */
+	u8	pack17;
+	u8	icps;		/* ICN clock pulse shaping */
+	u8	mswitch;	/* Read mode switch */
+	u8	pack18[6];
+	u8	pb_dbug;
+};
+
+int ethernet_present(void);
+int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset);
+int ivm_analyze_eeprom(unsigned char *buf, int len);
+
+int trigger_fpga_config(void);
+int wait_for_fpga_config(void);
+int fpga_reset(void);
+int toggle_eeprom_spi_bus(void);
+
+int get_testpin(void);
+
+int set_km_env(void);
+
+#define DELAY_ABORT_SEQ		62  /* @200kHz 9 clocks = 44us, 62us is ok */
+#define DELAY_HALF_PERIOD	(500 / (CONFIG_SYS_I2C_SPEED / 1000))
+
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+
+int i2c_soft_read_pin(void);
+int i2c_make_abort(void);
+#endif /* __KEYMILE_COMMON_H */
diff --git a/roms/u-boot/board/keymile/common/ivm.c b/roms/u-boot/board/keymile/common/ivm.c
new file mode 100644
index 000000000..14c70b9ad
--- /dev/null
+++ b/roms/u-boot/board/keymile/common/ivm.c
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ */
+
+#include <common.h>
+#include <cli_hush.h>
+#include <env.h>
+#include <i2c.h>
+#include "common.h"
+
+#define MAC_STR_SZ	20
+
+static int ivm_calc_crc(unsigned char *buf, int len)
+{
+	const unsigned short crc_tab[16] = {
+		0x0000, 0xCC01, 0xD801, 0x1400,
+		0xF001, 0x3C00, 0x2800, 0xE401,
+		0xA001, 0x6C00, 0x7800, 0xB401,
+		0x5000, 0x9C01, 0x8801, 0x4400};
+
+	unsigned short crc     = 0;   /* final result */
+	unsigned short r1      = 0;   /* temp */
+	unsigned char  byte    = 0;   /* input buffer */
+	int	i;
+
+	/* calculate CRC from array data */
+	for (i = 0; i < len; i++) {
+		byte = buf[i];
+
+		/* lower 4 bits */
+		r1 = crc_tab[crc & 0xF];
+		crc = ((crc) >> 4) & 0x0FFF;
+		crc = crc ^ r1 ^ crc_tab[byte & 0xF];
+
+		/* upper 4 bits */
+		r1 = crc_tab[crc & 0xF];
+		crc = (crc >> 4) & 0x0FFF;
+		crc = crc ^ r1 ^ crc_tab[(byte >> 4) & 0xF];
+	}
+	return crc;
+}
+
+static int ivm_set_value(char *name, char *value)
+{
+	char tempbuf[256];
+
+	if (value) {
+		sprintf(tempbuf, "%s=%s", name, value);
+		return set_local_var(tempbuf, 0);
+	}
+	unset_local_var(name);
+	return 0;
+}
+
+static int ivm_get_value(unsigned char *buf, int len, char *name, int off,
+			 int check)
+{
+	unsigned short	val;
+	unsigned char	valbuf[30];
+
+	if (buf[off + 0] != buf[off + 2] &&
+	    buf[off + 2] != buf[off + 4]) {
+		printf("%s Error corrupted %s\n", __func__, name);
+		val = -1;
+	} else {
+		val = buf[off + 0] + (buf[off + 1] << 8);
+		if (val == 0 && check == 1)
+			val = -1;
+	}
+	sprintf((char *)valbuf, "%x", val);
+	ivm_set_value(name, (char *)valbuf);
+	return val;
+}
+
+#define INV_BLOCKSIZE		0x100
+#define INV_DATAADDRESS		0x21
+#define INVENTORYDATASIZE	(INV_BLOCKSIZE - INV_DATAADDRESS - 3)
+
+#define IVM_POS_SHORT_TEXT		0
+#define IVM_POS_MANU_ID			1
+#define IVM_POS_MANU_SERIAL		2
+#define IVM_POS_PART_NUMBER		3
+#define IVM_POS_BUILD_STATE		4
+#define IVM_POS_SUPPLIER_PART_NUMBER	5
+#define IVM_POS_DELIVERY_DATE		6
+#define IVM_POS_SUPPLIER_BUILD_STATE	7
+#define IVM_POS_CUSTOMER_ID		8
+#define IVM_POS_CUSTOMER_PROD_ID	9
+#define IVM_POS_HISTORY			10
+#define IVM_POS_SYMBOL_ONLY		11
+
+static char convert_char(char c)
+{
+	return (c < ' ' || c > '~') ? '.' : c;
+}
+
+static int ivm_findinventorystring(int type,
+				   unsigned char *const string,
+				   unsigned long maxlen,
+				   unsigned char *buf)
+{
+	int xcode = 0;
+	unsigned long cr = 0;
+	unsigned long addr = INV_DATAADDRESS;
+	unsigned long size = 0;
+	unsigned long nr = type;
+	int stop = 0;	/* stop on semicolon */
+
+	memset(string, '\0', maxlen);
+	switch (type) {
+	case IVM_POS_SYMBOL_ONLY:
+		nr = 0;
+		stop = 1;
+	break;
+	default:
+		nr = type;
+		stop = 0;
+	}
+
+	/* Look for the requested number of CR. */
+	while ((cr != nr) && (addr < INVENTORYDATASIZE)) {
+		if (buf[addr] == '\r')
+			cr++;
+		addr++;
+	}
+
+	/*
+	 * the expected number of CR was found until the end of the IVM
+	 *  content --> fill string
+	 */
+	if (addr < INVENTORYDATASIZE) {
+		/* Copy the IVM string in the corresponding string */
+		for (; (buf[addr] != '\r')		&&
+		     ((buf[addr] != ';') ||  (!stop))	&&
+		     (size < (maxlen - 1)		&&
+		     (addr < INVENTORYDATASIZE)); addr++) {
+			size += sprintf((char *)string + size, "%c",
+					convert_char (buf[addr]));
+		}
+
+		/*
+		 * copy phase is done: check if everything is ok. If not,
+		 * the inventory data is most probably corrupted: tell
+		 * the world there is a problem!
+		 */
+		if (addr == INVENTORYDATASIZE) {
+			xcode = -1;
+			printf("Error end of string not found\n");
+		} else if ((size > (maxlen - 1)) &&
+			   (buf[addr] != '\r')) {
+			xcode = -1;
+			printf("string too long till next CR\n");
+		}
+	} else {
+		/*
+		 * some CR are missing...
+		 * the inventory data is most probably corrupted
+		 */
+		xcode = -1;
+		printf("not enough cr found\n");
+	}
+	return xcode;
+}
+
+#define GET_STRING(name, which, len) \
+	if (ivm_findinventorystring(which, valbuf, len, buf) == 0) { \
+		ivm_set_value(name, (char *)valbuf); \
+	}
+
+static int ivm_check_crc(unsigned char *buf, int block)
+{
+	unsigned long	crc;
+	unsigned long	crceeprom;
+
+	crc = ivm_calc_crc(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2);
+	crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] +
+			buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256);
+	if (crc != crceeprom) {
+		if (block == 0)
+			printf("Error CRC Block: %d EEprom: calculated: %lx EEprom: %lx\n",
+			       block, crc, crceeprom);
+		return -1;
+	}
+	return 0;
+}
+
+/* take care of the possible MAC address offset and the IVM content offset */
+static int process_mac(unsigned char *valbuf, unsigned char *buf,
+		       int offset, bool unique)
+{
+	unsigned char mac[6];
+	unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6];
+
+	/* use an intermediate buffer, to not change IVM content
+	 * MAC address is at offset 1
+	 */
+	memcpy(mac, buf + 1, 6);
+
+	/* MAC address can be set to locally administred, this is only allowed
+	 * for interfaces which have now connection to the outside. For these
+	 * addresses we need to set the second bit in the first byte.
+	 */
+	if (!unique)
+		mac[0] |= 0x2;
+
+	if (offset) {
+		val += offset;
+		mac[3] = (val >> 16) & 0xff;
+		mac[4] = (val >> 8) & 0xff;
+		mac[5] = val & 0xff;
+	}
+
+	sprintf((char *)valbuf, "%pM", mac);
+	return 0;
+}
+
+static int ivm_analyze_block2(unsigned char *buf, int len)
+{
+	unsigned char	valbuf[MAC_STR_SZ];
+	unsigned long	count;
+
+	/* IVM_MAC Address begins at offset 1 */
+	sprintf((char *)valbuf, "%pM", buf + 1);
+	ivm_set_value("IVM_MacAddress", (char *)valbuf);
+	/* IVM_MacCount */
+	count = (buf[10] << 24) +
+		   (buf[11] << 16) +
+		   (buf[12] << 8)  +
+		    buf[13];
+	if (count == 0xffffffff)
+		count = 1;
+	sprintf((char *)valbuf, "%lx", count);
+	ivm_set_value("IVM_MacCount", (char *)valbuf);
+	return 0;
+}
+
+int ivm_analyze_eeprom(unsigned char *buf, int len)
+{
+	unsigned short	val;
+	unsigned char	valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
+	unsigned char	*tmp;
+
+	if (ivm_check_crc(buf, 0) != 0)
+		return -1;
+
+	ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
+		      "IVM_BoardId", 0, 1);
+	val = ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
+			    "IVM_HWKey", 6, 1);
+	if (val != 0xffff) {
+		sprintf((char *)valbuf, "%x", ((val / 100) % 10));
+		ivm_set_value("IVM_HWVariant", (char *)valbuf);
+		sprintf((char *)valbuf, "%x", (val % 100));
+		ivm_set_value("IVM_HWVersion", (char *)valbuf);
+	}
+	ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
+		      "IVM_Functions", 12, 0);
+
+	GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8)
+	GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64)
+	tmp = (unsigned char *)env_get("IVM_DeviceName");
+	if (tmp) {
+		int	len = strlen((char *)tmp);
+		int	i = 0;
+
+		while (i < len) {
+			if (tmp[i] == ';') {
+				ivm_set_value("IVM_ShortText",
+					      (char *)&tmp[i + 1]);
+				break;
+			}
+			i++;
+		}
+		if (i >= len)
+			ivm_set_value("IVM_ShortText", NULL);
+	} else {
+		ivm_set_value("IVM_ShortText", NULL);
+	}
+	GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32)
+	GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20)
+	GET_STRING("IVM_ManufacturerPartNumber", IVM_POS_PART_NUMBER, 32)
+	GET_STRING("IVM_ManufacturerBuildState", IVM_POS_BUILD_STATE, 32)
+	GET_STRING("IVM_SupplierPartNumber", IVM_POS_SUPPLIER_PART_NUMBER, 32)
+	GET_STRING("IVM_DelieveryDate", IVM_POS_DELIVERY_DATE, 32)
+	GET_STRING("IVM_SupplierBuildState", IVM_POS_SUPPLIER_BUILD_STATE, 32)
+	GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32)
+	GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32)
+
+	if (ivm_check_crc(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0)
+		return 0;
+	ivm_analyze_block2(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2],
+			   CONFIG_SYS_IVM_EEPROM_PAGE_LEN);
+
+	return 0;
+}
+
+static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset)
+{
+	unsigned char	*page2;
+	unsigned char	valbuf[MAC_STR_SZ];
+
+	/* do we have the page 2 filled ? if not return */
+	if (ivm_check_crc(buf, 2))
+		return 0;
+	page2 = &buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2];
+
+	if (IS_ENABLED(CONFIG_KMTEGR1)) {
+		/* KMTEGR1 has a special setup. eth0 has no connection to the
+		 * outside and gets an locally administred MAC address, eth1 is
+		 * the debug interface and gets the official MAC address from
+		 * the IVM
+		 */
+		process_mac(valbuf, page2, mac_address_offset, false);
+		env_set((char *)"ethaddr", (char *)valbuf);
+		process_mac(valbuf, page2, mac_address_offset, true);
+		env_set((char *)"eth1addr", (char *)valbuf);
+	} else if (IS_ENABLED(CONFIG_ARCH_LS1021A)) {
+		/* LS102xA has 1xRGMII for debug connection and
+		 * 2xSGMII for back-plane mgmt connection
+		 */
+		process_mac(valbuf, page2, 1, true);
+		env_set((char *)"ethaddr", (char *)valbuf);
+		process_mac(valbuf, page2, 2, true);
+		env_set((char *)"eth1addr", (char *)valbuf);
+		process_mac(valbuf, page2, mac_address_offset, true);
+		env_set((char *)"eth2addr", (char *)valbuf);
+	} else {
+		process_mac(valbuf, page2, mac_address_offset, true);
+		env_set((char *)"ethaddr", (char *)valbuf);
+	}
+	if (IS_ENABLED(CONFIG_TARGET_KMCENT2)) {
+		/* 3rd ethernet interface */
+		process_mac(valbuf, page2, 2, true);
+		env_set((char *)"eth4addr", (char *)valbuf);
+	}
+
+	return 0;
+}
+
+int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset)
+{
+	int ret;
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *eedev = NULL;
+
+	ret = i2c_get_chip_for_busnum(CONFIG_KM_IVM_BUS,
+				      CONFIG_SYS_I2C_EEPROM_ADDR, 1, &eedev);
+	if (ret) {
+		printf("failed to get device for EEPROM at address 0x%02x\n",
+		       CONFIG_SYS_I2C_EEPROM_ADDR);
+		return 1;
+	}
+
+	ret = dm_i2c_read(eedev, 0, buf, len);
+	if (ret != 0) {
+		printf("Error: Unable to read from I2C EEPROM at address %02X:%02X\n",
+		       CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		return 1;
+	}
+#else
+	i2c_set_bus_num(CONFIG_KM_IVM_BUS);
+	/* add deblocking here */
+	i2c_make_abort();
+
+	ret = i2c_read(CONFIG_SYS_IVM_EEPROM_ADR, 0, 1, buf, len);
+	if (ret != 0) {
+		printf("Error reading EEprom\n");
+		return -2;
+	}
+#endif
+	return ivm_populate_env(buf, len, mac_address_offset);
+}
diff --git a/roms/u-boot/board/keymile/common/qrio.c b/roms/u-boot/board/keymile/common/qrio.c
new file mode 100644
index 000000000..25937ee36
--- /dev/null
+++ b/roms/u-boot/board/keymile/common/qrio.c
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+#include "common.h"
+#include "qrio.h"
+
+/* QRIO ID register offset */
+#define ID_REV_OFF		0x00
+
+/* QRIO GPIO register offsets */
+#define DIRECT_OFF		0x18
+#define GPRT_OFF		0x1c
+
+void show_qrio(void)
+{
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
+
+	printf("QRIO: id = %u, revision = %u\n",
+	       (id_rev >> 8) & 0xff, id_rev & 0xff);
+}
+
+int qrio_get_gpio(u8 port_off, u8 gpio_nr)
+{
+	u32 gprt;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	gprt = in_be32(qrio_base + port_off + GPRT_OFF);
+
+	return (gprt >> gpio_nr) & 1U;
+}
+
+void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value)
+{
+	u32 gprt, mask;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	mask = 1U << gpio_nr;
+
+	gprt = in_be32(qrio_base + port_off + GPRT_OFF);
+	if (value)
+		gprt |= mask;
+	else
+		gprt &= ~mask;
+
+	out_be32(qrio_base + port_off + GPRT_OFF, gprt);
+}
+
+void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value)
+{
+	u32 direct, mask;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	mask = 1U << gpio_nr;
+
+	direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+	direct |= mask;
+	out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+
+	qrio_set_gpio(port_off, gpio_nr, value);
+}
+
+void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr)
+{
+	u32 direct, mask;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	mask = 1U << gpio_nr;
+
+	direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+	direct &= ~mask;
+	out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+}
+
+void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
+{
+	u32 direct, mask;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	mask = 1U << gpio_nr;
+
+	direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+	if (val == 0)
+		/* set to output -> GPIO drives low */
+		direct |= mask;
+	else
+		/* set to input -> GPIO floating */
+		direct &= ~mask;
+
+	out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+}
+
+#define WDMASK_OFF	0x16
+
+void qrio_wdmask(u8 bit, bool wden)
+{
+	u16 wdmask;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	wdmask = in_be16(qrio_base + WDMASK_OFF);
+
+	if (wden)
+		wdmask |= (1 << bit);
+	else
+		wdmask &= ~(1 << bit);
+
+	out_be16(qrio_base + WDMASK_OFF, wdmask);
+}
+
+#define PRST_OFF	0x1a
+
+void qrio_prst(u8 bit, bool en, bool wden)
+{
+	u16 prst;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	qrio_wdmask(bit, wden);
+
+	prst = in_be16(qrio_base + PRST_OFF);
+
+	if (en)
+		prst &= ~(1 << bit);
+	else
+		prst |= (1 << bit);
+
+	out_be16(qrio_base + PRST_OFF, prst);
+}
+
+#define PRSTCFG_OFF	0x1c
+
+void qrio_prstcfg(u8 bit, u8 mode)
+{
+	unsigned long prstcfg;
+	u8 i;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
+
+	for (i = 0; i < 2; i++) {
+		if (mode & (1 << i))
+			__set_bit(2 * bit + i, &prstcfg);
+		else
+			__clear_bit(2 * bit + i, &prstcfg);
+	}
+
+	out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
+}
+
+#define CTRLH_OFF		0x02
+#define CTRLH_WRL_BOOT		0x01
+#define CTRLH_WRL_UNITRUN	0x02
+
+void qrio_set_leds(void)
+{
+	u8 ctrlh;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	/* set UNIT LED to RED and BOOT LED to ON */
+	ctrlh = in_8(qrio_base + CTRLH_OFF);
+	ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN);
+	out_8(qrio_base + CTRLH_OFF, ctrlh);
+}
+
+#define CTRLL_OFF		0x03
+#define CTRLL_WRB_BUFENA	0x20
+
+void qrio_enable_app_buffer(void)
+{
+	u8 ctrll;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	/* enable application buffer */
+	ctrll = in_8(qrio_base + CTRLL_OFF);
+	ctrll |= (CTRLL_WRB_BUFENA);
+	out_8(qrio_base + CTRLL_OFF, ctrll);
+}
+
+#define REASON1_OFF	0x12
+#define REASON1_CPUWD	0x01
+
+void qrio_cpuwd_flag(bool flag)
+{
+	u8 reason1;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	reason1 = in_8(qrio_base + REASON1_OFF);
+	if (flag)
+		reason1 |= REASON1_CPUWD;
+	else
+		reason1 &= ~REASON1_CPUWD;
+	out_8(qrio_base + REASON1_OFF, reason1);
+}
+
+#define REASON0_OFF	0x13
+#define REASON0_SWURST	0x80
+#define REASON0_CPURST	0x40
+#define REASON0_BPRST	0x20
+#define REASON0_COPRST	0x10
+#define REASON0_SWCRST	0x08
+#define REASON0_WDRST	0x04
+#define REASON0_KBRST	0x02
+#define REASON0_POWUP	0x01
+#define UNIT_RESET\
+	(REASON0_POWUP | REASON0_COPRST | REASON0_KBRST |\
+	 REASON0_BPRST | REASON0_SWURST | REASON0_WDRST)
+#define CORE_RESET      ((REASON1_CPUWD << 8) | REASON0_SWCRST)
+
+bool qrio_reason_unitrst(void)
+{
+	u16 reason;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	reason = in_be16(qrio_base + REASON1_OFF);
+
+	return (reason & UNIT_RESET) > 0;
+}
+
+#define RSTCFG_OFF	0x11
+
+void qrio_uprstreq(u8 mode)
+{
+	u32 rstcfg;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	rstcfg = in_8(qrio_base + RSTCFG_OFF);
+
+	if (mode & UPREQ_CORE_RST)
+		rstcfg |= UPREQ_CORE_RST;
+	else
+		rstcfg &= ~UPREQ_CORE_RST;
+
+	out_8(qrio_base + RSTCFG_OFF, rstcfg);
+}
+
+/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
+ * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
+ * For I2C only the low state is activly driven and high state is pulled-up
+ * by a resistor. Therefore the deblock GPIOs are used
+ *  -> as an active output to drive a low state
+ *  -> as an open-drain input to have a pulled-up high state
+ */
+
+/* By default deblock GPIOs are floating */
+void i2c_deblock_gpio_cfg(void)
+{
+	/* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
+	qrio_gpio_direction_input(KM_I2C_DEBLOCK_PORT,
+				  KM_I2C_DEBLOCK_SCL);
+	qrio_gpio_direction_input(KM_I2C_DEBLOCK_PORT,
+				  KM_I2C_DEBLOCK_SDA);
+
+	qrio_set_gpio(KM_I2C_DEBLOCK_PORT,
+		      KM_I2C_DEBLOCK_SCL, 0);
+	qrio_set_gpio(KM_I2C_DEBLOCK_PORT,
+		      KM_I2C_DEBLOCK_SDA, 0);
+}
+
+void set_sda(int state)
+{
+	qrio_set_opendrain_gpio(KM_I2C_DEBLOCK_PORT,
+				KM_I2C_DEBLOCK_SDA, state);
+}
+
+void set_scl(int state)
+{
+	qrio_set_opendrain_gpio(KM_I2C_DEBLOCK_PORT,
+				KM_I2C_DEBLOCK_SCL, state);
+}
+
+int get_sda(void)
+{
+	return qrio_get_gpio(KM_I2C_DEBLOCK_PORT,
+			     KM_I2C_DEBLOCK_SDA);
+}
+
+int get_scl(void)
+{
+	return qrio_get_gpio(KM_I2C_DEBLOCK_PORT,
+			     KM_I2C_DEBLOCK_SCL);
+}
+
diff --git a/roms/u-boot/board/keymile/common/qrio.h b/roms/u-boot/board/keymile/common/qrio.h
new file mode 100644
index 000000000..757bcbf2f
--- /dev/null
+++ b/roms/u-boot/board/keymile/common/qrio.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 ABB
+ * Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
+ */
+
+#ifndef __QRIO_H
+#define __QRIO_H
+
+/* QRIO GPIO ports */
+#define QRIO_GPIO_A		0x40
+#define QRIO_GPIO_B		0x60
+
+void show_qrio(void);
+int qrio_get_gpio(u8 port_off, u8 gpio_nr);
+void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val);
+void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value);
+void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value);
+void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr);
+
+/* QRIO Periphery reset configurations */
+#define PRSTCFG_POWUP_UNIT_CORE_RST	0x0
+#define PRSTCFG_POWUP_UNIT_RST		0x1
+#define PRSTCFG_POWUP_RST		0x3
+
+void qrio_prst(u8 bit, bool en, bool wden);
+void qrio_wdmask(u8 bit, bool wden);
+void qrio_prstcfg(u8 bit, u8 mode);
+void qrio_set_leds(void);
+void qrio_enable_app_buffer(void);
+void qrio_cpuwd_flag(bool flag);
+bool qrio_reason_unitrst(void);
+
+/* QRIO uP reset request configurations */
+#define UPREQ_UNIT_RST		0x0
+#define UPREQ_CORE_RST		0x1
+
+void qrio_uprstreq(u8 mode);
+
+void i2c_deblock_gpio_cfg(void);
+#endif /* __QRIO_H */
diff --git a/roms/u-boot/board/keymile/km83xx/Kconfig b/roms/u-boot/board/keymile/km83xx/Kconfig
new file mode 100644
index 000000000..8247ae39d
--- /dev/null
+++ b/roms/u-boot/board/keymile/km83xx/Kconfig
@@ -0,0 +1,176 @@
+menu "KM 83xx Options"
+	depends on MPC83xx
+
+config KM_ENABLE_FULL_DM_DTS_SUPPORT
+	bool "enable full DM/DTS support for KM 83xx boards"
+	default y
+	select CMD_DM
+	select DM
+	select DM_ETH
+	select DM_MDIO
+	select DM_SERIAL
+	select OF_CONTROL
+	select PINCTRL
+	select PINCTRL_QE
+	select PHYLIB
+endmenu
+
+config SYS_MEMTEST_START
+	default 0x00100000
+
+config SYS_MEMTEST_END
+	default 0x00f00000
+
+if TARGET_KMETER1
+
+config SYS_BOARD
+	default "km83xx"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_CONFIG_NAME
+	default "kmeter1"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_MPC8360
+	imply CMD_CRAMFS
+	imply CMD_DIAG
+	imply FS_CRAMFS
+
+endif
+
+if TARGET_KMCOGE5NE
+
+config SYS_BOARD
+	default "km83xx"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_CONFIG_NAME
+	default "kmcoge5ne"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_MPC8360
+	imply CMD_CRAMFS
+	imply CMD_DIAG
+	imply FS_CRAMFS
+
+endif
+
+if TARGET_KMTEGR1
+
+config SYS_BOARD
+	default "km83xx"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_CONFIG_NAME
+	default "kmtegr1"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_MPC8309
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+endif
+
+if TARGET_TUXX1
+
+config SYS_BOARD
+	default "km83xx"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_CONFIG_NAME
+	default "tuxx1"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_MPC832X
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+endif
+
+if TARGET_KMSUPX5
+
+config SYS_BOARD
+	default "km83xx"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_CONFIG_NAME
+	default "kmsupx5"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_MPC832X
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+endif
+
+if TARGET_TUGE1
+
+config SYS_BOARD
+	default "km83xx"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_CONFIG_NAME
+	default "tuge1"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_MPC832X
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+endif
+
+if TARGET_KMOPTI2
+
+config SYS_BOARD
+	default "km83xx"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_CONFIG_NAME
+	default "kmopti2"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_MPC832X
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+endif
+
+if TARGET_KMTEPR2
+
+config SYS_BOARD
+	default "km83xx"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_CONFIG_NAME
+	default "kmtepr2"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_MPC832X
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+endif
diff --git a/roms/u-boot/board/keymile/km83xx/MAINTAINERS b/roms/u-boot/board/keymile/km83xx/MAINTAINERS
new file mode 100644
index 000000000..9268719a7
--- /dev/null
+++ b/roms/u-boot/board/keymile/km83xx/MAINTAINERS
@@ -0,0 +1,31 @@
+KM83XX BOARD
+M:	Holger Brunck <holger.brunck@hitachi-powergrids.com>
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	board/keymile/km83xx/
+F:	include/configs/km8360.h
+F:	configs/kmcoge5ne_defconfig
+F:	configs/kmeter1_defconfig
+F:	include/configs/tuxx1.h
+F:	configs/kmopti2_defconfig
+F:	configs/kmsupx5_defconfig
+F:	configs/kmtepr2_defconfig
+F:	configs/kmtegr1_defconfig
+F:	configs/tuge1_defconfig
+F:	configs/tuxx1_defconfig
+F:	arch/powerpc/dts/km8309-uboot.dtsi
+F:	arch/powerpc/dts/km8321-uboot.dtsi
+F:	arch/powerpc/dts/km8321.dtsi
+F:	arch/powerpc/dts/km836x-uboot.dtsi
+F:	arch/powerpc/dts/km836x.dtsi
+F:	arch/powerpc/dts/kmcoge5ne-uboot.dtsi
+F:	arch/powerpc/dts/kmcoge5ne.dts
+F:	arch/powerpc/dts/kmeter1-uboot.dtsi
+F:	arch/powerpc/dts/kmeter1.dts
+F:	arch/powerpc/dts/kmopti2.dts
+F:	arch/powerpc/dts/kmsupc5.dts
+F:	arch/powerpc/dts/kmsupm5.dts
+F:	arch/powerpc/dts/kmtegr1.dts
+F:	arch/powerpc/dts/kmtepr2.dts
+F:	arch/powerpc/dts/kmtuge1.dts
+F:	arch/powerpc/dts/kmtuxa1.dts
diff --git a/roms/u-boot/board/keymile/km83xx/Makefile b/roms/u-boot/board/keymile/km83xx/Makefile
new file mode 100644
index 000000000..0aef65498
--- /dev/null
+++ b/roms/u-boot/board/keymile/km83xx/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o
diff --git a/roms/u-boot/board/keymile/km83xx/README.kmeter1 b/roms/u-boot/board/keymile/km83xx/README.kmeter1
new file mode 100644
index 000000000..b85d7764b
--- /dev/null
+++ b/roms/u-boot/board/keymile/km83xx/README.kmeter1
@@ -0,0 +1,91 @@
+Keymile kmeter1 Board
+-----------------------------------------
+1.	Alternative Boot EEPROM
+
+    Upon the kmeter1 startup the I2C_1 controller is used to fetch the boot
+    configuration from a serial EEPROM. During the development and debugging
+    phase it might be helpful to apply an alternative boot configuration in
+    a simple way. Therefore it is an alternative boot eeprom on the PIGGY,
+    which can be activated by setting the "ST" jumper on the PIGGY board.
+
+2.	Memory Map
+
+    BaseAddr    PortSz  Size  Device
+    ----------- ------  -----  ------
+    0x0000_0000 64 bit  256MB  DDR
+    0x8000_0000  8 bit  256KB  GPIO/PIGGY on CS1
+    0xa000_0000  8 bit  256MB  PAXE on CS3
+    0xe000_0000           2MB  Int Mem Reg Space
+    0xf000_0000 16 bit  256MB  FLASH on CS0
+
+
+    DDR-SDRAM:
+    The current realization is made with four 16-bits memory devices.
+    Mounting options have been foreseen for device architectures from
+    4Mx16 to 512Mx16. The kmeter1 is equipped with four 32Mx16 devices
+    thus resulting in a total capacity of 256MBytes.
+
+3. Compilation
+
+	Assuming you're using BASH shell:
+
+		export CROSS_COMPILE=your-cross-compile-prefix
+		cd u-boot
+		make distclean
+		make kmeter1_config
+		make
+
+4. Downloading and Flashing Images
+
+4.0 Download over serial line using Kermit:
+
+	loadb
+	[Drop to kermit:
+	    ^\c
+	    send <u-boot-bin-image>
+	    c
+	]
+
+
+    Or via tftp:
+
+	tftp 10000 u-boot.bin
+    => run load
+    Using UEC0 device
+    TFTP from server 192.168.1.1; our IP address is 192.168.205.4
+    Filename '/tftpboot/kmeter1/u-boot.bin'.
+    Load address: 0x200000
+    Loading: ##############
+    done
+    Bytes transferred = 204204 (31dac hex)
+    =>
+
+4.1 Reflash U-Boot Image using U-Boot
+
+    => run update
+    ..... done
+    Un-Protected 5 sectors
+
+    ..... done
+    Erased 5 sectors
+    Copy to Flash... done
+    ..... done
+    Protected 5 sectors
+    Total of 204204 bytes were the same
+    Saving Environment to Flash...
+    . done
+    Un-Protected 1 sectors
+    . done
+    Un-Protected 1 sectors
+    Erasing Flash...
+    . done
+    Erased 1 sectors
+    Writing to Flash... done
+    . done
+    Protected 1 sectors
+    . done
+    Protected 1 sectors
+    =>
+
+5. Notes
+	1) The console baudrate for kmeter1 is 115200bps.
diff --git a/roms/u-boot/board/keymile/km83xx/km83xx.c b/roms/u-boot/board/keymile/km83xx/km83xx.c
new file mode 100644
index 000000000..ecc8c786b
--- /dev/null
+++ b/roms/u-boot/board/keymile/km83xx/km83xx.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008 - 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#include <common.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <ioports.h>
+#include <log.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <pci.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <post.h>
+
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
+static int piggy_present(void)
+{
+	struct km_bec_fpga __iomem *base =
+		(struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
+
+	return in_8(&base->bprth) & PIGGY_PRESENT;
+}
+
+int ethernet_present(void)
+{
+	return piggy_present();
+}
+
+int board_early_init_r(void)
+{
+	struct km_bec_fpga *base =
+		(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+
+#if defined(CONFIG_ARCH_MPC8360)
+	unsigned short	svid;
+	/*
+	 * Because of errata in the UCCs, we have to write to the reserved
+	 * registers to slow the clocks down.
+	 */
+	svid =  SVR_REV(mfspr(SVR));
+	switch (svid) {
+	case 0x0020:
+		/*
+		 * MPC8360ECE.pdf QE_ENET10 table 4:
+		 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
+		 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
+		 */
+		setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
+		break;
+	case 0x0021:
+		/*
+		 * MPC8360ECE.pdf QE_ENET10 table 4:
+		 * IMMR + 0x14AC[24:27] = 1010
+		 */
+		clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
+			0x00000050, 0x000000a0);
+		break;
+	}
+#endif
+
+	/* enable the PHY on the PIGGY */
+	setbits_8(&base->pgy_eth, 0x01);
+	/* enable the Unit LED (green) */
+	setbits_8(&base->oprth, WRL_BOOT);
+	/* enable Application Buffer */
+	setbits_8(&base->oprtl, OPRTL_XBUFENA);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+			CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
+	return 0;
+}
+
+int last_stage_init(void)
+{
+#if defined(CONFIG_TARGET_KMCOGE5NE)
+	struct bfticu_iomap *base =
+		(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
+	u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
+
+	if (dip_switch != 0) {
+		/* start bootloader */
+		puts("DIP:   Enabled\n");
+		env_set("actual_bank", "0");
+	}
+#endif
+	set_km_env();
+	return 0;
+}
+
+static int fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
+	out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+	udelay(200);
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+
+	msize = CONFIG_SYS_DDR_SIZE << 20;
+	disable_addr_trans();
+	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
+	enable_addr_trans();
+	msize /= (1024 * 1024);
+	if (CONFIG_SYS_DDR_SIZE != msize) {
+		for (ddr_size = msize << 20, ddr_size_log2 = 0;
+			(ddr_size > 1);
+			ddr_size = ddr_size >> 1, ddr_size_log2++)
+			if (ddr_size & 1)
+				return -1;
+		out_be32(&im->sysconf.ddrlaw[0].ar,
+			(LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
+		out_be32(&im->ddr.csbnds[0].csbnds,
+			(((msize / 16) - 1) & 0xff));
+	}
+
+	return msize;
+}
+
+int dram_init(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -ENXIO;
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+		CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
+	msize = fixed_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize DDR ECC byte
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME);
+
+	if (piggy_present())
+		puts(" with PIGGY.");
+	puts("\n");
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_POST)
+int post_hotkeys_pressed(void)
+{
+	int testpin = 0;
+	struct km_bec_fpga *base =
+		(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+	int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
+	testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
+	debug("post_hotkeys_pressed: %d\n", !testpin);
+	return testpin;
+}
+
+ulong post_word_load(void)
+{
+	void* addr = (ulong *) (CPM_POST_WORD_ADDR);
+	debug("post_word_load 0x%08lX:  0x%08X\n", (ulong)addr, in_le32(addr));
+	return in_le32(addr);
+
+}
+void post_word_store(ulong value)
+{
+	void* addr = (ulong *) (CPM_POST_WORD_ADDR);
+	debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
+	out_le32(addr, value);
+}
+
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	*vstart = CONFIG_SYS_MEMTEST_START;
+	*size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
+	debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/keymile/km83xx/km83xx_i2c.c b/roms/u-boot/board/keymile/km83xx/km83xx_i2c.c
new file mode 100644
index 000000000..62100b194
--- /dev/null
+++ b/roms/u-boot/board/keymile/km83xx/km83xx_i2c.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <linux/ctype.h>
+#include <linux/delay.h>
+#include "../common/common.h"
+
+static void i2c_write_start_seq(void)
+{
+	struct fsl_i2c_base *base;
+	base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
+			CONFIG_SYS_I2C_OFFSET);
+	udelay(DELAY_ABORT_SEQ);
+	out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+	udelay(DELAY_ABORT_SEQ);
+	out_8(&base->cr, (I2C_CR_MEN));
+}
+
+int i2c_make_abort(void)
+{
+	struct fsl_i2c_base *base;
+	base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
+			CONFIG_SYS_I2C_OFFSET);
+	uchar   last;
+	int     nbr_read = 0;
+	int     i = 0;
+	int	    ret = 0;
+
+	/* wait after each operation to finsh with a delay */
+	out_8(&base->cr, (I2C_CR_MSTA));
+	udelay(DELAY_ABORT_SEQ);
+	out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+	udelay(DELAY_ABORT_SEQ);
+	in_8(&base->dr);
+	udelay(DELAY_ABORT_SEQ);
+	last = in_8(&base->dr);
+	nbr_read++;
+
+	/*
+	 * do read until the last bit is 1, but stop if the full eeprom is
+	 * read.
+	 */
+	while (((last & 0x01) != 0x01) &&
+		(nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
+		udelay(DELAY_ABORT_SEQ);
+		last = in_8(&base->dr);
+		nbr_read++;
+	}
+	if ((last & 0x01) != 0x01)
+		ret = -2;
+	if ((last != 0xff) || (nbr_read > 1))
+		printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
+			nbr_read, last);
+	udelay(DELAY_ABORT_SEQ);
+	out_8(&base->cr, (I2C_CR_MEN));
+	udelay(DELAY_ABORT_SEQ);
+	/* clear status reg */
+	out_8(&base->sr, 0);
+
+	for (i = 0; i < 5; i++)
+		i2c_write_start_seq();
+	if (ret != 0)
+		printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n",
+			nbr_read, last);
+
+	return ret;
+}
diff --git a/roms/u-boot/board/keymile/km_arm/Kconfig b/roms/u-boot/board/keymile/km_arm/Kconfig
new file mode 100644
index 000000000..6f55cfab8
--- /dev/null
+++ b/roms/u-boot/board/keymile/km_arm/Kconfig
@@ -0,0 +1,69 @@
+menu "KM ARM Options"
+	depends on ARM
+
+config KM_FPGA_CONFIG
+	bool "FPGA Configuration"
+	default n
+	help
+	  Include capability to change FPGA configuration.
+
+config KM_FPGA_FORCE_CONFIG
+	bool "FPGA reconfiguration"
+	default n
+	help
+	  If yes we force to reconfigure the FPGA always
+
+config KM_FPGA_NO_RESET
+	bool "FPGA skip reset"
+	default n
+	help
+	  If yes we skip triggering a reset of the FPGA
+
+config KM_ENV_IS_IN_SPI_NOR
+	bool "Environment in SPI NOR"
+	default n
+	help
+	  Put the U-Boot environment in the SPI NOR flash.
+
+config KM_PIGGY4_88E6061
+	bool "Piggy via Switch 88E6061"
+	default n
+	help
+	  The Piggy4 board is connected via a Marvell 88E6061 switch.
+
+config KM_PIGGY4_88E6352
+	bool "Piggy via Switch 88E6352"
+	default n
+	help
+	  The Piggy4 board is connected via a Marvell 88E6352 switch.
+
+endmenu
+
+if TARGET_KM_KIRKWOOD
+
+config SYS_BOARD
+	default "km_arm"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_CONFIG_NAME
+	default "km_kirkwood"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select BOARD_LATE_INIT
+	select DM
+	select DM_ETH
+	select DM_SERIAL
+	select DM_SPI
+	select DM_SPI_FLASH
+	select USB
+	select USB_EHCI_HCD
+	select USB_EHCI_MARVELL
+	imply CMD_CRAMFS
+	imply CMD_DIAG
+	imply FS_CRAMFS
+	imply CMD_USB
+
+endif
diff --git a/roms/u-boot/board/keymile/km_arm/MAINTAINERS b/roms/u-boot/board/keymile/km_arm/MAINTAINERS
new file mode 100644
index 000000000..8da58da96
--- /dev/null
+++ b/roms/u-boot/board/keymile/km_arm/MAINTAINERS
@@ -0,0 +1,11 @@
+KM_ARM BOARD
+M:	Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
+S:	Maintained
+F:	board/keymile/km_arm/
+F:	include/configs/km_kirkwood.h
+F:	configs/km_kirkwood_defconfig
+F:	configs/km_kirkwood_128m16_defconfig
+F:	configs/km_kirkwood_pci_defconfig
+F:	configs/kmcoge5un_defconfig
+F:	configs/kmnusa_defconfig
+F:	configs/kmsuse2_defconfig
diff --git a/roms/u-boot/board/keymile/km_arm/Makefile b/roms/u-boot/board/keymile/km_arm/Makefile
new file mode 100644
index 000000000..79ccc763e
--- /dev/null
+++ b/roms/u-boot/board/keymile/km_arm/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= km_arm.o ../common/common.o ../common/ivm.o
+
+ifdef CONFIG_KM_FPGA_CONFIG
+obj-y	+= fpga_config.o
+endif
diff --git a/roms/u-boot/board/keymile/km_arm/fpga_config.c b/roms/u-boot/board/keymile/km_arm/fpga_config.c
new file mode 100644
index 000000000..839b162ee
--- /dev/null
+++ b/roms/u-boot/board/keymile/km_arm/fpga_config.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+
+/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
+#define KM_XLX_PROGRAM_B_PIN    39
+
+#define BOCO_ADDR	0x10
+
+#define ID_REG		0x00
+#define BOCO2_ID	0x5b
+
+static int check_boco2(void)
+{
+	int ret;
+	u8 id;
+
+	ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1);
+	if (ret) {
+		printf("%s: error reading the BOCO id !!\n", __func__);
+		return ret;
+	}
+
+	return (id == BOCO2_ID);
+}
+
+static int boco_clear_bits(u8 reg, u8 flags)
+{
+	int ret;
+	u8 regval;
+
+	/* give access to the EEPROM from FPGA */
+	ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error reading the BOCO @%#x !!\n",
+		       __func__, reg);
+		return ret;
+	}
+	regval &= ~flags;
+	ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error writing the BOCO @%#x !!\n",
+		       __func__, reg);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int boco_set_bits(u8 reg, u8 flags)
+{
+	int ret;
+	u8 regval;
+
+	/* give access to the EEPROM from FPGA */
+	ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error reading the BOCO @%#x !!\n",
+		       __func__, reg);
+		return ret;
+	}
+	regval |= flags;
+	ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error writing the BOCO @%#x !!\n",
+		       __func__, reg);
+		return ret;
+	}
+
+	return 0;
+}
+
+#define SPI_REG		0x06
+#define CFG_EEPROM	0x02
+#define FPGA_PROG	0x04
+#define FPGA_INIT_B	0x10
+#define FPGA_DONE	0x20
+
+#ifndef CONFIG_KM_FPGA_FORCE_CONFIG
+static int fpga_done(void)
+{
+	int ret = 0;
+	u8 regval;
+
+	/* this is only supported with the boco2 design */
+	if (!check_boco2())
+		return 0;
+
+	ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error reading the BOCO @%#x !!\n",
+			__func__, SPI_REG);
+		return 0;
+	}
+
+	return regval & FPGA_DONE ? 1 : 0;
+}
+#endif /* CONFIG_KM_FPGA_FORCE_CONFIG */
+
+static int skip;
+
+int trigger_fpga_config(void)
+{
+	int ret = 0;
+
+	skip = 0;
+#ifndef CONFIG_KM_FPGA_FORCE_CONFIG
+	/* if the FPGA is already configured, we do not want to
+	 * reconfigure it
+	 */
+	skip = 0;
+	if (fpga_done()) {
+		printf("PCIe FPGA config: skipped\n");
+		skip = 1;
+		return 0;
+	}
+#endif /* CONFIG_KM_FPGA_FORCE_CONFIG */
+
+	if (check_boco2()) {
+		/* we have a BOCO2, this has to be triggered here */
+
+		/* make sure the FPGA_can access the EEPROM */
+		ret = boco_clear_bits(SPI_REG, CFG_EEPROM);
+		if (ret)
+			return ret;
+
+		/* trigger the config start */
+		ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);
+		if (ret)
+			return ret;
+
+		/* small delay for the pulse */
+		udelay(10);
+
+		/* up signal for pulse end */
+		ret = boco_set_bits(SPI_REG, FPGA_PROG);
+		if (ret)
+			return ret;
+
+		/* finally, raise INIT_B to remove the config delay */
+		ret = boco_set_bits(SPI_REG, FPGA_INIT_B);
+		if (ret)
+			return ret;
+
+	} else {
+		/* we do it the old way, with the gpio pin */
+		kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
+		kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
+		/* small delay for the pulse */
+		udelay(10);
+		kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
+	}
+
+	return 0;
+}
+
+int wait_for_fpga_config(void)
+{
+	int ret = 0;
+	u8 spictrl;
+	u32 timeout = 20000;
+
+	if (skip)
+		return 0;
+
+	if (!check_boco2()) {
+		/* we do not have BOCO2, this is not really used */
+		return 0;
+	}
+
+	printf("PCIe FPGA config:");
+	do {
+		ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1);
+		if (ret) {
+			printf("%s: error reading the BOCO spictrl !!\n",
+			       __func__);
+			return ret;
+		}
+		if (timeout-- == 0) {
+			printf(" FPGA_DONE timeout\n");
+			return -EFAULT;
+		}
+		udelay(10);
+	} while (!(spictrl & FPGA_DONE));
+
+	printf(" done\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_KM_FPGA_NO_RESET)
+int fpga_reset(void)
+{
+	/* no dedicated reset pin for FPGA */
+	return 0;
+}
+#else
+
+#define PRST1		0x4
+#define PCIE_RST	0x10
+#define TRAFFIC_RST	0x04
+
+int fpga_reset(void)
+{
+	int ret = 0;
+	u8 resets;
+
+	if (!check_boco2()) {
+		/* we do not have BOCO2, this is not really used */
+		return 0;
+	}
+
+	/* if we have skipped, we only want to reset the PCIe part */
+	resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
+
+	ret = boco_clear_bits(PRST1, resets);
+	if (ret)
+		return ret;
+
+	/* small delay for the pulse */
+	udelay(10);
+
+	ret = boco_set_bits(PRST1, resets);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+#endif
+
+/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
+ * is available from the Bobcat SPI bus
+ */
+int toggle_eeprom_spi_bus(void)
+{
+	int ret = 0;
+
+	if (!check_boco2()) {
+		/* we do not have BOCO2, this is not really used */
+		return 0;
+	}
+
+	ret = boco_set_bits(SPI_REG, CFG_EEPROM);
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/keymile/km_arm/km_arm.c b/roms/u-boot/board/keymile/km_arm/km_arm.c
new file mode 100644
index 000000000..e9af090a3
--- /dev/null
+++ b/roms/u-boot/board/keymile/km_arm/km_arm.c
@@ -0,0 +1,520 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#include <common.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <nand.h>
+#include <net.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <spi.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * BOCO FPGA definitions
+ */
+#define BOCO		0x10
+#define REG_CTRL_H		0x02
+#define MASK_WRL_UNITRUN	0x01
+#define MASK_RBX_PGY_PRESENT	0x40
+#define REG_IRQ_CIRQ2		0x2d
+#define MASK_RBI_DEFECT_16	0x01
+
+/*
+ * PHY registers definitions
+ */
+#define PHY_MARVELL_OUI					0x5043
+#define PHY_MARVELL_88E1118_MODEL			0x0022
+#define PHY_MARVELL_88E1118R_MODEL			0x0024
+
+#define PHY_MARVELL_PAGE_REG				0x0016
+#define PHY_MARVELL_DEFAULT_PAGE			0x0000
+
+#define PHY_MARVELL_88E1118R_LED_CTRL_PAGE		0x0003
+#define PHY_MARVELL_88E1118R_LED_CTRL_REG		0x0010
+
+#define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED		0x1000
+#define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB	(0x7 << 0)
+#define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT		(0x3 << 4)
+#define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK		(0x0 << 8)
+
+/* I/O pin to erase flash RGPP09 = MPP43 */
+#define KM_FLASH_ERASE_ENABLE	43
+
+/* Multi-Purpose Pins Functionality configuration */
+static const u32 kwmpp_config[] = {
+	MPP0_NF_IO2,
+	MPP1_NF_IO3,
+	MPP2_NF_IO4,
+	MPP3_NF_IO5,
+	MPP4_NF_IO6,
+	MPP5_NF_IO7,
+	MPP6_SYSRST_OUTn,
+	MPP7_PEX_RST_OUTn,
+#if defined(CONFIG_SYS_I2C_SOFT)
+	MPP8_GPIO,		/* SDA */
+	MPP9_GPIO,		/* SCL */
+#endif
+	MPP10_UART0_TXD,
+	MPP11_UART0_RXD,
+	MPP12_GPO,		/* Reserved */
+	MPP13_UART1_TXD,
+	MPP14_UART1_RXD,
+	MPP15_GPIO,		/* Not used */
+	MPP16_GPIO,		/* Not used */
+	MPP17_GPIO,		/* Reserved */
+	MPP18_NF_IO0,
+	MPP19_NF_IO1,
+	MPP20_GPIO,
+	MPP21_GPIO,
+	MPP22_GPIO,
+	MPP23_GPIO,
+	MPP24_GPIO,
+	MPP25_GPIO,
+	MPP26_GPIO,
+	MPP27_GPIO,
+	MPP28_GPIO,
+	MPP29_GPIO,
+	MPP30_GPIO,
+	MPP31_GPIO,
+	MPP32_GPIO,
+	MPP33_GPIO,
+	MPP34_GPIO,		/* CDL1 (input) */
+	MPP35_GPIO,		/* CDL2 (input) */
+	MPP36_GPIO,		/* MAIN_IRQ (input) */
+	MPP37_GPIO,		/* BOARD_LED */
+	MPP38_GPIO,		/* Piggy3 LED[1] */
+	MPP39_GPIO,		/* Piggy3 LED[2] */
+	MPP40_GPIO,		/* Piggy3 LED[3] */
+	MPP41_GPIO,		/* Piggy3 LED[4] */
+	MPP42_GPIO,		/* Piggy3 LED[5] */
+	MPP43_GPIO,		/* Piggy3 LED[6] */
+	MPP44_GPIO,		/* Piggy3 LED[7], BIST_EN_L */
+	MPP45_GPIO,		/* Piggy3 LED[8] */
+	MPP46_GPIO,		/* Reserved */
+	MPP47_GPIO,		/* Reserved */
+	MPP48_GPIO,		/* Reserved */
+	MPP49_GPIO,		/* SW_INTOUTn */
+	0
+};
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
+#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
+/*
+ * All boards with PIGGY4 connected via a simple switch have ethernet always
+ * present.
+ */
+int ethernet_present(void)
+{
+	return 1;
+}
+#else
+int ethernet_present(void)
+{
+	uchar	buf;
+	int	ret = 0;
+
+	if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
+		printf("%s: Error reading Boco\n", __func__);
+		return -1;
+	}
+	if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
+		ret = 1;
+
+	return ret;
+}
+#endif
+
+static int initialize_unit_leds(void)
+{
+	/*
+	 * Init the unit LEDs per default they all are
+	 * ok apart from bootstat
+	 */
+	uchar buf;
+
+	if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
+		printf("%s: Error reading Boco\n", __func__);
+		return -1;
+	}
+	buf |= MASK_WRL_UNITRUN;
+	if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
+		printf("%s: Error writing Boco\n", __func__);
+		return -1;
+	}
+	return 0;
+}
+
+static void set_bootcount_addr(void)
+{
+	uchar buf[32];
+	unsigned int bootcountaddr;
+
+	bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
+	sprintf((char *)buf, "0x%x", bootcountaddr);
+	env_set("bootcountaddr", (char *)buf);
+}
+
+int misc_init_r(void)
+{
+	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+			CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
+
+	initialize_unit_leds();
+	set_km_env();
+	set_bootcount_addr();
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_SYS_I2C_SOFT)
+	u32 tmp;
+
+	/* set the 2 bitbang i2c pins as output gpios */
+	tmp = readl(MVEBU_GPIO0_BASE + 4);
+	writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS), MVEBU_GPIO0_BASE + 4);
+#endif
+	/* adjust SDRAM size for bank 0 */
+	mvebu_sdram_size_adjust(0);
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/*
+	 * The KM_FLASH_GPIO_PIN switches between using a
+	 * NAND or a SPI FLASH. Set this pin on start
+	 * to NAND mode.
+	 */
+	kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+	kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
+
+#if defined(CONFIG_SYS_I2C_SOFT)
+	/*
+	 * Reinit the GPIO for I2C Bitbang driver so that the now
+	 * available gpio framework is consistent. The calls to
+	 * direction output in are not necessary, they are already done in
+	 * board_early_init_f
+	 */
+	kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
+	kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
+	kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
+#endif
+
+#if defined(CONFIG_KM_FPGA_CONFIG)
+	trigger_fpga_config();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_KM_COGE5UN)
+	u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
+
+	/* if pin 1 do full erase */
+	if (dip_switch != 0) {
+		/* start bootloader */
+		puts("DIP:   Enabled\n");
+		env_set("actual_bank", "0");
+	}
+#endif
+
+#if defined(CONFIG_KM_FPGA_CONFIG)
+	wait_for_fpga_config();
+	fpga_reset();
+	toggle_eeprom_spi_bus();
+#endif
+	return 0;
+}
+
+static const u32 spi_mpp_config[] = {
+	MPP1_SPI_MOSI,
+	MPP2_SPI_SCK,
+	MPP3_SPI_MISO,
+	0
+};
+
+static u32 spi_mpp_backup[4];
+
+int mvebu_board_spi_claim_bus(struct udevice *dev)
+{
+	spi_mpp_backup[3] = 0;
+
+	/* set new spi mpp config and save current one */
+	kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
+
+	kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
+
+	return 0;
+}
+
+int mvebu_board_spi_release_bus(struct udevice *dev)
+{
+	/* restore saved mpp config */
+	kirkwood_mpp_conf(spi_mpp_backup, NULL);
+
+	kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
+
+	return 0;
+}
+
+#if (defined(CONFIG_KM_PIGGY4_88E6061))
+
+#define	PHY_LED_SEL_REG		0x18
+#define PHY_LED0_LINK		(0x5)
+#define PHY_LED1_ACT		(0x8 << 4)
+#define PHY_LED2_INT		(0xe << 8)
+#define	PHY_SPEC_CTRL_REG	0x1c
+#define PHY_RGMII_CLK_STABLE	(0x1 << 10)
+#define PHY_CLSA		(0x1 << 1)
+
+/* Configure and enable MV88E3018 PHY */
+void reset_phy(void)
+{
+	char *name = "egiga0";
+	unsigned short reg;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* RGMII clk transition on data stable */
+	if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
+		printf("Error reading PHY spec ctrl reg\n");
+	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
+			 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
+		printf("Error writing PHY spec ctrl reg\n");
+
+	/* leds setup */
+	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
+			 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
+		printf("Error writing PHY LED reg\n");
+
+	/* reset the phy */
+	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
+}
+#elif defined(CONFIG_KM_PIGGY4_88E6352)
+
+#include <mv88e6352.h>
+
+#if defined(CONFIG_KM_NUSA)
+struct mv88e_sw_reg extsw_conf[] = {
+	/*
+	 * port 0, PIGGY4, autoneg
+	 * first the fix for the 1000Mbits Autoneg, this is from
+	 * a Marvell errata, the regs are undocumented
+	 */
+	{ PHY(0), PHY_PAGE, AN1000FIX_PAGE },
+	{ PHY(0), PHY_STATUS, AN1000FIX },
+	{ PHY(0), PHY_PAGE, 0 },
+	/* now the real port and phy configuration */
+	{ PORT(0), PORT_PHY, NO_SPEED_FOR },
+	{ PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+	{ PHY(0), PHY_1000_CTRL, NO_ADV },
+	{ PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
+	{ PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
+		FULL_DUPLEX },
+	/* port 1, unused */
+	{ PORT(1), PORT_CTRL, PORT_DIS },
+	{ PHY(1), PHY_CTRL, PHY_PWR_DOWN },
+	{ PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+	/* port 2, unused */
+	{ PORT(2), PORT_CTRL, PORT_DIS },
+	{ PHY(2), PHY_CTRL, PHY_PWR_DOWN },
+	{ PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+	/* port 3, unused */
+	{ PORT(3), PORT_CTRL, PORT_DIS },
+	{ PHY(3), PHY_CTRL, PHY_PWR_DOWN },
+	{ PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+	/* port 4, ICNEV, SerDes, SGMII */
+	{ PORT(4), PORT_STATUS, NO_PHY_DETECT },
+	{ PORT(4), PORT_PHY, SPEED_1000_FOR },
+	{ PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+	{ PHY(4), PHY_CTRL, PHY_PWR_DOWN },
+	{ PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+	/* port 5, CPU_RGMII */
+	{ PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
+		FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
+		FULL_DPX_FOR | SPEED_1000_FOR },
+	{ PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+	/* port 6, unused, this port has no phy */
+	{ PORT(6), PORT_CTRL, PORT_DIS },
+};
+#else
+struct mv88e_sw_reg extsw_conf[] = {};
+#endif
+
+void reset_phy(void)
+{
+#if defined(CONFIG_KM_MVEXTSW_ADDR)
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
+		ARRAY_SIZE(extsw_conf));
+	mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
+#endif
+}
+
+#else
+/* Configure and enable MV88E1118 PHY on the piggy*/
+void reset_phy(void)
+{
+	unsigned int oui;
+	unsigned char model, rev;
+
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* reset the phy */
+	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
+
+	/* get PHY model */
+	if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
+		return;
+
+	/* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
+	if (oui == PHY_MARVELL_OUI &&
+	    model == PHY_MARVELL_88E1118R_MODEL) {
+		/* set page register to 3 */
+		if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
+				 PHY_MARVELL_PAGE_REG,
+				 PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
+			printf("Error writing PHY page reg\n");
+
+		/*
+		 * leds setup as printed on PCB:
+		 * LED2 (Link): 0x0 (On Link, Off No Link)
+		 * LED1 (Activity): 0x3 (On Activity, Off No Activity)
+		 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
+		 */
+		if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
+				 PHY_MARVELL_88E1118R_LED_CTRL_REG,
+				 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
+				 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
+				 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
+				 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
+			printf("Error writing PHY LED reg\n");
+
+		/* set page register back to 0 */
+		if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
+				 PHY_MARVELL_PAGE_REG,
+				 PHY_MARVELL_DEFAULT_PAGE))
+			printf("Error writing PHY page reg\n");
+	}
+}
+#endif
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_I2C_SOFT)
+void set_sda(int state)
+{
+	I2C_ACTIVE;
+	I2C_SDA(state);
+}
+
+void set_scl(int state)
+{
+	I2C_SCL(state);
+}
+
+int get_sda(void)
+{
+	I2C_TRISTATE;
+	return I2C_READ;
+}
+
+int get_scl(void)
+{
+	return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
+}
+#endif
+
+#if defined(CONFIG_POST)
+
+#define KM_POST_EN_L	44
+#define POST_WORD_OFF	8
+
+int post_hotkeys_pressed(void)
+{
+	if (IS_ENABLED(CONFIG_KM_COGE5UN))
+		return kw_gpio_get_value(KM_POST_EN_L);
+	else
+		return !kw_gpio_get_value(KM_POST_EN_L);
+}
+
+ulong post_word_load(void)
+{
+	void *addr = (void *)(gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
+
+	return in_le32(addr);
+
+}
+void post_word_store(ulong value)
+{
+	void *addr = (void *)(gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
+
+	out_le32(addr, value);
+}
+
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	*vstart = CONFIG_SYS_SDRAM_BASE;
+
+	/* we go up to relocation plus a 1 MB margin */
+	*size = CONFIG_SYS_TEXT_BASE - (1 << 20);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+int eeprom_write_enable(unsigned int dev_addr, int state)
+{
+	kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
+
+	return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
+}
+#endif
diff --git a/roms/u-boot/board/keymile/km_arm/kwbimage-memphis.cfg b/roms/u-boot/board/keymile/km_arm/kwbimage-memphis.cfg
new file mode 100644
index 000000000..d850e1011
--- /dev/null
+++ b/roms/u-boot/board/keymile/km_arm/kwbimage-memphis.cfg
@@ -0,0 +1,179 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# (C) Copyright 2011
+# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222	# MPP Control 0 Register
+# bit 3-0:   MPPSel0	2, NF_IO[2]
+# bit 7-4:   MPPSel1	2, NF_IO[3]
+# bit 12-8:  MPPSel2	2, NF_IO[4]
+# bit 15-12: MPPSel3	2, NF_IO[5]
+# bit 19-16: MPPSel4	1, NF_IO[6]
+# bit 23-20: MPPSel5	1, NF_IO[7]
+# bit 27-24: MPPSel6	1, SYSRST_O
+# bit 31-28: MPPSel7	0, GPO[7]
+
+DATA 0xFFD10004 0x03303300
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   MPPSel16	0, GPIO[16]
+# bit 7-4:   MPPSel17	0, GPIO[17]
+# bit 12-8:  MPPSel18	1, NF_IO[0]
+# bit 15-12: MPPSel19	1, NF_IO[1]
+# bit 19-16: MPPSel20	0, GPIO[20]
+# bit 23-20: MPPSel21	0, GPIO[21]
+# bit 27-24: MPPSel22	0, GPIO[22]
+# bit 31-28: MPPSel23	0, GPIO[23]
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
+DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
+
+#Dram initalization
+DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
+# bit13-0:  0x4E0 (DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x38543000	# DDR Controller Control Low
+# bit 3-0:  0 reserved
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302433E	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A3E	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000001	#  DDR Address Control
+# bit1-0:   01, Cs0width=x16
+# bit3-2:   00, Cs0size=2Gb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+DATA 0xFFD01420 0x00000006	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd disabled
+# bit5-3:  000, required
+# bit6:    0,  DDR ODT control msb disabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add a sample stage
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00084520	# DDR2 SDRAM Timing Low
+# bit3-0  : 0000, required
+# bit7-4  : 0010, M_ODT assertion 2 cycles after read
+# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
+# bit15-12: 0100, internal ODT assertion 4 cycles after read
+# bit19-16: 1000, internal ODT de-assertion 8 cycles after read
+# bit31-20: 0   , required
+
+DATA 0xFFD0147c 0x00008451	# DDR2 SDRAM Timing High
+# bit3-0  : 0001, M_ODT assertion same cycle as write
+# bit7-4  : 0101, M_ODT de-assertion x cycles after write
+# bit11-8 : 0100, internal ODT assertion x cycles after write
+# bit15-12: 1000, internal ODT de-assertion x cycles after write
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit3-0:  0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  00, ODT1 controlled by register
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000F801	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
+# bit9-8:  0, ODTEn, controlled by ODT0Rd and ODT0Wr
+# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm
+# bit14   :1, STARTBURST ODT enabled
+# bit15   :1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/keymile/km_arm/kwbimage.cfg b/roms/u-boot/board/keymile/km_arm/kwbimage.cfg
new file mode 100644
index 000000000..6b62ce0ab
--- /dev/null
+++ b/roms/u-boot/board/keymile/km_arm/kwbimage.cfg
@@ -0,0 +1,161 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222	# MPP Control 0 Register
+# bit 3-0:   MPPSel0	2, NF_IO[2]
+# bit 7-4:   MPPSel1	2, NF_IO[3]
+# bit 12-8:  MPPSel2	2, NF_IO[4]
+# bit 15-12: MPPSel3	2, NF_IO[5]
+# bit 19-16: MPPSel4	1, NF_IO[6]
+# bit 23-20: MPPSel5	1, NF_IO[7]
+# bit 27-24: MPPSel6	1, SYSRST_O
+# bit 31-28: MPPSel7	0, GPO[7]
+
+DATA 0xFFD10004 0x03303300
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   MPPSel16	0, GPIO[16]
+# bit 7-4:   MPPSel17	0, GPIO[17]
+# bit 12-8:  MPPSel18	1, NF_IO[0]
+# bit 15-12: MPPSel19	1, NF_IO[1]
+# bit 19-16: MPPSel20	0, GPIO[20]
+# bit 23-20: MPPSel21	0, GPIO[21]
+# bit 27-24: MPPSel22	0, GPIO[22]
+# bit 31-28: MPPSel23	0, GPIO[23]
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
+DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
+
+#Dram initalization
+DATA 0xFFD01400 0x43000400	# SDRAM Configuration Register
+# bit13-0:  0x400 (DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x39543000	# DDR Controller Control Low
+# bit 3-0:  0 reserved
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x34136552	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000033	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000D	#  DDR Address Control
+# bit1-0:   01, Cs0width=x16
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+DATA 0xFFD01420 0x00000044	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    1,  DDR ODT control lsd disabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  0  , no sample stage
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+DATA 0xFFD01428 0x00074510
+DATA 0xFFD0147c 0x00007451
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010001	#  DDR ODT Control (Low)
+# bit3-0:  0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  00, ODT1 controlled by register
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000FC11	# CPU ODT Control
+# bit3-0:  F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit9-8:  1, ODTEn, never active
+# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/keymile/km_arm/kwbimage_128M16_1.cfg b/roms/u-boot/board/keymile/km_arm/kwbimage_128M16_1.cfg
new file mode 100644
index 000000000..e30c0feec
--- /dev/null
+++ b/roms/u-boot/board/keymile/km_arm/kwbimage_128M16_1.cfg
@@ -0,0 +1,257 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# (C) Copyright 2012
+# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
+#
+# (C) Copyright 2012
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222	# MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_SI   (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_SO   (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300	# MPP Control 1 Register
+# bit 3-0:   0, MPPSel8	 GPIO[8]
+# bit 7-4:   0, MPPSel9  GPIO[9]
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 UA1_TXD
+# bit 27-24: 3, MPPSel14 UA1_RXD
+# bit 31-28: 0, MPPSel15 GPIO[15]
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 12-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5-3:   3, Reserved
+# bit 6:     0, Reserved
+# bit 7:     0, RGMII-pads voltage = 3.3V
+# bit 10-8:  3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14:    0, Reserved
+# bit 15:    0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16  0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
+# bit 0-1:   2, Tag RAM RTC RAM0
+# bit 3-2:   1, Tag RAM WTC RAM0
+# bit 7-4:   6, Reserve
+# bit 9-8:   2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
+# bit 15-0:  ???, Reserve
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ???,Reserve
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
+# bit 13-0:  0x4E0, DDR2 clks refresh rate
+# bit 14:    0, reserved
+# bit 15:    0, reserved
+# bit 16:    0, CPU to Dram Write buffer policy
+# bit 17:    0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24:    1, enable exit self refresh mode on DDR access
+# bit 25:    1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000	# DDR Controller Control Low
+# bit 3-0:   0, reserved
+# bit 4:     0, 2T mode =addr/cmd in same cycle
+# bit 5:     0, clk is driven during self refresh, we don't care for APX
+# bit 6:     0, use recommended falling edge of clk for addr/cmd
+# bit 7-11:  0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14:    0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18:    1, cpu lock transaction enabled
+# bit 19:    0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM
+# bit 30-28: 3, required
+# bit 31:    0,no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302444e	# DDR Timing (Low) (active cycles value +1)
+# bit 3-0:   0xE, TRAS, 15 clk (45 ns)
+# bit 7-4:   0x4, TRCD, 5 clk (15 ns)
+# bit 11-8:  0x4, TRP, 5 clk (15 ns)
+# bit 15-12: 0x4, TWR, 5 clk (15 ns)
+# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
+# bit 20:      0, extended TRAS msb
+# bit 23-21:   0, reserved
+# bit 27-24: 0x3, TRRD, 4 clk (10 ns)
+# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+
+DATA 0xFFD0140C 0x0000003e	#  DDR Timing (High)
+# bit 6-0:   0x3E, TRFC, 63 clk (195 ns)
+# bit 8-7:      0, TR2R
+# bit 10-9:     0, TR2W
+# bit 12-11:    0, TW2W
+# bit 31-13:    0, reserved
+
+DATA 0xFFD01410 0x00000001	#  DDR Address Control
+# bit 1-0:    1, Cs0width=x16
+# bit 3-2:    0, Cs0size=2Gb
+# bit 5-4:    0, Cs1width=nonexistent
+# bit 7-6:    0, Cs1size =nonexistent
+# bit 9-8:    0, Cs2width=nonexistent
+# bit 11-10:  0, Cs2size =nonexistent
+# bit 13-12:  0, Cs3width=nonexistent
+# bit 15-14:  0, Cs3size =nonexistent
+# bit 16:     0, Cs0AddrSel
+# bit 17:     0, Cs1AddrSel
+# bit 18:     0, Cs2AddrSel
+# bit 19:     0, Cs3AddrSel
+# bit 31-20:  0, required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit 0:      0,  OpenPage enabled
+# bit 31-1:   0, required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit 3-0:    0, DDR cmd
+# bit 31-4:   0, required
+
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+# bit 2-0:    2, Burst Length = 4
+# bit 3:      0, Burst Type
+# bit 6-4:    5, CAS Latency = 5
+# bit 7:      0, Test mode
+# bit 8:      0, DLL Reset
+# bit 11-9:   3, Write recovery for auto-precharge must be 3
+# bit 12:     0, Active power down exit time, fast exit
+# bit 14-13:  0, reserved
+# bit 31-15:  0, reserved
+
+DATA 0xFFD01420 0x00000006	#  DDR Extended Mode
+# bit 0:      0, DDR DLL enabled
+# bit 1:      1,  DDR drive strength reduced
+# bit 2:      1,  DDR ODT control lsb, 75 ohm termination [RTT0]
+# bit 5-3:    0, required
+# bit 6:      0, DDR ODT control msb, 75 ohm termination [RTT1]
+# bit 9-7:    0, required
+# bit 10:     0, differential DQS enabled
+# bit 11:     0, required
+# bit 12:     0, DDR output buffer enabled
+# bit 31-13:  0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit 2-0:    7, required
+# bit 3:      1, MBUS Burst Chop disabled
+# bit 6-4:    7, required
+# bit 7:      0, reserved
+# bit 8:      1, add sample stage required for f > 266 MHz
+# bit 9:      0, no half clock cycle addition to dataout
+# bit 10:     0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11:     0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16:  0, required
+
+DATA 0xFFD01428 0x00084520	# DDR2 SDRAM Timing Low
+# bit 3-0:    0, required
+# bit 7-4:    2, M_ODT assertion 2 cycles after read start command
+# bit 11-8:   5, M_ODT de-assertion 5 cycles after read start command
+#                (ODT turn off delay 2,5 clk cycles)
+# bit 15-12:  4, internal ODT time based on bit 7-4
+#                with the considered SDRAM internal delay
+# bit 19-16:  8, internal ODT de-assertion based on bit 11-8
+#                with the considered SDRAM internal delay
+# bit 31-20:  0, required
+
+DATA 0xFFD0147c 0x00008452	# DDR2 SDRAM Timing High
+# bit 3-0:    2, M_ODT assertion same as bit 11-8
+# bit 7-4:    5, M_ODT de-assertion same as bit 15-12
+# bit 11-8:   4, internal ODT assertion 2 cycles after write start command
+#                with the considered SDRAM internal delay
+# bit 15-12:  8, internal ODT de-assertion 5 cycles after write start command
+#                with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+# bit 23-0:   0, reserved
+# bit 31-24:  0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit 0:      1, Window enabled
+# bit 1:      0, Write Protect disabled
+# bit 3-2:    0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit 3-0:     0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4:     0, ODT0Rd, MODT[1] not asserted
+# bit 11-8:    0, required
+# big 15-11:   0, required
+# bit 19-16:   1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20:   0, ODT0Wr, MODT[1] not asserted
+# bit 27-24:   0, required
+# bit 31-28:   0, required
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit 1-0:     0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2:     0, ODT1 controlled by register
+# bit 31-4:    0, required
+
+DATA 0xFFD0149C 0x0000E801	# CPU ODT Control
+# bit 3-0:     1, ODTRd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4:     0, ODTWr, Internal ODT not asserted during write to DRAM
+# bit 9-8:     0, ODTEn, controlled by ODTRd and ODTWr
+# bit 11-10:   2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12:   2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14:      1, STARTBURST ODT enabled
+# bit 15:      1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit 0:       1, enable DDR init upon this register write
+# bit 31-1:    0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/keymile/km_arm/kwbimage_256M8_1.cfg b/roms/u-boot/board/keymile/km_arm/kwbimage_256M8_1.cfg
new file mode 100644
index 000000000..91ea5f007
--- /dev/null
+++ b/roms/u-boot/board/keymile/km_arm/kwbimage_256M8_1.cfg
@@ -0,0 +1,257 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2012
+# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
+# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com
+# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+# This configuration applies to COGE5 design (ARM-part)
+# Two 8-Bit devices are connected on the 16-Bit bus on the same
+# chip-select. The supported devices are
+#   MT47H256M8EB-3IT:C
+#   MT47H256M8EB-25EIT:C
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222	# MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_MOSI (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_MISO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300	# MPP Control 1 Register
+# bit 3-0:   0, MPPSel8	 GPIO[8] CPU_SDA bitbanged
+# bit 7-4:   0, MPPSel9  GPIO[9] CPU_SCL bitbanged
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 GPIO[14]
+# bit 27-24: 3, MPPSel14 GPIO[15]
+# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 11-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5-3:   3, Reserved
+# bit 6:     0, Reserved
+# bit 7:     0, RGMII-pads voltage = 3.3V
+# bit 10-8:  3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14:    0, Reserved
+# bit 15:    0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16  0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
+# bit 0-1:   2, Tag RAM RTC RAM0
+# bit 3-2:   1, Tag RAM WTC RAM0
+# bit 7-4:   6, Reserved
+# bit 9-8:   2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
+# bit 15-0:  ?, Reserved
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ?,Reserved
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
+# bit 13-0:  0x4E0, DDR2 clks refresh rate
+# bit 14:    0, reserved
+# bit 15:    0, reserved
+# bit 16:    0, CPU to Dram Write buffer policy
+# bit 17:    0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24:    1, enable exit self refresh mode on DDR access
+# bit 25:    1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000	# DDR Controller Control Low
+# bit 3-0:   0, reserved
+# bit 4:     0, 2T mode =addr/cmd in same cycle
+# bit 5:     0, clk is driven during self refresh, we don't care for APX
+# bit 6:     0, use recommended falling edge of clk for addr/cmd
+# bit 7-11:  0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14:    0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18:    1, cpu lock transaction enabled
+# bit 19:    0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
+# bit 30-28: 3, required
+# bit 31:    0, no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2202444E	# DDR Timing (Low) (active cycles value +1)
+# bit 3-0:   0xe, TRAS = 45ns -> 15 clk cycles
+# bit 7-4:   0x4, TRCD = 15ns -> 5 clk cycles
+# bit 11-8:  0x4, TRP = 15ns -> 5 clk cycles
+# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
+# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
+# bit 20:      0, extended TRAS msb
+# bit 23-21:   0, reserved
+# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
+# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
+
+DATA 0xFFD0140C 0x0000003E	#  DDR Timing (High)
+# bit 6-0:   0x3E, TRFC = 195ns -> 63 clk cycles
+# bit 8-7:      0, TR2R
+# bit 10-9:     0, TR2W
+# bit 12-11:    0, TW2W
+# bit 31-13:    0, reserved
+
+DATA 0xFFD01410 0x00000000	#  DDR Address Control
+# bit 1-0:    0, Cs0width=x8 (2 devices)
+# bit 3-2:    0, Cs0size=2Gb
+# bit 5-4:    0, Cs1width=nonexistent
+# bit 7-6:    0, Cs1size =nonexistent
+# bit 9-8:    0, Cs2width=nonexistent
+# bit 11-10:  0, Cs2size =nonexistent
+# bit 13-12:  0, Cs3width=nonexistent
+# bit 15-14:  0, Cs3size =nonexistent
+# bit 16:     0, Cs0AddrSel
+# bit 17:     0, Cs1AddrSel
+# bit 18:     0, Cs2AddrSel
+# bit 19:     0, Cs3AddrSel
+# bit 31-20:  0, required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit 0:      0,  OpenPage enabled
+# bit 31-1:   0, required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit 3-0:    0, DDR cmd
+# bit 31-4:   0, required
+
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+# bit 2-0:    2, Burst Length = 4
+# bit 3:      0, Burst Type
+# bit 6-4:    5, CAS Latency = 5
+# bit 7:      0, Test mode
+# bit 8:      0, DLL Reset
+# bit 11-9:   3, Write recovery for auto-precharge must be 3
+# bit 12:     0, Active power down exit time, fast exit
+# bit 14-13:  0, reserved
+# bit 31-15:  0, reserved
+
+DATA 0xFFD01420 0x00000006	#  DDR Extended Mode
+# bit 0:      0, DDR DLL enabled
+# bit 1:      1, DDR drive strenght reduced
+# bit 2:      1, DDR ODT control lsb, 75ohm termination [RTT0]
+# bit 5-3:    0, required
+# bit 6:      0, DDR ODT control msb, 75ohm termination [RTT1]
+# bit 9-7:    0, required
+# bit 10:     0, differential DQS enabled
+# bit 11:     0, required
+# bit 12:     0, DDR output buffer enabled
+# bit 31-13:  0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit 2-0:    7, required
+# bit 3:      1, MBUS Burst Chop disabled
+# bit 6-4:    7, required
+# bit 7:      0, reserved
+# bit 8:      1, add sample stage required for > 266Mhz
+# bit 9:      0, no half clock cycle addition to dataout
+# bit 10:     0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11:     0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16:  0, required
+
+DATA 0xFFD01428 0x00084520	# DDR2 SDRAM Timing Low
+# bit 3-0:    0, required
+# bit 7-4:    2, M_ODT assertion 2 cycles after read start command
+# bit 11-8:   5, M_ODT de-assertion 5 cycles after read start command
+#                (ODT turn off delay 2,5 clk cycles)
+# bit 15-12:  4, internal ODT time based on bit 7-4
+#                with the considered SDRAM internal delay
+# bit 19-16:  8, internal ODT de-assertion based on bit 11-8
+#                with the considered SDRAM internal delay
+# bit 31-20:  0, required
+
+DATA 0xFFD0147c 0x00008452	# DDR2 SDRAM Timing High
+# bit 3-0:    2, M_ODT assertion same as bit 11-8
+# bit 7-4:    5, M_ODT de-assertion same as bit 15-12
+# bit 11-8:   4, internal ODT assertion 2 cycles after write start command
+#                with the considered SDRAM internal delay
+# bit 15-12:  8, internal ODT de-assertion 5 cycles after write start command
+#                with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+# bit 23-0:   0, reserved
+# bit 31-24:  0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x1FFFFFF1	# CS[0]n Size
+# bit 0:      1, Window enabled
+# bit 1:      0, Write Protect disabled
+# bit 3-2:    0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24:0x1F, Size (i.e. 512MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit 3-0:     0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4:     0, ODT0Rd, MODT[1] not asserted
+# bit 11-8:    0, required
+# big 15-11:   0, required
+# bit 19-16:   1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20:   0, ODT0Wr, MODT[1] not asserted
+# bit 27-24:   0, required
+# bit 31-28:   0, required
+
+DATA 0xFFD01498 0x00000004	#  DDR ODT Control (High)
+# bit 1-0:     0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2:     1, ODT1 never active
+# bit 31-4:    0, required
+
+DATA 0xFFD0149C 0x0000E801	# CPU ODT Control
+# bit 3-0:     1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4:     0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
+# bit 9-8:     0, ODTEn, controlled by ODT0Rd and ODT0Wr
+# bit 11-10:   2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12:   2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14:      1, STARTBURST ODT enabled
+# bit 15:      1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit 0:       1, enable DDR init upon this register write
+# bit 31-1:    0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/keymile/kmcent2/Kconfig b/roms/u-boot/board/keymile/kmcent2/Kconfig
new file mode 100644
index 000000000..848d230fb
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmcent2/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_KMCENT2
+
+config SYS_BOARD
+	default "kmcent2"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_CONFIG_NAME
+	default "kmcent2"
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select ARCH_T1040
+	select PHYS_64BIT
+
+endif
diff --git a/roms/u-boot/board/keymile/kmcent2/MAINTAINERS b/roms/u-boot/board/keymile/kmcent2/MAINTAINERS
new file mode 100644
index 000000000..142647555
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmcent2/MAINTAINERS
@@ -0,0 +1,8 @@
+KMCENT2 BOARD
+M:	Niel Fourie <lusus@denx.de>
+S:	Maintained
+F:	board/keymile/kmcent2/
+F:	include/configs/kmcent2.h
+F:	configs/kmcent2_defconfig
+F:	arch/powerpc/dts/kmcent2.dts
+F:	arch/powerpc/dts/kmcent2-u-boot.dtsi
diff --git a/roms/u-boot/board/keymile/kmcent2/Makefile b/roms/u-boot/board/keymile/kmcent2/Makefile
new file mode 100644
index 000000000..6b26e861f
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmcent2/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier:	GPL-2.0+
+# (C) Copyright 2016 Keymile AG
+# Rainer Boschung <rainer.boschung@keymile.com>
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+
+obj-y	+= kmcent2.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-y	+= ../common/common.o
+obj-y	+= ../common/ivm.o
+obj-y	+= ../common/qrio.o
diff --git a/roms/u-boot/board/keymile/kmcent2/ddr.c b/roms/u-boot/board/keymile/kmcent2/ddr.c
new file mode 100644
index 000000000..4f778206f
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmcent2/ddr.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+#include <asm/mpc85xx_gpio.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DQSn_POS(n)		(3 - (((n) - 1) % 4)) * 8
+#define DQSn_START(n, start)	((start) << DQSn_POS(n))
+
+void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+
+	/* 1/2 clk delay between wr command and data strobe */
+	popts->write_data_delay = 4;
+	/* clk lauched 1/2 applied cylcle after address command */
+	popts->clk_adjust = 4;
+	/* 1T timing: command/address held for only 1 cycle */
+	popts->twot_en = 0;
+	popts->threet_en = 0;
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x3b;
+
+	/* we have only one module, half str should be OK */
+	popts->half_strength_driver_enable = 1;
+	/*
+	 * Write leveling override
+	 */
+	/* set for DDR3-1600 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x7;
+	/* DQS write leveling start time according layout */
+	popts->wrlvl_ctl_2 = (DQSn_START(1, 0x06) |
+			      DQSn_START(2, 0x06) |
+			      DQSn_START(3, 0x07) |
+			      DQSn_START(4, 0x07));
+	popts->wrlvl_ctl_3 = (DQSn_START(5, 0x07) |
+			      DQSn_START(6, 0x08) |
+			      DQSn_START(7, 0x08) |
+			      DQSn_START(8, 0x08));
+
+	/*
+	 * rtt and wtt_wr override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+int dram_init(void)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/keymile/kmcent2/kmcent2.c b/roms/u-boot/board/keymile/kmcent2/kmcent2.c
new file mode 100644
index 000000000..4f5164e63
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmcent2/kmcent2.c
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <asm/cache.h>
+#include <asm/fsl_fdt.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_liodn.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <fdt_support.h>
+#include <fm_eth.h>
+#include <hwconfig.h>
+#include <image.h>
+#include <linux/compiler.h>
+#include <net.h>
+#include <netdev.h>
+#include <vsc9953.h>
+
+#include "../common/common.h"
+#include "../common/qrio.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
+int checkboard(void)
+{
+	printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME);
+
+	return 0;
+}
+
+#define RSTRQSR1_WDT_RR	0x00200000
+#define RSTRQSR1_SW_RR	0x00100000
+
+int board_early_init_f(void)
+{
+	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	bool cpuwd_flag = false;
+
+	/* board specific IFC configuration: increased bus turnaround time */
+	setbits_be32(&ifc.gregs->ifc_gcr, 8 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+	/* configure mode for uP reset request */
+	qrio_uprstreq(UPREQ_CORE_RST);
+
+	/* board only uses the DDR_MCK0, so disable the DDR_MCK1 */
+	setbits_be32(&gur->ddrclkdr, 0x40000000);
+
+	/* set reset reason according CPU register */
+	if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+	    RSTRQSR1_WDT_RR)
+		cpuwd_flag = true;
+
+	qrio_cpuwd_flag(cpuwd_flag);
+	/* clear CPU bits by writing 1 */
+	setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
+
+	/* configure PRST lines for the application: */
+	/*
+	 * ETHSW_DDR_RST:
+	 * reset at power-up and unit reset only and enable WD on it
+	 */
+	qrio_prstcfg(KM_ETHSW_DDR_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_wdmask(KM_ETHSW_DDR_RST, true);
+	/*
+	 * XES_PHY_RST:
+	 * reset at power-up and unit reset only and enable WD on it
+	 */
+	qrio_prstcfg(KM_XES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_wdmask(KM_XES_PHY_RST, true);
+	/*
+	 * ES_PHY_RST:
+	 * reset at power-up and unit reset only and enable WD on it
+	 */
+	qrio_prstcfg(KM_ES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_wdmask(KM_ES_PHY_RST, true);
+	/*
+	 * EFE_RST:
+	 * reset at power-up and unit reset only and enable WD on it
+	 */
+	qrio_prstcfg(KM_EFE_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_wdmask(KM_EFE_RST, true);
+	/*
+	 * BFTIC4_RST:
+	 * reset at power-up and unit reset only and enable WD on it
+	 */
+	qrio_prstcfg(KM_BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_wdmask(KM_BFTIC4_RST, true);
+	/*
+	 * DPAXE_RST:
+	 * reset at power-up and unit reset only and enable WD on it
+	 */
+	qrio_prstcfg(KM_DPAXE_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_wdmask(KM_DPAXE_RST, true);
+	/*
+	 * PEXSW_RST:
+	 * reset at power-up and unit reset only, deassert reset w/o WD
+	 */
+	qrio_prstcfg(KM_PEXSW_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_prst(KM_PEXSW_RST, false, false);
+	/*
+	 * PEXSW_NT_RST:
+	 * reset at power-up and unit reset only, deassert reset w/o WD
+	 */
+	qrio_prstcfg(KM_PEXSW_NT_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_prst(KM_PEXSW_NT_RST, false, false);
+	/*
+	 * BOBCAT_RST:
+	 * reset at power-up and unit reset only, deassert reset w/o WD
+	 */
+	qrio_prstcfg(KM_BOBCAT_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_prst(KM_BOBCAT_RST, false, false);
+	/*
+	 * FEMT_RST:
+	 * reset at power-up and unit reset only and enable WD
+	 */
+	qrio_prstcfg(KM_FEMT_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_wdmask(KM_FEMT_RST, true);
+	/*
+	 * FOAM_RST:
+	 * reset at power-up and unit reset only and enable WD
+	 */
+	qrio_prstcfg(KM_FOAM_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_wdmask(KM_FOAM_RST, true);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	int ret = 0;
+
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 2;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash */
+		disable_tlb(flash_esel);
+	}
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	set_liodns();
+	setup_qbman_portals();
+
+	qrio_set_leds();
+
+	/* enable Application Buffer */
+	qrio_enable_app_buffer();
+
+	return ret;
+}
+
+unsigned long get_serial_clock(unsigned long dummy)
+{
+	return (gd->bus_clk / 2);
+}
+
+unsigned long get_board_sys_clk(unsigned long dummy)
+{
+	return 66666666;
+}
+
+int misc_init_f(void)
+{
+	/* configure QRIO pis for i2c deblocking */
+	i2c_deblock_gpio_cfg();
+
+	/*
+	 * CFE_RST (front phy):
+	 * reset at power-up, unit and core reset, deasset reset w/o WD
+	 */
+	qrio_prstcfg(KM_CFE_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+	qrio_prst(KM_CFE_RST, false, false);
+
+	/*
+	 * ZL30158_RST (PTP clock generator):
+	 * reset at power-up only, deassert reset and enable WD on it
+	 */
+	qrio_prstcfg(KM_ZL30158_RST, PRSTCFG_POWUP_RST);
+	qrio_prst(KM_ZL30158_RST, false, false);
+
+	/*
+	 * ZL30364_RST (EEC generator):
+	 * reset at power-up only, deassert reset and enable WD on it
+	 */
+	qrio_prstcfg(KM_ZL30364_RST, PRSTCFG_POWUP_RST);
+	qrio_prst(KM_ZL30364_RST, false, false);
+
+	return 0;
+}
+
+#define USED_SRDS_BANK 0
+#define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100
+
+#define BRG01_IOCLK12	0x02000000
+#define EC2_GTX_CLK125	0x08000000
+
+int misc_init_r(void)
+{
+	serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG;
+	ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* check SERDES bank 0 reference clock */
+	u32 actual = in_be32(&regs->bank[USED_SRDS_BANK].pllcr0);
+
+	if (actual & SRDS_PLLCR0_POFF)
+		printf("Warning: SERDES bank %u pll is off\n", USED_SRDS_BANK);
+	if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) {
+		printf("Warning: SERDES bank %u expects %sMHz clock, is %sMHz\n",
+		       USED_SRDS_BANK,
+		       serdes_clock_to_string(EXPECTED_SRDS_RFCK),
+		       serdes_clock_to_string(actual));
+	}
+
+	/* QE IO clk : BRG01 is used over clk12 for HDLC clk (20 MhZ) */
+	out_be32(&scfg->qeioclkcr,
+		 in_be32(&scfg->qeioclkcr) | BRG01_IOCLK12);
+
+	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+			CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
+
+	/* Fix polarity of Card Detect and Write Protect */
+	out_be32(&gur->sdhcpcr, 0xFFFFFFFF);
+
+	/*
+	 * EC1 is disabled in our design, so we must explicitly set GTXCLKSEL
+	 * to EC2
+	 */
+	out_be32(&scfg->emiiocr, in_be32(&scfg->emiiocr) | EC2_GTX_CLK125);
+
+	return 0;
+}
+
+int hush_init_var(void)
+{
+	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	const char *kmem;
+	/* DIP switch support on BFTIC */
+	struct bfticu_iomap *bftic4 =
+		(struct bfticu_iomap *)SYS_BFTIC_BASE;
+	u8 dip_switch = in_8((u8 *)&bftic4->mswitch) & BFTICU_DIPSWITCH_MASK;
+
+	if (dip_switch != 0) {
+		/* start bootloader */
+		puts("DIP:   Enabled\n");
+		env_set("actual_bank", "0");
+	}
+
+	set_km_env();
+
+	/*
+	 * bootm_size is used to fixup the FDT memory node
+	 * set it to kernelmem that has the same value
+	 */
+	kmem = env_get("kernelmem");
+	if (kmem)
+		env_set("bootm_size", kmem);
+
+	return 0;
+}
+
+void fdt_fixup_fman_mac_addresses(void *blob)
+{
+	int node, ret;
+	char path[24];
+	unsigned char mac_addr[6];
+
+	/*
+	 * Just the fm1-mac5 must be set by us, u-boot handle the 2 others,
+	 * get the mac addr from env
+	 */
+	if (!eth_env_get_enetaddr_by_index("eth", 4, mac_addr)) {
+		printf("eth4addr env variable not defined\n");
+		return;
+	}
+
+	/* local management port */
+	strcpy(path, "/soc/fman/ethernet@e8000");
+	node = fdt_path_offset(blob, path);
+	if (node < 0) {
+		printf("no %s\n", path);
+		return;
+	}
+
+	ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+	if (ret) {
+		printf("%s\n\terror setting local-mac-address property\n",
+		       path);
+	}
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	fdt_fixup_liodn(blob);
+
+	fdt_fixup_fman_mac_addresses(blob);
+
+	if (hwconfig("qe-tdm"))
+		fdt_del_diu(blob);
+	return 0;
+}
+
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT	QRIO_GPIO_A
+#define SELFTEST_PIN	0
+
+int post_hotkeys_pressed(void)
+{
+	qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+	return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
diff --git a/roms/u-boot/board/keymile/kmcent2/law.c b/roms/u-boot/board/keymile/kmcent2/law.c
new file mode 100644
index 000000000..aa0f29f44
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmcent2/law.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <config.h>
+#include <asm/fsl_law.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+	SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC),
+/* other application LAW are not used in u-boot */
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/keymile/kmcent2/tlb.c b/roms/u-boot/board/keymile/kmcent2/tlb.c
new file mode 100644
index 000000000..dbd3b9b06
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmcent2/tlb.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <asm/mmu.h>
+#include <asm/u-boot.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
+		      0, 2, BOOKE_PAGESZ_128M, 1),
+
+	/* *I*G* - PCI1 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI1 I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 5, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 6, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 7, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 8, BOOKE_PAGESZ_16M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 9, BOOKE_PAGESZ_4M, 1),
+
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 10, BOOKE_PAGESZ_64K, 1),
+	/* QRIO */
+	SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
+		      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 11, BOOKE_PAGESZ_64K, 1),
+	/* MRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
+		      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 12, BOOKE_PAGESZ_128M, 1),
+	/* BFTIC */
+	SET_TLB_ENTRY(1, SYS_BFTIC_BASE, SYS_BFTIC_BASE_PHYS,
+		      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 13, BOOKE_PAGESZ_128M, 1),
+	/*
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so do not use them here!!.
+	 */
+	/* PAXE */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
+		      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 16, BOOKE_PAGESZ_128M, 1)
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/keymile/kmp204x/Kconfig b/roms/u-boot/board/keymile/kmp204x/Kconfig
new file mode 100644
index 000000000..f74d4295c
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmp204x/Kconfig
@@ -0,0 +1,20 @@
+if TARGET_KMP204X
+
+config SYS_BOARD
+	default "kmp204x"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_CONFIG_NAME
+	default "kmp204x"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_P2041
+	select FSL_DDR_INTERACTIVE
+	select PHYS_64BIT
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+endif
diff --git a/roms/u-boot/board/keymile/kmp204x/MAINTAINERS b/roms/u-boot/board/keymile/kmp204x/MAINTAINERS
new file mode 100644
index 000000000..8b9afffdc
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmp204x/MAINTAINERS
@@ -0,0 +1,6 @@
+KMP204X BOARD
+M:	Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
+S:	Maintained
+F:	board/keymile/kmp204x/
+F:	include/configs/kmp204x.h
+F:	configs/kmcoge4_defconfig
diff --git a/roms/u-boot/board/keymile/kmp204x/Makefile b/roms/u-boot/board/keymile/kmp204x/Makefile
new file mode 100644
index 000000000..5523ee99a
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmp204x/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+
+obj-y	:= kmp204x.o ddr.o eth.o tlb.o pci.o law.o ../common/common.o\
+		../common/ivm.o ../common/qrio.o
diff --git a/roms/u-boot/board/keymile/kmp204x/ddr.c b/roms/u-boot/board/keymile/kmp204x/ddr.c
new file mode 100644
index 000000000..77a00c55c
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmp204x/ddr.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	if (ctrl_num) {
+		printf("Wrong parameter for controller number %d", ctrl_num);
+		return;
+	}
+
+	/* automatic calibration for nb of cycles between read and DQS pre */
+	popts->cpo_override = 0xFF;
+
+	/* 1/2 clk delay between wr command and data strobe */
+	popts->write_data_delay = 4;
+	/* clk lauched 1/2 applied cylcle after address command */
+	popts->clk_adjust = 4;
+	/* 1T timing: command/address held for only 1 cycle */
+	popts->twot_en = 0;
+
+	/* we have only one module, half str should be OK */
+	popts->half_strength_driver_enable = 1;
+
+	/* wrlvl values overridden as recommended by ddr init func */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x6;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
+}
+
+int dram_init(void)
+{
+	phys_size_t dram_size = 0;
+
+	puts("Initializing with SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	debug("    DDR: ");
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/keymile/kmp204x/eth.c b/roms/u-boot/board/keymile/kmp204x/eth.c
new file mode 100644
index 000000000..29c5b339a
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmp204x/eth.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <phy.h>
+
+int board_eth_init(struct bd_info *bis)
+{
+	int ret = 0;
+#ifdef CONFIG_FMAN_ENET
+	struct fsl_pq_mdio_info dtsec_mdio_info;
+
+	printf("Initializing Fman\n");
+
+	dtsec_mdio_info.regs =
+		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+	/* DTESC1/2 don't have a PHY, they are temporarily disabled
+	 * so that u-boot doesn't try to unsuccessfuly enable them */
+	fm_disable_port(FM1_DTSEC1);
+	fm_disable_port(FM1_DTSEC2);
+
+	/*
+	 * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf
+	 * This is the debug interface, the only one used in u-boot
+	 */
+	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+	fm_info_set_mdio(FM1_DTSEC5,
+			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+
+	ret = cpu_eth_init(bis);
+
+	/* reenable DTSEC1/2 for later (kernel) */
+	fm_enable_port(FM1_DTSEC1);
+	fm_enable_port(FM1_DTSEC2);
+#endif
+
+	return ret;
+}
+
+#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL)
+
+#define mv88E1118_PAGE_REG	22
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) {
+		/* driver config is good */
+		if (phydev->drv->config)
+			phydev->drv->config(phydev);
+
+		/* but we still need to fix the LEDs */
+		phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840);
+		phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000);
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/keymile/kmp204x/kmp204x.c b/roms/u-boot/board/keymile/kmp204x/kmp204x.c
new file mode 100644
index 000000000..29dde7a80
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmp204x/kmp204x.c
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2011,2012 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <image.h>
+#include <init.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/common.h"
+#include "../common/qrio.h"
+#include "kmp204x.h"
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
+int checkboard(void)
+{
+	printf("Board: Keymile %s\n", CONFIG_SYS_CONFIG_NAME);
+
+	return 0;
+}
+
+#define ZL30158_RST	8
+#define BFTIC4_RST	0
+#define RSTRQSR1_WDT_RR	0x00200000
+#define RSTRQSR1_SW_RR	0x00100000
+
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	bool cpuwd_flag = false;
+
+	/* configure mode for uP reset request */
+	qrio_uprstreq(UPREQ_CORE_RST);
+
+	/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
+	setbits_be32(&gur->ddrclkdr, 0x001f000f);
+
+	/* set reset reason according CPU register */
+	if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+	    RSTRQSR1_WDT_RR)
+		cpuwd_flag = true;
+
+	qrio_cpuwd_flag(cpuwd_flag);
+	/* clear CPU bits by writing 1 */
+	setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
+
+	/* set the BFTIC's prstcfg to reset at power-up and unit reset only */
+	qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+	/* and enable WD on it */
+	qrio_wdmask(BFTIC4_RST, true);
+
+	/* set the ZL30138's prstcfg to reset at power-up only */
+	qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
+	/* and take it out of reset as soon as possible (needed for Hooper) */
+	qrio_prst(ZL30158_RST, false, false);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	int ret = 0;
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	set_liodns();
+	setup_qbman_portals();
+
+	ret = trigger_fpga_config();
+	if (ret)
+		printf("error triggering PCIe FPGA config\n");
+
+	/* enable the Unit LED (red) & Boot LED (on) */
+	qrio_set_leds();
+
+	/* enable Application Buffer */
+	qrio_enable_app_buffer();
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(unsigned long dummy)
+{
+	return 66666666;
+}
+
+#define ETH_FRONT_PHY_RST	15
+#define QSFP2_RST		11
+#define QSFP1_RST		10
+#define ZL30343_RST		9
+
+int misc_init_f(void)
+{
+	/* configure QRIO pis for i2c deblocking */
+	i2c_deblock_gpio_cfg();
+
+	/* configure the front phy's prstcfg and take it out of reset */
+	qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+	qrio_prst(ETH_FRONT_PHY_RST, false, false);
+
+	/* set the ZL30343 prstcfg to reset at power-up only */
+	qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
+	/* and enable the WD on it */
+	qrio_wdmask(ZL30343_RST, true);
+
+	/* set the QSFPs' prstcfg to reset at power-up and unit rst only */
+	qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
+
+	/* and enable the WD on them */
+	qrio_wdmask(QSFP1_RST, true);
+	qrio_wdmask(QSFP2_RST, true);
+
+	return 0;
+}
+
+#define NUM_SRDS_BANKS	2
+
+int misc_init_r(void)
+{
+	serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
+		SRDS_PLLCR0_RFCK_SEL_125};
+	unsigned int i;
+
+	/* check SERDES reference clocks */
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		u32 actual = in_be32(&regs->bank[i].pllcr0);
+		actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (actual != expected[i]) {
+			printf("Warning: SERDES bank %u expects reference \
+			       clock %sMHz, but actual is %sMHz\n", i + 1,
+			       serdes_clock_to_string(expected[i]),
+			       serdes_clock_to_string(actual));
+		}
+	}
+
+	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+			CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
+	return 0;
+}
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_LAST_STAGE_INIT)
+
+int last_stage_init(void)
+{
+#if defined(CONFIG_KMCOGE4)
+	/* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
+	struct bfticu_iomap *bftic4 =
+		(struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
+	u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
+
+	if (dip_switch != 0) {
+		/* start bootloader */
+		puts("DIP:   Enabled\n");
+		env_set("actual_bank", "0");
+	}
+#endif
+	set_km_env();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+void fdt_fixup_fman_mac_addresses(void *blob)
+{
+	int node, i, ret;
+	char *tmp, *end;
+	unsigned char mac_addr[6];
+
+	/* get the mac addr from env */
+	tmp = env_get("ethaddr");
+	if (!tmp) {
+		printf("ethaddr env variable not defined\n");
+		return;
+	}
+	for (i = 0; i < 6; i++) {
+		mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+		if (tmp)
+			tmp = (*end) ? end+1 : end;
+	}
+
+	/* find the correct fdt ethernet path and correct it */
+	node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
+	if (node < 0) {
+		printf("no /soc/fman/ethernet path offset\n");
+		return;
+	}
+	ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
+	if (ret) {
+		printf("error setting local-mac-address property\n");
+		return;
+	}
+}
+#endif
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+	fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_fman_mac_addresses(blob);
+#endif
+
+	return 0;
+}
+
+#if defined(CONFIG_POST)
+
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT	QRIO_GPIO_A
+#define SELFTEST_PIN	31
+
+int post_hotkeys_pressed(void)
+{
+	qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+	return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
+#endif
diff --git a/roms/u-boot/board/keymile/kmp204x/kmp204x.h b/roms/u-boot/board/keymile/kmp204x/kmp204x.h
new file mode 100644
index 000000000..3b858a557
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmp204x/kmp204x.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ */
+
+
+void pci_of_setup(void *blob, struct bd_info *bd);
diff --git a/roms/u-boot/board/keymile/kmp204x/law.c b/roms/u-boot/board/keymile/kmp204x/law.c
new file mode 100644
index 000000000..2d83dfea1
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmp204x/law.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#endif
+	SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
+	SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
+	SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/keymile/kmp204x/pbi.cfg b/roms/u-boot/board/keymile/kmp204x/pbi.cfg
new file mode 100644
index 000000000..3fdfb47ab
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmp204x/pbi.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Configure ALTCBAR for DCSR -> DCSR@89000000
+091380c0 000009C4
+09000010 00000000
+091380c0 000009C4
+09000014 00000000
+091380c0 000009C4
+09000018 81d00000
+#Workaround for A-004849
+091380c0 000009C4
+890B0050 00000002
+091380c0 000009C4
+890B0054 00000002
+091380c0 000009C4
+890B0058 00000002
+091380c0 000009C4
+890B005C 00000002
+091380c0 000009C4
+890B0090 00000002
+091380c0 000009C4
+890B0094 00000002
+091380c0 000009C4
+890B0098 00000002
+091380c0 000009C4
+890B009C 00000002
+091380c0 000009C4
+890B0108 00000012
+091380c0 000009C4
+#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
+89021008 0000f000
+091380c0 000009C4
+89021028 0000f000
+091380c0 000009C4
+89021048 0000f000
+091380c0 000009C4
+89021068 0000f000
+091380c0 000009C4
+#Flush PBL data
+09138000 00000000
+#Disable ALTCBAR
+09000018 00000000
+091380c0 000009C4
+#Initialize CPC1 as 1MB SRAM
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+09010100 00000000
+09010104 fff0000b
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff00000
+09000d08 81000013
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 27170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/roms/u-boot/board/keymile/kmp204x/pci.c b/roms/u-boot/board/keymile/kmp204x/pci.c
new file mode 100644
index 000000000..cdb498da0
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmp204x/pci.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+#include <linux/errno.h>
+
+#include "../common/qrio.h"
+#include "kmp204x.h"
+
+#define PROM_SEL_L	11
+/* control the PROM_SEL_L signal*/
+static void toggle_fpga_eeprom_bus(bool cpu_own)
+{
+	qrio_gpio_direction_output(QRIO_GPIO_A, PROM_SEL_L, !cpu_own);
+}
+
+#define CONF_SEL_L	10
+#define FPGA_PROG_L	19
+#define FPGA_DONE	18
+#define FPGA_INIT_L	17
+
+int trigger_fpga_config(void)
+{
+	int ret = 0, init_l;
+	/* approx 10ms */
+	u32 timeout = 10000;
+
+	/* make sure the FPGA_can access the EEPROM */
+	toggle_fpga_eeprom_bus(false);
+
+	/* assert CONF_SEL_L to be able to drive FPGA_PROG_L */
+	qrio_gpio_direction_output(QRIO_GPIO_A, CONF_SEL_L, 0);
+
+	/* trigger the config start */
+	qrio_gpio_direction_output(QRIO_GPIO_A, FPGA_PROG_L, 0);
+
+	/* small delay for INIT_L line */
+	udelay(10);
+
+	/* wait for FPGA_INIT to be asserted */
+	do {
+		init_l = qrio_get_gpio(QRIO_GPIO_A, FPGA_INIT_L);
+		if (timeout-- == 0) {
+			printf("FPGA_INIT timeout\n");
+			ret = -EFAULT;
+			break;
+		}
+		udelay(10);
+	} while (init_l);
+
+	/* deassert FPGA_PROG, config should start */
+	qrio_set_gpio(QRIO_GPIO_A, FPGA_PROG_L, 1);
+
+	return ret;
+}
+
+/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
+static int wait_for_fpga_config(void)
+{
+	int ret = 0, done;
+	/* approx 5 s */
+	u32 timeout = 500000;
+
+	printf("PCIe FPGA config:");
+	do {
+		done = qrio_get_gpio(QRIO_GPIO_A, FPGA_DONE);
+		if (timeout-- == 0) {
+			printf(" FPGA_DONE timeout\n");
+			ret = -EFAULT;
+			goto err_out;
+		}
+		udelay(10);
+	} while (!done);
+
+	printf(" done\n");
+
+err_out:
+	/* deactive CONF_SEL and give the CPU conf EEPROM access */
+	qrio_set_gpio(QRIO_GPIO_A, CONF_SEL_L, 1);
+	toggle_fpga_eeprom_bus(true);
+
+	return ret;
+}
+
+#define PCIE_SW_RST	14
+#define PEXHC_RST	13
+#define HOOPER_RST	12
+
+void pci_init_board(void)
+{
+	qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+	qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+	qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+
+	/* wait for the PCIe FPGA to be configured
+	 * it has been triggered earlier in board_early_init_r */
+	if (wait_for_fpga_config())
+		printf("error finishing PCIe FPGA config\n");
+
+	qrio_prst(PCIE_SW_RST, false, false);
+	qrio_prst(PEXHC_RST, false, false);
+	qrio_prst(HOOPER_RST, false, false);
+	/* Hooper is not direcly PCIe capable */
+	mdelay(50);
+
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, struct bd_info *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/roms/u-boot/board/keymile/kmp204x/rcw_kmp204x.cfg b/roms/u-boot/board/keymile/kmp204x/rcw_kmp204x.cfg
new file mode 100644
index 000000000..236d5138b
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmp204x/rcw_kmp204x.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for kmp204x boards
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+14600000 00000000 28200000 00000000
+148E70CF CFC02000 58000000 41000000
+00000000 00000000 00000000 F0428816
+00000000 00000000 00000000 00000000
diff --git a/roms/u-boot/board/keymile/kmp204x/tlb.c b/roms/u-boot/board/keymile/kmp204x/tlb.c
new file mode 100644
index 000000000..a268bd8e9
--- /dev/null
+++ b/roms/u-boot/board/keymile/kmp204x/tlb.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	/* TLB 1 */
+	/* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+	/* QRIO */
+	SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_64K, 1),
+	/* *I*G* - PCI1 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_512M, 1),
+	/* *I*G* - PCI3 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_512M, 1),
+	/* *I*G* - PCI1&3 I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_128K, 1),
+#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
+	/* LBAPP1 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256M, 1),
+#endif
+#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
+	/* LBAPP2 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_256M, 1),
+#endif
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 16, BOOKE_PAGESZ_32K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/keymile/pg-wcom-ls102xa/Kconfig b/roms/u-boot/board/keymile/pg-wcom-ls102xa/Kconfig
new file mode 100644
index 000000000..f0b5ceabb
--- /dev/null
+++ b/roms/u-boot/board/keymile/pg-wcom-ls102xa/Kconfig
@@ -0,0 +1,39 @@
+if TARGET_PG_WCOM_SELI8
+
+config SYS_BOARD
+	default "pg-wcom-ls102xa"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_SOC
+	default "ls102xa"
+
+config SYS_CONFIG_NAME
+	default "pg-wcom-seli8"
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	imply FS_CRAMFS
+
+endif
+
+if TARGET_PG_WCOM_EXPU1
+
+config SYS_BOARD
+	default "pg-wcom-ls102xa"
+
+config SYS_VENDOR
+	default "keymile"
+
+config SYS_SOC
+	default "ls102xa"
+
+config SYS_CONFIG_NAME
+	default "pg-wcom-expu1"
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	imply FS_CRAMFS
+
+endif
diff --git a/roms/u-boot/board/keymile/pg-wcom-ls102xa/MAINTAINERS b/roms/u-boot/board/keymile/pg-wcom-ls102xa/MAINTAINERS
new file mode 100644
index 000000000..26b202316
--- /dev/null
+++ b/roms/u-boot/board/keymile/pg-wcom-ls102xa/MAINTAINERS
@@ -0,0 +1,13 @@
+Hitachi Power Grids LS102XA BOARD
+M:	Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
+M:	Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
+M:	Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com>
+S:	Maintained
+F:	board/keymile/pg-wcom-ls102xa/
+F:	include/configs/km/pg-wcom-ls102xa.h
+F:	include/configs/pg-wcom-seli8.h
+F:	include/configs/pg-wcom-expu1.h
+F:	configs/pg_wcom_seli8_defconfig
+F:	configs/pg_wcom_expu1_defconfig
+F:	arch/arm/dts/ls1021a-pg-wcom-seli8.dts
+F:	arch/arm/dts/ls1021a-pg-wcom-expu1.dts
diff --git a/roms/u-boot/board/keymile/pg-wcom-ls102xa/Makefile b/roms/u-boot/board/keymile/pg-wcom-ls102xa/Makefile
new file mode 100644
index 000000000..229b0c282
--- /dev/null
+++ b/roms/u-boot/board/keymile/pg-wcom-ls102xa/Makefile
@@ -0,0 +1,11 @@
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+# Copyright 2021 Hitachi Power Grids. All rights reserved.
+#
+
+obj-y += pg-wcom-ls102xa.o ddr.o
+obj-y += ../common/common.o ../common/ivm.o ../common/qrio.o
+obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ../../freescale/common/ns_access.o
+obj-$(CONFIG_LS102XA_STREAM_ID) += ../../freescale/common/ls102xa_stream_id.o
+obj-$(CONFIG_ID_EEPROM) += ../../freescale/common/sys_eeprom.o
diff --git a/roms/u-boot/board/keymile/pg-wcom-ls102xa/ddr.c b/roms/u-boot/board/keymile/pg-wcom-ls102xa/ddr.c
new file mode 100644
index 000000000..4ec60f168
--- /dev/null
+++ b/roms/u-boot/board/keymile/pg-wcom-ls102xa/ddr.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 Hitachi Power Grids. All rights reserved.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/global_data.h>
+#include <asm/arch/ls102xa_soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+
+	// 1/2 DRAM cycle (should be increased in case of ADDR/CMD heavily loaded than the clock)
+	popts->clk_adjust = 0x4;
+	popts->write_data_delay = 0x4;
+	// wr leveling start value for lane 0
+	popts->wrlvl_start = 0x5;
+	// wr leveling start values for lanes 1-3 (lane 4 not there)
+	popts->wrlvl_ctl_2 = 0x05050500;
+	// 32-bit DRAM, no need to set start values for lanes we do not have (5-8)
+	popts->wrlvl_ctl_3 = 0x0;
+	popts->cpo_override = 0x1f;
+
+	/* force DDR bus width to 32 bits */
+	popts->data_bus_width = 1;
+	popts->otf_burst_chop_en = 0;
+	popts->burst_length = DDR_BL8;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 1;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	popts->cswl_override = DDR_CSWL_CS0;
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x58;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+int fsl_initdram(void)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing DDR....using SPD\n");
+	dram_size = fsl_ddr_sdram();
+
+	erratum_a008850_post();
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/roms/u-boot/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
new file mode 100644
index 000000000..db49e8ff2
--- /dev/null
+++ b/roms/u-boot/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Hitachi Power Grids. All rights reserved.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <fsl_sec.h>
+#include <fsl_devdis.h>
+#include <fsl_ddr.h>
+#include <spl.h>
+#include <fdt_support.h>
+#include <fsl_qe.h>
+#include <fsl_validate.h>
+
+#include "../common/common.h"
+#include "../common/qrio.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
+int checkboard(void)
+{
+	show_qrio();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return fsl_initdram();
+}
+
+int board_early_init_f(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+
+	/* Disable unused MCK1 */
+	setbits_be32(&gur->ddrclkdr, 2);
+
+	/* IFC Global Configuration */
+	setbits_be32(&ifc.gregs->ifc_gcr, 12 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+	setbits_be32(&ifc.gregs->ifc_ccr, IFC_CCR_CLK_DIV(3) |
+					  IFC_CCR_INV_CLK_EN);
+
+	/* clear BD & FR bits for BE BD's and frame data */
+	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+
+	init_early_memctl_regs();
+
+	/* QRIO Configuration */
+	qrio_uprstreq(UPREQ_CORE_RST);
+
+#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_SELI8)
+	qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_wdmask(KM_LIU_RST, true);
+
+	qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_wdmask(KM_PAXK_RST, true);
+#endif
+
+#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_EXPU1)
+	qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_wdmask(WCOM_TMG_RST, true);
+
+	qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_prst(WCOM_PHY_RST, false, false);
+
+	qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_wdmask(WCOM_QSFP_RST, true);
+
+	qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST);
+	qrio_prst(WCOM_CLIPS_RST, false, false);
+#endif
+	qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+	qrio_prst(KM_DBG_ETH_RST, false, false);
+
+	i2c_deblock_gpio_cfg();
+
+	/* enable the Unit LED (red) & Boot LED (on) */
+	qrio_set_leds();
+
+	/* enable Application Buffer */
+	qrio_enable_app_buffer();
+
+	arch_soc_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315))
+		erratum_a010315();
+
+	fsl_serdes_init();
+
+	ls102xa_smmu_stream_id_init();
+
+	u_qe_init();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	if (IS_ENABLED(CONFIG_FSL_DEVICE_DISABLE))
+		device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+
+	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+			CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	if (IS_ENABLED(CONFIG_PCI))
+		ft_pci_setup(blob, bd);
+
+	return 0;
+}
+
+#if defined(CONFIG_POST)
+int post_hotkeys_pressed(void)
+{
+	/* DIC26_SELFTEST: GPRTA0, GPA0 */
+	qrio_gpio_direction_input(QRIO_GPIO_A, 0);
+	return qrio_get_gpio(QRIO_GPIO_A, 0);
+}
+
+ulong post_word_load(void)
+{
+	/* POST word is located at the beginning of reserved physical RAM */
+	void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
+				gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
+	return in_le32(addr);
+}
+
+void post_word_store(ulong value)
+{
+	/* POST word is located at the beginning of reserved physical RAM */
+	void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
+				gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
+	out_le32(addr, value);
+}
+
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	/* Define only 1MiB range for mem_regions at the middle of the RAM */
+	/* For 1GiB range mem_regions takes approx. 4min */
+	*vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
+	*size = 1 << 20;
+	return 0;
+}
+#endif
+
+u8 flash_read8(void *addr)
+{
+	return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+	__raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 val = __raw_readw(addr);
+
+	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
+
+int hush_init_var(void)
+{
+	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	set_km_env();
+	return 0;
+}
diff --git a/roms/u-boot/board/keymile/scripts/README b/roms/u-boot/board/keymile/scripts/README
new file mode 100644
index 000000000..dd935b2c6
--- /dev/null
+++ b/roms/u-boot/board/keymile/scripts/README
@@ -0,0 +1,31 @@
+These scripts are needed for our development usecases. Copy this directory
+into your tftp root directory to be able to use this scripts.
+cp -r <u-boot-repo>/board/keymile/scripts <your_tftp_root>/
+
+To load and configure these usecase, two environment variables in the u-boot
+default environment must be parsed:
+run develop : setup environment to configure for rootfs via nfs
+run ramfs   : setup environment to configure for rootfs in ram
+
+Last change: 24.11.2011
+
+develop-common.txt
+============================
+This file defines variables for working with rootfs via nfs for powerpc and
+arm.
+
+develop-<arch>.txt
+============================
+This file defines architecture specific variables for working with rootfs via
+nfs arm.
+
+
+ramfs-common.txt
+============================
+This file defines variables for working with rootfs inside the ram for powerpc
+and arm.
+
+ramfs-<arch>.txt
+============================
+This file defines architecture specific variables for working with rootfs inside
+ram.
diff --git a/roms/u-boot/board/keymile/scripts/develop-arm.txt b/roms/u-boot/board/keymile/scripts/develop-arm.txt
new file mode 100644
index 000000000..4c12d3e1c
--- /dev/null
+++ b/roms/u-boot/board/keymile/scripts/develop-arm.txt
@@ -0,0 +1 @@
+setup_debug_env=tftpboot ${load_addr_r} scripts/develop-common.txt && env import -t ${load_addr_r} ${filesize} && run configure
diff --git a/roms/u-boot/board/keymile/scripts/develop-common.txt b/roms/u-boot/board/keymile/scripts/develop-common.txt
new file mode 100644
index 000000000..4384c0da3
--- /dev/null
+++ b/roms/u-boot/board/keymile/scripts/develop-common.txt
@@ -0,0 +1,12 @@
+altbootcmd=run ${subbootcmds}
+bootcmd=run ${subbootcmds}
+configure=run set_uimage; run set_tftppath; km_setboardid && run try_import_nfs_path && saveenv && reset
+subbootcmds=tftpfdt tftpkernel nfsargs add_default boot
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch}
+tftpfdt=if run set_fdthigh || test ${arch} != arm; then if tftpboot ${fdt_addr_r} ${tftppath}/fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; then; else tftpboot ${fdt_addr_r} ${tftppath}/${hostname}.dtb; fi; else true; fi
+tftpkernel=tftpboot ${load_addr_r} ${tftppath}/${uimage}
+toolchain=/opt/eldk
+rootfssize=0
+set_uimage=printenv uimage || setenv uimage uImage
+set_tftppath=if test ${hostname} = kmcoge5un; then setenv tftppath CI5UN; else if test ${hostname} = kmcoge5ne; then setenv tftppath CI5NE; else setenv tftppath ${IVM_Symbol}; fi; fi
+try_import_nfs_path=if tftpboot ${load_addr_r} ${tftppath}/nfs-path.txt; then env import -t ${load_addr_r} ${filesize}; else echo no auto nfs path imported; echo you can set nfsargs in /tftpboot/${tftppath}/nfs-path.txt and rerun develop; fi
diff --git a/roms/u-boot/board/keymile/scripts/develop-ppc_82xx.txt b/roms/u-boot/board/keymile/scripts/develop-ppc_82xx.txt
new file mode 100644
index 000000000..4c12d3e1c
--- /dev/null
+++ b/roms/u-boot/board/keymile/scripts/develop-ppc_82xx.txt
@@ -0,0 +1 @@
+setup_debug_env=tftpboot ${load_addr_r} scripts/develop-common.txt && env import -t ${load_addr_r} ${filesize} && run configure
diff --git a/roms/u-boot/board/keymile/scripts/develop-ppc_8xx.txt b/roms/u-boot/board/keymile/scripts/develop-ppc_8xx.txt
new file mode 100644
index 000000000..4c12d3e1c
--- /dev/null
+++ b/roms/u-boot/board/keymile/scripts/develop-ppc_8xx.txt
@@ -0,0 +1 @@
+setup_debug_env=tftpboot ${load_addr_r} scripts/develop-common.txt && env import -t ${load_addr_r} ${filesize} && run configure
diff --git a/roms/u-boot/board/keymile/scripts/ramfs-arm.txt b/roms/u-boot/board/keymile/scripts/ramfs-arm.txt
new file mode 100644
index 000000000..93f87faba
--- /dev/null
+++ b/roms/u-boot/board/keymile/scripts/ramfs-arm.txt
@@ -0,0 +1 @@
+setup_debug_env=tftpboot ${load_addr_r} scripts/ramfs-common.txt && env import -t ${load_addr_r} ${filesize} && run configure
diff --git a/roms/u-boot/board/keymile/scripts/ramfs-common.txt b/roms/u-boot/board/keymile/scripts/ramfs-common.txt
new file mode 100644
index 000000000..0a4a9c80b
--- /dev/null
+++ b/roms/u-boot/board/keymile/scripts/ramfs-common.txt
@@ -0,0 +1,15 @@
+addramfs=setenv bootargs "${bootargs} phram.phram=rootfs${boot_bank},${rootfsaddr},${rootfssize}"
+boot_bank=-1
+altbootcmd=run ${subbootcmds}
+bootcmd=run ${subbootcmds}
+subbootcmds=save_and_reset_once tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot
+save_and_reset_once=setenv save_and_reset_once true && saveenv && reset
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
+configure=run set_uimage; run set_tftppath; km_setboardid && run try_import_rootfssize && saveenv && reset
+setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value}
+tftpfdt=if run set_fdthigh || test ${arch} != arm; then if tftpboot ${fdt_addr_r} ${tftppath}/fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; then; else tftpboot ${fdt_addr_r} ${tftppath}/${hostname}.dtb; fi; else true; fi
+tftpkernel=tftpboot ${load_addr_r} ${tftppath}/${uimage}
+tftpramfs=tftpboot ${rootfsaddr} ${tftppath}/rootfsImage
+set_uimage=printenv uimage || setenv uimage uImage
+set_tftppath=if test ${hostname} = kmcoge5un; then setenv tftppath CI5UN; else if test ${hostname} = kmcoge5ne; then setenv tftppath CI5NE; else setenv tftppath ${IVM_Symbol}; fi; fi
+try_import_rootfssize=if tftpboot ${load_addr_r} ${tftppath}/rootfssize.txt; then env import -t ${load_addr_r} ${filesize}; else echo no auto rootfs size; echo you can set rootfssize in /tftpboot/${tftppath}/rootfssize.txt and rerun ramfs; fi
diff --git a/roms/u-boot/board/keymile/scripts/ramfs-ppc_82xx.txt b/roms/u-boot/board/keymile/scripts/ramfs-ppc_82xx.txt
new file mode 100644
index 000000000..93f87faba
--- /dev/null
+++ b/roms/u-boot/board/keymile/scripts/ramfs-ppc_82xx.txt
@@ -0,0 +1 @@
+setup_debug_env=tftpboot ${load_addr_r} scripts/ramfs-common.txt && env import -t ${load_addr_r} ${filesize} && run configure
diff --git a/roms/u-boot/board/keymile/scripts/ramfs-ppc_8xx.txt b/roms/u-boot/board/keymile/scripts/ramfs-ppc_8xx.txt
new file mode 100644
index 000000000..93f87faba
--- /dev/null
+++ b/roms/u-boot/board/keymile/scripts/ramfs-ppc_8xx.txt
@@ -0,0 +1 @@
+setup_debug_env=tftpboot ${load_addr_r} scripts/ramfs-common.txt && env import -t ${load_addr_r} ${filesize} && run configure
diff --git a/roms/u-boot/board/keymile/secu1/MAINTAINERS b/roms/u-boot/board/keymile/secu1/MAINTAINERS
new file mode 100644
index 000000000..3e40eef3c
--- /dev/null
+++ b/roms/u-boot/board/keymile/secu1/MAINTAINERS
@@ -0,0 +1,5 @@
+Hitachi Power Grids SECU1 BOARD
+M:	Holger Brunck <holger.brunck@hitachi-powergrids.com>
+S:	Maintained
+F:	include/configs/socfpga_arria5_secu1.h
+F:	configs/socfpga_secu1_defconfig
diff --git a/roms/u-boot/board/keymile/secu1/Makefile b/roms/u-boot/board/keymile/secu1/Makefile
new file mode 100644
index 000000000..69531807e
--- /dev/null
+++ b/roms/u-boot/board/keymile/secu1/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2020 Hitachi Power Grids
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o ../common/ivm.o
diff --git a/roms/u-boot/board/keymile/secu1/qts/iocsr_config.h b/roms/u-boot/board/keymile/secu1/qts/iocsr_config.h
new file mode 100644
index 000000000..7640c56db
--- /dev/null
+++ b/roms/u-boot/board/keymile/secu1/qts/iocsr_config.h
@@ -0,0 +1,694 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	1337
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	1528
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00100000,
+	0x40000000,
+	0x00000000,
+	0x00000100,
+	0x00040000,
+	0x00008000,
+	0x00080000,
+	0x20000000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00002000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x00001000,
+	0x00000000,
+	0x0300C000,
+	0x0000000C,
+	0x00000000,
+	0x00000000,
+	0x00000800,
+	0x01806018,
+	0x00000000,
+	0x01800000,
+	0x00001806,
+	0x00001806,
+	0x00000400,
+	0x00C0300C,
+	0x00C03000,
+	0x00C00003,
+	0x00000C03,
+	0x00300C03,
+	0x00000200,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00100000,
+	0x40000000,
+	0x00000000,
+	0x00000100,
+	0x00040000,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00002000,
+	0x00020000,
+	0x08000000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x00010000,
+	0x04000000,
+	0x00000000,
+	0x00000010,
+	0x00004000,
+	0x00000800,
+	0x00006018,
+	0x01806000,
+	0x00000006,
+	0x00000008,
+	0x00601806,
+	0x00000400,
+	0x0000300C,
+	0x00C03000,
+	0x00C00000,
+	0x00000003,
+	0x00000C03,
+	0x00000200,
+	0x00000000,
+	0x00601800,
+	0x80600000,
+	0x80000001,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x00100000,
+	0x40000000,
+	0x00000000,
+	0x00000100,
+	0x00040000,
+	0x00008000,
+	0x00080000,
+	0x20000000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00002000,
+	0x00018060,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x00001000,
+	0x0300C030,
+	0x00000000,
+	0x03000000,
+	0x0000000C,
+	0x00C0300C,
+	0x00000800,
+	0x01806018,
+	0x01806000,
+	0x00000006,
+	0x00000000,
+	0x00601806,
+	0x00000400,
+	0x00C0300C,
+	0x00C03000,
+	0x00C00003,
+	0x00000C03,
+	0x00300C03,
+	0x00000200,
+	0x00601806,
+	0x80601800,
+	0x80600001,
+	0x80000601,
+	0x00180601,
+	0x00000100,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x2CC20D80,
+	0x082000FF,
+	0x08028001,
+	0x00100000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x00000000,
+	0xC0000010,
+	0x00C00512,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xA2580000,
+	0x60001800,
+	0x00600289,
+	0x800A2580,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x512C0000,
+	0xB0000C00,
+	0x00300144,
+	0xC00512C0,
+	0x144B0000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000050,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xA0680514,
+	0xC3034028,
+	0x06181A00,
+	0x805140D0,
+	0x34069A06,
+	0x01A034D0,
+	0x240D0000,
+	0x28A06809,
+	0x00000340,
+	0xD000001A,
+	0x06809240,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x80000000,
+	0x01800A25,
+	0x00289600,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x44B00000,
+	0xC0003001,
+	0x00C00512,
+	0x00000FF0,
+	0x512C0000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x581D8000,
+	0x60001800,
+	0x00600289,
+	0x800A2580,
+	0x16076001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x512C0000,
+	0xB0000C00,
+	0x00300144,
+	0xC00512C0,
+	0x144B0000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000050,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xA0680514,
+	0x4D034028,
+	0x1A681A03,
+	0x805140D0,
+	0x34069A06,
+	0x01A00020,
+	0x240D0001,
+	0x49206809,
+	0x034D0340,
+	0xD01A681A,
+	0x06805140,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x80000000,
+	0x01800A25,
+	0x00289600,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x44B0090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x1C864000,
+	0x45147A07,
+	0xA228A3DA,
+	0xF491451E,
+	0x0358D348,
+	0x821A0000,
+	0x0000D000,
+	0x028A0680,
+	0xDA79E47A,
+	0x1EA228A3,
+	0xC8F49965,
+	0x000344B2,
+	0x00080000,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x00000000,
+	0x00000020,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040000,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x60120800,
+	0x00600289,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xC228A3DC,
+	0xF491451E,
+	0x0344B2C8,
+	0x821A034D,
+	0x0000D000,
+	0x00000680,
+	0xD469A47A,
+	0x1E83CF23,
+	0xC8F71E79,
+	0x000344B2,
+	0x00080000,
+	0x00001000,
+	0x00080000,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x00000000,
+	0x00000020,
+	0x0080C000,
+	0x41000000,
+	0x00000002,
+	0x00820008,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040000,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010000,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x0C864000,
+	0x79E47A03,
+	0x92AAA3D2,
+	0xF595551E,
+	0x034CF3C8,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDA79E47A,
+	0x1EA32CA3,
+	0xC8F69965,
+	0x000354F3,
+	0x00080000,
+	0x00001000,
+	0x00080000,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x00000000,
+	0x00000020,
+	0x0080C000,
+	0x41000000,
+	0x00000002,
+	0x00820008,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040000,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020000,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00002000,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x0C864000,
+	0x59647A03,
+	0xC3CF23DC,
+	0xF711451E,
+	0x0358D348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD459647A,
+	0x1E83CF23,
+	0x48F51E79,
+	0x000348D3,
+	0x00080000,
+	0x00001000,
+	0x00080000,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x00000000,
+	0x00000020,
+	0x0080C000,
+	0x41000000,
+	0x00000002,
+	0x00820008,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00008000,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x00000000,
+	0x00000010,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00141419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/keymile/secu1/qts/pinmux_config.h b/roms/u-boot/board/keymile/secu1/qts/pinmux_config.h
new file mode 100644
index 000000000..a9406060e
--- /dev/null
+++ b/roms/u-boot/board/keymile/secu1/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	3, /* EMACIO0 */
+	3, /* EMACIO1 */
+	3, /* EMACIO2 */
+	3, /* EMACIO3 */
+	3, /* EMACIO4 */
+	3, /* EMACIO5 */
+	3, /* EMACIO6 */
+	3, /* EMACIO7 */
+	3, /* EMACIO8 */
+	3, /* EMACIO9 */
+	3, /* EMACIO10 */
+	3, /* EMACIO11 */
+	3, /* EMACIO12 */
+	3, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	0, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	0, /* FLASHIO2 */
+	0, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	0, /* FLASHIO9 */
+	0, /* FLASHIO10 */
+	0, /* FLASHIO11 */
+	3, /* GENERALIO0 */
+	3, /* GENERALIO1 */
+	3, /* GENERALIO2 */
+	3, /* GENERALIO3 */
+	3, /* GENERALIO4 */
+	3, /* GENERALIO5 */
+	3, /* GENERALIO6 */
+	3, /* GENERALIO7 */
+	3, /* GENERALIO8 */
+	3, /* GENERALIO9 */
+	3, /* GENERALIO10 */
+	3, /* GENERALIO11 */
+	3, /* GENERALIO12 */
+	3, /* GENERALIO13 */
+	3, /* GENERALIO14 */
+	0, /* GENERALIO15 */
+	0, /* GENERALIO16 */
+	0, /* GENERALIO17 */
+	0, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	3, /* MIXED1IO0 */
+	3, /* MIXED1IO1 */
+	3, /* MIXED1IO2 */
+	3, /* MIXED1IO3 */
+	3, /* MIXED1IO4 */
+	3, /* MIXED1IO5 */
+	3, /* MIXED1IO6 */
+	3, /* MIXED1IO7 */
+	3, /* MIXED1IO8 */
+	3, /* MIXED1IO9 */
+	3, /* MIXED1IO10 */
+	3, /* MIXED1IO11 */
+	3, /* MIXED1IO12 */
+	3, /* MIXED1IO13 */
+	3, /* MIXED1IO14 */
+	0, /* MIXED1IO15 */
+	0, /* MIXED1IO16 */
+	0, /* MIXED1IO17 */
+	0, /* MIXED1IO18 */
+	0, /* MIXED1IO19 */
+	0, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	1, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/keymile/secu1/qts/pll_config.h b/roms/u-boot/board/keymile/secu1/qts/pll_config.h
new file mode 100644
index 000000000..f0c31860c
--- /dev/null
+++ b/roms/u-boot/board/keymile/secu1/qts/pll_config.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 24
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 1
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 14
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 40000000
+#define CONFIG_HPS_CLK_OSC2_HZ 40000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 600000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
+#define CONFIG_HPS_CLK_USBCLK_HZ 12500000
+#define CONFIG_HPS_CLK_NAND_HZ 31250000
+#define CONFIG_HPS_CLK_SDMMC_HZ 3125000
+#define CONFIG_HPS_CLK_QSPI_HZ 3125000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/roms/u-boot/board/keymile/secu1/qts/sdram_config.h b/roms/u-boot/board/keymile/secu1/qts/sdram_config.h
new file mode 100644
index 000000000..b0ff86ef3
--- /dev/null
+++ b/roms/u-boot/board/keymile/secu1/qts/sdram_config.h
@@ -0,0 +1,327 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			60
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		2341
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			13
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			17
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		200
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x10441
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x78
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x11
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x12
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x14
+#define RW_MGR_CLEAR_DQS_ENABLE	0x4B
+#define RW_MGR_EMR	0x09
+#define RW_MGR_EMR2	0x0D
+#define RW_MGR_EMR3	0x0F
+#define RW_MGR_EMR_OCD_ENABLE	0x0B
+#define RW_MGR_GUARANTEED_READ	0x4E
+#define RW_MGR_GUARANTEED_READ_CONT	0x56
+#define RW_MGR_GUARANTEED_WRITE	0x1A
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1D
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x21
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1F
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x77
+#define RW_MGR_IDLE_LOOP2	0x76
+#define RW_MGR_INIT_CKE_0	0x71
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x27
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x26
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x34
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x23
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x3B
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x3A
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x48
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x37
+#define RW_MGR_MR_CALIB	0x05
+#define RW_MGR_MR_DLL_RESET	0x07
+#define RW_MGR_MR_USER	0x03
+#define RW_MGR_NOP	0x01
+#define RW_MGR_PRECHARGE_ALL	0x16
+#define RW_MGR_READ_B2B	0x5B
+#define RW_MGR_READ_B2B_WAIT1	0x63
+#define RW_MGR_READ_B2B_WAIT2	0x6D
+#define RW_MGR_REFRESH	0x18
+
+/* Sequencer defines configuration */
+#define AFI_CLK_FREQ	301
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	6
+#define CALIB_VFIFO_OFFSET	4
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	416
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x555504bf
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	74
+#define TINIT_CNTR1_VAL	20
+#define TINIT_CNTR2_VAL	20
+#define TRESET_CNTR0_VAL	74
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x30700000,
+	0x38700000,
+	0x30700000,
+	0x20700000,
+	0x10000853,
+	0x10000853,
+	0x10000953,
+	0x10010000,
+	0x10010380,
+	0x10020000,
+	0x10030000,
+	0x10300400,
+	0x10600000,
+	0x10620000,
+	0x10200400,
+	0x10400000,
+	0x1c900000,
+	0x1c920000,
+	0x1c900008,
+	0x1c920008,
+	0x38f00000,
+	0x3cf00000,
+	0x38700000,
+	0x10100000,
+	0x18900000,
+	0x13500000,
+	0x13520000,
+	0x13500008,
+	0x13520008,
+	0x33700000,
+	0x10500008
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80180,
+	0x100,
+	0x80000,
+	0x200,
+	0x80000,
+	0x280,
+	0x80000,
+	0x300,
+	0x80000,
+	0x380,
+	0x80000,
+	0x400,
+	0x80000,
+	0x480,
+	0x80000,
+	0x500,
+	0x80000,
+	0x600,
+	0x8000,
+	0x680,
+	0xa000,
+	0x80000,
+	0x700,
+	0x80000,
+	0x780,
+	0x80000,
+	0x968,
+	0xcae8,
+	0x8e8,
+	0x8ae8,
+	0x988,
+	0xea88,
+	0x808,
+	0xaa88,
+	0x80000,
+	0xcc00,
+	0xcb80,
+	0xe080,
+	0xa00,
+	0x20ae0,
+	0x20ae0,
+	0x20ae0,
+	0x20ae0,
+	0xb00,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x60c80,
+	0x60e80,
+	0x60e80,
+	0x60e80,
+	0xa000,
+	0x8000,
+	0x80000,
+	0xcc00,
+	0xcb80,
+	0xe080,
+	0xa00,
+	0x30ae0,
+	0x30ae0,
+	0x30ae0,
+	0x30ae0,
+	0xb00,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x70c80,
+	0x70e80,
+	0x70e80,
+	0x70e80,
+	0xa000,
+	0x8000,
+	0x80000,
+	0xf58,
+	0x58,
+	0x80000,
+	0xf68,
+	0x168,
+	0x168,
+	0x8168,
+	0x40de8,
+	0x40ee8,
+	0x40ee8,
+	0x40ee8,
+	0xf68,
+	0x168,
+	0x168,
+	0xa168,
+	0x80000,
+	0x40c88,
+	0x40e88,
+	0x40e88,
+	0x40e88,
+	0x40d68,
+	0x40ee8,
+	0x40ee8,
+	0x40ee8,
+	0xa000,
+	0x40de8,
+	0x40ee8,
+	0x40ee8,
+	0x40ee8,
+	0x40e08,
+	0x40e88,
+	0x40e88,
+	0x40e88,
+	0xf00,
+	0xc000,
+	0x8000,
+	0xe000,
+	0x80000,
+	0x180,
+	0x8180,
+	0xa180,
+	0xc180,
+	0x80180,
+	0x8000,
+	0xa000,
+	0x80000
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/roms/u-boot/board/keymile/secu1/socfpga.c b/roms/u-boot/board/keymile/secu1/socfpga.c
new file mode 100644
index 000000000..6a4cb2178
--- /dev/null
+++ b/roms/u-boot/board/keymile/secu1/socfpga.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2020 Hitachi Power Grids
+ */
+#include <common.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+
+#include "../common/common.h"
+
+/*
+ * For FU1, the MAC address associated with the mgmt port should
+ * be the base address (as read from the IVM) + 4, and for FU2 it
+ * is + 10
+ */
+#define MAC_ADDRESS_OFFSET_FU1	4
+#define MAC_ADDRESS_OFFSET_FU2	10
+
+/*
+ * This function reads the state of GPIO40 and returns true (non-zero)
+ * if it is '1' and false(0) otherwise.
+ *
+ * This pin is routed to a pull-up on FU2 and a pull-down on
+ */
+#define GPIO_FU_DETECTION	40
+
+int secu1_is_fu2(void)
+{
+	int value;
+	int ret = gpio_request(GPIO_FU_DETECTION, "secu");
+
+	if (ret) {
+		printf("gpio: failed to request pin for FU  detection\n");
+		return 1;
+	}
+	gpio_direction_input(GPIO_FU_DETECTION);
+	value = gpio_get_value(GPIO_FU_DETECTION);
+
+	if (value == 1)
+		printf("FU2 detected\n");
+	else
+		printf("FU1 detected\n");
+
+	return value;
+}
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+	return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+	if (secu1_is_fu2())
+		ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+				MAC_ADDRESS_OFFSET_FU2);
+	else
+		ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+				MAC_ADDRESS_OFFSET_FU1);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/kmc/kzm9g/Kconfig b/roms/u-boot/board/kmc/kzm9g/Kconfig
new file mode 100644
index 000000000..f163efd98
--- /dev/null
+++ b/roms/u-boot/board/kmc/kzm9g/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KZM9G
+
+config SYS_BOARD
+	default "kzm9g"
+
+config SYS_VENDOR
+	default "kmc"
+
+config SYS_CONFIG_NAME
+	default "kzm9g"
+
+endif
diff --git a/roms/u-boot/board/kmc/kzm9g/MAINTAINERS b/roms/u-boot/board/kmc/kzm9g/MAINTAINERS
new file mode 100644
index 000000000..411efd1e3
--- /dev/null
+++ b/roms/u-boot/board/kmc/kzm9g/MAINTAINERS
@@ -0,0 +1,7 @@
+KZM9G BOARD
+M:	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+M:	Tetsuyuki Kobayashi <koba@kmckk.co.jp>
+S:	Maintained
+F:	board/kmc/kzm9g/
+F:	include/configs/kzm9g.h
+F:	configs/kzm9g_defconfig
diff --git a/roms/u-boot/board/kmc/kzm9g/Makefile b/roms/u-boot/board/kmc/kzm9g/Makefile
new file mode 100644
index 000000000..aebe9f354
--- /dev/null
+++ b/roms/u-boot/board/kmc/kzm9g/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+# (C) Copyright 2012 Renesas Solutions Corp.
+
+obj-y	:= kzm9g.o
diff --git a/roms/u-boot/board/kmc/kzm9g/kzm9g.c b/roms/u-boot/board/kmc/kzm9g/kzm9g.c
new file mode 100644
index 000000000..dccf4691a
--- /dev/null
+++ b/roms/u-boot/board/kmc/kzm9g/kzm9g.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CS0BCR_D (0x06C00400)
+#define CS4BCR_D (0x16c90400)
+#define CS0WCR_D (0x55062C42)
+#define CS4WCR_D (0x1e071dc3)
+
+#define CMNCR_BROMMD0   (1 << 21)
+#define CMNCR_BROMMD1   (1 << 22)
+#define CMNCR_BROMMD	(CMNCR_BROMMD0|CMNCR_BROMMD1)
+#define VCLKCR1_D	(0x27)
+
+#define SMSTPCR1_CMT0	(1 << 24)
+#define SMSTPCR1_I2C0	(1 << 16)
+#define SMSTPCR3_USB	(1 << 22)
+#define SMSTPCR3_I2C1	(1 << 23)
+
+#define PORT32CR (0xE6051020)
+#define PORT33CR (0xE6051021)
+#define PORT34CR (0xE6051022)
+#define PORT35CR (0xE6051023)
+
+static int cmp_loop(u32 *addr, u32 data, u32 cmp)
+{
+	int err = -1;
+	int timeout = 100;
+	u32 value;
+
+	while (timeout > 0) {
+		value = readl(addr);
+		if ((value & data) == cmp) {
+			err = 0;
+			break;
+		}
+		timeout--;
+	}
+
+	return err;
+}
+
+/* SBSC Init function */
+static void sbsc_init(struct sh73a0_sbsc *sbsc)
+{
+	writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0);
+	writel(0x5, &sbsc->sdgencnt);
+	cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+	writel(0xacc90159, &sbsc->sdcr0);
+	writel(0x00010059, &sbsc->sdcr1);
+	writel(0x50874114, &sbsc->sdwcrc0);
+	writel(0x33199b37, &sbsc->sdwcrc1);
+	writel(0x008f2313, &sbsc->sdwcrc2);
+	writel(0x31020707, &sbsc->sdwcr00);
+	writel(0x0017040a, &sbsc->sdwcr01);
+	writel(0x31020707, &sbsc->sdwcr10);
+	writel(0x0017040a, &sbsc->sdwcr11);
+	writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */
+	writel(0x30000000, &sbsc->sdwcr2);
+
+	writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
+	cmp_loop(&sbsc->sdpcr, 0x80, 0x80);
+
+	writel(0x00002710, &sbsc->sdgencnt);
+	cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+	writel(0x0000003f, &sbsc->sdmracr0);
+	writel(0x0, SDMRA1A);
+	writel(0x000001f4, &sbsc->sdgencnt);
+	cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+	writel(0x0000ff0a, &sbsc->sdmracr0);
+	if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE)
+		writel(0x0, SDMRA3A);
+	else
+		writel(0x0, SDMRA3B);
+
+	writel(0x00000032, &sbsc->sdgencnt);
+	cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+	if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) {
+		writel(0x00002201, &sbsc->sdmracr0);
+		writel(0x0, SDMRA1A);
+		writel(0x00000402, &sbsc->sdmracr0);
+		writel(0x0, SDMRA1A);
+		writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
+		writel(0x0, SDMRA1A);
+		writel(0x0, SDMRA2A);
+	} else {
+		writel(0x00002201, &sbsc->sdmracr0);
+		writel(0x0, SDMRA1B);
+		writel(0x00000402, &sbsc->sdmracr0);
+		writel(0x0, SDMRA1B);
+		writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
+		writel(0x0, SDMRA1B);
+		writel(0x0, SDMRA2B);
+	}
+
+	writel(0x88800004, &sbsc->sdmrtmpcr);
+	writel(0x00000004, &sbsc->sdmrtmpmsk);
+	writel(0xa55a0032, &sbsc->rtcor);
+	writel(0xa55a000c, &sbsc->rtcorh);
+	writel(0xa55a2048, &sbsc->rtcsr);
+	writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0);
+	writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1);
+	writel(0xfff20000, &sbsc->zqccr);
+
+	/* SCBS2 only */
+	if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) {
+		writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0);
+		writel(0xa5390000, &sbsc->dphycnt1);
+		writel(0x00001200, &sbsc->dphycnt0);
+		writel(0x07ce0000, &sbsc->dphycnt1);
+		writel(0x00001247, &sbsc->dphycnt0);
+		cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000);
+		writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0);
+	}
+}
+
+void s_init(void)
+{
+	struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE;
+	struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
+	struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
+		(struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
+	struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE;
+	struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE;
+	struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+	struct sh73a0_hpb_bscr *hpb_bscr =
+		(struct sh73a0_hpb_bscr *)HPBSCR_BASE;
+
+	/* Watchdog init */
+	writew(0xA507, &rwdt->rwtcsra0);
+
+	/* Secure control register Init */
+	#define LIFEC_SEC_SRC_BIT	(1 << 15)
+	writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC);
+
+	clrbits_le32(&cpg->smstpcr3, (1 << 15));
+	clrbits_le32(&cpg_srcr->srcr3, (1 << 15));
+	clrbits_le32(&cpg->smstpcr2, (1 << 18));
+	clrbits_le32(&cpg_srcr->srcr2, (1 << 18));
+	writel(0x0, &cpg->pllecr);
+
+	cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
+	cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+
+	writel(0x2D000000, &cpg->pll0cr);
+	writel(0x17100000, &cpg->pll1cr);
+	writel(0x96235880, &cpg->frqcrb);
+	cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+
+	writel(0xB, &cpg->flckcr);
+	clrbits_le32(&cpg->smstpcr0, (1 << 1));
+
+	clrbits_le32(&cpg_srcr->srcr0, (1 << 1));
+	writel(0x0514, &hpb_bscr->smgpiotime);
+	writel(0x0514, &hpb_bscr->smcmt2time);
+	writel(0x0514, &hpb_bscr->smcpgtime);
+	writel(0x0514, &hpb_bscr->smsysctime);
+
+	writel(0x00092000, &cpg->dvfscr4);
+	writel(0x000000DC, &cpg->dvfscr5);
+	writel(0x0, &cpg->pllecr);
+	cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
+
+	/* FRQCR Init */
+	writel(0x0012453C, &cpg->frqcra);
+	writel(0x80431350, &cpg->frqcrb);    /* ETM TRCLK  78MHz */
+	cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+	writel(0x00000B0B, &cpg->frqcrd);
+	cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+
+	/* Clock Init */
+	writel(0x00000003, PCLKCR);
+	writel(0x0000012F, &cpg->vclkcr1);
+	writel(0x00000119, &cpg->vclkcr2);
+	writel(0x00000119, &cpg->vclkcr3);
+	writel(0x00000002, &cpg->zbckcr);
+	writel(0x00000005, &cpg->flckcr);
+	writel(0x00000080, &cpg->sd0ckcr);
+	writel(0x00000080, &cpg->sd1ckcr);
+	writel(0x00000080, &cpg->sd2ckcr);
+	writel(0x0000003F, &cpg->fsiackcr);
+	writel(0x0000003F, &cpg->fsibckcr);
+	writel(0x00000080, &cpg->subckcr);
+	writel(0x0000000B, &cpg->spuackcr);
+	writel(0x0000000B, &cpg->spuvckcr);
+	writel(0x0000013F, &cpg->msuckcr);
+	writel(0x00000080, &cpg->hsickcr);
+	writel(0x0000003F, &cpg->mfck1cr);
+	writel(0x0000003F, &cpg->mfck2cr);
+	writel(0x00000107, &cpg->dsitckcr);
+	writel(0x00000313, &cpg->dsi0pckcr);
+	writel(0x0000130D, &cpg->dsi1pckcr);
+	writel(0x2A800E0E, &cpg->dsi0phycr);
+	writel(0x1E000000, &cpg->pll0cr);
+	writel(0x2D000000, &cpg->pll0cr);
+	writel(0x17100000, &cpg->pll1cr);
+	writel(0x27000080, &cpg->pll2cr);
+	writel(0x1D000000, &cpg->pll3cr);
+	writel(0x00080000, &cpg->pll0stpcr);
+	writel(0x000120C0, &cpg->pll1stpcr);
+	writel(0x00012000, &cpg->pll2stpcr);
+	writel(0x00000030, &cpg->pll3stpcr);
+
+	writel(0x0000000B, &cpg->pllecr);
+	cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00);
+
+	writel(0x000120F0, &cpg->dvfscr3);
+	writel(0x00000020, &cpg->mpmode);
+	writel(0x0000028A, &cpg->vrefcr);
+	writel(0xE4628087, &cpg->rmstpcr0);
+	writel(0xFFFFFFFF, &cpg->rmstpcr1);
+	writel(0x53FFFFFF, &cpg->rmstpcr2);
+	writel(0xFFFFFFFF, &cpg->rmstpcr3);
+	writel(0x00800D3D, &cpg->rmstpcr4);
+	writel(0xFFFFF3FF, &cpg->rmstpcr5);
+	writel(0x00000000, &cpg->smstpcr2);
+	writel(0x00040000, &cpg_srcr->srcr2);
+
+	clrbits_le32(&cpg->pllecr, (1 << 3));
+	cmp_loop(&cpg->pllecr, 0x00000800, 0x0);
+
+	writel(0x00000001, &hpb->hpbctrl6);
+	cmp_loop(&hpb->hpbctrl6, 0x1, 0x1);
+
+	writel(0x00001414, &cpg->frqcrd);
+	cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+
+	writel(0x1d000000, &cpg->pll3cr);
+	setbits_le32(&cpg->pllecr, (1 << 3));
+	cmp_loop(&cpg->pllecr, 0x800, 0x800);
+
+	/* SBSC1 Init*/
+	sbsc_init(sbsc1);
+
+	/* SBSC2 Init*/
+	sbsc_init(sbsc2);
+
+	writel(0x00000b0b, &cpg->frqcrd);
+	cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+	writel(0xfffffffc, &cpg->cpgxxcs4);
+}
+
+int board_early_init_f(void)
+{
+	struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
+	struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE;
+	struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
+		(struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
+
+	writel(CS0BCR_D, &bsc->cs0bcr);
+	writel(CS4BCR_D, &bsc->cs4bcr);
+	writel(CS0WCR_D, &bsc->cs0wcr);
+	writel(CS4WCR_D, &bsc->cs4wcr);
+
+	clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD);
+
+	clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
+	clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
+	clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
+	clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
+	writel(VCLKCR1_D, &cpg->vclkcr1);
+
+	/* Setup SCIF4 / workaround */
+	writeb(0x12, PORT32CR);
+	writeb(0x22, PORT33CR);
+	writeb(0x12, PORT34CR);
+	writeb(0x22, PORT35CR);
+
+	return 0;
+}
+
+void adjust_core_voltage(void)
+{
+	u8 data;
+
+	data = 0x35;
+	i2c_set_bus_num(0);
+	i2c_write(0x40, 3, 1, &data, 1);
+}
+
+int board_init(void)
+{
+	adjust_core_voltage();
+	sh73a0_pinmux_init();
+
+    /* SCIFA 4 */
+	gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
+	gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
+	gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
+	gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
+
+	/* Ethernet/SMSC */
+	gpio_request(GPIO_PORT224, NULL);
+	gpio_direction_input(GPIO_PORT224);
+
+	/* SMSC/USB */
+	gpio_request(GPIO_FN_CS4_, NULL);
+
+	/* MMCIF */
+	gpio_request(GPIO_FN_MMCCLK0, NULL);
+	gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
+
+	/* SDHI */
+	gpio_request(GPIO_FN_SDHIWP0, NULL);
+	gpio_request(GPIO_FN_SDHICD0, NULL);
+	gpio_request(GPIO_FN_SDHICMD0, NULL);
+	gpio_request(GPIO_FN_SDHICLK0,  NULL);
+	gpio_request(GPIO_FN_SDHID0_3,  NULL);
+	gpio_request(GPIO_FN_SDHID0_2,  NULL);
+	gpio_request(GPIO_FN_SDHID0_1,  NULL);
+	gpio_request(GPIO_FN_SDHID0_0,  NULL);
+	gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
+	gpio_request(GPIO_PORT15, NULL);
+	gpio_direction_output(GPIO_PORT15, 1);
+
+	/* I2C */
+	gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
+	gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
+	gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
+	gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
+
+	gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int ret = 0;
+#ifdef CONFIG_SMC911X
+	ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return ret;
+}
+
+void reset_cpu(void)
+{
+	/* Soft Power On Reset */
+	writel((1 << 31), RESCNT2);
+}
diff --git a/roms/u-boot/board/kobol/helios4/Kconfig b/roms/u-boot/board/kobol/helios4/Kconfig
new file mode 100644
index 000000000..cad51c1cf
--- /dev/null
+++ b/roms/u-boot/board/kobol/helios4/Kconfig
@@ -0,0 +1,24 @@
+menu "Helios4 configuration"
+	depends on TARGET_HELIOS4
+
+config ENV_SIZE
+	hex "Environment Size"
+	default 0x10000
+
+config ENV_OFFSET
+	hex "Environment offset"
+	default 0xF0000
+
+config ENV_SECT_SIZE
+	hex "Environment Sector-Size"
+	# Use SPI or SATA flash erase block size of 4 KiB
+	default 0x1000 if MVEBU_SPL_BOOT_DEVICE_SPI || MVEBU_SPL_BOOT_DEVICE_SATA
+	# Use optimistic 64 KiB erase block, will vary between actual media
+	default 0x10000 if MVEBU_SPL_BOOT_DEVICE_MMC || MVEBU_SPL_BOOT_DEVICE_UART
+
+config SYS_SPI_U_BOOT_OFFS
+	hex "address of u-boot payload in SPI flash"
+	default 0x20000
+	depends on MVEBU_SPL_BOOT_DEVICE_SPI
+
+endmenu
diff --git a/roms/u-boot/board/kobol/helios4/MAINTAINERS b/roms/u-boot/board/kobol/helios4/MAINTAINERS
new file mode 100644
index 000000000..c9610deee
--- /dev/null
+++ b/roms/u-boot/board/kobol/helios4/MAINTAINERS
@@ -0,0 +1,6 @@
+HELIOS4 BOARD
+M:	Dennis Gilmore <dgilmore@redhat.com>
+S:	Maintained
+F:	board/kobol/helios4/
+F:	include/configs/helios4.h
+F:	configs/helios4_defconfig
diff --git a/roms/u-boot/board/kobol/helios4/Makefile b/roms/u-boot/board/kobol/helios4/Makefile
new file mode 100644
index 000000000..63f079639
--- /dev/null
+++ b/roms/u-boot/board/kobol/helios4/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com>
+
+obj-y	:= helios4.o
diff --git a/roms/u-boot/board/kobol/helios4/README b/roms/u-boot/board/kobol/helios4/README
new file mode 100644
index 000000000..749f04827
--- /dev/null
+++ b/roms/u-boot/board/kobol/helios4/README
@@ -0,0 +1,46 @@
+Update from original Marvell U-Boot to mainline U-Boot:
+-------------------------------------------------------
+
+Generate the U-Boot image with these commands:
+
+$ make helios4_defconfig
+$ make
+
+The resulting image including the SPL binary with the
+full DDR setup is "u-boot-spl.kwb".
+
+Now all you need to do is copy this image on a SD card.
+For example with this command:
+
+$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1
+
+Please use the correct device node for your setup instead
+of "/dev/sdX" here!
+
+Boot selection:
+---------------
+
+Before powering up the board, boot selection should be done via the SW1 dip
+switch (0: OFF, 1: ON):
+
+ - SPI:     00010
+ - SD/eMMC: 00111
+ - SATA1:   11100
+ - UART:    11110
+
+Boot from UART:
+---------------
+
+Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5)
+to your host.
+
+Set the SW1 DIP switches to UART boot (see above).
+
+Run the following command to initiate U-Boot download:
+
+  ./tools/kwboot -p -b u-boot-spl.kwb /dev/ttyUSBX
+
+Use the correct UART device node for /dev/ttyUSBX.
+
+When download finishes start your favorite terminal emulator
+on /dev/ttyUSBX.
diff --git a/roms/u-boot/board/kobol/helios4/helios4.c b/roms/u-boot/board/kobol/helios4/helios4.c
new file mode 100644
index 000000000..9c5b687b3
--- /dev/null
+++ b/roms/u-boot/board/kobol/helios4/helios4.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com>
+ *  based on board/solidrun/clearfog/clearfog.c
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-15t1-helios4" as well as the upstream config for clearfog
+ */
+#define BOARD_GPP_OUT_ENA_LOW	0xffffffff
+#define BOARD_GPP_OUT_ENA_MID	0xffffffff
+
+#define BOARD_GPP_OUT_VAL_LOW	0x0
+#define BOARD_GPP_OUT_VAL_MID	0x0
+#define BOARD_GPP_POL_LOW	0x0
+#define BOARD_GPP_POL_MID	0x0
+
+static struct serdes_map board_serdes_map[] = {
+	{SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SATA1, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SATA3, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SATA2, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	*serdes_map_array = board_serdes_map;
+	*count = ARRAY_SIZE(board_serdes_map);
+	return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1600K,	/* speed_bin */
+	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
+	    MV_DDR_DIE_CAP_8GBIT,	/* mem_size */
+	    MV_DDR_FREQ_800,		/* frequency */
+	    0, 0,			/* cas_wl cas_l */
+	    MV_DDR_TEMP_LOW,		/* temperature */
+	    MV_DDR_TIM_DEFAULT} },	/* timing */
+	BUS_MASK_32BIT_ECC,		/* Busses mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+	writel(0x10400011, MVEBU_MPP_BASE + 0x08);
+	writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
+	writel(0x44400002, MVEBU_MPP_BASE + 0x10);
+	writel(0x41144004, MVEBU_MPP_BASE + 0x14);
+	writel(0x40333333, MVEBU_MPP_BASE + 0x18);
+	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Helios4\n");
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	cpu_eth_init(bis); /* Built in controller(s) come first */
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/kontron/sl28/Kconfig b/roms/u-boot/board/kontron/sl28/Kconfig
new file mode 100644
index 000000000..abcacc318
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/Kconfig
@@ -0,0 +1,61 @@
+if TARGET_SL28
+
+config SYS_BOARD
+	default "sl28"
+
+config SYS_VENDOR
+	default "kontron"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "kontron_sl28"
+
+config SYS_TEXT_BASE
+	default 0x96000000
+
+config SL28_SPL_LOADS_ATF_BL31
+	bool "SPL loads BL31 of the ARM Trusted Firmware"
+	select SPL_ATF
+	select SPL_ATF_LOAD_IMAGE_V2
+	select ARMV8_SEC_FIRMWARE_SUPPORT
+	select SEC_FIRMWARE_ARMV8_PSCI
+	help
+	  Enable this to load a BL31 image by the SPL. You have to
+	  provde a bl31.bin in u-boot's root directory.
+
+if SL28_SPL_LOADS_ATF_BL31
+
+config SL28_BL31_ENTRY_ADDR
+	hex "Entry point of the BL31 image"
+	default 0xfbe00000
+
+endif
+
+config SL28_SPL_LOADS_OPTEE_BL32
+	bool "SPL loads OP-TEE Trusted OS as BL32"
+	depends on SL28_SPL_LOADS_ATF_BL31
+	help
+	  Enable this to load a BL32 image by the SPL. You have to
+	  provde a tee.bin in u-boot's root directory.
+
+if SL28_SPL_LOADS_OPTEE_BL32
+
+config SL28_BL32_ENTRY_ADDR
+	hex "Entry point of the BL32 image"
+	default 0xfc000000
+
+endif
+
+config SL28_ENABLE_SER0_CONSOLE
+	bool "Enable console output on SER0"
+	select DM_SERIAL
+	select SPL_DM_SERIAL
+	select FSL_LPUART
+	help
+	  By default the console output of this board is on the second serial
+	  line (SER1). Sometimes it is desirable to enable output on the first
+	  serial line (SER0). For example, if you have a carrier which only
+	  supports the first serial port.
+endif
diff --git a/roms/u-boot/board/kontron/sl28/MAINTAINERS b/roms/u-boot/board/kontron/sl28/MAINTAINERS
new file mode 100644
index 000000000..a7b0fbbdd
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/MAINTAINERS
@@ -0,0 +1,7 @@
+Kontron SMARC-sAL28 board
+M:	Michael Walle <michael@walle.cc>
+S:	Maintained
+F:	arch/arm/dts/fsl-ls1028a-kontron-sl28-*
+F:	board/kontron/sl28/
+F:	configs/kontron_sl28_defconfig
+F:	include/configs/kontron_sl28.h
diff --git a/roms/u-boot/board/kontron/sl28/Makefile b/roms/u-boot/board/kontron/sl28/Makefile
new file mode 100644
index 000000000..5d220f074
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+ifndef CONFIG_SPL_BUILD
+obj-y += sl28.o cmds.o
+endif
+
+obj-y += common.o ddr.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_SPL_ATF) += spl_atf.o
+endif
diff --git a/roms/u-boot/board/kontron/sl28/cmds.c b/roms/u-boot/board/kontron/sl28/cmds.c
new file mode 100644
index 000000000..046d3b490
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/cmds.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * sl28 extension commands
+ *
+ * Copyright (c) 2020 Kontron Europe GmbH
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <linux/delay.h>
+
+#define CPLD_I2C_ADDR 0x4a
+#define REG_UFM_CTRL 0x02
+#define   UFM_CTRL_DCLK    BIT(1)
+#define   UFM_CTRL_DIN     BIT(2)
+#define   UFM_CTRL_PROGRAM BIT(3)
+#define   UFM_CTRL_ERASE   BIT(4)
+#define   UFM_CTRL_DSHIFT  BIT(5)
+#define   UFM_CTRL_DOUT    BIT(6)
+#define   UFM_CTRL_BUSY    BIT(7)
+
+static int ufm_shift_data(struct udevice *dev, u16 data_in, u16 *data_out)
+{
+	int i;
+	int ret;
+	u16 data = 0;
+
+	/* latch data */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, 0);
+	if (ret < 0)
+		return ret;
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+
+	/* assert drshift */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
+			       UFM_CTRL_DSHIFT | UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+
+	/* clock 16 data bits, reverse order */
+	for (i = 15; i >= 0; i--) {
+		u8 din = (data_in & (1 << i)) ? UFM_CTRL_DIN : 0;
+
+		ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DSHIFT
+				| din);
+		if (ret < 0)
+			return ret;
+		if (data_out) {
+			ret = dm_i2c_reg_read(dev, REG_UFM_CTRL);
+			if (ret < 0)
+				return ret;
+			if (ret & UFM_CTRL_DOUT)
+				data |= (1 << i);
+		}
+		ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
+				       UFM_CTRL_DSHIFT | UFM_CTRL_DCLK | din);
+		if (ret < 0)
+			return ret;
+	}
+
+	/* deassert drshift */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+
+	if (data_out)
+		*data_out = data;
+
+	return ret;
+}
+
+static int ufm_erase(struct udevice *dev)
+{
+	int ret;
+
+	/* erase, tEPMX is 500ms */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
+			       UFM_CTRL_DCLK | UFM_CTRL_ERASE);
+	if (ret < 0)
+		return ret;
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+	mdelay(500);
+
+	return 0;
+}
+
+static int ufm_program(struct udevice *dev)
+{
+	int ret;
+
+	/* program, tPPMX is 100us */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
+			       UFM_CTRL_DCLK | UFM_CTRL_PROGRAM);
+	if (ret < 0)
+		return ret;
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+	udelay(100);
+
+	return 0;
+}
+
+static int ufm_write(struct udevice *dev, u16 data)
+{
+	int ret;
+
+	ret = ufm_shift_data(dev, data, NULL);
+	if (ret < 0)
+		return ret;
+
+	ret = ufm_erase(dev);
+	if (ret < 0)
+		return ret;
+
+	return ufm_program(dev);
+}
+
+static int ufm_read(struct udevice *dev, u16 *data)
+{
+	return ufm_shift_data(dev, 0, data);
+}
+
+static int do_sl28_nvm(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	struct udevice *dev;
+	u16 nvm;
+	int ret;
+	char *endp;
+
+	if (i2c_get_chip_for_busnum(0, CPLD_I2C_ADDR, 1, &dev))
+		return CMD_RET_FAILURE;
+
+	if (argc > 1) {
+		nvm = simple_strtoul(argv[1], &endp, 16);
+		if (*endp != '\0') {
+			printf("ERROR: argument is not a valid number\n");
+			ret = -EINVAL;
+			goto out;
+		}
+
+		/*
+		 * We swap all bits, because the a zero bit in hardware means the
+		 * feature is enabled. But this is hard for the user.
+		 */
+		nvm ^= 0xffff;
+
+		ret = ufm_write(dev, nvm);
+		if (ret)
+			goto out;
+		printf("New settings will be activated after the next power cycle!\n");
+	} else {
+		ret = ufm_read(dev, &nvm);
+		if (ret)
+			goto out;
+		nvm ^= 0xffff;
+
+		printf("%04hx\n", nvm);
+	}
+
+	return CMD_RET_SUCCESS;
+
+out:
+	printf("command failed (%d)\n", ret);
+	return CMD_RET_FAILURE;
+}
+
+static char sl28_help_text[] =
+	"nvm [<hex>] - display/set the 16 non-volatile bits\n";
+
+U_BOOT_CMD_WITH_SUBCMDS(sl28, "SMARC-sAL28 specific", sl28_help_text,
+			U_BOOT_SUBCMD_MKENT(nvm, 2, 1, do_sl28_nvm));
diff --git a/roms/u-boot/board/kontron/sl28/common.c b/roms/u-boot/board/kontron/sl28/common.c
new file mode 100644
index 000000000..33c6843c3
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/common.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_lpuart_clk(void)
+{
+	return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
+}
diff --git a/roms/u-boot/board/kontron/sl28/ddr.c b/roms/u-boot/board/kontron/sl28/ddr.c
new file mode 100644
index 000000000..41426996a
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/ddr.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DCFG_GPPORCR1 0x20
+
+#define GPPORCR1_MEM_MASK		(0x7 << 5)
+#define GPPORCR1_MEM_512MB_CS0		(0x0 << 5)
+#define GPPORCR1_MEM_1GB_CS0		(0x1 << 5)
+#define GPPORCR1_MEM_2GB_CS0		(0x2 << 5)
+#define GPPORCR1_MEM_4GB_CS0_1		(0x3 << 5)
+#define GPPORCR1_MEM_4GB_CS0_2		(0x4 << 5)
+#define GPPORCR1_MEM_8GB_CS0_1_2_3	(0x5 << 5)
+#define GPPORCR1_MEM_8GB_CS0_1		(0x6 << 5)
+
+static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = {
+	.cs[0].bnds		= 0x0000007f,
+	.cs[0].config		= 0x80044402,
+	.cs[1].bnds		= 0x008000ff,
+	.cs[1].config		= 0x80004402,
+
+	.timing_cfg_0		= 0x9011010c,
+	.timing_cfg_3		= 0x010c1000,
+	.timing_cfg_1		= 0xbcb48c66,
+	.timing_cfg_2		= 0x0fc0d118,
+	.ddr_sdram_cfg		= 0xe70c000c,
+	.ddr_sdram_cfg_2	= 0x24401111,
+	.ddr_sdram_mode		= 0x00441c70,
+	.ddr_sdram_mode_3	= 0x00001c70,
+	.ddr_sdram_mode_5	= 0x00001c70,
+	.ddr_sdram_mode_7	= 0x00001c70,
+	.ddr_sdram_mode_2	= 0x00180000,
+	.ddr_sdram_mode_4	= 0x00180000,
+	.ddr_sdram_mode_6	= 0x00180000,
+	.ddr_sdram_mode_8	= 0x00180000,
+
+	.ddr_sdram_interval	= 0x0c30030c,
+	.ddr_data_init		= 0xdeadbeef,
+
+	.ddr_sdram_clk_cntl	= 0x02400000,
+
+	.timing_cfg_4		= 0x00000001,
+	.timing_cfg_5		= 0x04401400,
+
+	.ddr_zq_cntl		= 0x89080600,
+	.ddr_wrlvl_cntl		= 0x8675f606,
+	.ddr_wrlvl_cntl_2	= 0x04080700,
+	.ddr_wrlvl_cntl_3	= 0x00000009,
+
+	.ddr_cdr1		= 0x80040000,
+	.ddr_cdr2		= 0x0000bc01,
+};
+
+int fsl_initdram(void)
+{
+	u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1);
+	phys_size_t dram_size;
+
+	switch (gpporcr1 & GPPORCR1_MEM_MASK) {
+	case GPPORCR1_MEM_2GB_CS0:
+		dram_size = 0x80000000;
+		ddr_cfg_regs.cs[1].bnds = 0;
+		ddr_cfg_regs.cs[1].config = 0;
+		ddr_cfg_regs.cs[1].config_2 = 0;
+		break;
+	case GPPORCR1_MEM_4GB_CS0_1:
+		dram_size = 0x100000000ULL;
+		break;
+	case GPPORCR1_MEM_512MB_CS0:
+		dram_size = 0x20000000;
+		fallthrough; /* for now */
+	case GPPORCR1_MEM_1GB_CS0:
+		dram_size = 0x40000000;
+		fallthrough; /* for now */
+	case GPPORCR1_MEM_4GB_CS0_2:
+		dram_size = 0x100000000ULL;
+		fallthrough; /* for now */
+	case GPPORCR1_MEM_8GB_CS0_1:
+	case GPPORCR1_MEM_8GB_CS0_1_2_3:
+		dram_size = 0x200000000ULL;
+		fallthrough; /* for now */
+	default:
+		panic("Unsupported memory configuration (%08x)\n",
+		      gpporcr1 & GPPORCR1_MEM_MASK);
+		break;
+	}
+
+	if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD))
+		fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/kontron/sl28/sl28.c b/roms/u-boot/board/kontron/sl28/sl28.c
new file mode 100644
index 000000000..c8ed7ac81
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/sl28.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fsl_ddr.h>
+#include <fdt_support.h>
+#include <asm/global_data.h>
+#include <linux/libfdt.h>
+#include <env_internal.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <i2c.h>
+#include <asm/arch/soc.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+
+#include <fdtdec.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	fsl_lsch3_early_init_f();
+	return 0;
+}
+
+int board_init(void)
+{
+	if (CONFIG_IS_ENABLED(FSL_CAAM))
+		sec_init();
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int checkboard(void)
+{
+	printf("EL:    %d\n", current_el());
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_ddr_info(0);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+	int nbanks = CONFIG_NR_DRAM_BANKS;
+	int node;
+	int i;
+
+	ft_cpu_setup(blob, bd);
+
+	/* fixup DT for the two GPP DDR banks */
+	for (i = 0; i < nbanks; i++) {
+		base[i] = gd->bd->bi_dram[i].start;
+		size[i] = gd->bd->bi_dram[i].size;
+	}
+
+	fdt_fixup_memory_banks(blob, base, size, nbanks);
+
+	fdt_fixup_icid(blob);
+
+	if (CONFIG_IS_ENABLED(SL28_SPL_LOADS_OPTEE_BL32)) {
+		node = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
+		if (node)
+			fdt_set_node_status(blob, node, FDT_STATUS_OKAY, 0);
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/kontron/sl28/spl.c b/roms/u-boot/board/kontron/sl28/spl.c
new file mode 100644
index 000000000..0e6ad5f37
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/spl.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch-fsl-layerscape/fsl_serdes.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+
+#define DCFG_RCWSR25 0x160
+#define GPINFO_HW_VARIANT_MASK 0xff
+
+#define SERDES_LNDGCR0		0x1ea08c0
+#define   LNDGCR0_PROTS_MASK	GENMASK(11, 7)
+#define   LNDGCR0_PROTS_SATA	(0x2 << 7)
+#define SERDES_LNDGCR1		0x1ea08c4
+#define   LNDGCR1_RDAT_INV	BIT(31)
+
+/*
+ * On this board the SMARC PCIe lane D might be switched to SATA mode. This
+ * makes sense if this lane is connected to a Mini PCI slot and a mSATA card
+ * is plugged in. In this case, the RX pair is swapped and we need to invert
+ * the received data.
+ */
+static void fixup_sata_rx_polarity(void)
+{
+	u32 prot = in_le32(SERDES_LNDGCR0) & LNDGCR0_PROTS_MASK;
+	u32 tmp;
+
+	if (prot == LNDGCR0_PROTS_SATA) {
+		tmp = in_le32(SERDES_LNDGCR1);
+		tmp |= LNDGCR1_RDAT_INV;
+		out_le32(SERDES_LNDGCR1, tmp);
+	}
+}
+
+int sl28_variant(void)
+{
+	return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	int variant = sl28_variant();
+
+	switch (variant) {
+	case 1:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28-var1");
+	case 2:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28-var2");
+	case 3:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28-var3");
+	case 4:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28-var4");
+	default:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28");
+	}
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+}
+
+int board_early_init_f(void)
+{
+	fixup_sata_rx_polarity();
+	fsl_lsch3_early_init_f();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/kontron/sl28/spl_atf.c b/roms/u-boot/board/kontron/sl28/spl_atf.c
new file mode 100644
index 000000000..a9cd6850e
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/spl_atf.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * LS1028A TF-A calling support
+ *
+ * Copyright (c) 2020 Michael Walle <michael@walle.cc>
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <atf_common.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct region_info {
+	u64 addr;
+	u64 size;
+};
+
+struct dram_regions_info {
+	u64 num_dram_regions;
+	u64 total_dram_size;
+	struct region_info region[CONFIG_NR_DRAM_BANKS];
+};
+
+struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry,
+					      uintptr_t bl33_entry,
+					      uintptr_t fdt_addr)
+{
+	static struct dram_regions_info dram_regions_info = { 0 };
+	struct bl_params *bl_params;
+	struct bl_params_node *node;
+	void *dcfg_ccsr = (void *)DCFG_BASE;
+	int i;
+
+	dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		dram_regions_info.region[i].addr = gd->bd->bi_dram[i].start;
+		dram_regions_info.region[i].size = gd->bd->bi_dram[i].size;
+		dram_regions_info.total_dram_size += gd->bd->bi_dram[i].size;
+	}
+
+	bl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry,
+							fdt_addr);
+
+	for_each_bl_params_node(bl_params, node) {
+		if (node->image_id == ATF_BL31_IMAGE_ID) {
+			node->ep_info->args.arg3 = (uintptr_t)&dram_regions_info;
+			node->ep_info->args.arg4 = in_le32(dcfg_ccsr + DCFG_PORSR1);
+		}
+	}
+
+	return bl_params;
+}
diff --git a/roms/u-boot/board/kosagi/novena/Kconfig b/roms/u-boot/board/kosagi/novena/Kconfig
new file mode 100644
index 000000000..c5cbaabe6
--- /dev/null
+++ b/roms/u-boot/board/kosagi/novena/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KOSAGI_NOVENA
+
+config SYS_BOARD
+	default "novena"
+
+config SYS_VENDOR
+	default "kosagi"
+
+config SYS_CONFIG_NAME
+	default "novena"
+
+endif
diff --git a/roms/u-boot/board/kosagi/novena/MAINTAINERS b/roms/u-boot/board/kosagi/novena/MAINTAINERS
new file mode 100644
index 000000000..d3471c2d6
--- /dev/null
+++ b/roms/u-boot/board/kosagi/novena/MAINTAINERS
@@ -0,0 +1,6 @@
+NOVENA BOARD
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+F:	board/kosagi/novena/
+F:	include/configs/novena.h
+F:	configs/novena_defconfig
diff --git a/roms/u-boot/board/kosagi/novena/Makefile b/roms/u-boot/board/kosagi/novena/Makefile
new file mode 100644
index 000000000..64d32f5a9
--- /dev/null
+++ b/roms/u-boot/board/kosagi/novena/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014 Marek Vasut <marex@denx.de>
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= novena_spl.o
+else
+obj-y	:= novena.o
+obj-$(CONFIG_VIDEO_IPUV3)	+= video.o
+endif
diff --git a/roms/u-boot/board/kosagi/novena/novena.c b/roms/u-boot/board/kosagi/novena/novena.c
new file mode 100644
index 000000000..0e1b4a0a4
--- /dev/null
+++ b/roms/u-boot/board/kosagi/novena/novena.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Novena board support
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <eeprom.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <ahci.h>
+#include <env.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
+#include <dwc_ahsata.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/fb.h>
+#include <linux/input.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <stdio_dev.h>
+#include <video_console.h>
+
+#include "novena.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * GPIO button
+ */
+#ifdef CONFIG_KEYBOARD
+static struct input_config button_input;
+
+static int novena_gpio_button_read_keys(struct input_config *input)
+{
+	int key = KEY_ENTER;
+	if (gpio_get_value(NOVENA_BUTTON_GPIO))
+		return 0;
+	input_send_keycodes(&button_input, &key, 1);
+	return 1;
+}
+
+static int novena_gpio_button_getc(struct stdio_dev *dev)
+{
+	return input_getc(&button_input);
+}
+
+static int novena_gpio_button_tstc(struct stdio_dev *dev)
+{
+	return input_tstc(&button_input);
+}
+
+static int novena_gpio_button_init(struct stdio_dev *dev)
+{
+	gpio_direction_input(NOVENA_BUTTON_GPIO);
+	input_set_delays(&button_input, 250, 250);
+	return 0;
+}
+
+int drv_keyboard_init(void)
+{
+	int error;
+	struct stdio_dev dev = {
+		.name	= "button",
+		.flags	= DEV_FLAGS_INPUT,
+		.start	= novena_gpio_button_init,
+		.getc	= novena_gpio_button_getc,
+		.tstc	= novena_gpio_button_tstc,
+	};
+
+	gpio_request(NOVENA_BUTTON_GPIO, "button");
+
+	error = input_init(&button_input, 0);
+	if (error) {
+		debug("%s: Cannot set up input\n", __func__);
+		return -1;
+	}
+	input_add_tables(&button_input, false);
+	button_input.read_keys = novena_gpio_button_read_keys;
+
+	error = input_stdio_register(&dev);
+	if (error)
+		return error;
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display_clock();
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+	struct udevice *con;
+	char buf[DISPLAY_OPTIONS_BANNER_LENGTH];
+	int ret;
+
+	setup_display_lvds();
+
+	ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con);
+	if (ret)
+		return ret;
+
+	display_options_get_banner(false, buf, sizeof(buf));
+	vidconsole_position_cursor(con, 0, 0);
+	vidconsole_put_string(con, buf);
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Novena 4x\n");
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	struct pmic *p;
+	u32 reg;
+	int ret;
+
+	power_pfuze100_init(1);
+	p = pmic_get("PFUZE100");
+	if (!p)
+		return -EINVAL;
+
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	/* Set SWBST to 5.0V and enable (for USB) */
+	pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
+	reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
+	reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
+	pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+
+	return 0;
+}
+
+/* EEPROM configuration data */
+struct novena_eeprom_data {
+	uint8_t		signature[6];
+	uint8_t		version;
+	uint8_t		reserved;
+	uint32_t	serial;
+	uint8_t		mac[6];
+	uint16_t	features;
+};
+
+int misc_init_r(void)
+{
+	struct novena_eeprom_data data;
+	uchar *datap = (uchar *)&data;
+	const char *signature = "Novena";
+	int ret;
+
+	/* If 'ethaddr' is already set, do nothing. */
+	if (env_get("ethaddr"))
+		return 0;
+
+	/* EEPROM is at bus 2. */
+	ret = i2c_set_bus_num(2);
+	if (ret) {
+		puts("Cannot select EEPROM I2C bus.\n");
+		return 0;
+	}
+
+	/* EEPROM is at address 0x56. */
+	ret = eeprom_read(0x56, 0, datap, sizeof(data));
+	if (ret) {
+		puts("Cannot read I2C EEPROM.\n");
+		return 0;
+	}
+
+	/* Check EEPROM signature. */
+	if (memcmp(data.signature, signature, 6)) {
+		puts("Invalid I2C EEPROM signature.\n");
+		return 0;
+	}
+
+	/* Set ethernet address from EEPROM. */
+	eth_env_set_enetaddr("ethaddr", data.mac);
+
+	return ret;
+}
diff --git a/roms/u-boot/board/kosagi/novena/novena.h b/roms/u-boot/board/kosagi/novena/novena.h
new file mode 100644
index 000000000..f62f3f7b8
--- /dev/null
+++ b/roms/u-boot/board/kosagi/novena/novena.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Novena board support
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __BOARD_KOSAGI_NOVENA_NOVENA_H__
+#define __BOARD_KOSAGI_NOVENA_NOVENA_H__
+
+#define NOVENA_AUDIO_PWRON		IMX_GPIO_NR(5, 17)
+#define NOVENA_BACKLIGHT_PWM_GPIO	IMX_GPIO_NR(4, 29)
+#define NOVENA_BACKLIGHT_PWR_GPIO	IMX_GPIO_NR(4, 15)
+#define NOVENA_BUTTON_GPIO		IMX_GPIO_NR(4, 14)
+#define NOVENA_FPGA_RESET_N_GPIO	IMX_GPIO_NR(5, 7)
+#define NOVENA_HDMI_GHOST_HPD		IMX_GPIO_NR(5, 4)
+#define NOVENA_ITE6251_PWR_GPIO		IMX_GPIO_NR(5, 28)
+#define NOVENA_PCIE_DISABLE_GPIO	IMX_GPIO_NR(2, 16)
+#define NOVENA_PCIE_POWER_ON_GPIO	IMX_GPIO_NR(7, 12)
+#define NOVENA_PCIE_RESET_GPIO		IMX_GPIO_NR(3, 29)
+#define NOVENA_PCIE_WAKE_UP_GPIO	IMX_GPIO_NR(3, 22)
+#define NOVENA_SD_CD			IMX_GPIO_NR(1, 4)
+#define NOVENA_SD_WP			IMX_GPIO_NR(1, 2)
+
+#define NOVENA_IT6251_I2C_BUS	2
+#define NOVENA_IT6251_CHIPADDR	0x5c
+#define NOVENA_IT6251_LVDSADDR	0x5e
+
+void setup_display_clock(void);
+void setup_display_lvds(void);
+
+#endif	/* __BOARD_KOSAGI_NOVENA_NOVENA_H__ */
diff --git a/roms/u-boot/board/kosagi/novena/novena_spl.c b/roms/u-boot/board/kosagi/novena/novena_spl.c
new file mode 100644
index 000000000..3d22f2019
--- /dev/null
+++ b/roms/u-boot/board/kosagi/novena/novena_spl.c
@@ -0,0 +1,599 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Novena SPL
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/crm_regs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <spl.h>
+#include <linux/delay.h>
+
+#include <asm/arch/mx6-ddr.h>
+
+#include "novena.h"
+
+#define UART_PAD_CTRL						\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL						\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL						\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define ENET_PHY_CFG_PAD_CTRL					\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_22K_UP | PAD_CTL_HYS)
+
+#define RGMII_PAD_CTRL						\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL						\
+	(PAD_CTL_HYS |						\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL						\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_240ohm  | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define BUTTON_PAD_CTRL						\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/*
+ * Audio
+ */
+static iomux_v3_cfg_t audio_pads[] = {
+	/* AUD_PWRON */
+	MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_audio(void)
+{
+	imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads));
+	gpio_direction_output(NOVENA_AUDIO_PWRON, 1);
+}
+
+/*
+ * ENET
+ */
+static iomux_v3_cfg_t enet_pads1[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	/* pin 35, PHY_AD2 */
+	MX6_PAD_RGMII_RXC__GPIO6_IO30	| MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+	/* pin 32, MODE0 */
+	MX6_PAD_RGMII_RD0__GPIO6_IO25	| MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+	/* pin 31, MODE1 */
+	MX6_PAD_RGMII_RD1__GPIO6_IO27	| MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+	/* pin 28, MODE2 */
+	MX6_PAD_RGMII_RD2__GPIO6_IO28	| MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+	/* pin 27, MODE3 */
+	MX6_PAD_RGMII_RD3__GPIO6_IO29	| MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+	/* pin 33, CLK125_EN */
+	MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+
+	/* pin 42 PHY nRST */
+	MX6_PAD_EIM_D23__GPIO3_IO23		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t enet_pads2[] = {
+	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+
+	/* Assert Ethernet PHY nRST */
+	gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+
+	/*
+	 * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset
+	 * de-assertion. The intention is to use weak signal drivers (pull-ups)
+	 * to prevent the conflict between PHY pins becoming outputs after
+	 * reset and imx6 still driving the pins. The issue is described in PHY
+	 * datasheet, p.14
+	 */
+	gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
+	gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
+	gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
+	gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
+	gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
+	gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
+
+	/* Following reset timing (p.53, fig.8 from the PHY datasheet) */
+	mdelay(10);
+
+	/* De-assert Ethernet PHY nRST */
+	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+
+	/* PHY is now configured, connect FEC to the pads */
+	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+
+	/*
+	 * PHY datasheet recommends on p.53 to wait at least 100us after reset
+	 * before using MII, so we enforce the delay here
+	 */
+	udelay(100);
+}
+
+/*
+ * FPGA
+ */
+static iomux_v3_cfg_t fpga_pads[] = {
+	/* FPGA_RESET_N */
+	MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_fpga(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads));
+	gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0);
+}
+
+/*
+ * GPIO Button
+ */
+static iomux_v3_cfg_t button_pads[] = {
+	/* Debug */
+	MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_buttons(void)
+{
+	imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads));
+}
+
+/*
+ * I2C
+ */
+/*
+ * I2C1:
+ *  0x1d ... MMA7455L
+ *  0x30 ... SO-DIMM temp sensor
+ *  0x44 ... STMPE610
+ *  0x50 ... SO-DIMM ID
+ */
+struct i2c_pads_info i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode	= MX6_PAD_EIM_D21__I2C1_SCL | PC,
+		.gpio_mode	= MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+		.gp		= IMX_GPIO_NR(3, 21)
+	},
+	.sda = {
+		.i2c_mode	= MX6_PAD_EIM_D28__I2C1_SDA | PC,
+		.gpio_mode	= MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+		.gp		= IMX_GPIO_NR(3, 28)
+	}
+};
+
+/*
+ * I2C2:
+ *  0x08 ... PMIC
+ *  0x3a ... HDMI DCC
+ *  0x50 ... HDMI DCC
+ */
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode	= MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode	= MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.gp		= IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode	= MX6_PAD_EIM_D16__I2C2_SDA | PC,
+		.gpio_mode	= MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+		.gp		= IMX_GPIO_NR(3, 16)
+	}
+};
+
+/*
+ * I2C3:
+ *  0x11 ... ES8283
+ *  0x50 ... LCD EDID
+ *  0x56 ... EEPROM
+ */
+static struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode	= MX6_PAD_EIM_D17__I2C3_SCL | PC,
+		.gpio_mode	= MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+		.gp		= IMX_GPIO_NR(3, 17)
+	},
+	.sda = {
+		.i2c_mode	= MX6_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode	= MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+		.gp		= IMX_GPIO_NR(3, 18)
+	}
+};
+
+static void novena_spl_setup_iomux_i2c(void)
+{
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+}
+
+/*
+ * PCI express
+ */
+#ifdef CONFIG_CMD_PCI
+static iomux_v3_cfg_t pcie_pads[] = {
+	/* "Reset" pin */
+	MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* "Power on" pin */
+	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* "Wake up" pin (input) */
+	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* "Disable endpoint" (rfkill) pin */
+	MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_pcie(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+
+	/* Ensure PCIe is powered down */
+	gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0);
+
+	/* Put the card into reset */
+	gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0);
+
+	/* Input signal to wake system from mPCIe card */
+	gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO);
+
+	/* Drive RFKILL high, to ensure the radio is turned on */
+	gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1);
+}
+#else
+static inline void novena_spl_setup_iomux_pcie(void) {}
+#endif
+
+/*
+ * SDHC
+ */
+static iomux_v3_cfg_t usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
+	MX6_PAD_GPIO_4__GPIO1_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_sdhc(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+	/* Big SD write-protect and card-detect */
+	gpio_direction_input(IMX_GPIO_NR(1, 2));
+	gpio_direction_input(IMX_GPIO_NR(1, 4));
+}
+
+/*
+ * SPI
+ */
+#ifdef CONFIG_MXC_SPI
+static iomux_v3_cfg_t ecspi3_pads[] = {
+	/* SS1 */
+	MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_spi(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
+	/* De-assert the nCS */
+	gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1);
+	gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1);
+	gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1);
+}
+#else
+static void novena_spl_setup_iomux_spi(void) {}
+#endif
+
+/*
+ * UART
+ */
+static iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+
+};
+
+static void novena_spl_setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+/*
+ * Video
+ */
+#ifdef CONFIG_VIDEO
+static iomux_v3_cfg_t hdmi_pads[] = {
+	/* "Ghost HPD" pin */
+	MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* LCD_PWR_CTL */
+	MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* LCD_BL_ON */
+	MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* GPIO_PWM1 */
+	MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_video(void)
+{
+	imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads));
+	gpio_direction_input(NOVENA_HDMI_GHOST_HPD);
+}
+#else
+static inline void novena_spl_setup_iomux_video(void) {}
+#endif
+
+/*
+ * SPL boots from uSDHC card
+ */
+#ifdef CONFIG_FSL_ESDHC_IMX
+static struct fsl_esdhc_cfg usdhc_cfg = {
+	USDHC3_BASE_ADDR, 0, 4
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* There is no CD for a microSD card, assume always present. */
+	return 1;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif
+
+/* Configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+	.dram_sdclk_0		= 0x00020038,
+	.dram_sdclk_1		= 0x00020038,
+	.dram_cas		= 0x00000038,
+	.dram_ras		= 0x00000038,
+	.dram_reset		= 0x00000038,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0		= 0x00000038,
+	.dram_sdcke1		= 0x00000038,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2		= 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 40 ohm */
+	.dram_sdodt0		= 0x00000038,
+	.dram_sdodt1		= 0x00000038,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.dram_sdqs0		= 0x00000038,
+	.dram_sdqs1		= 0x00000038,
+	.dram_sdqs2		= 0x00000038,
+	.dram_sdqs3		= 0x00000038,
+	.dram_sdqs4		= 0x00000038,
+	.dram_sdqs5		= 0x00000038,
+	.dram_sdqs6		= 0x00000038,
+	.dram_sdqs7		= 0x00000038,
+
+	/* DQM[0:7]: Differential input, 40 ohm */
+	.dram_dqm0		= 0x00000038,
+	.dram_dqm1		= 0x00000038,
+	.dram_dqm2		= 0x00000038,
+	.dram_dqm3		= 0x00000038,
+	.dram_dqm4		= 0x00000038,
+	.dram_dqm5		= 0x00000038,
+	.dram_dqm6		= 0x00000038,
+	.dram_dqm7		= 0x00000038,
+};
+
+/* Configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs novena_grp_ioregs = {
+	/* DDR3 */
+	.grp_ddr_type		= 0x000c0000,
+	.grp_ddrmode_ctl	= 0x00020000,
+	/* Disable DDR pullups */
+	.grp_ddrpke		= 0x00000000,
+	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
+	.grp_addds		= 0x00000038,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+	.grp_ctlds		= 0x00000038,
+	/* DATA[00:63]: Differential input, 40 ohm */
+	.grp_ddrmode		= 0x00020000,
+	.grp_b0ds		= 0x00000038,
+	.grp_b1ds		= 0x00000038,
+	.grp_b2ds		= 0x00000038,
+	.grp_b3ds		= 0x00000038,
+	.grp_b4ds		= 0x00000038,
+	.grp_b5ds		= 0x00000038,
+	.grp_b6ds		= 0x00000038,
+	.grp_b7ds		= 0x00000038,
+};
+
+static struct mx6_mmdc_calibration novena_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0		= 0x00420048,
+	.p0_mpwldectrl1		= 0x006f0059,
+	.p1_mpwldectrl0		= 0x005a0104,
+	.p1_mpwldectrl1		= 0x01070113,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0		= 0x437c040b,
+	.p0_mpdgctrl1		= 0x0413040e,
+	.p1_mpdgctrl0		= 0x444f0446,
+	.p1_mpdgctrl1		= 0x044d0422,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl		= 0x4c424249,
+	.p1_mprddlctl		= 0x4e48414f,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl		= 0x42414641,
+	.p1_mpwrdlctl		= 0x46374b43,
+};
+
+static struct mx6_ddr_sysinfo novena_ddr_info = {
+	/* Width of data bus: 0=16, 1=32, 2=64 */
+	.dsize		= 2,
+	/* Config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,	/* 32Gb per CS */
+	/* Single chip select */
+	.ncs		= 1,
+	.cs1_mirror	= 0,
+	.rtt_wr		= 0,	/* RTT_Wr = RZQ/4 */
+	.rtt_nom	= 1,	/* RTT_Nom = RZQ/2 */
+	.walat		= 0,	/* Write additional latency */
+	.ralat		= 5,	/* Read additional latency */
+	.mif3_mode	= 3,	/* Command prediction working mode */
+	.bi_on		= 1,	/* Bank interleaving enabled */
+	.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
+};
+
+static struct mx6_ddr3_cfg elpida_4gib_1600 = {
+	.mem_speed	= 1600,
+	.density	= 4,
+	.width		= 64,
+	.banks		= 8,
+	.rowaddr	= 16,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1375,
+	.trcmin		= 4875,
+	.trasmin	= 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0xFFFFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+	board_postclk_init();
+#endif
+#ifdef CONFIG_FSL_ESDHC_IMX
+	get_clocks();
+#endif
+
+	/* Setup IOMUX and configure basics. */
+	novena_spl_setup_iomux_audio();
+	novena_spl_setup_iomux_buttons();
+	novena_spl_setup_iomux_enet();
+	novena_spl_setup_iomux_fpga();
+	novena_spl_setup_iomux_i2c();
+	novena_spl_setup_iomux_pcie();
+	novena_spl_setup_iomux_sdhc();
+	novena_spl_setup_iomux_spi();
+	novena_spl_setup_iomux_uart();
+	novena_spl_setup_iomux_video();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* Start the DDR DRAM */
+	mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
+	mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
+
+	/* Perform DDR DRAM calibration */
+	udelay(100);
+	mmdc_do_write_level_calibration(&novena_ddr_info);
+	mmdc_do_dqs_calibration(&novena_ddr_info);
+}
diff --git a/roms/u-boot/board/kosagi/novena/video.c b/roms/u-boot/board/kosagi/novena/video.c
new file mode 100644
index 000000000..a96a877f5
--- /dev/null
+++ b/roms/u-boot/board/kosagi/novena/video.c
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Novena video output support
+ *
+ * IT6251 code based on code Copyright (C) 2014 Sean Cross
+ * from https://github.com/xobs/novena-linux.git commit
+ * 3d85836ee1377d445531928361809612aa0a18db
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/fb.h>
+#include <linux/input.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+
+#include "novena.h"
+
+#define IT6251_VENDOR_ID_LOW				0x00
+#define IT6251_VENDOR_ID_HIGH				0x01
+#define IT6251_DEVICE_ID_LOW				0x02
+#define IT6251_DEVICE_ID_HIGH				0x03
+#define IT6251_SYSTEM_STATUS				0x0d
+#define IT6251_SYSTEM_STATUS_RINTSTATUS			(1 << 0)
+#define IT6251_SYSTEM_STATUS_RHPDSTATUS			(1 << 1)
+#define IT6251_SYSTEM_STATUS_RVIDEOSTABLE		(1 << 2)
+#define IT6251_SYSTEM_STATUS_RPLL_IOLOCK		(1 << 3)
+#define IT6251_SYSTEM_STATUS_RPLL_XPLOCK		(1 << 4)
+#define IT6251_SYSTEM_STATUS_RPLL_SPLOCK		(1 << 5)
+#define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK		(1 << 6)
+#define IT6251_REF_STATE				0x0e
+#define IT6251_REF_STATE_MAIN_LINK_DISABLED		(1 << 0)
+#define IT6251_REF_STATE_AUX_CHANNEL_READ		(1 << 1)
+#define IT6251_REF_STATE_CR_PATTERN			(1 << 2)
+#define IT6251_REF_STATE_EQ_PATTERN			(1 << 3)
+#define IT6251_REF_STATE_NORMAL_OPERATION		(1 << 4)
+#define IT6251_REF_STATE_MUTED				(1 << 5)
+
+#define IT6251_REG_PCLK_CNT_LOW				0x57
+#define IT6251_REG_PCLK_CNT_HIGH			0x58
+
+#define IT6521_RETRY_MAX				20
+
+static int it6251_is_stable(void)
+{
+	const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+	const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
+	int status;
+	int clkcnt;
+	int rpclkcnt;
+	int refstate;
+
+	rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
+		   ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
+	debug("RPCLKCnt: %d\n", rpclkcnt);
+
+	status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
+	debug("System status: 0x%02x\n", status);
+
+	clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
+		 ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
+		  0x0f00);
+	debug("Clock: 0x%02x\n", clkcnt);
+
+	refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
+	debug("Ref Link State: 0x%02x\n", refstate);
+
+	if ((refstate & 0x1f) != 0)
+		return 0;
+
+	/* If video is muted, that's a failure */
+	if (refstate & IT6251_REF_STATE_MUTED)
+		return 0;
+
+	if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE))
+		return 0;
+
+	return 1;
+}
+
+static int it6251_ready(void)
+{
+	const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+
+	/* Test if the IT6251 came out of reset by reading ID regs. */
+	if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
+		return 0;
+	if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
+		return 0;
+	if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
+		return 0;
+	if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
+		return 0;
+
+	return 1;
+}
+
+static void it6251_program_regs(void)
+{
+	const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+	const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
+
+	i2c_reg_write(caddr, 0x05, 0x00);
+	mdelay(1);
+
+	/* set LVDSRX address, and enable */
+	i2c_reg_write(caddr, 0xfd, 0xbc);
+	i2c_reg_write(caddr, 0xfe, 0x01);
+
+	/*
+	 * LVDSRX
+	 */
+	/* This write always fails, because the chip goes into reset */
+	/* reset LVDSRX */
+	i2c_reg_write(laddr, 0x05, 0xff);
+	i2c_reg_write(laddr, 0x05, 0x00);
+
+	/* reset LVDSRX PLL */
+	i2c_reg_write(laddr, 0x3b, 0x42);
+	i2c_reg_write(laddr, 0x3b, 0x43);
+
+	/* something with SSC PLL */
+	i2c_reg_write(laddr, 0x3c, 0x08);
+	/* don't swap links, but writing reserved registers */
+	i2c_reg_write(laddr, 0x0b, 0x88);
+
+	/* JEIDA, 8-bit depth  0x11, orig 0x42 */
+	i2c_reg_write(laddr, 0x2c, 0x01);
+	/* "reserved" */
+	i2c_reg_write(laddr, 0x32, 0x04);
+	/* "reserved" */
+	i2c_reg_write(laddr, 0x35, 0xe0);
+	/* "reserved" + clock delay */
+	i2c_reg_write(laddr, 0x2b, 0x24);
+
+	/* reset LVDSRX pix clock */
+	i2c_reg_write(laddr, 0x05, 0x02);
+	i2c_reg_write(laddr, 0x05, 0x00);
+
+	/*
+	 * DPTX
+	 */
+	/* set for two lane mode, normal op, no swapping, no downspread */
+	i2c_reg_write(caddr, 0x16, 0x02);
+
+	/* some AUX channel EDID magic */
+	i2c_reg_write(caddr, 0x23, 0x40);
+
+	/* power down lanes 3-0 */
+	i2c_reg_write(caddr, 0x5c, 0xf3);
+
+	/* enable DP scrambling, change EQ CR phase */
+	i2c_reg_write(caddr, 0x5f, 0x06);
+
+	/* color mode RGB, pclk/2 */
+	i2c_reg_write(caddr, 0x60, 0x02);
+	/* dual pixel input mode, no EO swap, no RGB swap */
+	i2c_reg_write(caddr, 0x61, 0x04);
+	/* M444B24 video format */
+	i2c_reg_write(caddr, 0x62, 0x01);
+
+	/* vesa range / not interlace / vsync high / hsync high */
+	i2c_reg_write(caddr, 0xa0, 0x0F);
+
+	/* hpd event timer set to 1.6-ish ms */
+	i2c_reg_write(caddr, 0xc9, 0xf5);
+
+	/* more reserved magic */
+	i2c_reg_write(caddr, 0xca, 0x4d);
+	i2c_reg_write(caddr, 0xcb, 0x37);
+
+	/* enhanced framing mode, auto video fifo reset, video mute disable */
+	i2c_reg_write(caddr, 0xd3, 0x03);
+
+	/* "vidstmp" and some reserved stuff */
+	i2c_reg_write(caddr, 0xd4, 0x45);
+
+	/* queue number -- reserved */
+	i2c_reg_write(caddr, 0xe7, 0xa0);
+	/* info frame packets  and reserved */
+	i2c_reg_write(caddr, 0xe8, 0x33);
+	/* more AVI stuff */
+	i2c_reg_write(caddr, 0xec, 0x00);
+
+	/* select PC master reg for aux channel? */
+	i2c_reg_write(caddr, 0x23, 0x42);
+
+	/* send PC request commands */
+	i2c_reg_write(caddr, 0x24, 0x00);
+	i2c_reg_write(caddr, 0x25, 0x00);
+	i2c_reg_write(caddr, 0x26, 0x00);
+
+	/* native aux read */
+	i2c_reg_write(caddr, 0x2b, 0x00);
+	/* back to internal */
+	i2c_reg_write(caddr, 0x23, 0x40);
+
+	/* voltage swing level 3 */
+	i2c_reg_write(caddr, 0x19, 0xff);
+	/* pre-emphasis level 3 */
+	i2c_reg_write(caddr, 0x1a, 0xff);
+
+	/* start link training */
+	i2c_reg_write(caddr, 0x17, 0x01);
+}
+
+static int it6251_init(void)
+{
+	const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+	int reg;
+	int tries, retries = 0;
+
+	for (retries = 0; retries < IT6521_RETRY_MAX; retries++) {
+		/* Program the chip. */
+		it6251_program_regs();
+
+		/* Wait for video stable. */
+		for (tries = 0; tries < 100; tries++) {
+			reg = i2c_reg_read(caddr, 0x17);
+			/* Test Link CFG, STS, LCS read done. */
+			if ((reg & 0xe0) != 0xe0) {
+				/* Not yet, wait a bit more. */
+				mdelay(2);
+				continue;
+			}
+
+			/* Test if the video input is stable. */
+			if (it6251_is_stable())
+				return 0;
+		}
+		/*
+		 * If we couldn't stabilize, requeue and try again,
+		 * because it means that the LVDS channel isn't
+		 * stable yet.
+		 */
+		printf("Display didn't stabilize.\n");
+		printf("This may be because the LVDS port is still in powersave mode.\n");
+		mdelay(50);
+	}
+
+	return -EINVAL;
+}
+
+static void enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static int lvds_enabled;
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	if (lvds_enabled)
+		return;
+
+	/* ITE IT6251 power enable. */
+	gpio_request(NOVENA_ITE6251_PWR_GPIO, "ite6251-power");
+	gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
+	mdelay(10);
+	gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
+	mdelay(20);
+	lvds_enabled = 1;
+}
+
+static int detect_lvds(struct display_info_t const *dev)
+{
+	int ret, loops = 250;
+
+	enable_lvds(dev);
+
+	ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
+	if (ret) {
+		puts("Cannot select IT6251 I2C bus.\n");
+		return 0;
+	}
+
+	/* Wait up-to ~250 mS for the LVDS to come up. */
+	while (--loops) {
+		ret = it6251_ready();
+		if (ret)
+			return ret;
+
+		mdelay(1);
+	}
+
+	return 0;
+}
+
+struct display_info_t const displays[] = {
+	{
+		/* HDMI Output */
+		.bus	= -1,
+		.addr	= 0,
+		.pixfmt	= IPU_PIX_FMT_RGB24,
+		.detect	= detect_hdmi,
+		.enable	= enable_hdmi,
+		.mode	= {
+			.name		= "HDMI",
+			.refresh	= 60,
+			.xres		= 1024,
+			.yres		= 768,
+			.pixclock	= 15384,
+			.left_margin	= 220,
+			.right_margin	= 40,
+			.upper_margin	= 21,
+			.lower_margin	= 7,
+			.hsync_len	= 60,
+			.vsync_len	= 10,
+			.sync		= FB_SYNC_EXT,
+			.vmode		= FB_VMODE_NONINTERLACED
+		},
+	}, {
+		/* LVDS Output: N133HSE-EA1 Rev. C1 */
+		.bus	= -1,
+		.pixfmt	= IPU_PIX_FMT_RGB24,
+		.detect	= detect_lvds,
+		.enable	= enable_lvds,
+		.mode	= {
+			.name		= "Chimei-FHD",
+			.refresh	= 60,
+			.xres		= 1920,
+			.yres		= 1080,
+			.pixclock	= 15384,
+			.left_margin	= 148,
+			.right_margin	= 88,
+			.upper_margin	= 36,
+			.lower_margin	= 4,
+			.hsync_len	= 44,
+			.vsync_len	= 5,
+			.sync		= FB_SYNC_HOR_HIGH_ACT |
+					  FB_SYNC_VERT_HIGH_ACT |
+					  FB_SYNC_EXT,
+			.vmode		= FB_VMODE_NONINTERLACED,
+		},
+	},
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+static void enable_vpll(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int timeout = 100000;
+
+	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+			BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+			BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
+			BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+	clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	while (timeout--)
+		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+			break;
+	if (timeout < 0)
+		printf("Warning: video pll lock timeout!\n");
+
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_BYPASS,
+			BM_ANADIG_PLL_VIDEO_ENABLE);
+}
+
+void setup_display_clock(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	enable_ipu_clock();
+	enable_vpll();
+	imx_setup_hdmi();
+
+	/* Turn on IPU LDB DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+	/* Switch LDB DI0 to PLL5 (Video PLL) */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
+			(0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+
+	/* LDB clock div by 3.5 */
+	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+	/* DI0 clock derived from ldb_di0_clk */
+	clrsetbits_le32(&mxc_ccm->chsccdr,
+			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+			(CHSCCDR_CLK_SEL_LDB_DI0 <<
+			 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
+			);
+
+	/* Enable both LVDS channels, both connected to DI0. */
+	writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
+	       IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
+	       IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
+	       IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
+	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+	       IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
+	       IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
+	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+	       &iomux->gpr[2]);
+
+	clrsetbits_le32(&iomux->gpr[3],
+			IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+			IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
+			(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+			 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
+			(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+			 IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+			);
+}
+
+void setup_display_lvds(void)
+{
+	int ret;
+
+	ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
+	if (ret) {
+		puts("Cannot select LVDS-to-eDP I2C bus.\n");
+		return;
+	}
+
+	/* The IT6251 should be ready now, if it's not, it's not connected. */
+	ret = it6251_ready();
+	if (!ret)
+		return;
+
+	/* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
+	ret = it6251_init();
+	if (!ret) {
+		gpio_request(NOVENA_BACKLIGHT_PWR_GPIO, "backlight-power");
+		gpio_request(NOVENA_BACKLIGHT_PWM_GPIO, "backlight-pwm");
+		/* Backlight power enable. */
+		gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
+		/* PWM backlight pin, always on for full brightness. */
+		gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1);
+	}
+}
diff --git a/roms/u-boot/board/l+g/vinco/Kconfig b/roms/u-boot/board/l+g/vinco/Kconfig
new file mode 100644
index 000000000..229b5ea12
--- /dev/null
+++ b/roms/u-boot/board/l+g/vinco/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VINCO
+
+config SYS_BOARD
+	default "vinco"
+
+config SYS_VENDOR
+	default "l+g"
+
+config SYS_CONFIG_NAME
+	default "vinco"
+
+endif
diff --git a/roms/u-boot/board/l+g/vinco/MAINTAINERS b/roms/u-boot/board/l+g/vinco/MAINTAINERS
new file mode 100644
index 000000000..0cd604417
--- /dev/null
+++ b/roms/u-boot/board/l+g/vinco/MAINTAINERS
@@ -0,0 +1,6 @@
+VInCo Platform
+M:	Gregory CLEMENT <gregory.clement@free-electrons.com>
+S:	Maintained
+F:	board/l+g/vinco
+F:	include/configs/vinco.h
+F:	configs/vinco_defconfig
diff --git a/roms/u-boot/board/l+g/vinco/Makefile b/roms/u-boot/board/l+g/vinco/Makefile
new file mode 100644
index 000000000..a2b8a2bc4
--- /dev/null
+++ b/roms/u-boot/board/l+g/vinco/Makefile
@@ -0,0 +1 @@
+obj-y += vinco.o
diff --git a/roms/u-boot/board/l+g/vinco/vinco.c b/roms/u-boot/board/l+g/vinco/vinco.c
new file mode 100644
index 000000000..f221f0526
--- /dev/null
+++ b/roms/u-boot/board/l+g/vinco/vinco.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board file for the VInCo platform
+ * Based on the the SAMA5-EK board file
+ * Configuration settings for the VInCo platform.
+ * Copyright (C) 2014 Atmel
+ *		      Bo Shen <voice.shen@atmel.com>
+ * Copyright (C) 2015 Free Electrons
+ *		      Gregory CLEMENT <gregory.clement@free-electrons.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/sama5d4.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+#include <spi.h>
+#include <version.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* FIXME gpio code here need to handle through DM_GPIO */
+#if !CONFIG_IS_ENABLED(DM_SPI)
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+}
+
+static void vinco_spi0_hw_init(void)
+{
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */
+
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);	/* SPI0_CS0 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+
+#ifdef CONFIG_CMD_USB
+static void vinco_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
+}
+#endif
+
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void vinco_mci0_hw_init(void)
+{
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1);	/* MCI0 CDA */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1);	/* MCI0 DA0 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1);	/* MCI0 DA1 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1);	/* MCI0 DA2 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1);	/* MCI0 DA3 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1);	/* MCI0 DA4 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1);	/* MCI0 DA5 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1);	/* MCI0 DA6 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1);	/* MCI0 DA7 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0);	/* MCI0 CLK */
+
+	/*
+	 * As the mci io internal pull down is too strong, so if the io needs
+	 * external pull up, the pull up resistor will be very small, if so
+	 * the power consumption will increase, so disable the interanl pull
+	 * down to save the power.
+	 */
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI0);
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	/* Enable power for MCI0 interface */
+	at91_set_pio_output(AT91_PIO_PORTE, 7, 1);
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI0);
+}
+#endif /* CONFIG_GENERIC_ATMEL_MCI */
+
+#ifdef CONFIG_MACB
+void vinco_macb0_hw_init(void)
+{
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_GMAC0);
+
+	/* Enable Phy*/
+	at91_set_pio_output(AT91_PIO_PORTE, 8, 1);
+}
+#endif
+
+static void vinco_serial3_hw_init(void)
+{
+	at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_USART3);
+}
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+	at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+	vinco_serial3_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#if !CONFIG_IS_ENABLED(DM_SPI)
+	vinco_spi0_hw_init();
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	vinco_mci0_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	vinco_macb0_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	vinco_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+	usb_eth_initialize(bis);
+#endif
+#endif
+
+	return rc;
+}
diff --git a/roms/u-boot/board/lego/ev3/Kconfig b/roms/u-boot/board/lego/ev3/Kconfig
new file mode 100644
index 000000000..14b3f0c1c
--- /dev/null
+++ b/roms/u-boot/board/lego/ev3/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LEGOEV3
+
+config SYS_BOARD
+	default "ev3"
+
+config SYS_VENDOR
+	default "lego"
+
+config SYS_CONFIG_NAME
+	default "legoev3"
+
+endif
diff --git a/roms/u-boot/board/lego/ev3/MAINTAINERS b/roms/u-boot/board/lego/ev3/MAINTAINERS
new file mode 100644
index 000000000..11b326160
--- /dev/null
+++ b/roms/u-boot/board/lego/ev3/MAINTAINERS
@@ -0,0 +1,6 @@
+LEGOEV3 BOARD
+M:	David Lechner <david@lechnology.com>
+S:	Maintained
+F:	board/lego/ev3/
+F:	include/configs/legoev3.h
+F:	configs/legoev3_defconfig
diff --git a/roms/u-boot/board/lego/ev3/Makefile b/roms/u-boot/board/lego/ev3/Makefile
new file mode 100644
index 000000000..11b52ca1d
--- /dev/null
+++ b/roms/u-boot/board/lego/ev3/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+
+obj-y	+= legoev3.o
diff --git a/roms/u-boot/board/lego/ev3/README b/roms/u-boot/board/lego/ev3/README
new file mode 100644
index 000000000..9ad93e820
--- /dev/null
+++ b/roms/u-boot/board/lego/ev3/README
@@ -0,0 +1,55 @@
+Summary
+=======
+
+LEGO MINDSTORMS EV3 is a toy robot produced by the LEGO Group. It is based
+on the davinci da850 evm. The EV3 has a 16MB spi flash and a SDHC microSD card
+reader.
+
+Booting
+=======
+
+The EV3 contains a bootloader in EEPROM that loads u-boot.bin from address 0x0
+of the SPI flash memory (with a size of 256KiB!). Because the EEPROM is read-
+only and it takes care of low level configuration (PLL and DDR), we don't use
+U-Boot to produce an SPL image.
+
+Using the default configuration, U-Boot had a boot scrips that works as follows:
+
+* Check to see if microSD card is present
+* If it is, try to load boot.scr from the first FAT partition
+* If loading boot.scr was successful, run it
+* Otherwise, try loading uEnv.txt
+* If loading uEnv.txt was successful, import it
+* If there is a uenvcmd variable (from uEnv.txt), run it
+* Try to load uImage from the first FAT partition
+* If it was successful, try to load da850-lego-ev3.dtb
+* If loading uImage was successful, boot it (DT is optional)
+* If none of the above was successful, try booting from flash
+
+Suggested Flash Memory Layout
+=============================
+
+The following is based on the default U-Boot configuration:
+
+| Image (file)       | Start Addr. | Max. Size         |
++--------------------+-------------+-------------------+
+| u-boot.bin         |         0x0 |  0x40000 (256KiB) |
+| da850-lego-ev3.dtb |     0x40000 |  0x10000 (64KiB)  |
+| uImage             |     0x50000 | 0x400000 (4MiB)   |
+| rootfs (squashfs)  |    0x450000 | 0xa00000 (10MiB)  |
+
+Writing image to flash
+======================
+
+The EEPROM contains a program for uploading an image file to the flash memory.
+The program is started by holding down the right button on the EV3 when powering
+it on. You can also `run fwupdateboot` in the u-boot shell to reboot into this
+mode. The image can then be uploaded using the official LEGO MINDSTORMS EV3
+software or a 3rd party program capable of uploading a firmware file.
+
+If you are booting from the microSD card, it is enough to just write uboot.bin
+to the flash. If you are not using a microSD card, you will need to create an
+image file using the layout described above.
+
+IMPORTANT: The EEPROM bootloader only copies 256k, so u-boot.img must not
+exceed that size!
diff --git a/roms/u-boot/board/lego/ev3/legoev3.c b/roms/u-boot/board/lego/ev3/legoev3.c
new file mode 100644
index 000000000..980ffef4c
--- /dev/null
+++ b/roms/u-boot/board/lego/ev3/legoev3.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 David Lechner <david@lechnology.com>
+ *
+ * Based on da850evm.c
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux_defs.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <linux/errno.h>
+#include <hwconfig.h>
+#include <asm/mach-types.h>
+#include <asm/setup.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define EEPROM_I2C_ADDR		0x50
+#define EEPROM_REV_OFFSET	0x3F00
+#define EEPROM_BDADDR_OFFSET	0x3F06
+
+const struct pinmux_resource pinmuxes[] = {
+	PINMUX_ITEM(spi0_pins_base),
+	PINMUX_ITEM(spi0_pins_scs0),
+	PINMUX_ITEM(uart1_pins_txrx),
+	PINMUX_ITEM(i2c0_pins),
+	PINMUX_ITEM(mmc0_pins),
+};
+
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
+const struct lpsc_resource lpsc[] = {
+	{ DAVINCI_LPSC_SPI0 },	/* Serial Flash */
+	{ DAVINCI_LPSC_UART1 },	/* console */
+	{ DAVINCI_LPSC_MMC_SD },
+};
+
+const int lpsc_size = ARRAY_SIZE(lpsc);
+
+/*
+ * The Bluetooth address serves as the board serial number.
+ */
+static void setup_serial_number(void)
+{
+	u32 offset;
+	char serial_number[13];
+	u8 buf[6];
+	u8 eeprom_rev;
+
+	if (env_get("serial#"))
+		return;
+
+	if (i2c_read(EEPROM_I2C_ADDR, EEPROM_REV_OFFSET, 2, buf, 2)) {
+		printf("\nEEPROM revision read failed!\n");
+		return;
+	}
+
+	/*
+	 * EEPROM rev 3 has Bluetooth address at EEPROM_REV_OFFSET.
+	 * Other revisions have checksum at EEPROM_REV_OFFSET+1
+	 * to detect this.
+	 */
+	if ((buf[0] ^ buf[1]) == 0xFF)
+		eeprom_rev = buf[0];
+	else
+		eeprom_rev = 3;
+
+	/* EEPROM rev 3 has Bluetooth address where rev should be */
+	offset = (eeprom_rev == 3) ? EEPROM_REV_OFFSET : EEPROM_BDADDR_OFFSET;
+
+	if (i2c_read(EEPROM_I2C_ADDR, offset, 2, buf, 6)) {
+		printf("\nEEPROM serial read failed!\n");
+		return;
+	}
+
+	sprintf(serial_number, "%02X%02X%02X%02X%02X%02X",
+		buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+
+	env_set("serial#", serial_number);
+}
+
+int board_early_init_f(void)
+{
+	/* enable the console UART */
+	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+		DAVINCI_UART_PWREMU_MGMT_UTRST),
+	       &davinci_uart1_ctrl_regs->pwremu_mgmt);
+
+	/*
+	 * Power on required peripherals
+	 * ARM does not have access by default to PSC0 and PSC1
+	 * assuming here that the DSP bootloader has set the IOPU
+	 * such that PSC access is available to ARM
+	 */
+	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+		return 1;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	irq_init();
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* setup the SUSPSRC for ARM to control emulation suspend */
+	writel(readl(&davinci_syscfg_regs->suspsrc) &
+	       ~(DAVINCI_SYSCFG_SUSPSRC_I2C |
+		 DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+		 DAVINCI_SYSCFG_SUSPSRC_UART1),
+	       &davinci_syscfg_regs->suspsrc);
+
+	/* configure pinmux settings */
+	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+		return 1;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setup_serial_number();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/lg/sniper/Kconfig b/roms/u-boot/board/lg/sniper/Kconfig
new file mode 100644
index 000000000..3f18d2120
--- /dev/null
+++ b/roms/u-boot/board/lg/sniper/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SNIPER
+
+config SYS_BOARD
+	default "sniper"
+
+config SYS_VENDOR
+	default "lg"
+
+config SYS_CONFIG_NAME
+	default "sniper"
+
+endif
diff --git a/roms/u-boot/board/lg/sniper/MAINTAINERS b/roms/u-boot/board/lg/sniper/MAINTAINERS
new file mode 100644
index 000000000..7226b092c
--- /dev/null
+++ b/roms/u-boot/board/lg/sniper/MAINTAINERS
@@ -0,0 +1,6 @@
+SNIPER BOARD
+M:	Paul Kocialkowski <contact@paulk.fr>
+S:	Maintained
+F:	board/lg/sniper/
+F:	include/configs/sniper.h
+F:	configs/sniper_defconfig
diff --git a/roms/u-boot/board/lg/sniper/Makefile b/roms/u-boot/board/lg/sniper/Makefile
new file mode 100644
index 000000000..549dcca4e
--- /dev/null
+++ b/roms/u-boot/board/lg/sniper/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# LG Optimus Black codename sniper board
+#
+# Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+
+obj-y := sniper.o
diff --git a/roms/u-boot/board/lg/sniper/sniper.c b/roms/u-boot/board/lg/sniper/sniper.c
new file mode 100644
index 000000000..3065461be
--- /dev/null
+++ b/roms/u-boot/board/lg/sniper/sniper.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * LG Optimus Black codename sniper board
+ *
+ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+ */
+
+#include <config.h>
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <fastboot.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/ctype.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <twl4030.h>
+#include "sniper.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const omap3_sysinfo sysinfo = {
+	.mtype = DDR_STACKED,
+	.board_string = "sniper",
+	.nand_string = "MMC"
+};
+
+static const struct ns16550_plat serial_omap_plat = {
+	.base = OMAP34XX_UART3,
+	.reg_shift = 2,
+	.clock = V_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
+};
+
+U_BOOT_DRVINFO(sniper_serial) = {
+	.name = "ns16550_serial",
+	.plat = &serial_omap_plat
+};
+
+static struct musb_hdrc_config musb_config = {
+	.multipoint = 1,
+	.dyn_fifo = 1,
+	.num_eps = 16,
+	.ram_bits = 12
+};
+
+static struct omap_musb_board_data musb_board_data = {
+	.interface_type	= MUSB_INTERFACE_ULPI,
+};
+
+static struct musb_hdrc_platform_data musb_platform_data = {
+	.mode = MUSB_PERIPHERAL,
+	.config = &musb_config,
+	.power = 100,
+	.platform_ops = &omap2430_ops,
+	.board_data = &musb_board_data,
+};
+
+void set_muxconf_regs(void)
+{
+	MUX_SNIPER();
+}
+
+#ifdef CONFIG_SPL_BUILD
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+	timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+	timings->ctrla = HYNIX_V_ACTIMA_200;
+	timings->ctrlb = HYNIX_V_ACTIMB_200;
+	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+	timings->mr = MICRON_V_MR_165;
+}
+#endif
+
+int board_init(void)
+{
+	/* GPMC init */
+	gpmc_init();
+
+	/* MACH number */
+	gd->bd->bi_arch_number = 3000;
+
+	/* ATAGs location */
+	gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	unsigned char keypad_matrix[64] = { 0 };
+	char reboot_mode[2] = { 0 };
+	unsigned char keys[3];
+	unsigned char data = 0;
+	int rc;
+
+	/* Power button reset init */
+
+	twl4030_power_reset_init();
+
+	/* Keypad */
+
+	twl4030_keypad_scan((unsigned char *)&keypad_matrix);
+
+	keys[0] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 0);
+	keys[1] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 1);
+	keys[2] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 2);
+
+	/* Reboot mode */
+
+	rc = omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
+
+	if (keys[0])
+		reboot_mode[0] = 'r';
+	else if (keys[1])
+		reboot_mode[0] = 'b';
+
+	if (rc < 0 || reboot_mode[0] == 'o') {
+		/*
+		 * When not rebooting, valid power on reasons are either the
+		 * power button, charger plug or USB plug.
+		 */
+
+		data |= twl4030_input_power_button();
+		data |= twl4030_input_charger();
+		data |= twl4030_input_usb();
+
+		if (!data)
+			twl4030_power_off();
+	}
+
+	if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) {
+		if (!env_get("reboot-mode"))
+			env_set("reboot-mode", (char *)reboot_mode);
+	}
+
+	omap_reboot_mode_clear();
+
+	/* Serial number */
+
+	omap_die_id_serial();
+
+	/* MUSB */
+
+	musb_register(&musb_platform_data, &musb_board_data, (void *)MUSB_BASE);
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	/* Sold devices are expected to be at least revision F. */
+	return 6;
+}
+
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	omap_die_id_get_board_serial(serialnr);
+}
+
+void reset_misc(void)
+{
+	char reboot_mode[2] = { 0 };
+
+	/*
+	 * Valid resets must contain the reboot mode magic, but we must not
+	 * override it when set previously (e.g. reboot to bootloader).
+	 */
+
+	omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
+	omap_reboot_mode_store(reboot_mode);
+}
+
+int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
+{
+	if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
+		return -ENOTSUPP;
+
+	return omap_reboot_mode_store("b");
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	return omap_mmc_init(1, 0, 0, -1, -1);
+}
+
+void board_mmc_power_init(void)
+{
+	twl4030_power_mmc_init(1);
+}
diff --git a/roms/u-boot/board/lg/sniper/sniper.h b/roms/u-boot/board/lg/sniper/sniper.h
new file mode 100644
index 000000000..db71ad86d
--- /dev/null
+++ b/roms/u-boot/board/lg/sniper/sniper.h
@@ -0,0 +1,364 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * LG Optimus Black codename sniper board
+ *
+ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+ */
+
+#ifndef _SNIPER_H_
+#define _SNIPER_H_
+
+#include <asm/arch/mux.h>
+
+#define MUX_SNIPER() \
+	/* SDRC */ \
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /* sdrc_d0 */\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /* sdrc_d1 */\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /* sdrc_d2 */\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /* sdrc_d3 */\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /* sdrc_d4 */\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /* sdrc_d5 */\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /* sdrc_d6 */\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /* sdrc_d7 */\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /* sdrc_d8 */\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /* sdrc_d9 */\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /* sdrc_d10 */\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /* sdrc_d11 */\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /* sdrc_d12 */\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /* sdrc_d13 */\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /* sdrc_d14 */\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /* sdrc_d15 */\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /* sdrc_d16 */\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /* sdrc_d17 */\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /* sdrc_d18 */\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /* sdrc_d19 */\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /* sdrc_d20 */\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /* sdrc_d21 */\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /* sdrc_d22 */\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /* sdrc_d23 */\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /* sdrc_d24 */\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /* sdrc_d25 */\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /* sdrc_d26 */\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /* sdrc_d27 */\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /* sdrc_d28 */\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /* sdrc_d29 */\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /* sdrc_d30 */\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /* sdrc_d31 */\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /* sdrc_clk */\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /* sdrc_dqs0 */\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /* sdrc_dqs1 */\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /* sdrc_dqs2 */\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /* sdrc_dqs3 */ \
+	/* GPMC */ \
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M4)) /* gpio_34 */ \
+	MUX_VAL(CP(GPMC_A2),		(IEN  | PTD | DIS | M4)) /* gpio_35 */ \
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M4)) /* gpio_36 */ \
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M4)) /* gpio_37 */\
+	MUX_VAL(CP(GPMC_A5),		(IEN  | PTD | DIS | M4)) /* gpio_38 */\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M4)) /* gpio_39 */\
+	MUX_VAL(CP(GPMC_A7),		(IEN  | PTD | DIS | M4)) /* gpio_40 */\
+	MUX_VAL(CP(GPMC_A8),		(IEN  | PTD | DIS | M4)) /* gpio_41 */\
+	MUX_VAL(CP(GPMC_A9),		(IEN  | PTD | EN  | M4)) /* gpio_42 */\
+	MUX_VAL(CP(GPMC_A10),		(IEN  | PTD | DIS | M4)) /* gpio_43 */\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /* gpmc_d0 */ \
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /* gpmc_d1 */ \
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /* gpmc_d2 */ \
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /* gpmc_d3 */ \
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /* gpmc_d4 */ \
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /* gpmc_d5 */ \
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /* gpmc_d6 */ \
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /* gpmc_d7 */ \
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /* gpmc_d8 */ \
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /* gpmc_d9 */ \
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /* gpmc_d10 */ \
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /* gpmc_d11 */ \
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /* gpmc_d12 */ \
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /* gpmc_d13 */ \
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /* gpmc_d14 */ \
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTD | DIS | M7)) \
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTD | DIS | M4)) /* gpio_52 */ \
+	MUX_VAL(CP(GPMC_NCS2),		(IEN  | PTD | DIS | M4)) /* gpio_53 */ \
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTD | DIS | M4)) /* gpio_54 */ \
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTD | DIS | M4)) /* gpio_55 */ \
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M3)) /* gpio_56 */ \
+	MUX_VAL(CP(GPMC_NCS6),		(IDIS | PTD | DIS | M4)) /* gpio_57 */ \
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTD | DIS | M4)) /* gpio_58 */ \
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M7)) /* safe_mode */ \
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M7)) \
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M7)) \
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M7)) \
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M4)) /* gpio_60 */ \
+	MUX_VAL(CP(GPMC_NBE1),		(IDIS | PTD | DIS | M4)) /* gpio_61 */ \
+	MUX_VAL(CP(GPMC_NWP),		(IDIS | PTD | DIS | M4)) /* gpio_62 */ \
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTD | DIS | M4)) /* gpio_63 */ \
+	MUX_VAL(CP(GPMC_WAIT2),		(IDIS | PTD | DIS | M2)) /* gpio_64 */ \
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTD | DIS | M2)) /* gpio_65 */ \
+	/* DSS */ \
+	MUX_VAL(CP(DSS_PCLK),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_HSYNC),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_VSYNC),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_ACBIAS),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M1)) /* dsi_dx0 */ \
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M1)) /* dsi_dy0 */ \
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M1)) /* dsi_dx1 */ \
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M1)) /* dsi_dy1 */ \
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M1)) /* dsi_dx2 */ \
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M1)) /* dsi_dy2 */ \
+	MUX_VAL(CP(DSS_DATA6),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA7),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA8),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA9),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA10),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA11),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA12),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA13),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA14),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA15),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA16),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M4)) /* gpio_87 */ \
+	MUX_VAL(CP(DSS_DATA18),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA19),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA20),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA21),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA22),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(DSS_DATA23),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	/* CAM */ \
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTD | EN  | M0)) /* cam_hs */ \
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTD | EN  | M0)) /* cam_vs */ \
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /* cam_xclka */ \
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTD | EN  | M0)) /* cam_pclk */ \
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /* gpio_98 */ \
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M2)) /* csi2_dx2 */ \
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M2)) /* csi2_dy2 */ \
+	MUX_VAL(CP(CAM_D2),		(IDIS | PTD | EN  | M4)) /* gpio_101 */ \
+	MUX_VAL(CP(CAM_D3),		(IDIS | PTD | DIS | M7)) /* safe_mode */ \
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /* cam_d4 */ \
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /* cam_d5 */ \
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /* cam_d6 */ \
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /* cam_d7 */ \
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /* cam_d8 */ \
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /* cam_d9 */ \
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /* cam_d10 */ \
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /* cam_d11 */ \
+	MUX_VAL(CP(CAM_XCLKB),		(IEN  | PTD | DIS | M0)) /* cam_xclkb */ \
+	MUX_VAL(CP(CAM_WEN),		(IDIS | PTD | DIS | M4)) /* gpio_167 */ \
+	MUX_VAL(CP(CAM_STROBE),		(IEN  | PTD | DIS | M7)) /* safe_mode */ \
+	/* CSI2 */ \
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /* csi2_dx0 */ \
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /* csi2_dy0 */ \
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /* csi2_dx1 */ \
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /* csi2_dy1 */ \
+	/* MCBSP2 */ \
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /* mcbsp2_fsx */ \
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /* mcbsp2_clkx */ \
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /* mcbsp2_dr */ \
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /* mcbsp2_dx */ \
+	/* MMC1 */ \
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTD | DIS | M0)) /* mmc1_clk */ \
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTD | DIS | M0)) /* mmc1_cmd */ \
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTD | DIS | M0)) /* mmc1_dat0 */ \
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTD | DIS | M0)) /* mmc1_dat1 */ \
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTD | DIS | M0)) /* mmc1_dat2 */ \
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTD | DIS | M0)) /* mmc1_dat3 */ \
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTD | DIS | M7)) /* safe_mode */ \
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTD | DIS | M7)) /* safe_mode */ \
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTD | DIS | M7)) /* safe_mode */ \
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTD | DIS | M7)) /* safe_mode */ \
+	/* MMC2 */ \
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | DIS | M0)) /* mmc2_clk */ \
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTD | DIS | M0)) /* mmc2_cmd */ \
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTD | DIS | M0)) /* mmc2_dat0 */ \
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTD | DIS | M0)) /* mmc2_dat1 */ \
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTD | DIS | M0)) /* mmc2_dat2 */ \
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTD | DIS | M0)) /* mmc2_dat3 */ \
+	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTD | DIS | M0)) /* mmc2_dat4 */ \
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTD | DIS | M0)) /* mmc2_dat5 */ \
+	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTD | DIS | M0)) /* mmc2_dat6 */ \
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTD | DIS | M0)) /* mmc2_dat7 */ \
+	/* MCBSP3 */ \
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) /* mcbsp3_dx */ \
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) /* mcbsp3_dr */ \
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) /* mcbsp3_clkx */ \
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) /* mcbsp3_fsx */ \
+	/* UART2 */ \
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | DIS | M0)) /* uart2_cts */ \
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /* uart2_rts */ \
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /* uart2_tx */ \
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) /* uart2_rx */ \
+	/* UART1 */ \
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /* uart1_tx */ \
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /* uart1_rts */ \
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTD | DIS | M0)) /* uart1_cts */ \
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /* uart1_rx */ \
+	/* MCBSP4 */ \
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /* gpio_152 */ \
+	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /* gpio_153 */ \
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /* gpio_154 */ \
+	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | DIS | M4)) /* gpio_155 */ \
+	/* MCBSP1 */ \
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) /* mcbsp1_clkr */ \
+	MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTD | DIS | M0)) /* mcbsp1_fsr */ \
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) /* mcbsp1_dx */ \
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) /* mcbsp1_dr */ \
+	MUX_VAL(CP(MCBSP_CLKS),		(IDIS | PTD | DIS | M7)) /* safe_mode */ \
+	MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /* gpio_161 */ \
+	MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /* gpio_162 */ \
+	/* UART3 */ \
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M4)) /* gpio_163 */ \
+	MUX_VAL(CP(UART3_RTS_SD),	(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /* uart3_rx_irrx */ \
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /* uart3_tx_irtx */ \
+	/* HSUSB0 */ \
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | EN  | M0)) /* hsusb0_clk */\
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTD | DIS | M0)) /* hsusb0_stp */\
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | EN  | M0)) /* hsusb0_dir */\
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | EN  | M0)) /* hsusb0_nxt */\
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | EN  | M0)) /* hsusb0_data0 */\
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | EN  | M0)) /* hsusb0_data1 */\
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | EN  | M0)) /* hsusb0_data2 */\
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | EN  | M0)) /* hsusb0_data3 */\
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | EN  | M0)) /* hsusb0_data4 */\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | EN  | M0)) /* hsusb0_data5 */\
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | EN  | M0)) /* hsusb0_data6 */\
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | EN  | M0)) /* hsusb0_data7 */ \
+	/* I2C1 */ \
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /* i2c1_scl */ \
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /* i2c1_sda */ \
+	/* I2C2 */ \
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTD | DIS | M0)) /* i2c2_scl */ \
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTD | DIS | M0)) /* i2c2_sda */ \
+	/* I2C3 */ \
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTD | DIS | M0)) /* i2c3_scl */ \
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTD | DIS | M0)) /* i2c3_sda */ \
+	/* I2C4 */ \
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /* i2c4_scl */ \
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /* i2c4_sda */ \
+	/* HDQ */ \
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTD | EN  | M4)) /* gpio_170 */ \
+	/* MCSPI1 */ \
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | DIS | M4)) /* gpio_175 */ \
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | DIS | M4)) /* gpio_176 */ \
+	MUX_VAL(CP(MCSPI1_CS3),		(IDIS | PTD | DIS | M4)) /* gpio_177 */ \
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | EN  | M0)) /* mcspi2_clk */ \
+	MUX_VAL(CP(MCSPI2_SIMO),	(IDIS | PTD | DIS | M0)) /* mcspi2_simo */ \
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /* mcspi2_somi */ \
+	MUX_VAL(CP(MCSPI2_CS0),		(IDIS | PTD | DIS | M4)) /* gpio_181 */ \
+	MUX_VAL(CP(MCSPI2_CS1),		(IDIS | PTD | DIS | M4)) /* gpio_182 */ \
+	/* SYS */ \
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /* sys_32k */ \
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /* sys_clkreq */ \
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /* sys_nirq */ \
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTU | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTU | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(SYS_BOOT6),		(IEN  | PTU | EN  | M7)) /* safe_mode */ \
+	MUX_VAL(CP(SYS_OFF_MODE),	(IDIS | PTD | DIS | M0)) /* sys_off_mode */ \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M4)) /* gpio_10 */ \
+	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTD | EN  | M7)) /* safe_mode */ \
+	/* JTAG */ \
+	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) /* jtag_ntrst */ \
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) /* jtag_tck */ \
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTU | EN  | M0)) /* jtag_tms */ \
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTU | EN  | M0)) /* jtag_tdi */ \
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) /* jtag_emu0 */ \
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) /* jtag_emu1 */ \
+	/* ETK */ \
+	MUX_VAL(CP(ETK_CLK_ES2),	(IEN  | PTD | DIS | M2)) /* sdmmc3_clk */ \
+	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M2)) /* sdmmc3_cmd */ \
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | EN  | M4)) /* gpio_14 */ \
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | DIS | M4)) /* gpio_15 */ \
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | DIS | M4)) /* gpio_16 */ \
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | DIS | M2)) /* sdmmc3_dat3 */ \
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | DIS | M2)) /* sdmmc3_dat0 */ \
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | DIS | M2)) /* sdmmc3_dat1 */ \
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | DIS | M2)) /* sdmmc3_dat2 */ \
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | EN  | M4)) /* gpio_21 */ \
+	MUX_VAL(CP(ETK_D8_ES2),		(IDIS | PTD | DIS | M4)) /* gpio_22 */ \
+	MUX_VAL(CP(ETK_D9_ES2),		(IDIS | PTD | DIS | M4)) /* gpio_23 */ \
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | EN  | M4)) /* gpio_24 */ \
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTD | DIS | M4)) /* gpio_25 */ \
+	MUX_VAL(CP(ETK_D12_ES2),	(IDIS | PTD | DIS | M4)) /* gpio_26 */ \
+	MUX_VAL(CP(ETK_D13_ES2),	(IDIS | PTD | DIS | M4)) /* gpio_27 */ \
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | EN  | M4)) /* gpio_28 */ \
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | EN  | M4)) /* gpio_29 */ \
+	/* D2D */ \
+	MUX_VAL(CP(D2D_MCAD0),		(IEN  | PTD | EN  | M0)) /* d2d_mcad0 */ \
+	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /* d2d_mcad1 */ \
+	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /* d2d_mcad2 */ \
+	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /* d2d_mcad3 */ \
+	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /* d2d_mcad4 */ \
+	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /* d2d_mcad5 */ \
+	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /* d2d_mcad6 */ \
+	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /* d2d_mcad7 */ \
+	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /* d2d_mcad8 */ \
+	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /* d2d_mcad9 */ \
+	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /* d2d_mcad10 */ \
+	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /* d2d_mcad11 */ \
+	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /* d2d_mcad12 */ \
+	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /* d2d_mcad13 */ \
+	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /* d2d_mcad14 */ \
+	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /* d2d_mcad15 */ \
+	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /* d2d_mcad16 */ \
+	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /* d2d_mcad17 */ \
+	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /* d2d_mcad18 */ \
+	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /* d2d_mcad19 */ \
+	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /* d2d_mcad20 */ \
+	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /* d2d_mcad21 */ \
+	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /* d2d_mcad22 */ \
+	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /* d2d_mcad23 */ \
+	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /* d2d_mcad24 */ \
+	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /* d2d_mcad25 */ \
+	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /* d2d_mcad26 */ \
+	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /* d2d_mcad27 */ \
+	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /* d2d_mcad28 */ \
+	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /* d2d_mcad29 */ \
+	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /* d2d_mcad30 */ \
+	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /* d2d_mcad31 */ \
+	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /* d2d_mcad32 */ \
+	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /* d2d_mcad33 */ \
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /* d2d_mcad34 */ \
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /* d2d_mcad35 */ \
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /* d2d_mcad36 */ \
+	MUX_VAL(CP(D2D_CLK26MI),	(IDIS | PTD | DIS | M0)) /* d2d_clk26mi */ \
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTU | EN  | M0)) /* d2d_nrespwron */ \
+	MUX_VAL(CP(D2D_NRESWARM),	(IDIS | PTD | DIS | M0)) /* d2d_nreswarm */ \
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IDIS | PTD | DIS | M0)) /* d2d_arm9nirq */ \
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IDIS | PTD | DIS | M0)) /* d2d_uma2p6fiq */ \
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | DIS | M0)) /* d2d_spint */ \
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | DIS | M0)) /* d2d_frint */ \
+	MUX_VAL(CP(D2D_DMAREQ0),	(IDIS | PTD | DIS | M0)) /* d2d_dmareq0 */ \
+	MUX_VAL(CP(D2D_DMAREQ1),	(IDIS | PTD | DIS | M0)) /* d2d_dmareq1 */ \
+	MUX_VAL(CP(D2D_DMAREQ2),	(IDIS | PTD | DIS | M0)) /* d2d_dmareq2 */ \
+	MUX_VAL(CP(D2D_DMAREQ3),	(IDIS | PTD | DIS | M0)) /* d2d_dmareq3 */ \
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /* d2d_n3gtrst */ \
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTU | EN  | M0)) /* d2d_n3gtdi */ \
+	MUX_VAL(CP(D2D_N3GTDO),		(IDIS | PTD | DIS | M0)) /* d2d_n3gtdo */ \
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTU | EN  | M0)) /* d2d_n3gtms */ \
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /* d2d_n3gtck */ \
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /* d2d_n3grtck */ \
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /* d2d_mstdby */ \
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /* d2d_swakeup */ \
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /* d2d_idlereq */ \
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /* d2d_idleack */ \
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /* d2d_mwrite */ \
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /* d2d_swrite */ \
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /* d2d_mread */ \
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /* d2d_sread */ \
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /* d2d_mbusflag */ \
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /* d2d_sbusflag */ \
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTD | DIS | M0)) /* sdrc_cke0 */ \
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M0)) /* sdrc_cke1 */ \
+	MUX_VAL(CP(GPIO127),		(IEN  | PTD | DIS | M7)) /* safe_mode */ \
+	MUX_VAL(CP(GPIO126),		(IDIS | PTD | DIS | M4)) /* gpio_126 */ \
+	MUX_VAL(CP(GPIO128),		(IDIS | PTD | DIS | M4)) /* gpio_128 */ \
+	MUX_VAL(CP(GPIO129),		(IEN  | PTD | DIS | M4)) /* gpio_129 */
+
+#endif
diff --git a/roms/u-boot/board/liebherr/display5/Kconfig b/roms/u-boot/board/liebherr/display5/Kconfig
new file mode 100644
index 000000000..b096c8917
--- /dev/null
+++ b/roms/u-boot/board/liebherr/display5/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_DISPLAY5
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "display5"
+
+config SYS_VENDOR
+	default "liebherr"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "display5"
+
+endif
diff --git a/roms/u-boot/board/liebherr/display5/MAINTAINERS b/roms/u-boot/board/liebherr/display5/MAINTAINERS
new file mode 100644
index 000000000..52178318b
--- /dev/null
+++ b/roms/u-boot/board/liebherr/display5/MAINTAINERS
@@ -0,0 +1,7 @@
+DISPLAY5 BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/liebherr/display5/
+F:	include/configs/display5.h
+F:	configs/display5_defconfig
+F:	configs/display5_factory_defconfig
diff --git a/roms/u-boot/board/liebherr/display5/Makefile b/roms/u-boot/board/liebherr/display5/Makefile
new file mode 100644
index 000000000..ee503add7
--- /dev/null
+++ b/roms/u-boot/board/liebherr/display5/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2017, DENX Software Engineering
+# Lukasz Majewski <lukma@denx.de>
+#
+# SPDX-License-Identifier:    GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+obj-y = spl.o
+else
+obj-y := display5.o
+endif
diff --git a/roms/u-boot/board/liebherr/display5/common.h b/roms/u-boot/board/liebherr/display5/common.h
new file mode 100644
index 000000000..44c747007
--- /dev/null
+++ b/roms/u-boot/board/liebherr/display5/common.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#ifndef __DISPL5_COMMON_H_
+#define __DISPL5_COMMON_H_
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |	       \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	       \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	       \
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	       \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED	  |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#endif /* __DISPL5_COMMON_H_ */
diff --git a/roms/u-boot/board/liebherr/display5/display5.c b/roms/u-boot/board/liebherr/display5/display5.c
new file mode 100644
index 000000000..e3a59dbec
--- /dev/null
+++ b/roms/u-boot/board/liebherr/display5/display5.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <env.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <malloc.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <linux/delay.h>
+
+#include <dm/platform_data/serial_mxc.h>
+#include <dm/platdata.h>
+
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool hw_ids_valid;
+static bool sw_ids_valid;
+static u32 cpu_id;
+static u32 unit_id;
+
+const char *gpio_table_sw_names[] = {
+	"GPIO2_4", "GPIO2_5", "GPIO2_6", "GPIO2_7"
+};
+
+const char *gpio_table_sw_ids_names[] = {
+	"sw0", "sw1", "sw2", "sw3"
+};
+
+const char *gpio_table_hw_names[] = {
+	"GPIO6_7", "GPIO6_9", "GPIO6_10", "GPIO6_11",
+	"GPIO4_7", "GPIO4_11", "GPIO4_13", "GPIO4_15"
+};
+
+const char *gpio_table_hw_ids_names[] = {
+	"hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7"
+};
+
+static int get_board_id(const char **pin_names, const char **ids_names,
+			int size, bool *valid, u32 *id)
+{
+	struct gpio_desc desc;
+	int i, ret, val;
+
+	*valid = false;
+
+	for (i = 0; i < size; i++) {
+		memset(&desc, 0, sizeof(desc));
+
+		ret = dm_gpio_lookup_name(pin_names[i], &desc);
+		if (ret) {
+			printf("Can't lookup request SWx gpios\n");
+			return ret;
+		}
+
+		ret = dm_gpio_request(&desc, ids_names[i]);
+		if (ret) {
+			printf("Can't lookup request SWx gpios\n");
+			return ret;
+		}
+
+		dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
+
+		val = dm_gpio_get_value(&desc);
+		if (val < 0) {
+			printf("Can't get SW%d ID\n", i);
+			*id = 0;
+			return val;
+		}
+		*id |= val << i;
+	}
+	*valid = true;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+iomux_v3_cfg_t const misc_pads[] = {
+	/* Prod ID GPIO pins */
+	MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* HW revision GPIO pins */
+	MX6_PAD_NANDF_CLE__GPIO6_IO07   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS0__GPIO6_IO11   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* XTALOSC */
+	MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* Emergency recovery pin */
+	MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*
+ * Do not overwrite the console
+ * Always use serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	fdt_fixup_ethernet(blob);
+	return 0;
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* display5 due to PCB routing can only work with 100 Mbps */
+	phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
+				 ADVERTISED_1000baseX_Full |
+				 SUPPORTED_1000baseT_Half |
+				 SUPPORTED_1000baseT_Full);
+
+	if (phydev->drv->config)
+		return phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct gpio_desc phy_int_gbe, spi2_wp;
+	int ret;
+
+	debug("board init\n");
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* Setup misc (application specific) stuff */
+	SETUP_IOMUX_PADS(misc_pads);
+
+	get_board_id(gpio_table_sw_names, &gpio_table_sw_ids_names[0],
+		     ARRAY_SIZE(gpio_table_sw_names), &sw_ids_valid, &unit_id);
+	debug("SWx unit_id 0x%x\n", unit_id);
+
+	get_board_id(gpio_table_hw_names, &gpio_table_hw_ids_names[0],
+		     ARRAY_SIZE(gpio_table_hw_names), &hw_ids_valid, &cpu_id);
+	debug("HWx cpu_id 0x%x\n", cpu_id);
+
+	if (hw_ids_valid && sw_ids_valid)
+		printf("ID:    unit type 0x%x rev 0x%x\n", unit_id, cpu_id);
+
+	udelay(25);
+
+	/* Setup low level FEC (ETH) */
+	ret = dm_gpio_lookup_name("GPIO1_28", &phy_int_gbe);
+	if (ret) {
+		printf("Cannot get GPIO1_28\n");
+	} else {
+		ret = dm_gpio_request(&phy_int_gbe, "INT_GBE");
+		if (!ret)
+			dm_gpio_set_dir_flags(&phy_int_gbe, GPIOD_IS_IN);
+	}
+
+	iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
+	enable_fec_anatop_clock(0, ENET_125MHZ);
+
+	/* Setup #WP for SPI-NOR memory */
+	ret = dm_gpio_lookup_name("GPIO7_0", &spi2_wp);
+	if (ret) {
+		printf("Cannot get GPIO7_0\n");
+	} else {
+		ret = dm_gpio_request(&spi2_wp, "spi2_#wp");
+		if (!ret)
+			dm_gpio_set_dir_flags(&spi2_wp, GPIOD_IS_OUT |
+					      GPIOD_IS_OUT_ACTIVE);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* eMMC, USDHC-4, 8-bit bus width */
+	/* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */
+	{"emmc",    MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+	{"spinor",  MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)},
+	{NULL,	0},
+};
+
+static void setup_boot_modes(void)
+{
+	add_board_boot_modes(board_boot_modes);
+}
+#else
+static inline void setup_boot_modes(void) {}
+#endif
+
+int misc_init_r(void)
+{
+	struct gpio_desc em_pad;
+	int ret;
+
+	setup_boot_modes();
+
+	ret = dm_gpio_lookup_name("GPIO3_29", &em_pad);
+	if (ret) {
+		printf("Can't find emergency PAD gpio\n");
+		return ret;
+	}
+
+	ret = dm_gpio_request(&em_pad, "Emergency_PAD");
+	if (ret) {
+		printf("Can't request emergency PAD gpio\n");
+		return ret;
+	}
+
+	dm_gpio_set_dir_flags(&em_pad, GPIOD_IS_IN);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/liebherr/display5/spl.c b/roms/u-boot/board/liebherr/display5/spl.c
new file mode 100644
index 000000000..39f70f578
--- /dev/null
+++ b/roms/u-boot/board/liebherr/display5/spl.c
@@ -0,0 +1,402 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <serial.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include "asm/arch/crm_regs.h"
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/imx-regs.h>
+#include "asm/arch/iomux.h"
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <netdev.h>
+#include <bootcount.h>
+#include <watchdog.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdclk_1 = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_reset = 0x00000030,
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = 0x00000030,
+	.dram_sdodt1 = 0x00000030,
+
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_sdqs2 = 0x00000030,
+	.dram_sdqs3 = 0x00000030,
+	.dram_sdqs4 = 0x00000030,
+	.dram_sdqs5 = 0x00000030,
+	.dram_sdqs6 = 0x00000030,
+	.dram_sdqs7 = 0x00000030,
+
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_dqm2 = 0x00000030,
+	.dram_dqm3 = 0x00000030,
+	.dram_dqm4 = 0x00000030,
+	.dram_dqm5 = 0x00000030,
+	.dram_dqm6 = 0x00000030,
+	.dram_dqm7 = 0x00000030,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_b2ds = 0x00000030,
+	.grp_b3ds = 0x00000030,
+	.grp_b4ds = 0x00000030,
+	.grp_b5ds = 0x00000030,
+	.grp_b6ds = 0x00000030,
+	.grp_b7ds = 0x00000030,
+};
+
+/* 4x128Mx16.cfg */
+static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x002D0028,
+	.p0_mpwldectrl1 = 0x0032002D,
+	.p1_mpwldectrl0 = 0x00210036,
+	.p1_mpwldectrl1 = 0x0019002E,
+	.p0_mpdgctrl0 = 0x4349035C,
+	.p0_mpdgctrl1 = 0x0348033D,
+	.p1_mpdgctrl0 = 0x43550362,
+	.p1_mpdgctrl1 = 0x03520316,
+	.p0_mprddlctl = 0x41393940,
+	.p1_mprddlctl = 0x3F3A3C47,
+	.p0_mpwrdlctl = 0x413A423A,
+	.p1_mpwrdlctl = 0x4042483E,
+};
+
+/* MT41K128M16JT-125 (2Gb density) */
+static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+iomux_v3_cfg_t const uart_console_pads[] = {
+	/* UART5 */
+	MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+void displ5_set_iomux_uart_spl(void)
+{
+	SETUP_IOMUX_PADS(uart_console_pads);
+}
+
+iomux_v3_cfg_t const misc_pads_spl[] = {
+	/* Emergency recovery pin */
+	MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void displ5_set_iomux_misc_spl(void)
+{
+	SETUP_IOMUX_PADS(misc_pads_spl);
+}
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi2_pads[] = {
+	/* SPI2, NOR Flash nWP, CS0 */
+	MX6_PAD_CSI0_DAT10__ECSPI2_MISO	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI0_DAT9__ECSPI2_MOSI	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI0_DAT8__ECSPI2_SCLK	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__GPIO5_IO29	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__GPIO7_IO00	| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+	if (bus != 1 || cs != 0)
+		return -EINVAL;
+
+	return IMX_GPIO_NR(5, 29);
+}
+
+void displ5_set_iomux_ecspi_spl(void)
+{
+	SETUP_IOMUX_PADS(ecspi2_pads);
+}
+
+#else
+void displ5_set_iomux_ecspi_spl(void) {}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__SD4_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__SD4_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__SD4_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__SD4_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__SD4_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_ALE__SD4_RESET	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+void displ5_set_iomux_usdhc_spl(void)
+{
+	SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+#else
+void displ5_set_iomux_usdhc_spl(void) {}
+#endif
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC3F, &ccm->CCGR1);
+	writel(0x0FFFCFC0, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+#ifdef CONFIG_MX6_DDRCAL
+static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+	struct mx6_mmdc_calibration calibration = {0};
+
+	mmdc_read_calibration(sysinfo, &calibration);
+
+	debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
+	debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
+	debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
+	debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
+	debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
+	debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
+	debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
+	debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
+	debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
+	debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
+	debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
+	debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
+}
+
+static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+	int ret;
+
+	/* Perform DDR DRAM calibration */
+	udelay(100);
+	ret = mmdc_do_write_level_calibration(sysinfo);
+	if (ret) {
+		printf("DDR: Write level calibration error [%d]\n", ret);
+		return;
+	}
+
+	ret = mmdc_do_dqs_calibration(sysinfo);
+	if (ret) {
+		printf("DDR: DQS calibration error [%d]\n", ret);
+		return;
+	}
+
+	spl_dram_print_cal(sysinfo);
+}
+#endif /* CONFIG_MX6_DDRCAL */
+
+static void spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize = 2,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density = 32, /* 32Gb per CS */
+		/* single chip select */
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
+		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
+		.walat = 1,	/* Write additional latency */
+		.ralat = 5,	/* Read additional latency */
+		.mif3_mode = 3,	/* Command prediction working mode */
+		.bi_on = 1,	/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
+		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
+	};
+
+	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
+
+#ifdef CONFIG_MX6_DDRCAL
+	spl_dram_perform_cal(&sysinfo);
+#endif
+}
+
+#ifdef CONFIG_SPL_SPI_SUPPORT
+static void displ5_init_ecspi(void)
+{
+	displ5_set_iomux_ecspi_spl();
+	enable_spi_clk(1, 1);
+}
+#else
+static inline void displ5_init_ecspi(void) { }
+#endif
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+static struct fsl_esdhc_cfg usdhc_cfg = {
+	.esdhc_base = USDHC4_BASE_ADDR,
+	.max_bus_width = 8,
+};
+
+int board_mmc_init(struct bd_info *bd)
+{
+	displ5_set_iomux_usdhc_spl();
+
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+	gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
+
+	return fsl_esdhc_initialize(bd, &usdhc_cfg);
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+	displ5_set_iomux_uart_spl();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	displ5_init_ecspi();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	displ5_set_iomux_misc_spl();
+
+	/* Initialize and reset WDT in SPL */
+	hw_watchdog_init();
+	WATCHDOG_RESET();
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+#define EM_PAD IMX_GPIO_NR(3, 29)
+int board_check_emergency_pad(void)
+{
+	int ret;
+
+	ret = gpio_direction_input(EM_PAD);
+	if (ret)
+		return ret;
+
+	return !gpio_get_value(EM_PAD);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	/* Default boot sequence SPI -> MMC */
+	spl_boot_list[0] = spl_boot_device();
+	spl_boot_list[1] = BOOT_DEVICE_MMC1;
+	spl_boot_list[2] = BOOT_DEVICE_UART;
+	spl_boot_list[3] = BOOT_DEVICE_NONE;
+
+	/*
+	 * In case of emergency PAD pressed, we always boot
+	 * to proper u-boot and perform recovery tasks there.
+	 */
+	if (board_check_emergency_pad())
+		return;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	/* 'fastboot' */
+	const char *s;
+
+	if (env_init() || env_load())
+		return;
+
+	s = env_get("BOOT_FROM");
+	if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
+		spl_boot_list[0] = BOOT_DEVICE_MMC1;
+		spl_boot_list[1] = spl_boot_device();
+	}
+#endif
+}
+
+void reset_cpu(void) {}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	if (env_get_yesno("boot_os") != 1)
+		return 1;
+#endif
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/liebherr/mccmon6/Kconfig b/roms/u-boot/board/liebherr/mccmon6/Kconfig
new file mode 100644
index 000000000..4cc7fc2ba
--- /dev/null
+++ b/roms/u-boot/board/liebherr/mccmon6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MCCMON6
+
+config SYS_BOARD
+	default "mccmon6"
+
+config SYS_VENDOR
+	default "liebherr"
+
+config SYS_CONFIG_NAME
+	default "mccmon6"
+
+endif
diff --git a/roms/u-boot/board/liebherr/mccmon6/MAINTAINERS b/roms/u-boot/board/liebherr/mccmon6/MAINTAINERS
new file mode 100644
index 000000000..c9c718305
--- /dev/null
+++ b/roms/u-boot/board/liebherr/mccmon6/MAINTAINERS
@@ -0,0 +1,7 @@
+MCCMON6 BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/liebherr/mccmon6/
+F:	include/configs/mccmon6.h
+F:	configs/mccmon6_nor_defconfig
+F:	configs/mccmon6_sd_defconfig
diff --git a/roms/u-boot/board/liebherr/mccmon6/Makefile b/roms/u-boot/board/liebherr/mccmon6/Makefile
new file mode 100644
index 000000000..3c9786c6b
--- /dev/null
+++ b/roms/u-boot/board/liebherr/mccmon6/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016-2017
+# Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ifdef CONFIG_SPL_BUILD
+obj-y  := spl.o
+else
+obj-y  := mccmon6.o
+endif
diff --git a/roms/u-boot/board/liebherr/mccmon6/mccmon6.c b/roms/u-boot/board/liebherr/mccmon6/mccmon6.c
new file mode 100644
index 000000000..1b49526fb
--- /dev/null
+++ b/roms/u-boot/board/liebherr/mccmon6/mccmon6.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <serial.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	env_set("board_name", "mccmon6");
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MCCMON6\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/liebherr/mccmon6/mon6_imximage_nor.cfg b/roms/u-boot/board/liebherr/mccmon6/mon6_imximage_nor.cfg
new file mode 100644
index 000000000..6f966a7dd
--- /dev/null
+++ b/roms/u-boot/board/liebherr/mccmon6/mon6_imximage_nor.cfg
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+IMAGE_VERSION	2
+BOOT_FROM	nor
diff --git a/roms/u-boot/board/liebherr/mccmon6/mon6_imximage_sd.cfg b/roms/u-boot/board/liebherr/mccmon6/mon6_imximage_sd.cfg
new file mode 100644
index 000000000..5a65e0f54
--- /dev/null
+++ b/roms/u-boot/board/liebherr/mccmon6/mon6_imximage_sd.cfg
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+IMAGE_VERSION	2
+BOOT_FROM	sd
diff --git a/roms/u-boot/board/liebherr/mccmon6/spl.c b/roms/u-boot/board/liebherr/mccmon6/spl.c
new file mode 100644
index 000000000..56eae3b4e
--- /dev/null
+++ b/roms/u-boot/board/liebherr/mccmon6/spl.c
@@ -0,0 +1,577 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Wandboard
+ * Author: Tungyi Lin <tungyilin1127@gmail.com>
+ *         Richard Hu <hakahu@gmail.com>
+ */
+
+#include <image.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <serial.h>
+#include <spl.h>
+#include <linux/delay.h>
+
+#include <asm/arch/mx6-ddr.h>
+/*
+ * Driving strength:
+ *   0x30 == 40 Ohm
+ *   0x28 == 48 Ohm
+ */
+
+#define IMX6DQ_DRIVE_STRENGTH		0x30
+#define IMX6SDL_DRIVE_STRENGTH		0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
+	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
+	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
+	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
+	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* H5T04G63AFR-PB */
+static struct mx6_ddr3_cfg h5t04g63afr = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+/* H5TQ2G63DFR-H9 */
+static struct mx6_ddr3_cfg h5tq2g63dfr = {
+	.mem_speed = 1333,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1350,
+	.trcmin = 4950,
+	.trasmin = 3600,
+};
+
+static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x001f001f,
+	.p0_mpwldectrl1 = 0x001f001f,
+	.p1_mpwldectrl0 = 0x001f001f,
+	.p1_mpwldectrl1 = 0x001f001f,
+	.p0_mpdgctrl0 = 0x4301030d,
+	.p0_mpdgctrl1 = 0x03020277,
+	.p1_mpdgctrl0 = 0x4300030a,
+	.p1_mpdgctrl1 = 0x02780248,
+	.p0_mprddlctl = 0x4536393b,
+	.p1_mprddlctl = 0x36353441,
+	.p0_mpwrdlctl = 0x41414743,
+	.p1_mpwrdlctl = 0x462f453f,
+};
+
+/* DDR 64bit 2GB */
+static struct mx6_ddr_sysinfo mem_q = {
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x001f001f,
+	.p0_mpwldectrl1 = 0x001f001f,
+	.p1_mpwldectrl0 = 0x001f001f,
+	.p1_mpwldectrl1 = 0x001f001f,
+	.p0_mpdgctrl0 = 0x420e020e,
+	.p0_mpdgctrl1 = 0x02000200,
+	.p1_mpdgctrl0 = 0x42020202,
+	.p1_mpdgctrl1 = 0x01720172,
+	.p0_mprddlctl = 0x494c4f4c,
+	.p1_mprddlctl = 0x4a4c4c49,
+	.p0_mpwrdlctl = 0x3f3f3133,
+	.p1_mpwrdlctl = 0x39373f2e,
+};
+
+static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x0040003c,
+	.p0_mpwldectrl1 = 0x0032003e,
+	.p0_mpdgctrl0 = 0x42350231,
+	.p0_mpdgctrl1 = 0x021a0218,
+	.p0_mprddlctl = 0x4b4b4e49,
+	.p0_mpwrdlctl = 0x3f3f3035,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+	.dsize		= 1,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
+	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
+		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
+	} else if (is_cpu_type(MXC_CPU_MX6Q)) {
+		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+		mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
+	}
+
+	udelay(100);
+}
+
+static void setup_spi(void)
+{
+	enable_spi_clk(true, 2);
+}
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* iomux */
+	setup_iomux_uart();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* enable ECSPI clocks */
+	setup_spi();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[0] = BOOT_DEVICE_MMC2;
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+		break;
+
+	case BOOT_DEVICE_NOR:
+		spl_boot_list[0] = BOOT_DEVICE_NOR;
+		break;
+	}
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	char s[16];
+	int ret;
+	/*
+	 * We use BOOT_DEVICE_MMC1, but SD card is connected
+	 * to MMC2
+	 *
+	 * Correct "mapping" is delivered in board defined
+	 * board_boot_order() function.
+	 *
+	 * SD card boot is regarded as a "development" one,
+	 * hence we _always_ go through the u-boot.
+	 *
+	 */
+	if (spl_boot_device() == BOOT_DEVICE_MMC1)
+		return 1;
+
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	env_init();
+	ret = env_get_f("boot_os", s, sizeof(s));
+	if ((ret != -1) && (strcmp(s, "no") == 0))
+		return 1;
+
+	/*
+	 * Check if SWUpdate recovery needs to be started
+	 *
+	 * recovery_status = NULL (not set - ret == -1) -> normal operation
+	 *
+	 * recovery_status = progress or
+	 * recovery_status = failed   or
+	 * recovery_status = <any value> -> start SWUpdate
+	 *
+	 */
+	ret = env_get_f("recovery_status", s, sizeof(s));
+	if (ret != -1)
+		return 1;
+
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define NOR_WP			IMX_GPIO_NR(1, 1)
+
+static iomux_v3_cfg_t const eimnor_pads[] = {
+	IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA0__EIM_AD00   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA1__EIM_AD01   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA2__EIM_AD02   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA3__EIM_AD03   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA4__EIM_AD04   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA5__EIM_AD05   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA6__EIM_AD06   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA7__EIM_AD07   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA8__EIM_AD08   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA9__EIM_AD09   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA10__EIM_AD10  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA11__EIM_AD11  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA12__EIM_AD12  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA13__EIM_AD13  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA14__EIM_AD14  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA15__EIM_AD15  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_OE__EIM_OE_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_RW__EIM_RW		| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void eimnor_cs_setup(void)
+{
+	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+	/* NOR configuration */
+	writel(0x00620181, &weim_regs->cs0gcr1);
+	writel(0x00000001, &weim_regs->cs0gcr2);
+	writel(0x0b020000, &weim_regs->cs0rcr1);
+	writel(0x0000b000, &weim_regs->cs0rcr2);
+	writel(0x0804a240, &weim_regs->cs0wcr1);
+	writel(0x00000000, &weim_regs->cs0wcr2);
+
+	writel(0x00000120, &weim_regs->wcr);
+	writel(0x00000010, &weim_regs->wiar);
+	writel(0x00000000, &weim_regs->ear);
+
+	set_chipselect_size(CS0_128);
+}
+
+static void setup_eimnor(void)
+{
+	SETUP_IOMUX_PADS(eimnor_pads);
+	gpio_direction_output(NOR_WP, 1);
+
+	enable_eim_clk(1);
+	eimnor_cs_setup();
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC2_CD_GPIO		IMX_GPIO_NR(1, 4)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* Carrier MicroSD Card Detect */
+	IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		/*
+		 * eMMC don't have card detect pin - since it is soldered to the
+		 * PCB board
+		 */
+		ret = 1;
+		break;
+	}
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int ret;
+	u32 index = 0;
+
+	/*
+	 * MMC MAP
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    Soldered on board eMMC device
+	 * mmc1                    MicroSD card
+	 */
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			usdhc_cfg[0].max_bus_width = 8;
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			usdhc_cfg[1].max_bus_width = 4;
+			gpio_direction_input(USDHC2_CD_GPIO);
+			break;
+		default:
+			printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
+			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BOARD_INIT
+#define DISPLAY_EN		IMX_GPIO_NR(1, 2)
+void spl_board_init(void)
+{
+	setup_eimnor();
+
+	gpio_direction_output(DISPLAY_EN, 1);
+}
+#endif /* CONFIG_SPL_BOARD_INIT */
diff --git a/roms/u-boot/board/liebherr/xea/Kconfig b/roms/u-boot/board/liebherr/xea/Kconfig
new file mode 100644
index 000000000..5428de464
--- /dev/null
+++ b/roms/u-boot/board/liebherr/xea/Kconfig
@@ -0,0 +1,24 @@
+if TARGET_XEA
+
+config SYS_BOARD
+	default "xea"
+
+config SYS_VENDOR
+	default "liebherr"
+
+config SYS_SOC
+	default "mxs"
+
+config SYS_CONFIG_NAME
+	default "xea"
+
+config ENV_SIZE
+	default 0x2000
+
+config ENV_SECT_SIZE
+	default 0x10000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+	default 0x80000 if ENV_IS_IN_SPI_FLASH
+
+endif
diff --git a/roms/u-boot/board/liebherr/xea/MAINTAINERS b/roms/u-boot/board/liebherr/xea/MAINTAINERS
new file mode 100644
index 000000000..623184d0f
--- /dev/null
+++ b/roms/u-boot/board/liebherr/xea/MAINTAINERS
@@ -0,0 +1,6 @@
+XEA BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/liebherr/xea/
+F:	include/configs/xea.h
+F:	configs/imx28_xea_defconfig
diff --git a/roms/u-boot/board/liebherr/xea/Makefile b/roms/u-boot/board/liebherr/xea/Makefile
new file mode 100644
index 000000000..abf500857
--- /dev/null
+++ b/roms/u-boot/board/liebherr/xea/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2019
+# Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= xea.o
+
+ifdef	CONFIG_SPL_BUILD
+obj-y	+= spl_xea.o
+endif
diff --git a/roms/u-boot/board/liebherr/xea/README b/roms/u-boot/board/liebherr/xea/README
new file mode 100644
index 000000000..3e55d3ea4
--- /dev/null
+++ b/roms/u-boot/board/liebherr/xea/README
@@ -0,0 +1,63 @@
+Building SPL/U-Boot for xea board
+=================================
+
+Setup environment, configure and build, e.g. by:
+
+ $ make imx28_xea_defconfig
+ $ make -j4 u-boot.sb u-boot.img
+
+Now you should see u-boot.sb and u-boot.img files in the build directory.
+
+
+Booting
+=======
+
+The boot ROM loads SPL from SPI NOR flash into SRAM.  SPL configures
+DRAM and loads either a Linux kernel (falcon mode) or, if the rescue
+pin is asserted, the main U-Boot.  Both kernel and U-Boot reside in
+eMMC boot partition 0.  For redundancy, a copy of U-Boot is also
+stored in SPI flash.  If a valid kernel image is not found, U-Boot is
+loaded from eMMC or, if this fails, SPI flash.
+
+Boot area layout
+----------------
+
+SPI NOR
+Offset          Function        File
+------------------------------------------
+0x00000000      SPL             u-boot.sb
+0x00010000      U-Boot          u-boot.img
+0x00080000      Environment
+
+eMMC
+Offset          Function        File
+------------------------------------------
+0x00000000      U-Boot          u-boot.img
+0x00080000      Devicetree      imx28-bttc.dtb
+0x00100000      Kernel          uImage
+
+
+Falcon mode
+===========
+
+In falcon mode, the default, SPL loads the kernel and devicetree
+directly.  For this to work, the stored devicetree must include
+correct "memory" and "chosen" nodes as these are not updated by SPL
+before booting the kernel.
+
+
+Updating from U-Boot
+====================
+
+The default U-Boot environment includes command sequences to update
+SPL, U-Boot, and kernel over TFTP.  These are as follows:
+
+- update_spl: writes u-boot.sb to SPI NOR
+- update_uboot: writes u-boot.img to eMMC and SPI NOR
+- update_kernel: writes kernel and devicetree to eMMC
+
+They can be invoked at the U-Boot prompt using the "run" command,
+e.g. "run update_spl" to update the SPL.
+
+These update commands download the above-named files from the
+${hostname} directory on the server provided by DHCP.
diff --git a/roms/u-boot/board/liebherr/xea/spl_xea.c b/roms/u-boot/board/liebherr/xea/spl_xea.c
new file mode 100644
index 000000000..192f68fca
--- /dev/null
+++ b/roms/u-boot/board/liebherr/xea/spl_xea.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DENX M28 Boot setup
+ *
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (C) 2018 DENX Software Engineering
+ * Måns Rullgård, DENX Software Engineering, mans@mansr.com
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_BOOT	(MXS_PAD_3V3)
+#define	MUX_CONFIG_TSC	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* AUART0 IRDA */
+	MX28_PAD_AUART0_RX__AUART0_RX,
+	MX28_PAD_AUART0_TX__AUART0_TX,
+
+	/* AUART 4 RS422 */
+	MX28_PAD_AUART0_CTS__AUART4_RX,
+	MX28_PAD_AUART0_RTS__AUART4_TX,
+
+	/* USB0 */
+	MX28_PAD_AUART1_CTS__USB0_OVERCURRENT,
+	MX28_PAD_AUART1_RTS__USB0_ID,
+	MX28_PAD_LCD_VSYNC__GPIO_1_28, /* PRW_On */
+
+	/* USB1 */
+	MX28_PAD_PWM2__USB1_OVERCURRENT,
+
+	/* eMMC */
+	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DETECT__GPIO_2_9, /* Reset for eMMC */
+	MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0,
+
+	/* DIG Keys */
+	MX28_PAD_GPMI_D00__GPIO_0_0,
+	MX28_PAD_GPMI_D01__GPIO_0_1,
+	MX28_PAD_GPMI_D02__GPIO_0_2,
+	MX28_PAD_GPMI_D03__GPIO_0_3,
+	MX28_PAD_GPMI_D04__GPIO_0_4,
+	MX28_PAD_GPMI_D05__GPIO_0_5,
+	MX28_PAD_GPMI_D06__GPIO_0_6,
+	MX28_PAD_GPMI_D07__GPIO_0_7,
+
+	/* ADR_0-2 */
+	MX28_PAD_GPMI_CE1N__GPIO_0_17,
+	MX28_PAD_GPMI_CE2N__GPIO_0_18,
+	MX28_PAD_GPMI_CE3N__GPIO_0_19,
+
+	/* Read Keys */
+	MX28_PAD_GPMI_RDY0__GPIO_0_20,
+
+	/* LATCH_EN */
+	MX28_PAD_GPMI_RDY1__GPIO_0_21,
+
+	/* Power off */
+	MX28_PAD_GPMI_RDN__GPIO_0_24,
+
+	/* I2C1 Touch */
+	MX28_PAD_AUART2_CTS__GPIO_3_10,
+	MX28_PAD_AUART2_RTS__GPIO_3_11,
+	MX28_PAD_GPMI_RDY2__GPIO_0_22, /* Touch Reset */
+
+	/* TIVA */
+	MX28_PAD_AUART1_RX__SSP2_CARD_DETECT,
+	MX28_PAD_SSP2_MISO__SSP2_D0,
+	MX28_PAD_SSP2_MOSI__SSP2_CMD,
+	MX28_PAD_SSP2_SCK__SSP2_SCK,
+	MX28_PAD_SSP2_SS0__SSP2_D3,
+	MX28_PAD_SSP2_SS1__GPIO_2_20,
+	MX28_PAD_SSP2_SS2__GPIO_2_21,
+
+	/* SPI3 NOR-Flash */
+	MX28_PAD_AUART1_TX__SSP3_CARD_DETECT,
+	MX28_PAD_AUART2_RX__SSP3_D1,
+	MX28_PAD_AUART2_TX__SSP3_D2,
+	MX28_PAD_SSP3_MISO__SSP3_D0,
+	MX28_PAD_SSP3_MOSI__SSP3_CMD,
+	MX28_PAD_SSP3_SCK__SSP3_SCK,
+	MX28_PAD_SSP3_SS0__SSP3_D3,
+
+	/* NOR-Flash CMD */
+	MX28_PAD_LCD_RS__GPIO_1_26, /* Hold */
+	MX28_PAD_LCD_WR_RWN__GPIO_1_25, /* write protect */
+
+	/* I2C0 Codec */
+	MX28_PAD_I2C0_SCL__I2C0_SCL,
+	MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+	/* I2S Codec */
+	MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK,
+	MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK,
+	MX28_PAD_SAIF0_MCLK__SAIF0_MCLK,
+	MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0,
+	MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0,
+
+	/* PWR-Hold */
+	MX28_PAD_SPDIF__GPIO_3_27,
+
+	/* EMI */
+	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+	/* Uart3 Bluetooth-Interface */
+	MX28_PAD_AUART3_CTS__AUART3_CTS,
+	MX28_PAD_AUART3_RTS__AUART3_RTS,
+	MX28_PAD_AUART3_RX__AUART3_RX,
+	MX28_PAD_AUART3_TX__AUART3_TX,
+
+	/* framebuffer */
+	MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
+
+	/* DUART RS232 */
+	MX28_PAD_PWM0__DUART_RX,
+	MX28_PAD_PWM1__DUART_TX,
+
+	/* FEC Ethernet */
+	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RX_CLK__GPIO_4_13, /* Phy Interrupt */
+	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* n.c. */
+	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_SSP1_CMD__GPIO_2_13, /* PHY reset */
+
+	/* TIVA boot control */
+	MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_BOOT, /* TIVA0 */
+	MX28_PAD_GPMI_WRN__GPIO_0_25 | MUX_CONFIG_BOOT, /* TIVA1 */
+};
+
+u32 mxs_dram_vals[] = {
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000100, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010101, 0x01010101,
+	0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101,
+	0x00000100, 0x00000100, 0x00000000, 0x00000002,
+	0x01010000, 0x07080403, 0x07005303, 0x0b0000c8,
+	0x0200a0c1, 0x0002040c, 0x0038430a, 0x04290322,
+	0x02040203, 0x00c8002b, 0x00000000, 0x00000000,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+	0x00000003, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000612, 0x01000102,
+	0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
+	0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300,
+	0x07400300, 0x07400300, 0x07400300, 0x00000005,
+	0x00000000, 0x00000000, 0x01000000, 0x00000000,
+	0x00000001, 0x000f1133, 0x00000000, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010000, 0x00030404,
+	0x00000002, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x01010000,
+	0x01000000, 0x03030000, 0x00010303, 0x01020202,
+	0x00000000, 0x02040101, 0x21002103, 0x00061200,
+	0x06120612, 0x00000642, 0x00000000, 0x00000004,
+	0x00000000, 0x00000080, 0x00000000, 0x00000000,
+	0x00000000, 0xffffffff
+};
+
+void lowlevel_init(void)
+{
+	struct mxs_pinctrl_regs *pinctrl_regs =
+		(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
+
+	/* Set EMI drive strength */
+	writel(0x00003fff, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr);
+	writel(0x00002aaa, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
+
+	mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/roms/u-boot/board/liebherr/xea/xea.c b/roms/u-boot/board/liebherr/xea/xea.c
new file mode 100644
index 000000000..cd11b0ada
--- /dev/null
+++ b/roms/u-boot/board/liebherr/xea/xea.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * XEA iMX28 board
+ *
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (C) 2018 DENX Software Engineering
+ * Måns Rullgård, DENX Software Engineering, mans@mansr.com
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/delay.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+#include <usb.h>
+#include <serial.h>
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+
+static void init_clocks(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+	/* IO1 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+	/* SSP0 clock at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+	/* SSP2 clock at 160MHz */
+	mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
+	/* SSP3 clock at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK3, 96000, 0);
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong arg)
+{
+	init_clocks();
+	preloader_console_init();
+}
+
+static int boot_tiva0, boot_tiva1;
+
+/* Check if TIVAs request booting via U-Boot proper */
+void spl_board_init(void)
+{
+	struct gpio_desc btiva0, btiva1, en_3_3v;
+	int ret;
+
+	/*
+	 * Setup GPIO0_0 (TIVA power enable pin) to be output high
+	 * to allow TIVA startup.
+	 */
+	ret = dm_gpio_lookup_name("GPIO0_0", &en_3_3v);
+	if (ret)
+		printf("Cannot get GPIO0_0\n");
+
+	ret = dm_gpio_request(&en_3_3v, "pwr_3_3v");
+	if (ret)
+		printf("Cannot request GPIO0_0\n");
+
+	/* Set GPIO0_0 to HIGH */
+	dm_gpio_set_dir_flags(&en_3_3v, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	ret = dm_gpio_lookup_name("GPIO0_23", &btiva0);
+	if (ret)
+		printf("Cannot get GPIO0_23\n");
+
+	ret = dm_gpio_lookup_name("GPIO0_25", &btiva1);
+	if (ret)
+		printf("Cannot get GPIO0_25\n");
+
+	ret = dm_gpio_request(&btiva0, "boot-tiva0");
+	if (ret)
+		printf("Cannot request GPIO0_23\n");
+
+	ret = dm_gpio_request(&btiva1, "boot-tiva1");
+	if (ret)
+		printf("Cannot request GPIO0_25\n");
+
+	dm_gpio_set_dir_flags(&btiva0, GPIOD_IS_IN);
+	dm_gpio_set_dir_flags(&btiva1, GPIOD_IS_IN);
+
+	udelay(1000);
+
+	boot_tiva0 = dm_gpio_get_value(&btiva0);
+	boot_tiva1 = dm_gpio_get_value(&btiva1);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = BOOT_DEVICE_MMC1;
+	spl_boot_list[1] = BOOT_DEVICE_SPI;
+	spl_boot_list[2] = BOOT_DEVICE_UART;
+}
+
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	debug("%s: btiva0: %d btiva1: %d\n", __func__, boot_tiva0, boot_tiva1);
+	return !boot_tiva0 || !boot_tiva1;
+}
+#else
+
+int board_early_init_f(void)
+{
+	init_clocks();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct gpio_desc phy_rst;
+	int ret;
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	cpu_eth_init(NULL);
+
+	/* PHY INT#/PWDN# */
+	ret = dm_gpio_lookup_name("GPIO4_13", &phy_rst);
+	if (ret) {
+		printf("Cannot get GPIO4_13\n");
+		return ret;
+	}
+
+	ret = dm_gpio_request(&phy_rst, "phy-rst");
+	if (ret) {
+		printf("Cannot request GPIO4_13\n");
+		return ret;
+	}
+
+	dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_IN);
+	udelay(1000);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+static int fdt_fixup_l2switch(void *blob)
+{
+	u8 ethaddr[6];
+	int ret;
+
+	if (eth_env_get_enetaddr("ethaddr", ethaddr)) {
+		ret = fdt_find_and_setprop(blob,
+					   "/ahb@80080000/switch@800f0000",
+					   "local-mac-address", ethaddr, 6, 1);
+		if (ret < 0)
+			printf("%s: can't find usbether@1 node: %d\n",
+			       __func__, ret);
+	}
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	/*
+	 * i.MX28 L2 switch needs manual update (fixup) of eth MAC address
+	 * (in 'local-mac-address' property) as it uses "switch@800f0000"
+	 * node, not set by default FIT image handling code in
+	 * "ethernet@800f0000"
+	 */
+	fdt_fixup_l2switch(blob);
+
+	return 0;
+}
+#endif
+
+#endif	/* CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/logicpd/am3517evm/Kconfig b/roms/u-boot/board/logicpd/am3517evm/Kconfig
new file mode 100644
index 000000000..743e500a5
--- /dev/null
+++ b/roms/u-boot/board/logicpd/am3517evm/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_AM3517_EVM
+
+config SYS_BOARD
+	default "am3517evm"
+
+config SYS_VENDOR
+	default "logicpd"
+
+config SYS_CONFIG_NAME
+	default "am3517_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/logicpd/am3517evm/MAINTAINERS b/roms/u-boot/board/logicpd/am3517evm/MAINTAINERS
new file mode 100644
index 000000000..198023fb1
--- /dev/null
+++ b/roms/u-boot/board/logicpd/am3517evm/MAINTAINERS
@@ -0,0 +1,6 @@
+AM3517EVM BOARD
+M:	Adam Ford <aford173@gmail.com>
+S:	Maintained
+F:	board/logicpd/am3517evm/
+F:	include/configs/am3517_evm.h
+F:	configs/am3517_evm_defconfig
diff --git a/roms/u-boot/board/logicpd/am3517evm/Makefile b/roms/u-boot/board/logicpd/am3517evm/Makefile
new file mode 100644
index 000000000..c07a98e93
--- /dev/null
+++ b/roms/u-boot/board/logicpd/am3517evm/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Based on ti/evm/Makefile
+#
+# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+
+obj-y	:= am3517evm.o
diff --git a/roms/u-boot/board/logicpd/am3517evm/am3517evm.c b/roms/u-boot/board/logicpd/am3517evm/am3517evm.c
new file mode 100644
index 000000000..f01416592
--- /dev/null
+++ b/roms/u-boot/board/logicpd/am3517evm/am3517evm.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am3517evm.c - board file for TI's AM3517 family of devices.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <net.h>
+#include <ns16550.h>
+#include <serial.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/omap_musb.h>
+#include <asm/arch/am35x_def.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/musb.h>
+#include <asm/mach-types.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include <i2c.h>
+#include "am3517evm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AM3517_IP_SW_RESET	0x48002598
+#define CPGMACSS_SW_RST		(1 << 1)
+#define PHY_GPIO		30
+
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+#endif
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_MUSB_AM35X
+static struct musb_hdrc_config musb_config = {
+	.multipoint     = 1,
+	.dyn_fifo       = 1,
+	.num_eps        = 16,
+	.ram_bits       = 12,
+};
+
+static struct omap_musb_board_data musb_board_data = {
+	.set_phy_power		= am35x_musb_phy_power,
+	.clear_irq		= am35x_musb_clear_irq,
+	.reset			= am35x_musb_reset,
+};
+
+static struct musb_hdrc_platform_data musb_plat = {
+#if defined(CONFIG_USB_MUSB_HOST)
+	.mode           = MUSB_HOST,
+#elif defined(CONFIG_USB_MUSB_GADGET)
+	.mode		= MUSB_PERIPHERAL,
+#else
+#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
+#endif
+	.config         = &musb_config,
+	.power          = 250,
+	.platform_ops	= &am35x_ops,
+	.board_data	= &musb_board_data,
+};
+
+static void am3517_evm_musb_init(void)
+{
+	/*
+	 * Set up USB clock/mode in the DEVCONF2 register.
+	 * USB2.0 PHY reference clock is 13 MHz
+	 */
+	clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+			CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
+			CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
+			CONF2_VBDTCTEN | CONF2_DATPOL);
+
+	musb_register(&musb_plat, &musb_board_data,
+			(void *)AM35XX_IPSS_USBOTGSS_BASE);
+}
+#else
+#define am3517_evm_musb_init() do {} while (0)
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Init i2c, ethernet, etc... (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+	u32 reset;
+
+	omap_die_id_display();
+
+	am3517_evm_musb_init();
+
+	/* ensure that the Ethernet module is out of reset */
+	reset = readl(AM3517_IP_SW_RESET);
+	reset &= (~CPGMACSS_SW_RST);
+	writel(reset, AM3517_IP_SW_RESET);
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_AM3517EVM();
+}
+
+
+#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
+int board_eth_init(struct bd_info *bis)
+{
+	int rv, n = 0;
+
+	rv = cpu_eth_init(bis);
+	if (rv > 0)
+		n += rv;
+
+	rv = usb_eth_initialize(bis);
+	if (rv > 0)
+		n += rv;
+
+	return n;
+}
+#endif
diff --git a/roms/u-boot/board/logicpd/am3517evm/am3517evm.h b/roms/u-boot/board/logicpd/am3517evm/am3517evm.h
new file mode 100644
index 000000000..0e5b8326b
--- /dev/null
+++ b/roms/u-boot/board/logicpd/am3517evm/am3517evm.h
@@ -0,0 +1,392 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * am3517evm.h - Header file for the AM3517 EVM.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.h
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef _AM3517EVM_H_
+#define _AM3517EVM_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"AM3517EVM Board",
+	"NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_AM3517EVM() \
+	/* SDRC */\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
+	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
+	/*sdrc_strben_dly0*/\
+	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
+	 /*sdrc_strben_dly1*/\
+	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
+	/* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS6),		(IDIS | PTD | DIS | M4)) \
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+							 /* - ETH_nRESET*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) \
+	/* DSS */\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
+	/* CAMERA */\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+							 /* - CAM_RESET*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) \
+	/* MMC */\
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
+	/* WriteProtect */\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) /*CardDetect*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
+	\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTD | DIS | M0)) \
+	/* McBSP */\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+							 /* - LCD_INI*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+							 /* - LCD_ENVDD */\
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+							 /* - LCD_QVGA/nVGA */\
+	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+							 /* - LCD_RESB */\
+	/* UART */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
+	/* I2C */\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
+	/* McSPI */\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
+							 /* - LAN_INTR*/\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M4)) \
+	/* CCDC */\
+	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M0)) \
+	/* RMII */\
+	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
+	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
+	MUX_VAL(CP(RMII_RXD0)	,	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
+	/* HECC */\
+	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTU | EN  | M0)) \
+	/* HSUSB */\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
+	/* HDQ */\
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) \
+	/* Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
+	/*SYS_nRESWARM */\
+	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | EN | M4)) \
+							/* - GPIO30 */\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+							 /* - PEN_IRQ */\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+							 /* - VIO_1V8*/\
+	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
+	/* JTAG */\
+	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) \
+	/* ETK (ES2 onwards) */\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0)) \
+	/* Die to Die */\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+
+#endif
diff --git a/roms/u-boot/board/logicpd/imx6/Kconfig b/roms/u-boot/board/logicpd/imx6/Kconfig
new file mode 100644
index 000000000..f5e2f58b1
--- /dev/null
+++ b/roms/u-boot/board/logicpd/imx6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6LOGICPD
+
+config SYS_BOARD
+       default "imx6"
+
+config SYS_VENDOR
+       default "logicpd"
+
+config SYS_CONFIG_NAME
+       default "imx6_logic"
+
+endif
diff --git a/roms/u-boot/board/logicpd/imx6/MAINTAINERS b/roms/u-boot/board/logicpd/imx6/MAINTAINERS
new file mode 100644
index 000000000..428031526
--- /dev/null
+++ b/roms/u-boot/board/logicpd/imx6/MAINTAINERS
@@ -0,0 +1,10 @@
+MX6LOGICPD BOARD
+M:     Adam Ford <aford173@gmail.com>
+S:     Maintained
+F:     board/logicpd/imx6/
+F:     include/configs/imx6_logic.h
+F:     configs/imx6q_logic_defconfig
+F:     arch/arm/dts/imx6-logicpd-baseboard.dtsi
+F:     arch/arm/dts/imx6-logicpd-som.dtsi
+F:     arch/arm/dts/imx6q-logicpd.dts
+F:     arch/arm/dts/imx6q-logicpd-u-boot.dtsi
diff --git a/roms/u-boot/board/logicpd/imx6/Makefile b/roms/u-boot/board/logicpd/imx6/Makefile
new file mode 100644
index 000000000..337df9247
--- /dev/null
+++ b/roms/u-boot/board/logicpd/imx6/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := imx6logic.o
+
diff --git a/roms/u-boot/board/logicpd/imx6/README b/roms/u-boot/board/logicpd/imx6/README
new file mode 100644
index 000000000..19f79c573
--- /dev/null
+++ b/roms/u-boot/board/logicpd/imx6/README
@@ -0,0 +1,83 @@
+U-Boot for LogicPD i.MX6 Development Kit
+----------------------------------------
+
+This file contains information for the port of U-Boot to the Logic PD Development kit.
+
+Logic PD has an i.MX6 System On Module (SOM) and a correspondong development
+board.  SOM has a built-in microSD socket, DDR and NAND flash.  The development kit has
+an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
+
+On the intial release, the SOM came with either an i.MX6D or i.MX6Q.
+
+For more details about Logic PD i.MX6 Development kit, visit:
+https://www.logicpd.com/
+
+Building U-Boot for Logic PD Development Kit
+--------------------------------------------
+To build U-Boot for the Dual and Quad variants:
+
+ make imx6q_logic_defconfig
+ make u-boot.imx CROSS_COMPILE=arm-linux-
+
+
+Flashing U-Boot into the SD card
+--------------------------------
+U-Boot is now building with SPL enabled which means there are two files to
+load into the SD card. Make sure the card is formatted with at least two
+partitions with the first partition being FAT32. First copy u-boot-dtb.img
+to the first partition then burn SPL to the SD card with dd.
+The SPL portion is programmed into a certain location for use by the internal
+bootROM and it cannot be changed.  The following instructions assume the SD
+card is located as /dev/sdb.
+
+  cp u-boot-dtb.img /dev/media/logic/boot
+  sudo dd if=SPL of=/dev/sdb bs=1k seek=1 oflag=sync status=none && sync
+
+
+Flashing U-Boot into NAND
+-------------------------
+Once in Linux with MTD support for the NAND on /dev/mtd0, program U-Boot with the following:
+with:
+
+  kobs-ng init -v -x u-boot-dtb.imx
+
+
+Using Falcon Mode
+-----------------
+With Falcon Mode enabled, U-Boot can be bypassed by having SPL directly load
+the kernel.  The device tree, Kernel and boot args must first be configured,
+and stored to a file on the micro SD card called 'args'
+The kernel uImage is built with LOAD_ADDR=0x12000000 and the device tree is
+assummed to be imx6q-logicpd.dtb.
+
+By default the mmcroot is set to the baseboard.
+
+  # Establish bootargs
+  run mmcargs
+
+  # Load Linux Kernel uImage
+  fatload mmc 1 $loadaddr uImage
+
+  # Load Device Tree
+  run loadfdt
+
+  # Setup the blob that will get passed to the kernel
+  spl export fdt ${loadaddr} - ${fdt_addr_r}
+
+  # Note the starting and ending address of the updated device tree.
+  # for this example:
+  # Loading Device Tree to 1ffdf000, end 1fff038b ... OK
+  # Notice that 0x1fff038b - 1ffdf000 = 0x1138b
+  # now Add 1, so the length is 0x1138c.
+
+  fatwrite mmc 1 0x1ffdf000 args 0x1138c
+
+  # Reset the board and it will bypass U-Boot and SPL will directly boot
+  # the uImage
+
+To interrupt the boot sequence and force U-Boot to load, hold the 'c' button
+while starting.
+
+Additional Support Documentation can be found at:
+https://support.logicpd.com/
+
diff --git a/roms/u-boot/board/logicpd/imx6/imx6logic.c b/roms/u-boot/board/logicpd/imx6/imx6logic.c
new file mode 100644
index 000000000..0d53548dc
--- /dev/null
+++ b/roms/u-boot/board/logicpd/imx6/imx6logic.c
@@ -0,0 +1,324 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Logic PD, Inc.
+ *
+ * Author: Adam Ford <aford173@gmail.com>
+ *
+ * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
+ * and updates by Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <miiphy.h>
+#include <input.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <serial.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define NAND_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+static iomux_v3_cfg_t const nand_pads[] = {
+	MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_ALE__NAND_ALE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_CLE__NAND_CLE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_WP_B__NAND_WP_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_RB0__NAND_READY_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D0__NAND_DATA00    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D1__NAND_DATA01    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D2__NAND_DATA02    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D3__NAND_DATA03    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D4__NAND_DATA04    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D5__NAND_DATA05    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D6__NAND_DATA06    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D7__NAND_DATA07    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_SD4_CLK__NAND_WE_B    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_SD4_CMD__NAND_RE_B    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+
+static void setup_nand_pins(void)
+{
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+}
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8031 output a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8031_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_early_init_f(void)
+{
+	setup_nand_pins();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	return 0;
+}
+
+int board_late_init(void)
+{
+	env_set("board_name", "imx6logic");
+
+	if (is_mx6dq()) {
+		env_set("board_rev", "MX6DQ");
+		if (!env_get("fdt_file"))
+			env_set("fdt_file", "imx6q-logicpd.dtb");
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6q-ddr.h>
+#include <spl.h>
+#include <linux/libfdt.h>
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned int reg = readl(&psrc->sbmr1) >> 11;
+	u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK;
+	unsigned int bmode = readl(&src_base->sbmr2);
+
+	/* If bmode is serial or USB phy is active, return serial */
+	if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) {
+		spl_boot_list[0] = BOOT_DEVICE_BOARD;
+		return;
+	}
+
+	switch (boot_mode >> IMX6_BMODE_SHIFT) {
+	case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
+		spl_boot_list[0] = BOOT_DEVICE_NAND;
+		break;
+	case IMX6_BMODE_SD:
+	case IMX6_BMODE_ESD:
+	case IMX6_BMODE_MMC:
+	case IMX6_BMODE_EMMC:
+		/*
+		 * Upon reading BOOT_CFG register the following map is done:
+		 * Bit 11 and 12 of BOOT_CFG register can determine the current
+		 * mmc port
+		 * 0x1                  SD1-SOM
+		 * 0x2                  SD2-Baseboard
+		 */
+
+		reg &= 0x3; /* Only care about bottom 2 bits */
+		switch (reg) {
+		case 0:
+			spl_boot_list[0] = BOOT_DEVICE_MMC1;
+			break;
+		case 1:
+			spl_boot_list[0] = BOOT_DEVICE_MMC2;
+			break;
+		}
+		break;
+	default:
+		/* By default use USB downloader */
+		spl_boot_list[0] = BOOT_DEVICE_BOARD;
+		break;
+	}
+
+	/* As a last resort, use serial downloader */
+	spl_boot_list[1] = BOOT_DEVICE_BOARD;
+}
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0xFFFFF300, &ccm->CCGR4);
+	writel(0x0F0000F3, &ccm->CCGR5);
+	writel(0x00000FFF, &ccm->CCGR6);
+}
+
+static int mx6q_dcd_table[] = {
+	MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+	MX6_IOM_GRP_DDRPKE, 0x00000000,
+	MX6_IOM_DRAM_SDCLK_0, 0x00000030,
+	MX6_IOM_DRAM_SDCLK_1, 0x00000030,
+	MX6_IOM_DRAM_CAS, 0x00000030,
+	MX6_IOM_DRAM_RAS, 0x00000030,
+	MX6_IOM_GRP_ADDDS, 0x00000030,
+	MX6_IOM_DRAM_RESET, 0x00000030,
+	MX6_IOM_DRAM_SDBA2, 0x00000000,
+	MX6_IOM_DRAM_SDODT0, 0x00000030,
+	MX6_IOM_DRAM_SDODT1, 0x00000030,
+	MX6_IOM_GRP_CTLDS, 0x00000030,
+	MX6_IOM_DDRMODE_CTL, 0x00020000,
+	MX6_IOM_DRAM_SDQS0, 0x00000030,
+	MX6_IOM_DRAM_SDQS1, 0x00000030,
+	MX6_IOM_DRAM_SDQS2, 0x00000030,
+	MX6_IOM_DRAM_SDQS3, 0x00000030,
+	MX6_IOM_GRP_DDRMODE, 0x00020000,
+	MX6_IOM_GRP_B0DS, 0x00000030,
+	MX6_IOM_GRP_B1DS, 0x00000030,
+	MX6_IOM_GRP_B2DS, 0x00000030,
+	MX6_IOM_GRP_B3DS, 0x00000030,
+	MX6_IOM_DRAM_DQM0, 0x00000030,
+	MX6_IOM_DRAM_DQM1, 0x00000030,
+	MX6_IOM_DRAM_DQM2, 0x00000030,
+	MX6_IOM_DRAM_DQM3, 0x00000030,
+	MX6_MMDC_P0_MDSCR, 0x00008000,
+	MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+	MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
+	MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
+	MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
+	MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
+	MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
+	MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
+	MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+	MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+	MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+	MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+	MX6_MMDC_P0_MPMUR0, 0x00000800,
+	MX6_MMDC_P0_MDPDC, 0x00020036,
+	MX6_MMDC_P0_MDOTC, 0x09444040,
+	MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
+	MX6_MMDC_P0_MDCFG1, 0xFF328F64,
+	MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+	MX6_MMDC_P0_MDMISC, 0x00011740,
+	MX6_MMDC_P0_MDSCR, 0x00008000,
+	MX6_MMDC_P0_MDRWD, 0x000026D2,
+	MX6_MMDC_P0_MDOR, 0x00BE1023,
+	MX6_MMDC_P0_MDASP, 0x00000047,
+	MX6_MMDC_P0_MDCTL, 0x85190000,
+	MX6_MMDC_P0_MDSCR, 0x00888032,
+	MX6_MMDC_P0_MDSCR, 0x00008033,
+	MX6_MMDC_P0_MDSCR, 0x00008031,
+	MX6_MMDC_P0_MDSCR, 0x19408030,
+	MX6_MMDC_P0_MDSCR, 0x04008040,
+	MX6_MMDC_P0_MDREF, 0x00007800,
+	MX6_MMDC_P0_MPODTCTRL, 0x00000007,
+	MX6_MMDC_P0_MDPDC, 0x00025576,
+	MX6_MMDC_P0_MAPSR, 0x00011006,
+	MX6_MMDC_P0_MDSCR, 0x00000000,
+	/* enable AXI cache for VDOA/VPU/IPU */
+
+	MX6_IOMUXC_GPR4, 0xF00000CF,
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	MX6_IOMUXC_GPR6, 0x007F007F,
+	MX6_IOMUXC_GPR7, 0x007F007F,
+};
+
+static void ddr_init(int *table, int size)
+{
+	int i;
+
+	for (i = 0; i < size / 2 ; i++)
+		writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_mx6dq())
+		ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
+}
+
+void board_init_f(ulong dummy)
+{
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* iomux and setup of uart and NAND pins */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* Enable device tree and early DM support*/
+	spl_early_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+#endif
diff --git a/roms/u-boot/board/logicpd/omap3som/Kconfig b/roms/u-boot/board/logicpd/omap3som/Kconfig
new file mode 100644
index 000000000..68d40dcd6
--- /dev/null
+++ b/roms/u-boot/board/logicpd/omap3som/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_OMAP3_LOGIC
+
+config SYS_BOARD
+	default "omap3som"
+
+config SYS_VENDOR
+	default "logicpd"
+
+config SYS_CONFIG_NAME
+	default "omap3_logic"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/logicpd/omap3som/MAINTAINERS b/roms/u-boot/board/logicpd/omap3som/MAINTAINERS
new file mode 100644
index 000000000..459393cf5
--- /dev/null
+++ b/roms/u-boot/board/logicpd/omap3som/MAINTAINERS
@@ -0,0 +1,9 @@
+OMAP3SOM BOARD
+M:	Adam Ford <aford173@gmail.com>
+S:	Maintained
+F:	board/logicpd/omap3som/
+F:	include/configs/omap3_logic.h
+F:	configs/omap3_logic_defconfig
+F:	configs/omap35_logic_defconfig
+F:	configs/omap35_logic_somlv_defconfig
+F:	configs/omap3_logic_somlv_defconfig
diff --git a/roms/u-boot/board/logicpd/omap3som/Makefile b/roms/u-boot/board/logicpd/omap3som/Makefile
new file mode 100644
index 000000000..61ef14e87
--- /dev/null
+++ b/roms/u-boot/board/logicpd/omap3som/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= omap3logic.o
diff --git a/roms/u-boot/board/logicpd/omap3som/README b/roms/u-boot/board/logicpd/omap3som/README
new file mode 100644
index 000000000..5aaf58f0a
--- /dev/null
+++ b/roms/u-boot/board/logicpd/omap3som/README
@@ -0,0 +1,56 @@
+Summary
+=======
+
+The source for omap3logic.c encompases the OMAP35 and DM3730 SOM-LV and DM3730 Torpedo platforms, but there are device trees custom taylored to each board.
+
+omap3_logic_defconfig = DM37 Torpedo / Torpedo + Wireless
+omap35_logic_defconfig = OMAP35 Torpedo
+omap3_logic_somlv_defconfig = DM37 SOM-LV
+omap35_logic_somlv_defconfig = OMAP35 SOM-LV
+
+The device tree included with each of the defconfig files will also direct the board as to which dtb file to load when loading the kernel, so it is not
+recomended to mix and match the defconfig files.
+
+Falcon Mode: FAT SD cards
+=========================
+
+In this case the additional file is written to the filesystem.  In this
+example we assume that the uImage and device tree to be used are already on
+the FAT filesystem (only the uImage MUST be for this to function
+afterwards) along with a Falcon Mode aware MLO and the FAT partition has
+already been created and marked bootable:
+
+U-Boot # mmc rescan
+# Load kernel and device tree into memory, perform export
+U-Boot # fatload mmc 0 ${loadaddr} uImage
+U-Boot # run loadfdt
+U-Boot # setenv optargs quiet
+U-Boot # run mmcargs
+U-Boot # run common_bootargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+
+This will print a number of lines and then end with something like:
+   Loading Device Tree to 8dec9000, end 8dee0295 ... OK
+
+So then note the starting address and write the args to mmc/sd:
+
+U-Boot # fatwrite mmc 0:1 0x8dec9000 args 0x20000
+
+The size of 0x20000 matches the CMD_SPL_WRITE_SIZE.
+
+Falcon Mode: NAND
+=================
+
+In this case the additional data is written to another partition of the
+NAND.  In this example we assume that the uImage and device tree to be are
+already located on the NAND somewhere (such as filesystem or mtd partition)
+along with a Falcon Mode aware MLO written to the correct locations for
+booting and mtdparts have been configured correctly for the board:
+
+U-Boot # nand read ${loadaddr} kernel
+U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
+U-Boot # run nandargs
+U-Boot # run common_bootargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+U-Boot # nand erase.part u-boot-spl-os
+U-Boot # nand write ${fdtaddr} u-boot-spl-os
diff --git a/roms/u-boot/board/logicpd/omap3som/omap3logic.c b/roms/u-boot/board/logicpd/omap3som/omap3logic.c
new file mode 100644
index 000000000..2379b5219
--- /dev/null
+++ b/roms/u-boot/board/logicpd/omap3som/omap3logic.c
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author :
+ *	Peter Barada <peter.barada@logicpd.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ */
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <net.h>
+#include <ns16550.h>
+#include <flash.h>
+#include <nand.h>
+#include <i2c.h>
+#include <serial.h>
+#include <twl4030.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/omap_mmc.h>
+#include <asm/mach-types.h>
+#include <linux/mtd/rawnand.h>
+#include <asm/omap_musb.h>
+#include <linux/errno.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include "omap3logic.h"
+#ifdef CONFIG_USB_EHCI_HCD
+#include <usb.h>
+#include <asm/ehci-omap.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1	0x00011203
+#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2	0x000A1302
+#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3	0x000F1302
+#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4	0x0A021303
+#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5	0x00120F18
+#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6	0x0A030000
+#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7	0x00000C50
+
+#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1	0x00011203
+#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2	0x00091102
+#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3	0x000D1102
+#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4	0x09021103
+#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5	0x00100D15
+#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6	0x09030000
+#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7	0x00000C50
+
+#define CONFIG_SMC911X_BASE 0x08000000
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank.  This
+ * provides the timing values back to the function that configures
+ * the memory.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+	timings->mr = MICRON_V_MR_165;
+
+	if (get_cpu_family() == CPU_OMAP36XX) {
+		/* 200 MHz works for OMAP36/DM37 */
+		/* 256MB DDR */
+		timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+		timings->ctrla = MICRON_V_ACTIMA_200;
+		timings->ctrlb = MICRON_V_ACTIMB_200;
+		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+	} else {
+		/* 165 MHz works for OMAP35 */
+		timings->mcfg = MICRON_V_MCFG_165(256 << 20);
+		timings->ctrla = MICRON_V_ACTIMA_165;
+		timings->ctrlb = MICRON_V_ACTIMB_165;
+		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+	}
+}
+
+#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
+#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
+#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
+
+void spl_board_prepare_for_linux(void)
+{
+	/* The Micron NAND starts locked which
+	 * prohibits mounting the NAND as RW
+	 * The following commands are what unlocks
+	 * the NAND to become RW Falcon Mode does not
+	 * have as many smarts as U-Boot, but Logic PD
+	 * only makes NAND with 512MB so these hard coded
+	 * values should work for all current models
+	 */
+
+	writeb(0x70, GPMC_NAND_COMMAND_0);
+	writeb(-1, GPMC_NAND_DATA_0);
+	writeb(0x7a, GPMC_NAND_COMMAND_0);
+	writeb(0x00, GPMC_NAND_ADDRESS_0);
+	writeb(0x00, GPMC_NAND_ADDRESS_0);
+	writeb(0x00, GPMC_NAND_ADDRESS_0);
+	writeb(-1, GPMC_NAND_COMMAND_0);
+
+	/* Begin address 0 */
+	writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
+	writeb(0x00, GPMC_NAND_ADDRESS_0);
+	writeb(0x00, GPMC_NAND_ADDRESS_0);
+	writeb(0x00, GPMC_NAND_ADDRESS_0);
+	writeb(-1, GPMC_NAND_DATA_0);
+
+	/* Ending address at the end of Flash */
+	writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
+	writeb(0xc0, GPMC_NAND_ADDRESS_0);
+	writeb(0xff, GPMC_NAND_ADDRESS_0);
+	writeb(0x03, GPMC_NAND_ADDRESS_0);
+	writeb(-1, GPMC_NAND_DATA_0);
+	writeb(0x79, GPMC_NAND_COMMAND_0);
+	writeb(-1, GPMC_NAND_DATA_0);
+	writeb(-1, GPMC_NAND_DATA_0);
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	twl4030_power_init();
+	twl4030_power_mmc_init(0);
+	omap_die_id_display();
+	return 0;
+}
+
+#if defined(CONFIG_FLASH_CFI_DRIVER)
+static const u32 gpmc_dm37_c2nor_config[] = {
+	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
+	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
+	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
+	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
+	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
+	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
+	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
+};
+
+static const u32 gpmc_omap35_c2nor_config[] = {
+	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
+	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
+	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
+	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
+	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
+	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
+	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
+};
+#endif
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+#if defined(CONFIG_FLASH_CFI_DRIVER)
+	if (get_cpu_family() == CPU_OMAP36XX) {
+		/* Enable CS2 for NOR Flash */
+		enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
+				      0x10000000, GPMC_SIZE_64M);
+	} else {
+		enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
+				      0x10000000, GPMC_SIZE_64M);
+	}
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+
+static void unlock_nand(void)
+{
+	int dev = nand_curr_device;
+	struct mtd_info *mtd;
+
+	mtd = get_nand_dev_by_index(dev);
+	nand_unlock(mtd, 0, mtd->size, 0);
+}
+
+#ifdef CONFIG_SMC911X
+/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
+static const u32 gpmc_lan92xx_config[] = {
+	NET_LAN92XX_GPMC_CONFIG1,
+	NET_LAN92XX_GPMC_CONFIG2,
+	NET_LAN92XX_GPMC_CONFIG3,
+	NET_LAN92XX_GPMC_CONFIG4,
+	NET_LAN92XX_GPMC_CONFIG5,
+	NET_LAN92XX_GPMC_CONFIG6,
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
+	unlock_nand();
+#endif
+
+#ifdef CONFIG_SMC911X
+	enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
+			CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+#endif
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_MMC)
+void board_mmc_power_init(void)
+{
+	twl4030_power_mmc_init(0);
+}
+#endif
diff --git a/roms/u-boot/board/logicpd/omap3som/omap3logic.h b/roms/u-boot/board/logicpd/omap3som/omap3logic.h
new file mode 100644
index 000000000..63c214178
--- /dev/null
+++ b/roms/u-boot/board/logicpd/omap3som/omap3logic.h
@@ -0,0 +1,255 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author:
+ * Peter Barada <peter.barada@logicpd.com>
+ */
+#ifndef _OMAP3LOGIC_H_
+#define _OMAP3LOGIC_H_
+
+/*
+ * OMAP3 GPMC register settings for CS1 LAN922x
+ */
+#define NET_LAN92XX_GPMC_CONFIG1	0x00001000
+#define NET_LAN92XX_GPMC_CONFIG2	0x00080801
+#define NET_LAN92XX_GPMC_CONFIG3	0x00000000
+#define NET_LAN92XX_GPMC_CONFIG4	0x08010801
+#define NET_LAN92XX_GPMC_CONFIG5	0x00080a0a
+#define NET_LAN92XX_GPMC_CONFIG6	0x03000280
+
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"Logic DM37x/OMAP35x reference board",
+	"NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_VAL(CP(SDRC_D0), (IEN  | PTD | DIS | M0)); /*SDRC_D0*/
+	MUX_VAL(CP(SDRC_D1), (IEN  | PTD | DIS | M0)); /*SDRC_D1*/
+	MUX_VAL(CP(SDRC_D2), (IEN  | PTD | DIS | M0)); /*SDRC_D2*/
+	MUX_VAL(CP(SDRC_D3), (IEN  | PTD | DIS | M0)); /*SDRC_D3*/
+	MUX_VAL(CP(SDRC_D4), (IEN  | PTD | DIS | M0)); /*SDRC_D4*/
+	MUX_VAL(CP(SDRC_D5), (IEN  | PTD | DIS | M0)); /*SDRC_D5*/
+	MUX_VAL(CP(SDRC_D6), (IEN  | PTD | DIS | M0)); /*SDRC_D6*/
+	MUX_VAL(CP(SDRC_D7), (IEN  | PTD | DIS | M0)); /*SDRC_D7*/
+	MUX_VAL(CP(SDRC_D8), (IEN  | PTD | DIS | M0)); /*SDRC_D8*/
+	MUX_VAL(CP(SDRC_D9), (IEN  | PTD | DIS | M0)); /*SDRC_D9*/
+	MUX_VAL(CP(SDRC_D10), (IEN  | PTD | DIS | M0)); /*SDRC_D10*/
+	MUX_VAL(CP(SDRC_D11), (IEN  | PTD | DIS | M0)); /*SDRC_D11*/
+	MUX_VAL(CP(SDRC_D12), (IEN  | PTD | DIS | M0)); /*SDRC_D12*/
+	MUX_VAL(CP(SDRC_D13), (IEN  | PTD | DIS | M0)); /*SDRC_D13*/
+	MUX_VAL(CP(SDRC_D14), (IEN  | PTD | DIS | M0)); /*SDRC_D14*/
+	MUX_VAL(CP(SDRC_D15), (IEN  | PTD | DIS | M0)); /*SDRC_D15*/
+	MUX_VAL(CP(SDRC_D16), (IEN  | PTD | DIS | M0)); /*SDRC_D16*/
+	MUX_VAL(CP(SDRC_D17), (IEN  | PTD | DIS | M0)); /*SDRC_D17*/
+	MUX_VAL(CP(SDRC_D18), (IEN  | PTD | DIS | M0)); /*SDRC_D18*/
+	MUX_VAL(CP(SDRC_D19), (IEN  | PTD | DIS | M0)); /*SDRC_D19*/
+	MUX_VAL(CP(SDRC_D20), (IEN  | PTD | DIS | M0)); /*SDRC_D20*/
+	MUX_VAL(CP(SDRC_D21), (IEN  | PTD | DIS | M0)); /*SDRC_D21*/
+	MUX_VAL(CP(SDRC_D22), (IEN  | PTD | DIS | M0)); /*SDRC_D22*/
+	MUX_VAL(CP(SDRC_D23), (IEN  | PTD | DIS | M0)); /*SDRC_D23*/
+	MUX_VAL(CP(SDRC_D24), (IEN  | PTD | DIS | M0)); /*SDRC_D24*/
+	MUX_VAL(CP(SDRC_D25), (IEN  | PTD | DIS | M0)); /*SDRC_D25*/
+	MUX_VAL(CP(SDRC_D26), (IEN  | PTD | DIS | M0)); /*SDRC_D26*/
+	MUX_VAL(CP(SDRC_D27), (IEN  | PTD | DIS | M0)); /*SDRC_D27*/
+	MUX_VAL(CP(SDRC_D28), (IEN  | PTD | DIS | M0)); /*SDRC_D28*/
+	MUX_VAL(CP(SDRC_D29), (IEN  | PTD | DIS | M0)); /*SDRC_D29*/
+	MUX_VAL(CP(SDRC_D30), (IEN  | PTD | DIS | M0)); /*SDRC_D30*/
+	MUX_VAL(CP(SDRC_D31), (IEN  | PTD | DIS | M0)); /*SDRC_D31*/
+	MUX_VAL(CP(SDRC_CLK), (IEN  | PTD | DIS | M0)); /*SDRC_CLK*/
+	MUX_VAL(CP(SDRC_DQS0), (IEN  | PTD | DIS | M0)); /*SDRC_DQS0*/
+	MUX_VAL(CP(SDRC_DQS1), (IEN  | PTD | DIS | M0)); /*SDRC_DQS1*/
+	MUX_VAL(CP(SDRC_DQS2), (IEN  | PTD | DIS | M0)); /*SDRC_DQS2*/
+	MUX_VAL(CP(SDRC_DQS3), (IEN  | PTD | DIS | M0)); /*SDRC_DQS3*/
+	MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN  | M0)); /*SDRC_CKE0*/
+	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/
+
+	MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN  | M0)); /*GPMC_A1*/
+	MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN  | M0)); /*GPMC_A2*/
+	MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN  | M0)); /*GPMC_A3*/
+	MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN  | M0)); /*GPMC_A4*/
+	MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN  | M0)); /*GPMC_A5*/
+	MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN  | M0)); /*GPMC_A6*/
+	MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN  | M0)); /*GPMC_A7*/
+	MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN  | M0)); /*GPMC_A8*/
+	MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN  | M0)); /*GPMC_A9*/
+	MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN  | M0)); /*GPMC_A10*/
+	MUX_VAL(CP(GPMC_D0), (IEN  | PTU | EN  | M0)); /*GPMC_D0*/
+	MUX_VAL(CP(GPMC_D1), (IEN  | PTU | EN  | M0)); /*GPMC_D1*/
+	MUX_VAL(CP(GPMC_D2), (IEN  | PTU | EN  | M0)); /*GPMC_D2*/
+	MUX_VAL(CP(GPMC_D3), (IEN  | PTU | EN  | M0)); /*GPMC_D3*/
+	MUX_VAL(CP(GPMC_D4),  (IEN  | PTU | EN  | M0)); /*GPMC_D4*/
+	MUX_VAL(CP(GPMC_D5),  (IEN  | PTU | EN  | M0)); /*GPMC_D5*/
+	MUX_VAL(CP(GPMC_D6),  (IEN  | PTU | EN  | M0)); /*GPMC_D6*/
+	MUX_VAL(CP(GPMC_D7),   (IEN  | PTU | EN  | M0)); /*GPMC_D7*/
+	MUX_VAL(CP(GPMC_D8),  (IEN  | PTU | EN  | M0)); /*GPMC_D8*/
+	MUX_VAL(CP(GPMC_D9),  (IEN  | PTU | EN  | M0)); /*GPMC_D9*/
+	MUX_VAL(CP(GPMC_D10), (IEN  | PTU | EN  | M0)); /*GPMC_D10*/
+	MUX_VAL(CP(GPMC_D11), (IEN  | PTU | EN  | M0)); /*GPMC_D11*/
+	MUX_VAL(CP(GPMC_D12), (IEN  | PTU | EN  | M0)); /*GPMC_D12*/
+	MUX_VAL(CP(GPMC_D13), (IEN  | PTU | EN  | M0)); /*GPMC_D13*/
+	MUX_VAL(CP(GPMC_D14), (IEN  | PTU | EN  | M0)); /*GPMC_D14*/
+	MUX_VAL(CP(GPMC_D15), (IEN  | PTU | EN  | M0)); /*GPMC_D15*/
+	MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN  | M0)); /*GPMC_nCS0*/
+	MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN  | M0)); /*GPMC_nCS1*/
+	MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN  | M0)); /*GPMC_nCS2*/
+	MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN  | M0)); /*GPMC_nCS3*/
+	MUX_VAL(CP(GPMC_NCS4), (IEN  | PTU | EN  | M0)); /*GPMC_nCS4*/
+	MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN  | M0)); /*GPMC_nCS5*/
+	MUX_VAL(CP(GPMC_NCS6), (IEN  | PTU | EN | M0)); /*GPMC_nCS6*/
+	MUX_VAL(CP(GPMC_NCS7), (IEN  | PTU | EN  | M0)); /*GPMC_nCS7*/
+	MUX_VAL(CP(GPMC_CLK),  (IDIS | PTU | EN  | M0)); /*GPMC_CLK*/
+	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/
+	MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/
+	MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/
+	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN  | M0)); /*GPMC_nBE0_CLE*/
+	MUX_VAL(CP(GPMC_NBE1), (IEN  | PTU | EN  | M0)); /*GPMC_nBE1*/
+	MUX_VAL(CP(GPMC_NWP),  (IEN  | PTD | DIS | M0)); /*GPMC_nWP*/
+	MUX_VAL(CP(GPMC_WAIT0), (IEN  | PTU | EN  | M0)); /*GPMC_WAIT0*/
+	MUX_VAL(CP(GPMC_WAIT1), (IEN  | PTU | EN  | M0)); /*GPMC_WAIT1*/
+	MUX_VAL(CP(GPMC_WAIT2), (IEN  | PTU | EN  | M4)); /*GPIO_64*/
+	MUX_VAL(CP(GPMC_WAIT3), (IEN  | PTU | EN  | M0)); /*GPMC_WAIT3*/
+
+	MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN  | M0)); /*MMC1_CLK*/
+	MUX_VAL(CP(MMC1_CMD), (IEN  | PTU | EN  | M0)); /*MMC1_CMD*/
+	MUX_VAL(CP(MMC1_DAT0), (IEN  | PTU | EN  | M0)); /*MMC1_DAT0*/
+	MUX_VAL(CP(MMC1_DAT1), (IEN  | PTU | EN  | M0)); /*MMC1_DAT1*/
+	MUX_VAL(CP(MMC1_DAT2), (IEN  | PTU | EN  | M0)); /*MMC1_DAT2*/
+	MUX_VAL(CP(MMC1_DAT3), (IEN  | PTU | EN  | M0)); /*MMC1_DAT3*/
+
+	MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/
+	MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/
+	MUX_VAL(CP(UART1_CTS), (IEN  | PTU | DIS | M0)); /*UART1_CTS*/
+	MUX_VAL(CP(UART1_RX), (IEN  | PTD | DIS | M0)); /*UART1_RX*/
+
+	MUX_VAL(CP(JTAG_TCK), (IEN  | PTD | DIS | M0)); /*JTAG_TCK*/
+	MUX_VAL(CP(JTAG_TMS), (IEN  | PTD | DIS | M0)); /*JTAG_TMS*/
+	MUX_VAL(CP(JTAG_TDI), (IEN  | PTD | DIS | M0)); /*JTAG_TDI*/
+	MUX_VAL(CP(JTAG_EMU0), (IEN  | PTD | DIS | M0)); /*JTAG_EMU0*/
+	MUX_VAL(CP(JTAG_EMU1), (IEN  | PTD | DIS | M0)); /*JTAG_EMU1*/
+
+	MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN  | M0)); /*ETK_CLK*/
+	MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/
+	MUX_VAL(CP(ETK_D0_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D0*/
+	MUX_VAL(CP(ETK_D1_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D1*/
+	MUX_VAL(CP(ETK_D2_ES2), (IEN  | PTD | EN  | M0)); /*ETK_D2*/
+	MUX_VAL(CP(ETK_D3_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D3*/
+	MUX_VAL(CP(ETK_D4_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D4*/
+	MUX_VAL(CP(ETK_D5_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D5*/
+	MUX_VAL(CP(ETK_D6_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D6*/
+	MUX_VAL(CP(ETK_D7_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D7*/
+	MUX_VAL(CP(ETK_D8_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D8*/
+	MUX_VAL(CP(ETK_D9_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D9*/
+#ifndef CONFIG_USB_EHCI_OMAP /* Torpedo does not use EHCI_OMAP */
+	MUX_VAL(CP(ETK_D10_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D10*/
+	MUX_VAL(CP(ETK_D11_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D11*/
+	MUX_VAL(CP(ETK_D12_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D12*/
+	MUX_VAL(CP(ETK_D13_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D13*/
+	MUX_VAL(CP(ETK_D14_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D14*/
+	MUX_VAL(CP(ETK_D15_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D15*/
+#endif
+
+	MUX_VAL(CP(D2D_MCAD1), (IEN  | PTD | EN  | M0)); /*d2d_mcad1*/
+	MUX_VAL(CP(D2D_MCAD2), (IEN  | PTD | EN  | M0)); /*d2d_mcad2*/
+	MUX_VAL(CP(D2D_MCAD3), (IEN  | PTD | EN  | M0)); /*d2d_mcad3*/
+	MUX_VAL(CP(D2D_MCAD4), (IEN  | PTD | EN  | M0)); /*d2d_mcad4*/
+	MUX_VAL(CP(D2D_MCAD5), (IEN  | PTD | EN  | M0)); /*d2d_mcad5*/
+	MUX_VAL(CP(D2D_MCAD6), (IEN  | PTD | EN  | M0)); /*d2d_mcad6*/
+	MUX_VAL(CP(D2D_MCAD7), (IEN  | PTD | EN  | M0)); /*d2d_mcad7*/
+	MUX_VAL(CP(D2D_MCAD8), (IEN  | PTD | EN  | M0)); /*d2d_mcad8*/
+	MUX_VAL(CP(D2D_MCAD9), (IEN  | PTD | EN  | M0)); /*d2d_mcad9*/
+	MUX_VAL(CP(D2D_MCAD10), (IEN  | PTD | EN  | M0)); /*d2d_mcad10*/
+	MUX_VAL(CP(D2D_MCAD11), (IEN  | PTD | EN  | M0)); /*d2d_mcad11*/
+	MUX_VAL(CP(D2D_MCAD12), (IEN  | PTD | EN  | M0)); /*d2d_mcad12*/
+	MUX_VAL(CP(D2D_MCAD13), (IEN  | PTD | EN  | M0)); /*d2d_mcad13*/
+	MUX_VAL(CP(D2D_MCAD14), (IEN  | PTD | EN  | M0)); /*d2d_mcad14*/
+	MUX_VAL(CP(D2D_MCAD15), (IEN  | PTD | EN  | M0)); /*d2d_mcad15*/
+	MUX_VAL(CP(D2D_MCAD16), (IEN  | PTD | EN  | M0)); /*d2d_mcad16*/
+	MUX_VAL(CP(D2D_MCAD17), (IEN  | PTD | EN  | M0)); /*d2d_mcad17*/
+	MUX_VAL(CP(D2D_MCAD18), (IEN  | PTD | EN  | M0)); /*d2d_mcad18*/
+	MUX_VAL(CP(D2D_MCAD19), (IEN  | PTD | EN  | M0)); /*d2d_mcad19*/
+	MUX_VAL(CP(D2D_MCAD20), (IEN  | PTD | EN  | M0)); /*d2d_mcad20*/
+	MUX_VAL(CP(D2D_MCAD21), (IEN  | PTD | EN  | M0)); /*d2d_mcad21*/
+	MUX_VAL(CP(D2D_MCAD22), (IEN  | PTD | EN  | M0)); /*d2d_mcad22*/
+	MUX_VAL(CP(D2D_MCAD23), (IEN  | PTD | EN  | M0)); /*d2d_mcad23*/
+	MUX_VAL(CP(D2D_MCAD24), (IEN  | PTD | EN  | M0)); /*d2d_mcad24*/
+	MUX_VAL(CP(D2D_MCAD25), (IEN  | PTD | EN  | M0)); /*d2d_mcad25*/
+	MUX_VAL(CP(D2D_MCAD26), (IEN  | PTD | EN  | M0)); /*d2d_mcad26*/
+	MUX_VAL(CP(D2D_MCAD27), (IEN  | PTD | EN  | M0)); /*d2d_mcad27*/
+	MUX_VAL(CP(D2D_MCAD28), (IEN  | PTD | EN  | M0)); /*d2d_mcad28*/
+	MUX_VAL(CP(D2D_MCAD29), (IEN  | PTD | EN  | M0)); /*d2d_mcad29*/
+	MUX_VAL(CP(D2D_MCAD30), (IEN  | PTD | EN  | M0)); /*d2d_mcad30*/
+	MUX_VAL(CP(D2D_MCAD31), (IEN  | PTD | EN  | M0)); /*d2d_mcad31*/
+	MUX_VAL(CP(D2D_MCAD32), (IEN  | PTD | EN  | M0)); /*d2d_mcad32*/
+	MUX_VAL(CP(D2D_MCAD33), (IEN  | PTD | EN  | M0)); /*d2d_mcad33*/
+	MUX_VAL(CP(D2D_MCAD34), (IEN  | PTD | EN  | M0)); /*d2d_mcad34*/
+	MUX_VAL(CP(D2D_MCAD35), (IEN  | PTD | EN  | M0)); /*d2d_mcad35*/
+	MUX_VAL(CP(D2D_MCAD36), (IEN  | PTD | EN  | M0)); /*d2d_mcad36*/
+	MUX_VAL(CP(D2D_CLK26MI), (IEN  | PTD | DIS | M0)); /*d2d_clk26mi*/
+	MUX_VAL(CP(D2D_NRESPWRON), (IEN  | PTD | EN  | M0)); /*d2d_nrespwron*/
+	MUX_VAL(CP(D2D_NRESWARM), (IEN  | PTU | EN  | M0)); /*d2d_nreswarm */
+	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN  | PTD | DIS | M0)); /*d2d_arm9nirq */
+	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN  | PTD | DIS | M0)); /*d2d_uma2p6fiq*/
+	MUX_VAL(CP(D2D_SPINT), (IEN  | PTD | EN  | M0)); /*d2d_spint*/
+	MUX_VAL(CP(D2D_FRINT), (IEN  | PTD | EN  | M0)); /*d2d_frint*/
+	MUX_VAL(CP(D2D_DMAREQ0), (IEN  | PTD | DIS | M0)); /*d2d_dmareq0*/
+	MUX_VAL(CP(D2D_DMAREQ1), (IEN  | PTD | DIS | M0)); /*d2d_dmareq1*/
+	MUX_VAL(CP(D2D_DMAREQ2), (IEN  | PTD | DIS | M0)); /*d2d_dmareq2*/
+	MUX_VAL(CP(D2D_DMAREQ3), (IEN  | PTD | DIS | M0)); /*d2d_dmareq3*/
+	MUX_VAL(CP(D2D_N3GTRST), (IEN  | PTD | DIS | M0)); /*d2d_n3gtrst*/
+	MUX_VAL(CP(D2D_N3GTDI),  (IEN  | PTD | DIS | M0)); /*d2d_n3gtdi*/
+	MUX_VAL(CP(D2D_N3GTDO),  (IEN  | PTD | DIS | M0)); /*d2d_n3gtdo*/
+	MUX_VAL(CP(D2D_N3GTMS),  (IEN  | PTD | DIS | M0)); /*d2d_n3gtms*/
+	MUX_VAL(CP(D2D_N3GTCK),  (IEN  | PTD | DIS | M0)); /*d2d_n3gtck*/
+	MUX_VAL(CP(D2D_N3GRTCK), (IEN  | PTD | DIS | M0)); /*d2d_n3grtck*/
+	MUX_VAL(CP(D2D_MSTDBY),  (IEN  | PTU | EN  | M0)); /*d2d_mstdby*/
+	MUX_VAL(CP(D2D_SWAKEUP), (IEN  | PTD | EN  | M0)); /*d2d_swakeup*/
+	MUX_VAL(CP(D2D_IDLEREQ), (IEN  | PTD | DIS | M0)); /*d2d_idlereq*/
+	MUX_VAL(CP(D2D_IDLEACK), (IEN  | PTU | EN  | M0)); /*d2d_idleack*/
+	MUX_VAL(CP(D2D_MWRITE),  (IEN  | PTD | DIS | M0)); /*d2d_mwrite*/
+	MUX_VAL(CP(D2D_SWRITE),  (IEN  | PTD | DIS | M0)); /*d2d_swrite*/
+	MUX_VAL(CP(D2D_MREAD),   (IEN  | PTD | DIS | M0)); /*d2d_mread*/
+	MUX_VAL(CP(D2D_SREAD),   (IEN  | PTD | DIS | M0)); /*d2d_sread*/
+	MUX_VAL(CP(D2D_MBUSFLAG), (IEN  | PTD | DIS | M0)); /*d2d_mbusflag*/
+	MUX_VAL(CP(D2D_SBUSFLAG), (IEN  | PTD | DIS | M0)); /*d2d_sbusflag*/
+
+#ifdef CONFIG_USB_EHCI_OMAP /* SOM-LV Uses EHCI-OMAP */
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M3));	/*HSUSB2_DATA0*/
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M3));	/*HSUSB2_DATA1*/
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0));	/*HSUSB2_DATA2*/
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0));	/*HSUSB2_DATA3*/
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0));	/*HSUSB2_DATA4*/
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0));	/*HSUSB2_DATA5*/
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0));	/*HSUSB2_DATA6*/
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0));	/*HSUSB2_DATA7*/
+	MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) 	/* GPIO_4 */
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | DIS | M3));	/*HSUSB2_CLK*/
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3));	/*HSUSB2_STP*/
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M3));	/*HSUSB2_DIR*/
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M3));	/*HSUSB2_NXT*/
+#endif
+
+}
+
+#endif
diff --git a/roms/u-boot/board/maxbcm/MAINTAINERS b/roms/u-boot/board/maxbcm/MAINTAINERS
new file mode 100644
index 000000000..3c8af2121
--- /dev/null
+++ b/roms/u-boot/board/maxbcm/MAINTAINERS
@@ -0,0 +1,6 @@
+MAXBCM BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/maxbcm/
+F:	include/configs/maxbcm.h
+F:	configs/maxbcm_defconfig
diff --git a/roms/u-boot/board/maxbcm/Makefile b/roms/u-boot/board/maxbcm/Makefile
new file mode 100644
index 000000000..07f81f59f
--- /dev/null
+++ b/roms/u-boot/board/maxbcm/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+
+obj-y	:= maxbcm.o
diff --git a/roms/u-boot/board/maxbcm/maxbcm.c b/roms/u-boot/board/maxbcm/maxbcm.c
new file mode 100644
index 000000000..e92132ad1
--- /dev/null
+++ b/roms/u-boot/board/maxbcm/maxbcm.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/mbus.h>
+
+#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Base addresses for the external device chip selects */
+#define DEV_CS0_BASE		0xe0000000
+#define DEV_CS1_BASE		0xe1000000
+#define DEV_CS2_BASE		0xe2000000
+#define DEV_CS3_BASE		0xe3000000
+
+/* DDR3 static configuration */
+MV_DRAM_MC_INIT ddr3_b0_maxbcm[MV_MAX_DDR3_STATIC_SIZE] = {
+	{0x00001400, 0x7301CC30},	/* DDR SDRAM Configuration Register */
+	{0x00001404, 0x30000820},	/* Dunit Control Low Register */
+	{0x00001408, 0x5515BAAB},	/* DDR SDRAM Timing (Low) Register */
+	{0x0000140C, 0x38DA3F97},	/* DDR SDRAM Timing (High) Register */
+	{0x00001410, 0x20100005},	/* DDR SDRAM Address Control Register */
+	{0x00001414, 0x0000F3FF},	/* DDR SDRAM Open Pages Control Reg */
+	{0x00001418, 0x00000e00},	/* DDR SDRAM Operation Register */
+	{0x0000141C, 0x00000672},	/* DDR SDRAM Mode Register */
+	{0x00001420, 0x00000004},	/* DDR SDRAM Extended Mode Register */
+	{0x00001424, 0x0000F3FF},	/* Dunit Control High Register */
+	{0x00001428, 0x0011A940},	/* Dunit Control High Register */
+	{0x0000142C, 0x014C5134},	/* Dunit Control High Register */
+	{0x0000147C, 0x0000D771},
+
+	{0x00001494, 0x00010000},	/* DDR SDRAM ODT Control (Low) Reg */
+	{0x0000149C, 0x00000001},	/* DDR Dunit ODT Control Register */
+	{0x000014A0, 0x00000001},
+	{0x000014A8, 0x00000101},
+
+	/* Recommended Settings from Marvell for 4 x 16 bit devices: */
+	{0x000014C0, 0x192424C9},	/* DRAM addr and Ctrl Driving Strenght*/
+	{0x000014C4, 0xAAA24C9},	/* DRAM Data and DQS Driving Strenght */
+
+	/*
+	 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
+	 * training sequence
+	 */
+	{0x000200e8, 0x3FFF0E01},
+	{0x00020184, 0x3FFFFFE0},	/* Close fast path Window to - 2G */
+
+	{0x0001504, 0x3FFFFFE1},	/* CS0 Size */
+	{0x000150C, 0x00000000},	/* CS1 Size */
+	{0x0001514, 0x00000000},	/* CS2 Size */
+	{0x000151C, 0x00000000},	/* CS3 Size */
+
+	{0x0020220, 0x00000007},	/* Reserved */
+
+	{0x00001538, 0x0000000B},	/* Read Data Sample Delays Register */
+	{0x0000153C, 0x0000000B},	/* Read Data Ready Delay Register */
+
+	{0x000015D0, 0x00000670},	/* MR0 */
+	{0x000015D4, 0x00000044},	/* MR1 */
+	{0x000015D8, 0x00000018},	/* MR2 */
+	{0x000015DC, 0x00000000},	/* MR3 */
+	{0x000015E0, 0x00000001},
+	{0x000015E4, 0x00203c18},	/* ZQDS Configuration Register */
+	{0x000015EC, 0xF800A225},	/* DDR PHY */
+
+	{0x0, 0x0}
+};
+
+MV_DRAM_MODES maxbcm_ddr_modes[MV_DDR3_MODES_NUMBER] = {
+	{"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm,  NULL},
+};
+
+extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
+
+/* MAXBCM: SERDES 0-4 PCIE, Serdes 7 = SGMII 0, all others =  unconnected */
+MV_BIN_SERDES_CFG maxbcm_serdes_cfg[] = {
+	{ MV_PEX_ROOT_COMPLEX, 0x20011111, 0x00000000,
+	  { PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
+	    PEX_BUS_DISABLED },
+	  0x1f, serdes_change_m_phy
+	}
+};
+
+MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
+{
+	/* Only one mode supported for this board */
+	return &maxbcm_ddr_modes[0];
+}
+
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
+{
+	return &maxbcm_serdes_cfg[0];
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * Don't configure MPP (pin multiplexing) and GPIO here,
+	 * its already done in bin_hdr
+	 */
+
+	/*
+	 * Setup some board specific mbus address windows
+	 */
+	mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0);
+	mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
+	mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2);
+	mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: maxBCM\n");
+
+	return 0;
+}
+
+/* Configure and enable MV88E6185 switch */
+int board_phy_config(struct phy_device *phydev)
+{
+	/*
+	 * todo:
+	 * Fill this with the real setup / config code.
+	 * Please see board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
+	 * for details.
+	 */
+	printf("88E6185 Initialized\n");
+	return 0;
+}
diff --git a/roms/u-boot/board/mediatek/mt7620/Kconfig b/roms/u-boot/board/mediatek/mt7620/Kconfig
new file mode 100644
index 000000000..b9137adcc
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7620/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
+
+config SYS_BOARD
+	default "mt7620"
+
+config SYS_VENDOR
+	default "mediatek"
+
+config SYS_CONFIG_NAME
+	default "mt7620"
+
+endif
diff --git a/roms/u-boot/board/mediatek/mt7620/MAINTAINERS b/roms/u-boot/board/mediatek/mt7620/MAINTAINERS
new file mode 100644
index 000000000..05db777ce
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7620/MAINTAINERS
@@ -0,0 +1,9 @@
+MT7620_RFB BOARD
+M:	Weijie Gao <weijie.gao@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt7620
+F:	include/configs/mt7620.h
+F:	configs/mt7620_rfb_defconfig
+F:	configs/mt7620_mt7530_rfb_defconfig
+F:	arch/mips/dts/mediatek,mt7620-rfb.dts
+F:	arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
diff --git a/roms/u-boot/board/mediatek/mt7620/Makefile b/roms/u-boot/board/mediatek/mt7620/Makefile
new file mode 100644
index 000000000..db129c5ab
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7620/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += board.o
diff --git a/roms/u-boot/board/mediatek/mt7620/board.c b/roms/u-boot/board/mediatek/mt7620/board.c
new file mode 100644
index 000000000..119b8fc9e
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7620/board.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
diff --git a/roms/u-boot/board/mediatek/mt7622/Kconfig b/roms/u-boot/board/mediatek/mt7622/Kconfig
new file mode 100644
index 000000000..d0abdc0a6
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7622/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_MT7622
+
+config SYS_BOARD
+	default "mt7622"
+
+config SYS_CONFIG_NAME
+	default "mt7622"
+
+config MTK_BROM_HEADER_INFO
+	string
+	default "lk=1"
+
+config MTK_BROM_HEADER_INFO
+	string
+	default "media=nor"
+
+endif
diff --git a/roms/u-boot/board/mediatek/mt7622/MAINTAINERS b/roms/u-boot/board/mediatek/mt7622/MAINTAINERS
new file mode 100644
index 000000000..a3e0e75ca
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7622/MAINTAINERS
@@ -0,0 +1,6 @@
+MT7622
+M:	Sam Shih <sam.shih@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt7622
+F:	include/configs/mt7622.h
+F:	configs/mt7622_rfb_defconfig
diff --git a/roms/u-boot/board/mediatek/mt7622/Makefile b/roms/u-boot/board/mediatek/mt7622/Makefile
new file mode 100644
index 000000000..2c54d86ff
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7622/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y	+= mt7622_rfb.o
+
diff --git a/roms/u-boot/board/mediatek/mt7622/mt7622_rfb.c b/roms/u-boot/board/mediatek/mt7622/mt7622_rfb.c
new file mode 100644
index 000000000..0504d6177
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7622/mt7622_rfb.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <common.h>
+#include <config.h>
+#include <env.h>
+#include <init.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	return 0;
+}
+
+int board_late_init(void)
+{
+	gd->env_valid = 1; //to load environment variable from persistent store
+	env_relocate();
+	return 0;
+}
diff --git a/roms/u-boot/board/mediatek/mt7623/Kconfig b/roms/u-boot/board/mediatek/mt7623/Kconfig
new file mode 100644
index 000000000..a8c670e71
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7623/Kconfig
@@ -0,0 +1,13 @@
+if TARGET_MT7623
+
+config SYS_BOARD
+	default "mt7623"
+
+config SYS_CONFIG_NAME
+	default "mt7623"
+
+config MTK_BROM_HEADER_INFO
+	string
+	default "lk=1"
+
+endif
diff --git a/roms/u-boot/board/mediatek/mt7623/MAINTAINERS b/roms/u-boot/board/mediatek/mt7623/MAINTAINERS
new file mode 100644
index 000000000..1a8d796bd
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7623/MAINTAINERS
@@ -0,0 +1,14 @@
+MT7623
+M:	Ryder Lee <ryder.lee@mediatek.com>
+M:	Weijie Gao <weijie.gao@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt7623
+F:	include/configs/mt7623.h
+F:	configs/mt7623n_bpir2_defconfig
+
+UNIELEC U7623
+M:	Ryder Lee <ryder.lee@mediatek.com>
+M:	David Woodhouse <dwmw2@infradead.org>
+S:	Maintained
+F:	arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts
+F:	configs/mt7623a_unielec_u7623_02_defconfig
diff --git a/roms/u-boot/board/mediatek/mt7623/Makefile b/roms/u-boot/board/mediatek/mt7623/Makefile
new file mode 100644
index 000000000..2b42071c4
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7623/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += mt7623_rfb.o
diff --git a/roms/u-boot/board/mediatek/mt7623/mt7623_rfb.c b/roms/u-boot/board/mediatek/mt7623/mt7623_rfb.c
new file mode 100644
index 000000000..755e87908
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7623/mt7623_rfb.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_MMC
+int mmc_get_boot_dev(void)
+{
+	int g_mmc_devid = -1;
+	char *uflag = (char *)0x81DFFFF0;
+
+	if (!find_mmc_device(1))
+		return 0;
+
+	if (strncmp(uflag,"eMMC",4)==0) {
+		g_mmc_devid = 0;
+		printf("Boot From Emmc(id:%d)\n\n", g_mmc_devid);
+	} else {
+		g_mmc_devid = 1;
+		printf("Boot From SD(id:%d)\n\n", g_mmc_devid);
+	}
+	return g_mmc_devid;
+}
+
+int mmc_get_env_dev(void)
+{
+	return mmc_get_boot_dev();
+}
+#endif
diff --git a/roms/u-boot/board/mediatek/mt7628/Kconfig b/roms/u-boot/board/mediatek/mt7628/Kconfig
new file mode 100644
index 000000000..d6b6f9d63
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7628/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_MT7628_RFB
+
+config SYS_BOARD
+	default "mt7628"
+
+config SYS_VENDOR
+	default "mediatek"
+
+config SYS_CONFIG_NAME
+	default "mt7628"
+
+endif
diff --git a/roms/u-boot/board/mediatek/mt7628/MAINTAINERS b/roms/u-boot/board/mediatek/mt7628/MAINTAINERS
new file mode 100644
index 000000000..032fd0e2f
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7628/MAINTAINERS
@@ -0,0 +1,7 @@
+MT7628_RFB BOARD
+M:	Weijie Gao <weijie.gao@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt7628
+F:	include/configs/mt7628.h
+F:	configs/mt7628_rfb_defconfig
+F:	arch/mips/dts/mediatek,mt7628-rfb.dts
diff --git a/roms/u-boot/board/mediatek/mt7628/Makefile b/roms/u-boot/board/mediatek/mt7628/Makefile
new file mode 100644
index 000000000..db129c5ab
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7628/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += board.o
diff --git a/roms/u-boot/board/mediatek/mt7628/board.c b/roms/u-boot/board/mediatek/mt7628/board.c
new file mode 100644
index 000000000..f837a06fb
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7628/board.c
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/mediatek/mt7629/Kconfig b/roms/u-boot/board/mediatek/mt7629/Kconfig
new file mode 100644
index 000000000..6055164b5
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7629/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_MT7629
+
+config SYS_BOARD
+	default "mt7629"
+
+config SYS_CONFIG_NAME
+	default "mt7629"
+
+config MTK_SPL_PAD_SIZE
+	hex
+	default 0x10000
+
+config MTK_BROM_HEADER_INFO
+	string
+	default "media=nor"
+
+endif
diff --git a/roms/u-boot/board/mediatek/mt7629/MAINTAINERS b/roms/u-boot/board/mediatek/mt7629/MAINTAINERS
new file mode 100644
index 000000000..424f11516
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7629/MAINTAINERS
@@ -0,0 +1,7 @@
+MT7629
+M:	Ryder Lee <ryder.lee@mediatek.com>
+M:	Weijie Gao <weijie.gao@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt7629
+F:	include/configs/mt7629.h
+F:	configs/mt7629_rfb_defconfig
diff --git a/roms/u-boot/board/mediatek/mt7629/Makefile b/roms/u-boot/board/mediatek/mt7629/Makefile
new file mode 100644
index 000000000..83ccbba8c
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7629/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += mt7629_rfb.o
diff --git a/roms/u-boot/board/mediatek/mt7629/mt7629_rfb.c b/roms/u-boot/board/mediatek/mt7629/mt7629_rfb.c
new file mode 100644
index 000000000..d1bca6d62
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt7629/mt7629_rfb.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/mediatek/mt8183/Kconfig b/roms/u-boot/board/mediatek/mt8183/Kconfig
new file mode 100644
index 000000000..b75c3b8d8
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8183/Kconfig
@@ -0,0 +1,13 @@
+if TARGET_MT8183
+
+config SYS_BOARD
+	default "mt8183"
+
+config SYS_CONFIG_NAME
+	default "mt8183"
+
+config MTK_BROM_HEADER_INFO
+	string
+	default "media=emmc"
+
+endif
diff --git a/roms/u-boot/board/mediatek/mt8183/MAINTAINERS b/roms/u-boot/board/mediatek/mt8183/MAINTAINERS
new file mode 100644
index 000000000..a49995e1b
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8183/MAINTAINERS
@@ -0,0 +1,6 @@
+MT8183 Pumpkin
+M:	Fabien Parent <fparent@baylibre.com>
+S:	Maintained
+F:	board/mediatek/mt8183
+F:	include/configs/mt8183.h
+F:	configs/mt8183_pumpkin_defconfig
diff --git a/roms/u-boot/board/mediatek/mt8183/Makefile b/roms/u-boot/board/mediatek/mt8183/Makefile
new file mode 100644
index 000000000..90b5b7232
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8183/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += mt8183_pumpkin.o
diff --git a/roms/u-boot/board/mediatek/mt8183/mt8183_pumpkin.c b/roms/u-boot/board/mediatek/mt8183/mt8183_pumpkin.c
new file mode 100644
index 000000000..db613ebdc
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8183/mt8183_pumpkin.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 BayLibre SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+
+int board_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (CONFIG_IS_ENABLED(USB_GADGET)) {
+		ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
+		if (ret) {
+			pr_err("%s: Cannot find USB device\n", __func__);
+			return ret;
+		}
+	}
+
+	if (CONFIG_IS_ENABLED(USB_ETHER))
+		usb_ether_init();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/mediatek/mt8512/Kconfig b/roms/u-boot/board/mediatek/mt8512/Kconfig
new file mode 100644
index 000000000..87bd1fbe6
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8512/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_MT8512
+
+config SYS_BOARD
+	default "mt8512"
+
+config SYS_CONFIG_NAME
+	default "mt8512"
+
+
+config MTK_BROM_HEADER_INFO
+	string
+	default "media=nor"
+
+endif
diff --git a/roms/u-boot/board/mediatek/mt8512/MAINTAINERS b/roms/u-boot/board/mediatek/mt8512/MAINTAINERS
new file mode 100644
index 000000000..966b1a749
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8512/MAINTAINERS
@@ -0,0 +1,6 @@
+MT8512
+M:	Mingming lee <mingming.lee@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt8512
+F:	include/configs/mt8512.h
+F:	configs/mt8512_bm1_emmc_defconfig
diff --git a/roms/u-boot/board/mediatek/mt8512/Makefile b/roms/u-boot/board/mediatek/mt8512/Makefile
new file mode 100644
index 000000000..c1f596b39
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8512/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += mt8512.o
diff --git a/roms/u-boot/board/mediatek/mt8512/mt8512.c b/roms/u-boot/board/mediatek/mt8512/mt8512.c
new file mode 100644
index 000000000..ac3adb801
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8512/mt8512.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <wdt.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = gd->ram_base + 0x100;
+
+	debug("gd->fdt_blob is %p\n", gd->fdt_blob);
+	return 0;
+}
diff --git a/roms/u-boot/board/mediatek/mt8516/Kconfig b/roms/u-boot/board/mediatek/mt8516/Kconfig
new file mode 100644
index 000000000..a87d3872f
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8516/Kconfig
@@ -0,0 +1,13 @@
+if TARGET_MT8516
+
+config SYS_BOARD
+	default "mt8516"
+
+config SYS_CONFIG_NAME
+	default "mt8516"
+
+config MTK_BROM_HEADER_INFO
+	string
+	default "media=emmc"
+
+endif
diff --git a/roms/u-boot/board/mediatek/mt8516/MAINTAINERS b/roms/u-boot/board/mediatek/mt8516/MAINTAINERS
new file mode 100644
index 000000000..2f0d8f646
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8516/MAINTAINERS
@@ -0,0 +1,6 @@
+MT8516 Pumpkin
+M:	Fabien Parent <fparent@baylibre.com>
+S:	Maintained
+F:	board/mediatek/mt8516
+F:	include/configs/mt8516.h
+F:	configs/mt8516_pumpkin_defconfig
diff --git a/roms/u-boot/board/mediatek/mt8516/Makefile b/roms/u-boot/board/mediatek/mt8516/Makefile
new file mode 100644
index 000000000..1d4815d13
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8516/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += mt8516_pumpkin.o
diff --git a/roms/u-boot/board/mediatek/mt8516/mt8516_pumpkin.c b/roms/u-boot/board/mediatek/mt8516/mt8516_pumpkin.c
new file mode 100644
index 000000000..42f3863b9
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8516/mt8516_pumpkin.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 BayLibre SAS
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (CONFIG_IS_ENABLED(USB_GADGET)) {
+		ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
+		if (ret) {
+			pr_err("%s: Cannot find USB device\n", __func__);
+			return ret;
+		}
+	}
+
+	if (CONFIG_IS_ENABLED(USB_ETHER))
+		usb_ether_init();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/mediatek/mt8518/Kconfig b/roms/u-boot/board/mediatek/mt8518/Kconfig
new file mode 100644
index 000000000..1971c4d8c
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8518/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_MT8518
+
+config SYS_BOARD
+	default "mt8518"
+
+config SYS_CONFIG_NAME
+	default "mt8518"
+
+
+config MTK_BROM_HEADER_INFO
+	string
+	default "media=nor"
+
+endif
diff --git a/roms/u-boot/board/mediatek/mt8518/MAINTAINERS b/roms/u-boot/board/mediatek/mt8518/MAINTAINERS
new file mode 100644
index 000000000..c9151947a
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8518/MAINTAINERS
@@ -0,0 +1,6 @@
+MT8518
+M:	Mingming lee <mingming.lee@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt8518
+F:	include/configs/mt8518.h
+F:	configs/mt8518_ap1_emmc_defconfig
diff --git a/roms/u-boot/board/mediatek/mt8518/Makefile b/roms/u-boot/board/mediatek/mt8518/Makefile
new file mode 100644
index 000000000..0884b32c5
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8518/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += mt8518_ap1.o
diff --git a/roms/u-boot/board/mediatek/mt8518/mt8518_ap1.c b/roms/u-boot/board/mediatek/mt8518/mt8518_ap1.c
new file mode 100644
index 000000000..fce5de676
--- /dev/null
+++ b/roms/u-boot/board/mediatek/mt8518/mt8518_ap1.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	debug("gd->fdt_blob is %p\n", gd->fdt_blob);
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_USB_GADGET
+	struct udevice *dev;
+	int ret;
+#endif
+
+#ifdef CONFIG_USB_GADGET
+	ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
+	if (ret) {
+		pr_err("%s: Cannot find USB device\n", __func__);
+		return ret;
+	}
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/menlo/m53menlo/Kconfig b/roms/u-boot/board/menlo/m53menlo/Kconfig
new file mode 100644
index 000000000..1953f5041
--- /dev/null
+++ b/roms/u-boot/board/menlo/m53menlo/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M53MENLO
+
+config SYS_BOARD
+	default "m53menlo"
+
+config SYS_VENDOR
+	default "menlo"
+
+config SYS_SOC
+	default "mx5"
+
+config SYS_CONFIG_NAME
+	default "m53menlo"
+
+endif
diff --git a/roms/u-boot/board/menlo/m53menlo/MAINTAINERS b/roms/u-boot/board/menlo/m53menlo/MAINTAINERS
new file mode 100644
index 000000000..7b7834006
--- /dev/null
+++ b/roms/u-boot/board/menlo/m53menlo/MAINTAINERS
@@ -0,0 +1,7 @@
+M53MENLO BOARD
+M:	Marek Vasut <marex@denx.de>
+M:	Olaf Mandel <o.mandel@menlosystems.com>
+S:	Maintained
+F:	board/menlo/m53menlo/
+F:	include/configs/m53menlo.h
+F:	configs/m53menlo_defconfig
diff --git a/roms/u-boot/board/menlo/m53menlo/Makefile b/roms/u-boot/board/menlo/m53menlo/Makefile
new file mode 100644
index 000000000..b4ab95a56
--- /dev/null
+++ b/roms/u-boot/board/menlo/m53menlo/Makefile
@@ -0,0 +1,9 @@
+#
+# Menlosystems M53Menlo
+# Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
+# Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= m53menlo.o
diff --git a/roms/u-boot/board/menlo/m53menlo/imximage.cfg b/roms/u-boot/board/menlo/m53menlo/imximage.cfg
new file mode 100644
index 000000000..282caf65e
--- /dev/null
+++ b/roms/u-boot/board/menlo/m53menlo/imximage.cfg
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * M53 DRAM init values
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/mach-imx/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+
+
+/* Boot Offset 0x400, valid for both SD and NAND boot. */
+BOOT_OFFSET	FLASH_OFFSET_STANDARD
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x53fa86f4 0x00000000	 /* GRP_DDRMODE_CTL */
+DATA 4 0x53fa8714 0x00000000	 /* GRP_DDRMODE */
+DATA 4 0x53fa86fc 0x00000000	 /* GRP_DDRPKE */
+DATA 4 0x53fa8724 0x04000000	 /* GRP_DDR_TYPE */
+
+DATA 4 0x53fa872c 0x00300000	 /* GRP_B3DS */
+DATA 4 0x53fa8554 0x00300000	 /* DRAM_DQM3 */
+DATA 4 0x53fa8558 0x00300040	 /* DRAM_SDQS3 */
+
+DATA 4 0x53fa8728 0x00300000	 /* GRP_B2DS */
+DATA 4 0x53fa8560 0x00300000	 /* DRAM_DQM2 */
+DATA 4 0x53fa8568 0x00300040	 /* DRAM_SDQS2 */
+
+DATA 4 0x53fa871c 0x00300000	 /* GRP_B1DS */
+DATA 4 0x53fa8594 0x00300000	 /* DRAM_DQM1 */
+DATA 4 0x53fa8590 0x00300040	 /* DRAM_SDQS1 */
+
+DATA 4 0x53fa8718 0x00300000	 /* GRP_B0DS */
+DATA 4 0x53fa8584 0x00300000	 /* DRAM_DQM0 */
+DATA 4 0x53fa857c 0x00300040	 /* DRAM_SDQS0 */
+
+DATA 4 0x53fa8578 0x00300000	 /* DRAM_SDCLK_0 */
+DATA 4 0x53fa8570 0x00300000	 /* DRAM_SDCLK_1 */
+
+DATA 4 0x53fa8574 0x00300000	 /* DRAM_CAS */
+DATA 4 0x53fa8588 0x00300000	 /* DRAM_RAS */
+DATA 4 0x53fa86f0 0x00300000	 /* GRP_ADDDS */
+DATA 4 0x53fa8720 0x00300000	 /* GRP_CTLDS */
+
+DATA 4 0x53fa8564 0x00300040	 /* DRAM_SDODT1 */
+DATA 4 0x53fa8580 0x00300040	 /* DRAM_SDODT0 */
+
+/* ESDCTL */
+DATA 4 0x63fd9088 0x32383535
+DATA 4 0x63fd9090 0x40383538
+DATA 4 0x63fd907c 0x0136014d
+DATA 4 0x63fd9080 0x01510141
+
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x555952e3
+DATA 4 0x63fd9010 0xb68e8b63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x09208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
diff --git a/roms/u-boot/board/menlo/m53menlo/m53menlo.c b/roms/u-boot/board/menlo/m53menlo/m53menlo.c
new file mode 100644
index 000000000..c34baca60
--- /dev/null
+++ b/roms/u-boot/board/menlo/m53menlo/m53menlo.c
@@ -0,0 +1,546 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Menlosystems M53Menlo board
+ *
+ * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/mach-imx/mx5_video.h>
+#include <asm/mach-imx/video.h>
+#include <asm/gpio.h>
+#include <asm/spl.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <fsl_esdhc_imx.h>
+#include <gzip.h>
+#include <i2c.h>
+#include <ipu_pixfmt.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <spl.h>
+#include <splash.h>
+#include <usb/ehci-ci.h>
+#include <video_console.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 mx53_dram_size[2];
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	/*
+	 * WARNING: We must override get_effective_memsize() function here
+	 * to report only the size of the first DRAM bank. This is to make
+	 * U-Boot relocator place U-Boot into valid memory, that is, at the
+	 * end of the first DRAM bank. If we did not override this function
+	 * like so, U-Boot would be placed at the address of the first DRAM
+	 * bank + total DRAM size - sizeof(uboot), which in the setup where
+	 * each DRAM bank contains 512MiB of DRAM would result in placing
+	 * U-Boot into invalid memory area close to the end of the first
+	 * DRAM bank.
+	 */
+	return PHYS_SDRAM_2 + mx53_dram_size[1];
+}
+
+int dram_init(void)
+{
+	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = mx53_dram_size[0];
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	static const iomux_v3_cfg_t uart_pads[] = {
+		MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
+		MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+static void setup_iomux_fec(void)
+{
+	static const iomux_v3_cfg_t fec_pads[] = {
+		/* MDIO pads */
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+
+		/* FEC 0 pads */
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+			     PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+			     PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+			     PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+			     PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+			     PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+
+		/* FEC 1 pads */
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
+			     PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
+			     PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
+			     PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
+			     PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
+			     PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
+			     PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+struct fsl_esdhc_cfg esdhc_cfg = {
+	MMC_SDHC1_BASE_ADDR,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+	gpio_direction_input(IMX_GPIO_NR(1, 1));
+
+	return !gpio_get_value(IMX_GPIO_NR(1, 1));
+}
+
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(struct bd_info *bis)
+{
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+	};
+
+	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+#endif
+
+static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
+{
+	static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+	int ret;
+
+	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
+	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
+
+	/*
+	 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
+	 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
+	 */
+	ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
+	if (ret)
+		puts("IPU:   Failed to configure LDB clock\n");
+
+	/* Configure CCM_CSCMR2 */
+	clrsetbits_le32(&mxc_ccm->cscmr2,
+			(0x7 << 26) | BIT(10) | BIT(8),
+			(0x5 << 26) | BIT(10) | BIT(8));
+
+	/* Configure LDB_CTRL */
+	writel(0x201, 0x53fa8008);
+}
+
+static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
+{
+	gpio_request(IMX_GPIO_NR(6, 0), "LCD");
+
+	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
+	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
+
+	/*
+	 * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
+	 * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
+	 */
+	enable_lvds_clock(dev, 63);
+}
+
+static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
+{
+	gpio_request(IMX_GPIO_NR(6, 0), "LCD");
+
+	/*
+	 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
+	 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
+	 */
+	enable_lvds_clock(dev, 233);
+
+	/* For ETM0700G0DH6 model, this may be enabled after the clock. */
+	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
+}
+
+static const char *lvds_compat_string;
+
+static int detect_lvds(struct display_info_t const *dev)
+{
+	u8 touchid[23];
+	u8 *touchptr = &touchid[0];
+	int ret;
+
+	ret = i2c_set_bus_num(0);
+	if (ret)
+		return 0;
+
+	/* Touchscreen is at address 0x38, ID register is 0xbb. */
+	ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
+	if (ret)
+		return 0;
+
+	/* EP0430 prefixes the response with 0xbb, skip it. */
+	if (*touchptr == 0xbb)
+		touchptr++;
+
+	/* Skip the 'EP' prefix. */
+	touchptr += 2;
+
+	ret = !memcmp(touchptr, &dev->mode.name[7], 4);
+	if (ret)
+		lvds_compat_string = dev->mode.name;
+
+	return ret;
+}
+
+void board_preboot_os(void)
+{
+	/* Power off the LCD to prevent awful color flicker */
+	gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	if (lvds_compat_string)
+		do_fixup_by_path_string(blob, "/panel", "compatible",
+					lvds_compat_string);
+
+	return 0;
+}
+
+struct display_info_t const displays[] = {
+	{
+		.bus	= 0,
+		.addr	= 0,
+		.detect	= detect_lvds,
+		.enable	= enable_lvds_etm0430g0dh6,
+		.pixfmt	= IPU_PIX_FMT_RGB666,
+		.mode	= {
+			.name		= "edt,etm0430g0dh6",
+			.refresh	= 60,
+			.xres		= 480,
+			.yres		= 272,
+			.pixclock	= 111111, /* picosecond (9 MHz) */
+			.left_margin	= 2,
+			.right_margin	= 2,
+			.upper_margin	= 2,
+			.lower_margin	= 2,
+			.hsync_len	= 41,
+			.vsync_len	= 10,
+			.sync		= 0x40000000,
+			.vmode          = FB_VMODE_NONINTERLACED
+		}
+	}, {
+		.bus	= 0,
+		.addr	= 0,
+		.detect	= detect_lvds,
+		.enable	= enable_lvds_etm0700g0dh6,
+		.pixfmt	= IPU_PIX_FMT_RGB666,
+		.mode	= {
+			.name		= "edt,etm0700g0dh6",
+			.refresh	= 60,
+			.xres		= 800,
+			.yres		= 480,
+			.pixclock	= 30048, /* picosecond (33.28 MHz) */
+			.left_margin	= 40,
+			.right_margin	= 88,
+			.upper_margin	= 10,
+			.lower_margin	= 33,
+			.hsync_len	= 128,
+			.vsync_len	= 2,
+			.sync		= FB_SYNC_EXT,
+			.vmode          = FB_VMODE_NONINTERLACED
+		}
+	}
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+#ifdef CONFIG_SPLASH_SCREEN
+static struct splash_location default_splash_locations[] = {
+	{
+		.name		= "mmc_fs",
+		.storage	= SPLASH_STORAGE_MMC,
+		.flags		= SPLASH_STORAGE_FS,
+		.devpart	= "0:1",
+	},
+};
+
+int splash_screen_prepare(void)
+{
+	return splash_source_load(default_splash_locations,
+				  ARRAY_SIZE(default_splash_locations));
+}
+#endif
+
+int board_late_init(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+	struct udevice *dev;
+	int xpos, ypos, ret;
+	char *s;
+	void *dst;
+	ulong addr, len;
+
+	splash_get_pos(&xpos, &ypos);
+
+	s = env_get("splashimage");
+	if (!s)
+		return 0;
+
+	addr = simple_strtoul(s, NULL, 16);
+	dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
+	if (!dst)
+		return -ENOMEM;
+
+	ret = splash_screen_prepare();
+	if (ret < 0)
+		goto splasherr;
+
+	len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
+	ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
+		     (uchar *)addr, &len);
+	if (ret) {
+		printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
+		goto splasherr;
+	}
+
+	ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
+	if (ret)
+		goto splasherr;
+
+	ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
+	if (ret)
+		goto splasherr;
+
+	return 0;
+
+splasherr:
+	free(dst);
+#endif
+	return 0;
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+	static const iomux_v3_cfg_t i2c_pads[] = {
+		/* I2C1 */
+		NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
+		/* I2C2 */
+		NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
+}
+
+static void setup_iomux_video(void)
+{
+	static const iomux_v3_cfg_t lcd_pads[] = {
+		MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
+		MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
+		MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
+		MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
+		MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+}
+
+static void setup_iomux_nand(void)
+{
+	static const iomux_v3_cfg_t nand_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
+			     PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
+			     PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
+			     PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
+			     PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
+			     PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
+			     PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
+			     PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
+			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
+			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
+			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
+			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
+			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
+			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
+			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
+			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+}
+
+static void m53_set_clock(void)
+{
+	int ret;
+	const u32 ref_clk = MXC_HCLK;
+	const u32 dramclk = 400;
+	u32 cpuclk;
+
+	gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
+
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
+					    PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
+	gpio_direction_input(IMX_GPIO_NR(4, 0));
+
+	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
+	cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
+
+	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
+
+	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
+	if (ret) {
+		printf("CPU:   Switch peripheral clock to %dMHz failed\n",
+		       dramclk);
+	}
+
+	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
+}
+
+static void m53_set_nand(void)
+{
+	u32 i;
+
+	/* NAND flash is muxed on ATA pins */
+	setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
+
+	/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
+	for (i = 0x4; i < 0x94; i += 0x18) {
+		clrbits_le32(WEIM_BASE_ADDR + i,
+			     WEIM_GCR2_MUX16_BYP_GRANT_MASK);
+	}
+
+	mxc_set_clock(0, 33, MXC_NFC_CLK);
+	enable_nfc_clk(1);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_iomux_fec();
+	setup_iomux_i2c();
+	setup_iomux_nand();
+	setup_iomux_video();
+
+	m53_set_clock();
+
+	mxc_set_sata_internal_clock();
+
+	/* NAND clock @ 33MHz */
+	m53_set_nand();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Menlosystems M53Menlo\n");
+
+	return 0;
+}
+
+/*
+ * NAND SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+	setup_iomux_nand();
+	m53_set_clock();
+	m53_set_nand();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NAND;
+}
+#endif
diff --git a/roms/u-boot/board/microchip/mpfs_icicle/Kconfig b/roms/u-boot/board/microchip/mpfs_icicle/Kconfig
new file mode 100644
index 000000000..467846237
--- /dev/null
+++ b/roms/u-boot/board/microchip/mpfs_icicle/Kconfig
@@ -0,0 +1,49 @@
+if TARGET_MICROCHIP_ICICLE
+
+config SYS_BOARD
+	default "mpfs_icicle"
+
+config SYS_VENDOR
+	default "microchip"
+
+config SYS_CPU
+	default "generic"
+
+config SYS_CONFIG_NAME
+	default "microchip_mpfs_icicle"
+
+config SYS_TEXT_BASE
+	default 0x80000000 if !RISCV_SMODE
+	default 0x80200000 if RISCV_SMODE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select GENERIC_RISCV
+	select BOARD_EARLY_INIT_F
+	select BOARD_LATE_INIT
+	imply SMP
+	imply CLK_CCF
+	imply CLK_MPFS
+	imply SYS_NS16550
+	imply CMD_DHCP
+	imply CMD_EXT2
+	imply CMD_EXT4
+	imply CMD_FAT
+	imply CMD_FS_GENERIC
+	imply CMD_NET
+	imply CMD_PING
+	imply CMD_MMC
+	imply DOS_PARTITION
+	imply EFI_PARTITION
+	imply IP_DYN
+	imply ISO_PARTITION
+	imply MACB
+	imply MII
+	imply PHY_LIB
+	imply PHY_VITESSE
+	imply MMC
+	imply MMC_WRITE
+	imply MMC_SDHCI
+	imply MMC_SDHCI_CADENCE
+
+endif
diff --git a/roms/u-boot/board/microchip/mpfs_icicle/MAINTAINERS b/roms/u-boot/board/microchip/mpfs_icicle/MAINTAINERS
new file mode 100644
index 000000000..22f3b97d8
--- /dev/null
+++ b/roms/u-boot/board/microchip/mpfs_icicle/MAINTAINERS
@@ -0,0 +1,7 @@
+Microchip MPFS icicle
+M:	Padmarao Begari <padmarao.begari@microchip.com>
+M:	Cyril Jean <cyril.jean@microchip.com>
+S:	Maintained
+F:	board/microchip/mpfs_icicle/
+F:	include/configs/microchip_mpfs_icicle.h
+F:	configs/microchip_mpfs_icicle_defconfig
diff --git a/roms/u-boot/board/microchip/mpfs_icicle/Makefile b/roms/u-boot/board/microchip/mpfs_icicle/Makefile
new file mode 100644
index 000000000..72b0410dd
--- /dev/null
+++ b/roms/u-boot/board/microchip/mpfs_icicle/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Microchip Technology Inc.
+# Padmarao Begari <padmarao.begari@microchip.com>
+#
+
+obj-y	+= mpfs_icicle.o
diff --git a/roms/u-boot/board/microchip/mpfs_icicle/mpfs_icicle.c b/roms/u-boot/board/microchip/mpfs_icicle/mpfs_icicle.c
new file mode 100644
index 000000000..afef719df
--- /dev/null
+++ b/roms/u-boot/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MPFS_SYSREG_SOFT_RESET		((unsigned int *)0x20002088)
+#define MPFS_SYS_SERVICE_CR		((unsigned int *)0x37020050)
+#define MPFS_SYS_SERVICE_SR		((unsigned int *)0x37020054)
+#define MPFS_SYS_SERVICE_MAILBOX	((unsigned char *)0x37020800)
+
+#define PERIPH_RESET_VALUE		0x1e8u
+#define SERVICE_CR_REQ			0x1u
+#define SERVICE_SR_BUSY			0x2u
+
+static void read_device_serial_number(u8 *response, u8 response_size)
+{
+	u8 idx;
+	u8 *response_buf;
+	unsigned int val;
+
+	response_buf = (u8 *)response;
+
+	writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR);
+	/*
+	 * REQ bit will remain set till the system controller starts
+	 * processing.
+	 */
+	do {
+		val = readl(MPFS_SYS_SERVICE_CR);
+	} while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ));
+
+	/*
+	 * Once system controller starts processing the busy bit will
+	 * go high and service is completed when busy bit is gone low
+	 */
+	do {
+		val = readl(MPFS_SYS_SERVICE_SR);
+	} while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY));
+
+	for (idx = 0; idx < response_size; idx++)
+		response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx);
+}
+
+int board_init(void)
+{
+	/* For now nothing to do here. */
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	unsigned int val;
+
+	/* Reset uart, mmc peripheral */
+	val = readl(MPFS_SYSREG_SOFT_RESET);
+	val = (val & ~(PERIPH_RESET_VALUE));
+	writel(val, MPFS_SYSREG_SOFT_RESET);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	u32 ret;
+	u32 node;
+	u8 idx;
+	u8 device_serial_number[16] = { 0 };
+	unsigned char mac_addr[6];
+	char icicle_mac_addr[20];
+	void *blob = (void *)gd->fdt_blob;
+
+	node = fdt_path_offset(blob, "ethernet0");
+	if (node < 0) {
+		printf("No ethernet0 path offset\n");
+		return -ENODEV;
+	}
+
+	ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr, 6);
+	if (ret) {
+		printf("No local-mac-address property\n");
+		return -EINVAL;
+	}
+
+	read_device_serial_number(device_serial_number, 16);
+
+	/* Update MAC address with device serial number */
+	mac_addr[0] = 0x00;
+	mac_addr[1] = 0x04;
+	mac_addr[2] = 0xA3;
+	mac_addr[3] = device_serial_number[2];
+	mac_addr[4] = device_serial_number[1];
+	mac_addr[5] = device_serial_number[0];
+
+	ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+	if (ret) {
+		printf("Error setting local-mac-address property\n");
+		return -ENODEV;
+	}
+
+	icicle_mac_addr[0] = '[';
+
+	sprintf(&icicle_mac_addr[1], "%pM", mac_addr);
+
+	icicle_mac_addr[18] = ']';
+	icicle_mac_addr[19] = '\0';
+
+	for (idx = 0; idx < 20; idx++) {
+		if (icicle_mac_addr[idx] == ':')
+			icicle_mac_addr[idx] = ' ';
+	}
+	env_set("icicle_mac_addr", icicle_mac_addr);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/microchip/pic32mzda/Kconfig b/roms/u-boot/board/microchip/pic32mzda/Kconfig
new file mode 100644
index 000000000..4f08e98b9
--- /dev/null
+++ b/roms/u-boot/board/microchip/pic32mzda/Kconfig
@@ -0,0 +1,16 @@
+
+if TARGET_PIC32MZDASK
+
+config SYS_BOARD
+	default "pic32mzda"
+
+config SYS_VENDOR
+	default "microchip"
+
+config SYS_CONFIG_NAME
+	default "pic32mzdask"
+
+config SYS_TEXT_BASE
+	default 0x9d004000
+
+endif
diff --git a/roms/u-boot/board/microchip/pic32mzda/MAINTAINERS b/roms/u-boot/board/microchip/pic32mzda/MAINTAINERS
new file mode 100644
index 000000000..c934f1a1f
--- /dev/null
+++ b/roms/u-boot/board/microchip/pic32mzda/MAINTAINERS
@@ -0,0 +1,6 @@
+PIC32MZDASK BOARD
+M:	Purna Chandra Mandal <purna.mandal@microchip.com>
+S:	Maintained
+F:	board/microchip/pic32mzda/
+F:	include/configs/pic32mzdask.h
+F:	configs/pic32mzdask_defconfig
diff --git a/roms/u-boot/board/microchip/pic32mzda/Makefile b/roms/u-boot/board/microchip/pic32mzda/Makefile
new file mode 100644
index 000000000..36295302a
--- /dev/null
+++ b/roms/u-boot/board/microchip/pic32mzda/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.mandal@microchip.com.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+obj-y := pic32mzda.o
diff --git a/roms/u-boot/board/microchip/pic32mzda/README b/roms/u-boot/board/microchip/pic32mzda/README
new file mode 100644
index 000000000..91d16ab7d
--- /dev/null
+++ b/roms/u-boot/board/microchip/pic32mzda/README
@@ -0,0 +1,22 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
+ */
+
+PIC32MZ[DA] Starter Kit
+----------------------------------------
+PIC32MZ[DA] Starter Kit is based on PIC32MZ[DA] family of micro-controller.
+This family is powered by MIPS M14KEC 32bit general purpose core and has
+advanced microcontroller features and peripherals.
+
+This processor boots with proprietary stage1 bootloader running from internal
+boot-flash. Stage1 bootloader inturns locates and jumps to U-Boot programmed
+on internal program-flash. Finally U-Boot loads OS image (along with other
+required files for booting) from either uSD card, or ethernet, or from USB
+storage.
+
+To boot Linux following three files are mandatory - uEnv.txt (custom U-Boot
+environment file), uImage, *.dtb (platform device-tree-blob file).
+
+U-Boot jumps to Linux using UHI specification.
+
+Visit http://microchip.com for details.
diff --git a/roms/u-boot/board/microchip/pic32mzda/pic32mzda.c b/roms/u-boot/board/microchip/pic32mzda/pic32mzda.c
new file mode 100644
index 000000000..e7337deea
--- /dev/null
+++ b/roms/u-boot/board/microchip/pic32mzda/pic32mzda.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Microchip PIC32MZ[DA] Starter Kit board
+ *
+ * Copyright (C) 2015, Microchip Technology Inc.
+ * Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <init.h>
+#include <malloc.h>
+#include <dt-bindings/clock/microchip,clock.h>
+#include <mach/pic32.h>
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	ulong rate;
+	struct udevice *dev;
+	struct clk clk;
+	int ret;
+
+	printf("Core: %s\n", get_core_name());
+
+	if (uclass_get_device(UCLASS_CLK, 0, &dev))
+		return 0;
+
+	clk.id = PB7CLK;
+	ret = clk_request(dev, &clk);
+	if (ret < 0)
+		return 0;
+
+	rate = clk_get_rate(&clk);
+	printf("CPU Speed: %lu MHz\n", rate / 1000000);
+
+	clk_free(&clk);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/mikrotik/crs3xx-98dx3236/.gitignore b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/.gitignore
new file mode 100644
index 000000000..775b9346b
--- /dev/null
+++ b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/.gitignore
@@ -0,0 +1 @@
+kwbimage.cfg
diff --git a/roms/u-boot/board/mikrotik/crs3xx-98dx3236/MAINTAINERS b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/MAINTAINERS
new file mode 100644
index 000000000..906ff9897
--- /dev/null
+++ b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/MAINTAINERS
@@ -0,0 +1,33 @@
+CRS3XX-98DX3236 BOARD
+M:	Luka Kovacic <luka.kovacic@sartura.hr>
+M:	Luka Perkov <luka.perkov@sartura.hr>
+S:	Maintained
+F:	board/mikrotik/crs3xx-98dx3236/
+F:	include/configs/crs3xx-98dx3236.h
+
+CRS305-1G-4S BOARD
+M:	Luka Kovacic <luka.kovacic@sartura.hr>
+M:	Luka Perkov <luka.perkov@sartura.hr>
+S:	Maintained
+F:	configs/crs305-1g-4s_defconfig
+F:	configs/crs305-1g-4s-bit_defconfig
+F:	arch/arm/dts/armada-xp-crs305-1g-4s.dts
+F:	arch/arm/dts/armada-xp-crs305-1g-4s-bit.dts
+
+CRS326-24G-2S BOARD
+M:	Luka Kovacic <luka.kovacic@sartura.hr>
+M:	Luka Perkov <luka.perkov@sartura.hr>
+S:	Maintained
+F:	configs/crs326-24g-2s_defconfig
+F:	configs/crs326-24g-2s-bit_defconfig
+F:	arch/arm/dts/armada-xp-crs326-24g-2s.dts
+F:	arch/arm/dts/armada-xp-crs326-24g-2s-bit.dts
+
+CRS328-4C-20S-4S BOARD
+M:	Luka Kovacic <luka.kovacic@sartura.hr>
+M:	Luka Perkov <luka.perkov@sartura.hr>
+S:	Maintained
+F:	configs/crs328-4c-20s-4s_defconfig
+F:	configs/crs328-4c-20s-4s-bit_defconfig
+F:	arch/arm/dts/armada-xp-crs328-4c-20s-4s.dts
+F:	arch/arm/dts/armada-xp-crs328-4c-20s-4s-bit.dts
diff --git a/roms/u-boot/board/mikrotik/crs3xx-98dx3236/Makefile b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/Makefile
new file mode 100644
index 000000000..0b2930d3e
--- /dev/null
+++ b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+
+obj-y	:= crs3xx-98dx3236.o
+extra-y	:= kwbimage.cfg
+
+quiet_cmd_sed = SED     $@
+      cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F)
+
+SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|"
+$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
+		include/config/auto.conf
+	  $(call if_changed,sed)
diff --git a/roms/u-boot/board/mikrotik/crs3xx-98dx3236/README b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/README
new file mode 100644
index 000000000..952f774ab
--- /dev/null
+++ b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/README
@@ -0,0 +1,23 @@
+MikroTik CRS3XX-98DX3236
+========================
+
+CRS3XX-98DX3236 is a U-Boot port that supports a series of MikroTik switches
+based on the Marvell Prestera 98DX3236 switch with an integrated CPU.
+
+Common specifications:
+ - Marvell Prestera 98DX3236 switch with an integrated ARMv7 CPU
+ - 512 MB DDR3 RAM
+ - UART @ 115200bps
+ - 16 MB SPI flash (Winbond 25Q128JVSM)
+
+Currently supported hardware:
+ - UART boot (using kwboot) and console
+ - SPI boot, environment and load kernel
+
+Planned:
+ - Gigabit Ethernet support (internal CPU <-> switch fabric connection)
+
+Getting binary.0
+================
+binary.0 (DDR3 init phase) can be retrieved/extracted from the integrated bootloader on the SPI flash.
+Then binary.0 can be replaced with the extracted blob.
diff --git a/roms/u-boot/board/mikrotik/crs3xx-98dx3236/binary.0 b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/binary.0
new file mode 100644
index 000000000..8dd687286
--- /dev/null
+++ b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/binary.0
@@ -0,0 +1,11 @@
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
diff --git a/roms/u-boot/board/mikrotik/crs3xx-98dx3236/crs3xx-98dx3236.c b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/crs3xx-98dx3236.c
new file mode 100644
index 000000000..315169ba6
--- /dev/null
+++ b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/crs3xx-98dx3236.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <linux/bitops.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * These values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2016_T1.0.eng_drop_v6"
+ */
+#define DB_DX_AC3_GPP_OUT_ENA_LOW	(~(BIT(0) | BIT(2) | BIT(3) | BIT(4) \
+					| BIT(6) | BIT(12) | BIT(13) \
+					| BIT(16) | BIT(17) | BIT(20) \
+					| BIT(29)  | BIT(30)))
+#define DB_DX_AC3_GPP_OUT_ENA_MID	(~(0))
+#define DB_DX_AC3_GPP_OUT_VAL_LOW	(BIT(0) | BIT(2) | BIT(3) | BIT(4) \
+					| BIT(6) | BIT(12) | BIT(13) \
+					| BIT(16) | BIT(17) | BIT(20) \
+					| BIT(29)  | BIT(30))
+#define DB_DX_AC3_GPP_OUT_VAL_MID	0x0
+#define DB_DX_AC3_GPP_POL_LOW		0x0
+#define DB_DX_AC3_GPP_POL_MID		0x0
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x00142222, MVEBU_MPP_BASE + 0x00);
+	writel(0x11122000, MVEBU_MPP_BASE + 0x04);
+	writel(0x44444004, MVEBU_MPP_BASE + 0x08);
+	writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
+	writel(0x00000001, MVEBU_MPP_BASE + 0x10);
+
+	/*
+	 * MVEBU_GPIO0_BASE is the User LED
+	 * MVEBU_GPIO1_BASE is the Reset Button (currently not used)
+	 */
+
+	/* Set GPP Out value */
+	writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	/* writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); */
+
+	/* Set GPP Polarity */
+	writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	/* writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); */
+
+	/* Set GPP Out Enable */
+	writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	/* writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); */
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: " CONFIG_SYS_BOARD "\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/mikrotik/crs3xx-98dx3236/kwbimage.cfg.in b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/kwbimage.cfg.in
new file mode 100644
index 000000000..9a58b33a6
--- /dev/null
+++ b/roms/u-boot/board/mikrotik/crs3xx-98dx3236/kwbimage.cfg.in
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/mikrotik/crs3xx-98dx3236/binary.0 0000005b 00000068
diff --git a/roms/u-boot/board/mpc8308_p1m/Kconfig b/roms/u-boot/board/mpc8308_p1m/Kconfig
new file mode 100644
index 000000000..b7e39dafb
--- /dev/null
+++ b/roms/u-boot/board/mpc8308_p1m/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_MPC8308_P1M
+
+config SYS_BOARD
+	default "mpc8308_p1m"
+
+config SYS_CONFIG_NAME
+	default "mpc8308_p1m"
+
+endif
diff --git a/roms/u-boot/board/mpc8308_p1m/MAINTAINERS b/roms/u-boot/board/mpc8308_p1m/MAINTAINERS
new file mode 100644
index 000000000..80d8de771
--- /dev/null
+++ b/roms/u-boot/board/mpc8308_p1m/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8308_P1M BOARD
+M:	Ilya Yanok <yanok@emcraft.com>
+S:	Maintained
+F:	board/mpc8308_p1m/
+F:	include/configs/mpc8308_p1m.h
+F:	configs/mpc8308_p1m_defconfig
diff --git a/roms/u-boot/board/mpc8308_p1m/Makefile b/roms/u-boot/board/mpc8308_p1m/Makefile
new file mode 100644
index 000000000..4ec3b0cda
--- /dev/null
+++ b/roms/u-boot/board/mpc8308_p1m/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010
+# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+
+obj-y	:= mpc8308_p1m.o sdram.o
diff --git a/roms/u-boot/board/mpc8308_p1m/mpc8308_p1m.c b/roms/u-boot/board/mpc8308_p1m/mpc8308_p1m.c
new file mode 100644
index 000000000..87607bd48
--- /dev/null
+++ b/roms/u-boot/board/mpc8308_p1m/mpc8308_p1m.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+int checkboard(void)
+{
+	printf("Board: MPC8308 P1M\n");
+
+	return 0;
+}
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+	law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(1, pcie_reg);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
+
+	return 0;
+}
+#endif
+
+int board_eth_init(struct bd_info *bis)
+{
+	int rv, num_if = 0;
+
+	/* Initialize TSECs first */
+	rv = cpu_eth_init(bis);
+	if (rv >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize TSECs.\n");
+
+	rv = pci_eth_init(bis);
+	if (rv >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+	return num_if;
+}
diff --git a/roms/u-boot/board/mpc8308_p1m/sdram.c b/roms/u-boot/board/mpc8308_p1m/sdram.c
new file mode 100644
index 000000000..62a2d8a53
--- /dev/null
+++ b/roms/u-boot/board/mpc8308_p1m/sdram.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * This files is  mostly identical to the original from
+ * board/freescale/mpc8308rdb/sdram.c
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mpc83xx.h>
+#include <asm/global_data.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+			CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	sync();
+
+	return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
+}
+
+int dram_init(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/mqmaker/miqi_rk3288/Kconfig b/roms/u-boot/board/mqmaker/miqi_rk3288/Kconfig
new file mode 100644
index 000000000..232a11209
--- /dev/null
+++ b/roms/u-boot/board/mqmaker/miqi_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MIQI_RK3288
+
+config SYS_BOARD
+	default "miqi_rk3288"
+
+config SYS_VENDOR
+	default "mqmaker"
+
+config SYS_CONFIG_NAME
+	default "miqi_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/mqmaker/miqi_rk3288/MAINTAINERS b/roms/u-boot/board/mqmaker/miqi_rk3288/MAINTAINERS
new file mode 100644
index 000000000..053a5e602
--- /dev/null
+++ b/roms/u-boot/board/mqmaker/miqi_rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+MIQI
+M:	Jernej Skrabec <jernej.skrabec@siol.net>
+S:	Maintained
+F:	board/mqmaker/miqi_rk3288
+F:	include/configs/miqi_rk3288.h
+F:	configs/miqi-rk3288_defconfig
diff --git a/roms/u-boot/board/mqmaker/miqi_rk3288/Makefile b/roms/u-boot/board/mqmaker/miqi_rk3288/Makefile
new file mode 100644
index 000000000..ec95affb3
--- /dev/null
+++ b/roms/u-boot/board/mqmaker/miqi_rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= miqi-rk3288.o
diff --git a/roms/u-boot/board/mqmaker/miqi_rk3288/miqi-rk3288.c b/roms/u-boot/board/mqmaker/miqi_rk3288/miqi-rk3288.c
new file mode 100644
index 000000000..779bc646b
--- /dev/null
+++ b/roms/u-boot/board/mqmaker/miqi_rk3288/miqi-rk3288.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
diff --git a/roms/u-boot/board/mscc/common/Makefile b/roms/u-boot/board/mscc/common/Makefile
new file mode 100644
index 000000000..4f0eded85
--- /dev/null
+++ b/roms/u-boot/board/mscc/common/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_JR2)	:= spi.o
+obj-$(CONFIG_SOC_OCELOT)	:= spi.o
diff --git a/roms/u-boot/board/mscc/common/spi.c b/roms/u-boot/board/mscc/common/spi.c
new file mode 100644
index 000000000..45b964933
--- /dev/null
+++ b/roms/u-boot/board/mscc/common/spi.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Coprporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <linux/bitops.h>
+
+void external_cs_manage(struct udevice *dev, bool enable)
+{
+	u32 cs = spi_chip_select(dev);
+	/* IF_SI0_OWNER, select the owner of the SI interface
+	 * Encoding: 0: SI Slave
+	 *	     1: SI Boot Master
+	 *	     2: SI Master Controller
+	 */
+	if (!enable) {
+		writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
+		       ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
+		       BASE_CFG + ICPU_SW_MODE);
+		clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
+				ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+				ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
+	} else {
+		writel(0, BASE_CFG + ICPU_SW_MODE);
+		clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
+				ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+				ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
+	}
+}
diff --git a/roms/u-boot/board/mscc/jr2/Kconfig b/roms/u-boot/board/mscc/jr2/Kconfig
new file mode 100644
index 000000000..68a2de8ca
--- /dev/null
+++ b/roms/u-boot/board/mscc/jr2/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+	default "mscc"
+
+if SOC_JR2
+
+config SYS_BOARD
+	default "jr2"
+
+config SYS_CONFIG_NAME
+	default "jr2"
+
+endif
+
diff --git a/roms/u-boot/board/mscc/jr2/Makefile b/roms/u-boot/board/mscc/jr2/Makefile
new file mode 100644
index 000000000..c1db2a904
--- /dev/null
+++ b/roms/u-boot/board/mscc/jr2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_JR2)	:= jr2.o
+
diff --git a/roms/u-boot/board/mscc/jr2/jr2.c b/roms/u-boot/board/mscc/jr2/jr2.c
new file mode 100644
index 000000000..1c516aacd
--- /dev/null
+++ b/roms/u-boot/board/mscc/jr2/jr2.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <asm/io.h>
+#include <led.h>
+#include <miiphy.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <asm/global_data.h>
+
+enum {
+	BOARD_TYPE_PCB110 = 0xAABBCE00,
+	BOARD_TYPE_PCB111,
+	BOARD_TYPE_PCB112,
+};
+
+int board_early_init_r(void)
+{
+	/* Prepare SPI controller to be used in master mode */
+	writel(0, BASE_CFG + ICPU_SW_MODE);
+	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
+			ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+			ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	return 0;
+}
+
+static void vcoreiii_gpio_set_alternate(int gpio, int mode)
+{
+	u32 mask;
+	u32 val0, val1;
+	void __iomem *reg0, *reg1;
+
+	if (gpio < 32) {
+		mask = BIT(gpio);
+		reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(0);
+		reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(1);
+	} else {
+		gpio -= 32;
+		mask = BIT(gpio);
+		reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(0);
+		reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(1);
+	}
+	val0 = readl(reg0);
+	val1 = readl(reg1);
+	if (mode == 1) {
+		writel(val0 | mask, reg0);
+		writel(val1 & ~mask, reg1);
+	} else if (mode == 2) {
+		writel(val0 & ~mask, reg0);
+		writel(val1 | mask, reg1);
+	} else if (mode == 3) {
+		writel(val0 | mask, reg0);
+		writel(val1 | mask, reg1);
+	} else {
+		writel(val0 & ~mask, reg0);
+		writel(val1 & ~mask, reg1);
+	}
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (gd->board_type == BOARD_TYPE_PCB110 ||
+	    gd->board_type == BOARD_TYPE_PCB112) {
+		phy_write(phydev, 0, 31, 0x10);
+		phy_write(phydev, 0, 18, 0x80F0);
+		while (phy_read(phydev, 0, 18) & 0x8000)
+			;
+		phy_write(phydev, 0, 31, 0);
+	}
+	if (gd->board_type == BOARD_TYPE_PCB111) {
+		phy_write(phydev, 0, 31, 0x10);
+		phy_write(phydev, 0, 18, 0x80A0);
+		while (phy_read(phydev, 0, 18) & 0x8000)
+			;
+		phy_write(phydev, 0, 14, 0x800);
+		phy_write(phydev, 0, 31, 0);
+	}
+
+	return 0;
+}
+
+void board_debug_uart_init(void)
+{
+	/* too early for the pinctrl driver, so configure the UART pins here */
+	vcoreiii_gpio_set_alternate(10, 1);
+	vcoreiii_gpio_set_alternate(11, 1);
+}
+
+static void do_board_detect(void)
+{
+	int i;
+	u16 pval;
+
+	/* MIIM 1 + 2  MDC/MDIO */
+	for (i = 56; i < 60; i++)
+		vcoreiii_gpio_set_alternate(i, 1);
+
+	/* small delay for settling the pins */
+	mdelay(30);
+
+	if (mscc_phy_rd(0, 0x10, 0x3, &pval) == 0 &&
+	    ((pval >> 4) & 0x3F) == 0x3c) {
+		gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */
+	} else if (mscc_phy_rd(1, 0x0, 0x3, &pval) == 0 &&
+		   ((pval >> 4) & 0x3F) == 0x3c) {
+		gd->board_type = BOARD_TYPE_PCB110; /* Jr2-24 */
+	} else {
+		/* Fall-back */
+		gd->board_type = BOARD_TYPE_PCB111; /* Jr2-48 */
+	}
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	if (gd->board_type == BOARD_TYPE_PCB110 &&
+	    strcmp(name, "jr2_pcb110") == 0)
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_PCB111 &&
+	    strcmp(name, "jr2_pcb111") == 0)
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_PCB112 &&
+	    strcmp(name, "serval2_pcb112") == 0)
+		return 0;
+
+	return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+	do_board_detect();
+	fdtdec_setup();
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/mscc/luton/Kconfig b/roms/u-boot/board/mscc/luton/Kconfig
new file mode 100644
index 000000000..e1199808d
--- /dev/null
+++ b/roms/u-boot/board/mscc/luton/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+if SOC_LUTON
+
+config SYS_VENDOR
+	default "mscc"
+
+config SYS_BOARD
+	default "luton"
+
+config SYS_CONFIG_NAME
+	default "luton"
+
+endif
diff --git a/roms/u-boot/board/mscc/luton/Makefile b/roms/u-boot/board/mscc/luton/Makefile
new file mode 100644
index 000000000..b27f7c773
--- /dev/null
+++ b/roms/u-boot/board/mscc/luton/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_LUTON)	:= luton.o
diff --git a/roms/u-boot/board/mscc/luton/luton.c b/roms/u-boot/board/mscc/luton/luton.c
new file mode 100644
index 000000000..038902d08
--- /dev/null
+++ b/roms/u-boot/board/mscc/luton/luton.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <led.h>
+#include <miiphy.h>
+
+enum {
+	BOARD_TYPE_PCB090 = 0xAABBCD00,
+	BOARD_TYPE_PCB091,
+};
+
+void board_debug_uart_init(void)
+{
+	/* too early for the pinctrl driver, so configure the UART pins here */
+	mscc_gpio_set_alternate(30, 1);
+	mscc_gpio_set_alternate(31, 1);
+}
+
+int board_early_init_r(void)
+{
+	/* Prepare SPI controller to be used in master mode */
+	writel(0, BASE_CFG + ICPU_SW_MODE);
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, 0, 31, 0x10);
+	phy_write(phydev, 0, 18, 0x80A0);
+	while (phy_read(phydev, 0, 18) & 0x8000)
+		;
+	phy_write(phydev, 0, 31, 0);
+	return 0;
+}
+
+static void do_board_detect(void)
+{
+	u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0xFFFF;
+
+	if (chipid == 0x7428 || chipid == 0x7424)
+		gd->board_type = BOARD_TYPE_PCB091;    // Lu10
+	else
+		gd->board_type = BOARD_TYPE_PCB090;    // Lu26
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	if (gd->board_type == BOARD_TYPE_PCB090 &&
+	    strcmp(name, "luton_pcb090") == 0)
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_PCB091 &&
+	    strcmp(name, "luton_pcb091") == 0)
+		return 0;
+
+	return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+	do_board_detect();
+	fdtdec_setup();
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/mscc/ocelot/Kconfig b/roms/u-boot/board/mscc/ocelot/Kconfig
new file mode 100644
index 000000000..9ddc0880b
--- /dev/null
+++ b/roms/u-boot/board/mscc/ocelot/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+	default "mscc"
+
+if SOC_OCELOT
+
+config SYS_BOARD
+	default "ocelot"
+
+config SYS_CONFIG_NAME
+	default "ocelot"
+
+endif
diff --git a/roms/u-boot/board/mscc/ocelot/Makefile b/roms/u-boot/board/mscc/ocelot/Makefile
new file mode 100644
index 000000000..9f28c8126
--- /dev/null
+++ b/roms/u-boot/board/mscc/ocelot/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_OCELOT)	:= ocelot.o
+
diff --git a/roms/u-boot/board/mscc/ocelot/ocelot.c b/roms/u-boot/board/mscc/ocelot/ocelot.c
new file mode 100644
index 000000000..c462890bb
--- /dev/null
+++ b/roms/u-boot/board/mscc/ocelot/ocelot.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <spi.h>
+#include <led.h>
+#include <wait_bit.h>
+#include <miiphy.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	BOARD_TYPE_PCB120 = 0xAABBCC00,
+	BOARD_TYPE_PCB123,
+};
+
+void mscc_switch_reset(bool enter)
+{
+	/* Nasty workaround to avoid GPIO19 (DDR!) being reset */
+	mscc_gpio_set_alternate(19, 2);
+
+	debug("applying SwC reset\n");
+
+	writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
+	writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+	if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
+			      PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
+		pr_err("Tiemout while waiting for switch reset\n");
+
+	/*
+	 * Reset GPIO19 mode back as regular GPIO, output, high (DDR
+	 * not reset) (Order is important)
+	 */
+	setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+	writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
+	mscc_gpio_set_alternate(19, 0);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (gd->board_type == BOARD_TYPE_PCB123)
+		return 0;
+
+	phy_write(phydev, 0, 31, 0x10);
+	phy_write(phydev, 0, 18, 0x80F0);
+	while (phy_read(phydev, 0, 18) & 0x8000)
+		;
+	phy_write(phydev, 0, 31, 0);
+
+	return 0;
+}
+
+void board_debug_uart_init(void)
+{
+	/* too early for the pinctrl driver, so configure the UART pins here */
+	mscc_gpio_set_alternate(6, 1);
+	mscc_gpio_set_alternate(7, 1);
+}
+
+int board_early_init_r(void)
+{
+	/* Prepare SPI controller to be used in master mode */
+	writel(0, BASE_CFG + ICPU_SW_MODE);
+	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
+			ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+			ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	return 0;
+}
+
+static void do_board_detect(void)
+{
+	u16 dummy = 0;
+
+	/* Enable MIIM */
+	mscc_gpio_set_alternate(14, 1);
+	mscc_gpio_set_alternate(15, 1);
+	if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
+		gd->board_type = BOARD_TYPE_PCB120;
+	else
+		gd->board_type = BOARD_TYPE_PCB123;
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	if (gd->board_type == BOARD_TYPE_PCB120 &&
+	    strcmp(name, "ocelot_pcb120") == 0)
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_PCB123 &&
+	    strcmp(name, "ocelot_pcb123") == 0)
+		return 0;
+
+	return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+	do_board_detect();
+	fdtdec_setup();
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/mscc/serval/Kconfig b/roms/u-boot/board/mscc/serval/Kconfig
new file mode 100644
index 000000000..64f1c683e
--- /dev/null
+++ b/roms/u-boot/board/mscc/serval/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+	default "mscc"
+
+if SOC_SERVAL
+
+config SYS_BOARD
+	default "serval"
+
+config SYS_CONFIG_NAME
+	default "serval"
+
+endif
diff --git a/roms/u-boot/board/mscc/serval/Makefile b/roms/u-boot/board/mscc/serval/Makefile
new file mode 100644
index 000000000..c7ba56e95
--- /dev/null
+++ b/roms/u-boot/board/mscc/serval/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_SERVAL)	:= serval.o
diff --git a/roms/u-boot/board/mscc/serval/serval.c b/roms/u-boot/board/mscc/serval/serval.c
new file mode 100644
index 000000000..94c1c42b7
--- /dev/null
+++ b/roms/u-boot/board/mscc/serval/serval.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <led.h>
+#include <miiphy.h>
+
+enum {
+	BOARD_TYPE_PCB106 = 0xAABBCD00,
+	BOARD_TYPE_PCB105,
+};
+
+int board_early_init_r(void)
+{
+	/* Prepare SPI controller to be used in master mode */
+	writel(0, BASE_CFG + ICPU_SW_MODE);
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, 0, 31, 0x10);
+	phy_write(phydev, 0, 18, 0x80F0);
+	while (phy_read(phydev, 0, 18) & 0x8000)
+		;
+	phy_write(phydev, 0, 14, 0x800);
+	phy_write(phydev, 0, 31, 0);
+	return 0;
+}
+
+static void do_board_detect(void)
+{
+	u16 gpio_in_reg;
+
+	/* Set MDIO and MDC */
+	mscc_gpio_set_alternate(9, 2);
+	mscc_gpio_set_alternate(10, 2);
+
+	/* Set GPIO page */
+	mscc_phy_wr(1, 16, 31, 0x10);
+	if (!mscc_phy_rd(1, 16, 15, &gpio_in_reg)) {
+		if (gpio_in_reg & 0x200)
+			gd->board_type = BOARD_TYPE_PCB106;
+		else
+			gd->board_type = BOARD_TYPE_PCB105;
+	} else {
+		gd->board_type = BOARD_TYPE_PCB105;
+	}
+	mscc_phy_wr(1, 16, 31, 0x0);
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	if (gd->board_type == BOARD_TYPE_PCB106 &&
+	    strcmp(name, "serval_pcb106") == 0)
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_PCB105 &&
+	    strcmp(name, "serval_pcb105") == 0)
+		return 0;
+
+	return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+	do_board_detect();
+	fdtdec_setup();
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/mscc/servalt/Kconfig b/roms/u-boot/board/mscc/servalt/Kconfig
new file mode 100644
index 000000000..61140f89b
--- /dev/null
+++ b/roms/u-boot/board/mscc/servalt/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+	default "mscc"
+
+if SOC_SERVALT
+
+config SYS_BOARD
+	default "servalt"
+
+config SYS_CONFIG_NAME
+	default "servalt"
+
+endif
diff --git a/roms/u-boot/board/mscc/servalt/Makefile b/roms/u-boot/board/mscc/servalt/Makefile
new file mode 100644
index 000000000..9a37eeaba
--- /dev/null
+++ b/roms/u-boot/board/mscc/servalt/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_SERVALT)	:= servalt.o
diff --git a/roms/u-boot/board/mscc/servalt/servalt.c b/roms/u-boot/board/mscc/servalt/servalt.c
new file mode 100644
index 000000000..252d8e315
--- /dev/null
+++ b/roms/u-boot/board/mscc/servalt/servalt.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <led.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	BOARD_TYPE_PCB116 = 0xAABBCE00,
+};
+
+int board_early_init_r(void)
+{
+	/* Prepare SPI controller to be used in master mode */
+	writel(0, BASE_CFG + ICPU_SW_MODE);
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	return 0;
+}
+
+static void do_board_detect(void)
+{
+	gd->board_type = BOARD_TYPE_PCB116; /* ServalT */
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	if (gd->board_type == BOARD_TYPE_PCB116 &&
+	    strcmp(name, "servalt_pcb116") == 0)
+		return 0;
+	return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+	do_board_detect();
+	fdtdec_setup();
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/myir/mys_6ulx/Kconfig b/roms/u-boot/board/myir/mys_6ulx/Kconfig
new file mode 100644
index 000000000..cbf72c6ec
--- /dev/null
+++ b/roms/u-boot/board/myir/mys_6ulx/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MYS_6ULX
+
+config SYS_BOARD
+	default "mys_6ulx"
+
+config SYS_VENDOR
+	default "myir"
+
+config SYS_CONFIG_NAME
+	default "mys_6ulx"
+
+endif
diff --git a/roms/u-boot/board/myir/mys_6ulx/MAINTAINERS b/roms/u-boot/board/myir/mys_6ulx/MAINTAINERS
new file mode 100644
index 000000000..d4ee66118
--- /dev/null
+++ b/roms/u-boot/board/myir/mys_6ulx/MAINTAINERS
@@ -0,0 +1,9 @@
+MYS_6ULX BOARD
+M:	Parthiban Nallathambi <parthiban@linumiz.com>
+S:	Maintained
+F:	arch/arm/dts/imx6ull-myir-mys-6ulx-nand.dts
+F:	arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi
+F:	arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi
+F:	board/myir/mys_6ulx/
+F:	configs/myir_mys_6ulx_defconfig
+F:	include/configs/mys_6ulx.h
diff --git a/roms/u-boot/board/myir/mys_6ulx/Makefile b/roms/u-boot/board/myir/mys_6ulx/Makefile
new file mode 100644
index 000000000..3c63e439a
--- /dev/null
+++ b/roms/u-boot/board/myir/mys_6ulx/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y  := mys_6ulx.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/roms/u-boot/board/myir/mys_6ulx/README b/roms/u-boot/board/myir/mys_6ulx/README
new file mode 100644
index 000000000..a0996659c
--- /dev/null
+++ b/roms/u-boot/board/myir/mys_6ulx/README
@@ -0,0 +1,52 @@
+How to use U-Boot on MYiR MYS-6ULX Single Board Computer
+--------------------------------------------------------
+
+- Configure and build U-Boot for MYS-6ULX iMX6ULL:
+
+    $ make mrproper
+    $ make myir_mys_6ulx_defconfig
+    $ make
+
+  This will generate SPL and u-boot-dtb.img images.
+
+Boot from MMC/SD:
+- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card:
+
+    $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+    $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Boot mode settings:
+
+  Boot switch position: SW1 -> 0
+			SW2 -> 1
+			SW3 -> 0
+			SW4 -> 1
+
+Boot from NAND:
+- Boot the board using SD/MMC or Serial download and load the SPL into memory
+either from SD/MMC or TFTP.
+
+Default MTD layout is 512k(spl),1m(uboot),1m(uboot-dup),-(ubi)
+
+Flash SPL to NAND from SD/MMC,
+
+    $ ext4load mmc 0:2 $loadaddr SPL
+    $ nand erase.part spl
+    $ nandbcb init $loadaddr 0x0 $filesize
+
+Flash u-boot proper to NAND from SD/MMC,
+
+    $ ext4load mmc 0:2 $loadaddr u-boot-dtb.img
+    $ nand erase.part uboot
+    $ nand write $loadaddr uboot $filesize
+
+- Boot mode settings:
+
+  Boot switch position: SW1 -> 1
+			SW2 -> 0
+			SW3 -> 0
+			SW4 -> 1
+
+- Connect the Serial cable to UART0 and the PC for the console.
+
+- Reset the board using and U-Boot should boot from NAND.
diff --git a/roms/u-boot/board/myir/mys_6ulx/mys_6ulx.c b/roms/u-boot/board/myir/mys_6ulx/mys_6ulx.c
new file mode 100644
index 000000000..847497bcb
--- /dev/null
+++ b/roms/u-boot/board/myir/mys_6ulx/mys_6ulx.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Linumiz
+ * Author: Parthiban Nallathambi <parthiban@linumiz.com>
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/bitops.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE         | PAD_CTL_PUE       | \
+			PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | \
+			PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart5_pads[] = {
+	MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+}
+
+#ifdef CONFIG_FEC_MXC
+
+static int setup_fec(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	/*
+	 * Use 50M anatop loopback REF_CLK1 for ENET1,
+	 * clear gpr1[13], set gpr1[17].
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/*
+	 * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
+	 * 50 MHz RMII clock mode.
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif /* CONFIG_FEC_MXC */
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	u32 cpurev = get_cpu_rev();
+
+	printf("Board: MYiR MYS-6ULX %s Single Board Computer\n",
+	       get_imx_type((cpurev & 0xFF000) >> 12));
+
+	return 0;
+}
diff --git a/roms/u-boot/board/myir/mys_6ulx/spl.c b/roms/u-boot/board/myir/mys_6ulx/spl.c
new file mode 100644
index 000000000..5cd4d0528
--- /dev/null
+++ b/roms/u-boot/board/myir/mys_6ulx/spl.c
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Linumiz
+ * Author: Parthiban Nallathambi <parthiban@linumiz.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <fsl_esdhc_imx.h>
+
+/* Configuration for Micron MT41K128M16JT-125, 32M x 16 x 8 -> 256MiB */
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x41480148,
+	.p0_mprddlctl = 0x40403E42,
+	.p0_mpwrdlctl = 0x40405852,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,		/* Bus size = 16bit */
+	.cs_density = 32,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 1,
+	.rtt_nom = 1,
+	.walat = 1,		/* Write additional latency */
+	.ralat = 5,		/* Read additional latency */
+	.mif3_mode = 3,		/* Command prediction working mode */
+	.bi_on = 1,		/* Bank interleaving enabled */
+	.pd_fast_exit = 1,
+	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 1,		/* Refresh cycles at 32KHz */
+	.refr = 7,		/* 8 refresh commands per refresh cycle */
+};
+
+/* MT41K128M16JT-125 (2Gb density) */
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE         | PAD_CTL_PUE       | \
+			PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW | \
+			PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | \
+			PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifndef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_NAND_RE_B__USDHC2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+	{
+		.esdhc_base = USDHC1_BASE_ADDR,
+		.max_bus_width = 4,
+	},
+#ifndef CONFIG_NAND_MXS
+	{
+		.esdhc_base = USDHC2_BASE_ADDR,
+		.max_bus_width = 8,
+	},
+#endif
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+#ifndef CONFIG_NAND_MXS
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+#endif
+		default:
+			printf("Warning - USDHC%d controller not supporting\n",
+			       i + 1);
+			return 0;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* Setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* Setup iomux and fec */
+	board_early_init_f();
+
+	/* Setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
diff --git a/roms/u-boot/board/netgear/cg3100d/Kconfig b/roms/u-boot/board/netgear/cg3100d/Kconfig
new file mode 100644
index 000000000..632c22d1f
--- /dev/null
+++ b/roms/u-boot/board/netgear/cg3100d/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_NETGEAR_CG3100D
+
+config SYS_BOARD
+	default "cg3100d"
+
+config SYS_VENDOR
+	default "netgear"
+
+config SYS_CONFIG_NAME
+	default "netgear_cg3100d"
+
+endif
diff --git a/roms/u-boot/board/netgear/cg3100d/MAINTAINERS b/roms/u-boot/board/netgear/cg3100d/MAINTAINERS
new file mode 100644
index 000000000..f1dcb1f62
--- /dev/null
+++ b/roms/u-boot/board/netgear/cg3100d/MAINTAINERS
@@ -0,0 +1,6 @@
+NETGEAR CG3100D BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/netgear/cg3100d/
+F:	include/configs/netgear_cg3100d.h
+F:	configs/netgear_cg3100d_ram_defconfig
diff --git a/roms/u-boot/board/netgear/cg3100d/Makefile b/roms/u-boot/board/netgear/cg3100d/Makefile
new file mode 100644
index 000000000..3e05bb55c
--- /dev/null
+++ b/roms/u-boot/board/netgear/cg3100d/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += cg3100d.o
diff --git a/roms/u-boot/board/netgear/cg3100d/cg3100d.c b/roms/u-boot/board/netgear/cg3100d/cg3100d.c
new file mode 100644
index 000000000..1e4b7281d
--- /dev/null
+++ b/roms/u-boot/board/netgear/cg3100d/cg3100d.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/netgear/dgnd3700v2/Kconfig b/roms/u-boot/board/netgear/dgnd3700v2/Kconfig
new file mode 100644
index 000000000..11af18878
--- /dev/null
+++ b/roms/u-boot/board/netgear/dgnd3700v2/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_NETGEAR_DGND3700V2
+
+config SYS_BOARD
+	default "dgnd3700v2"
+
+config SYS_VENDOR
+	default "netgear"
+
+config SYS_CONFIG_NAME
+	default "netgear_dgnd3700v2"
+
+endif
diff --git a/roms/u-boot/board/netgear/dgnd3700v2/MAINTAINERS b/roms/u-boot/board/netgear/dgnd3700v2/MAINTAINERS
new file mode 100644
index 000000000..aaa51c177
--- /dev/null
+++ b/roms/u-boot/board/netgear/dgnd3700v2/MAINTAINERS
@@ -0,0 +1,6 @@
+NETGEAR DGND3700V2 BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/netgear/dgnd3700v2/
+F:	include/configs/netgear_dgnd3700v2.h
+F:	configs/netgear_dgnd3700v2_ram_defconfig
diff --git a/roms/u-boot/board/netgear/dgnd3700v2/Makefile b/roms/u-boot/board/netgear/dgnd3700v2/Makefile
new file mode 100644
index 000000000..525f8ecdf
--- /dev/null
+++ b/roms/u-boot/board/netgear/dgnd3700v2/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += dgnd3700v2.o
diff --git a/roms/u-boot/board/netgear/dgnd3700v2/dgnd3700v2.c b/roms/u-boot/board/netgear/dgnd3700v2/dgnd3700v2.c
new file mode 100644
index 000000000..cfc3529c3
--- /dev/null
+++ b/roms/u-boot/board/netgear/dgnd3700v2/dgnd3700v2.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+#define GPIO_BASE_6362			0x10000080
+
+#define GPIO_MODE_6362_REG		0x18
+#define GPIO_MODE_6362_SERIAL_LED_DATA	BIT(2)
+#define GPIO_MODE_6362_SERIAL_LED_CLK	BIT(3)
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	void __iomem *gpio_regs = map_physmem(GPIO_BASE_6362, 0, MAP_NOCACHE);
+
+	/* Enable Serial LEDs */
+	setbits_be32(gpio_regs + GPIO_MODE_6362_REG,
+		     GPIO_MODE_6362_SERIAL_LED_DATA |
+		     GPIO_MODE_6362_SERIAL_LED_CLK);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/nokia/rx51/Kconfig b/roms/u-boot/board/nokia/rx51/Kconfig
new file mode 100644
index 000000000..ec6a571a2
--- /dev/null
+++ b/roms/u-boot/board/nokia/rx51/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NOKIA_RX51
+
+config SYS_BOARD
+	default "rx51"
+
+config SYS_VENDOR
+	default "nokia"
+
+config SYS_CONFIG_NAME
+	default "nokia_rx51"
+
+endif
diff --git a/roms/u-boot/board/nokia/rx51/MAINTAINERS b/roms/u-boot/board/nokia/rx51/MAINTAINERS
new file mode 100644
index 000000000..58b16bf9a
--- /dev/null
+++ b/roms/u-boot/board/nokia/rx51/MAINTAINERS
@@ -0,0 +1,8 @@
+RX51 BOARD
+M:	Pali Rohár <pali@kernel.org>
+S:	Maintained
+F:	board/nokia/rx51/
+F:	include/configs/nokia_rx51.h
+F:	configs/nokia_rx51_defconfig
+F:	doc/README.nokia_rx51
+F:	test/nokia_rx51_test.sh
diff --git a/roms/u-boot/board/nokia/rx51/Makefile b/roms/u-boot/board/nokia/rx51/Makefile
new file mode 100644
index 000000000..842f9e6a6
--- /dev/null
+++ b/roms/u-boot/board/nokia/rx51/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y := rx51.o
+obj-y += lowlevel_init.o
diff --git a/roms/u-boot/board/nokia/rx51/lowlevel_init.S b/roms/u-boot/board/nokia/rx51/lowlevel_init.S
new file mode 100644
index 000000000..1466d976f
--- /dev/null
+++ b/roms/u-boot/board/nokia/rx51/lowlevel_init.S
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali@kernel.org>
+ */
+
+#include <config.h>
+
+relocaddr:		/* address of this relocaddr section after coping */
+	.word .		/* address of section (calculated at compile time) */
+
+startaddr:		/* address of u-boot after copying */
+	.word CONFIG_SYS_TEXT_BASE
+
+kernaddr:		/* address of kernel after copying */
+	.word KERNEL_ADDRESS
+
+kernsize:		/* maximal size of kernel image */
+	.word KERNEL_MAXSIZE
+
+kernoffs:		/* offset of kernel image in loaded u-boot */
+	.word KERNEL_OFFSET
+
+imagesize:		/* maximal size of image */
+	.word IMAGE_MAXSIZE
+
+ih_magic:		/* IH_MAGIC in big endian from include/image.h */
+	.word 0x56190527
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: Copy attached kernel to address KERNEL_ADDRESS
+ *              Copy u-boot to address CONFIG_SYS_TEXT_BASE
+ *              Return to copied u-boot address
+ */
+
+.global save_boot_params
+save_boot_params:
+	/* Get return address */
+	ldr	lr, =save_boot_params_ret
+
+/* Copy valid attached kernel to address KERNEL_ADDRESS */
+
+copy_kernel_start:
+	adr	r0, relocaddr	/* r0 - address of section relocaddr */
+	ldr	r1, relocaddr	/* r1 - address of relocaddr after relocation */
+	cmp	r0, r1
+
+	/* r4 - calculated offset */
+	subhi	r4, r0, r1
+	sublo	r4, r1, r0
+
+	/* r0 - start of kernel before */
+	ldr	r0, startaddr
+	addhi	r0, r0, r4
+	sublo	r0, r0, r4
+	ldr	r1, kernoffs
+	add	r0, r0, r1
+
+	/* r3 - start of kernel after */
+	ldr	r3, kernaddr
+
+	/* r2 - end of kernel after */
+	ldr	r1, kernsize
+	add	r2, r3, r1
+
+	/* r1 - end of kernel before */
+	add	r1, r0, r1
+
+	/* remove header in target kernel */
+	mov	r5, #0
+	str	r5, [r3]
+
+	/* check for valid kernel uImage */
+	ldr	r4, [r0]	/* r4 - 4 bytes header of kernel */
+	ldr	r5, ih_magic	/* r5 - IH_MAGIC */
+	cmp	r4, r5
+	bne	copy_kernel_end	/* skip if invalid image */
+
+copy_kernel_loop:
+	ldmdb	r1!, {r3 - r10}
+	stmdb	r2!, {r3 - r10}
+	cmp	r1, r0
+	bhi	copy_kernel_loop
+
+copy_kernel_end:
+	mov	r5, #0
+	str	r5, [r0]	/* remove 4 bytes header of kernel */
+
+
+/* Fix u-boot code */
+
+fix_start:
+	adr	r0, relocaddr	/* r0 - address of section relocaddr */
+	ldr	r1, relocaddr	/* r1 - address of relocaddr after relocation */
+	cmp	r0, r1
+
+	beq	copy_uboot_end	/* skip if u-boot is on correct address */
+
+	/* r5 - calculated offset */
+	subhi	r5, r0, r1
+	sublo	r5, r1, r0
+
+	/* r6 - maximal u-boot size */
+	ldr	r6, imagesize
+
+	/* r1 - start of u-boot after */
+	ldr	r1, startaddr
+
+	/* r0 - start of u-boot before */
+	addhi	r0, r1, r5
+	sublo	r0, r1, r5
+
+	/* check if we need to move uboot copy code before calling it */
+	cmp	r5, r6
+	bhi	copy_uboot_start /* now coping u-boot code directly is safe */
+
+
+copy_code_start:
+	/* r0 - start of u-boot before */
+	/* r1 - start of u-boot after */
+	/* r6 - maximal u-boot size */
+
+	/* r7 - maximal kernel size */
+	ldr	r7, kernsize
+
+	/* r4 - end of kernel before */
+	add	r4, r0, r6
+	add	r4, r4, r7
+
+	/* r5 - end of u-boot after */
+	ldr	r5, startaddr
+	add	r5, r5, r6
+
+	/* r2 - start of loop code after */
+	cmp	r4, r5		/* higher address (r4 or r5) */
+	movhs	r2, r4
+	movlo	r2, r5
+
+	/* r3 - end of loop code before */
+	adr	r3, end
+
+	/* r4 - end of loop code after */
+	adr	r4, copy_uboot_start
+	sub	r4, r3, r4
+	add	r4, r2, r4
+
+copy_code_loop:
+	ldmdb	r3!, {r7 - r10}
+	stmdb	r4!, {r7 - r10}
+	cmp	r4, r2
+	bhi	copy_code_loop
+
+copy_code_end:
+	mov	pc, r2
+
+
+/*
+ * Copy u-boot to address CONFIG_SYS_TEXT_BASE
+ *
+ * Nokia X-Loader loading secondary image to address 0x80400000
+ * NOLO loading boot image to random place, so it doesn't really
+ * matter what is set in CONFIG_SYS_TEXT_BASE. We have to copy
+ * u-boot to CONFIG_SYS_TEXT_BASE address.
+ */
+
+copy_uboot_start:
+	/* r0 - start of u-boot before */
+	/* r1 - start of u-boot after */
+	/* r6 - maximal u-boot size */
+
+	/* r2 - end of u-boot after */
+	add	r2, r1, r6
+
+	/* condition for copying from left to right */
+	cmp	r0, r1
+	addlo	r1, r0, r6	/* r1 - end of u-boot before */
+	blo	copy_uboot_loop_right
+
+copy_uboot_loop_left:
+	ldmia	r0!, {r3 - r10}
+	stmia	r1!, {r3 - r10}
+	cmp	r1, r2
+	blo	copy_uboot_loop_left
+	b	copy_uboot_end
+
+copy_uboot_loop_right:
+	ldmdb	r1!, {r3 - r10}
+	stmdb	r2!, {r3 - r10}
+	cmp	r1, r0
+	bhi	copy_uboot_loop_right
+
+copy_uboot_end:
+	bx	lr
+
+end:
diff --git a/roms/u-boot/board/nokia/rx51/rx51.c b/roms/u-boot/board/nokia/rx51/rx51.c
new file mode 100644
index 000000000..7bd5fbd71
--- /dev/null
+++ b/roms/u-boot/board/nokia/rx51/rx51.c
@@ -0,0 +1,724 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012
+ * Ивайло Димитров <freemangordon@abv.bg>
+ *
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali@kernel.org>
+ *
+ * (C) Copyright 2010
+ * Alistair Buxton <a.j.buxton@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code:
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <watchdog.h>
+#include <malloc.h>
+#include <twl4030.h>
+#include <i2c.h>
+#include <video_fb.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/bitops.h>
+#include <asm/mach-types.h>
+#include <asm/omap_i2c.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+
+#include "tag_omap.h"
+
+/* Needed for ROM SMC call */
+struct emu_hal_params_rx51 {
+	u32 num_params;
+	u32 param1;
+	u32 param2;
+	u32 param3;
+	u32 param4;
+};
+
+#define ONENAND_GPMC_CONFIG1_RX51	0xfb001202
+#define ONENAND_GPMC_CONFIG2_RX51	0x00111100
+#define ONENAND_GPMC_CONFIG3_RX51	0x00020200
+#define ONENAND_GPMC_CONFIG4_RX51	0x11001102
+#define ONENAND_GPMC_CONFIG5_RX51	0x03101616
+#define ONENAND_GPMC_CONFIG6_RX51	0x90060000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+GraphicDevice gdev;
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"Nokia RX-51",
+	"OneNAND"
+};
+
+/* This structure contains default omap tags needed for booting Maemo 5 */
+static struct tag_omap omap[] = {
+	OMAP_TAG_UART_CONFIG(0x04),
+	OMAP_TAG_SERIAL_CONSOLE_CONFIG(0x03, 0x01C200),
+	OMAP_TAG_LCD_CONFIG("acx565akm", "internal", 90, 0x18),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cam_focus", 0x44, 0x1, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cam_launch", 0x45, 0x1, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cam_shutter", 0x6e, 0x1, 0x0, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_apeslpx", 0x46, 0x2, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_bsi", 0x9d, 0x2, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_en", 0x4a, 0x2, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst", 0x4b, 0x6, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst_rq", 0x49, 0x6, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_wddis", 0x0d, 0x2, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("headphone", 0xb1, 0x1, 0x1, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("kb_lock", 0x71, 0x1, 0x0, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("proximity", 0x59, 0x0, 0x0, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("sleep_ind", 0xa2, 0x2, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("slide", GPIO_SLIDE, 0x0, 0x0, 0x0),
+	OMAP_TAG_WLAN_CX3110X_CONFIG(0x25, 0xff, 87, 42, -1),
+	OMAP_TAG_PARTITION_CONFIG("bootloader", 128 * 1024, 0x00000000, 0x00000003),
+	OMAP_TAG_PARTITION_CONFIG("config", 384 * 1024, 0x00020000, 0x00000000),
+	OMAP_TAG_PARTITION_CONFIG("log", 256 * 1024, 0x00080000, 0x00000000),
+	OMAP_TAG_PARTITION_CONFIG("kernel", 2 * 1024*1024, 0x000c0000, 0x00000000),
+	OMAP_TAG_PARTITION_CONFIG("initfs", 2 * 1024*1024, 0x002c0000, 0x00000000),
+	OMAP_TAG_PARTITION_CONFIG("rootfs", 257280 * 1024, 0x004c0000, 0x00000000),
+	OMAP_TAG_BOOT_REASON_CONFIG("pwr_key"),
+	OMAP_TAG_VERSION_STR_CONFIG("product", "RX-51"),
+	OMAP_TAG_VERSION_STR_CONFIG("hw-build", "2101"),
+	OMAP_TAG_VERSION_STR_CONFIG("nolo", "1.4.14"),
+	OMAP_TAG_VERSION_STR_CONFIG("boot-mode", "normal"),
+	{ }
+};
+
+static char *boot_reason_ptr;
+static char *hw_build_ptr;
+static char *nolo_version_ptr;
+static char *boot_mode_ptr;
+static int serial_was_console_enabled;
+
+/*
+ * Routine: init_omap_tags
+ * Description: Initialize pointers to values in tag_omap
+ */
+static void init_omap_tags(void)
+{
+	char *component;
+	char *version;
+	int i = 0;
+	while (omap[i].hdr.tag) {
+		switch (omap[i].hdr.tag) {
+		case OMAP_TAG_BOOT_REASON:
+			boot_reason_ptr = omap[i].u.boot_reason.reason_str;
+			break;
+		case OMAP_TAG_VERSION_STR:
+			component = omap[i].u.version.component;
+			version = omap[i].u.version.version;
+			if (strcmp(component, "hw-build") == 0)
+				hw_build_ptr = version;
+			else if (strcmp(component, "nolo") == 0)
+				nolo_version_ptr = version;
+			else if (strcmp(component, "boot-mode") == 0)
+				boot_mode_ptr = version;
+			break;
+		default:
+			break;
+		}
+		i++;
+	}
+}
+
+static void reuse_omap_atags(struct tag_omap *t)
+{
+	char *component;
+	char *version;
+	while (t->hdr.tag) {
+		switch (t->hdr.tag) {
+		case OMAP_TAG_BOOT_REASON:
+			memset(boot_reason_ptr, 0, 12);
+			strcpy(boot_reason_ptr, t->u.boot_reason.reason_str);
+			break;
+		case OMAP_TAG_VERSION_STR:
+			component = t->u.version.component;
+			version = t->u.version.version;
+			if (strcmp(component, "hw-build") == 0) {
+				memset(hw_build_ptr, 0, 12);
+				strcpy(hw_build_ptr, version);
+			} else if (strcmp(component, "nolo") == 0) {
+				memset(nolo_version_ptr, 0, 12);
+				strcpy(nolo_version_ptr, version);
+			} else if (strcmp(component, "boot-mode") == 0) {
+				memset(boot_mode_ptr, 0, 12);
+				strcpy(boot_mode_ptr, version);
+			}
+			break;
+		case OMAP_TAG_UART:
+			if (t->u.uart.enabled_uarts)
+				serial_was_console_enabled = 1;
+			break;
+		case OMAP_TAG_SERIAL_CONSOLE:
+			serial_was_console_enabled = 1;
+			break;
+		default:
+			break;
+		}
+		t = tag_omap_next(t);
+	}
+}
+
+/*
+ * Routine: reuse_atags
+ * Description: Reuse atags from previous bootloader.
+ *              Reuse only only HW build, boot reason, boot mode and nolo
+ */
+static void reuse_atags(void)
+{
+	struct tag *t = (struct tag *)gd->bd->bi_boot_params;
+
+	/* First tag must be ATAG_CORE */
+	if (t->hdr.tag != ATAG_CORE)
+		return;
+
+	if (!boot_reason_ptr || !hw_build_ptr)
+		return;
+
+	/* Last tag must be ATAG_NONE */
+	while (t->hdr.tag != ATAG_NONE) {
+		switch (t->hdr.tag) {
+		case ATAG_REVISION:
+			memset(hw_build_ptr, 0, 12);
+			sprintf(hw_build_ptr, "%x", t->u.revision.rev);
+			break;
+		case ATAG_BOARD:
+			reuse_omap_atags((struct tag_omap *)&t->u);
+			break;
+		default:
+			break;
+		}
+		t = tag_next(t);
+	}
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_CMD_ONENAND)
+	const u32 gpmc_regs_onenandrx51[GPMC_MAX_REG] = {
+		ONENAND_GPMC_CONFIG1_RX51,
+		ONENAND_GPMC_CONFIG2_RX51,
+		ONENAND_GPMC_CONFIG3_RX51,
+		ONENAND_GPMC_CONFIG4_RX51,
+		ONENAND_GPMC_CONFIG5_RX51,
+		ONENAND_GPMC_CONFIG6_RX51,
+		0
+	};
+#endif
+	/* in SRAM or SDRAM, finish GPMC */
+	gpmc_init();
+#if defined(CONFIG_CMD_ONENAND)
+	enable_gpmc_cs_config(gpmc_regs_onenandrx51, &gpmc_cfg->cs[0],
+			      CONFIG_SYS_ONENAND_BASE, GPMC_SIZE_256M);
+#endif
+	/* Enable the clks & power */
+	per_clocks_enable();
+	/* boot param addr */
+	gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
+	return 0;
+}
+
+/*
+ * Routine: get_board_revision
+ * Description: Return board revision.
+ */
+u32 get_board_rev(void)
+{
+	return simple_strtol(hw_build_ptr, NULL, 16);
+}
+
+/*
+ * Routine: setup_board_tags
+ * Description: Append board specific boot tags.
+ */
+void setup_board_tags(struct tag **in_params)
+{
+	int setup_console_atag;
+	char *setup_boot_reason_atag;
+	char *setup_boot_mode_atag;
+	char *str;
+	int i;
+	int size;
+	int total_size;
+	struct tag *params;
+	struct tag_omap *t;
+
+	params = (struct tag *)gd->bd->bi_boot_params;
+
+	params->u.core.flags = 0x0;
+	params->u.core.pagesize = 0x1000;
+	params->u.core.rootdev = 0x0;
+
+	/* append omap atag only if env setup_omap_atag is set to 1 */
+	str = env_get("setup_omap_atag");
+	if (!str || str[0] != '1')
+		return;
+
+	str = env_get("setup_console_atag");
+	if (str && str[0]) {
+		if (str[0] == '1')
+			setup_console_atag = 1;
+		else
+			setup_console_atag = 0;
+	} else {
+		if (serial_was_console_enabled)
+			setup_console_atag = 1;
+		else
+			setup_console_atag = 0;
+	}
+
+	setup_boot_reason_atag = env_get("setup_boot_reason_atag");
+	setup_boot_mode_atag = env_get("setup_boot_mode_atag");
+
+	params = *in_params;
+	t = (struct tag_omap *)&params->u;
+	total_size = sizeof(struct tag_header);
+
+	for (i = 0; omap[i].hdr.tag; i++) {
+
+		/* skip serial console tag */
+		if (!setup_console_atag &&
+			omap[i].hdr.tag == OMAP_TAG_SERIAL_CONSOLE)
+			continue;
+
+		size = omap[i].hdr.size + sizeof(struct tag_omap_header);
+		memcpy(t, &omap[i], size);
+
+		/* set uart tag to 0 - disable serial console */
+		if (!setup_console_atag && omap[i].hdr.tag == OMAP_TAG_UART)
+			t->u.uart.enabled_uarts = 0;
+
+		/* change boot reason */
+		if (setup_boot_reason_atag &&
+			omap[i].hdr.tag == OMAP_TAG_BOOT_REASON) {
+			memset(t->u.boot_reason.reason_str, 0, 12);
+			strcpy(t->u.boot_reason.reason_str,
+				setup_boot_reason_atag);
+		}
+
+		/* change boot mode */
+		if (setup_boot_mode_atag &&
+			omap[i].hdr.tag == OMAP_TAG_VERSION_STR &&
+			strcmp(omap[i].u.version.component, "boot-mode") == 0) {
+			memset(t->u.version.version, 0, 12);
+			strcpy(t->u.version.version, setup_boot_mode_atag);
+		}
+
+		total_size += size;
+		t = tag_omap_next(t);
+
+	}
+
+	params->hdr.tag = ATAG_BOARD;
+	params->hdr.size = total_size >> 2;
+	params = tag_next(params);
+
+	*in_params = params;
+}
+
+/*
+ * Routine: video_hw_init
+ * Description: Set up the GraphicDevice depending on sys_boot.
+ */
+void *video_hw_init(void)
+{
+	/* fill in Graphic Device */
+	gdev.frameAdrs = 0x8f9c0000;
+	gdev.winSizeX = 800;
+	gdev.winSizeY = 480;
+	gdev.gdfBytesPP = 2;
+	gdev.gdfIndex = GDF_16BIT_565RGB;
+	memset((void *)gdev.frameAdrs, 0, 0xbb800);
+	return (void *) &gdev;
+}
+
+/*
+ * Routine: twl4030_regulator_set_mode
+ * Description: Set twl4030 regulator mode over i2c powerbus.
+ */
+static void twl4030_regulator_set_mode(u8 id, u8 mode)
+{
+	u16 msg = MSG_SINGULAR(DEV_GRP_P1, id, mode);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PB_WORD_MSB, msg >> 8);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PB_WORD_LSB, msg & 0xff);
+}
+
+static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
+{
+	u32 i, num_params = *parameters;
+	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
+
+	/*
+	 * copy the parameters to an un-cached area to avoid coherency
+	 * issues
+	 */
+	for (i = 0; i < num_params; i++) {
+		__raw_writel(*parameters, sram_scratch_space);
+		parameters++;
+		sram_scratch_space++;
+	}
+
+	/* Now make the PPA call */
+	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
+}
+
+void omap3_set_aux_cr_secure(u32 acr)
+{
+	struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+
+	emu_romcode_params.num_params = 2;
+	emu_romcode_params.param1 = acr;
+
+	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+			       (u32 *)&emu_romcode_params);
+}
+
+/*
+ * Routine: omap3_update_aux_cr_secure_rx51
+ * Description: Modify the contents Auxiliary Control Register.
+ * Parameters:
+ *   set_bits - bits to set in ACR
+ *   clr_bits - bits to clear in ACR
+ */
+static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
+{
+	u32 acr;
+
+	/* Read ACR */
+	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+	acr &= ~clear_bits;
+	acr |= set_bits;
+	omap3_set_aux_cr_secure(acr);
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts.
+ */
+int misc_init_r(void)
+{
+	struct udevice *dev;
+	char buf[12];
+	u8 state;
+
+	/* disable lp5523 led */
+	if (i2c_get_chip_for_busnum(1, 0x32, 1, &dev) == 0)
+		dm_i2c_reg_write(dev, 0x00, 0x00);
+
+	/* initialize twl4030 power managment */
+	twl4030_power_init();
+	twl4030_power_mmc_init(0);
+	twl4030_power_mmc_init(1);
+
+	/* set VSIM to 1.8V */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
+				TWL4030_PM_RECEIVER_VSIM_VSEL_18,
+				TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
+				TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+	/* store I2C access state */
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+			    &state);
+
+	/* enable I2C access to powerbus (needed for twl4030 regulator) */
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+			     0x02);
+
+	/* set VAUX3, VSIM and VMMC1 state to active - enable eMMC memory */
+	twl4030_regulator_set_mode(RES_VAUX3, RES_STATE_ACTIVE);
+	twl4030_regulator_set_mode(RES_VSIM, RES_STATE_ACTIVE);
+	twl4030_regulator_set_mode(RES_VMMC1, RES_STATE_ACTIVE);
+
+	/* restore I2C access state */
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+			     state);
+
+	/* set env variable attkernaddr for relocated kernel */
+	sprintf(buf, "%#x", KERNEL_ADDRESS);
+	env_set("attkernaddr", buf);
+
+	/* initialize omap tags */
+	init_omap_tags();
+
+	/* reuse atags from previous bootloader */
+	reuse_atags();
+
+	omap_die_id_display();
+	print_cpuinfo();
+
+	/*
+	 * Cortex-A8(r1p0..r1p2) errata 430973 workaround
+	 * Set IBE bit in Auxiliary Control Register
+	 *
+	 * Call this routine only on real secure device
+	 * Qemu does not implement secure PPA and crash
+	 */
+	if (get_device_type() == HS_DEVICE)
+		omap3_update_aux_cr_secure_rx51(1 << 6, 0);
+
+	return 0;
+}
+
+static unsigned long int twl_wd_time; /* last time of watchdog reset */
+static unsigned long int twl_i2c_lock;
+
+/*
+ * Routine: hw_watchdog_reset
+ * Description: Reset timeout of twl4030 watchdog.
+ */
+void hw_watchdog_reset(void)
+{
+	u8 timeout = 0;
+
+	/* do not reset watchdog too often - max every 4s */
+	if (get_timer(twl_wd_time) < 4 * CONFIG_SYS_HZ)
+		return;
+
+	/* localy lock twl4030 i2c bus */
+	if (test_and_set_bit(0, &twl_i2c_lock))
+		return;
+
+	/* read actual watchdog timeout */
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER,
+			    TWL4030_PM_RECEIVER_WATCHDOG_CFG, &timeout);
+
+	/* timeout 0 means watchdog is disabled */
+	/* reset watchdog timeout to 31s (maximum) */
+	if (timeout != 0)
+		twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+				     TWL4030_PM_RECEIVER_WATCHDOG_CFG, 31);
+
+	/* store last watchdog reset time */
+	twl_wd_time = get_timer(0);
+
+	/* localy unlock twl4030 i2c bus */
+	test_and_clear_bit(0, &twl_i2c_lock);
+}
+
+/*
+ * TWL4030 keypad handler for cfb_console
+ */
+
+static const char keymap[] = {
+	/* normal */
+	'q',  'o',  'p',  ',', '\b',    0,  'a',  's',
+	'w',  'd',  'f',  'g',  'h',  'j',  'k',  'l',
+	'e',  '.',    0,  '\r',   0,  'z',  'x',  'c',
+	'r',  'v',  'b',  'n',  'm',  ' ',  ' ',    0,
+	't',    0,    0,    0,    0,    0,    0,    0,
+	'y',    0,    0,    0,    0,    0,    0,    0,
+	'u',    0,    0,    0,    0,    0,    0,    0,
+	'i',    5,    6,    0,    0,    0,    0,    0,
+	/* fn */
+	'1',  '9',  '0',  '=', '\b',    0,  '*',  '+',
+	'2',  '#',  '-',  '_',  '(',  ')',  '&',  '!',
+	'3',  '?',  '^', '\r',    0,  156,  '$',  238,
+	'4',  '/', '\\',  '"', '\'',  '@',    0,  '<',
+	'5',  '|',  '>',    0,    0,    0,    0,    0,
+	'6',    0,    0,    0,    0,    0,    0,    0,
+	'7',    0,    0,    0,    0,    0,    0,    0,
+	'8',   16,   17,    0,    0,    0,    0,    0,
+};
+
+static u8 keys[8];
+static u8 old_keys[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+#define KEYBUF_SIZE 32
+static u8 keybuf[KEYBUF_SIZE];
+static u8 keybuf_head;
+static u8 keybuf_tail;
+
+/*
+ * Routine: rx51_kp_init
+ * Description: Initialize HW keyboard.
+ */
+int rx51_kp_init(void)
+{
+	int ret = 0;
+	u8 ctrl;
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+				  TWL4030_KEYPAD_KEYP_CTRL_REG, &ctrl);
+
+	if (ret)
+		return ret;
+
+	/* turn on keyboard and use hardware scanning */
+	ctrl |= TWL4030_KEYPAD_CTRL_KBD_ON;
+	ctrl |= TWL4030_KEYPAD_CTRL_SOFT_NRST;
+	ctrl |= TWL4030_KEYPAD_CTRL_SOFTMODEN;
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_CTRL_REG, ctrl);
+	/* enable key event status */
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_IMR1, 0xfe);
+	/* enable interrupt generation on rising and falling */
+	/* this is a workaround for qemu twl4030 emulation */
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_EDR, 0x57);
+	/* enable ISR clear on read */
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_SIH_CTRL, 0x05);
+	return 0;
+}
+
+static void rx51_kp_fill(u8 k, u8 mods)
+{
+	/* check if some cursor key without meta fn key was pressed */
+	if (!(mods & 2) && (k == 18 || k == 31 || k == 33 || k == 34)) {
+		keybuf[keybuf_tail++] = '\e';
+		keybuf_tail %= KEYBUF_SIZE;
+		keybuf[keybuf_tail++] = '[';
+		keybuf_tail %= KEYBUF_SIZE;
+		if (k == 18) /* up */
+			keybuf[keybuf_tail++] = 'A';
+		else if (k == 31) /* left */
+			keybuf[keybuf_tail++] = 'D';
+		else if (k == 33) /* down */
+			keybuf[keybuf_tail++] = 'B';
+		else if (k == 34) /* right */
+			keybuf[keybuf_tail++] = 'C';
+		keybuf_tail %= KEYBUF_SIZE;
+		return;
+	}
+
+	if (mods & 2) { /* fn meta key was pressed */
+		k = keymap[k+64];
+	} else {
+		k = keymap[k];
+		if (mods & 1) { /* ctrl key was pressed */
+			if (k >= 'a' && k <= 'z')
+				k -= 'a' - 1;
+		}
+		if (mods & 4) { /* shift key was pressed */
+			if (k >= 'a' && k <= 'z')
+				k += 'A' - 'a';
+			else if (k == '.')
+				k = ':';
+			else if (k == ',')
+				k = ';';
+		}
+	}
+	keybuf[keybuf_tail++] = k;
+	keybuf_tail %= KEYBUF_SIZE;
+}
+
+/*
+ * Routine: rx51_kp_tstc
+ * Description: Test if key was pressed (from buffer).
+ */
+int rx51_kp_tstc(struct stdio_dev *sdev)
+{
+	u8 c, r, dk, i;
+	u8 intr;
+	u8 mods;
+
+	/* localy lock twl4030 i2c bus */
+	if (test_and_set_bit(0, &twl_i2c_lock))
+		return 0;
+
+	/* twl4030 remembers up to 2 events */
+	for (i = 0; i < 2; i++) {
+
+		/* check interrupt register for events */
+		twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_ISR1 + (2 * i), &intr);
+
+		/* no event */
+		if (!(intr&1))
+			continue;
+
+		/* read the key state */
+		twl4030_i2c_read(TWL4030_CHIP_KEYPAD,
+				 TWL4030_KEYPAD_FULL_CODE_7_0, keys, 8);
+
+		/* cut out modifier keys from the keystate */
+		mods = keys[4] >> 4;
+		keys[4] &= 0x0f;
+
+		for (c = 0; c < 8; c++) {
+
+			/* get newly pressed keys only */
+			dk = ((keys[c] ^ old_keys[c])&keys[c]);
+			old_keys[c] = keys[c];
+
+			/* fill the keybuf */
+			for (r = 0; r < 8; r++) {
+				if (dk&1)
+					rx51_kp_fill((c*8)+r, mods);
+				dk = dk >> 1;
+			}
+
+		}
+
+	}
+
+	/* localy unlock twl4030 i2c bus */
+	test_and_clear_bit(0, &twl_i2c_lock);
+
+	return (KEYBUF_SIZE + keybuf_tail - keybuf_head)%KEYBUF_SIZE;
+}
+
+/*
+ * Routine: rx51_kp_getc
+ * Description: Get last pressed key (from buffer).
+ */
+int rx51_kp_getc(struct stdio_dev *sdev)
+{
+	keybuf_head %= KEYBUF_SIZE;
+	while (!rx51_kp_tstc(sdev))
+		WATCHDOG_RESET();
+	return keybuf[keybuf_head++];
+}
+
+static const struct mmc_config rx51_mmc_cfg = {
+	.host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
+	.f_min = 400000,
+	.f_max = 52000000,
+	.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
+	.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
+};
+
+static const struct omap_hsmmc_plat rx51_mmc[] = {
+	{ rx51_mmc_cfg, (struct hsmmc *)OMAP_HSMMC1_BASE },
+	{ rx51_mmc_cfg, (struct hsmmc *)OMAP_HSMMC2_BASE },
+};
+
+U_BOOT_DRVINFOS(rx51_mmc) = {
+	{ "omap_hsmmc", &rx51_mmc[0] },
+	{ "omap_hsmmc", &rx51_mmc[1] },
+};
+
+static const struct omap_i2c_plat rx51_i2c[] = {
+	{ I2C_BASE1, 100000, OMAP_I2C_REV_V1 },
+	{ I2C_BASE2, 100000, OMAP_I2C_REV_V1 },
+	{ I2C_BASE3, 100000, OMAP_I2C_REV_V1 },
+};
+
+U_BOOT_DRVINFOS(rx51_i2c) = {
+	{ "i2c_omap", &rx51_i2c[0] },
+	{ "i2c_omap", &rx51_i2c[1] },
+	{ "i2c_omap", &rx51_i2c[2] },
+};
diff --git a/roms/u-boot/board/nokia/rx51/tag_omap.h b/roms/u-boot/board/nokia/rx51/tag_omap.h
new file mode 100644
index 000000000..b99d6b7de
--- /dev/null
+++ b/roms/u-boot/board/nokia/rx51/tag_omap.h
@@ -0,0 +1,294 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali@kernel.org>
+ *
+ * (C) Copyright 2011
+ * marcel@mesa.nl, Mesa Consulting B.V.
+ *
+ * (C) Copyright 2004-2005
+ * Nokia Corporation
+ */
+
+
+/*
+ *  Code copied from maemo kernel 2.6.28 file
+ *  arch/arm/plat-omap/include/mach/board.h
+ *
+ *  Information structures for board-specific data
+ *
+ *  Copyright (C) 2004	Nokia Corporation
+ *  Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+
+/* Different peripheral ids */
+#define OMAP_TAG_CLOCK		0x4f01
+#define OMAP_TAG_SERIAL_CONSOLE	0x4f03
+#define OMAP_TAG_USB		0x4f04
+#define OMAP_TAG_LCD		0x4f05
+#define OMAP_TAG_GPIO_SWITCH	0x4f06
+#define OMAP_TAG_UART		0x4f07
+#define OMAP_TAG_FBMEM		0x4f08
+#define OMAP_TAG_STI_CONSOLE	0x4f09
+#define OMAP_TAG_CAMERA_SENSOR	0x4f0a
+#define OMAP_TAG_PARTITION	0x4f0b
+#define OMAP_TAG_TEA5761	0x4f10
+#define OMAP_TAG_TMP105		0x4f11
+
+#define OMAP_TAG_BOOT_REASON	0x4f80
+#define OMAP_TAG_FLASH_PART_STR	0x4f81
+#define OMAP_TAG_VERSION_STR	0x4f82
+
+#define OMAP_TAG_NOKIA_BT	0x4e01
+#define OMAP_TAG_WLAN_CX3110X	0x4e02
+#define OMAP_TAG_CBUS		0x4e03
+#define OMAP_TAG_EM_ASIC_BB5	0x4e04
+
+
+struct omap_clock_config {
+	/* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
+	u8 system_clock_type;
+};
+
+struct omap_serial_console_config {
+	u8 console_uart;
+	u32 console_speed;
+};
+
+struct omap_sti_console_config {
+	unsigned enable:1;
+	u8 channel;
+};
+
+struct omap_usb_config {
+	/* Configure drivers according to the connectors on your board:
+	 *  - "A" connector (rectagular)
+	 *	... for host/OHCI use, set "register_host".
+	 *  - "B" connector (squarish) or "Mini-B"
+	 *	... for device/gadget use, set "register_dev".
+	 *  - "Mini-AB" connector (very similar to Mini-B)
+	 *	... for OTG use as device OR host, initialize "otg"
+	 */
+	unsigned	register_host:1;
+	unsigned	register_dev:1;
+	u8		otg;	/* port number, 1-based:  usb1 == 2 */
+
+	u8		hmc_mode;
+
+	/* implicitly true if otg:  host supports remote wakeup? */
+	u8		rwc;
+
+	/* signaling pins used to talk to transceiver on usbN:
+	 *  0 == usbN unused
+	 *  2 == usb0-only, using internal transceiver
+	 *  3 == 3 wire bidirectional
+	 *  4 == 4 wire bidirectional
+	 *  6 == 6 wire unidirectional (or TLL)
+	 */
+	u8		pins[3];
+};
+
+struct omap_lcd_config {
+	char panel_name[16];
+	char ctrl_name[16];
+	s16  nreset_gpio;
+	u8   data_lines;
+};
+
+struct omap_fbmem_config {
+	u32 start;
+	u32 size;
+};
+
+struct omap_gpio_switch_config {
+	char name[12];
+	u16 gpio;
+	u8 flags:4;
+	u8 type:4;
+	unsigned int key_code:24; /* Linux key code */
+};
+
+struct omap_uart_config {
+	/* Bit field of UARTs present; bit 0 --> UART1 */
+	unsigned int enabled_uarts;
+};
+
+struct omap_tea5761_config {
+	u16 enable_gpio;
+};
+
+struct omap_partition_config {
+	char name[16];
+	unsigned int size;
+	unsigned int offset;
+	/* same as in include/linux/mtd/partitions.h */
+	unsigned int mask_flags;
+};
+
+struct omap_flash_part_str_config {
+	char part_table[0];
+};
+
+struct omap_boot_reason_config {
+	char reason_str[12];
+};
+
+struct omap_version_config {
+	char component[12];
+	char version[12];
+};
+
+/*
+ *  Code copied from maemo kernel 2.6.28 file
+ *  arch/arm/plat-omap/include/mach/board-nokia.h
+ *
+ *  Information structures for Nokia-specific board config data
+ *
+ *  Copyright (C) 2005  Nokia Corporation
+ */
+
+struct omap_bluetooth_config {
+	u8 chip_type;
+	u8 bt_wakeup_gpio;
+	u8 host_wakeup_gpio;
+	u8 reset_gpio;
+	u8 bt_uart;
+	u8 bd_addr[6];
+	u8 bt_sysclk;
+};
+
+struct omap_wlan_cx3110x_config {
+	u8 chip_type;
+	u8 reserverd;
+	s16 power_gpio;
+	s16 irq_gpio;
+	s16 spi_cs_gpio;
+};
+
+struct omap_cbus_config {
+	s16 clk_gpio;
+	s16 dat_gpio;
+	s16 sel_gpio;
+};
+
+struct omap_em_asic_bb5_config {
+	s16 retu_irq_gpio;
+	s16 tahvo_irq_gpio;
+};
+
+/*
+ *  omap_tag handling
+ *
+ *  processing omap tag structures
+ *
+ *  Copyright (C) 2011  marcel@mesa.nl, Mesa Consulting B.V.
+ *  Copyright (C) 2012  Pali Rohár <pali@kernel.org>
+ */
+
+/* TI OMAP specific information */
+#define ATAG_BOARD	0x414f4d50
+
+struct tag_omap_header {
+	u16 tag;
+	u16 size;
+};
+
+struct tag_omap {
+	struct tag_omap_header hdr;
+	union {
+		struct omap_clock_config clock;
+		struct omap_serial_console_config serial_console;
+		struct omap_sti_console_config sti_console;
+		struct omap_usb_config usb;
+		struct omap_lcd_config lcd;
+		struct omap_fbmem_config fbmem;
+		struct omap_gpio_switch_config gpio_switch;
+		struct omap_uart_config uart;
+		struct omap_tea5761_config tea5761;
+		struct omap_partition_config partition;
+		struct omap_flash_part_str_config flash_part_str;
+		struct omap_boot_reason_config boot_reason;
+		struct omap_version_config version;
+		struct omap_bluetooth_config bluetooth;
+		struct omap_wlan_cx3110x_config wlan_cx3110x;
+		struct omap_cbus_config cbus;
+		struct omap_em_asic_bb5_config em_asic_bb5;
+	} u;
+};
+
+#define tag_omap_next(t)	((struct tag_omap *)((u8 *)(t) + \
+				(t)->hdr.size + sizeof(struct tag_omap_header)))
+
+#define OMAP_TAG_HEADER_CONFIG(config, type) \
+	.hdr.tag = config, \
+	.hdr.size = sizeof(struct type)
+
+#define OMAP_TAG_UART_CONFIG(p1) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_UART, omap_uart_config), \
+		.u.uart.enabled_uarts = p1, \
+	}
+
+#define OMAP_TAG_SERIAL_CONSOLE_CONFIG(p1, p2) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_SERIAL_CONSOLE, \
+			omap_serial_console_config), \
+		.u.serial_console.console_uart = p1, \
+		.u.serial_console.console_speed = p2, \
+	}
+
+#define OMAP_TAG_LCD_CONFIG(p1, p2, p3, p4) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_LCD, omap_lcd_config), \
+		.u.lcd.panel_name = p1, \
+		.u.lcd.ctrl_name = p2, \
+		.u.lcd.nreset_gpio = p3, \
+		.u.lcd.data_lines = p4, \
+	}
+
+#define OMAP_TAG_GPIO_SWITCH_CONFIG(p1, p2, p3, p4, p5) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_GPIO_SWITCH, \
+			omap_gpio_switch_config), \
+		.u.gpio_switch.name = p1, \
+		.u.gpio_switch.gpio = p2, \
+		.u.gpio_switch.flags = p3, \
+		.u.gpio_switch.type = p4, \
+		.u.gpio_switch.key_code = p5, \
+	}
+
+#define OMAP_TAG_WLAN_CX3110X_CONFIG(p1, p2, p3, p4, p5) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_WLAN_CX3110X, \
+			omap_wlan_cx3110x_config), \
+		.u.wlan_cx3110x.chip_type = p1, \
+		.u.wlan_cx3110x.reserverd = p2, \
+		.u.wlan_cx3110x.power_gpio = p3, \
+		.u.wlan_cx3110x.irq_gpio = p4, \
+		.u.wlan_cx3110x.spi_cs_gpio = p5, \
+	}
+
+#define OMAP_TAG_PARTITION_CONFIG(p1, p2, p3, p4) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_PARTITION, \
+			omap_partition_config), \
+		.u.partition.name = p1, \
+		.u.partition.size = p2, \
+		.u.partition.offset = p3, \
+		.u.partition.mask_flags = p4, \
+	}
+
+#define OMAP_TAG_BOOT_REASON_CONFIG(p1) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_BOOT_REASON, \
+			omap_boot_reason_config), \
+		.u.boot_reason.reason_str = p1, \
+	}
+
+#define OMAP_TAG_VERSION_STR_CONFIG(p1, p2) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_VERSION_STR, \
+			omap_version_config), \
+		.u.version.component = p1, \
+		.u.version.version = p2, \
+	}
diff --git a/roms/u-boot/board/novtech/meerkat96/Kconfig b/roms/u-boot/board/novtech/meerkat96/Kconfig
new file mode 100644
index 000000000..b0e46fcc1
--- /dev/null
+++ b/roms/u-boot/board/novtech/meerkat96/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MEERKAT96
+
+config SYS_BOARD
+	default "meerkat96"
+
+config SYS_VENDOR
+	default "novtech"
+
+config SYS_CONFIG_NAME
+	default "meerkat96"
+
+endif
diff --git a/roms/u-boot/board/novtech/meerkat96/MAINTAINERS b/roms/u-boot/board/novtech/meerkat96/MAINTAINERS
new file mode 100644
index 000000000..2a53b6309
--- /dev/null
+++ b/roms/u-boot/board/novtech/meerkat96/MAINTAINERS
@@ -0,0 +1,6 @@
+MEERKAT96 BOARD
+M:	Shawn Guo <shawnguo@kernel.org>
+S:	Maintained
+F:	board/novtech/meerkat96
+F:	include/configs/meerkat96.h
+F:	configs/meerkat96_defconfig
diff --git a/roms/u-boot/board/novtech/meerkat96/Makefile b/roms/u-boot/board/novtech/meerkat96/Makefile
new file mode 100644
index 000000000..f27e05641
--- /dev/null
+++ b/roms/u-boot/board/novtech/meerkat96/Makefile
@@ -0,0 +1 @@
+obj-y := meerkat96.o
diff --git a/roms/u-boot/board/novtech/meerkat96/README b/roms/u-boot/board/novtech/meerkat96/README
new file mode 100644
index 000000000..bca2fad5a
--- /dev/null
+++ b/roms/u-boot/board/novtech/meerkat96/README
@@ -0,0 +1,18 @@
+* Build U-Boot for Meerkat96 board
+
+  $ make mrproper
+  $ make meerkat96_defconfig
+  $ make
+
+  It will generate the U-Boot binary called u-boot-dtb.imx
+
+* Install U-Boot to MicroSD card
+
+  Plug MicroSD card to a Linux machine (with card reader), find the
+  device name and replace sd[x] with the name in the following command.
+
+  $ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=512 seek=2
+
+  It will install U-Boot to MicroSD card at 1KiB offset.  Insert the
+  card to Meerkat96 MicroSD slot, power up the board, and U-Boot should
+  boot from the card.
diff --git a/roms/u-boot/board/novtech/meerkat96/imximage.cfg b/roms/u-boot/board/novtech/meerkat96/imximage.cfg
new file mode 100644
index 000000000..86275b84d
--- /dev/null
+++ b/roms/u-boot/board/novtech/meerkat96/imximage.cfg
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : sd
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable OCRAM EPDC */
+DATA 4 0x30340004 0x4F400005
+
+/* =============================================================================
+ * DDR Controller Registers
+ * =============================================================================
+ * Memory type:           DDR3
+ * Manufacturer:          ISSI
+ * Device Part Number:    IS43TR16256AL-125KBL
+ * Clock Freq.:           533MHz
+ * Density per CS in Gb:  4
+ * Chip Selects used:     1
+ * Number of Banks:       8
+ * Row address:          15
+ * Column address:       10
+ * Data bus width:       16
+ * ROW-BANK interleave:  ENABLED
+ * =============================================================================
+ */
+
+DATA 4 0x30391000 0x00000002    // deassert presetn
+DATA 4 0x307A0000 0x01041001    // DDRC_MSTR
+DATA 4 0x307A0064 0x00400046    // DDRC_RFSHTMG
+DATA 4 0x307a0490 0x00000001    // DDRC_PCTRL_0
+DATA 4 0x307A00D4 0x00690000    // DDRC_INIT1
+DATA 4 0x307A00D0 0x00020083    // DDRC_INIT0
+DATA 4 0x307A00DC 0x09300004    // DDRC_INIT3
+DATA 4 0x307A00E0 0x04080000    // DDRC_INIT4
+DATA 4 0x307A00E4 0x00100004    // DDRC_INIT5
+DATA 4 0x307A00F4 0x0000033F    // DDRC_RANKCTL
+DATA 4 0x307A0100 0x090B1109    // DDRC_DRAMTMG0
+DATA 4 0x307A0104 0x0007020D    // DDRC_DRAMTMG1
+DATA 4 0x307A0108 0x03040407    // DDRC_DRAMTMG2
+DATA 4 0x307A010C 0x00002006    // DDRC_DRAMTMG3
+DATA 4 0x307A0110 0x04020205    // DDRC_DRAMTMG4
+DATA 4 0x307A0114 0x03030202    // DDRC_DRAMTMG5
+DATA 4 0x307A0120 0x00000803    // DDRC_DRAMTMG8
+DATA 4 0x307A0180 0x00800020    // DDRC_ZQCTL0
+DATA 4 0x307A0190 0x02098204    // DDRC_DFITMG0
+DATA 4 0x307A0194 0x00030303    // DDRC_DFITMG1
+DATA 4 0x307A01A0 0x80400003    // DDRC_DFIUPD0
+DATA 4 0x307A01A4 0x00100020    // DDRC_DFIUPD1
+DATA 4 0x307A01A8 0x80100004    // DDRC_DFIUPD2
+DATA 4 0x307A0200 0x00000015    // DDRC_ADDRMAP0
+DATA 4 0x307A0204 0x00070707    // DDRC_ADDRMAP1
+DATA 4 0x307A0210 0x00000F0F    // DDRC_ADDRMAP4
+DATA 4 0x307A0214 0x06060606    // DDRC_ADDRMAP5
+DATA 4 0x307A0218 0x0F060606    // DDRC_ADDRMAP6
+DATA 4 0x307A0240 0x06000604    // DDRC_ODTCFG
+DATA 4 0x307A0244 0x00000001    // DDRC_ODTMAP
+
+
+/* =============================================================================
+ * PHY Control Register
+ * =============================================================================
+ */
+
+DATA 4 0x30391000 0x00000000    // deassert presetn
+DATA 4 0x30790000 0x17420F40    // DDR_PHY_PHY_CON0
+DATA 4 0x30790004 0x10210100    // DDR_PHY_PHY_CON1
+DATA 4 0x30790010 0x00060807    // DDR_PHY_PHY_CON4
+DATA 4 0x307900B0 0x1010007E    // DDR_PHY_MDLL_CON0
+DATA 4 0x3079009C 0x00000D6E    // DDR_PHY_DRVDS_CON0
+DATA 4 0x30790030 0x08080808    // DDR_PHY_OFFSET_WR_CON0
+DATA 4 0x30790020 0x08080808    // DDR_PHY_OFFSET_RD_CON0
+DATA 4 0x30790050 0x01000010    // DDR_PHY_OFFSETD_CON0
+DATA 4 0x30790050 0x00000010    // DDR_PHY_OFFSETD_CON0
+DATA 4 0x30790018 0x0000000F    // DDR_PHY_LP_CON0
+DATA 4 0x307900C0 0x0E407304    // DDR_PHY_ZQ_CON0 - Start Manual ZQ
+DATA 4 0x307900C0 0x0E447304
+DATA 4 0x307900C0 0x0E447306
+DATA 4 0x307900C0 0x0E447304    // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
+DATA 4 0x307900C0 0x0E407304    // DDR_PHY_ZQ_CON0 - End Manual ZQ
+
+
+/* =============================================================================
+ * Final Initialization start sequence
+ * =============================================================================
+ */
+
+DATA 4 0x30384130 0x00000000    // Disable Clock
+DATA 4 0x30340020 0x00000178    // IOMUX_GRP_GRP8 - Start input to PHY
+DATA 4 0x30384130 0x00000002    // Enable Clock
+/* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */
diff --git a/roms/u-boot/board/novtech/meerkat96/meerkat96.c b/roms/u-boot/board/novtech/meerkat96/meerkat96.c
new file mode 100644
index 000000000..1edebe5db
--- /dev/null
+++ b/roms/u-boot/board/novtech/meerkat96/meerkat96.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Linaro Ltd.
+ * Copyright (C) 2016 NXP Semiconductors
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <common.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
+			PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const meerkat96_pads[] = {
+	/* UART6 as debug serial */
+	MX7D_PAD_SD1_CD_B__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_SD1_WP__UART6_DCE_TX   | MUX_PAD_CTRL(UART_PAD_CTRL),
+	/* WDOG1 for reset */
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	imx_iomux_v3_setup_multiple_pads(meerkat96_pads,
+					 ARRAY_SIZE(meerkat96_pads));
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *mode;
+
+	if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
+		mode = "secure";
+	else
+		mode = "non-secure";
+
+	printf("Board: i.MX7D Meerkat96 in %s mode\n", mode);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/nvidia/beaver/Kconfig b/roms/u-boot/board/nvidia/beaver/Kconfig
new file mode 100644
index 000000000..23f7c945f
--- /dev/null
+++ b/roms/u-boot/board/nvidia/beaver/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BEAVER
+
+config SYS_BOARD
+	default "beaver"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "beaver"
+
+endif
diff --git a/roms/u-boot/board/nvidia/beaver/MAINTAINERS b/roms/u-boot/board/nvidia/beaver/MAINTAINERS
new file mode 100644
index 000000000..26bcacc8e
--- /dev/null
+++ b/roms/u-boot/board/nvidia/beaver/MAINTAINERS
@@ -0,0 +1,7 @@
+BEAVER BOARD
+M:	Tom Warren <twarren@nvidia.com>
+M:	Stephen Warren <swarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/beaver/
+F:	include/configs/beaver.h
+F:	configs/beaver_defconfig
diff --git a/roms/u-boot/board/nvidia/beaver/Makefile b/roms/u-boot/board/nvidia/beaver/Makefile
new file mode 100644
index 000000000..80cff3eb9
--- /dev/null
+++ b/roms/u-boot/board/nvidia/beaver/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+
+obj-y	= ../cardhu/cardhu.o
diff --git a/roms/u-boot/board/nvidia/cardhu/Kconfig b/roms/u-boot/board/nvidia/cardhu/Kconfig
new file mode 100644
index 000000000..63ace66aa
--- /dev/null
+++ b/roms/u-boot/board/nvidia/cardhu/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CARDHU
+
+config SYS_BOARD
+	default "cardhu"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "cardhu"
+
+endif
diff --git a/roms/u-boot/board/nvidia/cardhu/MAINTAINERS b/roms/u-boot/board/nvidia/cardhu/MAINTAINERS
new file mode 100644
index 000000000..d3c3e368c
--- /dev/null
+++ b/roms/u-boot/board/nvidia/cardhu/MAINTAINERS
@@ -0,0 +1,6 @@
+CARDHU BOARD
+M:	Tom Warren <twarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/cardhu/
+F:	include/configs/cardhu.h
+F:	configs/cardhu_defconfig
diff --git a/roms/u-boot/board/nvidia/cardhu/Makefile b/roms/u-boot/board/nvidia/cardhu/Makefile
new file mode 100644
index 000000000..95971053d
--- /dev/null
+++ b/roms/u-boot/board/nvidia/cardhu/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2010-2012
+#  NVIDIA Corporation <www.nvidia.com>
+
+obj-y	:= cardhu.o
diff --git a/roms/u-boot/board/nvidia/cardhu/cardhu.c b/roms/u-boot/board/nvidia/cardhu/cardhu.c
new file mode 100644
index 000000000..6848e3400
--- /dev/null
+++ b/roms/u-boot/board/nvidia/cardhu/cardhu.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+#include "pinmux-config-cardhu.h"
+#include <i2c.h>
+
+#define PMU_I2C_ADDRESS		0x2D
+#define MAX_I2C_RETRY		3
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_pingrp_table(tegra3_pinmux_common,
+		ARRAY_SIZE(tegra3_pinmux_common));
+
+	pinmux_config_pingrp_table(unused_pins_lowpower,
+		ARRAY_SIZE(unused_pins_lowpower));
+
+	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
+	pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
+}
+
+#if defined(CONFIG_MMC_SDHCI_TEGRA)
+/*
+ * Do I2C/PMU writes to bring up SD card bus power
+ *
+ */
+void board_sdmmc_voltage_init(void)
+{
+	struct udevice *dev;
+	uchar reg, data_buffer[1];
+	int ret;
+	int i;
+
+	ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
+	if (ret) {
+		debug("%s: Cannot find PMIC I2C chip\n", __func__);
+		return;
+	}
+
+	/* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */
+	data_buffer[0] = 0x65;
+	reg = 0x32;
+
+	for (i = 0; i < MAX_I2C_RETRY; ++i) {
+		if (dm_i2c_write(dev, reg, data_buffer, 1))
+			udelay(100);
+	}
+
+	/* TPS659110: GPIO7_REG = PDEN, output a 1 to EN_3V3_SYS */
+	data_buffer[0] = 0x09;
+	reg = 0x67;
+
+	for (i = 0; i < MAX_I2C_RETRY; ++i) {
+		if (dm_i2c_write(dev, reg, data_buffer, 1))
+			udelay(100);
+	}
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+	/*
+	 * NOTE: We don't do mmc-specific pin muxes here.
+	 * They were done globally in pinmux_init().
+	 */
+
+	/* Bring up the SDIO1 power rail */
+	board_sdmmc_voltage_init();
+}
+#endif	/* MMC */
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+	struct udevice *dev;
+	u8 addr, data[1];
+	int err;
+
+	err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
+	if (err) {
+		debug("failed to find PMU bus\n");
+		return err;
+	}
+
+	/* TPS659110: LDO1_REG = 1.05V, ACTIVE */
+	data[0] = 0x15;
+	addr = 0x30;
+
+	err = dm_i2c_write(dev, addr, data, 1);
+	if (err) {
+		debug("failed to set VDD supply\n");
+		return err;
+	}
+
+	/* GPIO: PEX = 3.3V */
+	err = gpio_request(TEGRA_GPIO(L, 7), "PEX");
+	if (err < 0)
+		return err;
+
+	gpio_direction_output(TEGRA_GPIO(L, 7), 1);
+
+	/* TPS659110: LDO2_REG = 1.05V, ACTIVE */
+	data[0] = 0x15;
+	addr = 0x31;
+
+	err = dm_i2c_write(dev, addr, data, 1);
+	if (err) {
+		debug("failed to set AVDD supply\n");
+		return err;
+	}
+
+	return 0;
+}
+#endif /* PCI */
diff --git a/roms/u-boot/board/nvidia/cardhu/pinmux-config-cardhu.h b/roms/u-boot/board/nvidia/cardhu/pinmux-config-cardhu.h
new file mode 100644
index 000000000..c7e114802
--- /dev/null
+++ b/roms/u-boot/board/nvidia/cardhu/pinmux-config-cardhu.h
@@ -0,0 +1,335 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _PINMUX_CONFIG_CARDHU_H_
+#define _PINMUX_CONFIG_CARDHU_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io)		\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{							\
+		.drvgrp		= PMUX_DRVGRP_##_drvgrp,	\
+		.slwf		= _slwf,			\
+		.slwr		= _slwr,			\
+		.drvup		= _drvup,			\
+		.drvdn		= _drvdn,			\
+		.lpmd		= PMUX_LPMD_##_lpmd,		\
+		.schmt		= PMUX_SCHMT_##_schmt,		\
+		.hsm		= PMUX_HSM_##_hsm,		\
+	}
+
+static struct pmux_pingrp_config tegra3_pinmux_common[] = {
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* SDMMC4 pinmux */
+	LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
+	LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
+	DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
+	DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
+	DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
+
+	/* KBC keys */
+	DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
+
+	/* GPIOs */
+	/* SDMMC1 CD gpio */
+	DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
+	/* SDMMC1 WP gpio */
+	LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* Touch panel GPIO */
+	/* Touch IRQ */
+	DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
+
+	/* Touch RESET */
+	DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
+
+	/* Power rails GPIO */
+	DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
+
+	LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+};
+
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+static struct pmux_drvgrp_config cardhu_padctrl[] = {
+	/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+	DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+		SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif	/* _PINMUX_CONFIG_CARDHU_H_ */
diff --git a/roms/u-boot/board/nvidia/dalmore/Kconfig b/roms/u-boot/board/nvidia/dalmore/Kconfig
new file mode 100644
index 000000000..96eaa01cf
--- /dev/null
+++ b/roms/u-boot/board/nvidia/dalmore/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DALMORE
+
+config SYS_BOARD
+	default "dalmore"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "dalmore"
+
+endif
diff --git a/roms/u-boot/board/nvidia/dalmore/MAINTAINERS b/roms/u-boot/board/nvidia/dalmore/MAINTAINERS
new file mode 100644
index 000000000..fe86375ca
--- /dev/null
+++ b/roms/u-boot/board/nvidia/dalmore/MAINTAINERS
@@ -0,0 +1,6 @@
+DALMORE BOARD
+M:	Tom Warren <twarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/dalmore/
+F:	include/configs/dalmore.h
+F:	configs/dalmore_defconfig
diff --git a/roms/u-boot/board/nvidia/dalmore/Makefile b/roms/u-boot/board/nvidia/dalmore/Makefile
new file mode 100644
index 000000000..bc114e61c
--- /dev/null
+++ b/roms/u-boot/board/nvidia/dalmore/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+
+obj-y	:= dalmore.o
diff --git a/roms/u-boot/board/nvidia/dalmore/dalmore.c b/roms/u-boot/board/nvidia/dalmore/dalmore.c
new file mode 100644
index 000000000..72511e401
--- /dev/null
+++ b/roms/u-boot/board/nvidia/dalmore/dalmore.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include "pinmux-config-dalmore.h"
+#include <i2c.h>
+
+#define BAT_I2C_ADDRESS		0x48	/* TPS65090 charger */
+#define PMU_I2C_ADDRESS		0x58	/* TPS65913 PMU */
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_pingrp_table(tegra114_pinmux_set_nontristate,
+		ARRAY_SIZE(tegra114_pinmux_set_nontristate));
+
+	pinmux_config_pingrp_table(tegra114_pinmux_common,
+		ARRAY_SIZE(tegra114_pinmux_common));
+
+	pinmux_config_pingrp_table(unused_pins_lowpower,
+		ARRAY_SIZE(unused_pins_lowpower));
+
+	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
+	pinmux_config_drvgrp_table(dalmore_padctrl,
+		ARRAY_SIZE(dalmore_padctrl));
+}
+
+#if defined(CONFIG_MMC_SDHCI_TEGRA)
+/*
+ * Do I2C/PMU writes to bring up SD card bus power
+ *
+ */
+void board_sdmmc_voltage_init(void)
+{
+	struct udevice *dev;
+	uchar reg, data_buffer[1];
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
+	if (ret) {
+		debug("%s: Cannot find PMIC I2C chip\n", __func__);
+		return;
+	}
+
+	/* TPS65913: LDO9_VOLTAGE = 3.3V */
+	data_buffer[0] = 0x31;
+	reg = 0x61;
+
+	ret = dm_i2c_write(dev, reg, data_buffer, 1);
+	if (ret)
+		printf("%s: PMU i2c_write %02X<-%02X returned %d\n",
+			__func__, reg, data_buffer[0], ret);
+
+	/* TPS65913: LDO9_CTRL = Active */
+	data_buffer[0] = 0x01;
+	reg = 0x60;
+
+	ret = dm_i2c_write(dev, reg, data_buffer, 1);
+	if (ret)
+		printf("%s: PMU i2c_write %02X<-%02X returned %d\n",
+			__func__, reg, data_buffer[0], ret);
+
+	/* TPS65090: FET6_CTRL = enable output auto discharge, enable FET6 */
+	data_buffer[0] = 0x03;
+	reg = 0x14;
+
+	ret = i2c_get_chip_for_busnum(0, BAT_I2C_ADDRESS, 1, &dev);
+	if (ret) {
+		debug("%s: Cannot find charger I2C chip\n", __func__);
+		return;
+	}
+	ret = dm_i2c_write(dev, reg, data_buffer, 1);
+	if (ret)
+		printf("%s: BAT i2c_write %02X<-%02X returned %d\n",
+			__func__, reg, data_buffer[0], ret);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+	/*
+	 * NOTE: We don't do mmc-specific pin muxes here.
+	 * They were done globally in pinmux_init().
+	 */
+
+	/* Bring up the SDIO3 power rail */
+	board_sdmmc_voltage_init();
+}
+#endif /* MMC */
diff --git a/roms/u-boot/board/nvidia/dalmore/pinmux-config-dalmore.h b/roms/u-boot/board/nvidia/dalmore/pinmux-config-dalmore.h
new file mode 100644
index 000000000..4acf141a8
--- /dev/null
+++ b/roms/u-boot/board/nvidia/dalmore/pinmux-config-dalmore.h
@@ -0,0 +1,359 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _PINMUX_CONFIG_DALMORE_H_
+#define _PINMUX_CONFIG_DALMORE_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io)		\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od)		\
+	{								\
+		.pingrp     = PMUX_PINGRP_##_pingrp,			\
+		.func       = PMUX_FUNC_##_mux,				\
+		.pull       = PMUX_PULL_##_pull,			\
+		.tristate   = PMUX_TRI_##_tri,				\
+		.io         = PMUX_PIN_##_io,				\
+		.lock       = PMUX_PIN_LOCK_##_lock,			\
+		.od         = PMUX_PIN_OD_##_od,			\
+		.ioreset    = PMUX_PIN_IO_RESET_DEFAULT,		\
+	}
+
+#define USB_PINMUX CEC_PINMUX
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{						\
+		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
+		.slwf   = _slwf,			\
+		.slwr   = _slwr,			\
+		.drvup  = _drvup,			\
+		.drvdn  = _drvdn,			\
+		.lpmd   = PMUX_LPMD_##_lpmd,		\
+		.schmt  = PMUX_SCHMT_##_schmt,		\
+		.hsm    = PMUX_HSM_##_hsm,		\
+	}
+
+static struct pmux_pingrp_config tegra114_pinmux_common[] = {
+	/* EXTPERIPH1 pinmux */
+	DEFAULT_PINMUX(CLK1_OUT_PW4,      EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2S0 pinmux */
+	DEFAULT_PINMUX(DAP1_DIN_PN1,      I2S0,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT_PN2,     I2S0,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_FS_PN0,       I2S0,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK_PN3,     I2S0,        NORMAL,    NORMAL,   INPUT),
+
+	/* I2S1 pinmux */
+	DEFAULT_PINMUX(DAP2_DIN_PA4,      I2S1,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT_PA5,     I2S1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_FS_PA2,       I2S1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK_PA3,     I2S1,        NORMAL,    NORMAL,   INPUT),
+
+	/* I2S3 pinmux */
+	DEFAULT_PINMUX(DAP4_DIN_PP5,      I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT_PP6,     I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_FS_PP4,       I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK_PP7,     I2S3,        NORMAL,    NORMAL,   INPUT),
+
+	/* CLDVFS pinmux */
+	DEFAULT_PINMUX(DVFS_PWM_PX0,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DVFS_CLK_PX2,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+
+	/* ULPI pinmux */
+	DEFAULT_PINMUX(ULPI_CLK_PY0,      ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA0_PO1,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA1_PO2,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2_PO3,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3_PO4,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4_PO5,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5_PO6,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6_PO7,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7_PO0,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DIR_PY1,      ULPI,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(ULPI_NXT_PY2,      ULPI,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(ULPI_STP_PY3,      ULPI,        NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	/* VI pinmux */
+	VI_PINMUX(CAM_MCLK_PCC0, VI_ALT3,  NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+	/* VI_ALT1 pinmux */
+	VI_PINMUX(PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+	/* VGP4 pinmux */
+	VI_PINMUX(PBB4, VGP4,    NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	/* UARTD pinmux */
+	DEFAULT_PINMUX(GMI_A16_PJ7,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_A17_PB0,       UARTD,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_A18_PB1,       UARTD,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_A19_PK7,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* SPI4 pinmux */
+	DEFAULT_PINMUX(GMI_AD5_PG5,       SPI4,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_AD6_PG6,       SPI4,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_AD7_PG7,       SPI4,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_AD12_PH4,      RSVD1,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_CS6_N_PI3,     SPI4,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_WR_N_PI0,      SPI4,        NORMAL,    NORMAL,   INPUT),
+
+	/* PWM1 pinmux */
+	DEFAULT_PINMUX(GMI_AD9_PH1,       PWM1,        NORMAL,    NORMAL,   OUTPUT),
+
+	/* SOC pinmux */
+	DEFAULT_PINMUX(GMI_CS1_N_PJ2,     SOC,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GMI_OE_N_PI1,      SOC,         NORMAL,    TRISTATE, INPUT),
+
+	/* EXTPERIPH2 pinmux */
+	DEFAULT_PINMUX(CLK2_OUT_PW5,      EXTPERIPH2,  NORMAL,    NORMAL,   OUTPUT),
+
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK_PZ0,    SDMMC1,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD_PZ1,    SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0_PY7,   SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1_PY6,   SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2_PY5,   SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3_PY4,   SDMMC1,      UP,        NORMAL,   INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK_PA6,    SDMMC3,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD_PA7,    SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0_PB7,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1_PB6,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2_PB5,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3_PB4,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,  UP,        TRISTATE, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,  DOWN,      NORMAL,   INPUT),
+
+	/* SDMMC4 pinmux */
+	DEFAULT_PINMUX(SDMMC4_CLK_PCC4,    SDMMC4,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_CMD_PT7,     SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT0_PAA0,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT1_PAA1,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT2_PAA2,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT3_PAA3,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT4_PAA4,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT5_PAA5,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT6_PAA6,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT7_PAA7,   SDMMC4,      UP,        NORMAL,   INPUT),
+
+	/* BLINK pinmux */
+	DEFAULT_PINMUX(CLK_32K_OUT_PA0,   BLINK,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* KBC pinmux */
+	DEFAULT_PINMUX(KB_COL0_PQ0,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_COL1_PQ1,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_COL2_PQ2,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_ROW0_PR0,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_ROW1_PR1,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_ROW2_PR2,       KBC,         UP,        NORMAL,   INPUT),
+
+	/*Audio Codec*/
+	DEFAULT_PINMUX(DAP3_DIN_PP1,      RSVD1,       NORMAL,    TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(DAP3_SCLK_PP3,     RSVD1,       NORMAL,    TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(PV0,               RSVD1,       NORMAL,    TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(KB_ROW7_PR7,       RSVD1,       UP,        NORMAL,   INPUT),
+
+	/* UARTA pinmux */
+	DEFAULT_PINMUX(KB_ROW10_PS2,      UARTA,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW9_PS1,       UARTA,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2CPWR pinmux (I2C5) */
+	I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	/* SYSCLK pinmux */
+	DEFAULT_PINMUX(SYS_CLK_REQ_PZ5,   SYSCLK,      NORMAL,    NORMAL,   OUTPUT),
+
+	/* RTCK pinmux */
+	DEFAULT_PINMUX(JTAG_RTCK,     RTCK,        NORMAL,    NORMAL,   INPUT),
+
+	/* CLK pinmux */
+	DEFAULT_PINMUX(CLK_32K_IN,    CLK,         NORMAL,    TRISTATE, INPUT),
+
+	/* PWRON pinmux */
+	DEFAULT_PINMUX(CORE_PWR_REQ,  PWRON,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* CPU pinmux */
+	DEFAULT_PINMUX(CPU_PWR_REQ,   CPU,         NORMAL,    NORMAL,   OUTPUT),
+
+	/* PMI pinmux */
+	DEFAULT_PINMUX(PWR_INT_N,     PMI,         NORMAL,    TRISTATE, INPUT),
+
+	/* RESET_OUT_N pinmux */
+	DEFAULT_PINMUX(RESET_OUT_N,   RESET_OUT_N, NORMAL,    NORMAL,   OUTPUT),
+
+	/* EXTPERIPH3 pinmux */
+	DEFAULT_PINMUX(CLK3_OUT_PEE0,      EXTPERIPH3,  NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	/* UARTB pinmux */
+	DEFAULT_PINMUX(UART2_CTS_N_PJ5,   UARTB,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART2_RTS_N_PJ6,   UARTB,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* IRDA pinmux */
+	DEFAULT_PINMUX(UART2_RXD_PC3,     IRDA,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART2_TXD_PC2,     IRDA,        NORMAL,    NORMAL,   OUTPUT),
+
+	/* UARTC pinmux */
+	DEFAULT_PINMUX(UART3_CTS_N_PA1,   UARTC,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N_PC0,   UARTC,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD_PW7,     UARTC,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART3_TXD_PW6,     UARTC,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* OWR pinmux */
+	DEFAULT_PINMUX(OWR,               OWR,         NORMAL,    NORMAL,   INPUT),
+
+	/* CEC pinmux */
+	CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* I2C4 pinmux */
+	DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+	DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+
+	/* USB pinmux */
+	USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	/* nct */
+	DEFAULT_PINMUX(GPIO_X6_AUD_PX6,   SPI6,        UP,        TRISTATE, INPUT),
+};
+
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(CLK1_REQ_PEE2,     RSVD3,       DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(USB_VBUS_EN1_PN5,  RSVD3,       DOWN, TRISTATE, OUTPUT),
+};
+
+/* Initially setting all used GPIO's to non-TRISTATE */
+static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = {
+	DEFAULT_PINMUX(GPIO_X4_AUD_PX4,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GPIO_X5_AUD_PX5,     RSVD1,  UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_X6_AUD_PX6,     RSVD3,  UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_X7_AUD_PX7,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GPIO_W2_AUD_PW2,     RSVD1,  UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_W3_AUD_PW3,     SPI6,   UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_X1_AUD_PX1,     RSVD3,  DOWN,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_X3_AUD_PX3,     RSVD3,  UP,      NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(DAP3_FS_PP0,         I2S2,   DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(DAP3_DIN_PP1,        I2S2,   DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(DAP3_DOUT_PP2,       I2S2,   DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(DAP3_SCLK_PP3,       I2S2,   DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(PV0,                 RSVD3,  NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(PV1,                 RSVD1,  NORMAL,  NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(PBB3,                RSVD3,  DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(PBB5,                RSVD3,  DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(PBB6,                RSVD3,  DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(PBB7,                RSVD3,  DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(PCC1,                RSVD3,  DOWN,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(PCC2,                RSVD3,  DOWN,    NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(GMI_AD0_PG0,         GMI,    NORMAL,  NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GMI_AD1_PG1,         GMI,    NORMAL,  NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GMI_AD10_PH2,        GMI,    DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11_PH3,        GMI,    DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GMI_AD12_PH4,        GMI,    UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GMI_AD13_PH5,        GMI,    DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GMI_AD2_PG2,         GMI,    NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GMI_AD3_PG3,         GMI,    NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GMI_AD8_PH0,         GMI,    DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GMI_ADV_N_PK0,       GMI,    UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GMI_CLK_PK1,         GMI,    DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GMI_CS0_N_PJ0,       GMI,    UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GMI_CS2_N_PK3,       GMI,    UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GMI_CS3_N_PK4,       GMI,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GMI_CS4_N_PK2,       GMI,    UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GMI_CS7_N_PI6,       GMI,    UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GMI_DQS_P_PJ3,       GMI,    UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GMI_IORDY_PI5,       GMI,    UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GMI_WP_N_PC7,        GMI,    UP,      NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(SDMMC1_WP_N_PV3,     SPI4,   UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(CLK2_REQ_PCC5,       RSVD3,  NORMAL,  NORMAL,    OUTPUT),
+
+	DEFAULT_PINMUX(KB_COL3_PQ3,         KBC,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(KB_COL4_PQ4,         SDMMC3, UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL5_PQ5,         KBC,    UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL6_PQ6,         KBC,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(KB_COL7_PQ7,         KBC,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(KB_ROW3_PR3,         KBC,    DOWN,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW4_PR4,         KBC,    DOWN,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW6_PR6,         KBC,    DOWN,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW8_PS0,         KBC,    UP,      NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(CLK3_REQ_PEE1,       RSVD3,  NORMAL,  NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(PU4,                 RSVD3,  NORMAL,  NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(PU5,                 RSVD3,  NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(PU6,                 RSVD3,  NORMAL,  NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(HDMI_INT_PN7,        RSVD1,   DOWN,    NORMAL,   INPUT),
+
+	DEFAULT_PINMUX(GMI_AD9_PH1,         PWM1,   NORMAL,   NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(SPDIF_IN_PK6,        USB,    NORMAL,   NORMAL,   INPUT),
+
+	DEFAULT_PINMUX(SDMMC3_CD_N_PV2,     SDMMC3, UP,       NORMAL,   INPUT),
+};
+
+static struct pmux_drvgrp_config dalmore_padctrl[] = {
+	/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+	DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+		SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
+};
+#endif /* PINMUX_CONFIG_COMMON_H */
diff --git a/roms/u-boot/board/nvidia/harmony/Kconfig b/roms/u-boot/board/nvidia/harmony/Kconfig
new file mode 100644
index 000000000..328c94677
--- /dev/null
+++ b/roms/u-boot/board/nvidia/harmony/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_HARMONY
+
+config SYS_BOARD
+	default "harmony"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "harmony"
+
+endif
diff --git a/roms/u-boot/board/nvidia/harmony/MAINTAINERS b/roms/u-boot/board/nvidia/harmony/MAINTAINERS
new file mode 100644
index 000000000..f3508edc3
--- /dev/null
+++ b/roms/u-boot/board/nvidia/harmony/MAINTAINERS
@@ -0,0 +1,6 @@
+HARMONY BOARD
+M:	Tom Warren <twarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/harmony/
+F:	include/configs/harmony.h
+F:	configs/harmony_defconfig
diff --git a/roms/u-boot/board/nvidia/harmony/Makefile b/roms/u-boot/board/nvidia/harmony/Makefile
new file mode 100644
index 000000000..2e1027bf9
--- /dev/null
+++ b/roms/u-boot/board/nvidia/harmony/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2010,2011
+#  NVIDIA Corporation <www.nvidia.com>
+
+obj-y	:= harmony.o
diff --git a/roms/u-boot/board/nvidia/harmony/harmony.c b/roms/u-boot/board/nvidia/harmony/harmony.c
new file mode 100644
index 000000000..dd56a39ca
--- /dev/null
+++ b/roms/u-boot/board/nvidia/harmony/harmony.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
+	funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
+
+	/* For power GPIO PI6 */
+	pinmux_tristate_disable(PMUX_PINGRP_ATA);
+	/* For CD GPIO PH2 */
+	pinmux_tristate_disable(PMUX_PINGRP_ATD);
+
+	/* For power GPIO PT3 */
+	pinmux_tristate_disable(PMUX_PINGRP_DTB);
+	/* For CD GPIO PI5 */
+	pinmux_tristate_disable(PMUX_PINGRP_ATC);
+}
+#endif
+
+void pin_mux_usb(void)
+{
+	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+	pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+	pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+	/* USB2 PHY reset GPIO */
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
+}
+
+void pin_mux_display(void)
+{
+	pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
+	pinmux_tristate_disable(PMUX_PINGRP_SDC);
+}
diff --git a/roms/u-boot/board/nvidia/jetson-tk1/Kconfig b/roms/u-boot/board/nvidia/jetson-tk1/Kconfig
new file mode 100644
index 000000000..d90a74ea3
--- /dev/null
+++ b/roms/u-boot/board/nvidia/jetson-tk1/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_JETSON_TK1
+
+config SYS_BOARD
+	default "jetson-tk1"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "jetson-tk1"
+
+endif
diff --git a/roms/u-boot/board/nvidia/jetson-tk1/MAINTAINERS b/roms/u-boot/board/nvidia/jetson-tk1/MAINTAINERS
new file mode 100644
index 000000000..a5c687d14
--- /dev/null
+++ b/roms/u-boot/board/nvidia/jetson-tk1/MAINTAINERS
@@ -0,0 +1,6 @@
+JETSON-TK1 BOARD
+M:	Stephen Warren <swarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/jetson-tk1/
+F:	include/configs/jetson-tk1.h
+F:	configs/jetson-tk1_defconfig
diff --git a/roms/u-boot/board/nvidia/jetson-tk1/Makefile b/roms/u-boot/board/nvidia/jetson-tk1/Makefile
new file mode 100644
index 000000000..0f054117c
--- /dev/null
+++ b/roms/u-boot/board/nvidia/jetson-tk1/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= ../venice2/as3722_init.o
+obj-y	+= jetson-tk1.o
diff --git a/roms/u-boot/board/nvidia/jetson-tk1/jetson-tk1.c b/roms/u-boot/board/nvidia/jetson-tk1/jetson-tk1.c
new file mode 100644
index 000000000..d34953126
--- /dev/null
+++ b/roms/u-boot/board/nvidia/jetson-tk1/jetson-tk1.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <power/as3722.h>
+#include <power/pmic.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+
+#include "pinmux-config-jetson-tk1.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_clear_tristate_input_clamping();
+
+	gpio_config_table(jetson_tk1_gpio_inits,
+			  ARRAY_SIZE(jetson_tk1_gpio_inits));
+
+	pinmux_config_pingrp_table(jetson_tk1_pingrps,
+				   ARRAY_SIZE(jetson_tk1_pingrps));
+
+	pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
+				   ARRAY_SIZE(jetson_tk1_drvgrps));
+
+	pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps,
+					ARRAY_SIZE(jetson_tk1_mipipadctrlgrps));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+/* TODO: Convert to driver model */
+static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
+{
+	int err;
+
+	if (sd > 6)
+		return -EINVAL;
+
+	err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
+	if (err) {
+		pr_err("failed to update SD control register: %d", err);
+		return err;
+	}
+
+	return 0;
+}
+
+int tegra_pcie_board_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_PMIC,
+					  DM_DRIVER_GET(pmic_as3722), &dev);
+	if (ret) {
+		debug("%s: Failed to find PMIC\n", __func__);
+		return ret;
+	}
+
+	ret = as3722_sd_enable(dev, 4);
+	if (ret < 0) {
+		pr_err("failed to enable SD4: %d\n", ret);
+		return ret;
+	}
+
+	ret = as3722_sd_set_voltage(dev, 4, 0x24);
+	if (ret < 0) {
+		pr_err("failed to set SD4 voltage: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+#endif /* PCI */
diff --git a/roms/u-boot/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/roms/u-boot/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
new file mode 100644
index 000000000..fc5cdd1eb
--- /dev/null
+++ b/roms/u-boot/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ */
+
+/*
+ * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
+ *
+ * To generate this file, use the tegra-pinmux-scripts tool available from
+ * https://github.com/NVIDIA/tegra-pinmux-scripts
+ * Run "board-to-uboot.py jetson-tk1".
+ */
+
+#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
+#define _PINMUX_CONFIG_JETSON_TK1_H_
+
+#define GPIO_INIT(_port, _gpio, _init)			\
+	{						\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
+		.init	= TEGRA_GPIO_INIT_##_init,	\
+	}
+
+static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
+	/*        port, pin, init_val */
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(G,    4,   IN),
+	GPIO_INIT(H,    2,   OUT0),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    7,   IN),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    4,   OUT0),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(O,    1,   IN),
+	GPIO_INIT(O,    4,   IN),
+	GPIO_INIT(P,    2,   OUT0),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(Q,    5,   IN),
+	GPIO_INIT(R,    0,   OUT0),
+	GPIO_INIT(R,    2,   OUT0),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(R,    7,   IN),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(U,    0,   IN),
+	GPIO_INIT(U,    1,   IN),
+	GPIO_INIT(U,    2,   IN),
+	GPIO_INIT(U,    3,   IN),
+	GPIO_INIT(U,    4,   IN),
+	GPIO_INIT(U,    5,   IN),
+	GPIO_INIT(U,    6,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(V,    1,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    7,   OUT0),
+	GPIO_INIT(BB,   3,   OUT0),
+	GPIO_INIT(BB,   5,   OUT0),
+	GPIO_INIT(BB,   6,   OUT0),
+	GPIO_INIT(BB,   7,   OUT0),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   2,   IN),
+	GPIO_INIT(EE,   2,   OUT1),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
+	/*     pingrp,                 mux,          pull,   tri,      e_input, od,      rcv_sel */
+	PINCFG(CLK_32K_OUT_PA0,        SOC,          UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_CTS_N_PA1,        GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP2_FS_PA2,            I2S1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP2_SCLK_PA3,          I2S1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP2_DIN_PA4,           I2S1,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_DOUT_PA5,          I2S1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_PA6,         SDMMC3,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CMD_PA7,         SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PB0,                    UARTD,        UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PB1,                    UARTD,        UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT3_PB4,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT2_PB5,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT1_PB6,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT0_PB7,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_RTS_N_PC0,        GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_TXD_PC2,          IRDA,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_RXD_PC3,          IRDA,         UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GEN1_I2C_SCL_PC4,       I2C1,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN1_I2C_SDA_PC5,       I2C1,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PC7,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG0,                    DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG1,                    DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG2,                    DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG3,                    DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG4,                    DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG5,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG6,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG7,                    SPI4,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH0,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH1,                    PWM1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH2,                    DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH3,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH4,                    DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH5,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH6,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH7,                    DEFAULT,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI0,                    DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI1,                    DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI2,                    RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI3,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI4,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI5,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI6,                    DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI7,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ0,                    DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PJ2,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_CTS_N_PJ5,        UARTB,        UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART2_RTS_N_PJ6,        UARTB,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ7,                    UARTD,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK0,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK1,                    DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK2,                    DEFAULT,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PK3,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK4,                    DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_OUT_PK5,          RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_IN_PK6,           DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK7,                    UARTD,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_FS_PN0,            RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_DIN_PN1,           RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_DOUT_PN2,          SATA,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_SCLK_PN3,          RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN0_PN4,       USB,          NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(USB_VBUS_EN1_PN5,       USB,          NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(HDMI_INT_PN7,           DEFAULT,      DOWN,   TRISTATE, INPUT,   DEFAULT, NORMAL),
+	PINCFG(ULPI_DATA7_PO0,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA0_PO1,         DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA1_PO2,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA2_PO3,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA3_PO4,         DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA4_PO5,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA5_PO6,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA6_PO7,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_FS_PP0,            I2S2,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_DIN_PP1,           I2S2,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_DOUT_PP2,          DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_SCLK_PP3,          RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_FS_PP4,            RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DIN_PP5,           RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DOUT_PP6,          RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_SCLK_PP7,          RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL0_PQ0,            DEFAULT,      UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL1_PQ1,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL2_PQ2,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL3_PQ3,            DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL4_PQ4,            SDMMC3,       UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL5_PQ5,            DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL6_PQ6,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL7_PQ7,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW0_PR0,            DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW1_PR1,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW2_PR2,            DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW3_PR3,            KBC,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW4_PR4,            DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW5_PR5,            RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW6_PR6,            DISPLAYA_ALT, NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW7_PR7,            DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW8_PS0,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW9_PS1,            UARTA,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW10_PS2,           UARTA,        UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW11_PS3,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW12_PS4,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW13_PS5,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW14_PS6,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW15_PS7,           DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW16_PT0,           DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW17_PT1,           DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GEN2_I2C_SCL_PT5,       I2C2,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN2_I2C_SDA_PT6,       I2C2,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_CMD_PT7,         SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU0,                    DEFAULT,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU1,                    DEFAULT,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU2,                    DEFAULT,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU3,                    DEFAULT,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU4,                    DEFAULT,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU5,                    DEFAULT,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU6,                    DEFAULT,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PV0,                    DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PV1,                    DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CD_N_PV2,        SDMMC3,       UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_WP_N_PV3,        SDMMC1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DDC_SCL_PV4,            I2C4,         NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+	PINCFG(DDC_SDA_PV5,            I2C4,         NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+	PINCFG(GPIO_W2_AUD_PW2,        RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_W3_AUD_PW3,        SPI6,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_PW4,          EXTPERIPH1,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK2_OUT_PW5,           EXTPERIPH2,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART3_TXD_PW6,          RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART3_RXD_PW7,          RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DVFS_PWM_PX0,           CLDVFS,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X1_AUD_PX1,        DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DVFS_CLK_PX2,           CLDVFS,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X3_AUD_PX3,        RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X4_AUD_PX4,        DEFAULT,      NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GPIO_X5_AUD_PX5,        RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X6_AUD_PX6,        GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X7_AUD_PX7,        DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_CLK_PY0,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DIR_PY1,           SPI1,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_NXT_PY2,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_STP_PY3,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT3_PY4,        SDMMC1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT2_PY5,        SDMMC1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT1_PY6,        SDMMC1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT0_PY7,        RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CLK_PZ0,         RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CMD_PZ1,         SDMMC1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PWR_I2C_SCL_PZ6,        I2CPWR,       NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PWR_I2C_SDA_PZ7,        I2CPWR,       NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_DAT0_PAA0,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT1_PAA1,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT2_PAA2,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT3_PAA3,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT4_PAA4,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT5_PAA5,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT6_PAA6,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT7_PAA7,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PBB0,                   VIMCLK2_ALT,  NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CAM_I2C_SCL_PBB1,       I2C3,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(CAM_I2C_SDA_PBB2,       I2C3,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PBB3,                   DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB4,                   VGP4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB5,                   DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB6,                   DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB7,                   DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CAM_MCLK_PCC0,          VI_ALT3,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PCC1,                   DEFAULT,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PCC2,                   DEFAULT,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_CLK_PCC4,        SDMMC4,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK2_REQ_PCC5,          RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_RST_N_PDD1,      PE0,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_CLKREQ_N_PDD2,   PE0,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_WAKE_N_PDD3,        PE,           NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_RST_N_PDD5,      PE1,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_CLKREQ_N_PDD6,   PE1,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK3_OUT_PEE0,          EXTPERIPH3,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK3_REQ_PEE1,          RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_REQ_PEE2,     DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(HDMI_CEC_PEE3,          CEC,          NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DP_HPD_PFF0,            DP,           NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN2_PFF1,      RSVD2,        DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(PFF2,                   RSVD2,        DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(CORE_PWR_REQ,           PWRON,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CPU_PWR_REQ,            CPU,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PWR_INT_N,              PMI,          UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(RESET_OUT_N,            RESET_OUT_N,  NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK_32K_IN,             CLK,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(JTAG_RTCK,              RTCK,         UP,     NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{						\
+		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
+		.slwf   = _slwf,			\
+		.slwr   = _slwr,			\
+		.drvup  = _drvup,			\
+		.drvdn  = _drvdn,			\
+		.lpmd   = PMUX_LPMD_##_lpmd,		\
+		.schmt  = PMUX_SCHMT_##_schmt,		\
+		.hsm    = PMUX_HSM_##_hsm,		\
+	}
+
+static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
+};
+
+#define MIPIPADCTRLCFG(_grp, _mux) \
+	{							\
+		.grp		= PMUX_MIPIPADCTRLGRP_##_grp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+	}
+
+static const struct pmux_mipipadctrlgrp_config jetson_tk1_mipipadctrlgrps[] = {
+	/*             grp,   mux */
+	MIPIPADCTRLCFG(DSI_B, DSI_B),
+};
+
+#endif /* PINMUX_CONFIG_JETSON_TK1_H */
diff --git a/roms/u-boot/board/nvidia/nyan-big/Kconfig b/roms/u-boot/board/nvidia/nyan-big/Kconfig
new file mode 100644
index 000000000..341c8d75c
--- /dev/null
+++ b/roms/u-boot/board/nvidia/nyan-big/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NYAN_BIG
+
+config SYS_BOARD
+	default "nyan-big"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "nyan-big"
+
+endif
diff --git a/roms/u-boot/board/nvidia/nyan-big/MAINTAINERS b/roms/u-boot/board/nvidia/nyan-big/MAINTAINERS
new file mode 100644
index 000000000..779077729
--- /dev/null
+++ b/roms/u-boot/board/nvidia/nyan-big/MAINTAINERS
@@ -0,0 +1,6 @@
+NYAN-BIG BOARD
+M:	Allen Martin <amartin@nvidia.com>
+S:	Maintained
+F:	board/nvidia/nyan-big/
+F:	include/configs/nyan-big.h
+F:	configs/nyan-big_defconfig
diff --git a/roms/u-boot/board/nvidia/nyan-big/Makefile b/roms/u-boot/board/nvidia/nyan-big/Makefile
new file mode 100644
index 000000000..cd2f61dc9
--- /dev/null
+++ b/roms/u-boot/board/nvidia/nyan-big/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= ../venice2/as3722_init.o
+obj-y	+= nyan-big.o
diff --git a/roms/u-boot/board/nvidia/nyan-big/README b/roms/u-boot/board/nvidia/nyan-big/README
new file mode 100644
index 000000000..0e53d8d92
--- /dev/null
+++ b/roms/u-boot/board/nvidia/nyan-big/README
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2018 Google LLC
+# Written by Simon Glass <sjg@chromium.org>
+
+U-Boot on Nyan
+==============
+
+Nyan-big is supported by mainline U-Boot. This device is based on Tegra124.
+To build it, use the nyan-big config.
+
+To boot it, connect a USB A-A cable from your computer to the back USB port.
+Connect a servo board. Then with t20_rec and warn_rst held down:
+
+   sudo tegrarcm --bct cbootimage-configs/tegra124/nvidia/norrin/PM370_Hynix_2GB_H5TC4G63AFR_PBA_924MHz_01212014.bct
+	    --bootloader u-boot-dtb-tegra.bin --loadaddr 0x80108000
+
+The norrin config is close enough that it works well with Nyan.
diff --git a/roms/u-boot/board/nvidia/nyan-big/nyan-big.c b/roms/u-boot/board/nvidia/nyan-big/nyan-big.c
new file mode 100644
index 000000000..06a36f8ed
--- /dev/null
+++ b/roms/u-boot/board/nvidia/nyan-big/nyan-big.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <linux/delay.h>
+#include <power/as3722.h>
+#include <power/pmic.h>
+#include "pinmux-config-nyan-big.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	gpio_config_table(nyan_big_gpio_inits,
+			  ARRAY_SIZE(nyan_big_gpio_inits));
+
+	pinmux_config_pingrp_table(nyan_big_pingrps,
+				   ARRAY_SIZE(nyan_big_pingrps));
+
+	pinmux_config_drvgrp_table(nyan_big_drvgrps,
+				   ARRAY_SIZE(nyan_big_drvgrps));
+}
+
+int tegra_board_id(void)
+{
+	static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
+					TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
+					-1};
+
+	gpio_claim_vector(vector, "board_id%d");
+	return gpio_get_values_as_int(vector);
+}
+
+int tegra_lcd_pmic_init(int board_id)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_PMIC,
+					  DM_DRIVER_GET(pmic_as3722), &dev);
+	if (ret) {
+		debug("%s: Failed to find PMIC\n", __func__);
+		return ret;
+	}
+
+	if (board_id == 0)
+		pmic_reg_write(dev, 0x00, 0x3c);
+	else
+		pmic_reg_write(dev, 0x00, 0x50);
+	pmic_reg_write(dev, 0x12, 0x10);
+	pmic_reg_write(dev, 0x0c, 0x07);
+	pmic_reg_write(dev, 0x20, 0x10);
+
+	return 0;
+}
+
+/* Setup required information for Linux kernel */
+static void setup_kernel_info(void)
+{
+	struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
+
+	/* The kernel graphics driver needs this region locked down */
+	writel(0, &mc->mc_video_protect_bom);
+	writel(0, &mc->mc_video_protect_size_mb);
+	writel(1, &mc->mc_video_protect_reg_ctrl);
+}
+
+/*
+ * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
+ * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
+ * Otherwise reading AHUB devices will hang when the kernel boots.
+ */
+static void enable_required_clocks(void)
+{
+	static enum periph_id ids[] = {
+		PERIPH_ID_I2S0,
+		PERIPH_ID_I2S1,
+		PERIPH_ID_I2S2,
+		PERIPH_ID_I2S3,
+		PERIPH_ID_I2S4,
+		PERIPH_ID_AUDIO,
+		PERIPH_ID_APBIF,
+		PERIPH_ID_DAM0,
+		PERIPH_ID_DAM1,
+		PERIPH_ID_DAM2,
+		PERIPH_ID_AMX0,
+		PERIPH_ID_AMX1,
+		PERIPH_ID_ADX0,
+		PERIPH_ID_ADX1,
+		PERIPH_ID_SPDIF,
+		PERIPH_ID_AFC0,
+		PERIPH_ID_AFC1,
+		PERIPH_ID_AFC2,
+		PERIPH_ID_AFC3,
+		PERIPH_ID_AFC4,
+		PERIPH_ID_AFC5,
+		PERIPH_ID_EXTPERIPH1
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ids); i++)
+		clock_enable(ids[i]);
+	udelay(2);
+	for (i = 0; i < ARRAY_SIZE(ids); i++)
+		reset_set_enable(ids[i], 0);
+}
+
+int nvidia_board_init(void)
+{
+	clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
+	clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_CLK_M, 1500000);
+
+	/* For external MAX98090 audio codec */
+	clock_external_output(1);
+	setup_kernel_info();
+	enable_required_clocks();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/roms/u-boot/board/nvidia/nyan-big/pinmux-config-nyan-big.h
new file mode 100644
index 000000000..43c757e03
--- /dev/null
+++ b/roms/u-boot/board/nvidia/nyan-big/pinmux-config-nyan-big.h
@@ -0,0 +1,294 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ */
+
+/*
+ * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
+ *
+ * To generate this file, use the tegra-pinmux-scripts tool available from
+ * https://github.com/NVIDIA/tegra-pinmux-scripts
+ * Run "board-to-uboot.py nyan-big".
+ */
+
+#ifndef _PINMUX_CONFIG_NYAN_BIG_H_
+#define _PINMUX_CONFIG_NYAN_BIG_H_
+
+#define GPIO_INIT(_port, _gpio, _init)			\
+	{						\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
+		.init	= TEGRA_GPIO_INIT_##_init,	\
+	}
+
+static const struct tegra_gpio_config nyan_big_gpio_inits[] = {
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    0,   IN),
+	GPIO_INIT(C,    7,   IN),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    6,   IN),
+	GPIO_INIT(H,    7,   OUT1),
+	GPIO_INIT(I,    0,   IN),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    5,   OUT1),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(I,    7,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(J,    7,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    4,   OUT0),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(P,    2,   OUT0),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    2,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(Q,    6,   IN),
+	GPIO_INIT(Q,    7,   IN),
+	GPIO_INIT(R,    0,   OUT0),
+	GPIO_INIT(R,    1,   IN),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(R,    7,   IN),
+	GPIO_INIT(S,    3,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(U,    4,   IN),
+	GPIO_INIT(U,    5,   IN),
+	GPIO_INIT(U,    6,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(W,    3,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    7,   OUT0),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+static const struct pmux_pingrp_config nyan_big_pingrps[] = {
+	/*     pingrp,                 mux,         pull,   tri,      e_input, od,      rcv_sel */
+	PINCFG(CLK_32K_OUT_PA0,        DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_CTS_N_PA1,        GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP2_FS_PA2,            I2S1,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_SCLK_PA3,          I2S1,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_DIN_PA4,           I2S1,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_DOUT_PA5,          I2S1,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_PA6,         SDMMC3,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CMD_PA7,         SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PB0,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PB1,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT3_PB4,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT2_PB5,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT1_PB6,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT0_PB7,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_RTS_N_PC0,        GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_TXD_PC2,          IRDA,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_RXD_PC3,          IRDA,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GEN1_I2C_SCL_PC4,       I2C1,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN1_I2C_SDA_PC5,       I2C1,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PC7,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG0,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG1,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG2,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG3,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG4,                    SPI4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG5,                    SPI4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG6,                    SPI4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG7,                    SPI4,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH0,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH1,                    PWM1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH2,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH3,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH4,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH5,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH6,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH7,                    DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI0,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI1,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI2,                    RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI3,                    SPI4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI4,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI5,                    DEFAULT,     UP,     NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI6,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI7,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PJ0,                    DEFAULT,     UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PJ2,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_CTS_N_PJ5,        GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_RTS_N_PJ6,        GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ7,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PK0,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK1,                    DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK2,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PK3,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK4,                    DEFAULT,     UP,     NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_OUT_PK5,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_IN_PK6,           DEFAULT,     DOWN,   NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK7,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP1_FS_PN0,            RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_DIN_PN1,           RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_DOUT_PN2,          I2S0,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_SCLK_PN3,          RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN0_PN4,       USB,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(USB_VBUS_EN1_PN5,       USB,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(HDMI_INT_PN7,           DEFAULT,     DOWN,   NORMAL,   INPUT,   DEFAULT, NORMAL),
+	PINCFG(ULPI_DATA7_PO0,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA0_PO1,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA1_PO2,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA2_PO3,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA3_PO4,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA4_PO5,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA5_PO6,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA6_PO7,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_FS_PP0,            I2S2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_DIN_PP1,           I2S2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_DOUT_PP2,          DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_SCLK_PP3,          RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_FS_PP4,            RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DIN_PP5,           RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DOUT_PP6,          RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_SCLK_PP7,          RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL0_PQ0,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL1_PQ1,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL2_PQ2,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL3_PQ3,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL4_PQ4,            SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL5_PQ5,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL6_PQ6,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL7_PQ7,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW0_PR0,            DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW1_PR1,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW2_PR2,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW3_PR3,            KBC,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW4_PR4,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW5_PR5,            RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW6_PR6,            KBC,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW7_PR7,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW8_PS0,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW9_PS1,            UARTA,       DOWN,   NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW10_PS2,           UARTA,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW11_PS3,           DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW12_PS4,           DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW13_PS5,           RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW14_PS6,           RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW15_PS7,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW16_PT0,           RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW17_PT1,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GEN2_I2C_SCL_PT5,       I2C2,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN2_I2C_SDA_PT6,       I2C2,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_CMD_PT7,         SDMMC4,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU0,                    RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU1,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU2,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU3,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU4,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU5,                    DEFAULT,     UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU6,                    DEFAULT,     UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PV0,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PV1,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CD_N_PV2,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_WP_N_PV3,        SDMMC1,      DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DDC_SCL_PV4,            I2C4,        NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+	PINCFG(DDC_SDA_PV5,            I2C4,        NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+	PINCFG(GPIO_W2_AUD_PW2,        RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_W3_AUD_PW3,        DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_PW4,          EXTPERIPH1,  NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK2_OUT_PW5,           RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART3_TXD_PW6,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART3_RXD_PW7,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DVFS_PWM_PX0,           CLDVFS,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X1_AUD_PX1,        DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DVFS_CLK_PX2,           CLDVFS,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X3_AUD_PX3,        RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X4_AUD_PX4,        DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GPIO_X5_AUD_PX5,        RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X6_AUD_PX6,        GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X7_AUD_PX7,        DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_CLK_PY0,           SPI1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DIR_PY1,           SPI1,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_NXT_PY2,           SPI1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_STP_PY3,           SPI1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT3_PY4,        SDMMC1,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT2_PY5,        SDMMC1,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT1_PY6,        SDMMC1,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT0_PY7,        SDMMC1,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CLK_PZ0,         SDMMC1,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CMD_PZ1,         SDMMC1,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PWR_I2C_SCL_PZ6,        I2CPWR,      NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PWR_I2C_SDA_PZ7,        I2CPWR,      NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_DAT0_PAA0,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT1_PAA1,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT2_PAA2,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT3_PAA3,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT4_PAA4,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT5_PAA5,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT6_PAA6,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT7_PAA7,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PBB0,                   VGP6,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CAM_I2C_SCL_PBB1,       I2C3,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(CAM_I2C_SDA_PBB2,       I2C3,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PBB3,                   VGP3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB4,                   VGP4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB5,                   RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB6,                   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB7,                   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CAM_MCLK_PCC0,          VI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PCC1,                   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PCC2,                   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_CLK_PCC4,        SDMMC4,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK2_REQ_PCC5,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_RST_N_PDD1,      RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_CLKREQ_N_PDD2,   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_WAKE_N_PDD3,        RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_RST_N_PDD5,      RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_CLKREQ_N_PDD6,   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK3_OUT_PEE0,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK3_REQ_PEE1,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_REQ_PEE2,     RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(HDMI_CEC_PEE3,          CEC,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DP_HPD_PFF0,            DP,          NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN2_PFF1,      RSVD2,       DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(PFF2,                   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(CORE_PWR_REQ,           PWRON,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CPU_PWR_REQ,            CPU,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PWR_INT_N,              PMI,         NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(RESET_OUT_N,            RESET_OUT_N, NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(OWR,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, NORMAL),
+	PINCFG(CLK_32K_IN,             CLK,         NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(JTAG_RTCK,              RTCK,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{						\
+		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
+		.slwf   = _slwf,			\
+		.slwr   = _slwr,			\
+		.drvup  = _drvup,			\
+		.drvdn  = _drvdn,			\
+		.lpmd   = PMUX_LPMD_##_lpmd,		\
+		.schmt  = PMUX_SCHMT_##_schmt,		\
+		.hsm    = PMUX_HSM_##_hsm,		\
+	}
+
+static const struct pmux_drvgrp_config nyan_big_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_NYAN_BIG_H */
diff --git a/roms/u-boot/board/nvidia/p2371-0000/Kconfig b/roms/u-boot/board/nvidia/p2371-0000/Kconfig
new file mode 100644
index 000000000..f94be12be
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2371-0000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P2371_0000
+
+config SYS_BOARD
+	default "p2371-0000"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "p2371-0000"
+
+endif
diff --git a/roms/u-boot/board/nvidia/p2371-0000/MAINTAINERS b/roms/u-boot/board/nvidia/p2371-0000/MAINTAINERS
new file mode 100644
index 000000000..e6d04bf7c
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2371-0000/MAINTAINERS
@@ -0,0 +1,6 @@
+P2371-0000 BOARD
+M:	Tom Warren <twarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/p2371-0000/
+F:	include/configs/p2371-0000.h
+F:	configs/p2371-0000_defconfig
diff --git a/roms/u-boot/board/nvidia/p2371-0000/Makefile b/roms/u-boot/board/nvidia/p2371-0000/Makefile
new file mode 100644
index 000000000..9f580ae5b
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2371-0000/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013-2015
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= p2371-0000.o
diff --git a/roms/u-boot/board/nvidia/p2371-0000/p2371-0000.c b/roms/u-boot/board/nvidia/p2371-0000/p2371-0000.c
new file mode 100644
index 000000000..b819b049f
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2371-0000/p2371-0000.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013-2019
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <log.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "../p2571/max77620_init.h"
+
+void pin_mux_mmc(void)
+{
+	struct udevice *dev;
+	uchar val;
+	int ret;
+
+	/* Turn on MAX77620 LDO2 to 3.3V for SD card power */
+	debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
+	ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+		return;
+	}
+	/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+	val = 0xF2;
+	ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+}
diff --git a/roms/u-boot/board/nvidia/p2371-2180/Kconfig b/roms/u-boot/board/nvidia/p2371-2180/Kconfig
new file mode 100644
index 000000000..8622bdaa1
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2371-2180/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P2371_2180
+
+config SYS_BOARD
+	default "p2371-2180"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "p2371-2180"
+
+endif
diff --git a/roms/u-boot/board/nvidia/p2371-2180/MAINTAINERS b/roms/u-boot/board/nvidia/p2371-2180/MAINTAINERS
new file mode 100644
index 000000000..815377490
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2371-2180/MAINTAINERS
@@ -0,0 +1,6 @@
+P2371-2180 BOARD
+M:	Tom Warren <twarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/p2371-2180/
+F:	include/configs/p2371-2180.h
+F:	configs/p2371-2180_defconfig
diff --git a/roms/u-boot/board/nvidia/p2371-2180/Makefile b/roms/u-boot/board/nvidia/p2371-2180/Makefile
new file mode 100644
index 000000000..10aefb071
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2371-2180/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013-2015
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= p2371-2180.o
diff --git a/roms/u-boot/board/nvidia/p2371-2180/p2371-2180.c b/roms/u-boot/board/nvidia/p2371-2180/p2371-2180.c
new file mode 100644
index 000000000..7423a97ad
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2371-2180/p2371-2180.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013-2019
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <log.h>
+#include <net.h>
+#include <linux/bitops.h>
+#include <linux/libfdt.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/cboot.h>
+#include "../p2571/max77620_init.h"
+
+void pin_mux_mmc(void)
+{
+	struct udevice *dev;
+	uchar val;
+	int ret;
+
+	/* Turn on MAX77620 LDO2 to 3.3V for SD card power */
+	debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
+	ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+		return;
+	}
+	/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+	val = 0xF2;
+	ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+
+	/* Disable LDO4 discharge */
+	ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+	if (ret) {
+		printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
+	} else {
+		val &= ~BIT(1); /* ADE */
+		ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+		if (ret)
+			printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
+	}
+
+	/* Set MBLPD */
+	ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+	if (ret) {
+		printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+	} else {
+		val |= BIT(6); /* MBLPD */
+		ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+		if (ret)
+			printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+	}
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+	struct udevice *dev;
+	uchar val;
+	int ret;
+
+	/* Turn on MAX77620 LDO1 to 1.05V for PEX power */
+	debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__);
+	ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+		return -1;
+	}
+	/* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+	val = 0xCA;
+	ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret);
+
+	return 0;
+}
+#endif /* PCI */
+
+static void ft_mac_address_setup(void *fdt)
+{
+	const void *cboot_fdt = (const void *)cboot_boot_x0;
+	uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+	const char *path;
+	int offset, err;
+
+	err = cboot_get_ethaddr(cboot_fdt, local_mac);
+	if (err < 0)
+		memset(local_mac, 0, ETH_ALEN);
+
+	path = fdt_get_alias(fdt, "ethernet");
+	if (!path)
+		return;
+
+	debug("ethernet alias found: %s\n", path);
+
+	offset = fdt_path_offset(fdt, path);
+	if (offset < 0) {
+		printf("ethernet alias points to absent node %s\n", path);
+		return;
+	}
+
+	if (is_valid_ethaddr(local_mac)) {
+		err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+				  ETH_ALEN);
+		if (!err)
+			debug("Local MAC address set: %pM\n", local_mac);
+	}
+
+	if (eth_env_get_enetaddr("ethaddr", mac)) {
+		if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+			err = fdt_setprop(fdt, offset, "mac-address", mac,
+					  ETH_ALEN);
+			if (!err)
+				debug("MAC address set: %pM\n", mac);
+		}
+	}
+}
+
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
+{
+	struct fdt_memory fb;
+	int err;
+
+	err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
+	if (err < 0) {
+		if (err != -FDT_ERR_NOTFOUND)
+			printf("failed to get carveout for %s: %d\n", node,
+			       err);
+
+		return err;
+	}
+
+	err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
+				  &fb);
+	if (err < 0) {
+		printf("failed to set carveout for %s: %d\n", node, err);
+		return err;
+	}
+
+	return 0;
+}
+
+static void ft_carveout_setup(void *fdt)
+{
+	const void *cboot_fdt = (const void *)cboot_boot_x0;
+	static const char * const nodes[] = {
+		"/host1x@50000000/dc@54200000",
+		"/host1x@50000000/dc@54240000",
+	};
+	unsigned int i;
+	int err;
+
+	for (i = 0; i < ARRAY_SIZE(nodes); i++) {
+		err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
+		if (err < 0) {
+			if (err != -FDT_ERR_NOTFOUND)
+				printf("failed to copy carveout for %s: %d\n",
+				       nodes[i], err);
+			continue;
+		}
+	}
+}
+
+int ft_board_setup(void *fdt, struct bd_info *bd)
+{
+	ft_mac_address_setup(fdt);
+	ft_carveout_setup(fdt);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/nvidia/p2571/Kconfig b/roms/u-boot/board/nvidia/p2571/Kconfig
new file mode 100644
index 000000000..7bc487484
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2571/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P2571
+
+config SYS_BOARD
+	default "p2571"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "p2571"
+
+endif
diff --git a/roms/u-boot/board/nvidia/p2571/MAINTAINERS b/roms/u-boot/board/nvidia/p2571/MAINTAINERS
new file mode 100644
index 000000000..c165135a9
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2571/MAINTAINERS
@@ -0,0 +1,6 @@
+P2571 BOARD
+M:	Tom Warren <twarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/p2571/
+F:	include/configs/p2571.h
+F:	configs/p2571_defconfig
diff --git a/roms/u-boot/board/nvidia/p2571/Makefile b/roms/u-boot/board/nvidia/p2571/Makefile
new file mode 100644
index 000000000..627b7efa2
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2571/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013-2015
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= p2571.o
diff --git a/roms/u-boot/board/nvidia/p2571/max77620_init.h b/roms/u-boot/board/nvidia/p2571/max77620_init.h
new file mode 100644
index 000000000..ea5402c1c
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2571/max77620_init.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _MAX77620_INIT_H_
+#define _MAX77620_INIT_H_
+
+/* MAX77620-PMIC-specific early init regs */
+
+#define MAX77620_I2C_ADDR		0x78
+#define MAX77620_I2C_ADDR_7BIT		0x3C
+
+#define MAX77620_CNFGGLBL1_REG		0x00
+
+#define MAX77620_SD0_REG		0x16
+#define MAX77620_SD1_REG		0x17
+#define MAX77620_SD2_REG		0x18
+#define MAX77620_SD3_REG		0x19
+#define MAX77620_CNFG2SD_REG		0x22
+
+#define MAX77620_CNFG1_L0_REG		0x23
+#define MAX77620_CNFG2_L0_REG		0x24
+#define MAX77620_CNFG1_L1_REG		0x25
+#define MAX77620_CNFG2_L1_REG		0x26
+#define MAX77620_CNFG1_L2_REG		0x27
+#define MAX77620_CNFG2_L2_REG		0x28
+#define MAX77620_CNFG1_L3_REG		0x29
+#define MAX77620_CNFG2_L3_REG		0x2A
+#define MAX77620_CNFG1_L4_REG		0x2B
+#define MAX77620_CNFG2_L4_REG		0x2C
+#define MAX77620_CNFG1_L5_REG		0x2D
+#define MAX77620_CNFG2_L5_REG		0x2E
+#define MAX77620_CNFG1_L6_REG		0x2F
+#define MAX77620_CNFG2_L6_REG		0x30
+#define MAX77620_CNFG1_L7_REG		0x31
+#define MAX77620_CNFG2_L7_REG		0x32
+#define MAX77620_CNFG1_L8_REG		0x33
+#define MAX77620_CNFG2_L8_REG		0x34
+#define MAX77620_CNFG3_LDO_REG		0x35
+
+#define MAX77620_GPIO0_REG		0x36
+#define MAX77620_GPIO1_REG		0x37
+#define MAX77620_GPIO2_REG		0x38
+#define MAX77620_GPIO3_REG		0x39
+#define MAX77620_GPIO4_REG		0x3A
+#define MAX77620_GPIO5_REG		0x3B
+#define MAX77620_GPIO6_REG		0x3C
+#define MAX77620_GPIO7_REG		0x3D
+#define MAX77620_GPIO_PUE_GPIO		0x3E
+#define MAX77620_GPIO_PDE_GPIO		0x3F
+
+#define MAX77620_AME_GPIO		0x40
+#define MAX77620_REG_ONOFF_CFG1		0x41
+#define MAX77620_REG_ONOFF_CFG2		0x42
+
+#define MAX77620_CID0_REG		0x58
+#define MAX77620_CID1_REG		0x59
+#define MAX77620_CID2_REG		0x5A
+#define MAX77620_CID3_REG		0x5B
+#define MAX77620_CID4_REG		0x5C
+#define MAX77620_CID5_REG		0x5D
+
+#define I2C_SEND_2_BYTES	0x0A02
+
+void pmic_enable_cpu_vdd(void);
+
+#endif	/* _MAX77620_INIT_H_ */
diff --git a/roms/u-boot/board/nvidia/p2571/p2571.c b/roms/u-boot/board/nvidia/p2571/p2571.c
new file mode 100644
index 000000000..a4c4259ee
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2571/p2571.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013-2019
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <log.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
+#include "max77620_init.h"
+
+void pin_mux_mmc(void)
+{
+	struct udevice *dev;
+	uchar val;
+	int ret;
+
+	/* Turn on MAX77620 LDO2 to 3.3V for SD card power */
+	debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
+	ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+		return;
+	}
+	/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+	val = 0xF2;
+	ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+}
+
+/*
+ * Routine: start_cpu_fan
+ * Description: Enable/start PWM CPU fan on P2571
+ */
+void start_cpu_fan(void)
+{
+	/* GPIO_PE4 is PS_VDD_FAN_ENABLE */
+	gpio_request(TEGRA_GPIO(E, 4), "FAN_VDD");
+	gpio_direction_output(TEGRA_GPIO(E, 4), 1);
+}
diff --git a/roms/u-boot/board/nvidia/p2771-0000/Kconfig b/roms/u-boot/board/nvidia/p2771-0000/Kconfig
new file mode 100644
index 000000000..1b1116f02
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2771-0000/Kconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if TARGET_P2771_0000
+
+config SYS_BOARD
+	default "p2771-0000"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "p2771-0000"
+
+endif
diff --git a/roms/u-boot/board/nvidia/p2771-0000/MAINTAINERS b/roms/u-boot/board/nvidia/p2771-0000/MAINTAINERS
new file mode 100644
index 000000000..cf4913a9a
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2771-0000/MAINTAINERS
@@ -0,0 +1,7 @@
+P2771-0000 BOARD
+M:	Stephen Warren <swarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/p2771-0000/
+F:	include/configs/p2771-0000.h
+F:	configs/p2771-0000-000_defconfig
+F:	configs/p2771-0000-500_defconfig
diff --git a/roms/u-boot/board/nvidia/p2771-0000/Makefile b/roms/u-boot/board/nvidia/p2771-0000/Makefile
new file mode 100644
index 000000000..b28a47d90
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2771-0000/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y	+= p2771-0000.o
diff --git a/roms/u-boot/board/nvidia/p2771-0000/p2771-0000.c b/roms/u-boot/board/nvidia/p2771-0000/p2771-0000.c
new file mode 100644
index 000000000..508c4d27b
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p2771-0000/p2771-0000.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION
+ */
+
+#include <common.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <log.h>
+#include <net.h>
+#include <linux/libfdt.h>
+#include <asm/arch-tegra/cboot.h>
+#include "../p2571/max77620_init.h"
+
+void pin_mux_mmc(void)
+{
+	struct udevice *dev;
+	uchar val;
+	int ret;
+
+	/* Turn on MAX77620 LDO3 to 3.3V for SD card power */
+	debug("%s: Set LDO3 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
+	ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+		return;
+	}
+	/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+	val = 0xF2;
+	ret = dm_i2c_write(dev, MAX77620_CNFG1_L3_REG, &val, 1);
+	if (ret) {
+		printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+		return;
+	}
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+	struct udevice *dev;
+	uchar val;
+	int ret;
+
+	/* Turn on MAX77620 LDO7 to 1.05V for PEX power */
+	debug("%s: Set LDO7 for PEX power to 1.05V\n", __func__);
+	ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+		return -1;
+	}
+	/* 0xC5 for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+	val = 0xC5;
+	ret = dm_i2c_write(dev, MAX77620_CNFG1_L7_REG, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x3c 0x31 failed: %d\n", ret);
+
+	return 0;
+}
+#endif
+
+static void ft_mac_address_setup(void *fdt)
+{
+	const void *cboot_fdt = (const void *)cboot_boot_x0;
+	uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+	const char *path;
+	int offset, err;
+
+	err = cboot_get_ethaddr(cboot_fdt, local_mac);
+	if (err < 0)
+		memset(local_mac, 0, ETH_ALEN);
+
+	path = fdt_get_alias(fdt, "ethernet");
+	if (!path)
+		return;
+
+	debug("ethernet alias found: %s\n", path);
+
+	offset = fdt_path_offset(fdt, path);
+	if (offset < 0) {
+		printf("ethernet alias points to absent node %s\n", path);
+		return;
+	}
+
+	if (is_valid_ethaddr(local_mac)) {
+		err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+				  ETH_ALEN);
+		if (!err)
+			debug("Local MAC address set: %pM\n", local_mac);
+	}
+
+	if (eth_env_get_enetaddr("ethaddr", mac)) {
+		if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+			err = fdt_setprop(fdt, offset, "mac-address", mac,
+					  ETH_ALEN);
+			if (!err)
+				debug("MAC address set: %pM\n", mac);
+		}
+	}
+}
+
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
+{
+	struct fdt_memory fb;
+	int err;
+
+	err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
+	if (err < 0) {
+		if (err != -FDT_ERR_NOTFOUND)
+			printf("failed to get carveout for %s: %d\n", node,
+			       err);
+
+		return err;
+	}
+
+	err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
+				  &fb);
+	if (err < 0) {
+		printf("failed to set carveout for %s: %d\n", node, err);
+		return err;
+	}
+
+	return 0;
+}
+
+static void ft_carveout_setup(void *fdt)
+{
+	const void *cboot_fdt = (const void *)cboot_boot_x0;
+	static const char * const nodes[] = {
+		"/host1x@13e00000/display-hub@15200000/display@15200000",
+		"/host1x@13e00000/display-hub@15200000/display@15210000",
+		"/host1x@13e00000/display-hub@15200000/display@15220000",
+	};
+	unsigned int i;
+	int err;
+
+	for (i = 0; i < ARRAY_SIZE(nodes); i++) {
+		printf("copying carveout for %s...\n", nodes[i]);
+
+		err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
+		if (err < 0) {
+			if (err != -FDT_ERR_NOTFOUND)
+				printf("failed to copy carveout for %s: %d\n",
+				       nodes[i], err);
+
+			continue;
+		}
+	}
+}
+
+int ft_board_setup(void *fdt, struct bd_info *bd)
+{
+	ft_mac_address_setup(fdt);
+	ft_carveout_setup(fdt);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/nvidia/p3450-0000/Kconfig b/roms/u-boot/board/nvidia/p3450-0000/Kconfig
new file mode 100644
index 000000000..7a08cd886
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p3450-0000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P3450_0000
+
+config SYS_BOARD
+	default "p3450-0000"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "p3450-0000"
+
+endif
diff --git a/roms/u-boot/board/nvidia/p3450-0000/MAINTAINERS b/roms/u-boot/board/nvidia/p3450-0000/MAINTAINERS
new file mode 100644
index 000000000..40700066b
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p3450-0000/MAINTAINERS
@@ -0,0 +1,6 @@
+P3450-0000 BOARD
+M:	Tom Warren <twarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/p3450-0000/
+F:	include/configs/p3450-0000.h
+F:	configs/p3450-0000_defconfig
diff --git a/roms/u-boot/board/nvidia/p3450-0000/Makefile b/roms/u-boot/board/nvidia/p3450-0000/Makefile
new file mode 100644
index 000000000..993c506d8
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p3450-0000/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2018
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= p3450-0000.o
diff --git a/roms/u-boot/board/nvidia/p3450-0000/p3450-0000.c b/roms/u-boot/board/nvidia/p3450-0000/p3450-0000.c
new file mode 100644
index 000000000..e6b66966c
--- /dev/null
+++ b/roms/u-boot/board/nvidia/p3450-0000/p3450-0000.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <linux/bitops.h>
+#include <linux/libfdt.h>
+#include <pca953x.h>
+#include <asm/arch-tegra/cboot.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "../p2571/max77620_init.h"
+
+void pin_mux_mmc(void)
+{
+	struct udevice *dev;
+	uchar val;
+	int ret;
+
+	/* Turn on MAX77620 LDO2 to 3.3V for SD card power */
+	debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
+	ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+		return;
+	}
+	/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+	val = 0xF2;
+	ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+
+	/* Disable LDO4 discharge */
+	ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+	if (ret) {
+		printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
+	} else {
+		val &= ~BIT(1); /* ADE */
+		ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+		if (ret)
+			printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
+	}
+
+	/* Set MBLPD */
+	ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+	if (ret) {
+		printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+	} else {
+		val |= BIT(6); /* MBLPD */
+		ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+		if (ret)
+			printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+	}
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+	struct udevice *dev;
+	uchar val;
+	int ret;
+
+	/* Turn on MAX77620 LDO1 to 1.05V for PEX power */
+	debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__);
+	ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+		return -1;
+	}
+	/* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+	val = 0xCA;
+	ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret);
+
+	return 0;
+}
+#endif /* PCI */
+
+static void ft_mac_address_setup(void *fdt)
+{
+	const void *cboot_fdt = (const void *)cboot_boot_x0;
+	uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+	const char *path;
+	int offset, err;
+
+	err = cboot_get_ethaddr(cboot_fdt, local_mac);
+	if (err < 0)
+		memset(local_mac, 0, ETH_ALEN);
+
+	path = fdt_get_alias(fdt, "ethernet");
+	if (!path)
+		return;
+
+	debug("ethernet alias found: %s\n", path);
+
+	offset = fdt_path_offset(fdt, path);
+	if (offset < 0) {
+		printf("ethernet alias points to absent node %s\n", path);
+		return;
+	}
+
+	if (is_valid_ethaddr(local_mac)) {
+		err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+				  ETH_ALEN);
+		if (!err)
+			debug("Local MAC address set: %pM\n", local_mac);
+	}
+
+	if (eth_env_get_enetaddr("ethaddr", mac)) {
+		if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+			err = fdt_setprop(fdt, offset, "mac-address", mac,
+					  ETH_ALEN);
+			if (!err)
+				debug("MAC address set: %pM\n", mac);
+		}
+	}
+}
+
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
+{
+	struct fdt_memory fb;
+	int err;
+
+	err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
+	if (err < 0) {
+		if (err != -FDT_ERR_NOTFOUND)
+			printf("failed to get carveout for %s: %d\n", node,
+			       err);
+
+		return err;
+	}
+
+	err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
+				  &fb);
+	if (err < 0) {
+		printf("failed to set carveout for %s: %d\n", node, err);
+		return err;
+	}
+
+	return 0;
+}
+
+static void ft_carveout_setup(void *fdt)
+{
+	const void *cboot_fdt = (const void *)cboot_boot_x0;
+	static const char * const nodes[] = {
+		"/host1x@50000000/dc@54200000",
+		"/host1x@50000000/dc@54240000",
+	};
+	unsigned int i;
+	int err;
+
+	for (i = 0; i < ARRAY_SIZE(nodes); i++) {
+		printf("copying carveout for %s...\n", nodes[i]);
+
+		err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
+		if (err < 0) {
+			if (err != -FDT_ERR_NOTFOUND)
+				printf("failed to copy carveout for %s: %d\n",
+				       nodes[i], err);
+
+			continue;
+		}
+	}
+}
+
+int ft_board_setup(void *fdt, struct bd_info *bd)
+{
+	ft_mac_address_setup(fdt);
+	ft_carveout_setup(fdt);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/nvidia/seaboard/Kconfig b/roms/u-boot/board/nvidia/seaboard/Kconfig
new file mode 100644
index 000000000..0924bde48
--- /dev/null
+++ b/roms/u-boot/board/nvidia/seaboard/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SEABOARD
+
+config SYS_BOARD
+	default "seaboard"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "seaboard"
+
+endif
diff --git a/roms/u-boot/board/nvidia/seaboard/MAINTAINERS b/roms/u-boot/board/nvidia/seaboard/MAINTAINERS
new file mode 100644
index 000000000..7926ca19a
--- /dev/null
+++ b/roms/u-boot/board/nvidia/seaboard/MAINTAINERS
@@ -0,0 +1,6 @@
+SEABOARD BOARD
+M:	Tom Warren <twarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/seaboard/
+F:	include/configs/seaboard.h
+F:	configs/seaboard_defconfig
diff --git a/roms/u-boot/board/nvidia/seaboard/Makefile b/roms/u-boot/board/nvidia/seaboard/Makefile
new file mode 100644
index 000000000..7793e7272
--- /dev/null
+++ b/roms/u-boot/board/nvidia/seaboard/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2010,2011
+#  NVIDIA Corporation <www.nvidia.com>
+
+obj-y	:= seaboard.o
diff --git a/roms/u-boot/board/nvidia/seaboard/seaboard.c b/roms/u-boot/board/nvidia/seaboard/seaboard.c
new file mode 100644
index 000000000..b88aa8e96
--- /dev/null
+++ b/roms/u-boot/board/nvidia/seaboard/seaboard.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
+
+/* TODO: Remove this code when the SPI switch is working */
+#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
+void gpio_early_init_uart(void)
+{
+	/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
+	gpio_request(TEGRA_GPIO(I, 3), "uart_en");
+	gpio_direction_output(TEGRA_GPIO(I, 3), 0);
+}
+#endif
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
+	funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
+
+	/* For power GPIO PI6 */
+	pinmux_tristate_disable(PMUX_PINGRP_ATA);
+	/* For CD GPIO PI5 */
+	pinmux_tristate_disable(PMUX_PINGRP_ATC);
+}
+#endif
+
+void pin_mux_usb(void)
+{
+	/* For USB0's GPIO PD0. For now, since we have no pinmux in fdt */
+	pinmux_tristate_disable(PMUX_PINGRP_SLXK);
+	/* For USB1's ULPI signals */
+	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+	pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+	pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+	/* USB1 PHY reset GPIO */
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
+}
diff --git a/roms/u-boot/board/nvidia/venice2/Kconfig b/roms/u-boot/board/nvidia/venice2/Kconfig
new file mode 100644
index 000000000..6905f0014
--- /dev/null
+++ b/roms/u-boot/board/nvidia/venice2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VENICE2
+
+config SYS_BOARD
+	default "venice2"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "venice2"
+
+endif
diff --git a/roms/u-boot/board/nvidia/venice2/MAINTAINERS b/roms/u-boot/board/nvidia/venice2/MAINTAINERS
new file mode 100644
index 000000000..221df654d
--- /dev/null
+++ b/roms/u-boot/board/nvidia/venice2/MAINTAINERS
@@ -0,0 +1,6 @@
+VENICE2 BOARD
+M:	Tom Warren <twarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/venice2/
+F:	include/configs/venice2.h
+F:	configs/venice2_defconfig
diff --git a/roms/u-boot/board/nvidia/venice2/Makefile b/roms/u-boot/board/nvidia/venice2/Makefile
new file mode 100644
index 000000000..5fac5ab1f
--- /dev/null
+++ b/roms/u-boot/board/nvidia/venice2/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= as3722_init.o
+obj-y	+= venice2.o
diff --git a/roms/u-boot/board/nvidia/venice2/as3722_init.c b/roms/u-boot/board/nvidia/venice2/as3722_init.c
new file mode 100644
index 000000000..ba676547d
--- /dev/null
+++ b/roms/u-boot/board/nvidia/venice2/as3722_init.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+#include "as3722_init.h"
+
+/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(addr, &reg->cmd_addr0);
+	writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(data, &reg->cmd_data1);
+	writel(config, &reg->cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+	debug("%s entry\n", __func__);
+
+#ifdef AS3722_SD1VOLTAGE_DATA
+	/* Set up VDD_CORE, for boards where OTP is incorrect*/
+	debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
+	/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+#endif
+
+	debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
+	/*
+	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
+	/*
+	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
+	/*
+	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.2V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
+	/*
+	 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to bypass 3.3V straight thru, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+}
diff --git a/roms/u-boot/board/nvidia/venice2/as3722_init.h b/roms/u-boot/board/nvidia/venice2/as3722_init.h
new file mode 100644
index 000000000..17e7d76ae
--- /dev/null
+++ b/roms/u-boot/board/nvidia/venice2/as3722_init.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+/* AS3722-PMIC-specific early init regs */
+
+#define AS3722_I2C_ADDR		0x80
+
+#define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
+#define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
+#define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
+#define AS3722_SDCONTROL_REG	0x4D
+
+#define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
+#define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC */
+#define AS3722_LDCONTROL_REG	0x4E
+
+#if defined(CONFIG_TARGET_VENICE2)
+#define AS3722_SD0VOLTAGE_DATA	(0x2800 | AS3722_SD0VOLTAGE_REG)
+#else /* TK1 or Nyan-Big */
+#define AS3722_SD0VOLTAGE_DATA	(0x3C00 | AS3722_SD0VOLTAGE_REG)
+#endif
+#define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
+
+#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_CEI_TK1_SOM)
+#define AS3722_SD1VOLTAGE_DATA	(0x2800 | AS3722_SD1VOLTAGE_REG)
+#define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
+#endif
+
+#define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
+#define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
+
+#define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
+
+#define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
+
+#define I2C_SEND_2_BYTES	0x0A02
+
+void pmic_enable_cpu_vdd(void);
diff --git a/roms/u-boot/board/nvidia/venice2/pinmux-config-venice2.h b/roms/u-boot/board/nvidia/venice2/pinmux-config-venice2.h
new file mode 100644
index 000000000..fc7fea406
--- /dev/null
+++ b/roms/u-boot/board/nvidia/venice2/pinmux-config-venice2.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ */
+
+/*
+ * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
+ *
+ * To generate this file, use the tegra-pinmux-scripts tool available from
+ * https://github.com/NVIDIA/tegra-pinmux-scripts
+ * Run "board-to-uboot.py venice2".
+ */
+
+#ifndef _PINMUX_CONFIG_VENICE2_H_
+#define _PINMUX_CONFIG_VENICE2_H_
+
+#define GPIO_INIT(_port, _gpio, _init)			\
+	{						\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
+		.init	= TEGRA_GPIO_INIT_##_init,	\
+	}
+
+static const struct tegra_gpio_config venice2_gpio_inits[] = {
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    0,   IN),
+	GPIO_INIT(C,    7,   IN),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    5,   OUT0),
+	GPIO_INIT(H,    6,   IN),
+	GPIO_INIT(H,    7,   OUT1),
+	GPIO_INIT(I,    0,   IN),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(I,    4,   OUT0),
+	GPIO_INIT(I,    5,   OUT1),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(J,    7,   IN),
+	GPIO_INIT(K,    0,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    3,   IN),
+	GPIO_INIT(K,    4,   OUT0),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(O,    2,   IN),
+	GPIO_INIT(O,    5,   IN),
+	GPIO_INIT(O,    6,   OUT0),
+	GPIO_INIT(O,    7,   IN),
+	GPIO_INIT(P,    2,   OUT0),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    2,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(Q,    6,   IN),
+	GPIO_INIT(Q,    7,   IN),
+	GPIO_INIT(R,    0,   OUT0),
+	GPIO_INIT(R,    1,   IN),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(S,    0,   IN),
+	GPIO_INIT(S,    3,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(U,    4,   IN),
+	GPIO_INIT(U,    5,   IN),
+	GPIO_INIT(U,    6,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(V,    1,   IN),
+	GPIO_INIT(W,    3,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    7,   OUT0),
+	GPIO_INIT(CC,   5,   OUT0),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+static const struct pmux_pingrp_config venice2_pingrps[] = {
+	/*     pingrp,                 mux,         pull,   tri,      e_input, od,      rcv_sel */
+	PINCFG(CLK_32K_OUT_PA0,        DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_CTS_N_PA1,        UARTC,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_FS_PA2,            I2S1,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_SCLK_PA3,          I2S1,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_DIN_PA4,           I2S1,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_DOUT_PA5,          I2S1,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_PA6,         SDMMC3,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CMD_PA7,         SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PB0,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PB1,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT3_PB4,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT2_PB5,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT1_PB6,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT0_PB7,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_RTS_N_PC0,        UARTC,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_TXD_PC2,          IRDA,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_RXD_PC3,          IRDA,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GEN1_I2C_SCL_PC4,       I2C1,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN1_I2C_SDA_PC5,       I2C1,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PC7,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG0,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG1,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG2,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG3,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PG4,                    SPI4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG5,                    SPI4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG6,                    SPI4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG7,                    SPI4,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH0,                    PWM0,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH1,                    PWM1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH2,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH3,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH4,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH5,                    DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH6,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH7,                    DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI0,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI1,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI2,                    DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI3,                    SPI4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI4,                    DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI5,                    DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI6,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI7,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ0,                    DEFAULT,     UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PJ2,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_CTS_N_PJ5,        UARTB,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART2_RTS_N_PJ6,        UARTB,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ7,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PK0,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PK1,                    DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK2,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PK3,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PK4,                    DEFAULT,     UP,     NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_OUT_PK5,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_IN_PK6,           DEFAULT,     DOWN,   NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK7,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP1_FS_PN0,            I2S0,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP1_DIN_PN1,           I2S0,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP1_DOUT_PN2,          I2S0,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP1_SCLK_PN3,          I2S0,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN0_PN4,       USB,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(USB_VBUS_EN1_PN5,       USB,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(HDMI_INT_PN7,           DEFAULT,     DOWN,   NORMAL,   INPUT,   DEFAULT, NORMAL),
+	PINCFG(ULPI_DATA7_PO0,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA0_PO1,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA1_PO2,         DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA2_PO3,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA3_PO4,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA4_PO5,         DEFAULT,     UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA5_PO6,         DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA6_PO7,         DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP3_FS_PP0,            I2S2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_DIN_PP1,           I2S2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_DOUT_PP2,          DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_SCLK_PP3,          RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_FS_PP4,            I2S3,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DIN_PP5,           I2S3,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP4_DOUT_PP6,          I2S3,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_SCLK_PP7,          I2S3,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL0_PQ0,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL1_PQ1,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL2_PQ2,            DEFAULT,     UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL3_PQ3,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL4_PQ4,            SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL5_PQ5,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL6_PQ6,            DEFAULT,     UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_COL7_PQ7,            DEFAULT,     UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW0_PR0,            DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW1_PR1,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW2_PR2,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW3_PR3,            KBC,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW4_PR4,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW5_PR5,            RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW6_PR6,            KBC,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW7_PR7,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW8_PS0,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW9_PS1,            UARTA,       DOWN,   NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW10_PS2,           UARTA,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW11_PS3,           DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW12_PS4,           DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW13_PS5,           RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW14_PS6,           RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW15_PS7,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(KB_ROW16_PT0,           RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW17_PT1,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GEN2_I2C_SCL_PT5,       I2C2,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN2_I2C_SDA_PT6,       I2C2,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_CMD_PT7,         SDMMC4,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU0,                    UARTA,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU1,                    UARTA,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU2,                    UARTA,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU3,                    UARTA,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU4,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU5,                    DEFAULT,     UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU6,                    DEFAULT,     UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PV0,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PV1,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CD_N_PV2,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_WP_N_PV3,        SDMMC1,      DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DDC_SCL_PV4,            I2C4,        NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+	PINCFG(DDC_SDA_PV5,            I2C4,        NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+	PINCFG(GPIO_W2_AUD_PW2,        RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_W3_AUD_PW3,        DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_PW4,          EXTPERIPH1,  NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK2_OUT_PW5,           RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART3_TXD_PW6,          UARTC,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART3_RXD_PW7,          UARTC,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DVFS_PWM_PX0,           CLDVFS,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X1_AUD_PX1,        DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DVFS_CLK_PX2,           CLDVFS,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X3_AUD_PX3,        DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GPIO_X4_AUD_PX4,        DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GPIO_X5_AUD_PX5,        RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X6_AUD_PX6,        GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X7_AUD_PX7,        DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_CLK_PY0,           SPI1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DIR_PY1,           SPI1,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_NXT_PY2,           SPI1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_STP_PY3,           SPI1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT3_PY4,        SDMMC1,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT2_PY5,        SDMMC1,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT1_PY6,        SDMMC1,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT0_PY7,        SDMMC1,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CLK_PZ0,         SDMMC1,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CMD_PZ1,         SDMMC1,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PWR_I2C_SCL_PZ6,        I2CPWR,      NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PWR_I2C_SDA_PZ7,        I2CPWR,      NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_DAT0_PAA0,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT1_PAA1,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT2_PAA2,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT3_PAA3,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT4_PAA4,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT5_PAA5,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT6_PAA6,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT7_PAA7,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PBB0,                   VGP6,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CAM_I2C_SCL_PBB1,       I2C3,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(CAM_I2C_SDA_PBB2,       I2C3,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PBB3,                   VGP3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB4,                   VGP4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB5,                   RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB6,                   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB7,                   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CAM_MCLK_PCC0,          VI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PCC1,                   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PCC2,                   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_CLK_PCC4,        SDMMC4,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK2_REQ_PCC5,          DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_RST_N_PDD1,      RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_CLKREQ_N_PDD2,   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_WAKE_N_PDD3,        RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_RST_N_PDD5,      RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_CLKREQ_N_PDD6,   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK3_OUT_PEE0,          EXTPERIPH3,  NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK3_REQ_PEE1,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_REQ_PEE2,     RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(HDMI_CEC_PEE3,          CEC,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DP_HPD_PFF0,            DP,          UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN2_PFF1,      RSVD2,       DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(PFF2,                   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(CORE_PWR_REQ,           PWRON,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CPU_PWR_REQ,            CPU,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PWR_INT_N,              PMI,         NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(RESET_OUT_N,            RESET_OUT_N, NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(OWR,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, NORMAL),
+	PINCFG(CLK_32K_IN,             CLK,         NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(JTAG_RTCK,              RTCK,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{						\
+		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
+		.slwf   = _slwf,			\
+		.slwr   = _slwr,			\
+		.drvup  = _drvup,			\
+		.drvdn  = _drvdn,			\
+		.lpmd   = PMUX_LPMD_##_lpmd,		\
+		.schmt  = PMUX_SCHMT_##_schmt,		\
+		.hsm    = PMUX_HSM_##_hsm,		\
+	}
+
+static const struct pmux_drvgrp_config venice2_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_VENICE2_H */
diff --git a/roms/u-boot/board/nvidia/venice2/venice2.c b/roms/u-boot/board/nvidia/venice2/venice2.c
new file mode 100644
index 000000000..d89bbe5ec
--- /dev/null
+++ b/roms/u-boot/board/nvidia/venice2/venice2.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-venice2.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_set_tristate_input_clamping();
+
+	gpio_config_table(venice2_gpio_inits,
+			  ARRAY_SIZE(venice2_gpio_inits));
+
+	pinmux_config_pingrp_table(venice2_pingrps,
+				   ARRAY_SIZE(venice2_pingrps));
+
+	pinmux_config_drvgrp_table(venice2_drvgrps,
+				   ARRAY_SIZE(venice2_drvgrps));
+}
diff --git a/roms/u-boot/board/nvidia/ventana/Kconfig b/roms/u-boot/board/nvidia/ventana/Kconfig
new file mode 100644
index 000000000..c1ad7b767
--- /dev/null
+++ b/roms/u-boot/board/nvidia/ventana/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VENTANA
+
+config SYS_BOARD
+	default "ventana"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "ventana"
+
+endif
diff --git a/roms/u-boot/board/nvidia/ventana/MAINTAINERS b/roms/u-boot/board/nvidia/ventana/MAINTAINERS
new file mode 100644
index 000000000..285b84dbd
--- /dev/null
+++ b/roms/u-boot/board/nvidia/ventana/MAINTAINERS
@@ -0,0 +1,7 @@
+VENTANA BOARD
+M:	Tom Warren <twarren@nvidia.com>
+M:	Stephen Warren <swarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/ventana/
+F:	include/configs/ventana.h
+F:	configs/ventana_defconfig
diff --git a/roms/u-boot/board/nvidia/ventana/Makefile b/roms/u-boot/board/nvidia/ventana/Makefile
new file mode 100644
index 000000000..3bec3fe33
--- /dev/null
+++ b/roms/u-boot/board/nvidia/ventana/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2010,2011
+#  NVIDIA Corporation <www.nvidia.com>
+
+obj-y	= ../seaboard/seaboard.o
diff --git a/roms/u-boot/board/olimex/mx23_olinuxino/Kconfig b/roms/u-boot/board/olimex/mx23_olinuxino/Kconfig
new file mode 100644
index 000000000..0b151c9bb
--- /dev/null
+++ b/roms/u-boot/board/olimex/mx23_olinuxino/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX23_OLINUXINO
+
+config SYS_BOARD
+	default "mx23_olinuxino"
+
+config SYS_VENDOR
+	default "olimex"
+
+config SYS_SOC
+	default "mxs"
+
+config SYS_CONFIG_NAME
+	default "mx23_olinuxino"
+
+endif
diff --git a/roms/u-boot/board/olimex/mx23_olinuxino/MAINTAINERS b/roms/u-boot/board/olimex/mx23_olinuxino/MAINTAINERS
new file mode 100644
index 000000000..25f4a10e9
--- /dev/null
+++ b/roms/u-boot/board/olimex/mx23_olinuxino/MAINTAINERS
@@ -0,0 +1,6 @@
+MX23_OLINUXINO BOARD
+M:	Marek Vasut <marek.vasut@gmail.com>
+S:	Maintained
+F:	board/olimex/mx23_olinuxino/
+F:	include/configs/mx23_olinuxino.h
+F:	configs/mx23_olinuxino_defconfig
diff --git a/roms/u-boot/board/olimex/mx23_olinuxino/Makefile b/roms/u-boot/board/olimex/mx23_olinuxino/Makefile
new file mode 100644
index 000000000..b2ea89743
--- /dev/null
+++ b/roms/u-boot/board/olimex/mx23_olinuxino/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ifndef	CONFIG_SPL_BUILD
+obj-y	:= mx23_olinuxino.o
+else
+obj-y	:= spl_boot.o
+endif
diff --git a/roms/u-boot/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/roms/u-boot/board/olimex/mx23_olinuxino/mx23_olinuxino.c
new file mode 100644
index 000000000..bdd5fcd76
--- /dev/null
+++ b/roms/u-boot/board/olimex/mx23_olinuxino/mx23_olinuxino.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Olimex MX23 Olinuxino board
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#ifdef CONFIG_LED_STATUS
+#include <status_led.h>
+#endif
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+
+	/* SSP0 clock at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_USB
+int board_ehci_hcd_init(int port)
+{
+	/* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
+	gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1);
+	udelay(100);
+	return 0;
+}
+
+int board_ehci_hcd_exit(int port)
+{
+	/* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
+	gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 0);
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
+	status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_STATE);
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/olimex/mx23_olinuxino/spl_boot.c b/roms/u-boot/board/olimex/mx23_olinuxino/spl_boot.c
new file mode 100644
index 000000000..248176c23
--- /dev/null
+++ b/roms/u-boot/board/olimex/mx23_olinuxino/spl_boot.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Olimex MX23 Olinuxino Boot setup
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP	(MXS_PAD_8MA | MXS_PAD_PULLUP)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* DUART */
+	MX23_PAD_PWM0__DUART_RX,
+	MX23_PAD_PWM1__DUART_TX,
+
+	/* EMI */
+	MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
+
+	MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+
+	MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+
+	/* Green LED */
+	MX23_PAD_SSP1_DETECT__GPIO_2_1 |
+		(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL),
+
+	/* MMC 0 */
+	MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
+	MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
+	MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
+	MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
+	MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
+	MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
+
+	/* Ethernet */
+	MX23_PAD_GPMI_ALE__GPIO_0_17 |
+		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+};
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
+
+/* Fine-tune the DRAM configuration. */
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+	/* Enable Auto Precharge. */
+	dram_vals[3] |= 1 << 8;
+	/* Enable Fast Writes. */
+	dram_vals[5] |= 1 << 8;
+	/* tEMRS = 3*tCK */
+	dram_vals[10] &= ~(0x3 << 8);
+	dram_vals[10] |= (0x3 << 8);
+	/* CASLAT = 3*tCK */
+	dram_vals[11] &= ~(0x3 << 0);
+	dram_vals[11] |= (0x3 << 0);
+	/* tCKE = 1*tCK */
+	dram_vals[12] &= ~(0x7 << 0);
+	dram_vals[12] |= (0x1 << 0);
+	/* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
+	dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
+	dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
+	/* tDAL = 6*tCK */
+	dram_vals[15] &= ~(0xf << 16);
+	dram_vals[15] |= (0x6 << 16);
+	/* tREF = 1040*tCK */
+	dram_vals[26] &= ~0xffff;
+	dram_vals[26] |= 0x0410;
+	/* tRAS_MAX = 9334*tCK */
+	dram_vals[32] &= ~0xffff;
+	dram_vals[32] |= 0x2475;
+}
diff --git a/roms/u-boot/board/opalkelly/zynq/MAINTAINERS b/roms/u-boot/board/opalkelly/zynq/MAINTAINERS
new file mode 100644
index 000000000..df4b9b6da
--- /dev/null
+++ b/roms/u-boot/board/opalkelly/zynq/MAINTAINERS
@@ -0,0 +1,6 @@
+ZYNQ BOARD
+M:	Tom McLeod <tom.mcleod@opalkelly.com>
+S:	Maintained
+F:	board/opalkelly/zynq/
+F:	include/configs/syzygy_hub.h
+F:	configs/syzygy_hub_defconfig
diff --git a/roms/u-boot/board/opalkelly/zynq/Makefile b/roms/u-boot/board/opalkelly/zynq/Makefile
new file mode 100644
index 000000000..19e893e43
--- /dev/null
+++ b/roms/u-boot/board/opalkelly/zynq/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	:= board.o
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
diff --git a/roms/u-boot/board/opalkelly/zynq/board.c b/roms/u-boot/board/opalkelly/zynq/board.c
new file mode 100644
index 000000000..ee666185e
--- /dev/null
+++ b/roms/u-boot/board/opalkelly/zynq/board.c
@@ -0,0 +1,3 @@
+#include "../../xilinx/common/board.c"
+
+#include "../../xilinx/zynq/board.c"
diff --git a/roms/u-boot/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/roms/u-boot/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
new file mode 100644
index 000000000..80f2b83b5
--- /dev/null
+++ b/roms/u-boot/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0+
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+* (c) Copyright 2017 Opal Kelly Inc.
+ *****************************************************************************/
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC044DU),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003F01U, 0x00001201U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002E0037U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0x7FFF8000U),
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00088000U),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0x7FFF0000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0x7FFF8000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U),
+	EMIT_MASKWRITE(0XE000A00C, 0x003F003FU, 0x00370008U),
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00088000U),
+	EMIT_MASKWRITE(0XE000A00C, 0x003F003FU, 0x00370000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKWRITE(0XE000A00C, 0x003F003FU, 0x00370008U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_reset_apu_3_0[] = {
+	EMIT_MASKWRITE(0xF8000244, 0x00000022U, 0x00000022U),
+	EMIT_EXIT(),
+};
+
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_reset_apu_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
+
diff --git a/roms/u-boot/board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg b/roms/u-boot/board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg
new file mode 100644
index 000000000..c0dcfe9a0
--- /dev/null
+++ b/roms/u-boot/board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (C) 2016 Freescale Semiconductor, Inc.
+// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION	2
+BOOT_FROM	sd
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+/* Samsung K4B4G1646D-BCMA */
+DATA 4 0x020e04b4 0x000c0000
+DATA 4 0x020e04ac 0x00000000
+DATA 4 0x020e027c 0x00000030
+DATA 4 0x020e0250 0x00000030
+DATA 4 0x020e024c 0x00000030
+DATA 4 0x020e0490 0x00000030
+DATA 4 0x020e0288 0x000c0030
+DATA 4 0x020e0270 0x00000000
+DATA 4 0x020e0260 0x00000030
+DATA 4 0x020e0264 0x00000030
+DATA 4 0x020e04a0 0x00000030
+DATA 4 0x020e0494 0x00020000
+DATA 4 0x020e0280 0x00000030
+DATA 4 0x020e0284 0x00000030
+DATA 4 0x020e04b0 0x00020000
+DATA 4 0x020e0498 0x00000030
+DATA 4 0x020e04a4 0x00000030
+DATA 4 0x020e0244 0x00000030
+DATA 4 0x020e0248 0x00000030
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x00030009
+DATA 4 0x021b083c 0x01440148
+DATA 4 0x021b0848 0x40403640
+DATA 4 0x021b0850 0x4040322a
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b08c0 0x00944009
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x1b333030
+DATA 4 0x021b000c 0x676b52f2
+DATA 4 0x021b0010 0x926d0b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00211740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000004f
+DATA 4 0x021b0000 0x84180000
+DATA 4 0x021b0890 0x00400000
+DATA 4 0x021b001c 0x02008032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x15108030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00007800
+DATA 4 0x021b0818 0x00000227
+DATA 4 0x021b0004 0x0002552d
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
diff --git a/roms/u-boot/board/out4/o4-imx6ull-nano/Kconfig b/roms/u-boot/board/out4/o4-imx6ull-nano/Kconfig
new file mode 100644
index 000000000..e2ab80b6d
--- /dev/null
+++ b/roms/u-boot/board/out4/o4-imx6ull-nano/Kconfig
@@ -0,0 +1,64 @@
+if TARGET_O4_IMX6ULL_NANO
+
+config SYS_BOARD
+	default "o4-imx6ull-nano"
+
+config SYS_VENDOR
+	default "out4"
+
+config SYS_CONFIG_NAME
+	default "o4-imx6ull-nano"
+
+choice
+	prompt "Memory model"
+	default K4B4G1646D_BCMA
+	help
+	    Memory type setup.
+
+	    Please choose correct memory model here.
+
+config K4B4G1646D_BCMA
+	bool "K4B4G1646D-BCMA 256Mx16 (512 MiB/chip)"
+	help
+	    Samsung DDR3 SDRAM
+	    K4B4G1646D-BCMA
+
+config MT41K256M16HA_125E
+	bool "MT41K256M16HA-125:E 256Mx16 (512 MiB/chip)"
+	help
+	    Micron DDR3L SDRAM
+	    MT41K256M16HA-125:E
+
+endchoice
+
+choice
+	prompt "Mainboard model"
+	default O4_IMX_NANO
+	help
+	    Mainboard setup.
+
+	    Please choose correct main board model here.
+
+config O4_IMX_NANO
+	bool "O4-iMX-NANO"
+	help
+	    A baseboard for EV-iMX280-NANO module:
+	    https://out4.ru/products/board/18-o4-imx-nano.html
+
+config EV_IMX280_NANO_X_MB
+	bool "EV-IMX280-NANO-X-MB"
+	help
+	    A simple baseboard for EV-iMX280-NANO module:
+	    http://evodbg.net/products/mx28-eval-kits/14-ev-imx280-nano-x-mb.html
+
+endchoice
+
+config IMX_CONFIG
+	default "board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg" if K4B4G1646D_BCMA
+	default "board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg" if MT41K256M16HA_125E
+
+config DEFAULT_DEVICE_TREE
+	default "o4-imx-nano" if O4_IMX_NANO
+	default "ev-imx280-nano-x-mb" if EV_IMX280_NANO_X_MB
+
+endif
diff --git a/roms/u-boot/board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg b/roms/u-boot/board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg
new file mode 100644
index 000000000..6f823a727
--- /dev/null
+++ b/roms/u-boot/board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (C) 2016 Freescale Semiconductor, Inc.
+// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION	2
+BOOT_FROM	sd
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+/* Micron MT41K256M16HA-125:E */
+DATA 4 0x020e04b4 0x000c0000
+DATA 4 0x020e04ac 0x00000000
+DATA 4 0x020e027c 0x00000030
+DATA 4 0x020e0250 0x00000030
+DATA 4 0x020e024c 0x00000030
+DATA 4 0x020e0490 0x00000030
+DATA 4 0x020e0288 0x000c0030
+DATA 4 0x020e0270 0x00000000
+DATA 4 0x020e0260 0x00000030
+DATA 4 0x020e0264 0x00000030
+DATA 4 0x020e04a0 0x00000030
+DATA 4 0x020e0494 0x00020000
+DATA 4 0x020e0280 0x00000030
+DATA 4 0x020e0284 0x00000030
+DATA 4 0x020e04b0 0x00020000
+DATA 4 0x020e0498 0x00000030
+DATA 4 0x020e04a4 0x00000030
+DATA 4 0x020e0244 0x00000030
+DATA 4 0x020e0248 0x00000030
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x0005000b
+DATA 4 0x021b083c 0x01400144
+DATA 4 0x021b0848 0x4040343a
+DATA 4 0x021b0850 0x4040342a
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b08c0 0x00944009
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x1b333030
+DATA 4 0x021b000c 0x676b52f2
+DATA 4 0x021b0010 0x91eb0b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00211740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000004f
+DATA 4 0x021b0000 0x84180000
+DATA 4 0x021b0890 0x00400000
+DATA 4 0x021b001c 0x02008032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x15108030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00007800
+DATA 4 0x021b0818 0x00000227
+DATA 4 0x021b0004 0x0002552d
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
diff --git a/roms/u-boot/board/out4/o4-imx6ull-nano/Makefile b/roms/u-boot/board/out4/o4-imx6ull-nano/Makefile
new file mode 100644
index 000000000..a3f4646d9
--- /dev/null
+++ b/roms/u-boot/board/out4/o4-imx6ull-nano/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
+
+obj-y := o4-imx6ull-nano.o
diff --git a/roms/u-boot/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c b/roms/u-boot/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c
new file mode 100644
index 000000000..edb200e9e
--- /dev/null
+++ b/roms/u-boot/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
+
+#include <asm/arch-mx6/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <common.h>
+#include <env.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+static int setup_fec_clock(void)
+{
+	if (IS_ENABLED(CONFIG_FEC_MXC) && !IS_ENABLED(CONFIG_CLK_IMX6Q)) {
+		struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+		int ret;
+
+		/*
+		 * Use 50M anatop loopback REF_CLK1 for ENET1,
+		 * clear gpr1[13], set gpr1[17].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+		ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+		if (ret)
+			return ret;
+
+		if (!IS_ENABLED(CONFIG_EV_IMX280_NANO_X_MB)) {
+			/*
+			 * Use 50M anatop loopback REF_CLK2 for ENET2,
+			 * clear gpr1[14], set gpr1[18].
+			 */
+			clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+					IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+			ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+			if (ret)
+				return ret;
+		}
+
+		enable_enet_clk(1);
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return setup_fec_clock();
+}
+
+int board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_CMD_BMODE))
+		add_board_boot_modes(NULL);
+
+	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+		const char *model;
+
+		model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+		if (model)
+			env_set("board_name", model);
+	}
+
+	if (is_boot_from_usb()) {
+		env_set("bootcmd", "run bootcmd_mfg");
+		env_set("bootdelay", "0");
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/phytec/pcl063/Kconfig b/roms/u-boot/board/phytec/pcl063/Kconfig
new file mode 100644
index 000000000..58f72f279
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcl063/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_PCL063
+
+config SYS_BOARD
+	default "pcl063"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "pcl063"
+
+endif
+
+if TARGET_PCL063_ULL
+
+config SYS_BOARD
+	default "pcl063"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "pcl063_ull"
+
+endif
diff --git a/roms/u-boot/board/phytec/pcl063/MAINTAINERS b/roms/u-boot/board/phytec/pcl063/MAINTAINERS
new file mode 100644
index 000000000..02be541cc
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcl063/MAINTAINERS
@@ -0,0 +1,18 @@
+PCL063 BOARD
+M:	Martyn Welch <martyn.welch@collabora.com>
+M:	Parthiban Nallathambi <parthitce@gmail.com>
+S:	Maintained
+F:	arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+F:	arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
+F:	arch/arm/dts/imx6ul-phytec-segin.dtsi
+F:	arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+F:	arch/arm/dts/imx6ull-phytec-phycore-som.dtsi
+F:	arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
+F:	arch/arm/dts/imx6ull-phytec-segin.dtsi
+F:	arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
+F:	arch/arm/dts/imx6ull-u-boot.dtsi
+F:	board/phytec/pcl063/
+F:	configs/phycore_pcl063_defconfig
+F:	configs/phycore_pcl063_ull_defconfig
+F:	include/configs/pcl063.h
+F:	include/configs/pcl063_ull.h
diff --git a/roms/u-boot/board/phytec/pcl063/Makefile b/roms/u-boot/board/phytec/pcl063/Makefile
new file mode 100644
index 000000000..53c73c9b0
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcl063/Makefile
@@ -0,0 +1,7 @@
+# Copyright (C) 2018 Collabora Ltd.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := pcl063.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/roms/u-boot/board/phytec/pcl063/README b/roms/u-boot/board/phytec/pcl063/README
new file mode 100644
index 000000000..be83bdb0d
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcl063/README
@@ -0,0 +1,26 @@
+How to use U-Boot on PHYTEC phyBOARD-i.MX6UL-Segin
+--------------------------------------------------
+
+- Configure and build U-Boot for phyCORE-i.MX6UL:
+
+    $ make mrproper
+    $ make phycore_pcl063_defconfig
+    $ make
+
+  This will generate SPL and u-boot-dtb.img images.
+
+- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card:
+
+    $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+    $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+  JP1:   Open: Boot from NAND
+       Closed: Boot from SD/MMC1
+
+- Connect the Serial cable to UART0 and the PC for the console.
+
+- Insert the micro SD card in the board and power it up.
+
+- U-Boot messages should come up.
diff --git a/roms/u-boot/board/phytec/pcl063/pcl063.c b/roms/u-boot/board/phytec/pcl063/pcl063.c
new file mode 100644
index 000000000..b2e435f69
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcl063/pcl063.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on board/ccv/xpress/xpress.c:
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/bitops.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE         | PAD_CTL_PUE       | \
+			PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | \
+			PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart5_pads[] = {
+	MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+}
+
+#ifdef CONFIG_NAND_MXS
+
+#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
+
+#define NANDREADYPC MUX_PAD_CTRL(NAND_PAD_READY0_CTRL)
+
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B		| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B		| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B	| NANDREADYPC,
+};
+
+static void setup_gpmi_nand(void)
+{
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+	setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
+			  (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+}
+
+#endif /* CONFIG_NAND_MXS */
+
+#ifdef CONFIG_FEC_MXC
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE       | \
+			   PAD_CTL_SPEED_HIGH  | PAD_CTL_DSE_48ohm | \
+			   PAD_CTL_SRE_FAST)
+
+#define MDIO_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE      | \
+			   PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | \
+			   PAD_CTL_ODE)
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_pads[] = {
+	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+	imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	/*
+	 * Use 50M anatop loopback REF_CLK1 for ENET1,
+	 * clear gpr1[13], set gpr1[17].
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	/*
+	 * Use 50M anatop loopback REF_CLK2 for ENET2,
+	 * clear gpr1[14], set gpr1[18].
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/*
+	 * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
+	 * 50 MHz RMII clock mode.
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif /* CONFIG_FEC_MXC */
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+#ifdef CONFIG_FEC_MXC
+	setup_iomux_fec();
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	u32 cpurev = get_cpu_rev();
+
+	printf("Board: PHYTEC phyCORE-i.MX%s\n",
+	      get_imx_type((cpurev & 0xFF000) >> 12));
+
+	return 0;
+}
diff --git a/roms/u-boot/board/phytec/pcl063/spl.c b/roms/u-boot/board/phytec/pcl063/spl.c
new file mode 100644
index 000000000..fea4aa336
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcl063/spl.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on board/ccv/xpress/spl.c:
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <fsl_esdhc_imx.h>
+
+/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x41480148,
+	.p0_mprddlctl = 0x40403E42,
+	.p0_mpwrdlctl = 0x40405852,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,		/* Bus size = 16bit */
+	.cs_density = 18,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 1,
+	.rtt_nom = 1,
+	.walat = 1,		/* Write additional latency */
+	.ralat = 5,		/* Read additional latency */
+	.mif3_mode = 3,		/* Command prediction working mode */
+	.bi_on = 1,		/* Bank interleaving enabled */
+	.pd_fast_exit = 1,
+	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 1,		/* Refresh cycles at 32KHz */
+	.refr = 7,		/* 8 refresh commands per refresh cycle */
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 933,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 1,
+	.trcd = 1391,
+	.trcmin = 4791,
+	.trasmin = 3400,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE         | PAD_CTL_PUE       | \
+			PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW | \
+			PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | \
+			PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifndef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_NAND_RE_B__USDHC2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+	{
+		.esdhc_base = USDHC1_BASE_ADDR,
+		.max_bus_width = 4,
+	},
+#ifndef CONFIG_NAND_MXS
+	{
+		.esdhc_base = USDHC2_BASE_ADDR,
+		.max_bus_width = 8,
+	},
+#endif
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+#ifndef CONFIG_NAND_MXS
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+#endif
+		default:
+			printf("Warning - USDHC%d controller not supporting\n",
+			       i + 1);
+			return 0;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* Setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* Setup iomux and fec */
+	board_early_init_f();
+
+	/* Setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
diff --git a/roms/u-boot/board/phytec/pcm052/Kconfig b/roms/u-boot/board/phytec/pcm052/Kconfig
new file mode 100644
index 000000000..4fde21c58
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcm052/Kconfig
@@ -0,0 +1,33 @@
+if TARGET_PCM052
+
+config SYS_BOARD
+	default "pcm052"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "pcm052"
+
+config PCM052_DDR_SIZE
+	int
+	default 256
+
+endif
+
+if TARGET_BK4R1
+
+config SYS_BOARD
+	default "pcm052"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "bk4r1"
+
+config PCM052_DDR_SIZE
+	int
+	default 512
+
+endif
diff --git a/roms/u-boot/board/phytec/pcm052/MAINTAINERS b/roms/u-boot/board/phytec/pcm052/MAINTAINERS
new file mode 100644
index 000000000..66fe06e49
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcm052/MAINTAINERS
@@ -0,0 +1,8 @@
+PCM052 BOARD
+M:	Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
+S:	Maintained
+F:	board/phytec/pcm052/
+F:	include/configs/bk4r1.h
+F:	include/configs/pcm052.h
+F:	configs/bk4r1_defconfig
+F:	configs/pcm052_defconfig
diff --git a/roms/u-boot/board/phytec/pcm052/Makefile b/roms/u-boot/board/phytec/pcm052/Makefile
new file mode 100644
index 000000000..ebbc9b237
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcm052/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+
+obj-y	:= pcm052.o
diff --git a/roms/u-boot/board/phytec/pcm052/imximage.cfg b/roms/u-boot/board/phytec/pcm052/imximage.cfg
new file mode 100644
index 000000000..cf72b84e7
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcm052/imximage.cfg
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 3ADEV <http://www.3adev.com>
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/mach-imx/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET	FLASH_OFFSET_STANDARD
diff --git a/roms/u-boot/board/phytec/pcm052/pcm052.c b/roms/u-boot/board/phytec/pcm052/pcm052.c
new file mode 100644
index 000000000..f9cf4abd4
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcm052/pcm052.c
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/ddrmc-vf610.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <env.h>
+#include <led.h>
+#include <miiphy.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ddrmc_cr_setting pcm052_cr_settings[] = {
+	/* not in the datasheets, but in the original code */
+	{ 0x00002000, 105 },
+	{ 0x00000020, 110 },
+	/* AXI */
+	{ DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
+	{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
+	{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
+		   DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
+	{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
+		   DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
+	{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+		   DDRMC_CR122_AXI0_PRIRLX(100), 122 },
+	{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
+		   DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
+	{ DDRMC_CR124_AXI1_PRIRLX(100), 124 },
+	{ DDRMC_CR126_PHY_RDLAT(11), 126 },
+	{ DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
+	{ DDRMC_CR137_PHYCTL_DL(2), 137 },
+	{ DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+		   DDRMC_CR139_PHY_WRLV_DLL(3) |
+		   DDRMC_CR139_PHY_WRLV_EN(3), 139 },
+	{ DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+		   DDRMC_CR154_PAD_ZQ_MODE(1) |
+		   DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
+		   DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
+	{ DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
+	{ DDRMC_CR158_TWR(6), 158 },
+	{ DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
+		   DDRMC_CR161_TODTH_WR(6), 161 },
+	/* end marker */
+	{ 0, -1 }
+};
+
+/* PHY settings -- most of them differ from default in imx-regs.h */
+
+#define PCM052_DDRMC_PHY_DQ_TIMING			0x00002213
+#define PCM052_DDRMC_PHY_CTRL				0x00290000
+#define PCM052_DDRMC_PHY_SLAVE_CTRL			0x00002c00
+#define PCM052_DDRMC_PHY_PROC_PAD_ODT			0x00010020
+
+static struct ddrmc_phy_setting pcm052_phy_settings[] = {
+	{ PCM052_DDRMC_PHY_DQ_TIMING,  0 },
+	{ PCM052_DDRMC_PHY_DQ_TIMING, 16 },
+	{ PCM052_DDRMC_PHY_DQ_TIMING, 32 },
+	{ PCM052_DDRMC_PHY_DQ_TIMING, 48 },
+	{ DDRMC_PHY_DQS_TIMING,  1 },
+	{ DDRMC_PHY_DQS_TIMING, 17 },
+	{ DDRMC_PHY_DQS_TIMING, 33 },
+	{ DDRMC_PHY_DQS_TIMING, 49 },
+	{ PCM052_DDRMC_PHY_CTRL,  2 },
+	{ PCM052_DDRMC_PHY_CTRL, 18 },
+	{ PCM052_DDRMC_PHY_CTRL, 34 },
+	{ DDRMC_PHY_MASTER_CTRL,  3 },
+	{ DDRMC_PHY_MASTER_CTRL, 19 },
+	{ DDRMC_PHY_MASTER_CTRL, 35 },
+	{ PCM052_DDRMC_PHY_SLAVE_CTRL,  4 },
+	{ PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
+	{ PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
+	{ DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
+	{ PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
+
+	/* end marker */
+	{ 0, -1 }
+};
+
+int dram_init(void)
+{
+#if defined(CONFIG_TARGET_PCM052)
+
+	static const struct ddr3_jedec_timings pcm052_ddr_timings = {
+		.tinit             = 5,
+		.trst_pwron        = 80000,
+		.cke_inactive      = 200000,
+		.wrlat             = 5,
+		.caslat_lin        = 12,
+		.trc               = 6,
+		.trrd              = 4,
+		.tccd              = 4,
+		.tbst_int_interval = 4,
+		.tfaw              = 18,
+		.trp               = 6,
+		.twtr              = 4,
+		.tras_min          = 15,
+		.tmrd              = 4,
+		.trtp              = 4,
+		.tras_max          = 14040,
+		.tmod              = 12,
+		.tckesr            = 4,
+		.tcke              = 3,
+		.trcd_int          = 6,
+		.tras_lockout      = 1,
+		.tdal              = 10,
+		.bstlen            = 3,
+		.tdll              = 512,
+		.trp_ab            = 6,
+		.tref              = 1542,
+		.trfc              = 64,
+		.tref_int          = 5,
+		.tpdex             = 3,
+		.txpdll            = 10,
+		.txsnr             = 68,
+		.txsr              = 506,
+		.cksrx             = 5,
+		.cksre             = 5,
+		.freq_chg_en       = 1,
+		.zqcl              = 256,
+		.zqinit            = 512,
+		.zqcs              = 64,
+		.ref_per_zq        = 64,
+		.zqcs_rotate       = 1,
+		.aprebit           = 10,
+		.cmd_age_cnt       = 255,
+		.age_cnt           = 255,
+		.q_fullness        = 0,
+		.odt_rd_mapcs0     = 1,
+		.odt_wr_mapcs0     = 1,
+		.wlmrd             = 40,
+		.wldqsen           = 25,
+	};
+
+    const int row_diff = 2;
+
+#elif defined(CONFIG_TARGET_BK4R1)
+
+	static const struct ddr3_jedec_timings pcm052_ddr_timings = {
+		.tinit             = 5,
+		.trst_pwron        = 80000,
+		.cke_inactive      = 200000,
+		.wrlat             = 5,
+		.caslat_lin        = 12,
+		.trc               = 6,
+		.trrd              = 4,
+		.tccd              = 4,
+		.tbst_int_interval = 0,
+		.tfaw              = 16,
+		.trp               = 6,
+		.twtr              = 4,
+		.tras_min          = 15,
+		.tmrd              = 4,
+		.trtp              = 4,
+		.tras_max          = 28080,
+		.tmod              = 12,
+		.tckesr            = 4,
+		.tcke              = 3,
+		.trcd_int          = 6,
+		.tras_lockout      = 1,
+		.tdal              = 12,
+		.bstlen            = 3,
+		.tdll              = 512,
+		.trp_ab            = 6,
+		.tref              = 3120,
+		.trfc              = 104,
+		.tref_int          = 0,
+		.tpdex             = 3,
+		.txpdll            = 10,
+		.txsnr             = 108,
+		.txsr              = 512,
+		.cksrx             = 5,
+		.cksre             = 5,
+		.freq_chg_en       = 1,
+		.zqcl              = 256,
+		.zqinit            = 512,
+		.zqcs              = 64,
+		.ref_per_zq        = 64,
+		.zqcs_rotate       = 1,
+		.aprebit           = 10,
+		.cmd_age_cnt       = 255,
+		.age_cnt           = 255,
+		.q_fullness        = 0,
+		.odt_rd_mapcs0     = 1,
+		.odt_wr_mapcs0     = 1,
+		.wlmrd             = 40,
+		.wldqsen           = 25,
+	};
+
+    const int row_diff = 1;
+
+#else /* Unknown PCM052 variant */
+
+#error DDR characteristics undefined for this target. Please define them.
+
+#endif
+
+	ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
+			     pcm052_phy_settings, 1, row_diff);
+
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static void clock_init(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+
+	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+			CCM_CCGR0_UART1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+			CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+			CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+			CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+			CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
+			CCM_CCGR2_QSPI0_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+			CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+			CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+			CCM_CCGR4_GPC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+			CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+			CCM_CCGR7_SDHC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+			CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+			CCM_CCGR10_NFC_CTRL_MASK);
+
+	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
+			ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+			ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+			CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
+			CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
+			CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
+			CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
+			CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
+			CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
+			CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
+	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+			CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+			CCM_CACRR_ARM_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+			CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
+			CCM_CSCMR1_QSPI0_CLK_SEL(3) |
+			CCM_CSCMR1_NFC_CLK_SEL(0));
+	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+			CCM_CSCDR1_RMII_CLK_EN);
+	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+			CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
+			CCM_CSCDR2_NFC_EN);
+	clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
+			CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
+			CCM_CSCDR3_QSPI0_X2_DIV(1) |
+			CCM_CSCDR3_QSPI0_X4_DIV(3) |
+			CCM_CSCDR3_NFC_PRE_DIV(5));
+	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+			CCM_CSCMR2_RMII_CLK_SEL(0));
+}
+
+static void mscm_init(void)
+{
+	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+	int i;
+
+	for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_early_init_f(void)
+{
+	clock_init();
+	mscm_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/*
+	 * Enable external 32K Oscillator
+	 *
+	 * The internal clock experiences significant drift
+	 * so we must use the external oscillator in order
+	 * to maintain correct time in the hwclock
+	 */
+	setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
+	return 0;
+}
+
+#ifdef CONFIG_TARGET_BK4R1
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[4];
+	struct fuse_bank4_regs *fuse =
+		(struct fuse_bank4_regs *)bank->fuse_regs;
+	u32 value;
+
+	/*
+	 * BK4 has different layout of stored MAC address
+	 * than one used in imx_get_mac_from_fuse() @ generic.c
+	 */
+
+	switch (dev_id) {
+	case 0:
+		value = readl(&fuse->mac_addr1);
+
+		mac[0] = value >> 8;
+		mac[1] = value;
+
+		value = readl(&fuse->mac_addr0);
+		mac[2] = value >> 24;
+		mac[3] = value >> 16;
+		mac[4] = value >> 8;
+		mac[5] = value;
+		break;
+	case 1:
+		value = readl(&fuse->mac_addr2);
+
+		mac[0] = value >> 24;
+		mac[1] = value >> 16;
+		mac[2] = value >> 8;
+		mac[3] = value;
+
+		value = readl(&fuse->mac_addr1);
+		mac[4] = value >> 24;
+		mac[5] = value >> 16;
+		break;
+	}
+}
+
+int board_late_init(void)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	u32 reg;
+
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	/*
+	 * BK4r1 handle emergency/service SD card boot
+	 * Checking the SBMR1 register BOOTCFG1 byte:
+	 * NAND:
+	 *      bit [2] - NAND data width - 16
+	 *	bit [5] - NAND fast boot
+	 *	bit [7] = 1 - NAND as a source of booting
+	 * SD card (0x64):
+	 *      bit [4] = 0 - SD card source
+	 *	bit [6] = 1 - SD/MMC source
+	 */
+
+	reg = readl(&psrc->sbmr1);
+	if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) &&
+	    !(reg & SRC_SBMR1_BOOTCFG1_MMC)) {
+		printf("------ SD card boot -------\n");
+		env_set_default("!LVFBootloader", 0);
+		env_set("bootcmd",
+			"run prepare_install_bk4r1_envs; run install_bk4r1rs");
+	}
+
+	return 0;
+}
+
+/**
+ * KSZ8081
+ */
+#define MII_KSZ8081_REFERENCE_CLOCK_SELECT	0x1f
+#define RMII_50MHz_CLOCK	0x8180
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* Set 50 MHz reference clock */
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
+		  RMII_50MHz_CLOCK);
+
+	return genphy_config(phydev);
+}
+#endif /* CONFIG_TARGET_BK4R1 */
+
+int checkboard(void)
+{
+#ifdef CONFIG_TARGET_BK4R1
+	u32 *gpio3_pdir = (u32 *)(GPIO3_BASE_ADDR + 0x10);
+
+	/*
+	 * USB_RESET_N (PTC30 - GPIO103 - PORT3[7]):
+	 * L333 -> pull up added -> read 1
+	 * L320 -> no pull up -> read 0
+	 *
+	 * Default iomuxc_ptc30 value after reset: 0x300061 -> RCON28
+	 * - input enabled, pull (up/down) disabled
+	 */
+	if (*gpio3_pdir & BIT(7))
+		puts("Board: BK4r1 (L333)\n");
+	else
+		puts("Board: BK4r1 (L320)\n");
+#else
+	puts("Board: PCM-052\n");
+#endif
+	return 0;
+}
diff --git a/roms/u-boot/board/phytec/pcm058/Kconfig b/roms/u-boot/board/phytec/pcm058/Kconfig
new file mode 100644
index 000000000..d099275d4
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcm058/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PCM058
+
+config SYS_BOARD
+	default "pcm058"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "pcm058"
+
+endif
diff --git a/roms/u-boot/board/phytec/pcm058/MAINTAINERS b/roms/u-boot/board/phytec/pcm058/MAINTAINERS
new file mode 100644
index 000000000..909dfc44a
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcm058/MAINTAINERS
@@ -0,0 +1,7 @@
+PHYTEC PHYBOARD MIRA
+M:	Niel Fourie <lusus@denx.de>
+S:	Maintained
+F:	board/phytec/pcm058/
+F:	include/configs/pcm058.h
+F:	configs/pcm058_defconfig
+F:	arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi
diff --git a/roms/u-boot/board/phytec/pcm058/Makefile b/roms/u-boot/board/phytec/pcm058/Makefile
new file mode 100644
index 000000000..75b503d95
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcm058/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+
+obj-y  := pcm058.o
diff --git a/roms/u-boot/board/phytec/pcm058/README b/roms/u-boot/board/phytec/pcm058/README
new file mode 100644
index 000000000..687366bff
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcm058/README
@@ -0,0 +1,90 @@
+Board information
+-----------------
+
+The SBC produced by Phytec has a SOM based on a i.MX6Q.
+The SOM is sold in two versions, with eMMC or with NAND. Support
+here is for the SOM with NAND.
+The evaluation board "phyBoard-Mira" is thought to be used
+together with the SOM.
+
+More information on the board can be found on manufacturer's
+website:
+
+http://www.phytec.de/produkt/single-board-computer/phyboard-mira/
+http://www.phytec.de/fileadmin/user_upload/images/content/1.Products/SOMs/phyCORE-i.MX6/L-808e_1.pdf
+
+Building U-Boot
+-------------------------------
+
+$ make pcm058_defconfig
+$ make
+
+This generates the artifacts SPL and u-boot.img.
+The SOM can boot from NAND or from SD-Card, having the SPI-NOR
+as second option.
+The dip switch "DIP-1" on the board let choose between
+NAND and SD.
+
+DIP-1 set to off:	Boot first from NAND, then try SPI
+DIP-1 set to on:	Boot first from SD, then try SPI
+
+The bootloader was tested with DIP-1 set to on. If a SD-card
+is present, then the RBL tries to load SPL from the SD Card, if not,
+RBL loads from SPI-NOR. The SPL tries then to load from the same
+device where SPL was loaded (SD or SPI). Booting from NAND is
+not supported.
+
+Flashing U-Boot onto an SD card
+-------------------------------
+
+After a successful build, the generated SPL and U-boot binaries can be copied
+to an SD card. Adjust the SD card device as necessary:
+
+$ sudo dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=1k seek=1
+
+This is equivalent to separately copying the SPL and U-boot using:
+
+$ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1
+$ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197
+
+The default bootscripts expect a kernel fit-image file named "fitImage" in the
+first partition and Linux ext4 rootfs in the second partition.
+
+Flashing U-boot to the SPI Flash, for booting Linux from NAND
+-------------------------------------------------------------
+
+The SD card created above can also be used to install the SPL and U-boot into
+the SPI flash. Boot U-boot from the SD card as above, and stop at the autoboot.
+
+Then, clear the SPI flash:
+
+=> sf probe
+=> sf erase 0x0 0x1000000
+
+Load the equivalent of u-boot-with-spl.imx from the raw MMC into memory and
+copy to the SPI. The SPL is expected at an offset of 0x400, and its size is
+maximum 392*512-byte blocks in size, therefore 0x188 blocks, totaling 0x31000
+bytes. Assume U-boot should fit into 640KiB, therefore 0x500 512-byte blocks,
+totalling 0xA0000 bytes. Adding these together:
+
+=> mmc read ${loadaddr} 0x2 0x688
+=> sf write ${loadaddr} 0x400 0xD1000
+
+The SPL is located at offset 0x400, and U-boot at 0x31400 in SPI flash, as to
+match the SD Card layout. This would allow, instead of reading from the SD Card
+above, with networking and TFTP correctly configured, the equivalent of:
+
+=> tftp u-boot-with-spl.imx
+=> sf write ${fileaddr} 0x400 ${filesize}
+
+The default NAND bootscripts expect a single MTD partition named "rootfs",
+which in turn contains the UBI volumes "fit" (which contains the kernel fit-
+image) and "root" (which contains a ubifs root filesystem).
+
+The "bootm_size" variable in the environment
+--------------------------------------------
+
+By default, U-boot relocates the device tree towards the upper end of the RAM,
+which kernels using CONFIG_HIGHMEM=y may not be able to access during early
+boot. With the bootm_size variable set to 0x30000000, U-boot relocates the
+device tree to below this address instead.
diff --git a/roms/u-boot/board/phytec/pcm058/pcm058.c b/roms/u-boot/board/phytec/pcm058/pcm058.c
new file mode 100644
index 000000000..5e5b129ef
--- /dev/null
+++ b/roms/u-boot/board/phytec/pcm058/pcm058.c
@@ -0,0 +1,287 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
+ */
+
+/*
+ * Please note: there are two version of the board
+ * one with NAND and the other with eMMC.
+ * Both NAND and eMMC cannot be set because they share the
+ * same pins (SD4)
+ */
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/sys_proto.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMX6Q_DRIVE_STRENGTH	0x30
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno - 1;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
+	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+	/* config gpmi and bch clock to 100 MHz */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+	/* enable ENFC_CLK_ROOT clock */
+	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	setup_gpmi_nand();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+/*
+ * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
+ * see Table 8-11 and Table 5-9
+ *  BOOT_CFG1[7] = 1 (boot from NAND)
+ *  BOOT_CFG1[5] = 0 - raw NAND
+ *  BOOT_CFG1[4] = 0 - default pad settings
+ *  BOOT_CFG1[3:2] = 00 - devices = 1
+ *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
+ *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
+ *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
+ *  BOOT_CFG2[0] = 0 - Reset time 12ms
+ */
+static const struct boot_mode board_boot_modes[] = {
+	/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
+	{"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
+	{"mmc0",  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <linux/libfdt.h>
+
+static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdclk_1 = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_reset = 0x00000030,
+	.dram_sdcke0 = 0x00000030,
+	.dram_sdcke1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = 0x00000030,
+	.dram_sdodt1 = 0x00000030,
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_sdqs2 = 0x00000030,
+	.dram_sdqs3 = 0x00000030,
+	.dram_sdqs4 = 0x00000030,
+	.dram_sdqs5 = 0x00000030,
+	.dram_sdqs6 = 0x00000030,
+	.dram_sdqs7 = 0x00000030,
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_dqm2 = 0x00000030,
+	.dram_dqm3 = 0x00000030,
+	.dram_dqm4 = 0x00000030,
+	.dram_dqm5 = 0x00000030,
+	.dram_dqm6 = 0x00000030,
+	.dram_dqm7 = 0x00000030,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_ddr_type =  0x000C0000,
+	.grp_ddrmode_ctl =  0x00020000,
+	.grp_ddrpke =  0x00000000,
+	.grp_addds = IMX6Q_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6Q_DRIVE_STRENGTH,
+	.grp_ddrmode =  0x00020000,
+	.grp_b0ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6Q_DRIVE_STRENGTH,
+};
+
+static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x00140014,
+	.p0_mpwldectrl1 =  0x000A0015,
+	.p1_mpwldectrl0 =  0x000A001E,
+	.p1_mpwldectrl1 =  0x000A0015,
+	.p0_mpdgctrl0 =  0x43080314,
+	.p0_mpdgctrl1 =  0x02680300,
+	.p1_mpdgctrl0 =  0x430C0318,
+	.p1_mpdgctrl1 =  0x03000254,
+	.p0_mprddlctl =  0x3A323234,
+	.p1_mprddlctl =  0x3E3C3242,
+	.p0_mpwrdlctl =  0x2A2E3632,
+	.p1_mpwrdlctl =  0x3C323E34,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+	.SRT       = 1,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize = 2,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density = 32, /* 32Gb per CS */
+		/* single chip select */
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
+		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
+		.walat = 1,	/* Write additional latency */
+		.ralat = 5,	/* Read additional latency */
+		.mif3_mode = 3,	/* Command prediction working mode */
+		.bi_on = 1,	/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
+	};
+
+	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+	printf("Boot device %x\n", spl_boot_list[0]);
+	switch (spl_boot_list[0]) {
+	case BOOT_DEVICE_SPI:
+		spl_boot_list[1] = BOOT_DEVICE_UART;
+		break;
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[1] = BOOT_DEVICE_SPI;
+		spl_boot_list[2] = BOOT_DEVICE_UART;
+		break;
+	default:
+		printf("Boot device %x\n", spl_boot_list[0]);
+	}
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup clock gating */
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* setup AXI */
+	gpr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* Enable device tree and early DM support*/
+	spl_early_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+
+/*
+ *  Manually probe the SPI bus devices, as this does not happen when the
+ *  SPI Flash is probed, which then fails to find the bus.
+ */
+void spl_board_init(void)
+{
+	struct udevice *udev;
+	int ret = uclass_get_device_by_name(UCLASS_SPI, "spi@2008000", &udev);
+
+	if (ret) {
+		printf("SPI bus probe failed, err = %d\n", ret);
+	};
+}
+#endif
diff --git a/roms/u-boot/board/phytec/phycore_am335x_r2/Kconfig b/roms/u-boot/board/phytec/phycore_am335x_r2/Kconfig
new file mode 100644
index 000000000..77055e043
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_am335x_r2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PHYCORE_AM335X_R2
+
+config SYS_BOARD
+	default "phycore_am335x_r2"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "phycore_am335x_r2"
+
+endif
diff --git a/roms/u-boot/board/phytec/phycore_am335x_r2/MAINTAINERS b/roms/u-boot/board/phytec/phycore_am335x_r2/MAINTAINERS
new file mode 100644
index 000000000..8d02b0e19
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_am335x_r2/MAINTAINERS
@@ -0,0 +1,11 @@
+phyCORE AM335x R2 WEGA BOARD
+M:	Niel Fourie <lusus@denx.de>
+M:	Parthiban Nallathambi <parthiban@linumiz.com>
+S:	Maintained
+F:	arch/arm/dts/am335x-regor.dtsi
+F:	arch/arm/dts/am335x-regor-rdk.dts
+F:	arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
+F:	board/phytec/phycore_am335x_r2
+F:	include/configs/phycore_am335x_r2.h
+F:	configs/phycore-am335x-r2-regor_defconfig
+F:	configs/phycore-am335x-r2-wega_defconfig
diff --git a/roms/u-boot/board/phytec/phycore_am335x_r2/Makefile b/roms/u-boot/board/phytec/phycore_am335x_r2/Makefile
new file mode 100644
index 000000000..ff6f8b422
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_am335x_r2/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/roms/u-boot/board/phytec/phycore_am335x_r2/board.c b/roms/u-boot/board/phytec/phycore_am335x_r2/board.c
new file mode 100644
index 000000000..5ca941520
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_am335x_r2/board.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <power/tps65910.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+#include <fdt_support.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* DDR RAM defines */
+#define DDR_CLK_MHZ		400 /* DDR_DPLL_MULT value */
+
+#define OSC	(V_OSCK / 1000000)
+const struct dpll_params dpll_ddr = {
+		DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= 0x18B,
+	.cm1ioctl		= 0x18B,
+	.cm2ioctl		= 0x18B,
+	.dt0ioctl		= 0x18B,
+	.dt1ioctl		= 0x18B,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = 0x80,
+	.cmd0iclkout = 0x0,
+
+	.cmd1csratio = 0x80,
+	.cmd1iclkout = 0x0,
+
+	.cmd2csratio = 0x80,
+	.cmd2iclkout = 0x0,
+};
+
+enum {
+	PHYCORE_R2_MT41K128M16JT_256MB,
+	PHYCORE_R2_MT41K256M16TW107IT_512MB,
+	PHYCORE_R2_MT41K512M16HA125IT_1024MB,
+};
+
+struct am335x_sdram_timings {
+	struct emif_regs ddr3_emif_reg_data;
+	struct ddr_data ddr3_data;
+};
+
+static struct am335x_sdram_timings physom_timings[] = {
+	[PHYCORE_R2_MT41K128M16JT_256MB] = {
+		.ddr3_emif_reg_data = {
+			.sdram_config = 0x61C052B2,
+			.ref_ctrl = 0x00000C30,
+			.sdram_tim1 = 0x0AAAD4DB,
+			.sdram_tim2 = 0x26437FDA,
+			.sdram_tim3 = 0x501F83FF,
+			.zq_config = 0x50074BE4,
+			.emif_ddr_phy_ctlr_1 = 0x7,
+			.ocp_config = 0x003d3d3d,
+		},
+		.ddr3_data = {
+			.datardsratio0 = 0x36,
+			.datawdsratio0 = 0x38,
+			.datafwsratio0 = 0x99,
+			.datawrsratio0 = 0x73,
+		},
+	},
+	[PHYCORE_R2_MT41K256M16TW107IT_512MB] = {
+		.ddr3_emif_reg_data = {
+			.sdram_config = 0x61C05332,
+			.ref_ctrl = 0x00000C30,
+			.sdram_tim1 = 0x0AAAD4DB,
+			.sdram_tim2 = 0x266B7FDA,
+			.sdram_tim3 = 0x501F867F,
+			.zq_config = 0x50074BE4,
+			.emif_ddr_phy_ctlr_1 = 0x7,
+			.ocp_config = 0x003d3d3d,
+		},
+		.ddr3_data = {
+			.datardsratio0 = 0x37,
+			.datawdsratio0 = 0x38,
+			.datafwsratio0 = 0x92,
+			.datawrsratio0 = 0x72,
+		},
+	},
+	[PHYCORE_R2_MT41K512M16HA125IT_1024MB] = {
+		.ddr3_emif_reg_data = {
+			.sdram_config = 0x61C053B2,
+			.ref_ctrl = 0x00000C30,
+			.sdram_tim1 = 0x0AAAD4DB,
+			.sdram_tim2 = 0x268F7FDA,
+			.sdram_tim3 = 0x501F88BF,
+			.zq_config = 0x50074BE4,
+			.emif_ddr_phy_ctlr_1 = 0x7,
+			.ocp_config = 0x003d3d3d,
+		},
+		.ddr3_data = {
+			.datardsratio0 = 0x38,
+			.datawdsratio0 = 0x4d,
+			.datafwsratio0 = 0x9d,
+			.datawrsratio0 = 0x82,
+		},
+	},
+};
+
+void sdram_init(void)
+{
+	/* Configure memory to maximum supported size for detection */
+	int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
+
+	config_ddr(DDR_CLK_MHZ, &ioregs,
+		   &physom_timings[ram_type_index].ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
+		   0);
+
+	/* Detect memory physically present */
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_MAX_RAM_BANK_SIZE);
+
+	/* Reconfigure memory for actual detected size */
+	switch (gd->ram_size) {
+	case SZ_1G:
+		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
+		break;
+	case SZ_512M:
+		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
+		break;
+	case SZ_256M:
+	default:
+		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
+		break;
+	}
+	config_ddr(DDR_CLK_MHZ, &ioregs,
+		   &physom_timings[ram_type_index].ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
+		   0);
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	int ind = get_sys_clk_index();
+	int freq = am335x_get_efuse_mpu_max_freq(cdev);
+
+	switch (freq) {
+	case MPUPLL_M_1000:
+		return &dpll_mpu_opp[ind][5];
+	case MPUPLL_M_800:
+		return &dpll_mpu_opp[ind][4];
+	case MPUPLL_M_720:
+		return &dpll_mpu_opp[ind][3];
+	case MPUPLL_M_600:
+		return &dpll_mpu_opp[ind][2];
+	case MPUPLL_M_500:
+		return &dpll_mpu_opp100;
+	case MPUPLL_M_300:
+		return &dpll_mpu_opp[ind][0];
+	}
+
+	return &dpll_mpu_opp[ind][0];
+}
+
+static void scale_vcores_generic(int freq)
+{
+	int sil_rev, mpu_vdd;
+
+	/*
+	 * We use a TPS65910 PMIC. For all  MPU frequencies we support we use a
+	 * CORE voltage of 1.10V. For MPU voltage we need to switch based on
+	 * the frequency we are running at.
+	 */
+	if (power_tps65910_init(0))
+		return;
+
+	/*
+	 * Depending on MPU clock and PG we will need a different
+	 * VDD to drive at that speed.
+	 */
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
+
+	/* Tell the TPS65910 to use i2c */
+	tps65910_set_i2c_control();
+
+	/* First update MPU voltage. */
+	if (tps65910_voltage_update(MPU, mpu_vdd))
+		return;
+
+	/* Second, update the CORE voltage. */
+	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
+		return;
+}
+
+void scale_vcores(void)
+{
+	int freq;
+
+	freq = am335x_get_efuse_mpu_max_freq(cdev);
+	scale_vcores_generic(freq);
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_i2c0_pin_mux();
+	enable_board_pin_mux();
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+	static const struct node_info nodes[] = {
+		{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+	};
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/phytec/phycore_am335x_r2/board.h b/roms/u-boot/board/phytec/phycore_am335x_r2/board.h
new file mode 100644
index 000000000..1b90861dd
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_am335x_r2/board.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * Phytec phyCORE-AM335x (PCL060 / PCM060) boards information header
+ *
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to access the PMIC. We then have a main
+ * pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_cbmux_pin_mux(void);
+#endif
diff --git a/roms/u-boot/board/phytec/phycore_am335x_r2/mux.c b/roms/u-boot/board/phytec/phycore_am335x_r2/mux.c
new file mode 100644
index 000000000..7091c985b
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_am335x_r2/mux.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+#endif
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+#ifdef CONFIG_SPI
+static struct module_pin_mux spi0_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_SCLK */
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_D0 */
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
+	{-1},
+};
+#endif
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},     /* RMII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},   /* RMII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1)},               /* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},               /* RMII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},               /* RMII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},    /* RMII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},    /* RMII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},    /* MDIO_CLK */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+	{-1},
+};
+
+static struct module_pin_mux cbmux_pin_mux[] = {
+	{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
+	{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN},	/* JP4 */
+	{-1},
+};
+
+#ifdef CONFIG_MTD_RAW_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+#endif
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(cbmux_pin_mux);
+#ifdef CONFIG_MTD_RAW_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#endif
+#ifdef CONFIG_SPI
+	configure_module_pin_mux(spi0_pin_mux);
+#endif
+}
diff --git a/roms/u-boot/board/phytec/phycore_imx8mm/Kconfig b/roms/u-boot/board/phytec/phycore_imx8mm/Kconfig
new file mode 100644
index 000000000..92f5524bd
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_imx8mm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PHYCORE_IMX8MM
+
+config SYS_BOARD
+	default "phycore_imx8mm"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "phycore_imx8mm"
+
+endif
diff --git a/roms/u-boot/board/phytec/phycore_imx8mm/MAINTAINERS b/roms/u-boot/board/phytec/phycore_imx8mm/MAINTAINERS
new file mode 100644
index 000000000..9edec7b7d
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_imx8mm/MAINTAINERS
@@ -0,0 +1,9 @@
+phyCORE-i.MX8M Mini
+M:      Teresa Remmet <t.remmet@phytec.de>
+W:      https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/
+S:      Maintained
+F:      arch/arm/dts/phycore-imx8mm.dts
+F:      arch/arm/dts/phycore-imx8mm-u-boot.dtsi
+F:      board/phytec/phycore_imx8mm/
+F:      configs/phycore-imx8mm_defconfig
+F:      include/configs/phycore_imx8mm.h
diff --git a/roms/u-boot/board/phytec/phycore_imx8mm/Makefile b/roms/u-boot/board/phytec/phycore_imx8mm/Makefile
new file mode 100644
index 000000000..27f6c027b
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_imx8mm/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
+# Author: Teresa Remmet <t.remmet@phytec.de>
+
+obj-y += phycore-imx8mm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/roms/u-boot/board/phytec/phycore_imx8mm/lpddr4_timing.c b/roms/u-boot/board/phytec/phycore_imx8mm/lpddr4_timing.c
new file mode 100644
index 000000000..811ac2641
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_imx8mm/lpddr4_timing.c
@@ -0,0 +1,1846 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020 PHYTEC Messtechnik GmbH
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa1080020},
+	{0x3d400020, 0x223},
+	{0x3d400024, 0x3a980},
+	{0x3d400064, 0x5b00d2},
+	{0x3d4000d0, 0xc00305ba},
+	{0x3d4000d4, 0x940000},
+	{0x3d4000dc, 0xd4002d},
+	{0x3d4000e0, 0x310000},
+	{0x3d4000e8, 0x66004d},
+	{0x3d4000ec, 0x16004d},
+	{0x3d400100, 0x191e1920},
+	{0x3d400104, 0x60630},
+	{0x3d40010c, 0xb0b000},
+	{0x3d400110, 0xe04080e},
+	{0x3d400114, 0x2040c0c},
+	{0x3d400118, 0x1010007},
+	{0x3d40011c, 0x401},
+	{0x3d400130, 0x20600},
+	{0x3d400134, 0xc100002},
+	{0x3d400138, 0xd8},
+	{0x3d400144, 0x96004b},
+	{0x3d400180, 0x2ee0017},
+	{0x3d400184, 0x2605b8e},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x497820a},
+	{0x3d400194, 0x80303},
+	{0x3d4001b4, 0x170a},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x1},
+	{0x3d4000f4, 0xc99},
+	{0x3d400108, 0x70e1617},
+	{0x3d400200, 0x1f},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0x7070707},
+	{0x3d400250, 0x29001701},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x4000030},
+	{0x3d400264, 0x900093e7},
+	{0x3d40026c, 0x2005574},
+	{0x3d400400, 0x111},
+	{0x3d400408, 0x72ff},
+	{0x3d400494, 0x2100e07},
+	{0x3d400498, 0x620096},
+	{0x3d40049c, 0x1100e07},
+	{0x3d4004a0, 0xc8012c},
+	{0x3d402020, 0x21},
+	{0x3d402024, 0x7d00},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0xc001c},
+	{0x3d4020dc, 0x840000},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004d},
+	{0x3d4020ec, 0x16004d},
+	{0x3d402100, 0xa040305},
+	{0x3d402104, 0x30407},
+	{0x3d402108, 0x203060b},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x2040202},
+	{0x3d402114, 0x2030202},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x1d},
+	{0x3d402144, 0x14000a},
+	{0x3d402180, 0x640004},
+	{0x3d402190, 0x3818200},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x100},
+	{0x3d4020f4, 0xc99},
+	{0x3d403020, 0x21},
+	{0x3d403024, 0x1f40},
+	{0x3d403050, 0x20d040},
+	{0x3d403064, 0x30007},
+	{0x3d4030dc, 0x840000},
+	{0x3d4030e0, 0x310000},
+	{0x3d4030e8, 0x66004d},
+	{0x3d4030ec, 0x16004d},
+	{0x3d403100, 0xa010102},
+	{0x3d403104, 0x30404},
+	{0x3d403108, 0x203060b},
+	{0x3d40310c, 0x505000},
+	{0x3d403110, 0x2040202},
+	{0x3d403114, 0x2030202},
+	{0x3d403118, 0x1010004},
+	{0x3d40311c, 0x301},
+	{0x3d403130, 0x20300},
+	{0x3d403134, 0xa100002},
+	{0x3d403138, 0x8},
+	{0x3d403144, 0x50003},
+	{0x3d403180, 0x190004},
+	{0x3d403190, 0x3818200},
+	{0x3d403194, 0x80303},
+	{0x3d4031b4, 0x100},
+	{0x3d4030f4, 0xc99},
+	{0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x3},
+	{0x110a3, 0x4},
+	{0x110a4, 0x5},
+	{0x110a5, 0x2},
+	{0x110a6, 0x7},
+	{0x110a7, 0x6},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x3},
+	{0x120a3, 0x2},
+	{0x120a4, 0x5},
+	{0x120a5, 0x4},
+	{0x120a6, 0x7},
+	{0x120a7, 0x6},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x21005f, 0x1ff},
+	{0x21015f, 0x1ff},
+	{0x21105f, 0x1ff},
+	{0x21115f, 0x1ff},
+	{0x21205f, 0x1ff},
+	{0x21215f, 0x1ff},
+	{0x21305f, 0x1ff},
+	{0x21315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x19},
+	{0x1200c5, 0x7},
+	{0x2200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x2},
+	{0x22002e, 0x2},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x220024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x3},
+	{0x120056, 0xa},
+	{0x220056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x21004d, 0xe00},
+	{0x21014d, 0xe00},
+	{0x21104d, 0xe00},
+	{0x21114d, 0xe00},
+	{0x21204d, 0xe00},
+	{0x21214d, 0xe00},
+	{0x21304d, 0xe00},
+	{0x21314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x210049, 0xeba},
+	{0x210149, 0xeba},
+	{0x211049, 0xeba},
+	{0x211149, 0xeba},
+	{0x212049, 0xeba},
+	{0x212149, 0xeba},
+	{0x213049, 0xeba},
+	{0x213149, 0xeba},
+	{0x43, 0x63},
+	{0x1043, 0x63},
+	{0x2043, 0x63},
+	{0x3043, 0x63},
+	{0x4043, 0x63},
+	{0x5043, 0x63},
+	{0x6043, 0x63},
+	{0x7043, 0x63},
+	{0x8043, 0x63},
+	{0x9043, 0x63},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x2ee},
+	{0x120008, 0x64},
+	{0x220008, 0x19},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x2200b2, 0xdc},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
+	{0x212043, 0x5a1},
+	{0x212143, 0x5a1},
+	{0x213043, 0x5a1},
+	{0x213143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x2200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
+	{0x200f0, 0x660},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5665},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x200c7, 0x21},
+	{0x1200c7, 0x21},
+	{0x2200c7, 0x21},
+	{0x200ca, 0x24},
+	{0x1200ca, 0x24},
+	{0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
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+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xbb8},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x101},
+	{0x54003, 0x190},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x64},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xbb8},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x5d},
+	{0x2000c, 0xbb},
+	{0x2000d, 0x753},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xc},
+	{0x12000c, 0x19},
+	{0x12000d, 0xfa},
+	{0x12000e, 0x10},
+	{0x22000b, 0x3},
+	{0x22000c, 0x6},
+	{0x22000d, 0x3e},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x220010, 0x5a},
+	{0x220011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
diff --git a/roms/u-boot/board/phytec/phycore_imx8mm/phycore-imx8mm.c b/roms/u-boot/board/phytec/phycore_imx8mm/phycore-imx8mm.c
new file mode 100644
index 000000000..ef6472916
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_imx8mm/phycore-imx8mm.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <env.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	setup_fec();
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+	switch (get_boot_device()) {
+	case SD2_BOOT:
+		env_set_ulong("mmcdev", 1);
+		break;
+	case MMC3_BOOT:
+		env_set_ulong("mmcdev", 2);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/phytec/phycore_imx8mm/spl.c b/roms/u-boot/board/phytec/phycore_imx8mm/spl.c
new file mode 100644
index 000000000..64f0780f6
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_imx8mm/spl.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	case QSPI_BOOT:
+		return BOOT_DEVICE_NOR;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+
+	arch_cpu_init();
+
+	init_uart_clk(2);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000", &dev);
+	if (ret < 0) {
+		printf("Failed to find clock node. Check device tree\n");
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/phytec/phycore_imx8mp/Kconfig b/roms/u-boot/board/phytec/phycore_imx8mp/Kconfig
new file mode 100644
index 000000000..7a20d6e8f
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_imx8mp/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PHYCORE_IMX8MP
+
+config SYS_BOARD
+	default "phycore_imx8mp"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "phycore_imx8mp"
+
+endif
diff --git a/roms/u-boot/board/phytec/phycore_imx8mp/MAINTAINERS b/roms/u-boot/board/phytec/phycore_imx8mp/MAINTAINERS
new file mode 100644
index 000000000..cb7ce558a
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_imx8mp/MAINTAINERS
@@ -0,0 +1,9 @@
+phyCORE-i.MX8M Plus
+M:      Teresa Remmet <t.remmet@phytec.de>
+W:      https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-plus/
+S:      Maintained
+F:      arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
+F:      arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
+F:      board/phytec/phycore_imx8mp/
+F:      configs/phycore-imx8mp_defconfig
+F:      include/configs/phycore_imx8mp.h
diff --git a/roms/u-boot/board/phytec/phycore_imx8mp/Makefile b/roms/u-boot/board/phytec/phycore_imx8mp/Makefile
new file mode 100644
index 000000000..c4c434c94
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_imx8mp/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2020 PHYTEC Messtechnik GmbH
+# Author: Teresa Remmet <t.remmet@phytec.de>
+
+obj-y += phycore-imx8mp.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/roms/u-boot/board/phytec/phycore_imx8mp/lpddr4_timing.c b/roms/u-boot/board/phytec/phycore_imx8mp/lpddr4_timing.c
new file mode 100644
index 000000000..e59dd7437
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_imx8mp/lpddr4_timing.c
@@ -0,0 +1,1849 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2020 Phytec Messtechnik GmbH
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400020, 0x323 },
+	{ 0x3d400024, 0x1e84800 },
+	{ 0x3d400064, 0x7a0118 },
+	{ 0x3d4000d0, 0xc00307a3 },
+	{ 0x3d4000d4, 0xc50000 },
+	{ 0x3d4000dc, 0xf4003f },
+	{ 0x3d4000e0, 0x330000 },
+	{ 0x3d4000e8, 0x660048 },
+	{ 0x3d4000ec, 0x160048 },
+	{ 0x3d400100, 0x2028222a },
+	{ 0x3d400104, 0x807bf },
+	{ 0x3d40010c, 0xe0e000 },
+	{ 0x3d400110, 0x12040a12 },
+	{ 0x3d400114, 0x2050f0f },
+	{ 0x3d400118, 0x1010009 },
+	{ 0x3d40011c, 0x501 },
+	{ 0x3d400130, 0x20800 },
+	{ 0x3d400134, 0xe100002 },
+	{ 0x3d400138, 0x120 },
+	{ 0x3d400144, 0xc80064 },
+	{ 0x3d400180, 0x3e8001e },
+	{ 0x3d400184, 0x3207a12 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x49f820e },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x1f0e },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x9121c1c },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf07 },
+	{ 0x3d400250, 0x1f05 },
+	{ 0x3d400254, 0x1f },
+	{ 0x3d400264, 0x90003ff },
+	{ 0x3d40026c, 0x20003ff },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x1000e00 },
+	{ 0x3d400498, 0x3ff0000 },
+	{ 0x3d40049c, 0x1000e00 },
+	{ 0x3d4004a0, 0x3ff0000 },
+	{ 0x3d402020, 0x21 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x330000 },
+	{ 0x3d4020e8, 0x660048 },
+	{ 0x3d4020ec, 0x160048 },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x21 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x330000 },
+	{ 0x3d4030e8, 0x660048 },
+	{ 0x3d4030ec, 0x160048 },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x18 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x3e8 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x1204a, 0x500 },
+	{ 0x1304a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xfa0 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x3ff4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x3ff4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xf400 },
+	{ 0x54033, 0x333f },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xf400 },
+	{ 0x54039, 0x333f },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xfa0 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x3ff4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x3ff4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xf400 },
+	{ 0x54033, 0x333f },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xf400 },
+	{ 0x54039, 0x333f },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x1 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x448 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0xf },
+	{ 0x9016b, 0x7c0 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x0 },
+	{ 0x9016e, 0xe8 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x47 },
+	{ 0x90171, 0x630 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x8 },
+	{ 0x90174, 0x618 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0xe0 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x7c8 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x8 },
+	{ 0x9017d, 0x8140 },
+	{ 0x9017e, 0x10c },
+	{ 0x9017f, 0x0 },
+	{ 0x90180, 0x478 },
+	{ 0x90181, 0x109 },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x7d },
+	{ 0x2000c, 0xfa },
+	{ 0x2000d, 0x9c4 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 4000mts 1D */
+		.drate = 4000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 4000mts 2D */
+		.drate = 4000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 4000, 400, 100, },
+};
diff --git a/roms/u-boot/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/roms/u-boot/board/phytec/phycore_imx8mp/phycore-imx8mp.c
new file mode 100644
index 000000000..67649078c
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_imx8mp/phycore-imx8mp.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <env.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+	switch (get_boot_device()) {
+	case SD2_BOOT:
+		env_set_ulong("mmcdev", 1);
+		break;
+	case MMC3_BOOT:
+		env_set_ulong("mmcdev", 2);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/phytec/phycore_imx8mp/spl.c b/roms/u-boot/board/phytec/phycore_imx8mp/spl.c
new file mode 100644
index 000000000..f9fa8d1e1
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_imx8mp/spl.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+
+	ret = power_pca9450_init(0, 0x25);
+	if (ret)
+		printf("power init failed");
+	p = pmic_get("PCA9450");
+	pmic_probe(p);
+
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+
+	/* increase VDD_SOC to typical value 0.95V */
+	pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
+
+	/* set WDOG_B_CFG to cold reset */
+	pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
+
+	return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+
+#define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	arch_cpu_init();
+
+	init_uart_clk(1);
+
+	board_early_init_f();
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	preloader_console_init();
+
+	enable_tzc380();
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
diff --git a/roms/u-boot/board/phytec/phycore_rk3288/Kconfig b/roms/u-boot/board/phytec/phycore_rk3288/Kconfig
new file mode 100644
index 000000000..57cd8e26e
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PHYCORE_RK3288
+
+config SYS_BOARD
+	default "phycore_rk3288"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "phycore_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/phytec/phycore_rk3288/MAINTAINERS b/roms/u-boot/board/phytec/phycore_rk3288/MAINTAINERS
new file mode 100644
index 000000000..9c0de3cc8
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+phyCORE-RK3288
+M:	Wadim Egorov <w.egorov@phytec.de>
+S:	Maintained
+F:	board/phytec/phycore_rk3288
+F:	include/configs/phycore_rk3288.h
+F:	configs/phycore-rk3288_defconfig
diff --git a/roms/u-boot/board/phytec/phycore_rk3288/Makefile b/roms/u-boot/board/phytec/phycore_rk3288/Makefile
new file mode 100644
index 000000000..f379fbe93
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_rk3288/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2017 PHYTEC Messtechnik GmbH
+# Author: Wadim Egorov <w.egorov@phytec.de>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += phycore-rk3288.o
diff --git a/roms/u-boot/board/phytec/phycore_rk3288/phycore-rk3288.c b/roms/u-boot/board/phytec/phycore_rk3288/phycore-rk3288.c
new file mode 100644
index 000000000..f588fc3b0
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_rk3288/phycore-rk3288.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ */
+
+#include <eeprom.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <env_internal.h>
+#include <i2c.h>
+#include <i2c_eeprom.h>
+#include <netdev.h>
+#include <linux/bitops.h>
+#include "som.h"
+#include <power/regulator.h>
+#include <power/rk8xx_pmic.h>
+
+static int valid_rk3288_som(struct rk3288_som *som)
+{
+	unsigned char *p = (unsigned char *)som;
+	unsigned char *e = p + sizeof(struct rk3288_som) - 1;
+	int hw = 0;
+
+	while (p < e) {
+		hw += hweight8(*p);
+		p++;
+	}
+
+	return hw == som->bs;
+}
+
+int rk3288_board_late_init(void)
+{
+	int ret;
+	struct udevice *dev;
+	struct rk3288_som opt;
+	int off;
+
+	/* Get the identificatioin page of M24C32-D EEPROM */
+	off = fdt_path_offset(gd->fdt_blob, "eeprom0");
+	if (off < 0) {
+		printf("%s: No eeprom0 path offset\n", __func__);
+		return off;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+	if (ret) {
+		printf("%s: Could not find EEPROM\n", __func__);
+		return ret;
+	}
+
+	ret = i2c_set_chip_offset_len(dev, 2);
+	if (ret)
+		return ret;
+
+	ret = i2c_eeprom_read(dev, 0, (uint8_t *)&opt,
+				sizeof(struct rk3288_som));
+	if (ret) {
+		printf("%s: Could not read EEPROM\n", __func__);
+		return ret;
+	}
+
+	if (opt.api_version != 0 || !valid_rk3288_som(&opt)) {
+		printf("Invalid data or wrong EEPROM layout version.\n");
+		/* Proceed anyway, since there is no fallback option */
+	}
+
+	if (is_valid_ethaddr(opt.mac))
+		eth_env_set_enetaddr("ethaddr", opt.mac);
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#if !defined(CONFIG_SPL_OF_PLATDATA)
+static int phycore_init(void)
+{
+	struct udevice *pmic;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
+	if (ret)
+		return ret;
+
+#if defined(CONFIG_SPL_POWER_SUPPORT)
+	/* Increase USB input current to 2A */
+	ret = rk818_spl_configure_usb_input_current(pmic, 2000);
+	if (ret)
+		return ret;
+
+	/* Close charger when USB lower then 3.26V */
+	ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+#if !defined(CONFIG_SPL_OF_PLATDATA)
+	int ret;
+
+	if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
+		ret = phycore_init();
+		if (ret) {
+			debug("Failed to set up phycore power settings: %d\n",
+			      ret);
+			return;
+		}
+	}
+#endif
+}
+#endif
diff --git a/roms/u-boot/board/phytec/phycore_rk3288/som.h b/roms/u-boot/board/phytec/phycore_rk3288/som.h
new file mode 100644
index 000000000..f627264f5
--- /dev/null
+++ b/roms/u-boot/board/phytec/phycore_rk3288/som.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ */
+
+/*
+ * rk3288_som struct represents the eeprom layout for PHYTEC RK3288 based SoMs
+ */
+struct rk3288_som {
+	unsigned char api_version;	/* EEPROM layout API version */
+	unsigned char mod_version;	/* PCM/PFL/PCA */
+	unsigned char option[12];	/* coding for variants */
+	unsigned char som_rev;		/* SOM revision */
+	unsigned char mac[6];
+	unsigned char ksp;		/* 1: KSP, 2: KSM */
+	unsigned char kspno;		/* Number for KSP/KSM module */
+	unsigned char reserved[8];	/* not used */
+	unsigned char bs;		/* Bits set in previous bytes */
+} __attribute__ ((__packed__));
diff --git a/roms/u-boot/board/phytium/durian/Kconfig b/roms/u-boot/board/phytium/durian/Kconfig
new file mode 100644
index 000000000..dc0710925
--- /dev/null
+++ b/roms/u-boot/board/phytium/durian/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DURIAN
+
+config SYS_BOARD
+	default "durian"
+
+config SYS_VENDOR
+	default "phytium"
+
+config SYS_CONFIG_NAME
+	default "durian"
+
+endif
diff --git a/roms/u-boot/board/phytium/durian/MAINTAINERS b/roms/u-boot/board/phytium/durian/MAINTAINERS
new file mode 100644
index 000000000..895b7621e
--- /dev/null
+++ b/roms/u-boot/board/phytium/durian/MAINTAINERS
@@ -0,0 +1,8 @@
+DURIAN BOARD
+M:	liuhao <liuhao@phytium.com.cn>
+M:	shuyiqi <shuyiqi@phytium.com.cn>
+S:	Maintained
+F:	board/phytium/durian/*
+F:	include/configs/durian.h
+F:	configs/durian_defconfig
+
diff --git a/roms/u-boot/board/phytium/durian/Makefile b/roms/u-boot/board/phytium/durian/Makefile
new file mode 100644
index 000000000..c2fbf1983
--- /dev/null
+++ b/roms/u-boot/board/phytium/durian/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019
+# shuyiqi  <shuyiqi@phytium.com.cn>
+# liuhao   <liuhao@phytium.com.cn>
+#
+
+obj-y += durian.o
+
diff --git a/roms/u-boot/board/phytium/durian/README b/roms/u-boot/board/phytium/durian/README
new file mode 100644
index 000000000..4443133e1
--- /dev/null
+++ b/roms/u-boot/board/phytium/durian/README
@@ -0,0 +1,59 @@
+Here is the step-by-step to boot U-Boot on phytium durian board.
+
+Compile U-Boot
+==============
+  > make durian_defconfig
+  > make
+
+Get the prebuild binary about BPF
+=================================
+  > cd ../
+  > git clone https://github.com/phytium-durian/bpf.git
+
+Package the image
+=================
+  > cd bpf
+  > cp ../u-boot/u-boot.bin ./
+  > ./dopack
+
+  The fip-all.bin is the final image.
+
+Flash the image into the spi nor-flash
+======================================
+  Any spi nor-flash and appropriate tool can be used to flash.
+  For example, we choose the S25FL256 chip that produced from
+  SPANSION company and EZP_XPro V1.2.
+
+Reset the board, you can get U-Boot log message from boot console:
+
+Power on...
+Start pcie setup!
+End pcie setup!
+Start ddr setup!
+End ddr setup!
+Jump to entrypoint: 0x500000
+
+U-Boot 2019.10-00594-g9ccc1b17ea-dirty (Oct 18 2019 - 00:17:09 +0800)
+
+DRAM:  1.9 GiB
+In:    uart@28001000
+Out:   uart@28001000
+Err:   uart@28001000
+scanning bus for devices...
+Target spinup took 0 ms.
+SATA link 1 timeout.
+SATA link 2 timeout.
+SATA link 3 timeout.
+AHCI 0001.0000 32 slots 4 ports 6 Gbps 0xf impl SATA mode
+flags: 64bit ncq led only pmp fbss pio slum part sxs
+  Device 0: (0:0) Vendor: ATA Prod.: ST1000DM010-2EP1 Rev: CC43
+            Type: Hard Disk
+            Capacity: 953869.7 MB = 931.5 GB (1953525168 x 512)
+SATA link 0 timeout.
+SATA link 1 timeout.
+SATA link 2 timeout.
+SATA link 3 timeout.
+AHCI 0001.0000 32 slots 4 ports 6 Gbps 0xf impl SATA mode
+flags: 64bit ncq led only pmp fbss pio slum part sxs
+Hit any key to stop autoboot:  0
+durian#
diff --git a/roms/u-boot/board/phytium/durian/cpu.h b/roms/u-boot/board/phytium/durian/cpu.h
new file mode 100644
index 000000000..a5a213d30
--- /dev/null
+++ b/roms/u-boot/board/phytium/durian/cpu.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019
+ * Phytium Technology Ltd <www.phytium.com>
+ * shuyiqi <shuyiqi@phytium.com.cn>
+ */
+
+#ifndef _FT_DURIAN_H
+#define _FT_DURIAN_H
+
+/* FLUSH L3 CASHE */
+#define HNF_COUNT           0x8
+#define HNF_PSTATE_REQ      (HNF_BASE + 0x10)
+#define HNF_PSTATE_STAT     (HNF_BASE + 0x18)
+#define HNF_PSTATE_OFF      0x0
+#define HNF_PSTATE_SFONLY   0x1
+#define HNF_PSTATE_HALF     0x2
+#define HNF_PSTATE_FULL     0x3
+#define HNF_STRIDE          0x10000
+#define HNF_BASE            (unsigned long)(0x3A200000)
+
+#endif /* _FT_DURIAN_H */
+
diff --git a/roms/u-boot/board/phytium/durian/durian.c b/roms/u-boot/board/phytium/durian/durian.c
new file mode 100644
index 000000000..ef13f7cff
--- /dev/null
+++ b/roms/u-boot/board/phytium/durian/durian.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * shuyiqi <shuyiqi@phytium.com.cn>
+ * liuhao  <liuhao@phytium.com.cn>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <log.h>
+#include <asm/armv8/mmu.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <linux/arm-smccc.h>
+#include <linux/kernel.h>
+#include <scsi.h>
+#include "cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->mem_clk = 0;
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
+	debug("reset cpu error, %lx\n", res.a0);
+}
+
+static struct mm_region durian_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				 PTE_BLOCK_NON_SHARE |
+				 PTE_BLOCK_PXN |
+				 PTE_BLOCK_UXN
+	},
+	{
+		.virt = (u64)PHYS_SDRAM_1,
+		.phys = (u64)PHYS_SDRAM_1,
+		.size = (u64)PHYS_SDRAM_1_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				 PTE_BLOCK_NS |
+				 PTE_BLOCK_INNER_SHARE
+	},
+	{
+		0,
+	}
+};
+
+struct mm_region *mem_map = durian_mem_map;
+
+int print_cpuinfo(void)
+{
+	printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk);
+	return 0;
+}
+
+int __asm_flush_l3_dcache(void)
+{
+	int i, pstate;
+
+	for (i = 0; i < HNF_COUNT; i++)
+		writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
+	for (i = 0; i < HNF_COUNT; i++) {
+		do {
+			pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
+		} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
+	}
+
+	for (i = 0; i < HNF_COUNT; i++)
+		writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	int ret;
+
+	/* pci e */
+	pci_init();
+	/* scsi scan */
+	ret = scsi_scan(true);
+	if (ret) {
+		printf("scsi scan failed\n");
+		return CMD_RET_FAILURE;
+	}
+	return ret;
+}
+
diff --git a/roms/u-boot/board/pine64/pinebook-pro-rk3399/Kconfig b/roms/u-boot/board/pine64/pinebook-pro-rk3399/Kconfig
new file mode 100644
index 000000000..3bb7ca448
--- /dev/null
+++ b/roms/u-boot/board/pine64/pinebook-pro-rk3399/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PINEBOOK_PRO_RK3399
+
+config SYS_BOARD
+	default "pinebook-pro-rk3399"
+
+config SYS_VENDOR
+	default "pine64"
+
+config SYS_CONFIG_NAME
+	default "pinebook-pro-rk3399"
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/pine64/pinebook-pro-rk3399/MAINTAINERS b/roms/u-boot/board/pine64/pinebook-pro-rk3399/MAINTAINERS
new file mode 100644
index 000000000..227c1c0be
--- /dev/null
+++ b/roms/u-boot/board/pine64/pinebook-pro-rk3399/MAINTAINERS
@@ -0,0 +1,8 @@
+PINEBOOK_PRO
+M:	Peter Robinson <pbrobinson@gmail.com>
+S:	Maintained
+F:	board/pine64/rk3399-pinebook-pro/
+F:	include/configs/rk3399-pinebook-pro.h
+F:	arch/arm/dts/rk3399-pinebook-pro.dts
+F:	arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
+F:	configs/pinebook-pro-rk3399_defconfig
diff --git a/roms/u-boot/board/pine64/pinebook-pro-rk3399/Makefile b/roms/u-boot/board/pine64/pinebook-pro-rk3399/Makefile
new file mode 100644
index 000000000..2f692a12a
--- /dev/null
+++ b/roms/u-boot/board/pine64/pinebook-pro-rk3399/Makefile
@@ -0,0 +1 @@
+obj-y	+= pinebook-pro-rk3399.o
diff --git a/roms/u-boot/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/roms/u-boot/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
new file mode 100644
index 000000000..516292aaa
--- /dev/null
+++ b/roms/u-boot/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2020 Peter Robinson <pbrobinson at gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/misc.h>
+#include <power/regulator.h>
+
+#define GRF_IO_VSEL_BT565_SHIFT 0
+#define PMUGRF_CON0_VSEL_SHIFT 8
+
+#ifndef CONFIG_SPL_BUILD
+int board_early_init_f(void)
+{
+	struct udevice *regulator;
+	int ret;
+
+	ret = regulator_get_by_platname("vcc5v0_usb", &regulator);
+	if (ret) {
+		pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret);
+		goto out;
+	}
+
+	ret = regulator_set_enable(regulator, true);
+	if (ret)
+		pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret);
+
+out:
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+static void setup_iodomain(void)
+{
+	struct rk3399_grf_regs *grf =
+	   syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	struct rk3399_pmugrf_regs *pmugrf =
+	   syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+
+	/* BT565 is in 1.8v domain */
+	rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
+
+	/* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
+	rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
+}
+
+int misc_init_r(void)
+{
+	const u32 cpuid_offset = 0x7;
+	const u32 cpuid_length = 0x10;
+	u8 cpuid[cpuid_length];
+	int ret;
+
+	setup_iodomain();
+
+	ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+	if (ret)
+		return ret;
+
+	ret = rockchip_cpuid_set(cpuid, cpuid_length);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+#endif
diff --git a/roms/u-boot/board/pine64/rockpro64_rk3399/Kconfig b/roms/u-boot/board/pine64/rockpro64_rk3399/Kconfig
new file mode 100644
index 000000000..3353f1fd0
--- /dev/null
+++ b/roms/u-boot/board/pine64/rockpro64_rk3399/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROCKPRO64_RK3399
+
+config SYS_BOARD
+	default "rockpro64_rk3399"
+
+config SYS_VENDOR
+	default "pine64"
+
+config SYS_CONFIG_NAME
+	default "rockpro64_rk3399"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/pine64/rockpro64_rk3399/MAINTAINERS b/roms/u-boot/board/pine64/rockpro64_rk3399/MAINTAINERS
new file mode 100644
index 000000000..303db144a
--- /dev/null
+++ b/roms/u-boot/board/pine64/rockpro64_rk3399/MAINTAINERS
@@ -0,0 +1,8 @@
+ROCKPRO64
+M:	Akash Gajjar <akash@openedev.com>
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	board/pine64/rockpro64_rk3399
+F:	include/configs/rockpro64_rk3399.h
+F:	arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
+F:	configs/rockpro64-rk3399_defconfig
diff --git a/roms/u-boot/board/pine64/rockpro64_rk3399/Makefile b/roms/u-boot/board/pine64/rockpro64_rk3399/Makefile
new file mode 100644
index 000000000..b015c47e6
--- /dev/null
+++ b/roms/u-boot/board/pine64/rockpro64_rk3399/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2019 Vasily Khoruzhick
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= rockpro64-rk3399.o
diff --git a/roms/u-boot/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c b/roms/u-boot/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
new file mode 100644
index 000000000..d79084614
--- /dev/null
+++ b/roms/u-boot/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Vasily Khoruzhick <anarsoul@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/misc.h>
+
+#define GRF_IO_VSEL_BT565_SHIFT 0
+#define PMUGRF_CON0_VSEL_SHIFT 8
+
+#ifdef CONFIG_MISC_INIT_R
+static void setup_iodomain(void)
+{
+	struct rk3399_grf_regs *grf =
+	    syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	struct rk3399_pmugrf_regs *pmugrf =
+	    syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+
+	/* BT565 is in 1.8v domain */
+	rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
+
+	/* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
+	rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
+}
+
+int misc_init_r(void)
+{
+	const u32 cpuid_offset = 0x7;
+	const u32 cpuid_length = 0x10;
+	u8 cpuid[cpuid_length];
+	int ret;
+
+	setup_iodomain();
+
+	ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+	if (ret)
+		return ret;
+
+	ret = rockchip_cpuid_set(cpuid, cpuid_length);
+	if (ret)
+		return ret;
+
+	ret = rockchip_setup_macaddr();
+
+	return ret;
+}
+
+#endif
diff --git a/roms/u-boot/board/ppcag/bg0900/Kconfig b/roms/u-boot/board/ppcag/bg0900/Kconfig
new file mode 100644
index 000000000..d7f2368a2
--- /dev/null
+++ b/roms/u-boot/board/ppcag/bg0900/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BG0900
+
+config SYS_BOARD
+	default "bg0900"
+
+config SYS_VENDOR
+	default "ppcag"
+
+config SYS_SOC
+	default "mxs"
+
+config SYS_CONFIG_NAME
+	default "bg0900"
+
+endif
diff --git a/roms/u-boot/board/ppcag/bg0900/MAINTAINERS b/roms/u-boot/board/ppcag/bg0900/MAINTAINERS
new file mode 100644
index 000000000..853c0d59c
--- /dev/null
+++ b/roms/u-boot/board/ppcag/bg0900/MAINTAINERS
@@ -0,0 +1,6 @@
+BG0900 BOARD
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+F:	board/ppcag/bg0900/
+F:	include/configs/bg0900.h
+F:	configs/bg0900_defconfig
diff --git a/roms/u-boot/board/ppcag/bg0900/Makefile b/roms/u-boot/board/ppcag/bg0900/Makefile
new file mode 100644
index 000000000..540bd9dc1
--- /dev/null
+++ b/roms/u-boot/board/ppcag/bg0900/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ifndef	CONFIG_SPL_BUILD
+obj-y	:= bg0900.o
+else
+obj-y	:= spl_boot.o
+endif
diff --git a/roms/u-boot/board/ppcag/bg0900/bg0900.c b/roms/u-boot/board/ppcag/bg0900/bg0900.c
new file mode 100644
index 000000000..578f5c73b
--- /dev/null
+++ b/roms/u-boot/board/ppcag/bg0900/bg0900.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PPC-AG BG0900 board
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/delay.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+	/* IO1 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+	/* SSP2 clock at 160MHz */
+	mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(struct bd_info *bis)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct eth_device *dev;
+	int ret;
+
+	ret = cpu_eth_init(bis);
+
+	/* BG0900 uses ENET_CLK PAD to drive FEC clock */
+	writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
+	       &clkctrl_regs->hw_clkctrl_enet);
+
+	/* Reset FEC PHYs */
+	gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
+	udelay(200);
+	gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
+
+	ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+	if (ret) {
+		puts("FEC MXS: Unable to init FEC0\n");
+		return ret;
+	}
+
+	dev = eth_get_dev_by_name("FEC0");
+	if (!dev) {
+		puts("FEC MXS: Unable to get FEC0 device entry\n");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+#endif
diff --git a/roms/u-boot/board/ppcag/bg0900/spl_boot.c b/roms/u-boot/board/ppcag/bg0900/spl_boot.c
new file mode 100644
index 000000000..b46bc8939
--- /dev/null
+++ b/roms/u-boot/board/ppcag/bg0900/spl_boot.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PPC-AG BG0900 Boot setup
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_GPMI	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* DUART */
+	MX28_PAD_PWM0__DUART_RX,
+	MX28_PAD_PWM1__DUART_TX,
+
+	/* GPMI NAND */
+	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RDN__GPMI_RDN |
+		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+
+	/* FEC0 */
+	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+	/* FEC0 Reset */
+	MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
+		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+	/* EMI */
+	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+	/* SPI2 (for SPI flash) */
+	MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_SS0__SSP2_D3 |
+		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+};
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+	/*
+	 * DDR Controller Registers
+	 * Manufacturer:	Winbond
+	 * Device Part Number:	W972GG6JB-25I
+	 * Clock Freq.:		200MHz
+	 * Density:		2Gb
+	 * Chip Selects:	1
+	 * Number of Banks:	8
+	 * Row address:		14
+	 * Column address:	10
+	 */
+
+	dram_vals[0x74 / 4] = 0x0102010A;
+	dram_vals[0x98 / 4] = 0x04005003;
+	dram_vals[0x9c / 4] = 0x090000c8;
+
+	dram_vals[0xa8 / 4] = 0x0036b009;
+	dram_vals[0xac / 4] = 0x03270612;
+
+	dram_vals[0xb0 / 4] = 0x02020202;
+	dram_vals[0xb4 / 4] = 0x00c80029;
+
+	dram_vals[0xc0 / 4] = 0x00011900;
+
+	dram_vals[0x12c / 4] = 0x07400300;
+	dram_vals[0x130 / 4] = 0x07400300;
+	dram_vals[0x2c4 / 4] = 0x02030303;
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/roms/u-boot/board/qca/ap121/Kconfig b/roms/u-boot/board/qca/ap121/Kconfig
new file mode 100644
index 000000000..4fd6a7167
--- /dev/null
+++ b/roms/u-boot/board/qca/ap121/Kconfig
@@ -0,0 +1,27 @@
+if TARGET_AP121
+
+config SYS_VENDOR
+	default "qca"
+
+config SYS_BOARD
+	default "ap121"
+
+config SYS_CONFIG_NAME
+	default "ap121"
+
+config SYS_TEXT_BASE
+	default 0x9f000000
+
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_ICACHE_LINE_SIZE
+	default 32
+
+endif
diff --git a/roms/u-boot/board/qca/ap121/MAINTAINERS b/roms/u-boot/board/qca/ap121/MAINTAINERS
new file mode 100644
index 000000000..8b02988d6
--- /dev/null
+++ b/roms/u-boot/board/qca/ap121/MAINTAINERS
@@ -0,0 +1,6 @@
+AP121 BOARD
+M:	Wills Wang <wills.wang@live.com>
+S:	Maintained
+F:	board/qca/ap121/
+F:	include/configs/ap121.h
+F:	configs/ap121_defconfig
diff --git a/roms/u-boot/board/qca/ap121/Makefile b/roms/u-boot/board/qca/ap121/Makefile
new file mode 100644
index 000000000..7cdf53cf9
--- /dev/null
+++ b/roms/u-boot/board/qca/ap121/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	= ap121.o
diff --git a/roms/u-boot/board/qca/ap121/ap121.c b/roms/u-boot/board/qca/ap121/ap121.c
new file mode 100644
index 000000000..60a2e1914
--- /dev/null
+++ b/roms/u-boot/board/qca/ap121/ap121.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <mach/ath79.h>
+#include <debug_uart.h>
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+			   MAP_NOCACHE);
+
+	/*
+	 * GPIO9 as input, GPIO10 as output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OE);
+	val &= ~AR933X_GPIO(9);
+	val |= AR933X_GPIO(10);
+	writel(val, regs + AR71XX_GPIO_REG_OE);
+
+	/*
+	 * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_FUNC);
+	val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE;
+	writel(val, regs + AR71XX_GPIO_REG_FUNC);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	ddr_init();
+	ath79_eth_reset();
+	return 0;
+}
diff --git a/roms/u-boot/board/qca/ap143/Kconfig b/roms/u-boot/board/qca/ap143/Kconfig
new file mode 100644
index 000000000..74c632a03
--- /dev/null
+++ b/roms/u-boot/board/qca/ap143/Kconfig
@@ -0,0 +1,27 @@
+if TARGET_AP143
+
+config SYS_VENDOR
+	default "qca"
+
+config SYS_BOARD
+	default "ap143"
+
+config SYS_CONFIG_NAME
+	default "ap143"
+
+config SYS_TEXT_BASE
+	default 0x9f000000
+
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_ICACHE_LINE_SIZE
+	default 32
+
+endif
diff --git a/roms/u-boot/board/qca/ap143/MAINTAINERS b/roms/u-boot/board/qca/ap143/MAINTAINERS
new file mode 100644
index 000000000..11cb14fc7
--- /dev/null
+++ b/roms/u-boot/board/qca/ap143/MAINTAINERS
@@ -0,0 +1,6 @@
+AP143 BOARD
+M:	Wills Wang <wills.wang@live.com>
+S:	Maintained
+F:	board/qca/ap143/
+F:	include/configs/ap143.h
+F:	configs/ap143_defconfig
diff --git a/roms/u-boot/board/qca/ap143/Makefile b/roms/u-boot/board/qca/ap143/Makefile
new file mode 100644
index 000000000..bf9fd83af
--- /dev/null
+++ b/roms/u-boot/board/qca/ap143/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	= ap143.o
diff --git a/roms/u-boot/board/qca/ap143/ap143.c b/roms/u-boot/board/qca/ap143/ap143.c
new file mode 100644
index 000000000..ac6505413
--- /dev/null
+++ b/roms/u-boot/board/qca/ap143/ap143.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <mach/ath79.h>
+#include <debug_uart.h>
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+			   MAP_NOCACHE);
+
+	/*
+	 * GPIO9 as input, GPIO10 as output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OE);
+	val |= QCA953X_GPIO(9);
+	val &= ~QCA953X_GPIO(10);
+	writel(val, regs + AR71XX_GPIO_REG_OE);
+
+	/*
+	 * Enable GPIO10 as UART0_SOUT
+	 */
+	val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
+	val &= ~QCA953X_GPIO_MUX_MASK(16);
+	val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
+	writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
+
+	/*
+	 * Enable GPIO9 as UART0_SIN
+	 */
+	val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
+	val &= ~QCA953X_GPIO_MUX_MASK(8);
+	val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
+	writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
+
+	/*
+	 * Enable GPIO10 output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OUT);
+	val |= QCA953X_GPIO(10);
+	writel(val, regs + AR71XX_GPIO_REG_OUT);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	ddr_init();
+	ath79_eth_reset();
+	return 0;
+}
diff --git a/roms/u-boot/board/qca/ap152/Kconfig b/roms/u-boot/board/qca/ap152/Kconfig
new file mode 100644
index 000000000..f6ad498e8
--- /dev/null
+++ b/roms/u-boot/board/qca/ap152/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AP152
+
+config SYS_VENDOR
+	default "qca"
+
+config SYS_BOARD
+	default "ap152"
+
+config SYS_CONFIG_NAME
+	default "ap152"
+
+config SYS_TEXT_BASE
+	default 0x9f000000
+
+endif
diff --git a/roms/u-boot/board/qca/ap152/MAINTAINERS b/roms/u-boot/board/qca/ap152/MAINTAINERS
new file mode 100644
index 000000000..785ec2766
--- /dev/null
+++ b/roms/u-boot/board/qca/ap152/MAINTAINERS
@@ -0,0 +1,6 @@
+AP152 BOARD
+M:	Rosy Song <rosysong@rosinson.com>
+S:	Maintained
+F:	board/qca/ap152/
+F:	include/configs/ap152.h
+F:	configs/ap152_defconfig
diff --git a/roms/u-boot/board/qca/ap152/Makefile b/roms/u-boot/board/qca/ap152/Makefile
new file mode 100644
index 000000000..4270afa12
--- /dev/null
+++ b/roms/u-boot/board/qca/ap152/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	= ap152.o
diff --git a/roms/u-boot/board/qca/ap152/ap152.c b/roms/u-boot/board/qca/ap152/ap152.c
new file mode 100644
index 000000000..1064705d2
--- /dev/null
+++ b/roms/u-boot/board/qca/ap152/ap152.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Rosy Song <rosysong@rosinson.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <mach/ath79.h>
+#include <debug_uart.h>
+
+#define RST_RESET_RTC_RESET_LSB 27
+#define RST_RESET_RTC_RESET_MASK 0x08000000
+#define RST_RESET_RTC_RESET_SET(x) \
+	(((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK)
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+			   MAP_NOCACHE);
+
+	/* UART : RX18, TX22 done
+	 * GPIO18 as input, GPIO22 as output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OE);
+	val |= QCA956X_GPIO(18);
+	val &= ~QCA956X_GPIO(22);
+	writel(val, regs + AR71XX_GPIO_REG_OE);
+
+	/*
+	 * Enable GPIO22 as UART0_SOUT
+	 */
+	val = readl(regs + QCA956X_GPIO_REG_OUT_FUNC5);
+	val &= ~QCA956X_GPIO_MUX_MASK(16);
+	val |= QCA956X_GPIO_OUT_MUX_UART0_SOUT << 16;
+	writel(val, regs + QCA956X_GPIO_REG_OUT_FUNC5);
+
+	/*
+	 * Enable GPIO18 as UART0_SIN
+	 */
+	val = readl(regs + QCA956X_GPIO_REG_IN_ENABLE0);
+	val &= ~QCA956X_GPIO_MUX_MASK(8);
+	val |= QCA956X_GPIO_IN_MUX_UART0_SIN << 8;
+	writel(val, regs + QCA956X_GPIO_REG_IN_ENABLE0);
+
+	/*
+	 * Enable GPIO22 output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OUT);
+	val |= QCA956X_GPIO(22);
+	writel(val, regs + AR71XX_GPIO_REG_OUT);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	u32 reg;
+	void __iomem *rst_regs = map_physmem(AR71XX_RESET_BASE,
+							 AR71XX_RESET_SIZE, MAP_NOCACHE);
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	/* CPU:775, DDR:650, AHB:258 */
+	qca956x_pll_init();
+	qca956x_ddr_init();
+#endif
+
+	/* Take WMAC out of reset */
+	reg = readl(rst_regs + QCA956X_RESET_REG_RESET_MODULE);
+	reg &= (~RST_RESET_RTC_RESET_SET(1));
+	writel(reg, rst_regs + QCA956X_RESET_REG_RESET_MODULE);
+
+	ath79_eth_reset();
+	return 0;
+}
diff --git a/roms/u-boot/board/qualcomm/dragonboard410c/Kconfig b/roms/u-boot/board/qualcomm/dragonboard410c/Kconfig
new file mode 100644
index 000000000..03bd7ae30
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard410c/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_DRAGONBOARD410C
+
+config SYS_BOARD
+	default "dragonboard410c"
+
+config SYS_VENDOR
+	default "qualcomm"
+
+config SYS_SOC
+	default "apq8016"
+
+config SYS_CONFIG_NAME
+	default "dragonboard410c"
+
+endif
diff --git a/roms/u-boot/board/qualcomm/dragonboard410c/MAINTAINERS b/roms/u-boot/board/qualcomm/dragonboard410c/MAINTAINERS
new file mode 100644
index 000000000..83448f5c1
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard410c/MAINTAINERS
@@ -0,0 +1,6 @@
+DRAGONBOARD410C BOARD
+M:	Ramon Fried <rfried.dev@gmail.com>
+S:	Maintained
+F:	board/qualcomm/dragonboard410c/
+F:	include/configs/dragonboard410c.h
+F:	configs/dragonboard410c_defconfig
diff --git a/roms/u-boot/board/qualcomm/dragonboard410c/Makefile b/roms/u-boot/board/qualcomm/dragonboard410c/Makefile
new file mode 100644
index 000000000..9b452041f
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard410c/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+
+obj-y	:= dragonboard410c.o
+obj-y	+= lowlevel_init.o
+extra-y += head.o
diff --git a/roms/u-boot/board/qualcomm/dragonboard410c/dragonboard410c.c b/roms/u-boot/board/qualcomm/dragonboard410c/dragonboard410c.c
new file mode 100644
index 000000000..0d282de95
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for Dragonboard 410C
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <usb.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <fdt_support.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/misc.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* pointer to the device tree ammended by the firmware */
+extern void *fw_dtb;
+
+void *board_fdt_blob_setup(void)
+{
+	if (fdt_magic(fw_dtb) != FDT_MAGIC) {
+		printf("Firmware provided invalid dtb!\n");
+		return NULL;
+	}
+
+	return fw_dtb;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	static struct udevice *pmic_gpio;
+	static struct gpio_desc hub_reset, usb_sel;
+	int ret = 0, node;
+
+	if (!pmic_gpio) {
+		ret = uclass_get_device_by_name(UCLASS_GPIO,
+						"pm8916_gpios@c000",
+						&pmic_gpio);
+		if (ret < 0) {
+			printf("Failed to find pm8916_gpios@c000 node.\n");
+			return ret;
+		}
+	}
+
+	/* Try to request gpios needed to start usb host on dragonboard */
+	if (!dm_gpio_is_valid(&hub_reset)) {
+		node = fdt_subnode_offset(gd->fdt_blob,
+					  dev_of_offset(pmic_gpio),
+					  "usb_hub_reset_pm");
+		if (node < 0) {
+			printf("Failed to find usb_hub_reset_pm dt node.\n");
+			return node;
+		}
+		ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
+						 "gpios", 0, &hub_reset, 0);
+		if (ret < 0) {
+			printf("Failed to request usb_hub_reset_pm gpio.\n");
+			return ret;
+		}
+	}
+
+	if (!dm_gpio_is_valid(&usb_sel)) {
+		node = fdt_subnode_offset(gd->fdt_blob,
+					  dev_of_offset(pmic_gpio),
+					  "usb_sw_sel_pm");
+		if (node < 0) {
+			printf("Failed to find usb_sw_sel_pm dt node.\n");
+			return 0;
+		}
+		ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
+						 "gpios", 0, &usb_sel, 0);
+		if (ret < 0) {
+			printf("Failed to request usb_sw_sel_pm gpio.\n");
+			return ret;
+		}
+	}
+
+	if (init == USB_INIT_HOST) {
+		/* Start USB Hub */
+		dm_gpio_set_dir_flags(&hub_reset,
+				      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+		mdelay(100);
+		/* Switch usb to host connectors */
+		dm_gpio_set_dir_flags(&usb_sel,
+				      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+		mdelay(100);
+	} else { /* Device */
+		/* Disable hub */
+		dm_gpio_set_dir_flags(&hub_reset, GPIOD_IS_OUT);
+		/* Switch back to device connector */
+		dm_gpio_set_dir_flags(&usb_sel, GPIOD_IS_OUT);
+	}
+
+	return 0;
+}
+
+/* Check for vol- button - if pressed - stop autoboot */
+int misc_init_r(void)
+{
+	struct udevice *pon;
+	struct gpio_desc resin;
+	int node, ret;
+
+	ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8916_pon@800", &pon);
+	if (ret < 0) {
+		printf("Failed to find PMIC pon node. Check device tree\n");
+		return 0;
+	}
+
+	node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
+				  "key_vol_down");
+	if (node < 0) {
+		printf("Failed to find key_vol_down node. Check device tree\n");
+		return 0;
+	}
+
+	if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
+				       &resin, 0)) {
+		printf("Failed to request key_vol_down button.\n");
+		return 0;
+	}
+
+	if (dm_gpio_get_value(&resin)) {
+		env_set("bootdelay", "-1");
+		env_set("bootcmd", "fastboot 0");
+		printf("key_vol_down pressed - Starting fastboot.\n");
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	char serial[16];
+
+	memset(serial, 0, 16);
+	snprintf(serial, 13, "%x", msm_board_serial());
+	env_set("serial#", serial);
+	return 0;
+}
+
+/* Fixup of DTB for Linux Kernel
+ * 1. Fixup installed DRAM.
+ * 2. Fixup WLAN/BT Mac address:
+ *	First, check if MAC addresses for WLAN/BT exists as environemnt
+ *	variables wlanaddr,btaddr. if not, generate a unique address.
+ */
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u8 mac[ARP_HLEN];
+
+	msm_fixup_memory(blob);
+
+	if (!eth_env_get_enetaddr("wlanaddr", mac)) {
+		msm_generate_mac_addr(mac);
+	};
+
+	do_fixup_by_compat(blob, "qcom,wcnss-wlan",
+			   "local-mac-address", mac, ARP_HLEN, 1);
+
+
+	if (!eth_env_get_enetaddr("btaddr", mac)) {
+		msm_generate_mac_addr(mac);
+
+/* The BD address is same as WLAN MAC address but with
+ * least significant bit flipped.
+ */
+		mac[0] ^= 0x01;
+	};
+
+	do_fixup_by_compat(blob, "qcom,wcnss-bt",
+			   "local-bd-address", mac, ARP_HLEN, 1);
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	psci_system_reset();
+}
diff --git a/roms/u-boot/board/qualcomm/dragonboard410c/head.S b/roms/u-boot/board/qualcomm/dragonboard410c/head.S
new file mode 100644
index 000000000..33e9d305f
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard410c/head.S
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ARM64 header for proper chain-loading with Little Kernel.
+ *
+ * Little Kernel shipped with Dragonboard410C boots standard Linux images for
+ * ARM64. This file adds header that is required to boot U-Boot properly.
+ *
+ * For details see:
+ * https://www.kernel.org/doc/Documentation/arm64/booting.txt
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ */
+
+#include <config.h>
+
+.global _arm64_header
+_arm64_header:
+	b _start
+	.word 0
+	/* Image load offset from start of RAM, little-endian */
+	.quad   CONFIG_SYS_TEXT_BASE-PHYS_SDRAM_1
+	/* Effective size of kernel image, little-endian */
+	.quad   0 /* 0x60000 - ignored */
+	/* Informative flags, little-endian */
+	.quad   0
+	.quad   0                               /* reserved */
+	.quad   0                               /* reserved */
+	.quad   0                               /* reserved */
+	.byte   0x41                            /* Magic number, "ARM\x64" */
+	.byte   0x52
+	.byte   0x4d
+	.byte   0x64
+	.word   0                               /* reserved */
diff --git a/roms/u-boot/board/qualcomm/dragonboard410c/lowlevel_init.S b/roms/u-boot/board/qualcomm/dragonboard410c/lowlevel_init.S
new file mode 100644
index 000000000..762fed561
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard410c/lowlevel_init.S
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016
+ * Cédric Schieli <cschieli@gmail.com>
+ */
+
+#include <config.h>
+
+.align 8
+.global fw_dtb
+fw_dtb:
+	.dword 0x0
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: save ATAG/FDT address provided by the firmware at boot time
+ */
+
+.global save_boot_params
+save_boot_params:
+
+	/* The firmware provided ATAG/FDT address can be found in r2/x0 */
+	adr	x8, fw_dtb
+	str	x0, [x8]
+
+	/* Returns */
+	b	save_boot_params_ret
diff --git a/roms/u-boot/board/qualcomm/dragonboard410c/readme.txt b/roms/u-boot/board/qualcomm/dragonboard410c/readme.txt
new file mode 100644
index 000000000..a90d0f52e
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard410c/readme.txt
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+
+Build & Run instructions:
+
+1) Install mkbootimg and dtbTool from
+   git://codeaurora.org/quic/kernel/skales (15ece94f09 worked for me)
+2) Setup CROSS_COMPILE to aarch64 compiler
+3) make dragonboard410c_config
+4) make
+5) generate fake, empty ramdisk (can have 0 bytes)
+$ touch rd
+
+6) Generate qualcomm device tree table with dtbTool [1]
+$ dtbTool -o dt.img arch/arm/dts
+
+7) Generate Android boot image with mkbootimg [2]:
+$ mkbootimg --kernel=u-boot-dtb.bin --output=u-boot.img --dt=dt.img  \
+  --pagesize 2048 --base 0x80000000 --ramdisk=rd --cmdline=""
+
+8) Enter fastboot (reboot board with vol- button pressed)
+
+9) Boot it:
+$ fastboot boot u-boot.img
+or flash as kernel:
+$ fastboot flash boot u-boot.img
+$ fastboot reboot
+
+
+What is working:
+- UART
+- GPIO (SoC)
+- SD
+- eMMC
+- Reset
+- USB in EHCI mode (usb starts does switch device->host, usb stop does the opposite)
+- PMIC GPIOS (but not in generic subsystem)
+- PMIC "special" buttons (power, vol-)
+
+What is not working / known bugs:
+- SDHCI is slow (~2.5MiB/s for SD and eMMC)
+
+[1] To boot any kernel image, Little Kernel requires valid device tree for the
+platform it runs on. dtbTool creates device tree table that Little Kernel scans.
+Later on proper device tree is passed to next boot stage.
+Full device tree is not required to boot u-boot. Enough would be:
+/dts-v1/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. Dragonboard 410c";
+	compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
+	qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
+	qcom,board-id = <0x10018 0x0>;
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	chosen { };
+	aliases { };
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0x3da00000>;
+	};
+};
+
+but for simplicity (and because size of image is not that critical) we use
+existing Qualcomm device trees.
+
+[2] Note that ramdisk is required, even if it is unused.
diff --git a/roms/u-boot/board/qualcomm/dragonboard410c/u-boot.lds b/roms/u-boot/board/qualcomm/dragonboard410c/u-boot.lds
new file mode 100644
index 000000000..fc1bba8cf
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard410c/u-boot.lds
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Override linker script for fastboot-readable images
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_arm64_header)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(8);
+	.text :
+	{
+		*(.__image_copy_start)
+		board/qualcomm/dragonboard410c/head.o (.text*)
+		CPUDIR/start.o (.text*)
+	}
+
+	/* This needs to come before *(.text*) */
+	.efi_runtime : {
+                __efi_runtime_start = .;
+		*(.text.efi_runtime*)
+		*(.rodata.efi_runtime*)
+		*(.data.efi_runtime*)
+                __efi_runtime_stop = .;
+	}
+
+	.text_rest :
+	{
+		*(.text*)
+	}
+
+	. = ALIGN(8);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(8);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(8);
+
+	. = .;
+
+	. = ALIGN(8);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(8);
+
+	.efi_runtime : {
+                __efi_runtime_start = .;
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+                __efi_runtime_stop = .;
+	}
+
+	.efi_runtime_rel : {
+                __efi_runtime_rel_start = .;
+		*(.rel*.efi_runtime)
+		*(.rel*.efi_runtime.*)
+                __efi_runtime_rel_stop = .;
+	}
+
+	. = ALIGN(8);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	. = ALIGN(8);
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rela.dyn : {
+		*(.rela*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	_end = .;
+
+	. = ALIGN(8);
+
+	.bss_start : {
+		KEEP(*(.__bss_start));
+	}
+
+	.bss : {
+		*(.bss*)
+		 . = ALIGN(8);
+	}
+
+	.bss_end : {
+		KEEP(*(.__bss_end));
+	}
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/roms/u-boot/board/qualcomm/dragonboard820c/Kconfig b/roms/u-boot/board/qualcomm/dragonboard820c/Kconfig
new file mode 100644
index 000000000..aff9af527
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard820c/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_DRAGONBOARD820C
+
+config SYS_BOARD
+	default "dragonboard820c"
+
+config SYS_VENDOR
+	default "qualcomm"
+
+config SYS_SOC
+	default "apq8096"
+
+config SYS_CONFIG_NAME
+	default "dragonboard820c"
+
+endif
diff --git a/roms/u-boot/board/qualcomm/dragonboard820c/MAINTAINERS b/roms/u-boot/board/qualcomm/dragonboard820c/MAINTAINERS
new file mode 100644
index 000000000..7ef905bdf
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard820c/MAINTAINERS
@@ -0,0 +1,6 @@
+DRAGONBOARD820C BOARD
+M:	Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
+S:	Maintained
+F:	board/qualcomm/dragonboard820c/
+F:	include/configs/dragonboard820c.h
+F:	configs/dragonboard820c_defconfig
diff --git a/roms/u-boot/board/qualcomm/dragonboard820c/Makefile b/roms/u-boot/board/qualcomm/dragonboard820c/Makefile
new file mode 100644
index 000000000..643311f5b
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard820c/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@gmail.com>
+
+obj-y	:= dragonboard820c.o
+extra-y += head.o
diff --git a/roms/u-boot/board/qualcomm/dragonboard820c/dragonboard820c.c b/roms/u-boot/board/qualcomm/dragonboard820c/dragonboard820c.c
new file mode 100644
index 000000000..4ccb1a075
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard820c/dragonboard820c.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for Dragonboard 820C
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ */
+
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/arch/sysmap-apq8096.h>
+#include <env.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <linux/arm-smccc.h>
+#include <linux/psci.h>
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <asm/psci.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
+
+	return 0;
+}
+
+static void sdhci_power_init(void)
+{
+	const u32 TLMM_PULL_MASK = 0x3;
+	const u32 TLMM_HDRV_MASK = 0x7;
+
+	struct tlmm_cfg {
+		u32 bit;  /* bit in the register      */
+		u8 mask;  /* mask clk/dat/cmd control */
+		u8 val;
+	};
+
+	/* bit offsets in the sdc tlmm register */
+	enum {  SDC1_DATA_HDRV = 0,
+		SDC1_CMD_HDRV  = 3,
+		SDC1_CLK_HDRV  = 6,
+		SDC1_DATA_PULL = 9,
+		SDC1_CMD_PULL  = 11,
+		SDC1_CLK_PULL  = 13,
+		SDC1_RCLK_PULL = 15,
+	};
+
+	enum {  TLMM_PULL_DOWN	 = 0x1,
+		TLMM_PULL_UP   = 0x3,
+		TLMM_NO_PULL   = 0x0,
+	};
+
+	enum {  TLMM_CUR_VAL_10MA = 0x04,
+		TLMM_CUR_VAL_16MA = 0x07,
+	};
+	int i;
+
+	/* drive strength configs for sdhc pins */
+	const struct tlmm_cfg hdrv[] = {
+	
+		{ SDC1_CLK_HDRV,  TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, },
+		{ SDC1_CMD_HDRV,  TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, },
+		{ SDC1_DATA_HDRV, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, },
+	};
+
+	/* pull configs for sdhc pins */
+	const struct tlmm_cfg pull[] = {
+	
+		{ SDC1_CLK_PULL,  TLMM_NO_PULL, TLMM_PULL_MASK, },
+		{ SDC1_CMD_PULL,  TLMM_PULL_UP, TLMM_PULL_MASK, },
+		{ SDC1_DATA_PULL, TLMM_PULL_UP, TLMM_PULL_MASK, },
+	};
+
+	const struct tlmm_cfg rclk[] = {
+	
+		{ SDC1_RCLK_PULL, TLMM_PULL_DOWN, TLMM_PULL_MASK,},
+	};
+
+	for (i = 0; i < ARRAY_SIZE(hdrv); i++)
+		clrsetbits_le32(SDC1_HDRV_PULL_CTL_REG,
+				hdrv[i].mask << hdrv[i].bit,
+			hdrv[i].val  << hdrv[i].bit);
+
+	for (i = 0; i < ARRAY_SIZE(pull); i++)
+		clrsetbits_le32(SDC1_HDRV_PULL_CTL_REG,
+				pull[i].mask << pull[i].bit,
+			pull[i].val  << pull[i].bit);
+
+	for (i = 0; i < ARRAY_SIZE(rclk); i++)
+		clrsetbits_le32(SDC1_HDRV_PULL_CTL_REG,
+				rclk[i].mask << rclk[i].bit,
+			rclk[i].val  << rclk[i].bit);
+}
+
+static void show_psci_version(void)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+	printf("PSCI:  v%ld.%ld\n",
+	       PSCI_VERSION_MAJOR(res.a0),
+		PSCI_VERSION_MINOR(res.a0));
+}
+
+int board_init(void)
+{
+	sdhci_power_init();
+	show_psci_version();
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	psci_system_reset();
+}
+
+/* Check for vol- button - if pressed - stop autoboot */
+int misc_init_r(void)
+{
+	struct udevice *pon;
+	struct gpio_desc resin;
+	int node, ret;
+
+	ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8994_pon@800", &pon);
+	if (ret < 0) {
+		printf("Failed to find PMIC pon node. Check device tree\n");
+		return 0;
+	}
+
+	node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
+				  "key_vol_down");
+	if (node < 0) {
+		printf("Failed to find key_vol_down node. Check device tree\n");
+		return 0;
+	}
+
+	if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
+				       &resin, 0)) {
+		printf("Failed to request key_vol_down button.\n");
+		return 0;
+	}
+
+	if (dm_gpio_get_value(&resin)) {
+		env_set("bootdelay", "-1");
+		printf("Power button pressed - dropping to console.\n");
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/qualcomm/dragonboard820c/head.S b/roms/u-boot/board/qualcomm/dragonboard820c/head.S
new file mode 100644
index 000000000..29be61a90
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard820c/head.S
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ARM64 header for proper chain-loading with Little Kernel.
+ *
+ * Little Kernel shipped with Dragonboard820C boots standard Linux images for
+ * ARM64. This file adds header that is required to boot U-Boot properly.
+ *
+ * For details see:
+ * https://www.kernel.org/doc/Documentation/arm64/booting.txt
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ */
+
+#include <config.h>
+
+/*
+ *   per document in linux/Doc/arm64/booting.text
+ */
+.global _arm64_header
+_arm64_header:
+	b _start
+	.word 0
+	.quad   CONFIG_SYS_TEXT_BASE-PHYS_SDRAM_1 /* Image load offset, LE */
+	.quad   0    /* Effective size of kernel image, little-endian */
+	.quad   0    /* kernel flags, little-endian */
+	.quad   0    /* reserved */
+	.quad   0    /* reserved */
+	.quad   0    /* reserved */
+	.byte   0x41 /* Magic number, "ARM\x64" */
+	.byte   0x52
+	.byte   0x4d
+	.byte   0x64
+	.word   0    /* reserved (used for PE COFF offset) */
diff --git a/roms/u-boot/board/qualcomm/dragonboard820c/readme.txt b/roms/u-boot/board/qualcomm/dragonboard820c/readme.txt
new file mode 100644
index 000000000..966e9520e
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard820c/readme.txt
@@ -0,0 +1,457 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+
+================================================================================
+             What is working (enough to boot a distro from SD card)
+================================================================================
+   - UART
+   - SD card
+   - PSCI reset
+   - Environment in EXT4 partition 1 in SD card (check defconfig for details)
+         dont forget to insert the card in the SD slot before booting if you
+         are going to make mods to the environment
+
+================================================================================
+                     Build & Run instructions
+================================================================================
+
+1) Install mkbootimg and dtbTool from Codeaurora:
+
+   git://codeaurora.org/quic/kernel/skales
+   commit 8492547e404e969262d9070dee9bdd15668bb70f worked for me.
+
+2) Setup CROSS_COMPILE to aarch64 compiler or if you use ccache just do
+   CROSS_COMPILE="ccache aarch64-linux-gnu-"
+
+3) cd to the u-boot tree
+
+  $ make dragonboard820c_config
+  $ make -j `nproc`
+
+4) generate fake, empty ramdisk (can have 0 bytes)
+
+   $ touch rd
+
+5) Generate qualcomm device tree table with dtbTool
+
+   $ dtbTool -o dt.img arch/arm/dts
+
+6) Generate Android boot image with mkbootimg:
+
+   $ mkbootimg --kernel=u-boot-dtb.bin             \
+               --output=u-boot.img                 \
+               --dt=dt.img                         \
+               --pagesize 4096                     \
+               --base 0x80000000                   \
+               --ramdisk=rd                        \
+               --cmdline=""
+
+7) Reboot the board into fastboot mode
+   - plug the board micro-usb to your laptop usb host.
+   - reboot the board with vol- button pressed
+
+8) Boot the uboot image using fastboot
+
+   $ fastboot boot u-boot.img
+
+   or flash it to the UFS drive boot partition:
+
+   $ fastboot flash boot u-boot.img
+   $ fastboot reboot
+
+
+================================================================================
+      To boot a linux kernel from SDHCI with the ROOTFS on an NFS share:
+================================================================================
+
+1) create an EXT4 partition on the SD card (must be partition #1)
+
+2) build the kernel image and dtb  (documented extensively somewhere else)
+
+3) copy the drivers to the NFS partition (ie: 192.168.1.2 /exports/db820c-rootfs)
+
+4) add the u-boot headers to the image:
+
+    $ mkimage -A arm64                                     \
+              -O linux                                     \
+              -C none                                      \
+              -T kernel                                    \
+              -a 0x80080000                                \
+              -e 0x80080000                                \
+              -n Dragonboard820c                           \
+              -d $kernel/arch/arm64/boot/Image             \
+              uImage
+
+5) copy the generated uImage and the device tree binary to the SD card EXT4
+   partition
+
+    $ cp uImage /mnt/boot/
+    $ cp apq8096-db820c.dtb /mnt/boot/
+
+6) on the SD card create /extlinux/extlinux.conf  as follows:
+
+   default nfs
+   prompt 1
+   timeout 10
+
+   LABEL nfs
+      MENU NFS entry
+      LINUX /uImage
+      FDT /apq8096-db820c.dtb
+      APPEND root=/dev/nfs rw                                         \
+             nfsroot=192.168.1.2:/exports/db829c-rootfs,v3,tcp        \
+             rootwait                                                 \
+             ip=dhcp consoleblank=0                                   \
+             console=tty0                                             \
+             console=ttyMSM0,115200n8                                 \
+             earlyprintk earlycon=msm_serial_dm,0x75b0000             \
+             androidboot.bootdevice=624000.ufshc                      \
+             androidboot.verifiedbootstate=orange                     \
+             androidboot.ver0
+
+7) remove the SD card from the laptop and insert it back to the db820 board.
+   the SD card EXT4 partition#1 should contain:
+      /uImage
+      /apq8096-db820c.dtb
+      /extlinux/extlinux.conf
+
+8) reboot the db820 board
+
+================================================================================
+                    Successful boot sequence
+================================================================================
+
+Format: Log Type - Time(microsec) - Message - Optional Info
+Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
+S - QC_IMAGE_VERSION_STRING=BOOT.XF.1.0-00301
+S - IMAGE_VARIANT_STRING=M8996LAB
+S - OEM_IMAGE_VERSION_STRING=crm-ubuntu68
+S - Boot Interface: UFS
+S - Secure Boot: Off
+S - Boot Config @ 0x00076044 = 0x000001c9
+S - JTAG ID @ 0x000760f4 = 0x4003e0e1
+S - OEM ID @ 0x000760f8 = 0x00000000
+S - Serial Number @ 0x00074138 = 0x2e8844ce
+S - OEM Config Row 0 @ 0x00074188 = 0x0000000000000000
+S - OEM Config Row 1 @ 0x00074190 = 0x0000000000000000
+S - Feature Config Row 0 @ 0x000741a0 = 0x0050000010000100
+S - Feature Config Row 1 @ 0x000741a8 = 0x00fff00001ffffff
+S - Core 0 Frequency, 1228 MHz
+B -         0 - PBL, Start
+B -     10412 - bootable_media_detect_entry, Start
+B -     47480 - bootable_media_detect_success, Start
+B -     47481 - elf_loader_entry, Start
+B -     49027 - auth_hash_seg_entry, Start
+B -     49129 - auth_hash_seg_exit, Start
+B -     82403 - elf_segs_hash_verify_entry, Start
+B -     84905 - PBL, End
+B -     86955 - SBL1, Start
+B -    182969 - usb: hs_phy_nondrive_start
+B -    183305 - usb: PLL lock success - 0x3
+B -    186294 - usb: hs_phy_nondrive_finish
+B -    190442 - boot_flash_init, Start
+D -        30 - boot_flash_init, Delta
+B -    197548 - sbl1_ddr_set_default_params, Start
+D -        30 - sbl1_ddr_set_default_params, Delta
+B -    205509 - boot_config_data_table_init, Start
+D -    200659 - boot_config_data_table_init, Delta - (60 Bytes)
+B -    410713 - CDT Version:3,Platform ID:24,Major ID:1,Minor ID:0,Subtype:0
+B -    415410 - Image Load, Start
+D -     22570 - PMIC Image Loaded, Delta - (37272 Bytes)
+B -    437980 - pm_device_init, Start
+B -    443744 - PON REASON:PM0:0x200000061 PM1:0x200000021
+B -    480161 - PM_SET_VAL:Skip
+D -     40016 - pm_device_init, Delta
+B -    482083 - pm_driver_init, Start
+D -      2928 - pm_driver_init, Delta
+B -    488671 - pm_sbl_chg_init, Start
+D -        91 - pm_sbl_chg_init, Delta
+B -    495442 - vsense_init, Start
+D -         0 - vsense_init, Delta
+B -    505171 - Pre_DDR_clock_init, Start
+D -       396 - Pre_DDR_clock_init, Delta
+B -    509045 - ddr_initialize_device, Start
+B -    512766 - 8996 v3.x detected, Max frequency = 1.8 GHz
+B -    522373 - ddr_initialize_device, Delta
+B -    522404 - DDR ID, Rank 0, Rank 1, 0x6, 0x300, 0x300
+B -    526247 - Basic DDR tests done
+B -    594994 - clock_init, Start
+D -       274 - clock_init, Delta
+B -    598349 - Image Load, Start
+D -      4331 - QSEE Dev Config Image Loaded, Delta - (46008 Bytes)
+B -    603808 - Image Load, Start
+D -      5338 - APDP Image Loaded, Delta - (0 Bytes)
+B -    612409 - usb: UFS Serial - 2f490ecf
+B -    616801 - usb: fedl, vbus_low
+B -    620431 - Image Load, Start
+D -     55418 - QSEE Image Loaded, Delta - (1640572 Bytes)
+B -    675849 - Image Load, Start
+D -      2013 - SEC Image Loaded, Delta - (4096 Bytes)
+B -    683413 - sbl1_efs_handle_cookies, Start
+D -       457 - sbl1_efs_handle_cookies, Delta
+B -    691892 - Image Load, Start
+D -     14396 - QHEE Image Loaded, Delta - (254184 Bytes)
+B -    706319 - Image Load, Start
+D -     14061 - RPM Image Loaded, Delta - (223900 Bytes)
+B -    721111 - Image Load, Start
+D -      3233 - STI Image Loaded, Delta - (0 Bytes)
+B -    727913 - Image Load, Start
+D -     34709 - APPSBL Image Loaded, Delta - (748716 Bytes)
+B -    762713 - SBL1, End
+D -    680028 - SBL1, Delta
+S - Flash Throughput, 94000 KB/s  (2959024 Bytes,  31250 us)
+S - DDR Frequency, 1017 MHz
+Android Bootloader - UART_DM Initialized!!!
+
+[0] BUILD_VERSION=
+[0] BUILD_DATE=16:07:51 - Nov 17 2017
+[0] welcome to lk
+[10] platform_init()
+[10] target_init()
+[10] RPM GLink Init
+[10] Opening RPM Glink Port success
+[10] Opening SSR Glink Port success
+[20] Glink Connection between APPS and RPM established
+[20] Glink Connection between APPS and RPM established
+[40] UFS init success
+[80] Qseecom Init Done in Appsbl
+[80] secure app region addr=0x86600000 size=0x2200000[90] TZ App region notif returned with status:0 addr:86600000 size:35651584
+[100] TZ App log region register returned with status:0 addr:916d4000 size:4096
+[100] Qseecom TZ Init Done in Appsbl
+[120] Loading cmnlib done
+[120] qseecom_start_app: Loading app keymaster for the first time
+[150] <8>keymaster: "\"KEYMASTER Init \""
+[160] Selected panel: none
+Skip panel configuration
+[160] pm8x41_get_is_cold_boot: cold boot
+[170] boot_verifier: Device is in ORANGE boot state.
+[180] Device is unlocked! Skipping verification...
+[180] Loading (boot) image (348160): start
+[190] Loading (boot) image (348160): done
+[190] use_signed_kernel=1, is_unlocked=1, is_tampered=0.
+[200] Your device has been unlocked and cant be trusted.
+Wait for 5 seconds before proceeding
+
+[5200] mdtp: mdtp_img loaded
+[5210] mdtp: is_test_mode: test mode is set to 1
+[5210] mdtp: read_metadata: SUCCESS
+[5230] LK SEC APP Handle: 0x1
+[5230] Return value from recv_data: 14
+[5240] Return value from recv_data: 14
+[5250] Return value from recv_data: 14
+[5260] DTB Total entry: 1, DTB version: 3
+[5260] Using DTB entry 0x00000123/00000000/0x00000018/0 for device 0x00000123/00030001/0x00010018/0
+[5270] cmdline:  androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange androidboot.veritymode=enforcing androidboot.serialno=2f490ecf androidboot.baseband=apq mdss_mdp.panel=0
+[5290] Updating device tree: start
+[5290] Updating device tree: done
+[5290] Return value from recv_data: 14
+[5300] RPM GLINK UnInit
+[5300] Qseecom De-Init Done in Appsbl
+[5300] booting linux @ 0x80080000, ramdisk @ 0x82200000 (0), tags/device tree @ 0x82000000
+[5310] Jumping to kernel via monitor
+
+U-Boot 2017.11-00145-ge895117 (Nov 29 2017 - 10:04:06 +0100)
+Qualcomm-DragonBoard 820C
+
+DRAM:  3 GiB
+PSCI:  v1.0
+MMC:   sdhci@74a4900: 0
+In:    serial@75b0000
+Out:   serial@75b0000
+Err:   serial@75b0000
+Net:   Net Initialization Skipped
+No ethernet found.
+Hit any key to stop autoboot:  0
+switch to partitions #0, OK
+mmc0 is current device
+Scanning mmc 0:1...
+Found /extlinux/extlinux.conf
+Retrieving file: /extlinux/extlinux.conf
+433 bytes read in 71 ms (5.9 KiB/s)
+1:      nfs root
+
+Retrieving file: /uImage
+19397184 bytes read in 2024 ms (9.1 MiB/s)
+append: root=/dev/nfs rw nfsroot=192.168.1.2:/db820c/rootfs,v3,tcp rootwait ip=dhcp consoleblank=0 console=tty0 console=ttyMSM0,115200n8 earlyprintk earlycon=msm_serial_dm,0x75b0000 androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange androidboot.ver0
+
+Retrieving file: /apq8096-db820c.dtb
+38134 bytes read in 37 ms (1005.9 KiB/s)
+
+## Booting kernel from Legacy Image at 95000000 ...
+   Image Name:   Dragonboard820c
+   Image Type:   AArch64 Linux Kernel Image (uncompressed)
+   Data Size:    19397120 Bytes = 18.5 MiB
+   Load Address: 80080000
+   Entry Point:  80080000
+   Verifying Checksum ... OK
+## Flattened Device Tree blob at 93000000
+   Booting using the fdt blob at 0x93000000
+   Loading Kernel Image ... OK
+   Using Device Tree in place at 0000000093000000, end 000000009300c4f5
+
+Starting kernel ...
+
+[    0.000000] Booting Linux on physical CPU 0x0
+[    0.000000] Linux version 4.11.3-30039-g5a922a1 (jramirez@igloo) (gcc version 6.3.1 20170404 (Linaro GCC 6.3-2017.05) ) #1 SMP PREEMPT Wed Oct 18 10:21:11 CEST 2017
+[    0.000000] Boot CPU: AArch64 Processor [511f2112]
+[    0.000000] earlycon: msm_serial_dm0 at MMIO 0x00000000075b0000 (options '')
+[    0.000000] bootconsole [msm_serial_dm0] enabled
+[    0.000000] efi: Getting EFI parameters from FDT:
+[    0.000000] efi: UEFI not found.
+[    0.000000] OF: reserved mem: OVERLAP DETECTED!
+[    0.000000] adsp@8ea00000 (0x000000008ea00000--0x0000000090400000) overlaps with gpu@8f200000 (0x000000008f200000--0x000000008f300000)
+[    0.000000] Reserved memory: created DMA memory pool at 0x000000008f200000, size 1 MiB
+[    0.000000] OF: reserved mem: initialized node gpu@8f200000, compatible id shared-dma-pool
+[    0.000000] Reserved memory: created DMA memory pool at 0x0000000090400000, size 8 MiB
+[    0.000000] OF: reserved mem: initialized node venus@90400000, compatible id shared-dma-pool
+[    0.000000] cma: Reserved 128 MiB at 0x00000000b8000000
+[    0.000000] NUMA: No NUMA configuration found
+[    0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000bfffffff]
+[    0.000000] NUMA: Adding memblock [0x80000000 - 0x857fffff] on node 0
+[    0.000000] NUMA: Adding memblock [0x91800000 - 0xbfffffff] on node 0
+[    0.000000] NUMA: Initmem setup node 0 [mem 0x80000000-0xbfffffff]
+[    0.000000] NUMA: NODE_DATA [mem 0xb7fb6680-0xb7fb817f]
+[    0.000000] Zone ranges:
+[    0.000000]   DMA      [mem 0x0000000080000000-0x00000000bfffffff]
+[    0.000000]   Normal   empty
+[    0.000000] Movable zone start for each node
+[    0.000000] Early memory node ranges
+[    0.000000]   node   0: [mem 0x0000000080000000-0x00000000857fffff]
+[    0.000000]   node   0: [mem 0x0000000091800000-0x00000000bfffffff]
+[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000000bfffffff]
+[    0.000000] psci: probing for conduit method from DT.
+[    0.000000] psci: PSCIv1.0 detected in firmware.
+[    0.000000] psci: Using standard PSCI v0.2 function IDs
+[    0.000000] psci: MIGRATE_INFO_TYPE not supported.
+[    0.000000] percpu: Embedded 23 pages/cpu @ffff8000de9a3000 s57240 r8192 d28776 u94208
+[    0.000000] pcpu-alloc: s57240 r8192 d28776 u94208 alloc=23*4096
+[    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
+[    0.000000] Detected PIPT I-cache on CPU0
+[    0.000000] Built 1 zonelists in Node order, mobility grouping on.  Total pages: 720293
+[    0.000000] Policy zone: Normal
+[    0.000000] Kernel command line: root=/dev/nfs rw nfsroot=192.168.1.2:/db820c/rootfs,v3,tcp rootwait ip=dhcp consoleblank=0
+console=tty0 console=ttyMSM0,115200n8 earlyprintk earlycon=msm_serial_dm,0x75b0000 androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange a
+ndroidboot.ver0
+[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
+[    0.000000] software IO TLB [mem 0xd3fff000-0xd7fff000] (64MB) mapped at [ffff800053fff000-ffff800057ffefff]
+[    0.000000] Memory: 2644172K/2926908K available (11196K kernel code, 1470K rwdata, 5132K rodata, 1088K init, 449K bss, 151664K reserved, 131072K cma-reser
+ved)
+[    0.000000] Virtual kernel memory layout:
+[    0.000000]     modules : 0xffff000000000000 - 0xffff000008000000   (   128 MB)
+[    0.000000]     vmalloc : 0xffff000008000000 - 0xffff7dffbfff0000   (129022 GB)
+[    0.000000]       .text : 0xffff000008080000 - 0xffff000008b70000   ( 11200 KB)
+[    0.000000]     .rodata : 0xffff000008b70000 - 0xffff000009080000   (  5184 KB)
+[    0.000000]       .init : 0xffff000009080000 - 0xffff000009190000   (  1088 KB)
+[    0.000000]       .data : 0xffff000009190000 - 0xffff0000092ffa00   (  1471 KB)
+[    0.000000]        .bss : 0xffff0000092ffa00 - 0xffff00000937014c   (   450 KB)
+[    0.000000]     fixed   : 0xffff7dfffe7fd000 - 0xffff7dfffec00000   (  4108 KB)
+[    0.000000]     PCI I/O : 0xffff7dfffee00000 - 0xffff7dffffe00000   (    16 MB)
+[    0.000000]     vmemmap : 0xffff7e0000000000 - 0xffff800000000000   (  2048 GB maximum)
+[    0.000000]               0xffff7e0000000000 - 0xffff7e00037a93c0   (    55 MB actual)
+[    0.000000]     memory  : 0xffff800000000000 - 0xffff8000dea4f000   (  3562 MB)
+[    0.000000] SLUB: HWalign=128, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+[    0.000000] Preemptible hierarchical RCU implementation.
+[    0.000000]  Build-time adjustment of leaf fanout to 64.
+[    0.000000]  RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
+[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4
+[    0.000000] NR_IRQS:64 nr_irqs:64 0
+[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000009c00000
+[    0.000000] GICv2m: range[mem 0x09bd0000-0x09bd0fff], SPI[544:639]
+[    0.000000] arm_arch_timer: Architected cp15 and mmio timer(s) running at 19.20MHz (virt/virt).
+[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x46d987e47, max_idle_ns: 440795202767 ns
+[    0.000002] sched_clock: 56 bits at 19MHz, resolution 52ns, wraps every 4398046511078ns
+
+[....]
+
+
+Some kernel information:
+
+root@linaro-developer:~# cat /proc/cpuinfo
+processor       : 0
+BogoMIPS        : 38.40
+Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
+CPU implementer : 0x51
+CPU architecture: 8
+CPU variant     : 0x1
+CPU part        : 0x211
+CPU revision    : 2
+
+processor       : 1
+BogoMIPS        : 38.40
+Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
+CPU implementer : 0x51
+CPU architecture: 8
+CPU variant     : 0x1
+CPU part        : 0x211
+CPU revision    : 2
+
+processor       : 2
+BogoMIPS        : 38.40
+Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
+CPU implementer : 0x51
+CPU architecture: 8
+CPU variant     : 0x1
+CPU part        : 0x205
+CPU revision    : 2
+
+processor       : 3
+BogoMIPS        : 38.40
+Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
+CPU implementer : 0x51
+CPU architecture: 8
+CPU variant     : 0x1
+CPU part        : 0x205
+CPU revision    : 2
+
+root@linaro-developer:~# uname -a
+Linux linaro-developer 4.11.3-30039-g5a922a1 #1 SMP PREEMPT Wed Oct 18 10:21:11 CEST 2017 aarch64 GNU/Linux
+
+root@linaro-developer:~# cat /proc/cmdline
+root=/dev/nfs rw nfsroot=192.168.1.2:/db820c/rootfs,v3,tcp rootwait ip=dhcp consoleblank=0 console=tty0 console=ttyMSM0,115200n8 earlyprintk earlycon=msm_serial_dm,0x75b0000 androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange androidboot.ver0
+
+root@linaro-developer:~# cat /proc/meminfo
+MemTotal:        2776332 kB
+MemFree:         2593696 kB
+MemAvailable:    2561432 kB
+Buffers:               0 kB
+Cached:            94744 kB
+SwapCached:            0 kB
+Active:            43888 kB
+Inactive:          72972 kB
+Active(anon):      22968 kB
+Inactive(anon):    24616 kB
+Active(file):      20920 kB
+Inactive(file):    48356 kB
+Unevictable:           0 kB
+Mlocked:               0 kB
+SwapTotal:             0 kB
+SwapFree:              0 kB
+Dirty:                 0 kB
+Writeback:             0 kB
+AnonPages:         22120 kB
+Mapped:            29284 kB
+Shmem:             25468 kB
+Slab:              32876 kB
+SReclaimable:      12924 kB
+SUnreclaim:        19952 kB
+KernelStack:        2144 kB
+PageTables:          928 kB
+NFS_Unstable:          0 kB
+Bounce:                0 kB
+WritebackTmp:          0 kB
+CommitLimit:     1388164 kB
+Committed_AS:     204192 kB
+VmallocTotal:   135290290112 kB
+VmallocUsed:           0 kB
+VmallocChunk:          0 kB
+AnonHugePages:      2048 kB
+ShmemHugePages:        0 kB
+ShmemPmdMapped:        0 kB
+CmaTotal:         131072 kB
+CmaFree:          130356 kB
+HugePages_Total:       0
+HugePages_Free:        0
+HugePages_Rsvd:        0
+HugePages_Surp:        0
+Hugepagesize:       2048 kB
diff --git a/roms/u-boot/board/qualcomm/dragonboard820c/u-boot.lds b/roms/u-boot/board/qualcomm/dragonboard820c/u-boot.lds
new file mode 100644
index 000000000..dcf8256ce
--- /dev/null
+++ b/roms/u-boot/board/qualcomm/dragonboard820c/u-boot.lds
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Override linker script for fastboot-readable images
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_arm64_header)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(8);
+	.text :
+	{
+		*(.__image_copy_start)
+		board/qualcomm/dragonboard820c/head.o (.text*)
+		CPUDIR/start.o (.text*)
+	}
+
+	/* This needs to come before *(.text*) */
+	.efi_runtime : {
+                __efi_runtime_start = .;
+		*(.text.efi_runtime*)
+		*(.rodata.efi_runtime*)
+		*(.data.efi_runtime*)
+                __efi_runtime_stop = .;
+	}
+
+	.text_rest :
+	{
+		*(.text*)
+	}
+
+	. = ALIGN(8);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(8);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(8);
+
+	. = .;
+
+	. = ALIGN(8);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(8);
+
+	.efi_runtime_rel : {
+                __efi_runtime_rel_start = .;
+		*(.rel*.efi_runtime)
+		*(.rel*.efi_runtime.*)
+                __efi_runtime_rel_stop = .;
+	}
+
+	. = ALIGN(8);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	. = ALIGN(8);
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rela.dyn : {
+		*(.rela*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	_end = .;
+
+	. = ALIGN(8);
+
+	.bss_start : {
+		KEEP(*(.__bss_start));
+	}
+
+	.bss : {
+		*(.bss*)
+		 . = ALIGN(8);
+	}
+
+	.bss_end : {
+		KEEP(*(.__bss_end));
+	}
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/roms/u-boot/board/radxa/rock/Kconfig b/roms/u-boot/board/radxa/rock/Kconfig
new file mode 100644
index 000000000..855b9b695
--- /dev/null
+++ b/roms/u-boot/board/radxa/rock/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROCK
+
+config SYS_BOARD
+	default "rock"
+
+config SYS_VENDOR
+	default "radxa"
+
+config SYS_CONFIG_NAME
+	default "rock"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/radxa/rock/MAINTAINERS b/roms/u-boot/board/radxa/rock/MAINTAINERS
new file mode 100644
index 000000000..c5f59c0a6
--- /dev/null
+++ b/roms/u-boot/board/radxa/rock/MAINTAINERS
@@ -0,0 +1,6 @@
+RADXA_ROCK
+M:	Heiko Stuebner <heiko@sntech.de>
+S:	Maintained
+F:	board/radxa/rock
+F:	include/configs/rock.h
+F:	configs/rock_defconfig
diff --git a/roms/u-boot/board/radxa/rock/Makefile b/roms/u-boot/board/radxa/rock/Makefile
new file mode 100644
index 000000000..fe94b60c3
--- /dev/null
+++ b/roms/u-boot/board/radxa/rock/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Heiko Stuebner
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= rock.o
diff --git a/roms/u-boot/board/radxa/rock/rock.c b/roms/u-boot/board/radxa/rock/rock.c
new file mode 100644
index 000000000..bdc02a6a7
--- /dev/null
+++ b/roms/u-boot/board/radxa/rock/rock.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/radxa/rock2/Kconfig b/roms/u-boot/board/radxa/rock2/Kconfig
new file mode 100644
index 000000000..c2ff9e996
--- /dev/null
+++ b/roms/u-boot/board/radxa/rock2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROCK2
+
+config SYS_BOARD
+	default "rock2"
+
+config SYS_VENDOR
+	default "radxa"
+
+config SYS_CONFIG_NAME
+	default "rock2"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/radxa/rock2/MAINTAINERS b/roms/u-boot/board/radxa/rock2/MAINTAINERS
new file mode 100644
index 000000000..a697e6828
--- /dev/null
+++ b/roms/u-boot/board/radxa/rock2/MAINTAINERS
@@ -0,0 +1,6 @@
+FIREFLY
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/radxa/rock2
+F:	include/configs/rock2.h
+F:	configs/rock2_defconfig
diff --git a/roms/u-boot/board/radxa/rock2/Makefile b/roms/u-boot/board/radxa/rock2/Makefile
new file mode 100644
index 000000000..caa305bbb
--- /dev/null
+++ b/roms/u-boot/board/radxa/rock2/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= rock2.o
diff --git a/roms/u-boot/board/radxa/rock2/rock2.c b/roms/u-boot/board/radxa/rock2/rock2.c
new file mode 100644
index 000000000..bdc02a6a7
--- /dev/null
+++ b/roms/u-boot/board/radxa/rock2/rock2.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/raidsonic/ib62x0/Kconfig b/roms/u-boot/board/raidsonic/ib62x0/Kconfig
new file mode 100644
index 000000000..129aac8b6
--- /dev/null
+++ b/roms/u-boot/board/raidsonic/ib62x0/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IB62X0
+
+config SYS_BOARD
+	default "ib62x0"
+
+config SYS_VENDOR
+	default "raidsonic"
+
+config SYS_CONFIG_NAME
+	default "ib62x0"
+
+endif
diff --git a/roms/u-boot/board/raidsonic/ib62x0/MAINTAINERS b/roms/u-boot/board/raidsonic/ib62x0/MAINTAINERS
new file mode 100644
index 000000000..423aa0cf2
--- /dev/null
+++ b/roms/u-boot/board/raidsonic/ib62x0/MAINTAINERS
@@ -0,0 +1,6 @@
+IB62X0 BOARD
+M:	Luka Perkov <luka@openwrt.org>
+S:	Maintained
+F:	board/raidsonic/ib62x0/
+F:	include/configs/ib62x0.h
+F:	configs/ib62x0_defconfig
diff --git a/roms/u-boot/board/raidsonic/ib62x0/Makefile b/roms/u-boot/board/raidsonic/ib62x0/Makefile
new file mode 100644
index 000000000..3e6bc688e
--- /dev/null
+++ b/roms/u-boot/board/raidsonic/ib62x0/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= ib62x0.o
diff --git a/roms/u-boot/board/raidsonic/ib62x0/ib62x0.c b/roms/u-boot/board/raidsonic/ib62x0/ib62x0.c
new file mode 100644
index 000000000..f9bc07649
--- /dev/null
+++ b/roms/u-boot/board/raidsonic/ib62x0/ib62x0.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011-2012
+ * Gerald Kerma <dreagle@doukki.net>
+ * Luka Perkov <luka@openwrt.org>
+ * Simon Baatz <gmbnomis@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "ib62x0.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(IB62x0_OE_VAL_LOW,
+			  IB62x0_OE_VAL_HIGH,
+			  IB62x0_OE_LOW, IB62x0_OE_HIGH);
+
+	/* Set SATA activity LEDs to default off */
+	writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_SATA1_ACTn,
+		MPP21_SATA0_ACTn,
+		MPP22_GPIO,     /* Power LED red */
+		MPP24_GPIO,     /* Power off device */
+		MPP25_GPIO,     /* Power LED green */
+		MPP27_GPIO,     /* USB transfer LED */
+		MPP28_GPIO,     /* Reset button */
+		MPP29_GPIO,     /* USB Copy button */
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/raidsonic/ib62x0/ib62x0.h b/roms/u-boot/board/raidsonic/ib62x0/ib62x0.h
new file mode 100644
index 000000000..3690e1353
--- /dev/null
+++ b/roms/u-boot/board/raidsonic/ib62x0/ib62x0.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011-2012
+ * Gerald Kerma <dreagle@doukki.net>
+ * Simon Baatz <gmbnomis@gmail.com>
+ * Luka Perkov <luka@openwrt.org>
+ */
+
+#ifndef __IB62x0_H
+#define __IB62x0_H
+
+#define IB62x0_OE_LOW		(~(1 << 22 | 1 << 24 | 1 << 25 | 1 << 27))
+#define IB62x0_OE_HIGH		(~(0))
+#define IB62x0_OE_VAL_LOW	0
+#define IB62x0_OE_VAL_HIGH	0
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+/* SATAHC related */
+#define MVSATAHC_LED_CONF_REG       (MV_SATA_BASE + 0x2C)
+#define MVSATAHC_LED_POLARITY_CTRL  (1 << 3)
+
+#endif /* __IB62x0_H */
diff --git a/roms/u-boot/board/raidsonic/ib62x0/kwbimage.cfg b/roms/u-boot/board/raidsonic/ib62x0/kwbimage.cfg
new file mode 100644
index 000000000..1249a0e4b
--- /dev/null
+++ b/roms/u-boot/board/raidsonic/ib62x0/kwbimage.cfg
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011-2012
+# Gerald Kerma <dreagle@doukki.net>
+# Simon Baatz <gmbnomis@gmail.com>
+# Luka Perkov <luka@openwrt.org>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xffd100e0 0x1b1b1b9b
+
+# Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xffd01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30, (3120 DDR2 clks refresh rate)
+# bit23-14: 0x0,
+# bit24:    0x1,   enable exit self refresh mode on DDR access
+# bit25:    0x1,   required
+# bit29-26: 0x0,
+# bit31-30: 0x1,
+
+DATA 0xffd01404 0x37543000	# DDR Controller Control Low
+# bit4:     0x0, addr/cmd in smame cycle
+# bit5:     0x0, clk is driven during self refresh, we don't care for APX
+# bit6:     0x0, use recommended falling edge of clk for addr/cmd
+# bit14:    0x0, input buffer always powered up
+# bit18:    0x1, cpu lock transaction enabled
+# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 0x3, required
+# bit31:    0x0, no additional STARTBURST delay
+
+DATA 0xffd01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11-8:  TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000a33	# DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: 0x0, required
+
+DATA 0xffd01410 0x0000000c	# DDR Address Control
+# bit1-0:   00,  Cs0width (x8)
+# bit3-2:   11,  Cs0size (1Gb)
+# bit5-4:   00,  Cs1width (x8)
+# bit7-6:   11,  Cs1size (1Gb)
+# bit9-8:   00,  Cs2width (nonexistent)
+# bit11-10: 00,  Cs2size (nonexistent)
+# bit13-12: 00,  Cs3width (nonexistent)
+# bit15-14: 00,  Cs3size (nonexistent)
+# bit16:    0,   Cs0AddrSel
+# bit17:    0,   Cs1AddrSel
+# bit18:    0,   Cs2AddrSel
+# bit19:    0,   Cs3AddrSel
+# bit31-20: 0x0, required
+
+DATA 0xffd01414 0x00000000	# DDR Open Pages Control
+# bit0:    0,   OpenPage enabled
+# bit31-1: 0x0, required
+
+DATA 0xffd01418 0x00000000	# DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0x0, required
+
+DATA 0xffd0141c 0x00000c52	# DDR Mode
+# bit2-0:   0x2, BurstLen=2 required
+# bit3:     0x0, BurstType=0 required
+# bit6-4:   0x4, CL=5
+# bit7:     0x0, TestMode=0 normal
+# bit8:     0x0, DLL reset=0 normal
+# bit11-9:  0x6, auto-precharge write recovery
+# bit12:    0x0, PD must be zero
+# bit31-13: 0x0, required
+
+DATA 0xffd01420 0x00000040	# DDR Extended Mode
+# bit0:     0,   DDR DLL enabled
+# bit1:     0,   DDR drive strenght normal
+# bit2:     1,   DDR ODT control lsd (disabled)
+# bit5-3:   0x0, required
+# bit6:     0,   DDR ODT control msb, (disabled)
+# bit9-7:   0x0, required
+# bit10:    0,   differential DQS enabled
+# bit11:    0,   required
+# bit12:    0,   DDR output buffer enabled
+# bit31-13: 0x0, required
+
+DATA 0xffd01424 0x0000f17f	# DDR Controller Control High
+# bit2-0:   0x7, required
+# bit3:     0x1, MBUS Burst Chop disabled
+# bit6-4:   0x7, required
+# bit7:     0x0,
+# bit8:     0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9:     0x0, no half clock cycle addition to dataout
+# bit10:    0x0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11:    0x0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf, required
+# bit31-16: 0,   required
+
+DATA 0xffd01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xffd01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xffd01504 0x0ffffff1	# CS[0]n Size
+# bit0:     0x1,     Window enabled
+# bit1:     0x0,     Write Protect disabled
+# bit3-2:   0x0,     CS0 hit selected
+# bit23-4:  0xfffff, required
+# bit31-24: 0x0f,    Size (i.e. 256MB)
+
+DATA 0xffd01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xffd0150c 0x00000000	# CS[1]n Size, window disabled
+
+DATA 0xffd01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xffd0151c 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000	# DDR ODT Control (Low)
+# bit3-0:     ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4:     ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000	# DDR ODT Control (High)
+# bit1-0:  0x0, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  0x1, ODT1 active NEVER!
+# bit31-4: 0x0, required
+
+DATA 0xffd0149c 0x0000e803	# CPU ODT Control
+DATA 0xffd01480 0x00000001	# DDR Initialization Control
+# bit0: 0x1, enable DDR init upon this register write
+
+DATA 0xffd20134 0x66666666	# L2 RAM Timing 0 Register
+DATA 0xffd20138 0x66666666	# L2 RAM Timing 1 Register
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/raspberrypi/rpi/Kconfig b/roms/u-boot/board/raspberrypi/rpi/Kconfig
new file mode 100644
index 000000000..e40088fde
--- /dev/null
+++ b/roms/u-boot/board/raspberrypi/rpi/Kconfig
@@ -0,0 +1,10 @@
+if SYS_BOARD = "rpi"
+
+config RPI_EFI_NR_SPIN_PAGES
+	int "Spin table page count"
+	default 1
+	help
+	  Number of pages to reserve starting at page 0 for spin tables in the EFI
+	  memory map
+
+endif
diff --git a/roms/u-boot/board/raspberrypi/rpi/MAINTAINERS b/roms/u-boot/board/raspberrypi/rpi/MAINTAINERS
new file mode 100644
index 000000000..4f1b23efc
--- /dev/null
+++ b/roms/u-boot/board/raspberrypi/rpi/MAINTAINERS
@@ -0,0 +1,6 @@
+RPI BOARD
+M:	Matthias Brugger <mbrugger@suse.com>
+S:	Maintained
+F:	board/raspberrypi/rpi/
+F:	include/configs/rpi.h
+F:	configs/rpi_*defconfig
diff --git a/roms/u-boot/board/raspberrypi/rpi/Makefile b/roms/u-boot/board/raspberrypi/rpi/Makefile
new file mode 100644
index 000000000..b1186cdf1
--- /dev/null
+++ b/roms/u-boot/board/raspberrypi/rpi/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# (C) Copyright 2012 Stephen Warren
+
+obj-y	:= rpi.o
+obj-y	+= lowlevel_init.o
diff --git a/roms/u-boot/board/raspberrypi/rpi/lowlevel_init.S b/roms/u-boot/board/raspberrypi/rpi/lowlevel_init.S
new file mode 100644
index 000000000..8c39b3e12
--- /dev/null
+++ b/roms/u-boot/board/raspberrypi/rpi/lowlevel_init.S
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016
+ * Cédric Schieli <cschieli@gmail.com>
+ */
+
+#include <config.h>
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: save ATAG/FDT address provided by the firmware at boot time
+ */
+
+.global save_boot_params
+save_boot_params:
+
+	/* The firmware provided ATAG/FDT address can be found in r2/x0 */
+#ifdef CONFIG_ARM64
+	adr	x8, fw_dtb_pointer
+	str	x0, [x8]
+#else
+	ldr	r8, =fw_dtb_pointer
+	str	r2, [r8]
+#endif
+
+	/* Returns */
+	b	save_boot_params_ret
diff --git a/roms/u-boot/board/raspberrypi/rpi/rpi.c b/roms/u-boot/board/raspberrypi/rpi/rpi.c
new file mode 100644
index 000000000..df52a4689
--- /dev/null
+++ b/roms/u-boot/board/raspberrypi/rpi/rpi.c
@@ -0,0 +1,514 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2012-2016 Stephen Warren
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <env.h>
+#include <efi_loader.h>
+#include <fdt_support.h>
+#include <fdt_simplefb.h>
+#include <init.h>
+#include <lcd.h>
+#include <memalign.h>
+#include <mmc.h>
+#include <asm/gpio.h>
+#include <asm/arch/mbox.h>
+#include <asm/arch/msg.h>
+#include <asm/arch/sdhci.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_bcm283x_mu.h>
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+#endif
+#include <watchdog.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Assigned in lowlevel_init.S
+ * Push the variable into the .data section so that it
+ * does not get cleared later.
+ */
+unsigned long __section(".data") fw_dtb_pointer;
+
+/* TODO(sjg@chromium.org): Move these to the msg.c file */
+struct msg_get_arm_mem {
+	struct bcm2835_mbox_hdr hdr;
+	struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
+	u32 end_tag;
+};
+
+struct msg_get_board_rev {
+	struct bcm2835_mbox_hdr hdr;
+	struct bcm2835_mbox_tag_get_board_rev get_board_rev;
+	u32 end_tag;
+};
+
+struct msg_get_board_serial {
+	struct bcm2835_mbox_hdr hdr;
+	struct bcm2835_mbox_tag_get_board_serial get_board_serial;
+	u32 end_tag;
+};
+
+struct msg_get_mac_address {
+	struct bcm2835_mbox_hdr hdr;
+	struct bcm2835_mbox_tag_get_mac_address get_mac_address;
+	u32 end_tag;
+};
+
+struct msg_get_clock_rate {
+	struct bcm2835_mbox_hdr hdr;
+	struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
+	u32 end_tag;
+};
+
+#ifdef CONFIG_ARM64
+#define DTB_DIR "broadcom/"
+#else
+#define DTB_DIR ""
+#endif
+
+/*
+ * https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
+ */
+struct rpi_model {
+	const char *name;
+	const char *fdtfile;
+	bool has_onboard_eth;
+};
+
+static const struct rpi_model rpi_model_unknown = {
+	"Unknown model",
+	DTB_DIR "bcm283x-rpi-other.dtb",
+	false,
+};
+
+static const struct rpi_model rpi_models_new_scheme[] = {
+	[0x0] = {
+		"Model A",
+		DTB_DIR "bcm2835-rpi-a.dtb",
+		false,
+	},
+	[0x1] = {
+		"Model B",
+		DTB_DIR "bcm2835-rpi-b.dtb",
+		true,
+	},
+	[0x2] = {
+		"Model A+",
+		DTB_DIR "bcm2835-rpi-a-plus.dtb",
+		false,
+	},
+	[0x3] = {
+		"Model B+",
+		DTB_DIR "bcm2835-rpi-b-plus.dtb",
+		true,
+	},
+	[0x4] = {
+		"2 Model B",
+		DTB_DIR "bcm2836-rpi-2-b.dtb",
+		true,
+	},
+	[0x6] = {
+		"Compute Module",
+		DTB_DIR "bcm2835-rpi-cm.dtb",
+		false,
+	},
+	[0x8] = {
+		"3 Model B",
+		DTB_DIR "bcm2837-rpi-3-b.dtb",
+		true,
+	},
+	[0x9] = {
+		"Zero",
+		DTB_DIR "bcm2835-rpi-zero.dtb",
+		false,
+	},
+	[0xA] = {
+		"Compute Module 3",
+		DTB_DIR "bcm2837-rpi-cm3.dtb",
+		false,
+	},
+	[0xC] = {
+		"Zero W",
+		DTB_DIR "bcm2835-rpi-zero-w.dtb",
+		false,
+	},
+	[0xD] = {
+		"3 Model B+",
+		DTB_DIR "bcm2837-rpi-3-b-plus.dtb",
+		true,
+	},
+	[0xE] = {
+		"3 Model A+",
+		DTB_DIR "bcm2837-rpi-3-a-plus.dtb",
+		false,
+	},
+	[0x10] = {
+		"Compute Module 3+",
+		DTB_DIR "bcm2837-rpi-cm3.dtb",
+		false,
+	},
+	[0x11] = {
+		"4 Model B",
+		DTB_DIR "bcm2711-rpi-4-b.dtb",
+		true,
+	},
+	[0x13] = {
+		"400",
+		DTB_DIR "bcm2711-rpi-400.dtb",
+		true,
+	},
+	[0x14] = {
+		"Compute Module 4",
+		DTB_DIR "bcm2711-rpi-cm4.dtb",
+		true,
+	},
+};
+
+static const struct rpi_model rpi_models_old_scheme[] = {
+	[0x2] = {
+		"Model B",
+		DTB_DIR "bcm2835-rpi-b.dtb",
+		true,
+	},
+	[0x3] = {
+		"Model B",
+		DTB_DIR "bcm2835-rpi-b.dtb",
+		true,
+	},
+	[0x4] = {
+		"Model B rev2",
+		DTB_DIR "bcm2835-rpi-b-rev2.dtb",
+		true,
+	},
+	[0x5] = {
+		"Model B rev2",
+		DTB_DIR "bcm2835-rpi-b-rev2.dtb",
+		true,
+	},
+	[0x6] = {
+		"Model B rev2",
+		DTB_DIR "bcm2835-rpi-b-rev2.dtb",
+		true,
+	},
+	[0x7] = {
+		"Model A",
+		DTB_DIR "bcm2835-rpi-a.dtb",
+		false,
+	},
+	[0x8] = {
+		"Model A",
+		DTB_DIR "bcm2835-rpi-a.dtb",
+		false,
+	},
+	[0x9] = {
+		"Model A",
+		DTB_DIR "bcm2835-rpi-a.dtb",
+		false,
+	},
+	[0xd] = {
+		"Model B rev2",
+		DTB_DIR "bcm2835-rpi-b-rev2.dtb",
+		true,
+	},
+	[0xe] = {
+		"Model B rev2",
+		DTB_DIR "bcm2835-rpi-b-rev2.dtb",
+		true,
+	},
+	[0xf] = {
+		"Model B rev2",
+		DTB_DIR "bcm2835-rpi-b-rev2.dtb",
+		true,
+	},
+	[0x10] = {
+		"Model B+",
+		DTB_DIR "bcm2835-rpi-b-plus.dtb",
+		true,
+	},
+	[0x11] = {
+		"Compute Module",
+		DTB_DIR "bcm2835-rpi-cm.dtb",
+		false,
+	},
+	[0x12] = {
+		"Model A+",
+		DTB_DIR "bcm2835-rpi-a-plus.dtb",
+		false,
+	},
+	[0x13] = {
+		"Model B+",
+		DTB_DIR "bcm2835-rpi-b-plus.dtb",
+		true,
+	},
+	[0x14] = {
+		"Compute Module",
+		DTB_DIR "bcm2835-rpi-cm.dtb",
+		false,
+	},
+	[0x15] = {
+		"Model A+",
+		DTB_DIR "bcm2835-rpi-a-plus.dtb",
+		false,
+	},
+};
+
+static uint32_t revision;
+static uint32_t rev_scheme;
+static uint32_t rev_type;
+static const struct rpi_model *model;
+
+int dram_init(void)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1);
+	int ret;
+
+	BCM2835_MBOX_INIT_HDR(msg);
+	BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY);
+
+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+	if (ret) {
+		printf("bcm2835: Could not query ARM memory size\n");
+		return -1;
+	}
+
+	gd->ram_size = msg->get_arm_mem.body.resp.mem_size;
+
+	/*
+	 * In some configurations the memory size returned by VideoCore
+	 * is not aligned to the section size, what is mandatory for
+	 * the u-boot's memory setup.
+	 */
+	gd->ram_size &= ~MMU_SECTION_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD
+int dram_init_banksize(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_memory_banksize();
+	if (ret)
+		return ret;
+
+	return fdtdec_setup_mem_size_base();
+}
+#endif
+
+static void set_fdtfile(void)
+{
+	const char *fdtfile;
+
+	if (env_get("fdtfile"))
+		return;
+
+	fdtfile = model->fdtfile;
+	env_set("fdtfile", fdtfile);
+}
+
+/*
+ * If the firmware provided a valid FDT at boot time, let's expose it in
+ * ${fdt_addr} so it may be passed unmodified to the kernel.
+ */
+static void set_fdt_addr(void)
+{
+	if (env_get("fdt_addr"))
+		return;
+
+	if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
+		return;
+
+	env_set_hex("fdt_addr", fw_dtb_pointer);
+}
+
+/*
+ * Prevent relocation from stomping on a firmware provided FDT blob.
+ */
+unsigned long board_get_usable_ram_top(unsigned long total_size)
+{
+	if ((gd->ram_top - fw_dtb_pointer) > SZ_64M)
+		return gd->ram_top;
+	return fw_dtb_pointer & ~0xffff;
+}
+
+static void set_usbethaddr(void)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1);
+	int ret;
+
+	if (!model->has_onboard_eth)
+		return;
+
+	if (env_get("usbethaddr"))
+		return;
+
+	BCM2835_MBOX_INIT_HDR(msg);
+	BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
+
+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+	if (ret) {
+		printf("bcm2835: Could not query MAC address\n");
+		/* Ignore error; not critical */
+		return;
+	}
+
+	eth_env_set_enetaddr("usbethaddr", msg->get_mac_address.body.resp.mac);
+
+	if (!env_get("ethaddr"))
+		env_set("ethaddr", env_get("usbethaddr"));
+
+	return;
+}
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+static void set_board_info(void)
+{
+	char s[11];
+
+	snprintf(s, sizeof(s), "0x%X", revision);
+	env_set("board_revision", s);
+	snprintf(s, sizeof(s), "%d", rev_scheme);
+	env_set("board_rev_scheme", s);
+	/* Can't rename this to board_rev_type since it's an ABI for scripts */
+	snprintf(s, sizeof(s), "0x%X", rev_type);
+	env_set("board_rev", s);
+	env_set("board_name", model->name);
+}
+#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
+
+static void set_serial_number(void)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_serial, msg, 1);
+	int ret;
+	char serial_string[17] = { 0 };
+
+	if (env_get("serial#"))
+		return;
+
+	BCM2835_MBOX_INIT_HDR(msg);
+	BCM2835_MBOX_INIT_TAG_NO_REQ(&msg->get_board_serial, GET_BOARD_SERIAL);
+
+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+	if (ret) {
+		printf("bcm2835: Could not query board serial\n");
+		/* Ignore error; not critical */
+		return;
+	}
+
+	snprintf(serial_string, sizeof(serial_string), "%016llx",
+		 msg->get_board_serial.body.resp.serial);
+	env_set("serial#", serial_string);
+}
+
+int misc_init_r(void)
+{
+	set_fdt_addr();
+	set_fdtfile();
+	set_usbethaddr();
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+	set_serial_number();
+
+	return 0;
+}
+
+static void get_board_rev(void)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1);
+	int ret;
+	const struct rpi_model *models;
+	uint32_t models_count;
+
+	BCM2835_MBOX_INIT_HDR(msg);
+	BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV);
+
+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+	if (ret) {
+		printf("bcm2835: Could not query board revision\n");
+		/* Ignore error; not critical */
+		return;
+	}
+
+	/*
+	 * For details of old-vs-new scheme, see:
+	 * https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py
+	 * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=99293&p=690282
+	 * (a few posts down)
+	 *
+	 * For the RPi 1, bit 24 is the "warranty bit", so we mask off just the
+	 * lower byte to use as the board rev:
+	 * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250
+	 * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594
+	 */
+	revision = msg->get_board_rev.body.resp.rev;
+	if (revision & 0x800000) {
+		rev_scheme = 1;
+		rev_type = (revision >> 4) & 0xff;
+		models = rpi_models_new_scheme;
+		models_count = ARRAY_SIZE(rpi_models_new_scheme);
+	} else {
+		rev_scheme = 0;
+		rev_type = revision & 0xff;
+		models = rpi_models_old_scheme;
+		models_count = ARRAY_SIZE(rpi_models_old_scheme);
+	}
+	if (rev_type >= models_count) {
+		printf("RPI: Board rev 0x%x outside known range\n", rev_type);
+		model = &rpi_model_unknown;
+	} else if (!models[rev_type].name) {
+		printf("RPI: Board rev 0x%x unknown\n", rev_type);
+		model = &rpi_model_unknown;
+	} else {
+		model = &models[rev_type];
+	}
+
+	printf("RPI %s (0x%x)\n", model->name, revision);
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+	hw_watchdog_init();
+#endif
+
+	get_board_rev();
+
+	gd->bd->bi_boot_params = 0x100;
+
+	return bcm2835_power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
+}
+
+/*
+ * If the firmware passed a device tree use it for U-Boot.
+ */
+void *board_fdt_blob_setup(void)
+{
+	if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
+		return NULL;
+	return (void *)fw_dtb_pointer;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	/*
+	 * For now, we simply always add the simplefb DT node. Later, we
+	 * should be more intelligent, and e.g. only do this if no enabled DT
+	 * node exists for the "real" graphics driver.
+	 */
+	lcd_dt_simplefb_add_node(blob);
+
+#ifdef CONFIG_EFI_LOADER
+	/* Reserve the spin table */
+	efi_add_memory_map(0, CONFIG_RPI_EFI_NR_SPIN_PAGES << EFI_PAGE_SHIFT,
+			   EFI_RESERVED_MEMORY_TYPE);
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/renesas/alt/Kconfig b/roms/u-boot/board/renesas/alt/Kconfig
new file mode 100644
index 000000000..957962de2
--- /dev/null
+++ b/roms/u-boot/board/renesas/alt/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ALT
+
+config SYS_BOARD
+	default "alt"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "alt"
+
+endif
diff --git a/roms/u-boot/board/renesas/alt/MAINTAINERS b/roms/u-boot/board/renesas/alt/MAINTAINERS
new file mode 100644
index 000000000..6ec140b22
--- /dev/null
+++ b/roms/u-boot/board/renesas/alt/MAINTAINERS
@@ -0,0 +1,6 @@
+ALT BOARD
+M:	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+S:	Maintained
+F:	board/renesas/alt/
+F:	include/configs/alt.h
+F:	configs/alt_defconfig
diff --git a/roms/u-boot/board/renesas/alt/Makefile b/roms/u-boot/board/renesas/alt/Makefile
new file mode 100644
index 000000000..53418699b
--- /dev/null
+++ b/roms/u-boot/board/renesas/alt/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/alt/Makefile
+#
+# Copyright (C) 2014 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= alt_spl.o
+else
+obj-y	:= alt.o qos.o
+endif
diff --git a/roms/u-boot/board/renesas/alt/alt.c b/roms/u-boot/board/renesas/alt/alt.c
new file mode 100644
index 000000000..3b60afc59
--- /dev/null
+++ b/roms/u-boot/board/renesas/alt/alt.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/alt/alt.c
+ *
+ * Copyright (C) 2014, 2015 Renesas Electronics Corporation
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <hang.h>
+#include <init.h>
+#include <malloc.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <env_internal.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <div64.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS */
+	qos_init();
+}
+
+#define TMU0_MSTP125	BIT(25)
+#define MMC0_MSTP315	BIT(15)
+
+#define SD1CKCR		0xE6150078
+#define SD_97500KHZ	0x7
+
+int board_early_init_f(void)
+{
+	/* TMU */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+	/* Set SD1 to the 97.5MHz */
+	writel(SD_97500KHZ, SD1CKCR);
+
+	return 0;
+}
+
+#define ETHERNET_PHY_RESET	56	/* GPIO 1 24 */
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Force ethernet PHY out of reset */
+	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+	gpio_direction_output(ETHERNET_PHY_RESET, 0);
+	mdelay(20);
+	gpio_direction_output(ETHERNET_PHY_RESET, 1);
+	udelay(1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+/* KSZ8041RNLI */
+#define PHY_CONTROL1		0x1E
+#define PHY_LED_MODE		0xC000
+#define PHY_LED_MODE_ACK	0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+	ret &= ~PHY_LED_MODE;
+	ret |= PHY_LED_MODE_ACK;
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	struct udevice *dev;
+	const u8 pmic_bus = 7;
+	const u8 pmic_addr = 0x58;
+	u8 data;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+	if (ret)
+		hang();
+
+	ret = dm_i2c_read(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+
+	data |= BIT(1);
+
+	ret = dm_i2c_write(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	const u32 load_magic = 0xb33fc0de;
+
+	/* Block environment access if loaded using JTAG */
+	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+	    (op != ENVOP_INIT))
+		return ENVL_UNKNOWN;
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	return ENVL_SPI_FLASH;
+}
diff --git a/roms/u-boot/board/renesas/alt/alt_spl.c b/roms/u-boot/board/renesas/alt/alt_spl.c
new file mode 100644
index 000000000..cdaa04e4f
--- /dev/null
+++ b/roms/u-boot/board/renesas/alt/alt_spl.c
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/alt/alt_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125	BIT(25)
+#define SCIF2_MSTP719	BIT(19)
+#define QSPI_MSTP917	BIT(17)
+
+#define SD1CKCR		0xE6150078
+#define SD_97500KHZ	0x7
+
+struct reg_config {
+	u16	off;
+	u32	val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+		;
+}
+
+static void spl_init_sys(void)
+{
+	u32 r0 = 0;
+
+	writel(0xa5a5a500, 0xe6020004);
+	writel(0xa5a5a500, 0xe6030004);
+
+	asm volatile(
+		/* ICIALLU - Invalidate I$ to PoU */
+		"mcr	15, 0, %0, cr7, cr5, 0	\n"
+		/* BPIALL - Invalidate branch predictors */
+		"mcr	15, 0, %0, cr7, cr5, 6	\n"
+		/* Set SCTLR[IZ] */
+		"mrc	15, 0, %0, cr1, cr0, 0	\n"
+		"orr	%0, #0x1800		\n"
+		"mcr	15, 0, %0, cr1, cr0, 0	\n"
+		"isb	sy			\n"
+		:"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+	static const struct reg_config pfc_with_unlock[] = {
+		{ 0x0090, 0x00000000 },
+		{ 0x0094, 0x00000000 },
+		{ 0x0098, 0x00000000 },
+		{ 0x0020, 0x00000000 },
+		{ 0x0024, 0x00000000 },
+		{ 0x0028, 0x40000000 },
+		{ 0x002c, 0x00000155 },
+		{ 0x0030, 0x00000002 },
+		{ 0x0034, 0x00000000 },
+		{ 0x0038, 0x00000000 },
+		{ 0x003c, 0x00000000 },
+		{ 0x0040, 0x60000000 },
+		{ 0x0044, 0x36dab6db },
+		{ 0x0048, 0x926da012 },
+		{ 0x004c, 0x0008c383 },
+		{ 0x0050, 0x00000000 },
+		{ 0x0054, 0x00000140 },
+		{ 0x0004, 0xffffffff },
+		{ 0x0008, 0x00ec3fff },
+		{ 0x000c, 0x5bffffff },
+		{ 0x0010, 0x01bfe1ff },
+		{ 0x0014, 0x5bffffff },
+		{ 0x0018, 0x0f4b200f },
+		{ 0x001c, 0x03ffffff },
+	};
+
+	static const struct reg_config pfc_without_unlock[] = {
+		{ 0x0100, 0x00000000 },
+		{ 0x0104, 0x4203fc00 },
+		{ 0x0108, 0x00000000 },
+		{ 0x010c, 0x159007ff },
+		{ 0x0110, 0x80000000 },
+		{ 0x0114, 0x00de481f },
+		{ 0x0118, 0x00000000 },
+	};
+
+	static const struct reg_config pfc_with_unlock2[] = {
+		{ 0x0060, 0xffffffff },
+		{ 0x0064, 0xfffff000 },
+		{ 0x0068, 0x55555500 },
+		{ 0x006c, 0xffffff00 },
+		{ 0x0070, 0x00000000 },
+	};
+
+	static const u32 pfc_base = 0xe6060000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+		writel(~pfc_with_unlock[i].val, pfc_base);
+		writel(pfc_with_unlock[i].val,
+		       pfc_base | pfc_with_unlock[i].off);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+		writel(pfc_without_unlock[i].val,
+		       pfc_base | pfc_without_unlock[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
+		writel(~pfc_with_unlock2[i].val, pfc_base);
+		writel(pfc_with_unlock2[i].val,
+		       pfc_base | pfc_with_unlock2[i].off);
+	}
+}
+
+static void spl_init_gpio(void)
+{
+	static const u16 gpio_offs[] = {
+		0x1000, 0x2000, 0x3000, 0x4000, 0x5000
+	};
+
+	static const struct reg_config gpio_set[] = {
+		{ 0x2000, 0x24000000 },
+		{ 0x4000, 0xa4000000 },
+		{ 0x5000, 0x0004c000 },
+	};
+
+	static const struct reg_config gpio_clr[] = {
+		{ 0x1000, 0x01000000 },
+		{ 0x2000, 0x24000000 },
+		{ 0x3000, 0x00000000 },
+		{ 0x4000, 0xa4000000 },
+		{ 0x5000, 0x0084c380 },
+	};
+
+	static const u32 gpio_base = 0xe6050000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+	static const struct reg_config lbsc_config[] = {
+		{ 0x00, 0x00000020 },
+		{ 0x08, 0x00002020 },
+		{ 0x30, 0x2a103320 },
+		{ 0x38, 0xff70ff70 },
+	};
+
+	static const u16 lbsc_offs[] = {
+		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
+	};
+
+	static const u32 lbsc_base = 0xfec00200;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+		writel(lbsc_config[i].val,
+		       lbsc_base | lbsc_config[i].off);
+		writel(lbsc_config[i].val,
+		       lbsc_base | (lbsc_config[i].off + 4));
+	}
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+		writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+	static const struct reg_config dbsc_config1[] = {
+		{ 0x0018, 0x21000000 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0018, 0x10000000 },
+		{ 0x0280, 0x0000a55a },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x80000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config2[] = {
+		{ 0x0290, 0x00000006 },
+		{ 0x02a0, 0x0005c000 },
+	};
+
+	static const struct reg_config dbsc_config4[] = {
+		{ 0x0290, 0x00000010 },
+		{ 0x02a0, 0xf00464db },
+		{ 0x0290, 0x00000061 },
+		{ 0x02a0, 0x0000006d },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000073 },
+		{ 0x0020, 0x00000007 },
+		{ 0x0024, 0x0f030a02 },
+		{ 0x0030, 0x00000001 },
+		{ 0x00b0, 0x00000000 },
+		{ 0x0040, 0x00000009 },
+		{ 0x0044, 0x00000007 },
+		{ 0x0048, 0x00000000 },
+		{ 0x0050, 0x00000009 },
+		{ 0x0054, 0x000a0009 },
+		{ 0x0058, 0x00000021 },
+		{ 0x005c, 0x00000018 },
+		{ 0x0060, 0x00000005 },
+		{ 0x0064, 0x0000001b },
+		{ 0x0068, 0x00000007 },
+		{ 0x006c, 0x0000000a },
+		{ 0x0070, 0x00000009 },
+		{ 0x0074, 0x00000010 },
+		{ 0x0078, 0x000000ae },
+		{ 0x007c, 0x00140005 },
+		{ 0x0080, 0x00050004 },
+		{ 0x0084, 0x50213005 },
+		{ 0x0088, 0x000c0000 },
+		{ 0x008c, 0x00000200 },
+		{ 0x0090, 0x00000040 },
+		{ 0x0100, 0x00000001 },
+		{ 0x00c0, 0x00020001 },
+		{ 0x00c8, 0x20082008 },
+		{ 0x0380, 0x00020003 },
+		{ 0x0390, 0x0000001f },
+	};
+
+	static const struct reg_config dbsc_config5[] = {
+		{ 0x0244, 0x00000011 },
+		{ 0x0290, 0x00000003 },
+		{ 0x02a0, 0x0300c4e1 },
+		{ 0x0290, 0x00000023 },
+		{ 0x02a0, 0x00fcb6d0 },
+		{ 0x0290, 0x00000011 },
+		{ 0x02a0, 0x1000040b },
+		{ 0x0290, 0x00000012 },
+		{ 0x02a0, 0x85589955 },
+		{ 0x0290, 0x00000013 },
+		{ 0x02a0, 0x1a852400 },
+		{ 0x0290, 0x00000014 },
+		{ 0x02a0, 0x300210b4 },
+		{ 0x0290, 0x00000015 },
+		{ 0x02a0, 0x00000b50 },
+		{ 0x0290, 0x00000016 },
+		{ 0x02a0, 0x00000006 },
+		{ 0x0290, 0x00000017 },
+		{ 0x02a0, 0x00000010 },
+		{ 0x0290, 0x0000001a },
+		{ 0x02a0, 0x910035c7 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config6[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000181 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config7[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x0000fe01 },
+		{ 0x0304, 0x00000000 },
+		{ 0x00f4, 0x01004c20 },
+		{ 0x00f8, 0x014000aa },
+		{ 0x00e0, 0x00000140 },
+		{ 0x00e4, 0x00081450 },
+		{ 0x00e8, 0x00010000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config8[] = {
+		{ 0x0014, 0x00000001 },
+		{ 0x0010, 0x00000001 },
+		{ 0x0280, 0x00000000 },
+	};
+
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
+		writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+		writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+	dbsc_wait(0x240);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void spl_init_qspi(void)
+{
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	static const u32 qspi_base = 0xe6b10000;
+
+	writeb(0x08, qspi_base + 0x00);
+	writeb(0x00, qspi_base + 0x01);
+	writeb(0x06, qspi_base + 0x02);
+	writeb(0x01, qspi_base + 0x0a);
+	writeb(0x00, qspi_base + 0x0b);
+	writeb(0x00, qspi_base + 0x0c);
+	writeb(0x00, qspi_base + 0x0d);
+	writeb(0x00, qspi_base + 0x0e);
+
+	writew(0xe080, qspi_base + 0x10);
+
+	writeb(0xc0, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x08);
+	writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
+
+	/* Set SD1 to the 97.5MHz */
+	writel(SD_97500KHZ, SD1CKCR);
+
+	spl_init_sys();
+	spl_init_pfc();
+	spl_init_gpio();
+	spl_init_lbsc();
+	spl_init_dbsc();
+	spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	const u32 jtag_magic = 0x1337c0de;
+	const u32 load_magic = 0xb33fc0de;
+
+	/*
+	 * If JTAG probe sets special word at 0xe6300020, then it must
+	 * put U-Boot into RAM and SPL will start it from RAM.
+	 */
+	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+		printf("JTAG boot detected!\n");
+
+		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+			;
+
+		spl_boot_list[0] = BOOT_DEVICE_RAM;
+		spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+		return;
+	}
+
+	/* Boot from SPI NOR with YMODEM UART fallback. */
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+	spl_boot_list[1] = BOOT_DEVICE_UART;
+	spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/roms/u-boot/board/renesas/alt/qos.c b/roms/u-boot/board/renesas/alt/qos.c
new file mode 100644
index 000000000..2f657505c
--- /dev/null
+++ b/roms/u-boot/board/renesas/alt/qos.c
@@ -0,0 +1,999 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/alt/qos.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
+/* QoS version 0.311 for ES1 and version 0.321 for ES2 */
+
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+#if defined(CONFIG_QOS_PRI_MEDIA)
+#define is_qos_pri_media()	1
+#else
+#define is_qos_pri_media()	0
+#endif
+
+#if defined(CONFIG_QOS_PRI_NORMAL)
+#define is_qos_pri_normal()	1
+#else
+#define is_qos_pri_normal()	0
+#endif
+
+#if defined(CONFIG_QOS_PRI_GFX)
+#define is_qos_pri_gfx()	1
+#else
+#define is_qos_pri_gfx()	0
+#endif
+
+void qos_init(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	if (is_qos_pri_media()) {
+		writel(0x1F0B0604, &s3c->s3crorr);
+		writel(0x1F0E0705, &s3c->s3cworr);
+	} else if (is_qos_pri_normal()) {
+		writel(0x1F0B0908, &s3c->s3crorr);
+		writel(0x1F0E0A08, &s3c->s3cworr);
+	} else if (is_qos_pri_media()) {
+		writel(0x1F0B0B0B, &s3c->s3crorr);
+		writel(0x1F0E0C0C, &s3c->s3cworr);
+	}
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_media())
+		writel(0x20AA2100, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_media())
+		writel(0x20AA2200, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_media())
+		writel(0x20AA2100, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x80928092, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00820092, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20FA, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20FA, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x0000207D, &qos_addr->dbtmval0);
+		writel(0x00002053, &qos_addr->dbtmval1);
+		writel(0x0000202A, &qos_addr->dbtmval2);
+		writel(0x00001FBD, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002064, &qos_addr->dbthres0);
+		writel(0x0000203E, &qos_addr->dbthres1);
+		writel(0x00002019, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x0000207D, &qos_addr->dbtmval0);
+		writel(0x00002053, &qos_addr->dbtmval1);
+		writel(0x00002043, &qos_addr->dbtmval2);
+		writel(0x00002030, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002064, &qos_addr->dbthres0);
+		writel(0x0000203E, &qos_addr->dbthres1);
+		writel(0x00002031, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* CCI-400 -QoS */
+	if (IS_R8A7794_ES2()) {
+		writel(0x20001000, CCI_400_MAXOT_1);
+		writel(0x20001000, CCI_400_MAXOT_2);
+	} else {
+		writel(0x20000800, CCI_400_MAXOT_1);
+		writel(0x20000800, CCI_400_MAXOT_2);
+	}
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000016, &mxi->mxwtcr);
+	writel(0x00780080, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000E, &mxi_qos->du0);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000206E, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+}
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/roms/u-boot/board/renesas/alt/qos.h b/roms/u-boot/board/renesas/alt/qos.h
new file mode 100644
index 000000000..d92c43704
--- /dev/null
+++ b/roms/u-boot/board/renesas/alt/qos.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/roms/u-boot/board/renesas/blanche/Kconfig b/roms/u-boot/board/renesas/blanche/Kconfig
new file mode 100644
index 000000000..ac4730a62
--- /dev/null
+++ b/roms/u-boot/board/renesas/blanche/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BLANCHE
+
+config SYS_BOARD
+	default "blanche"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "blanche"
+
+endif
diff --git a/roms/u-boot/board/renesas/blanche/MAINTAINERS b/roms/u-boot/board/renesas/blanche/MAINTAINERS
new file mode 100644
index 000000000..4b3114ace
--- /dev/null
+++ b/roms/u-boot/board/renesas/blanche/MAINTAINERS
@@ -0,0 +1,7 @@
+BLANCHE BOARD
+M:	Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com>
+S:	Maintained
+F:	board/renesas/blanche/
+F:	include/configs/blanche.h
+F:	configs/blanche_defconfig
+
diff --git a/roms/u-boot/board/renesas/blanche/Makefile b/roms/u-boot/board/renesas/blanche/Makefile
new file mode 100644
index 000000000..21986af47
--- /dev/null
+++ b/roms/u-boot/board/renesas/blanche/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/blanche/Makefile
+#
+# Copyright (C) 2016 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= blanche.o qos.o
diff --git a/roms/u-boot/board/renesas/blanche/blanche.c b/roms/u-boot/board/renesas/blanche/blanche.c
new file mode 100644
index 000000000..a36526986
--- /dev/null
+++ b/roms/u-boot/board/renesas/blanche/blanche.c
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/blanche/blanche.c
+ *     This file is blanche board support.
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/sh_sdhi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/processor.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <env.h>
+#include <hang.h>
+#include <i2c.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define	CPG_PLL1CR	0xE6150028
+#define	CPG_PLL3CR	0xE61500DC
+
+#define TMU0_MSTP125	BIT(25)
+#define QSPI_MSTP917	BIT(17)
+
+struct reg_config {
+	u16	off;
+	u32	val;
+};
+
+static void blanche_init_sys(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+	u32 cpu_type;
+
+	cpu_type = rmobile_get_cpu_type();
+	if (cpu_type == 0x4A) {
+		writel(0x4D000000, CPG_PLL1CR);
+		writel(0x4F000000, CPG_PLL3CR);
+	}
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+}
+
+static void blanche_init_pfc(void)
+{
+	static const struct reg_config pfc_with_unlock[] = {
+		{ 0x0004, 0x0bffffff },
+		{ 0x0008, 0x002fffff },
+		{ 0x0014, 0x00000fff },
+		{ 0x0018, 0x00010fff },
+		{ 0x001c, 0x00010fff },
+		{ 0x0020, 0x00010fff },
+		{ 0x0024, 0x00010fff },
+		{ 0x0028, 0x00010fff },
+		{ 0x002c, 0x04006000 },
+		{ 0x0030, 0x303fefe0 },
+		{ 0x0058, 0x0002000e },
+	};
+
+	static const struct reg_config pfc_without_unlock[] = {
+		{ 0x0108, 0x00000000 },
+		{ 0x010c, 0x0803FF40 },
+		{ 0x0110, 0x0000FFFF },
+		{ 0x0114, 0x00010FFF },
+		{ 0x011c, 0x0001AFFF },
+		{ 0x0124, 0x0001CFFF },
+		{ 0x0128, 0xC0438001 },
+		{ 0x012c, 0x0FC00007 },
+	};
+
+	static const u32 pfc_base = 0xe6060000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+		writel(~pfc_with_unlock[i].val, pfc_base);
+		writel(pfc_with_unlock[i].val,
+		       pfc_base | pfc_with_unlock[i].off);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+		writel(pfc_without_unlock[i].val,
+		       pfc_base | pfc_without_unlock[i].off);
+}
+
+static void blanche_init_lbsc(void)
+{
+	static const struct reg_config lbsc_config[] = {
+		{ 0x00, 0x00000020 },
+		{ 0x08, 0x00002020 },
+		{ 0x30, 0x2a103320 },
+		{ 0x38, 0x19102110 },
+	};
+
+	static const u32 lbsc_base = 0xfec00200;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+		writel(lbsc_config[i].val,
+		       lbsc_base | lbsc_config[i].off);
+		writel(lbsc_config[i].val,
+		       lbsc_base | (lbsc_config[i].off + 4));
+	}
+}
+
+#if defined(CONFIG_MTD_NOR_FLASH)
+static void dbsc_wait(u16 reg)
+{
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+		;
+}
+
+static void blanche_init_dbsc(void)
+{
+	static const struct reg_config dbsc_config1[] = {
+		{ 0x0280, 0x0000a55a },
+		{ 0x0018, 0x21000000 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0018, 0x10000000 },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x80000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config2[] = {
+		{ 0x0290, 0x00000006 },
+		{ 0x02a0, 0x0001c000 },
+	};
+
+	static const struct reg_config dbsc_config4[] = {
+		{ 0x0290, 0x0000000f },
+		{ 0x02a0, 0x00181ee4 },
+		{ 0x0290, 0x00000010 },
+		{ 0x02a0, 0xf00464db },
+		{ 0x0290, 0x00000061 },
+		{ 0x02a0, 0x0000008d },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000073 },
+		{ 0x0020, 0x00000007 },
+		{ 0x0024, 0x0f030a02 },
+		{ 0x0030, 0x00000001 },
+		{ 0x00b0, 0x00000000 },
+		{ 0x0040, 0x0000000b },
+		{ 0x0044, 0x00000008 },
+		{ 0x0048, 0x00000000 },
+		{ 0x0050, 0x0000000b },
+		{ 0x0054, 0x000c000b },
+		{ 0x0058, 0x00000027 },
+		{ 0x005c, 0x0000001c },
+		{ 0x0060, 0x00000006 },
+		{ 0x0064, 0x00000020 },
+		{ 0x0068, 0x00000008 },
+		{ 0x006c, 0x0000000c },
+		{ 0x0070, 0x00000009 },
+		{ 0x0074, 0x00000012 },
+		{ 0x0078, 0x000000d0 },
+		{ 0x007c, 0x00140005 },
+		{ 0x0080, 0x00050004 },
+		{ 0x0084, 0x70233005 },
+		{ 0x0088, 0x000c0000 },
+		{ 0x008c, 0x00000300 },
+		{ 0x0090, 0x00000040 },
+		{ 0x0100, 0x00000001 },
+		{ 0x00c0, 0x00020001 },
+		{ 0x00c8, 0x20082004 },
+		{ 0x0380, 0x00020002 },
+		{ 0x0390, 0x0000001f },
+	};
+
+	static const struct reg_config dbsc_config5[] = {
+		{ 0x0244, 0x00000011 },
+		{ 0x0290, 0x00000003 },
+		{ 0x02a0, 0x0300c4e1 },
+		{ 0x0290, 0x00000023 },
+		{ 0x02a0, 0x00fcdb60 },
+		{ 0x0290, 0x00000011 },
+		{ 0x02a0, 0x1000040b },
+		{ 0x0290, 0x00000012 },
+		{ 0x02a0, 0x9d9cbb66 },
+		{ 0x0290, 0x00000013 },
+		{ 0x02a0, 0x1a868400 },
+		{ 0x0290, 0x00000014 },
+		{ 0x02a0, 0x300214d8 },
+		{ 0x0290, 0x00000015 },
+		{ 0x02a0, 0x00000d70 },
+		{ 0x0290, 0x00000016 },
+		{ 0x02a0, 0x00000004 },
+		{ 0x0290, 0x00000017 },
+		{ 0x02a0, 0x00000018 },
+		{ 0x0290, 0x0000001a },
+		{ 0x02a0, 0x910035c7 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config6[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000181 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config7[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x0000fe01 },
+		{ 0x0304, 0x00000000 },
+		{ 0x00f4, 0x01004c20 },
+		{ 0x00f8, 0x014000aa },
+		{ 0x00e0, 0x00000140 },
+		{ 0x00e4, 0x00081860 },
+		{ 0x00e8, 0x00010000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config8[] = {
+		{ 0x0014, 0x00000001 },
+		{ 0x0010, 0x00000001 },
+		{ 0x0280, 0x00000000 },
+	};
+
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
+		writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+		writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+	dbsc_wait(0x240);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void s_init_wait(volatile unsigned int cnt)
+{
+	volatile u32 i = cnt * 0x10000;
+
+	while (i-- > 0)
+		;
+}
+#endif
+
+void s_init(void)
+{
+	blanche_init_sys();
+	qos_init();
+	blanche_init_pfc();
+	blanche_init_lbsc();
+#if defined(CONFIG_MTD_NOR_FLASH)
+	s_init_wait(10);
+	blanche_init_dbsc();
+#endif /* CONFIG_MTD_NOR_FLASH */
+}
+
+int board_early_init_f(void)
+{
+	/* TMU0 */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	/* QSPI */
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+/* Added for BLANCHE(R-CarV2H board) */
+#ifndef CONFIG_DM_ETH
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_SMC911X
+	struct eth_device *dev;
+	uchar eth_addr[6];
+
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+
+	if (!eth_env_get_enetaddr("ethaddr", eth_addr)) {
+		dev = eth_get_dev_by_index(0);
+		if (dev) {
+			eth_env_set_enetaddr("ethaddr", dev->enetaddr);
+		} else {
+			printf("blanche: Couldn't get eth device\n");
+			rc = -1;
+		}
+	}
+
+#endif
+
+	return rc;
+}
+#endif
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	struct udevice *dev;
+	const u8 pmic_bus = 6;
+	const u8 pmic_addr = 0x58;
+	u8 data;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+	if (ret)
+		hang();
+
+	ret = dm_i2c_read(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+
+	data |= BIT(1);
+
+	ret = dm_i2c_write(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+}
diff --git a/roms/u-boot/board/renesas/blanche/qos.c b/roms/u-boot/board/renesas/blanche/qos.c
new file mode 100644
index 000000000..e3ad83ee0
--- /dev/null
+++ b/roms/u-boot/board/renesas/blanche/qos.c
@@ -0,0 +1,1365 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/blanche/qos.c
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20082004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	// writel(0x00000000, &s3c->s3cadsplcr);
+	writel(0x1F0D0C0C, &s3c->s3crorr);
+	writel(0x1F1F0C0C, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x80918099, &s3c_qos->s3cqos0);
+	writel(0x20410010, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x0000204B, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x00001FC4, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x0000206E, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x0000205A, &qos_addr->dbthres0);
+		writel(0x0000205A, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000100, &mxi->mxaxirtcr);
+	writel(0xFF530100, &mxi->mxaxiwtcr);
+	writel(0x00000100, &mxi->mxs3crtcr);
+	writel(0xFF530100, &mxi->mxs3cwtcr);
+	writel(0x004000C0, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->du0);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADM_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADS_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AXI64TO128W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVBW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCIW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCSW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2DW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBSW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTXBW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRABW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADMW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADSW_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYXW_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_IMP0_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000211B, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SY2_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256W_AXI128TO256_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXMW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXIW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_IMP0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SY2W_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RT_BASE;
+	writel(0x00002001, &axi_qos->qosctset1);
+	writel(0x00002001, &axi_qos->qosctset2);
+	writel(0x00002001, &axi_qos->qosctset3);
+	writel(0x00000000, &axi_qos->qosthres0);
+	writel(0x00000000, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHXW_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBGW_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTW_BASE;
+	writel(0x00002001, &axi_qos->qosctset1);
+	writel(0x00002001, &axi_qos->qosctset2);
+	writel(0x00002001, &axi_qos->qosctset3);
+	writel(0x00000000, &axi_qos->qosthres0);
+	writel(0x00000000, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000000A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002018, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002259, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCTU0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCTU0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU1R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU1W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002046, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN1W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002046, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_RDRW_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x000020D0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS01R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x0000000C, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS01W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x000000C0, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS23R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x0000000C, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS23W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x000000C0, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS45R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x0000000C, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS45W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x000000C0, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002069, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002069, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE4R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE4W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC4R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC4W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x000020D3, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x000020D3, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000201A, &axi_qos->qosctset0);
+	writel(0x00000018, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002006, &axi_qos->qosctset0);
+	writel(0x00000018, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000201A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002042, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE1R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE1W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC1R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC1W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE2R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE2W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC2R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC2W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE3R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE3W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC3R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC3W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* DMS Register(SYS-AXI) */
+	writel(0x00000000, SYS_AXI_AVBDMSCR);
+	writel(0x00000000, SYS_AXI_AX2MDMSCR);
+	writel(0x00000000, SYS_AXI_CC50DMSCR);
+	writel(0x00000000, SYS_AXI_CCIDMSCR);
+	writel(0x00000000, SYS_AXI_CSDMSCR);
+	writel(0x00000000, SYS_AXI_G2DDMSCR);
+	writel(0x00000000, SYS_AXI_IMP1DMSCR);
+	writel(0x00000000, SYS_AXI_LBSMDMSCR);
+	writel(0x00000000, SYS_AXI_MMUDSDMSCR);
+	writel(0x00000000, SYS_AXI_MMUMXDMSCR);
+	writel(0x00000000, SYS_AXI_MMUS0DMSCR);
+	writel(0x00000000, SYS_AXI_MMUS1DMSCR);
+	writel(0x00000000, SYS_AXI_RTMXDMSCR);
+	writel(0x00000000, SYS_AXI_SDM0DMSCR);
+	writel(0x00000000, SYS_AXI_SDM1DMSCR);
+	writel(0x00000000, SYS_AXI_SDS0DMSCR);
+	writel(0x00000000, SYS_AXI_SDS1DMSCR);
+	writel(0x00000000, SYS_AXI_TRABDMSCR);
+	writel(0x00000000, SYS_AXI_X128TO64SLVDMSCR);
+	writel(0x00000000, SYS_AXI_X64TO128SLVDMSCR);
+	writel(0x00000000, SYS_AXI_AVBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_AX2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_GICSLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMPSLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMPSLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMX0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMX1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMX2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_LBSSLVDMSCR);
+	writel(0x00000000, SYS_AXI_MXTSLVDMSCR);
+	writel(0x00000000, SYS_AXI_SYAPBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_QSAPBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_RTXSLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC3SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC65SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC8SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SDAP0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SGXSLV1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STMSLVDMSCR);
+	writel(0x00000000, SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR);
+	writel(0x00000000, SYS_AXI_TSPL0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_TSPL1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_TSPL2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_UTLBDSSLVDMSCR);
+	writel(0x00000000, SYS_AXI_UTLBS0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_UTLBS1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_ROT0DMSCR);
+	writel(0x00000000, SYS_AXI_ROT1DMSCR);
+	writel(0x00000000, SYS_AXI_ROT2DMSCR);
+	writel(0x00000000, SYS_AXI_ROT3DMSCR);
+	writel(0x00000000, SYS_AXI_ROT4DMSCR);
+	writel(0x00000000, SYS_AXI_IMUX3SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR0PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR0XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR1PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR1XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR2PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR2XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR3SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR3PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR3XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR4SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR4PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR4XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_ADM_DMSCR);
+	writel(0x00000000, SYS_AXI_ADS_DMSCR);
+
+	/* DMS Register(RT-AXI) */
+	writel(0x00000000, DM_AXI_DMAXICONF);
+	writel(0x00000019, DM_AXI_DMAPBCONF);
+	writel(0x00000000, DM_AXI_DMADMCONF);
+	writel(0x00000000, DM_AXI_DMSDM0CONF);
+	writel(0x00000000, DM_AXI_DMSDM1CONF);
+	writel(0x00000004, DM_AXI_DMQSPAPSLVCONF);
+	writel(0x00000004, DM_AXI_RAPD4SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD4SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD5SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD6SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD65DSLVCONF);
+	writel(0x00000004, DM_AXI_SDAP0SLVCONF);
+	writel(0x00000004, DM_AXI_MAPD2SLVCONF);
+	writel(0x00000004, DM_AXI_MAPD3SLVCONF);
+	writel(0x00000000, DM_AXI_DMXXDEFAULTSLAVESLVCONF);
+	writel(0x00000100, DM_AXI_DMADMRQOSCONF);
+	writel(0x0000214C, DM_AXI_DMADMRQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMADMRQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMADMRQOSQON);
+	writel(0x00000005, DM_AXI_DMADMRQOSIN);
+	writel(0x00000000, DM_AXI_DMADMRQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM0RQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM0RQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM0RQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM0RQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM0RQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM0RQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM1RQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM1RQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM1RQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM1RQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM1RQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM1RQOSSTAT);
+	writel(0x00002041, DM_AXI_DMRQOSCTSET1);
+	writel(0x00002023, DM_AXI_DMRQOSCTSET2);
+	writel(0x0000200A, DM_AXI_DMRQOSCTSET3);
+	writel(0x00002050, DM_AXI_DMRQOSTHRES0);
+	writel(0x00002032, DM_AXI_DMRQOSTHRES1);
+	writel(0x00002014, DM_AXI_DMRQOSTHRES2);
+	writel(0x00000100, DM_AXI_DMADMWQOSCONF);
+	writel(0x0000214C, DM_AXI_DMADMWQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMADMWQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMADMWQOSQON);
+	writel(0x00000005, DM_AXI_DMADMWQOSIN);
+	writel(0x00000000, DM_AXI_DMADMWQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM0WQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM0WQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM0WQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM0WQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM0WQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM0WQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM1WQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM1WQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM1WQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM1WQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM1WQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM1WQOSSTAT);
+	writel(0x00002041, DM_AXI_DMWQOSCTSET1);
+	writel(0x00002023, DM_AXI_DMWQOSCTSET2);
+	writel(0x0000200A, DM_AXI_DMWQOSCTSET3);
+	writel(0x00002050, DM_AXI_DMWQOSTHRES0);
+	writel(0x00002032, DM_AXI_DMWQOSTHRES1);
+	writel(0x00002014, DM_AXI_DMWQOSTHRES2);
+	writel(0x00000000, DM_AXI_RDMDMSCR);
+	writel(0x00000000, DM_AXI_SDM0DMSCR);
+	writel(0x00000000, DM_AXI_SDM1DMSCR);
+	writel(0x00000000, DM_AXI_DMQSPAPSLVDMSCR);
+	writel(0x00000000, DM_AXI_RAPD4SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD4SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD5SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD6SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD65DSLVDMSCR);
+	writel(0x00000000, DM_AXI_SDAP0SLVDMSCR);
+	writel(0x00000000, DM_AXI_MAPD2SLVDMSCR);
+	writel(0x00000000, DM_AXI_MAPD3SLVDMSCR);
+	writel(0x00000000, DM_AXI_DMXXDEFAULTSLAVESLVDMSCR);
+	writel(0x00000001, DM_AXI_DMXREGDMSENN);
+
+	/* DMS Register(SYS-AXI256) */
+	writel(0x00000000, SYS_AXI256_SYXDMSCR);
+	writel(0x00000000, SYS_AXI256_MXIDMSCR);
+	writel(0x00000000, SYS_AXI256_X128TO256SLVDMSCR);
+	writel(0x00000000, SYS_AXI256_X256TO128SLVDMSCR);
+	writel(0x00000000, SYS_AXI256_SYXSLVDMSCR);
+	writel(0x00000000, SYS_AXI256_CCXSLVDMSCR);
+	writel(0x00000000, SYS_AXI256_S3CSLVDMSCR);
+
+	/* DMS Register(MXT) */
+	writel(0x00000000, MXT_SYXDMSCR);
+	writel(0x00000000, MXT_IMRSLVDMSCR);
+	writel(0x00000000, MXT_VINSLVDMSCR);
+	writel(0x00000000, MXT_VPC1SLVDMSCR);
+	writel(0x00000000, MXT_VSPD0SLVDMSCR);
+	writel(0x00000000, MXT_VSPD1SLVDMSCR);
+	writel(0x00000000, MXT_MAP1SLVDMSCR);
+	writel(0x00000000, MXT_MAP2SLVDMSCR);
+	writel(0x00000000, MXT_MAP2BSLVDMSCR);
+
+	/* DMS Register(MXI) */
+	writel(0x00000002, MXI_JPURDMSCR);
+	writel(0x00000002, MXI_JPUWDMSCR);
+	writel(0x00000002, MXI_VCTU0RDMSCR);
+	writel(0x00000002, MXI_VCTU0WDMSCR);
+	writel(0x00000002, MXI_VDCTU0RDMSCR);
+	writel(0x00000002, MXI_VDCTU0WDMSCR);
+	writel(0x00000002, MXI_VDCTU1RDMSCR);
+	writel(0x00000002, MXI_VDCTU1WDMSCR);
+	writel(0x00000002, MXI_VIN0WDMSCR);
+	writel(0x00000002, MXI_VIN1WDMSCR);
+	writel(0x00000002, MXI_RDRWDMSCR);
+	writel(0x00000002, MXI_IMS01RDMSCR);
+	writel(0x00000002, MXI_IMS01WDMSCR);
+	writel(0x00000002, MXI_IMS23RDMSCR);
+	writel(0x00000002, MXI_IMS23WDMSCR);
+	writel(0x00000002, MXI_IMS45RDMSCR);
+	writel(0x00000002, MXI_IMS45WDMSCR);
+	writel(0x00000002, MXI_IMRRDMSCR);
+	writel(0x00000002, MXI_IMRWDMSCR);
+	writel(0x00000002, MXI_ROTCE4RDMSCR);
+	writel(0x00000002, MXI_ROTCE4WDMSCR);
+	writel(0x00000002, MXI_ROTVLC4RDMSCR);
+	writel(0x00000002, MXI_ROTVLC4WDMSCR);
+	writel(0x00000002, MXI_VSPD0RDMSCR);
+	writel(0x00000002, MXI_VSPD0WDMSCR);
+	writel(0x00000002, MXI_VSPD1RDMSCR);
+	writel(0x00000002, MXI_VSPD1WDMSCR);
+	writel(0x00000002, MXI_DU0RDMSCR);
+	writel(0x00000002, MXI_DU0WDMSCR);
+	writel(0x00000002, MXI_VSP0RDMSCR);
+	writel(0x00000002, MXI_VSP0WDMSCR);
+	writel(0x00000002, MXI_ROTCE0RDMSCR);
+	writel(0x00000002, MXI_ROTCE0WDMSCR);
+	writel(0x00000002, MXI_ROTVLC0RDMSCR);
+	writel(0x00000002, MXI_ROTVLC0WDMSCR);
+	writel(0x00000002, MXI_ROTCE1RDMSCR);
+	writel(0x00000002, MXI_ROTCE1WDMSCR);
+	writel(0x00000002, MXI_ROTVLC1RDMSCR);
+	writel(0x00000002, MXI_ROTVLC1WDMSCR);
+	writel(0x00000002, MXI_ROTCE2RDMSCR);
+	writel(0x00000002, MXI_ROTCE2WDMSCR);
+	writel(0x00000002, MXI_ROTVLC2RDMSCR);
+	writel(0x00000002, MXI_ROTVLC2WDMSCR);
+	writel(0x00000002, MXI_ROTCE3RDMSCR);
+	writel(0x00000002, MXI_ROTCE3WDMSCR);
+	writel(0x00000002, MXI_ROTVLC3RDMSCR);
+	writel(0x00000002, MXI_ROTVLC3WDMSCR);
+
+	/* DMS Register(CCI-AXI) */
+	writel(0x00000000, CCI_AXI_MMUS0DMSCR);
+	writel(0x00000000, CCI_AXI_SYX2DMSCR);
+	writel(0x00000000, CCI_AXI_MMURDMSCR);
+	writel(0x00000000, CCI_AXI_MMUDSDMSCR);
+	writel(0x00000000, CCI_AXI_MMUMDMSCR);
+	writel(0x00000000, CCI_AXI_MXIDMSCR);
+	writel(0x00000000, CCI_AXI_MMUS1DMSCR);
+	writel(0x00000000, CCI_AXI_MMUMPDMSCR);
+	writel(0x00000000, CCI_AXI_DVMDMSCR);
+	writel(0x00000000, CCI_AXI_CCISLVDMSCR);
+
+	/* CC-AXI Function Register */
+	writel(0x00000011, CCI_AXI_IPMMUIDVMCR);
+	writel(0x00000011, CCI_AXI_IPMMURDVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUS0DVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUS1DVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUMPDVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUDSDVMCR);
+	writel(0x0000F700, CCI_AXI_AX2ADDRMASK);
+
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
diff --git a/roms/u-boot/board/renesas/blanche/qos.h b/roms/u-boot/board/renesas/blanche/qos.h
new file mode 100644
index 000000000..6d2febc4d
--- /dev/null
+++ b/roms/u-boot/board/renesas/blanche/qos.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/roms/u-boot/board/renesas/condor/Kconfig b/roms/u-boot/board/renesas/condor/Kconfig
new file mode 100644
index 000000000..2286d88de
--- /dev/null
+++ b/roms/u-boot/board/renesas/condor/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CONDOR
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "condor"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "condor"
+
+endif
diff --git a/roms/u-boot/board/renesas/condor/MAINTAINERS b/roms/u-boot/board/renesas/condor/MAINTAINERS
new file mode 100644
index 000000000..73b010b9e
--- /dev/null
+++ b/roms/u-boot/board/renesas/condor/MAINTAINERS
@@ -0,0 +1,6 @@
+CONDOR BOARD
+M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+S:	Maintained
+F:	board/renesas/condor/
+F:	include/configs/condor.h
+F:	configs/r8a77980_condor_defconfig
diff --git a/roms/u-boot/board/renesas/condor/Makefile b/roms/u-boot/board/renesas/condor/Makefile
new file mode 100644
index 000000000..cf6d566a9
--- /dev/null
+++ b/roms/u-boot/board/renesas/condor/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/condor/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= ../rcar-common/gen3-spl.o
+else
+obj-y	:= condor.o ../rcar-common/common.o
+endif
diff --git a/roms/u-boot/board/renesas/condor/condor.c b/roms/u-boot/board/renesas/condor/condor.c
new file mode 100644
index 000000000..e930de31b
--- /dev/null
+++ b/roms/u-boot/board/renesas/condor/condor.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/condor/condor.c
+ *     This file is Condor board support.
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.vasut+renesas@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	return 0;
+}
+
+#define RST_BASE	0xE6160000
+#define RST_CA57RESCNT	(RST_BASE + 0x40)
+#define RST_CA53RESCNT	(RST_BASE + 0x44)
+#define RST_RSTOUTCR	(RST_BASE + 0x58)
+#define RST_CA57_CODE	0xA5A5000F
+#define RST_CA53_CODE	0x5A5A000F
+
+void reset_cpu(void)
+{
+	unsigned long midr, cputype;
+
+	asm volatile("mrs %0, midr_el1" : "=r" (midr));
+	cputype = (midr >> 4) & 0xfff;
+
+	if (cputype == 0xd03)
+		writel(RST_CA53_CODE, RST_CA53RESCNT);
+	else if (cputype == 0xd07)
+		writel(RST_CA57_CODE, RST_CA57RESCNT);
+	else
+		hang();
+}
diff --git a/roms/u-boot/board/renesas/draak/Kconfig b/roms/u-boot/board/renesas/draak/Kconfig
new file mode 100644
index 000000000..9106387bb
--- /dev/null
+++ b/roms/u-boot/board/renesas/draak/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_DRAAK
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "draak"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "draak"
+
+endif
diff --git a/roms/u-boot/board/renesas/draak/MAINTAINERS b/roms/u-boot/board/renesas/draak/MAINTAINERS
new file mode 100644
index 000000000..1dbcc2811
--- /dev/null
+++ b/roms/u-boot/board/renesas/draak/MAINTAINERS
@@ -0,0 +1,6 @@
+DRAAK BOARD
+M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+S:	Maintained
+F:	board/renesas/draak/
+F:	include/configs/draak.h
+F:	configs/r8a77995_draak_defconfig
diff --git a/roms/u-boot/board/renesas/draak/Makefile b/roms/u-boot/board/renesas/draak/Makefile
new file mode 100644
index 000000000..1fc90d1da
--- /dev/null
+++ b/roms/u-boot/board/renesas/draak/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/draak/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= ../rcar-common/gen3-spl.o
+else
+obj-y	:= draak.o ../rcar-common/common.o
+endif
diff --git a/roms/u-boot/board/renesas/draak/draak.c b/roms/u-boot/board/renesas/draak/draak.c
new file mode 100644
index 000000000..1d76f95ae
--- /dev/null
+++ b/roms/u-boot/board/renesas/draak/draak.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/draak/draak.c
+ *     This file is Draak board support.
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GSX_MSTP112		BIT(12)	/* 3DG */
+#define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
+#define DVFS_MSTP926		BIT(26)
+#define HSUSB_MSTP704		BIT(4)	/* HSUSB */
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+	/* DVFS for reset */
+	mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
+#endif
+	return 0;
+}
+
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS			0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
+#define HSUSB_REG_UGCTRL2		0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL	0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	/* USB1 pull-up */
+	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+	/* Configure the HSUSB block */
+	mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
+	/* Choice USB0SEL */
+	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+	/* low power status */
+	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
+	return 0;
+}
+
+#define RST_BASE	0xE6160000
+#define RST_CA53RESCNT	(RST_BASE + 0x44)
+#define RST_CA53_CODE	0x5A5A000F
+
+void reset_cpu(void)
+{
+	writel(RST_CA53_CODE, RST_CA53RESCNT);
+}
diff --git a/roms/u-boot/board/renesas/eagle/Kconfig b/roms/u-boot/board/renesas/eagle/Kconfig
new file mode 100644
index 000000000..1e0710e73
--- /dev/null
+++ b/roms/u-boot/board/renesas/eagle/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EAGLE
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "eagle"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "eagle"
+
+endif
diff --git a/roms/u-boot/board/renesas/eagle/MAINTAINERS b/roms/u-boot/board/renesas/eagle/MAINTAINERS
new file mode 100644
index 000000000..f387c1361
--- /dev/null
+++ b/roms/u-boot/board/renesas/eagle/MAINTAINERS
@@ -0,0 +1,6 @@
+EAGLE BOARD
+M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+S:	Maintained
+F:	board/renesas/eagle/
+F:	include/configs/eagle.h
+F:	configs/r8a77970_eagle_defconfig
diff --git a/roms/u-boot/board/renesas/eagle/Makefile b/roms/u-boot/board/renesas/eagle/Makefile
new file mode 100644
index 000000000..062c46ba2
--- /dev/null
+++ b/roms/u-boot/board/renesas/eagle/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/eagle/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= ../rcar-common/gen3-spl.o
+else
+obj-y	:= eagle.o ../rcar-common/common.o
+endif
diff --git a/roms/u-boot/board/renesas/eagle/eagle.c b/roms/u-boot/board/renesas/eagle/eagle.c
new file mode 100644
index 000000000..bb32e3d2c
--- /dev/null
+++ b/roms/u-boot/board/renesas/eagle/eagle.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/eagle/eagle.c
+ *     This file is Eagle board support.
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPGWPR  0xE6150900
+#define CPGWPCR	0xE6150904
+
+/* PLL */
+#define PLL0CR		0xE61500D8
+#define PLL0_STC_MASK	0x7F000000
+#define PLL0_STC_OFFSET	24
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+	u32 stc;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* CPU frequency setting. Set to 0.8GHz */
+	stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
+	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+}
+
+int board_early_init_f(void)
+{
+	/* Unlock CPG access */
+	writel(0xA5A5FFFF, CPGWPR);
+	writel(0x5A5A0000, CPGWPCR);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	return 0;
+}
+
+#define RST_BASE	0xE6160000
+#define RST_CA57RESCNT	(RST_BASE + 0x40)
+#define RST_CA53RESCNT	(RST_BASE + 0x44)
+#define RST_RSTOUTCR	(RST_BASE + 0x58)
+#define RST_CA57_CODE	0xA5A5000F
+#define RST_CA53_CODE	0x5A5A000F
+
+void reset_cpu(void)
+{
+	unsigned long midr, cputype;
+
+	asm volatile("mrs %0, midr_el1" : "=r" (midr));
+	cputype = (midr >> 4) & 0xfff;
+
+	if (cputype == 0xd03)
+		writel(RST_CA53_CODE, RST_CA53RESCNT);
+	else if (cputype == 0xd07)
+		writel(RST_CA57_CODE, RST_CA57RESCNT);
+	else
+		hang();
+}
diff --git a/roms/u-boot/board/renesas/ebisu/Kconfig b/roms/u-boot/board/renesas/ebisu/Kconfig
new file mode 100644
index 000000000..f500a94c9
--- /dev/null
+++ b/roms/u-boot/board/renesas/ebisu/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EBISU
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "ebisu"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "ebisu"
+
+endif
diff --git a/roms/u-boot/board/renesas/ebisu/MAINTAINERS b/roms/u-boot/board/renesas/ebisu/MAINTAINERS
new file mode 100644
index 000000000..facad520c
--- /dev/null
+++ b/roms/u-boot/board/renesas/ebisu/MAINTAINERS
@@ -0,0 +1,6 @@
+EBISU BOARD
+M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+S:	Maintained
+F:	board/renesas/ebisu/
+F:	include/configs/ebisu.h
+F:	configs/r8a77990_ebisu_defconfig
diff --git a/roms/u-boot/board/renesas/ebisu/Makefile b/roms/u-boot/board/renesas/ebisu/Makefile
new file mode 100644
index 000000000..1fd9a03ec
--- /dev/null
+++ b/roms/u-boot/board/renesas/ebisu/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/ebisu/Makefile
+#
+# Copyright (C) 2018 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= ../rcar-common/gen3-spl.o
+else
+obj-y	:= ebisu.o ../rcar-common/common.o
+endif
diff --git a/roms/u-boot/board/renesas/ebisu/ebisu.c b/roms/u-boot/board/renesas/ebisu/ebisu.c
new file mode 100644
index 000000000..9d4af8d3a
--- /dev/null
+++ b/roms/u-boot/board/renesas/ebisu/ebisu.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/ebisu/ebisu.c
+ *     This file is Ebisu board support.
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut+renesas@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	return 0;
+}
+
+#define RST_BASE	0xE6160000
+#define RST_CA53RESCNT	(RST_BASE + 0x44)
+#define RST_CA53_CODE	0x5A5A000F
+
+void reset_cpu(void)
+{
+	writel(RST_CA53_CODE, RST_CA53RESCNT);
+}
diff --git a/roms/u-boot/board/renesas/gose/Kconfig b/roms/u-boot/board/renesas/gose/Kconfig
new file mode 100644
index 000000000..930a44559
--- /dev/null
+++ b/roms/u-boot/board/renesas/gose/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GOSE
+
+config SYS_BOARD
+	default "gose"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "gose"
+
+endif
diff --git a/roms/u-boot/board/renesas/gose/MAINTAINERS b/roms/u-boot/board/renesas/gose/MAINTAINERS
new file mode 100644
index 000000000..cad5be99b
--- /dev/null
+++ b/roms/u-boot/board/renesas/gose/MAINTAINERS
@@ -0,0 +1,6 @@
+ALT BOARD
+M:	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+S:	Maintained
+F:	board/renesas/gose/
+F:	include/configs/gose.h
+F:	configs/gose_defconfig
diff --git a/roms/u-boot/board/renesas/gose/Makefile b/roms/u-boot/board/renesas/gose/Makefile
new file mode 100644
index 000000000..c6a1dc21c
--- /dev/null
+++ b/roms/u-boot/board/renesas/gose/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/gose/Makefile
+#
+# Copyright (C) 2014 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= gose_spl.o
+else
+obj-y	:= gose.o qos.o
+endif
diff --git a/roms/u-boot/board/renesas/gose/gose.c b/roms/u-boot/board/renesas/gose/gose.c
new file mode 100644
index 000000000..51768c315
--- /dev/null
+++ b/roms/u-boot/board/renesas/gose/gose.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/gose/gose.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <hang.h>
+#include <init.h>
+#include <malloc.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <env_internal.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+	u32 stc;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* CPU frequency setting. Set to 1.5GHz */
+	stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+	/* QoS */
+	qos_init();
+}
+
+#define TMU0_MSTP125	BIT(25)
+
+#define SD1CKCR		0xE6150078
+#define SD2CKCR		0xE615026C
+#define SD_97500KHZ	0x7
+
+int board_early_init_f(void)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+	/*
+	 * SD0 clock is set to 97.5MHz by default.
+	 * Set SD1 and SD2 to the 97.5MHz as well.
+	 */
+	writel(SD_97500KHZ, SD1CKCR);
+	writel(SD_97500KHZ, SD2CKCR);
+
+	return 0;
+}
+
+#define ETHERNET_PHY_RESET	176	/* GPIO 5 22 */
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Force ethernet PHY out of reset */
+	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+	gpio_direction_output(ETHERNET_PHY_RESET, 0);
+	mdelay(10);
+	gpio_direction_output(ETHERNET_PHY_RESET, 1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+/* KSZ8041RNLI */
+#define PHY_CONTROL1		0x1E
+#define PHY_LED_MODE		0xC000
+#define PHY_LED_MODE_ACK	0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+	ret &= ~PHY_LED_MODE;
+	ret |= PHY_LED_MODE_ACK;
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	struct udevice *dev;
+	const u8 pmic_bus = 6;
+	const u8 pmic_addr = 0x58;
+	u8 data;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+	if (ret)
+		hang();
+
+	ret = dm_i2c_read(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+
+	data |= BIT(1);
+
+	ret = dm_i2c_write(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	const u32 load_magic = 0xb33fc0de;
+
+	/* Block environment access if loaded using JTAG */
+	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+	    (op != ENVOP_INIT))
+		return ENVL_UNKNOWN;
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	return ENVL_SPI_FLASH;
+}
diff --git a/roms/u-boot/board/renesas/gose/gose_spl.c b/roms/u-boot/board/renesas/gose/gose_spl.c
new file mode 100644
index 000000000..c0bf72044
--- /dev/null
+++ b/roms/u-boot/board/renesas/gose/gose_spl.c
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/gose/gose_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125	BIT(25)
+#define SCIF0_MSTP721	BIT(21)
+#define QSPI_MSTP917	BIT(17)
+
+#define SD2CKCR		0xE615026C
+#define SD_97500KHZ	0x7
+
+struct reg_config {
+	u16	off;
+	u32	val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+		;
+}
+
+static void spl_init_sys(void)
+{
+	u32 r0 = 0;
+
+	writel(0xa5a5a500, 0xe6020004);
+	writel(0xa5a5a500, 0xe6030004);
+
+	asm volatile(
+		/* ICIALLU - Invalidate I$ to PoU */
+		"mcr	15, 0, %0, cr7, cr5, 0	\n"
+		/* BPIALL - Invalidate branch predictors */
+		"mcr	15, 0, %0, cr7, cr5, 6	\n"
+		/* Set SCTLR[IZ] */
+		"mrc	15, 0, %0, cr1, cr0, 0	\n"
+		"orr	%0, #0x1800		\n"
+		"mcr	15, 0, %0, cr1, cr0, 0	\n"
+		"isb	sy			\n"
+		:"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+	static const struct reg_config pfc_with_unlock[] = {
+		{ 0x0090, 0x60000000 },
+		{ 0x0094, 0x60000000 },
+		{ 0x0098, 0x00800200 },
+		{ 0x009c, 0x00000000 },
+		{ 0x0020, 0x00000000 },
+		{ 0x0024, 0x00000000 },
+		{ 0x0028, 0x000244c8 },
+		{ 0x002c, 0x00000000 },
+		{ 0x0030, 0x00002400 },
+		{ 0x0034, 0x01520000 },
+		{ 0x0038, 0x00724003 },
+		{ 0x003c, 0x00000000 },
+		{ 0x0040, 0x00000000 },
+		{ 0x0044, 0x00000000 },
+		{ 0x0048, 0x00000000 },
+		{ 0x004c, 0x00000000 },
+		{ 0x0050, 0x00000000 },
+		{ 0x0054, 0x00000000 },
+		{ 0x0058, 0x00000000 },
+		{ 0x005c, 0x00000000 },
+		{ 0x0160, 0x00000000 },
+		{ 0x0004, 0xffffffff },
+		{ 0x0008, 0x00ec3fff },
+		{ 0x000c, 0x3bc001e7 },
+		{ 0x0010, 0x5bffffff },
+		{ 0x0014, 0x1ffffffb },
+		{ 0x0018, 0x01bffff0 },
+		{ 0x001c, 0xcf7fffff },
+		{ 0x0074, 0x0381fc00 },
+	};
+
+	static const struct reg_config pfc_without_unlock[] = {
+		{ 0x0100, 0xffffffdf },
+		{ 0x0104, 0xc883c3ff },
+		{ 0x0108, 0x1201f3c9 },
+		{ 0x010c, 0x00000000 },
+		{ 0x0110, 0xffffeb04 },
+		{ 0x0114, 0xc003ffff },
+		{ 0x0118, 0x0800000f },
+		{ 0x011c, 0x001800f0 },
+	};
+
+	static const u32 pfc_base = 0xe6060000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+		writel(~pfc_with_unlock[i].val, pfc_base);
+		writel(pfc_with_unlock[i].val,
+		       pfc_base | pfc_with_unlock[i].off);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+		writel(pfc_without_unlock[i].val,
+		       pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+	static const u16 gpio_offs[] = {
+		0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
+	};
+
+	static const struct reg_config gpio_set[] = {
+		{ 0x2000, 0x04381000 },
+		{ 0x5000, 0x00000000 },
+		{ 0x5800, 0x000e0000 },
+	};
+
+	static const struct reg_config gpio_clr[] = {
+		{ 0x1000, 0x00000000 },
+		{ 0x2000, 0x04381010 },
+		{ 0x3000, 0x00000000 },
+		{ 0x4000, 0x00000000 },
+		{ 0x5000, 0x00400000 },
+		{ 0x5400, 0x00000000 },
+		{ 0x5800, 0x000e0380 },
+	};
+
+	static const u32 gpio_base = 0xe6050000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+	static const struct reg_config lbsc_config[] = {
+		{ 0x00, 0x00000020 },
+		{ 0x08, 0x00002020 },
+		{ 0x30, 0x2a103320 },
+		{ 0x38, 0xff70ff70 },
+	};
+
+	static const u16 lbsc_offs[] = {
+		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+	};
+
+	static const u32 lbsc_base = 0xfec00200;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+		writel(lbsc_config[i].val,
+		       lbsc_base | lbsc_config[i].off);
+		writel(lbsc_config[i].val,
+		       lbsc_base | (lbsc_config[i].off + 4));
+	}
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+		writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+	static const struct reg_config dbsc_config1[] = {
+		{ 0x0280, 0x0000a55a },
+		{ 0x0018, 0x21000000 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0018, 0x10000000 },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x80000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config2[] = {
+		{ 0x0290, 0x00000006 },
+		{ 0x02a0, 0x0001c000 },
+	};
+
+	static const struct reg_config dbsc_config4[] = {
+		{ 0x0290, 0x00000010 },
+		{ 0x02a0, 0xf00464db },
+		{ 0x0290, 0x00000061 },
+		{ 0x02a0, 0x0000006d },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000073 },
+		{ 0x0020, 0x00000007 },
+		{ 0x0024, 0x0f030a02 },
+		{ 0x0030, 0x00000001 },
+		{ 0x00b0, 0x00000000 },
+		{ 0x0040, 0x0000000b },
+		{ 0x0044, 0x00000008 },
+		{ 0x0048, 0x00000000 },
+		{ 0x0050, 0x0000000b },
+		{ 0x0054, 0x000c000b },
+		{ 0x0058, 0x00000027 },
+		{ 0x005c, 0x0000001c },
+		{ 0x0060, 0x00000006 },
+		{ 0x0064, 0x00000020 },
+		{ 0x0068, 0x00000008 },
+		{ 0x006c, 0x0000000c },
+		{ 0x0070, 0x00000009 },
+		{ 0x0074, 0x00000012 },
+		{ 0x0078, 0x000000d0 },
+		{ 0x007c, 0x00140005 },
+		{ 0x0080, 0x00050004 },
+		{ 0x0084, 0x70233005 },
+		{ 0x0088, 0x000c0000 },
+		{ 0x008c, 0x00000200 },
+		{ 0x0090, 0x00000040 },
+		{ 0x0100, 0x00000001 },
+		{ 0x00c0, 0x00020001 },
+		{ 0x00c8, 0x20042004 },
+		{ 0x0380, 0x00020002 },
+		{ 0x0390, 0x0000001f },
+	};
+
+	static const struct reg_config dbsc_config5[] = {
+		{ 0x0244, 0x00000011 },
+		{ 0x0290, 0x00000003 },
+		{ 0x02a0, 0x0300c561 },
+		{ 0x0290, 0x00000023 },
+		{ 0x02a0, 0x00fcdb60 },
+		{ 0x0290, 0x00000011 },
+		{ 0x02a0, 0x1000040b },
+		{ 0x0290, 0x00000012 },
+		{ 0x02a0, 0x9d9cbb66 },
+		{ 0x0290, 0x00000013 },
+		{ 0x02a0, 0x1a868400 },
+		{ 0x0290, 0x00000014 },
+		{ 0x02a0, 0x300214d8 },
+		{ 0x0290, 0x00000015 },
+		{ 0x02a0, 0x00000d70 },
+		{ 0x0290, 0x00000016 },
+		{ 0x02a0, 0x00000006 },
+		{ 0x0290, 0x00000017 },
+		{ 0x02a0, 0x00000018 },
+		{ 0x0290, 0x0000001a },
+		{ 0x02a0, 0x910035c7 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config6[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000181 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config7[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x0000fe01 },
+		{ 0x0304, 0x00000000 },
+		{ 0x00f4, 0x01004c20 },
+		{ 0x00f8, 0x014000aa },
+		{ 0x00e0, 0x00000140 },
+		{ 0x00e4, 0x00081860 },
+		{ 0x00e8, 0x00010000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config8[] = {
+		{ 0x0014, 0x00000001 },
+		{ 0x0010, 0x00000001 },
+		{ 0x0280, 0x00000000 },
+	};
+
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
+		writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+		writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+	dbsc_wait(0x240);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void spl_init_qspi(void)
+{
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	static const u32 qspi_base = 0xe6b10000;
+
+	writeb(0x08, qspi_base + 0x00);
+	writeb(0x00, qspi_base + 0x01);
+	writeb(0x06, qspi_base + 0x02);
+	writeb(0x01, qspi_base + 0x0a);
+	writeb(0x00, qspi_base + 0x0b);
+	writeb(0x00, qspi_base + 0x0c);
+	writeb(0x00, qspi_base + 0x0d);
+	writeb(0x00, qspi_base + 0x0e);
+
+	writew(0xe080, qspi_base + 0x10);
+
+	writeb(0xc0, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x08);
+	writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	/*
+	 * SD0 clock is set to 97.5MHz by default.
+	 * Set SD2 to the 97.5MHz as well.
+	 */
+	writel(SD_97500KHZ, SD2CKCR);
+
+	spl_init_sys();
+	spl_init_pfc();
+	spl_init_gpio();
+	spl_init_lbsc();
+	spl_init_dbsc();
+	spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	const u32 jtag_magic = 0x1337c0de;
+	const u32 load_magic = 0xb33fc0de;
+
+	/*
+	 * If JTAG probe sets special word at 0xe6300020, then it must
+	 * put U-Boot into RAM and SPL will start it from RAM.
+	 */
+	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+		printf("JTAG boot detected!\n");
+
+		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+			;
+
+		spl_boot_list[0] = BOOT_DEVICE_RAM;
+		spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+		return;
+	}
+
+	/* Boot from SPI NOR with YMODEM UART fallback. */
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+	spl_boot_list[1] = BOOT_DEVICE_UART;
+	spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/roms/u-boot/board/renesas/gose/qos.c b/roms/u-boot/board/renesas/gose/qos.c
new file mode 100644
index 000000000..1c4ebfc6a
--- /dev/null
+++ b/roms/u-boot/board/renesas/gose/qos.c
@@ -0,0 +1,1202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/gose/qos.c
+ *     This file is gose QoS setting.
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
+/* QoS version 0.311 */
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+#if defined(CONFIG_QOS_PRI_MEDIA)
+#define is_qos_pri_media()	1
+#else
+#define is_qos_pri_media()	0
+#endif
+
+#if defined(CONFIG_QOS_PRI_NORMAL)
+#define is_qos_pri_normal()	1
+#else
+#define is_qos_pri_normal()	0
+#endif
+
+#if defined(CONFIG_QOS_PRI_GFX)
+#define is_qos_pri_gfx()	1
+#else
+#define is_qos_pri_gfx()	0
+#endif
+
+void qos_init(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	writel(0x00000000, &s3c->s3cadsplcr);
+	if (is_qos_pri_media()) {
+		writel(0x1F0B0604, &s3c->s3crorr);
+		writel(0x1F0E0705, &s3c->s3cworr);
+	} else if (is_qos_pri_normal()) {
+		writel(0x1F0B0908, &s3c->s3crorr);
+		writel(0x1F0C0A08, &s3c->s3cworr);
+	} else if (is_qos_pri_gfx()) {
+		writel(0x1F0B0B0B, &s3c->s3crorr);
+		writel(0x1F0E0C0C, &s3c->s3cworr);
+	}
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x00820092, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00820092, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20FA, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20FA, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000201E, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* CCI-400 -QoS */
+	writel(0x20001000, CCI_400_MAXOT_1);
+	writel(0x20001000, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000016, &mxi->mxwtcr);
+	writel(0x00200000, &mxi->mxs3cracr);
+	writel(0x00200000, &mxi->mxs3cwacr);
+	writel(0x00200000, &mxi->mxaxiracr);
+	writel(0x00200000, &mxi->mxaxiwacr);
+	writel(0x00780080, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000E, &mxi_qos->du0);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002299, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000206E, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+}
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/roms/u-boot/board/renesas/gose/qos.h b/roms/u-boot/board/renesas/gose/qos.h
new file mode 100644
index 000000000..29f05c7ff
--- /dev/null
+++ b/roms/u-boot/board/renesas/gose/qos.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/roms/u-boot/board/renesas/grpeach/Kconfig b/roms/u-boot/board/renesas/grpeach/Kconfig
new file mode 100644
index 000000000..00dc496b8
--- /dev/null
+++ b/roms/u-boot/board/renesas/grpeach/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GRPEACH
+
+config SYS_BOARD
+	default "grpeach"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "grpeach"
+
+endif
diff --git a/roms/u-boot/board/renesas/grpeach/MAINTAINERS b/roms/u-boot/board/renesas/grpeach/MAINTAINERS
new file mode 100644
index 000000000..4ab7773b0
--- /dev/null
+++ b/roms/u-boot/board/renesas/grpeach/MAINTAINERS
@@ -0,0 +1,6 @@
+GRPEACH BOARD
+M:	Marek Vasut <marek.vasut@gmail.com>
+S:	Maintained
+F:	board/renesas/grpeach/
+F:	include/configs/grpeach.h
+F:	configs/grpeach_defconfig
diff --git a/roms/u-boot/board/renesas/grpeach/Makefile b/roms/u-boot/board/renesas/grpeach/Makefile
new file mode 100644
index 000000000..48e185ce3
--- /dev/null
+++ b/roms/u-boot/board/renesas/grpeach/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2017 Renesas Electronics
+# Copyright (C) 2017 Chris Brandt
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	:= grpeach.o
+obj-y	+= lowlevel_init.o
diff --git a/roms/u-boot/board/renesas/grpeach/grpeach.c b/roms/u-boot/board/renesas/grpeach/grpeach.c
new file mode 100644
index 000000000..199ec4a31
--- /dev/null
+++ b/roms/u-boot/board/renesas/grpeach/grpeach.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Renesas Electronics
+ * Copyright (C) Chris Brandt
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+#define RZA1_WDT_BASE	0xfcfe0000
+#define WTCSR		0x00
+#define WTCNT		0x02
+#define WRCSR		0x04
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	/* Dummy read (must read WRCSR:WOVF at least once before clearing) */
+	readb(RZA1_WDT_BASE + WRCSR);
+
+	writew(0xa500, RZA1_WDT_BASE + WRCSR);
+	writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
+	writew(0x5a00, RZA1_WDT_BASE + WTCNT);
+	writew(0xa578, RZA1_WDT_BASE + WTCSR);
+
+	for (;;)
+		asm volatile("wfi");
+}
diff --git a/roms/u-boot/board/renesas/grpeach/lowlevel_init.S b/roms/u-boot/board/renesas/grpeach/lowlevel_init.S
new file mode 100644
index 000000000..9a66dfa6c
--- /dev/null
+++ b/roms/u-boot/board/renesas/grpeach/lowlevel_init.S
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Renesas Electronics
+ * Copyright (C) 2017 Chris Brandt
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+
+/* Watchdog Registers */
+#define RZA1_WDT_BASE	0xFCFE0000
+#define WTCSR	(RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */
+#define WTCNT	(RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */
+#define WRCSR	(RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */
+
+/* Standby controller registers (chapter 55) */
+#define RZA1_STBCR_BASE	0xFCFE0020
+#define STBCR1	(RZA1_STBCR_BASE + 0x00)
+#define STBCR2	(RZA1_STBCR_BASE + 0x04)
+#define STBCR3	(RZA1_STBCR_BASE + 0x400)
+#define STBCR4	(RZA1_STBCR_BASE + 0x404)
+#define STBCR5	(RZA1_STBCR_BASE + 0x408)
+#define STBCR6	(RZA1_STBCR_BASE + 0x40c)
+#define STBCR7	(RZA1_STBCR_BASE + 0x410)
+#define STBCR8	(RZA1_STBCR_BASE + 0x414)
+#define STBCR9	(RZA1_STBCR_BASE + 0x418)
+#define STBCR10	(RZA1_STBCR_BASE + 0x41c)
+#define STBCR11	(RZA1_STBCR_BASE + 0x420)
+#define STBCR12	(RZA1_STBCR_BASE + 0x424)
+#define STBCR13	(RZA1_STBCR_BASE + 0x450)
+
+/* Clock Registers */
+#define RZA1_FRQCR_BASE	0xFCFE0010
+#define FRQCR	(RZA1_FRQCR_BASE + 0x00)
+#define FRQCR2	(RZA1_FRQCR_BASE + 0x04)
+
+#define SYSCR1	0xFCFE0400 /* System control register 1 */
+#define SYSCR2	0xFCFE0404 /* System control register 2 */
+#define SYSCR3	0xFCFE0408 /* System control register 3 */
+
+/* Disable WDT */
+#define WTCSR_D		0xA518
+#define WTCNT_D		0x5A00
+
+/* Enable all peripheral clocks */
+#define STBCR3_D	0x00000000
+#define STBCR4_D	0x00000000
+#define STBCR5_D	0x00000000
+#define STBCR6_D	0x00000000
+#define STBCR7_D	0x00000024
+#define STBCR8_D	0x00000005
+#define STBCR9_D	0x00000000
+#define STBCR10_D	0x00000000
+#define STBCR11_D	0x000000c0
+#define STBCR12_D	0x000000f0
+
+/*
+ * Set all system clocks to full speed.
+ * On reset, the CPU will be running at 1/2 speed.
+ * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges
+ */
+#define FRQCR_D		0x0035
+#define FRQCR2_D	0x0001
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	/* PL310 init */
+	write32 0x3fffff80, 0x00000001
+
+	/* Disable WDT */
+	write16	WTCSR, WTCSR_D
+	write16	WTCNT, WTCNT_D
+
+	/* Set clocks */
+	write16	FRQCR, FRQCR_D
+	write16	FRQCR2, FRQCR2_D
+
+	/* Enable all peripherals(Standby Control) */
+	write8 STBCR3, STBCR3_D
+	write8 STBCR4, STBCR4_D
+	write8 STBCR5, STBCR5_D
+	write8 STBCR6, STBCR6_D
+	write8 STBCR7, STBCR7_D
+	write8 STBCR8, STBCR8_D
+	write8 STBCR9, STBCR9_D
+	write8 STBCR10, STBCR10_D
+	write8 STBCR11, STBCR11_D
+	write8 STBCR12, STBCR12_D
+
+	/* For serial booting, enable read ahead caching to speed things up */
+#define DRCR_0  0x3FEFA00C
+	write32 DRCR_0, 0x00010100	/* Read Burst ON, Length=2 */
+
+	/* Enable all internal RAM */
+	write8 SYSCR1, 0xFF
+	write8 SYSCR2, 0xFF
+	write8 SYSCR3, 0xFF
+
+	nop
+	/* back to arch calling code */
+	mov	pc, lr
+
+	.align 4
diff --git a/roms/u-boot/board/renesas/koelsch/Kconfig b/roms/u-boot/board/renesas/koelsch/Kconfig
new file mode 100644
index 000000000..6475f02b6
--- /dev/null
+++ b/roms/u-boot/board/renesas/koelsch/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KOELSCH
+
+config SYS_BOARD
+	default "koelsch"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "koelsch"
+
+endif
diff --git a/roms/u-boot/board/renesas/koelsch/MAINTAINERS b/roms/u-boot/board/renesas/koelsch/MAINTAINERS
new file mode 100644
index 000000000..5267b9fad
--- /dev/null
+++ b/roms/u-boot/board/renesas/koelsch/MAINTAINERS
@@ -0,0 +1,6 @@
+KOELSCH BOARD
+M:	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+S:	Maintained
+F:	board/renesas/koelsch/
+F:	include/configs/koelsch.h
+F:	configs/koelsch_defconfig
diff --git a/roms/u-boot/board/renesas/koelsch/Makefile b/roms/u-boot/board/renesas/koelsch/Makefile
new file mode 100644
index 000000000..77cf06740
--- /dev/null
+++ b/roms/u-boot/board/renesas/koelsch/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/koelsch/Makefile
+#
+# Copyright (C) 2013 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= koelsch_spl.o
+else
+obj-y	:= koelsch.o qos.o
+endif
diff --git a/roms/u-boot/board/renesas/koelsch/koelsch.c b/roms/u-boot/board/renesas/koelsch/koelsch.c
new file mode 100644
index 000000000..7e94bd820
--- /dev/null
+++ b/roms/u-boot/board/renesas/koelsch/koelsch.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/koelsch/koelsch.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <hang.h>
+#include <init.h>
+#include <malloc.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <env_internal.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <div64.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+	u32 stc;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* CPU frequency setting. Set to 1.5GHz */
+	stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+	/* QoS */
+	qos_init();
+}
+
+#define TMU0_MSTP125	BIT(25)
+
+#define SD1CKCR		0xE6150078
+#define SD2CKCR		0xE615026C
+#define SD_97500KHZ	0x7
+
+int board_early_init_f(void)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+	/*
+	 * SD0 clock is set to 97.5MHz by default.
+	 * Set SD1 and SD2 to the 97.5MHz as well.
+	 */
+	writel(SD_97500KHZ, SD1CKCR);
+	writel(SD_97500KHZ, SD2CKCR);
+
+	return 0;
+}
+
+#define ETHERNET_PHY_RESET	176	/* GPIO 5 22 */
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Force ethernet PHY out of reset */
+	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+	gpio_direction_output(ETHERNET_PHY_RESET, 0);
+	mdelay(10);
+	gpio_direction_output(ETHERNET_PHY_RESET, 1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+/* Koelsch has KSZ8041NL/RNL */
+#define PHY_CONTROL1		0x1E
+#define PHY_LED_MODE		0xC000
+#define PHY_LED_MODE_ACK	0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+	ret &= ~PHY_LED_MODE;
+	ret |= PHY_LED_MODE_ACK;
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	struct udevice *dev;
+	const u8 pmic_bus = 6;
+	const u8 pmic_addr = 0x58;
+	u8 data;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+	if (ret)
+		hang();
+
+	ret = dm_i2c_read(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+
+	data |= BIT(1);
+
+	ret = dm_i2c_write(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	const u32 load_magic = 0xb33fc0de;
+
+	/* Block environment access if loaded using JTAG */
+	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+	    (op != ENVOP_INIT))
+		return ENVL_UNKNOWN;
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	return ENVL_SPI_FLASH;
+}
diff --git a/roms/u-boot/board/renesas/koelsch/koelsch_spl.c b/roms/u-boot/board/renesas/koelsch/koelsch_spl.c
new file mode 100644
index 000000000..b377f7071
--- /dev/null
+++ b/roms/u-boot/board/renesas/koelsch/koelsch_spl.c
@@ -0,0 +1,412 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/koelsch/koelsch_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125	BIT(25)
+#define SCIF0_MSTP721	BIT(21)
+#define QSPI_MSTP917	BIT(17)
+
+#define SD2CKCR		0xE615026C
+#define SD_97500KHZ	0x7
+
+struct reg_config {
+	u16	off;
+	u32	val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+
+	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+		;
+
+	while (!(readl(dbsc3_1_base + reg) & BIT(0)))
+		;
+}
+
+static void spl_init_sys(void)
+{
+	u32 r0 = 0;
+
+	writel(0xa5a5a500, 0xe6020004);
+	writel(0xa5a5a500, 0xe6030004);
+
+	asm volatile(
+		/* ICIALLU - Invalidate I$ to PoU */
+		"mcr	15, 0, %0, cr7, cr5, 0	\n"
+		/* BPIALL - Invalidate branch predictors */
+		"mcr	15, 0, %0, cr7, cr5, 6	\n"
+		/* Set SCTLR[IZ] */
+		"mrc	15, 0, %0, cr1, cr0, 0	\n"
+		"orr	%0, #0x1800		\n"
+		"mcr	15, 0, %0, cr1, cr0, 0	\n"
+		"isb	sy			\n"
+		:"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+	static const struct reg_config pfc_with_unlock[] = {
+		{ 0x0090, 0x60000000 },
+		{ 0x0094, 0x60000000 },
+		{ 0x0098, 0x00800200 },
+		{ 0x009c, 0x00000000 },
+		{ 0x0020, 0x00000000 },
+		{ 0x0024, 0x00000000 },
+		{ 0x0028, 0x000244c8 },
+		{ 0x002c, 0x00000000 },
+		{ 0x0030, 0x00002400 },
+		{ 0x0034, 0x01520000 },
+		{ 0x0038, 0x00724003 },
+		{ 0x003c, 0x00000000 },
+		{ 0x0040, 0x00000000 },
+		{ 0x0044, 0x00000000 },
+		{ 0x0048, 0x00000000 },
+		{ 0x004c, 0x00000000 },
+		{ 0x0050, 0x00000000 },
+		{ 0x0054, 0x00000000 },
+		{ 0x0058, 0x00000000 },
+		{ 0x005c, 0x00000000 },
+		{ 0x0160, 0x00000000 },
+		{ 0x0004, 0xffffffff },
+		{ 0x0008, 0x00ec3fff },
+		{ 0x000c, 0x3bc001e7 },
+		{ 0x0010, 0x5bffffff },
+		{ 0x0014, 0x1ffffffb },
+		{ 0x0018, 0x01bffff0 },
+		{ 0x001c, 0xcf7fffff },
+		{ 0x0074, 0x0381fc00 },
+	};
+
+	static const struct reg_config pfc_without_unlock[] = {
+		{ 0x0100, 0xffffffdf },
+		{ 0x0104, 0xc883c3ff },
+		{ 0x0108, 0x1201f3c9 },
+		{ 0x010c, 0x00000000 },
+		{ 0x0110, 0xffffeb04 },
+		{ 0x0114, 0xc003ffff },
+		{ 0x0118, 0x0800000f },
+		{ 0x011c, 0x001800f0 },
+	};
+
+	static const u32 pfc_base = 0xe6060000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+		writel(~pfc_with_unlock[i].val, pfc_base);
+		writel(pfc_with_unlock[i].val,
+		       pfc_base | pfc_with_unlock[i].off);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+		writel(pfc_without_unlock[i].val,
+		       pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+	static const u16 gpio_offs[] = {
+		0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
+	};
+
+	static const struct reg_config gpio_set[] = {
+		{ 0x2000, 0x04381000 },
+		{ 0x5000, 0x00000000 },
+		{ 0x5800, 0x000e0000 },
+
+	};
+
+	static const struct reg_config gpio_clr[] = {
+		{ 0x1000, 0x00000000 },
+		{ 0x2000, 0x04381010 },
+		{ 0x3000, 0x00000000 },
+		{ 0x4000, 0x00000000 },
+		{ 0x5000, 0x00400000 },
+		{ 0x5400, 0x00000000 },
+		{ 0x5800, 0x000e0380 },
+	};
+
+	static const u32 gpio_base = 0xe6050000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+	static const struct reg_config lbsc_config[] = {
+		{ 0x00, 0x00000020 },
+		{ 0x08, 0x00002020 },
+		{ 0x30, 0x2a103320 },
+		{ 0x38, 0xff70ff70 },
+	};
+
+	static const u16 lbsc_offs[] = {
+		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+	};
+
+	static const u32 lbsc_base = 0xfec00200;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+		writel(lbsc_config[i].val,
+		       lbsc_base | lbsc_config[i].off);
+		writel(lbsc_config[i].val,
+		       lbsc_base | (lbsc_config[i].off + 4));
+	}
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+		writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+	static const struct reg_config dbsc_config1[] = {
+		{ 0x0018, 0x21000000 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0018, 0x10000000 },
+		{ 0x0280, 0x0000a55a },
+		{ 0x0290, 0x00000010 },
+		{ 0x02a0, 0xf004649b },
+		{ 0x0020, 0x00000007 },
+		{ 0x0024, 0x0f030a02 },
+		{ 0x0030, 0x00000001 },
+		{ 0x00b0, 0x00000000 },
+		{ 0x0040, 0x0000000b },
+		{ 0x0044, 0x00000008 },
+		{ 0x0048, 0x00000000 },
+		{ 0x0050, 0x0000000b },
+		{ 0x0054, 0x000c000b },
+		{ 0x0058, 0x00000027 },
+		{ 0x005c, 0x0000001c },
+		{ 0x0060, 0x00000006 },
+		{ 0x0064, 0x00000020 },
+		{ 0x0068, 0x00000008 },
+		{ 0x006c, 0x0000000c },
+		{ 0x0070, 0x00000009 },
+		{ 0x0074, 0x00000012 },
+		{ 0x0078, 0x000000d0 },
+		{ 0x007c, 0x00140005 },
+		{ 0x0080, 0x00050004 },
+		{ 0x0084, 0x70233005 },
+		{ 0x0088, 0x000c0000 },
+		{ 0x008c, 0x00000300 },
+		{ 0x0090, 0x00000040 },
+		{ 0x0100, 0x00000001 },
+		{ 0x00c0, 0x00020001 },
+		{ 0x00c8, 0x20082008 },
+		{ 0x0380, 0x00020002 },
+		{ 0x0390, 0x0000001f },
+	};
+
+	static const struct reg_config dbsc_config5[] = {
+		{ 0x0244, 0x00000011 },
+		{ 0x0290, 0x00000006 },
+		{ 0x02a0, 0x0005c000 },
+		{ 0x0290, 0x00000003 },
+		{ 0x02a0, 0x0300c481 },
+		{ 0x0290, 0x00000023 },
+		{ 0x02a0, 0x00fdb6c0 },
+		{ 0x0290, 0x00000011 },
+		{ 0x02a0, 0x1000040b },
+		{ 0x0290, 0x00000012 },
+		{ 0x02a0, 0x9d9cbb66 },
+		{ 0x0290, 0x00000013 },
+		{ 0x02a0, 0x1a868400 },
+		{ 0x0290, 0x00000014 },
+		{ 0x02a0, 0x300214d8 },
+		{ 0x0290, 0x00000015 },
+		{ 0x02a0, 0x00000d70 },
+		{ 0x0290, 0x00000016 },
+		{ 0x02a0, 0x00000006 },
+		{ 0x0290, 0x00000017 },
+		{ 0x02a0, 0x00000018 },
+		{ 0x0290, 0x0000001a },
+		{ 0x02a0, 0x910035c7 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config6[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000181 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config7[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x0000fe01 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config8[] = {
+		{ 0x0304, 0x00000000 },
+		{ 0x00f4, 0x01004c20 },
+		{ 0x00f8, 0x014000aa },
+		{ 0x00e0, 0x00000140 },
+		{ 0x00e4, 0x00081860 },
+		{ 0x00e8, 0x00010000 },
+		{ 0x0014, 0x00000001 },
+		{ 0x0010, 0x00000001 },
+		{ 0x0280, 0x00000000 },
+	};
+
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
+		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+		writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
+	}
+
+	dbsc_wait(0x240);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
+		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+		writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
+		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+		writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
+		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+		writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
+		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+		writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
+	}
+
+}
+
+static void spl_init_qspi(void)
+{
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	static const u32 qspi_base = 0xe6b10000;
+
+	writeb(0x08, qspi_base + 0x00);
+	writeb(0x00, qspi_base + 0x01);
+	writeb(0x06, qspi_base + 0x02);
+	writeb(0x01, qspi_base + 0x0a);
+	writeb(0x00, qspi_base + 0x0b);
+	writeb(0x00, qspi_base + 0x0c);
+	writeb(0x00, qspi_base + 0x0d);
+	writeb(0x00, qspi_base + 0x0e);
+
+	writew(0xe080, qspi_base + 0x10);
+
+	writeb(0xc0, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x08);
+	writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+	int i;
+
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	/*
+	 * SD0 clock is set to 97.5MHz by default.
+	 * Set SD2 to the 97.5MHz as well.
+	 */
+	writel(SD_97500KHZ, SD2CKCR);
+
+	spl_init_sys();
+	spl_init_pfc();
+	spl_init_gpio();
+	spl_init_lbsc();
+
+	/* Unknown, likely ES1.0-specific delay */
+	for (i = 0; i < 100000; i++)
+		asm volatile("nop");
+
+	spl_init_dbsc();
+	spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	const u32 jtag_magic = 0x1337c0de;
+	const u32 load_magic = 0xb33fc0de;
+
+	/*
+	 * If JTAG probe sets special word at 0xe6300020, then it must
+	 * put U-Boot into RAM and SPL will start it from RAM.
+	 */
+	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+		printf("JTAG boot detected!\n");
+
+		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+			;
+
+		spl_boot_list[0] = BOOT_DEVICE_RAM;
+		spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+		return;
+	}
+
+	/* Boot from SPI NOR with YMODEM UART fallback. */
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+	spl_boot_list[1] = BOOT_DEVICE_UART;
+	spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/roms/u-boot/board/renesas/koelsch/qos.c b/roms/u-boot/board/renesas/koelsch/qos.c
new file mode 100644
index 000000000..f884e5fe6
--- /dev/null
+++ b/roms/u-boot/board/renesas/koelsch/qos.c
@@ -0,0 +1,1390 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/koelsch/qos.c
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.240 for ES1 and version 0.411 for ES2 */
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_1_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_1_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_1_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_1_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_1_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_1_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_1_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_1_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_1_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_1_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_1_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_1_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_1_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_1_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_1_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_1_QOS_R15_BASE,
+};
+
+static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_1_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_1_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_1_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_1_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_1_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_1_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_1_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_1_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_1_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_1_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_1_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_1_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_1_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_1_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_1_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_1_QOS_W15_BASE,
+};
+
+#if defined(CONFIG_QOS_PRI_MEDIA)
+#define is_qos_pri_media()	1
+#else
+#define is_qos_pri_media()	0
+#endif
+
+#if defined(CONFIG_QOS_PRI_NORMAL)
+#define is_qos_pri_normal()	1
+#else
+#define is_qos_pri_normal()	0
+#endif
+
+#if defined(CONFIG_QOS_PRI_GFX)
+#define is_qos_pri_gfx()	1
+#else
+#define is_qos_pri_gfx()	0
+#endif
+
+void qos_init(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+	writel(0x20042004, DBSC3_1_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	if (IS_R8A7791_ES2()) {
+		/* Linear All mode */
+		/* writel(0x00000000, &s3c->s3cadsplcr); */
+		/* Linear Linear 0x7000 to 0x7800 mode */
+		writel(0x00BF1B0C, &s3c->s3cadsplcr);
+		/* Split Linear 0x6800 t 0x7000 mode */
+		/* writel(0x00DF1B0C, &s3c->s3cadsplcr); */
+		/* Ssplit All mode */
+		/* writel(0x00FF1B0C, &s3c->s3cadsplcr); */
+
+		if (is_qos_pri_media()) {
+			writel(0x1F0B0604, &s3c->s3crorr);
+			writel(0x1F0E0705, &s3c->s3cworr);
+		} else if (is_qos_pri_normal()) {
+			writel(0x1F0B0908, &s3c->s3crorr);
+			writel(0x1F0E0A08, &s3c->s3cworr);
+		} else if (is_qos_pri_gfx()) {
+			writel(0x1F0B0B0B, &s3c->s3crorr);
+			writel(0x1F0E0C0C, &s3c->s3cworr);
+		}
+	} else {
+		writel(0x00FF1B1D, &s3c->s3cadsplcr);
+		writel(0x1F0D0C0C, &s3c->s3crorr);
+		writel(0x1F0D0C0A, &s3c->s3cworr);
+	}
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+
+	if (IS_R8A7791_ES2()) {
+		if (is_qos_pri_media())
+			writel(0x20AA2300, &s3c_qos->s3cqos3);
+		else if (is_qos_pri_normal())
+			writel(0x20AA2200, &s3c_qos->s3cqos3);
+		else if (is_qos_pri_gfx())
+			writel(0x20AA2100, &s3c_qos->s3cqos3);
+	} else {
+		writel(0x20AA2200, &s3c_qos->s3cqos3);
+	}
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+
+	if (IS_R8A7791_ES2()) {
+		if (is_qos_pri_media())
+			writel(0x20AA2300, &s3c_qos->s3cqos7);
+		else if (is_qos_pri_normal())
+			writel(0x20AA2200, &s3c_qos->s3cqos7);
+		else if (is_qos_pri_gfx())
+			writel(0x20AA2100, &s3c_qos->s3cqos7);
+	} else {
+		writel(0x20AA2200, &s3c_qos->s3cqos7);
+	}
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	if (IS_R8A7791_ES2()) {
+		if (is_qos_pri_media())
+			writel(0x20AA2300, &s3c_qos->s3cqos3);
+		else if (is_qos_pri_normal())
+			writel(0x20AA2200, &s3c_qos->s3cqos3);
+		else if (is_qos_pri_gfx())
+			writel(0x20AA2100, &s3c_qos->s3cqos3);
+	} else {
+		writel(0x20AA2200, &s3c_qos->s3cqos3);
+	}
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	if (IS_R8A7791_ES2()) {
+		if (is_qos_pri_media())
+			writel(0x20AA2300, &s3c_qos->s3cqos7);
+		else if (is_qos_pri_normal())
+			writel(0x20AA2200, &s3c_qos->s3cqos7);
+		else if (is_qos_pri_gfx())
+			writel(0x20AA2100, &s3c_qos->s3cqos7);
+	} else {
+		writel(0x20AA2200, &s3c_qos->s3cqos7);
+	}
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x80928092, &s3c_qos->s3cqos0);
+	else
+		writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x80928092, &s3c_qos->s3cqos0);
+	else
+		writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20FA, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20FA, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000201E, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC1 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000201E, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC1 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* CCI-400 -QoS */
+	writel(0x20001000, CCI_400_MAXOT_1);
+	writel(0x20001000, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)XI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000016, &mxi->mxwtcr);
+		writel(0x00780080, &mxi->mxsaar0);
+		writel(0x02000800, &mxi->mxsaar1);
+	} else {
+		writel(0x00000013, &mxi->mxwtcr);
+	}
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000E, &mxi_qos->du0);
+	writel(0x0000000D, &mxi_qos->du1);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000001, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002299, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000206E, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	if (IS_R8A7791_ES2())
+		writel(0x000020EB, &axi_qos->qosctset0);
+	else
+		writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	if (IS_R8A7791_ES2())
+		writel(0x000020EB, &axi_qos->qosctset0);
+	else
+		writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	if (IS_R8A7791_ES2())
+		writel(0x000020EB, &axi_qos->qosctset0);
+	else
+		writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	if (IS_R8A7791_ES2())
+		writel(0x00001FF0, &axi_qos->qosctset0);
+	else
+		writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	if (IS_R8A7791_ES2())
+		writel(0x00002001, &axi_qos->qosthres2);
+	else
+		writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000003, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000003, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000003, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000003, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000003, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000000, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+}
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/roms/u-boot/board/renesas/koelsch/qos.h b/roms/u-boot/board/renesas/koelsch/qos.h
new file mode 100644
index 000000000..d92c43704
--- /dev/null
+++ b/roms/u-boot/board/renesas/koelsch/qos.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/roms/u-boot/board/renesas/lager/Kconfig b/roms/u-boot/board/renesas/lager/Kconfig
new file mode 100644
index 000000000..e990c2019
--- /dev/null
+++ b/roms/u-boot/board/renesas/lager/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LAGER
+
+config SYS_BOARD
+	default "lager"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "lager"
+
+endif
diff --git a/roms/u-boot/board/renesas/lager/MAINTAINERS b/roms/u-boot/board/renesas/lager/MAINTAINERS
new file mode 100644
index 000000000..a09868614
--- /dev/null
+++ b/roms/u-boot/board/renesas/lager/MAINTAINERS
@@ -0,0 +1,6 @@
+LAGER BOARD
+M:	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+S:	Maintained
+F:	board/renesas/lager/
+F:	include/configs/lager.h
+F:	configs/lager_defconfig
diff --git a/roms/u-boot/board/renesas/lager/Makefile b/roms/u-boot/board/renesas/lager/Makefile
new file mode 100644
index 000000000..379368fdf
--- /dev/null
+++ b/roms/u-boot/board/renesas/lager/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/lager/Makefile
+#
+# Copyright (C) 2013 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= lager_spl.o
+else
+obj-y	:= lager.o qos.o
+endif
diff --git a/roms/u-boot/board/renesas/lager/lager.c b/roms/u-boot/board/renesas/lager/lager.c
new file mode 100644
index 000000000..87c5e0137
--- /dev/null
+++ b/roms/u-boot/board/renesas/lager/lager.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/lager/lager.c
+ *     This file is lager board support.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <env_internal.h>
+#include <hang.h>
+#include <init.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <mmc.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* CPU frequency setting. Set to 1.4GHz */
+	if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
+		u32 stat = 0;
+		u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
+			<< PLL0_STC_BIT;
+		clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+		do {
+			stat = readl(PLLECR) & PLL0ST;
+		} while (stat == 0x0);
+	}
+
+	/* QoS(Quality-of-Service) Init */
+	qos_init();
+}
+
+#define TMU0_MSTP125	BIT(25)
+
+#define SD1CKCR		0xE6150078
+#define SD2CKCR		0xE615026C
+#define SD_97500KHZ	0x7
+
+int board_early_init_f(void)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+	/*
+	 * SD0 clock is set to 97.5MHz by default.
+	 * Set SD1 and SD2 to the 97.5MHz as well.
+	 */
+	writel(SD_97500KHZ, SD1CKCR);
+	writel(SD_97500KHZ, SD2CKCR);
+
+	return 0;
+}
+
+#define ETHERNET_PHY_RESET	185	/* GPIO 5 31 */
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Force ethernet PHY out of reset */
+	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+	gpio_direction_output(ETHERNET_PHY_RESET, 0);
+	mdelay(10);
+	gpio_direction_output(ETHERNET_PHY_RESET, 1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+/* KSZ8041NL/RNL */
+#define PHY_CONTROL1		0x1E
+#define PHY_LED_MODE		0xC000
+#define PHY_LED_MODE_ACK	0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+	ret &= ~PHY_LED_MODE;
+	ret |= PHY_LED_MODE_ACK;
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	struct udevice *dev;
+	const u8 pmic_bus = 2;
+	const u8 pmic_addr = 0x58;
+	u8 data;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+	if (ret)
+		hang();
+
+	ret = dm_i2c_read(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+
+	data |= BIT(1);
+
+	ret = dm_i2c_write(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	const u32 load_magic = 0xb33fc0de;
+
+	/* Block environment access if loaded using JTAG */
+	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+	    (op != ENVOP_INIT))
+		return ENVL_UNKNOWN;
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	return ENVL_SPI_FLASH;
+}
diff --git a/roms/u-boot/board/renesas/lager/lager_spl.c b/roms/u-boot/board/renesas/lager/lager_spl.c
new file mode 100644
index 000000000..d3d397e8f
--- /dev/null
+++ b/roms/u-boot/board/renesas/lager/lager_spl.c
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/lager/lager_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125	BIT(25)
+#define SCIF0_MSTP721	BIT(21)
+#define QSPI_MSTP917	BIT(17)
+
+#define SD2CKCR		0xE615026C
+#define SD_97500KHZ	0x7
+
+struct reg_config {
+	u16	off;
+	u32	val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+		;
+}
+
+static void spl_init_sys(void)
+{
+	u32 r0 = 0;
+
+	writel(0xa5a5a500, 0xe6020004);
+	writel(0xa5a5a500, 0xe6030004);
+
+	asm volatile(
+		/* ICIALLU - Invalidate I$ to PoU */
+		"mcr	15, 0, %0, cr7, cr5, 0	\n"
+		/* BPIALL - Invalidate branch predictors */
+		"mcr	15, 0, %0, cr7, cr5, 6	\n"
+		/* Set SCTLR[IZ] */
+		"mrc	15, 0, %0, cr1, cr0, 0	\n"
+		"orr	%0, #0x1800		\n"
+		"mcr	15, 0, %0, cr1, cr0, 0	\n"
+		"isb	sy			\n"
+		:"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+	static const struct reg_config pfc_with_unlock[] = {
+		{ 0x0090, 0x00000000 },
+		{ 0x0094, 0x00000000 },
+		{ 0x0098, 0xc0000000 },
+		{ 0x0020, 0x00000000 },
+		{ 0x0024, 0x00000000 },
+		{ 0x0028, 0x00000000 },
+		{ 0x002c, 0x20000000 },
+		{ 0x0030, 0x00001249 },
+		{ 0x0034, 0x00000278 },
+		{ 0x0038, 0x00000841 },
+		{ 0x003c, 0x00000000 },
+		{ 0x0040, 0x00000000 },
+		{ 0x0044, 0x10000000 },
+		{ 0x0048, 0x00000001 },
+		{ 0x004c, 0x0004aab0 },
+		{ 0x0050, 0x37301b00 },
+		{ 0x0054, 0x00048da3 },
+		{ 0x0058, 0x089044a1 },
+		{ 0x005c, 0x2a3a55b4 },
+		{ 0x0160, 0x00000003 },
+		{ 0x0004, 0xffffffff },
+		{ 0x0008, 0x2aef3fff },
+		{ 0x000c, 0x3fffffff },
+		{ 0x0010, 0xff7fc07f },
+		{ 0x0014, 0x7f3ff3f8 },
+		{ 0x0018, 0x1cfdfff7 },
+	};
+
+	static const struct reg_config pfc_without_unlock[] = {
+		{ 0x0100, 0x1fffffff },
+		{ 0x0104, 0xffff0318 },
+		{ 0x0108, 0x387fffe1 },
+		{ 0x010c, 0x00803f80 },
+		{ 0x0110, 0x1520009f },
+		{ 0x0114, 0x00000000 },
+		{ 0x0118, 0x00000000 },
+	};
+
+	static const u32 pfc_base = 0xe6060000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+		writel(~pfc_with_unlock[i].val, pfc_base);
+		writel(pfc_with_unlock[i].val,
+		       pfc_base | pfc_with_unlock[i].off);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+		writel(pfc_without_unlock[i].val,
+		       pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+	static const u16 gpio_offs[] = {
+		0x1000, 0x3000, 0x4000, 0x5000
+	};
+
+	static const struct reg_config gpio_set[] = {
+		{ 0x4000, 0x00c00000 },
+		{ 0x5000, 0x63020000 },
+	};
+
+	static const struct reg_config gpio_clr[] = {
+		{ 0x1000, 0x00000000 },
+		{ 0x3000, 0x00000000 },
+		{ 0x4000, 0x00c00000 },
+		{ 0x5000, 0xe3020000 },
+	};
+
+	static const u32 gpio_base = 0xe6050000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+	static const struct reg_config lbsc_config[] = {
+		{ 0x00, 0x00000020 },
+		{ 0x08, 0x00002020 },
+		{ 0x30, 0x02150326 },
+		{ 0x38, 0x077f077f },
+	};
+
+	static const u16 lbsc_offs[] = {
+		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+	};
+
+	static const u32 lbsc_base = 0xfec00200;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+		writel(lbsc_config[i].val,
+		       lbsc_base | lbsc_config[i].off);
+		writel(lbsc_config[i].val,
+		       lbsc_base | (lbsc_config[i].off + 4));
+	}
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+		writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+	static const struct reg_config dbsc_config1[] = {
+		{ 0x0018, 0x21000000 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0018, 0x10000000 },
+		{ 0x0280, 0x0000a55a },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x80000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config4[] = {
+		{ 0x0290, 0x00000010 },
+		{ 0x02a0, 0xf004649b },
+		{ 0x0290, 0x0000000f },
+		{ 0x02a0, 0x00181ee4 },
+		{ 0x0290, 0x00000060 },
+		{ 0x02a0, 0x330657b2 },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000071 },
+		{ 0x0020, 0x00000007 },
+		{ 0x0024, 0x10030a02 },
+		{ 0x0030, 0x00000001 },
+		{ 0x00b0, 0x00000000 },
+		{ 0x0040, 0x0000000b },
+		{ 0x0044, 0x00000008 },
+		{ 0x0048, 0x00000000 },
+		{ 0x0050, 0x0000000b },
+		{ 0x0054, 0x000c000b },
+		{ 0x0058, 0x00000027 },
+		{ 0x005c, 0x0000001c },
+		{ 0x0060, 0x00000005 },
+		{ 0x0064, 0x00000018 },
+		{ 0x0068, 0x00000008 },
+		{ 0x006c, 0x0000000c },
+		{ 0x0070, 0x00000009 },
+		{ 0x0074, 0x00000012 },
+		{ 0x0078, 0x000000d0 },
+		{ 0x007c, 0x00140005 },
+		{ 0x0080, 0x00050004 },
+		{ 0x0084, 0x70233005 },
+		{ 0x0088, 0x000c0000 },
+		{ 0x008c, 0x00000300 },
+		{ 0x0090, 0x00000040 },
+		{ 0x0100, 0x00000001 },
+		{ 0x00c0, 0x00020001 },
+		{ 0x00c8, 0x20082008 },
+		{ 0x0380, 0x00020002 },
+		{ 0x0390, 0x0000000f },
+	};
+
+	static const struct reg_config dbsc_config5[] = {
+		{ 0x0244, 0x00000011 },
+		{ 0x0290, 0x00000006 },
+		{ 0x02a0, 0x0005c000 },
+		{ 0x0290, 0x00000003 },
+		{ 0x02a0, 0x0300c481 },
+		{ 0x0290, 0x00000023 },
+		{ 0x02a0, 0x00fdb6c0 },
+		{ 0x0290, 0x00000011 },
+		{ 0x02a0, 0x1000040b },
+		{ 0x0290, 0x00000012 },
+		{ 0x02a0, 0x9d5cbb66 },
+		{ 0x0290, 0x00000013 },
+		{ 0x02a0, 0x1a868300 },
+		{ 0x0290, 0x00000014 },
+		{ 0x02a0, 0x300214d8 },
+		{ 0x0290, 0x00000015 },
+		{ 0x02a0, 0x00000d70 },
+		{ 0x0290, 0x00000016 },
+		{ 0x02a0, 0x00000006 },
+		{ 0x0290, 0x00000017 },
+		{ 0x02a0, 0x00000018 },
+		{ 0x0290, 0x0000001a },
+		{ 0x02a0, 0x910035c7 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config6[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000181 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config7[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x0000fe01 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config8[] = {
+		{ 0x0304, 0x00000000 },
+		{ 0x00f4, 0x01004c20 },
+		{ 0x00f8, 0x014000aa },
+		{ 0x00e0, 0x00000140 },
+		{ 0x00e4, 0x00081860 },
+		{ 0x00e8, 0x00010000 },
+		{ 0x0014, 0x00000001 },
+		{ 0x0010, 0x00000001 },
+		{ 0x0280, 0x00000000 },
+	};
+
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+		writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+	dbsc_wait(0x240);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void spl_init_qspi(void)
+{
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	static const u32 qspi_base = 0xe6b10000;
+
+	writeb(0x08, qspi_base + 0x00);
+	writeb(0x00, qspi_base + 0x01);
+	writeb(0x06, qspi_base + 0x02);
+	writeb(0x01, qspi_base + 0x0a);
+	writeb(0x00, qspi_base + 0x0b);
+	writeb(0x00, qspi_base + 0x0c);
+	writeb(0x00, qspi_base + 0x0d);
+	writeb(0x00, qspi_base + 0x0e);
+
+	writew(0xe080, qspi_base + 0x10);
+
+	writeb(0xc0, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x08);
+	writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	/*
+	 * SD0 clock is set to 97.5MHz by default.
+	 * Set SD2 to the 97.5MHz as well.
+	 */
+	writel(SD_97500KHZ, SD2CKCR);
+
+	spl_init_sys();
+	spl_init_pfc();
+	spl_init_gpio();
+	spl_init_lbsc();
+	spl_init_dbsc();
+	spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	const u32 jtag_magic = 0x1337c0de;
+	const u32 load_magic = 0xb33fc0de;
+
+	/*
+	 * If JTAG probe sets special word at 0xe6300020, then it must
+	 * put U-Boot into RAM and SPL will start it from RAM.
+	 */
+	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+		printf("JTAG boot detected!\n");
+
+		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+			;
+
+		spl_boot_list[0] = BOOT_DEVICE_RAM;
+		spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+		return;
+	}
+
+	/* Boot from SPI NOR with YMODEM UART fallback. */
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+	spl_boot_list[1] = BOOT_DEVICE_UART;
+	spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/roms/u-boot/board/renesas/lager/qos.c b/roms/u-boot/board/renesas/lager/qos.c
new file mode 100644
index 000000000..f01ca2fac
--- /dev/null
+++ b/roms/u-boot/board/renesas/lager/qos.c
@@ -0,0 +1,2432 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/lager/qos.c
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.955 for ES1 and version 0.973 for ES2 */
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+/* QoS version 0.955 for ES1 */
+static void qos_init_es1(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	writel(0x80FF1C1E, &s3c->s3cadsplcr);
+	writel(0x1F060505, &s3c->s3crorr);
+	writel(0x1F020100, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00800080, &s3c_qos->s3cqos0);
+	writel(0x22000010, &s3c_qos->s3cqos1);
+	writel(0x22002200, &s3c_qos->s3cqos2);
+	writel(0x2F002200, &s3c_qos->s3cqos3);
+	writel(0x2F002F00, &s3c_qos->s3cqos4);
+	writel(0x22000010, &s3c_qos->s3cqos5);
+	writel(0x22002200, &s3c_qos->s3cqos6);
+	writel(0x2F002200, &s3c_qos->s3cqos7);
+	writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00800080, &s3c_qos->s3cqos0);
+	writel(0x22000010, &s3c_qos->s3cqos1);
+	writel(0x22002200, &s3c_qos->s3cqos2);
+	writel(0x2F002200, &s3c_qos->s3cqos3);
+	writel(0x2F002F00, &s3c_qos->s3cqos4);
+	writel(0x22000010, &s3c_qos->s3cqos5);
+	writel(0x22002200, &s3c_qos->s3cqos6);
+	writel(0x2F002200, &s3c_qos->s3cqos7);
+	writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x80918099, &s3c_qos->s3cqos0);
+	writel(0x20410010, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00810089, &s3c_qos->s3cqos0);
+	writel(0x20410001, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	writel(0x00200808, &s3c->s3carcr11);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000203, &qos_addr->dblgcnt);
+		writel(0x00002064, &qos_addr->dbtmval0);
+		writel(0x00002048, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00002019, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002019, &qos_addr->dbthres0);
+		writel(0x00002019, &qos_addr->dbthres1);
+		writel(0x00002019, &qos_addr->dbthres2);
+		writel(0x00000000, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000203, &qos_addr->dblgcnt);
+		writel(0x00002064, &qos_addr->dbtmval0);
+		writel(0x00002048, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00002019, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002019, &qos_addr->dbthres0);
+		writel(0x00002019, &qos_addr->dbthres1);
+		writel(0x00002019, &qos_addr->dbthres2);
+		writel(0x00000000, &qos_addr->dblgqon);
+	}
+
+	/* CCI-400 -QoS */
+	writel(0x20001000, CCI_400_MAXOT_1);
+	writel(0x20001000, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000013, &mxi->mxwtcr);
+	writel(0x00B800C0, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+	writel(0x00200000, &mxi->mxs3cracr);
+	writel(0x00200000, &mxi->mxs3cwacr);
+	writel(0x00200000, &mxi->mxaxiracr);
+	writel(0x00200000, &mxi->mxaxiwacr);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000D, &mxi_qos->du0);
+	writel(0x0000000D, &mxi_qos->du1);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002003, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000000, &axi_qos->qosqon);
+}
+
+#if defined(CONFIG_QOS_PRI_MEDIA)
+#define is_qos_pri_media()	1
+#else
+#define is_qos_pri_media()	0
+#endif
+
+#if defined(CONFIG_QOS_PRI_NORMAL)
+#define is_qos_pri_normal()	1
+#else
+#define is_qos_pri_normal()	0
+#endif
+
+#if defined(CONFIG_QOS_PRI_GFX)
+#define is_qos_pri_gfx()	1
+#else
+#define is_qos_pri_gfx()	0
+#endif
+
+/* QoS version 0.963 for ES2 */
+static void qos_init_es2(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	writel(0x80000000, &s3c->s3cadsplcr);
+	if (is_qos_pri_media()) {
+		writel(0x1F060302, &s3c->s3crorr);
+		writel(0x07070302, &s3c->s3cworr);
+	} else if (is_qos_pri_normal()) {
+		writel(0x1F060504, &s3c->s3crorr);
+		writel(0x07070503, &s3c->s3cworr);
+	} else if (is_qos_pri_gfx()) {
+		writel(0x1F060606, &s3c->s3crorr);
+		writel(0x07070606, &s3c->s3cworr);
+	}
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x80928092, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00828092, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20FA, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20FA, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	writel(0x00310808, &s3c->s3carcr11);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000201E, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000016, &mxi->mxwtcr);
+	writel(0x00B800C0, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000E, &mxi_qos->du0);
+	writel(0x0000000E, &mxi_qos->du1);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002299, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000206E, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020dc, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020dc, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+}
+
+void qos_init(void)
+{
+	if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X)
+		qos_init_es2();
+	else
+		qos_init_es1();
+}
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/roms/u-boot/board/renesas/lager/qos.h b/roms/u-boot/board/renesas/lager/qos.h
new file mode 100644
index 000000000..d92c43704
--- /dev/null
+++ b/roms/u-boot/board/renesas/lager/qos.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/roms/u-boot/board/renesas/porter/Kconfig b/roms/u-boot/board/renesas/porter/Kconfig
new file mode 100644
index 000000000..a6f621b73
--- /dev/null
+++ b/roms/u-boot/board/renesas/porter/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PORTER
+
+config SYS_BOARD
+	default "porter"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "porter"
+
+endif
diff --git a/roms/u-boot/board/renesas/porter/MAINTAINERS b/roms/u-boot/board/renesas/porter/MAINTAINERS
new file mode 100644
index 000000000..1dc6a1caf
--- /dev/null
+++ b/roms/u-boot/board/renesas/porter/MAINTAINERS
@@ -0,0 +1,6 @@
+PORTER BOARD
+M:	Cogent Embedded, Inc. <source@cogentembedded.com>
+S:	Maintained
+F:	board/renesas/porter/
+F:	include/configs/porter.h
+F:	configs/porter_defconfig
diff --git a/roms/u-boot/board/renesas/porter/Makefile b/roms/u-boot/board/renesas/porter/Makefile
new file mode 100644
index 000000000..c237ee5ec
--- /dev/null
+++ b/roms/u-boot/board/renesas/porter/Makefile
@@ -0,0 +1,14 @@
+#
+# board/renesas/porter/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+# Copyright (C) 2015 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= porter_spl.o
+else
+obj-y	:= porter.o qos.o
+endif
diff --git a/roms/u-boot/board/renesas/porter/porter.c b/roms/u-boot/board/renesas/porter/porter.c
new file mode 100644
index 000000000..b0f850525
--- /dev/null
+++ b/roms/u-boot/board/renesas/porter/porter.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/porter/porter.c
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <hang.h>
+#include <init.h>
+#include <malloc.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <env_internal.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <div64.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+	u32 stc;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* CPU frequency setting. Set to 1.5GHz */
+	stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+	/* QoS */
+	qos_init();
+}
+
+#define TMU0_MSTP125	BIT(25)
+
+#define SD2CKCR		0xE615026C
+#define SD_97500KHZ	0x7
+
+int board_early_init_f(void)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+	/*
+	 * SD0 clock is set to 97.5MHz by default.
+	 * Set SD2 to the 97.5MHz as well.
+	 */
+	writel(SD_97500KHZ, SD2CKCR);
+
+	return 0;
+}
+
+#define ETHERNET_PHY_RESET	176	/* GPIO 5 22 */
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Force ethernet PHY out of reset */
+	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+	gpio_direction_output(ETHERNET_PHY_RESET, 0);
+	mdelay(10);
+	gpio_direction_output(ETHERNET_PHY_RESET, 1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+/* porter has KSZ8041RNLI */
+#define PHY_CONTROL1		0x1E
+#define PHY_LED_MODE		0xC000
+#define PHY_LED_MODE_ACK	0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+	ret &= ~PHY_LED_MODE;
+	ret |= PHY_LED_MODE_ACK;
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	struct udevice *dev;
+	const u8 pmic_bus = 6;
+	const u8 pmic_addr = 0x5a;
+	u8 data;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+	if (ret)
+		hang();
+
+	ret = dm_i2c_read(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+
+	data |= BIT(1);
+
+	ret = dm_i2c_write(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	const u32 load_magic = 0xb33fc0de;
+
+	/* Block environment access if loaded using JTAG */
+	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+	    (op != ENVOP_INIT))
+		return ENVL_UNKNOWN;
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	return ENVL_SPI_FLASH;
+}
diff --git a/roms/u-boot/board/renesas/porter/porter_spl.c b/roms/u-boot/board/renesas/porter/porter_spl.c
new file mode 100644
index 000000000..8595770c3
--- /dev/null
+++ b/roms/u-boot/board/renesas/porter/porter_spl.c
@@ -0,0 +1,493 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/porter/porter_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125	BIT(25)
+#define SCIF0_MSTP721	BIT(21)
+#define QSPI_MSTP917	BIT(17)
+
+#define SD2CKCR		0xE615026C
+#define SD_97500KHZ	0x7
+
+struct reg_config {
+	u16	off;
+	u32	val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+
+	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+		;
+
+	while (!(readl(dbsc3_1_base + reg) & BIT(0)))
+		;
+}
+
+static void spl_init_sys(void)
+{
+	u32 r0 = 0;
+
+	writel(0xa5a5a500, 0xe6020004);
+	writel(0xa5a5a500, 0xe6030004);
+
+	asm volatile(
+		/* ICIALLU - Invalidate I$ to PoU */
+		"mcr	15, 0, %0, cr7, cr5, 0	\n"
+		/* BPIALL - Invalidate branch predictors */
+		"mcr	15, 0, %0, cr7, cr5, 6	\n"
+		/* Set SCTLR[IZ] */
+		"mrc	15, 0, %0, cr1, cr0, 0	\n"
+		"orr	%0, #0x1800		\n"
+		"mcr	15, 0, %0, cr1, cr0, 0	\n"
+		"isb	sy			\n"
+		:"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+	static const struct reg_config pfc_with_unlock[] = {
+		{ 0x0090, 0x60000000 },
+		{ 0x0094, 0x60000000 },
+		{ 0x0098, 0x00800200 },
+		{ 0x009c, 0x00000000 },
+		{ 0x0020, 0x00000000 },
+		{ 0x0024, 0x00000000 },
+		{ 0x0028, 0x000244c8 },
+		{ 0x002c, 0x00000000 },
+		{ 0x0030, 0x00002400 },
+		{ 0x0034, 0x01520000 },
+		{ 0x0038, 0x00724003 },
+		{ 0x003c, 0x00000000 },
+		{ 0x0040, 0x00000000 },
+		{ 0x0044, 0x00000000 },
+		{ 0x0048, 0x00000000 },
+		{ 0x004c, 0x00000000 },
+		{ 0x0050, 0x00000000 },
+		{ 0x0054, 0x00000000 },
+		{ 0x0058, 0x00000000 },
+		{ 0x005c, 0x00000000 },
+		{ 0x0160, 0x00000000 },
+		{ 0x0004, 0xffffffff },
+		{ 0x0008, 0x00ec3fff },
+		{ 0x000c, 0x3bc001e7 },
+		{ 0x0010, 0x5bffffff },
+		{ 0x0014, 0x1ffffffb },
+		{ 0x0018, 0x01bffff0 },
+		{ 0x001c, 0xcf7fffff },
+		{ 0x0074, 0x0381fc00 },
+	};
+
+	static const struct reg_config pfc_without_unlock[] = {
+		{ 0x0100, 0xffffffdf },
+		{ 0x0104, 0xc883c3ff },
+		{ 0x0108, 0x1201f3c9 },
+		{ 0x010c, 0x00000000 },
+		{ 0x0110, 0xffffeb04 },
+		{ 0x0114, 0xc003ffff },
+		{ 0x0118, 0x0800000f },
+		{ 0x011c, 0x00187ff0 },
+	};
+
+	static const u32 pfc_base = 0xe6060000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+		writel(~pfc_with_unlock[i].val, pfc_base);
+		writel(pfc_with_unlock[i].val,
+		       pfc_base | pfc_with_unlock[i].off);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+		writel(pfc_without_unlock[i].val,
+		       pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+	static const u16 gpio_offs[] = {
+		0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
+	};
+
+	static const struct reg_config gpio_set[] = {
+		{ 0x2000, 0x04381000 },
+		{ 0x5000, 0x00000000 },
+		{ 0x5800, 0x000e0000 },
+	};
+
+	static const struct reg_config gpio_clr[] = {
+		{ 0x1000, 0x00000000 },
+		{ 0x2000, 0x04381010 },
+		{ 0x3000, 0x00000000 },
+		{ 0x4000, 0x00000000 },
+		{ 0x5000, 0x00400000 },
+		{ 0x5400, 0x00000000 },
+		{ 0x5800, 0x000e0380 },
+	};
+
+	static const u32 gpio_base = 0xe6050000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+	static const struct reg_config lbsc_config[] = {
+		{ 0x00, 0x00000020 },
+		{ 0x08, 0x00002020 },
+		{ 0x30, 0x2a103320 },
+		{ 0x38, 0xff70ff70 },
+	};
+
+	static const u16 lbsc_offs[] = {
+		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+	};
+
+	static const u32 lbsc_base = 0xfec00200;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+		writel(lbsc_config[i].val,
+		       lbsc_base | lbsc_config[i].off);
+		writel(lbsc_config[i].val,
+		       lbsc_base | (lbsc_config[i].off + 4));
+	}
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+		writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+	static const struct reg_config dbsc_config1[] = {
+		{ 0x0280, 0x0000a55a },
+		{ 0x4000, 0x0000a55a },
+		{ 0x4008, 0x00000001 },
+		{ 0x0018, 0x21000000 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0018, 0x10000000 },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x80000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config2[] = {
+		{ 0x0290, 0x00000006 },
+		{ 0x02a0, 0x0001c000 },
+	};
+
+	static const struct reg_config dbsc_config3r0d0[] = {
+		{ 0x0290, 0x0000000f },
+		{ 0x02a0, 0x00181885 },
+		{ 0x0290, 0x00000070 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x00000080 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x00000090 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x000000a0 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x000000b0 },
+		{ 0x02a0, 0x7c000880 },
+		{ 0x0290, 0x000000c0 },
+		{ 0x02a0, 0x7c000880 },
+		{ 0x0290, 0x000000d0 },
+		{ 0x02a0, 0x7c000880 },
+		{ 0x0290, 0x000000e0 },
+		{ 0x02a0, 0x7c000880 },
+	};
+	static const struct reg_config dbsc_config3r0d1[] = {
+		{ 0x0290, 0x0000000f },
+		{ 0x02a0, 0x00181885 },
+		{ 0x0290, 0x00000070 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x00000080 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x00000090 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x000000a0 },
+		{ 0x02a0, 0x7c000887 },
+	};
+
+	static const struct reg_config dbsc_config3r2[] = {
+		{ 0x0290, 0x0000000f },
+		{ 0x02a0, 0x00181224 },
+	};
+
+	static const struct reg_config dbsc_config4[] = {
+		{ 0x0290, 0x00000010 },
+		{ 0x02a0, 0xf004649b },
+		{ 0x0290, 0x00000061 },
+		{ 0x02a0, 0x0000006d },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000073 },
+		{ 0x0020, 0x00000007 },
+		{ 0x0024, 0x0f030a02 },
+		{ 0x0030, 0x00000001 },
+		{ 0x00b0, 0x00000000 },
+		{ 0x0040, 0x0000000b },
+		{ 0x0044, 0x00000008 },
+		{ 0x0048, 0x00000000 },
+		{ 0x0050, 0x0000000b },
+		{ 0x0054, 0x000c000b },
+		{ 0x0058, 0x00000027 },
+		{ 0x005c, 0x0000001c },
+		{ 0x0060, 0x00000006 },
+		{ 0x0064, 0x00000020 },
+		{ 0x0068, 0x00000008 },
+		{ 0x006c, 0x0000000c },
+		{ 0x0070, 0x00000009 },
+		{ 0x0074, 0x00000012 },
+		{ 0x0078, 0x000000d0 },
+		{ 0x007c, 0x00140005 },
+		{ 0x0080, 0x00050004 },
+		{ 0x0084, 0x70233005 },
+		{ 0x0088, 0x000c0000 },
+		{ 0x008c, 0x00000200 },
+		{ 0x0090, 0x00000040 },
+		{ 0x0100, 0x00000001 },
+		{ 0x00c0, 0x00020001 },
+		{ 0x00c8, 0x20042004 },
+		{ 0x0380, 0x00020002 },
+		{ 0x0390, 0x0000001f },
+	};
+
+	static const struct reg_config dbsc_config5[] = {
+		{ 0x0244, 0x00000011 },
+		{ 0x0290, 0x00000003 },
+		{ 0x02a0, 0x0300c561 },
+		{ 0x0290, 0x00000023 },
+		{ 0x02a0, 0x00fcdb60 },
+		{ 0x0290, 0x00000011 },
+		{ 0x02a0, 0x1000040b },
+		{ 0x0290, 0x00000012 },
+		{ 0x02a0, 0x9d9cbb66 },
+		{ 0x0290, 0x00000013 },
+		{ 0x02a0, 0x1a868400 },
+		{ 0x0290, 0x00000014 },
+		{ 0x02a0, 0x300214d8 },
+		{ 0x0290, 0x00000015 },
+		{ 0x02a0, 0x00000d70 },
+		{ 0x0290, 0x00000016 },
+		{ 0x02a0, 0x00000006 },
+		{ 0x0290, 0x00000017 },
+		{ 0x02a0, 0x00000018 },
+		{ 0x0290, 0x0000001a },
+		{ 0x02a0, 0x910035c7 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config6[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000181 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config7[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x0000fe01 },
+		{ 0x0304, 0x00000000 },
+		{ 0x00f4, 0x01004c20 },
+		{ 0x00f8, 0x014a00b9 },
+		{ 0x00e0, 0x00000140 },
+		{ 0x00e4, 0x00081860 },
+		{ 0x00e8, 0x00010000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config8[] = {
+		{ 0x0014, 0x00000001 },
+		{ 0x0290, 0x00000010 },
+		{ 0x02a0, 0xf00464db },
+		{ 0x4008, 0x00000000 },
+		{ 0x4000, 0x00000000 },
+		{ 0x0010, 0x00000001 },
+		{ 0x0280, 0x00000000 },
+	};
+
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+	static const u32 prr_base = 0xff000044;
+	const u16 prr_rev = readl(prr_base) & 0x7fff;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
+		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+		writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
+		writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+		writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
+	}
+
+	if (prr_rev == 0x4700) {
+		for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
+			writel(dbsc_config3r0d0[i].val,
+				dbsc3_0_base | dbsc_config3r0d0[i].off);
+		}
+		for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
+			writel(dbsc_config3r0d1[i].val,
+				dbsc3_1_base | dbsc_config3r0d1[i].off);
+		}
+	} else if (prr_rev != 0x4710) {
+		for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
+			writel(dbsc_config3r2[i].val,
+				dbsc3_0_base | dbsc_config3r2[i].off);
+			writel(dbsc_config3r2[i].val,
+				dbsc3_1_base | dbsc_config3r2[i].off);
+		}
+	}
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
+		writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+		writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
+	}
+
+	dbsc_wait(0x240);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
+		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+		writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
+		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+		writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
+		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+		writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
+		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+		writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
+	}
+
+}
+
+static void spl_init_qspi(void)
+{
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	static const u32 qspi_base = 0xe6b10000;
+
+	writeb(0x08, qspi_base + 0x00);
+	writeb(0x00, qspi_base + 0x01);
+	writeb(0x06, qspi_base + 0x02);
+	writeb(0x01, qspi_base + 0x0a);
+	writeb(0x00, qspi_base + 0x0b);
+	writeb(0x00, qspi_base + 0x0c);
+	writeb(0x00, qspi_base + 0x0d);
+	writeb(0x00, qspi_base + 0x0e);
+
+	writew(0xe080, qspi_base + 0x10);
+
+	writeb(0xc0, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x08);
+	writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	/*
+	 * SD0 clock is set to 97.5MHz by default.
+	 * Set SD2 to the 97.5MHz as well.
+	 */
+	writel(SD_97500KHZ, SD2CKCR);
+
+	spl_init_sys();
+	spl_init_pfc();
+	spl_init_gpio();
+	spl_init_lbsc();
+	spl_init_dbsc();
+	spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	const u32 jtag_magic = 0x1337c0de;
+	const u32 load_magic = 0xb33fc0de;
+
+	/*
+	 * If JTAG probe sets special word at 0xe6300020, then it must
+	 * put U-Boot into RAM and SPL will start it from RAM.
+	 */
+	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+		printf("JTAG boot detected!\n");
+
+		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+			;
+
+		spl_boot_list[0] = BOOT_DEVICE_RAM;
+		spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+		return;
+	}
+
+	/* Boot from SPI NOR with YMODEM UART fallback. */
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+	spl_boot_list[1] = BOOT_DEVICE_UART;
+	spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/roms/u-boot/board/renesas/porter/qos.c b/roms/u-boot/board/renesas/porter/qos.c
new file mode 100644
index 000000000..bca54f7f7
--- /dev/null
+++ b/roms/u-boot/board/renesas/porter/qos.c
@@ -0,0 +1,1311 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/porter/qos.c
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.240 for ES1 and version 0.334 for ES2 */
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_1_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_1_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_1_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_1_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_1_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_1_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_1_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_1_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_1_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_1_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_1_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_1_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_1_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_1_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_1_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_1_QOS_R15_BASE,
+};
+
+static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_1_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_1_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_1_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_1_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_1_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_1_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_1_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_1_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_1_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_1_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_1_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_1_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_1_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_1_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_1_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_1_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+	writel(0x20042004, DBSC3_1_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	if (IS_R8A7791_ES2()) {
+		/* Linear All mode */
+		/* writel(0x00000000, &s3c->s3cadsplcr); */
+		/* Linear Linear 0x7000 to 0x7800 mode */
+		writel(0x00BF1B0C, &s3c->s3cadsplcr);
+		/* Split Linear 0x6800 t 0x7000 mode */
+		/* writel(0x00DF1B0C, &s3c->s3cadsplcr); */
+		/* Ssplit All mode */
+		/* writel(0x00FF1B0C, &s3c->s3cadsplcr); */
+		writel(0x1F0B0908, &s3c->s3crorr);
+		writel(0x1F0C0A08, &s3c->s3cworr);
+	} else {
+		writel(0x00FF1B1D, &s3c->s3cadsplcr);
+		writel(0x1F0D0C0C, &s3c->s3crorr);
+		writel(0x1F0D0C0A, &s3c->s3cworr);
+	}
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20FA, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20FA, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000201E, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC1 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000201E, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC1 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* CCI-400 -QoS */
+	writel(0x20001000, CCI_400_MAXOT_1);
+	writel(0x20001000, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000013, &mxi->mxwtcr);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000E, &mxi_qos->du0);
+	writel(0x0000000D, &mxi_qos->du1);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002299, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000206E, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	if (IS_R8A7791_ES2())
+		writel(0x000020EB, &axi_qos->qosctset0);
+	else
+		writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	if (IS_R8A7791_ES2())
+		writel(0x000020EB, &axi_qos->qosctset0);
+	else
+		writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	if (IS_R8A7791_ES2())
+		writel(0x000020EB, &axi_qos->qosctset0);
+	else
+		writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	if (IS_R8A7791_ES2())
+		writel(0x00001FF0, &axi_qos->qosctset0);
+	else
+		writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	if (IS_R8A7791_ES2())
+		writel(0x00002001, &axi_qos->qosthres2);
+	else
+		writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000003, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000003, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000003, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000003, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000003, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	if (IS_R8A7791_ES2())
+		writel(0x00000000, &axi_qos->qosconf);
+	else
+		writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	if (IS_R8A7791_ES2()) {
+		writel(0x00000001, &axi_qos->qosthres0);
+		writel(0x00000001, &axi_qos->qosthres1);
+	} else {
+		writel(0x00002064, &axi_qos->qosthres0);
+		writel(0x00002004, &axi_qos->qosthres1);
+	}
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+}
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/roms/u-boot/board/renesas/porter/qos.h b/roms/u-boot/board/renesas/porter/qos.h
new file mode 100644
index 000000000..2cdbfd90a
--- /dev/null
+++ b/roms/u-boot/board/renesas/porter/qos.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/roms/u-boot/board/renesas/r2dplus/Kconfig b/roms/u-boot/board/renesas/r2dplus/Kconfig
new file mode 100644
index 000000000..6597870a8
--- /dev/null
+++ b/roms/u-boot/board/renesas/r2dplus/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_R2DPLUS
+
+config SYS_BOARD
+	default "r2dplus"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "r2dplus"
+
+endif
diff --git a/roms/u-boot/board/renesas/r2dplus/MAINTAINERS b/roms/u-boot/board/renesas/r2dplus/MAINTAINERS
new file mode 100644
index 000000000..58877c509
--- /dev/null
+++ b/roms/u-boot/board/renesas/r2dplus/MAINTAINERS
@@ -0,0 +1,7 @@
+R2DPLUS BOARD
+M:	Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S:	Maintained
+F:	board/renesas/r2dplus/
+F:	include/configs/r2dplus.h
+F:	configs/r2dplus_defconfig
diff --git a/roms/u-boot/board/renesas/r2dplus/Makefile b/roms/u-boot/board/renesas/r2dplus/Makefile
new file mode 100644
index 000000000..51d8d244d
--- /dev/null
+++ b/roms/u-boot/board/renesas/r2dplus/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+obj-y	:= r2dplus.o
+extra-y	+= lowlevel_init.o
diff --git a/roms/u-boot/board/renesas/r2dplus/lowlevel_init.S b/roms/u-boot/board/renesas/r2dplus/lowlevel_init.S
new file mode 100644
index 000000000..33f6e0782
--- /dev/null
+++ b/roms/u-boot/board/renesas/r2dplus/lowlevel_init.S
@@ -0,0 +1,117 @@
+/*
+ * modified from SH-IPL+g (init-r0p751rlc0011rl.S)
+ * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
+ * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+*/
+
+#include <config.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+	.global lowlevel_init
+	.text
+	.align	2
+
+lowlevel_init:
+
+	write32	CCR_A, CCR_D_D
+
+	write32	MMUCR_A, MMUCR_D
+
+	write32	BCR1_A, BCR1_D
+
+	write16	BCR2_A, BCR2_D
+
+	write16	BCR3_A, BCR3_D
+
+	write32	BCR4_A, BCR4_D
+
+	write32	WCR1_A, WCR1_D
+
+	write32	WCR2_A, WCR2_D
+
+	write32	WCR3_A, WCR3_D
+
+	write16	PCR_A, PCR_D
+
+	write16	LED_A, LED_D
+
+	write32	MCR_A, MCR_D1
+
+	write16	RTCNT_A, RTCNT_D
+
+	write16	RTCOR_A, RTCOR_D
+
+	write16	RFCR_A, RFCR_D
+
+	write16	RTCSR_A, RTCSR_D
+
+	write8	SDMR3_A, SDMR3_D0
+
+	/* Wait DRAM refresh 30 times */
+	mov.l	RFCR_A, r1
+	mov	#30, r3
+1:
+	mov.w	@r1, r0
+	extu.w	r0, r2
+	cmp/hi	r3, r2
+	bf	1b
+
+	write32	MCR_A, MCR_D2
+
+	write8	SDMR3_A, SDMR3_D1
+
+	write32	IRLMASK_A, IRLMASK_D
+
+	write32	CCR_A, CCR_D_E
+
+	rts
+	nop
+
+	.align	2
+CCR_A:		.long	CCR		/* Cache Control Register */
+CCR_D_D:	.long	0x0808		/* Flush the cache, disable */
+CCR_D_E:	.long	0x8000090B
+
+FRQCR_A:	.long	FRQCR		/* FRQCR Address */
+FRQCR_D:	.long	0x00000e0a	/* 03/07/15 modify */
+BCR1_A:		.long	BCR1		/* BCR1 Address */
+BCR1_D:		.long	0x00180008
+BCR2_A:		.long	BCR2		/* BCR2 Address */
+BCR2_D:		.long	0xabe8
+BCR3_A:		.long	BCR3		/* BCR3 Address */
+BCR3_D:		.long	0x0000
+BCR4_A:		.long	BCR4		/* BCR4 Address */
+BCR4_D:		.long	0x00000010
+WCR1_A:		.long	WCR1		/* WCR1 Address */
+WCR1_D:		.long	0x33343333
+WCR2_A:		.long	WCR2		/* WCR2 Address */
+WCR2_D:		.long	0xcff86fbf
+WCR3_A:		.long	WCR3		/* WCR3 Address */
+WCR3_D:		.long	0x07777707
+LED_A:		.long	0x04000036	/* LED Address */
+LED_D:		.long	0xFF		/* LED Data */
+RTCNT_A:	.long	RTCNT		/* RTCNT Address */
+RTCNT_D:	.word	0xA500		/* RTCNT Write Code A5h Data 00h */
+.align 2
+RTCOR_A:	.long	RTCOR		/* RTCOR Address */
+RTCOR_D:	.word	0xA534		/* RTCOR Write Code */
+.align 2
+RTCSR_A:	.long	RTCSR		/* RTCSR Address */
+RTCSR_D:	.word	0xA510		/* RTCSR Write Code */
+.align 2
+SDMR3_A:	.long	0xFF9400CC	/* SDMR3 Address */
+SDMR3_D0:	.long	0x55
+SDMR3_D1:	.long	0x00
+MCR_A:		.long	MCR		/* MCR Address */
+MCR_D1:		.long	0x081901F4	/* MRSET:'0' */
+MCR_D2:		.long	0x481901F4	/* MRSET:'1' */
+RFCR_A:		.long	RFCR		/* RFCR Address */
+RFCR_D:		.long	0xA400		/* RFCR Write Code A4h Data 00h */
+PCR_A:		.long	PCR		/* PCR Address */
+PCR_D:		.long	0x0000
+MMUCR_A:	.long	MMUCR		/* MMUCCR Address */
+MMUCR_D:	.long	0x00000000	/* MMUCCR Data */
+IRLMASK_A:	.long	0xA4000000	/* IRLMASK Address */
+IRLMASK_D:	.long	0x00000000	/* IRLMASK Data */
diff --git a/roms/u-boot/board/renesas/r2dplus/r2dplus.c b/roms/u-boot/board/renesas/r2dplus/r2dplus.c
new file mode 100644
index 000000000..4b9959a43
--- /dev/null
+++ b/roms/u-boot/board/renesas/r2dplus/r2dplus.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+int checkboard(void)
+{
+	puts("BOARD: Renesas Solutions R2D Plus\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+#define FPGA_BASE		0xA4000000
+#define FPGA_CFCTL		(FPGA_BASE + 0x04)
+#define CFCTL_EN		(0x432)
+#define FPGA_CFPOW		(FPGA_BASE + 0x06)
+#define CFPOW_ON		(0x02)
+#define FPGA_CFCDINTCLR	(FPGA_BASE + 0x2A)
+#define CFCDINTCLR_EN	(0x01)
+
+void ide_set_reset(int idereset)
+{
+	/* if reset = 1 IDE reset will be asserted */
+	if (idereset) {
+		outw(CFCTL_EN, FPGA_CFCTL);	/* CF enable */
+		outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
+		outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
+	}
+}
+
+#ifndef CONFIG_DM_ETH
+int board_eth_init(struct bd_info *bis)
+{
+	return pci_eth_init(bis);
+}
+#endif
diff --git a/roms/u-boot/board/renesas/rcar-common/common.c b/roms/u-boot/board/renesas/rcar-common/common.c
new file mode 100644
index 000000000..0352d341e
--- /dev/null
+++ b/roms/u-boot/board/renesas/rcar-common/common.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/rcar-common/common.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <dm/uclass-internal.h>
+#include <asm/arch/rmobile.h>
+#include <linux/libfdt.h>
+
+#ifdef CONFIG_RCAR_GEN3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* If the firmware passed a device tree use it for U-Boot DRAM setup. */
+extern u64 rcar_atf_boot_args[];
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+	void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+	if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
+		fdt_overlay_apply_node((void *)fdt_blob, 0, atf_fdt_blob, 0);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node)
+{
+	struct fdt_resource first_mem_res, curr_mem_res;
+	int curr_mem_reg, first_mem_reg = 0;
+	int ret;
+
+	for (;;) {
+		ret = fdt_get_resource(blob, first_mem_node, "reg",
+				       first_mem_reg++, &first_mem_res);
+		if (ret) /* No more entries, no overlap found */
+			return 0;
+
+		curr_mem_reg = 0;
+		for (;;) {
+			ret = fdt_get_resource(blob, curr_mem_node, "reg",
+					       curr_mem_reg++, &curr_mem_res);
+			if (ret) /* No more entries, check next tuple */
+				break;
+
+			if (curr_mem_res.end < first_mem_res.start)
+				continue;
+
+			if (curr_mem_res.start >= first_mem_res.end)
+				continue;
+
+			printf("Overlap found: 0x%llx..0x%llx / 0x%llx..0x%llx\n",
+				first_mem_res.start, first_mem_res.end,
+				curr_mem_res.start, curr_mem_res.end);
+
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	/*
+	 * Scrub duplicate /memory@* node entries here. Some R-Car DTs might
+	 * contain multiple /memory@* nodes, however fdt_fixup_memory_banks()
+	 * either generates single /memory node or updates the first /memory
+	 * node. Any remaining memory nodes are thus potential duplicates.
+	 *
+	 * However, it is not possible to delete all the memory nodes right
+	 * away, since some of those might not be DRAM memory nodes, but some
+	 * sort of other memory. Thus, delete only the memory nodes which are
+	 * in the R-Car3 DBSC ranges.
+	 */
+	int mem = 0, first_mem_node = 0;
+
+	for (;;) {
+		mem = fdt_node_offset_by_prop_value(blob, mem,
+						    "device_type", "memory", 7);
+		if (mem < 0)
+			break;
+		if (!fdtdec_get_is_enabled(blob, mem))
+			continue;
+
+		/* First memory node, patched by U-Boot */
+		if (!first_mem_node) {
+			first_mem_node = mem;
+			continue;
+		}
+
+		/* Check the remaining nodes and delete duplicates */
+		if (!is_mem_overlap(blob, first_mem_node, mem))
+			continue;
+
+		/* Delete duplicate node, start again */
+		fdt_del_node(blob, mem);
+		first_mem_node = 0;
+		mem = 0;
+	}
+
+	return 0;
+}
+#endif
+#endif
diff --git a/roms/u-boot/board/renesas/rcar-common/gen3-spl.c b/roms/u-boot/board/renesas/rcar-common/gen3-spl.c
new file mode 100644
index 000000000..b02a946a2
--- /dev/null
+++ b/roms/u-boot/board/renesas/rcar-common/gen3-spl.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R-Car Gen3 recovery SPL
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/io.h>
+#include <spl.h>
+#include <linux/bitops.h>
+
+#define RCAR_CNTC_BASE	0xE6080000
+#define CNTCR_EN	BIT(0)
+
+void board_init_f(ulong dummy)
+{
+	writel(CNTCR_EN, RCAR_CNTC_BASE);
+	timer_init();
+}
+
+void spl_board_init(void)
+{
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_UART;
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	debug("image entry point: 0x%lx\n", spl_image->entry_point);
+	if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) {
+		typedef void (*image_entry_arg_t)(int, int, int, int)
+			__attribute__ ((noreturn));
+		image_entry_arg_t image_entry =
+			(image_entry_arg_t)(uintptr_t) spl_image->entry_point;
+		image_entry(IH_MAGIC, CONFIG_SPL_TEXT_BASE, 0, 0);
+	} else {
+		typedef void __noreturn (*image_entry_noargs_t)(void);
+		image_entry_noargs_t image_entry =
+			(image_entry_noargs_t)spl_image->entry_point;
+		image_entry();
+	}
+}
+
+void s_init(void)
+{
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/roms/u-boot/board/renesas/salvator-x/Kconfig b/roms/u-boot/board/renesas/salvator-x/Kconfig
new file mode 100644
index 000000000..ed4c479f7
--- /dev/null
+++ b/roms/u-boot/board/renesas/salvator-x/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SALVATOR_X
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "salvator-x"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "salvator-x"
+
+endif
diff --git a/roms/u-boot/board/renesas/salvator-x/MAINTAINERS b/roms/u-boot/board/renesas/salvator-x/MAINTAINERS
new file mode 100644
index 000000000..7335bc3cd
--- /dev/null
+++ b/roms/u-boot/board/renesas/salvator-x/MAINTAINERS
@@ -0,0 +1,6 @@
+SALVATOR_X BOARD
+M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S:	Maintained
+F:	board/renesas/salvator-x/
+F:	include/configs/salvator-x.h
+F:	configs/rcar3_salvator-x_defconfig
diff --git a/roms/u-boot/board/renesas/salvator-x/Makefile b/roms/u-boot/board/renesas/salvator-x/Makefile
new file mode 100644
index 000000000..95258079e
--- /dev/null
+++ b/roms/u-boot/board/renesas/salvator-x/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/salvator-x/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= ../rcar-common/gen3-spl.o
+else
+obj-y	:= salvator-x.o ../rcar-common/common.o
+endif
diff --git a/roms/u-boot/board/renesas/salvator-x/salvator-x.c b/roms/u-boot/board/renesas/salvator-x/salvator-x.c
new file mode 100644
index 000000000..071076a33
--- /dev/null
+++ b/roms/u-boot/board/renesas/salvator-x/salvator-x.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/salvator-x/salvator-x.c
+ *     This file is Salvator-X/Salvator-XS board support.
+ *
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
+ * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <image.h>
+#include <init.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DVFS_MSTP926		BIT(26)
+#define HSUSB_MSTP704		BIT(4)	/* HSUSB */
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+	/* DVFS for reset */
+	mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
+#endif
+	return 0;
+}
+
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS			0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
+#define HSUSB_REG_UGCTRL2		0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL	0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	/* USB1 pull-up */
+	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+	/* Configure the HSUSB block */
+	mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
+	/* Choice USB0SEL */
+	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+	/* low power status */
+	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
+	return 0;
+}
+
+#define RST_BASE	0xE6160000
+#define RST_CA57RESCNT	(RST_BASE + 0x40)
+#define RST_CA53RESCNT	(RST_BASE + 0x44)
+#define RST_RSTOUTCR	(RST_BASE + 0x58)
+#define RST_CODE	0xA5A5000F
+
+void reset_cpu(void)
+{
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+	i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
+#else
+	/* only CA57 ? */
+	writel(RST_CODE, RST_CA57RESCNT);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* PRR driver is not available yet */
+	u32 cpu_type = rmobile_get_cpu_type();
+
+	if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
+	    !strcmp(name, "r8a77950-salvator-x-u-boot"))
+		return 0;
+
+	if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
+	    !strcmp(name, "r8a77960-salvator-x-u-boot"))
+		return 0;
+
+	if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
+	    !strcmp(name, "r8a77965-salvator-x-u-boot"))
+		return 0;
+
+	return -1;
+}
+#endif
diff --git a/roms/u-boot/board/renesas/silk/Kconfig b/roms/u-boot/board/renesas/silk/Kconfig
new file mode 100644
index 000000000..07aee0e50
--- /dev/null
+++ b/roms/u-boot/board/renesas/silk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SILK
+
+config SYS_BOARD
+	default "silk"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "silk"
+
+endif
diff --git a/roms/u-boot/board/renesas/silk/MAINTAINERS b/roms/u-boot/board/renesas/silk/MAINTAINERS
new file mode 100644
index 000000000..b566ccfbd
--- /dev/null
+++ b/roms/u-boot/board/renesas/silk/MAINTAINERS
@@ -0,0 +1,6 @@
+SILK BOARD
+M:	Cogent Embedded, Inc. <source@cogentembedded.com>
+S:	Maintained
+F:	board/renesas/silk/
+F:	include/configs/silk.h
+F:	configs/silk_defconfig
diff --git a/roms/u-boot/board/renesas/silk/Makefile b/roms/u-boot/board/renesas/silk/Makefile
new file mode 100644
index 000000000..b5c3ad8d9
--- /dev/null
+++ b/roms/u-boot/board/renesas/silk/Makefile
@@ -0,0 +1,14 @@
+#
+# board/renesas/silk/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+# Copyright (C) 2015 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= silk_spl.o
+else
+obj-y	:= silk.o qos.o
+endif
diff --git a/roms/u-boot/board/renesas/silk/qos.c b/roms/u-boot/board/renesas/silk/qos.c
new file mode 100644
index 000000000..43a298986
--- /dev/null
+++ b/roms/u-boot/board/renesas/silk/qos.c
@@ -0,0 +1,950 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/silk/qos.c
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
+/* QoS version 0.11 */
+
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	writel(0x1F0D0B0A, &s3c->s3crorr);
+	writel(0x1F0D0B09, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x80928092, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20FA, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20FA, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x0000207D, &qos_addr->dbtmval0);
+		writel(0x00002053, &qos_addr->dbtmval1);
+		writel(0x0000202A, &qos_addr->dbtmval2);
+		writel(0x00001FBD, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002064, &qos_addr->dbthres0);
+		writel(0x0000203E, &qos_addr->dbthres1);
+		writel(0x00002019, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x0000207D, &qos_addr->dbtmval0);
+		writel(0x00002053, &qos_addr->dbtmval1);
+		writel(0x00002043, &qos_addr->dbtmval2);
+		writel(0x00002030, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002064, &qos_addr->dbthres0);
+		writel(0x0000203E, &qos_addr->dbthres1);
+		writel(0x00002031, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* CCI-400 -QoS */
+	writel(0x20000800, CCI_400_MAXOT_1);
+	writel(0x20000800, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000013, &mxi->mxwtcr);
+	writel(0x00780080, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000E, &mxi_qos->du0);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000206E, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+}
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/roms/u-boot/board/renesas/silk/qos.h b/roms/u-boot/board/renesas/silk/qos.h
new file mode 100644
index 000000000..2cdbfd90a
--- /dev/null
+++ b/roms/u-boot/board/renesas/silk/qos.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/roms/u-boot/board/renesas/silk/silk.c b/roms/u-boot/board/renesas/silk/silk.c
new file mode 100644
index 000000000..4558070af
--- /dev/null
+++ b/roms/u-boot/board/renesas/silk/silk.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/silk/silk.c
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <hang.h>
+#include <init.h>
+#include <malloc.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <env_internal.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <div64.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS */
+	qos_init();
+}
+
+#define TMU0_MSTP125	BIT(25)
+#define MMC0_MSTP315	BIT(15)
+
+#define SD1CKCR		0xE6150078
+#define SD_97500KHZ	0x7
+
+int board_early_init_f(void)
+{
+	/* TMU */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+	/* Set SD1 to the 97.5MHz */
+	writel(SD_97500KHZ, SD1CKCR);
+
+	return 0;
+}
+
+#define ETHERNET_PHY_RESET	56	/* GPIO 1 24 */
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Force ethernet PHY out of reset */
+	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+	gpio_direction_output(ETHERNET_PHY_RESET, 0);
+	mdelay(20);
+	gpio_direction_output(ETHERNET_PHY_RESET, 1);
+	udelay(1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+/* porter has KSZ8041RNLI */
+#define PHY_CONTROL1		0x1E
+#define PHY_LED_MODE		0xC000
+#define PHY_LED_MODE_ACK	0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+	ret &= ~PHY_LED_MODE;
+	ret |= PHY_LED_MODE_ACK;
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	struct udevice *dev;
+	const u8 pmic_bus = 1;
+	const u8 pmic_addr = 0x5a;
+	u8 data;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+	if (ret)
+		hang();
+
+	ret = dm_i2c_read(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+
+	data |= BIT(1);
+
+	ret = dm_i2c_write(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	const u32 load_magic = 0xb33fc0de;
+
+	/* Block environment access if loaded using JTAG */
+	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+	    (op != ENVOP_INIT))
+		return ENVL_UNKNOWN;
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	return ENVL_SPI_FLASH;
+}
diff --git a/roms/u-boot/board/renesas/silk/silk_spl.c b/roms/u-boot/board/renesas/silk/silk_spl.c
new file mode 100644
index 000000000..afb9f85ff
--- /dev/null
+++ b/roms/u-boot/board/renesas/silk/silk_spl.c
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/silk/silk_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125	BIT(25)
+#define SCIF2_MSTP719	BIT(19)
+#define QSPI_MSTP917	BIT(17)
+
+#define SD1CKCR		0xE6150078
+#define SD_97500KHZ	0x7
+
+struct reg_config {
+	u16	off;
+	u32	val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+		;
+}
+
+static void spl_init_sys(void)
+{
+	u32 r0 = 0;
+
+	writel(0xa5a5a500, 0xe6020004);
+	writel(0xa5a5a500, 0xe6030004);
+
+	asm volatile(
+		/* ICIALLU - Invalidate I$ to PoU */
+		"mcr	15, 0, %0, cr7, cr5, 0	\n"
+		/* BPIALL - Invalidate branch predictors */
+		"mcr	15, 0, %0, cr7, cr5, 6	\n"
+		/* Set SCTLR[IZ] */
+		"mrc	15, 0, %0, cr1, cr0, 0	\n"
+		"orr	%0, #0x1800		\n"
+		"mcr	15, 0, %0, cr1, cr0, 0	\n"
+		"isb	sy			\n"
+		:"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+	static const struct reg_config pfc_with_unlock[] = {
+		{ 0x0090, 0x00018040 },
+		{ 0x0094, 0x00000000 },
+		{ 0x0098, 0x00000000 },
+		{ 0x0020, 0x94000000 },
+		{ 0x0024, 0x00000006 },
+		{ 0x0028, 0x40000000 },
+		{ 0x002c, 0x00000155 },
+		{ 0x0030, 0x00000002 },
+		{ 0x0034, 0x00000000 },
+		{ 0x0038, 0x00000000 },
+		{ 0x003c, 0x00000000 },
+		{ 0x0040, 0x60000000 },
+		{ 0x0044, 0x36dab6db },
+		{ 0x0048, 0x926da012 },
+		{ 0x004c, 0x0008c383 },
+		{ 0x0050, 0x00000000 },
+		{ 0x0054, 0x00000140 },
+		{ 0x0004, 0xffffffff },
+		{ 0x0008, 0x00ec3fff },
+		{ 0x000c, 0x5bffffff },
+		{ 0x0010, 0x01bfe1ff },
+		{ 0x0014, 0x5bffffff },
+		{ 0x0018, 0x0f4b200f },
+		{ 0x001c, 0x03ffffff },
+	};
+
+	static const struct reg_config pfc_without_unlock[] = {
+		{ 0x0100, 0x00000000 },
+		{ 0x0104, 0x4203fdf0 },
+		{ 0x0108, 0x00000000 },
+		{ 0x010c, 0x159007ff },
+		{ 0x0110, 0x80000000 },
+		{ 0x0114, 0x00de481f },
+		{ 0x0118, 0x00000000 },
+	};
+
+	static const struct reg_config pfc_with_unlock2[] = {
+		{ 0x0060, 0xffffffff },
+		{ 0x0064, 0xfffff000 },
+		{ 0x0068, 0x55555500 },
+		{ 0x006c, 0xffffff00 },
+		{ 0x0070, 0x00000000 },
+	};
+
+	static const u32 pfc_base = 0xe6060000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+		writel(~pfc_with_unlock[i].val, pfc_base);
+		writel(pfc_with_unlock[i].val,
+		       pfc_base | pfc_with_unlock[i].off);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+		writel(pfc_without_unlock[i].val,
+		       pfc_base | pfc_without_unlock[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
+		writel(~pfc_with_unlock2[i].val, pfc_base);
+		writel(pfc_with_unlock2[i].val,
+		       pfc_base | pfc_with_unlock2[i].off);
+	}
+}
+
+static void spl_init_gpio(void)
+{
+	static const u16 gpio_offs[] = {
+		0x1000, 0x2000, 0x3000, 0x4000
+	};
+
+	static const struct reg_config gpio_set[] = {
+		{ 0x2000, 0x24000000 },
+		{ 0x4000, 0xa4000000 },
+		{ 0x5000, 0x0084c000 },
+	};
+
+	static const struct reg_config gpio_clr[] = {
+		{ 0x1000, 0x01000000 },
+		{ 0x2000, 0x24000000 },
+		{ 0x3000, 0x00000000 },
+		{ 0x4000, 0xa4000000 },
+		{ 0x5000, 0x00044380 },
+	};
+
+	static const u32 gpio_base = 0xe6050000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x20 | gpio_offs[i]);
+	writel(BIT(23), gpio_base | 0x5020);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x00 | gpio_offs[i]);
+	writel(BIT(23), gpio_base | 0x5000);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+	static const struct reg_config lbsc_config[] = {
+		{ 0x00, 0x00000020 },
+		{ 0x08, 0x00002020 },
+		{ 0x30, 0x2a103320 },
+		{ 0x38, 0xff70ff70 },
+	};
+
+	static const u16 lbsc_offs[] = {
+		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
+	};
+
+	static const u32 lbsc_base = 0xfec00200;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+		writel(lbsc_config[i].val,
+		       lbsc_base | lbsc_config[i].off);
+		writel(lbsc_config[i].val,
+		       lbsc_base | (lbsc_config[i].off + 4));
+	}
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+		writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+	static const struct reg_config dbsc_config1[] = {
+		{ 0x0018, 0x21000000 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0018, 0x10000000 },
+		{ 0x0280, 0x0000a55a },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x80000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config2[] = {
+		{ 0x0290, 0x00000006 },
+		{ 0x02a0, 0x0005c000 },
+	};
+
+	static const struct reg_config dbsc_config3r2[] = {
+		{ 0x0290, 0x0000000f },
+		{ 0x02a0, 0x00181224 },
+	};
+
+	static const struct reg_config dbsc_config4[] = {
+		{ 0x0290, 0x00000010 },
+		{ 0x02a0, 0xf004649b },
+		{ 0x0290, 0x00000061 },
+		{ 0x02a0, 0x0000006d },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000073 },
+		{ 0x0020, 0x00000007 },
+		{ 0x0024, 0x0f030a02 },
+		{ 0x0030, 0x00000001 },
+		{ 0x00b0, 0x00000000 },
+		{ 0x0040, 0x00000009 },
+		{ 0x0044, 0x00000007 },
+		{ 0x0048, 0x00000000 },
+		{ 0x0050, 0x00000009 },
+		{ 0x0054, 0x000a0009 },
+		{ 0x0058, 0x00000021 },
+		{ 0x005c, 0x00000018 },
+		{ 0x0060, 0x00000005 },
+		{ 0x0064, 0x00000020 },
+		{ 0x0068, 0x00000007 },
+		{ 0x006c, 0x0000000a },
+		{ 0x0070, 0x00000009 },
+		{ 0x0074, 0x00000010 },
+		{ 0x0078, 0x000000ae },
+		{ 0x007c, 0x00140005 },
+		{ 0x0080, 0x00050004 },
+		{ 0x0084, 0x50213005 },
+		{ 0x0088, 0x000c0000 },
+		{ 0x008c, 0x00000200 },
+		{ 0x0090, 0x00000040 },
+		{ 0x0100, 0x00000001 },
+		{ 0x00c0, 0x00020001 },
+		{ 0x00c8, 0x20042004 },
+		{ 0x0380, 0x00020003 },
+		{ 0x0390, 0x0000001f },
+	};
+
+	static const struct reg_config dbsc_config5[] = {
+		{ 0x0244, 0x00000011 },
+		{ 0x0290, 0x00000003 },
+		{ 0x02a0, 0x0300c4e1 },
+		{ 0x0290, 0x00000023 },
+		{ 0x02a0, 0x00fcb6d0 },
+		{ 0x0290, 0x00000011 },
+		{ 0x02a0, 0x1000040b },
+		{ 0x0290, 0x00000012 },
+		{ 0x02a0, 0x85589955 },
+		{ 0x0290, 0x00000013 },
+		{ 0x02a0, 0x1a852400 },
+		{ 0x0290, 0x00000014 },
+		{ 0x02a0, 0x300210b4 },
+		{ 0x0290, 0x00000015 },
+		{ 0x02a0, 0x00000b50 },
+		{ 0x0290, 0x00000016 },
+		{ 0x02a0, 0x00000006 },
+		{ 0x0290, 0x00000017 },
+		{ 0x02a0, 0x00000010 },
+		{ 0x0290, 0x0000001a },
+		{ 0x02a0, 0x910035c7 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config6[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000181 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config7[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x0000fe01 },
+		{ 0x0304, 0x00000000 },
+		{ 0x00f4, 0x01004c20 },
+		{ 0x00f8, 0x012c00be },
+		{ 0x00e0, 0x00000140 },
+		{ 0x00e4, 0x00081450 },
+		{ 0x00e8, 0x00010000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config8[] = {
+		{ 0x0014, 0x00000001 },
+		{ 0x0290, 0x00000010 },
+		{ 0x02a0, 0xf00464db },
+		{ 0x0010, 0x00000001 },
+		{ 0x0280, 0x00000000 },
+	};
+
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
+		writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
+		writel(dbsc_config3r2[i].val,
+			dbsc3_0_base | dbsc_config3r2[i].off);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+		writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+	dbsc_wait(0x240);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void spl_init_qspi(void)
+{
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	static const u32 qspi_base = 0xe6b10000;
+
+	writeb(0x08, qspi_base + 0x00);
+	writeb(0x00, qspi_base + 0x01);
+	writeb(0x06, qspi_base + 0x02);
+	writeb(0x01, qspi_base + 0x0a);
+	writeb(0x00, qspi_base + 0x0b);
+	writeb(0x00, qspi_base + 0x0c);
+	writeb(0x00, qspi_base + 0x0d);
+	writeb(0x00, qspi_base + 0x0e);
+
+	writew(0xe080, qspi_base + 0x10);
+
+	writeb(0xc0, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x08);
+	writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
+
+	/* Set SD1 to the 97.5MHz */
+	writel(SD_97500KHZ, SD1CKCR);
+
+	spl_init_sys();
+	spl_init_pfc();
+	spl_init_gpio();
+	spl_init_lbsc();
+	spl_init_dbsc();
+	spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	const u32 jtag_magic = 0x1337c0de;
+	const u32 load_magic = 0xb33fc0de;
+
+	/*
+	 * If JTAG probe sets special word at 0xe6300020, then it must
+	 * put U-Boot into RAM and SPL will start it from RAM.
+	 */
+	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+		printf("JTAG boot detected!\n");
+
+		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+			;
+
+		spl_boot_list[0] = BOOT_DEVICE_RAM;
+		spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+		return;
+	}
+
+	/* Boot from SPI NOR with YMODEM UART fallback. */
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+	spl_boot_list[1] = BOOT_DEVICE_UART;
+	spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/roms/u-boot/board/renesas/stout/Kconfig b/roms/u-boot/board/renesas/stout/Kconfig
new file mode 100644
index 000000000..cbbc6dd9e
--- /dev/null
+++ b/roms/u-boot/board/renesas/stout/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_STOUT
+
+config SYS_BOARD
+	default "stout"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "stout"
+
+endif
diff --git a/roms/u-boot/board/renesas/stout/MAINTAINERS b/roms/u-boot/board/renesas/stout/MAINTAINERS
new file mode 100644
index 000000000..b7098e795
--- /dev/null
+++ b/roms/u-boot/board/renesas/stout/MAINTAINERS
@@ -0,0 +1,6 @@
+STOUT BOARD
+M:	Cogent Embedded, Inc. <source@cogentembedded.com>
+S:	Maintained
+F:	board/renesas/stout/
+F:	include/configs/stout.h
+F:	configs/stout_defconfig
diff --git a/roms/u-boot/board/renesas/stout/Makefile b/roms/u-boot/board/renesas/stout/Makefile
new file mode 100644
index 000000000..b8875bb7b
--- /dev/null
+++ b/roms/u-boot/board/renesas/stout/Makefile
@@ -0,0 +1,15 @@
+#
+# board/renesas/stout/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Europe GmbH
+# Copyright (C) 2015 Renesas Electronics Corporation
+# Copyright (C) 2015 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= stout_spl.o
+else
+obj-y	:= stout.o cpld.o qos.o
+endif
diff --git a/roms/u-boot/board/renesas/stout/cpld.c b/roms/u-boot/board/renesas/stout/cpld.c
new file mode 100644
index 000000000..ac8048c81
--- /dev/null
+++ b/roms/u-boot/board/renesas/stout/cpld.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Stout board CPLD access support
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe GmbH
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include "cpld.h"
+
+#define SCLK			(92 + 24)
+#define SSTBZ			(92 + 25)
+#define MOSI			(92 + 26)
+#define MISO			(92 + 27)
+
+#define CPLD_ADDR_MODE		0x00 /* RW */
+#define CPLD_ADDR_MUX		0x01 /* RW */
+#define CPLD_ADDR_HDMI		0x02 /* RW */
+#define CPLD_ADDR_DIPSW		0x08 /* R */
+#define CPLD_ADDR_RESET		0x80 /* RW */
+#define CPLD_ADDR_VERSION	0xFF /* R */
+
+static u32 cpld_read(u8 addr)
+{
+	int i;
+	u32 data = 0;
+
+	for (i = 0; i < 8; i++) {
+		gpio_set_value(MOSI, addr & 0x80); /* MSB first */
+		gpio_set_value(SCLK, 1);
+		addr <<= 1;
+		gpio_set_value(SCLK, 0);
+	}
+
+	gpio_set_value(MOSI, 0); /* READ */
+	gpio_set_value(SSTBZ, 0);
+	gpio_set_value(SCLK, 1);
+	gpio_set_value(SCLK, 0);
+	gpio_set_value(SSTBZ, 1);
+
+	for (i = 0; i < 32; i++) {
+		gpio_set_value(SCLK, 1);
+		data <<= 1;
+		data |= gpio_get_value(MISO); /* MSB first */
+		gpio_set_value(SCLK, 0);
+	}
+
+	return data;
+}
+
+static void cpld_write(u8 addr, u32 data)
+{
+	int i;
+
+	for (i = 0; i < 32; i++) {
+		gpio_set_value(MOSI, data & (1 << 31)); /* MSB first */
+		gpio_set_value(SCLK, 1);
+		data <<= 1;
+		gpio_set_value(SCLK, 0);
+	}
+
+	for (i = 0; i < 8; i++) {
+		gpio_set_value(MOSI, addr & 0x80); /* MSB first */
+		gpio_set_value(SCLK, 1);
+		addr <<= 1;
+		gpio_set_value(SCLK, 0);
+	}
+
+	gpio_set_value(MOSI, 1); /* WRITE */
+	gpio_set_value(SSTBZ, 0);
+	gpio_set_value(SCLK, 1);
+	gpio_set_value(SCLK, 0);
+	gpio_set_value(SSTBZ, 1);
+}
+
+/* LSI pin pull-up control */
+#define PUPR3		0xe606010C
+#define PUPR3_SD3_DAT1	(1 << 27)
+
+void cpld_init(void)
+{
+	u32 val;
+
+	/* PULL-UP on MISO line */
+	val = readl(PUPR3);
+	val |= PUPR3_SD3_DAT1;
+	writel(val, PUPR3);
+
+	gpio_request(SCLK, "SCLK");
+	gpio_request(SSTBZ, "SSTBZ");
+	gpio_request(MOSI, "MOSI");
+	gpio_request(MISO, "MISO");
+
+	gpio_direction_output(SCLK, 0);
+	gpio_direction_output(SSTBZ, 1);
+	gpio_direction_output(MOSI, 0);
+	gpio_direction_input(MISO);
+
+	/* dummy read */
+	cpld_read(CPLD_ADDR_VERSION);
+
+	printf("CPLD version:              0x%08x\n",
+	       cpld_read(CPLD_ADDR_VERSION));
+	printf("H2 Mode setting (MD0..28): 0x%08x\n",
+	       cpld_read(CPLD_ADDR_MODE));
+	printf("Multiplexer settings:      0x%08x\n",
+	       cpld_read(CPLD_ADDR_MUX));
+	printf("HDMI setting:              0x%08x\n",
+	       cpld_read(CPLD_ADDR_HDMI));
+	printf("DIPSW (SW3):               0x%08x\n",
+	       cpld_read(CPLD_ADDR_DIPSW));
+
+#ifdef CONFIG_SH_SDHI
+	/* switch MUX to SD0 */
+	val = cpld_read(CPLD_ADDR_MUX);
+	val &= ~MUX_MSK_SD0;
+	val |= MUX_VAL_SD0;
+	cpld_write(CPLD_ADDR_MUX, val);
+#endif
+}
+
+static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc,
+		   char *const argv[])
+{
+	u32 addr, val;
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
+	      addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_HDMI ||
+	      addr == CPLD_ADDR_DIPSW || addr == CPLD_ADDR_RESET)) {
+		printf("cpld invalid addr\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (argc == 3 && strcmp(argv[1], "read") == 0) {
+		printf("0x%x\n", cpld_read(addr));
+	} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+		val = simple_strtoul(argv[3], NULL, 16);
+		if (addr == CPLD_ADDR_MUX) {
+			/* never mask SCIFA0 console */
+			val &= ~MUX_MSK_SCIFA0_USB;
+			val |= MUX_VAL_SCIFA0_USB;
+		}
+		cpld_write(addr, val);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	cpld, 4, 1, do_cpld,
+	"CPLD access",
+	"read addr\n"
+	"cpld write addr val\n"
+);
+
+void reset_cpu(void)
+{
+	cpld_write(CPLD_ADDR_RESET, 1);
+}
diff --git a/roms/u-boot/board/renesas/stout/cpld.h b/roms/u-boot/board/renesas/stout/cpld.h
new file mode 100644
index 000000000..acbeefe74
--- /dev/null
+++ b/roms/u-boot/board/renesas/stout/cpld.h
@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Stout board CPLD definition
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe GmbH
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ */
+
+#ifndef _CPLD_H_
+#define _CPLD_H_
+
+/* power-up behaviour */
+#define MODE_MSK_FREE_RUN		0x00000001
+#define MODE_VAL_FREE_RUN		0x00000000
+#define MODE_MSK_STEP_UP		0x00000001
+#define MODE_VAL_STEP_UP		0x00000000
+
+/* boot source */
+#define MODE_MSK_BOOT_SQPI_16KB_FAST	0x0000000E
+#define MODE_VAL_BOOT_SQPI_16KB_FAST	0x00000004
+#define MODE_MSK_BOOT_SQPI_16KB_SLOW	0x0000000E
+#define MODE_VAL_BOOT_SQPI_16KB_SLOW	0x00000008
+#define MODE_MSK_BOOT_SQPI_4KB_SLOW	0x0000000E
+#define MODE_VAL_BOOT_SQPI_4KB_SLOW	0x0000000C
+
+/* booting CPU */
+#define MODE_MSK_BOOT_CA15		0x000000C0
+#define MODE_VAL_BOOT_CA15		0x00000000
+#define MODE_MSK_BOOT_CA7		0x000000C0
+#define MODE_VAL_BOOT_CA7		0x00000040
+#define MODE_MSK_BOOT_SH4		0x000000C0
+#define MODE_VAL_BOOT_SH4		0x000000C0
+
+/* JTAG connection */
+#define MODE_MSK_JTAG_CORESIGHT		0xC0301C00
+#define MODE_VAL_JTAG_CORESIGHT		0x00200000
+#define MODE_MSK_JTAG_SH4		0xC0301C00
+#define MODE_VAL_JTAG_SH4		0x00300000
+
+/* DDR3 (PLL) speed */
+#define MODE_MSK_DDR3_1600		0x00080000
+#define MODE_VAL_DDR3_1600		0x00000000
+#define MODE_MSK_DDR3_1333		0x00080000
+#define MODE_VAL_DDR3_1333		0x00080000
+
+/* ComboPhy0 mode */
+#define MODE_MSK_PHY0_SATA0		0x01000000
+#define MODE_VAL_PHY0_SATA0		0x00000000
+#define MODE_MSK_PHY0_PCIE		0x01000000
+#define MODE_VAL_PHY0_PCIE		0x01000000
+
+/* ComboPhy1 mode */
+#define MODE_MSK_PHY1_SATA1		0x00800000
+#define MODE_VAL_PHY1_SATA1		0x00000000
+#define MODE_MSK_PHY1_USB3		0x00800000
+#define MODE_VAL_PHY1_USB3		0x00800000
+
+/*
+ * Illegal multiplexer combinations.
+ *    MUX                      Conflicts
+ *    name                  with any one of
+ * VIN0_BT656            VIN0_full, SD2
+ * VIN0_full             VIN0_BT656, SD2, AVB, VIN2_(all)
+ * VIN1_BT656            VIN1_(others), SD0
+ * VIN1_10bit            VIN1_(others), SD0, VIN3_with*, I2C1
+ * VIN1_12bit            VIN1_(others), SD0, VIN3_with*, I2C1, SCIFA0_(all)
+ * VIN2_BT656            VIN0_full, VIN2_(others), AVB,
+ * VIN2_withSYNC         VIN0_full, VIN2_(others), AVB, I2C1, SCIFA0_(all),
+ *                       VIN3_with*
+ * VIN2_withFIELD        VIN0_full, VIN2_(others), AVB, SQPI_(all)
+ * VIN2_withSYNCandFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all), I2C1,
+ *                       SCIFA0_(all), VIN3_with*
+ * VIN3_BT656            VIN3_(others), IRQ3
+ * VIN3_withFIELD        VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC,
+ *                       VIN2_withSYNCandFIELD, VIN1_10bit
+ * VIN3_withSYNCandFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC,
+ *                       VIN2_withSYNCandFIELD, VIN1_10bit, I2C1
+ * AVB                   VIN0_full, VIN2_(all)
+ * QSPI_ONBOARD          VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_COMEXPRESS
+ * QSPI_COMEXPRESS       VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_ONBOARD
+ * I2C1                  VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD,
+ *                       VIN3_withSYNCandFIELD
+ * IRQ3                  VIN3_(all)
+ * SCIFA0_USB            VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD,
+ *                       SCIFA0_COMEXPRESS
+ * SCIFA0_COMEXPRESS     VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD,
+ *                       SCIFA0_USB
+ * SCIFA2                PWM210
+ * ETH_ONBOARD           ETH_COMEXPRESS
+ * ETH_COMEXPRESS        ETH_ONBOARD
+ * SD0                   VIN1_(all)
+ * SD2                   VIN0_(all)
+ * PWM210                SCIFA2
+ */
+
+/* connected to COM Express connector and CN6 for camera, BT656 only */
+#define MUX_MSK_VIN0_BT656		0x00001001
+#define MUX_VAL_VIN0_BT656		0x00000000
+/* connected to COM Express connector and CN6 for camera, all modes */
+#define MUX_MSK_VIN0_full		0x00001007
+#define MUX_VAL_VIN0_full		0x00000002
+/* connected to COM Express connector, BT656 only */
+#define MUX_MSK_VIN1_BT656		0x00000801
+#define MUX_VAL_VIN1_BT656		0x00000800
+/* connected to COM Express connector, all 10-bit modes */
+#define MUX_MSK_VIN1_10bit		0x00000821
+#define MUX_VAL_VIN1_10bit		0x00000800
+/* connected to COM Express connector, all 12-bit modes */
+#define MUX_MSK_VIN1_12bit		0x000008A1
+#define MUX_VAL_VIN1_12bit		0x00000880
+/* connected to COM Express connector, BT656 only */
+#define MUX_MSK_VIN2_BT656		0x00000007
+#define MUX_VAL_VIN2_BT656		0x00000006
+/* connected to COM Express connector, modes with sync signals */
+#define MUX_MSK_VIN2_withSYNC		0x000000A7
+#define MUX_VAL_VIN2_withSYNC		0x00000086
+/* connected to COM Express connector, modes with field, clken signals */
+#define MUX_MSK_VIN2_withFIELD		0x0000000F
+#define MUX_VAL_VIN2_withFIELD		0x0000000E
+/* connected to COM Express connector, modes with sync, field, clken signals */
+#define MUX_MSK_VIN2_withSYNCandFIELD	0x000000AF
+#define MUX_VAL_VIN2_withSYNCandFIELD	0x0000008E
+/* connected to COM Express connector, BT656 only */
+#define MUX_MSK_VIN3_BT656		0x00000101
+#define MUX_VAL_VIN3_BT656		0x00000100
+/* connected to COM Express connector, modes with field, clken signals */
+#define MUX_MSK_VIN3_withFIELD		0x00000121
+#define MUX_VAL_VIN3_withFIELD		0x00000120
+/* connected to COM Express connector, modes with sync, field, clken signals */
+#define MUX_MSK_VIN3_withSYNCandFIELD	0x00000161
+#define MUX_VAL_VIN3_withSYNCandFIELD	0x00000120
+/* connected to COM Express connector (RGMII) */
+#define MUX_MSK_AVB			0x00000003
+#define MUX_VAL_AVB			0x00000000
+/* connected to on-board QSPI flash */
+#define MUX_MSK_QSPI_ONBOARD		0x00000019
+#define MUX_VAL_QSPI_ONBOARD		0x00000000
+/* connected to COM Express connector */
+#define MUX_MSK_QSPI_COMEXPRESS		0x00000019
+#define MUX_VAL_QSPI_COMEXPRESS		0x00000010
+/* connected to COM Express connector and PMIC */
+#define MUX_MSK_I2C1			0x00000061
+#define MUX_VAL_I2C1			0x00000060
+/* connected to HDMI driver */
+#define MUX_MSK_IRQ3			0x00000101
+#define MUX_VAL_IRQ3			0x00000000
+/* connected to USB/FTDI */
+#define MUX_MSK_SCIFA0_USB		0x00004081
+#define MUX_VAL_SCIFA0_USB		0x00004000
+/* connected to COM Express connector */
+#define MUX_MSK_SCIFA0_COMEXPRESS	0x00004081
+#define MUX_VAL_SCIFA0_COMEXPRESS	0x00000000
+/* connected to COM Express connector */
+#define MUX_MSK_SCIFA2			0x00002001
+#define MUX_VAL_SCIFA2			0x00000000
+/* connected to on-board 10/100 Phy */
+#define MUX_MSK_ETH_ONBOARD		0x00000600
+#define MUX_VAL_ETH_ONBOARD		0x00000000
+/* connected to COM Express connector (RMII) */
+#define MUX_MSK_ETH_COMEXPRESS		0x00000600
+#define MUX_VAL_ETH_COMEXPRESS		0x00000400
+/* connected to on-board MicroSD slot */
+#define MUX_MSK_SD0			0x00000801
+#define MUX_VAL_SD0			0x00000000
+/* connected to COM Express connector */
+#define MUX_MSK_SD2			0x00001001
+#define MUX_VAL_SD2			0x00001000
+/* connected to COM Express connector */
+#define MUX_MSK_PWM210			0x00002001
+#define MUX_VAL_PWM210			0x00002000
+
+#define HDMI_MSK			0x07
+#define HDMI_OFF			0x00
+#define HDMI_ONBOARD			0x07
+#define HDMI_COMEXPRESS			0x05
+#define HDMI_ONBOARD_NODDC		0x03
+#define HDMI_COMEXPRESS_NODDC		0x01
+
+void cpld_init(void);
+
+#endif	/* _CPLD_H_ */
diff --git a/roms/u-boot/board/renesas/stout/qos.c b/roms/u-boot/board/renesas/stout/qos.c
new file mode 100644
index 000000000..c2f0b8538
--- /dev/null
+++ b/roms/u-boot/board/renesas/stout/qos.c
@@ -0,0 +1,2434 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/stout/qos.c
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe GmbH
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.955 for ES1 and version 0.973 for ES2 */
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+/* QoS version 0.955 for ES1 */
+static void qos_init_es1(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	writel(0x80FF1C1E, &s3c->s3cadsplcr);
+	writel(0x1F060505, &s3c->s3crorr);
+	writel(0x1F020100, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00800080, &s3c_qos->s3cqos0);
+	writel(0x22000010, &s3c_qos->s3cqos1);
+	writel(0x22002200, &s3c_qos->s3cqos2);
+	writel(0x2F002200, &s3c_qos->s3cqos3);
+	writel(0x2F002F00, &s3c_qos->s3cqos4);
+	writel(0x22000010, &s3c_qos->s3cqos5);
+	writel(0x22002200, &s3c_qos->s3cqos6);
+	writel(0x2F002200, &s3c_qos->s3cqos7);
+	writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00800080, &s3c_qos->s3cqos0);
+	writel(0x22000010, &s3c_qos->s3cqos1);
+	writel(0x22002200, &s3c_qos->s3cqos2);
+	writel(0x2F002200, &s3c_qos->s3cqos3);
+	writel(0x2F002F00, &s3c_qos->s3cqos4);
+	writel(0x22000010, &s3c_qos->s3cqos5);
+	writel(0x22002200, &s3c_qos->s3cqos6);
+	writel(0x2F002200, &s3c_qos->s3cqos7);
+	writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x80918099, &s3c_qos->s3cqos0);
+	writel(0x20410010, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00810089, &s3c_qos->s3cqos0);
+	writel(0x20410001, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	writel(0x00200808, &s3c->s3carcr11);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000203, &qos_addr->dblgcnt);
+		writel(0x00002064, &qos_addr->dbtmval0);
+		writel(0x00002048, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00002019, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002019, &qos_addr->dbthres0);
+		writel(0x00002019, &qos_addr->dbthres1);
+		writel(0x00002019, &qos_addr->dbthres2);
+		writel(0x00000000, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000203, &qos_addr->dblgcnt);
+		writel(0x00002064, &qos_addr->dbtmval0);
+		writel(0x00002048, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00002019, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002019, &qos_addr->dbthres0);
+		writel(0x00002019, &qos_addr->dbthres1);
+		writel(0x00002019, &qos_addr->dbthres2);
+		writel(0x00000000, &qos_addr->dblgqon);
+	}
+
+	/* CCI-400 -QoS */
+	writel(0x20001000, CCI_400_MAXOT_1);
+	writel(0x20001000, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000013, &mxi->mxwtcr);
+	writel(0x00B800C0, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+	writel(0x00200000, &mxi->mxs3cracr);
+	writel(0x00200000, &mxi->mxs3cwacr);
+	writel(0x00200000, &mxi->mxaxiracr);
+	writel(0x00200000, &mxi->mxaxiwacr);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000D, &mxi_qos->du0);
+	writel(0x0000000D, &mxi_qos->du1);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002003, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000000, &axi_qos->qosqon);
+}
+
+#if defined(CONFIG_QOS_PRI_MEDIA)
+#define is_qos_pri_media()	1
+#else
+#define is_qos_pri_media()	0
+#endif
+
+#if defined(CONFIG_QOS_PRI_NORMAL)
+#define is_qos_pri_normal()	1
+#else
+#define is_qos_pri_normal()	0
+#endif
+
+#if defined(CONFIG_QOS_PRI_GFX)
+#define is_qos_pri_gfx()	1
+#else
+#define is_qos_pri_gfx()	0
+#endif
+
+/* QoS version 0.963 for ES2 */
+static void qos_init_es2(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	writel(0x80000000, &s3c->s3cadsplcr);
+	if (is_qos_pri_media()) {
+		writel(0x1F060302, &s3c->s3crorr);
+		writel(0x07070302, &s3c->s3cworr);
+	} else if (is_qos_pri_normal()) {
+		writel(0x1F060504, &s3c->s3crorr);
+		writel(0x07070503, &s3c->s3cworr);
+	} else if (is_qos_pri_gfx()) {
+		writel(0x1F060606, &s3c->s3crorr);
+		writel(0x07070606, &s3c->s3cworr);
+	}
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos3);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	if (is_qos_pri_media())
+		writel(0x20AA2300, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_normal())
+		writel(0x20AA2200, &s3c_qos->s3cqos7);
+	else if (is_qos_pri_gfx())
+		writel(0x20AA2100, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x80928092, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00828092, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20FA, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20FA, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	writel(0x00310808, &s3c->s3carcr11);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000201E, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000016, &mxi->mxwtcr);
+	writel(0x00B800C0, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000E, &mxi_qos->du0);
+	writel(0x0000000E, &mxi_qos->du1);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002299, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000206E, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020dc, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020dc, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002004, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+}
+
+void qos_init(void)
+{
+	if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X)
+		qos_init_es2();
+	else
+		qos_init_es1();
+}
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/roms/u-boot/board/renesas/stout/qos.h b/roms/u-boot/board/renesas/stout/qos.h
new file mode 100644
index 000000000..d98915ede
--- /dev/null
+++ b/roms/u-boot/board/renesas/stout/qos.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Renesas Electronics Europe GmbH
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/roms/u-boot/board/renesas/stout/stout.c b/roms/u-boot/board/renesas/stout/stout.c
new file mode 100644
index 000000000..3fdf936dd
--- /dev/null
+++ b/roms/u-boot/board/renesas/stout/stout.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/stout/stout.c
+ *     This file is Stout board support.
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe GmbH
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <env_internal.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <mmc.h>
+#include "qos.h"
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* CPU frequency setting. Set to 1.4GHz */
+	if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
+		u32 stat = 0;
+		u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
+			<< PLL0_STC_BIT;
+		clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+		do {
+			stat = readl(PLLECR) & PLL0ST;
+		} while (stat == 0x0);
+	}
+
+	/* QoS(Quality-of-Service) Init */
+	qos_init();
+}
+
+#define TMU0_MSTP125	BIT(25)
+
+#define SD2CKCR		0xE6150078
+#define SD2_97500KHZ	0x7
+
+int board_early_init_f(void)
+{
+	/* TMU0 */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+	/*
+	 * SD0 clock is set to 97.5MHz by default.
+	 * Set SD2 to the 97.5MHz as well.
+	 */
+	writel(SD2_97500KHZ, SD2CKCR);
+
+	return 0;
+}
+
+#define ETHERNET_PHY_RESET	123	/* GPIO 3 31 */
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	cpld_init();
+
+	/* Force ethernet PHY out of reset */
+	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+	gpio_direction_output(ETHERNET_PHY_RESET, 0);
+	mdelay(20);
+	gpio_direction_output(ETHERNET_PHY_RESET, 1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+/* Stout has KSZ8041NL/RNL */
+#define PHY_CONTROL1		0x1E
+#define PHY_LED_MODE		0xC000
+#define PHY_LED_MODE_ACK	0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+	ret &= ~PHY_LED_MODE;
+	ret |= PHY_LED_MODE_ACK;
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+	return 0;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	const u32 load_magic = 0xb33fc0de;
+
+	/* Block environment access if loaded using JTAG */
+	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+	    (op != ENVOP_INIT))
+		return ENVL_UNKNOWN;
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	return ENVL_SPI_FLASH;
+}
diff --git a/roms/u-boot/board/renesas/stout/stout_spl.c b/roms/u-boot/board/renesas/stout/stout_spl.c
new file mode 100644
index 000000000..c37c05571
--- /dev/null
+++ b/roms/u-boot/board/renesas/stout/stout_spl.c
@@ -0,0 +1,479 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/stout/stout_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125	BIT(25)
+#define SCIFA0_MSTP204	BIT(4)
+#define QSPI_MSTP917	BIT(17)
+
+#define SD2CKCR		0xE615026C
+#define SD_97500KHZ	0x7
+
+struct reg_config {
+	u16	off;
+	u32	val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+
+	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+		;
+
+	while (!(readl(dbsc3_1_base + reg) & BIT(0)))
+		;
+}
+
+static void spl_init_sys(void)
+{
+	u32 r0 = 0;
+
+	writel(0xa5a5a500, 0xe6020004);
+	writel(0xa5a5a500, 0xe6030004);
+
+	asm volatile(
+		/* ICIALLU - Invalidate I$ to PoU */
+		"mcr	15, 0, %0, cr7, cr5, 0	\n"
+		/* BPIALL - Invalidate branch predictors */
+		"mcr	15, 0, %0, cr7, cr5, 6	\n"
+		/* Set SCTLR[IZ] */
+		"mrc	15, 0, %0, cr1, cr0, 0	\n"
+		"orr	%0, #0x1800		\n"
+		"mcr	15, 0, %0, cr1, cr0, 0	\n"
+		"isb	sy			\n"
+		:"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+	static const struct reg_config pfc_with_unlock[] = {
+		{ 0x0090, 0x00140300 },
+		{ 0x0094, 0x09500000 },
+		{ 0x0098, 0xc0000084 },
+		{ 0x0020, 0x01a33492 },
+		{ 0x0024, 0x10000000 },
+		{ 0x0028, 0x08449252 },
+		{ 0x002c, 0x2925b322 },
+		{ 0x0030, 0x0c311249 },
+		{ 0x0034, 0x10124000 },
+		{ 0x0038, 0x00001295 },
+		{ 0x003c, 0x50890000 },
+		{ 0x0040, 0x0eaa56aa },
+		{ 0x0044, 0x55550000 },
+		{ 0x0048, 0x00000005 },
+		{ 0x004c, 0x54800000 },
+		{ 0x0050, 0x3736db55 },
+		{ 0x0054, 0x29148da3 },
+		{ 0x0058, 0x48c446e1 },
+		{ 0x005c, 0x2a3a54dc },
+		{ 0x0160, 0x00000023 },
+		{ 0x0004, 0xfca0ffff },
+		{ 0x0008, 0x3fbffbf0 },
+		{ 0x000c, 0x3ffdffff },
+		{ 0x0010, 0x00ffffff },
+		{ 0x0014, 0xfc3ffff3 },
+		{ 0x0018, 0xe4fdfff7 },
+	};
+
+	static const struct reg_config pfc_without_unlock[] = {
+		{ 0x0104, 0xffffbfff },
+		{ 0x0108, 0xb1ffffe1 },
+		{ 0x010c, 0xffffffff },
+		{ 0x0110, 0xffffffff },
+		{ 0x0114, 0xe047beab },
+		{ 0x0118, 0x00000203 },
+	};
+
+	static const u32 pfc_base = 0xe6060000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+		writel(~pfc_with_unlock[i].val, pfc_base);
+		writel(pfc_with_unlock[i].val,
+		       pfc_base | pfc_with_unlock[i].off);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+		writel(pfc_without_unlock[i].val,
+		       pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+	static const u16 gpio_offs[] = {
+		0x1000, 0x3000, 0x4000, 0x5000
+	};
+
+	static const struct reg_config gpio_set[] = {
+		{ 0x4000, 0x00c00000 },
+		{ 0x5000, 0x63020000 },
+	};
+
+	static const struct reg_config gpio_clr[] = {
+		{ 0x1000, 0x00000000 },
+		{ 0x3000, 0x00000000 },
+		{ 0x4000, 0x00c00000 },
+		{ 0x5000, 0xe3020000 },
+	};
+
+	static const u32 gpio_base = 0xe6050000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+	static const struct reg_config lbsc_config[] = {
+		{ 0x00, 0x00000020 },
+		{ 0x08, 0x00002020 },
+		{ 0x30, 0x02150326 },
+		{ 0x38, 0x077f077f },
+	};
+
+	static const u16 lbsc_offs[] = {
+		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+	};
+
+	static const u32 lbsc_base = 0xfec00200;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+		writel(lbsc_config[i].val,
+		       lbsc_base | lbsc_config[i].off);
+		writel(lbsc_config[i].val,
+		       lbsc_base | (lbsc_config[i].off + 4));
+	}
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+		writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+	static const struct reg_config dbsc_config1[] = {
+		{ 0x0280, 0x0000a55a },
+		{ 0x0018, 0x21000000 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0018, 0x10000000 },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x80000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config2[] = {
+		{ 0x0290, 0x00000006 },
+		{ 0x02a0, 0x0001c000 },
+	};
+
+	static const struct reg_config dbsc_config3r0d0[] = {
+		{ 0x0290, 0x0000000f },
+		{ 0x02a0, 0x00181885 },
+		{ 0x0290, 0x00000070 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x00000080 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x00000090 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x000000a0 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x000000b0 },
+		{ 0x02a0, 0x7c000880 },
+		{ 0x0290, 0x000000c0 },
+		{ 0x02a0, 0x7c000880 },
+		{ 0x0290, 0x000000d0 },
+		{ 0x02a0, 0x7c000880 },
+		{ 0x0290, 0x000000e0 },
+		{ 0x02a0, 0x7c000880 },
+	};
+
+	static const struct reg_config dbsc_config3r0d1[] = {
+		{ 0x0290, 0x0000000f },
+		{ 0x02a0, 0x00181885 },
+		{ 0x0290, 0x00000070 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x00000080 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x00000090 },
+		{ 0x02a0, 0x7c000887 },
+		{ 0x0290, 0x000000a0 },
+		{ 0x02a0, 0x7c000887 },
+	};
+
+	static const struct reg_config dbsc_config3r2[] = {
+		{ 0x0290, 0x0000000f },
+		{ 0x02a0, 0x00181224 },
+	};
+
+	static const struct reg_config dbsc_config4[] = {
+		{ 0x0290, 0x00000010 },
+		{ 0x02a0, 0xf004649b },
+		{ 0x0290, 0x00000061 },
+		{ 0x02a0, 0x0000006d },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000073 },
+		{ 0x0020, 0x00000007 },
+		{ 0x0024, 0x0f030a02 },
+		{ 0x0030, 0x00000001 },
+		{ 0x00b0, 0x00000000 },
+		{ 0x0040, 0x0000000b },
+		{ 0x0044, 0x00000008 },
+		{ 0x0048, 0x00000000 },
+		{ 0x0050, 0x0000000b },
+		{ 0x0054, 0x000c000b },
+		{ 0x0058, 0x00000027 },
+		{ 0x005c, 0x0000001c },
+		{ 0x0060, 0x00000006 },
+		{ 0x0064, 0x00000020 },
+		{ 0x0068, 0x00000008 },
+		{ 0x006c, 0x0000000c },
+		{ 0x0070, 0x00000009 },
+		{ 0x0074, 0x00000012 },
+		{ 0x0078, 0x000000d0 },
+		{ 0x007c, 0x00140005 },
+		{ 0x0080, 0x00050004 },
+		{ 0x0084, 0x70233005 },
+		{ 0x0088, 0x000c0000 },
+		{ 0x008c, 0x00000200 },
+		{ 0x0090, 0x00000040 },
+		{ 0x0100, 0x00000001 },
+		{ 0x00c0, 0x00020001 },
+		{ 0x00c8, 0x20042004 },
+		{ 0x0380, 0x00020002 },
+		{ 0x0390, 0x0000001f },
+	};
+
+	static const struct reg_config dbsc_config5[] = {
+		{ 0x0244, 0x00000011 },
+		{ 0x0290, 0x00000003 },
+		{ 0x02a0, 0x0300c4e1 },
+		{ 0x0290, 0x00000023 },
+		{ 0x02a0, 0x00fcdb60 },
+		{ 0x0290, 0x00000011 },
+		{ 0x02a0, 0x1000040b },
+		{ 0x0290, 0x00000012 },
+		{ 0x02a0, 0x9d9cbb66 },
+		{ 0x0290, 0x00000013 },
+		{ 0x02a0, 0x1a868400 },
+		{ 0x0290, 0x00000014 },
+		{ 0x02a0, 0x300214d8 },
+		{ 0x0290, 0x00000015 },
+		{ 0x02a0, 0x00000d70 },
+		{ 0x0290, 0x00000016 },
+		{ 0x02a0, 0x00000006 },
+		{ 0x0290, 0x00000017 },
+		{ 0x02a0, 0x00000018 },
+		{ 0x0290, 0x0000001a },
+		{ 0x02a0, 0x910035c7 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config6[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000181 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config7[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x0000fe01 },
+		{ 0x0304, 0x00000000 },
+		{ 0x00f4, 0x01004c20 },
+		{ 0x00f8, 0x014000aa },
+		{ 0x00e0, 0x00000140 },
+		{ 0x00e4, 0x00081860 },
+		{ 0x00e8, 0x00010000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config8[] = {
+		{ 0x0014, 0x00000001 },
+		{ 0x0010, 0x00000001 },
+		{ 0x0280, 0x00000000 },
+	};
+
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+	static const u32 prr_base = 0xff000044;
+	const u16 prr_rev = readl(prr_base) & 0x7fff;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
+		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+		writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
+		writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+		writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
+	}
+
+	if (prr_rev == 0x4500) {
+		for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
+			writel(dbsc_config3r0d0[i].val,
+				dbsc3_0_base | dbsc_config3r0d0[i].off);
+		}
+		for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
+			writel(dbsc_config3r0d1[i].val,
+				dbsc3_1_base | dbsc_config3r0d1[i].off);
+		}
+	} else if (prr_rev != 0x4510) {
+		for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
+			writel(dbsc_config3r2[i].val,
+				dbsc3_0_base | dbsc_config3r2[i].off);
+			writel(dbsc_config3r2[i].val,
+				dbsc3_1_base | dbsc_config3r2[i].off);
+		}
+	}
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
+		writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+		writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
+	}
+
+	dbsc_wait(0x240);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
+		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+		writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
+		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+		writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
+		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+		writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
+	}
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
+		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+		writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
+	}
+
+}
+
+static void spl_init_qspi(void)
+{
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	static const u32 qspi_base = 0xe6b10000;
+
+	writeb(0x08, qspi_base + 0x00);
+	writeb(0x00, qspi_base + 0x01);
+	writeb(0x06, qspi_base + 0x02);
+	writeb(0x01, qspi_base + 0x0a);
+	writeb(0x00, qspi_base + 0x0b);
+	writeb(0x00, qspi_base + 0x0c);
+	writeb(0x00, qspi_base + 0x0d);
+	writeb(0x00, qspi_base + 0x0e);
+
+	writew(0xe080, qspi_base + 0x10);
+
+	writeb(0xc0, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x08);
+	writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
+
+	/*
+	 * SD0 clock is set to 97.5MHz by default.
+	 * Set SD2 to the 97.5MHz as well.
+	 */
+	writel(SD_97500KHZ, SD2CKCR);
+
+	spl_init_sys();
+	spl_init_pfc();
+	spl_init_gpio();
+	spl_init_lbsc();
+	spl_init_dbsc();
+	spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	const u32 jtag_magic = 0x1337c0de;
+	const u32 load_magic = 0xb33fc0de;
+
+	/*
+	 * If JTAG probe sets special word at 0xe6300020, then it must
+	 * put U-Boot into RAM and SPL will start it from RAM.
+	 */
+	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+		printf("JTAG boot detected!\n");
+
+		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+			;
+
+		spl_boot_list[0] = BOOT_DEVICE_RAM;
+		spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+		return;
+	}
+
+	/* Boot from SPI NOR with YMODEM UART fallback. */
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+	spl_boot_list[1] = BOOT_DEVICE_UART;
+	spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/roms/u-boot/board/renesas/ulcb/Kconfig b/roms/u-boot/board/renesas/ulcb/Kconfig
new file mode 100644
index 000000000..1e9a10d28
--- /dev/null
+++ b/roms/u-boot/board/renesas/ulcb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ULCB
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "ulcb"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "ulcb"
+
+endif
diff --git a/roms/u-boot/board/renesas/ulcb/MAINTAINERS b/roms/u-boot/board/renesas/ulcb/MAINTAINERS
new file mode 100644
index 000000000..564eb561b
--- /dev/null
+++ b/roms/u-boot/board/renesas/ulcb/MAINTAINERS
@@ -0,0 +1,6 @@
+ULCB BOARD
+M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+S:	Maintained
+F:	board/renesas/ulcb/
+F:	include/configs/ulcb.h
+F:	configs/rcar3_ulcb_defconfig
diff --git a/roms/u-boot/board/renesas/ulcb/Makefile b/roms/u-boot/board/renesas/ulcb/Makefile
new file mode 100644
index 000000000..f4d24c68a
--- /dev/null
+++ b/roms/u-boot/board/renesas/ulcb/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/ulcb/Makefile
+#
+# Copyright (C) 2017 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= ../rcar-common/gen3-spl.o
+else
+obj-y	:= ulcb.o cpld.o ../rcar-common/common.o
+endif
diff --git a/roms/u-boot/board/renesas/ulcb/cpld.c b/roms/u-boot/board/renesas/ulcb/cpld.c
new file mode 100644
index 000000000..ebb2d6f74
--- /dev/null
+++ b/roms/u-boot/board/renesas/ulcb/cpld.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ULCB board CPLD access support
+ *
+ * Copyright (C) 2017 Renesas Electronics Corporation
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/err.h>
+#include <sysreset.h>
+
+#define CPLD_ADDR_MODE		0x00 /* RW */
+#define CPLD_ADDR_MUX		0x02 /* RW */
+#define CPLD_ADDR_DIPSW6	0x08 /* R */
+#define CPLD_ADDR_RESET		0x80 /* RW */
+#define CPLD_ADDR_VERSION	0xFF /* R */
+
+struct renesas_ulcb_sysreset_priv {
+	struct gpio_desc	miso;
+	struct gpio_desc	mosi;
+	struct gpio_desc	sck;
+	struct gpio_desc	sstbz;
+};
+
+static u32 cpld_read(struct udevice *dev, u8 addr)
+{
+	struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
+	u32 data = 0;
+	int i;
+
+	for (i = 0; i < 8; i++) {
+		dm_gpio_set_value(&priv->mosi, !!(addr & 0x80)); /* MSB first */
+		dm_gpio_set_value(&priv->sck, 1);
+		addr <<= 1;
+		dm_gpio_set_value(&priv->sck, 0);
+	}
+
+	dm_gpio_set_value(&priv->mosi, 0); /* READ */
+	dm_gpio_set_value(&priv->sstbz, 0);
+	dm_gpio_set_value(&priv->sck, 1);
+	dm_gpio_set_value(&priv->sck, 0);
+	dm_gpio_set_value(&priv->sstbz, 1);
+
+	for (i = 0; i < 32; i++) {
+		dm_gpio_set_value(&priv->sck, 1);
+		data <<= 1;
+		data |= dm_gpio_get_value(&priv->miso); /* MSB first */
+		dm_gpio_set_value(&priv->sck, 0);
+	}
+
+	return data;
+}
+
+static void cpld_write(struct udevice *dev, u8 addr, u32 data)
+{
+	struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
+	int i;
+
+	for (i = 0; i < 32; i++) {
+		dm_gpio_set_value(&priv->mosi, data & (1 << 31)); /* MSB first */
+		dm_gpio_set_value(&priv->sck, 1);
+		data <<= 1;
+		dm_gpio_set_value(&priv->sck, 0);
+	}
+
+	for (i = 0; i < 8; i++) {
+		dm_gpio_set_value(&priv->mosi, addr & 0x80); /* MSB first */
+		dm_gpio_set_value(&priv->sck, 1);
+		addr <<= 1;
+		dm_gpio_set_value(&priv->sck, 0);
+	}
+
+	dm_gpio_set_value(&priv->mosi, 1); /* WRITE */
+	dm_gpio_set_value(&priv->sstbz, 0);
+	dm_gpio_set_value(&priv->sck, 1);
+	dm_gpio_set_value(&priv->sck, 0);
+	dm_gpio_set_value(&priv->sstbz, 1);
+}
+
+static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc,
+		   char *const argv[])
+{
+	struct udevice *dev;
+	u32 addr, val;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
+					  DM_DRIVER_GET(sysreset_renesas_ulcb),
+					  &dev);
+	if (ret)
+		return ret;
+
+	if (argc == 2 && strcmp(argv[1], "info") == 0) {
+		printf("CPLD version:\t\t\t0x%08x\n",
+		       cpld_read(dev, CPLD_ADDR_VERSION));
+		printf("H3 Mode setting (MD0..28):\t0x%08x\n",
+		       cpld_read(dev, CPLD_ADDR_MODE));
+		printf("Multiplexer settings:\t\t0x%08x\n",
+		       cpld_read(dev, CPLD_ADDR_MUX));
+		printf("DIPSW (SW6):\t\t\t0x%08x\n",
+		       cpld_read(dev, CPLD_ADDR_DIPSW6));
+		return 0;
+	}
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
+	      addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_DIPSW6 ||
+	      addr == CPLD_ADDR_RESET)) {
+		printf("Invalid CPLD register address\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (argc == 3 && strcmp(argv[1], "read") == 0) {
+		printf("0x%x\n", cpld_read(dev, addr));
+	} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+		val = simple_strtoul(argv[3], NULL, 16);
+		cpld_write(dev, addr, val);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	cpld, 4, 1, do_cpld,
+	"CPLD access",
+	"info\n"
+	"cpld read addr\n"
+	"cpld write addr val\n"
+);
+
+static int renesas_ulcb_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	cpld_write(dev, CPLD_ADDR_RESET, 1);
+
+	return -EINPROGRESS;
+}
+
+static int renesas_ulcb_sysreset_probe(struct udevice *dev)
+{
+	struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
+
+	if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
+				 GPIOD_IS_IN))
+		return -EINVAL;
+
+	if (gpio_request_by_name(dev, "gpio-sck", 0, &priv->sck,
+				 GPIOD_IS_OUT))
+		return -EINVAL;
+
+	if (gpio_request_by_name(dev, "gpio-sstbz", 0, &priv->sstbz,
+				 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE))
+		return -EINVAL;
+
+	if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
+				 GPIOD_IS_OUT))
+		return -EINVAL;
+
+	/* PULL-UP on MISO line */
+	setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
+
+	/* Dummy read */
+	cpld_read(dev, CPLD_ADDR_VERSION);
+
+	return 0;
+}
+
+static struct sysreset_ops renesas_ulcb_sysreset = {
+	.request	= renesas_ulcb_sysreset_request,
+};
+
+static const struct udevice_id renesas_ulcb_sysreset_ids[] = {
+	{ .compatible = "renesas,ulcb-cpld" },
+	{ }
+};
+
+U_BOOT_DRIVER(sysreset_renesas_ulcb) = {
+	.name		= "renesas_ulcb_sysreset",
+	.id		= UCLASS_SYSRESET,
+	.ops		= &renesas_ulcb_sysreset,
+	.probe		= renesas_ulcb_sysreset_probe,
+	.of_match	= renesas_ulcb_sysreset_ids,
+	.priv_auto	= sizeof(struct renesas_ulcb_sysreset_priv),
+};
diff --git a/roms/u-boot/board/renesas/ulcb/ulcb.c b/roms/u-boot/board/renesas/ulcb/ulcb.c
new file mode 100644
index 000000000..7ba194865
--- /dev/null
+++ b/roms/u-boot/board/renesas/ulcb/ulcb.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/ulcb/ulcb.c
+ *     This file is ULCB board support.
+ *
+ * Copyright (C) 2017 Renesas Electronics Corporation
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DVFS_MSTP926		BIT(26)
+#define HSUSB_MSTP704		BIT(4)	/* HSUSB */
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+	/* DVFS for reset */
+	mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
+#endif
+	return 0;
+}
+
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS			0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
+#define HSUSB_REG_UGCTRL2		0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL	0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	/* USB1 pull-up */
+	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+	/* Configure the HSUSB block */
+	mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
+	/* Choice USB0SEL */
+	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+	/* low power status */
+	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
+	return 0;
+}
+
+#ifdef CONFIG_MULTI_DTB_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* PRR driver is not available yet */
+	u32 cpu_type = rmobile_get_cpu_type();
+
+	if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
+	    !strcmp(name, "r8a77950-ulcb-u-boot"))
+		return 0;
+
+	if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
+	    !strcmp(name, "r8a77960-ulcb-u-boot"))
+		return 0;
+
+	if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
+	    !strcmp(name, "r8a77965-ulcb-u-boot"))
+		return 0;
+
+	return -1;
+}
+#endif
diff --git a/roms/u-boot/board/rockchip/evb_px30/Kconfig b/roms/u-boot/board/rockchip/evb_px30/Kconfig
new file mode 100644
index 000000000..0042c8e4d
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_px30/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_PX30
+
+config SYS_BOARD
+	default "evb_px30"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_px30"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/evb_px30/MAINTAINERS b/roms/u-boot/board/rockchip/evb_px30/MAINTAINERS
new file mode 100644
index 000000000..4dc060c50
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_px30/MAINTAINERS
@@ -0,0 +1,7 @@
+EVB-PX30
+M:      Kever Yang <kever.yang@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/evb_px30
+F:      include/configs/evb_px30.h
+F:      configs/evb-px30_defconfig
+F:      configs/firefly-px30_defconfig
diff --git a/roms/u-boot/board/rockchip/evb_px30/Makefile b/roms/u-boot/board/rockchip/evb_px30/Makefile
new file mode 100644
index 000000000..74b0b9f44
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_px30/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb_px30.o
diff --git a/roms/u-boot/board/rockchip/evb_px30/evb_px30.c b/roms/u-boot/board/rockchip/evb_px30/evb_px30.c
new file mode 100644
index 000000000..29464ae63
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_px30/evb_px30.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
diff --git a/roms/u-boot/board/rockchip/evb_px5/Kconfig b/roms/u-boot/board/rockchip/evb_px5/Kconfig
new file mode 100644
index 000000000..9a04ee7e6
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_px5/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_PX5
+
+config SYS_BOARD
+	default "evb_px5"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_px5"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/evb_px5/MAINTAINERS b/roms/u-boot/board/rockchip/evb_px5/MAINTAINERS
new file mode 100644
index 000000000..5d09fbf0a
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_px5/MAINTAINERS
@@ -0,0 +1,6 @@
+PX5 EVB
+M:	Andy Yan <andy.yan@rock-chips.com>
+S:	Maintained
+F:	board/rockchip/evb_px5
+F:	include/configs/evb_px5.h
+F:	configs/evb-px5_defconfig
diff --git a/roms/u-boot/board/rockchip/evb_px5/Makefile b/roms/u-boot/board/rockchip/evb_px5/Makefile
new file mode 100644
index 000000000..40f6ff8e7
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_px5/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2017 Rockchip Electronics Co., Ltd
+
+obj-y	+= evb-px5.o
diff --git a/roms/u-boot/board/rockchip/evb_px5/README b/roms/u-boot/board/rockchip/evb_px5/README
new file mode 100644
index 000000000..de980f2f2
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_px5/README
@@ -0,0 +1 @@
+see board/rockchip/sheep_rk3368/README
diff --git a/roms/u-boot/board/rockchip/evb_px5/evb-px5.c b/roms/u-boot/board/rockchip/evb_px5/evb-px5.c
new file mode 100644
index 000000000..b81f97088
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_px5/evb-px5.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Andy Yan
+ */
diff --git a/roms/u-boot/board/rockchip/evb_rk3036/Kconfig b/roms/u-boot/board/rockchip/evb_rk3036/Kconfig
new file mode 100644
index 000000000..ef45f6292
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3036/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3036
+
+config SYS_BOARD
+	default "evb_rk3036"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3036"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/evb_rk3036/MAINTAINERS b/roms/u-boot/board/rockchip/evb_rk3036/MAINTAINERS
new file mode 100644
index 000000000..91f8a839c
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3036/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3036
+M:      huang lin <hl@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/evb_rk3036
+F:      include/configs/evb_rk3036.h
+F:      configs/evb-rk3036_defconfig
diff --git a/roms/u-boot/board/rockchip/evb_rk3036/Makefile b/roms/u-boot/board/rockchip/evb_rk3036/Makefile
new file mode 100644
index 000000000..0403836e1
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3036/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb_rk3036.o
diff --git a/roms/u-boot/board/rockchip/evb_rk3036/evb_rk3036.c b/roms/u-boot/board/rockchip/evb_rk3036/evb_rk3036.c
new file mode 100644
index 000000000..8c606463e
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3036/evb_rk3036.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/uart.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
+
+void get_ddr_config(struct rk3036_ddr_config *config)
+{
+	/* K4B4G1646Q config */
+	config->ddr_type = 3;
+	config->rank = 2;
+	config->cs0_row = 15;
+	config->cs1_row = 15;
+
+	/* 8bank */
+	config->bank = 3;
+	config->col = 10;
+
+	/* 16bit bw */
+	config->bw = 1;
+}
diff --git a/roms/u-boot/board/rockchip/evb_rk3128/Kconfig b/roms/u-boot/board/rockchip/evb_rk3128/Kconfig
new file mode 100644
index 000000000..5b3095ade
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3128/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3128
+
+config SYS_BOARD
+	default "evb_rk3128"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3128"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/evb_rk3128/MAINTAINERS b/roms/u-boot/board/rockchip/evb_rk3128/MAINTAINERS
new file mode 100644
index 000000000..f5145d1f0
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3128/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3128
+M:      Kever Yang <kever.yang@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/evb_rk3128
+F:      include/configs/evb_rk3128.h
+F:      configs/evb-rk3128_defconfig
diff --git a/roms/u-boot/board/rockchip/evb_rk3128/Makefile b/roms/u-boot/board/rockchip/evb_rk3128/Makefile
new file mode 100644
index 000000000..078bb898c
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3128/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evk-rk3128.o
diff --git a/roms/u-boot/board/rockchip/evb_rk3128/evk-rk3128.c b/roms/u-boot/board/rockchip/evb_rk3128/evk-rk3128.c
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3128/evk-rk3128.c
diff --git a/roms/u-boot/board/rockchip/evb_rk3229/Kconfig b/roms/u-boot/board/rockchip/evb_rk3229/Kconfig
new file mode 100644
index 000000000..361dcb186
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3229/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3229
+
+config SYS_BOARD
+	default "evb_rk3229"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3229"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/evb_rk3229/MAINTAINERS b/roms/u-boot/board/rockchip/evb_rk3229/MAINTAINERS
new file mode 100644
index 000000000..dfa1090c3
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3229/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3229
+M:      Kever Yang <kever.yang@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/evb_rk3229
+F:      include/configs/evb_rk3229.h
+F:      configs/evb-rk3229_defconfig
diff --git a/roms/u-boot/board/rockchip/evb_rk3229/Makefile b/roms/u-boot/board/rockchip/evb_rk3229/Makefile
new file mode 100644
index 000000000..65dcd8be3
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3229/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb_rk3229.o
diff --git a/roms/u-boot/board/rockchip/evb_rk3229/README b/roms/u-boot/board/rockchip/evb_rk3229/README
new file mode 100644
index 000000000..9068225e2
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3229/README
@@ -0,0 +1,71 @@
+Get the Source and prebuild binary
+==================================
+
+  > mkdir ~/evb_rk3229
+  > cd ~/evb_rk3229
+  > git clone git://git.denx.de/u-boot.git
+  > git clone https://github.com/OP-TEE/optee_os.git
+  > git clone https://github.com/rockchip-linux/rkbin.git
+  > git clone https://github.com/rockchip-linux/rkdeveloptool.git
+
+Compile the OP-TEE
+===============
+
+  > cd optee_os
+  > make clean
+  > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x
+  Get tee.bin in this step, copy it to U-Boot root dir:
+  > cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin
+
+Compile the U-Boot
+==================
+
+  > cd ../u-boot
+  > export CROSS_COMPILE=arm-linux-gnueabihf-
+  > make evb-rk3229_defconfig
+  > make
+  > make u-boot.itb
+
+  Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step.
+
+Compile the rkdeveloptool
+=======================
+  Follow instructions in latest README
+  > cd ../rkflashtool
+  > autoreconf -i
+  > ./configure
+  > make
+  > sudo make install
+
+  Get rkdeveloptool in you Host in this step.
+
+Both origin binaries and Tool are ready now, choose either option 1 or
+option 2 to deploy U-Boot.
+
+Package the image
+=================
+
+  > cd ../u-boot
+  > tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img
+  > cat spl/u-boot-spl.bin >> idbloader.img
+
+  Get idbloader.img in this step.
+
+Flash the image to eMMC
+=======================
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+  > cd ..
+  > rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin
+  > rkdeveloptool wl 64 u-boot/idbloader.img
+  > rkdeveloptool wl 0x4000 u-boot/u-boot.itb
+  > rkdeveloptool rd
+
+Flash the image to SD card
+==========================
+  > dd if=u-boot/idbloader.img of=/dev/sdb seek=64
+  > dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384
+
+You should be able to get U-Boot log message with OP-TEE boot info.
+
+For more detail, please reference to:
+http://opensource.rock-chips.com/wiki_Boot_option
diff --git a/roms/u-boot/board/rockchip/evb_rk3229/evb_rk3229.c b/roms/u-boot/board/rockchip/evb_rk3229/evb_rk3229.c
new file mode 100644
index 000000000..c64c62f7b
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3229/evb_rk3229.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/uart.h>
+
diff --git a/roms/u-boot/board/rockchip/evb_rk3288/Kconfig b/roms/u-boot/board/rockchip/evb_rk3288/Kconfig
new file mode 100644
index 000000000..8ab07f41f
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3288
+
+config SYS_BOARD
+	default "evb_rk3288"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/evb_rk3288/MAINTAINERS b/roms/u-boot/board/rockchip/evb_rk3288/MAINTAINERS
new file mode 100644
index 000000000..9bd6b1e8a
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3288/MAINTAINERS
@@ -0,0 +1,12 @@
+EVB-RK3288
+M:	Lin Huang <hl@rock-chips.com>
+S:	Maintained
+F:	board/rockchip/evb_rk3288
+F:	include/configs/evb_rk3288.h
+F:	configs/evb-rk3288_defconfig
+
+ROCK-PI-N8
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/rock-pi-n8-rk3288_defconfig
+F:	arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi
diff --git a/roms/u-boot/board/rockchip/evb_rk3288/Makefile b/roms/u-boot/board/rockchip/evb_rk3288/Makefile
new file mode 100644
index 000000000..c11b65760
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb-rk3288.o
diff --git a/roms/u-boot/board/rockchip/evb_rk3288/evb-rk3288.c b/roms/u-boot/board/rockchip/evb_rk3288/evb-rk3288.c
new file mode 100644
index 000000000..779bc646b
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3288/evb-rk3288.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
diff --git a/roms/u-boot/board/rockchip/evb_rk3308/Kconfig b/roms/u-boot/board/rockchip/evb_rk3308/Kconfig
new file mode 100644
index 000000000..0074429cb
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3308/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3308
+
+config SYS_BOARD
+	default "evb_rk3308"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/evb_rk3308/MAINTAINERS b/roms/u-boot/board/rockchip/evb_rk3308/MAINTAINERS
new file mode 100644
index 000000000..0af119ae0
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3308/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3308
+M:      Andy Yan <andy.yan@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/evb_rk3308
+F:      include/configs/evb_rk3308.h
+F:      configs/evb-rk3308_defconfig
diff --git a/roms/u-boot/board/rockchip/evb_rk3308/Makefile b/roms/u-boot/board/rockchip/evb_rk3308/Makefile
new file mode 100644
index 000000000..05de5560f
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3308/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb_rk3308.o
diff --git a/roms/u-boot/board/rockchip/evb_rk3308/evb_rk3308.c b/roms/u-boot/board/rockchip/evb_rk3308/evb_rk3308.c
new file mode 100644
index 000000000..e0c96fd70
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3308/evb_rk3308.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <adc.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define KEY_DOWN_MIN_VAL        0
+#define KEY_DOWN_MAX_VAL        30
+
+/*
+ * Two board variants whith adc channel 3 is for board id
+ * v10: 1024, v11: 512
+ * v10: adc channel 0 for dnl key
+ * v11: adc channel 1 for dnl key
+ */
+int rockchip_dnl_key_pressed(void)
+{
+	unsigned int key_val, id_val;
+	int key_ch;
+
+	if (adc_channel_single_shot("saradc", 3, &id_val)) {
+		printf("%s read board id failed\n", __func__);
+		return false;
+	}
+
+	if (abs(id_val - 1024) <= 30)
+		key_ch = 0;
+	else
+		key_ch = 1;
+
+	if (adc_channel_single_shot("saradc", key_ch, &key_val)) {
+		printf("%s read adc key val failed\n", __func__);
+		return false;
+	}
+
+	if (key_val >= KEY_DOWN_MIN_VAL && key_val <= KEY_DOWN_MAX_VAL)
+		return true;
+	else
+		return false;
+}
diff --git a/roms/u-boot/board/rockchip/evb_rk3328/Kconfig b/roms/u-boot/board/rockchip/evb_rk3328/Kconfig
new file mode 100644
index 000000000..ef446b49d
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3328/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3328
+
+config SYS_BOARD
+	default "evb_rk3328"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3328"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/evb_rk3328/MAINTAINERS b/roms/u-boot/board/rockchip/evb_rk3328/MAINTAINERS
new file mode 100644
index 000000000..14fda46e8
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3328/MAINTAINERS
@@ -0,0 +1,33 @@
+EVB-RK3328
+M:      Kever Yang <kever.yang@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/evb_rk3328
+F:      include/configs/evb_rk3328.h
+F:      configs/evb-rk3328_defconfig
+
+NANOPI-R2S-RK3328
+M:      David Bauer <mail@david-bauer.net>
+S:      Maintained
+F:      configs/nanopi-r2s-rk3328_defconfig
+F:      arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+F:      arch/arm/dts/rk3328-nanopi-r2s.dts
+
+ROC-RK3328-CC
+M:      Loic Devulder <ldevulder@suse.com>
+M:      Chen-Yu Tsai <wens@csie.org>
+S:      Maintained
+F:      configs/roc-cc-rk3328_defconfig
+F:      arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+
+ROCK64-RK3328
+M:      Matwey V. Kornilov <matwey.kornilov@gmail.com>
+S:      Maintained
+F:      configs/rock64-rk3328_defconfig
+F:      arch/arm/dts/rk3328-rock64-u-boot.dtsi
+
+ROCKPIE-RK3328
+M:      Banglang Huang <banglang.huang@foxmail.com>
+S:      Maintained
+F:      configs/rock-pi-e-rk3328_defconfig
+F:      arch/arm/dts/rk3328-rock-pi-e.dts
+F:      arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
diff --git a/roms/u-boot/board/rockchip/evb_rk3328/Makefile b/roms/u-boot/board/rockchip/evb_rk3328/Makefile
new file mode 100644
index 000000000..81c5de86d
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3328/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb-rk3328.o
diff --git a/roms/u-boot/board/rockchip/evb_rk3328/README b/roms/u-boot/board/rockchip/evb_rk3328/README
new file mode 100644
index 000000000..6cbb66a4c
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3328/README
@@ -0,0 +1,70 @@
+Introduction
+============
+
+RK3328 key features we might use in U-Boot:
+* CPU: ARMv8 64bit quad-core Cortex-A53
+* IRAM: 36KB
+* DRAM: 4GB-16MB dual-channel
+* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
+* SD/MMC: support SD 3.0, MMC 4.51
+* USB: USB2.0 EHCI host port *2
+* Display: RGB/HDMI/DP/MIPI/EDP
+
+evb key features:
+* regulator: pwm regulator for CPU B/L
+* PMIC: rk808
+* debug console: UART2
+
+In order to support Arm Trust Firmware(ATF), we need to use the
+miniloader from rockchip which:
+* do DRAM init
+* load and verify ATF image
+* load and verify U-Boot image
+
+Here is the step-by-step to boot to U-Boot on rk3328.
+
+Get the Source and prebuild binary
+==================================
+
+  > mkdir ~/evb_rk3328
+  > cd ~/evb_rk3328
+  > git clone https://github.com/ARM-software/arm-trusted-firmware.git
+  > git clone https://github.com/rockchip-linux/rkbin
+  > git clone https://github.com/rockchip-linux/rkflashtool
+
+Compile ATF
+===============
+
+  > cd arm-trusted-firmware
+  > make realclean
+  > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3328 bl31
+
+Compile U-Boot
+==================
+
+  > cd ../u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3328_defconfig all
+
+Compile rkflashtool
+=======================
+
+  > cd ../rkflashtool
+  > make
+
+Package image for miniloader
+================================
+  > cd ..
+  > cp arm-trusted-firmware/build/rk3328/release/bl31.bin rkbin/rk33
+  > ./rkbin/tools/trust_merger rkbin/tools/RK3328TRUST.ini
+  > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img
+  > mkdir image
+  > mv trust.img ./image/
+  > mv uboot.img ./image/rk3328evb-uboot.bin
+
+Flash image
+===============
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+
+  > ./rkflashtool/rkflashloader rk3328evb
+
+You should be able to get U-Boot log message in console/UART2 now.
diff --git a/roms/u-boot/board/rockchip/evb_rk3328/evb-rk3328.c b/roms/u-boot/board/rockchip/evb_rk3328/evb-rk3328.c
new file mode 100644
index 000000000..779bc646b
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3328/evb-rk3328.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
diff --git a/roms/u-boot/board/rockchip/evb_rk3399/Kconfig b/roms/u-boot/board/rockchip/evb_rk3399/Kconfig
new file mode 100644
index 000000000..412b81cbe
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3399/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3399
+
+config SYS_BOARD
+	default "evb_rk3399"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3399"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/evb_rk3399/MAINTAINERS b/roms/u-boot/board/rockchip/evb_rk3399/MAINTAINERS
new file mode 100644
index 000000000..25e308d18
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3399/MAINTAINERS
@@ -0,0 +1,90 @@
+EVB-RK3399
+M:      Kever Yang <kever.yang@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/evb_rk3399
+F:      include/configs/evb_rk3399.h
+F:      configs/evb-rk3399_defconfig
+F:      configs/firefly-rk3399_defconfig
+
+KHADAS-EDGE
+M:	Nick Xie <nick@khadas.com>
+S:	Maintained
+F:	configs/khadas-edge-rk3399_defconfig
+F:	arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
+
+KHADAS-EDGE-CAPTAIN
+M:	Nick Xie <nick@khadas.com>
+S:	Maintained
+F:	configs/khadas-edge-captain-rk3399_defconfig
+F:	arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi
+
+KHADAS-EDGE-V
+M:	Nick Xie <nick@khadas.com>
+S:	Maintained
+F:	configs/khadas-edge-v-rk3399_defconfig
+F:	arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi
+
+LEEZ-P710
+M:	Andy Yan <andy.yan@rock-chips.com>
+S:      Maintained
+F:	arch/arm/dts/rk3399-leez-p710-u-boot.dtsi
+F:	configs/leez-rk3399_defconfig
+
+NANOPC-T4
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/nanopc-t4-rk3399_defconfig
+F:	arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
+
+NANOPI-M4
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/nanopi-m4-rk3399_defconfig
+F:	arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
+
+NANOPI-M4-2GB
+M:	Jagan Teki <jagan@amarulasolutions.com>
+M:	Deepak Das <deepakdas.linux@gmail.com>
+S:	Maintained
+F:	configs/nanopi-m4-2gb-rk3399_defconfig
+F:	arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi
+
+NANOPI-M4B
+M:	Alexandre Vicenzi <linux@alxd.me>
+S:	Maintained
+F:	configs/nanopi-m4b-rk3399_defconfig
+F:	arch/arm/dts/rk3399-nanopi-m4b-u-boot.dtsi
+
+NANOPI-NEO4
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/nanopi-neo4-rk3399_defconfig
+F:	arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
+
+NANOPI-R4S
+M:	Xiaobo Tian <peterwillcn@gmail.com>
+S:	Maintained
+F:	configs/nanopi-r4s-rk3399_defconfig
+F:	arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
+
+ORANGEPI-RK3399
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/orangepi-rk3399_defconfig
+F:	arch/arm/dts/rk3399-u-boot.dtsi
+F:	arch/arm/dts/rk3399-orangepi-u-boot.dtsi
+
+ROCK-PI-4
+M:	Akash Gajjar <akash@openedev.com>
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/rock-pi-4-rk3399_defconfig
+F:	arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+F:	configs/rock-pi-4c-rk3399_defconfig
+F:	arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
+
+ROCK-PI-N10
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/rock-pi-n10-rk3399pro_defconfig
+F:	arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi
diff --git a/roms/u-boot/board/rockchip/evb_rk3399/Makefile b/roms/u-boot/board/rockchip/evb_rk3399/Makefile
new file mode 100644
index 000000000..aaa51c212
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3399/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb-rk3399.o
diff --git a/roms/u-boot/board/rockchip/evb_rk3399/README b/roms/u-boot/board/rockchip/evb_rk3399/README
new file mode 100644
index 000000000..c6f58203e
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3399/README
@@ -0,0 +1,122 @@
+Introduction
+============
+
+RK3399 key features we might use in U-Boot:
+* CPU: ARMv8 64bit Big-Little architecture,
+*      Big: dual-core Cortex-A72
+*      Little: quad-core Cortex-A53
+* IRAM: 200KB
+* DRAM: 4GB-128MB dual-channel
+* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
+* SD/MMC: support SD 3.0, MMC 4.51
+* USB: USB3.0 type-C port *2 with dwc3 controller
+*      USB2.0 EHCI host port *2
+* Display: RGB/HDMI/DP/MIPI/EDP
+
+evb key features:
+* regulator: pwm regulator for CPU B/L
+* PMIC: rk808
+* debug console: UART2
+
+In order to support Arm Trust Firmware(ATF), we can use either SPL or
+miniloader from rockchip to do:
+* do DRAM init
+* load and verify ATF image
+* load and verify U-Boot image
+
+Here is the step-by-step to boot to U-Boot on rk3399.
+
+Get the Source and prebuild binary
+==================================
+
+  > mkdir ~/evb_rk3399
+  > cd ~/evb_rk3399
+  > git clone https://github.com/ARM-software/arm-trusted-firmware.git
+  > git clone https://github.com/rockchip-linux/rkbin.git
+  > git clone https://github.com/rockchip-linux/rkdeveloptool.git
+
+
+Compile ATF
+===========
+
+  > cd arm-trusted-firmware
+  > make realclean
+  > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
+
+  Get bl31.elf in this step, copy it to U-Boot root dir:
+  > cp build/rk3399/release/bl31/bl31.elf ../u-boot/
+
+  Or you can get the bl31.elf directly from Rockchip:
+  > cp rkbin/rk33/rk3399_bl31_v1.00.elf ../u-boot/bl31.elf
+
+
+Compile U-Boot
+==============
+
+  > cd ../u-boot
+  > export CROSS_COMPILE=aarch64-linux-gnu-
+  > make evb-rk3399_defconfig
+  for firefly-rk3399, use below instead:
+  > make firefly-rk3399_defconfig
+  > make
+  > make u-boot.itb
+
+  Get spl/u-boot-spl.bin and u-boot.itb in this step.
+
+Compile rkdeveloptool
+=====================
+
+Get rkdeveloptool installed on your Host in this step.
+
+Follow instructions in latest README, example:
+  > cd ../rkdeveloptool
+  > autoreconf -i
+  > ./configure
+  > make
+  > sudo make install
+
+Both origin binaries and Tool are ready now, choose either option 1 or
+option 2 to deploy U-Boot.
+
+Package the image
+=================
+
+Package the image for U-Boot SPL(option 1)
+--------------------------------
+  > cd ..
+  > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin idbspl.img
+
+  Get idbspl.img in this step.
+
+Package the image for Rockchip miniloader(option 2)
+------------------------------------------
+  > cd ..
+  > cp arm-trusted-firmware/build/rk3399/release/bl31.elf rkbin/rk33
+  > ./rkbin/tools/trust_merger rkbin/tools/RK3399TRUST.ini
+  > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img
+
+  Get trust.img and uboot.img in this step.
+
+Flash the image to eMMC
+=======================
+
+Flash the image with U-Boot SPL(option 1)
+-------------------------------
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+  > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
+  > rkdeveloptool wl 64 u-boot/idbspl.img
+  > rkdeveloptool wl 0x4000 u-boot/u-boot.itb
+  > rkdeveloptool rd
+
+Flash the image with Rockchip miniloader(option 2)
+----------------------------------------
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+  > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
+  > rkdeveloptool ul rkbin/rk33/rk3399_loader_v1.08.106.bin
+  > rkdeveloptool wl 0x4000 u-boot/uboot.img
+  > rkdeveloptool wl 0x6000 u-boot/trust.img
+  > rkdeveloptool rd
+
+You should be able to get U-Boot log in console/UART2(baurdrate 1500000)
+For more detail, please reference to:
+http://opensource.rock-chips.com/wiki_Boot_option
diff --git a/roms/u-boot/board/rockchip/evb_rk3399/evb-rk3399.c b/roms/u-boot/board/rockchip/evb_rk3399/evb-rk3399.c
new file mode 100644
index 000000000..abb76585c
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch-rockchip/periph.h>
+#include <power/regulator.h>
+
+#ifndef CONFIG_SPL_BUILD
+int board_early_init_f(void)
+{
+	struct udevice *regulator;
+	int ret;
+
+	ret = regulator_get_by_platname("vcc5v0_host", &regulator);
+	if (ret) {
+		debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
+		goto out;
+	}
+
+	ret = regulator_set_enable(regulator, true);
+	if (ret)
+		debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret);
+
+out:
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/rockchip/evb_rv1108/Kconfig b/roms/u-boot/board/rockchip/evb_rv1108/Kconfig
new file mode 100644
index 000000000..4a76e0b9f
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rv1108/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RV1108
+
+config SYS_BOARD
+	default "evb_rv1108"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rv1108"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/evb_rv1108/MAINTAINERS b/roms/u-boot/board/rockchip/evb_rv1108/MAINTAINERS
new file mode 100644
index 000000000..94def320c
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rv1108/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RV1108
+M:      Andy Yan <andy.yan@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/evb_rv1108
+F:      include/configs/evb_rv1108.h
+F:      configs/evb-rv1108_defconfig
diff --git a/roms/u-boot/board/rockchip/evb_rv1108/Makefile b/roms/u-boot/board/rockchip/evb_rv1108/Makefile
new file mode 100644
index 000000000..dd99054d5
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rv1108/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb_rv1108.o
diff --git a/roms/u-boot/board/rockchip/evb_rv1108/README b/roms/u-boot/board/rockchip/evb_rv1108/README
new file mode 100644
index 000000000..79a97c313
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rv1108/README
@@ -0,0 +1,46 @@
+Here is the step-by-step to boot U-Boot on rv1108 evb.
+
+Get ddr init binary
+==============================================================================
+  > git clone  https://github.com/rockchip-linux/rkbin.git
+
+Compile  U-Boot
+===========================
+  > make CROSS_COMPILE=arm-linux-gnueabi- evb-rv1108_defconfig  all
+  > ./tools/mkimage  -n rv1108 -T rksd -d ../rkbin/rv1x/rv1108ddr_v1.00.bin spl.bin
+  > cat spl.bin u-boot.bin > u-boot.img
+
+Flash the image by rkdeveloptool
+================================
+rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git
+
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+  > rkdeveloptool db ./rkbin/rv1x/rv1108usbboot_v1.00.bin
+  > rkdeveloptool wl 0x40 u-boot.img
+  > rkdeveloptool RD
+
+You should be able to get U-Boot log message from boot console:
+
+DDR Version V1.02 20170220
+In
+400MHz
+DDR3
+Bus Width=16 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=512MB
+mach:2
+OUT
+
+
+U-Boot 2017.05-00693-g3a5b171 (Jun 01 2017 - 17:37:53 +0800)
+
+Model: Rockchip RV1108 Evaluation board
+DRAM:  128 MiB
+APLL: 600000000 DPLL:792000000 GPLL:384000000
+MMC:
+Using default environment
+
+In:    serial@10210000
+Out:   serial@10210000
+Err:   serial@10210000
+Net:   No ethernet found.
+Hit any key to stop autoboot:  0
+=>
diff --git a/roms/u-boot/board/rockchip/evb_rv1108/evb_rv1108.c b/roms/u-boot/board/rockchip/evb_rv1108/evb_rv1108.c
new file mode 100644
index 000000000..e6ac59864
--- /dev/null
+++ b/roms/u-boot/board/rockchip/evb_rv1108/evb_rv1108.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C)Copyright 2016 Rockchip Electronics Co., Ltd
+ * Authors: Andy Yan <andy.yan@rock-chips.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <syscon.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rv1108.h>
+#include <asm/arch-rockchip/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	struct rv1108_grf *grf;
+	enum {
+		GPIO3C3_SHIFT           = 6,
+		GPIO3C3_MASK            = 3 << GPIO3C3_SHIFT,
+
+		GPIO3C2_SHIFT           = 4,
+		GPIO3C2_MASK            = 3 << GPIO3C2_SHIFT,
+
+		GPIO2D2_SHIFT		= 4,
+		GPIO2D2_MASK		= 3 << GPIO2D2_SHIFT,
+		GPIO2D2_GPIO            = 0,
+		GPIO2D2_UART2_SOUT_M0,
+
+		GPIO2D1_SHIFT		= 2,
+		GPIO2D1_MASK		= 3 << GPIO2D1_SHIFT,
+		GPIO2D1_GPIO            = 0,
+		GPIO2D1_UART2_SIN_M0,
+	};
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+	/*evb board use UART2 m0 for debug*/
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D2_MASK | GPIO2D1_MASK,
+		     GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
+		     GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
+	rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = 0x8000000;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/rockchip/kylin_rk3036/Kconfig b/roms/u-boot/board/rockchip/kylin_rk3036/Kconfig
new file mode 100644
index 000000000..8d35b4e62
--- /dev/null
+++ b/roms/u-boot/board/rockchip/kylin_rk3036/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_KYLIN_RK3036
+
+config SYS_BOARD
+	default "kylin_rk3036"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "kylin_rk3036"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/kylin_rk3036/MAINTAINERS b/roms/u-boot/board/rockchip/kylin_rk3036/MAINTAINERS
new file mode 100644
index 000000000..5453e7d98
--- /dev/null
+++ b/roms/u-boot/board/rockchip/kylin_rk3036/MAINTAINERS
@@ -0,0 +1,6 @@
+KYLIN-RK3036
+M:      huang lin <hl@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/kylin_rk3036
+F:      include/configs/kylin_rk3036.h
+F:      configs/kylin-rk3036_defconfig
diff --git a/roms/u-boot/board/rockchip/kylin_rk3036/Makefile b/roms/u-boot/board/rockchip/kylin_rk3036/Makefile
new file mode 100644
index 000000000..066327050
--- /dev/null
+++ b/roms/u-boot/board/rockchip/kylin_rk3036/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= kylin_rk3036.o
diff --git a/roms/u-boot/board/rockchip/kylin_rk3036/kylin_rk3036.c b/roms/u-boot/board/rockchip/kylin_rk3036/kylin_rk3036.c
new file mode 100644
index 000000000..0ca91cdeb
--- /dev/null
+++ b/roms/u-boot/board/rockchip/kylin_rk3036/kylin_rk3036.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/uart.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
+#include <asm/gpio.h>
+
+void get_ddr_config(struct rk3036_ddr_config *config)
+{
+	/* K4B4G1646Q config */
+	config->ddr_type = 3;
+	config->rank = 1;
+	config->cs0_row = 15;
+	config->cs1_row = 15;
+
+	/* 8bank */
+	config->bank = 3;
+	config->col = 10;
+
+	/* 16bit bw */
+	config->bw = 1;
+}
+
+#define FASTBOOT_KEY_GPIO 93
+
+int fastboot_key_pressed(void)
+{
+	gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key");
+	gpio_direction_input(FASTBOOT_KEY_GPIO);
+	return !gpio_get_value(FASTBOOT_KEY_GPIO);
+}
+
+#define ROCKCHIP_BOOT_MODE_FASTBOOT	0x5242C309
+
+int rk_board_late_init(void)
+{
+	if (fastboot_key_pressed()) {
+		printf("enter fastboot!\n");
+		env_set("preboot", "setenv preboot; fastboot usb0");
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/rockchip/sheep_rk3368/Kconfig b/roms/u-boot/board/rockchip/sheep_rk3368/Kconfig
new file mode 100644
index 000000000..d39b5e8b1
--- /dev/null
+++ b/roms/u-boot/board/rockchip/sheep_rk3368/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SHEEP
+
+config SYS_BOARD
+	default "sheep_rk3368"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "sheep_rk3368"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/sheep_rk3368/MAINTAINERS b/roms/u-boot/board/rockchip/sheep_rk3368/MAINTAINERS
new file mode 100644
index 000000000..cd5de9923
--- /dev/null
+++ b/roms/u-boot/board/rockchip/sheep_rk3368/MAINTAINERS
@@ -0,0 +1,6 @@
+RK3368 Sheep Board
+M:	Andy Yan <andy.yan@rock-chips.com>
+S:	Maintained
+F:	board/rockchip/sheep_rk3368
+F:	include/configs/sheep_rk3368.h
+F:	configs/sheep-rk3368_defconfig
diff --git a/roms/u-boot/board/rockchip/sheep_rk3368/Makefile b/roms/u-boot/board/rockchip/sheep_rk3368/Makefile
new file mode 100644
index 000000000..966152811
--- /dev/null
+++ b/roms/u-boot/board/rockchip/sheep_rk3368/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2017 Rockchip Electronics Co., Ltd
+
+obj-y	+= sheep_rk3368.o
diff --git a/roms/u-boot/board/rockchip/sheep_rk3368/README b/roms/u-boot/board/rockchip/sheep_rk3368/README
new file mode 100644
index 000000000..2d078cbe5
--- /dev/null
+++ b/roms/u-boot/board/rockchip/sheep_rk3368/README
@@ -0,0 +1,44 @@
+Here is the step-by-step to boot to U-Boot on rk3368.
+
+Get miniloader and trust.img form rockchip vendor u-boot source code
+==============================================================================
+  > git clone  https://github.com/rockchip-linux/u-boot.git rockchip-uboot
+  > cd rockchip-uboot
+  > make rk3368_defconfig /*chose px5_defconfig if you run a px5 platform here*/
+  > ./mkv8.sh
+
+Compile the upstream U-Boot
+===========================
+  > cd u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- sheep-rk3368_defconfig  all
+
+Package u-boot for miniloader
+================================
+  > ../rockchip-uboot/tools/loaderimage --pack --uboot u-boot.bin u-boot.img
+
+Flash the image by rkdeveloptool
+================================
+rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git
+
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+  > rkdeveloptool db ./rockchip-uboot/rk3368_loader_v2.00.256.bin
+  > rkdeveloptool wl 0x6000 ./rockchip-uboot/trust.img
+  > rkdeveloptool wl 0x4000 ./u-boot/u-boot.img
+  > rkdeveloptool RD
+
+You should be able to get U-Boot log message from boot console:
+
+U-Boot 2017.05-rc3-01094-g9ddd1e8-dirty (May 15 2017 - 15:57:23 +0800)
+
+Model: Rockchip sheep board
+DRAM:  2 GiB
+MMC:   dwmmc@ff0f0000: 0
+Using default environment
+
+In:    serial@ff690000
+Out:   serial@ff690000
+Err:   serial@ff690000
+Net:   Net Initialization Skipped
+No ethernet found.
+Hit any key to stop autoboot:  0
+=>
diff --git a/roms/u-boot/board/rockchip/sheep_rk3368/sheep_rk3368.c b/roms/u-boot/board/rockchip/sheep_rk3368/sheep_rk3368.c
new file mode 100644
index 000000000..b81f97088
--- /dev/null
+++ b/roms/u-boot/board/rockchip/sheep_rk3368/sheep_rk3368.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Andy Yan
+ */
diff --git a/roms/u-boot/board/rockchip/tinker_rk3288/Kconfig b/roms/u-boot/board/rockchip/tinker_rk3288/Kconfig
new file mode 100644
index 000000000..bca6c37bc
--- /dev/null
+++ b/roms/u-boot/board/rockchip/tinker_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TINKER_RK3288
+
+config SYS_BOARD
+	default "tinker_rk3288"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "tinker_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/rockchip/tinker_rk3288/MAINTAINERS b/roms/u-boot/board/rockchip/tinker_rk3288/MAINTAINERS
new file mode 100644
index 000000000..ed5de682c
--- /dev/null
+++ b/roms/u-boot/board/rockchip/tinker_rk3288/MAINTAINERS
@@ -0,0 +1,13 @@
+TINKER-RK3288
+M:	Lin Huang <hl@rock-chips.com>
+S:	Maintained
+F:	board/rockchip/tinker_rk3288
+F:	include/configs/tinker_rk3288.h
+F:	configs/tinker-rk3288_defconfig
+
+TINKER-S-RK3288
+M:	Michael Trimarchi <michael@amarulasolutions.com>
+S:	Maintained
+F:	board/rockchip/tinker_rk3288
+F:	include/configs/tinker_rk3288.h
+F:	configs/tinker-s-rk3288_defconfig
diff --git a/roms/u-boot/board/rockchip/tinker_rk3288/Makefile b/roms/u-boot/board/rockchip/tinker_rk3288/Makefile
new file mode 100644
index 000000000..432367f4e
--- /dev/null
+++ b/roms/u-boot/board/rockchip/tinker_rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= tinker-rk3288.o
diff --git a/roms/u-boot/board/rockchip/tinker_rk3288/tinker-rk3288.c b/roms/u-boot/board/rockchip/tinker_rk3288/tinker-rk3288.c
new file mode 100644
index 000000000..f85209c64
--- /dev/null
+++ b/roms/u-boot/board/rockchip/tinker_rk3288/tinker-rk3288.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <eeprom.h>
+#include <env.h>
+#include <i2c_eeprom.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/io.h>
+
+static int get_ethaddr_from_eeprom(u8 *addr)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev);
+	if (ret)
+		return ret;
+
+	return i2c_eeprom_read(dev, 0, addr, 6);
+}
+
+int rk3288_board_late_init(void)
+{
+	u8 ethaddr[6];
+
+	if (get_ethaddr_from_eeprom(ethaddr))
+		return 0;
+
+	if (is_valid_ethaddr(ethaddr))
+		eth_env_set_enetaddr("ethaddr", ethaddr);
+
+	return 0;
+}
+
+int mmc_get_env_dev(void)
+{
+	u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
+
+	if (bootdevice_brom_id == BROM_BOOTSOURCE_EMMC)
+		return 0;
+
+	return 1;
+}
diff --git a/roms/u-boot/board/ronetix/imx7-cm/Kconfig b/roms/u-boot/board/ronetix/imx7-cm/Kconfig
new file mode 100644
index 000000000..a4bc48f69
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx7-cm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX7_CM
+
+config SYS_BOARD
+	default "imx7-cm"
+
+config SYS_VENDOR
+	default "ronetix"
+
+config SYS_SOC
+	default "mx7"
+
+config SYS_CONFIG_NAME
+	default "imx7-cm"
+
+endif
diff --git a/roms/u-boot/board/ronetix/imx7-cm/MAINTAINERS b/roms/u-boot/board/ronetix/imx7-cm/MAINTAINERS
new file mode 100644
index 000000000..184c88746
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx7-cm/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX7-CM BOARD
+M:	Ilko Iliev <iliev@ronetix.com>
+S:	Maintained
+F:	board/ronetix/imx7_cm/
+F:	include/configs/imx7_cm.h
+F:	configs/imx7_cm_defconfig
\ No newline at end of file
diff --git a/roms/u-boot/board/ronetix/imx7-cm/Makefile b/roms/u-boot/board/ronetix/imx7-cm/Makefile
new file mode 100644
index 000000000..7e08f238a
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx7-cm/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2017 NXP Semiconductors
+
+ifdef CONFIG_SPL_BUILD
+obj-y  += spl.o
+else
+obj-y  += imx7-cm.o
+endif
diff --git a/roms/u-boot/board/ronetix/imx7-cm/README b/roms/u-boot/board/ronetix/imx7-cm/README
new file mode 100644
index 000000000..43e8c4fb7
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx7-cm/README
@@ -0,0 +1,11 @@
+U-Boot for the Ronetix i.MX7-CM board
+
+Build U-Boot
+============
+$ make imx7_cm_defconfig
+$ make
+
+Burn the images to a SD card
+============================
+$ sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync
+$ sudo dd if=u-boot-dtb.img  of=/dev/sdX bs=1k seek=69; sync
diff --git a/roms/u-boot/board/ronetix/imx7-cm/imx7-cm.c b/roms/u-boot/board/ronetix/imx7-cm/imx7-cm.c
new file mode 100644
index 000000000..c23097f04
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx7-cm/imx7-cm.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Ronetix GmbH
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+	unsigned int reg, rev;
+
+	ret = pmic_get("pmic@8", &dev);
+	if (ret == -ENODEV) {
+		puts("No pmic\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
+
+	reg = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+	rev = pmic_reg_read(dev, PFUZE3000_REVID);
+	printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev);
+
+	/* disable Low Power Mode during standby mode */
+	reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
+	reg |= 0x1;
+	pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
+
+	/* SW1A/1B mode set to APS/APS */
+	reg = 0x8;
+	pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
+	pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
+
+	/* SW1A/1B standby voltage set to 1.025V */
+	reg = 0xd;
+	pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
+	pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
+
+	/* decrease SW1B normal voltage to 0.975V */
+	reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
+	reg &= ~0x1f;
+	reg |= PFUZE3000_SW1AB_SETP(975);
+	pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
+
+	return 0;
+}
+
+static int setup_fec(void)
+{
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_fec();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: iMX7-CM\n");
+	return 0;
+}
diff --git a/roms/u-boot/board/ronetix/imx7-cm/spl.c b/roms/u-boot/board/ronetix/imx7-cm/spl.c
new file mode 100644
index 000000000..d36f734e4
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx7-cm/spl.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Ronetix GmbH
+ *
+ * Author: Ilko Iliev <iliev@ronetix.at>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch-mx7/mx7-ddr.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <spl.h>
+
+static struct ddrc ddrc_regs_val = {
+	.mstr		= 0x01040001,
+	.rfshtmg	= 0x00400046,
+	.init1		= 0x00690000,
+	.init0		= 0x00020083,
+	.init3		= 0x09300004,
+	.init4		= 0x04080000,
+	.init5		= 0x00100004,
+	.rankctl	= 0x0000033F,
+	.dramtmg0	= 0x09081109,
+	.dramtmg1	= 0x0007020d,
+	.dramtmg2	= 0x03040407,
+	.dramtmg3	= 0x00002006,
+	.dramtmg4	= 0x04020205,
+	.dramtmg5	= 0x03030202,
+	.dramtmg8	= 0x00000803,
+	.zqctl0		= 0x00800020,
+	.dfitmg0	= 0x02098204,
+	.dfitmg1	= 0x00030303,
+	.dfiupd0	= 0x80400003,
+	.dfiupd1	= 0x00100020,
+	.dfiupd2	= 0x80100004,
+	.addrmap4	= 0x00000F0F,
+	.odtcfg		= 0x06000604,
+	.odtmap		= 0x00000001,
+	.rfshtmg	= 0x00400046,
+	.dramtmg0	= 0x09081109,
+	.addrmap0	= 0x0000001f,
+	.addrmap1	= 0x00080808,
+	.addrmap4	= 0x00000f0f,
+	.addrmap5	= 0x07070707,
+	.addrmap6	= 0x0f0f0707,
+};
+
+static struct ddrc_mp ddrc_mp_val = {
+	.pctrl_0	= 0x00000001,
+};
+
+static struct ddr_phy ddr_phy_regs_val = {
+	.phy_con0	= 0x17420f40,
+	.phy_con1	= 0x10210100,
+	.phy_con4	= 0x00060807,
+	.mdll_con0	= 0x1010007e,
+	.drvds_con0	= 0x00000d6e,
+	.cmd_sdll_con0	= 0x00000010,
+	.offset_lp_con0	= 0x0000000f,
+	.offset_rd_con0	= 0x0a0a0a0a,
+	.offset_wr_con0	= 0x06060606,
+};
+
+static struct mx7_calibration calib_param = {
+	.num_val	= 5,
+	.values		= {
+		0x0E407304,
+		0x0E447304,
+		0x0E447306,
+		0x0E447304,
+		0x0E447304,
+	},
+};
+
+static void ddr_init(void)
+{
+	mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, &calib_param);
+}
+
+#define UART_PAD_CTRL		(PAD_CTL_DSE_3P3V_49OHM | \
+				PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+void uart1_pads_set(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+void board_init_f(ulong dummy)
+{
+	arch_cpu_init();
+
+	uart1_pads_set();
+
+	timer_init();
+
+	preloader_console_init();
+
+	ddr_init();
+
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
+
+void reset_cpu(void)
+{
+}
+
+#define USDHC_PAD_CTRL		(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+				PAD_CTL_HYS | PAD_CTL_PUE | \
+				PAD_CTL_PUS_PU47KOHM)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+void usdhc1_pads_set(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg = {
+	USDHC1_BASE_ADDR, 0, 4
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	usdhc1_pads_set();
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
diff --git a/roms/u-boot/board/ronetix/imx8mq-cm/Kconfig b/roms/u-boot/board/ronetix/imx8mq-cm/Kconfig
new file mode 100644
index 000000000..9dd6a86ad
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx8mq-cm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MQ_CM
+
+config SYS_BOARD
+	default "imx8mq-cm"
+
+config SYS_VENDOR
+	default "ronetix"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_cm"
+
+endif
diff --git a/roms/u-boot/board/ronetix/imx8mq-cm/MAINTAINERS b/roms/u-boot/board/ronetix/imx8mq-cm/MAINTAINERS
new file mode 100644
index 000000000..962a83267
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx8mq-cm/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8MQ-CM BOARD
+M:	Ilko Iliev <iliev@ronetix.at>
+S:	Maintained
+F:	board/ronetix/imx8mq-cm/
+F:	include/configs/imx8mq_cm.h
+F:	configs/imx8mq_cm_defconfig
diff --git a/roms/u-boot/board/ronetix/imx8mq-cm/Makefile b/roms/u-boot/board/ronetix/imx8mq-cm/Makefile
new file mode 100644
index 000000000..0d9d8e646
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx8mq-cm/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mq_cm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/roms/u-boot/board/ronetix/imx8mq-cm/README b/roms/u-boot/board/ronetix/imx8mq-cm/README
new file mode 100644
index 000000000..1d43fa5f4
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx8mq-cm/README
@@ -0,0 +1,42 @@
+U-Boot for the Ronetix i.MX8MQ-CM board
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ cd imx-atf
+$ git checkout imx_4.19.35_1.0.0
+$ make PLAT=imx8mq bl31
+$ cd ..
+$ cp imx-atf/build/imx8mq/release/bl31.bin .
+
+Get the ddr firmware
+====================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+$ chmod +x firmware-imx-8.9.bin
+$ ./firmware-imx-8.9.bin
+$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin .
+
+Build U-Boot
+============
+$ /opt/cross/aarch64-ronetix-linux-9.2/bin/aarch64-ronetix-linux-gnu-
+$ make imx8mq_cm_defconfig
+$ make
+
+Burn the flash.bin to MicroSD card offset 33KB
+==============================================
+$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=sync
+$sudo dd if=u-boot.itb of=/dev/sd[x] bs=1024 seek=384 conv=sync
+
+Boot
+====
+Set Boot switch on base board iMX8M-MB to SD boot:
+    SW1[8:1]: OFF OFF OFF ON - OFF ON OFF OFF
+    SW4[2:1]: OFF OFF
+    J4: 1,2 - open; 3,4 - close; 5,6 - open
diff --git a/roms/u-boot/board/ronetix/imx8mq-cm/imx8mq_cm.c b/roms/u-boot/board/ronetix/imx8mq-cm/imx8mq_cm.c
new file mode 100644
index 000000000..9805a3a7d
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx8mq-cm/imx8mq_cm.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+
+int board_init(void)
+{
+	setup_fec();
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+		env_set("board_name", "imx8mq-cm");
+		env_set("board_rev", "v2.0");
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg b/roms/u-boot/board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg
new file mode 100644
index 000000000..268b5ae71
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#define __ASSEMBLY__
+
+BOOT_FROM	sd
+LOADER		mkimage.flash.mkimage	0x7E1000
\ No newline at end of file
diff --git a/roms/u-boot/board/ronetix/imx8mq-cm/lpddr4_timing.c b/roms/u-boot/board/ronetix/imx8mq-cm/lpddr4_timing.c
new file mode 100644
index 000000000..685600ee6
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx8mq-cm/lpddr4_timing.c
@@ -0,0 +1,1866 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+#define WR_POST_EXT_3200	/* recommend to define */
+
+struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/* Start to config, default 3200mbps */
+	{ DDRC_DBG1(0), 0x00000001 },
+	{ DDRC_PWRCTL(0), 0x00000001 },
+	{ DDRC_MSTR(0), 0xa1080020 },
+	{ DDRC_MSTR2(0), 0x00000000 },
+	{ DDRC_RFSHTMG(0), 0x006100E0 },
+	{ DDRC_INIT0(0), 0xc003061c },
+	{ DDRC_INIT1(0), 0x9e0000 },
+	{ DDRC_INIT3(0), 0xd4002d },
+#ifdef WR_POST_EXT_3200
+	{ DDRC_INIT4(0), 0x00330008 },
+#else
+	{ DDRC_INIT4(0), 0x00310008 },
+#endif
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0016004a },
+
+	{ DDRC_DRAMTMG0(0), 0x1A201B22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00C0C000 },
+	{ DDRC_DRAMTMG4(0), 0x0F04080F },
+	{ DDRC_DRAMTMG5(0), 0x02040C0C },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x00000401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0C100002 },
+	{ DDRC_DRAMTMG14(0), 0x00000096 },
+	{ DDRC_DRAMTMG17(0), 0x00A00050 },
+
+	{ DDRC_ZQCTL0(0), 0xc3200018 },
+	{ DDRC_ZQCTL1(0), 0x028061A8 },
+	{ DDRC_ZQCTL2(0), 0x00000000 },
+
+	{ DDRC_DFITMG0(0), 0x0497820A },
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xE0400018 },
+	{ DDRC_DFIUPD1(0), 0x00DF00E4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x00000011 },
+	{ DDRC_DFITMG2(0), 0x0000170A },
+
+	{ DDRC_DBICTL(0), 0x00000001 },
+	{ DDRC_DFIPHYMSTR(0), 0x00000001 },
+	{ DDRC_RANKCTL(0), 0x00000639 },
+	{ DDRC_DRAMTMG2(0), 0x70e1617 },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), 0x0000001F },
+	{ DDRC_ADDRMAP3(0), 0x00000000 },
+	{ DDRC_ADDRMAP4(0), 0x00001F1F },
+	/* bank interleave */
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	{ DDRC_ADDRMAP6(0), 0xf070707 },
+
+	/* performance setting */
+	{ DDRC_ODTCFG(0), 0x0b060908 },
+	{ DDRC_ODTMAP(0), 0x00000000 },
+	{ DDRC_SCHED(0), 0x29001505 },
+	{ DDRC_SCHED1(0), 0x0000002c },
+	{ DDRC_PERFHPR1(0), 0x5900575b },
+	/* 150T starve and 0x90 max tran len */
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	/* 300T starve and 0x10 max tran len */
+	{ DDRC_PERFWR1(0), 0x1000012c },
+	{ DDRC_DBG0(0), 0x00000016 },
+	{ DDRC_DBG1(0), 0x00000000 },
+	{ DDRC_DBGCMD(0), 0x00000000 },
+	{ DDRC_SWCTL(0), 0x00000001 },
+	{ DDRC_POISONCFG(0), 0x00000011 },
+	{ DDRC_PCCFG(0), 0x00000111 },
+	{ DDRC_PCFGR_0(0), 0x000010f3 },
+	{ DDRC_PCFGW_0(0), 0x000072ff },
+	{ DDRC_PCTRL_0(0), 0x00000001 },
+	/* disable Read Qos*/
+	{ DDRC_PCFGQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	/* disable Write Qos*/
+	{ DDRC_PCFGWQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0x0000ffff },
+
+	/* Frequency 1: 400mbps */
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0a040305 },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x00030407 },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0203060b },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x02040202 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x02030202 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x00000301 },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x00000013 },
+	{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x0014000a },
+	{ DDRC_FREQ1_DERATEINT(0), 0x00007d00 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x3818200 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x00000100 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0xc0012 },
+	{ DDRC_FREQ1_INIT3(0), 0x840000 },
+	{ DDRC_FREQ1_INIT4(0), 0x310000 },
+	{ DDRC_FREQ1_INIT6(0), 0x66004a },
+	{ DDRC_FREQ1_INIT7(0), 0x16004a },
+
+	/* Frequency 2: 100mbps */
+	{ DDRC_FREQ2_DRAMTMG0(0), 0xa010102 },
+	{ DDRC_FREQ2_DRAMTMG1(0), 0x30404 },
+	{ DDRC_FREQ2_DRAMTMG2(0), 0x203060b },
+	{ DDRC_FREQ2_DRAMTMG3(0), 0x505000 },
+	{ DDRC_FREQ2_DRAMTMG4(0), 0x2040202 },
+	{ DDRC_FREQ2_DRAMTMG5(0), 0x2030202 },
+	{ DDRC_FREQ2_DRAMTMG6(0), 0x1010004 },
+	{ DDRC_FREQ2_DRAMTMG7(0), 0x301 },
+	{ DDRC_FREQ2_DRAMTMG14(0), 0x5 },
+	{ DDRC_FREQ2_DRAMTMG17(0), 0x50003 },
+	{ DDRC_FREQ2_DERATEINT(0), 0x1f40 },
+	{ DDRC_FREQ2_DFITMG0(0), 0x3818200 },
+	{ DDRC_FREQ2_DFITMG2(0), 0x00000100 },
+	{ DDRC_FREQ2_RFSHTMG(0), 0x30005 },
+	{ DDRC_FREQ2_INIT3(0), 0x840000 },
+	{ DDRC_FREQ2_INIT4(0), 0x310000 },
+	{ DDRC_FREQ2_INIT6(0), 0x66004a },
+	{ DDRC_FREQ2_INIT7(0), 0x16004a },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x2 },
+	{ 0x110a3, 0x3 },
+	{ 0x110a4, 0x4 },
+	{ 0x110a5, 0x5 },
+	{ 0x110a6, 0x6 },
+	{ 0x110a7, 0x7 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x2 },
+	{ 0x120a3, 0x3 },
+	{ 0x120a4, 0x4 },
+	{ 0x120a5, 0x5 },
+	{ 0x120a6, 0x6 },
+	{ 0x120a7, 0x7 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x220024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x320 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x200c7, 0x80 },
+	{ 0x1200c7, 0x80 },
+	{ 0x2200c7, 0x80 },
+	{ 0x200ca, 0x106 },
+	{ 0x1200ca, 0x106 },
+	{ 0x2200ca, 0x106 },
+	{ 0x20110, 0x2 },
+	{ 0x20111, 0x3 },
+	{ 0x20112, 0x4 },
+	{ 0x20113, 0x5 },
+	{ 0x20114, 0x0 },
+	{ 0x20115, 0x1 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block parameter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block parameter for training firmware */
+struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block parameter for training firmware */
+struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block parameter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xf },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a7, 0x0 },
+	{ 0x900a8, 0x790 },
+	{ 0x900a9, 0x11a },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x7b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x0 },
+	{ 0x900b1, 0x7c8 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xc },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x0 },
+	{ 0x90169, 0x8 },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x448 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
+	{ 0x9016e, 0x7c0 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x7c8 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x7d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x2003a, 0x2 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P1 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.fsp_table = { 3200, 400, 100, },
+};
diff --git a/roms/u-boot/board/ronetix/imx8mq-cm/spl.c b/roms/u-boot/board/ronetix/imx8mq-cm/spl.c
new file mode 100644
index 000000000..c32a06f12
--- /dev/null
+++ b/roms/u-boot/board/ronetix/imx8mq-cm/spl.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/delay.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void spl_dram_init(void)
+{
+	/* ddr init */
+	ddr_init(&dram_timing);
+}
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+							 ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+							 ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers(%d)"
+					" than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/ronetix/pm9261/Kconfig b/roms/u-boot/board/ronetix/pm9261/Kconfig
new file mode 100644
index 000000000..8c5419810
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9261/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PM9261
+
+config SYS_BOARD
+	default "pm9261"
+
+config SYS_VENDOR
+	default "ronetix"
+
+config SYS_CONFIG_NAME
+	default "pm9261"
+
+endif
diff --git a/roms/u-boot/board/ronetix/pm9261/MAINTAINERS b/roms/u-boot/board/ronetix/pm9261/MAINTAINERS
new file mode 100644
index 000000000..a09b6c073
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9261/MAINTAINERS
@@ -0,0 +1,6 @@
+PM9261 BOARD
+M:	Ilko Iliev <iliev@ronetix.at>
+S:	Maintained
+F:	board/ronetix/pm9261/
+F:	include/configs/pm9261.h
+F:	configs/pm9261_defconfig
diff --git a/roms/u-boot/board/ronetix/pm9261/Makefile b/roms/u-boot/board/ronetix/pm9261/Makefile
new file mode 100644
index 000000000..9fa3dfb66
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9261/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+# Ilko Iliev <www.ronetix.at>
+
+obj-y += pm9261.o
+obj-$(CONFIG_RED_LED) += led.o
diff --git a/roms/u-boot/board/ronetix/pm9261/led.c b/roms/u-boot/board/ronetix/pm9261/led.c
new file mode 100644
index 000000000..df955830b
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9261/led.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <asm/gpio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+
+void coloured_LED_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+	gpio_direction_output(CONFIG_RED_LED, 1);
+	gpio_direction_output(CONFIG_GREEN_LED, 1);
+	gpio_direction_output(CONFIG_YELLOW_LED, 1);
+
+	gpio_set_value(CONFIG_RED_LED, 0);
+	gpio_set_value(CONFIG_GREEN_LED, 1);
+	gpio_set_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/roms/u-boot/board/ronetix/pm9261/pm9261.c b/roms/u-boot/board/ronetix/pm9261/pm9261.c
new file mode 100644
index 000000000..5be2c5e19
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9261/pm9261.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
+#include <net.h>
+#endif
+#include <netdev.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9261_nand_hw_init(void)
+{
+	unsigned long csa;
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+	/* Enable NandFlash */
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* NANDOE */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* NANDWE */
+}
+#endif
+
+
+#ifdef CONFIG_DRIVER_DM9000
+static void pm9261_dm9000_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	/* Configure SMC CS2 for DM9000 */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[2].setup);
+
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
+		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
+		&smc->cs[2].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
+		&smc->cs[2].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+		AT91_SMC_MODE_TDF_CYCLE(1),
+		&smc->cs[2].mode);
+
+	/* Configure Interrupt pin as input, no pull-up */
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of PM9261-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PM9261;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	pm9261_nand_hw_init();
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+	pm9261_dm9000_hw_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(struct bd_info *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+				PHYS_SDRAM_SIZE);
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_DRIVER_DM9000
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init();
+#endif
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard (void)
+{
+	char buf[32];
+
+	printf ("Board : Ronetix PM9261\n");
+	printf ("Crystal frequency: %8s MHz\n",
+					strmhz(buf, get_main_clk_rate()));
+	printf ("CPU clock        : %8s MHz\n",
+					strmhz(buf, get_cpu_clk_rate()));
+	printf ("Master clock     : %8s MHz\n",
+					strmhz(buf, get_mck_clk_rate()));
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/ronetix/pm9263/Kconfig b/roms/u-boot/board/ronetix/pm9263/Kconfig
new file mode 100644
index 000000000..5b47d3484
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9263/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PM9263
+
+config SYS_BOARD
+	default "pm9263"
+
+config SYS_VENDOR
+	default "ronetix"
+
+config SYS_CONFIG_NAME
+	default "pm9263"
+
+endif
diff --git a/roms/u-boot/board/ronetix/pm9263/MAINTAINERS b/roms/u-boot/board/ronetix/pm9263/MAINTAINERS
new file mode 100644
index 000000000..f26e82ace
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9263/MAINTAINERS
@@ -0,0 +1,6 @@
+PM9263 BOARD
+M:	Ilko Iliev <iliev@ronetix.at>
+S:	Maintained
+F:	board/ronetix/pm9263/
+F:	include/configs/pm9263.h
+F:	configs/pm9263_defconfig
diff --git a/roms/u-boot/board/ronetix/pm9263/Makefile b/roms/u-boot/board/ronetix/pm9263/Makefile
new file mode 100644
index 000000000..e81c57e21
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9263/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+# Ilko Iliev <www.ronetix.at>
+
+obj-y += pm9263.o
+obj-$(CONFIG_AT91_LED) += led.o
diff --git a/roms/u-boot/board/ronetix/pm9263/led.c b/roms/u-boot/board/ronetix/pm9263/led.c
new file mode 100644
index 000000000..524b4afcb
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9263/led.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <asm/gpio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+
+void coloured_LED_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+
+	gpio_direction_output(CONFIG_RED_LED, 1);
+	gpio_direction_output(CONFIG_GREEN_LED, 1);
+
+	gpio_set_value(CONFIG_RED_LED, 0);
+	gpio_set_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/roms/u-boot/board/ronetix/pm9263/pm9263.c b/roms/u-boot/board/ronetix/pm9263/pm9263.c
new file mode 100644
index 000000000..95c0dec4d
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9263/pm9263.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9263_nand_hw_init(void)
+{
+	unsigned long csa;
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+	/* Enable NandFlash */
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void pm9263_macb_hw_init(void)
+{
+	/*
+	 * PB27 enables the 50MHz oscillator for Ethernet PHY
+	 * 1 - enable
+	 * 0 - disable
+	 */
+	at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
+	at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
+
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PC25) => PHY normal mode (not Test mode)
+	 *	ERX0 (PE25) => PHY ADDR0
+	 *	ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+
+	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
+
+	/* Re-enable pull-up */
+	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
+
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+
+#ifdef CONFIG_LCD_IN_PSRAM
+
+#define PSRAM_CRE_PIN	AT91_PIO_PORTB, 29
+#define PSRAM_CTRL_REG	(PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
+
+/* Initialize the PSRAM memory */
+static int pm9263_lcd_hw_psram_init(void)
+{
+	unsigned long csa;
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+	/* Enable CS3  3.3v, no pull-ups */
+	csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
+		AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
+
+	writel(csa, &matrix->csa[1]);
+
+	/* Configure SMC1 CS0 for PSRAM - 16-bit */
+	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[0].setup);
+
+	writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
+		AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
+		&smc->cs[0].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+		&smc->cs[0].cycle);
+
+	writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
+		&smc->cs[0].mode);
+
+	/* setup PB29 as output */
+	at91_set_pio_output(PSRAM_CRE_PIN, 1);
+
+	at91_set_pio_value(PSRAM_CRE_PIN, 0);	/* set PSRAM_CRE_PIN to '0' */
+
+	/* PSRAM: write BCR */
+	readw(PSRAM_CTRL_REG);
+	readw(PSRAM_CTRL_REG);
+	writew(1, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
+	writew(0x9d4f, PSRAM_CTRL_REG);	/* write the BCR */
+
+	/* write RCR of the PSRAM */
+	readw(PSRAM_CTRL_REG);
+	readw(PSRAM_CTRL_REG);
+	writew(0, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
+	/* set RCR; 0x10-async mode,0x90-page mode */
+	writew(0x90, PSRAM_CTRL_REG);
+
+	/*
+	 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
+	 * MT45W2M16B - CRE must be 0
+	 * MT45W2M16A - CRE must be 1
+	 */
+	writew(0x1234, PHYS_PSRAM);
+	writew(0x5678, PHYS_PSRAM + 2);
+
+	/* test if the chip is MT45W2M16B */
+	if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
+		/* try with CRE=1 (MT45W2M16A) */
+		at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
+
+		/* write RCR of the PSRAM */
+		readw(PSRAM_CTRL_REG);
+		readw(PSRAM_CTRL_REG);
+		writew(0, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
+		/* set RCR;0x10-async mode,0x90-page mode */
+		writew(0x90, PSRAM_CTRL_REG);
+
+
+		writew(0x1234, PHYS_PSRAM);
+		writew(0x5678, PHYS_PSRAM+2);
+		if ((readw(PHYS_PSRAM) != 0x1234)
+		  || (readw(PHYS_PSRAM + 2) != 0x5678))
+			return 1;
+
+	}
+
+	/* Bus matrix */
+	writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
+	writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
+
+	return 0;
+}
+#endif
+
+static void pm9263_lcd_hw_init(void)
+{
+	/* Power Control */
+	at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);	/* power down */
+
+#ifdef CONFIG_LCD_IN_PSRAM
+	/* initialize te PSRAM */
+	int stat = pm9263_lcd_hw_psram_init();
+
+	gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
+#else
+	gd->fb_base = ATMEL_BASE_SRAM0;
+#endif
+
+}
+
+#endif /* CONFIG_LCD */
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of AT91SAM9263EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PM9263;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	pm9263_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	pm9263_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	pm9263_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+				PHYS_SDRAM_SIZE);
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
+#endif
+	return rc;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard (void)
+{
+	char *ss;
+
+	printf ("Board : Ronetix PM9263\n");
+
+	switch (gd->fb_base) {
+	case PHYS_PSRAM:
+		ss = "(PSRAM)";
+		break;
+
+	case ATMEL_BASE_SRAM0:
+		ss = "(Internal SRAM)";
+		break;
+
+	default:
+		ss = "";
+		break;
+	}
+	printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
+
+	printf ("\n");
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/ronetix/pm9g45/Kconfig b/roms/u-boot/board/ronetix/pm9g45/Kconfig
new file mode 100644
index 000000000..ad5309f81
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9g45/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PM9G45
+
+config SYS_BOARD
+	default "pm9g45"
+
+config SYS_VENDOR
+	default "ronetix"
+
+config SYS_CONFIG_NAME
+	default "pm9g45"
+
+endif
diff --git a/roms/u-boot/board/ronetix/pm9g45/MAINTAINERS b/roms/u-boot/board/ronetix/pm9g45/MAINTAINERS
new file mode 100644
index 000000000..255a357fa
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9g45/MAINTAINERS
@@ -0,0 +1,6 @@
+PM9G45 BOARD
+M:	Ilko Iliev <iliev@ronetix.at>
+S:	Maintained
+F:	board/ronetix/pm9g45/
+F:	include/configs/pm9g45.h
+F:	configs/pm9g45_defconfig
diff --git a/roms/u-boot/board/ronetix/pm9g45/Makefile b/roms/u-boot/board/ronetix/pm9g45/Makefile
new file mode 100644
index 000000000..04795c197
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9g45/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+
+obj-y += pm9g45.o
diff --git a/roms/u-boot/board/ronetix/pm9g45/pm9g45.c b/roms/u-boot/board/ronetix/pm9g45/pm9g45.c
new file mode 100644
index 000000000..8d5825c7f
--- /dev/null
+++ b/roms/u-boot/board/ronetix/pm9g45/pm9g45.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Ilko Iliev <iliev@ronetix.at>
+ * Asen Dimov <dimov@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9g45_nand_hw_init(void)
+{
+	unsigned long csa;
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->ccr[6]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
+		&smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_DBW_8 |
+		AT91_SMC_MODE_TDF_CYCLE(3),
+		&smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+#ifdef CONFIG_SYS_NAND_READY_PIN
+	/* Configure RDY/BSY */
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+#endif
+
+	/* Enable NandFlash */
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void pm9g45_macb_hw_init(void)
+{
+	/*
+	 * PD2 enables the 50MHz oscillator for Ethernet PHY
+	 * 1 - enable
+	 * 0 - disable
+	 */
+	at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
+	at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
+
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA15) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA12) => PHY ADDR0
+	 *	ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
+
+	/* Re-enable pull-up */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+
+	at91_macb_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+
+	at91_seriald_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of AT91SAM9M10G45EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	pm9g45_nand_hw_init();
+#endif
+
+#ifdef CONFIG_MACB
+	pm9g45_macb_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init();
+#endif
+}
+#endif
+
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
+#endif
+	return rc;
+}
diff --git a/roms/u-boot/board/sagem/f@st1704/Kconfig b/roms/u-boot/board/sagem/f@st1704/Kconfig
new file mode 100644
index 000000000..4566fcc9c
--- /dev/null
+++ b/roms/u-boot/board/sagem/f@st1704/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_SAGEM_FAST1704
+
+config SYS_BOARD
+	default "f@st1704"
+
+config SYS_VENDOR
+	default "sagem"
+
+config SYS_CONFIG_NAME
+	default "sagem_f@st1704"
+
+endif
diff --git a/roms/u-boot/board/sagem/f@st1704/MAINTAINERS b/roms/u-boot/board/sagem/f@st1704/MAINTAINERS
new file mode 100644
index 000000000..72e1c5ccd
--- /dev/null
+++ b/roms/u-boot/board/sagem/f@st1704/MAINTAINERS
@@ -0,0 +1,6 @@
+SAGEM F@ST1704 BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/sagem/f@st1704/
+F:	include/configs/sagem_f@st1704.h
+F:	configs/sagem_f@st1704_ram_defconfig
diff --git a/roms/u-boot/board/sagem/f@st1704/Makefile b/roms/u-boot/board/sagem/f@st1704/Makefile
new file mode 100644
index 000000000..08d44a0b8
--- /dev/null
+++ b/roms/u-boot/board/sagem/f@st1704/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += f@st1704.o
diff --git a/roms/u-boot/board/sagem/f@st1704/f@st1704.c b/roms/u-boot/board/sagem/f@st1704/f@st1704.c
new file mode 100644
index 000000000..1e4b7281d
--- /dev/null
+++ b/roms/u-boot/board/sagem/f@st1704/f@st1704.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/samsung/arndale/Kconfig b/roms/u-boot/board/samsung/arndale/Kconfig
new file mode 100644
index 000000000..b620974ba
--- /dev/null
+++ b/roms/u-boot/board/samsung/arndale/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ARNDALE
+
+config SYS_BOARD
+	default "arndale"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "arndale"
+
+endif
diff --git a/roms/u-boot/board/samsung/arndale/MAINTAINERS b/roms/u-boot/board/samsung/arndale/MAINTAINERS
new file mode 100644
index 000000000..aa64c7a18
--- /dev/null
+++ b/roms/u-boot/board/samsung/arndale/MAINTAINERS
@@ -0,0 +1,6 @@
+ARNDALE BOARD
+M:	Krzysztof Kozlowski <krzk@kernel.org>
+S:	Maintained
+F:	board/samsung/arndale/
+F:	include/configs/arndale.h
+F:	configs/arndale_defconfig
diff --git a/roms/u-boot/board/samsung/arndale/Makefile b/roms/u-boot/board/samsung/arndale/Makefile
new file mode 100644
index 000000000..1fd6e180b
--- /dev/null
+++ b/roms/u-boot/board/samsung/arndale/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2013 Samsung Electronics
+
+obj-y	+= arndale_spl.o
+obj-y	+= arndale.o
diff --git a/roms/u-boot/board/samsung/arndale/arndale.c b/roms/u-boot/board/samsung/arndale/arndale.c
new file mode 100644
index 000000000..b43242fd3
--- /dev/null
+++ b/roms/u-boot/board/samsung/arndale/arndale.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <log.h>
+#include <usb.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/power.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB_EHCI_EXYNOS
+int board_usb_init(int index, enum usb_init_type init)
+{
+	/* Configure gpios for usb 3503 hub:
+	 * disconnect, toggle reset and connect
+	 */
+	gpio_request(EXYNOS5_GPIO_D17, "usb_connect");
+	gpio_request(EXYNOS5_GPIO_X35, "usb_reset");
+	gpio_direction_output(EXYNOS5_GPIO_D17, 0);
+	gpio_direction_output(EXYNOS5_GPIO_X35, 0);
+
+	gpio_direction_output(EXYNOS5_GPIO_X35, 1);
+	gpio_direction_output(EXYNOS5_GPIO_D17, 1);
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+	return 0;
+}
+
+int dram_init(void)
+{
+	int i;
+	u32 addr;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+	}
+	return 0;
+}
+
+int power_init_board(void)
+{
+	set_ps_hold_ctrl();
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	int i;
+	u32 addr, size;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+		gd->bd->bi_dram[i].start = addr;
+		gd->bd->bi_dram[i].size = size;
+	}
+
+	return 0;
+}
+
+static int board_uart_init(void)
+{
+	int err = 0, uart_id;
+
+	for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+		err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+		if (err) {
+			debug("UART%d not configured\n",
+			      (uart_id - PERIPH_ID_UART0));
+			return err;
+		}
+	}
+	return err;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	int err;
+
+	err = board_uart_init();
+	if (err) {
+		debug("UART init failed\n");
+		return err;
+	}
+	return err;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("\nBoard: Arndale\n");
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_S5P_PA_SYSRAM
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+	writel(addr, CONFIG_S5P_PA_SYSRAM);
+
+	/* make sure this write is really executed */
+	__asm__ volatile ("dsb\n");
+}
+#endif
diff --git a/roms/u-boot/board/samsung/arndale/arndale_spl.c b/roms/u-boot/board/samsung/arndale/arndale_spl.c
new file mode 100644
index 000000000..6ad0273e0
--- /dev/null
+++ b/roms/u-boot/board/samsung/arndale/arndale_spl.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#include <common.h>
+#include <asm/arch/spl.h>
+
+#define SIGNATURE	0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+		__section(".machine_param") = {
+	.signature	= SIGNATURE,
+	.version	= 1,
+	.params		= "vmubfasirM",
+	.size		= sizeof(machine_param),
+
+	.mem_iv_size	= 0x1f,
+	.mem_type	= DDR_MODE_DDR3,
+
+	/*
+	 * Set uboot_size to 0x100000 bytes.
+	 *
+	 * This is an overly conservative value chosen to accommodate all
+	 * possible U-Boot image.  You are advised to set this value to a
+	 * smaller realistic size via scripts that modifies the .machine_param
+	 * section of output U-Boot image.
+	 */
+	.uboot_size	= 0x100000,
+
+	.boot_source	= BOOT_MODE_OM,
+	.frequency_mhz	= 800,
+	.arm_freq_mhz	= 1000,
+	.serial_base	= 0x12c30000,
+	.i2c_base	= 0x12c60000,
+	.mem_manuf	= MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+	if (machine_param.signature != SIGNATURE) {
+		/* Will hang if SIGNATURE dont match */
+		while (1)
+			;
+	}
+
+	return &machine_param;
+}
diff --git a/roms/u-boot/board/samsung/common/Makefile b/roms/u-boot/board/samsung/common/Makefile
new file mode 100644
index 000000000..3593c77cb
--- /dev/null
+++ b/roms/u-boot/board/samsung/common/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2012 Samsung Electronics
+# Lukasz Majewski <l.majewski@samsung.com>
+
+obj-$(CONFIG_USB_GADGET_DOWNLOAD) += gadget.o
+obj-$(CONFIG_MISC_COMMON) += misc.o
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_BOARD_COMMON)	+= board.o
+ifdef CONFIG_EXYNOS5_DT
+obj-y += exynos5-dt.o
+obj-$(CONFIG_BOARD_TYPES) += exynos5-dt-types.o
+endif
+endif
diff --git a/roms/u-boot/board/samsung/common/board.c b/roms/u-boot/board/samsung/common/board.c
new file mode 100644
index 000000000..104d2a657
--- /dev/null
+++ b/roms/u-boot/board/samsung/common/board.c
@@ -0,0 +1,394 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013 SAMSUNG Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <env.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <spi.h>
+#include <tmu.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/board.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/system.h>
+#include <asm/arch/sromc.h>
+#include <lcd.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <stdio_dev.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+#include <linux/delay.h>
+#include <samsung/misc.h>
+#include <dm/pinctrl.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int exynos_early_init_f(void)
+{
+	return 0;
+}
+
+__weak int exynos_power_init(void)
+{
+	return 0;
+}
+
+/**
+ * get_boot_mmc_dev() - read boot MMC device id from XOM[7:5] pins.
+ */
+static int get_boot_mmc_dev(void)
+{
+	u32 mode = readl(EXYNOS4_OP_MODE) & 0x1C;
+
+	if (mode == 0x04)
+		return 2; /* MMC2: SD */
+
+	/* MMC0: eMMC or unknown */
+	return 0;
+}
+
+#if defined CONFIG_EXYNOS_TMU
+/* Boot Time Thermal Analysis for SoC temperature threshold breach */
+static void boot_temp_check(void)
+{
+	int temp;
+
+	switch (tmu_monitor(&temp)) {
+	case TMU_STATUS_NORMAL:
+		break;
+	case TMU_STATUS_TRIPPED:
+		/*
+		 * Status TRIPPED ans WARNING means corresponding threshold
+		 * breach
+		 */
+		puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
+		set_ps_hold_ctrl();
+		hang();
+		break;
+	case TMU_STATUS_WARNING:
+		puts("EXYNOS_TMU: WARNING! Temperature very high\n");
+		break;
+	case TMU_STATUS_INIT:
+		/*
+		 * TMU_STATUS_INIT means something is wrong with temperature
+		 * sensing and TMU status was changed back from NORMAL to INIT.
+		 */
+		puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n");
+		break;
+	default:
+		debug("EXYNOS_TMU: Unknown TMU state\n");
+	}
+}
+#endif
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#if defined CONFIG_EXYNOS_TMU
+	if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
+		debug("%s: Failed to init TMU\n", __func__);
+		return -1;
+	}
+	boot_temp_check();
+#endif
+#ifdef CONFIG_TZSW_RESERVED_DRAM_SIZE
+	/* The last few MB of memory can be reserved for secure firmware */
+	ulong size = CONFIG_TZSW_RESERVED_DRAM_SIZE;
+
+	gd->ram_size -= size;
+	gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size;
+#endif
+	return exynos_init();
+}
+
+int dram_init(void)
+{
+	unsigned int i;
+	unsigned long addr;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+	}
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	unsigned int i;
+	unsigned long addr, size;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+		gd->bd->bi_dram[i].start = addr;
+		gd->bd->bi_dram[i].size = size;
+	}
+
+	return 0;
+}
+
+static int board_uart_init(void)
+{
+#ifndef CONFIG_PINCTRL_EXYNOS
+	int err, uart_id, ret = 0;
+
+	for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+		err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+		if (err) {
+			debug("UART%d not configured\n",
+			      (uart_id - PERIPH_ID_UART0));
+			ret |= err;
+		}
+	}
+	return ret;
+#else
+	return 0;
+#endif
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	int err;
+#ifdef CONFIG_BOARD_TYPES
+	set_board_type();
+#endif
+	err = board_uart_init();
+	if (err) {
+		debug("UART init failed\n");
+		return err;
+	}
+
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+	board_i2c_init(gd->fdt_blob);
+#endif
+
+	return exynos_early_init_f();
+}
+#endif
+
+#if defined(CONFIG_POWER) || defined(CONFIG_DM_PMIC)
+int power_init_board(void)
+{
+	set_ps_hold_ctrl();
+
+	return exynos_power_init();
+}
+#endif
+
+#ifdef CONFIG_SMC911X
+static int decode_sromc(const void *blob, struct fdt_sromc *config)
+{
+	int err;
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
+	if (node < 0) {
+		debug("Could not find SROMC node\n");
+		return node;
+	}
+
+	config->bank = fdtdec_get_int(blob, node, "bank", 0);
+	config->width = fdtdec_get_int(blob, node, "width", 2);
+
+	err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
+			FDT_SROM_TIMING_COUNT);
+	if (err < 0) {
+		debug("Could not decode SROMC configuration Error: %s\n",
+		      fdt_strerror(err));
+		return -FDT_ERR_NOTFOUND;
+	}
+	return 0;
+}
+#endif
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifdef CONFIG_SMC911X
+	u32 smc_bw_conf, smc_bc_conf;
+	struct fdt_sromc config;
+	fdt_addr_t base_addr;
+	int node;
+
+	node = decode_sromc(gd->fdt_blob, &config);
+	if (node < 0) {
+		debug("%s: Could not find sromc configuration\n", __func__);
+		return 0;
+	}
+	node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
+	if (node < 0) {
+		debug("%s: Could not find lan9215 configuration\n", __func__);
+		return 0;
+	}
+
+	/* We now have a node, so any problems from now on are errors */
+	base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+	if (base_addr == FDT_ADDR_T_NONE) {
+		debug("%s: Could not find lan9215 address\n", __func__);
+		return -1;
+	}
+
+	/* Ethernet needs data bus width of 16 bits */
+	if (config.width != 2) {
+		debug("%s: Unsupported bus width %d\n", __func__,
+		      config.width);
+		return -1;
+	}
+	smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
+			| SROMC_BYTE_ENABLE(config.bank);
+
+	smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |
+			SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
+			SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
+			SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
+			SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |
+			SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
+			SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
+
+	/* Select and configure the SROMC bank */
+	exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
+	s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
+	return smc911x_initialize(0, base_addr);
+#endif
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_BOARDINFO) || defined(CONFIG_DISPLAY_BOARDINFO_LATE)
+int checkboard(void)
+{
+	if (IS_ENABLED(CONFIG_BOARD_TYPES)) {
+		const char *board_info;
+
+		if (IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) {
+			/*
+			 * Printing type requires having revision, although
+			 * this will succeed only if done late.
+			 * Otherwise revision will be set in misc_init_r().
+			 */
+			set_board_revision();
+		}
+
+		board_info = get_board_type();
+
+		if (board_info)
+			printf("Type:  %s\n", board_info);
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	struct udevice *dev;
+	int ret;
+	int mmcbootdev = get_boot_mmc_dev();
+	char mmcbootdev_str[16];
+
+	ret = uclass_first_device_err(UCLASS_CROS_EC, &dev);
+	if (ret && ret != -ENODEV) {
+		/* Force console on */
+		gd->flags &= ~GD_FLG_SILENT;
+
+		printf("cros-ec communications failure %d\n", ret);
+		puts("\nPlease reset with Power+Refresh\n\n");
+		panic("Cannot init cros-ec device");
+		return -1;
+	}
+
+	printf("Boot device: MMC(%u)\n", mmcbootdev);
+	sprintf(mmcbootdev_str, "%u", mmcbootdev);
+	env_set("mmcbootdev", mmcbootdev_str);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	if (IS_ENABLED(CONFIG_BOARD_TYPES) &&
+	    !IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) {
+		/*
+		 * If revision was not set by late display boardinfo,
+		 * set it here. At this point regulators should be already
+		 * available.
+		 */
+		set_board_revision();
+	}
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+	keys_init();
+	check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+	if (panel_info.logo_on)
+		draw_logo();
+#endif
+	return 0;
+}
+#endif
+
+void reset_misc(void)
+{
+	struct gpio_desc gpio = {};
+	int node;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
+			"samsung,emmc-reset");
+	if (node < 0)
+		return;
+
+	gpio_request_by_name_nodev(offset_to_ofnode(node), "reset-gpio", 0,
+				   &gpio, GPIOD_IS_OUT);
+
+	if (dm_gpio_is_valid(&gpio)) {
+		/*
+		 * Reset eMMC
+		 *
+		 * FIXME: Need to optimize delay time. Minimum 1usec pulse is
+		 *	  required by 'JEDEC Standard No.84-A441' (eMMC)
+		 *	  document but real delay time is expected to greater
+		 *	  than 1usec.
+		 */
+		dm_gpio_set_value(&gpio, 0);
+		mdelay(10);
+		dm_gpio_set_value(&gpio, 1);
+	}
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+#ifdef CONFIG_USB_DWC3
+	dwc3_uboot_exit(index);
+#endif
+	return 0;
+}
+
+int mmc_get_env_dev(void)
+{
+	return get_boot_mmc_dev();
+}
diff --git a/roms/u-boot/board/samsung/common/bootscripts/autoboot.cmd b/roms/u-boot/board/samsung/common/bootscripts/autoboot.cmd
new file mode 100644
index 000000000..d66bcccf5
--- /dev/null
+++ b/roms/u-boot/board/samsung/common/bootscripts/autoboot.cmd
@@ -0,0 +1,92 @@
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d autoboot.cmd boot.scr
+#
+# It requires a list of environment variables to be defined before load:
+# platform dependent: board_name, fdtfile, console
+# system dependent: mmcbootdev, mmcbootpart, mmcrootdev, mmcrootpart, rootfstype
+#
+setenv fdtaddr     "40800000"
+setenv initrdname  "uInitrd"
+setenv initrdaddr  "42000000"
+setenv loaddtb     "load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} ${fdtfile}"
+setenv loadinitrd  "load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} ${initrdname}"
+setenv loadkernel  "load mmc ${mmcbootdev}:${mmcbootpart} '${kerneladdr}' '${kernelname}'"
+setenv kernel_args "setenv bootargs ${console} root=/dev/mmcblk${mmcrootdev}p${mmcrootpart} rootfstype=${rootfstype} rootwait ${opts}"
+
+#### Routine: check_dtb - check that target.dtb exists on boot partition
+setenv check_dtb "
+if test -e mmc '${mmcbootdev}':'${mmcbootpart}' '${fdtfile}'; then
+	run loaddtb;
+	setenv fdt_addr ${fdtaddr};
+else
+	echo Warning! Booting without DTB: '${fdtfile}'!;
+	setenv fdt_addr;
+fi;"
+
+#### Routine: check_ramdisk - check that uInitrd exists on boot partition
+setenv check_ramdisk "
+if test -e mmc '${mmcbootdev}':'${mmcbootpart}' '${initrdname}'; then
+	echo "Found ramdisk image.";
+	run loadinitrd;
+	setenv initrd_addr ${initrdaddr};
+else
+	echo Warning! Booting without RAMDISK: '${initrdname}'!;
+	setenv initrd_addr -;
+fi;"
+
+#### Routine: boot_fit - check that env $board_name is set and boot proper config of ITB image
+setenv setboot_fit "
+if test -e '${board_name}'; then
+	setenv fdt_addr ;
+	setenv initrd_addr ;
+	setenv kerneladdr  0x42000000;
+	setenv kernelname  Image.itb;
+	setenv itbcfg      "\"#${board_name}\"";
+	setenv imgbootcmd  bootm;
+else
+	echo Warning! Variable: \$board_name is undefined!;
+fi"
+
+#### Routine: setboot_uimg - prepare env to boot uImage
+setenv setboot_uimg "
+	setenv kerneladdr 0x40007FC0;
+	setenv kernelname uImage;
+	setenv itbcfg     ;
+	setenv imgbootcmd bootm;
+	run check_dtb;
+	run check_ramdisk;"
+
+#### Routine: setboot_zimg - prepare env to boot zImage
+setenv setboot_zimg "
+	setenv kerneladdr 0x40007FC0;
+	setenv kernelname zImage;
+	setenv itbcfg     ;
+	setenv imgbootcmd bootz;
+	run check_dtb;
+	run check_ramdisk;"
+
+#### Routine: boot_img - boot the kernel after env setup
+setenv boot_img "
+	run loadkernel;
+	run kernel_args;
+	'${imgbootcmd}' '${kerneladdr}${itbcfg}' '${initrd_addr}' '${fdt_addr}';"
+
+#### Routine: autoboot - choose proper boot path
+setenv autoboot "
+if test -e mmc ${mmcbootdev}:${mmcbootpart} Image.itb; then
+	echo Found kernel image: Image.itb;
+	run setboot_fit;
+	run boot_img;
+elif test -e mmc ${mmcbootdev}:${mmcbootpart} zImage; then
+	echo Found kernel image: zImage;
+	run setboot_zimg;
+	run boot_img;
+elif test -e mmc ${mmcbootdev}:${mmcbootpart} uImage; then
+	echo Found kernel image: uImage;
+	run setboot_uimg;
+	run boot_img;
+fi;"
+
+#### Execute the defined autoboot macro
+run autoboot
diff --git a/roms/u-boot/board/samsung/common/bootscripts/bootzimg.cmd b/roms/u-boot/board/samsung/common/bootscripts/bootzimg.cmd
new file mode 100644
index 000000000..2fb4c163a
--- /dev/null
+++ b/roms/u-boot/board/samsung/common/bootscripts/bootzimg.cmd
@@ -0,0 +1,10 @@
+setenv kernelname zImage;
+setenv boot_kernel "setenv bootargs \"${console} root=/dev/mmcblk${mmcrootdev}p${mmcrootpart} rootfstype=${rootfstype} rootwait ${opts}\";
+load mmc ${mmcbootdev}:${mmcbootpart} 0x40007FC0 '${kernelname}';
+if load mmc ${mmcbootdev}:${mmcbootpart} 40800000 ${fdtfile}; then
+	bootz 0x40007FC0 - 40800000;
+else
+	echo Warning! Booting without DTB: '${fdtfile}'!;
+	bootz 0x40007FC0 -;
+fi;"
+run boot_kernel;
\ No newline at end of file
diff --git a/roms/u-boot/board/samsung/common/dfu_sample_env.txt b/roms/u-boot/board/samsung/common/dfu_sample_env.txt
new file mode 100644
index 000000000..d6ee8a228
--- /dev/null
+++ b/roms/u-boot/board/samsung/common/dfu_sample_env.txt
@@ -0,0 +1,9 @@
+mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${rootfstype} rootwait ${console}; run loaduimage; bootm 0x40007FC0
+rootfstype=ext4
+loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage
+mmcdev=0
+mmcbootpart=2
+mmcrootpart=5
+console=console=ttySAC2,115200n8
+bootcmd=run mmcboot
+dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0 2
diff --git a/roms/u-boot/board/samsung/common/exynos-uboot-spl.lds b/roms/u-boot/board/samsung/common/exynos-uboot-spl.lds
new file mode 100644
index 000000000..5b32f7feb
--- /dev/null
+++ b/roms/u-boot/board/samsung/common/exynos-uboot-spl.lds
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Based on arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+ */
+
+MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE, \
+		LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+		__start = .;
+		*(.vectors)
+		arch/arm/cpu/armv7/start.o (.text*)
+		*(.text*)
+	} >.sram
+	. = ALIGN(4);
+
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+	. = ALIGN(4);
+
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
+
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} >.sram
+	. = ALIGN(4);
+
+	.machine_param : { *(.machine_param) } >.sram
+	. = ALIGN(4);
+
+	__image_copy_end = .;
+
+	.end :
+	{
+		*(.__end)
+	} >.sram
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} >.sram
+}
diff --git a/roms/u-boot/board/samsung/common/exynos5-dt-types.c b/roms/u-boot/board/samsung/common/exynos5-dt-types.c
new file mode 100644
index 000000000..e2d5a7c9b
--- /dev/null
+++ b/roms/u-boot/board/samsung/common/exynos5-dt-types.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ */
+
+#include <common.h>
+#include <adc.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/s2mps11.h>
+#include <samsung/exynos5-dt-types.h>
+#include <samsung/misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct udevice_id board_ids[] = {
+	{ .compatible = "samsung,odroidxu3", .data = EXYNOS5_BOARD_ODROID_XU3 },
+	{ .compatible = "samsung,exynos5", .data = EXYNOS5_BOARD_GENERIC },
+	{ },
+};
+
+/**
+ * Odroix XU3/XU4/HC1/HC2 board revisions (from HC1+_HC2_MAIN_REV0.1_20171017.pdf):
+ * Rev   ADCmax  Board
+ * 0.1     0     XU3 0.1
+ * 0.2   372     XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231)
+ * 0.3  1280     XU4 0.1
+ * 0.4   739     XU4 0.2
+ * 0.5  1016     XU4+Air0.1 (Passive cooling)
+ * 0.6  1309     XU4-HC1 0.1
+ * 0.7  1470     XU4-HC1+ 0.1 (HC2)
+ * Use +1% for ADC value tolerance in the array below, the code loops until
+ * the measured ADC value is lower than then ADCmax from the array.
+ */
+struct odroid_rev_info odroid_info[] = {
+	{ EXYNOS5_BOARD_ODROID_XU3_REV01, 1, 10, "xu3" },
+	{ EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 375, "xu3" },
+	{ EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1293, "xu4" },
+	{ EXYNOS5_BOARD_ODROID_HC1_REV01, 1, 1322, "hc1" },
+	{ EXYNOS5_BOARD_ODROID_HC2_REV01, 1, 1484, "hc1" },
+	{ EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" },
+};
+
+static unsigned int odroid_get_rev(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(odroid_info); i++) {
+		if (odroid_info[i].board_type == gd->board_type)
+			return odroid_info[i].board_rev;
+	}
+
+	return 0;
+}
+
+/*
+ * Read ADC at least twice and check the resuls.  If regulator providing voltage
+ * on to measured point was just turned on, first reads might require time
+ * to stabilize.
+ */
+static int odroid_get_adc_val(unsigned int *adcval)
+{
+	unsigned int adcval_prev = 0;
+	int ret, retries = 20;
+
+	ret = adc_channel_single_shot("adc@12D10000", CONFIG_ODROID_REV_AIN,
+				      &adcval_prev);
+	if (ret)
+		return ret;
+
+	while (retries--) {
+		mdelay(5);
+
+		ret = adc_channel_single_shot("adc@12D10000",
+					      CONFIG_ODROID_REV_AIN, adcval);
+		if (ret)
+			return ret;
+
+		/*
+		 * If difference between ADC reads is less than 3%,
+		 * accept the result
+		 */
+		if ((100 * abs(*adcval - adcval_prev) / adcval_prev) < 3)
+			return ret;
+
+		adcval_prev = *adcval;
+	}
+
+	return ret;
+}
+
+static int odroid_get_board_type(void)
+{
+	unsigned int adcval;
+	int ret, i;
+
+	ret = odroid_get_adc_val(&adcval);
+	if (ret)
+		goto rev_default;
+
+	for (i = 0; i < ARRAY_SIZE(odroid_info); i++) {
+		/* ADC tolerance: +1% */
+		if (adcval < odroid_info[i].adc_val)
+			return odroid_info[i].board_type;
+	}
+
+rev_default:
+	return EXYNOS5_BOARD_ODROID_XU3;
+}
+
+/**
+ * odroid_get_type_str - returns pointer to one of the board type string.
+ * Board types: "xu3", "xu3-lite", "xu4". However the "xu3lite" can be
+ * detected only when the i2c controller is ready to use. Fortunately,
+ * XU3 and XU3L are compatible, and the information about board lite
+ * revision is needed before booting the linux, to set proper environment
+ * variable: $fdtfile.
+ */
+static const char *odroid_get_type_str(void)
+{
+	const char *type_xu3l = "xu3-lite";
+	struct udevice *dev, *chip;
+	int i, ret;
+
+	if (gd->board_type != EXYNOS5_BOARD_ODROID_XU3_REV02)
+		goto exit;
+
+	ret = pmic_get("s2mps11_pmic@66", &dev);
+	if (ret)
+		goto exit;
+
+	/* Enable LDO26: 3.0V */
+	ret = pmic_reg_write(dev, S2MPS11_REG_L26CTRL,
+			     S2MPS11_LDO26_ENABLE);
+	if (ret)
+		goto exit;
+
+	/* Check XU3Lite by probe INA231 I2C0:0x40 */
+	ret = uclass_get_device(UCLASS_I2C, 0, &dev);
+	if (ret)
+		goto exit;
+
+	ret = dm_i2c_probe(dev, 0x40, 0x0, &chip);
+	if (ret)
+		return type_xu3l;
+
+exit:
+	for (i = 0; i < ARRAY_SIZE(odroid_info); i++) {
+		if (odroid_info[i].board_type == gd->board_type)
+			return odroid_info[i].name;
+	}
+
+	return NULL;
+}
+
+bool board_is_odroidxu3(void)
+{
+	if (gd->board_type >= EXYNOS5_BOARD_ODROID_XU3 &&
+	    gd->board_type <= EXYNOS5_BOARD_ODROID_XU3_REV02)
+		return true;
+
+	return false;
+}
+
+bool board_is_odroidxu4(void)
+{
+	if (gd->board_type == EXYNOS5_BOARD_ODROID_XU4_REV01)
+		return true;
+
+	return false;
+}
+
+bool board_is_odroidhc1(void)
+{
+	if (gd->board_type == EXYNOS5_BOARD_ODROID_HC1_REV01)
+		return true;
+
+	return false;
+}
+
+bool board_is_odroidhc2(void)
+{
+	if (gd->board_type == EXYNOS5_BOARD_ODROID_HC2_REV01)
+		return true;
+
+	return false;
+}
+
+bool board_is_generic(void)
+{
+	if (gd->board_type == EXYNOS5_BOARD_GENERIC)
+		return true;
+
+	return false;
+}
+
+/**
+ * get_board_rev() - return detected board revision.
+ *
+ * @return:  return board revision number for XU3 or 0 for generic
+ */
+u32 get_board_rev(void)
+{
+	if (board_is_generic())
+		return 0;
+
+	return odroid_get_rev();
+}
+
+/**
+ * get_board_type() - returns board type string.
+ *
+ * @return:  return board type string for XU3 or empty string for generic
+ */
+const char *get_board_type(void)
+{
+	const char *generic = "";
+
+	if (board_is_generic())
+		return generic;
+
+	return odroid_get_type_str();
+}
+
+/**
+ * set_board_type() - set board type in gd->board_type.
+ * As default type set EXYNOS5_BOARD_GENERIC. If Odroid is detected,
+ * set its proper type based on device tree.
+ *
+ * This might be called early when some more specific ways to detect revision
+ * are not yet available.
+ */
+void set_board_type(void)
+{
+	const struct udevice_id *of_match = board_ids;
+	int ret;
+
+	gd->board_type = EXYNOS5_BOARD_GENERIC;
+
+	while (of_match->compatible) {
+		ret = fdt_node_check_compatible(gd->fdt_blob, 0,
+						of_match->compatible);
+		if (ret)
+			of_match++;
+
+		gd->board_type = of_match->data;
+		break;
+	}
+}
+
+/**
+ * set_board_revision() - set detailed board type in gd->board_type.
+ * Should be called when resources (e.g. regulators) are available
+ * so ADC can be used to detect the specific revision of a board.
+ */
+void set_board_revision(void)
+{
+	if (board_is_odroidxu3())
+		gd->board_type = odroid_get_board_type();
+}
diff --git a/roms/u-boot/board/samsung/common/exynos5-dt.c b/roms/u-boot/board/samsung/common/exynos5-dt.c
new file mode 100644
index 000000000..1318ea716
--- /dev/null
+++ b/roms/u-boot/board/samsung/common/exynos5-dt.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dwc3-uboot.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <samsung-usb-phy-uboot.h>
+#include <spi.h>
+#include <usb.h>
+#include <video_bridge.h>
+#include <asm/gpio.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/sromc.h>
+#include <power/pmic.h>
+#include <power/max77686_pmic.h>
+#include <power/regulator.h>
+#include <power/s2mps11.h>
+#include <power/s5m8767.h>
+#include <samsung/exynos5-dt-types.h>
+#include <samsung/misc.h>
+#include <tmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int exynos_init(void)
+{
+	return 0;
+}
+
+static int exynos_set_regulator(const char *name, uint uv)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = regulator_get_by_platname(name, &dev);
+	if (ret) {
+		debug("%s: Cannot find regulator %s\n", __func__, name);
+		return ret;
+	}
+	ret = regulator_set_value(dev, uv);
+	if (ret) {
+		debug("%s: Cannot set regulator %s\n", __func__, name);
+		return ret;
+	}
+
+	return 0;
+}
+
+int exynos_power_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+#ifdef CONFIG_PMIC_S2MPS11
+	ret = pmic_get("s2mps11_pmic@66", &dev);
+#else
+	ret = pmic_get("max77686_pmic@09", &dev);
+	if (!ret) {
+		/* TODO(sjg@chromium.org): Move into the clock/pmic API */
+		ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_32KHZ, 0,
+				MAX77686_32KHCP_EN);
+		if (ret)
+			return ret;
+		ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_BBAT, 0,
+				MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V);
+		if (ret)
+			return ret;
+	} else {
+		ret = pmic_get("s5m8767_pmic@66", &dev);
+		/* TODO(sjg@chromium.org): Use driver model to access clock */
+#ifdef CONFIG_PMIC_S5M8767
+		if (!ret)
+			s5m8767_enable_32khz_cp(dev);
+#endif
+	}
+#endif	/* CONFIG_PMIC_S2MPS11 */
+	if (ret == -ENODEV)
+		return 0;
+
+	ret = regulators_enable_boot_on(false);
+	if (ret)
+		return ret;
+
+	ret = exynos_set_regulator("vdd_mif", 1100000);
+	if (ret)
+		return ret;
+
+	ret = exynos_set_regulator("vdd_arm", 1300000);
+	if (ret)
+		return ret;
+	ret = exynos_set_regulator("vdd_int", 1012500);
+	if (ret)
+		return ret;
+	ret = exynos_set_regulator("vdd_g3d", 1200000);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int board_get_revision(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device dwc3_device_data = {
+	.maximum_speed = USB_SPEED_SUPER,
+	.base = 0x12400000,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+	dwc3_uboot_handle_interrupt(0);
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	struct exynos_usb3_phy *phy = (struct exynos_usb3_phy *)
+		samsung_get_base_usb3_phy();
+
+	if (!phy) {
+		pr_err("usb3 phy not supported\n");
+		return -ENODEV;
+	}
+
+	set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
+	exynos5_usb3_phy_init(phy);
+
+	return dwc3_uboot_init(&dwc3_device_data);
+}
+#endif
+#ifdef CONFIG_SET_DFU_ALT_INFO
+char *get_dfu_alt_system(char *interface, char *devstr)
+{
+	char *info = "Not supported!";
+
+	if (board_is_odroidxu4() || board_is_odroidhc1() || board_is_odroidhc2())
+		return info;
+
+	return env_get("dfu_alt_system");
+}
+
+char *get_dfu_alt_boot(char *interface, char *devstr)
+{
+	char *info = "Not supported!";
+	struct mmc *mmc;
+	char *alt_boot;
+	int dev_num;
+
+	if (board_is_odroidxu4() || board_is_odroidhc1() || board_is_odroidhc2())
+		return info;
+
+	dev_num = simple_strtoul(devstr, NULL, 10);
+
+	mmc = find_mmc_device(dev_num);
+	if (!mmc)
+		return NULL;
+
+	if (mmc_init(mmc))
+		return NULL;
+
+	if (IS_SD(mmc))
+		alt_boot = CONFIG_DFU_ALT_BOOT_SD;
+	else
+		alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
+
+	return alt_boot;
+}
+#endif
diff --git a/roms/u-boot/board/samsung/common/gadget.c b/roms/u-boot/board/samsung/common/gadget.c
new file mode 100644
index 000000000..6d783e61e
--- /dev/null
+++ b/roms/u-boot/board/samsung/common/gadget.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2013 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#include <common.h>
+#include <linux/usb/ch9.h>
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	if (!strcmp(name, "usb_dnl_thor")) {
+		put_unaligned(CONFIG_G_DNL_THOR_VENDOR_NUM, &dev->idVendor);
+		put_unaligned(CONFIG_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct);
+	} else if (!strcmp(name, "usb_dnl_ums")) {
+		put_unaligned(CONFIG_G_DNL_UMS_VENDOR_NUM, &dev->idVendor);
+		put_unaligned(CONFIG_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct);
+	} else {
+		put_unaligned(CONFIG_USB_GADGET_VENDOR_NUM, &dev->idVendor);
+		put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
+	}
+	return 0;
+}
diff --git a/roms/u-boot/board/samsung/common/misc.c b/roms/u-boot/board/samsung/common/misc.c
new file mode 100644
index 000000000..b3b1bbcc8
--- /dev/null
+++ b/roms/u-boot/board/samsung/common/misc.c
@@ -0,0 +1,486 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <lcd.h>
+#include <libtizen.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <samsung/misc.h>
+#include <errno.h>
+#include <version.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <linux/sizes.h>
+#include <asm/arch/cpu.h>
+#include <asm/gpio.h>
+#include <linux/input.h>
+#include <dm.h>
+/*
+ * Use #ifdef to work around conflicting headers while we wait for this to be
+ * converted to driver model.
+ */
+#ifdef CONFIG_DM_PMIC_MAX77686
+#include <power/max77686_pmic.h>
+#endif
+#ifdef CONFIG_DM_PMIC_MAX8998
+#include <power/max8998_pmic.h>
+#endif
+#ifdef CONFIG_PMIC_MAX8997
+#include <power/max8997_pmic.h>
+#endif
+#include <power/pmic.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SET_DFU_ALT_INFO
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+	size_t buf_size = CONFIG_SET_DFU_ALT_BUF_LEN;
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, buf_size);
+	char *alt_info = "Settings not found!";
+	char *status = "error!\n";
+	char *alt_setting;
+	char *alt_sep;
+	int offset = 0;
+
+	puts("DFU alt info setting: ");
+
+	alt_setting = get_dfu_alt_boot(interface, devstr);
+	if (alt_setting) {
+		env_set("dfu_alt_boot", alt_setting);
+		offset = snprintf(buf, buf_size, "%s", alt_setting);
+	}
+
+	alt_setting = get_dfu_alt_system(interface, devstr);
+	if (alt_setting) {
+		if (offset)
+			alt_sep = ";";
+		else
+			alt_sep = "";
+
+		offset += snprintf(buf + offset, buf_size - offset,
+				    "%s%s", alt_sep, alt_setting);
+	}
+
+	if (offset) {
+		alt_info = buf;
+		status = "done\n";
+	}
+
+	env_set("dfu_alt_info", alt_info);
+	puts(status);
+}
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void)
+{
+	char info[64];
+
+	snprintf(info, ARRAY_SIZE(info), "%u.%u", (s5p_cpu_rev & 0xf0) >> 4,
+		 s5p_cpu_rev & 0xf);
+	env_set("soc_rev", info);
+
+	snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id);
+	env_set("soc_id", info);
+
+#ifdef CONFIG_REVISION_TAG
+	snprintf(info, ARRAY_SIZE(info), "%x", get_board_rev());
+	env_set("board_rev", info);
+#endif
+#ifdef CONFIG_OF_LIBFDT
+	const char *bdtype = "";
+	const char *bdname = CONFIG_SYS_BOARD;
+
+#ifdef CONFIG_BOARD_TYPES
+	bdtype = get_board_type();
+	if (!bdtype)
+		bdtype = "";
+
+	sprintf(info, "%s%s", bdname, bdtype);
+	env_set("board_name", info);
+#endif
+	snprintf(info, ARRAY_SIZE(info),  "%s%x-%s%s.dtb",
+		 CONFIG_SYS_SOC, s5p_cpu_id, bdname, bdtype);
+	env_set("fdtfile", info);
+#endif
+}
+#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
+
+#ifdef CONFIG_LCD_MENU
+static int power_key_pressed(u32 reg)
+{
+	struct udevice *dev;
+	int ret;
+	u32 status;
+	u32 mask;
+
+	if (IS_ENABLED(CONFIG_TARGET_TRATS))
+		ret = pmic_get("max8997-pmic", &dev);
+	else if (IS_ENABLED(CONFIG_TARGET_TRATS2))
+		ret = pmic_get("max77686-pmic", &dev);
+	else if (IS_ENABLED(CONFIG_TARGET_S5PC210_UNIVERSAL))
+		ret = pmic_get("max8998-pmic", &dev);
+	else
+		return 0;
+
+	if (ret)
+		return ret;
+
+	if (reg == KEY_PWR_STATUS_REG)
+		mask = KEY_PWR_STATUS_MASK;
+	else
+		mask = KEY_PWR_INTERRUPT_MASK;
+
+	status = pmic_reg_read(dev, reg);
+	if (status < 0)
+		return status;
+
+	return !!(status & mask);
+}
+
+static int key_pressed(int key)
+{
+	int value;
+
+	switch (key) {
+	case KEY_POWER:
+		value = power_key_pressed(KEY_PWR_INTERRUPT_REG);
+		break;
+	case KEY_VOLUMEUP:
+		value = !gpio_get_value(KEY_VOL_UP_GPIO);
+		break;
+	case KEY_VOLUMEDOWN:
+		value = !gpio_get_value(KEY_VOL_DOWN_GPIO);
+		break;
+	default:
+		value = 0;
+		break;
+	}
+
+	return value;
+}
+
+#ifdef CONFIG_LCD
+static int check_keys(void)
+{
+	int keys = 0;
+
+	if (key_pressed(KEY_POWER))
+		keys += KEY_POWER;
+	if (key_pressed(KEY_VOLUMEUP))
+		keys += KEY_VOLUMEUP;
+	if (key_pressed(KEY_VOLUMEDOWN))
+		keys += KEY_VOLUMEDOWN;
+
+	return keys;
+}
+
+/*
+ * 0 BOOT_MODE_INFO
+ * 1 BOOT_MODE_THOR
+ * 2 BOOT_MODE_UMS
+ * 3 BOOT_MODE_DFU
+ * 4 BOOT_MODE_EXIT
+ */
+static char *
+mode_name[BOOT_MODE_EXIT + 1][2] = {
+	{"DEVICE", ""},
+	{"THOR", "thor"},
+	{"UMS", "ums"},
+	{"DFU", "dfu"},
+	{"GPT", "gpt"},
+	{"ENV", "env"},
+	{"EXIT", ""},
+};
+
+static char *
+mode_info[BOOT_MODE_EXIT + 1] = {
+	"info",
+	"downloader",
+	"mass storage",
+	"firmware update",
+	"restore",
+	"default",
+	"and run normal boot"
+};
+
+static char *
+mode_cmd[BOOT_MODE_EXIT + 1] = {
+	"",
+	"thor 0 mmc 0",
+	"ums 0 mmc 0",
+	"dfu 0 mmc 0",
+	"gpt write mmc 0 $partitions",
+	"env default -a; saveenv",
+	"",
+};
+
+static void display_board_info(void)
+{
+#ifdef CONFIG_MMC
+	struct mmc *mmc = find_mmc_device(0);
+#endif
+	vidinfo_t *vid = &panel_info;
+
+	lcd_position_cursor(4, 4);
+
+	lcd_printf("%s\n\t", U_BOOT_VERSION);
+	lcd_puts("\n\t\tBoard Info:\n");
+#ifdef CONFIG_SYS_BOARD
+	lcd_printf("\tBoard name: %s\n", CONFIG_SYS_BOARD);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	lcd_printf("\tBoard rev: %u\n", get_board_rev());
+#endif
+	lcd_printf("\tDRAM banks: %u\n", CONFIG_NR_DRAM_BANKS);
+	lcd_printf("\tDRAM size: %u MB\n", gd->ram_size / SZ_1M);
+
+#ifdef CONFIG_MMC
+	if (mmc) {
+		if (!mmc->capacity)
+			mmc_init(mmc);
+
+		lcd_printf("\teMMC size: %llu MB\n", mmc->capacity / SZ_1M);
+	}
+#endif
+	if (vid)
+		lcd_printf("\tDisplay resolution: %u x % u\n",
+			   vid->vl_col, vid->vl_row);
+
+	lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix);
+}
+#endif
+
+static int mode_leave_menu(int mode)
+{
+#ifdef CONFIG_LCD
+	char *exit_option;
+	char *exit_reset = "reset";
+	char *exit_back = "back";
+	struct cmd_tbl *cmd;
+	int cmd_result;
+	int leave;
+
+	lcd_clear();
+
+	switch (mode) {
+	case BOOT_MODE_EXIT:
+		return 1;
+	case BOOT_MODE_INFO:
+		display_board_info();
+		exit_option = exit_back;
+		leave = 0;
+		break;
+	default:
+		cmd = find_cmd(mode_name[mode][1]);
+		if (cmd) {
+			printf("Enter: %s %s\n", mode_name[mode][0],
+			       mode_info[mode]);
+			lcd_printf("\n\n\t%s %s\n", mode_name[mode][0],
+				   mode_info[mode]);
+			lcd_puts("\n\tDo not turn off device before finish!\n");
+
+			cmd_result = run_command(mode_cmd[mode], 0);
+
+			if (cmd_result == CMD_RET_SUCCESS) {
+				printf("Command finished\n");
+				lcd_clear();
+				lcd_printf("\n\n\t%s finished\n",
+					   mode_name[mode][0]);
+
+				exit_option = exit_reset;
+				leave = 1;
+			} else {
+				printf("Command error\n");
+				lcd_clear();
+				lcd_printf("\n\n\t%s command error\n",
+					   mode_name[mode][0]);
+
+				exit_option = exit_back;
+				leave = 0;
+			}
+		} else {
+			lcd_puts("\n\n\tThis mode is not supported.\n");
+			exit_option = exit_back;
+			leave = 0;
+		}
+	}
+
+	lcd_printf("\n\n\tPress POWER KEY to %s\n", exit_option);
+
+	/* Clear PWR button Rising edge interrupt status flag */
+	power_key_pressed(KEY_PWR_INTERRUPT_REG);
+
+	/* Wait for PWR key */
+	while (!key_pressed(KEY_POWER))
+		mdelay(1);
+
+	lcd_clear();
+	return leave;
+#else
+	return 0;
+#endif
+}
+
+#ifdef CONFIG_LCD
+static void display_download_menu(int mode)
+{
+	char *selection[BOOT_MODE_EXIT + 1];
+	int i;
+
+	for (i = 0; i <= BOOT_MODE_EXIT; i++)
+		selection[i] = "[  ]";
+
+	selection[mode] = "[=>]";
+
+	lcd_clear();
+	lcd_printf("\n\n\t\tDownload Mode Menu\n\n");
+
+	for (i = 0; i <= BOOT_MODE_EXIT; i++)
+		lcd_printf("\t%s  %s - %s\n\n", selection[i],
+			   mode_name[i][0], mode_info[i]);
+}
+#endif
+
+static void download_menu(void)
+{
+#ifdef CONFIG_LCD
+	int mode = 0;
+	int last_mode = 0;
+	int run;
+	int key = 0;
+	int timeout = 15; /* sec */
+	int i;
+
+	display_download_menu(mode);
+
+	lcd_puts("\n");
+
+	/* Start count if no key is pressed */
+	while (check_keys())
+		continue;
+
+	while (timeout--) {
+		lcd_printf("\r\tNormal boot will start in: %2.d seconds.",
+			   timeout);
+
+		/* about 1000 ms in for loop */
+		for (i = 0; i < 10; i++) {
+			mdelay(100);
+			key = check_keys();
+			if (key)
+				break;
+		}
+		if (key)
+			break;
+	}
+
+	if (!key) {
+		lcd_clear();
+		return;
+	}
+
+	while (1) {
+		run = 0;
+
+		if (mode != last_mode)
+			display_download_menu(mode);
+
+		last_mode = mode;
+		mdelay(200);
+
+		key = check_keys();
+		switch (key) {
+		case KEY_POWER:
+			run = 1;
+			break;
+		case KEY_VOLUMEUP:
+			if (mode > 0)
+				mode--;
+			break;
+		case KEY_VOLUMEDOWN:
+			if (mode < BOOT_MODE_EXIT)
+				mode++;
+			break;
+		default:
+			break;
+		}
+
+		if (run) {
+			if (mode_leave_menu(mode))
+				run_command("reset", 0);
+
+			display_download_menu(mode);
+		}
+	}
+
+	lcd_clear();
+#endif
+}
+
+void check_boot_mode(void)
+{
+	int pwr_key;
+
+	pwr_key = power_key_pressed(KEY_PWR_STATUS_REG);
+	if (!pwr_key)
+		return;
+
+	/* Clear PWR button Rising edge interrupt status flag */
+	power_key_pressed(KEY_PWR_INTERRUPT_REG);
+
+	if (key_pressed(KEY_VOLUMEUP))
+		download_menu();
+	else if (key_pressed(KEY_VOLUMEDOWN))
+		mode_leave_menu(BOOT_MODE_THOR);
+}
+
+void keys_init(void)
+{
+	/* Set direction to input */
+	gpio_request(KEY_VOL_UP_GPIO, "volume-up");
+	gpio_request(KEY_VOL_DOWN_GPIO, "volume-down");
+	gpio_direction_input(KEY_VOL_UP_GPIO);
+	gpio_direction_input(KEY_VOL_DOWN_GPIO);
+}
+#endif /* CONFIG_LCD_MENU */
+
+#ifdef CONFIG_CMD_BMP
+void draw_logo(void)
+{
+	int x, y;
+	ulong addr;
+
+	addr = panel_info.logo_addr;
+	if (!addr) {
+		pr_err("There is no logo data.\n");
+		return;
+	}
+
+	if (panel_info.vl_width >= panel_info.logo_width) {
+		x = ((panel_info.vl_width - panel_info.logo_width) >> 1);
+		x += panel_info.logo_x_offset; /* For X center align */
+	} else {
+		x = 0;
+		printf("Warning: image width is bigger than display width\n");
+	}
+
+	if (panel_info.vl_height >= panel_info.logo_height) {
+		y = ((panel_info.vl_height - panel_info.logo_height) >> 1);
+		y += panel_info.logo_y_offset; /* For Y center align */
+	} else {
+		y = 0;
+		printf("Warning: image height is bigger than display height\n");
+	}
+
+	bmp_display(addr, x, y);
+}
+#endif /* CONFIG_CMD_BMP */
diff --git a/roms/u-boot/board/samsung/espresso7420/Kconfig b/roms/u-boot/board/samsung/espresso7420/Kconfig
new file mode 100644
index 000000000..62251c512
--- /dev/null
+++ b/roms/u-boot/board/samsung/espresso7420/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_ESPRESSO7420
+
+config SYS_BOARD
+	default "espresso7420"
+	help
+	  Espresso7420 is a development/evaluation board for Exynos7420 SoC.
+	  It includes multiple onboard compoments (EMMC/Codec) and various
+	  interconnects (USB/HDMI).
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "espresso7420"
+
+endif
diff --git a/roms/u-boot/board/samsung/espresso7420/MAINTAINERS b/roms/u-boot/board/samsung/espresso7420/MAINTAINERS
new file mode 100644
index 000000000..9145ad45e
--- /dev/null
+++ b/roms/u-boot/board/samsung/espresso7420/MAINTAINERS
@@ -0,0 +1,6 @@
+ESPRESSO7420 Board
+M:	Minkyu Kang <mk7.kang@samsung.com>
+S:	Maintained
+F:	board/samsung/espresso7420/
+F:	include/configs/espresso7420.h
+F:	configs/espresso7420_defconfig
diff --git a/roms/u-boot/board/samsung/espresso7420/Makefile b/roms/u-boot/board/samsung/espresso7420/Makefile
new file mode 100644
index 000000000..bb882eaa2
--- /dev/null
+++ b/roms/u-boot/board/samsung/espresso7420/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2016 Samsung Electronics
+# Thomas Abraham <thomas.ab@samsung.com>
+
+obj-y	+= espresso7420.o
diff --git a/roms/u-boot/board/samsung/espresso7420/espresso7420.c b/roms/u-boot/board/samsung/espresso7420/espresso7420.c
new file mode 100644
index 000000000..9f6fa8974
--- /dev/null
+++ b/roms/u-boot/board/samsung/espresso7420/espresso7420.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Espresso7420 board file
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ */
+
+#include <common.h>
+
+int exynos_init(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/board/samsung/goni/Kconfig b/roms/u-boot/board/samsung/goni/Kconfig
new file mode 100644
index 000000000..cbbf5a931
--- /dev/null
+++ b/roms/u-boot/board/samsung/goni/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_S5P_GONI
+
+config SYS_BOARD
+	default "goni"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_SOC
+	default "s5pc1xx"
+
+config SYS_CONFIG_NAME
+	default "s5p_goni"
+
+endif
diff --git a/roms/u-boot/board/samsung/goni/MAINTAINERS b/roms/u-boot/board/samsung/goni/MAINTAINERS
new file mode 100644
index 000000000..7643f9c89
--- /dev/null
+++ b/roms/u-boot/board/samsung/goni/MAINTAINERS
@@ -0,0 +1,6 @@
+GONI BOARD
+M:	Jaehoon Chung <jh80.chung@samsung.com>
+S:	Maintained
+F:	board/samsung/goni/
+F:	include/configs/s5p_goni.h
+F:	configs/s5p_goni_defconfig
diff --git a/roms/u-boot/board/samsung/goni/Makefile b/roms/u-boot/board/samsung/goni/Makefile
new file mode 100644
index 000000000..2bf414170
--- /dev/null
+++ b/roms/u-boot/board/samsung/goni/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+
+obj-y	:= goni.o onenand.o
+obj-y	+= lowlevel_init.o
diff --git a/roms/u-boot/board/samsung/goni/goni.c b/roms/u-boot/board/samsung/goni/goni.c
new file mode 100644
index 000000000..b32b82fc2
--- /dev/null
+++ b/roms/u-boot/board/samsung/goni/goni.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2008-2009 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/arch/mmc.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <usb/dwc2_udc.h>
+#include <asm/arch/cpu.h>
+#include <power/max8998_pmic.h>
+#include <samsung/misc.h>
+#include <usb.h>
+#include <usb_mass_storage.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Set Initial global variables */
+	gd->bd->bi_arch_number = MACH_TYPE_GONI;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+void i2c_init_board(void)
+{
+	gpio_request(S5PC110_GPIO_J43, "i2c_clk");
+	gpio_request(S5PC110_GPIO_J40, "i2c_data");
+	gpio_direction_output(S5PC110_GPIO_J43, 1);
+	gpio_direction_output(S5PC110_GPIO_J40, 1);
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
+			PHYS_SDRAM_3_SIZE;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	puts("Board:\tGoni\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MMC
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret, ret_sd = 0;
+
+	/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
+	gpio_request(S5PC110_GPIO_J27, "massmemory_en");
+	gpio_direction_output(S5PC110_GPIO_J27, 1);
+
+	/*
+	 * MMC0 GPIO
+	 * GPG0[0]	SD_0_CLK
+	 * GPG0[1]	SD_0_CMD
+	 * GPG0[2]	SD_0_CDn	-> Not used
+	 * GPG0[3:6]	SD_0_DATA[0:3]
+	 */
+	for (i = S5PC110_GPIO_G00; i < S5PC110_GPIO_G07; i++) {
+		if (i == S5PC110_GPIO_G02)
+			continue;
+		/* GPG0[0:6] special function 2 */
+		gpio_cfg_pin(i, 0x2);
+		/* GPG0[0:6] pull disable */
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		/* GPG0[0:6] drv 4x */
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
+	}
+
+	ret = s5p_mmc_init(0, 4);
+	if (ret)
+		pr_err("MMC: Failed to init MMC:0.\n");
+
+	/*
+	 * SD card (T_FLASH) detect and init
+	 * T_FLASH_DETECT: EINT28: GPH3[4] input mode
+	 */
+	gpio_request(S5PC110_GPIO_H34, "t_flash_detect");
+	gpio_cfg_pin(S5PC110_GPIO_H34, S5P_GPIO_INPUT);
+	gpio_set_pull(S5PC110_GPIO_H34, S5P_GPIO_PULL_UP);
+
+	if (!gpio_get_value(S5PC110_GPIO_H34)) {
+		for (i = S5PC110_GPIO_G20; i < S5PC110_GPIO_G27; i++) {
+			if (i == S5PC110_GPIO_G22)
+				continue;
+
+			/* GPG2[0:6] special function 2 */
+			gpio_cfg_pin(i, 0x2);
+			/* GPG2[0:6] pull disable */
+			gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+			/* GPG2[0:6] drv 4x */
+			gpio_set_drv(i, S5P_GPIO_DRV_4X);
+		}
+
+		ret_sd = s5p_mmc_init(2, 4);
+		if (ret_sd)
+			pr_err("MMC: Failed to init SD card (MMC:2).\n");
+	}
+
+	return ret & ret_sd;
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+static int s5pc1xx_phy_control(int on)
+{
+	struct udevice *dev;
+	static int status;
+	int reg, ret;
+
+	ret = pmic_get("max8998-pmic", &dev);
+	if (ret)
+		return ret;
+
+	if (on && !status) {
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+		reg |= MAX8998_LDO3;
+		ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+		if (ret) {
+			puts("MAX8998 LDO setting error!\n");
+			return -EINVAL;
+		}
+
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+		reg |= MAX8998_LDO8;
+		ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
+		if (ret) {
+			puts("MAX8998 LDO setting error!\n");
+			return -EINVAL;
+		}
+		status = 1;
+	} else if (!on && status) {
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+		reg &= ~MAX8998_LDO3;
+		ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+		if (ret) {
+			puts("MAX8998 LDO setting error!\n");
+			return -EINVAL;
+		}
+
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+		reg &= ~MAX8998_LDO8;
+		ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
+		if (ret) {
+			puts("MAX8998 LDO setting error!\n");
+			return -EINVAL;
+		}
+		status = 0;
+	}
+	udelay(10000);
+	return 0;
+}
+
+struct dwc2_plat_otg_data s5pc110_otg_data = {
+	.phy_control = s5pc1xx_phy_control,
+	.regs_phy = S5PC110_PHY_BASE,
+	.regs_otg = S5PC110_OTG_BASE,
+	.usb_phy_ctrl = S5PC110_USB_PHY_CONTROL,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	debug("USB_udc_probe\n");
+	return dwc2_udc_probe(&s5pc110_otg_data);
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+	return 0;
+}
+#endif
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
diff --git a/roms/u-boot/board/samsung/goni/lowlevel_init.S b/roms/u-boot/board/samsung/goni/lowlevel_init.S
new file mode 100644
index 000000000..d38412e2c
--- /dev/null
+++ b/roms/u-boot/board/samsung/goni/lowlevel_init.S
@@ -0,0 +1,444 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has S5PC100 GPIO base, 0xE0300000
+ * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
+ * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
+ */
+
+	.globl lowlevel_init
+lowlevel_init:
+	mov	r11, lr
+
+	/* r5 has always zero */
+	mov	r5, #0
+
+	ldr	r7, =S5PC100_GPIO_BASE
+	ldr	r8, =S5PC100_GPIO_BASE
+	/* Read CPU ID */
+	ldr	r2, =S5PC110_PRO_ID
+	ldr	r0, [r2]
+	mov	r1, #0x00010000
+	and	r0, r0, r1
+	cmp	r0, r5
+	beq	100f
+	ldr	r8, =S5PC110_GPIO_BASE
+100:
+	/* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
+	cmp	r7, r8
+	beq	skip_check_didle			@ Support C110 only
+
+	ldr	r0, =S5PC110_RST_STAT
+	ldr	r1, [r0]
+	and	r1, r1, #0x000D0000
+	cmp	r1, #(0x1 << 19)			@ DEEPIDLE_WAKEUP
+	beq	didle_wakeup
+	cmp	r7, r8
+
+skip_check_didle:
+	addeq	r0, r8, #0x280				@ S5PC100_GPIO_J4
+	addne	r0, r8, #0x2C0				@ S5PC110_GPIO_J4
+	ldr	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
+	bic	r1, r1, #(0xf << 4)			@ 1 * 4-bit
+	orr	r1, r1, #(0x1 << 4)
+	str	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
+
+	ldr	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
+	bic	r1, r1, #(1 << 1)
+	str	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
+
+	/* Don't setup at s5pc100 */
+	beq	100f
+
+	/*
+	 * Initialize Async Register Setting for EVT1
+	 * Because we are setting EVT1 as the default value of EVT0,
+	 * setting EVT0 as well does not make things worse.
+	 * Thus, for the simplicity, we set for EVT0, too
+	 *
+	 * The "Async Registers" are:
+	 *	0xE0F0_0000
+	 *	0xE1F0_0000
+	 *	0xF180_0000
+	 *	0xF190_0000
+	 *	0xF1A0_0000
+	 *	0xF1B0_0000
+	 *	0xF1C0_0000
+	 *	0xF1D0_0000
+	 *	0xF1E0_0000
+	 *	0xF1F0_0000
+	 *	0xFAF0_0000
+	 */
+	ldr     r0, =0xe0f00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xe1f00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1800000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1900000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1a00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1b00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1c00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1d00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1e00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1f00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xfaf00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	/*
+	 * Diable ABB block to reduce sleep current at low temperature
+	 * Note that it's hidden register setup don't modify it
+	 */
+	ldr	r0, =0xE010C300
+	ldr	r1, =0x00800000
+	str	r1, [r0]
+
+100:
+	/* IO retension release */
+	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
+	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
+	ldr	r1, [r0]
+	ldreq	r2, =(1 << 31)				@ IO_RET_REL
+	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
+	orr	r1, r1, r2
+	/* Do not release retention here for S5PC110 */
+	streq	r1, [r0]
+
+	/* Disable Watchdog */
+	ldreq	r0, =S5PC100_WATCHDOG_BASE		@ 0xEA200000
+	ldrne	r0, =S5PC110_WATCHDOG_BASE		@ 0xE2700000
+	str	r5, [r0]
+
+	/* setting SRAM */
+	ldreq	r0, =S5PC100_SROMC_BASE
+	ldrne	r0, =S5PC110_SROMC_BASE
+	ldr	r1, =0x9
+	str	r1, [r0]
+
+	/* S5PC100 has 3 groups of interrupt sources */
+	ldreq	r0, =S5PC100_VIC0_BASE			@ 0xE4000000
+	ldrne	r0, =S5PC110_VIC0_BASE			@ 0xF2000000
+	add	r1, r0, #0x00100000
+	add	r2, r0, #0x00200000
+
+	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
+	mvn	r3, #0x0
+	str	r3, [r0, #0x14]				@ INTENCLEAR
+	str	r3, [r1, #0x14]				@ INTENCLEAR
+	str	r3, [r2, #0x14]				@ INTENCLEAR
+
+	/* Set all interrupts as IRQ */
+	str	r5, [r0, #0xc]				@ INTSELECT
+	str	r5, [r1, #0xc]				@ INTSELECT
+	str	r5, [r2, #0xc]				@ INTSELECT
+
+	/* Pending Interrupt Clear */
+	str	r5, [r0, #0xf00]			@ INTADDRESS
+	str	r5, [r1, #0xf00]			@ INTADDRESS
+	str	r5, [r2, #0xf00]			@ INTADDRESS
+
+	/* for UART */
+	bl	uart_asm_init
+
+	bl	internal_ram_init
+
+	cmp	r7, r8
+	/* Clear wakeup status register */
+	ldreq	r0, =S5PC100_WAKEUP_STAT
+	ldrne	r0, =S5PC110_WAKEUP_STAT
+	ldr	r1, [r0]
+	str	r1, [r0]
+
+	/* IO retension release */
+	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
+	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
+	ldr	r1, [r0]
+	ldreq	r2, =(1 << 31)				@ IO_RET_REL
+	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
+	orr	r1, r1, r2
+	str	r1, [r0]
+
+	b	1f
+
+didle_wakeup:
+	/* Wait when APLL is locked */
+	ldr	r0, =0xE0100100			@ S5PC110_APLL_CON
+lockloop:
+	ldr	r1, [r0]
+	and	r1, r1, #(1 << 29)
+	cmp	r1, #(1 << 29)
+	bne	lockloop
+
+	ldr	r0, =S5PC110_INFORM0
+	ldr	r1, [r0]
+	mov	pc, r1
+	nop
+	nop
+	nop
+	nop
+	nop
+
+1:
+	mov	lr, r11
+	mov	pc, lr
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
+
+	/* Check S5PC100 */
+	cmp	r7, r8
+	bne	110f
+100:
+	/* Set Lock Time */
+	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
+	str	r1, [r0, #0x000]		@ S5PC100_APLL_LOCK
+	str	r1, [r0, #0x004]		@ S5PC100_MPLL_LOCK
+	str	r1, [r0, #0x008]		@ S5PC100_EPLL_LOCK
+	str	r1, [r0, #0x00C]		@ S5PC100_HPLL_LOCK
+
+	/* S5P_APLL_CON */
+	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
+	str	r1, [r0, #0x100]
+	/* S5P_MPLL_CON */
+	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
+	str	r1, [r0, #0x104]
+	/* S5P_EPLL_CON */
+	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
+	str	r1, [r0, #0x108]
+	/* S5P_HPLL_CON */
+	ldr	r1, =0x80600603		@ SDIV 3, PDIV 6, MDIV 96
+	str	r1, [r0, #0x10C]
+
+	ldr     r1, [r0, #0x300]
+	ldr     r2, =0x00003fff
+	bic     r1, r1, r2
+	ldr     r2, =0x00011301
+
+	orr	r1, r1, r2
+	str	r1, [r0, #0x300]
+	ldr     r1, [r0, #0x304]
+	ldr     r2, =0x00011110
+	orr     r1, r1, r2
+	str     r1, [r0, #0x304]
+	ldr     r1, =0x00000001
+	str     r1, [r0, #0x308]
+
+	/* Set Source Clock */
+	ldr	r1, =0x00001111			@ A, M, E, HPLL Muxing
+	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
+
+	b	200f
+110:
+	ldr	r0, =0xE010C000			@ S5PC110_PWR_CFG
+
+	/* Set OSC_FREQ value */
+	ldr	r1, =0xf
+	str	r1, [r0, #0x100]		@ S5PC110_OSC_FREQ
+
+	/* Set MTC_STABLE value */
+	ldr	r1, =0xffffffff
+	str	r1, [r0, #0x110]		@ S5PC110_MTC_STABLE
+
+	/* Set CLAMP_STABLE value */
+	ldr	r1, =0x3ff03ff
+	str	r1, [r0, #0x114]		@ S5PC110_CLAMP_STABLE
+
+	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
+
+	/* Set Clock divider */
+	ldr	r1, =0x14131330			@ 1:1:4:4, 1:4:5
+	str	r1, [r0, #0x300]
+	ldr	r1, =0x11110111			@ UART[3210]: MMC[3210]
+	str	r1, [r0, #0x310]
+
+	/* Set Lock Time */
+	ldr	r1, =0x2cf			@ Locktime : 30us
+	str	r1, [r0, #0x000]		@ S5PC110_APLL_LOCK
+	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
+	str	r1, [r0, #0x008]		@ S5PC110_MPLL_LOCK
+	str	r1, [r0, #0x010]		@ S5PC110_EPLL_LOCK
+	str	r1, [r0, #0x020]		@ S5PC110_VPLL_LOCK
+
+	/* S5PC110_APLL_CON */
+	ldr	r1, =0x80C80601			@ 800MHz
+	str	r1, [r0, #0x100]
+	/* S5PC110_MPLL_CON */
+	ldr	r1, =0x829B0C01			@ 667MHz
+	str	r1, [r0, #0x108]
+	/* S5PC110_EPLL_CON */
+	ldr	r1, =0x80600602			@  96MHz VSEL 0 P 6 M 96 S 2
+	str	r1, [r0, #0x110]
+	/* S5PC110_VPLL_CON */
+	ldr	r1, =0x806C0603			@  54MHz
+	str	r1, [r0, #0x120]
+
+	/* Set Source Clock */
+	ldr	r1, =0x10001111			@ A, M, E, VPLL Muxing
+	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
+
+	/* OneDRAM(DMC0) clock setting */
+	ldr	r1, =0x01000000			@ ONEDRAM_SEL[25:24] 1 SCLKMPLL
+	str	r1, [r0, #0x218]		@ S5PC110_CLK_SRC6
+	ldr	r1, =0x30000000			@ ONEDRAM_RATIO[31:28] 3 + 1
+	str	r1, [r0, #0x318]		@ S5PC110_CLK_DIV6
+
+	/* XCLKOUT = XUSBXTI 24MHz */
+	add	r2, r0, #0xE000			@ S5PC110_OTHERS
+	ldr     r1, [r2]
+	orr	r1, r1, #(0x3 << 8)		@ CLKOUT[9:8] 3 XUSBXTI
+	str	r1, [r2]
+
+	/* CLK_IP0 */
+	ldr	r1, =0x8fefeeb			@ DMC[1:0] PDMA0[3] IMEM[5]
+	str	r1, [r0, #0x460]		@ S5PC110_CLK_IP0
+
+	/* CLK_IP1 */
+	ldr	r1, =0xe9fdf0f9			@ FIMD[0] USBOTG[16]
+						@ NANDXL[24]
+	str	r1, [r0, #0x464]		@ S5PC110_CLK_IP1
+
+	/* CLK_IP2 */
+	ldr	r1, =0xf75f7fc			@ CORESIGHT[8] MODEM[9]
+						@ HOSTIF[10] HSMMC0[16]
+						@ HSMMC2[18] VIC[27:24]
+	str	r1, [r0, #0x468]		@ S5PC110_CLK_IP2
+
+	/* CLK_IP3 */
+	ldr	r1, =0x8eff038c			@ I2C[8:6]
+						@ SYSTIMER[16] UART0[17]
+						@ UART1[18] UART2[19]
+						@ UART3[20] WDT[22]
+						@ PWM[23] GPIO[26] SYSCON[27]
+	str	r1, [r0, #0x46c]		@ S5PC110_CLK_IP3
+
+	/* CLK_IP4 */
+	ldr	r1, =0xfffffff1			@ CHIP_ID[0] TZPC[8:5]
+	str	r1, [r0, #0x470]		@ S5PC110_CLK_IP3
+
+200:
+	/* wait at least 200us to stablize all clock */
+	mov	r2, #0x10000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	mov	pc, lr
+
+internal_ram_init:
+	ldreq	r0, =0xE3800000
+	ldrne	r0, =0xF1500000
+	ldr	r1, =0x0
+	str	r1, [r0]
+
+	mov	pc, lr
+
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+	/* set GPIO to enable UART0-UART4 */
+	mov	r0, r8
+	ldr	r1, =0x22222222
+	str	r1, [r0, #0x0]			@ S5PC100_GPIO_A0_OFFSET
+	ldr	r1, =0x00002222
+	str	r1, [r0, #0x20]			@ S5PC100_GPIO_A1_OFFSET
+
+	/* Check S5PC100 */
+	cmp	r7, r8
+	bne	110f
+
+	/* UART_SEL GPK0[5] at S5PC100 */
+	add	r0, r8, #0x2A0			@ S5PC100_GPIO_K0_OFFSET
+	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
+	bic	r1, r1, #(0xf << 20)		@ 20 = 5 * 4-bit
+	orr	r1, r1, #(0x1 << 20)		@ Output
+	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
+
+	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
+	bic	r1, r1, #(0x3 << 10)		@ 10 = 5 * 2-bit
+	orr	r1, r1, #(0x2 << 10)		@ Pull-up enabled
+	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
+
+	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
+	orr	r1, r1, #(1 << 5)		@ 5 = 5 * 1-bit
+	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
+
+	b	200f
+110:
+	/*
+	 * Note that the following address
+	 * 0xE020'0360 is reserved address at S5PC100
+	 */
+	/* UART_SEL MP0_5[7] at S5PC110 */
+	add	r0, r8, #0x360			@ S5PC110_GPIO_MP0_5_OFFSET
+	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
+	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
+	orr	r1, r1, #(0x1 << 28)		@ Output
+	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
+
+	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
+	bic	r1, r1, #(0x3 << 14)		@ 14 = 7 * 2-bit
+	orr	r1, r1, #(0x2 << 14)		@ Pull-up enabled
+	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
+
+	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
+	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
+	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
+200:
+	mov	pc, lr
diff --git a/roms/u-boot/board/samsung/goni/onenand.c b/roms/u-boot/board/samsung/goni/onenand.c
new file mode 100644
index 000000000..9f2179543
--- /dev/null
+++ b/roms/u-boot/board/samsung/goni/onenand.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ */
+
+#include <common.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+#include <onenand_uboot.h>
+
+int onenand_board_init(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+	this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
+	this->chip_probe = s5pc110_chip_probe;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/samsung/odroid/Kconfig b/roms/u-boot/board/samsung/odroid/Kconfig
new file mode 100644
index 000000000..8b52a0d58
--- /dev/null
+++ b/roms/u-boot/board/samsung/odroid/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ODROID
+
+config SYS_BOARD
+	default "odroid"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "odroid"
+
+endif
diff --git a/roms/u-boot/board/samsung/odroid/MAINTAINERS b/roms/u-boot/board/samsung/odroid/MAINTAINERS
new file mode 100644
index 000000000..3f2cf14be
--- /dev/null
+++ b/roms/u-boot/board/samsung/odroid/MAINTAINERS
@@ -0,0 +1,6 @@
+ODROID BOARD
+M:	Jaehoon Chung <jh80.chung@samsung.com>
+S:	Maintained
+F:	board/samsung/odroid/
+F:	include/configs/odroid.h
+F:	configs/odroid_defconfig
diff --git a/roms/u-boot/board/samsung/odroid/Makefile b/roms/u-boot/board/samsung/odroid/Makefile
new file mode 100644
index 000000000..5bf48313d
--- /dev/null
+++ b/roms/u-boot/board/samsung/odroid/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
+# Przemyslaw Marczak <p.marczak@samsung.com>
+
+obj-y	:= odroid.o
diff --git a/roms/u-boot/board/samsung/odroid/odroid.c b/roms/u-boot/board/samsung/odroid/odroid.c
new file mode 100644
index 000000000..90aab62d3
--- /dev/null
+++ b/roms/u-boot/board/samsung/odroid/odroid.c
@@ -0,0 +1,540 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/arch/cpu.h>
+#include <dm.h>
+#include <env.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/max77686_pmic.h>
+#include <errno.h>
+#include <mmc.h>
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+#include <samsung/misc.h>
+#include "setup.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_BOARD_TYPES
+/* Odroid board types */
+enum {
+	ODROID_TYPE_U3,
+	ODROID_TYPE_X2,
+	ODROID_TYPES,
+};
+
+void set_board_type(void)
+{
+	/* Set GPA1 pin 1 to HI - enable XCL205 output */
+	writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON);
+	writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4);
+	writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8);
+	writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc);
+
+	/* Set GPC1 pin 2 to IN - check XCL205 output state */
+	writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON);
+	writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8);
+
+	/* XCL205 - needs some latch time */
+	sdelay(200000);
+
+	/* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
+	if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN))
+		gd->board_type = ODROID_TYPE_X2;
+	else
+		gd->board_type = ODROID_TYPE_U3;
+}
+
+void set_board_revision(void)
+{
+	/*
+	 * Revision already set by set_board_type() because it can be
+	 * executed early.
+	 */
+}
+
+const char *get_board_type(void)
+{
+	const char *board_type[] = {"u3", "x2"};
+
+	return board_type[gd->board_type];
+}
+#endif
+
+#ifdef CONFIG_SET_DFU_ALT_INFO
+char *get_dfu_alt_system(char *interface, char *devstr)
+{
+	return env_get("dfu_alt_system");
+}
+
+char *get_dfu_alt_boot(char *interface, char *devstr)
+{
+	struct mmc *mmc;
+	char *alt_boot;
+	int dev_num;
+
+	dev_num = simple_strtoul(devstr, NULL, 10);
+
+	mmc = find_mmc_device(dev_num);
+	if (!mmc)
+		return NULL;
+
+	if (mmc_init(mmc))
+		return NULL;
+
+	alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD :
+				CONFIG_DFU_ALT_BOOT_EMMC;
+
+	return alt_boot;
+}
+#endif
+
+static void board_clock_init(void)
+{
+	unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
+	struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
+						samsung_get_base_clock();
+
+	/*
+	 * CMU_CPU clocks src to MPLL
+	 * Bit values:                 0  ; 1
+	 * MUX_APLL_SEL:        FIN_PLL   ; FOUT_APLL
+	 * MUX_CORE_SEL:        MOUT_APLL ; SCLK_MPLL
+	 * MUX_HPM_SEL:         MOUT_APLL ; SCLK_MPLL_USER_C
+	 * MUX_MPLL_USER_SEL_C: FIN_PLL   ; SCLK_MPLL
+	*/
+	clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
+		      MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
+	set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
+	      MUX_MPLL_USER_SEL_C(1);
+
+	clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
+
+	/* Wait for mux change */
+	while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
+		continue;
+
+	/* Set APLL to 1000MHz */
+	clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
+	set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
+
+	clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
+
+	/* Wait for PLL to be locked */
+	while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
+		continue;
+
+	/* Set CMU_CPU clocks src to APLL */
+	set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
+	      MUX_MPLL_USER_SEL_C(1);
+	clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
+
+	/* Wait for mux change */
+	while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
+		continue;
+
+	set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
+	      PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
+	      APLL_RATIO(0) | CORE2_RATIO(0);
+	/*
+	 * Set dividers for MOUTcore = 1000 MHz
+	 * coreout =      MOUT / (ratio + 1) = 1000 MHz (0)
+	 * corem0 =     armclk / (ratio + 1) = 333 MHz (2)
+	 * corem1 =     armclk / (ratio + 1) = 166 MHz (5)
+	 * periph =     armclk / (ratio + 1) = 1000 MHz (0)
+	 * atbout =       MOUT / (ratio + 1) = 200 MHz (4)
+	 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
+	 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
+	 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
+	*/
+	clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
+	      PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
+	      APLL_RATIO(7) | CORE2_RATIO(7);
+
+	clrsetbits_le32(&clk->div_cpu0, clr, set);
+
+	/* Wait for divider ready status */
+	while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
+		continue;
+
+	/*
+	 * For MOUThpm = 1000 MHz (MOUTapll)
+	 * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
+	 * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
+	 * cores_out = armclk / (ratio + 1) = 200 (4)
+	 */
+	clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
+	set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
+
+	clrsetbits_le32(&clk->div_cpu1, clr, set);
+
+	/* Wait for divider ready status */
+	while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
+		continue;
+
+	/*
+	 * Set CMU_DMC clocks src to APLL
+	 * Bit values:             0  ; 1
+	 * MUX_C2C_SEL:      SCLKMPLL ; SCLKAPLL
+	 * MUX_DMC_BUS_SEL:  SCLKMPLL ; SCLKAPLL
+	 * MUX_DPHY_SEL:     SCLKMPLL ; SCLKAPLL
+	 * MUX_MPLL_SEL:     FINPLL   ; MOUT_MPLL_FOUT
+	 * MUX_PWI_SEL:      0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
+	 * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
+	 * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
+	 * MUX_G2D_ACP_SEL:  OUT_ACP0 ; OUT_ACP1
+	*/
+	clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
+		      MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
+		      MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
+		      MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
+	set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
+	      MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
+	      MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
+
+	clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
+
+	/* Wait for mux change */
+	while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
+		continue;
+
+	/* Set MPLL to 800MHz */
+	set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
+
+	clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
+
+	/* Wait for PLL to be locked */
+	while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
+		continue;
+
+	/* Switch back CMU_DMC mux */
+	set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
+	      MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
+	      MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
+
+	clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
+
+	/* Wait for mux change */
+	while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
+		continue;
+
+	/* CLK_DIV_DMC0 */
+	clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
+	      DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
+	/*
+	 * For:
+	 * MOUTdmc = 800 MHz
+	 * MOUTdphy = 800 MHz
+	 *
+	 * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
+	 * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
+	 * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
+	 * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
+	 * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
+	 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
+	 */
+	set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
+	      DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
+
+	clrsetbits_le32(&clk->div_dmc0, clr, set);
+
+	/* Wait for divider ready status */
+	while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
+		continue;
+
+	/* CLK_DIV_DMC1 */
+	clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
+	      C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
+	/*
+	 * For:
+	 * MOUTg2d = 800 MHz
+	 * MOUTc2c = 800 Mhz
+	 * MOUTpwi = 108 MHz
+	 *
+	 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
+	 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
+	 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
+	 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
+	 */
+	set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
+	      C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
+
+	clrsetbits_le32(&clk->div_dmc1, clr, set);
+
+	/* Wait for divider ready status */
+	while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
+		continue;
+
+	/* CLK_SRC_PERIL0 */
+	clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
+	      UART3_SEL(15) | UART4_SEL(15);
+	/*
+	 * Set CLK_SRC_PERIL0 clocks src to MPLL
+	 * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
+	 *             5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
+	 *             8(SCLK_VPLL)
+	 *
+	 * Set all to SCLK_MPLL_USER_T
+	 */
+	set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
+	      UART4_SEL(6);
+
+	clrsetbits_le32(&clk->src_peril0, clr, set);
+
+	/* CLK_DIV_PERIL0 */
+	clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
+	      UART3_RATIO(15) | UART4_RATIO(15);
+	/*
+	 * For MOUTuart0-4: 800MHz
+	 *
+	 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
+	*/
+	set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
+	      UART3_RATIO(7) | UART4_RATIO(7);
+
+	clrsetbits_le32(&clk->div_peril0, clr, set);
+
+	while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
+		continue;
+
+	/* CLK_DIV_FSYS1 */
+	clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
+	      MMC1_PRE_RATIO(255);
+	/*
+	 * For MOUTmmc0-3 = 800 MHz (MPLL)
+	 *
+	 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
+	 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
+	 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
+	 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
+	*/
+	set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
+	      MMC1_PRE_RATIO(1);
+
+	clrsetbits_le32(&clk->div_fsys1, clr, set);
+
+	/* Wait for divider ready status */
+	while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
+		continue;
+
+	/* CLK_DIV_FSYS2 */
+	clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
+	      MMC3_PRE_RATIO(255);
+	/*
+	 * For MOUTmmc0-3 = 800 MHz (MPLL)
+	 *
+	 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
+	 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
+	 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
+	 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
+	*/
+	set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
+	      MMC3_PRE_RATIO(1);
+
+	clrsetbits_le32(&clk->div_fsys2, clr, set);
+
+	/* Wait for divider ready status */
+	while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
+		continue;
+
+	/* CLK_DIV_FSYS3 */
+	clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
+	/*
+	 * For MOUTmmc4 = 800 MHz (MPLL)
+	 *
+	 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
+	 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
+	*/
+	set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
+
+	clrsetbits_le32(&clk->div_fsys3, clr, set);
+
+	/* Wait for divider ready status */
+	while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
+		continue;
+
+	return;
+}
+
+static void board_gpio_init(void)
+{
+	/* eMMC Reset Pin */
+	gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
+
+	gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
+	gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
+	gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
+
+	/* Enable FAN (Odroid U3) */
+	gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
+
+	gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
+	gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
+	gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
+
+	/* OTG Vbus output (Odroid U3+) */
+	gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
+
+	gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
+	gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
+	gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
+
+	/* OTG INT (Odroid U3+) */
+	gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
+
+	gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
+	gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
+	gpio_direction_input(EXYNOS4X12_GPIO_X31);
+
+	/* Blue LED (Odroid X2/U2/U3) */
+	gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
+
+	gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
+
+#ifdef CONFIG_CMD_USB
+	/* USB3503A Reference frequency */
+	gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
+
+	/* USB3503A Connect */
+	gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
+
+	/* USB3503A Reset */
+	gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
+#endif
+}
+
+int exynos_early_init_f(void)
+{
+	board_clock_init();
+
+	return 0;
+}
+
+int exynos_init(void)
+{
+	board_gpio_init();
+
+	return 0;
+}
+
+int exynos_power_init(void)
+{
+	const char *mmc_regulators[] = {
+		"VDDQ_EMMC_1.8V",
+		"VDDQ_EMMC_2.8V",
+		"TFLASH_2.8V",
+		NULL,
+	};
+
+	if (regulator_list_autoset(mmc_regulators, NULL, true))
+		pr_err("Unable to init all mmc regulators\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_GADGET
+static int s5pc210_phy_control(int on)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = regulator_get_by_platname("VDD_UOTG_3.0V", &dev);
+	if (ret) {
+		pr_err("Regulator get error: %d\n", ret);
+		return ret;
+	}
+
+	if (on)
+		return regulator_set_mode(dev, OPMODE_ON);
+	else
+		return regulator_set_mode(dev, OPMODE_LPM);
+}
+
+struct dwc2_plat_otg_data s5pc210_otg_data = {
+	.phy_control	= s5pc210_phy_control,
+	.regs_phy	= EXYNOS4X12_USBPHY_BASE,
+	.regs_otg	= EXYNOS4X12_USBOTG_BASE,
+	.usb_phy_ctrl	= EXYNOS4X12_USBPHY_CONTROL,
+	.usb_flags	= PHY0_SLEEP,
+};
+#endif
+
+#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
+
+static void set_usb3503_ref_clk(void)
+{
+#ifdef CONFIG_BOARD_TYPES
+	/*
+	 * gpx3-0 chooses primary (low) or secondary (high) reference clock
+	 * frequencies table.  The choice of clock is done through hard-wired
+	 * REF_SEL pins.
+	 * The Odroid Us have reference clock at 24 MHz (00 entry from secondary
+	 * table) and Odroid Xs have it at 26 MHz (01 entry from primary table).
+	 */
+	if (gd->board_type == ODROID_TYPE_U3)
+		gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
+	else
+		gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
+#else
+	/* Choose Odroid Xs frequency without board types */
+	gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
+#endif /* CONFIG_BOARD_TYPES */
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+#ifdef CONFIG_CMD_USB
+	struct udevice *dev;
+	int ret;
+
+	set_usb3503_ref_clk();
+
+	/* Disconnect, Reset, Connect */
+	gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
+	gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
+	gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
+	gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
+
+	/* Power off and on BUCK8 for LAN9730 */
+	debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
+
+	ret = regulator_get_by_platname("VCC_P3V3_2.85V", &dev);
+	if (ret) {
+		pr_err("Regulator get error: %d\n", ret);
+		return ret;
+	}
+
+	ret = regulator_set_enable(dev, true);
+	if (ret) {
+		pr_err("Regulator %s enable setting error: %d\n", dev->name, ret);
+		return ret;
+	}
+
+	ret = regulator_set_value(dev, 750000);
+	if (ret) {
+		pr_err("Regulator %s value setting error: %d\n", dev->name, ret);
+		return ret;
+	}
+
+	ret = regulator_set_value(dev, 3300000);
+	if (ret) {
+		pr_err("Regulator %s value setting error: %d\n", dev->name, ret);
+		return ret;
+	}
+#endif
+	debug("USB_udc_probe\n");
+	return dwc2_udc_probe(&s5pc210_otg_data);
+}
+#endif
diff --git a/roms/u-boot/board/samsung/odroid/setup.h b/roms/u-boot/board/samsung/odroid/setup.h
new file mode 100644
index 000000000..5ee97ee25
--- /dev/null
+++ b/roms/u-boot/board/samsung/odroid/setup.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ */
+
+#ifndef __ODROIDU3_SETUP__
+#define __ODROIDU3_SETUP__
+
+/* A/M PLL_CON0 */
+#define SDIV(x)                 ((x) & 0x7)
+#define PDIV(x)                 (((x) & 0x3f) << 8)
+#define MDIV(x)                 (((x) & 0x3ff) << 16)
+#define FSEL(x)                 (((x) & 0x1) << 27)
+#define PLL_LOCKED_BIT          (0x1 << 29)
+#define PLL_ENABLE(x)           (((x) & 0x1) << 31)
+
+/* CLK_SRC_CPU */
+#define MUX_APLL_SEL(x)         ((x) & 0x1)
+#define MUX_CORE_SEL(x)         (((x) & 0x1) << 16)
+#define MUX_HPM_SEL(x)          (((x) & 0x1) << 20)
+#define MUX_MPLL_USER_SEL_C(x)  (((x) & 0x1) << 24)
+
+#define MUX_STAT_CHANGING       0x100
+
+/* CLK_MUX_STAT_CPU */
+#define APLL_SEL(x)             ((x) & 0x7)
+#define CORE_SEL(x)             (((x) & 0x7) << 16)
+#define HPM_SEL(x)              (((x) & 0x7) << 20)
+#define MPLL_USER_SEL_C(x)      (((x) & 0x7) << 24)
+#define MUX_STAT_CPU_CHANGING   (APLL_SEL(MUX_STAT_CHANGING) | \
+				CORE_SEL(MUX_STAT_CHANGING) | \
+				HPM_SEL(MUX_STAT_CHANGING) | \
+				MPLL_USER_SEL_C(MUX_STAT_CHANGING))
+
+/* CLK_DIV_CPU0 */
+#define CORE_RATIO(x)           ((x) & 0x7)
+#define COREM0_RATIO(x)         (((x) & 0x7) << 4)
+#define COREM1_RATIO(x)         (((x) & 0x7) << 8)
+#define PERIPH_RATIO(x)         (((x) & 0x7) << 12)
+#define ATB_RATIO(x)            (((x) & 0x7) << 16)
+#define PCLK_DBG_RATIO(x)       (((x) & 0x7) << 20)
+#define APLL_RATIO(x)           (((x) & 0x7) << 24)
+#define CORE2_RATIO(x)          (((x) & 0x7) << 28)
+
+/* CLK_DIV_STAT_CPU0 */
+#define DIV_CORE(x)             ((x) & 0x1)
+#define DIV_COREM0(x)           (((x) & 0x1) << 4)
+#define DIV_COREM1(x)           (((x) & 0x1) << 8)
+#define DIV_PERIPH(x)           (((x) & 0x1) << 12)
+#define DIV_ATB(x)              (((x) & 0x1) << 16)
+#define DIV_PCLK_DBG(x)         (((x) & 0x1) << 20)
+#define DIV_APLL(x)             (((x) & 0x1) << 24)
+#define DIV_CORE2(x)            (((x) & 0x1) << 28)
+
+#define DIV_STAT_CHANGING       0x1
+#define DIV_STAT_CPU0_CHANGING  (DIV_CORE(DIV_STAT_CHANGING) | \
+				DIV_COREM0(DIV_STAT_CHANGING) | \
+				DIV_COREM1(DIV_STAT_CHANGING) | \
+				DIV_PERIPH(DIV_STAT_CHANGING) | \
+				DIV_ATB(DIV_STAT_CHANGING) | \
+				DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
+				DIV_APLL(DIV_STAT_CHANGING) | \
+				DIV_CORE2(DIV_STAT_CHANGING))
+
+/* CLK_DIV_CPU1 */
+#define COPY_RATIO(x)           ((x) & 0x7)
+#define HPM_RATIO(x)            (((x) & 0x7) << 4)
+#define CORES_RATIO(x)          (((x) & 0x7) << 8)
+
+/* CLK_DIV_STAT_CPU1 */
+#define DIV_COPY(x)             ((x) & 0x7)
+#define DIV_HPM(x)              (((x) & 0x1) << 4)
+#define DIV_CORES(x)            (((x) & 0x1) << 8)
+
+#define DIV_STAT_CPU1_CHANGING	(DIV_COPY(DIV_STAT_CHANGING) | \
+				DIV_HPM(DIV_STAT_CHANGING) | \
+				DIV_CORES(DIV_STAT_CHANGING))
+
+/* CLK_SRC_DMC */
+#define MUX_C2C_SEL(x)		((x) & 0x1)
+#define MUX_DMC_BUS_SEL(x)	(((x) & 0x1) << 4)
+#define MUX_DPHY_SEL(x)		(((x) & 0x1) << 8)
+#define MUX_MPLL_SEL(x)		(((x) & 0x1) << 12)
+#define MUX_PWI_SEL(x)		(((x) & 0xf) << 16)
+#define MUX_G2D_ACP0_SEL(x)	(((x) & 0x1) << 20)
+#define MUX_G2D_ACP1_SEL(x)	(((x) & 0x1) << 24)
+#define MUX_G2D_ACP_SEL(x)	(((x) & 0x1) << 28)
+
+/* CLK_MUX_STAT_DMC */
+#define C2C_SEL(x)		(((x)) & 0x7)
+#define DMC_BUS_SEL(x)		(((x) & 0x7) << 4)
+#define DPHY_SEL(x)		(((x) & 0x7) << 8)
+#define MPLL_SEL(x)		(((x) & 0x7) << 12)
+/* #define PWI_SEL(x)		(((x) & 0xf) << 16)  - Reserved */
+#define G2D_ACP0_SEL(x)		(((x) & 0x7) << 20)
+#define G2D_ACP1_SEL(x)		(((x) & 0x7) << 24)
+#define G2D_ACP_SEL(x)		(((x) & 0x7) << 28)
+
+#define MUX_STAT_DMC_CHANGING	(C2C_SEL(MUX_STAT_CHANGING) | \
+				DMC_BUS_SEL(MUX_STAT_CHANGING) | \
+				DPHY_SEL(MUX_STAT_CHANGING) | \
+				MPLL_SEL(MUX_STAT_CHANGING) |\
+				G2D_ACP0_SEL(MUX_STAT_CHANGING) | \
+				G2D_ACP1_SEL(MUX_STAT_CHANGING) | \
+				G2D_ACP_SEL(MUX_STAT_CHANGING))
+
+/* CLK_DIV_DMC0 */
+#define ACP_RATIO(x)		((x) & 0x7)
+#define ACP_PCLK_RATIO(x)	(((x) & 0x7) << 4)
+#define DPHY_RATIO(x)		(((x) & 0x7) << 8)
+#define DMC_RATIO(x)		(((x) & 0x7) << 12)
+#define DMCD_RATIO(x)		(((x) & 0x7) << 16)
+#define DMCP_RATIO(x)		(((x) & 0x7) << 20)
+
+/* CLK_DIV_STAT_DMC0 */
+#define DIV_ACP(x)		((x) & 0x1)
+#define DIV_ACP_PCLK(x)		(((x) & 0x1) << 4)
+#define DIV_DPHY(x)		(((x) & 0x1) << 8)
+#define DIV_DMC(x)		(((x) & 0x1) << 12)
+#define DIV_DMCD(x)		(((x) & 0x1) << 16)
+#define DIV_DMCP(x)		(((x) & 0x1) << 20)
+
+#define DIV_STAT_DMC0_CHANGING	(DIV_ACP(DIV_STAT_CHANGING) | \
+				DIV_ACP_PCLK(DIV_STAT_CHANGING) | \
+				DIV_DPHY(DIV_STAT_CHANGING) | \
+				DIV_DMC(DIV_STAT_CHANGING) | \
+				DIV_DMCD(DIV_STAT_CHANGING) | \
+				DIV_DMCP(DIV_STAT_CHANGING))
+
+/* CLK_DIV_DMC1 */
+#define G2D_ACP_RATIO(x)	((x) & 0xf)
+#define C2C_RATIO(x)		(((x) & 0x7) << 4)
+#define PWI_RATIO(x)		(((x) & 0xf) << 8)
+#define C2C_ACLK_RATIO(x)	(((x) & 0x7) << 12)
+#define DVSEM_RATIO(x)		(((x) & 0x7f) << 16)
+#define DPM_RATIO(x)		(((x) & 0x7f) << 24)
+
+/* CLK_DIV_STAT_DMC1 */
+#define DIV_G2D_ACP(x)		((x) & 0x1)
+#define DIV_C2C(x)		(((x) & 0x1) << 4)
+#define DIV_PWI(x)		(((x) & 0x1) << 8)
+#define DIV_C2C_ACLK(x)		(((x) & 0x1) << 12)
+#define DIV_DVSEM(x)		(((x) & 0x1) << 16)
+#define DIV_DPM(x)		(((x) & 0x1) << 24)
+
+#define DIV_STAT_DMC1_CHANGING	(DIV_G2D_ACP(DIV_STAT_CHANGING) | \
+				DIV_C2C(DIV_STAT_CHANGING) | \
+				DIV_PWI(DIV_STAT_CHANGING) | \
+				DIV_C2C_ACLK(DIV_STAT_CHANGING) | \
+				DIV_DVSEM(DIV_STAT_CHANGING) | \
+				DIV_DPM(DIV_STAT_CHANGING))
+
+/* Set CLK_SRC_PERIL0 */
+#define UART4_SEL(x)		(((x) & 0xf) << 16)
+#define UART3_SEL(x)		(((x) & 0xf) << 12)
+#define UART2_SEL(x)		(((x) & 0xf) << 8)
+#define UART1_SEL(x)		(((x) & 0xf) << 4)
+#define UART0_SEL(x)		((x) & 0xf)
+
+/* Set CLK_DIV_PERIL0 */
+#define UART4_RATIO(x)		(((x) & 0xf) << 16)
+#define UART3_RATIO(x)		(((x) & 0xf) << 12)
+#define UART2_RATIO(x)		(((x) & 0xf) << 8)
+#define UART1_RATIO(x)		(((x) & 0xf) << 4)
+#define UART0_RATIO(x)		((x) & 0xf)
+
+/* Set CLK_DIV_STAT_PERIL0 */
+#define DIV_UART4(x)		(((x) & 0x1) << 16)
+#define DIV_UART3(x)		(((x) & 0x1) << 12)
+#define DIV_UART2(x)		(((x) & 0x1) << 8)
+#define DIV_UART1(x)		(((x) & 0x1) << 4)
+#define DIV_UART0(x)		((x) & 0x1)
+
+#define DIV_STAT_PERIL0_CHANGING	(DIV_UART4(DIV_STAT_CHANGING) | \
+					DIV_UART3(DIV_STAT_CHANGING) | \
+					DIV_UART2(DIV_STAT_CHANGING) | \
+					DIV_UART1(DIV_STAT_CHANGING) | \
+					DIV_UART0(DIV_STAT_CHANGING))
+
+/* CLK_DIV_FSYS1 */
+#define MMC0_RATIO(x)		((x) & 0xf)
+#define MMC0_PRE_RATIO(x)	(((x) & 0xff) << 8)
+#define MMC1_RATIO(x)		(((x) & 0xf) << 16)
+#define MMC1_PRE_RATIO(x)	(((x) & 0xff) << 24)
+
+/* CLK_DIV_STAT_FSYS1 */
+#define DIV_MMC0(x)		((x) & 1)
+#define DIV_MMC0_PRE(x)		(((x) & 1) << 8)
+#define DIV_MMC1(x)		(((x) & 1) << 16)
+#define DIV_MMC1_PRE(x)		(((x) & 1) << 24)
+
+#define DIV_STAT_FSYS1_CHANGING		(DIV_MMC0(DIV_STAT_CHANGING) | \
+					DIV_MMC0_PRE(DIV_STAT_CHANGING) | \
+					DIV_MMC1(DIV_STAT_CHANGING) | \
+					DIV_MMC1_PRE(DIV_STAT_CHANGING))
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO(x)		((x) & 0xf)
+#define MMC2_PRE_RATIO(x)	(((x) & 0xff) << 8)
+#define MMC3_RATIO(x)		(((x) & 0xf) << 16)
+#define MMC3_PRE_RATIO(x)	(((x) & 0xff) << 24)
+
+/* CLK_DIV_STAT_FSYS2 */
+#define DIV_MMC2(x)		((x) & 0x1)
+#define DIV_MMC2_PRE(x)		(((x) & 0x1) << 8)
+#define DIV_MMC3(x)		(((x) & 0x1) << 16)
+#define DIV_MMC3_PRE(x)		(((x) & 0x1) << 24)
+
+#define DIV_STAT_FSYS2_CHANGING		(DIV_MMC2(DIV_STAT_CHANGING) | \
+					DIV_MMC2_PRE(DIV_STAT_CHANGING) | \
+					DIV_MMC3(DIV_STAT_CHANGING) | \
+					DIV_MMC3_PRE(DIV_STAT_CHANGING))
+
+/* CLK_DIV_FSYS3 */
+#define MMC4_RATIO(x)		((x) & 0x7)
+#define MMC4_PRE_RATIO(x)	(((x) & 0xff) << 8)
+
+/* CLK_DIV_STAT_FSYS3 */
+#define DIV_MMC4(x)		((x) & 0x1)
+#define DIV_MMC4_PRE(x)		(((x) & 0x1) << 8)
+
+#define DIV_STAT_FSYS3_CHANGING		(DIV_MMC4(DIV_STAT_CHANGING) | \
+					DIV_MMC4_PRE(DIV_STAT_CHANGING))
+
+/* XCL205 GPIO config - Odroid U3 */
+#define XCL205_GPIO_BASE		EXYNOS4X12_GPIO_PART1_BASE
+#define XCL205_EN_GPIO_OFFSET		0x20 /* GPA1 */
+#define XCL205_EN_GPIO_PIN		1
+#define XCL205_EN_GPIO_CON		(XCL205_GPIO_BASE + \
+					 XCL205_EN_GPIO_OFFSET)
+#define XCL205_EN_GPIO_CON_CFG		(S5P_GPIO_OUTPUT << \
+					 4 * XCL205_EN_GPIO_PIN)
+#define XCL205_EN_GPIO_DAT_CFG		(0x1 << XCL205_EN_GPIO_PIN)
+#define XCL205_EN_GPIO_PUD_CFG		(S5P_GPIO_PULL_UP << \
+					 2 * XCL205_EN_GPIO_PIN)
+#define XCL205_EN_GPIO_DRV_CFG		(S5P_GPIO_DRV_4X << \
+					 2 * XCL205_EN_GPIO_PIN)
+
+#define XCL205_STATE_GPIO_OFFSET	0x80 /* GPC1 */
+#define XCL205_STATE_GPIO_PIN		2
+#define XCL205_STATE_GPIO_CON		(XCL205_GPIO_BASE + \
+					 XCL205_STATE_GPIO_OFFSET)
+#define XCL205_STATE_GPIO_DAT		XCL205_STATE_GPIO_CON + 0x4
+#define XCL205_STATE_GPIO_CON_CFG	(S5P_GPIO_INPUT << \
+					4 * XCL205_STATE_GPIO_PIN)
+#define XCL205_STATE_GPIO_PUD_CFG	(S5P_GPIO_PULL_NONE << \
+					 2 * XCL205_STATE_GPIO_PIN)
+
+#ifdef CONFIG_BOARD_TYPES
+extern void sdelay(unsigned long);
+#endif
+
+#endif /*__ODROIDU3_SETUP__ */
diff --git a/roms/u-boot/board/samsung/origen/Kconfig b/roms/u-boot/board/samsung/origen/Kconfig
new file mode 100644
index 000000000..63e3efe21
--- /dev/null
+++ b/roms/u-boot/board/samsung/origen/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ORIGEN
+
+config SYS_BOARD
+	default "origen"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "origen"
+
+endif
diff --git a/roms/u-boot/board/samsung/origen/MAINTAINERS b/roms/u-boot/board/samsung/origen/MAINTAINERS
new file mode 100644
index 000000000..8fb8f8115
--- /dev/null
+++ b/roms/u-boot/board/samsung/origen/MAINTAINERS
@@ -0,0 +1,6 @@
+ORIGEN BOARD
+M:	Minkyu Kang <mk7.kang@samsung.com>
+S:	Maintained
+F:	board/samsung/origen/
+F:	include/configs/origen.h
+F:	configs/origen_defconfig
diff --git a/roms/u-boot/board/samsung/origen/Makefile b/roms/u-boot/board/samsung/origen/Makefile
new file mode 100644
index 000000000..44691af09
--- /dev/null
+++ b/roms/u-boot/board/samsung/origen/Makefile
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Samsung Electronics
+
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+
+hostprogs-y := tools/mkorigenspl
+always := $(hostprogs-y)
+
+# omit -O2 option to suppress
+#   warning: dereferencing type-punned pointer will break strict-aliasing rules
+#
+# TODO:
+# Fix the root cause in tools/mkorigenspl.c and delete the following work-around
+$(obj)/tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))
+else
+obj-y	+= origen.o
+endif
diff --git a/roms/u-boot/board/samsung/origen/origen.c b/roms/u-boot/board/samsung/origen/origen.c
new file mode 100644
index 000000000..e17454ad7
--- /dev/null
+++ b/roms/u-boot/board/samsung/origen/origen.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include <usb.h>
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int exynos_init(void)
+{
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int exynos_early_init_f(void)
+{
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/samsung/origen/tools/mkorigenspl.c b/roms/u-boot/board/samsung/origen/tools/mkorigenspl.c
new file mode 100644
index 000000000..f4be86724
--- /dev/null
+++ b/roms/u-boot/board/samsung/origen/tools/mkorigenspl.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <string.h>
+#include <sys/stat.h>
+
+#define BUFSIZE			(16*1024)
+#define IMG_SIZE		(16*1024)
+#define SPL_HEADER_SIZE		16
+#define FILE_PERM		(S_IRUSR | S_IWUSR | S_IRGRP \
+				| S_IWGRP | S_IROTH | S_IWOTH)
+#define SPL_HEADER		"S5PC210 HEADER  "
+/*
+* Requirement:
+* IROM code reads first 14K bytes from boot device.
+* It then calculates the checksum of 14K-4 bytes and compare with data at
+* 14K-4 offset.
+*
+* This function takes two filenames:
+* IN  "u-boot-spl.bin" and
+* OUT "$(BOARD)-spl.bin as filenames.
+* It reads the "u-boot-spl.bin" in 16K buffer.
+* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer.
+* It writes the buffer to "$(BOARD)-spl.bin" file.
+*/
+
+int main(int argc, char **argv)
+{
+	int i, len;
+	unsigned char buffer[BUFSIZE] = {0};
+	int ifd, ofd;
+	unsigned int checksum = 0, count;
+
+	if (argc != 3) {
+		printf(" %d Wrong number of arguments\n", argc);
+		exit(EXIT_FAILURE);
+	}
+
+	ifd = open(argv[1], O_RDONLY);
+	if (ifd < 0) {
+		fprintf(stderr, "%s: Can't open %s: %s\n",
+			argv[0], argv[1], strerror(errno));
+		exit(EXIT_FAILURE);
+	}
+
+	ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
+	if (ofd < 0) {
+		fprintf(stderr, "%s: Can't open %s: %s\n",
+			argv[0], argv[2], strerror(errno));
+		if (ifd)
+			close(ifd);
+		exit(EXIT_FAILURE);
+	}
+
+	len = lseek(ifd, 0, SEEK_END);
+	lseek(ifd, 0, SEEK_SET);
+
+	memcpy(&buffer[0], SPL_HEADER, SPL_HEADER_SIZE);
+
+	count = (len < (IMG_SIZE - SPL_HEADER_SIZE))
+		? len : (IMG_SIZE - SPL_HEADER_SIZE);
+
+	if (read(ifd, buffer + SPL_HEADER_SIZE, count) != count) {
+		fprintf(stderr, "%s: Can't read %s: %s\n",
+			argv[0], argv[1], strerror(errno));
+
+		if (ifd)
+			close(ifd);
+		if (ofd)
+			close(ofd);
+
+		exit(EXIT_FAILURE);
+	}
+
+	for (i = 0; i < IMG_SIZE - SPL_HEADER_SIZE; i++)
+		checksum += buffer[i+16];
+
+	*(unsigned long *)buffer ^= 0x1f;
+	*(unsigned long *)(buffer+4) ^= checksum;
+
+	for (i = 1; i < SPL_HEADER_SIZE; i++)
+		buffer[i] ^= buffer[i-1];
+
+	if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {
+		fprintf(stderr, "%s: Can't write %s: %s\n",
+			argv[0], argv[2], strerror(errno));
+
+		if (ifd)
+			close(ifd);
+		if (ofd)
+			close(ofd);
+
+		exit(EXIT_FAILURE);
+	}
+
+	if (ifd)
+		close(ifd);
+	if (ofd)
+		close(ofd);
+
+	return EXIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/samsung/smdk5250/Kconfig b/roms/u-boot/board/samsung/smdk5250/Kconfig
new file mode 100644
index 000000000..11ffaee5c
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdk5250/Kconfig
@@ -0,0 +1,38 @@
+if TARGET_SMDK5250
+
+config SYS_BOARD
+	default "smdk5250"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "smdk5250"
+
+endif
+
+if TARGET_SNOW
+
+config SYS_BOARD
+	default "smdk5250"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "snow"
+
+endif
+
+if TARGET_SPRING
+
+config SYS_BOARD
+	default "smdk5250"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "spring"
+
+endif
diff --git a/roms/u-boot/board/samsung/smdk5250/MAINTAINERS b/roms/u-boot/board/samsung/smdk5250/MAINTAINERS
new file mode 100644
index 000000000..c60b6f81e
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdk5250/MAINTAINERS
@@ -0,0 +1,18 @@
+SMDK5250 BOARD
+M:	Jaehoon Chung <jh80.chung@samsung.com>
+S:	Maintained
+F:	board/samsung/smdk5250/
+F:	include/configs/smdk5250.h
+F:	configs/smdk5250_defconfig
+
+SNOW BOARD
+M:	Jaehoon Chung <jh80.chung@samsung.com>
+S:	Maintained
+F:	include/configs/snow.h
+F:	configs/snow_defconfig
+
+SPRING BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	include/configs/spring.h
+F:	configs/spring_defconfig
diff --git a/roms/u-boot/board/samsung/smdk5250/Makefile b/roms/u-boot/board/samsung/smdk5250/Makefile
new file mode 100644
index 000000000..bab027727
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdk5250/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2012 Samsung Electronics
+
+obj-y	+= smdk5250_spl.o
diff --git a/roms/u-boot/board/samsung/smdk5250/smdk5250_spl.c b/roms/u-boot/board/samsung/smdk5250/smdk5250_spl.c
new file mode 100644
index 000000000..b0ef34dd6
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdk5250/smdk5250_spl.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/clk.h>
+
+#define SIGNATURE	0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+		__section(".machine_param") = {
+	.signature	= SIGNATURE,
+	.version	= 1,
+	.params		= "vmubfasirM",
+	.size		= sizeof(machine_param),
+
+	.mem_iv_size	= 0x1f,
+	.mem_type	= DDR_MODE_DDR3,
+
+	/*
+	 * Set uboot_size to 0x100000 bytes.
+	 *
+	 * This is an overly conservative value chosen to accommodate all
+	 * possible U-Boot image.  You are advised to set this value to a
+	 * smaller realistic size via scripts that modifies the .machine_param
+	 * section of output U-Boot image.
+	 */
+	.uboot_size	= 0x100000,
+
+	.boot_source	= BOOT_MODE_OM,
+	.frequency_mhz	= 800,
+	.arm_freq_mhz	= 1700,
+	.serial_base	= 0x12c30000,
+	.i2c_base	= 0x12c60000,
+	.mem_manuf	= MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+	if (machine_param.signature != SIGNATURE) {
+		/* Will hang if SIGNATURE dont match */
+		while (1)
+			;
+	}
+
+	return &machine_param;
+}
diff --git a/roms/u-boot/board/samsung/smdk5420/Kconfig b/roms/u-boot/board/samsung/smdk5420/Kconfig
new file mode 100644
index 000000000..a9d62fffa
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdk5420/Kconfig
@@ -0,0 +1,51 @@
+if TARGET_ODROID_XU3
+
+config SYS_BOARD
+	default "smdk5420"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "odroid_xu3"
+
+endif
+
+if TARGET_PEACH_PI
+
+config SYS_BOARD
+	default "smdk5420"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "peach-pi"
+
+endif
+
+if TARGET_PEACH_PIT
+
+config SYS_BOARD
+	default "smdk5420"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "peach-pit"
+
+endif
+
+if TARGET_SMDK5420
+
+config SYS_BOARD
+	default "smdk5420"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "smdk5420"
+
+endif
diff --git a/roms/u-boot/board/samsung/smdk5420/MAINTAINERS b/roms/u-boot/board/samsung/smdk5420/MAINTAINERS
new file mode 100644
index 000000000..217ff71e3
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdk5420/MAINTAINERS
@@ -0,0 +1,18 @@
+SMDK5420 BOARD
+M:	Jaehoon Chung <jh80.chung@samsung.com>
+S:	Maintained
+F:	board/samsung/smdk5420/
+F:	include/configs/peach-pit.h
+F:	configs/peach-pit_defconfig
+F:	include/configs/smdk5420.h
+F:	configs/smdk5420_defconfig
+F:	include/configs/peach-pi.h
+F:	configs/peach-pi_defconfig
+
+ODROID-XU3 BOARD
+M:	Jaehoon Chung <jh80.chung@samsung.com>
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/samsung/smdk5420/
+F:	include/configs/odroid_xu3.h
+F:	configs/odroid-xu3_defconfig
diff --git a/roms/u-boot/board/samsung/smdk5420/Makefile b/roms/u-boot/board/samsung/smdk5420/Makefile
new file mode 100644
index 000000000..f23663409
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdk5420/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2013 Samsung Electronics
+
+obj-y	+= smdk5420_spl.o
diff --git a/roms/u-boot/board/samsung/smdk5420/smdk5420_spl.c b/roms/u-boot/board/samsung/smdk5420/smdk5420_spl.c
new file mode 100644
index 000000000..84126f560
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdk5420/smdk5420_spl.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 The Chromium OS Authors.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/clk.h>
+
+#define SIGNATURE	0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+		__section(".machine_param") = {
+	.signature	= SIGNATURE,
+	.version	= 1,
+	.params		= "vmubfasirM",
+	.size		= sizeof(machine_param),
+
+	.mem_iv_size	= 0x1f,
+	.mem_type	= DDR_MODE_DDR3,
+
+	/*
+	 * Set uboot_size to 0x100000 bytes.
+	 *
+	 * This is an overly conservative value chosen to accommodate all
+	 * possible U-Boot image.  You are advised to set this value to a
+	 * smaller realistic size via scripts that modifies the .machine_param
+	 * section of output U-Boot image.
+	 */
+	.uboot_size	= 0x100000,
+
+	.boot_source	= BOOT_MODE_OM,
+	.frequency_mhz	= 800,
+	.arm_freq_mhz	= 900,
+	.serial_base	= 0x12c30000,
+	.i2c_base	= 0x12c60000,
+	.mem_manuf	= MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+	if (machine_param.signature != SIGNATURE) {
+		/* Will hang if SIGNATURE dont match */
+		while (1)
+			;
+	}
+
+	return &machine_param;
+}
diff --git a/roms/u-boot/board/samsung/smdkc100/Kconfig b/roms/u-boot/board/samsung/smdkc100/Kconfig
new file mode 100644
index 000000000..d2157b4d0
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdkc100/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SMDKC100
+
+config SYS_BOARD
+	default "smdkc100"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_SOC
+	default "s5pc1xx"
+
+config SYS_CONFIG_NAME
+	default "smdkc100"
+
+endif
diff --git a/roms/u-boot/board/samsung/smdkc100/MAINTAINERS b/roms/u-boot/board/samsung/smdkc100/MAINTAINERS
new file mode 100644
index 000000000..39949e4dc
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdkc100/MAINTAINERS
@@ -0,0 +1,6 @@
+SMDKC100 BOARD
+M:	Minkyu Kang <mk7.kang@samsung.com>
+S:	Maintained
+F:	board/samsung/smdkc100/
+F:	include/configs/smdkc100.h
+F:	configs/smdkc100_defconfig
diff --git a/roms/u-boot/board/samsung/smdkc100/Makefile b/roms/u-boot/board/samsung/smdkc100/Makefile
new file mode 100644
index 000000000..00535ee54
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdkc100/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+
+obj-y	:= smdkc100.o
+obj-$(CONFIG_SAMSUNG_ONENAND)	+= onenand.o
+obj-y	+= lowlevel_init.o
diff --git a/roms/u-boot/board/samsung/smdkc100/lowlevel_init.S b/roms/u-boot/board/samsung/smdkc100/lowlevel_init.S
new file mode 100644
index 000000000..3fbe66e07
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdkc100/lowlevel_init.S
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ */
+
+	.globl lowlevel_init
+lowlevel_init:
+	mov	r9, lr
+
+	/* r5 has always zero */
+	mov	r5, #0
+
+	ldr	r8, =S5PC100_GPIO_BASE
+
+	/* Disable Watchdog */
+	ldr	r0, =S5PC100_WATCHDOG_BASE		@0xEA200000
+	orr	r0, r0, #0x0
+	str	r5, [r0]
+
+	/* setting SRAM */
+	ldr	r0, =S5PC100_SROMC_BASE
+	ldr	r1, =0x9
+	str	r1, [r0]
+
+	/* S5PC100 has 3 groups of interrupt sources */
+	ldr	r0, =S5PC100_VIC0_BASE			@0xE4000000
+	ldr	r1, =S5PC100_VIC1_BASE			@0xE4000000
+	ldr	r2, =S5PC100_VIC2_BASE			@0xE4000000
+
+	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
+	mvn	r3, #0x0
+	str	r3, [r0, #0x14]				@INTENCLEAR
+	str	r3, [r1, #0x14]				@INTENCLEAR
+	str	r3, [r2, #0x14]				@INTENCLEAR
+
+	/* Set all interrupts as IRQ */
+	str	r5, [r0, #0xc]				@INTSELECT
+	str	r5, [r1, #0xc]				@INTSELECT
+	str	r5, [r2, #0xc]				@INTSELECT
+
+	/* Pending Interrupt Clear */
+	str	r5, [r0, #0xf00]			@INTADDRESS
+	str	r5, [r1, #0xf00]			@INTADDRESS
+	str	r5, [r2, #0xf00]			@INTADDRESS
+
+	/* for UART */
+	bl uart_asm_init
+
+	/* for TZPC */
+	bl tzpc_asm_init
+
+1:
+	mov	lr, r9
+	mov	pc, lr
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	ldr	r8, =S5PC100_CLOCK_BASE		@ 0xE0100000
+
+	/* Set Clock divider */
+	ldr	r1, =0x00011110
+	str	r1, [r8, #0x304]
+	ldr	r1, =0x1
+	str	r1, [r8, #0x308]
+	ldr	r1, =0x00011301
+	str	r1, [r8, #0x300]
+
+	/* Set Lock Time */
+	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
+	str	r1, [r8, #0x000]		@ APLL_LOCK
+	str	r1, [r8, #0x004]		@ MPLL_LOCK
+	str	r1, [r8, #0x008]		@ EPLL_LOCK
+	str	r1, [r8, #0x00C]		@ HPLL_LOCK
+
+	/* APLL_CON */
+	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
+	str	r1, [r8, #0x100]
+	/* MPLL_CON */
+	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
+	str	r1, [r8, #0x104]
+	/* EPLL_CON */
+	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
+	str	r1, [r8, #0x108]
+	/* HPLL_CON */
+	ldr	r1, =0x80600603
+	str	r1, [r8, #0x10C]
+
+	/* Set Source Clock */
+	ldr	r1, =0x1111			@ A, M, E, HPLL Muxing
+	str	r1, [r8, #0x200]		@ CLK_SRC0
+
+	ldr	r1, =0x1000001			@ Uart Clock & CLK48M Muxing
+	str	r1, [r8, #0x204]		@ CLK_SRC1
+
+	ldr	r1, =0x9000			@ ARMCLK/4
+	str	r1, [r8, #0x400]		@ CLK_OUT
+
+	/* wait at least 200us to stablize all clock */
+	mov	r2, #0x10000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	mov	pc, lr
+
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+	mov	r0, r8
+	ldr	r1, =0x22222222
+	str	r1, [r0, #0x0]			@ GPA0_CON
+	ldr	r1, =0x00022222
+	str	r1, [r0, #0x20]			@ GPA1_CON
+
+	mov	pc, lr
+
+/*
+ * tzpc_asm_init: Initialize TZPC
+ */
+tzpc_asm_init:
+	ldr	r0, =0xE3800000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x804]
+	str	r1, [r0, #0x810]
+
+	ldr	r0, =0xE2800000
+	str	r1, [r0, #0x804]
+	str	r1, [r0, #0x810]
+	str	r1, [r0, #0x81C]
+
+	ldr	r0, =0xE2900000
+	str	r1, [r0, #0x804]
+	str	r1, [r0, #0x810]
+
+	mov	pc, lr
diff --git a/roms/u-boot/board/samsung/smdkc100/onenand.c b/roms/u-boot/board/samsung/smdkc100/onenand.c
new file mode 100644
index 000000000..04dc04a1a
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdkc100/onenand.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ */
+
+#include <common.h>
+#include <linux/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+
+#include <onenand_uboot.h>
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+int onenand_board_init(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct s5pc100_clock *clk =
+			(struct s5pc100_clock *)samsung_get_base_clock();
+	struct samsung_onenand *onenand;
+	int value;
+
+	this->base = (void *)S5PC100_ONENAND_BASE;
+	onenand = (struct samsung_onenand *)this->base;
+
+	/* D0 Domain memory clock gating */
+	value = readl(&clk->gate_d01);
+	value &= ~(1 << 2);		/* CLK_ONENANDC */
+	value |= (1 << 2);
+	writel(value, &clk->gate_d01);
+
+	value = readl(&clk->src0);
+	value &= ~(1 << 24);		/* MUX_1nand: 0 from HCLKD0 */
+	value &= ~(1 << 20);		/* MUX_HREF: 0 from FIN_27M */
+	writel(value, &clk->src0);
+
+	value = readl(&clk->div1);
+	value &= ~(3 << 16);		/* PCLKD1_RATIO */
+	value |= (1 << 16);
+	writel(value, &clk->div1);
+
+	writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
+
+	while (!(readl(&onenand->int_err_stat) & RST_CMP))
+		continue;
+
+	writel(RST_CMP, &onenand->int_err_ack);
+
+	/*
+	 * Access_Clock [2:0]
+	 * 166 MHz, 134 Mhz : 3
+	 * 100 Mhz, 60 Mhz  : 2
+	 */
+	writel(0x3, &onenand->acc_clock);
+
+	writel(INT_ERR_ALL, &onenand->int_err_mask);
+	writel(1 << 0, &onenand->int_pin_en);	/* Enable */
+
+	value = readl(&onenand->int_err_mask);
+	value &= ~RDY_ACT;
+	writel(value, &onenand->int_err_mask);
+
+	s3c_onenand_init(mtd);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/samsung/smdkc100/smdkc100.c b/roms/u-boot/board/samsung/smdkc100/smdkc100.c
new file mode 100644
index 000000000..69ed71540
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdkc100/smdkc100.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2008-2009 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/sromc.h>
+#include <netdev.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+static void smc9115_pre_init(void)
+{
+	u32 smc_bw_conf, smc_bc_conf;
+
+	/* gpio configuration GPK0CON */
+	gpio_cfg_pin(S5PC100_GPIO_K00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
+
+	/* Ethernet needs bus width of 16 bits */
+	smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+	smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe)
+			| SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4)
+			| SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
+
+	/* Select and configure the SROMC bank */
+	s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+}
+
+int board_init(void)
+{
+	smc9115_pre_init();
+
+	gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("Board:\tSMDKC100\n");
+	return 0;
+}
+#endif
+
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/roms/u-boot/board/samsung/smdkv310/Kconfig b/roms/u-boot/board/samsung/smdkv310/Kconfig
new file mode 100644
index 000000000..a6fd65769
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdkv310/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SMDKV310
+
+config SYS_BOARD
+	default "smdkv310"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "smdkv310"
+
+endif
diff --git a/roms/u-boot/board/samsung/smdkv310/MAINTAINERS b/roms/u-boot/board/samsung/smdkv310/MAINTAINERS
new file mode 100644
index 000000000..4fa153155
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdkv310/MAINTAINERS
@@ -0,0 +1,6 @@
+SMDKV310 BOARD
+M:	Jaehoon Chung <jh80.chung@samsung.com>
+S:	Maintained
+F:	board/samsung/smdkv310/
+F:	include/configs/smdkv310.h
+F:	configs/smdkv310_defconfig
diff --git a/roms/u-boot/board/samsung/smdkv310/Makefile b/roms/u-boot/board/samsung/smdkv310/Makefile
new file mode 100644
index 000000000..fccd8ffd2
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdkv310/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Samsung Electronics
+
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+
+hostprogs-y := tools/mksmdkv310spl
+always := $(hostprogs-y)
+else
+obj-y	+= smdkv310.o
+endif
diff --git a/roms/u-boot/board/samsung/smdkv310/smdkv310.c b/roms/u-boot/board/samsung/smdkv310/smdkv310.c
new file mode 100644
index 000000000..8811cbb9a
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdkv310/smdkv310.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sromc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void smc9115_pre_init(void)
+{
+	u32 smc_bw_conf, smc_bc_conf;
+
+	/* gpio configuration GPK0CON */
+	gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
+
+	/* Ethernet needs bus width of 16 bits */
+	smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+	smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F)
+			| SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F)
+			| SROMC_BC_TAH(0x0F)  | SROMC_BC_TACP(0x0F)
+			| SROMC_BC_PMC(0x0F);
+
+	/* Select and configure the SROMC bank */
+	s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+}
+
+int board_init(void)
+{
+	smc9115_pre_init();
+
+	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+							PHYS_SDRAM_1_SIZE);
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
+							PHYS_SDRAM_2_SIZE);
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
+							PHYS_SDRAM_3_SIZE);
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
+							PHYS_SDRAM_4_SIZE);
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("\nBoard: SMDKV310\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MMC
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, err;
+
+	/*
+	 * MMC2 SD card GPIO:
+	 *
+	 * GPK2[0]	SD_2_CLK(2)
+	 * GPK2[1]	SD_2_CMD(2)
+	 * GPK2[2]	SD_2_CDn
+	 * GPK2[3:6]	SD_2_DATA[0:3](2)
+	 */
+	for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) {
+		/* GPK2[0:6] special function 2 */
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+
+		/* GPK2[0:6] drv 4x */
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
+
+		/* GPK2[0:1] pull disable */
+		if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) {
+			gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+			continue;
+		}
+
+		/* GPK2[2:6] pull up */
+		gpio_set_pull(i, S5P_GPIO_PULL_UP);
+	}
+	err = s5p_mmc_init(2, 4);
+	return err;
+}
+#endif
+
+static int board_uart_init(void)
+{
+	int err;
+
+	err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART0 not configured\n");
+		return err;
+	}
+
+	err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART1 not configured\n");
+		return err;
+	}
+
+	err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART2 not configured\n");
+		return err;
+	}
+
+	err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("UART3 not configured\n");
+		return err;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	int err;
+	err = board_uart_init();
+	if (err) {
+		debug("UART init failed\n");
+		return err;
+	}
+	return err;
+}
+#endif
diff --git a/roms/u-boot/board/samsung/smdkv310/tools/mksmdkv310spl.c b/roms/u-boot/board/samsung/smdkv310/tools/mksmdkv310spl.c
new file mode 100644
index 000000000..378b85d72
--- /dev/null
+++ b/roms/u-boot/board/samsung/smdkv310/tools/mksmdkv310spl.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <string.h>
+#include <sys/stat.h>
+
+#define CHECKSUM_OFFSET		(14*1024-4)
+#define BUFSIZE			(16*1024)
+#define FILE_PERM		(S_IRUSR | S_IWUSR | S_IRGRP \
+				| S_IWGRP | S_IROTH | S_IWOTH)
+/*
+* Requirement:
+* IROM code reads first 14K bytes from boot device.
+* It then calculates the checksum of 14K-4 bytes and compare with data at
+* 14K-4 offset.
+*
+* This function takes two filenames:
+* IN  "u-boot-spl.bin" and
+* OUT "u-boot-mmc-spl.bin" as filenames.
+* It reads the "u-boot-spl.bin" in 16K buffer.
+* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer.
+* It writes the buffer to "u-boot-mmc-spl.bin" file.
+*/
+
+int main(int argc, char **argv)
+{
+	int i, len;
+	unsigned char buffer[BUFSIZE] = {0};
+	int ifd, ofd;
+	unsigned int checksum = 0, count;
+
+	if (argc != 3) {
+		printf(" %d Wrong number of arguments\n", argc);
+		exit(EXIT_FAILURE);
+	}
+
+	ifd = open(argv[1], O_RDONLY);
+	if (ifd < 0) {
+		fprintf(stderr, "%s: Can't open %s: %s\n",
+			argv[0], argv[1], strerror(errno));
+		exit(EXIT_FAILURE);
+	}
+
+	ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
+	if (ofd < 0) {
+		fprintf(stderr, "%s: Can't open %s: %s\n",
+			argv[0], argv[2], strerror(errno));
+		if (ifd)
+			close(ifd);
+		exit(EXIT_FAILURE);
+	}
+
+	len = lseek(ifd, 0, SEEK_END);
+	lseek(ifd, 0, SEEK_SET);
+
+	count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET;
+
+	if (read(ifd, buffer, count) != count) {
+		fprintf(stderr, "%s: Can't read %s: %s\n",
+			argv[0], argv[1], strerror(errno));
+
+		if (ifd)
+			close(ifd);
+		if (ofd)
+			close(ofd);
+
+		exit(EXIT_FAILURE);
+	}
+
+	for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++)
+		checksum += buffer[i];
+
+	memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum));
+
+	if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {
+		fprintf(stderr, "%s: Can't write %s: %s\n",
+			argv[0], argv[2], strerror(errno));
+
+		if (ifd)
+			close(ifd);
+		if (ofd)
+			close(ofd);
+
+		exit(EXIT_FAILURE);
+	}
+
+	if (ifd)
+		close(ifd);
+	if (ofd)
+		close(ofd);
+
+	return EXIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/samsung/trats/Kconfig b/roms/u-boot/board/samsung/trats/Kconfig
new file mode 100644
index 000000000..7e8377bb9
--- /dev/null
+++ b/roms/u-boot/board/samsung/trats/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TRATS
+
+config SYS_BOARD
+	default "trats"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "trats"
+
+endif
diff --git a/roms/u-boot/board/samsung/trats/MAINTAINERS b/roms/u-boot/board/samsung/trats/MAINTAINERS
new file mode 100644
index 000000000..060bcdb64
--- /dev/null
+++ b/roms/u-boot/board/samsung/trats/MAINTAINERS
@@ -0,0 +1,6 @@
+TRATS BOARD
+M:	Jaehoon Chung <jh80.chung@samsung.com>
+S:	Maintained
+F:	board/samsung/trats/
+F:	include/configs/trats.h
+F:	configs/trats_defconfig
diff --git a/roms/u-boot/board/samsung/trats/Makefile b/roms/u-boot/board/samsung/trats/Makefile
new file mode 100644
index 000000000..cb9ee5b59
--- /dev/null
+++ b/roms/u-boot/board/samsung/trats/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Samsung Electronics
+# Heungjun Kim <riverful.kim@samsung.com>
+
+obj-y	+= trats.o
diff --git a/roms/u-boot/board/samsung/trats/setup.h b/roms/u-boot/board/samsung/trats/setup.h
new file mode 100644
index 000000000..739bdf95f
--- /dev/null
+++ b/roms/u-boot/board/samsung/trats/setup.h
@@ -0,0 +1,619 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Machine Specific Values for TRATS board based on EXYNOS4210
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ */
+
+#ifndef _TRATS_SETUP_H
+#define _TRATS_SETUP_H
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+
+/* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */
+#define MUX_HPM_SEL_MOUTAPLL		0x0
+#define MUX_HPM_SEL_SCLKMPLL		0x1
+#define MUX_CORE_SEL_MOUTAPLL		0x0
+#define MUX_CORE_SEL_SCLKMPLL		0x1
+#define MUX_MPLL_SEL_FILPLL		0x0
+#define MUX_MPLL_SEL_MOUTMPLLFOUT	0x1
+#define MUX_APLL_SEL_FILPLL		0x0
+#define MUX_APLL_SEL_MOUTMPLLFOUT	0x1
+#define CLK_SRC_CPU_VAL			((MUX_HPM_SEL_MOUTAPLL << 20) \
+					| (MUX_CORE_SEL_MOUTAPLL << 16) \
+					| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
+					| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
+
+/* CLK_DIV_CPU0 */
+#define APLL_RATIO			0x0
+#define PCLK_DBG_RATIO			0x1
+#define ATB_RATIO			0x3
+#define PERIPH_RATIO			0x3
+#define COREM1_RATIO			0x7
+#define COREM0_RATIO			0x3
+#define CORE_RATIO			0x0
+#define CLK_DIV_CPU0_VAL		((APLL_RATIO << 24) \
+					| (PCLK_DBG_RATIO << 20) \
+					| (ATB_RATIO << 16) \
+					| (PERIPH_RATIO << 12) \
+					| (COREM1_RATIO << 8) \
+					| (COREM0_RATIO << 4) \
+					| (CORE_RATIO << 0))
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO			0x0
+#define COPY_RATIO			0x3
+#define CLK_DIV_CPU1_VAL		((HPM_RATIO << 4) | (COPY_RATIO))
+
+/* CLK_DIV_DMC0 */
+#define CORE_TIMERS_RATIO		0x1
+#define COPY2_RATIO			0x3
+#define DMCP_RATIO			0x1
+#define DMCD_RATIO			0x1
+#define DMC_RATIO			0x1
+#define DPHY_RATIO			0x1
+#define ACP_PCLK_RATIO			0x1
+#define ACP_RATIO			0x3
+#define CLK_DIV_DMC0_VAL		((CORE_TIMERS_RATIO << 28) \
+					| (COPY2_RATIO << 24) \
+					| (DMCP_RATIO << 20) \
+					| (DMCD_RATIO << 16) \
+					| (DMC_RATIO << 12) \
+					| (DPHY_RATIO << 8) \
+					| (ACP_PCLK_RATIO << 4)	\
+					| (ACP_RATIO << 0))
+
+/* CLK_DIV_DMC1 */
+#define DPM_RATIO			0x1
+#define DVSEM_RATIO			0x1
+#define PWI_RATIO			0x1
+#define CLK_DIV_DMC1_VAL		((DPM_RATIO << 24) \
+					| (DVSEM_RATIO << 16) \
+					| (PWI_RATIO << 8))
+
+/* CLK_SRC_TOP0 */
+#define MUX_ONENAND_SEL_ACLK_133	0x0
+#define MUX_ONENAND_SEL_ACLK_160	0x1
+#define MUX_ACLK_133_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_133_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_160_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_160_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_100_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_100_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_200_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_200_SEL_SCLKAPLL	0x1
+#define MUX_VPLL_SEL_FINPLL		0x0
+#define MUX_VPLL_SEL_FOUTVPLL		0x1
+#define MUX_EPLL_SEL_FINPLL		0x0
+#define MUX_EPLL_SEL_FOUTEPLL		0x1
+#define MUX_ONENAND_1_SEL_MOUTONENAND	0x0
+#define MUX_ONENAND_1_SEL_SCLKVPLL	0x1
+#define CLK_SRC_TOP0_VAL		((MUX_ONENAND_SEL_ACLK_160 << 28) \
+					| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
+					| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
+					| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
+					| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
+					| (MUX_VPLL_SEL_FOUTVPLL << 8) \
+					| (MUX_EPLL_SEL_FOUTEPLL << 4) \
+					| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
+
+/* CLK_DIV_TOP */
+#define ONENAND_RATIO			0x0
+#define ACLK_133_RATIO			0x5
+#define ACLK_160_RATIO			0x4
+#define ACLK_100_RATIO			0x7
+#define ACLK_200_RATIO			0x3
+#define CLK_DIV_TOP_VAL			((ONENAND_RATIO << 16)	\
+					| (ACLK_133_RATIO << 12)\
+					| (ACLK_160_RATIO << 8)	\
+					| (ACLK_100_RATIO << 4)	\
+					| (ACLK_200_RATIO << 0))
+
+/* CLK_DIV_LEFTBUS */
+#define GPL_RATIO			0x1
+#define GDL_RATIO			0x3
+#define CLK_DIV_LEFTBUS_VAL		((GPL_RATIO << 4) | (GDL_RATIO))
+
+/* CLK_DIV_RIGHTBUS */
+#define GPR_RATIO			0x1
+#define GDR_RATIO			0x3
+#define CLK_DIV_RIGHTBUS_VAL		((GPR_RATIO << 4) | (GDR_RATIO))
+
+/* CLK_SRS_FSYS: 6 = SCLKMPLL */
+#define SATA_SEL_SCLKMPLL		0
+#define SATA_SEL_SCLKAPLL		1
+
+#define MMC_SEL_XXTI			0
+#define MMC_SEL_XUSBXTI			1
+#define MMC_SEL_SCLK_HDMI24M		2
+#define MMC_SEL_SCLK_USBPHY0		3
+#define MMC_SEL_SCLK_USBPHY1		4
+#define MMC_SEL_SCLK_HDMIPHY		5
+#define MMC_SEL_SCLKMPLL		6
+#define MMC_SEL_SCLKEPLL		7
+#define MMC_SEL_SCLKVPLL		8
+
+#define MMCC0_SEL			MMC_SEL_SCLKMPLL
+#define MMCC1_SEL			MMC_SEL_SCLKMPLL
+#define MMCC2_SEL			MMC_SEL_SCLKMPLL
+#define MMCC3_SEL			MMC_SEL_SCLKMPLL
+#define MMCC4_SEL			MMC_SEL_SCLKMPLL
+#define CLK_SRC_FSYS_VAL		((SATA_SEL_SCLKMPLL << 24) \
+					| (MMCC4_SEL << 16) \
+					| (MMCC3_SEL << 12) \
+					| (MMCC2_SEL << 8) \
+					| (MMCC1_SEL << 4) \
+					| (MMCC0_SEL << 0))
+
+/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
+/* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */
+#define MMC0_RATIO			0xF
+#define MMC0_PRE_RATIO			0x0
+#define MMC1_RATIO			0xF
+#define MMC1_PRE_RATIO			0x0
+#define CLK_DIV_FSYS1_VAL		((MMC1_PRE_RATIO << 24) \
+					| (MMC1_RATIO << 16) \
+					| (MMC0_PRE_RATIO << 8) \
+					| (MMC0_RATIO << 0))
+
+/* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */
+#define MMC2_RATIO			0xF
+#define MMC2_PRE_RATIO			0x0
+#define MMC3_RATIO			0xF
+#define MMC3_PRE_RATIO			0x0
+#define CLK_DIV_FSYS2_VAL		((MMC3_PRE_RATIO << 24) \
+					| (MMC3_RATIO << 16) \
+					| (MMC2_PRE_RATIO << 8) \
+					| (MMC2_RATIO << 0))
+
+/* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */
+#define MMC4_RATIO			0xF
+#define MMC4_PRE_RATIO			0x0
+#define CLK_DIV_FSYS3_VAL		((MMC4_PRE_RATIO << 8) \
+					| (MMC4_RATIO << 0))
+
+/* CLK_SRC_PERIL0 */
+#define UART_SEL_XXTI			0
+#define UART_SEL_XUSBXTI		1
+#define UART_SEL_SCLK_HDMI24M		2
+#define UART_SEL_SCLK_USBPHY0		3
+#define UART_SEL_SCLK_USBPHY1		4
+#define UART_SEL_SCLK_HDMIPHY		5
+#define UART_SEL_SCLKMPLL		6
+#define UART_SEL_SCLKEPLL		7
+#define UART_SEL_SCLKVPLL		8
+
+#define UART0_SEL			UART_SEL_SCLKMPLL
+#define UART1_SEL			UART_SEL_SCLKMPLL
+#define UART2_SEL			UART_SEL_SCLKMPLL
+#define UART3_SEL			UART_SEL_SCLKMPLL
+#define UART4_SEL			UART_SEL_SCLKMPLL
+#define UART5_SEL			UART_SEL_SCLKMPLL
+#define CLK_SRC_PERIL0_VAL		((UART5_SEL << 16) \
+					| (UART4_SEL << 12) \
+					| (UART3_SEL << 12) \
+					| (UART2_SEL << 8) \
+					| (UART1_SEL << 4) \
+					| (UART0_SEL << 0))
+
+/* SCLK_UART[0-4] = MOUTUART[0-4] / (UART[0-4]_RATIO + 1) */
+/* CLK_DIV_PERIL0 */
+#define UART0_RATIO			7
+#define UART1_RATIO			7
+#define UART2_RATIO			7
+#define UART3_RATIO			4
+#define UART4_RATIO			7
+#define UART5_RATIO			7
+#define CLK_DIV_PERIL0_VAL		((UART5_RATIO << 16) \
+					| (UART4_RATIO << 12) \
+					| (UART3_RATIO << 12) \
+					| (UART2_RATIO << 8) \
+					| (UART1_RATIO << 4) \
+					| (UART0_RATIO << 0))
+
+/* CLK_DIV_PERIL3 */
+#define SLIMBUS_RATIO			0x0
+#define PWM_RATIO			0x8
+#define CLK_DIV_PERIL3_VAL		((SLIMBUS_RATIO << 4) \
+					| (PWM_RATIO << 0))
+
+/* Required period to generate a stable clock output */
+/* PLL_LOCK_TIME */
+#define PLL_LOCKTIME			0x1C20
+
+/* PLL Values */
+#define DISABLE				0
+#define ENABLE				1
+#define SET_PLL(mdiv, pdiv, sdiv)	((ENABLE << 31)\
+					| (mdiv << 16) \
+					| (pdiv << 8) \
+					| (sdiv << 0))
+
+/* APLL_CON0: 800MHz */
+#define APLL_MDIV			0xC8
+#define APLL_PDIV			0x6
+#define APLL_SDIV			0x1
+#define APLL_CON0_VAL			SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
+
+/* APLL_CON1 */
+#define APLL_AFC_ENB			0x1
+#define APLL_AFC			0x1C
+#define APLL_CON1_VAL			((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
+
+/* MPLL_CON0: 800MHz */
+#define MPLL_MDIV			0xC8
+#define MPLL_PDIV			0x6
+#define MPLL_SDIV			0x1
+#define MPLL_CON0_VAL			SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
+
+/* MPLL_CON1 */
+#define MPLL_AFC_ENB			0x1
+#define MPLL_AFC			0x1C
+#define MPLL_CON1_VAL			((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
+
+/* EPLL_CON0: 96MHz */
+#define EPLL_MDIV			0x30
+#define EPLL_PDIV			0x3
+#define EPLL_SDIV			0x2
+#define EPLL_CON0_VAL			SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
+
+/* EPLL_CON1 */
+#define EPLL_K				0x0
+#define EPLL_CON1_VAL			(EPLL_K >> 0)
+
+/* VPLL_CON0: 108MHz */
+#define VPLL_MDIV			0x35
+#define VPLL_PDIV			0x3
+#define VPLL_SDIV			0x2
+#define VPLL_CON0_VAL			SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
+
+/* VPLL_CON1 */
+#define VPLL_SSCG_EN			DISABLE
+#define VPLL_SEL_PF_DN_SPREAD		0x0
+#define VPLL_MRR			0x11
+#define VPLL_MFR			0x0
+#define VPLL_K				0x400
+#define VPLL_CON1_VAL			((VPLL_SSCG_EN << 31)\
+					| (VPLL_SEL_PF_DN_SPREAD << 29) \
+					| (VPLL_MRR << 24) \
+					| (VPLL_MFR << 16) \
+					| (VPLL_K << 0))
+
+/* CLOCK GATE */
+#define CLK_DIS				0x0
+#define CLK_EN				0x1
+
+#define BIT_CAM_CLK_PIXELASYNCM1	18
+#define BIT_CAM_CLK_PIXELASYNCM0	17
+#define BIT_CAM_CLK_PPMUCAMIF		16
+#define BIT_CAM_CLK_QEFIMC3		15
+#define BIT_CAM_CLK_QEFIMC2		14
+#define BIT_CAM_CLK_QEFIMC1		13
+#define BIT_CAM_CLK_QEFIMC0		12
+#define BIT_CAM_CLK_SMMUJPEG		11
+#define BIT_CAM_CLK_SMMUFIMC3		10
+#define BIT_CAM_CLK_SMMUFIMC2		9
+#define BIT_CAM_CLK_SMMUFIMC1		8
+#define BIT_CAM_CLK_SMMUFIMC0		7
+#define BIT_CAM_CLK_JPEG		6
+#define BIT_CAM_CLK_CSIS1		5
+#define BIT_CAM_CLK_CSIS0		4
+#define BIT_CAM_CLK_FIMC3		3
+#define BIT_CAM_CLK_FIMC2		2
+#define BIT_CAM_CLK_FIMC1		1
+#define BIT_CAM_CLK_FIMC0		0
+#define CLK_GATE_IP_CAM_ALL_EN		((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\
+					| (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\
+					| (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\
+					| (CLK_EN << BIT_CAM_CLK_QEFIMC3)\
+					| (CLK_EN << BIT_CAM_CLK_QEFIMC2)\
+					| (CLK_EN << BIT_CAM_CLK_QEFIMC1)\
+					| (CLK_EN << BIT_CAM_CLK_QEFIMC0)\
+					| (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\
+					| (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\
+					| (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\
+					| (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\
+					| (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\
+					| (CLK_EN << BIT_CAM_CLK_JPEG)\
+					| (CLK_EN << BIT_CAM_CLK_CSIS1)\
+					| (CLK_EN << BIT_CAM_CLK_CSIS0)\
+					| (CLK_EN << BIT_CAM_CLK_FIMC3)\
+					| (CLK_EN << BIT_CAM_CLK_FIMC2)\
+					| (CLK_EN << BIT_CAM_CLK_FIMC1)\
+					| (CLK_EN << BIT_CAM_CLK_FIMC0))
+#define CLK_GATE_IP_CAM_ALL_DIS		~CLK_GATE_IP_CAM_ALL_EN
+
+#define BIT_VP_CLK_PPMUTV		5
+#define BIT_VP_CLK_SMMUTV		4
+#define BIT_VP_CLK_HDMI			3
+#define BIT_VP_CLK_TVENC		2
+#define BIT_VP_CLK_MIXER		1
+#define BIT_VP_CLK_VP			0
+#define CLK_GATE_IP_VP_ALL_EN		((CLK_EN << BIT_VP_CLK_PPMUTV)\
+					| (CLK_EN << BIT_VP_CLK_SMMUTV)\
+					| (CLK_EN << BIT_VP_CLK_HDMI)\
+					| (CLK_EN << BIT_VP_CLK_TVENC)\
+					| (CLK_EN << BIT_VP_CLK_MIXER)\
+					| (CLK_EN << BIT_VP_CLK_VP))
+#define CLK_GATE_IP_VP_ALL_DIS		~CLK_GATE_IP_VP_ALL_EN
+
+#define BIT_MFC_CLK_PPMUMFC_R		4
+#define BIT_MFC_CLK_PPMUMFC_L		3
+#define BIT_MFC_CLK_SMMUMFC_R		2
+#define BIT_MFC_CLK_SMMUMFC_L		1
+#define BIT_MFC_CLK_MFC			0
+#define CLK_GATE_IP_MFC_ALL_EN		((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\
+					| (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\
+					| (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\
+					| (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\
+					| (CLK_EN << BIT_MFC_CLK_MFC))
+#define CLK_GATE_IP_MFC_ALL_DIS		~CLK_GATE_IP_MFC_ALL_EN
+
+#define BIT_G3D_CLK_QEG3D		2
+#define BIT_G3D_CLK_PPMUG3D		1
+#define BIT_G3D_CLK_G3D			0
+#define CLK_GATE_IP_G3D_ALL_EN		((CLK_EN << BIT_G3D_CLK_QEG3D)\
+					| (CLK_EN << BIT_G3D_CLK_PPMUG3D)\
+					| (CLK_EN << BIT_G3D_CLK_G3D))
+#define CLK_GATE_IP_G3D_ALL_DIS		~CLK_GATE_IP_G3D_ALL_EN
+
+#define BIT_IMAGE_CLK_PPMUIMAGE		9
+#define BIT_IMAGE_CLK_QEMDMA		8
+#define BIT_IMAGE_CLK_QEROTATOR		7
+#define BIT_IMAGE_CLK_QEG2D		6
+#define BIT_IMAGE_CLK_SMMUMDMA		5
+#define BIT_IMAGE_CLK_SMMUROTATOR	4
+#define BIT_IMAGE_CLK_SMMUG2D		3
+#define BIT_IMAGE_CLK_MDMA		2
+#define BIT_IMAGE_CLK_ROTATOR		1
+#define BIT_IMAGE_CLK_G2D		0
+#define CLK_GATE_IP_IMAGE_ALL_EN	((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\
+					| (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\
+					| (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\
+					| (CLK_EN << BIT_IMAGE_CLK_QEG2D)\
+					| (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\
+					| (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\
+					| (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\
+					| (CLK_EN << BIT_IMAGE_CLK_MDMA)\
+					| (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\
+					| (CLK_EN << BIT_IMAGE_CLK_G2D))
+#define CLK_GATE_IP_IMAGE_ALL_DIS	~CLK_GATE_IP_IMAGE_ALL_EN
+
+#define BIT_LCD0_CLK_PPMULCD0		5
+#define BIT_LCD0_CLK_SMMUFIMD0		4
+#define BIT_LCD0_CLK_DSIM0		3
+#define BIT_LCD0_CLK_MDNIE0		2
+#define BIT_LCD0_CLK_MIE0		1
+#define BIT_LCD0_CLK_FIMD0		0
+#define CLK_GATE_IP_LCD0_ALL_EN		((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\
+					| (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\
+					| (CLK_EN << BIT_LCD0_CLK_DSIM0)\
+					| (CLK_EN << BIT_LCD0_CLK_MDNIE0)\
+					| (CLK_EN << BIT_LCD0_CLK_MIE0)\
+					| (CLK_EN << BIT_LCD0_CLK_FIMD0))
+#define CLK_GATE_IP_LCD0_ALL_DIS	~CLK_GATE_IP_LCD0_ALL_EN
+
+#define BIT_LCD1_CLK_PPMULCD1		5
+#define BIT_LCD1_CLK_SMMUFIMD1		4
+#define BIT_LCD1_CLK_DSIM1		3
+#define BIT_LCD1_CLK_MDNIE1		2
+#define BIT_LCD1_CLK_MIE1		1
+#define BIT_LCD1_CLK_FIMD1		0
+#define CLK_GATE_IP_LCD1_ALL_EN		((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\
+					| (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\
+					| (CLK_EN << BIT_LCD1_CLK_DSIM1)\
+					| (CLK_EN << BIT_LCD1_CLK_MDNIE1)\
+					| (CLK_EN << BIT_LCD1_CLK_MIE1)\
+					| (CLK_EN << BIT_LCD1_CLK_FIMD1))
+#define CLK_GATE_IP_LCD1_ALL_DIS	~CLK_GATE_IP_LCD1_ALL_EN
+
+#define BIT_FSYS_CLK_SMMUPCIE		18
+#define BIT_FSYS_CLK_PPMUFILE		17
+#define BIT_FSYS_CLK_NFCON		16
+#define BIT_FSYS_CLK_ONENAND		15
+#define BIT_FSYS_CLK_PCIE		14
+#define BIT_FSYS_CLK_USBDEVICE		13
+#define BIT_FSYS_CLK_USBHOST		12
+#define BIT_FSYS_CLK_SROMC		11
+#define BIT_FSYS_CLK_SATA		10
+#define BIT_FSYS_CLK_SDMMC4		9
+#define BIT_FSYS_CLK_SDMMC3		8
+#define BIT_FSYS_CLK_SDMMC2		7
+#define BIT_FSYS_CLK_SDMMC1		6
+#define BIT_FSYS_CLK_SDMMC0		5
+#define BIT_FSYS_CLK_TSI		4
+#define BIT_FSYS_CLK_SATAPHY		3
+#define BIT_FSYS_CLK_PCIEPHY		2
+#define BIT_FSYS_CLK_PDMA1		1
+#define BIT_FSYS_CLK_PDMA0		0
+#define CLK_GATE_IP_FSYS_ALL_EN		((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\
+					| (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
+					| (CLK_EN << BIT_FSYS_CLK_NFCON)\
+					| (CLK_EN << BIT_FSYS_CLK_ONENAND)\
+					| (CLK_EN << BIT_FSYS_CLK_PCIE)\
+					| (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
+					| (CLK_EN << BIT_FSYS_CLK_USBHOST)\
+					| (CLK_EN << BIT_FSYS_CLK_SROMC)\
+					| (CLK_EN << BIT_FSYS_CLK_SATA)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC4)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC3)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC1)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
+					| (CLK_EN << BIT_FSYS_CLK_TSI)\
+					| (CLK_EN << BIT_FSYS_CLK_SATAPHY)\
+					| (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\
+					| (CLK_EN << BIT_FSYS_CLK_PDMA1)\
+					| (CLK_EN << BIT_FSYS_CLK_PDMA0))
+#define CLK_GATE_IP_FSYS_ALL_DIS	~CLK_GATE_IP_FSYS_ALL_EN
+
+#define BIT_GPS_CLK_SMMUGPS		1
+#define BIT_GPS_CLK_GPS			0
+#define CLK_GATE_IP_GPS_ALL_EN		((CLK_EN << BIT_GPS_CLK_SMMUGPS)\
+					| (CLK_EN << BIT_GPS_CLK_GPS))
+#define CLK_GATE_IP_GPS_ALL_DIS		~CLK_GATE_IP_GPS_ALL_EN
+
+#define BIT_PERIL_CLK_MODEMIF		28
+#define BIT_PERIL_CLK_AC97		27
+#define BIT_PERIL_CLK_SPDIF		26
+#define BIT_PERIL_CLK_SLIMBUS		25
+#define BIT_PERIL_CLK_PWM		24
+#define BIT_PERIL_CLK_PCM2		23
+#define BIT_PERIL_CLK_PCM1		22
+#define BIT_PERIL_CLK_I2S2		21
+#define BIT_PERIL_CLK_I2S1		20
+#define BIT_PERIL_CLK_RESERVED0		19
+#define BIT_PERIL_CLK_SPI2		18
+#define BIT_PERIL_CLK_SPI1		17
+#define BIT_PERIL_CLK_SPI0		16
+#define BIT_PERIL_CLK_TSADC		15
+#define BIT_PERIL_CLK_I2CHDMI		14
+#define BIT_PERIL_CLK_I2C7		13
+#define BIT_PERIL_CLK_I2C6		12
+#define BIT_PERIL_CLK_I2C5		11
+#define BIT_PERIL_CLK_I2C4		10
+#define BIT_PERIL_CLK_I2C3		9
+#define BIT_PERIL_CLK_I2C2		8
+#define BIT_PERIL_CLK_I2C1		7
+#define BIT_PERIL_CLK_I2C0		6
+#define BIT_PERIL_CLK_RESERVED1		5
+#define BIT_PERIL_CLK_UART4		4
+#define BIT_PERIL_CLK_UART3		3
+#define BIT_PERIL_CLK_UART2		2
+#define BIT_PERIL_CLK_UART1		1
+#define BIT_PERIL_CLK_UART0		0
+#define CLK_GATE_IP_PERIL_ALL_EN	((CLK_EN << BIT_PERIL_CLK_MODEMIF)\
+					| (CLK_EN << BIT_PERIL_CLK_AC97)\
+					| (CLK_EN << BIT_PERIL_CLK_SPDIF)\
+					| (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\
+					| (CLK_EN << BIT_PERIL_CLK_PWM)\
+					| (CLK_EN << BIT_PERIL_CLK_PCM2)\
+					| (CLK_EN << BIT_PERIL_CLK_PCM1)\
+					| (CLK_EN << BIT_PERIL_CLK_I2S2)\
+					| (CLK_EN << BIT_PERIL_CLK_I2S1)\
+					| (CLK_EN << BIT_PERIL_CLK_RESERVED0)\
+					| (CLK_EN << BIT_PERIL_CLK_SPI2)\
+					| (CLK_EN << BIT_PERIL_CLK_SPI1)\
+					| (CLK_EN << BIT_PERIL_CLK_SPI0)\
+					| (CLK_EN << BIT_PERIL_CLK_TSADC)\
+					| (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C7)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C6)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C5)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C4)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C3)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C2)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C1)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C0)\
+					| (CLK_EN << BIT_PERIL_CLK_RESERVED1)\
+					| (CLK_EN << BIT_PERIL_CLK_UART4)\
+					| (CLK_EN << BIT_PERIL_CLK_UART3)\
+					| (CLK_EN << BIT_PERIL_CLK_UART2)\
+					| (CLK_EN << BIT_PERIL_CLK_UART1)\
+					| (CLK_EN << BIT_PERIL_CLK_UART0))
+#define CLK_GATE_IP_PERIL_ALL_DIS	~CLK_GATE_IP_PERIL_ALL_EN
+
+#define BIT_PERIR_CLK_TMU_APBIF		17
+#define BIT_PERIR_CLK_KEYIF		16
+#define BIT_PERIR_CLK_RTC		15
+#define BIT_PERIR_CLK_WDT		14
+#define BIT_PERIR_CLK_MCT		13
+#define BIT_PERIR_CLK_SECKEY		12
+#define BIT_PERIR_CLK_HDMI_CEC		11
+#define BIT_PERIR_CLK_TZPC5		10
+#define BIT_PERIR_CLK_TZPC4		9
+#define BIT_PERIR_CLK_TZPC3		8
+#define BIT_PERIR_CLK_TZPC2		7
+#define BIT_PERIR_CLK_TZPC1		6
+#define BIT_PERIR_CLK_TZPC0		5
+#define BIT_PERIR_CLK_CMU_DMCPART	4
+#define BIT_PERIR_CLK_RESERVED		3
+#define BIT_PERIR_CLK_CMU_APBIF		2
+#define BIT_PERIR_CLK_SYSREG		1
+#define BIT_PERIR_CLK_CHIP_ID		0
+#define CLK_GATE_IP_PERIR_ALL_EN	((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\
+					| (CLK_EN << BIT_PERIR_CLK_KEYIF)\
+					| (CLK_EN << BIT_PERIR_CLK_RTC)\
+					| (CLK_EN << BIT_PERIR_CLK_WDT)\
+					| (CLK_EN << BIT_PERIR_CLK_MCT)\
+					| (CLK_EN << BIT_PERIR_CLK_SECKEY)\
+					| (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\
+					| (CLK_EN << BIT_PERIR_CLK_TZPC5)\
+					| (CLK_EN << BIT_PERIR_CLK_TZPC4)\
+					| (CLK_EN << BIT_PERIR_CLK_TZPC3)\
+					| (CLK_EN << BIT_PERIR_CLK_TZPC2)\
+					| (CLK_EN << BIT_PERIR_CLK_TZPC1)\
+					| (CLK_EN << BIT_PERIR_CLK_TZPC0)\
+					| (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\
+					| (CLK_EN << BIT_PERIR_CLK_RESERVED)\
+					| (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\
+					| (CLK_EN << BIT_PERIR_CLK_SYSREG)\
+					| (CLK_EN << BIT_PERIR_CLK_CHIP_ID))
+#define CLK_GATE_IP_PERIR_ALL_DIS	~CLK_GATE_IP_PERIR_ALL_EN
+
+#define BIT_BLOCK_CLK_GPS		7
+#define BIT_BLOCK_CLK_RESERVED		6
+#define BIT_BLOCK_CLK_LCD1		5
+#define BIT_BLOCK_CLK_LCD0		4
+#define BIT_BLOCK_CLK_G3D		3
+#define BIT_BLOCK_CLK_MFC		2
+#define BIT_BLOCK_CLK_TV		1
+#define BIT_BLOCK_CLK_CAM		0
+#define CLK_GATE_BLOCK_ALL_EN		((CLK_EN << BIT_BLOCK_CLK_GPS)\
+					| (CLK_EN << BIT_BLOCK_CLK_RESERVED)\
+					| (CLK_EN << BIT_BLOCK_CLK_LCD1)\
+					| (CLK_EN << BIT_BLOCK_CLK_LCD0)\
+					| (CLK_EN << BIT_BLOCK_CLK_G3D)\
+					| (CLK_EN << BIT_BLOCK_CLK_MFC)\
+					| (CLK_EN << BIT_BLOCK_CLK_TV)\
+					| (CLK_EN << BIT_BLOCK_CLK_CAM))
+#define CLK_GATE_BLOCK_ALL_DIS		~CLK_GATE_BLOCK_ALL_EN
+
+/*
+ * GATE CAM	: All block
+ * GATE VP	: All block
+ * GATE MFC	: All block
+ * GATE G3D	: All block
+ * GATE IMAGE	: All block
+ * GATE LCD0	: All block
+ * GATE LCD1	: All block
+ * GATE FSYS	: Enable - PDMA0,1, SDMMC0,2, USBHOST, USBDEVICE, PPMUFILE
+ * GATE GPS	: All block
+ * GATE PERI Left	: All Enable, Block - SLIMBUS, SPDIF, AC97
+ * GATE PERI Right	: All Enable, Block - KEYIF
+ * GATE Block	: All block
+ */
+#define CLK_GATE_IP_CAM_VAL		CLK_GATE_IP_CAM_ALL_DIS
+#define CLK_GATE_IP_VP_VAL		CLK_GATE_IP_VP_ALL_DIS
+#define CLK_GATE_IP_MFC_VAL		CLK_GATE_IP_MFC_ALL_DIS
+#define CLK_GATE_IP_G3D_VAL		CLK_GATE_IP_G3D_ALL_DIS
+#define CLK_GATE_IP_IMAGE_VAL		CLK_GATE_IP_IMAGE_ALL_DIS
+#define CLK_GATE_IP_LCD0_VAL		CLK_GATE_IP_LCD0_ALL_DIS
+#define CLK_GATE_IP_LCD1_VAL		CLK_GATE_IP_LCD1_ALL_DIS
+#define CLK_GATE_IP_FSYS_VAL		(CLK_GATE_IP_FSYS_ALL_DIS \
+					| (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
+					| (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
+					| (CLK_EN << BIT_FSYS_CLK_USBHOST)\
+					| (CLK_EN << BIT_FSYS_CLK_SROMC)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
+					| (CLK_EN << BIT_FSYS_CLK_PDMA1)\
+					| (CLK_EN << BIT_FSYS_CLK_PDMA0))
+#define CLK_GATE_IP_GPS_VAL		CLK_GATE_IP_GPS_ALL_DIS
+#define CLK_GATE_IP_PERIL_VAL		(CLK_GATE_IP_PERIL_ALL_DIS \
+					| ~((CLK_EN << BIT_PERIL_CLK_AC97)\
+					  | (CLK_EN << BIT_PERIL_CLK_SPDIF)\
+					  | (CLK_EN << BIT_PERIL_CLK_I2C2)\
+					  | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)))
+#define CLK_GATE_IP_PERIR_VAL		(CLK_GATE_IP_PERIR_ALL_DIS \
+					| ~((CLK_EN << BIT_PERIR_CLK_KEYIF)))
+#define CLK_GATE_BLOCK_VAL		CLK_GATE_BLOCK_ALL_DIS
+
+/* PS_HOLD: Data Hight, Output En */
+#define BIT_DAT				8
+#define BIT_EN				9
+#define EXYNOS4_PS_HOLD_CON_VAL		(0x1 << BIT_DAT | 0x1 << BIT_EN)
+
+#endif
diff --git a/roms/u-boot/board/samsung/trats/trats.c b/roms/u-boot/board/samsung/trats/trats.c
new file mode 100644
index 000000000..d06687620
--- /dev/null
+++ b/roms/u-boot/board/samsung/trats/trats.c
@@ -0,0 +1,475 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Donghwa Lee <dh09.lee@samsung.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <lcd.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mipi_dsim.h>
+#include <asm/arch/watchdog.h>
+#include <asm/arch/power.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <usb/dwc2_udc.h>
+#include <power/max8997_pmic.h>
+#include <power/max8997_muic.h>
+#include <power/battery.h>
+#include <power/max17042_fg.h>
+#include <power/pmic.h>
+#include <libtizen.h>
+#include <usb.h>
+#include <usb_mass_storage.h>
+
+#include "setup.h"
+
+unsigned int board_rev;
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	return board_rev;
+}
+#endif
+
+static void check_hw_revision(void);
+struct dwc2_plat_otg_data s5pc210_otg_data;
+
+int exynos_init(void)
+{
+	check_hw_revision();
+	printf("HW Revision:\t0x%x\n", board_rev);
+
+	return 0;
+}
+
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
+static void trats_low_power_mode(void)
+{
+	struct exynos4_clock *clk =
+	    (struct exynos4_clock *)samsung_get_base_clock();
+	struct exynos4_power *pwr =
+	    (struct exynos4_power *)samsung_get_base_power();
+
+	/* Power down CORE1 */
+	/* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
+	writel(0x0, &pwr->arm_core1_configuration);
+
+	/* Change the APLL frequency */
+	/* ENABLE (1 enable) | LOCKED (1 locked)  */
+	/* [31]              | [29]               */
+	/* FSEL      | MDIV          | PDIV            | SDIV */
+	/* [27]      | [25:16]       | [13:8]          | [2:0]      */
+	writel(0xa0c80604, &clk->apll_con0);
+
+	/* Change CPU0 clock divider */
+	/* CORE2_RATIO  | APLL_RATIO   | PCLK_DBG_RATIO | ATB_RATIO  */
+	/* [30:28]      | [26:24]      | [22:20]        | [18:16]    */
+	/* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO   | CORE_RATIO */
+	/* [14:12]      | [10:8]       | [6:4]          | [2:0]      */
+	writel(0x00000100, &clk->div_cpu0);
+
+	/* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
+	while (readl(&clk->div_stat_cpu0) & 0x1111111)
+		continue;
+
+	/* Change clock divider ratio for DMC */
+	/* DMCP_RATIO                  | DMCD_RATIO  */
+	/* [22:20]                     | [18:16]     */
+	/* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO   | ACP_RATIO */
+	/* [14:12]   | [10:8]     | [6:4]            | [2:0]     */
+	writel(0x13113117, &clk->div_dmc0);
+
+	/* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
+	while (readl(&clk->div_stat_dmc0) & 0x11111111)
+		continue;
+
+	/* Turn off unnecessary power domains */
+	writel(0x0, &pwr->xxti_configuration);	/* XXTI */
+	writel(0x0, &pwr->cam_configuration);	/* CAM */
+	writel(0x0, &pwr->tv_configuration);    /* TV */
+	writel(0x0, &pwr->mfc_configuration);   /* MFC */
+	writel(0x0, &pwr->g3d_configuration);   /* G3D */
+	writel(0x0, &pwr->gps_configuration);   /* GPS */
+	writel(0x0, &pwr->gps_alive_configuration);	/* GPS_ALIVE */
+
+	/* Turn off unnecessary clocks */
+	writel(0x0, &clk->gate_ip_cam);	/* CAM */
+	writel(0x0, &clk->gate_ip_tv);          /* TV */
+	writel(0x0, &clk->gate_ip_mfc);	/* MFC */
+	writel(0x0, &clk->gate_ip_g3d);	/* G3D */
+	writel(0x0, &clk->gate_ip_image);	/* IMAGE */
+	writel(0x0, &clk->gate_ip_gps);	/* GPS */
+}
+#endif
+
+int exynos_power_init(void)
+{
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
+	int chrg, ret;
+	struct power_battery *pb;
+	struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
+
+	/*
+	 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
+	 * to logical I2C adapter 0
+	 *
+	 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
+	 * to logical I2C adapter 1
+	 */
+	ret = power_fg_init(I2C_9);
+	ret |= power_muic_init(I2C_5);
+	ret |= power_bat_init(0);
+	if (ret)
+		return ret;
+
+	p_fg = pmic_get("MAX17042_FG");
+	if (!p_fg) {
+		puts("MAX17042_FG: Not found\n");
+		return -ENODEV;
+	}
+
+	p_chrg = pmic_get("MAX8997_PMIC");
+	if (!p_chrg) {
+		puts("MAX8997_PMIC: Not found\n");
+		return -ENODEV;
+	}
+
+	p_muic = pmic_get("MAX8997_MUIC");
+	if (!p_muic) {
+		puts("MAX8997_MUIC: Not found\n");
+		return -ENODEV;
+	}
+
+	p_bat = pmic_get("BAT_TRATS");
+	if (!p_bat) {
+		puts("BAT_TRATS: Not found\n");
+		return -ENODEV;
+	}
+
+	p_fg->parent =  p_bat;
+	p_chrg->parent = p_bat;
+	p_muic->parent = p_bat;
+
+	p_bat->low_power_mode = trats_low_power_mode;
+	p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
+
+	pb = p_bat->pbat;
+	chrg = p_muic->chrg->chrg_type(p_muic);
+	debug("CHARGER TYPE: %d\n", chrg);
+
+	if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
+		puts("No battery detected\n");
+		return 0;
+	}
+
+	p_fg->fg->fg_battery_check(p_fg, p_bat);
+
+	if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
+		puts("CHARGE Battery !\n");
+#endif
+
+	return 0;
+}
+
+static unsigned int get_hw_revision(void)
+{
+	int hwrev = 0;
+	char str[10];
+	int i;
+
+	/* hw_rev[3:0] == GPE1[3:0] */
+	for (i = 0; i < 4; i++) {
+		int pin = i + EXYNOS4_GPIO_E10;
+
+		sprintf(str, "hw_rev%d", i);
+		gpio_request(pin, str);
+		gpio_cfg_pin(pin, S5P_GPIO_INPUT);
+		gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
+	}
+
+	udelay(1);
+
+	for (i = 0; i < 4; i++)
+		hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
+
+	debug("hwrev 0x%x\n", hwrev);
+
+	return hwrev;
+}
+
+static void check_hw_revision(void)
+{
+	int hwrev;
+
+	hwrev = get_hw_revision();
+
+	board_rev |= hwrev;
+}
+
+
+#ifdef CONFIG_USB_GADGET
+static int s5pc210_phy_control(int on)
+{
+	struct udevice *dev;
+	int reg, ret;
+
+	ret = pmic_get("max8997-pmic", &dev);
+	if (ret)
+		return ret;
+
+	if (on) {
+		reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);
+		reg |= ENSAFEOUT1;
+		ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+		reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);
+		reg |= EN_LDO;
+		ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+		reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);
+		reg |= EN_LDO;
+		ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+	} else {
+		reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);
+		reg &= DIS_LDO;
+		ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+		reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);
+		reg &= DIS_LDO;
+		ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+		reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);
+		reg &= ~ENSAFEOUT1;
+		ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+
+	}
+
+	return 0;
+}
+
+struct dwc2_plat_otg_data s5pc210_otg_data = {
+	.phy_control	= s5pc210_phy_control,
+	.regs_phy	= EXYNOS4_USBPHY_BASE,
+	.regs_otg	= EXYNOS4_USBOTG_BASE,
+	.usb_phy_ctrl	= EXYNOS4_USBPHY_CONTROL,
+	.usb_flags	= PHY0_SLEEP,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	debug("USB_udc_probe\n");
+	return dwc2_udc_probe(&s5pc210_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
+	struct pmic *muic = pmic_get("MAX8997_MUIC");
+	if (!muic)
+		return 0;
+
+	return !!muic->chrg->chrg_type(muic);
+#else
+	return false;
+#endif
+
+}
+#endif
+
+static void pmic_reset(void)
+{
+	gpio_direction_output(EXYNOS4_GPIO_X07, 1);
+	gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
+}
+
+static void board_clock_init(void)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+
+	writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
+	writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
+	writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
+	writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
+
+	writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
+	writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
+	writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
+	writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
+	writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
+	writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
+	writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
+	writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
+	writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
+	writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
+	writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
+	writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
+
+	writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
+	writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
+	writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
+	writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
+	writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
+	writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
+	writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
+	writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
+	writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
+	writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
+	writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
+	writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
+
+	writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
+	writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
+	writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
+	writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
+	writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
+	writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
+	writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
+	writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
+	writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
+	writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
+	writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
+	writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
+}
+
+static void board_power_init(void)
+{
+	struct exynos4_power *pwr =
+		(struct exynos4_power *)samsung_get_base_power();
+
+	/* PS HOLD */
+	writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
+
+	/* Set power down */
+	writel(0, (unsigned int)&pwr->cam_configuration);
+	writel(0, (unsigned int)&pwr->tv_configuration);
+	writel(0, (unsigned int)&pwr->mfc_configuration);
+	writel(0, (unsigned int)&pwr->g3d_configuration);
+	writel(0, (unsigned int)&pwr->lcd1_configuration);
+	writel(0, (unsigned int)&pwr->gps_configuration);
+	writel(0, (unsigned int)&pwr->gps_alive_configuration);
+
+	/* It is necessary to power down core 1 */
+	/* to successfully boot CPU1 in kernel */
+	writel(0, (unsigned int)&pwr->arm_core1_configuration);
+}
+
+static void exynos_uart_init(void)
+{
+	/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
+	gpio_request(EXYNOS4_GPIO_Y47, "uart_sel");
+	gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
+	gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
+}
+
+int exynos_early_init_f(void)
+{
+	wdt_stop();
+	pmic_reset();
+	board_clock_init();
+	exynos_uart_init();
+	board_power_init();
+
+	return 0;
+}
+
+void exynos_reset_lcd(void)
+{
+	gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
+	gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
+	udelay(10000);
+	gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
+	udelay(10000);
+	gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
+}
+
+int lcd_power(void)
+{
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
+	int ret = 0;
+	struct pmic *p = pmic_get("MAX8997_PMIC");
+	if (!p)
+		return -ENODEV;
+
+	if (pmic_probe(p))
+		return 0;
+
+	/* LDO15 voltage: 2.2v */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
+	/* LDO13 voltage: 3.0v */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
+
+	if (ret) {
+		puts("MAX8997 LDO setting error!\n");
+		return -1;
+	}
+#endif
+	return 0;
+}
+
+int mipi_power(void)
+{
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
+	int ret = 0;
+	struct pmic *p = pmic_get("MAX8997_PMIC");
+	if (!p)
+		return -ENODEV;
+
+	if (pmic_probe(p))
+		return 0;
+
+	/* LDO3 voltage: 1.1v */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
+	/* LDO4 voltage: 1.8v */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
+
+	if (ret) {
+		puts("MAX8997 LDO setting error!\n");
+		return -1;
+	}
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_LCD
+void exynos_lcd_misc_init(vidinfo_t *vid)
+{
+#ifdef CONFIG_TIZEN
+	get_tizen_logo_info(vid);
+#endif
+#ifdef CONFIG_S6E8AX0
+	s6e8ax0_init();
+	env_set("lcdinfo", "lcd=s6e8ax0");
+#endif
+}
+#endif
diff --git a/roms/u-boot/board/samsung/trats2/Kconfig b/roms/u-boot/board/samsung/trats2/Kconfig
new file mode 100644
index 000000000..5670e14fa
--- /dev/null
+++ b/roms/u-boot/board/samsung/trats2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TRATS2
+
+config SYS_BOARD
+	default "trats2"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "trats2"
+
+endif
diff --git a/roms/u-boot/board/samsung/trats2/MAINTAINERS b/roms/u-boot/board/samsung/trats2/MAINTAINERS
new file mode 100644
index 000000000..ba17b4e0a
--- /dev/null
+++ b/roms/u-boot/board/samsung/trats2/MAINTAINERS
@@ -0,0 +1,6 @@
+TRATS2 BOARD
+M:	Jaehoon Chung <jh80.chung@samsung.com>
+S:	Maintained
+F:	board/samsung/trats2/
+F:	include/configs/trats2.h
+F:	configs/trats2_defconfig
diff --git a/roms/u-boot/board/samsung/trats2/Makefile b/roms/u-boot/board/samsung/trats2/Makefile
new file mode 100644
index 000000000..fd8325e4e
--- /dev/null
+++ b/roms/u-boot/board/samsung/trats2/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2000 - 2013 Samsung Electronics Co., Ltd. All rights reserved.
+# Sanghee Kim <sh0130.kim@samsung.com>
+
+obj-y	:= trats2.o
diff --git a/roms/u-boot/board/samsung/trats2/trats2.c b/roms/u-boot/board/samsung/trats2/trats2.c
new file mode 100644
index 000000000..59e6fbf4b
--- /dev/null
+++ b/roms/u-boot/board/samsung/trats2/trats2.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved.
+ * Sanghee Kim <sh0130.kim@samsung.com>
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <log.h>
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/mipi_dsim.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/max77686_pmic.h>
+#include <power/battery.h>
+#include <power/max77693_pmic.h>
+#include <power/max77693_muic.h>
+#include <power/max77693_fg.h>
+#include <libtizen.h>
+#include <errno.h>
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+#include <usb_mass_storage.h>
+
+static unsigned int board_rev = -1;
+
+static inline u32 get_model_rev(void);
+
+static void check_hw_revision(void)
+{
+	int modelrev = 0;
+	char str[12];
+	int i;
+
+	/*
+	 * GPM1[1:0]: MODEL_REV[1:0]
+	 * Don't set as pull-none for these N/C pin.
+	 * TRM say that it may cause unexcepted state and leakage current.
+	 * and pull-none is only for output function.
+	 */
+	for (i = 0; i < 2; i++) {
+		int pin = i + EXYNOS4X12_GPIO_M10;
+
+		sprintf(str, "model_rev%d", i);
+		gpio_request(pin, str);
+		gpio_cfg_pin(pin, S5P_GPIO_INPUT);
+	}
+
+	/* GPM1[5:2]: HW_REV[3:0] */
+	for (i = 0; i < 4; i++) {
+		int pin = i + EXYNOS4X12_GPIO_M12;
+
+		sprintf(str, "hw_rev%d", i);
+		gpio_request(pin, str);
+		gpio_cfg_pin(pin, S5P_GPIO_INPUT);
+		gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
+	}
+
+	/* GPM1[1:0]: MODEL_REV[1:0] */
+	for (i = 0; i < 2; i++)
+		modelrev |= (gpio_get_value(EXYNOS4X12_GPIO_M10 + i) << i);
+
+	/* board_rev[15:8] = model */
+	board_rev = modelrev << 8;
+}
+
+u32 get_board_rev(void)
+{
+	return board_rev;
+}
+
+static inline u32 get_model_rev(void)
+{
+	return (board_rev >> 8) & 0xff;
+}
+
+static void board_external_gpio_init(void)
+{
+	/*
+	 * some pins which in alive block are connected with external pull-up
+	 * but it's default setting is pull-down.
+	 * if that pin set as input then that floated
+	 */
+
+	gpio_set_pull(EXYNOS4X12_GPIO_X02, S5P_GPIO_PULL_NONE);	/* PS_ALS_INT */
+	gpio_set_pull(EXYNOS4X12_GPIO_X04, S5P_GPIO_PULL_NONE);	/* TSP_nINT */
+	gpio_set_pull(EXYNOS4X12_GPIO_X07, S5P_GPIO_PULL_NONE);	/* AP_PMIC_IRQ*/
+	gpio_set_pull(EXYNOS4X12_GPIO_X15, S5P_GPIO_PULL_NONE);	/* IF_PMIC_IRQ*/
+	gpio_set_pull(EXYNOS4X12_GPIO_X20, S5P_GPIO_PULL_NONE);	/* VOL_UP */
+	gpio_set_pull(EXYNOS4X12_GPIO_X21, S5P_GPIO_PULL_NONE);	/* VOL_DOWN */
+	gpio_set_pull(EXYNOS4X12_GPIO_X23, S5P_GPIO_PULL_NONE);	/* FUEL_ALERT */
+	gpio_set_pull(EXYNOS4X12_GPIO_X24, S5P_GPIO_PULL_NONE);	/* ADC_INT */
+	gpio_set_pull(EXYNOS4X12_GPIO_X27, S5P_GPIO_PULL_NONE);	/* nPOWER */
+	gpio_set_pull(EXYNOS4X12_GPIO_X30, S5P_GPIO_PULL_NONE);	/* WPC_INT */
+	gpio_set_pull(EXYNOS4X12_GPIO_X35, S5P_GPIO_PULL_NONE);	/* OK_KEY */
+	gpio_set_pull(EXYNOS4X12_GPIO_X37, S5P_GPIO_PULL_NONE);	/* HDMI_HPD */
+}
+
+int exynos_early_init_f(void)
+{
+	board_external_gpio_init();
+
+	return 0;
+}
+
+int exynos_init(void)
+{
+	struct exynos4_power *pwr =
+		(struct exynos4_power *)samsung_get_base_power();
+
+	check_hw_revision();
+	printf("HW Revision:\t0x%04x\n", board_rev);
+
+	/*
+	 * First bootloader on the TRATS2 platform uses
+	 * INFORM4 and INFORM5 registers for recovery
+	 *
+	 * To indicate correct boot chain - those two
+	 * registers must be cleared out
+	 */
+	writel(0, &pwr->inform4);
+	writel(0, &pwr->inform5);
+
+	return 0;
+}
+
+int exynos_power_init(void)
+{
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
+	int chrg;
+	struct power_battery *pb;
+	struct pmic *p_chrg, *p_muic, *p_fg, *p_bat;
+
+	pmic_init_max77693(I2C_10);	/* I2C adapter 10 - bus name soft1 */
+	power_muic_init(I2C_10);	/* I2C adapter 10 - bus name soft1 */
+	power_fg_init(I2C_9);		/* I2C adapter 9 - bus name soft0 */
+	power_bat_init(0);
+
+	p_chrg = pmic_get("MAX77693_PMIC");
+	if (!p_chrg) {
+		puts("MAX77693_PMIC: Not found\n");
+		return -ENODEV;
+	}
+
+	p_muic = pmic_get("MAX77693_MUIC");
+	if (!p_muic) {
+		puts("MAX77693_MUIC: Not found\n");
+		return -ENODEV;
+	}
+
+	p_fg = pmic_get("MAX77693_FG");
+	if (!p_fg) {
+		puts("MAX17042_FG: Not found\n");
+		return -ENODEV;
+	}
+
+	if (p_chrg->chrg->chrg_bat_present(p_chrg) == 0)
+		puts("No battery detected\n");
+
+	p_bat = pmic_get("BAT_TRATS2");
+	if (!p_bat) {
+		puts("BAT_TRATS2: Not found\n");
+		return -ENODEV;
+	}
+
+	p_fg->parent =  p_bat;
+	p_chrg->parent = p_bat;
+	p_muic->parent = p_bat;
+
+	p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
+
+	pb = p_bat->pbat;
+	chrg = p_muic->chrg->chrg_type(p_muic);
+	debug("CHARGER TYPE: %d\n", chrg);
+
+	if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
+		puts("No battery detected\n");
+		return 0;
+	}
+
+	p_fg->fg->fg_battery_check(p_fg, p_bat);
+
+	if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
+		puts("CHARGE Battery !\n");
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_USB_GADGET
+static int s5pc210_phy_control(int on)
+{
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
+	int ret = 0;
+	unsigned int val;
+	struct pmic *p, *p_pmic, *p_muic;
+
+	p_pmic = pmic_get("MAX77686_PMIC");
+	if (!p_pmic)
+		return -ENODEV;
+
+	if (pmic_probe(p_pmic))
+		return -1;
+
+	p_muic = pmic_get("MAX77693_MUIC");
+	if (!p_muic)
+		return -ENODEV;
+
+	if (pmic_probe(p_muic))
+		return -1;
+
+	if (on) {
+		ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON);
+		if (ret)
+			return -1;
+
+		p = pmic_get("MAX77693_PMIC");
+		if (!p)
+			return -ENODEV;
+
+		if (pmic_probe(p))
+			return -1;
+
+		/* SAFEOUT */
+		ret = pmic_reg_read(p, MAX77693_SAFEOUT, &val);
+		if (ret)
+			return -1;
+
+		val |= MAX77693_ENSAFEOUT1;
+		ret = pmic_reg_write(p, MAX77693_SAFEOUT, val);
+		if (ret)
+			return -1;
+
+		/* PATH: USB */
+		ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1,
+			MAX77693_MUIC_CTRL1_DN1DP2);
+
+	} else {
+		ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM);
+		if (ret)
+			return -1;
+
+		/* PATH: UART */
+		ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1,
+			MAX77693_MUIC_CTRL1_UT1UR2);
+	}
+
+	if (ret)
+		return -1;
+#endif
+	return 0;
+}
+
+struct dwc2_plat_otg_data s5pc210_otg_data = {
+	.phy_control	= s5pc210_phy_control,
+	.regs_phy	= EXYNOS4X12_USBPHY_BASE,
+	.regs_otg	= EXYNOS4X12_USBOTG_BASE,
+	.usb_phy_ctrl	= EXYNOS4X12_USBPHY_CONTROL,
+	.usb_flags	= PHY0_SLEEP,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	debug("USB_udc_probe\n");
+	return dwc2_udc_probe(&s5pc210_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
+	struct pmic *muic = pmic_get("MAX77693_MUIC");
+	if (!muic)
+		return 0;
+
+	return !!muic->chrg->chrg_type(muic);
+#else
+	return false;
+#endif
+}
+#endif
+
+/*
+ * LCD
+ */
+
+#ifdef CONFIG_LCD
+int mipi_power(void)
+{
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
+	struct pmic *p = pmic_get("MAX77686_PMIC");
+
+	/* LDO8 VMIPI_1.0V_AP */
+	max77686_set_ldo_mode(p, 8, OPMODE_ON);
+	/* LDO10 VMIPI_1.8V_AP */
+	max77686_set_ldo_mode(p, 10, OPMODE_ON);
+#endif
+
+	return 0;
+}
+
+void exynos_lcd_power_on(void)
+{
+#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
+	struct pmic *p = pmic_get("MAX77686_PMIC");
+
+	/* LCD_2.2V_EN: GPC0[1] */
+	gpio_request(EXYNOS4X12_GPIO_C01, "lcd_2v2_en");
+	gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP);
+	gpio_direction_output(EXYNOS4X12_GPIO_C01, 1);
+
+	/* LDO25 VCC_3.1V_LCD */
+	pmic_probe(p);
+	max77686_set_ldo_voltage(p, 25, 3100000);
+	max77686_set_ldo_mode(p, 25, OPMODE_LPM);
+#endif
+}
+
+void exynos_reset_lcd(void)
+{
+	/* reset lcd */
+	gpio_request(EXYNOS4X12_GPIO_F21, "lcd_reset");
+	gpio_direction_output(EXYNOS4X12_GPIO_F21, 0);
+	udelay(10);
+	gpio_set_value(EXYNOS4X12_GPIO_F21, 1);
+}
+
+void exynos_lcd_misc_init(vidinfo_t *vid)
+{
+#ifdef CONFIG_TIZEN
+	get_tizen_logo_info(vid);
+#endif
+#ifdef CONFIG_S6E8AX0
+	s6e8ax0_init();
+#endif
+}
+#endif /* LCD */
diff --git a/roms/u-boot/board/samsung/universal_c210/Kconfig b/roms/u-boot/board/samsung/universal_c210/Kconfig
new file mode 100644
index 000000000..e69266811
--- /dev/null
+++ b/roms/u-boot/board/samsung/universal_c210/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_S5PC210_UNIVERSAL
+
+config SYS_BOARD
+	default "universal_c210"
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "s5pc210_universal"
+
+endif
diff --git a/roms/u-boot/board/samsung/universal_c210/MAINTAINERS b/roms/u-boot/board/samsung/universal_c210/MAINTAINERS
new file mode 100644
index 000000000..00d611042
--- /dev/null
+++ b/roms/u-boot/board/samsung/universal_c210/MAINTAINERS
@@ -0,0 +1,6 @@
+UNIVERSAL_C210 BOARD
+M:	Jaehoon Chung <jh80.chung@samsung.com>
+S:	Maintained
+F:	board/samsung/universal_c210/
+F:	include/configs/s5pc210_universal.h
+F:	configs/s5pc210_universal_defconfig
diff --git a/roms/u-boot/board/samsung/universal_c210/Makefile b/roms/u-boot/board/samsung/universal_c210/Makefile
new file mode 100644
index 000000000..1c90dac0f
--- /dev/null
+++ b/roms/u-boot/board/samsung/universal_c210/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2010 Samsung Electronics
+# Minkyu Kang <mk7.kang@samsung.com>
+
+obj-y	:= universal.o onenand.o
diff --git a/roms/u-boot/board/samsung/universal_c210/onenand.c b/roms/u-boot/board/samsung/universal_c210/onenand.c
new file mode 100644
index 000000000..37e911c43
--- /dev/null
+++ b/roms/u-boot/board/samsung/universal_c210/onenand.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ */
+
+#include <common.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+
+int onenand_board_init(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+	this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
+	this->chip_probe = s5pc210_chip_probe;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/samsung/universal_c210/universal.c b/roms/u-boot/board/samsung/universal_c210/universal.c
new file mode 100644
index 000000000..9ef11b847
--- /dev/null
+++ b/roms/u-boot/board/samsung/universal_c210/universal.c
@@ -0,0 +1,405 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2010 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <log.h>
+#include <spi.h>
+#include <lcd.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/adc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/watchdog.h>
+#include <ld9040.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+#include <asm/arch/cpu.h>
+#include <power/max8998_pmic.h>
+#include <libtizen.h>
+#include <samsung/misc.h>
+#include <usb_mass_storage.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int board_rev;
+static int init_pmic_lcd(void);
+
+u32 get_board_rev(void)
+{
+	return board_rev;
+}
+
+int exynos_power_init(void)
+{
+	return init_pmic_lcd();
+}
+
+static int get_hwrev(void)
+{
+	return board_rev & 0xFF;
+}
+
+static unsigned short get_adc_value(int channel)
+{
+	struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
+	unsigned short ret = 0;
+	unsigned int reg;
+	unsigned int loop = 0;
+
+	writel(channel & 0xF, &adc->adcmux);
+	writel((1 << 14) | (49 << 6), &adc->adccon);
+	writel(1000 & 0xffff, &adc->adcdly);
+	writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
+	udelay(10);
+	writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
+	udelay(10);
+
+	do {
+		udelay(1);
+		reg = readl(&adc->adccon);
+	} while (!(reg & (1 << 15)) && (loop++ < 1000));
+
+	ret = readl(&adc->adcdat0) & 0xFFF;
+
+	return ret;
+}
+
+static int adc_power_control(int on)
+{
+	struct udevice *dev;
+	int ret;
+	u8 reg;
+
+	ret = pmic_get("max8998-pmic", &dev);
+	if (ret) {
+		puts("Failed to get MAX8998!\n");
+		return ret;
+	}
+
+	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+	if (on)
+		reg |= MAX8998_LDO4;
+	else
+		reg &= ~MAX8998_LDO4;
+
+	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+	if (ret) {
+		puts("MAX8998 LDO setting error\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static unsigned int get_hw_revision(void)
+{
+	int hwrev, mode0, mode1;
+
+	adc_power_control(1);
+
+	mode0 = get_adc_value(1);		/* HWREV_MODE0 */
+	mode1 = get_adc_value(2);		/* HWREV_MODE1 */
+
+	/*
+	 * XXX Always set the default hwrev as the latest board
+	 * ADC = (voltage) / 3.3 * 4096
+	 */
+	hwrev = 3;
+
+#define IS_RANGE(x, min, max)	((x) > (min) && (x) < (max))
+	if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200))
+		hwrev = 0x0;		/* 0.01V	0.01V */
+	if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200))
+		hwrev = 0x1;		/* 610mV	0.01V */
+	if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200))
+		hwrev = 0x2;		/* 1.16V	0.01V */
+	if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200))
+		hwrev = 0x3;		/* 1.79V	0.01V */
+#undef IS_RANGE
+
+	debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
+
+	adc_power_control(0);
+
+	return hwrev;
+}
+
+static void check_hw_revision(void)
+{
+	int hwrev;
+
+	hwrev = get_hw_revision();
+
+	board_rev |= hwrev;
+}
+
+#ifdef CONFIG_USB_GADGET
+static int s5pc210_phy_control(int on)
+{
+	struct udevice *dev;
+	int ret;
+	u8 reg;
+
+	ret = pmic_get("max8998-pmic", &dev);
+	if (ret) {
+		puts("Failed to get MAX8998!\n");
+		return ret;
+	}
+
+	if (on) {
+		reg = pmic_reg_read(dev, MAX8998_REG_BUCK_ACTIVE_DISCHARGE3);
+		reg |= MAX8998_SAFEOUT1;
+		ret |= pmic_reg_write(dev,
+			MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, reg);
+
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+		reg |= MAX8998_LDO3;
+		ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+		reg |= MAX8998_LDO8;
+		ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
+
+	} else {
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+		reg &= ~MAX8998_LDO8;
+		ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
+
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+		reg &= ~MAX8998_LDO3;
+		ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+
+		reg = pmic_reg_read(dev, MAX8998_REG_BUCK_ACTIVE_DISCHARGE3);
+		reg &= ~MAX8998_SAFEOUT1;
+		ret |= pmic_reg_write(dev,
+			MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, reg);
+	}
+
+	if (ret) {
+		puts("MAX8998 LDO setting error!\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+struct dwc2_plat_otg_data s5pc210_otg_data = {
+	.phy_control = s5pc210_phy_control,
+	.regs_phy = EXYNOS4_USBPHY_BASE,
+	.regs_otg = EXYNOS4_USBOTG_BASE,
+	.usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
+	.usb_flags = PHY0_SLEEP,
+};
+#endif
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	debug("USB_udc_probe\n");
+	return dwc2_udc_probe(&s5pc210_otg_data);
+}
+
+int exynos_early_init_f(void)
+{
+	wdt_stop();
+
+	return 0;
+}
+
+static int init_pmic_lcd(void)
+{
+	struct udevice *dev;
+	unsigned char val;
+	int ret = 0;
+
+	ret = pmic_get("max8998-pmic", &dev);
+	if (ret) {
+		puts("Failed to get MAX8998 for init_pmic_lcd()!\n");
+		return ret;
+	}
+
+	/* LDO7 1.8V */
+	val = 0x02; /* (1800 - 1600) / 100; */
+	ret |= pmic_reg_write(dev,  MAX8998_REG_LDO7, val);
+
+	/* LDO17 3.0V */
+	val = 0xe; /* (3000 - 1600) / 100; */
+	ret |= pmic_reg_write(dev,  MAX8998_REG_LDO17, val);
+
+	/* Disable unneeded regulators */
+	/*
+	 * ONOFF1
+	 * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
+	 * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
+	 */
+	val = 0xB9;
+	ret |= pmic_reg_write(dev,  MAX8998_REG_ONOFF1, val);
+
+	/* ONOFF2
+	 * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
+	 * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
+	 */
+	val = 0x50;
+	ret |= pmic_reg_write(dev,  MAX8998_REG_ONOFF2, val);
+
+	/* ONOFF3
+	 * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
+	 * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
+	 */
+	val = 0x00;
+	ret |= pmic_reg_write(dev,  MAX8998_REG_ONOFF3, val);
+
+	if (ret) {
+		puts("LCD pmic initialisation error!\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void exynos_cfg_lcd_gpio(void)
+{
+	unsigned int i, f3_end = 4;
+
+	for (i = 0; i < 8; i++) {
+		/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
+		gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2));
+		gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2));
+		gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2));
+		/* pull-up/down disable */
+		gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE);
+		gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE);
+		gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE);
+
+		/* drive strength to max (24bit) */
+		gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X);
+		gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
+		gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X);
+		gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW);
+		gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X);
+		gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
+	}
+
+	for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) {
+		/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(2));
+		/* pull-up/down disable */
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		/* drive strength to max (24bit) */
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
+		gpio_set_rate(i, S5P_GPIO_DRV_SLOW);
+	}
+
+	/* gpio pad configuration for LCD reset. */
+	gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
+	gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
+}
+
+int mipi_power(void)
+{
+	return 0;
+}
+
+void exynos_reset_lcd(void)
+{
+	gpio_set_value(EXYNOS4_GPIO_Y45, 1);
+	udelay(10000);
+	gpio_set_value(EXYNOS4_GPIO_Y45, 0);
+	udelay(10000);
+	gpio_set_value(EXYNOS4_GPIO_Y45, 1);
+	udelay(100);
+}
+
+void exynos_lcd_power_on(void)
+{
+	struct udevice *dev;
+	int ret;
+	u8 reg;
+
+	ret = pmic_get("max8998-pmic", &dev);
+	if (ret) {
+		puts("Failed to get MAX8998!\n");
+		return;
+	}
+
+	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF3);
+	reg |= MAX8998_LDO17;
+	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF3, reg);
+	if (ret) {
+		puts("MAX8998 LDO setting error\n");
+		return;
+	}
+
+	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+	reg |= MAX8998_LDO7;
+	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
+	if (ret) {
+		puts("MAX8998 LDO setting error\n");
+		return;
+	}
+}
+
+void exynos_cfg_ldo(void)
+{
+	ld9040_cfg_ldo();
+}
+
+void exynos_enable_ldo(unsigned int onoff)
+{
+	ld9040_enable_ldo(onoff);
+}
+
+int exynos_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
+
+	switch (get_hwrev()) {
+	case 0:
+		/*
+		 * Set the low to enable LDO_EN
+		 * But when you use the test board for eMMC booting
+		 * you should set it HIGH since it removes the inverter
+		 */
+		/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
+		gpio_request(EXYNOS4_GPIO_E36, "ldo_en");
+		gpio_direction_output(EXYNOS4_GPIO_E36, 0);
+		break;
+	default:
+		/*
+		 * Default reset state is High and there's no inverter
+		 * But set it as HIGH to ensure
+		 */
+		/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
+		gpio_request(EXYNOS4_GPIO_E13, "massmemory_en");
+		gpio_direction_output(EXYNOS4_GPIO_E13, 1);
+		break;
+	}
+
+	check_hw_revision();
+	printf("HW Revision:\t0x%x\n", board_rev);
+
+	return 0;
+}
+
+#ifdef CONFIG_LCD
+void exynos_lcd_misc_init(vidinfo_t *vid)
+{
+#ifdef CONFIG_TIZEN
+	get_tizen_logo_info(vid);
+#endif
+
+	/* for LD9040. */
+	vid->pclk_name = 1;	/* MPLL */
+	vid->sclk_div = 1;
+
+	env_set("lcdinfo", "lcd=ld9040");
+}
+#endif
diff --git a/roms/u-boot/board/sandbox/MAINTAINERS b/roms/u-boot/board/sandbox/MAINTAINERS
new file mode 100644
index 000000000..d32561cd1
--- /dev/null
+++ b/roms/u-boot/board/sandbox/MAINTAINERS
@@ -0,0 +1,35 @@
+SANDBOX BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/sandbox/
+F:	include/configs/sandbox.h
+F:	configs/sandbox_defconfig
+
+SANDBOX64 BOARD
+M:	Simon Glass <sjg@chromium.org>
+M:	Mario Six <mario.six@gdsys.cc>
+S:	Maintained
+F:	board/sandbox/
+F:	include/configs/sandbox.h
+F:	configs/sandbox64_defconfig
+
+SANDBOX SPL BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/sandbox/
+F:	include/configs/sandbox_spl.h
+F:	configs/sandbox_spl_defconfig
+
+SANDBOX NOINST BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/sandbox/
+F:	include/configs/sandbox_spl.h
+F:	configs/sandbox_noinst_defconfig
+
+SANDBOX FLAT TREE BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/sandbox/
+F:	include/configs/sandbox.h
+F:	configs/sandbox_flattree_defconfig
diff --git a/roms/u-boot/board/sandbox/Makefile b/roms/u-boot/board/sandbox/Makefile
new file mode 100644
index 000000000..411b53c2b
--- /dev/null
+++ b/roms/u-boot/board/sandbox/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+
+obj-y	:= sandbox.o
diff --git a/roms/u-boot/board/sandbox/sandbox.c b/roms/u-boot/board/sandbox/sandbox.c
new file mode 100644
index 000000000..dcd73451a
--- /dev/null
+++ b/roms/u-boot/board/sandbox/sandbox.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <cros_ec.h>
+#include <dm.h>
+#include <env_internal.h>
+#include <init.h>
+#include <led.h>
+#include <os.h>
+#include <asm/global_data.h>
+#include <asm/test.h>
+#include <asm/u-boot-sandbox.h>
+#include <malloc.h>
+
+#include <extension_board.h>
+
+/*
+ * Pointer to initial global data area
+ *
+ * Here we initialize it.
+ */
+gd_t *gd;
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+/* Add a simple GPIO device */
+U_BOOT_DRVINFO(gpio_sandbox) = {
+	.name = "sandbox_gpio",
+};
+#endif
+
+#ifndef CONFIG_TIMER
+/* system timer offset in ms */
+static unsigned long sandbox_timer_offset;
+
+void timer_test_add_offset(unsigned long offset)
+{
+	sandbox_timer_offset += offset;
+}
+
+unsigned long timer_read_counter(void)
+{
+	return os_get_nsec() / 1000 + sandbox_timer_offset * 1000;
+}
+#endif
+
+/* specific order for sandbox: nowhere is the first value, used by default */
+static enum env_location env_locations[] = {
+	ENVL_NOWHERE,
+	ENVL_EXT4,
+	ENVL_FAT,
+};
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	if (prio >= ARRAY_SIZE(env_locations))
+		return ENVL_UNKNOWN;
+
+	return env_locations[prio];
+}
+
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
+}
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	return 0;
+}
+
+int ft_board_setup(void *fdt, struct bd_info *bd)
+{
+	/* Create an arbitrary reservation to allow testing OF_BOARD_SETUP.*/
+	return fdt_add_mem_rsv(fdt, 0x00d02000, 0x4000);
+}
+
+#ifdef CONFIG_CMD_EXTENSION
+int extension_board_scan(struct list_head *extension_list)
+{
+	struct extension *extension;
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		extension = calloc(1, sizeof(struct extension));
+		snprintf(extension->overlay, sizeof(extension->overlay), "overlay%d.dtbo", i);
+		snprintf(extension->name, sizeof(extension->name), "extension board %d", i);
+		snprintf(extension->owner, sizeof(extension->owner), "sandbox");
+		snprintf(extension->version, sizeof(extension->version), "1.1");
+		snprintf(extension->other, sizeof(extension->other), "Fictionnal extension board");
+		list_add_tail(&extension->list, extension_list);
+	}
+
+	return i;
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_CROS_EC, &dev);
+	if (ret && ret != -ENODEV) {
+		/* Force console on */
+		gd->flags &= ~GD_FLG_SILENT;
+
+		printf("cros-ec communications failure %d\n", ret);
+		puts("\nPlease reset with Power+Refresh\n\n");
+		panic("Cannot init cros-ec device");
+		return -1;
+	}
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/sbc8349/Kconfig b/roms/u-boot/board/sbc8349/Kconfig
new file mode 100644
index 000000000..129d6b92e
--- /dev/null
+++ b/roms/u-boot/board/sbc8349/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SBC8349
+
+config SYS_BOARD
+	default "sbc8349"
+
+config SYS_CONFIG_NAME
+	default "sbc8349"
+
+endif
diff --git a/roms/u-boot/board/sbc8349/MAINTAINERS b/roms/u-boot/board/sbc8349/MAINTAINERS
new file mode 100644
index 000000000..af95c1dd0
--- /dev/null
+++ b/roms/u-boot/board/sbc8349/MAINTAINERS
@@ -0,0 +1,8 @@
+SBC8349 BOARD
+M:	Paul Gortmaker <paul.gortmaker@windriver.com>
+S:	Maintained
+F:	board/sbc8349/
+F:	include/configs/sbc8349.h
+F:	configs/sbc8349_defconfig
+F:	configs/sbc8349_PCI_33_defconfig
+F:	configs/sbc8349_PCI_66_defconfig
diff --git a/roms/u-boot/board/sbc8349/Makefile b/roms/u-boot/board/sbc8349/Makefile
new file mode 100644
index 000000000..c46917408
--- /dev/null
+++ b/roms/u-boot/board/sbc8349/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2006 Wind River Systems, Inc.
+
+obj-y += sbc8349.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/roms/u-boot/board/sbc8349/README b/roms/u-boot/board/sbc8349/README
new file mode 100644
index 000000000..3c142e040
--- /dev/null
+++ b/roms/u-boot/board/sbc8349/README
@@ -0,0 +1,127 @@
+
+
+	U-Boot for Wind River SBC834x Boards
+	====================================
+
+
+The Wind River SBC834x board is a 6U form factor (not CPCI) reference
+design that uses the MPC8347E or MPC8349E processor.  U-Boot support
+for this board is heavily based on the existing U-Boot support for
+Freescale MPC8349 reference boards.
+
+Support has been primarily tested on the SBC8349 version of the board,
+although earlier versions were also tested on the SBC8347.  The primary
+difference in the two is the level of PCI functionality.
+
+	http://www.windriver.com/products/OCD/SBC8347E_49E/
+
+
+Flash Details:
+==============
+
+The flash type is intel 28F640Jx (4096x16) [one device].  Base address
+is 0xFF80_0000 which is also where the Hardware Reset Configuration
+Word (HRCW) is stored.  Caution should be used to not reset the
+board without having a valid HRCW in place (i.e. erased flash) as
+then a Wind River ICE will be required to restore the HRCW and flash
+image.
+
+
+Restoring a corrupted or missing flash image:
+=============================================
+
+Note that U-Boot versions up to and including 2009.06 had essentially
+two copies of U-Boot in flash; one at the very beginning, which set
+the HRCW, and one at the very end, which was the image that was run.
+As of this point in time, the two have been combined into just one
+at the beginning of flash, which provides both the HRCW, and the image
+that is executed.  This frees up the remainder of flash for other uses.
+Use of the U-Boot command "fli" will indicate what parts are in use.
+Details for storing U-Boot to flash using a Wind River ICE can be found
+on page 19 of the board manual (request ERG-00328-001).  The following
+is a summary of that information:
+
+  - Connect ICE and establish connection to it from WorkBench/OCD.
+  - Ensure you have background mode (BKM) in the OCD terminal window.
+  - Select the appropriate flash type (listed above)
+  - Prepare a U-Boot image by using the Wind River Convert utility;
+    by using "Convert and Add file" on the ELF file from your build.
+    Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are
+    trying to preserve your old environment settings and user flash).
+  - Set the start address of the erase/flash process to FF80_0000
+  - Set the target RAM required to 64kB.
+  - Select sectors for erasing (see note on environment below)
+  - Select Erase and Reprogram.
+
+Note that some versions of the register files used with Workbench
+would zero some TSEC registers, which inhibits ethernet operation
+by U-Boot when this register file is played to the target.  Using
+"INN" in the OCD terminal window instead of "IN" before the "GO"
+will not play the register file, and allow U-Boot to use the TSEC
+interface while executed from the ICE "GO" command.
+
+Alternatively, you can locate the register file which will be named
+WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines
+beginning with "SCGA TSEC1" and "SCGA TSEC2".  This allows you to
+use all the remaining register file content.
+
+If you wish to preserve your prior U-Boot environment settings,
+then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF.
+The size for converting (and erasing) must be at least as large
+as u-boot.bin.
+
+
+Updating U-Boot with U-Boot:
+============================
+
+This procedure is very similar to other boards that have U-Boot installed.
+Assuming that the network has been configured, and that the new u-boot.bin
+has been copied to the TFTP server, the commands are:
+
+	tftp 200000 u-boot.bin
+	protect off all
+	erase ff800000 ff83ffff
+	cp.b 200000 ff800000 40000
+	protect on all
+
+You may wish to do a "md ff800000 20" operation as a prefix and postfix
+to the above steps to inspect/compare the HRCW before/after as an extra
+safety check before resetting the board upon completion of the reflash.
+
+PCI:
+====
+
+There are three configuration choices:
+	sbc8349_config
+	sbc8349_PCI_33_config
+	sbc8349_PCI_66_config
+
+The 1st does not enable CONFIG_PCI, and assumes that the PCI slot
+will be left empty (M66EN high), and so the board will operate with
+a base clock of 66MHz.  Note that you need both PCI enabled in U-Boot
+and linux in order to have functional PCI under linux.  The only
+reason for choosing to not enable PCI would be if you had a very
+early (rev 1.0) CPU with possible PCI issues.
+
+The second enables PCI support and builds for a 33MHz clock rate.  Note
+that if a 33MHz 32bit card is inserted in the slot, then the whole board
+will clock down to a 33MHz base clock instead of the default 66MHz.  This
+will change the baud clocks and mess up your serial console output if you
+were previously running at 66MHz.  If you want to use a 33MHz PCI card,
+then you should build a U-Boot with sbc8349_PCI_33_config and store this
+to flash prior to powering down the board and inserting the 33MHz PCI
+card.
+
+The third option builds PCI support in, and leaves the clocking at the
+default 66MHz.  This has been tested with an intel PCI-X e1000 card.
+This is also the appropriate choice for people with a recent (non 1.0)
+CPU who currently have the PCI slot physically empty, but intend to
+possibly add a PCI-X card at a later date.
+
+   => pci
+   Scanning PCI devices on bus 0
+   BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
+   _____________________________________________________________
+   00.00.00   0x1957     0x0080     Processor               0x20
+   00.11.00   0x8086     0x1026     Network controller      0x00
+   =>
diff --git a/roms/u-boot/board/sbc8349/pci.c b/roms/u-boot/board/sbc8349/pci.c
new file mode 100644
index 000000000..26c4f24e4
--- /dev/null
+++ b/roms/u-boot/board/sbc8349/pci.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * pci.c -- WindRiver SBC8349 PCI board support.
+ * Copyright (c) 2006 Wind River Systems, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * Based on MPC8349 PCI support but w/o PIB related code.
+ */
+
+#include <init.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+#include <linux/delay.h>
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not supported. There is only one
+ * physical PCI slot on the board.
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci1_regions };
+
+	/* Enable all 8 PCI_CLK_OUTPUTS */
+	clk->occr = 0xff000000;
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	udelay(2000);
+
+	mpc83xx_pci_init(1, reg);
+}
diff --git a/roms/u-boot/board/sbc8349/sbc8349.c b/roms/u-boot/board/sbc8349/sbc8349.c
new file mode 100644
index 000000000..b440a0b17
--- /dev/null
+++ b/roms/u-boot/board/sbc8349/sbc8349.c
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * sbc8349.c -- WindRiver SBC8349 board support.
+ * Copyright (c) 2006-2007 Wind River Systems, Inc.
+ *
+ * Paul Gortmaker <paul.gortmaker@windriver.com>
+ * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/bitops.h>
+#include <asm/global_data.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd_sdram.h>
+#include <miiphy.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <linux/libfdt.h>
+#endif
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fixed_sdram(void);
+void sdram_init(void);
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f (void)
+{
+	return 0;
+}
+#endif
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+int dram_init(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+	/*
+	 * Initialize SDRAM if it is on local bus.
+	 */
+	sdram_init();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE;
+	u32 ddr_size = msize << 20;	/* DDR size in bytes */
+	u32 ddr_size_log2 = __ilog2(msize);
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+#if (CONFIG_SYS_DDR_SIZE != 256)
+#warning Currently any ddr size other than 256 is not supported
+#endif
+
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+	im->ddr.csbnds[2].csbnds =
+		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
+				CSBNDS_EA_SHIFT) & CSBNDS_EA);
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
+
+	/* currently we use only one CS, so disable the other banks */
+	im->ddr.cs_config[0] = 0;
+	im->ddr.cs_config[1] = 0;
+	im->ddr.cs_config[3] = 0;
+
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+
+	im->ddr.sdram_cfg =
+		SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+		| SDRAM_CFG_2T_EN
+#endif
+		| SDRAM_CFG_SDRAM_TYPE_DDR1;
+#if defined (CONFIG_DDR_32BIT)
+	/* for 32-bit mode burst length is 8 */
+	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	udelay(200);
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	return msize;
+}
+#endif/*!CONFIG_SYS_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+	puts("Board: Wind River SBC834x\n");
+	return 0;
+}
+
+/*
+ * if board is fitted with SDRAM
+ */
+#if defined(CONFIG_SYS_BR2_PRELIM)  \
+	&& defined(CONFIG_SYS_OR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+				 LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+				 LSDMR_WRC3 | LSDMR_CL3;
+
+	puts("\n   SDRAM on Local Bus: ");
+	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+	 */
+
+	/* setup mtrpt, lsrt and lbcr for LB bus */
+	lbc->lbcr = 0x00000000;
+	/* LB refresh timer prescal, 266MHz/32 */
+	lbc->mrtpr = 0x20000000;
+	/* LB sdram refresh timer, about 6us */
+	lbc->lsrt = 0x32000000;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller Machine Mode Register.
+	 */
+	/* 0x40636733; normal operation */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+
+	/* 0x68636733; precharge all the banks */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/* 0x48636733; auto refresh */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+	asm("sync");
+	/*1 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*2 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*3 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*4 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*5 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*6 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*7 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*8 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/* 0x58636733; mode register write operation */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/* 0x40636733; normal operation */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+}
+#else
+void sdram_init(void)
+{
+	puts("   SDRAM on Local Bus: Disabled in config\n");
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/sbc8548/Kconfig b/roms/u-boot/board/sbc8548/Kconfig
new file mode 100644
index 000000000..626cbdf2a
--- /dev/null
+++ b/roms/u-boot/board/sbc8548/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SBC8548
+
+config SYS_BOARD
+	default "sbc8548"
+
+config SYS_CONFIG_NAME
+	default "sbc8548"
+
+endif
diff --git a/roms/u-boot/board/sbc8548/MAINTAINERS b/roms/u-boot/board/sbc8548/MAINTAINERS
new file mode 100644
index 000000000..ba1f2475e
--- /dev/null
+++ b/roms/u-boot/board/sbc8548/MAINTAINERS
@@ -0,0 +1,10 @@
+SBC8548 BOARD
+M:	Paul Gortmaker <paul.gortmaker@windriver.com>
+S:	Maintained
+F:	board/sbc8548/
+F:	include/configs/sbc8548.h
+F:	configs/sbc8548_defconfig
+F:	configs/sbc8548_PCI_33_defconfig
+F:	configs/sbc8548_PCI_33_PCIE_defconfig
+F:	configs/sbc8548_PCI_66_defconfig
+F:	configs/sbc8548_PCI_66_PCIE_defconfig
diff --git a/roms/u-boot/board/sbc8548/Makefile b/roms/u-boot/board/sbc8548/Makefile
new file mode 100644
index 000000000..83d208cf1
--- /dev/null
+++ b/roms/u-boot/board/sbc8548/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2004-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007 Wind River Systems Inc <www.windriver.com>.
+# Added support for Wind River SBC8548 board
+
+obj-y	+= sbc8548.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/roms/u-boot/board/sbc8548/README b/roms/u-boot/board/sbc8548/README
new file mode 100644
index 000000000..0def245bd
--- /dev/null
+++ b/roms/u-boot/board/sbc8548/README
@@ -0,0 +1,269 @@
+Intro:
+======
+
+The SBC8548 is a stand alone single board computer with a 1GHz
+MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
+memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
+and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
+ethernet connections.
+
+U-Boot Configuration:
+=====================
+
+The following possible U-Boot configuration targets are available:
+
+	1) sbc8548_config
+	2) sbc8548_PCI_33_config
+	3) sbc8548_PCI_66_config
+	4) sbc8548_PCI_33_PCIE_config
+	5) sbc8548_PCI_66_PCIE_config
+
+Generally speaking, most people should choose to use #5.  Details
+of each choice are listed below.
+
+Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
+will be left empty (M66EN high), and so the board will operate with
+a base clock of 66MHz.	Note that you need both PCI enabled in U-Boot
+and linux in order to have functional PCI under linux.
+
+The second enables PCI support and builds for a 33MHz clock rate.  Note
+that if a 33MHz 32bit card is inserted in the slot, then the whole board
+will clock down to a 33MHz base clock instead of the default 66MHz.  This
+will change the baud clocks and mess up your serial console output if you
+were previously running at 66MHz.  If you want to use a 33MHz PCI card,
+then you should build a U-Boot with a _PCI_33_ config and store this
+to flash prior to powering down the board and inserting the 33MHz PCI
+card. [The above discussion assumes that the SW2[1-4] has not been changed
+to reflect a different CCB:SYSCLK ratio]
+
+The third option builds PCI support in, and leaves the clocking at the
+default 66MHz.	Options four and five are just repeats of option two
+and three, but with PCI-e support enabled as well.
+
+PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
+is shown below for sbc8548_PCI_66_PCIE_config.	(Note that PCI-e with
+a 33MHz PCI configuration is currently untested.)
+
+    => pci 0
+    Scanning PCI devices on bus 0
+    BusDevFun  VendorId	  DeviceId   Device Class	Sub-Class
+    _____________________________________________________________
+    00.00.00   0x1057	  0x0012     Processor		     0x20
+    00.01.00   0x8086	  0x1026     Network controller	     0x00
+    => pci 1
+    Scanning PCI devices on bus 1
+    BusDevFun  VendorId	  DeviceId   Device Class	Sub-Class
+    _____________________________________________________________
+    01.00.00   0x1957	  0x0012     Processor		     0x20
+    => pci 2
+    Scanning PCI devices on bus 2
+    BusDevFun  VendorId	  DeviceId   Device Class	Sub-Class
+    _____________________________________________________________
+    02.00.00   0x1148	  0x9e00     Network controller	     0x00
+    =>
+
+Memory Size and using SPD:
+==========================
+
+The default configuration uses hard coded memory configuration settings
+for 256MB of DDR2 @400MHz.  It does not by default use the DDR2 SPD
+EEPROM data to read what memory is installed.
+
+There is a hardware errata, which causes the older local bus SDRAM
+SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
+that the SPD data can not be read reliably.  You can test if your
+board has the errata fix by running "i2c probe".  If you see 0x53
+as a valid device, it has been fixed.  If you only see 0x50, 0x51
+then your board does not have the fix.
+
+You can also visually inspect the board to see if this hardware
+fix has been applied:
+
+      1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
+	 the back of the PCB behind the DDR SDRAM SODIMM connector.
+      2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
+	 to R313 pin 2.	 Pin 2 for each resistor is the end of the
+	 resistor closest to the CPU.
+
+Boards without the mod will have R314 and R313 in parallel, like "||".
+After the mod, they will be touching and form an "L" shape.
+
+If you want to upgrade to larger RAM size, you can simply enable
+	#define CONFIG_SPD_EEPROM
+	#define CONFIG_DDR_SPD
+in include/configs/sbc8548.h file.  (The lines are already there
+but listed as #undef).
+
+If you did the i2c test, and your board does not have the errata
+fix, then you will have to physically remove the LBC 128MB DIMM
+from the board's socket to resolve the above i2c address overlap
+issue and allow SPD autodetection of RAM to work.
+
+
+Updating U-Boot with U-Boot:
+============================
+
+Note that versions of U-Boot up to and including 2009.08 had U-Boot stored
+at 0xfff8_0000 -> 0xffff_ffff (512k).  Currently it is being stored from
+0xfffa_0000 -> 0xffff_ffff (384k).  If you use an old macro/script to
+update U-Boot with U-Boot and it uses the old address, you will render
+your board inoperable, and you will require JTAG recovery.
+
+The following steps list how to update with the current address:
+
+	tftp u-boot.bin
+	md 200000 10
+	protect off all
+	erase fffa0000 ffffffff
+	cp.b 200000 fffa0000 60000
+	md fffa0000 10
+	protect on all
+
+The "md" steps in the above are just a precautionary step that allow
+you to confirm the U-Boot version that was downloaded, and then confirm
+that it was copied to flash.
+
+The above assumes that you are using the default board settings which
+have U-Boot in the 8MB flash, tied to /CS0.
+
+If you are running the default 8MB /CS0 settings but want to store an
+image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
+(as a backup, etc) then the steps will become:
+
+	tftp u-boot.bin
+	md 200000 10
+	protect off all
+	era eff00000 efffffff
+	cp.b 200000 eff00000 100000
+	md eff00000 10
+	protect on all
+
+Finally, if you are running the alternate 64MB /CS0 settings and want
+to update the in-use U-Boot image, then (again with CONFIG_SYS_ALT_BOOT
+enabled) the steps will become:
+
+	tftp u-boot.bin
+	md 200000 10
+	protect off all
+	era fff00000 ffffffff
+	cp.b 200000 fff00000 100000
+	md fff00000 10
+	protect on all
+
+
+Hardware Reference:
+===================
+
+The following contains some summary information on hardware settings
+that are relevant to U-Boot, based on the board manual.	 For the
+most up to date and complete details of the board, please request the
+reference manual ERG-00327-001.pdf from www.windriver.com
+
+Boot flash:
+	intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
+
+Sodimm flash:
+	intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
+	Note that this address reflects the default setting for
+	the JTAG debugging tools, but since the alignment is
+	rather inconvenient, U-Boot puts it at 0xec00_0000.
+
+
+	Jumpers:
+
+Jumper		Name		ON		OFF
+----------------------------------------------------------------
+JP12		CS0/CS6 swap	see note[*]	see note[*]
+
+JP13		SODIMM flash	write OK	writes disabled
+		write prot.
+
+JP14		HRESET/TRST	joined		isolated
+
+JP15		PWR ON		when AC pwr	use S1 for on/off
+
+JP16		Demo LEDs	lit		not lit
+
+JP19		PCI mode	PCI		PCI-X
+
+
+[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
+onto /CS0 and the SODIMM flash on /CS6 (default).  When JP12
+is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
+SODIMM flash and /CS6 is for the boot flash.  Note that in this
+alternate setting, you also need to switch SW2.8 to ON.
+See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting
+and boot U-Boot from the 64MB SODIMM
+
+
+	Switches:
+
+The defaults are marked with a *
+
+Name		Desc.			ON		OFF
+------------------------------------------------------------------
+S1		Pwr toggle		n/a		n/a
+
+SW2.1		CFG_SYS_PLL0		1		0*
+SW2.2		CFG_SYS_PLL1		1*		0
+SW2.3		CFG_SYS_PLL2		1*		0
+SW2.4		CFG_SYS_PLL3		1		0*
+SW2.5		CFG_CORE_PLL0		1*		0
+SW2.6		CFG_CORE_PLL1		1		0*
+SW2.7		CFG_CORE_PLL2		1*		0
+SW2.8		CFG_ROM_LOC1		1		0*
+
+SW3.1		CFG_HOST_AGT0		1*		0
+SW3.2		CFG_HOST_AGT1		1*		0
+SW3.3		CFG_HOST_AGT2		1*		0
+SW3.4		CFG_IO_PORTS0		1*		0
+SW3.5		CFG_IO_PORTS0		1		0*
+SW3.6		CFG_IO_PORTS0		1		0*
+
+SerDes CLK(MHz)		SW5.1		SW5.2
+----------------------------------------------
+25			0		0
+100*			1		0
+125			0		1
+200			1		1
+
+SerDes CLK spread	SW5.3		SW5.4
+----------------------------------------------
++/- 0.25%		0		0
+-0.50%			1		0
+-0.75%			0		1
+No Spread*		1		1
+
+SW4 settings are readable from the EPLD and are currently not used for
+any hardware settings (i.e. user configuration switches).
+
+	LEDs:
+
+Name		Desc.			ON		OFF
+------------------------------------------------------------------
+D13		PCI/PCI-X		PCI-X		PCI
+D14		3.3V PWR		3.3V		no power
+D15		SYSCLK			66MHz		33MHz
+
+
+	Default Memory Map:
+
+start		end		CS<n>	width	Desc.
+----------------------------------------------------------------------
+0000_0000	0fff_ffff	MCS0,1	64	DDR2 (256MB)
+f000_0000	f7ff_ffff	CS3,4	32	LB SDRAM (128MB)
+f800_0000	f8b0_1fff	CS5	-	EPLD
+fb80_0000	ff7f_ffff	CS6	32	SODIMM flash (64MB) [*]
+ff80_0000	ffff_ffff	CS0	8	Boot flash (8MB)
+
+[*] fb80 represents the default programmed by WR JTAG register files,
+    but U-Boot places the flash at either ec00 or fc00 based on JP12.
+
+The EPLD on CS5 demuxes the following devices at the following offsets:
+
+offset		size	width	device
+--------------------------------------------------------
+0		1fff	8	7 segment display LED
+10_0000		1fff	4	user switches
+30_0000		1fff	4	HW Rev. register
+b0_0000		1fff	8	8kB EEPROM
diff --git a/roms/u-boot/board/sbc8548/ddr.c b/roms/u-boot/board/sbc8548/ddr.c
new file mode 100644
index 000000000..61bc77c41
--- /dev/null
+++ b/roms/u-boot/board/sbc8548/ddr.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <linux/delay.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
+
+#ifdef CONFIG_SPD_EEPROM
+/*
+ * Workaround for hardware errata.  An i2c address conflict
+ * existed on earlier boards; the workaround moved the DDR
+ * SPD from 0x51 to 0x53.  So we try and read 0x53 1st, and
+ * if that fails, then fall back to reading at 0x51.
+ */
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+	int ret;
+
+#ifdef ALT_SPD_EEPROM_ADDRESS
+	if (i2c_address == SPD_EEPROM_ADDRESS) {
+		ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,
+				sizeof(generic_spd_eeprom_t));
+		if (ret == 0)
+			return;		/* Good data at 0x53 */
+		memset(spd, 0, sizeof(generic_spd_eeprom_t));
+	}
+#endif
+	ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
+				sizeof(generic_spd_eeprom_t));
+	if (ret) {
+		printf("DDR: failed to read SPD from addr %u\n", i2c_address);
+		memset(spd, 0, sizeof(generic_spd_eeprom_t));
+	}
+}
+
+#else
+/*
+ *  fixed_sdram init -- doesn't use serial presence detect.
+ *  Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
+ */
+phys_size_t fixed_sdram(void)
+{
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+
+	out_be32(&ddr->cs0_bnds,	0x0000007f);
+	out_be32(&ddr->cs1_bnds,	0x008000ff);
+	out_be32(&ddr->cs2_bnds,	0x00000000);
+	out_be32(&ddr->cs3_bnds,	0x00000000);
+
+	out_be32(&ddr->cs0_config,	0x80010101);
+	out_be32(&ddr->cs1_config,	0x80010101);
+	out_be32(&ddr->cs2_config,	0x00000000);
+	out_be32(&ddr->cs3_config,	0x00000000);
+
+	out_be32(&ddr->timing_cfg_3,	0x00000000);
+	out_be32(&ddr->timing_cfg_0,	0x00220802);
+	out_be32(&ddr->timing_cfg_1,	0x38377322);
+	out_be32(&ddr->timing_cfg_2,	0x0fa044C7);
+
+	out_be32(&ddr->sdram_cfg,	0x4300C000);
+	out_be32(&ddr->sdram_cfg_2,	0x24401000);
+
+	out_be32(&ddr->sdram_mode,	0x23C00542);
+	out_be32(&ddr->sdram_mode_2,	0x00000000);
+
+	out_be32(&ddr->sdram_interval,	0x05080100);
+	out_be32(&ddr->sdram_md_cntl,	0x00000000);
+	out_be32(&ddr->sdram_data_init,	0x00000000);
+	out_be32(&ddr->sdram_clk_cntl,	0x03800000);
+	asm("sync;isync;msync");
+	udelay(500);
+
+	#ifdef CONFIG_DDR_ECC
+	  /* Enable ECC checking */
+	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
+	#else
+	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+	#endif
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
diff --git a/roms/u-boot/board/sbc8548/law.c b/roms/u-boot/board/sbc8548/law.c
new file mode 100644
index 000000000..97271ea6f
--- /dev/null
+++ b/roms/u-boot/board/sbc8548/law.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000	0x0fff_ffff	DDR			256M
+ * 0x8000_0000	0x9fff_ffff	PCI1 MEM		512M
+ * 0xa000_0000	0xbfff_ffff	PCIe MEM		512M
+ * 0xe000_0000	0xe000_ffff	CCSR			1M
+ * 0xe200_0000	0xe27f_ffff	PCI1 IO			8M
+ * 0xe280_0000	0xe2ff_ffff	PCIe IO			8M
+ * 0xec00_0000	0xefff_ffff	FLASH (2nd bank)	64M
+ * 0xf000_0000	0xf7ff_ffff	SDRAM			128M
+ * 0xf8b0_0000	0xf80f_ffff	EEPROM			1M
+ * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M
+ *
+ * If swapped CS0/CS6 via JP12+SW2.8:
+ * 0xef80_0000	0xefff_ffff	FLASH (2nd bank)	8M
+ * 0xfc00_0000	0xffff_ffff	FLASH (boot bank)	64M
+ *
+ * Notes:
+ *	CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *	If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_SYS_ALT_BOOT
+	SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+#else
+	SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#endif
+#ifndef CONFIG_SPD_EEPROM
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
+#endif
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#else
+	/* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/sbc8548/sbc8548.c b/roms/u-boot/board/sbc8548/sbc8548.c
new file mode 100644
index 000000000..bd4b528d0
--- /dev/null
+++ b/roms/u-boot/board/sbc8548/sbc8548.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
+ *
+ * Copyright 2007 Embedded Specialties, Inc.
+ *
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <spd_sdram.h>
+#include <netdev.h>
+#include <tsec.h>
+#include <miiphy.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+void local_bus_init(void);
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+	volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
+
+	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
+			in_8(rev) >> 4);
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	out_be32(&ecm->eedr, 0xffffffff);	/* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff);	/* enable ecm errors */
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+
+	lbc_mhz = sysinfo.freq_localbus / 1000000;
+	clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
+
+	debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
+
+	out_be32(&gur->lbiuiplldcr1, 0x00078080);
+	if (clkdiv == 16) {
+		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
+	} else if (clkdiv == 8) {
+		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
+	} else if (clkdiv == 4) {
+		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
+	}
+
+	/*
+	 * Local Bus Clock > 83.3 MHz. According to timing
+	 * specifications set LCRR[EADC] to 2 delay cycles.
+	 */
+	if (lbc_mhz > 83) {
+		lcrr &= ~LCRR_EADC;
+		lcrr |= LCRR_EADC_2;
+	}
+
+	/*
+	 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
+	 * disable PLL bypass for Local Bus Clock > 83 MHz.
+	 */
+	if (lbc_mhz >= 66)
+		lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
+
+	else
+		lcrr |= LCRR_DBYP;	/* DLL Bypass */
+
+	out_be32(&lbc->lcrr, lcrr);
+	asm("sync;isync;msync");
+
+	 /*
+	 * According to MPC8548ERMAD Rev.1.3 read back LCRR
+	 * and terminate with isync
+	 */
+	lcrr = in_be32(&lbc->lcrr);
+	asm ("isync;");
+
+	/* let DLL stabilize */
+	udelay(500);
+
+	out_be32(&lbc->ltesr, 0xffffffff);	/* Clear LBC error IRQs */
+	out_be32(&lbc->lteir, 0xffffffff);	/* Enable LBC error IRQs */
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
+
+	uint idx;
+	const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
+
+	puts("    SDRAM: ");
+
+	print_size(size, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
+	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
+
+	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+	asm("msync");
+
+	out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
+	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+	asm("msync");
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	*sdram_addr2 = 0xff;
+	ppcDcbf((unsigned long) sdram_addr2);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		*sdram_addr2 = 0xff;
+		ppcDcbf((unsigned long) sdram_addr2);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	*sdram_addr2 = 0xff;
+	ppcDcbf((unsigned long) sdram_addr2);
+	udelay(100);
+
+	/*
+	 * Issue RFEN command.
+	 */
+	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	*sdram_addr2 = 0xff;
+	ppcDcbf((unsigned long) sdram_addr2);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CONFIG_SYS_MEMTEST_START,
+	       CONFIG_SYS_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif	/* CONFIG_PCI1 */
+
+#ifdef CONFIG_PCI
+void
+pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int first_free_busno = 0;
+
+#ifdef CONFIG_PCI1
+	struct fsl_pci_info pci_info;
+	u32 devdisr = in_be32(&gur->devdisr);
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	u32 porpllsr = in_be32(&gur->porpllsr);
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
+		uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+		uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+		uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* get_clock_freq() */
+
+		printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
+			(pci_32) ? 32 : 64,
+			(pci_speed == 33000000) ? "33" :
+			(pci_speed == 66000000) ? "66" : "unknown",
+			pci_clk_sel ? "sync" : "async",
+			pci_arb ? "arbiter" : "external-arbiter");
+
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+	} else {
+		printf("PCI: disabled\n");
+	}
+
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
+
+	fsl_pcie_init_board(first_free_busno);
+}
+#endif
+
+int board_eth_init(struct bd_info *bis)
+{
+	tsec_standard_init(bis);
+	pci_eth_init(bis);
+	return 0;	/* otherwise cpu_eth_init gets run */
+}
+
+int last_stage_init(void)
+{
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_FSL_PCI_INIT
+	FT_FSL_PCI_SETUP;
+#endif
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/sbc8548/tlb.c b/roms/u-boot/board/sbc8548/tlb.c
new file mode 100644
index 000000000..8ad01d10e
--- /dev/null
+++ b/roms/u-boot/board/sbc8548/tlb.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	64M	Non-cacheable, guarded
+	 * 0xfc000000	56M	unused
+	 * 0xff800000	8M	boot FLASH
+	 *	.... or ....
+	 * 0xfc000000	64M	user flash
+	 *
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 1:	1G	Non-cacheable, guarded
+	 * 0x80000000	512M	PCI1 MEM
+	 * 0xa0000000	512M	PCIe MEM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1G, 1),
+
+	/*
+	 * TLB 2:	64M	Non-cacheable, guarded
+	 * 0xe0000000	1M	CCSRBAR
+	 * 0xe2000000	8M	PCI1 IO
+	 * 0xe2800000	8M	PCIe IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
+	/*
+	 * TLB 3:	64M	Cacheable, non-guarded
+	 * 0xf0000000	64M	LBC SDRAM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 3, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 4:	64M	Cacheable, non-guarded
+	 * 0xf4000000	64M	LBC SDRAM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
+		      CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 4, BOOKE_PAGESZ_64M, 1),
+#endif
+
+	/*
+	 * TLB 5:	16M	Cacheable, non-guarded
+	 * 0xf8000000	1M	7-segment LED display
+	 * 0xf8100000	1M	User switches
+	 * 0xf8300000	1M	Board revision
+	 * 0xf8b00000	1M	EEPROM
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_16M, 1),
+
+#ifndef CONFIG_SYS_ALT_BOOT
+	/*
+	 * TLB 6:	64M	Non-cacheable, guarded
+	 * 0xec000000	64M	64MB user FLASH
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+#else
+	/*
+	 * TLB 6:	4M	Non-cacheable, guarded
+	 * 0xef800000	4M	1st 1/2 8MB soldered FLASH
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_4M, 1),
+
+	/*
+	 * TLB 7:	4M	Non-cacheable, guarded
+	 * 0xefc00000	4M	2nd half 8MB soldered FLASH
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
+		      CONFIG_SYS_ALT_FLASH + 0x400000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_4M, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/sbc8641d/Kconfig b/roms/u-boot/board/sbc8641d/Kconfig
new file mode 100644
index 000000000..8dfc90cf8
--- /dev/null
+++ b/roms/u-boot/board/sbc8641d/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SBC8641D
+
+config SYS_BOARD
+	default "sbc8641d"
+
+config SYS_CONFIG_NAME
+	default "sbc8641d"
+
+endif
diff --git a/roms/u-boot/board/sbc8641d/MAINTAINERS b/roms/u-boot/board/sbc8641d/MAINTAINERS
new file mode 100644
index 000000000..a50b541ff
--- /dev/null
+++ b/roms/u-boot/board/sbc8641d/MAINTAINERS
@@ -0,0 +1,6 @@
+SBC8641D BOARD
+M:	Paul Gortmaker <paul.gortmaker@windriver.com>
+S:	Maintained
+F:	board/sbc8641d/
+F:	include/configs/sbc8641d.h
+F:	configs/sbc8641d_defconfig
diff --git a/roms/u-boot/board/sbc8641d/Makefile b/roms/u-boot/board/sbc8641d/Makefile
new file mode 100644
index 000000000..c48f82d3d
--- /dev/null
+++ b/roms/u-boot/board/sbc8641d/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= sbc8641d.o
+obj-y	+= law.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/roms/u-boot/board/sbc8641d/README b/roms/u-boot/board/sbc8641d/README
new file mode 100644
index 000000000..4999b7763
--- /dev/null
+++ b/roms/u-boot/board/sbc8641d/README
@@ -0,0 +1,49 @@
+Wind River SBC8641D reference board
+===========================
+
+Created 06/14/2007 Joe Hamman
+Copyright 2007, Embedded Specialties, Inc.
+Copyright 2007 Wind River Systems, Inc.
+-----------------------------
+
+1. Building U-Boot
+------------------
+The SBC8641D code is known to build using ELDK 4.1.
+
+    $ make sbc8641d_config
+    Configuring for sbc8641d board...
+
+    $ make
+
+
+2. Switch and Jumper Settings
+-----------------------------
+All Jumpers & Switches are in their default positions.  Please refer to
+the board documentation for details.  Some settings control CPU voltages
+and settings may change with board revisions.
+
+3. Known limitations
+--------------------
+PCI:
+	The PCI command may hang if no boards are present in either slot.
+
+4. Reflashing U-Boot
+--------------------
+The board has two independent flash devices which can be used for dual
+booting, or for U-Boot backup and recovery.  A two pin jumper on the
+three pin JP10 determines which device is attached to /CS0 line.
+
+Assuming one device has a functional U-Boot, and the other device has
+a recently installed non-functional image, to perform a recovery from
+that non-functional image goes essentially as follows:
+
+a) power down the board and jumper JP10 to select the functional image.
+b) power on the board and let it get to U-Boot prompt.
+c) while on, using static precautions, move JP10 back to the failed image.
+d) use "md fff00000" to confirm you are looking at the failed image
+e) turn off write protect with "prot off all"
+f) get new image, i.e. "tftp 200000 /somepath/u-boot.bin"
+g) erase failed image: "erase FFF00000 FFF5FFFF"
+h) copy in new image: "cp.b 200000 FFF00000 60000"
+i) ensure new image is written: "md fff00000"
+k) power cycle the board and confirm new image works.
diff --git a/roms/u-boot/board/sbc8641d/ddr.c b/roms/u-boot/board/sbc8641d/ddr.c
new file mode 100644
index 000000000..b6c1847b1
--- /dev/null
+++ b/roms/u-boot/board/sbc8641d/ddr.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/roms/u-boot/board/sbc8641d/law.c b/roms/u-boot/board/sbc8641d/law.c
new file mode 100644
index 000000000..dc4696d12
--- /dev/null
+++ b/roms/u-boot/board/sbc8641d/law.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW (Local Access Window) configuration:
+ *
+ * 0x0000_0000	DDR			256M
+ * 0x1000_0000	DDR2			256M
+ * 0x8000_0000	PCIE1 MEM		512M
+ * 0xa000_0000	PCIE2 MEM		512M
+ * 0xc000_0000	RapidIO			512M
+ * 0xe200_0000	PCIE1 IO		16M
+ * 0xe300_0000	PCIE2 IO		16M
+ * 0xf800_0000	CCSRBAR			2M
+ * 0xfe00_0000	FLASH (boot bank)	32M
+ *
+ */
+
+
+struct law_entry law_table[] = {
+#if !defined(CONFIG_SPD_EEPROM)
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+		 LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
+#endif
+	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/sbc8641d/sbc8641d.c b/roms/u-boot/board/sbc8641d/sbc8641d.c
new file mode 100644
index 000000000..a67092daf
--- /dev/null
+++ b/roms/u-boot/board/sbc8641d/sbc8641d.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman joe.hamman@embeddedspecialties.com
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <log.h>
+#include <pci.h>
+#include <asm/global_data.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+long int fixed_sdram (void);
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Wind River SBC8641D\n");
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = fsl_ddr_sdram();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+	debug("    DDR: ");
+	gd->ram_size = dram_size;
+
+	return 0;
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram(void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	puts ("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	puts ("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	puts ("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+long int fixed_sdram (void)
+{
+#if !defined(CONFIG_SYS_RAMBOOT)
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
+	ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
+	ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
+	ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
+	ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+	ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+
+	asm ("sync;isync");
+
+	udelay(500);
+
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
+	asm ("sync; isync");
+
+	udelay(500);
+	ddr = &immap->im_ddr2;
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
+	ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
+	ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
+	ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
+	ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
+	ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
+	ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
+	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
+	ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
+	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
+
+	asm ("sync;isync");
+
+	udelay(500);
+
+	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
+	asm ("sync; isync");
+
+	udelay(500);
+#endif
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif				/* !defined(CONFIG_SPD_EEPROM) */
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif /* CONFIG_PCI */
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	FT_FSL_PCI_SETUP;
+
+	return 0;
+}
+#endif
+
+void sbc8641d_reset_board (void)
+{
+	puts ("Resetting board....\n");
+}
+
+/*
+ * get_board_sys_clk
+ *      Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long get_board_sys_clk (ulong dummy)
+{
+	int i;
+	ulong val = 0;
+
+	i = 5;
+	i &= 0x07;
+
+	switch (i) {
+	case 0:
+		val = 33000000;
+		break;
+	case 1:
+		val = 40000000;
+		break;
+	case 2:
+		val = 50000000;
+		break;
+	case 3:
+		val = 66000000;
+		break;
+	case 4:
+		val = 83000000;
+		break;
+	case 5:
+		val = 100000000;
+		break;
+	case 6:
+		val = 134000000;
+		break;
+	case 7:
+		val = 166000000;
+		break;
+	}
+
+	return val;
+}
+
+void board_reset(void)
+{
+#ifdef CONFIG_SYS_RESET_ADDRESS
+	ulong addr = CONFIG_SYS_RESET_ADDRESS;
+
+	/* flush and disable I/D cache */
+	__asm__ __volatile__ ("mfspr	3, 1008"	::: "r3");
+	__asm__ __volatile__ ("ori	5, 5, 0xcc00"	::: "r5");
+	__asm__ __volatile__ ("ori	4, 3, 0xc00"	::: "r4");
+	__asm__ __volatile__ ("andc	5, 3, 5"	::: "r5");
+	__asm__ __volatile__ ("sync");
+	__asm__ __volatile__ ("mtspr	1008, 4");
+	__asm__ __volatile__ ("isync");
+	__asm__ __volatile__ ("sync");
+	__asm__ __volatile__ ("mtspr	1008, 5");
+	__asm__ __volatile__ ("isync");
+	__asm__ __volatile__ ("sync");
+
+	/*
+	 * SRR0 has system reset vector, SRR1 has default MSR value
+	 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
+	 */
+	__asm__ __volatile__ ("mtspr	26, %0"		:: "r" (addr));
+	__asm__ __volatile__ ("li	4, (1 << 6)"	::: "r4");
+	__asm__ __volatile__ ("mtspr	27, 4");
+	__asm__ __volatile__ ("rfi");
+#endif
+}
diff --git a/roms/u-boot/board/seeed/linkit-smart-7688/Kconfig b/roms/u-boot/board/seeed/linkit-smart-7688/Kconfig
new file mode 100644
index 000000000..a9d63285c
--- /dev/null
+++ b/roms/u-boot/board/seeed/linkit-smart-7688/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_LINKIT_SMART_7688
+
+config SYS_BOARD
+	default "linkit-smart-7688"
+
+config SYS_VENDOR
+	default "seeed"
+
+config SYS_CONFIG_NAME
+	default "linkit-smart-7688"
+
+endif
diff --git a/roms/u-boot/board/seeed/linkit-smart-7688/MAINTAINERS b/roms/u-boot/board/seeed/linkit-smart-7688/MAINTAINERS
new file mode 100644
index 000000000..f2186c1b9
--- /dev/null
+++ b/roms/u-boot/board/seeed/linkit-smart-7688/MAINTAINERS
@@ -0,0 +1,8 @@
+LINKIT_SMART_7688 BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/seeed/linkit-smart-7688
+F:	include/configs/linkit-smart-7688.h
+F:	configs/linkit-smart-7688_defconfig
+F:	configs/linkit-smart-7688-ram_defconfig
+F:	arch/mips/dts/linkit-smart-7688.dts
diff --git a/roms/u-boot/board/seeed/linkit-smart-7688/Makefile b/roms/u-boot/board/seeed/linkit-smart-7688/Makefile
new file mode 100644
index 000000000..70cd7a8e5
--- /dev/null
+++ b/roms/u-boot/board/seeed/linkit-smart-7688/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += board.o
diff --git a/roms/u-boot/board/seeed/linkit-smart-7688/board.c b/roms/u-boot/board/seeed/linkit-smart-7688/board.c
new file mode 100644
index 000000000..bf7c69ea8
--- /dev/null
+++ b/roms/u-boot/board/seeed/linkit-smart-7688/board.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+#define MT76XX_GPIO1_MODE	0x10000060
+
+void board_debug_uart_init(void)
+{
+	void __iomem *gpio_mode;
+
+	/* Select UART2 mode instead of GPIO mode (default) */
+	gpio_mode = ioremap_nocache(MT76XX_GPIO1_MODE, 0x100);
+	clrbits_le32(gpio_mode, GENMASK(27, 26));
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * The pin muxing of UART2 also needs to be done, if debug uart
+	 * is not enabled. So we need to call this function here as well.
+	 */
+	board_debug_uart_init();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/seeed/npi_imx6ull/Kconfig b/roms/u-boot/board/seeed/npi_imx6ull/Kconfig
new file mode 100644
index 000000000..5e298299a
--- /dev/null
+++ b/roms/u-boot/board/seeed/npi_imx6ull/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NPI_IMX6ULL
+
+config SYS_BOARD
+	default "npi_imx6ull"
+
+config SYS_VENDOR
+	default "seeed"
+
+config SYS_CONFIG_NAME
+	default "npi_imx6ull"
+
+endif
diff --git a/roms/u-boot/board/seeed/npi_imx6ull/MAINTAINERS b/roms/u-boot/board/seeed/npi_imx6ull/MAINTAINERS
new file mode 100644
index 000000000..c6a915c79
--- /dev/null
+++ b/roms/u-boot/board/seeed/npi_imx6ull/MAINTAINERS
@@ -0,0 +1,9 @@
+NPI_IMX6ULL BOARD
+M:	Navin Sankar Velliangiri <navin@linumiz.com>
+S:	Maintained
+F:	arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts
+F:	arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi
+F:	arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi
+F:	board/seeed/npi-imx6ull/
+F:	configs/seeed_npi_imx6ull_defconfig
+F:	include/configs/npi_imx6ull.h
diff --git a/roms/u-boot/board/seeed/npi_imx6ull/Makefile b/roms/u-boot/board/seeed/npi_imx6ull/Makefile
new file mode 100644
index 000000000..93ea41351
--- /dev/null
+++ b/roms/u-boot/board/seeed/npi_imx6ull/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	:= npi_imx6ull.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/roms/u-boot/board/seeed/npi_imx6ull/README b/roms/u-boot/board/seeed/npi_imx6ull/README
new file mode 100644
index 000000000..01d218a9b
--- /dev/null
+++ b/roms/u-boot/board/seeed/npi_imx6ull/README
@@ -0,0 +1,61 @@
+How to use U-BOOT on SeeedStudio NPI-IMX6ULL Single Board Computer
+------------------------------------------------------------------
+
+- Configure and build U-Boot for NPI-IMX6ULL:
+
+    $ export ARCH=arm
+    $ export CROSS_COMPILE=arm-none-linux-gnueabihf-
+    $ make seeed_npi_imx6ull_defconfig
+    $ make
+
+This will generate SPL and u-boot-dtb.img images.
+
+Boot from MMC/SD:
+- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card:
+
+    $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+    $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Boot mode settings:
+
+  Boot switch position: SW1 -> 0
+			SW2 -> 1
+			SW3 -> 0
+			SW4 -> 0
+			SW5 -> 1
+			SW6 -> 0
+			SW7 -> 0
+			SW8 -> 1
+
+Boot from NAND:
+- Boot the board using SD/MMC or Serial download and load the SPL into memory
+either from SD/MMC or TFTP.
+
+Default MTD layout is 512k(spl),1m(uboot),1m(uboot-dup),-(ubi)
+
+Flash SPL to NAND from SD/MMC,
+
+    $ ext4load mmc 0:2 $loadaddr SPL
+    $ nand erase.part spl
+    $ nandbcb init $loadaddr 0x0 $filesize
+
+Flash u-boot image to NAND from SD/MMC,
+
+    $ ext4load mmc 0:2 $loadaddr u-boot-dtb.img
+    $ nand erase.part uboot
+    $ nand write $loadaddr uboot $filesize
+
+- Boot mode settings:
+
+  Boot switch position: SW1 -> 0
+			SW2 -> 1
+			SW3 -> 1
+			SW4 -> 0
+			SW5 -> 0
+			SW6 -> 1
+			SW7 -> 0
+			SW8 -> 0
+
+- Connect the Serial cable to UART0 and the PC for the console.
+
+- Reset the board using reset button and U-Boot should boot from NAND.
diff --git a/roms/u-boot/board/seeed/npi_imx6ull/npi_imx6ull.c b/roms/u-boot/board/seeed/npi_imx6ull/npi_imx6ull.c
new file mode 100644
index 000000000..eb9ee555c
--- /dev/null
+++ b/roms/u-boot/board/seeed/npi_imx6ull/npi_imx6ull.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Linumiz
+ * Author: Navin Sankar Velliangiri <navin@linumiz.com>
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/bitops.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE         | PAD_CTL_PUE       | \
+			PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | \
+			PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+
+static int setup_fec(int fec_id)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	if (fec_id == 0) {
+		/*
+		 * Use 50MHz anatop loopback REF_CLK1 for ENET1,
+		 * clear gpr1[13], set gpr1[17].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+	} else {
+		/*
+		 * Use 50MHz anatop loopbak REF_CLK2 for ENET2,
+		 * clear gpr1[14], set gpr1[18].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+	}
+
+	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec(CONFIG_FEC_ENET_DEV);
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: Seeed NPi i.MX6ULL Dev Board\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/seeed/npi_imx6ull/spl.c b/roms/u-boot/board/seeed/npi_imx6ull/spl.c
new file mode 100644
index 000000000..4b56f52d9
--- /dev/null
+++ b/roms/u-boot/board/seeed/npi_imx6ull/spl.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Linumiz
+ * Author: Navin Sankar Velliangiri <navin@linumiz.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <fsl_esdhc_imx.h>
+
+/* Configuration for Micron MT41K256M16TW-107 32M x 16 x 8 -> 512MiB */
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x41480148,
+	.p0_mprddlctl = 0x40403E42,
+	.p0_mpwrdlctl = 0x40405852,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,             /* Bus size = 16bit */
+	.cs_density = 32,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 1,
+	.rtt_nom = 1,
+	.walat = 1,             /* Write additional latency */
+	.ralat = 5,             /* Read additional latency */
+	.mif3_mode = 3,         /* Command prediction working mode */
+	.bi_on = 1,             /* Bank interleaving enabled */
+	.pd_fast_exit = 1,
+	.sde_to_rst = 0x10,
+	.rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
+	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 1,            /* Refresh cycles at 32KHz */
+	.refr = 7,              /* 8 refresh commands per refresh cycle */
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE         | PAD_CTL_PUE       | \
+			PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW | \
+			PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | \
+			PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifndef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_NAND_RE_B__USDHC2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+	{
+		.esdhc_base = USDHC1_BASE_ADDR,
+		.max_bus_width = 4,
+	},
+#ifndef CONFIG_NAND_MXS
+	{
+		.esdhc_base = USDHC2_BASE_ADDR,
+		.max_bus_width = 8,
+	},
+#endif
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+#ifndef CONFIG_NAND_MXS
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+#endif
+		default:
+			printf("Warning - USDHC%d controller not supporting\n",
+			       i + 1);
+			return 0;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* Setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* Setup iomux and fec */
+	board_early_init_f();
+
+	/* Setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
diff --git a/roms/u-boot/board/sfr/nb4_ser/Kconfig b/roms/u-boot/board/sfr/nb4_ser/Kconfig
new file mode 100644
index 000000000..78aefb547
--- /dev/null
+++ b/roms/u-boot/board/sfr/nb4_ser/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_SFR_NB4_SER
+
+config SYS_BOARD
+	default "nb4_ser"
+
+config SYS_VENDOR
+	default "sfr"
+
+config SYS_CONFIG_NAME
+	default "sfr_nb4_ser"
+
+endif
diff --git a/roms/u-boot/board/sfr/nb4_ser/MAINTAINERS b/roms/u-boot/board/sfr/nb4_ser/MAINTAINERS
new file mode 100644
index 000000000..bf80267f0
--- /dev/null
+++ b/roms/u-boot/board/sfr/nb4_ser/MAINTAINERS
@@ -0,0 +1,6 @@
+SFR NEUFBOX 4 SERCOMM BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/sfr/nb4_ser/
+F:	include/configs/sfr_nb4_ser.h
+F:	configs/sfr_nb4-ser_ram_defconfig
diff --git a/roms/u-boot/board/sfr/nb4_ser/Makefile b/roms/u-boot/board/sfr/nb4_ser/Makefile
new file mode 100644
index 000000000..ab7ad76b2
--- /dev/null
+++ b/roms/u-boot/board/sfr/nb4_ser/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += nb4-ser.o
diff --git a/roms/u-boot/board/sfr/nb4_ser/nb4-ser.c b/roms/u-boot/board/sfr/nb4_ser/nb4-ser.c
new file mode 100644
index 000000000..1e4b7281d
--- /dev/null
+++ b/roms/u-boot/board/sfr/nb4_ser/nb4-ser.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <common.h>
diff --git a/roms/u-boot/board/siemens/capricorn/Kconfig b/roms/u-boot/board/siemens/capricorn/Kconfig
new file mode 100644
index 000000000..21c3ef909
--- /dev/null
+++ b/roms/u-boot/board/siemens/capricorn/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_GIEDI
+
+config SYS_BOARD
+	default "capricorn"
+
+config SYS_VENDOR
+	default "siemens"
+
+config SYS_CONFIG_NAME
+	default "giedi"
+
+endif
+
+if TARGET_DENEB
+
+config SYS_BOARD
+	default "capricorn"
+
+config SYS_VENDOR
+	default "siemens"
+
+config SYS_CONFIG_NAME
+	default "deneb"
+
+endif
diff --git a/roms/u-boot/board/siemens/capricorn/MAINTAINERS b/roms/u-boot/board/siemens/capricorn/MAINTAINERS
new file mode 100644
index 000000000..bc7d163e1
--- /dev/null
+++ b/roms/u-boot/board/siemens/capricorn/MAINTAINERS
@@ -0,0 +1,11 @@
+CAPRICORN BOARD
+M:	Anatolij Gustschin <agust@denx.de>
+S:	Maintained
+F:	board/siemens/capricorn/
+F:	include/configs/capricorn-common.h
+F:	include/configs/deneb.h
+F:	include/configs/giedi.h
+F:	include/configs/siemens-ccp-common.h
+F:	include/configs/siemens-env-common.h
+F:	configs/deneb_defconfig
+F:	configs/giedi_defconfig
diff --git a/roms/u-boot/board/siemens/capricorn/Makefile b/roms/u-boot/board/siemens/capricorn/Makefile
new file mode 100644
index 000000000..d5846cc8e
--- /dev/null
+++ b/roms/u-boot/board/siemens/capricorn/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Siemens AG
+#
+
+obj-y += board.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += ../common/factoryset.o
+endif
diff --git a/roms/u-boot/board/siemens/capricorn/board.c b/roms/u-boot/board/siemens/capricorn/board.c
new file mode 100644
index 000000000..dcbab8e4d
--- /dev/null
+++ b/roms/u-boot/board/siemens/capricorn/board.c
@@ -0,0 +1,453 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2019 NXP
+ *
+ * Copyright 2019 Siemens AG
+ *
+ */
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <log.h>
+#include <netdev.h>
+#include <env_internal.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <led.h>
+#include <pca953x.h>
+#include <power-domain.h>
+#include <asm/gpio.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+#ifndef CONFIG_SPL
+#include <asm/arch-imx8/clock.h>
+#endif
+#include <linux/delay.h>
+#include "../common/factoryset.h"
+
+#define GPIO_PAD_CTRL \
+		((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL \
+		((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+		 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL \
+		((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart2_pads[] = {
+	SC_P_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+int board_early_init_f(void)
+{
+	/* Set UART clock root to 80 MHz */
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	int ret;
+
+	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+	ret |= sc_pm_setup_uart(SC_R_UART_2, rate);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#define ENET_PHY_RESET	IMX_GPIO_NR(0, 3)
+#define ENET_TEST_1	IMX_GPIO_NR(0, 8)
+#define ENET_TEST_2	IMX_GPIO_NR(0, 9)
+
+/*#define ETH_IO_TEST*/
+static iomux_cfg_t enet_reset[] = {
+	SC_P_ESAI0_SCKT | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+#ifdef ETH_IO_TEST
+	/* GPIO0.IO08 MODE3: TXD0 */
+	SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(4) |
+	MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	/* GPIO0.IO09 MODE3: TXD1 */
+	SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(4) |
+	MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+#endif
+};
+
+static void enet_device_phy_reset(void)
+{
+	int ret = 0;
+
+	imx8_iomux_setup_multiple_pads(enet_reset, ARRAY_SIZE(enet_reset));
+
+	ret = gpio_request(ENET_PHY_RESET, "enet_phy_reset");
+	if (!ret) {
+		gpio_direction_output(ENET_PHY_RESET, 1);
+		gpio_set_value(ENET_PHY_RESET, 0);
+		/* SMSC9303 TRM chapter 14.5.2 */
+		udelay(200);
+		gpio_set_value(ENET_PHY_RESET, 1);
+	} else {
+		printf("ENET RESET failed!\n");
+	}
+
+#ifdef ETH_IO_TEST
+	ret =  gpio_request(ENET_TEST_1, "enet_test1");
+	if (!ret) {
+		int i;
+
+		printf("ENET TEST 1!\n");
+		for (i = 0; i < 20; i++) {
+			gpio_direction_output(ENET_TEST_1, 1);
+			gpio_set_value(ENET_TEST_1, 0);
+			udelay(50);
+			gpio_set_value(ENET_TEST_1, 1);
+			udelay(50);
+		}
+		gpio_free(ENET_TEST_1);
+	} else {
+		printf("GPIO for ENET TEST 1 failed!\n");
+	}
+	ret =  gpio_request(ENET_TEST_2, "enet_test2");
+	if (!ret) {
+		int i;
+
+		printf("ENET TEST 2!\n");
+		for (i = 0; i < 20; i++) {
+			gpio_direction_output(ENET_TEST_2, 1);
+			gpio_set_value(ENET_TEST_2, 0);
+			udelay(50);
+			gpio_set_value(ENET_TEST_2, 1);
+			udelay(50);
+		}
+		gpio_free(ENET_TEST_2);
+	} else {
+		printf("GPIO for ENET TEST 2 failed!\n");
+	}
+#endif
+}
+
+int setup_gpr_fec(void)
+{
+	sc_ipc_t ipc_handle = -1;
+	sc_err_t err = 0;
+	unsigned int test;
+
+	/*
+	 * TX_CLK_SEL: it controls a mux between clock coming from the pad 50M
+	 * input pin and clock generated internally to connectivity subsystem
+	 *	0: internal clock
+	 *	1: external clock --->  your choice for RMII
+	 *
+	 * CLKDIV_SEL: it controls a div by 2 on the internal clock path à
+	 *	it should be don’t care when using external clock
+	 *	0: non-divided clock
+	 *	1: clock divided by 2
+	 * 50_DISABLE or 125_DISABLE:
+	 *	it’s used to disable the clock tree going outside the chip
+	 *	when reference clock is generated internally.
+	 *	It should be don’t care when reference clock is provided
+	 *	externally.
+	 *	0: clock is enabled
+	 *	1: clock is disabled
+	 *
+	 * SC_C_TXCLK		= 24,
+	 * SC_C_CLKDIV		= 25,
+	 * SC_C_DISABLE_50	= 26,
+	 * SC_C_DISABLE_125	= 27,
+	 */
+
+	err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1);
+	if (err != SC_ERR_NONE)
+		printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK);
+
+	sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
+	debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test);
+
+	err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0);
+	if (err != SC_ERR_NONE)
+		printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV);
+
+	sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, &test);
+	debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test);
+
+	err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0);
+	if (err != SC_ERR_NONE)
+		printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50);
+
+	sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
+	debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test);
+
+	err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1);
+	if (err != SC_ERR_NONE)
+		printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125);
+
+	sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
+	debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test);
+
+	err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1);
+	if (err != SC_ERR_NONE)
+		printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125);
+
+	sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, &test);
+	debug("TEST SC_C %d-->%d\n\r", SC_C_SEL_125, test);
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#endif
+
+static int setup_fec(void)
+{
+	setup_gpr_fec();
+	/* Reset ENET PHY */
+	enet_device_phy_reset();
+	return 0;
+}
+
+void reset_cpu(void)
+{
+}
+
+#ifndef CONFIG_SPL_BUILD
+/* LED's */
+static int board_led_init(void)
+{
+	struct udevice *bus, *dev;
+	u8 pca_led[2] = { 0x00, 0x00 };
+	int ret;
+
+	/* init all GPIO LED's */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	/* enable all leds on PCA9552 */
+	ret = uclass_get_device_by_seq(UCLASS_I2C, PCA9552_1_I2C_BUS, &bus);
+	if (ret) {
+		printf("ERROR: I2C get %d\n", ret);
+		return ret;
+	}
+
+	ret = dm_i2c_probe(bus, PCA9552_1_I2C_ADDR, 0, &dev);
+	if (ret) {
+		printf("ERROR: PCA9552 probe failed\n");
+		return ret;
+	}
+
+	ret = dm_i2c_write(dev, 0x16, pca_led, sizeof(pca_led));
+	if (ret) {
+		printf("ERROR: PCA9552 write failed\n");
+		return ret;
+	}
+
+	mdelay(1);
+	return ret;
+}
+#endif /* !CONFIG_SPL_BUILD */
+
+int checkboard(void)
+{
+	puts("Board: Capricorn\n");
+
+	/*
+	 * Running build_info() doesn't work with current SCFW blob.
+	 * Uncomment below call when new blob is available.
+	 */
+	/*build_info();*/
+
+	print_bootinfo();
+	return 0;
+}
+
+int board_init(void)
+{
+	setup_fec();
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+static int check_mmc_autodetect(void)
+{
+	char *autodetect_str = env_get("mmcautodetect");
+
+	if (autodetect_str && (strcmp(autodetect_str, "yes") == 0))
+		return 1;
+
+	return 0;
+}
+
+/* This should be defined for each board */
+__weak int mmc_map_to_kernel_blk(int dev_no)
+{
+	return dev_no;
+}
+
+void board_late_mmc_env_init(void)
+{
+	char cmd[32];
+	char mmcblk[32];
+	u32 dev_no = mmc_get_env_dev();
+
+	if (!check_mmc_autodetect())
+		return;
+
+	env_set_ulong("mmcdev", dev_no);
+
+	/* Set mmcblk env */
+	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+		mmc_map_to_kernel_blk(dev_no));
+	env_set("mmcroot", mmcblk);
+
+	sprintf(cmd, "mmc dev %d", dev_no);
+	run_command(cmd, 0);
+}
+
+#ifndef CONFIG_SPL_BUILD
+int factoryset_read_eeprom(int i2c_addr);
+
+static int load_parameters_from_factoryset(void)
+{
+	int ret;
+
+	ret = factoryset_read_eeprom(EEPROM_I2C_ADDR);
+	if (ret)
+		return ret;
+
+	return factoryset_env_set();
+}
+
+int board_late_init(void)
+{
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+	/* Init LEDs */
+	if (board_led_init())
+		printf("I2C LED init failed\n");
+
+	/* Set environment from factoryset */
+	if (load_parameters_from_factoryset())
+		printf("Loading factoryset parameters failed!\n");
+
+	return 0;
+}
+
+/* Service button */
+#define MAX_PIN_NUMBER			128
+#define BOARD_DEFAULT_BUTTON_GPIO	IMX_GPIO_NR(1, 31)
+
+unsigned char get_button_state(char * const envname, unsigned char def)
+{
+	int button = 0;
+	int gpio;
+	char *ptr_env;
+
+	/* If button is not found we take default */
+	ptr_env = env_get(envname);
+	if (!ptr_env) {
+		printf("Using default: %u\n", def);
+		gpio = def;
+	} else {
+		gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0);
+		if (gpio > MAX_PIN_NUMBER)
+			gpio = def;
+	}
+
+	gpio_request(gpio, "");
+	gpio_direction_input(gpio);
+	if (gpio_get_value(gpio))
+		button = 1;
+	else
+		button = 0;
+
+	gpio_free(gpio);
+
+	return button;
+}
+
+/*
+ * This command returns the status of the user button on
+ * Input - none
+ * Returns -	1 if button is held down
+ *		0 if button is not held down
+ */
+static int
+do_userbutton(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int button = 0;
+
+	button = get_button_state("button_usr1", BOARD_DEFAULT_BUTTON_GPIO);
+
+	if (argc > 1)
+		printf("Button state: %u\n", button);
+
+	return button;
+}
+
+U_BOOT_CMD(
+	usrbutton, CONFIG_SYS_MAXARGS, 2, do_userbutton,
+	"Return the status of user button",
+	"[print]"
+);
+
+#define ERST	IMX_GPIO_NR(0, 3)
+
+static int
+do_eth_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	gpio_request(ERST, "ERST");
+	gpio_direction_output(ERST, 0);
+	udelay(200);
+	gpio_set_value(ERST, 1);
+	return 0;
+}
+
+U_BOOT_CMD(
+	switch_rst, CONFIG_SYS_MAXARGS, 2, do_eth_reset,
+	"Reset eth phy",
+	"[print]"
+);
+#endif /* ! CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/siemens/capricorn/imximage.cfg b/roms/u-boot/board/siemens/capricorn/imximage.cfg
new file mode 100644
index 000000000..9f9df68e6
--- /dev/null
+++ b/roms/u-boot/board/siemens/capricorn/imximage.cfg
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ *
+ * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU capricorn-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/roms/u-boot/board/siemens/capricorn/spl.c b/roms/u-boot/board/siemens/capricorn/spl.c
new file mode 100644
index 000000000..8e077d73a
--- /dev/null
+++ b/roms/u-boot/board/siemens/capricorn/spl.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Copyright 2019 Siemens AG
+ *
+ */
+#include <common.h>
+#include <init.h>
+#include <spl.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+
+	uclass_find_first_device(UCLASS_MISC, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+}
+
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/siemens/capricorn/uboot-container.cfg b/roms/u-boot/board/siemens/capricorn/uboot-container.cfg
new file mode 100644
index 000000000..816581181
--- /dev/null
+++ b/roms/u-boot/board/siemens/capricorn/uboot-container.cfg
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* This file is to create a container image could be loaded by SPL */
+BOOT_FROM SD 0x400
+SOC_TYPE IMX8QX
+CONTAINER
+IMAGE A35 bl31.bin	0x80000000
+IMAGE A35 u-boot.bin	CONFIG_SYS_TEXT_BASE
diff --git a/roms/u-boot/board/siemens/common/board.c b/roms/u-boot/board/siemens/common/board.c
new file mode 100644
index 000000000..1bdf404ac
--- /dev/null
+++ b/roms/u-boot/board/siemens/common/board.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Common board functions for siemens AM335X based boards
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/board/ti/am335x/board.c
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <malloc.h>
+#include <serial.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <watchdog.h>
+#include <asm/mach-types.h>
+#include "../common/factoryset.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	/* Initalize the board header */
+	enable_i2c0_pin_mux();
+	i2c_set_bus_num(0);
+
+	/* enable early the console */
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();
+	gd->have_console = 1;
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+
+	enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+	spl_siemens_board_init();
+	board_init_ddr();
+
+	return;
+}
+#endif /* #ifdef CONFIG_SPL_BUILD */
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif /* defined(CONFIG_HW_WATCHDOG) */
+	i2c_set_bus_num(0);
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+#ifdef CONFIG_MACH_TYPE
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+#endif
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_FACTORYSET
+	factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
+#endif
+
+	gpmc_init();
+
+#ifdef CONFIG_NAND_CS_INIT
+	board_nand_cs_init();
+#endif
+#ifdef CONFIG_VIDEO
+	board_video_init();
+#endif
+
+	return 0;
+}
+#endif /* #ifndef CONFIG_SPL_BUILD */
+
+#define OSC	(V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+		DDR_PLL_FREQ, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
+#ifndef CONFIG_SPL_BUILD
+
+#define MAX_NR_LEDS	10
+#define MAX_PIN_NUMBER	128
+#define STARTUP	0
+
+#if defined(BOARD_DFU_BUTTON_GPIO)
+unsigned char get_button_state(char * const envname, unsigned char def)
+{
+	int button = 0;
+	int gpio;
+	char *ptr_env;
+
+	/* If button is not found we take default */
+	ptr_env = env_get(envname);
+	if (NULL == ptr_env) {
+		gpio = def;
+	} else {
+		gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0);
+		if (gpio > MAX_PIN_NUMBER)
+			gpio = def;
+	}
+
+	gpio_request(gpio, "");
+	gpio_direction_input(gpio);
+	if (gpio_get_value(gpio))
+		button = 1;
+	else
+		button = 0;
+
+	gpio_free(gpio);
+
+	return button;
+}
+/**
+ * This command returns the status of the user button on
+ * Input - none
+ * Returns -	1 if button is held down
+ *		0 if button is not held down
+ */
+static int
+do_userbutton(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int button = 0;
+	button = get_button_state("button_dfu0", BOARD_DFU_BUTTON_GPIO);
+	button |= get_button_state("button_dfu1", BOARD_DFU_BUTTON_GPIO);
+	return button;
+}
+
+U_BOOT_CMD(
+	dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton,
+	"Return the status of the DFU button",
+	""
+);
+#endif
+
+static int
+do_usertestwdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	printf("\n\n\n Go into infinite loop\n\n\n");
+	while (1)
+		;
+	return 0;
+};
+
+U_BOOT_CMD(
+	testwdt, CONFIG_SYS_MAXARGS, 1,	do_usertestwdt,
+	"Sends U-Boot into infinite loop",
+	""
+);
+
+/**
+ * Get led gpios from env and set them.
+ * The led define in environment need to need to be of the form ledN=NN,S0,S1
+ * where N is an unsigned integer from 0 to 9 and S0 and S1 is 0 or 1. S0
+ * defines the startup state of the led, S1 the special state of the led when
+ * it enters e.g. dfu mode.
+ */
+void set_env_gpios(unsigned char state)
+{
+	char *ptr_env;
+	char str_tmp[5];	/* must contain "ledX"*/
+	unsigned char i, idx, pos1, pos2, ccount;
+	unsigned char gpio_n, gpio_s0, gpio_s1;
+
+	for (i = 0; i < MAX_NR_LEDS; i++) {
+		sprintf(str_tmp, "led%d", i);
+
+		/* If env var is not found we stop */
+		ptr_env = env_get(str_tmp);
+		if (NULL == ptr_env)
+			break;
+
+		/* Find sperators position */
+		pos1 = 0;
+		pos2 = 0;
+		ccount = 0;
+		for (idx = 0; ptr_env[idx] != '\0'; idx++) {
+			if (ptr_env[idx] == ',') {
+				if (ccount++ < 1)
+					pos1 = idx;
+				else
+					pos2 = idx;
+			}
+		}
+		/* Bad led description skip this definition */
+		if (pos2 <= pos1 || ccount > 2)
+			continue;
+
+		/* Get pin number and request gpio */
+		memset(str_tmp, 0, sizeof(str_tmp));
+		strncpy(str_tmp, ptr_env, pos1*sizeof(char));
+		gpio_n = (unsigned char)simple_strtoul(str_tmp, NULL, 0);
+
+		/* Invalid gpio number skip definition */
+		if (gpio_n > MAX_PIN_NUMBER)
+			continue;
+
+		gpio_request(gpio_n, "");
+
+		if (state == STARTUP) {
+			/* get pin state 0 and set */
+			memset(str_tmp, 0, sizeof(str_tmp));
+			strncpy(str_tmp, ptr_env+pos1+1,
+				(pos2-pos1-1)*sizeof(char));
+			gpio_s0 = (unsigned char)simple_strtoul(str_tmp, NULL,
+								0);
+
+			gpio_direction_output(gpio_n, gpio_s0);
+
+		} else {
+			/* get pin state 1 and set */
+			memset(str_tmp, 0, sizeof(str_tmp));
+			strcpy(str_tmp, ptr_env+pos2+1);
+			gpio_s1 = (unsigned char)simple_strtoul(str_tmp, NULL,
+								0);
+			gpio_direction_output(gpio_n, gpio_s1);
+		}
+	} /* loop through defined led in environment */
+}
+
+static int do_board_led(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;
+	if ((unsigned char)simple_strtoul(argv[1], NULL, 0) == STARTUP)
+		set_env_gpios(0);
+	else
+		set_env_gpios(1);
+	return 0;
+};
+
+U_BOOT_CMD(
+	draco_led, CONFIG_SYS_MAXARGS, 2,	do_board_led,
+	"Set LEDs defined in environment",
+	"<0|1>"
+);
+#endif /* !CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/siemens/common/factoryset.c b/roms/u-boot/board/siemens/common/factoryset.c
new file mode 100644
index 000000000..2e3ae1a54
--- /dev/null
+++ b/roms/u-boot/board/siemens/common/factoryset.c
@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Read FactorySet information from EEPROM into global structure.
+ * (C) Copyright 2013 Siemens Schweiz AG
+ */
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#include <common.h>
+#include <env.h>
+#include <dm.h>
+#include <env_internal.h>
+#include <i2c.h>
+#include <log.h>
+#include <asm/io.h>
+#if !CONFIG_IS_ENABLED(TARGET_GIEDI) && !CONFIG_IS_ENABLED(TARGET_DENEB)
+#include <asm/arch/cpu.h>
+#endif
+#include <asm/arch/sys_proto.h>
+#include <asm/unaligned.h>
+#include <net.h>
+#include <errno.h>
+#include <g_dnl.h>
+#include "factoryset.h"
+
+#define EEPR_PG_SZ		0x80
+#define EEPROM_FATORYSET_OFFSET	0x400
+#define OFF_PG            EEPROM_FATORYSET_OFFSET/EEPR_PG_SZ
+
+/* Global variable that contains necessary information from FactorySet */
+struct factorysetcontainer factory_dat;
+
+#define fact_get_char(i) *((char *)&eeprom_buf[i])
+
+static int fact_match(unsigned char *eeprom_buf, uchar *s1, int i2)
+{
+	if (s1 == NULL)
+		return -1;
+
+	while (*s1 == fact_get_char(i2++))
+		if (*s1++ == '=')
+			return i2;
+
+	if (*s1 == '\0' && fact_get_char(i2-1) == '=')
+		return i2;
+
+	return -1;
+}
+
+static int get_factory_val(unsigned char *eeprom_buf, int size, uchar *name,
+			uchar *buf, int len)
+{
+	int i, nxt = 0;
+
+	for (i = 0; fact_get_char(i) != '\0'; i = nxt + 1) {
+		int val, n;
+
+		for (nxt = i; fact_get_char(nxt) != '\0'; ++nxt) {
+			if (nxt >= size)
+				return -1;
+		}
+
+		val = fact_match(eeprom_buf, (uchar *)name, i);
+		if (val < 0)
+			continue;
+
+		/* found; copy out */
+		for (n = 0; n < len; ++n, ++buf) {
+			*buf = fact_get_char(val++);
+			if (*buf == '\0')
+				return n;
+		}
+
+		if (n)
+			*--buf = '\0';
+
+		printf("env_buf [%d bytes] too small for value of \"%s\"\n",
+		       len, name);
+
+		return n;
+	}
+	return -1;
+}
+
+static
+int get_factory_record_val(unsigned char *eeprom_buf, int size,	uchar *record,
+	uchar *name, uchar *buf, int len)
+{
+	int ret = -1;
+	int i, nxt = 0;
+	int c;
+	unsigned char end = 0xff;
+	unsigned char tmp;
+
+	for (i = 0; fact_get_char(i) != end; i = nxt) {
+		nxt = i + 1;
+		if (fact_get_char(i) == '>') {
+			int pos;
+			int endpos;
+			int z;
+			int level = 0;
+
+			c = strncmp((char *)&eeprom_buf[i + 1], (char *)record,
+				    strlen((char *)record));
+			if (c == 0) {
+				/* record found */
+				pos = i + strlen((char *)record) + 2;
+				nxt = pos;
+				/* search for "<" */
+				c = -1;
+				for (z = pos; fact_get_char(z) != end; z++) {
+					if (fact_get_char(z) == '<') {
+						if (level == 0) {
+							endpos = z;
+							nxt = endpos;
+							c = 0;
+							break;
+						} else {
+							level--;
+						}
+					}
+					if (fact_get_char(z) == '>')
+						level++;
+				}
+			} else {
+				continue;
+			}
+			if (c == 0) {
+				/* end found -> call get_factory_val */
+				tmp = eeprom_buf[endpos];
+				eeprom_buf[endpos] = end;
+				ret = get_factory_val(&eeprom_buf[pos],
+					endpos - pos, name, buf, len);
+				/* fix buffer */
+				eeprom_buf[endpos] = tmp;
+				debug("%s: %s.%s = %s\n",
+				      __func__, record, name, buf);
+				return ret;
+			}
+		}
+	}
+	return ret;
+}
+
+int factoryset_read_eeprom(int i2c_addr)
+{
+	int i, pages = 0, size = 0;
+	unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH];
+	unsigned char *cp, *cp1;
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *bus, *dev;
+	int ret;
+#endif
+
+#if defined(CONFIG_DFU_OVER_USB)
+	factory_dat.usb_vendor_id = CONFIG_USB_GADGET_VENDOR_NUM;
+	factory_dat.usb_product_id = CONFIG_USB_GADGET_PRODUCT_NUM;
+#endif
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	ret = uclass_get_device_by_seq(UCLASS_I2C, EEPROM_I2C_BUS, &bus);
+	if (ret)
+		goto err;
+
+	ret = dm_i2c_probe(bus, i2c_addr, 0, &dev);
+	if (ret)
+		goto err;
+
+	ret = i2c_set_chip_offset_len(dev, 2);
+	if (ret)
+		goto err;
+
+	ret = dm_i2c_read(dev, EEPROM_FATORYSET_OFFSET, hdr, sizeof(hdr));
+	if (ret)
+		goto err;
+#else
+	if (i2c_probe(i2c_addr))
+		goto err;
+
+	if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr)))
+		goto err;
+#endif
+
+	if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) {
+		printf("FactorySet is not right in eeprom.\n");
+		return 1;
+	}
+
+	/* get FactorySet size */
+	size = (hdr[2] << 8) + hdr[3] + sizeof(hdr);
+	if (size > 0x3bfa)
+		size = 0x3bfa;
+
+	pages = size / EEPR_PG_SZ;
+
+	/*
+	 * read the eeprom using i2c
+	 * I can not read entire eeprom in once, so separate into several
+	 * times. Furthermore, fetch eeprom take longer time, so we fetch
+	 * data after every time we got a record from eeprom
+	 */
+	debug("Read eeprom page :\n");
+	for (i = 0; i < pages; i++) {
+#if CONFIG_IS_ENABLED(DM_I2C)
+		ret = dm_i2c_read(dev, (OFF_PG + i) * EEPR_PG_SZ,
+				  eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ);
+		if (ret)
+			goto err;
+#else
+		if (i2c_read(i2c_addr, (OFF_PG + i) * EEPR_PG_SZ, 2,
+			     eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ))
+			goto err;
+#endif
+	}
+
+	if (size % EEPR_PG_SZ) {
+#if CONFIG_IS_ENABLED(DM_I2C)
+		ret = dm_i2c_read(dev, (OFF_PG + pages) * EEPR_PG_SZ,
+				  eeprom_buf + (pages * EEPR_PG_SZ),
+				  size % EEPR_PG_SZ);
+		if (ret)
+			goto err;
+#else
+		if (i2c_read(i2c_addr, (OFF_PG + pages) * EEPR_PG_SZ, 2,
+			     eeprom_buf + (pages * EEPR_PG_SZ),
+			     (size % EEPR_PG_SZ)))
+			goto err;
+#endif
+	}
+
+	/* we do below just for eeprom align */
+	for (i = 0; i < size; i++)
+		if (eeprom_buf[i] == '\n')
+			eeprom_buf[i] = 0;
+
+	/* skip header */
+	size -= sizeof(hdr);
+	cp = (uchar *)eeprom_buf + sizeof(hdr);
+
+	/* get mac address */
+	get_factory_record_val(cp, size, (uchar *)"ETH1", (uchar *)"mac",
+			       buf, MAX_STRING_LENGTH);
+	cp1 = buf;
+	for (i = 0; i < 6; i++) {
+		factory_dat.mac[i] = simple_strtoul((char *)cp1, NULL, 16);
+		cp1 += 3;
+	}
+
+#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB)
+	/* get mac address for WLAN */
+	ret = get_factory_record_val(cp, size, (uchar *)"WLAN1", (uchar *)"mac",
+				     buf, MAX_STRING_LENGTH);
+	if (ret > 0) {
+		cp1 = buf;
+		for (i = 0; i < 6; i++) {
+			factory_dat.mac_wlan[i] = simple_strtoul((char *)cp1,
+								 NULL, 16);
+			cp1 += 3;
+		}
+	}
+#endif
+
+#if defined(CONFIG_DFU_OVER_USB)
+	/* read vid and pid for dfu mode */
+	if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1",
+					(uchar *)"vid", buf,
+					MAX_STRING_LENGTH)) {
+		factory_dat.usb_vendor_id = simple_strtoul((char *)buf,
+							   NULL, 16);
+	}
+
+	if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1",
+					(uchar *)"pid", buf,
+					MAX_STRING_LENGTH)) {
+		factory_dat.usb_product_id = simple_strtoul((char *)buf,
+							    NULL, 16);
+	}
+	printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id,
+	       factory_dat.usb_product_id);
+#endif
+#if defined(CONFIG_VIDEO)
+	if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1",
+					(uchar *)"name", factory_dat.disp_name,
+					MAX_STRING_LENGTH)) {
+		debug("display name: %s\n", factory_dat.disp_name);
+	}
+#endif
+	if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+					(uchar *)"num", factory_dat.serial,
+					MAX_STRING_LENGTH)) {
+		debug("serial number: %s\n", factory_dat.serial);
+	}
+	if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+					(uchar *)"ver", buf,
+					MAX_STRING_LENGTH)) {
+		factory_dat.version = simple_strtoul((char *)buf,
+							    NULL, 16);
+		debug("version number: %d\n", factory_dat.version);
+	}
+	/* Get ASN from factory set if available */
+	if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+					(uchar *)"id", factory_dat.asn,
+					MAX_STRING_LENGTH)) {
+		debug("factoryset asn: %s\n", factory_dat.asn);
+	} else {
+		factory_dat.asn[0] = 0;
+	}
+	/* Get COMP/ver from factory set if available */
+	if (0 <= get_factory_record_val(cp, size, (uchar *)"COMP",
+					(uchar *)"ver",
+					factory_dat.comp_version,
+					MAX_STRING_LENGTH)) {
+		debug("factoryset COMP/ver: %s\n", factory_dat.comp_version);
+	} else {
+		strcpy((char *)factory_dat.comp_version, "1.0");
+	}
+
+	return 0;
+
+err:
+	printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
+	return 1;
+}
+
+static int get_mac_from_efuse(uint8_t mac[6])
+{
+#ifdef CONFIG_AM33XX
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+	uint32_t mac_hi, mac_lo;
+
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+
+	mac[0] = mac_hi & 0xFF;
+	mac[1] = (mac_hi & 0xFF00) >> 8;
+	mac[2] = (mac_hi & 0xFF0000) >> 16;
+	mac[3] = (mac_hi & 0xFF000000) >> 24;
+	mac[4] = mac_lo & 0xFF;
+	mac[5] = (mac_lo & 0xFF00) >> 8;
+#else
+	/* unhandled */
+	memset(mac, 0, 6);
+#endif
+	if (!is_valid_ethaddr(mac)) {
+		puts("Warning: ethaddr not set by FactorySet or E-fuse. ");
+		puts("Set <ethaddr> variable to overcome this.\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int factoryset_mac_env_set(void)
+{
+	uint8_t mac_addr[6];
+
+	/* Set mac from factoryset or try reading E-fuse */
+	debug("FactorySet: Set mac address\n");
+	if (is_valid_ethaddr(factory_dat.mac)) {
+		memcpy(mac_addr, factory_dat.mac, 6);
+	} else {
+		debug("Warning: FactorySet: <ethaddr> not set. Fallback to E-fuse\n");
+		if (get_mac_from_efuse(mac_addr) < 0)
+			return -1;
+	}
+
+	eth_env_set_enetaddr("ethaddr", mac_addr);
+
+#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB)
+	eth_env_set_enetaddr("eth1addr", mac_addr);
+
+	/* wlan mac */
+	if (is_valid_ethaddr(factory_dat.mac_wlan))
+		eth_env_set_enetaddr("eth2addr", factory_dat.mac_wlan);
+#endif
+	return 0;
+}
+
+static void factoryset_dtb_env_set(void)
+{
+	/* Set ASN in environment*/
+	if (factory_dat.asn[0] != 0) {
+		env_set("dtb_name", (char *)factory_dat.asn);
+	} else {
+		/* dtb suffix gets added in load script */
+		env_set("dtb_name", "default");
+	}
+}
+
+int factoryset_env_set(void)
+{
+	int ret = 0;
+
+	factoryset_dtb_env_set();
+
+	if (factoryset_mac_env_set() < 0)
+		ret = -1;
+
+	return ret;
+}
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor);
+	put_unaligned(factory_dat.usb_product_id, &dev->idProduct);
+	g_dnl_set_serialnumber((char *)factory_dat.serial);
+
+	return 0;
+}
+
+int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+	return factory_dat.version;
+}
+#endif /* defined(CONFIG_SPL_BUILD) */
diff --git a/roms/u-boot/board/siemens/common/factoryset.h b/roms/u-boot/board/siemens/common/factoryset.h
new file mode 100644
index 000000000..261a21768
--- /dev/null
+++ b/roms/u-boot/board/siemens/common/factoryset.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common board functions for siemens AM335X based boards
+ * (C) Copyright 2013 Siemens Schweiz AG
+ */
+
+#ifndef __FACTORYSET_H
+#define __FACTORYSET_H
+
+#define MAX_STRING_LENGTH	32
+
+struct factorysetcontainer {
+	uchar mac[6];
+#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB)
+	uchar mac_wlan[6];
+#endif
+	int usb_vendor_id;
+	int usb_product_id;
+	int pxm50;
+#if defined(CONFIG_VIDEO)
+	unsigned char disp_name[MAX_STRING_LENGTH];
+#endif
+	unsigned char serial[MAX_STRING_LENGTH];
+	int version;
+	uchar asn[MAX_STRING_LENGTH];
+	uchar comp_version[MAX_STRING_LENGTH];
+};
+
+int factoryset_read_eeprom(int i2c_addr);
+int factoryset_env_set(void);
+extern struct factorysetcontainer factory_dat;
+
+#endif /* __FACTORYSET_H */
diff --git a/roms/u-boot/board/siemens/corvus/Kconfig b/roms/u-boot/board/siemens/corvus/Kconfig
new file mode 100644
index 000000000..69fe0f072
--- /dev/null
+++ b/roms/u-boot/board/siemens/corvus/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CORVUS
+
+config SYS_BOARD
+	default "corvus"
+
+config SYS_VENDOR
+	default "siemens"
+
+config SYS_CONFIG_NAME
+	default "corvus"
+
+endif
diff --git a/roms/u-boot/board/siemens/corvus/MAINTAINERS b/roms/u-boot/board/siemens/corvus/MAINTAINERS
new file mode 100644
index 000000000..59176aae5
--- /dev/null
+++ b/roms/u-boot/board/siemens/corvus/MAINTAINERS
@@ -0,0 +1,6 @@
+CORVUS BOARD
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	board/siemens/corvus/
+F:	include/configs/corvus.h
+F:	configs/corvus_defconfig
diff --git a/roms/u-boot/board/siemens/corvus/Makefile b/roms/u-boot/board/siemens/corvus/Makefile
new file mode 100644
index 000000000..c67acc613
--- /dev/null
+++ b/roms/u-boot/board/siemens/corvus/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile for siemens CORVUS (AT91SAM9G45) based board
+# (C) Copyright 2013 Siemens AG
+#
+# Based on:
+# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+
+obj-y += board.o
diff --git a/roms/u-boot/board/siemens/corvus/board.c b/roms/u-boot/board/siemens/corvus/board.c
new file mode 100644
index 000000000..a6e1737be
--- /dev/null
+++ b/roms/u-boot/board/siemens/corvus/board.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for Siemens CORVUS (AT91SAM9G45) based board
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_serial.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <asm/arch/clk.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#ifndef CONFIG_DM_ETH
+#include <netdev.h>
+#endif
+#include <spi.h>
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+#include <asm/arch/atmel_usba_udc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void corvus_request_gpio(void)
+{
+	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
+	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+	gpio_request(AT91_PIN_PD7, "d0");
+	gpio_request(AT91_PIN_PD8, "d1");
+	gpio_request(AT91_PIN_PA12, "d2");
+	gpio_request(AT91_PIN_PA13, "d3");
+	gpio_request(AT91_PIN_PA15, "d4");
+	gpio_request(AT91_PIN_PB7, "recovery button");
+	gpio_request(AT91_PIN_PD1, "USB0");
+	gpio_request(AT91_PIN_PD3, "USB1");
+	gpio_request(AT91_PIN_PB18, "SPICS1");
+	gpio_request(AT91_PIN_PB3, "SPICS0");
+	gpio_request(CONFIG_RED_LED, "red led");
+	gpio_request(CONFIG_GREEN_LED, "green led");
+}
+
+static void corvus_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void spl_board_init(void)
+{
+	corvus_request_gpio();
+	/*
+	 * For on the sam9m10g45ek board, the chip wm9711 stay in the test
+	 * mode, so it need do some action to exit mode.
+	 */
+	at91_set_gpio_output(AT91_PIN_PD7, 0);
+	at91_set_gpio_output(AT91_PIN_PD8, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+
+	corvus_nand_hw_init();
+
+	/* Configure recovery button PINs */
+	at91_set_gpio_input(AT91_PIN_PB7, 1);
+
+	/* check if button is pressed */
+	if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
+		u32 boot_device;
+
+		debug("Recovery button pressed\n");
+		boot_device = spl_boot_device();
+		switch (boot_device) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+		case BOOT_DEVICE_NAND:
+			nand_init();
+			spl_nand_erase_one(0, 0);
+			break;
+#endif
+		}
+	}
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_DIC_DS |
+		    ATMEL_MPDDRC_CR_DQMS_SHARED |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+	ddr2->rtr = 0x24b;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddrc_config ddr2;
+
+	ddr2_conf(&ddr2);
+
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void taurus_usb_hw_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+
+	at91_set_gpio_output(AT91_PIN_PD1, 0);
+	at91_set_gpio_output(AT91_PIN_PD3, 0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void corvus_macb_hw_init(void)
+{
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *      RXDV (PA15) => PHY normal mode (not Test mode)
+	 *      ERX0 (PA12) => PHY ADDR0
+	 *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
+
+	at91_phy_reset();
+
+	/* Re-enable pull-up */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+
+	/* And the pins. */
+	at91_macb_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+	corvus_request_gpio();
+	return 0;
+}
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+/* from ./arch/arm/mach-at91/armv7/sama5d3_devices.c */
+void at91_udp_hw_init(void)
+{
+	/* Enable UPLL clock */
+	at91_upll_clk_enable();
+
+	/* Enable UDPHS clock */
+	at91_periph_clk_enable(ATMEL_ID_UDPHS);
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* we have to request the gpios again after relocation */
+	corvus_request_gpio();
+#ifdef CONFIG_CMD_NAND
+	corvus_nand_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 4);
+#endif
+#ifdef CONFIG_MACB
+	corvus_macb_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	taurus_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+	usba_udc_probe(&pdata);
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifndef CONFIG_DM_ETH
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+#endif
+
+/* SPI chip select control */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+			at91_set_gpio_output(AT91_PIN_PB18, 0);
+			break;
+	case 0:
+	default:
+			at91_set_gpio_output(AT91_PIN_PB3, 0);
+			break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+			at91_set_gpio_output(AT91_PIN_PB18, 1);
+			break;
+	case 0:
+	default:
+			at91_set_gpio_output(AT91_PIN_PB3, 1);
+			break;
+	}
+}
+
+static struct atmel_serial_plat at91sam9260_serial_plat = {
+	.base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DRVINFO(at91sam9260_serial) = {
+	.name	= "serial_atmel",
+	.plat = &at91sam9260_serial_plat,
+};
diff --git a/roms/u-boot/board/siemens/draco/Kconfig b/roms/u-boot/board/siemens/draco/Kconfig
new file mode 100644
index 000000000..a699c7d46
--- /dev/null
+++ b/roms/u-boot/board/siemens/draco/Kconfig
@@ -0,0 +1,63 @@
+if TARGET_DRACO
+
+config SYS_BOARD
+	default "draco"
+
+config SYS_VENDOR
+	default "siemens"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "draco"
+
+endif
+
+if TARGET_THUBAN
+
+config SYS_BOARD
+	default "draco"
+
+config SYS_VENDOR
+	default "siemens"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "thuban"
+
+endif
+
+if TARGET_RASTABAN
+
+config SYS_BOARD
+	default "draco"
+
+config SYS_VENDOR
+	default "siemens"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "rastaban"
+
+endif
+
+if TARGET_ETAMIN
+
+config SYS_BOARD
+        default "draco"
+
+config SYS_VENDOR
+        default "siemens"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "etamin"
+
+endif
diff --git a/roms/u-boot/board/siemens/draco/MAINTAINERS b/roms/u-boot/board/siemens/draco/MAINTAINERS
new file mode 100644
index 000000000..c73f18c00
--- /dev/null
+++ b/roms/u-boot/board/siemens/draco/MAINTAINERS
@@ -0,0 +1,11 @@
+DRACO BOARD
+M:	Samuel Egli <samuel.egli@siemens.com>
+S:	Maintained
+F:	board/siemens/draco/
+F:	include/configs/draco.h
+F:	configs/draco_defconfig
+F:	configs/etamin_defconfig
+F:	include/configs/thuban.h
+F:	configs/thuban_defconfig
+F:	include/configs/rastaban.h
+F:	configs/rastaban_defconfig
diff --git a/roms/u-boot/board/siemens/draco/Makefile b/roms/u-boot/board/siemens/draco/Makefile
new file mode 100644
index 000000000..3e3394a86
--- /dev/null
+++ b/roms/u-boot/board/siemens/draco/Makefile
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# (C) Copyright 2013 Siemens Schweiz AG
+# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# Based on:
+# u-boot:/board/ti/am335x/Makefile
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
+ifndef CONFIG_SPL_BUILD
+obj-y += ../common/factoryset.o
+endif
diff --git a/roms/u-boot/board/siemens/draco/board.c b/roms/u-boot/board/siemens/draco/board.c
new file mode 100644
index 000000000..01fdfb5cb
--- /dev/null
+++ b/roms/u-boot/board/siemens/draco/board.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for TI AM335X based draco board
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ *
+ * Board functions for TI AM335X based boards
+ * u-boot:/board/ti/am335x/board.c
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <net.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <watchdog.h>
+#include <linux/delay.h>
+#include "board.h"
+#include "../common/factoryset.h"
+#include <nand.h>
+
+#ifdef CONFIG_SPL_BUILD
+static struct draco_baseboard_id __section(".data") settings;
+
+#if DDR_PLL_FREQ == 303
+#if !defined(CONFIG_TARGET_ETAMIN)
+/* Default@303MHz-i0 */
+const struct ddr3_data ddr3_default = {
+	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
+	0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
+	0x0000093B, 0x0000014A,
+	"default name @303MHz           \0",
+	"default marking                \0",
+};
+#else
+/* etamin board */
+const struct ddr3_data ddr3_default = {
+	0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
+	0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
+	0x0000093B, 0x0000018A,
+	"test-etamin                    \0",
+	"generic-8Gbit                  \0",
+};
+#endif
+#elif DDR_PLL_FREQ == 400
+/* Default@400MHz-i0 */
+const struct ddr3_data ddr3_default = {
+	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
+	0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
+	0x00000618, 0x0000014A,
+	"default name @400MHz           \0",
+	"default marking                \0",
+};
+#endif
+
+static void set_default_ddr3_timings(void)
+{
+	printf("Set default DDR3 settings\n");
+	settings.ddr3 = ddr3_default;
+}
+
+static void print_ddr3_timings(void)
+{
+	printf("\nDDR3\n");
+	printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
+	printf("device:\t\t%s\n", settings.ddr3.manu_name);
+	printf("marking:\t%s\n", settings.ddr3.manu_marking);
+	printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
+	       "default", "diff");
+	PRINTARGS(magic);
+	PRINTARGS(version);
+	PRINTARGS(ddr3_sratio);
+	PRINTARGS(iclkout);
+
+	PRINTARGS(dt0rdsratio0);
+	PRINTARGS(dt0wdsratio0);
+	PRINTARGS(dt0fwsratio0);
+	PRINTARGS(dt0wrsratio0);
+
+	PRINTARGS(sdram_tim1);
+	PRINTARGS(sdram_tim2);
+	PRINTARGS(sdram_tim3);
+
+	PRINTARGS(emif_ddr_phy_ctlr_1);
+
+	PRINTARGS(sdram_config);
+	PRINTARGS(ref_ctrl);
+	PRINTARGS(ioctr_val);
+}
+
+static void print_chip_data(void)
+{
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+	printf("\nCPU BOARD\n");
+	printf("device: \t'%s'\n", settings.chip.sdevname);
+	printf("hw version: \t'%s'\n", settings.chip.shwver);
+	printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+#define AM335X_NAND_ECC_MASK 0x0f
+#define AM335X_NAND_ECC_TYPE_16 0x02
+
+static int ecc_type;
+
+struct am335x_nand_geometry {
+	u32 magic;
+	u8 nand_geo_addr;
+	u8 nand_geo_page;
+	u8 nand_bus;
+};
+
+static int draco_read_nand_geometry(void)
+{
+	struct am335x_nand_geometry geo;
+
+	/* Read NAND geometry */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
+		     (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
+		printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
+		return -EIO;
+	}
+	if (geo.magic != 0xa657b310) {
+		printf("%s: bad magic: %x\n", __func__, geo.magic);
+		return -EFAULT;
+	}
+	if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
+		ecc_type = 16;
+	else
+		ecc_type = 8;
+
+	return 0;
+}
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+	/* Check if baseboard eeprom is available */
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
+		return 1;
+	}
+
+#ifdef CONFIG_SPL_BUILD
+	/* Read Siemens eeprom data (DDR3) */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
+		     (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
+		printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
+		set_default_ddr3_timings();
+	}
+	/* Read Siemens eeprom data (CHIP) */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
+		     (uchar *)&settings.chip, sizeof(settings.chip)))
+		printf("Could not read chip settings\n");
+
+	if (ddr3_default.magic == settings.ddr3.magic &&
+	    ddr3_default.version == settings.ddr3.version) {
+		printf("Using DDR3 settings from EEPROM\n");
+	} else {
+		if (ddr3_default.magic != settings.ddr3.magic)
+			printf("Warning: No valid DDR3 data in eeprom.\n");
+		if (ddr3_default.version != settings.ddr3.version)
+			printf("Warning: DDR3 data version does not match.\n");
+
+		printf("Using default settings\n");
+		set_default_ddr3_timings();
+	}
+
+	if (MAGIC_CHIP == settings.chip.magic)
+		print_chip_data();
+	else
+		printf("Warning: No chip data in eeprom\n");
+
+	print_ddr3_timings();
+
+	return draco_read_nand_geometry();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+static void board_init_ddr(void)
+{
+struct emif_regs draco_ddr3_emif_reg_data = {
+	.zq_config = 0x50074BE4,
+};
+
+struct ddr_data draco_ddr3_data = {
+};
+
+struct cmd_control draco_ddr3_cmd_ctrl_data = {
+};
+
+struct ctrl_ioregs draco_ddr3_ioregs = {
+};
+
+	/* pass values from eeprom */
+	draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
+	draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
+	draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
+	draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
+		settings.ddr3.emif_ddr_phy_ctlr_1;
+	draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
+	draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
+	draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
+
+	draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
+	draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
+	draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
+	draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
+
+	draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
+	draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
+	draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
+	draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
+	draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
+	draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
+
+	draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
+	draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
+	draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
+	draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
+	draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
+
+	config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
+		   &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
+}
+
+static void spl_siemens_board_init(void)
+{
+	return;
+}
+#endif /* if def CONFIG_SPL_BUILD */
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	int ret;
+
+	ret = draco_read_nand_geometry();
+	if (ret != 0)
+		return ret;
+
+	nand_curr_device = 0;
+	omap_nand_switch_ecc(1, ecc_type);
+#ifdef CONFIG_TARGET_ETAMIN
+	nand_curr_device = 1;
+	omap_nand_switch_ecc(1, ecc_type);
+#endif
+#ifdef CONFIG_FACTORYSET
+	/* Set ASN in environment*/
+	if (factory_dat.asn[0] != 0) {
+		env_set("dtb_name", (char *)factory_dat.asn);
+	} else {
+		/* dtb suffix gets added in load script */
+		env_set("dtb_name", "am335x-draco");
+	}
+#else
+	env_set("dtb_name", "am335x-draco");
+#endif
+
+	return 0;
+}
+#endif
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+		.phy_if		= PHY_INTERFACE_MODE_MII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 4,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+	(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
+int board_eth_init(struct bd_info *bis)
+{
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+	int n = 0;
+	int rv;
+
+	factoryset_env_set();
+
+	/* Set rgmii mode and enable rmii clock to be sourced from chip */
+	writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+	return n;
+}
+
+static int do_switch_reset(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	/* Reset SMSC LAN9303 switch for default configuration */
+	gpio_request(GPIO_LAN9303_NRST, "nRST");
+	gpio_direction_output(GPIO_LAN9303_NRST, 0);
+	/* assert active low reset for 200us */
+	udelay(200);
+	gpio_set_value(GPIO_LAN9303_NRST, 1);
+
+	return 0;
+};
+
+U_BOOT_CMD(
+	switch_rst, CONFIG_SYS_MAXARGS, 1,	do_switch_reset,
+	"Reset LAN9303 switch via its reset pin",
+	""
+);
+#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+
+#ifdef CONFIG_NAND_CS_INIT
+/* GPMC definitions for second nand cs1 */
+static const u32 gpmc_nand_config[] = {
+	ETAMIN_NAND_GPMC_CONFIG1,
+	ETAMIN_NAND_GPMC_CONFIG2,
+	ETAMIN_NAND_GPMC_CONFIG3,
+	ETAMIN_NAND_GPMC_CONFIG4,
+	ETAMIN_NAND_GPMC_CONFIG5,
+	ETAMIN_NAND_GPMC_CONFIG6,
+	/*CONFIG7- computed as params */
+};
+
+static void board_nand_cs_init(void)
+{
+	enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
+			      0x18000000, GPMC_SIZE_16M);
+}
+#endif
+
+#include "../common/board.c"
diff --git a/roms/u-boot/board/siemens/draco/board.h b/roms/u-boot/board/siemens/draco/board.h
new file mode 100644
index 000000000..7c29a45c0
--- /dev/null
+++ b/roms/u-boot/board/siemens/draco/board.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ * u-boot:/board/ti/am335x/board.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#define PARGS(x)	#x , /* Parameter Name */ \
+			settings.ddr3.x, /* EEPROM Value */ \
+			ddr3_default.x, /* Default Value */ \
+			settings.ddr3.x-ddr3_default.x /* Difference */
+
+#define PRINTARGS(y)	printf("%-20s, %8x, %8x, %4d\n", PARGS(y))
+
+#define MAGIC_CHIP	0x50494843
+
+/* Automatic generated definition */
+/* Wed, 16 Apr 2014 16:50:41 +0200 */
+/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */
+struct ddr3_data {
+	unsigned int magic;			/* 0x33524444 */
+	unsigned int version;			/* 0x56312e35 */
+	unsigned short int ddr3_sratio;		/* 0x0080 */
+	unsigned short int iclkout;		/* 0x0000 */
+	unsigned short int dt0rdsratio0;	/* 0x003A */
+	unsigned short int dt0wdsratio0;	/* 0x003F */
+	unsigned short int dt0fwsratio0;	/* 0x009F */
+	unsigned short int dt0wrsratio0;	/* 0x0079 */
+	unsigned int sdram_tim1;		/* 0x0888A39B */
+	unsigned int sdram_tim2;		/* 0x26247FDA */
+	unsigned int sdram_tim3;		/* 0x501F821F */
+	unsigned int emif_ddr_phy_ctlr_1;	/* 0x00100206 */
+	unsigned int sdram_config;		/* 0x61A44A32 */
+	unsigned int ref_ctrl;			/* 0x0000093B */
+	unsigned int ioctr_val;			/* 0x0000014A */
+	char manu_name[32];			/* "default@303MHz \0" */
+	char manu_marking[32];			/* "default \0" */
+};
+
+struct chip_data {
+	unsigned int  magic;
+	char sdevname[16];
+	char shwver[7];
+};
+
+struct draco_baseboard_id {
+	struct ddr3_data ddr3;
+	struct chip_data chip;
+};
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+
+/* Forwared declaration, defined in common board.c */
+void set_env_gpios(unsigned char state);
+#endif
diff --git a/roms/u-boot/board/siemens/draco/mux.c b/roms/u-boot/board/siemens/draco/mux.c
new file mode 100644
index 000000000..3f2d41bef
--- /dev/null
+++ b/roms/u-boot/board/siemens/draco/mux.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * pinmux setup for siemens draco board
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/mux.c
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_csn1), MODE(0) | PULLUDEN | PULLUP_EN},    /* NAND_CS1 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+static struct module_pin_mux gpios_pin_mux[] = {
+	/* DFU button GPIO0_27*/
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	{OFFSET(gpmc_csn3), MODE(7) },			/* LED0 GPIO2_0 */
+	{OFFSET(emu0), MODE(7)},			/* LED1 GPIO3_7 */
+	/* Triacs in HW Rev 2 */
+	{OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y5 GPIO0_12*/
+	{OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y3 GPIO2_28*/
+	{OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y7 GPIO2_27*/
+	/* Triacs initial HW Rev */
+	{OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_28 Y1 */
+	{OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_31 Y2 */
+	{OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS},	/* 0_11 Y3 */
+	{OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS},	/* 0_10 Y4 */
+	{OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS},	/* 2_1  Y5 */
+	{OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS},		/* 3_8  Y6 */
+	{OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_15 Y7 */
+	/* Remaining pins that were not used in this file */
+	{OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
+	/* nRST for SMSC LAN9303 switch - GPIO2_24 */
+	{OFFSET(lcd_pclk), MODE(7) | PULLUDEN | PULLUP_EN }, /* LAN9303 nRST */
+	{-1},
+};
+
+static struct module_pin_mux ethernet_pin_mux[] = {
+	{OFFSET(mii1_col), (MODE(3) | RXACTIVE)},
+	{OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
+	{OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
+	{OFFSET(mii1_txen), (MODE(1))},
+	{OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)},
+	{OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_txd1), (MODE(1))},
+	{OFFSET(mii1_txd0), (MODE(1))},
+	{OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)},
+	{OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)},
+	{OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)},
+	{OFFSET(mii1_rxd2), (MODE(1))},
+	{OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
+	{OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
+	{OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
+	{OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+	configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	enable_uart3_pin_mux();
+	configure_module_pin_mux(nand_pin_mux);
+	configure_module_pin_mux(ethernet_pin_mux);
+	configure_module_pin_mux(gpios_pin_mux);
+}
diff --git a/roms/u-boot/board/siemens/pxm2/Kconfig b/roms/u-boot/board/siemens/pxm2/Kconfig
new file mode 100644
index 000000000..62604ecb3
--- /dev/null
+++ b/roms/u-boot/board/siemens/pxm2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PXM2
+
+config SYS_BOARD
+	default "pxm2"
+
+config SYS_VENDOR
+	default "siemens"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "pxm2"
+
+endif
diff --git a/roms/u-boot/board/siemens/pxm2/MAINTAINERS b/roms/u-boot/board/siemens/pxm2/MAINTAINERS
new file mode 100644
index 000000000..dc02fe87c
--- /dev/null
+++ b/roms/u-boot/board/siemens/pxm2/MAINTAINERS
@@ -0,0 +1,6 @@
+PXM2 BOARD
+M:	Samuel Egli <samuel.egli@siemens.com>
+S:	Maintained
+F:	board/siemens/pxm2/
+F:	include/configs/pxm2.h
+F:	configs/pxm2_defconfig
diff --git a/roms/u-boot/board/siemens/pxm2/Makefile b/roms/u-boot/board/siemens/pxm2/Makefile
new file mode 100644
index 000000000..3e3394a86
--- /dev/null
+++ b/roms/u-boot/board/siemens/pxm2/Makefile
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# (C) Copyright 2013 Siemens Schweiz AG
+# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# Based on:
+# u-boot:/board/ti/am335x/Makefile
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
+ifndef CONFIG_SPL_BUILD
+obj-y += ../common/factoryset.o
+endif
diff --git a/roms/u-boot/board/siemens/pxm2/board.c b/roms/u-boot/board/siemens/pxm2/board.c
new file mode 100644
index 000000000..b5e9b4242
--- /dev/null
+++ b/roms/u-boot/board/siemens/pxm2/board.c
@@ -0,0 +1,467 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for TI AM335X based pxm2 board
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <log.h>
+#include <malloc.h>
+#include <net.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include "../../../drivers/video/da8xx-fb.h"
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <watchdog.h>
+#include "board.h"
+#include "../common/factoryset.h"
+#include "pmic.h"
+#include <nand.h>
+#include <bmp_layout.h>
+
+#ifdef CONFIG_SPL_BUILD
+static void board_init_ddr(void)
+{
+struct emif_regs pxm2_ddr3_emif_reg_data = {
+	.sdram_config = 0x41805332,
+	.sdram_tim1 = 0x666b3c9,
+	.sdram_tim2 = 0x243631ca,
+	.sdram_tim3 = 0x33f,
+	.emif_ddr_phy_ctlr_1 = 0x100005,
+	.zq_config = 0,
+	.ref_ctrl = 0x81a,
+};
+
+struct ddr_data pxm2_ddr3_data = {
+	.datardsratio0 = 0x81204812,
+	.datawdsratio0 = 0,
+	.datafwsratio0 = 0x8020080,
+	.datawrsratio0 = 0x4010040,
+};
+
+struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
+	.cmd0csratio = 0x80,
+	.cmd0iclkout = 0,
+	.cmd1csratio = 0x80,
+	.cmd1iclkout = 0,
+	.cmd2csratio = 0x80,
+	.cmd2iclkout = 0,
+};
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= DDR_IOCTRL_VAL,
+	.cm1ioctl		= DDR_IOCTRL_VAL,
+	.cm2ioctl		= DDR_IOCTRL_VAL,
+	.dt0ioctl		= DDR_IOCTRL_VAL,
+	.dt1ioctl		= DDR_IOCTRL_VAL,
+};
+
+	config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
+		   &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
+}
+
+/*
+ * voltage switching for MPU frequency switching.
+ * @module = mpu - 0, core - 1
+ * @vddx_op_vol_sel = vdd voltage to set
+ */
+
+#define MPU	0
+#define CORE	1
+
+int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
+{
+	uchar buf[4];
+	unsigned int reg_offset;
+
+	if (module == MPU)
+		reg_offset = PMIC_VDD1_OP_REG;
+	else
+		reg_offset = PMIC_VDD2_OP_REG;
+
+	/* Select VDDx OP   */
+	if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+		return 1;
+
+	buf[0] &= ~PMIC_OP_REG_CMD_MASK;
+
+	if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+		return 1;
+
+	/* Configure VDDx OP  Voltage */
+	if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+		return 1;
+
+	buf[0] &= ~PMIC_OP_REG_SEL_MASK;
+	buf[0] |= vddx_op_vol_sel;
+
+	if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+		return 1;
+
+	if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+		return 1;
+
+	if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
+		return 1;
+
+	return 0;
+}
+
+#define OSC     (V_OSCK/1000000)
+
+const struct dpll_params dpll_mpu_pxm2 = {
+		720, OSC-1, 1, -1, -1, -1, -1};
+
+void spl_siemens_board_init(void)
+{
+	uchar buf[4];
+	/*
+	 * pxm2 PMIC code.  All boards currently want an MPU voltage
+	 * of 1.2625V and CORE voltage of 1.1375V to operate at
+	 * 720MHz.
+	 */
+	if (i2c_probe(PMIC_CTRL_I2C_ADDR))
+		return;
+
+	/* VDD1/2 voltage selection register access by control i/f */
+	if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
+		return;
+
+	buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
+
+	if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
+		return;
+
+	/* Frequency switching for OPP 120 */
+	if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
+	    voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
+		printf("voltage update failed\n");
+	}
+}
+#endif /* if def CONFIG_SPL_BUILD */
+
+int read_eeprom(void)
+{
+	/* nothing ToDo here for this board */
+
+	return 0;
+}
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+		.phy_if		= PHY_INTERFACE_MODE_RMII,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+		.phy_if		= PHY_INTERFACE_MODE_RMII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 4,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+	(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
+int board_eth_init(struct bd_info *bis)
+{
+	int n = 0;
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+#ifdef CONFIG_FACTORYSET
+	int rv;
+	if (!is_valid_ethaddr(factory_dat.mac))
+		printf("Error: no valid mac address\n");
+	else
+		eth_env_set_enetaddr("ethaddr", factory_dat.mac);
+#endif /* #ifdef CONFIG_FACTORYSET */
+
+	/* Set rgmii mode and enable rmii clock to be sourced from chip */
+	writel(RGMII_MODE_ENABLE  | RGMII_INT_DELAY, &cdev->miisel);
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+#endif
+	return n;
+}
+#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+static struct da8xx_panel lcd_panels[] = {
+	/* AUO G156XW01 V1 */
+	[0] = {
+		.name = "AUO_G156XW01_V1",
+		.width = 1376,
+		.height = 768,
+		.hfp = 14,
+		.hbp = 64,
+		.hsw = 56,
+		.vfp = 1,
+		.vbp = 28,
+		.vsw = 3,
+		.pxl_clk = 60000000,
+		.invert_pxl_clk = 0,
+	},
+	/* AUO B101EVN06 V0 */
+	[1] = {
+		.name = "AUO_B101EVN06_V0",
+		.width = 1280,
+		.height = 800,
+		.hfp = 52,
+		.hbp = 84,
+		.hsw = 36,
+		.vfp = 3,
+		.vbp = 14,
+		.vsw = 6,
+		.pxl_clk = 60000000,
+		.invert_pxl_clk = 0,
+	},
+	/*
+	 * Settings from factoryset
+	 * stored in EEPROM
+	 */
+	[2] = {
+		.name = "factoryset",
+		.width = 0,
+		.height = 0,
+		.hfp = 0,
+		.hbp = 0,
+		.hsw = 0,
+		.vfp = 0,
+		.vbp = 0,
+		.vsw = 0,
+		.pxl_clk = 60000000,
+		.invert_pxl_clk = 0,
+	},
+};
+
+static const struct display_panel disp_panel = {
+	WVGA,
+	32,
+	16,
+	COLOR_ACTIVE,
+};
+
+static const struct lcd_ctrl_config lcd_cfg = {
+	&disp_panel,
+	.ac_bias		= 255,
+	.ac_bias_intrpt		= 0,
+	.dma_burst_sz		= 16,
+	.bpp			= 32,
+	.fdd			= 0x80,
+	.tft_alt_mode		= 0,
+	.stn_565_mode		= 0,
+	.mono_8bit_mode		= 0,
+	.invert_line_clock	= 1,
+	.invert_frm_clock	= 1,
+	.sync_edge		= 0,
+	.sync_ctrl		= 1,
+	.raster_order		= 0,
+};
+
+static int set_gpio(int gpio, int state)
+{
+	gpio_request(gpio, "temp");
+	gpio_direction_output(gpio, state);
+	gpio_set_value(gpio, state);
+	gpio_free(gpio);
+	return 0;
+}
+
+static int enable_backlight(void)
+{
+	set_gpio(BOARD_LCD_POWER, 1);
+	set_gpio(BOARD_BACK_LIGHT, 1);
+	set_gpio(BOARD_TOUCH_POWER, 1);
+	return 0;
+}
+
+static int enable_pwm(void)
+{
+	struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
+	struct pwmss_ecap_regs *ecap;
+	int ticks = PWM_TICKS;
+	int duty = PWM_DUTY;
+
+	ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
+	/* enable clock */
+	setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
+	/* TimeStam Counter register */
+	writel(0xdb9, &ecap->tsctr);
+	/* config period */
+	writel(ticks - 1, &ecap->cap3);
+	writel(ticks - 1, &ecap->cap1);
+	setbits_le16(&ecap->ecctl2,
+		     (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
+	/* config duty */
+	writel(duty, &ecap->cap2);
+	writel(duty, &ecap->cap4);
+	/* start */
+	setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
+	return 0;
+}
+
+static struct dpll_regs dpll_lcd_regs = {
+	.cm_clkmode_dpll = CM_WKUP + 0x98,
+	.cm_idlest_dpll = CM_WKUP + 0x48,
+	.cm_clksel_dpll = CM_WKUP + 0x54,
+};
+
+/* no console on this board */
+int board_cfb_skip(void)
+{
+	return 1;
+}
+
+#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
+#define PLL_GET_N(v) (v & 0x7f)
+
+static int get_clk(struct dpll_regs *dpll_regs)
+{
+	unsigned int val;
+	unsigned int m, n;
+	int f = 0;
+
+	val = readl(dpll_regs->cm_clksel_dpll);
+	m = PLL_GET_M(val);
+	n = PLL_GET_N(val);
+	f = (m * V_OSCK) / n;
+
+	return f;
+};
+
+int clk_get(int clk)
+{
+	return get_clk(&dpll_lcd_regs);
+};
+
+static int conf_disp_pll(int m, int n)
+{
+	struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
+	struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+	struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
+
+	u32 *const clk_domains[] = {
+		&cmper->lcdclkctrl,
+		0
+	};
+	u32 *const clk_modules_explicit_en[] = {
+		&cmper->lcdclkctrl,
+		&cmper->lcdcclkstctrl,
+		&cmper->epwmss0clkctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+	writel(0x0, &cmdpll->clklcdcpixelclk);
+
+	do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
+
+	return 0;
+}
+
+static int board_video_init(void)
+{
+	conf_disp_pll(24, 1);
+	if (factory_dat.pxm50)
+		da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
+	else
+		da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
+
+	enable_pwm();
+	enable_backlight();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	int ret;
+
+	omap_nand_switch_ecc(1, 8);
+
+#ifdef CONFIG_FACTORYSET
+	if (factory_dat.asn[0] != 0) {
+		char tmp[2 * MAX_STRING_LENGTH + 2];
+
+		if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
+			factory_dat.pxm50 = 1;
+		else
+			factory_dat.pxm50 = 0;
+		sprintf(tmp, "%s_%s", factory_dat.asn,
+			factory_dat.comp_version);
+		ret = env_set("boardid", tmp);
+		if (ret)
+			printf("error setting board id\n");
+	} else {
+		factory_dat.pxm50 = 1;
+		ret = env_set("boardid", "PXM50_1.0");
+		if (ret)
+			printf("error setting board id\n");
+	}
+	debug("PXM50: %d\n", factory_dat.pxm50);
+#endif
+
+	return 0;
+}
+#endif
+
+#include "../common/board.c"
diff --git a/roms/u-boot/board/siemens/pxm2/board.h b/roms/u-boot/board/siemens/pxm2/board.h
new file mode 100644
index 000000000..af21fc474
--- /dev/null
+++ b/roms/u-boot/board/siemens/pxm2/board.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ * u-boot:/board/ti/am335x/board.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/roms/u-boot/board/siemens/pxm2/mux.c b/roms/u-boot/board/siemens/pxm2/mux.c
new file mode 100644
index 000000000..2f35bb4a7
--- /dev/null
+++ b/roms/u-boot/board/siemens/pxm2/mux.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * pinmux setup for siemens pxm2 board
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_TXD */
+	{-1},
+};
+
+#ifdef CONFIG_MTD_RAW_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */
+	{OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN},	/* MCASP0_AHCLKX */
+	{-1},
+};
+#endif
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+	{OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+#ifndef CONFIG_NO_ETH
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux rgmii2_pin_mux[] = {
+	{OFFSET(gpmc_a0), MODE(2)},			/* RGMII2_TCTL */
+	{OFFSET(gpmc_a1), MODE(2) | RXACTIVE},		/* RGMII2_RCTL */
+	{OFFSET(gpmc_a2), MODE(2)},			/* RGMII2_TD3 */
+	{OFFSET(gpmc_a3), MODE(2)},			/* RGMII2_TD2 */
+	{OFFSET(gpmc_a4), MODE(2)},			/* RGMII2_TD1 */
+	{OFFSET(gpmc_a5), MODE(2)},			/* RGMII2_TD0 */
+	{OFFSET(gpmc_a6), MODE(7)},			/* RGMII2_TCLK */
+	{OFFSET(gpmc_a7), MODE(2) | RXACTIVE},		/* RGMII2_RCLK */
+	{OFFSET(gpmc_a8), MODE(2) | RXACTIVE},		/* RGMII2_RD3 */
+	{OFFSET(gpmc_a9), MODE(7)},			/* RGMII2_RD2 */
+	{OFFSET(gpmc_a10), MODE(2) | RXACTIVE},		/* RGMII2_RD1 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+#endif
+
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)},	/* MMC0_CD */
+	{-1},
+};
+#endif
+
+static struct module_pin_mux lcdc_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD_DAT0 */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD_DAT1 */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD_DAT2 */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD_DAT3 */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD_DAT4 */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD_DAT5 */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD_DAT6 */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD_DAT7 */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD_DAT8 */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD_DAT9 */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD_DAT10 */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD_DAT11 */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD_DAT12 */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD_DAT13 */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD_DAT14 */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD_DAT15 */
+	{OFFSET(gpmc_ad8), (MODE(1))},			/* LCD_DAT16 */
+	{OFFSET(gpmc_ad9), (MODE(1))},		/* LCD_DAT17 */
+	{OFFSET(gpmc_ad10), (MODE(1))},		/* LCD_DAT18 */
+	{OFFSET(gpmc_ad11), (MODE(1))},		/* LCD_DAT19 */
+	{OFFSET(gpmc_ad12), (MODE(1))},		/* LCD_DAT20 */
+	{OFFSET(gpmc_ad13), (MODE(1))},		/* LCD_DAT21 */
+	{OFFSET(gpmc_ad14), (MODE(1))},		/* LCD_DAT22 */
+	{OFFSET(gpmc_ad15), (MODE(1))},		/* LCD_DAT23 */
+	{OFFSET(lcd_vsync), (MODE(0))},		/* LCD_VSYNC */
+	{OFFSET(lcd_hsync), (MODE(0))},		/* LCD_HSYNC */
+	{OFFSET(lcd_pclk), (MODE(0))},		/* LCD_PCLK */
+	{OFFSET(lcd_ac_bias_en), (MODE(0))},	/* LCD_AC_BIAS_EN */
+	{-1},
+};
+
+static struct module_pin_mux ecap0_pin_mux[] = {
+	{OFFSET(ecap0_in_pwm0_out), (MODE(0))},
+	{-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	{OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/
+	{OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */
+	{OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */
+	{-1},
+};
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+	configure_module_pin_mux(i2c1_pin_mux);
+#ifdef CONFIG_MTD_RAW_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#endif
+#ifndef CONFIG_NO_ETH
+	configure_module_pin_mux(rgmii1_pin_mux);
+	configure_module_pin_mux(rgmii2_pin_mux);
+#endif
+#ifdef CONFIG_MMC
+	configure_module_pin_mux(mmc0_pin_mux);
+#endif
+	configure_module_pin_mux(lcdc_pin_mux);
+	configure_module_pin_mux(gpio_pin_mux);
+	configure_module_pin_mux(ecap0_pin_mux);
+}
diff --git a/roms/u-boot/board/siemens/pxm2/pmic.h b/roms/u-boot/board/siemens/pxm2/pmic.h
new file mode 100644
index 000000000..37660460a
--- /dev/null
+++ b/roms/u-boot/board/siemens/pxm2/pmic.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef PMIC_H
+#define PMIC_H
+
+/*
+ * The PMIC on this board is a TPS65910.
+ */
+
+#define PMIC_SR_I2C_ADDR		0x12
+#define PMIC_CTRL_I2C_ADDR		0x2D
+/* PMIC Register offsets */
+#define PMIC_VDD1_REG			0x21
+#define PMIC_VDD1_OP_REG		0x22
+#define PMIC_VDD2_REG			0x24
+#define PMIC_VDD2_OP_REG		0x25
+#define PMIC_DEVCTRL_REG		0x3f
+
+/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
+#define PMIC_VGAIN_SEL_MASK		(0x3 << 6)
+#define PMIC_ILMAX_MASK			(0x1 << 5)
+#define PMIC_TSTEP_MASK			(0x7 << 2)
+#define PMIC_ST_MASK			(0x3)
+
+#define PMIC_REG_VGAIN_SEL_X1		(0x0 << 6)
+#define PMIC_REG_VGAIN_SEL_X1_0		(0x1 << 6)
+#define PMIC_REG_VGAIN_SEL_X3		(0x2 << 6)
+#define PMIC_REG_VGAIN_SEL_X4		(0x3 << 6)
+
+#define PMIC_REG_ILMAX_1_0_A		(0x0 << 5)
+#define PMIC_REG_ILMAX_1_5_A		(0x1 << 5)
+
+#define PMIC_REG_TSTEP_			(0x0 << 2)
+#define PMIC_REG_TSTEP_12_5		(0x1 << 2)
+#define PMIC_REG_TSTEP_9_4		(0x2 << 2)
+#define PMIC_REG_TSTEP_7_5		(0x3 << 2)
+#define PMIC_REG_TSTEP_6_25		(0x4 << 2)
+#define PMIC_REG_TSTEP_4_7		(0x5 << 2)
+#define PMIC_REG_TSTEP_3_12		(0x6 << 2)
+#define PMIC_REG_TSTEP_2_5		(0x7 << 2)
+
+#define PMIC_REG_ST_OFF			(0x0)
+#define PMIC_REG_ST_ON_HI_POW		(0x1)
+#define PMIC_REG_ST_OFF_1		(0x2)
+#define PMIC_REG_ST_ON_LOW_POW		(0x3)
+
+
+/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
+#define PMIC_OP_REG_SEL				(0x7F)
+
+#define PMIC_OP_REG_CMD_MASK			(0x1 << 7)
+#define PMIC_OP_REG_CMD_OP			(0x0 << 7)
+#define PMIC_OP_REG_CMD_SR			(0x1 << 7)
+
+#define PMIC_OP_REG_SEL_MASK			(0x7F)
+#define PMIC_OP_REG_SEL_1_1_3			(0x2E)	/* 1.1375 V */
+#define PMIC_OP_REG_SEL_1_2_6			(0x38)	/* 1.2625 V */
+
+/* Device control register . (DEVCTRL_REG) */
+#define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK	(0x1 << 4)
+#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C	(0x0 << 4)
+#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C	(0x1 << 4)
+
+#endif
diff --git a/roms/u-boot/board/siemens/rut/Kconfig b/roms/u-boot/board/siemens/rut/Kconfig
new file mode 100644
index 000000000..337107766
--- /dev/null
+++ b/roms/u-boot/board/siemens/rut/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_RUT
+
+config SYS_BOARD
+	default "rut"
+
+config SYS_VENDOR
+	default "siemens"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "rut"
+
+endif
diff --git a/roms/u-boot/board/siemens/rut/MAINTAINERS b/roms/u-boot/board/siemens/rut/MAINTAINERS
new file mode 100644
index 000000000..1e9271090
--- /dev/null
+++ b/roms/u-boot/board/siemens/rut/MAINTAINERS
@@ -0,0 +1,6 @@
+RUT BOARD
+M:	Samuel Egli <samuel.egli@siemens.com>
+S:	Maintained
+F:	board/siemens/rut/
+F:	include/configs/rut.h
+F:	configs/rut_defconfig
diff --git a/roms/u-boot/board/siemens/rut/Makefile b/roms/u-boot/board/siemens/rut/Makefile
new file mode 100644
index 000000000..3e3394a86
--- /dev/null
+++ b/roms/u-boot/board/siemens/rut/Makefile
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# (C) Copyright 2013 Siemens Schweiz AG
+# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# Based on:
+# u-boot:/board/ti/am335x/Makefile
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
+ifndef CONFIG_SPL_BUILD
+obj-y += ../common/factoryset.o
+endif
diff --git a/roms/u-boot/board/siemens/rut/board.c b/roms/u-boot/board/siemens/rut/board.c
new file mode 100644
index 000000000..e0f232d3b
--- /dev/null
+++ b/roms/u-boot/board/siemens/rut/board.c
@@ -0,0 +1,495 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for TI AM335X based rut board
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/board.c
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <malloc.h>
+#include <net.h>
+#include <spi.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <video.h>
+#include <watchdog.h>
+#include <linux/delay.h>
+#include "board.h"
+#include "../common/factoryset.h"
+#include "../../../drivers/video/da8xx-fb.h"
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+static void board_init_ddr(void)
+{
+struct emif_regs rut_ddr3_emif_reg_data = {
+	.sdram_config = 0x61C04AB2,
+	.sdram_tim1 = 0x0888A39B,
+	.sdram_tim2 = 0x26337FDA,
+	.sdram_tim3 = 0x501F830F,
+	.emif_ddr_phy_ctlr_1 = 0x6,
+	.zq_config = 0x50074BE4,
+	.ref_ctrl = 0x93B,
+};
+
+struct ddr_data rut_ddr3_data = {
+	.datardsratio0 = 0x3b,
+	.datawdsratio0 = 0x85,
+	.datafwsratio0 = 0x100,
+	.datawrsratio0 = 0xc1,
+};
+
+struct cmd_control rut_ddr3_cmd_ctrl_data = {
+	.cmd0csratio = 0x40,
+	.cmd0iclkout = 1,
+	.cmd1csratio = 0x40,
+	.cmd1iclkout = 1,
+	.cmd2csratio = 0x40,
+	.cmd2iclkout = 1,
+};
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= RUT_IOCTRL_VAL,
+	.cm1ioctl		= RUT_IOCTRL_VAL,
+	.cm2ioctl		= RUT_IOCTRL_VAL,
+	.dt0ioctl		= RUT_IOCTRL_VAL,
+	.dt1ioctl		= RUT_IOCTRL_VAL,
+};
+
+	config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
+		   &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
+}
+
+static int request_and_pulse_reset(int gpio, const char *name)
+{
+	int ret;
+	const int delay_us = 2000; /* 2ms */
+
+	ret = gpio_request(gpio, name);
+	if (ret < 0) {
+		printf("%s: Unable to request %s\n", __func__, name);
+		goto err;
+	}
+
+	ret = gpio_direction_output(gpio, 0);
+	if (ret < 0) {
+		printf("%s: Unable to set %s  as output\n", __func__, name);
+		goto err_free_gpio;
+	}
+
+	udelay(delay_us);
+
+	gpio_set_value(gpio, 1);
+
+	return 0;
+
+err_free_gpio:
+	gpio_free(gpio);
+err:
+	return ret;
+}
+
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#define ETH_PHY_RESET_GPIO		GPIO_TO_PIN(2, 18)
+#define MAXTOUCH_RESET_GPIO		GPIO_TO_PIN(3, 18)
+#define DISPLAY_RESET_GPIO		GPIO_TO_PIN(3, 19)
+
+#define REQUEST_AND_PULSE_RESET(N) \
+		request_and_pulse_reset(N, #N);
+
+static void spl_siemens_board_init(void)
+{
+	REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
+	REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
+	REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
+}
+#endif /* if def CONFIG_SPL_BUILD */
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 1,
+		.phy_if		= PHY_INTERFACE_MODE_RMII,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 0,
+		.phy_if		= PHY_INTERFACE_MODE_RMII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+	(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
+int board_eth_init(struct bd_info *bis)
+{
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+	int n = 0;
+	int rv;
+
+#ifndef CONFIG_SPL_BUILD
+	factoryset_env_set();
+#endif
+
+	/* Set rgmii mode and enable rmii clock to be sourced from chip */
+	writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+	return n;
+}
+#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+
+#if defined(CONFIG_HW_WATCHDOG)
+static bool hw_watchdog_init_done;
+static int  hw_watchdog_trigger_level;
+
+void hw_watchdog_reset(void)
+{
+	if (!hw_watchdog_init_done)
+		return;
+
+	hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
+	gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
+}
+
+void hw_watchdog_init(void)
+{
+	gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
+	gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
+
+	hw_watchdog_reset();
+
+	hw_watchdog_init_done = 1;
+}
+#endif /* defined(CONFIG_HW_WATCHDOG) */
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+static struct da8xx_panel lcd_panels[] = {
+	/* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
+	[0] = {
+		.name   = "KWH043MC17-F01",
+		.width  = 480,
+		.height = 800,
+		.hfp = 50,              /* no spec, "don't care" values */
+		.hbp = 50,
+		.hsw = 50,
+		.vfp = 50,
+		.vbp = 50,
+		.vsw = 50,
+		.pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
+		.invert_pxl_clk = 1,
+	},
+	/* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
+	[1] = {
+		.name   = "KWH043ST20-F01",
+		.width  = 480,
+		.height = 800,
+		.hfp = 50,              /* no spec, "don't care" values */
+		.hbp = 50,
+		.hsw = 50,
+		.vfp = 50,
+		.vbp = 50,
+		.vsw = 50,
+		.pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
+		.invert_pxl_clk = 1,
+	},
+	/* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
+	[2] = {
+		.name   = "MI0430VT-1",
+		.width  = 480,
+		.height = 800,
+		.hfp = 50,              /* no spec, "don't care" values */
+		.hbp = 50,
+		.hsw = 50,
+		.vfp = 50,
+		.vbp = 50,
+		.vsw = 50,
+		.pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
+		.invert_pxl_clk = 1,
+	},
+};
+
+static const struct display_panel disp_panels[] = {
+	[0] = {
+		WVGA,
+		16,	/* RGB 888 */
+		16,
+		COLOR_ACTIVE,
+	},
+	[1] = {
+		WVGA,
+		16,	/* RGB 888 */
+		16,
+		COLOR_ACTIVE,
+	},
+	[2] = {
+		WVGA,
+		24,	/* RGB 888 */
+		16,
+		COLOR_ACTIVE,
+	},
+};
+
+static const struct lcd_ctrl_config lcd_cfgs[] = {
+	[0] = {
+		&disp_panels[0],
+		.ac_bias		= 255,
+		.ac_bias_intrpt		= 0,
+		.dma_burst_sz		= 16,
+		.bpp			= 16,
+		.fdd			= 0x80,
+		.tft_alt_mode		= 0,
+		.stn_565_mode		= 0,
+		.mono_8bit_mode		= 0,
+		.invert_line_clock	= 1,
+		.invert_frm_clock	= 1,
+		.sync_edge		= 0,
+		.sync_ctrl		= 1,
+		.raster_order		= 0,
+	},
+	[1] = {
+		&disp_panels[1],
+		.ac_bias		= 255,
+		.ac_bias_intrpt		= 0,
+		.dma_burst_sz		= 16,
+		.bpp			= 16,
+		.fdd			= 0x80,
+		.tft_alt_mode		= 0,
+		.stn_565_mode		= 0,
+		.mono_8bit_mode		= 0,
+		.invert_line_clock	= 1,
+		.invert_frm_clock	= 1,
+		.sync_edge		= 0,
+		.sync_ctrl		= 1,
+		.raster_order		= 0,
+	},
+	[2] = {
+		&disp_panels[2],
+		.ac_bias		= 255,
+		.ac_bias_intrpt		= 0,
+		.dma_burst_sz		= 16,
+		.bpp			= 24,
+		.fdd			= 0x80,
+		.tft_alt_mode		= 0,
+		.stn_565_mode		= 0,
+		.mono_8bit_mode		= 0,
+		.invert_line_clock	= 1,
+		.invert_frm_clock	= 1,
+		.sync_edge		= 0,
+		.sync_ctrl		= 1,
+		.raster_order		= 0,
+	},
+
+};
+
+/* no console on this board */
+int board_cfb_skip(void)
+{
+	return 1;
+}
+
+#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
+#define PLL_GET_N(v) (v & 0x7f)
+
+static struct dpll_regs dpll_lcd_regs = {
+	.cm_clkmode_dpll = CM_WKUP + 0x98,
+	.cm_idlest_dpll = CM_WKUP + 0x48,
+	.cm_clksel_dpll = CM_WKUP + 0x54,
+};
+
+static int get_clk(struct dpll_regs *dpll_regs)
+{
+	unsigned int val;
+	unsigned int m, n;
+	int f = 0;
+
+	val = readl(dpll_regs->cm_clksel_dpll);
+	m = PLL_GET_M(val);
+	n = PLL_GET_N(val);
+	f = (m * V_OSCK) / n;
+
+	return f;
+};
+
+int clk_get(int clk)
+{
+	return get_clk(&dpll_lcd_regs);
+};
+
+static int conf_disp_pll(int m, int n)
+{
+	struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
+	struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
+#if defined(DISPL_PLL_SPREAD_SPECTRUM)
+	struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
+#endif
+
+	u32 *const clk_domains[] = {
+		&cmper->lcdclkctrl,
+		0
+	};
+	u32 *const clk_modules_explicit_en[] = {
+		&cmper->lcdclkctrl,
+		&cmper->lcdcclkstctrl,
+		&cmper->spi1clkctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+
+	do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
+
+#if defined(DISPL_PLL_SPREAD_SPECTRUM)
+	writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
+	writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
+	writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
+	       &cmwkup->clkmoddplldisp); /* 0x98 */
+#endif
+	return 0;
+}
+
+static int set_gpio(int gpio, int state)
+{
+	gpio_request(gpio, "temp");
+	gpio_direction_output(gpio, state);
+	gpio_set_value(gpio, state);
+	gpio_free(gpio);
+	return 0;
+}
+
+static int enable_lcd(void)
+{
+	unsigned char buf[1];
+
+	set_gpio(BOARD_LCD_RESET, 0);
+	mdelay(1);
+	set_gpio(BOARD_LCD_RESET, 1);
+	mdelay(1);
+
+	/* spi lcd init */
+	kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
+
+	/* backlight on */
+	buf[0] = 0xf;
+	i2c_write(0x24, 0x7, 1, buf, 1);
+	buf[0] = 0x3f;
+	i2c_write(0x24, 0x8, 1, buf, 1);
+	return 0;
+}
+
+int arch_early_init_r(void)
+{
+	enable_lcd();
+	return 0;
+}
+
+static int board_video_init(void)
+{
+	int i;
+	int anzdisp = ARRAY_SIZE(lcd_panels);
+	int display = 1;
+
+	for (i = 0; i < anzdisp; i++) {
+		if (strncmp((const char *)factory_dat.disp_name,
+			    lcd_panels[i].name,
+		    strlen((const char *)factory_dat.disp_name)) == 0) {
+			printf("DISPLAY: %s\n", factory_dat.disp_name);
+			break;
+		}
+	}
+	if (i == anzdisp) {
+		i = 1;
+		printf("%s: %s not found, using default %s\n", __func__,
+		       factory_dat.disp_name, lcd_panels[i].name);
+	}
+	conf_disp_pll(24, 1);
+	da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
+			 lcd_cfgs[display].bpp);
+
+	return 0;
+}
+#endif /* ifdef CONFIG_VIDEO */
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	int ret;
+	char tmp[2 * MAX_STRING_LENGTH + 2];
+
+	omap_nand_switch_ecc(1, 8);
+
+	if (factory_dat.asn[0] != 0)
+		sprintf(tmp, "%s_%s", factory_dat.asn,
+			factory_dat.comp_version);
+	else
+		strcpy(tmp, "QMX7.E38_4.0");
+
+	ret = env_set("boardid", tmp);
+	if (ret)
+		printf("error setting board id\n");
+
+	return 0;
+}
+#endif
+
+#include "../common/board.c"
diff --git a/roms/u-boot/board/siemens/rut/board.h b/roms/u-boot/board/siemens/rut/board.h
new file mode 100644
index 000000000..af21fc474
--- /dev/null
+++ b/roms/u-boot/board/siemens/rut/board.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ * u-boot:/board/ti/am335x/board.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/roms/u-boot/board/siemens/rut/mux.c b/roms/u-boot/board/siemens/rut/mux.c
new file mode 100644
index 000000000..d80120bbd
--- /dev/null
+++ b/roms/u-boot/board/siemens/rut/mux.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * pinmux setup for siemens rut board
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux ddr_pin_mux[] = {
+	{OFFSET(ddr_resetn), (MODE(0))},
+	{OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_ck), (MODE(0))},
+	{OFFSET(ddr_nck), (MODE(0))},
+	{OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_ba1), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_ba2), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a0), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a1), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a2), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a3), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a4), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a5), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a6), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a7), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a8), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a9), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a10), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a11), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a12), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a13), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a14), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a15), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_odt), (MODE(0))},
+	{OFFSET(ddr_d0), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d1), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d2), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d3), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d4), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d5), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d6), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d7), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d8), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d9), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d10), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d11), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d12), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d13), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d14), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d15), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_dqm0), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_dqm1), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_dqs0), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_dqsn0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(ddr_dqs1), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_dqsn1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(ddr_vref), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ddr_vtp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(gpmc_ad8), (MODE(1))},
+	{OFFSET(gpmc_ad9), (MODE(1))},
+	{OFFSET(gpmc_ad10), (MODE(1))},
+	{OFFSET(gpmc_ad11), (MODE(1))},
+	{OFFSET(gpmc_ad12), (MODE(1))},
+	{OFFSET(gpmc_ad13), (MODE(1))},
+	{OFFSET(gpmc_ad14), (MODE(1))},
+	{OFFSET(gpmc_ad15), (MODE(1))},
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_vsync), (MODE(0))},
+	{OFFSET(lcd_hsync), (MODE(0))},
+	{OFFSET(lcd_pclk), (MODE(0))},
+	{OFFSET(lcd_ac_bias_en), (MODE(0))},
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux mii_pin_mux[] = {
+	{OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
+	{OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
+	{OFFSET(mii1_txen), (MODE(1))},
+	{OFFSET(mii1_txd1), (MODE(1))},
+	{OFFSET(mii1_txd0), (MODE(1))},
+	{OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
+	{OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
+	{OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
+	{OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	{OFFSET(mii1_col), (MODE(7) | RXACTIVE)},
+	{OFFSET(uart1_ctsn), (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(uart1_rtsn), (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(uart1_txd), (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_txclk), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_rxclk), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_rxd3), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_rxd2), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a0), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a1), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a4), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a5), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a6), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a7), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a8), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a10), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a11), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_wpn), (MODE(7) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(gpmc_be1n), (MODE(7) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(gpmc_csn1), (MODE(7) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(gpmc_csn2), (MODE(7) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(gpmc_csn3), (MODE(7) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mcasp0_aclkr), (MODE(7) | RXACTIVE)},
+	{OFFSET(mcasp0_fsr), (MODE(7))},
+	{OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)},
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE)},
+	{OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(xdma_event_intr1), (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+	{OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux usb0_pin_mux[] = {
+	{OFFSET(usb0_dm), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_dp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_ce), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_id), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_drvvbus), (MODE(0))},
+	{-1},
+};
+
+static struct module_pin_mux usb1_pin_mux[] = {
+	{OFFSET(usb1_dm), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb1_dp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb1_ce), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb1_id), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb1_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb1_drvvbus), (MODE(0))},
+	{-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(spi0_cs1), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux spi1_pin_mux[] = {
+	{OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux jtag_pin_mux[] = {
+	{OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(tdo), (MODE(0) | PULLUP_EN)},
+	{OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(ntrst), (MODE(0) | RXACTIVE)},
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUP_EN)},
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUP_EN)},
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)},
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux ainx_pin_mux[] = {
+	{OFFSET(ain7), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain6), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain5), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain4), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain3), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain2), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain1), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain0), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux rtc_pin_mux[] = {
+	{OFFSET(osc1_in), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(osc1_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux gpmc_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(gpmc_clk), (MODE(0) | RXACTIVE)},
+	{-1},
+};
+
+static struct module_pin_mux pmic_pin_mux[] = {
+	{OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux osc_pin_mux[] = {
+	{OFFSET(osc0_in), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(osc0_out), (MODE(0) | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux pwm_pin_mux[] = {
+	{OFFSET(ecap0_in_pwm0_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(gpmc_a2), (MODE(6))},
+	{OFFSET(gpmc_a3), (MODE(6))},
+	{-1},
+};
+
+static struct module_pin_mux emu_pin_mux[] = {
+	{OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux vref_pin_mux[] = {
+	{OFFSET(vrefp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(vrefn), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux misc_pin_mux[] = {
+	{OFFSET(porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)},
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(ddr_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(mii_pin_mux);
+	configure_module_pin_mux(gpio_pin_mux);
+	configure_module_pin_mux(i2c1_pin_mux);
+	configure_module_pin_mux(usb0_pin_mux);
+	configure_module_pin_mux(usb1_pin_mux);
+	configure_module_pin_mux(spi0_pin_mux);
+	configure_module_pin_mux(spi1_pin_mux);
+	configure_module_pin_mux(jtag_pin_mux);
+	configure_module_pin_mux(nand_pin_mux);
+	configure_module_pin_mux(ainx_pin_mux);
+	configure_module_pin_mux(rtc_pin_mux);
+	configure_module_pin_mux(gpmc_pin_mux);
+	configure_module_pin_mux(pmic_pin_mux);
+	configure_module_pin_mux(osc_pin_mux);
+	configure_module_pin_mux(pwm_pin_mux);
+	configure_module_pin_mux(emu_pin_mux);
+	configure_module_pin_mux(vref_pin_mux);
+	configure_module_pin_mux(misc_pin_mux);
+}
diff --git a/roms/u-boot/board/siemens/smartweb/Kconfig b/roms/u-boot/board/siemens/smartweb/Kconfig
new file mode 100644
index 000000000..0871bcc32
--- /dev/null
+++ b/roms/u-boot/board/siemens/smartweb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SMARTWEB
+
+config SYS_BOARD
+	default "smartweb"
+
+config SYS_VENDOR
+	default "siemens"
+
+config SYS_CONFIG_NAME
+	default "smartweb"
+
+endif
diff --git a/roms/u-boot/board/siemens/smartweb/MAINTAINERS b/roms/u-boot/board/siemens/smartweb/MAINTAINERS
new file mode 100644
index 000000000..51298ffb5
--- /dev/null
+++ b/roms/u-boot/board/siemens/smartweb/MAINTAINERS
@@ -0,0 +1,6 @@
+SMARTWEB_HW BOARD
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	board/siemens/smartweb
+F:	include/configs/smartweb.h
+F:	configs/smartweb_defconfig
diff --git a/roms/u-boot/board/siemens/smartweb/Makefile b/roms/u-boot/board/siemens/smartweb/Makefile
new file mode 100644
index 000000000..49cb32491
--- /dev/null
+++ b/roms/u-boot/board/siemens/smartweb/Makefile
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2012
+# Markus Hubig <mhubig@imko.de>
+# IMKO GmbH <www.imko.de>
+#
+# (C) Copyright 2014
+# Heiko Schocher <hs@denx.de>
+# DENX Software Engineering GmbH
+
+obj-y	+= smartweb.o
diff --git a/roms/u-boot/board/siemens/smartweb/smartweb.c b/roms/u-boot/board/siemens/smartweb/smartweb.c
new file mode 100644
index 000000000..d500a6214
--- /dev/null
+++ b/roms/u-boot/board/siemens/smartweb/smartweb.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Achim Ehrlich <aehrlich@taskit.de>
+ * taskit GmbH <www.taskit.de>
+ *
+ * (C) Copyright 2012-
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ * (C) Copyright 2014
+ * Heiko Schocher <hs@denx.de>
+ * DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9_sdramc.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_serial.h>
+#include <asm/arch/at91_spi.h>
+#include <spi.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <watchdog.h>
+# include <net.h>
+#ifndef CONFIG_DM_ETH
+# include <netdev.h>
+#endif
+#include <g_dnl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void smartweb_request_gpio(void)
+{
+	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
+	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+	gpio_request(AT91_PIN_PA26, "ena PHY");
+}
+
+static void smartweb_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+static void smartweb_macb_hw_init(void)
+{
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+	/* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
+	at91_set_gpio_output(AT91_PIN_PA26, 0);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+		pin_to_mask(AT91_PIN_PA15) |
+		pin_to_mask(AT91_PIN_PA17) |
+		pin_to_mask(AT91_PIN_PA25) |
+		pin_to_mask(AT91_PIN_PA26) |
+		pin_to_mask(AT91_PIN_PA28) |
+		pin_to_mask(AT91_PIN_PA29),
+		&pioa->pudr);
+
+	at91_phy_reset();
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+		pin_to_mask(AT91_PIN_PA15) |
+		pin_to_mask(AT91_PIN_PA17) |
+		pin_to_mask(AT91_PIN_PA25) |
+		pin_to_mask(AT91_PIN_PA26) |
+		pin_to_mask(AT91_PIN_PA28) |
+		pin_to_mask(AT91_PIN_PA29),
+		&pioa->puer);
+
+	/* Initialize EMAC=MACB hardware */
+	at91_macb_hw_init();
+}
+
+#ifdef CONFIG_USB_GADGET_AT91
+#include <linux/usb/at91_udc.h>
+
+void at91_udp_hw_init(void)
+{
+	/* Enable PLLB */
+	at91_pllb_clk_enable(get_pllb_init());
+
+	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
+	at91_periph_clk_enable(ATMEL_ID_UDP);
+
+	at91_system_clk_enable(AT91SAM926x_PMC_UDP);
+}
+
+struct at91_udc_data board_udc_data  = {
+	.baseaddr = ATMEL_BASE_UDP0,
+};
+#endif
+
+int board_early_init_f(void)
+{
+	/* enable this here, as we have SPL without serial support */
+	at91_seriald_hw_init();
+	smartweb_request_gpio();
+	return 0;
+}
+
+int board_init(void)
+{
+	smartweb_request_gpio();
+	/* power LED red */
+	at91_set_gpio_output(AT91_PIN_PC6, 0);
+	at91_set_gpio_output(AT91_PIN_PC7, 1);
+	/* alarm LED off */
+	at91_set_gpio_output(AT91_PIN_PC8, 0);
+	at91_set_gpio_output(AT91_PIN_PC9, 0);
+	/* prog LED red */
+	at91_set_gpio_output(AT91_PIN_PC10, 0);
+	at91_set_gpio_output(AT91_PIN_PC11, 1);
+
+#ifdef CONFIG_USB_GADGET_AT91
+	at91_udp_hw_init();
+	at91_udc_probe(&board_udc_data);
+#endif
+
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	smartweb_nand_hw_init();
+	smartweb_macb_hw_init();
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(
+		(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifndef CONFIG_DM_ETH
+#ifdef CONFIG_MACB
+int board_eth_init(struct bd_info *bis)
+{
+	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
+}
+#endif /* CONFIG_MACB */
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+#include <spi_flash.h>
+
+void matrix_init(void)
+{
+	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+	writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
+			| AT91_MATRIX_SLOT_CYCLE_(0x40),
+			&mat->scfg[3]);
+}
+
+void at91_spl_board_init(void)
+{
+	smartweb_request_gpio();
+	/* power LED orange */
+	at91_set_gpio_output(AT91_PIN_PC6, 1);
+	at91_set_gpio_output(AT91_PIN_PC7, 1);
+	/* alarm LED orange */
+	at91_set_gpio_output(AT91_PIN_PC8, 1);
+	at91_set_gpio_output(AT91_PIN_PC9, 1);
+	/* prog LED red */
+	at91_set_gpio_output(AT91_PIN_PC10, 0);
+	at91_set_gpio_output(AT91_PIN_PC11, 1);
+
+	smartweb_nand_hw_init();
+	at91_set_gpio_input(AT91_PIN_PA28, 1);
+	at91_set_gpio_input(AT91_PIN_PA29, 1);
+
+	/* check if both  button are pressed */
+	if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
+		at91_get_gpio_value(AT91_PIN_PA29) == 0) {
+		smartweb_nand_hw_init();
+		nand_init();
+		spl_nand_erase_one(0, 0);
+	}
+}
+
+#define SDRAM_BASE_CONF	(AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \
+			 | AT91_SDRAMC_CAS_2 \
+			 | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
+			 | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \
+			 | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \
+			 | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8))
+
+void mem_init(void)
+{
+	struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC;
+	struct sdramc_reg setting;
+
+	setting.cr = SDRAM_BASE_CONF;
+	setting.mdr = AT91_SDRAMC_MD_SDRAM;
+	setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
+
+	/*
+	 * I write here directly in this register, because this
+	 * approach is smaller than calling at91_set_a_periph() in a
+	 * for loop. This saved me 96 bytes.
+	 */
+	writel(0xffff0000, &port->pdr);
+
+	writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
+	sdramc_initialize(ATMEL_BASE_CS1, &setting);
+}
+#endif
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	g_dnl_set_serialnumber("1");
+	return 0;
+}
diff --git a/roms/u-boot/board/siemens/taurus/Kconfig b/roms/u-boot/board/siemens/taurus/Kconfig
new file mode 100644
index 000000000..28816bc1a
--- /dev/null
+++ b/roms/u-boot/board/siemens/taurus/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_TAURUS
+
+config SYS_BOARD
+	default "taurus"
+
+config SYS_VENDOR
+	default "siemens"
+
+config SYS_CONFIG_NAME
+	default "taurus"
+
+choice
+	prompt "Board Type AXM/TAURUS"
+	default BOARD_AXM
+
+config BOARD_AXM
+	bool "AXM board type"
+	help
+	  Select this, if you want to build for AXM board.
+
+config BOARD_TAURUS
+	bool "TAURUS board type"
+	help
+	  Select this, if you want to build for TAURUS board.
+
+endchoice
+
+endif
diff --git a/roms/u-boot/board/siemens/taurus/MAINTAINERS b/roms/u-boot/board/siemens/taurus/MAINTAINERS
new file mode 100644
index 000000000..74e3518e0
--- /dev/null
+++ b/roms/u-boot/board/siemens/taurus/MAINTAINERS
@@ -0,0 +1,7 @@
+TAURUS BOARD
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	board/siemens/taurus/
+F:	include/configs/taurus.h
+F:	configs/axm_defconfig
+F:	configs/taurus_defconfig
diff --git a/roms/u-boot/board/siemens/taurus/Makefile b/roms/u-boot/board/siemens/taurus/Makefile
new file mode 100644
index 000000000..8c3b1c1c6
--- /dev/null
+++ b/roms/u-boot/board/siemens/taurus/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile for Siemens TAURUS (AT91SAM9G20) based board
+# (C) Copyright 2013 Siemens AG
+#
+# Based on:
+# U-Boot file: board/atmel/at91sam9260ek/Makefile
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+
+obj-y	+= taurus.o
diff --git a/roms/u-boot/board/siemens/taurus/taurus.c b/roms/u-boot/board/siemens/taurus/taurus.c
new file mode 100644
index 000000000..cad16f906
--- /dev/null
+++ b/roms/u-boot/board/siemens/taurus/taurus.c
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for Siemens TAURUS (AT91SAM9G20) based boards
+ * (C) Copyright Siemens AG
+ *
+ * Based on:
+ * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <command.h>
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <flash.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91sam9_sdramc.h>
+#include <asm/arch/atmel_serial.h>
+#include <asm/arch/clk.h>
+#include <asm/gpio.h>
+#include <linux/mtd/rawnand.h>
+#include <atmel_mci.h>
+#include <asm/arch/at91_spi.h>
+#include <spi.h>
+
+#include <net.h>
+#ifndef CONFIG_DM_ETH
+#include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void taurus_request_gpio(void)
+{
+	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
+	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+	gpio_request(AT91_PIN_PA25, "ena PHY");
+}
+
+static void taurus_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+#include <spi_flash.h>
+
+void matrix_init(void)
+{
+	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+	writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
+			| AT91_MATRIX_SLOT_CYCLE_(0x40),
+			&mat->scfg[3]);
+}
+
+#if defined(CONFIG_BOARD_AXM)
+static int at91_is_recovery(void)
+{
+	if ((at91_get_gpio_value(AT91_PIN_PA26) == 0) &&
+	    (at91_get_gpio_value(AT91_PIN_PA27) == 0))
+		return 1;
+
+	return 0;
+}
+#elif defined(CONFIG_BOARD_TAURUS)
+static int at91_is_recovery(void)
+{
+	if (at91_get_gpio_value(AT91_PIN_PA31) == 0)
+		return 1;
+
+	return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+	taurus_nand_hw_init();
+	at91_spi0_hw_init(TAURUS_SPI_MASK);
+
+#if defined(CONFIG_BOARD_AXM)
+	/* Configure LED PINs */
+	at91_set_gpio_output(AT91_PIN_PA6, 0);
+	at91_set_gpio_output(AT91_PIN_PA8, 0);
+	at91_set_gpio_output(AT91_PIN_PA9, 0);
+	at91_set_gpio_output(AT91_PIN_PA10, 0);
+	at91_set_gpio_output(AT91_PIN_PA11, 0);
+	at91_set_gpio_output(AT91_PIN_PA12, 0);
+
+	/* Configure recovery button PINs */
+	at91_set_gpio_input(AT91_PIN_PA26, 1);
+	at91_set_gpio_input(AT91_PIN_PA27, 1);
+#elif defined(CONFIG_BOARD_TAURUS)
+	at91_set_gpio_input(AT91_PIN_PA31, 1);
+#endif
+
+	/* check for recovery mode */
+	if (at91_is_recovery() == 1) {
+		struct spi_flash *flash;
+
+		puts("Recovery button pressed\n");
+		nand_init();
+		spl_nand_erase_one(0, 0);
+		flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
+					0,
+					CONFIG_SF_DEFAULT_SPEED,
+					CONFIG_SF_DEFAULT_MODE);
+		if (!flash) {
+			puts("no flash\n");
+		} else {
+			puts("erase spi flash sector 0\n");
+			spi_flash_erase(flash, 0,
+					CONFIG_SYS_NAND_U_BOOT_SIZE);
+		}
+	}
+}
+
+#define SDRAM_BASE_CONF	(AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_3 \
+			 |AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
+			 | AT91_SDRAMC_TWR_VAL(3) | AT91_SDRAMC_TRC_VAL(9) \
+			 | AT91_SDRAMC_TRP_VAL(3) | AT91_SDRAMC_TRCD_VAL(3) \
+			 | AT91_SDRAMC_TRAS_VAL(6) | AT91_SDRAMC_TXSR_VAL(10))
+
+void sdramc_configure(unsigned int mask)
+{
+	struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct sdramc_reg setting;
+
+	at91_sdram_hw_init();
+	setting.cr = SDRAM_BASE_CONF | mask;
+	setting.mdr = AT91_SDRAMC_MD_SDRAM;
+	setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
+
+	writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
+		AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
+		&ma->ebicsa);
+
+	sdramc_initialize(ATMEL_BASE_CS1, &setting);
+}
+
+void mem_init(void)
+{
+	unsigned int ram_size = 0;
+
+	/* Configure SDRAM for 128MB */
+	sdramc_configure(AT91_SDRAMC_NC_10);
+
+	/* Do memtest for 128MB */
+	ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				CONFIG_SYS_SDRAM_SIZE);
+
+	/*
+	 * If 32MB or 16MB should be supported check also for
+	 * expected mirroring at A16 and A17
+	 * To find mirror addresses depends how the collumns are connected
+	 * at RAM (internaly or externaly)
+	 * If the collumns are not in inverted order the mirror size effect
+	 * behaves like normal SRAM with A0,A1,A2,etc. connected incremantal
+	 */
+
+	/* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/
+	if (ram_size == 0x800) {
+		printf("\n\r 64MB\n");
+		sdramc_configure(AT91_SDRAMC_NC_9);
+	} else {
+		/* Size already initialized */
+		printf("\n\r 128MB\n");
+	}
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void siemens_phy_reset(void)
+{
+	/*
+	 * we need to reset PHY for 200us
+	 * because of bug in ATMEL G20 CPU (undefined initial state of GPIO)
+	 */
+	if ((readl(AT91_ASM_RSTC_SR) & AT91_RSTC_RSTTYP) ==
+	    AT91_RSTC_RSTTYP_GENERAL)
+		at91_set_gpio_value(AT91_PIN_PA25, 0); /* reset eth switch */
+}
+
+static void taurus_macb_hw_init(void)
+{
+	/* Enable EMAC clock */
+	at91_periph_clk_enable(ATMEL_ID_EMAC0);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0);
+
+	siemens_phy_reset();
+
+	at91_phy_reset();
+
+	at91_set_gpio_input(AT91_PIN_PA25, 1);   /* ERST tri-state */
+
+	/* Re-enable pull-up */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1);
+
+	/* Initialize EMAC=MACB hardware */
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(struct bd_info *bd)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	/* Enable clocks for all PIOs */
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+	at91_seriald_hw_init();
+	taurus_request_gpio();
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_GADGET_AT91
+#include <linux/usb/at91_udc.h>
+
+void at91_udp_hw_init(void)
+{
+	/* Enable PLLB */
+	at91_pllb_clk_enable(get_pllb_init());
+
+	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
+	at91_periph_clk_enable(ATMEL_ID_UDP);
+
+	at91_system_clk_enable(AT91SAM926x_PMC_UDP);
+}
+
+struct at91_udc_data board_udc_data  = {
+	.baseaddr = ATMEL_BASE_UDP0,
+};
+#endif
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	taurus_request_gpio();
+#ifdef CONFIG_CMD_NAND
+	taurus_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	taurus_macb_hw_init();
+#endif
+	at91_spi0_hw_init(TAURUS_SPI_MASK);
+#ifdef CONFIG_USB_GADGET_AT91
+	at91_udp_hw_init();
+	at91_udc_probe(&board_udc_data);
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_BOARD_AXM)
+/*
+ * Booting the Fallback Image.
+ *
+ *  The function is used to provide and
+ *  boot the image with the fallback
+ *  parameters, incase if the faulty image
+ *  in upgraded over the base firmware.
+ *
+ */
+static int upgrade_failure_fallback(void)
+{
+	char *partitionset_active = NULL;
+	char *rootfs = NULL;
+	char *rootfs_fallback = NULL;
+	char *kern_off;
+	char *kern_off_fb;
+	char *kern_size;
+	char *kern_size_fb;
+
+	partitionset_active = env_get("partitionset_active");
+	if (partitionset_active) {
+		if (partitionset_active[0] == 'A')
+			env_set("partitionset_active", "B");
+		else
+			env_set("partitionset_active", "A");
+	} else {
+		printf("partitionset_active missing.\n");
+		return -ENOENT;
+	}
+
+	rootfs = env_get("rootfs");
+	rootfs_fallback = env_get("rootfs_fallback");
+	env_set("rootfs", rootfs_fallback);
+	env_set("rootfs_fallback", rootfs);
+
+	kern_size = env_get("kernel_size");
+	kern_size_fb = env_get("kernel_size_fallback");
+	env_set("kernel_size", kern_size_fb);
+	env_set("kernel_size_fallback", kern_size);
+
+	kern_off = env_get("kernel_Off");
+	kern_off_fb = env_get("kernel_Off_fallback");
+	env_set("kernel_Off", kern_off_fb);
+	env_set("kernel_Off_fallback", kern_off);
+
+	env_set("bootargs", '\0');
+	env_set("upgrade_available", '\0');
+	env_set("boot_retries", '\0');
+	env_save();
+
+	return 0;
+}
+
+static int do_upgrade_available(struct cmd_tbl *cmdtp, int flag, int argc,
+				char *const argv[])
+{
+	unsigned long upgrade_available = 0;
+	unsigned long boot_retry = 0;
+	char boot_buf[10];
+
+	upgrade_available = simple_strtoul(env_get("upgrade_available"), NULL,
+					   10);
+	if (upgrade_available) {
+		boot_retry = simple_strtoul(env_get("boot_retries"), NULL, 10);
+		boot_retry++;
+		sprintf(boot_buf, "%lx", boot_retry);
+		env_set("boot_retries", boot_buf);
+		env_save();
+
+		/*
+		 * Here the boot_retries count is checked, and if the
+		 * count becomes greater than 2 switch back to the
+		 * fallback, and reset the board.
+		 */
+
+		if (boot_retry > 2) {
+			if (upgrade_failure_fallback() == 0)
+				do_reset(NULL, 0, 0, NULL);
+			return -1;
+		}
+	}
+	return 0;
+}
+
+U_BOOT_CMD(
+	upgrade_available,	1,	1,	do_upgrade_available,
+	"check Siemens update",
+	"no parameters"
+);
+#endif
+#endif
diff --git a/roms/u-boot/board/sifive/unleashed/Kconfig b/roms/u-boot/board/sifive/unleashed/Kconfig
new file mode 100644
index 000000000..b3b4342a1
--- /dev/null
+++ b/roms/u-boot/board/sifive/unleashed/Kconfig
@@ -0,0 +1,54 @@
+if TARGET_SIFIVE_UNLEASHED
+
+config SYS_BOARD
+	default "unleashed"
+
+config SYS_VENDOR
+	default "sifive"
+
+config SYS_CPU
+	default "fu540"
+
+config SYS_CONFIG_NAME
+	default "sifive-unleashed"
+
+config SYS_TEXT_BASE
+	default 0x80200000 if SPL
+	default 0x80000000 if !RISCV_SMODE
+	default 0x80200000 if RISCV_SMODE
+
+config SPL_TEXT_BASE
+	default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x80000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select SIFIVE_FU540
+	select ENV_IS_IN_SPI_FLASH
+	select BINMAN
+	select RESET_SIFIVE
+	imply CMD_DHCP
+	imply CMD_EXT2
+	imply CMD_EXT4
+	imply CMD_FAT
+	imply CMD_FS_GENERIC
+	imply CMD_GPT
+	imply PARTITION_TYPE_GUID
+	imply CMD_NET
+	imply CMD_PING
+	imply CMD_SF
+	imply DOS_PARTITION
+	imply EFI_PARTITION
+	imply IP_DYN
+	imply ISO_PARTITION
+	imply PHY_LIB
+	imply PHY_MSCC
+	imply SPI_FLASH
+	imply SPI_FLASH_ISSI
+	imply SYSRESET
+	imply SYSRESET_GPIO
+	imply CMD_I2C
+
+endif
diff --git a/roms/u-boot/board/sifive/unleashed/MAINTAINERS b/roms/u-boot/board/sifive/unleashed/MAINTAINERS
new file mode 100644
index 000000000..2ea00749c
--- /dev/null
+++ b/roms/u-boot/board/sifive/unleashed/MAINTAINERS
@@ -0,0 +1,10 @@
+SiFive HiFive Unleashed BOARD
+M:	Paul Walmsley <paul.walmsley@sifive.com>
+M:	Palmer Dabbelt <palmer@dabbelt.com>
+M:	Anup Patel <anup.patel@wdc.com>
+M:	Atish Patra <atish.patra@wdc.com>
+S:	Maintained
+F:	board/sifive/unleashed/
+F:	doc/board/sifive/unleashed.rst
+F:	include/configs/sifive-unleashed.h
+F:	configs/sifive_unleashed_defconfig
diff --git a/roms/u-boot/board/sifive/unleashed/Makefile b/roms/u-boot/board/sifive/unleashed/Makefile
new file mode 100644
index 000000000..5821679dd
--- /dev/null
+++ b/roms/u-boot/board/sifive/unleashed/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+
+obj-y	+= unleashed.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/roms/u-boot/board/sifive/unleashed/spl.c b/roms/u-boot/board/sifive/unleashed/spl.c
new file mode 100644
index 000000000..fe27316b2
--- /dev/null
+++ b/roms/u-boot/board/sifive/unleashed/spl.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <init.h>
+#include <spl.h>
+#include <misc.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
+
+#define GEM_PHY_RESET		SIFIVE_GENERIC_GPIO_NR(0, 12)
+
+#define MODE_SELECT_REG		0x1000
+#define MODE_SELECT_QSPI	0x6
+#define MODE_SELECT_SD		0xb
+#define MODE_SELECT_MASK	GENMASK(3, 0)
+
+int spl_board_init_f(void)
+{
+	int ret;
+
+	ret = spl_soc_init();
+	if (ret) {
+		debug("FU540 SPL init failed: %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * GEMGXL init VSC8541 PHY reset sequence;
+	 * leave pull-down active for 2ms
+	 */
+	udelay(2000);
+	ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
+	if (ret) {
+		debug("gem_phy_reset gpio request failed: %d\n", ret);
+		return ret;
+	}
+
+	/* Set GPIO 12 (PHY NRESET) */
+	ret = gpio_direction_output(GEM_PHY_RESET, 1);
+	if (ret) {
+		debug("gem_phy_reset gpio direction set failed: %d\n", ret);
+		return ret;
+	}
+
+	udelay(1);
+
+	/* Reset PHY again to enter unmanaged mode */
+	gpio_set_value(GEM_PHY_RESET, 0);
+	udelay(1);
+	gpio_set_value(GEM_PHY_RESET, 1);
+	mdelay(15);
+
+	return 0;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 mode_select = readl((void *)MODE_SELECT_REG);
+	u32 boot_device = mode_select & MODE_SELECT_MASK;
+
+	switch (boot_device) {
+	case MODE_SELECT_QSPI:
+		return BOOT_DEVICE_SPI;
+	case MODE_SELECT_SD:
+		return BOOT_DEVICE_MMC1;
+	default:
+		debug("Unsupported boot device 0x%x but trying MMC1\n",
+		      boot_device);
+		return BOOT_DEVICE_MMC1;
+	}
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/sifive/unleashed/unleashed.c b/roms/u-boot/board/sifive/unleashed/unleashed.c
new file mode 100644
index 000000000..a4e78220c
--- /dev/null
+++ b/roms/u-boot/board/sifive/unleashed/unleashed.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <log.h>
+#include <linux/bitops.h>
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include <misc.h>
+#include <spl.h>
+#include <asm/arch/cache.h>
+
+/*
+ * This define is a value used for error/unknown serial.
+ * If we really care about distinguishing errors and 0 is
+ * valid, we'll need a different one.
+ */
+#define ERROR_READING_SERIAL_NUMBER       0
+
+#ifdef CONFIG_MISC_INIT_R
+
+#if CONFIG_IS_ENABLED(SIFIVE_OTP)
+static u32 otp_read_serialnum(struct udevice *dev)
+{
+	int ret;
+	u32 serial[2] = {0};
+
+	for (int i = 0xfe * 4; i > 0; i -= 8) {
+		ret = misc_read(dev, i, serial, sizeof(serial));
+
+		if (ret != sizeof(serial)) {
+			printf("%s: error reading serial from OTP\n", __func__);
+			break;
+		}
+
+		if (serial[0] == ~serial[1])
+			return serial[0];
+	}
+
+	return ERROR_READING_SERIAL_NUMBER;
+}
+#endif
+
+static u32 fu540_read_serialnum(void)
+{
+	u32 serial = ERROR_READING_SERIAL_NUMBER;
+
+#if CONFIG_IS_ENABLED(SIFIVE_OTP)
+	struct udevice *dev;
+	int ret;
+
+	/* init OTP */
+	ret = uclass_get_device_by_driver(UCLASS_MISC,
+					  DM_DRIVER_GET(sifive_otp), &dev);
+
+	if (ret) {
+		debug("%s: could not find otp device\n", __func__);
+		return serial;
+	}
+
+	/* read serial from OTP and set env var */
+	serial = otp_read_serialnum(dev);
+#endif
+
+	return serial;
+}
+
+static void fu540_setup_macaddr(u32 serialnum)
+{
+	/* Default MAC address */
+	unsigned char mac[6] = { 0x70, 0xb3, 0xd5, 0x92, 0xf0, 0x00 };
+
+	/*
+	 * We derive our board MAC address by ORing last three bytes
+	 * of board serial number to above default MAC address.
+	 *
+	 * This logic of deriving board MAC address is taken from
+	 * SiFive FSBL and is kept unchanged.
+	 */
+	mac[5] |= (serialnum >>  0) & 0xff;
+	mac[4] |= (serialnum >>  8) & 0xff;
+	mac[3] |= (serialnum >> 16) & 0xff;
+
+	/* Update environment variable */
+	eth_env_set_enetaddr("ethaddr", mac);
+}
+
+int misc_init_r(void)
+{
+	u32 serial_num;
+	char buf[9] = {0};
+
+	/* Set ethaddr environment variable from board serial number */
+	if (!env_get("serial#")) {
+		serial_num = fu540_read_serialnum();
+		if (!serial_num) {
+			WARN(true, "Board serial number should not be 0 !!\n");
+			return 0;
+		}
+		snprintf(buf, sizeof(buf), "%08x", serial_num);
+		env_set("serial#", buf);
+		fu540_setup_macaddr(serial_num);
+	}
+	return 0;
+}
+
+#endif
+
+int board_init(void)
+{
+	int ret;
+
+	/* enable all cache ways */
+	ret = cache_enable_ways();
+	if (ret) {
+		debug("%s: could not enable cache ways\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/sifive/unmatched/Kconfig b/roms/u-boot/board/sifive/unmatched/Kconfig
new file mode 100644
index 000000000..88b5883ca
--- /dev/null
+++ b/roms/u-boot/board/sifive/unmatched/Kconfig
@@ -0,0 +1,51 @@
+if TARGET_SIFIVE_UNMATCHED
+
+config SYS_BOARD
+	default "unmatched"
+
+config SYS_VENDOR
+	default "sifive"
+
+config SYS_CPU
+	default "fu740"
+
+config SYS_CONFIG_NAME
+	default "sifive-unmatched"
+
+config SYS_TEXT_BASE
+	default 0x80200000 if SPL
+	default 0x80000000 if !RISCV_SMODE
+	default 0x80200000 if RISCV_SMODE
+
+config SPL_TEXT_BASE
+	default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x80000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select SIFIVE_FU740
+	select SUPPORT_SPL
+	select RESET_SIFIVE
+	select BINMAN
+	imply CMD_DHCP
+	imply CMD_EXT2
+	imply CMD_EXT4
+	imply CMD_FAT
+	imply CMD_FS_GENERIC
+	imply CMD_GPT
+	imply PARTITION_TYPE_GUID
+	imply CMD_NET
+	imply CMD_PING
+	imply CMD_SF
+	imply DOS_PARTITION
+	imply EFI_PARTITION
+	imply IP_DYN
+	imply ISO_PARTITION
+	imply PHY_LIB
+	imply PHY_MSCC
+	imply SYSRESET
+	imply SYSRESET_GPIO
+
+endif
diff --git a/roms/u-boot/board/sifive/unmatched/MAINTAINERS b/roms/u-boot/board/sifive/unmatched/MAINTAINERS
new file mode 100644
index 000000000..94c9510bf
--- /dev/null
+++ b/roms/u-boot/board/sifive/unmatched/MAINTAINERS
@@ -0,0 +1,9 @@
+SiFive HiFive Unmatched FU740 BOARD
+M:	Paul Walmsley <paul.walmsley@sifive.com>
+M:	Pragnesh Patel <pragnesh.patel@sifive.com>
+M:	Green Wan <green.wan@sifive.com>
+S:	Maintained
+F:	board/sifive/unmatched/
+F:	doc/board/sifive/hifive-unmatched-fu740.rst
+F:	include/configs/sifive-unmatched.h
+F:	configs/sifive_unmatched_defconfig
diff --git a/roms/u-boot/board/sifive/unmatched/Makefile b/roms/u-boot/board/sifive/unmatched/Makefile
new file mode 100644
index 000000000..6308c80d6
--- /dev/null
+++ b/roms/u-boot/board/sifive/unmatched/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2020-2021 SiFive, Inc
+
+obj-y   += unmatched.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/roms/u-boot/board/sifive/unmatched/spl.c b/roms/u-boot/board/sifive/unmatched/spl.c
new file mode 100644
index 000000000..5e1333b09
--- /dev/null
+++ b/roms/u-boot/board/sifive/unmatched/spl.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020-2021 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <init.h>
+#include <spl.h>
+#include <misc.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
+
+#define GEM_PHY_RESET	SIFIVE_GENERIC_GPIO_NR(0, 12)
+
+#define MODE_SELECT_REG		0x1000
+#define MODE_SELECT_SD		0xb
+#define MODE_SELECT_MASK	GENMASK(3, 0)
+
+int spl_board_init_f(void)
+{
+	int ret;
+
+	ret = spl_soc_init();
+	if (ret) {
+		debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * GEMGXL init VSC8541 PHY reset sequence;
+	 * leave pull-down active for 2ms
+	 */
+	udelay(2000);
+	ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
+	if (ret) {
+		debug("gem_phy_reset gpio request failed: %d\n", ret);
+		return ret;
+	}
+
+	/* Set GPIO 12 (PHY NRESET) */
+	ret = gpio_direction_output(GEM_PHY_RESET, 1);
+	if (ret) {
+		debug("gem_phy_reset gpio direction set failed: %d\n", ret);
+		return ret;
+	}
+
+	udelay(1);
+
+	/* Reset PHY again to enter unmanaged mode */
+	gpio_set_value(GEM_PHY_RESET, 0);
+	udelay(1);
+	gpio_set_value(GEM_PHY_RESET, 1);
+	mdelay(15);
+
+	return 0;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 mode_select = readl((void *)MODE_SELECT_REG);
+	u32 boot_device = mode_select & MODE_SELECT_MASK;
+
+	switch (boot_device) {
+	case MODE_SELECT_SD:
+		return BOOT_DEVICE_MMC1;
+	default:
+		debug("Unsupported boot device 0x%x but trying MMC1\n",
+		      boot_device);
+		return BOOT_DEVICE_MMC1;
+	}
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/sifive/unmatched/unmatched.c b/roms/u-boot/board/sifive/unmatched/unmatched.c
new file mode 100644
index 000000000..6d6055958
--- /dev/null
+++ b/roms/u-boot/board/sifive/unmatched/unmatched.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020-2021, SiFive Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/cache.h>
+
+int board_init(void)
+{
+	int ret;
+
+	/* enable all cache ways */
+	ret = cache_enable_ways();
+	if (ret) {
+		debug("%s: could not enable cache ways\n", __func__);
+		return ret;
+	}
+	return 0;
+}
diff --git a/roms/u-boot/board/silinux/ek874/Kconfig b/roms/u-boot/board/silinux/ek874/Kconfig
new file mode 100644
index 000000000..60b390a12
--- /dev/null
+++ b/roms/u-boot/board/silinux/ek874/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SILINUX_EK874
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "ek874"
+
+config SYS_VENDOR
+	default "silinux"
+
+config SYS_CONFIG_NAME
+	default "silinux-ek874"
+
+endif
diff --git a/roms/u-boot/board/silinux/ek874/MAINTAINERS b/roms/u-boot/board/silinux/ek874/MAINTAINERS
new file mode 100644
index 000000000..57a71b83b
--- /dev/null
+++ b/roms/u-boot/board/silinux/ek874/MAINTAINERS
@@ -0,0 +1,6 @@
+SILINUX_EK874 BOARD
+M:	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+S:	Maintained
+F:	board/silinux/ek874/
+F:	include/configs/silinux-ek874.h
+F:	configs/silinux_ek874_defconfig
diff --git a/roms/u-boot/board/silinux/ek874/Makefile b/roms/u-boot/board/silinux/ek874/Makefile
new file mode 100644
index 000000000..4c8f0925f
--- /dev/null
+++ b/roms/u-boot/board/silinux/ek874/Makefile
@@ -0,0 +1,13 @@
+#
+# board/silinux/ek874/Makefile
+#
+# Copyright (C) 2021 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= ../../renesas/rcar-common/gen3-spl.o
+else
+obj-y	:= ek874.o ../../renesas/rcar-common/common.o
+endif
diff --git a/roms/u-boot/board/silinux/ek874/ek874.c b/roms/u-boot/board/silinux/ek874/ek874.c
new file mode 100644
index 000000000..5a219cd98
--- /dev/null
+++ b/roms/u-boot/board/silinux/ek874/ek874.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/silinux/ek874/ek874.c
+ *     This file is ek874 board support.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+
+#define RST_BASE	0xE6160000
+#define RST_CA53RESCNT	(RST_BASE + 0x44)
+#define RST_CA53_CODE	0x5A5A000F
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	writel(RST_CA53_CODE, RST_CA53RESCNT);
+}
diff --git a/roms/u-boot/board/sipeed/maix/Kconfig b/roms/u-boot/board/sipeed/maix/Kconfig
new file mode 100644
index 000000000..adf6abb57
--- /dev/null
+++ b/roms/u-boot/board/sipeed/maix/Kconfig
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+
+if TARGET_SIPEED_MAIX
+
+config SYS_BOARD
+	default "maix"
+
+config SYS_VENDOR
+	default "sipeed"
+
+config SYS_CPU
+	default "generic"
+
+config SYS_CONFIG_NAME
+	default "sipeed-maix"
+
+config SYS_TEXT_BASE
+	default 0x80000000
+
+config DEFAULT_DEVICE_TREE
+	default "k210-maix-bit"
+
+config NR_CPUS
+	default 2
+
+config NR_DRAM_BANKS
+	default 3
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select GENERIC_RISCV
+	select RISCV_PRIV_1_9
+	imply SMP
+	imply DM_SERIAL
+	imply SIFIVE_SERIAL
+	imply SIFIVE_CLINT
+	imply POWER_DOMAIN
+	imply SIMPLE_PM_BUS
+	imply CLK_CCF
+	imply CLK_COMPOSITE_CCF
+	imply CLK_K210
+	imply DM_RESET
+	imply RESET_SYSCON
+	imply SYSRESET
+	imply SYSRESET_SYSCON
+	imply PINCTRL
+	imply PINCONF
+	imply PINCTRL_K210
+	imply DM_GPIO
+	imply DWAPB_GPIO
+	imply SIFIVE_GPIO
+	imply CMD_GPIO
+	imply LED
+	imply LED_GPIO
+	imply SPI
+	imply DESIGNWARE_SPI
+	imply SPI_FLASH_GIGADEVICE
+	imply SPI_FLASH_WINBOND
+	imply DM_MTD
+	imply SPI_FLASH_MTD
+	imply CMD_MTD
+	imply ENV_IS_IN_SPI_FLASH
+	imply MMC
+	imply MMC_BROKEN_CD
+	imply MMC_SPI
+	imply CMD_MMC
+	imply DOS_PARTITION
+	imply EFI_PARTITION
+	imply CMD_PART
+	imply CMD_FS_GENERIC
+	imply WDT
+	imply DESIGNWARE_WATCHDOG
+endif
diff --git a/roms/u-boot/board/sipeed/maix/MAINTAINERS b/roms/u-boot/board/sipeed/maix/MAINTAINERS
new file mode 100644
index 000000000..0778af7a5
--- /dev/null
+++ b/roms/u-boot/board/sipeed/maix/MAINTAINERS
@@ -0,0 +1,11 @@
+Sipeed Maix BOARD
+M:	Sean Anderson <seanga2@gmail.com>
+S:	Maintained
+F:	arch/riscv/dts/k210.dtsi
+F:	arch/riscv/dts/k210-maix-bit.dts
+F:	board/sipeed/maix/
+F:	configs/sipeed_maix*_defconfig
+F:	doc/board/sipeed/
+F:	include/configs/sipeed-maix.h
+F:	include/dt-bindings/*/k210-sysctl.h
+F:	test/dm/k210_pll.c
diff --git a/roms/u-boot/board/sipeed/maix/Makefile b/roms/u-boot/board/sipeed/maix/Makefile
new file mode 100644
index 000000000..4acff5b31
--- /dev/null
+++ b/roms/u-boot/board/sipeed/maix/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+
+obj-y += maix.o
diff --git a/roms/u-boot/board/sipeed/maix/maix.c b/roms/u-boot/board/sipeed/maix/maix.c
new file mode 100644
index 000000000..52e4fee2f
--- /dev/null
+++ b/roms/u-boot/board/sipeed/maix/maix.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_SDRAM_SIZE;
+}
+
+static int sram_init(void)
+{
+	int ret, i;
+	const char * const banks[] = { "sram0", "sram1", "aisram" };
+	ofnode memory;
+	struct clk clk;
+
+	/* Enable RAM clocks */
+	memory = ofnode_by_compatible(ofnode_null(), "kendryte,k210-sram");
+	if (ofnode_equal(memory, ofnode_null()))
+		return -ENOENT;
+
+	for (i = 0; i < ARRAY_SIZE(banks); i++) {
+		ret = clk_get_by_name_nodev(memory, banks[i], &clk);
+		if (ret)
+			continue;
+
+		ret = clk_enable(&clk);
+		clk_free(&clk);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	return sram_init();
+}
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/board/socrates/Kconfig b/roms/u-boot/board/socrates/Kconfig
new file mode 100644
index 000000000..ca945c278
--- /dev/null
+++ b/roms/u-boot/board/socrates/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SOCRATES
+
+config SYS_BOARD
+	default "socrates"
+
+config SYS_CONFIG_NAME
+	default "socrates"
+
+endif
diff --git a/roms/u-boot/board/socrates/MAINTAINERS b/roms/u-boot/board/socrates/MAINTAINERS
new file mode 100644
index 000000000..2b27a73c1
--- /dev/null
+++ b/roms/u-boot/board/socrates/MAINTAINERS
@@ -0,0 +1,8 @@
+SOCRATES BOARD
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	board/socrates/
+F:	include/configs/socrates.h
+F:	configs/socrates_defconfig
+F:	arch/powerpc/dts/socrates.dts
+F:	arch/powerpc/dts/socrates-u-boot.dtsi
diff --git a/roms/u-boot/board/socrates/Makefile b/roms/u-boot/board/socrates/Makefile
new file mode 100644
index 000000000..e14db8e5d
--- /dev/null
+++ b/roms/u-boot/board/socrates/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2008
+# Sergei Poselenov,  Emcraft Systems, sposelenov@emcraft.com.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= socrates.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-y	+= nand.o
+obj-y	+= sdram.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/roms/u-boot/board/socrates/ddr.c b/roms/u-boot/board/socrates/ddr.c
new file mode 100644
index 000000000..3a94f7bec
--- /dev/null
+++ b/roms/u-boot/board/socrates/ddr.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/roms/u-boot/board/socrates/law.c b/roms/u-boot/board/socrates/law.c
new file mode 100644
index 000000000..840941b63
--- /dev/null
+++ b/roms/u-boot/board/socrates/law.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000	   0x2fff_ffff	   DDR			   512M
+ * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
+ * 0xc000_0000	   0xc00f_ffff	   FPGA			   1M
+ * 0xc800_0000	   0xcbff_ffff	   LIME			   64M
+ * 0xe000_0000	   0xe00f_ffff	   CCSR			   1M (mapped by CCSRBAR)
+ * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
+ * 0xfc00_0000	   0xffff_ffff	   FLASH		   64M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#if defined(CONFIG_SYS_FPGA_BASE)
+	SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+	SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/socrates/nand.c b/roms/u-boot/board/socrates/nand.c
new file mode 100644
index 000000000..07c493679
--- /dev/null
+++ b/roms/u-boot/board/socrates/nand.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_SYS_NAND_BASE)
+#include <nand.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+
+static int state;
+static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte);
+static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
+static u_char sc_nand_read_byte(struct mtd_info *mtd);
+static u16 sc_nand_read_word(struct mtd_info *mtd);
+static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
+static int sc_nand_device_ready(struct mtd_info *mtdinfo);
+
+#define FPGA_NAND_CMD_MASK		(0x7 << 28)
+#define FPGA_NAND_CMD_COMMAND		(0x0 << 28)
+#define FPGA_NAND_CMD_ADDR		(0x1 << 28)
+#define FPGA_NAND_CMD_READ		(0x2 << 28)
+#define FPGA_NAND_CMD_WRITE		(0x3 << 28)
+#define FPGA_NAND_BUSY			(0x1 << 15)
+#define FPGA_NAND_ENABLE		(0x1 << 31)
+#define FPGA_NAND_DATA_SHIFT		16
+
+/**
+ * sc_nand_write_byte -  write one byte to the chip
+ * @mtd:	MTD device structure
+ * @byte:	pointer to data byte to write
+ */
+static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte)
+{
+	sc_nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
+}
+
+/**
+ * sc_nand_write_buf -  write buffer to chip
+ * @mtd:	MTD device structure
+ * @buf:	data buffer
+ * @len:	number of bytes to write
+ */
+static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	int i;
+	struct nand_chip *this = mtd_to_nand(mtd);
+
+	for (i = 0; i < len; i++) {
+		out_be32(this->IO_ADDR_W,
+			 state | (buf[i] << FPGA_NAND_DATA_SHIFT));
+	}
+}
+
+
+/**
+ * sc_nand_read_byte -  read one byte from the chip
+ * @mtd:	MTD device structure
+ */
+static u_char sc_nand_read_byte(struct mtd_info *mtd)
+{
+	u8 byte;
+	sc_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
+	return byte;
+}
+
+/**
+ * sc_nand_read_word -  read one word from the chip
+ * @mtd:	MTD device structure
+ */
+static u16 sc_nand_read_word(struct mtd_info *mtd)
+{
+	u16 word;
+	sc_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
+	return word;
+}
+
+/**
+ * sc_nand_read_buf -  read chip data into buffer
+ * @mtd:	MTD device structure
+ * @buf:	buffer to store date
+ * @len:	number of bytes to read
+ */
+static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	int i;
+	struct nand_chip *this = mtd_to_nand(mtd);
+	int val;
+
+	val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ;
+
+	out_be32(this->IO_ADDR_W, val);
+	for (i = 0; i < len; i++) {
+		buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff;
+	}
+}
+
+/**
+ * sc_nand_device_ready - Check the NAND device is ready for next command.
+ * @mtd:	MTD device structure
+ */
+static int sc_nand_device_ready(struct mtd_info *mtdinfo)
+{
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
+
+	if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
+		return 0; /* busy */
+	return 1;
+}
+
+/**
+ * sc_nand_hwcontrol - NAND control functions wrapper.
+ * @mtd:	MTD device structure
+ * @cmd:	Command
+ */
+static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+	if (ctrl & NAND_CTRL_CHANGE) {
+		state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE);
+
+		switch (ctrl & (NAND_ALE | NAND_CLE)) {
+		case 0:
+			state |= FPGA_NAND_CMD_WRITE;
+			break;
+
+		case NAND_ALE:
+			state |= FPGA_NAND_CMD_ADDR;
+			break;
+
+		case NAND_CLE:
+			state |= FPGA_NAND_CMD_COMMAND;
+			break;
+
+		default:
+			printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
+		}
+
+		if (ctrl & NAND_NCE)
+			state |= FPGA_NAND_ENABLE;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		sc_nand_write_byte(mtdinfo, cmd);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->cmd_ctrl = sc_nand_hwcontrol;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->dev_ready = sc_nand_device_ready;
+	nand->read_byte = sc_nand_read_byte;
+	nand->read_word = sc_nand_read_word;
+	nand->write_buf = sc_nand_write_buf;
+	nand->read_buf = sc_nand_read_buf;
+
+	return 0;
+}
+
+#endif
diff --git a/roms/u-boot/board/socrates/sdram.c b/roms/u-boot/board/socrates/sdram.c
new file mode 100644
index 000000000..d358a209a
--- /dev/null
+++ b/roms/u-boot/board/socrates/sdram.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <spd_sdram.h>
+#include <linux/delay.h>
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Autodetect onboard DDR SDRAM on 85xx platforms
+ *
+ * NOTE: Some of the hardcoded values are hardware dependant,
+ *       so this should be extended for other future boards
+ *       using this routine!
+ */
+phys_size_t fixed_sdram(void)
+{
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+
+	/*
+	 * Disable memory controller.
+	 */
+	ddr->cs0_config = 0;
+	ddr->sdram_cfg = 0;
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
+
+	asm ("sync;isync;msync");
+	udelay(1000);
+
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
+	asm ("sync; isync; msync");
+	udelay(1000);
+
+	if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
+		/*
+		 * OK, size detected -> all done
+		 */
+		return CONFIG_SYS_SDRAM_SIZE<<20;
+	}
+
+	return 0;				/* nothing found !		*/
+}
+#endif
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram(void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf ("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf ("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf ("SDRAM test passed.\n");
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/socrates/socrates.c b/roms/u-boot/board/socrates/socrates.c
new file mode 100644
index 000000000..3444af6a8
--- /dev/null
+++ b/roms/u-boot/board/socrates/socrates.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <env.h>
+#include <init.h>
+#include <pci.h>
+#include <uuid.h>
+#include <asm/global_data.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <flash.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <video_fb.h>
+#include "upm_table.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[];	/* FLASH chips info */
+
+void local_bus_init (void);
+ulong flash_get_size (ulong base, int banknum);
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	char buf[64];
+	int f;
+	int i = env_get_f("serial#", buf, sizeof(buf));
+#ifdef CONFIG_PCI
+	char *src;
+#endif
+
+	puts("Board: Socrates");
+	if (i > 0) {
+		puts(", serial# ");
+		puts(buf);
+	}
+	putc('\n');
+
+#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
+	/* Check the PCI_clk sel bit */
+	if (in_be32(&gur->porpllsr) & (1<<15)) {
+		src = "SYSCLK";
+		f = CONFIG_SYS_CLK_FREQ;
+	} else {
+		src = "PCI_CLK";
+		f = CONFIG_PCI_CLK_FREQ;
+	}
+	printf ("PCI1:  32 bit, %d MHz (%s)\n",	f/1000000, src);
+#else
+	printf ("PCI1:  disabled\n");
+#endif
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/*
+	 * Adjust flash start and offset to detected values
+	 */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Check if boot FLASH isn't max size
+	 */
+	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
+		set_lbc_or(0, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+		set_lbc_br(0, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
+
+		/*
+		 * Re-check to get correct base address
+		 */
+		flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
+	}
+
+	/*
+	 * Check if only one FLASH bank is available
+	 */
+	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
+		set_lbc_or(1, 0);
+		set_lbc_br(1, 0);
+
+		/*
+		 * Re-do flash protection upon new addresses
+		 */
+		flash_protect(FLAG_PROTECT_CLEAR,
+			      gd->bd->bi_flashstart, 0xffffffff,
+			      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+		/* Monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE +
+			      monitor_flash_len - 1,
+			      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+		/* Environment protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_ENV_ADDR,
+			      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+			      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+		/* Redundant environment protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_ENV_ADDR_REDUND,
+			      CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+	}
+
+#if defined(CONFIG_DM_PCI)
+	pci_init();
+#endif
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init (void)
+{
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+	sys_info_t sysinfo;
+	uint clkdiv;
+	uint lbc_mhz;
+	uint lcrr = CONFIG_SYS_LBC_LCRR;
+
+	get_sys_info (&sysinfo);
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
+	lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
+
+	/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
+	if (lbc_mhz >= 66)
+		lcrr &= ~LCRR_DBYP;	/* DLL Enabled */
+	else
+		lcrr |= LCRR_DBYP;	/* DLL Bypass */
+
+	out_be32 (&lbc->lcrr, lcrr);
+	asm ("sync;isync;msync");
+
+	out_be32 (&lbc->ltesr, 0xffffffff);	/* Clear LBC error interrupts */
+	out_be32 (&lbc->lteir, 0xffffffff);	/* Enable LBC error interrupts */
+	out_be32 (&ecm->eedr, 0xffffffff);	/* Clear ecm errors */
+	out_be32 (&ecm->eeer, 0xffffffff);	/* Enable ecm errors */
+
+	/* Init UPMA for FPGA access */
+	out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
+	upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
+
+	/* Init UPMB for Lime controller access */
+	out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
+	upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* set and reset the GPIO pin 2 which will reset the W83782G chip */
+	out_8((unsigned char*)&gur->gpoutdr, 0x3F );
+	out_be32((unsigned int*)&gur->gpiocr, 0x200 );	/* enable GPOut */
+	udelay(200);
+	out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
+
+	return (0);
+}
+#endif /* CONFIG_BOARD_EARLY_INIT_R */
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u32 val[12];
+	int rc, i = 0;
+
+	ft_cpu_setup(blob, bd);
+
+	/* Fixup NOR FLASH mapping */
+	val[i++] = 0;				/* chip select number */
+	val[i++] = 0;				/* always 0 */
+	val[i++] = gd->bd->bi_flashstart;
+	val[i++] = gd->bd->bi_flashsize;
+
+	/* Fixup FPGA mapping */
+	val[i++] = 3;				/* chip select number */
+	val[i++] = 0;				/* always 0 */
+	val[i++] = CONFIG_SYS_FPGA_BASE;
+	val[i++] = CONFIG_SYS_FPGA_SIZE;
+
+	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
+				  val, i * sizeof(u32), 1);
+	if (rc)
+		printf("Unable to update localbus ranges, err=%s\n",
+		       fdt_strerror(rc));
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+#if defined(CONFIG_OF_SEPARATE)
+void *board_fdt_blob_setup(void)
+{
+	void *fw_dtb;
+
+	fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
+	if (fdt_magic(fw_dtb) != FDT_MAGIC) {
+		printf("DTB is not passed via %x\n", (u32)fw_dtb);
+		return NULL;
+	}
+
+	return fw_dtb;
+}
+#endif
+
+int get_serial_clock(void)
+{
+	return 333333330;
+}
diff --git a/roms/u-boot/board/socrates/tlb.c b/roms/u-boot/board/socrates/tlb.c
new file mode 100644
index 000000000..de80c3c0e
--- /dev/null
+++ b/roms/u-boot/board/socrates/tlb.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+
+	/*
+	 * TLB 1:	64M	Non-cacheable, guarded
+	 * 0xfc000000	64M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#if defined(CONFIG_SYS_FPGA_BASE)
+	/*
+	 * TLB 4:	1M	Non-cacheable, guarded
+	 * 0xc0000000	1M	FPGA and NAND
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_1M, 1),
+#endif
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xc8000000	16M	LIME GDC framebuffer
+	 * 0xc9fc0000	256K	LIME GDC MMIO
+	 * (0xcbfc0000	256K	LIME GDC MMIO)
+	 * MMIO is relocatable and could be at 0xcbfc0000
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 7+8:	512M	DDR, cache disabled (needed for memory test)
+	 * 0x00000000  512M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_256M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/socrates/upm_table.h b/roms/u-boot/board/socrates/upm_table.h
new file mode 100644
index 000000000..1fc9c5c9a
--- /dev/null
+++ b/roms/u-boot/board/socrates/upm_table.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __UPM_TABLE_H
+#define __UPM_TABLE_H
+
+/* UPM Table Configuration Code for FPGA access */
+static const unsigned int UPMTableA[] =
+{
+	0x00fcec00,  0x00fcec00,  0x00fcec00,  0x00fcec00, /* Words 0 to 3	*/
+	0x00fcec00,  0x00fcfc00,  0x00fcfc00,  0x00fcec05, /* Words 4 to 7	*/
+	0x00fcec00,  0x00fcec00,  0x00fcec04,  0x00fcec04, /* Words 8 to 11	*/
+	0x00fcec04,  0x00fcec04,  0x00fcec04,  0x00fcec04, /* Words 12 to 15	*/
+	0x00fcec04,  0x00fcec04,  0x0fffec00,  0xffffec00, /* Words 16 to 19	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 20 to 23	*/
+	0x00ffec00,  0x00ffec00,  0x00f3ec00,  0x0fffec00, /* Words 24 to 27	*/
+	0x0ffffc04,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 28 to 31	*/
+	0x00ffec00,  0x00ffec00,  0x00f3ec04,  0x00f3ec04, /* Words 32 to 35	*/
+	0x00f3ec04,  0x00f3ec04,  0x00f3ec04,  0x00f3ec04, /* Words 36 to 39	*/
+	0x00f3ec04,  0x00f3ec04,  0x0fffec00,  0xffffec00, /* Words 40 to 43	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 44 to 47	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec00, /* Words 48 to 51	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec00, /* Words 52 to 55	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 56 to 59	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01  /* Words 60 to 63	*/
+};
+
+/* LIME UPM B Table Configuration Code */
+static unsigned int UPMTableB[] =
+{
+	0x0ffefc00,  0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc00, /* Words 0 to 3	*/
+	0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc04,  0x0ffffc01, /* Words 4 to 7	*/
+	0x0ffefc00,  0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc00, /* Words 8 to 11	*/
+	0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc04,  0x0ffcfc04, /* Words 12 to 15	*/
+	0x0ffcfc04,  0x0ffcfc04,  0x0ffcfc04,  0x0ffcfc04, /* Words 16 to 19	*/
+	0x0ffcfc04,  0x0ffcfc04,  0x0ffffc00,  0xfffffc01, /* Words 20 to 23	*/
+	0x0cfffc00,  0x00fffc00,  0x00fffc00,  0x00fffc00, /* Words 24 to 27	*/
+	0x00fffc00,  0x00fffc00,  0x00fffc04,  0x0ffffc01, /* Words 28 to 31	*/
+	0x0cfffc00,  0x00fffc00,  0x00fffc00,  0x00fffc00, /* Words 32 to 35	*/
+	0x00fffc00,  0x00fffc00,  0x00fffc04,  0x00fffc04, /* Words 36 to 39	*/
+	0x00fffc04,  0x00fffc04,  0x00fffc04,  0x00fffc04, /* Words 40 to 43	*/
+	0x00fffc04,  0x00fffc04,  0x0ffffc00,  0xfffffc01, /* Words 44 to 47	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 48 to 51	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 52 to 55	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 56 to 59	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01  /* Words 60 to 63	*/
+};
+#endif
diff --git a/roms/u-boot/board/softing/vining_2000/Kconfig b/roms/u-boot/board/softing/vining_2000/Kconfig
new file mode 100644
index 000000000..90d45a7f6
--- /dev/null
+++ b/roms/u-boot/board/softing/vining_2000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SOFTING_VINING_2000
+
+config SYS_BOARD
+	default "vining_2000"
+
+config SYS_VENDOR
+	default "softing"
+
+config SYS_CONFIG_NAME
+	default "vining_2000"
+
+endif
diff --git a/roms/u-boot/board/softing/vining_2000/MAINTAINERS b/roms/u-boot/board/softing/vining_2000/MAINTAINERS
new file mode 100644
index 000000000..0df78c6b9
--- /dev/null
+++ b/roms/u-boot/board/softing/vining_2000/MAINTAINERS
@@ -0,0 +1,6 @@
+VINING_2000 BOARD
+M:	Silvio Fricke <open-source@softing.de>
+S:	Maintained
+F:	board/softing/vining_2000/
+F:	include/configs/vining_2000.h
+F:	configs/vining_2000_defconfig
diff --git a/roms/u-boot/board/softing/vining_2000/Makefile b/roms/u-boot/board/softing/vining_2000/Makefile
new file mode 100644
index 000000000..84f66a67b
--- /dev/null
+++ b/roms/u-boot/board/softing/vining_2000/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2016 samtec automotive software & electronics gmbh
+# Copyright (C) 2017-2019 softing automotive electronics gmbH
+
+obj-y  := vining_2000.o
diff --git a/roms/u-boot/board/softing/vining_2000/imximage.cfg b/roms/u-boot/board/softing/vining_2000/imximage.cfg
new file mode 100644
index 000000000..f6f59ddf5
--- /dev/null
+++ b/roms/u-boot/board/softing/vining_2000/imximage.cfg
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ * Copyright (C) 2017-2019 softing automotive electronics gmbH
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000028
+DATA 4 0x020e02fc 0x00000028
+DATA 4 0x020e05f4 0x00000028
+
+/* Control */
+DATA 4 0x020e0340 0x00000028
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000028
+DATA 4 0x020e0314 0x00000028
+DATA 4 0x020e0614 0x00000028
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000028
+DATA 4 0x020e0334 0x00000028
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e033c 0x00000028
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+/* Calibrations - ZQ */
+DATA 4 0x021b0800 0xa1390003
+
+/* Write leveling */
+DATA 4 0x021b080c 0x00290025
+DATA 4 0x021b0810 0x00210022
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x4142013a
+DATA 4 0x021b0840 0x012e0123
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x43474949
+DATA 4 0x021b0850 0x38383c38
+
+/* Read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333040
+DATA 4 0x021b000c 0x676b52f2
+DATA 4 0x021b0010 0x926e8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000005f
+DATA 4 0x021b0000 0x84190000
+
+/* Initialize MT41K256M16HA-125 - MR2 */
+DATA 4 0x021b001c 0x02008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00048031
+/* MR0 */
+DATA 4 0x021b001c 0x15108030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00007800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b001c 0x00000000
diff --git a/roms/u-boot/board/softing/vining_2000/vining_2000.c b/roms/u-boot/board/softing/vining_2000/vining_2000.c
new file mode 100644
index 000000000..aaeeee361
--- /dev/null
+++ b/roms/u-boot/board/softing/vining_2000/vining_2000.c
@@ -0,0 +1,610 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ * Copyright (C) 2017-2019 softing automotive electronics gmbH
+ *
+ * Author: Christoph Fritz <chf.fritz@googlemail.com>
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <env.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <pwm.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE |	\
+	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm |		\
+	PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL  PAD_CTL_DSE_34ohm
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE |			\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH |		\
+	PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm)
+
+#define USDHC_CLK_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
+
+#define USDHC_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |	\
+	PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |	\
+	PAD_CTL_SRE_FAST)
+
+#define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |	\
+	PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
+
+#define GPIO_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_PKE)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const pwm_led_pads[] = {
+	MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
+	MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
+	MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
+};
+
+static int board_net_init(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	unsigned char eth1addr[6];
+	int ret;
+
+	/* just to get second mac address */
+	imx_get_mac_from_fuse(1, eth1addr);
+	if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
+		eth_env_set_enetaddr("eth1addr", eth1addr);
+
+	/*
+	 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
+	 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
+	 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1],
+			IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
+			IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
+			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+	if (ret)
+		goto eth_fail;
+
+	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+	if (ret)
+		goto eth_fail;
+
+	return ret;
+
+eth_fail:
+	printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
+	return ret;
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+		.gp = IMX_GPIO_NR(1, 0),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+		.gp = IMX_GPIO_NR(1, 1),
+	},
+};
+
+static struct pmic *pfuze_init(unsigned char i2cbus)
+{
+	struct pmic *p;
+	int ret;
+	u32 reg;
+
+	ret = power_pfuze100_init(i2cbus);
+	if (ret)
+		return NULL;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return NULL;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE%i00 ID=0x%02x\n", (reg & 1) ? 2 : 1, reg);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+	return p;
+}
+
+static int pfuze_mode_init(struct pmic *p, u32 mode)
+{
+	unsigned char offset, i, switch_num;
+	u32 id;
+	int ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
+	id = id & 0xf;
+
+	if (id == 0) {
+		switch_num = 6;
+		offset = PFUZE100_SW1CMODE;
+	} else if (id == 1) {
+		switch_num = 4;
+		offset = PFUZE100_SW2MODE;
+	} else {
+		printf("Not supported, id=%d\n", id);
+		return -EINVAL;
+	}
+
+	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+	if (ret < 0) {
+		printf("Set SW1AB mode error!\n");
+		return ret;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
+		if (ret < 0) {
+			printf("Set switch 0x%x mode error!\n",
+			       offset + i * SWITCH_SIZE);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+
+	p = pfuze_init(I2C_PMIC);
+	if (!p)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	set_ldo_voltage(LDO_ARM, 1175);	/* Set VDDARM to 1.175V */
+	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	/* OGT1 */
+	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* OTG2 */
+	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_iomux_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+#endif
+
+#ifdef CONFIG_PWM_IMX
+static int set_pwm_leds(void)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
+					 ARRAY_SIZE(pwm_led_pads));
+	/* enable backlight PWM 2, green LED */
+	ret = pwm_init(1, 0, 0);
+	if (ret)
+		goto error;
+	/* duty cycle 200ns, period: 8000ns */
+	ret = pwm_config(1, 200, 8000);
+	if (ret)
+		goto error;
+	ret = pwm_enable(1);
+	if (ret)
+		goto error;
+
+	/* enable backlight PWM 1, blue LED */
+	ret = pwm_init(0, 0, 0);
+	if (ret)
+		goto error;
+	/* duty cycle 200ns, period: 8000ns */
+	ret = pwm_config(0, 200, 8000);
+	if (ret)
+		goto error;
+	ret = pwm_enable(0);
+	if (ret)
+		goto error;
+
+	/* enable backlight PWM 6, red LED */
+	ret = pwm_init(5, 0, 0);
+	if (ret)
+		goto error;
+	/* duty cycle 200ns, period: 8000ns */
+	ret = pwm_config(5, 200, 8000);
+	if (ret)
+		goto error;
+	ret = pwm_enable(5);
+
+error:
+	return ret;
+}
+#else
+static int set_pwm_leds(void)
+{
+	return 0;
+}
+#endif
+
+#define ADCx_HC0        0x00
+#define ADCx_HS         0x08
+#define ADCx_HS_C0      BIT(0)
+#define ADCx_R0         0x0c
+#define ADCx_CFG        0x14
+#define ADCx_CFG_SWMODE 0x308
+#define ADCx_GC         0x18
+#define ADCx_GC_CAL     BIT(7)
+
+static int read_adc(u32 *val)
+{
+	int ret;
+	void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
+
+	/* use software mode */
+	writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
+
+	/* start auto calibration */
+	setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
+	ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
+	if (ret)
+		goto adc_exit;
+
+	/* start conversion */
+	writel(0, b + ADCx_HC0);
+
+	/* wait for conversion */
+	ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
+	if (ret)
+		goto adc_exit;
+
+	/* read result */
+	*val = readl(b + ADCx_R0);
+
+adc_exit:
+	if (ret)
+		printf("ADC failure (ret=%i)\n", ret);
+	unmap_physmem(b, MAP_NOCACHE);
+	return ret;
+}
+
+#define VAL_UPPER	2498
+#define VAL_LOWER	1550
+
+static int set_pin_state(void)
+{
+	u32 val;
+	int ret;
+
+	ret = read_adc(&val);
+	if (ret)
+		return ret;
+
+	if (val >= VAL_UPPER)
+		env_set("pin_state", "connected");
+	else if (val < VAL_UPPER && val > VAL_LOWER)
+		env_set("pin_state", "open");
+	else
+		env_set("pin_state", "button");
+
+	return ret;
+}
+
+int board_late_init(void)
+{
+	int ret;
+
+	ret = set_pwm_leds();
+	if (ret)
+		return ret;
+
+	ret = set_pin_state();
+
+	return ret;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_usb();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_MXC
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+	return board_net_init();
+}
+
+int checkboard(void)
+{
+	puts("Board: VIN|ING 2000\n");
+
+	return 0;
+}
+
+#define PCIE_PHY_PUP_REQ		BIT(7)
+
+void board_preboot_os(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
+
+	/* Bring the PCI power domain up, so that old vendorkernel works. */
+	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+	setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+	setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <linux/libfdt.h>
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+static iomux_v3_cfg_t const pcie_pads[] = {
+	MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void vining2000_spl_setup_iomux_pcie(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
+static void vining2000_spl_setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
+
+int board_mmc_init(struct bd_info *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+	gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0		= 0x00000028,
+	.dram_dqm1		= 0x00000028,
+	.dram_dqm2		= 0x00000028,
+	.dram_dqm3		= 0x00000028,
+	.dram_ras		= 0x00000028,
+	.dram_cas		= 0x00000028,
+	.dram_odt0		= 0x00000028,
+	.dram_odt1		= 0x00000028,
+	.dram_sdba2		= 0x00000000,
+	.dram_sdcke0		= 0x00003000,
+	.dram_sdcke1		= 0x00003000,
+	.dram_sdclk_0		= 0x00000030,
+	.dram_sdqs0		= 0x00000028,
+	.dram_sdqs1		= 0x00000028,
+	.dram_sdqs2		= 0x00000028,
+	.dram_sdqs3		= 0x00000028,
+	.dram_reset		= 0x00000028,
+};
+
+const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds		= 0x00000028,
+	.grp_b0ds		= 0x00000028,
+	.grp_b1ds		= 0x00000028,
+	.grp_b2ds		= 0x00000028,
+	.grp_b3ds		= 0x00000028,
+	.grp_ctlds		= 0x00000028,
+	.grp_ddr_type		= 0x000c0000,
+	.grp_ddrmode		= 0x00020000,
+	.grp_ddrmode_ctl	= 0x00020000,
+	.grp_ddrpke		= 0x00000000,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0		= 0x0022001C,
+	.p0_mpwldectrl1		= 0x001F001A,
+	.p0_mpdgctrl0		= 0x01380134,
+	.p0_mpdgctrl1		= 0x0124011C,
+	.p0_mprddlctl		= 0x42404444,
+	.p0_mpwrdlctl		= 0x36383C38,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed	= 1600,
+	.density	= 4,
+	.width		= 32,
+	.banks		= 8,
+	.rowaddr	= 15,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1391,
+	.trcmin		= 4875,
+	.trasmin	= 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xF000000F, &ccm->CCGR0);	/* AIPS_TZ{1,2,3} */
+	writel(0x303C0000, &ccm->CCGR1);	/* GPT, OCRAM */
+	writel(0x00FFFCC0, &ccm->CCGR2);	/* IPMUX, I2C1, I2C3 */
+	writel(0x3F300030, &ccm->CCGR3);	/* OCRAM, MMDC, ENET */
+	writel(0x0000C003, &ccm->CCGR4);	/* PCI, PL301 */
+	writel(0x0F0330C3, &ccm->CCGR5);	/* UART, ROM */
+	writel(0x00000F00, &ccm->CCGR6);	/* SDHI4, EIM */
+}
+
+static void vining2000_spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		.dsize		= mem_ddr.width / 32,
+		.cs_density	= 24,
+		.ncs		= 1,
+		.cs1_mirror	= 0,
+		.rtt_wr		= 1,	/* RTT_wr = RZQ/4 */
+		.rtt_nom	= 1,	/* RTT_Nom = RZQ/4 */
+		.walat		= 1,	/* Write additional latency */
+		.ralat		= 5,	/* Read additional latency */
+		.mif3_mode	= 3,	/* Command prediction working mode */
+		.bi_on		= 1,	/* Bank interleaving enabled */
+		.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.ddr_type	= DDR_TYPE_DDR3,
+		.refsel		= 1,	/* Refresh cycles at 32KHz */
+		.refr		= 7,	/* 8 refresh commands per refresh cycle */
+	};
+
+	mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+
+	/* Perform DDR DRAM calibration */
+	udelay(100);
+	mmdc_do_write_level_calibration(&sysinfo);
+	mmdc_do_dqs_calibration(&sysinfo);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+
+	/* iomux setup */
+	vining2000_spl_setup_iomux_pcie();
+	vining2000_spl_setup_iomux_uart();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* reset the PCIe device */
+	gpio_set_value(IMX_GPIO_NR(4, 6), 1);
+	udelay(50);
+	gpio_set_value(IMX_GPIO_NR(4, 6), 0);
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	vining2000_spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/roms/u-boot/board/softing/vining_fpga/MAINTAINERS b/roms/u-boot/board/softing/vining_fpga/MAINTAINERS
new file mode 100644
index 000000000..c2002fe3c
--- /dev/null
+++ b/roms/u-boot/board/softing/vining_fpga/MAINTAINERS
@@ -0,0 +1,5 @@
+VINING FPGA BOARD
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+F:	include/configs/socfpga_vining_fpga.h
+F:	configs/socfpga_vining_fpga_defconfig
diff --git a/roms/u-boot/board/softing/vining_fpga/Makefile b/roms/u-boot/board/softing/vining_fpga/Makefile
new file mode 100644
index 000000000..e1c8a6b3c
--- /dev/null
+++ b/roms/u-boot/board/softing/vining_fpga/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/softing/vining_fpga/qts/iocsr_config.h b/roms/u-boot/board/softing/vining_fpga/qts/iocsr_config.h
new file mode 100644
index 000000000..8c78aecdd
--- /dev/null
+++ b/roms/u-boot/board/softing/vining_fpga/qts/iocsr_config.h
@@ -0,0 +1,659 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00000000,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00018060,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00000000,
+	0x300C0000,
+	0x000000C0,
+	0x00000000,
+	0x00000000,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00000060,
+	0x00018060,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x01800000,
+	0x00000006,
+	0x00601806,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x300C0300,
+	0x300C0000,
+	0x0FF00000,
+	0x00000000,
+	0x000300C0,
+	0x00008000,
+	0x18060180,
+	0x18060000,
+	0x00000000,
+	0x00000000,
+	0x00018060,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x00000030,
+	0x00000000,
+	0x0300C030,
+	0x00002000,
+	0x00018060,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+	0x0000C030,
+	0x00000000,
+	0x03000000,
+	0x0000000C,
+	0x00C0300C,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xD4380000,
+	0xE0003000,
+	0x00C00350,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x70001800,
+	0x006001A8,
+	0x8006A1C0,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x350E0000,
+	0x38000C00,
+	0x003000D4,
+	0xC00350E0,
+	0x0D438000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680A28,
+	0x41034051,
+	0x12481A00,
+	0x80A280D0,
+	0x34051406,
+	0x01A02490,
+	0x080D0000,
+	0x51406802,
+	0x02490340,
+	0xD000001A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0xC0000000,
+	0x018006A1,
+	0x001A8700,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xD4380000,
+	0xE0003000,
+	0x00C00350,
+	0x00000FF0,
+	0x350E0000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x70001800,
+	0x006001A8,
+	0x8006A1C0,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x350E0000,
+	0x38000C00,
+	0x003000D4,
+	0xC00350E0,
+	0x0D438000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680208,
+	0x49034051,
+	0x12481A02,
+	0x80A280D0,
+	0x34030C06,
+	0x01A00040,
+	0x280D0002,
+	0x5140680A,
+	0x01450340,
+	0xD00A281A,
+	0x0680E380,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0xC0000000,
+	0x018006A1,
+	0x001A8700,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xD438090C,
+	0x00003000,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8A28A3DD,
+	0xF6D1451E,
+	0x034AD348,
+	0x821A0000,
+	0x0000D000,
+	0x05140680,
+	0xDD59647A,
+	0x1E8A28A3,
+	0x48F6D145,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x70120800,
+	0x006001A8,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8A28A3DD,
+	0xF6D1451E,
+	0x034AD348,
+	0x821A0186,
+	0x0000D000,
+	0x00000680,
+	0xDD59647A,
+	0x1E8A28A3,
+	0x48F6D145,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xD438090C,
+	0x00003000,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8A28A3DD,
+	0xF6D1451E,
+	0x034AD348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDD59647A,
+	0x1E8A28A3,
+	0x48F6D145,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8A28A3DD,
+	0xF6D1451E,
+	0x034AD348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDD59647A,
+	0x1E8A28A3,
+	0x48F6D145,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/softing/vining_fpga/qts/pinmux_config.h b/roms/u-boot/board/softing/vining_fpga/qts/pinmux_config.h
new file mode 100644
index 000000000..f73ccbbab
--- /dev/null
+++ b/roms/u-boot/board/softing/vining_fpga/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	2, /* FLASHIO0 */
+	2, /* FLASHIO1 */
+	2, /* FLASHIO2 */
+	2, /* FLASHIO3 */
+	2, /* FLASHIO4 */
+	2, /* FLASHIO5 */
+	2, /* FLASHIO6 */
+	2, /* FLASHIO7 */
+	2, /* FLASHIO8 */
+	2, /* FLASHIO9 */
+	2, /* FLASHIO10 */
+	2, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	3, /* GENERALIO9 */
+	3, /* GENERALIO10 */
+	3, /* GENERALIO11 */
+	3, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	2, /* GENERALIO15 */
+	2, /* GENERALIO16 */
+	0, /* GENERALIO17 */
+	0, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	2, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	1, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	1, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/softing/vining_fpga/qts/pll_config.h b/roms/u-boot/board/softing/vining_fpga/qts/pll_config.h
new file mode 100644
index 000000000..fa0461833
--- /dev/null
+++ b/roms/u-boot/board/softing/vining_fpga/qts/pll_config.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 488281
+#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
+#define CONFIG_HPS_CLK_QSPI_HZ 320000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/roms/u-boot/board/softing/vining_fpga/qts/sdram_config.h b/roms/u-boot/board/softing/vining_fpga/qts/sdram_config.h
new file mode 100644
index 000000000..ec067eb47
--- /dev/null
+++ b/roms/u-boot/board/softing/vining_fpga/qts/sdram_config.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			104
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0		0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x10441
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x78
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	7
+#define CALIB_VFIFO_OFFSET	5
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x555504b4
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080421,
+	0x10080520,
+	0x10090046,
+	0x100a0088,
+	0x100b0000,
+	0x10380400,
+	0x10080441,
+	0x100804c0,
+	0x100a0026,
+	0x10090110,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/roms/u-boot/board/softing/vining_fpga/socfpga.c b/roms/u-boot/board/softing/vining_fpga/socfpga.c
new file mode 100644
index 000000000..aaedf0345
--- /dev/null
+++ b/roms/u-boot/board/softing/vining_fpga/socfpga.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>
+#include <eeprom.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <status_led.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_late_init(void)
+{
+	const unsigned int phy_nrst_gpio = 0;
+	const unsigned int usb_nrst_gpio = 35;
+	int ret;
+
+	status_led_set(1, CONFIG_LED_STATUS_ON);
+	status_led_set(2, CONFIG_LED_STATUS_ON);
+
+	/* Address of boot parameters for ATAG (if ATAG is used) */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio");
+	if (!ret)
+		gpio_direction_output(phy_nrst_gpio, 1);
+	else
+		printf("Cannot remove PHY from reset!\n");
+
+	ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio");
+	if (!ret)
+		gpio_direction_output(usb_nrst_gpio, 1);
+	else
+		printf("Cannot remove USB from reset!\n");
+
+	mdelay(50);
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+int misc_init_r(void)
+{
+	uchar data[128];
+	char str[32];
+	u32 serial;
+	int ret;
+
+	/* EEPROM is at address 0x50 (at bus CONFIG_SYS_EEPROM_BUS_NUM). */
+	ret = eeprom_read(0x50, 0, data, sizeof(data));
+	if (ret) {
+		puts("Cannot read I2C EEPROM.\n");
+		return 0;
+	}
+
+	/* Check EEPROM signature. */
+	if (!(data[0] == 0xa5 && data[1] == 0x5a)) {
+		puts("Invalid I2C EEPROM signature.\n");
+		env_set("unit_serial", "invalid");
+		env_set("unit_ident", "VINing-xxxx-STD");
+		env_set("hostname", "vining-invalid");
+		return 0;
+	}
+
+	/* If 'unit_serial' is already set, do nothing. */
+	if (!env_get("unit_serial")) {
+		/* This field is Big Endian ! */
+		serial = (data[0x54] << 24) | (data[0x55] << 16) |
+			 (data[0x56] << 8) | (data[0x57] << 0);
+		memset(str, 0, sizeof(str));
+		sprintf(str, "%07i", serial);
+		env_set("unit_serial", str);
+	}
+
+	if (!env_get("unit_ident")) {
+		memset(str, 0, sizeof(str));
+		memcpy(str, &data[0x2e], 18);
+		env_set("unit_ident", str);
+	}
+
+	/* Set ethernet address from EEPROM. */
+	if (!env_get("ethaddr") && is_valid_ethaddr(&data[0x62]))
+		eth_env_set_enetaddr("ethaddr", &data[0x62]);
+	if (!env_get("eth1addr") && is_valid_ethaddr(&data[0x6a]))
+		eth_env_set_enetaddr("eth1addr", &data[0x6a]);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/solidrun/clearfog/Kconfig b/roms/u-boot/board/solidrun/clearfog/Kconfig
new file mode 100644
index 000000000..cf9525809
--- /dev/null
+++ b/roms/u-boot/board/solidrun/clearfog/Kconfig
@@ -0,0 +1,62 @@
+menu "ClearFog configuration"
+	depends on TARGET_CLEARFOG
+
+config TARGET_CLEARFOG_BASE
+	bool "Use ClearFog Base static configuration"
+	help
+	  Use the ClearFog Base as the static configuration instead of the
+	  default which uses the ClearFog Pro.
+
+	  Runtime board detection is always attempted and used if available. The
+	  static configuration is used as a fallback in cases where runtime
+	  detection is disabled, is not available in hardware, or otherwise fails.
+
+	  Only newer revisions of the ClearFog product line support runtime
+	  detection via additional EEPROM hardware. This option enables selecting
+	  the Base variant for older hardware revisions.
+
+config CLEARFOG_CON3_SATA
+	bool "Use CON3 slot in SATA mode"
+	help
+	  Use the CON3 port with SATA protocol instead of the default PCIe.
+	  The ClearFog port allows usage of either mSATA or miniPCIe
+	  modules, but the desired protocol must be configured at build
+	  time since it affects the SerDes topology layout.
+
+config CLEARFOG_CON2_SATA
+	bool "Use CON2 slot in SATA mode"
+	depends on !TARGET_CLEARFOG_BASE
+	help
+	  Use the CON2 port with SATA protocol instead of the default PCIe.
+	  The ClearFog port allows usage of either mSATA or miniPCIe
+	  modules, but the desired protocol must be configured at build
+	  time since it affects the SerDes topology layout.
+
+config CLEARFOG_SFP_25GB
+	bool "Enable 2.5 Gbps mode for SFP"
+	help
+	  Set the SFP module connection to support 2.5 Gbps transfer speed for the
+	  SGMII connection (requires a supporting SFP). By default, transfer speed
+	  of 1.25 Gbps is used, suitable for a more common 1 Gbps SFP module.
+
+config ENV_SIZE
+	hex "Environment Size"
+	default 0x10000
+
+config ENV_OFFSET
+	hex "Environment offset"
+	default 0xF0000
+
+config ENV_SECT_SIZE
+	hex "Environment Sector-Size"
+	# Use SPI flash erase block size of 4 KiB
+	default 0x1000 if MVEBU_SPL_BOOT_DEVICE_SPI || MVEBU_SPL_BOOT_DEVICE_SATA
+	# Use optimistic 64 KiB erase block, will vary between actual media
+	default 0x10000 if MVEBU_SPL_BOOT_DEVICE_MMC || MVEBU_SPL_BOOT_DEVICE_UART
+
+config SYS_SPI_U_BOOT_OFFS
+	hex "address of u-boot payload in SPI flash"
+	default 0x20000
+	depends on MVEBU_SPL_BOOT_DEVICE_SPI
+
+endmenu
diff --git a/roms/u-boot/board/solidrun/clearfog/MAINTAINERS b/roms/u-boot/board/solidrun/clearfog/MAINTAINERS
new file mode 100644
index 000000000..6646d9620
--- /dev/null
+++ b/roms/u-boot/board/solidrun/clearfog/MAINTAINERS
@@ -0,0 +1,7 @@
+CLEARFOG BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/soldrun/clearfog/
+F:	include/configs/clearfog.h
+F:	configs/clearfog_defconfig
+F:	configs/clearfog_gt_8k_defconfig
diff --git a/roms/u-boot/board/solidrun/clearfog/Makefile b/roms/u-boot/board/solidrun/clearfog/Makefile
new file mode 100644
index 000000000..5cfda3283
--- /dev/null
+++ b/roms/u-boot/board/solidrun/clearfog/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+
+obj-y	:= clearfog.o
diff --git a/roms/u-boot/board/solidrun/clearfog/README b/roms/u-boot/board/solidrun/clearfog/README
new file mode 100644
index 000000000..9375be849
--- /dev/null
+++ b/roms/u-boot/board/solidrun/clearfog/README
@@ -0,0 +1,74 @@
+Update from original Marvell U-Boot to mainline U-Boot:
+-------------------------------------------------------
+
+Generate the U-Boot image with these commands:
+
+$ make clearfog_defconfig
+$ make
+
+The resulting image including the SPL binary with the
+full DDR setup is "u-boot-spl.kwb".
+
+Now all you need to do is copy this image on a SD card.
+For example with this command:
+
+$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1
+
+Please use the correct device node for your setup instead
+of "/dev/sdX" here!
+
+Install U-Boot on eMMC:
+-----------------------
+
+To make SPL load the main U-Boot image from the eMMC boot partition enable
+eMMC boot acknowledgement and boot partition with the following U-Boot
+command:
+
+  mmc partconf 0 1 1 0
+
+Install U-Boot on eMMC boot partition from Linux running on Clearfog:
+
+  echo 0 > /sys/block/mmcblk0boot0/force_ro
+  dd if=u-boot-spl.kwb of=/dev/mmcblk0boot0
+
+Note that the SD card is not accessible when the Clearfog SOM has eMMC.
+Consider initial boot from UART (see below).
+
+Install U-Boot on SATA:
+-----------------------
+
+When loading the main U-Boot image from raw SATA sector, set
+CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR to 0x141.
+
+Boot selection:
+---------------
+
+Before powering up the board, boot selection should be done via the SW1 dip
+switch (0: OFF, 1: ON):
+
+ - SPI:     00010
+ - SD/eMMC: 00111
+ - M.2 SSD: 11100
+ - UART:    01001 [1]
+
+[1]: According to SolidRun's manual, 11110 should be used for UART booting on
+     the ClearFog 'Pro' variant.
+     However, this doesn't work (anymore) at least on Rev. 2.1 (but '01001' as
+     mentionend for the 'Base' variant does).
+
+Boot from UART:
+---------------
+
+Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5)
+to your host.
+
+Set the SW1 DIP switches to UART boot (see above).
+
+Run the following command to initiate U-Boot download:
+
+  ./tools/kwboot -b u-boot-spl.kwb /dev/ttyUSBX
+
+Use the correct UART device node for /dev/ttyUSBX.
+
+When download finishes start your favorite terminal emulator
+on /dev/ttyUSBX.
diff --git a/roms/u-boot/board/solidrun/clearfog/clearfog.c b/roms/u-boot/board/solidrun/clearfog/clearfog.c
new file mode 100644
index 000000000..c920cf8d6
--- /dev/null
+++ b/roms/u-boot/board/solidrun/clearfog/clearfog.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include "../common/tlv_data.h"
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-15t1-clearfog"
+ */
+#define BOARD_GPP_OUT_ENA_LOW	0xffffffff
+#define BOARD_GPP_OUT_ENA_MID	0xffffffff
+
+#define BOARD_GPP_OUT_VAL_LOW	0x0
+#define BOARD_GPP_OUT_VAL_MID	0x0
+#define BOARD_GPP_POL_LOW	0x0
+#define BOARD_GPP_POL_MID	0x0
+
+static struct tlv_data cf_tlv_data;
+
+static void cf_read_tlv_data(void)
+{
+	static bool read_once;
+
+	if (read_once)
+		return;
+	read_once = true;
+
+	read_tlv_data(&cf_tlv_data);
+}
+
+/* The starting board_serdes_map reflects original Clearfog Pro usage */
+static struct serdes_map board_serdes_map[] = {
+	{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+};
+
+void config_cfbase_serdes_map(void)
+{
+	board_serdes_map[4].serdes_type = USB3_HOST0;
+	board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS;
+	board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
+}
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	cf_read_tlv_data();
+
+	/* Apply build configuration options before runtime configuration */
+	if (IS_ENABLED(CONFIG_CLEARFOG_SFP_25GB))
+		board_serdes_map[5].serdes_speed = SERDES_SPEED_3_125_GBPS;
+
+	if (IS_ENABLED(CONFIG_CLEARFOG_CON2_SATA)) {
+		board_serdes_map[4].serdes_type = SATA2;
+		board_serdes_map[4].serdes_speed = SERDES_SPEED_3_GBPS;
+		board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
+		board_serdes_map[4].swap_rx = 1;
+	}
+
+	if (IS_ENABLED(CONFIG_CLEARFOG_CON3_SATA)) {
+		board_serdes_map[2].serdes_type = SATA1;
+		board_serdes_map[2].serdes_speed = SERDES_SPEED_3_GBPS;
+		board_serdes_map[2].serdes_mode = SERDES_DEFAULT_MODE;
+		board_serdes_map[2].swap_rx = 1;
+	}
+
+	/* Apply runtime detection changes */
+	if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) {
+		board_serdes_map[0].serdes_type = PEX0;
+		board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS;
+		board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1;
+	} else if (sr_product_is(&cf_tlv_data, "Clearfog Pro")) {
+		/* handle recognized product as noop, no adjustment required */
+	} else if (sr_product_is(&cf_tlv_data, "Clearfog Base")) {
+		config_cfbase_serdes_map();
+	} else {
+		/*
+		 * Fallback to static default. EEPROM TLV support is not
+		 * enabled, runtime detection failed, hardware support is not
+		 * present, EEPROM is corrupt, or an unrecognized product name
+		 * is present.
+		 */
+		if (IS_ENABLED(CONFIG_SPL_CMD_TLV_EEPROM))
+			puts("EEPROM TLV detection failed: ");
+		puts("Using static config for ");
+		if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) {
+			puts("Clearfog Base.\n");
+			config_cfbase_serdes_map();
+		} else {
+			puts("Clearfog Pro.\n");
+		}
+	}
+
+	*serdes_map_array = board_serdes_map;
+	*count = ARRAY_SIZE(board_serdes_map);
+	return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1600K,	/* speed_bin */
+	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
+	    MV_DDR_DIE_CAP_4GBIT,	/* mem_size */
+	    MV_DDR_FREQ_800,		/* frequency */
+	    0, 0,			/* cas_wl cas_l */
+	    MV_DDR_TEMP_LOW,		/* temperature */
+	    MV_DDR_TIM_DEFAULT} },	/* timing */
+	BUS_MASK_32BIT,			/* Busses mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
+	{ {0} },			/* raw spd data */
+	{0},				/* timing parameters */
+	{ {0} },			/* electrical configuration */
+	{0,},				/* electrical parameters */
+	0x3,				/* clock enable mask */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	struct if_params *ifp = &board_topology_map.interface_params[0];
+
+	cf_read_tlv_data();
+
+	switch (cf_tlv_data.ram_size) {
+	case 4:
+	default:
+		ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
+		break;
+	case 8:
+		ifp->memory_size = MV_DDR_DIE_CAP_8GBIT;
+		break;
+	}
+
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+	writel(0x10400011, MVEBU_MPP_BASE + 0x08);
+	writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
+	writel(0x44400002, MVEBU_MPP_BASE + 0x10);
+	writel(0x41144004, MVEBU_MPP_BASE + 0x14);
+	writel(0x40333333, MVEBU_MPP_BASE + 0x18);
+	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/* Toggle GPIO41 to reset onboard switch and phy */
+	clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
+	clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
+	/* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
+	clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
+	clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
+	mdelay(1);
+	setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
+	setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
+	mdelay(10);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *board = "Clearfog Pro";
+	if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
+		board = "Clearfog Base";
+
+	cf_read_tlv_data();
+	if (strlen(cf_tlv_data.tlv_product_name[0]) > 0)
+		board = cf_tlv_data.tlv_product_name[0];
+
+	printf("Board: SolidRun %s", board);
+	if (strlen(cf_tlv_data.tlv_product_name[1]) > 0)
+		printf(", %s", cf_tlv_data.tlv_product_name[1]);
+	puts("\n");
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	cpu_eth_init(bis); /* Built in controller(s) come first */
+	return pci_eth_init(bis);
+}
+
+int board_late_init(void)
+{
+	if (env_get("fdtfile"))
+		return 0;
+
+	cf_read_tlv_data();
+
+	if (sr_product_is(&cf_tlv_data, "Clearfog Base"))
+		env_set("fdtfile", "armada-388-clearfog-base.dtb");
+	else if (sr_product_is(&cf_tlv_data, "Clearfog GTR S4"))
+		env_set("fdtfile", "armada-385-clearfog-gtr-s4.dtb");
+	else if (sr_product_is(&cf_tlv_data, "Clearfog GTR L8"))
+		env_set("fdtfile", "armada-385-clearfog-gtr-l8.dtb");
+	else if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
+		env_set("fdtfile", "armada-388-clearfog-base.dtb");
+	else
+		env_set("fdtfile", "armada-388-clearfog-pro.dtb");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/solidrun/common/Makefile b/roms/u-boot/board/solidrun/common/Makefile
new file mode 100644
index 000000000..a72ac1b7b
--- /dev/null
+++ b/roms/u-boot/board/solidrun/common/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) SolidRun
+
+obj-$(CONFIG_TARGET_CLEARFOG) += tlv_data.o
diff --git a/roms/u-boot/board/solidrun/common/tlv_data.c b/roms/u-boot/board/solidrun/common/tlv_data.c
new file mode 100644
index 000000000..11d6e4a13
--- /dev/null
+++ b/roms/u-boot/board/solidrun/common/tlv_data.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 SolidRun
+ */
+
+#include <common.h>
+#include <compiler.h>
+#include <tlv_eeprom.h>
+#include "tlv_data.h"
+
+#define SR_TLV_CODE_RAM_SIZE	0x81
+
+static void store_product_name(struct tlvinfo_tlv *tlv_entry,
+			       struct tlv_data *td)
+{
+	int len;
+	char *dest;
+
+	if (strlen(td->tlv_product_name[0]) == 0)
+		dest = td->tlv_product_name[0];
+	else if (strlen(td->tlv_product_name[1]) == 0)
+		dest = td->tlv_product_name[1];
+	else
+		return;
+
+	len = min_t(unsigned int, tlv_entry->length,
+		    sizeof(td->tlv_product_name[0]) - 1);
+	memcpy(dest, tlv_entry->value, len);
+}
+
+static void parse_tlv_vendor_ext(struct tlvinfo_tlv *tlv_entry,
+				 struct tlv_data *td)
+{
+	u8 *val = tlv_entry->value;
+	u32 pen; /* IANA Private Enterprise Numbers */
+
+	if (tlv_entry->length < 5) /* 4 bytes PEN + at least 1 byte type */
+		return;
+
+	/* PEN is big endian */
+	pen = (val[0] << 24) | (val[1] << 16) | (val[2] << 8) | val[3];
+	/* Not a real PEN */
+	if (pen != 0xffffffff)
+		return;
+
+	if (val[4] != SR_TLV_CODE_RAM_SIZE)
+		return;
+	if (tlv_entry->length != 6)
+		return;
+	td->ram_size = val[5];
+}
+
+static void parse_tlv_data(u8 *eeprom, struct tlvinfo_header *hdr,
+			   struct tlvinfo_tlv *entry, struct tlv_data *td)
+{
+	unsigned int tlv_offset, tlv_len;
+
+	tlv_offset = sizeof(struct tlvinfo_header);
+	tlv_len = sizeof(struct tlvinfo_header) + be16_to_cpu(hdr->totallen);
+	while (tlv_offset < tlv_len) {
+		entry = (struct tlvinfo_tlv *)&eeprom[tlv_offset];
+
+		switch (entry->type) {
+		case TLV_CODE_PRODUCT_NAME:
+			store_product_name(entry, td);
+			break;
+		case TLV_CODE_VENDOR_EXT:
+			parse_tlv_vendor_ext(entry, td);
+			break;
+		default:
+			break;
+		}
+
+		tlv_offset += sizeof(struct tlvinfo_tlv) + entry->length;
+	}
+}
+
+void read_tlv_data(struct tlv_data *td)
+{
+	u8 eeprom_data[TLV_TOTAL_LEN_MAX];
+	struct tlvinfo_header *tlv_hdr;
+	struct tlvinfo_tlv *tlv_entry;
+	int ret, i;
+
+	for (i = 0; i < 2; i++) {
+		ret = read_tlvinfo_tlv_eeprom(eeprom_data, &tlv_hdr,
+					      &tlv_entry, i);
+		if (ret < 0)
+			continue;
+		parse_tlv_data(eeprom_data, tlv_hdr, tlv_entry, td);
+	}
+}
+
+bool sr_product_is(const struct tlv_data *td, const char *product)
+{
+	/* Allow prefix sub-string match */
+	if (strncmp(td->tlv_product_name[0], product, strlen(product)) == 0)
+		return true;
+	if (strncmp(td->tlv_product_name[1], product, strlen(product)) == 0)
+		return true;
+
+	return false;
+}
diff --git a/roms/u-boot/board/solidrun/common/tlv_data.h b/roms/u-boot/board/solidrun/common/tlv_data.h
new file mode 100644
index 000000000..a1432e4b8
--- /dev/null
+++ b/roms/u-boot/board/solidrun/common/tlv_data.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 SolidRun
+ */
+
+#ifndef __BOARD_SR_COMMON_H_
+#define __BOARD_SR_COMMON_H_
+
+struct tlv_data {
+	/* Store product name of both SOM and carrier */
+	char tlv_product_name[2][32];
+	unsigned int ram_size;
+};
+
+void read_tlv_data(struct tlv_data *td);
+bool sr_product_is(const struct tlv_data *td, const char *product);
+
+#endif /* __BOARD_SR_COMMON_H_ */
diff --git a/roms/u-boot/board/solidrun/mx6cuboxi/Kconfig b/roms/u-boot/board/solidrun/mx6cuboxi/Kconfig
new file mode 100644
index 000000000..741c1754f
--- /dev/null
+++ b/roms/u-boot/board/solidrun/mx6cuboxi/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6CUBOXI
+
+config SYS_BOARD
+	default "mx6cuboxi"
+
+config SYS_VENDOR
+	default "solidrun"
+
+config SYS_CONFIG_NAME
+	default "mx6cuboxi"
+
+endif
diff --git a/roms/u-boot/board/solidrun/mx6cuboxi/MAINTAINERS b/roms/u-boot/board/solidrun/mx6cuboxi/MAINTAINERS
new file mode 100644
index 000000000..055852166
--- /dev/null
+++ b/roms/u-boot/board/solidrun/mx6cuboxi/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6CUBOXI BOARD
+M:	Baruch Siach <baruch@tkos.co.il>
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/solidrun/mx6cuboxi/
+F:	include/configs/mx6cuboxi.h
+F:	configs/mx6cuboxi_defconfig
diff --git a/roms/u-boot/board/solidrun/mx6cuboxi/Makefile b/roms/u-boot/board/solidrun/mx6cuboxi/Makefile
new file mode 100644
index 000000000..6e5becbd2
--- /dev/null
+++ b/roms/u-boot/board/solidrun/mx6cuboxi/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+
+obj-y  := mx6cuboxi.o
diff --git a/roms/u-boot/board/solidrun/mx6cuboxi/README b/roms/u-boot/board/solidrun/mx6cuboxi/README
new file mode 100644
index 000000000..5d0a45d92
--- /dev/null
+++ b/roms/u-boot/board/solidrun/mx6cuboxi/README
@@ -0,0 +1,21 @@
+How to use U-Boot on Solid-run mx6 Hummingboard and Cubox-i
+-----------------------------------------------------------
+
+- Build U-Boot for Hummingboard/Cubox-i:
+
+$ make mrproper
+$ make mx6cuboxi_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Insert the SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/roms/u-boot/board/solidrun/mx6cuboxi/mx6cuboxi.c b/roms/u-boot/board/solidrun/mx6cuboxi/mx6cuboxi.c
new file mode 100644
index 000000000..3eadc38f6
--- /dev/null
+++ b/roms/u-boot/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -0,0 +1,773 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * Based on SPL code from Solidrun tree, which is:
+ * Author: Tungyi Lin <tungyilin1127@gmail.com>
+ *
+ * Derived from EDM_CF_IMX6 code by TechNexion,Inc
+ * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <env.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <malloc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USB_H1_VBUS	IMX_GPIO_NR(1, 0)
+
+enum board_type {
+	CUBOXI          = 0x00,
+	HUMMINGBOARD    = 0x01,
+	HUMMINGBOARD2   = 0x02,
+	UNKNOWN         = 0x03,
+};
+
+static struct gpio_desc board_detect_desc[5];
+
+#define MEM_STRIDE 0x4000000
+static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
+{
+        volatile u32 *addr;
+        u32          save[64];
+        u32          cnt;
+        u32          size;
+        int          i = 0;
+
+        /* First save the data */
+        for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
+                addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
+                sync ();
+                save[i++] = *addr;
+                sync ();
+        }
+
+        /* First write a signature */
+        * (volatile u32 *)base = 0x12345678;
+        for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) {
+                * (volatile u32 *)((u32)base + size) = size;
+                sync ();
+                if (* (volatile u32 *)((u32)base) == size) {	/* We reached the overlapping address */
+                        break;
+                }
+        }
+
+        /* Restore the data */
+        for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
+                addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
+                sync ();
+                *addr = save[i--];
+                sync ();
+        }
+
+        return (size);
+}
+
+int dram_init(void)
+{
+	u32 max_size = imx_ddr_size();
+
+	gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
+						(u32)max_size);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_RST__SD3_RESET       | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const board_detect[] = {
+	/* These pins are for sensing if it is a CuBox-i or a HummingBoard */
+	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09  | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04   | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08  | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const som_rev_detect[] = {
+	/* These pins are for sensing if it is a CuBox-i or a HummingBoard */
+	IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00  | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04  | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+#ifdef CONFIG_VIDEO_IPUV3
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {
+	{
+		.bus	= -1,
+		.addr	= 0,
+		.pixfmt	= IPU_PIX_FMT_RGB24,
+		.detect	= detect_hdmi,
+		.enable	= do_enable_hdmi,
+		.mode	= {
+			.name           = "HDMI",
+			/* 1024x768@60Hz (VESA)*/
+			.refresh        = 60,
+			.xres           = 1024,
+			.yres           = 768,
+			.pixclock       = 15384,
+			.left_margin    = 160,
+			.right_margin   = 24,
+			.upper_margin   = 29,
+			.lower_margin   = 3,
+			.hsync_len      = 136,
+			.vsync_len      = 6,
+			.sync           = FB_SYNC_EXT,
+			.vmode          = FB_VMODE_NONINTERLACED
+		}
+	}
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+static int setup_display(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+	int timeout = 100000;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
+	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	reg = readl(&ccm->analog_pll_video);
+	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
+	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
+	writel(reg, &ccm->analog_pll_video);
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
+	writel(reg, &ccm->analog_pll_video);
+
+	while (timeout--)
+		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+			break;
+	if (timeout < 0) {
+		printf("Warning: video pll lock timeout!\n");
+		return -ETIMEDOUT;
+	}
+
+	reg = readl(&ccm->analog_pll_video);
+	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
+	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
+	writel(reg, &ccm->analog_pll_video);
+
+	/* gate ipu1_di0_clk */
+	clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+	/* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
+	reg = readl(&ccm->chsccdr);
+	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
+		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
+		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
+	       (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
+	       (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &ccm->chsccdr);
+
+	/* enable ipu1_di0_clk */
+	setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+	return 0;
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+static int setup_fec(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	ret = enable_fec_anatop_clock(0, ENET_25MHZ);
+	if (ret)
+		return ret;
+
+	/* set gpr1[ENET_CLK_SEL] */
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+	setup_fec();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	int ret = 0;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_VIDEO_IPUV3
+	ret = setup_display();
+#endif
+
+	return ret;
+}
+
+static int request_detect_gpios(void)
+{
+	int node;
+	int ret;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
+		"solidrun,hummingboard-detect");
+	if (node < 0)
+		return -ENODEV;
+
+	ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
+		"detect-gpios", board_detect_desc,
+		ARRAY_SIZE(board_detect_desc), GPIOD_IS_IN);
+
+	return ret;
+}
+
+static int free_detect_gpios(void)
+{
+	return gpio_free_list_nodev(board_detect_desc,
+		ARRAY_SIZE(board_detect_desc));
+}
+
+static enum board_type board_type(void)
+{
+	int val1, val2, val3;
+
+	SETUP_IOMUX_PADS(board_detect);
+
+	/*
+	 * Machine selection -
+	 * Machine      val1, val2, val3
+	 * ----------------------------
+	 * HB2            x     x    0
+	 * HB rev 3.x     x     0    x
+	 * CBi            0     1    x
+	 * HB             1     1    x
+	 */
+
+	gpio_direction_input(IMX_GPIO_NR(2, 8));
+	val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
+
+	if (val3 == 0)
+		return HUMMINGBOARD2;
+
+	gpio_direction_input(IMX_GPIO_NR(3, 4));
+	val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
+
+	if (val2 == 0)
+		return HUMMINGBOARD;
+
+	gpio_direction_input(IMX_GPIO_NR(4, 9));
+	val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
+
+	if (val1 == 0) {
+		return CUBOXI;
+	} else {
+		return HUMMINGBOARD;
+	}
+}
+
+static bool is_rev_15_som(void)
+{
+	int val1, val2;
+	SETUP_IOMUX_PADS(som_rev_detect);
+
+	val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
+	val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
+
+	if (val1 == 1 && val2 == 0)
+		return true;
+
+	return false;
+}
+
+static bool has_emmc(void)
+{
+	struct mmc *mmc;
+	mmc = find_mmc_device(2);
+	if (!mmc)
+		return 0;
+	return (mmc_get_op_cond(mmc) < 0) ? 0 : 1;
+}
+
+int checkboard(void)
+{
+	request_detect_gpios();
+
+	switch (board_type()) {
+	case CUBOXI:
+		puts("Board: MX6 Cubox-i");
+		break;
+	case HUMMINGBOARD:
+		puts("Board: MX6 HummingBoard");
+		break;
+	case HUMMINGBOARD2:
+		puts("Board: MX6 HummingBoard2");
+		break;
+	case UNKNOWN:
+	default:
+		puts("Board: Unknown\n");
+		goto out;
+	}
+
+	if (is_rev_15_som())
+		puts(" (som rev 1.5)\n");
+	else
+		puts("\n");
+
+	free_detect_gpios();
+out:
+	return 0;
+}
+
+/* Override the default implementation, DT model is not accurate */
+int show_board_info(void)
+{
+	return checkboard();
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	request_detect_gpios();
+
+	switch (board_type()) {
+	case CUBOXI:
+		env_set("board_name", "CUBOXI");
+		break;
+	case HUMMINGBOARD:
+		env_set("board_name", "HUMMINGBOARD");
+		break;
+	case HUMMINGBOARD2:
+		env_set("board_name", "HUMMINGBOARD2");
+		break;
+	case UNKNOWN:
+	default:
+		env_set("board_name", "CUBOXI");
+	}
+
+	if (is_mx6dq())
+		env_set("board_rev", "MX6Q");
+	else
+		env_set("board_rev", "MX6DL");
+
+	if (is_rev_15_som())
+		env_set("som_rev", "V15");
+
+	if (has_emmc())
+		env_set("has_emmc", "yes");
+
+	free_detect_gpios();
+#endif
+
+	return 0;
+}
+
+/*
+ * This is not a perfect match. Avoid dependency on the DM GPIO driver needed
+ * for accurate board detection. Hummingboard2 DT is good enough for U-Boot on
+ * all Hummingboard/Cubox-i platforms.
+ */
+int board_fit_config_name_match(const char *name)
+{
+	char tmp_name[36];
+
+	snprintf(tmp_name, sizeof(tmp_name), "%s-hummingboard2-emmc-som-v15",
+			is_mx6dq() ? "imx6q" : "imx6dl");
+
+	return strcmp(name, tmp_name);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned int reg = readl(&psrc->sbmr1) >> 11;
+	u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK;
+	unsigned int bmode = readl(&src_base->sbmr2);
+
+	/* If bmode is serial or USB phy is active, return serial */
+	if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) {
+		spl_boot_list[0] = BOOT_DEVICE_BOARD;
+		return;
+	}
+
+	switch (boot_mode >> IMX6_BMODE_SHIFT) {
+	case IMX6_BMODE_SD:
+	case IMX6_BMODE_ESD:
+	case IMX6_BMODE_MMC:
+	case IMX6_BMODE_EMMC:
+		/*
+		 * Upon reading BOOT_CFG register the following map is done:
+		 * Bit 11 and 12 of BOOT_CFG register can determine the current
+		 * mmc port
+		 * 0x1                  SD2
+		 * 0x2                  SD3
+		 */
+
+		reg &= 0x3; /* Only care about bottom 2 bits */
+		switch (reg) {
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			spl_boot_list[0] = BOOT_DEVICE_MMC1;
+			break;
+		case 2:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			spl_boot_list[0] = BOOT_DEVICE_MMC2;
+			break;
+		}
+		break;
+	default:
+		/* By default use USB downloader */
+		spl_boot_list[0] = BOOT_DEVICE_BOARD;
+		break;
+	}
+
+	/* As a last resort, use serial downloader */
+	spl_boot_list[1] = BOOT_DEVICE_BOARD;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <asm/arch/mx6-ddr.h>
+static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
+	.dram_sdclk_0 =  0x00020030,
+	.dram_sdclk_1 =  0x00020030,
+	.dram_cas =  0x00020030,
+	.dram_ras =  0x00020030,
+	.dram_reset =  0x000c0030,
+	.dram_sdcke0 =  0x00003000,
+	.dram_sdcke1 =  0x00003000,
+	.dram_sdba2 =  0x00000000,
+	.dram_sdodt0 =  0x00003030,
+	.dram_sdodt1 =  0x00003030,
+	.dram_sdqs0 =  0x00000030,
+	.dram_sdqs1 =  0x00000030,
+	.dram_sdqs2 =  0x00000030,
+	.dram_sdqs3 =  0x00000030,
+	.dram_sdqs4 =  0x00000030,
+	.dram_sdqs5 =  0x00000030,
+	.dram_sdqs6 =  0x00000030,
+	.dram_sdqs7 =  0x00000030,
+	.dram_dqm0 =  0x00020030,
+	.dram_dqm1 =  0x00020030,
+	.dram_dqm2 =  0x00020030,
+	.dram_dqm3 =  0x00020030,
+	.dram_dqm4 =  0x00020030,
+	.dram_dqm5 =  0x00020030,
+	.dram_dqm6 =  0x00020030,
+	.dram_dqm7 =  0x00020030,
+};
+
+static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
+	.dram_sdclk_0 = 0x00000028,
+	.dram_sdclk_1 = 0x00000028,
+	.dram_cas =	0x00000028,
+	.dram_ras =	0x00000028,
+	.dram_reset =	0x000c0028,
+	.dram_sdcke0 =	0x00003000,
+	.dram_sdcke1 =	0x00003000,
+	.dram_sdba2 =	0x00000000,
+	.dram_sdodt0 =	0x00003030,
+	.dram_sdodt1 =	0x00003030,
+	.dram_sdqs0 =	0x00000028,
+	.dram_sdqs1 =	0x00000028,
+	.dram_sdqs2 =	0x00000028,
+	.dram_sdqs3 =	0x00000028,
+	.dram_sdqs4 =	0x00000028,
+	.dram_sdqs5 =	0x00000028,
+	.dram_sdqs6 =	0x00000028,
+	.dram_sdqs7 =	0x00000028,
+	.dram_dqm0 =	0x00000028,
+	.dram_dqm1 =	0x00000028,
+	.dram_dqm2 =	0x00000028,
+	.dram_dqm3 =	0x00000028,
+	.dram_dqm4 =	0x00000028,
+	.dram_dqm5 =	0x00000028,
+	.dram_dqm6 =	0x00000028,
+	.dram_dqm7 =	0x00000028,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
+	.grp_ddr_type =  0x000C0000,
+	.grp_ddrmode_ctl =  0x00020000,
+	.grp_ddrpke =  0x00000000,
+	.grp_addds =  0x00000030,
+	.grp_ctlds =  0x00000030,
+	.grp_ddrmode =  0x00020000,
+	.grp_b0ds =  0x00000030,
+	.grp_b1ds =  0x00000030,
+	.grp_b2ds =  0x00000030,
+	.grp_b3ds =  0x00000030,
+	.grp_b4ds =  0x00000030,
+	.grp_b5ds =  0x00000030,
+	.grp_b6ds =  0x00000030,
+	.grp_b7ds =  0x00000030,
+};
+
+static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = 0x00000028,
+	.grp_ctlds = 0x00000028,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = 0x00000028,
+	.grp_b1ds = 0x00000028,
+	.grp_b2ds = 0x00000028,
+	.grp_b3ds = 0x00000028,
+	.grp_b4ds = 0x00000028,
+	.grp_b5ds = 0x00000028,
+	.grp_b6ds = 0x00000028,
+	.grp_b7ds = 0x00000028,
+};
+
+/* microSOM with Dual processor and 1GB memory */
+static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x00000000,
+	.p0_mpwldectrl1 =  0x00000000,
+	.p1_mpwldectrl0 =  0x00000000,
+	.p1_mpwldectrl1 =  0x00000000,
+	.p0_mpdgctrl0 =    0x0314031c,
+	.p0_mpdgctrl1 =    0x023e0304,
+	.p1_mpdgctrl0 =    0x03240330,
+	.p1_mpdgctrl1 =    0x03180260,
+	.p0_mprddlctl =    0x3630323c,
+	.p1_mprddlctl =    0x3436283a,
+	.p0_mpwrdlctl =    0x36344038,
+	.p1_mpwrdlctl =    0x422a423c,
+};
+
+/* microSOM with Quad processor and 2GB memory */
+static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x00000000,
+	.p0_mpwldectrl1 =  0x00000000,
+	.p1_mpwldectrl0 =  0x00000000,
+	.p1_mpwldectrl1 =  0x00000000,
+	.p0_mpdgctrl0 =    0x0314031c,
+	.p0_mpdgctrl1 =    0x023e0304,
+	.p1_mpdgctrl0 =    0x03240330,
+	.p1_mpdgctrl1 =    0x03180260,
+	.p0_mprddlctl =    0x3630323c,
+	.p1_mprddlctl =    0x3436283a,
+	.p0_mpwrdlctl =    0x36344038,
+	.p1_mpwrdlctl =    0x422a423c,
+};
+
+/* microSOM with Solo processor and 512MB memory */
+static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x0045004D,
+	.p0_mpwldectrl1 = 0x003A0047,
+	.p0_mpdgctrl0 =   0x023C0224,
+	.p0_mpdgctrl1 =   0x02000220,
+	.p0_mprddlctl =   0x44444846,
+	.p0_mpwrdlctl =   0x32343032,
+};
+
+/* microSOM with Dual lite processor and 1GB memory */
+static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x0045004D,
+	.p0_mpwldectrl1 =  0x003A0047,
+	.p1_mpwldectrl0 =  0x001F001F,
+	.p1_mpwldectrl1 =  0x00210035,
+	.p0_mpdgctrl0 =    0x023C0224,
+	.p0_mpdgctrl1 =    0x02000220,
+	.p1_mpdgctrl0 =    0x02200220,
+	.p1_mpdgctrl1 =    0x02040208,
+	.p0_mprddlctl =    0x44444846,
+	.p1_mprddlctl =    0x4042463C,
+	.p0_mpwrdlctl =    0x32343032,
+	.p1_mpwrdlctl =    0x36363430,
+};
+
+static struct mx6_ddr3_cfg mem_ddr_2g = {
+	.mem_speed = 1600,
+	.density   = 2,
+	.width     = 16,
+	.banks     = 8,
+	.rowaddr   = 14,
+	.coladdr   = 10,
+	.pagesz    = 2,
+	.trcd      = 1375,
+	.trcmin    = 4875,
+	.trasmin   = 3500,
+};
+
+static struct mx6_ddr3_cfg mem_ddr_4g = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 16,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(int width)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus: 0=16, 1=32, 2=64 */
+		.dsize = width / 32,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density = 32,	/* 32Gb per CS */
+		.ncs = 1,		/* single chip select */
+		.cs1_mirror = 0,
+		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
+		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
+		.walat = 1,	/* Write additional latency */
+		.ralat = 5,	/* Read additional latency */
+		.mif3_mode = 3,	/* Command prediction working mode */
+		.bi_on = 1,	/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
+	};
+
+	if (is_mx6dq())
+		mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
+	else
+		mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
+
+	if (is_cpu_type(MXC_CPU_MX6D))
+		mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
+	else if (is_cpu_type(MXC_CPU_MX6Q))
+		mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
+	else if (is_cpu_type(MXC_CPU_MX6DL))
+		mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
+	else if (is_cpu_type(MXC_CPU_MX6SOLO))
+		mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	if (is_cpu_type(MXC_CPU_MX6SOLO))
+		spl_dram_init(32);
+	else
+		spl_dram_init(64);
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/roms/u-boot/board/somlabs/visionsom-6ull/Kconfig b/roms/u-boot/board/somlabs/visionsom-6ull/Kconfig
new file mode 100644
index 000000000..37408aa79
--- /dev/null
+++ b/roms/u-boot/board/somlabs/visionsom-6ull/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SOMLABS_VISIONSOM_6ULL
+
+config SYS_BOARD
+	default "visionsom-6ull"
+
+config SYS_VENDOR
+	default "somlabs"
+
+config SYS_CONFIG_NAME
+	default "somlabs_visionsom_6ull"
+
+endif
diff --git a/roms/u-boot/board/somlabs/visionsom-6ull/MAINTAINERS b/roms/u-boot/board/somlabs/visionsom-6ull/MAINTAINERS
new file mode 100644
index 000000000..905c000bc
--- /dev/null
+++ b/roms/u-boot/board/somlabs/visionsom-6ull/MAINTAINERS
@@ -0,0 +1,6 @@
+VISIONSOM-6ULL BOARD
+M:	Arkadiusz Karas <arkadiusz.karas@somlabs.com>
+S:	Maintained
+F:	board/somlabs/visionsom-6ull/
+F:	include/configs/somlabs_visionsom_6ull.h
+F:	configs/somlabs_visionsom_6ull_defconfig
diff --git a/roms/u-boot/board/somlabs/visionsom-6ull/Makefile b/roms/u-boot/board/somlabs/visionsom-6ull/Makefile
new file mode 100644
index 000000000..9c3768aa4
--- /dev/null
+++ b/roms/u-boot/board/somlabs/visionsom-6ull/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2019 Arkadiusz Karas <arkadiusz.karas@somlabs.com>
+
+obj-y  := visionsom-6ull.o
diff --git a/roms/u-boot/board/somlabs/visionsom-6ull/imximage.cfg b/roms/u-boot/board/somlabs/visionsom-6ull/imximage.cfg
new file mode 100644
index 000000000..b49a2df6d
--- /dev/null
+++ b/roms/u-boot/board/somlabs/visionsom-6ull/imximage.cfg
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 A. Karas
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : sd
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Micron MT41K256M16TW-107 */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x00000030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000000
+DATA 4 0x021B083C 0x41570155
+DATA 4 0x021B0848 0x4040474A
+DATA 4 0x021B0850 0x40405550
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00921012
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D0B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0x84180000
+DATA 4 0x021B0890 0x23400A38
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
diff --git a/roms/u-boot/board/somlabs/visionsom-6ull/visionsom-6ull.c b/roms/u-boot/board/somlabs/visionsom-6ull/visionsom-6ull.c
new file mode 100644
index 000000000..076c641d8
--- /dev/null
+++ b/roms/u-boot/board/somlabs/visionsom-6ull/visionsom-6ull.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2019 A. Karas, SomLabs
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	/*
+	 * Use 50M anatop loopback REF_CLK1 for ENET1,
+	 * clear gpr1[13], set gpr1[17].
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+	return devno;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	if (is_cpu_type(MXC_CPU_MX6ULL))
+		env_set("board", "visionsom-6ull");
+	else
+		env_set("board", "visionsom-6ul");
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: SoMLabs VisionSOM-6UL%s\n",
+	       is_cpu_type(MXC_CPU_MX6ULL) ? "L" : "");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/spear/spear300/Kconfig b/roms/u-boot/board/spear/spear300/Kconfig
new file mode 100644
index 000000000..27360f32e
--- /dev/null
+++ b/roms/u-boot/board/spear/spear300/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SPEAR300
+
+config SYS_BOARD
+	default "spear300"
+
+config SYS_VENDOR
+	default "spear"
+
+config SYS_SOC
+	default "spear"
+
+config SYS_CONFIG_NAME
+	default "spear3xx_evb"
+
+endif
diff --git a/roms/u-boot/board/spear/spear300/MAINTAINERS b/roms/u-boot/board/spear/spear300/MAINTAINERS
new file mode 100644
index 000000000..07152aefb
--- /dev/null
+++ b/roms/u-boot/board/spear/spear300/MAINTAINERS
@@ -0,0 +1,13 @@
+SPEAR300 BOARD
+M:	Vipin Kumar <vipin.kumar@st.com>
+S:	Maintained
+F:	board/spear/spear300/
+F:	include/configs/spear3xx_evb.h
+F:	configs/spear300_defconfig
+
+SPEAR300_NAND BOARD
+#M:	-
+S:	Maintained
+F:	configs/spear300_nand_defconfig
+F:	configs/spear300_usbtty_defconfig
+F:	configs/spear300_usbtty_nand_defconfig
diff --git a/roms/u-boot/board/spear/spear300/Makefile b/roms/u-boot/board/spear/spear300/Makefile
new file mode 100644
index 000000000..d638bfc3f
--- /dev/null
+++ b/roms/u-boot/board/spear/spear300/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= spear300.o
diff --git a/roms/u-boot/board/spear/spear300/spear300.c b/roms/u-boot/board/spear/spear300/spear300.c
new file mode 100644
index 000000000..a59453839
--- /dev/null
+++ b/roms/u-boot/board/spear/spear300/spear300.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/mach-types.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+int board_init(void)
+{
+	return spear_board_init(MACH_TYPE_SPEAR300);
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+void board_nand_init()
+{
+	struct misc_regs *const misc_regs_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
+
+#if defined(CONFIG_NAND_FSMC)
+	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG30) ||
+	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG31)) {
+
+		fsmc_nand_init(nand);
+	}
+#endif
+	return;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int ret = 0;
+
+#if defined(CONFIG_ETH_DESIGNWARE)
+	u32 interface = PHY_INTERFACE_MODE_MII;
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
+		ret++;
+#endif
+	return ret;
+}
diff --git a/roms/u-boot/board/spear/spear310/Kconfig b/roms/u-boot/board/spear/spear310/Kconfig
new file mode 100644
index 000000000..0c95fa35a
--- /dev/null
+++ b/roms/u-boot/board/spear/spear310/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SPEAR310
+
+config SYS_BOARD
+	default "spear310"
+
+config SYS_VENDOR
+	default "spear"
+
+config SYS_SOC
+	default "spear"
+
+config SYS_CONFIG_NAME
+	default "spear3xx_evb"
+
+endif
diff --git a/roms/u-boot/board/spear/spear310/MAINTAINERS b/roms/u-boot/board/spear/spear310/MAINTAINERS
new file mode 100644
index 000000000..4f9aa15b8
--- /dev/null
+++ b/roms/u-boot/board/spear/spear310/MAINTAINERS
@@ -0,0 +1,15 @@
+SPEAR310 BOARD
+M:	Vipin Kumar <vipin.kumar@st.com>
+S:	Maintained
+F:	board/spear/spear310/
+F:	include/configs/spear3xx_evb.h
+F:	configs/spear310_defconfig
+
+SPEAR310_NAND BOARD
+#M:	-
+S:	Maintained
+F:	configs/spear310_nand_defconfig
+F:	configs/spear310_pnor_defconfig
+F:	configs/spear310_usbtty_defconfig
+F:	configs/spear310_usbtty_nand_defconfig
+F:	configs/spear310_usbtty_pnor_defconfig
diff --git a/roms/u-boot/board/spear/spear310/Makefile b/roms/u-boot/board/spear/spear310/Makefile
new file mode 100644
index 000000000..581d41432
--- /dev/null
+++ b/roms/u-boot/board/spear/spear310/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= spear310.o
diff --git a/roms/u-boot/board/spear/spear310/spear310.c b/roms/u-boot/board/spear/spear310/spear310.c
new file mode 100644
index 000000000..b4c3c0c5c
--- /dev/null
+++ b/roms/u-boot/board/spear/spear310/spear310.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/mach-types.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+int board_init(void)
+{
+	return spear_board_init(MACH_TYPE_SPEAR310);
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+void board_nand_init()
+{
+	struct misc_regs *const misc_regs_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
+
+#if defined(CONFIG_NAND_FSMC)
+	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG30) ||
+	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG31)) {
+
+		fsmc_nand_init(nand);
+	}
+#endif
+	return;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int ret = 0;
+
+#if defined(CONFIG_ETH_DESIGNWARE)
+	u32 interface = PHY_INTERFACE_MODE_MII;
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
+		ret++;
+#endif
+#if defined(CONFIG_MACB)
+	if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
+				CONFIG_MACB0_PHY) >= 0)
+		ret++;
+
+	if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE,
+				CONFIG_MACB1_PHY) >= 0)
+		ret++;
+
+	if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE,
+				CONFIG_MACB2_PHY) >= 0)
+		ret++;
+
+	if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE,
+				CONFIG_MACB3_PHY) >= 0)
+		ret++;
+#endif
+	return ret;
+}
diff --git a/roms/u-boot/board/spear/spear320/Kconfig b/roms/u-boot/board/spear/spear320/Kconfig
new file mode 100644
index 000000000..df176230f
--- /dev/null
+++ b/roms/u-boot/board/spear/spear320/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SPEAR320
+
+config SYS_BOARD
+	default "spear320"
+
+config SYS_VENDOR
+	default "spear"
+
+config SYS_SOC
+	default "spear"
+
+config SYS_CONFIG_NAME
+	default "spear3xx_evb"
+
+endif
diff --git a/roms/u-boot/board/spear/spear320/MAINTAINERS b/roms/u-boot/board/spear/spear320/MAINTAINERS
new file mode 100644
index 000000000..bf7809230
--- /dev/null
+++ b/roms/u-boot/board/spear/spear320/MAINTAINERS
@@ -0,0 +1,15 @@
+SPEAR320 BOARD
+M:	Vipin Kumar <vipin.kumar@st.com>
+S:	Maintained
+F:	board/spear/spear320/
+F:	include/configs/spear3xx_evb.h
+F:	configs/spear320_defconfig
+
+SPEAR320_NAND BOARD
+#M:	-
+S:	Maintained
+F:	configs/spear320_nand_defconfig
+F:	configs/spear320_pnor_defconfig
+F:	configs/spear320_usbtty_defconfig
+F:	configs/spear320_usbtty_nand_defconfig
+F:	configs/spear320_usbtty_pnor_defconfig
diff --git a/roms/u-boot/board/spear/spear320/Makefile b/roms/u-boot/board/spear/spear320/Makefile
new file mode 100644
index 000000000..062cbc417
--- /dev/null
+++ b/roms/u-boot/board/spear/spear320/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= spear320.o
diff --git a/roms/u-boot/board/spear/spear320/spear320.c b/roms/u-boot/board/spear/spear320/spear320.c
new file mode 100644
index 000000000..291337b80
--- /dev/null
+++ b/roms/u-boot/board/spear/spear320/spear320.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/mach-types.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+
+#define PLGPIO_SEL_36	0xb3000028
+#define PLGPIO_IO_36	0xb3000038
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+static void spear_phy_reset(void)
+{
+	writel(0x10, PLGPIO_IO_36);
+	writel(0x10, PLGPIO_SEL_36);
+}
+
+int board_init(void)
+{
+	spear_phy_reset();
+	return spear_board_init(MACH_TYPE_SPEAR320);
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+void board_nand_init()
+{
+	struct misc_regs *const misc_regs_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
+
+#if defined(CONFIG_NAND_FSMC)
+	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG30) ||
+	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG31)) {
+
+		fsmc_nand_init(nand);
+	}
+#endif
+
+	return;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int ret = 0;
+
+#if defined(CONFIG_ETH_DESIGNWARE)
+	u32 interface = PHY_INTERFACE_MODE_MII;
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
+		ret++;
+#endif
+#if defined(CONFIG_MACB)
+	if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
+				CONFIG_MACB0_PHY) >= 0)
+		ret++;
+#endif
+	return ret;
+}
diff --git a/roms/u-boot/board/spear/spear600/Kconfig b/roms/u-boot/board/spear/spear600/Kconfig
new file mode 100644
index 000000000..d562e64f0
--- /dev/null
+++ b/roms/u-boot/board/spear/spear600/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SPEAR600
+
+config SYS_BOARD
+	default "spear600"
+
+config SYS_VENDOR
+	default "spear"
+
+config SYS_SOC
+	default "spear"
+
+config SYS_CONFIG_NAME
+	default "spear6xx_evb"
+
+endif
diff --git a/roms/u-boot/board/spear/spear600/MAINTAINERS b/roms/u-boot/board/spear/spear600/MAINTAINERS
new file mode 100644
index 000000000..ddcd11a87
--- /dev/null
+++ b/roms/u-boot/board/spear/spear600/MAINTAINERS
@@ -0,0 +1,13 @@
+SPEAR600 BOARD
+M:	Vipin Kumar <vipin.kumar@st.com>
+S:	Maintained
+F:	board/spear/spear600/
+F:	include/configs/spear6xx_evb.h
+F:	configs/spear600_defconfig
+
+SPEAR600_NAND BOARD
+#M:	-
+S:	Maintained
+F:	configs/spear600_nand_defconfig
+F:	configs/spear600_usbtty_defconfig
+F:	configs/spear600_usbtty_nand_defconfig
diff --git a/roms/u-boot/board/spear/spear600/Makefile b/roms/u-boot/board/spear/spear600/Makefile
new file mode 100644
index 000000000..d25163e3f
--- /dev/null
+++ b/roms/u-boot/board/spear/spear600/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= spear600.o
diff --git a/roms/u-boot/board/spear/spear600/spear600.c b/roms/u-boot/board/spear/spear600/spear600.c
new file mode 100644
index 000000000..4706c52c1
--- /dev/null
+++ b/roms/u-boot/board/spear/spear600/spear600.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/mach-types.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+int board_init(void)
+{
+	return spear_board_init(MACH_TYPE_SPEAR600);
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+void board_nand_init()
+{
+	struct misc_regs *const misc_regs_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
+
+#if defined(CONFIG_NAND_FSMC)
+	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
+		fsmc_nand_init(nand);
+#endif
+	return;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int ret = 0;
+
+#if defined(CONFIG_ETH_DESIGNWARE)
+	u32 interface = PHY_INTERFACE_MODE_MII;
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
+		ret++;
+#endif
+	return ret;
+}
diff --git a/roms/u-boot/board/spear/x600/Kconfig b/roms/u-boot/board/spear/x600/Kconfig
new file mode 100644
index 000000000..59f2b1ef5
--- /dev/null
+++ b/roms/u-boot/board/spear/x600/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_X600
+
+config SPL_LDSCRIPT
+	default "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
+
+config SYS_BOARD
+	default "x600"
+
+config SYS_VENDOR
+	default "spear"
+
+config SYS_SOC
+	default "spear"
+
+config SYS_CONFIG_NAME
+	default "x600"
+
+endif
diff --git a/roms/u-boot/board/spear/x600/MAINTAINERS b/roms/u-boot/board/spear/x600/MAINTAINERS
new file mode 100644
index 000000000..bff682494
--- /dev/null
+++ b/roms/u-boot/board/spear/x600/MAINTAINERS
@@ -0,0 +1,6 @@
+X600 BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/spear/x600/
+F:	include/configs/x600.h
+F:	configs/x600_defconfig
diff --git a/roms/u-boot/board/spear/x600/Makefile b/roms/u-boot/board/spear/x600/Makefile
new file mode 100644
index 000000000..3ed841577
--- /dev/null
+++ b/roms/u-boot/board/spear/x600/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-y	:= fpga.o x600.o
+endif
diff --git a/roms/u-boot/board/spear/x600/fpga.c b/roms/u-boot/board/spear/x600/fpga.c
new file mode 100644
index 000000000..5140694b9
--- /dev/null
+++ b/roms/u-boot/board/spear/x600/fpga.c
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <log.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_ssp.h>
+#include <linux/delay.h>
+
+/*
+ * FPGA program pin configuration on X600:
+ *
+ * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
+ * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
+ * 16bit serial writes via this SSP port to write the data bits into the
+ * FPGA.
+ */
+#define CONFIG_SYS_FPGA_PROG		2
+#define CONFIG_SYS_FPGA_DONE		3
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+static void fpga_reset(int assert)
+{
+	/*
+	 * On x600 we have no means to toggle the FPGA reset signal
+	 */
+	debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
+}
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+static int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+	debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
+
+	gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
+
+	return assert;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+static int fpga_init_fn(int cookie)
+{
+	static int state;
+
+	debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
+
+	/*
+	 * On x600, the FPGA INIT signal is not connected to the SoC.
+	 * We can't read the INIT status. Let's return the "correct"
+	 * INIT signal state generated via a local state-machine.
+	 */
+	if (++state == 1) {
+		return 1;
+	} else {
+		state = 0;
+		return 0;
+	}
+}
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+static int fpga_done_fn(int cookie)
+{
+	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+
+	/*
+	 * Wait for Tx-FIFO to become empty before looking for DONE
+	 */
+	while (!(readl(&ssp->sspsr) & SSPSR_TFE))
+		;
+
+	if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
+		return 1;
+	else
+		return 0;
+}
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+static int fpga_pre_config_fn(int cookie)
+{
+	debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
+	fpga_reset(true);
+
+	return 0;
+}
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+static int fpga_post_config_fn(int cookie)
+{
+	int rc = 0;
+
+	debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
+
+	fpga_reset(true);
+	udelay(100);
+	fpga_reset(false);
+	udelay(100);
+
+	return rc;
+}
+
+static int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	/*
+	 * No dedicated clock signal on x600 (data & clock generated)
+	 * in SSP interface. So we don't have to do anything here.
+	 */
+	return assert_clk;
+}
+
+static int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+	static int count;
+	static u16 data;
+
+	/*
+	 * First collect 16 bits of data
+	 */
+	data = data << 1;
+	if (assert_write)
+		data |= 1;
+
+	/*
+	 * If 16 bits are not available, return for more bits
+	 */
+	count++;
+	if (count != 16)
+		return assert_write;
+
+	count = 0;
+
+	/*
+	 * Wait for Tx-FIFO to become ready
+	 */
+	while (!(readl(&ssp->sspsr) & SSPSR_TNF))
+		;
+
+	/* Send 16 bits to FPGA via SSP bus */
+	writel(data, &ssp->sspdr);
+
+	return assert_write;
+}
+
+static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_clk_fn,
+	fpga_init_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	fpga_post_config_fn,
+};
+
+static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+	XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
+};
+
+/*
+ * Initialize the SelectMap interface.  We assume that the mode and the
+ * initial state of all of the port pins have already been set!
+ */
+static void fpga_serialslave_init(void)
+{
+	debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
+	fpga_pgm_fn(false, false, 0);	/* make sure program pin is inactive */
+}
+
+static int expi_setup(int freq)
+{
+	struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
+
+	pll2_m = (freq * 2) / 1000;
+	pll2_n = 15;
+	pll2_p = 1;
+	expi_x = 1;
+	expi_y = 2;
+
+	/*
+	 * Disable reset, Low compression, Disable retiming, Enable Expi,
+	 * Enable soft reset, DMA, PLL2, Internal
+	 */
+	writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
+	       EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
+	       EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
+	       &misc->expi_clk_cfg);
+
+	/*
+	 * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
+	 * Enable PLL2, Disable reset
+	 */
+	writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
+	writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
+	       PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
+
+	/*
+	 * Disable soft reset
+	 */
+	clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
+
+	return 0;
+}
+
+/*
+ * Initialize the fpga
+ */
+int x600_init_fpga(void)
+{
+	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+	struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	/* Enable SSP2 clock */
+	writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
+	       &misc->periph1_clken);
+
+	/* Set EXPI clock to 45 MHz */
+	expi_setup(45000);
+
+	/* Configure GPIO directions */
+	gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
+	gpio_direction_input(CONFIG_SYS_FPGA_DONE);
+
+	writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
+	writel(SSPCR1_SSE, &ssp->sspcr1);
+
+	/*
+	 * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
+	 * speed.
+	 *
+	 * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
+	 * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
+	 */
+	writel(2, &ssp->sspcpsr);
+
+	fpga_init();
+	fpga_serialslave_init();
+
+	debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
+	fpga_add(fpga_xilinx, &fpga[0]);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/spear/x600/fpga.h b/roms/u-boot/board/spear/x600/fpga.h
new file mode 100644
index 000000000..f5e6f31a4
--- /dev/null
+++ b/roms/u-boot/board/spear/x600/fpga.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ */
+
+int x600_init_fpga(void);
diff --git a/roms/u-boot/board/spear/x600/x600.c b/roms/u-boot/board/spear/x600/x600.c
new file mode 100644
index 000000000..9c30581ec
--- /dev/null
+++ b/roms/u-boot/board/spear/x600/x600.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <flash.h>
+#include <init.h>
+#include <micrel.h>
+#include <nand.h>
+#include <net.h>
+#include <netdev.h>
+#include <phy.h>
+#include <rtc.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <linux/mtd/fsmc_nand.h>
+#include "fpga.h"
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+int board_init(void)
+{
+	/*
+	 * X600 is equipped with an M41T82 RTC. This RTC has the
+	 * HT bit (Halt Update), which needs to be cleared upon
+	 * power-up. Otherwise the RTC is halted.
+	 */
+	rtc_reset();
+
+	return spear_board_init(MACH_TYPE_SPEAR600);
+}
+
+int board_late_init(void)
+{
+	/*
+	 * Monitor and env protection on by default
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
+		      CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
+		      2 * CONFIG_ENV_SECT_SIZE - 1,
+		      &flash_info[0]);
+
+	/* Init FPGA subsystem */
+	x600_init_fpga();
+
+	return 0;
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+void board_nand_init(void)
+{
+	struct misc_regs *const misc_regs_p =
+		(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
+
+	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
+		fsmc_nand_init(nand);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	unsigned short id1, id2;
+
+	/* check whether KSZ9031 or AR8035 has to be configured */
+	id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
+	id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
+
+	if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
+		/* PHY configuration for Micrel KSZ9031 */
+		printf("PHY KSZ9031 detected - ");
+
+		phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
+
+		/* control data pad skew - devaddr = 0x02, register = 0x04 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x03FF);
+	} else {
+		/* PHY configuration for Vitesse VSC8641 */
+		printf("PHY VSC8641 detected - ");
+
+		/* Extended PHY control 1, select GMII */
+		phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
+
+		/* Software reset necessary after GMII mode selction */
+		phy_reset(phydev);
+
+		/* Enable extended page register access */
+		phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
+
+		/* 17e: Enhanced LED behavior, needs to be written twice */
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+
+		/* 16e: Enhanced LED method select */
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
+
+		/* Disable extended page register access */
+		phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
+
+		/* Enable clock output pin */
+		phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
+	}
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int ret = 0;
+
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE,
+				  PHY_INTERFACE_MODE_GMII) >= 0)
+		ret++;
+
+	return ret;
+}
diff --git a/roms/u-boot/board/sr1500/MAINTAINERS b/roms/u-boot/board/sr1500/MAINTAINERS
new file mode 100644
index 000000000..ed013a852
--- /dev/null
+++ b/roms/u-boot/board/sr1500/MAINTAINERS
@@ -0,0 +1,6 @@
+SOCFPGA SR1500 BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/sr1500/
+F:	include/configs/socfpga_sr1500.h
+F:	configs/socfpga_sr1500_defconfig
diff --git a/roms/u-boot/board/sr1500/Makefile b/roms/u-boot/board/sr1500/Makefile
new file mode 100644
index 000000000..e499116b6
--- /dev/null
+++ b/roms/u-boot/board/sr1500/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/sr1500/qts/iocsr_config.h b/roms/u-boot/board/sr1500/qts/iocsr_config.h
new file mode 100644
index 000000000..b3b167fa7
--- /dev/null
+++ b/roms/u-boot/board/sr1500/qts/iocsr_config.h
@@ -0,0 +1,659 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00100000,
+	0x40000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x000E0180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00020000,
+	0x00004000,
+	0x000700C0,
+	0x1C030000,
+	0x0C000000,
+	0x00000070,
+	0x0001C030,
+	0x00002000,
+	0x00018060,
+	0x0E018000,
+	0x06000000,
+	0x00000038,
+	0x0000E018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x001C0300,
+	0x300C0000,
+	0x300000C0,
+	0x000000C0,
+	0x000300C0,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x000000E0,
+	0x00018060,
+	0x00004000,
+	0x000300C0,
+	0x1C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x01800000,
+	0x00000006,
+	0x00001806,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x000C0300,
+	0x700C0000,
+	0x0FF00000,
+	0x00000000,
+	0x000700C0,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00000060,
+	0x00018060,
+	0x00004000,
+	0x200300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000070,
+	0x0001C030,
+	0x00002000,
+	0x10018060,
+	0x0E018000,
+	0x06000000,
+	0x00010018,
+	0x0000E018,
+	0x00001000,
+	0x0001C030,
+	0x04000000,
+	0x03000000,
+	0x0000800C,
+	0x00C0300C,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x0C3000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x20430000,
+	0x0C003001,
+	0x00C00481,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x90218000,
+	0x86001800,
+	0x00600240,
+	0x80090218,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x4810C000,
+	0x43000C00,
+	0x00300120,
+	0xC004810C,
+	0x12043000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x45034071,
+	0x0A281A01,
+	0x806180D0,
+	0x34071C06,
+	0x01A034D0,
+	0x180D0000,
+	0x71C06806,
+	0x01450340,
+	0xD000001A,
+	0x0680E380,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x18000000,
+	0x01800902,
+	0x00240860,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x20430000,
+	0x0C003001,
+	0x00C00481,
+	0x00000FF0,
+	0x4810C000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x90218000,
+	0x86001800,
+	0x00600240,
+	0x80090218,
+	0x24086001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x4810C000,
+	0x43000C00,
+	0x00300120,
+	0xC004810C,
+	0x12043000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x45034071,
+	0x0A281A01,
+	0x80E380D0,
+	0x34071C06,
+	0x01A00040,
+	0x180D0002,
+	0x71C06806,
+	0x01450340,
+	0xD00A281A,
+	0x06806180,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x18000000,
+	0x01800902,
+	0x00240860,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x2043090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xCB2CA3DD,
+	0xF5D5551E,
+	0x034AD348,
+	0x821A0000,
+	0x0000D000,
+	0x030C0680,
+	0xDD59647A,
+	0x1ECB2CA3,
+	0x48F5D555,
+	0x00035AD3,
+	0x00080000,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000010,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040000,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00808000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x86120800,
+	0x00600240,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xCB2CA3DD,
+	0xF5D9651E,
+	0x035AB2C8,
+	0x821A0041,
+	0x0000D000,
+	0x00000680,
+	0xDD59647A,
+	0x1ECB2CA3,
+	0x48F5D965,
+	0x00035AD3,
+	0x00080000,
+	0x00001000,
+	0x00080000,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000010,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820004,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040000,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00808000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x2043090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010000,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00202000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xCB2CA3D5,
+	0xF6D9651E,
+	0x035AB2C8,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDD59647A,
+	0x1ECB2CA3,
+	0x48F5D965,
+	0x00034AD3,
+	0x00080000,
+	0x00001000,
+	0x00080000,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x00000000,
+	0x00000010,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820004,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040000,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00800000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020000,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00001000,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x04864000,
+	0x69A47A01,
+	0xCB2CA3D5,
+	0xF6D9651E,
+	0x034AD348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1ECB2CA3,
+	0x48F6D965,
+	0x00034A92,
+	0x00080000,
+	0x00001000,
+	0x00080000,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x00000000,
+	0x00000010,
+	0x0080C000,
+	0x41000000,
+	0x00000002,
+	0x00820004,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00004000,
+	0x00010000,
+	0x40002080,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000008,
+	0x00000020,
+	0x00008000,
+	0x20001040,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/sr1500/qts/pinmux_config.h b/roms/u-boot/board/sr1500/qts/pinmux_config.h
new file mode 100644
index 000000000..a8b8dbade
--- /dev/null
+++ b/roms/u-boot/board/sr1500/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	0, /* GENERALIO15 */
+	0, /* GENERALIO16 */
+	0, /* GENERALIO17 */
+	0, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	0, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	0, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	0, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	0, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	0, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	0, /* GPLMUX40 */
+	0, /* GPLMUX41 */
+	0, /* GPLMUX42 */
+	0, /* GPLMUX43 */
+	0, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	0, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	0, /* GPLMUX53 */
+	0, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	0, /* GPLMUX57 */
+	0, /* GPLMUX58 */
+	0, /* GPLMUX59 */
+	0, /* GPLMUX60 */
+	0, /* GPLMUX61 */
+	0, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/sr1500/qts/pll_config.h b/roms/u-boot/board/sr1500/qts/pll_config.h
new file mode 100644
index 000000000..02f068f74
--- /dev/null
+++ b/roms/u-boot/board/sr1500/qts/pll_config.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 12500000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/roms/u-boot/board/sr1500/qts/sdram_config.h b/roms/u-boot/board/sr1500/qts/sdram_config.h
new file mode 100644
index 000000000..d25354bb4
--- /dev/null
+++ b/roms/u-boot/board/sr1500/qts/sdram_config.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			140
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x330
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	7
+#define CALIB_VFIFO_OFFSET	5
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x55550496
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080421,
+	0x10080520,
+	0x10090044,
+	0x100a0008,
+	0x100b0000,
+	0x10380400,
+	0x10080441,
+	0x100804c0,
+	0x100a0024,
+	0x10090010,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/roms/u-boot/board/sr1500/socfpga.c b/roms/u-boot/board/sr1500/socfpga.c
new file mode 100644
index 000000000..d9125a76b
--- /dev/null
+++ b/roms/u-boot/board/sr1500/socfpga.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+int board_early_init_f(void)
+{
+	int ret;
+
+	/* Reset the Marvell PHY 88E1510 */
+	ret = gpio_request(63, "PHY reset");
+	if (ret)
+		return ret;
+
+	gpio_direction_output(63, 0);
+	mdelay(1);
+	gpio_set_value(63, 1);
+	mdelay(10);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/st/common/Kconfig b/roms/u-boot/board/st/common/Kconfig
new file mode 100644
index 000000000..ddcf33a12
--- /dev/null
+++ b/roms/u-boot/board/st/common/Kconfig
@@ -0,0 +1,78 @@
+config CMD_STBOARD
+	bool "stboard - command for OTP board information"
+	depends on ARCH_STM32MP
+	default y if TARGET_ST_STM32MP15x
+	help
+	  This compile the stboard command to
+	  read and write the board in the OTP.
+
+config MTDPARTS_NAND0_BOOT
+	string "mtd boot partitions for nand0"
+	default "2m(fsbl),2m(ssbl1),2m(ssbl2)"
+	depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
+	help
+	  This define the partitions of nand0 used to build mtparts dynamically
+	  for boot from nand0.
+	  Each partition need to be aligned with the device erase block size,
+	  512KB is the max size for the NAND supported by stm32mp1 platform.
+
+config MTDPARTS_NAND0_TEE
+	string "mtd tee partitions for nand0"
+	default "512k(teeh),512k(teed),512k(teex)"
+	depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
+	help
+	  This define the tee partitions added in mtparts dynamically
+	  when tee is supported with boot from nand0.
+	  Each partition need to be aligned with the device erase block size,
+	  512KB is the max size for the NAND supported by stm32mp1 platform.
+
+config MTDPARTS_NOR0_BOOT
+	string "mtd boot partitions for nor0"
+	default "256k(fsbl1),256k(fsbl2),2m(ssbl),512k(u-boot-env)"
+	depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
+	help
+	  This define the partitions of nand0 used to build mtparts dynamically
+	  for boot from nor0.
+	  Each partition need to be aligned with the device erase block size,
+	  with 256KB we support all the NOR.
+	  U-Boot env partition (512kB) use 2 erase block for redundancy.
+
+config MTDPARTS_NOR0_TEE
+	string "mtd tee partitions for nor0"
+	default "256k(teeh),512k(teed),256k(teex)"
+	depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
+	help
+	  This define the tee partitions added in mtparts dynamically
+	  when tee is supported with boot from nor0.
+
+config MTDPARTS_SPINAND0_BOOT
+	string "mtd boot partitions for spi-nand0"
+	default "2m(fsbl),2m(ssbl1),2m(ssbl2)"
+	depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
+	help
+	  This define the partitions of nand0 used to build mtparts dynamically
+	  for boot from spi-nand0,
+	  512KB is the max size for the NAND supported by stm32mp1 platform.
+
+config MTDPARTS_SPINAND0_TEE
+	string "mtd tee partitions for spi-nand0"
+	default "512k(teeh),512k(teed),512k(teex)"
+	depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
+	help
+	  This define the tee partitions added in mtparts dynamically
+	  when tee is supported with boot from spi-nand0,
+	  512KB is the max size for the NAND supported by stm32mp1 platform.
+
+config DFU_ALT_RAM0
+	string "dfu for ram0"
+	default "uImage ram 0xc2000000 0x2000000;devicetree.dtb ram 0xc4000000 0x100000;uramdisk.image.gz ram 0xc4400000 0x10000000"
+	depends on ARCH_STM32MP && SET_DFU_ALT_INFO
+	help
+	  This defines the partitions of ram used to build dfu dynamically.
+
+config TYPEC_STUSB160X
+	tristate "STMicroelectronics STUSB160X Type-C controller driver"
+	depends on DM_I2C
+	help
+	  Say Y if your system has STMicroelectronics STUSB160X Type-C port
+	  controller.
diff --git a/roms/u-boot/board/st/common/MAINTAINERS b/roms/u-boot/board/st/common/MAINTAINERS
new file mode 100644
index 000000000..0c6db5477
--- /dev/null
+++ b/roms/u-boot/board/st/common/MAINTAINERS
@@ -0,0 +1,6 @@
+ST BOARDS
+M:	Patrick Delaunay <patrick.delaunay@foss.st.com>
+L:	uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
+T:	git https://source.denx.de/u-boot/custodians/u-boot-stm.git
+S:	Maintained
+F:	board/st/common/
diff --git a/roms/u-boot/board/st/common/Makefile b/roms/u-boot/board/st/common/Makefile
new file mode 100644
index 000000000..65bbebd6a
--- /dev/null
+++ b/roms/u-boot/board/st/common/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+#
+# Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+#
+
+obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o
+obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
+
+ifeq ($(CONFIG_ARCH_STM32MP),y)
+obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += stm32mp_mtdparts.o
+obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o
+endif
+
+obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o
diff --git a/roms/u-boot/board/st/common/cmd_stboard.c b/roms/u-boot/board/st/common/cmd_stboard.c
new file mode 100644
index 000000000..2fba38316
--- /dev/null
+++ b/roms/u-boot/board/st/common/cmd_stboard.c
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * the st command stboard supports the STMicroelectronics board identification
+ * saved in OTP 59.
+ *
+ * The ST product codification have several element
+ * - "Commercial Product Name" (CPN): type of product board (DKX, EVX)
+ *   associated to the board ID "MBxxxx"
+ * - "Finished Good" or "Finish Good" (FG):
+ *   effective content of the product without chip STM32MP1xx (LCD, Wifi,…)
+ * - BOM: cost variant for same FG (for example, several provider of the same
+ *   component)
+ *
+ * For example
+ * - commercial product = STM32MP157C-EV1 for board MB1263
+ * - Finished Good = EVA32MP157A1$AU1
+ *
+ * Both information are written on board and these information are also saved
+ * in OTP59, with:
+ * bit [31:16] (hex) => Board id, MBxxxx
+ * bit [15:12] (dec) => Variant CPN (1....15)
+ * bit [11:8]  (dec) => Revision board (index with A = 1, Z = 26)
+ * bit [7:4]   (dec) => Variant FG : finished good index
+ * bit [3:0]   (dec) => BOM (01, .... 255)
+ *
+ * and displayed with the format:
+ *   Board: MB<Board> Var<VarCPN>.<VarFG> Rev.<Revision>-<BOM>
+ */
+
+#ifndef CONFIG_SPL_BUILD
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <misc.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+
+static bool check_stboard(u16 board)
+{
+	unsigned int i;
+	/* list of supported ST boards */
+	const u16 st_board_id[] = {
+		0x1272,
+		0x1263,
+		0x1264,
+		0x1298,
+		0x1341,
+		0x1497,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(st_board_id); i++)
+		if (board == st_board_id[i])
+			return true;
+
+	return false;
+}
+
+static void display_stboard(u32 otp)
+{
+	/* display board indentification with OPT coding */
+	printf("Board: MB%04x Var%d.%d Rev.%c-%02d\n",
+	       otp >> 16,
+	       (otp >> 12) & 0xF,
+	       (otp >> 4) & 0xF,
+	       ((otp >> 8) & 0xF) - 1 + 'A',
+	       otp & 0xF);
+}
+
+static int do_stboard(struct cmd_tbl *cmdtp, int flag, int argc,
+		      char *const argv[])
+{
+	int ret;
+	u32 otp, lock;
+	u8 revision;
+	unsigned long board, var_cpn, var_fg, bom;
+	struct udevice *dev;
+	int confirmed = argc == 7 && !strcmp(argv[1], "-y");
+
+	argc -= 1 + confirmed;
+	argv += 1 + confirmed;
+
+	if (argc != 0 && argc != 5)
+		return CMD_RET_USAGE;
+
+	ret = uclass_get_device_by_driver(UCLASS_MISC,
+					  DM_DRIVER_GET(stm32mp_bsec),
+					  &dev);
+
+	ret = misc_read(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD),
+			&otp, sizeof(otp));
+
+	if (ret < 0) {
+		puts("OTP read error");
+		return CMD_RET_FAILURE;
+	}
+
+	ret = misc_read(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD),
+			&lock, sizeof(lock));
+	if (ret < 0) {
+		puts("LOCK read error");
+		return CMD_RET_FAILURE;
+	}
+
+	if (argc == 0) {
+		if (!otp)
+			puts("Board : OTP board FREE\n");
+		else
+			display_stboard(otp);
+		printf("      OTP %d %s locked !\n", BSEC_OTP_BOARD,
+		       lock == 1 ? "" : "NOT");
+		return CMD_RET_SUCCESS;
+	}
+
+	if (otp) {
+		display_stboard(otp);
+		printf("ERROR: OTP board not FREE\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (strict_strtoul(argv[0], 16, &board) < 0 ||
+	    board == 0 || board > 0xFFFF) {
+		printf("argument %d invalid: %s\n", 1, argv[0]);
+		return CMD_RET_USAGE;
+	}
+
+	if (strict_strtoul(argv[1], 10, &var_cpn) < 0 ||
+	    var_cpn == 0 || var_cpn > 15) {
+		printf("argument %d invalid: %s\n", 2, argv[1]);
+		return CMD_RET_USAGE;
+	}
+
+	revision = argv[2][0] - 'A' + 1;
+	if (strlen(argv[2]) > 1 || revision == 0 || revision > 15) {
+		printf("argument %d invalid: %s\n", 3, argv[2]);
+		return CMD_RET_USAGE;
+	}
+
+	if (strict_strtoul(argv[3], 10, &var_fg) < 0 ||
+	    var_fg > 15) {
+		printf("argument %d invalid: %s\n", 4, argv[3]);
+		return CMD_RET_USAGE;
+	}
+
+	if (strict_strtoul(argv[4], 10, &bom) < 0 ||
+	    bom == 0 || bom > 15) {
+		printf("argument %d invalid: %s\n", 4, argv[3]);
+		return CMD_RET_USAGE;
+	}
+
+	/* st board indentification value */
+	otp = (board << 16) | (var_cpn << 12) | (revision << 8) |
+	      (var_fg << 4) | bom;
+	display_stboard(otp);
+	printf("=> OTP[%d] = %08X\n", BSEC_OTP_BOARD, otp);
+
+	if (!check_stboard((u16)board)) {
+		printf("Unknown board MB%04x\n", (u16)board);
+		return CMD_RET_FAILURE;
+	}
+	if (!confirmed) {
+		printf("Warning: Programming BOARD in OTP is irreversible!\n");
+		printf("Really perform this OTP programming? <y/N>\n");
+
+		if (!confirm_yesno()) {
+			puts("BOARD programming aborted\n");
+			return CMD_RET_FAILURE;
+		}
+	}
+
+	ret = misc_write(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD),
+			 &otp, sizeof(otp));
+
+	if (ret < 0) {
+		puts("BOARD programming error\n");
+		return CMD_RET_FAILURE;
+	}
+
+	/* write persistent lock */
+	otp = 1;
+	ret = misc_write(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD),
+			 &otp, sizeof(otp));
+	if (ret < 0) {
+		puts("BOARD lock error\n");
+		return CMD_RET_FAILURE;
+	}
+
+	puts("BOARD programming done\n");
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(stboard, 7, 0, do_stboard,
+	   "read/write board reference in OTP",
+	   "\n"
+	   "  Print current board information\n"
+	   "stboard [-y] <Board> <VarCPN> <Revision> <VarFG> <BOM>\n"
+	   "  Write board information\n"
+	   "  - Board: xxxx, example 1264 for MB1264\n"
+	   "  - VarCPN: 1...15\n"
+	   "  - Revision: A...O\n"
+	   "  - VarFG: 0...15\n"
+	   "  - BOM: 1...15\n");
+
+#endif
diff --git a/roms/u-boot/board/st/common/stm32mp_dfu.c b/roms/u-boot/board/st/common/stm32mp_dfu.c
new file mode 100644
index 000000000..00d1fb8f5
--- /dev/null
+++ b/roms/u-boot/board/st/common/stm32mp_dfu.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <blk.h>
+#include <dm.h>
+#include <dfu.h>
+#include <env.h>
+#include <log.h>
+#include <memalign.h>
+#include <misc.h>
+#include <mtd.h>
+#include <mtd_node.h>
+#include <asm/arch/stm32prog.h>
+
+#define DFU_ALT_BUF_LEN SZ_1K
+
+static void board_get_alt_info_mmc(struct udevice *dev, char *buf)
+{
+	struct disk_partition info;
+	int p, len, devnum;
+	bool first = true;
+	const char *name;
+	struct mmc *mmc;
+	struct blk_desc *desc;
+
+	mmc = mmc_get_mmc_dev(dev);
+	if (!mmc)
+		return;
+
+	if (mmc_init(mmc))
+		return;
+
+	desc = mmc_get_blk_desc(mmc);
+	if (!desc)
+		return;
+
+	name = blk_get_if_type_name(desc->if_type);
+	devnum = desc->devnum;
+	len = strlen(buf);
+
+	if (buf[0] != '\0')
+		len += snprintf(buf + len,
+				DFU_ALT_BUF_LEN - len, "&");
+	len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
+			 "%s %d=", name, devnum);
+
+	if (IS_MMC(mmc) && mmc->capacity_boot) {
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
+				"%s%d_boot1 raw 0x0 0x%llx mmcpart 1;",
+				name, devnum, mmc->capacity_boot);
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
+				"%s%d_boot2 raw 0x0 0x%llx mmcpart 2",
+				name, devnum, mmc->capacity_boot);
+		first = false;
+	}
+
+	for (p = 1; p < MAX_SEARCH_PARTITIONS; p++) {
+		if (part_get_info(desc, p, &info))
+			continue;
+		if (!first)
+			len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, ";");
+		first = false;
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
+				"%s%d_%s part %d %d",
+				name, devnum, info.name, devnum, p);
+	}
+}
+
+static void board_get_alt_info_mtd(struct mtd_info *mtd, char *buf)
+{
+	struct mtd_info *part;
+	bool first = true;
+	const char *name;
+	int len, partnum = 0;
+
+	name = mtd->name;
+	len = strlen(buf);
+
+	if (buf[0] != '\0')
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, "&");
+	len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
+			"mtd %s=", name);
+
+	len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
+			"%s raw 0x0 0x%llx ",
+			name, mtd->size);
+
+	list_for_each_entry(part, &mtd->partitions, node) {
+		partnum++;
+		if (!first)
+			len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, ";");
+		first = false;
+
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
+				"%s_%s part %d",
+				name, part->name, partnum);
+	}
+}
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+	struct udevice *dev;
+	struct mtd_info *mtd;
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+
+	if (env_get("dfu_alt_info"))
+		return;
+
+	memset(buf, 0, sizeof(buf));
+
+	snprintf(buf, DFU_ALT_BUF_LEN,
+		 "ram 0=%s", CONFIG_DFU_ALT_RAM0);
+
+	if (CONFIG_IS_ENABLED(MMC)) {
+		if (!uclass_get_device(UCLASS_MMC, 0, &dev))
+			board_get_alt_info_mmc(dev, buf);
+
+		if (!uclass_get_device(UCLASS_MMC, 1, &dev))
+			board_get_alt_info_mmc(dev, buf);
+	}
+
+	if (CONFIG_IS_ENABLED(MTD)) {
+		/* probe all MTD devices */
+		mtd_probe_devices();
+
+		/* probe SPI flash device on a bus */
+		if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) {
+			mtd = get_mtd_device_nm("nor0");
+			if (!IS_ERR_OR_NULL(mtd))
+				board_get_alt_info_mtd(mtd, buf);
+		}
+
+		mtd = get_mtd_device_nm("nand0");
+		if (!IS_ERR_OR_NULL(mtd))
+			board_get_alt_info_mtd(mtd, buf);
+
+		mtd = get_mtd_device_nm("spi-nand0");
+		if (!IS_ERR_OR_NULL(mtd))
+			board_get_alt_info_mtd(mtd, buf);
+	}
+
+	if (IS_ENABLED(CONFIG_DFU_VIRT) &&
+	    IS_ENABLED(CMD_STM32PROG_USB)) {
+		strncat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN);
+
+		if (IS_ENABLED(CONFIG_PMIC_STPMIC1))
+			strncat(buf, "&virt 1=PMIC", DFU_ALT_BUF_LEN);
+	}
+
+	env_set("dfu_alt_info", buf);
+	puts("DFU alt info setting: done\n");
+}
+
+#if CONFIG_IS_ENABLED(DFU_VIRT)
+#include <dfu.h>
+#include <power/stpmic1.h>
+
+static int dfu_otp_read(u64 offset, u8 *buffer, long *size)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_MISC,
+					  DM_DRIVER_GET(stm32mp_bsec),
+					  &dev);
+	if (ret)
+		return ret;
+
+	ret = misc_read(dev, offset + STM32_BSEC_OTP_OFFSET, buffer, *size);
+	if (ret >= 0) {
+		*size = ret;
+		ret = 0;
+	}
+
+	return 0;
+}
+
+static int dfu_pmic_read(u64 offset, u8 *buffer, long *size)
+{
+	int ret;
+#ifdef CONFIG_PMIC_STPMIC1
+	struct udevice *dev;
+
+	ret = uclass_get_device_by_driver(UCLASS_MISC,
+					  DM_DRIVER_GET(stpmic1_nvm),
+					  &dev);
+	if (ret)
+		return ret;
+
+	ret = misc_read(dev, 0xF8 + offset, buffer, *size);
+	if (ret >= 0) {
+		*size = ret;
+		ret = 0;
+	}
+	if (ret == -EACCES) {
+		*size = 0;
+		ret = 0;
+	}
+#else
+	log_err("PMIC update not supported");
+	ret = -EOPNOTSUPP;
+#endif
+
+	return ret;
+}
+
+int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset,
+			 void *buf, long *len)
+{
+	switch (dfu->data.virt.dev_num) {
+	case 0x0:
+		return dfu_otp_read(offset, buf, len);
+	case 0x1:
+		return dfu_pmic_read(offset, buf, len);
+	}
+
+	if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
+	    dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
+		return stm32prog_read_medium_virt(dfu, offset, buf, len);
+
+	*len = 0;
+	return 0;
+}
+
+int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset,
+			  void *buf, long *len)
+{
+	if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
+	    dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
+		return stm32prog_write_medium_virt(dfu, offset, buf, len);
+
+	return -EOPNOTSUPP;
+}
+
+int __weak dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size)
+{
+	if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
+	    dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
+		return stm32prog_get_medium_size_virt(dfu, size);
+
+	*size = SZ_1K;
+
+	return 0;
+}
+
+#endif
diff --git a/roms/u-boot/board/st/common/stm32mp_mtdparts.c b/roms/u-boot/board/st/common/stm32mp_mtdparts.c
new file mode 100644
index 000000000..f074fc189
--- /dev/null
+++ b/roms/u-boot/board/st/common/stm32mp_mtdparts.c
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <dfu.h>
+#include <dm.h>
+#include <env.h>
+#include <env_internal.h>
+#include <log.h>
+#include <mtd.h>
+#include <mtd_node.h>
+#include <tee.h>
+#include <asm/arch/stm32prog.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+
+#define MTDPARTS_LEN		256
+#define MTDIDS_LEN		128
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * update the variables "mtdids" and "mtdparts" with boot, tee and user strings
+ */
+static void board_set_mtdparts(const char *dev,
+			       char *mtdids,
+			       char *mtdparts,
+			       const char *boot,
+			       const char *tee,
+			       const char *user)
+{
+	/* mtdids: "<dev>=<dev>, ...." */
+	if (mtdids[0] != '\0')
+		strcat(mtdids, ",");
+	strcat(mtdids, dev);
+	strcat(mtdids, "=");
+	strcat(mtdids, dev);
+
+	/* mtdparts: "mtdparts=<dev>:<mtdparts_<dev>>;..." */
+	if (mtdparts[0] != '\0')
+		strncat(mtdparts, ";", MTDPARTS_LEN);
+	else
+		strcat(mtdparts, "mtdparts=");
+
+	strncat(mtdparts, dev, MTDPARTS_LEN);
+	strncat(mtdparts, ":", MTDPARTS_LEN);
+
+	if (boot) {
+		strncat(mtdparts, boot, MTDPARTS_LEN);
+		strncat(mtdparts, ",", MTDPARTS_LEN);
+	}
+
+	if (tee) {
+		strncat(mtdparts, tee, MTDPARTS_LEN);
+		strncat(mtdparts, ",", MTDPARTS_LEN);
+	}
+
+	strncat(mtdparts, user, MTDPARTS_LEN);
+}
+
+void board_mtdparts_default(const char **mtdids, const char **mtdparts)
+{
+	struct mtd_info *mtd;
+	struct udevice *dev;
+	static char parts[3 * MTDPARTS_LEN + 1];
+	static char ids[MTDIDS_LEN + 1];
+	static bool mtd_initialized;
+	bool tee, nor, nand, spinand, serial;
+
+	if (mtd_initialized) {
+		*mtdids = ids;
+		*mtdparts = parts;
+		return;
+	}
+
+	tee = false;
+	nor = false;
+	nand = false;
+	spinand = false;
+	serial = false;
+
+	switch (get_bootmode() & TAMP_BOOT_DEVICE_MASK) {
+	case BOOT_SERIAL_UART:
+	case BOOT_SERIAL_USB:
+		serial = true;
+		if (CONFIG_IS_ENABLED(CMD_STM32PROG)) {
+			tee = stm32prog_get_tee_partitions();
+			nor = stm32prog_get_fsbl_nor();
+		}
+		nand = true;
+		spinand = true;
+		break;
+	case BOOT_FLASH_NAND:
+		nand = true;
+		break;
+	case BOOT_FLASH_SPINAND:
+		spinand = true;
+		break;
+	case BOOT_FLASH_NOR:
+		nor = true;
+		break;
+	default:
+		break;
+	}
+
+	if (!serial && CONFIG_IS_ENABLED(OPTEE) &&
+	    tee_find_device(NULL, NULL, NULL, NULL))
+		tee = true;
+
+	memset(parts, 0, sizeof(parts));
+	memset(ids, 0, sizeof(ids));
+
+	/* probe all MTD devices */
+	for (uclass_first_device(UCLASS_MTD, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		log_debug("mtd device = %s\n", dev->name);
+	}
+
+	if (nand) {
+		mtd = get_mtd_device_nm("nand0");
+		if (!IS_ERR_OR_NULL(mtd)) {
+			const char *mtd_tee = CONFIG_MTDPARTS_NAND0_TEE;
+			board_set_mtdparts("nand0", ids, parts,
+					   CONFIG_MTDPARTS_NAND0_BOOT,
+					   !nor && tee ? mtd_tee : NULL,
+					   "-(UBI)");
+			put_mtd_device(mtd);
+		}
+	}
+
+	if (spinand) {
+		mtd = get_mtd_device_nm("spi-nand0");
+		if (!IS_ERR_OR_NULL(mtd)) {
+			const char *mtd_tee = CONFIG_MTDPARTS_SPINAND0_TEE;
+			board_set_mtdparts("spi-nand0", ids, parts,
+					   CONFIG_MTDPARTS_SPINAND0_BOOT,
+					   !nor && tee ? mtd_tee : NULL,
+					   "-(UBI)");
+			put_mtd_device(mtd);
+		}
+	}
+
+	if (nor) {
+		if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) {
+			const char *mtd_tee = CONFIG_MTDPARTS_NOR0_TEE;
+			board_set_mtdparts("nor0", ids, parts,
+					   CONFIG_MTDPARTS_NOR0_BOOT,
+					   tee ? mtd_tee : NULL,
+					   "-(nor_user)");
+		}
+	}
+
+	mtd_initialized = true;
+	*mtdids = ids;
+	*mtdparts = parts;
+	log_debug("mtdids=%s & mtdparts=%s\n", ids, parts);
+}
diff --git a/roms/u-boot/board/st/common/stpmic1.c b/roms/u-boot/board/st/common/stpmic1.c
new file mode 100644
index 000000000..5fb1be2fd
--- /dev/null
+++ b/roms/u-boot/board/st/common/stpmic1.c
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_BOARD
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/stpmic1.h>
+
+int board_ddr_power_init(enum ddr_type ddr_type)
+{
+	struct udevice *dev;
+	bool buck3_at_1800000v = false;
+	int ret;
+	u32 buck2;
+
+	ret = uclass_get_device_by_driver(UCLASS_PMIC,
+					  DM_DRIVER_GET(pmic_stpmic1), &dev);
+	if (ret)
+		/* No PMIC on board */
+		return 0;
+
+	switch (ddr_type) {
+	case STM32MP_DDR3:
+		/* VTT = Set LDO3 to sync mode */
+		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+		if (ret < 0)
+			return ret;
+
+		ret &= ~STPMIC1_LDO3_MODE;
+		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+		ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
+
+		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+				     ret);
+		if (ret < 0)
+			return ret;
+
+		/* VDD_DDR = Set BUCK2 to 1.35V */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+				      STPMIC1_BUCK_VOUT_MASK,
+				      STPMIC1_BUCK2_1350000V);
+		if (ret < 0)
+			return ret;
+
+		/* Enable VDD_DDR = BUCK2 */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		/* Enable VREF */
+		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		/* Enable VTT = LDO3 */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		break;
+
+	case STM32MP_LPDDR2_16:
+	case STM32MP_LPDDR2_32:
+	case STM32MP_LPDDR3_16:
+	case STM32MP_LPDDR3_32:
+		/*
+		 * configure VDD_DDR1 = LDO3
+		 * Set LDO3 to 1.8V
+		 * + bypass mode if BUCK3 = 1.8V
+		 * + normal mode if BUCK3 != 1.8V
+		 */
+		ret = pmic_reg_read(dev,
+				    STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
+		if (ret < 0)
+			return ret;
+
+		if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
+			buck3_at_1800000v = true;
+
+		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+		if (ret < 0)
+			return ret;
+
+		ret &= ~STPMIC1_LDO3_MODE;
+		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+		ret |= STPMIC1_LDO3_1800000;
+		if (buck3_at_1800000v)
+			ret |= STPMIC1_LDO3_MODE;
+
+		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+				     ret);
+		if (ret < 0)
+			return ret;
+
+		/* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
+		switch (ddr_type) {
+		case STM32MP_LPDDR2_32:
+		case STM32MP_LPDDR3_32:
+			buck2 = STPMIC1_BUCK2_1250000V;
+			break;
+		default:
+		case STM32MP_LPDDR2_16:
+		case STM32MP_LPDDR3_16:
+			buck2 = STPMIC1_BUCK2_1200000V;
+			break;
+		}
+
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+				      STPMIC1_BUCK_VOUT_MASK,
+				      buck2);
+		if (ret < 0)
+			return ret;
+
+		/* Enable VDD_DDR1 = LDO3 */
+		ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		/* Enable VDD_DDR2 =BUCK2 */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		/* Enable VREF */
+		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		break;
+
+	default:
+		break;
+	};
+
+	return 0;
+}
+
+static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv)
+{
+	u32 value;
+
+	/* VDDCORE= STMPCI1 BUCK1 ramp=+25mV, 5 => 725mV, 36 => 1500mV */
+	value = ((voltage_mv - 725) / 25) + 5;
+	if (value < 5)
+		value = 5;
+	if (value > 36)
+		value = 36;
+
+	return pmic_clrsetbits(dev,
+			       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK1),
+			       STPMIC1_BUCK_VOUT_MASK,
+			       STPMIC1_BUCK_VOUT(value));
+}
+
+/* early init of PMIC */
+void stpmic1_init(u32 voltage_mv)
+{
+	struct udevice *dev;
+
+	if (uclass_get_device_by_driver(UCLASS_PMIC,
+					DM_DRIVER_GET(pmic_stpmic1), &dev))
+		return;
+
+	/* update VDDCORE = BUCK1 */
+	if (voltage_mv)
+		stmpic_buck1_set(dev, voltage_mv);
+
+	/* Keep vdd on during the reset cycle */
+	pmic_clrsetbits(dev,
+			STPMIC1_BUCKS_MRST_CR,
+			STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
+			STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
+
+	/* Check if debug is enabled to program PMIC according to the bit */
+	if (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) {
+		log_info("Keep debug unit ON\n");
+
+		pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR,
+				STPMIC1_MRST_BUCK_DEBUG,
+				STPMIC1_MRST_BUCK_DEBUG);
+
+		if (STPMIC1_MRST_LDO_DEBUG)
+			pmic_clrsetbits(dev, STPMIC1_LDOS_MRST_CR,
+					STPMIC1_MRST_LDO_DEBUG,
+					STPMIC1_MRST_LDO_DEBUG);
+	}
+}
diff --git a/roms/u-boot/board/st/common/stpmic1.h b/roms/u-boot/board/st/common/stpmic1.h
new file mode 100644
index 000000000..b17d6f163
--- /dev/null
+++ b/roms/u-boot/board/st/common/stpmic1.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+void stpmic1_init(u32 voltage_mv);
diff --git a/roms/u-boot/board/st/common/stusb160x.c b/roms/u-boot/board/st/common/stusb160x.c
new file mode 100644
index 000000000..f0385e5e3
--- /dev/null
+++ b/roms/u-boot/board/st/common/stusb160x.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * STMicroelectronics STUSB Type-C controller driver
+ * based on Linux drivers/usb/typec/stusb160x.c
+ *
+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY UCLASS_I2C_GENERIC
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+
+/* REGISTER */
+#define STUSB160X_CC_CONNECTION_STATUS		0x0E
+
+/* STUSB160X_CC_CONNECTION_STATUS bitfields */
+#define STUSB160X_CC_ATTACH			BIT(0)
+
+int stusb160x_cable_connected(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_I2C_GENERIC,
+					  DM_DRIVER_GET(stusb160x),
+					  &dev);
+	if (ret < 0)
+		return ret;
+
+	ret = dm_i2c_reg_read(dev, STUSB160X_CC_CONNECTION_STATUS);
+	if (ret < 0)
+		return 0;
+
+	return ret & STUSB160X_CC_ATTACH;
+}
+
+static const struct udevice_id stusb160x_ids[] = {
+	{ .compatible = "st,stusb1600" },
+	{}
+};
+
+U_BOOT_DRIVER(stusb160x) = {
+	.name = "stusb160x",
+	.id = UCLASS_I2C_GENERIC,
+	.of_match = stusb160x_ids,
+};
diff --git a/roms/u-boot/board/st/common/stusb160x.h b/roms/u-boot/board/st/common/stusb160x.h
new file mode 100644
index 000000000..fe39840b4
--- /dev/null
+++ b/roms/u-boot/board/st/common/stusb160x.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020, STMicroelectronics
+ */
+
+#ifdef CONFIG_TYPEC_STUSB160X
+int stusb160x_cable_connected(void);
+#else
+int stusb160x_cable_connected(void) { return -ENODEV; }
+#endif
diff --git a/roms/u-boot/board/st/stih410-b2260/Kconfig b/roms/u-boot/board/st/stih410-b2260/Kconfig
new file mode 100644
index 000000000..590add05f
--- /dev/null
+++ b/roms/u-boot/board/st/stih410-b2260/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STIH410_B2260
+
+config SYS_BOARD
+	string
+	default "stih410-b2260"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stih410"
+
+config SYS_CONFIG_NAME
+	string
+	default "stih410-b2260"
+
+endif
diff --git a/roms/u-boot/board/st/stih410-b2260/MAINTAINERS b/roms/u-boot/board/st/stih410-b2260/MAINTAINERS
new file mode 100644
index 000000000..6fa625507
--- /dev/null
+++ b/roms/u-boot/board/st/stih410-b2260/MAINTAINERS
@@ -0,0 +1,7 @@
+STIH410-B2260 BOARD
+M:	Patrice Chotard <patrice.chotard@foss.st.com>
+S:	Maintained
+F:	board/st/stih410-b2260/
+F:	include/configs/stih410-b2260.h
+F:	configs/stih410-b2260_defconfig
+F:	arch/arm/dts/stih*
diff --git a/roms/u-boot/board/st/stih410-b2260/Makefile b/roms/u-boot/board/st/stih410-b2260/Makefile
new file mode 100644
index 000000000..ea573ca14
--- /dev/null
+++ b/roms/u-boot/board/st/stih410-b2260/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
+
+obj-y	= board.o
diff --git a/roms/u-boot/board/st/stih410-b2260/board.c b/roms/u-boot/board/st/stih410-b2260/board.c
new file mode 100644
index 000000000..cd3a7dc51
--- /dev/null
+++ b/roms/u-boot/board/st/stih410-b2260/board.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <linux/usb/otg.h>
+#include <dwc3-sti-glue.h>
+#include <dwc3-uboot.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
+
+int board_init(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device dwc3_device_data = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+	dwc3_uboot_handle_interrupt(index);
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int node;
+	const void *blob = gd->fdt_blob;
+
+	/* find the snps,dwc3 node */
+	node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
+
+	dwc3_device_data.base = fdtdec_get_addr(blob, node, "reg");
+
+	return dwc3_uboot_init(&dwc3_device_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	dwc3_uboot_exit(index);
+	return 0;
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+	return 1;
+}
+#endif
diff --git a/roms/u-boot/board/st/stm32f429-discovery/Kconfig b/roms/u-boot/board/st/stm32f429-discovery/Kconfig
new file mode 100644
index 000000000..e73d11bad
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f429-discovery/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM32F429_DISCOVERY
+
+config SYS_BOARD
+	string
+	default "stm32f429-discovery"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stm32f4"
+
+config SYS_CONFIG_NAME
+	string
+	default "stm32f429-discovery"
+
+endif
diff --git a/roms/u-boot/board/st/stm32f429-discovery/MAINTAINERS b/roms/u-boot/board/st/stm32f429-discovery/MAINTAINERS
new file mode 100644
index 000000000..fdb62e98e
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f429-discovery/MAINTAINERS
@@ -0,0 +1,6 @@
+STM32F429-DISCOVERY BOARD
+M:	Kamil Lulko <kamil.lulko@gmail.com>
+S:	Maintained
+F:	board/st/stm32f429-discovery/
+F:	include/configs/stm32f429-discovery.h
+F:	configs/stm32f429-discovery_defconfig
diff --git a/roms/u-boot/board/st/stm32f429-discovery/Makefile b/roms/u-boot/board/st/stm32f429-discovery/Makefile
new file mode 100644
index 000000000..6b02c0fdd
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f429-discovery/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2015
+# Kamil Lulko, <kamil.lulko@gmail.com>
+
+obj-y	:= stm32f429-discovery.o
+obj-y	+= led.o
diff --git a/roms/u-boot/board/st/stm32f429-discovery/led.c b/roms/u-boot/board/st/stm32f429-discovery/led.c
new file mode 100644
index 000000000..539c139bb
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f429-discovery/led.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <asm-generic/gpio.h>
+
+void coloured_LED_init(void)
+{
+	gpio_request(CONFIG_RED_LED, "red led");
+	gpio_direction_output(CONFIG_RED_LED, 0);
+	gpio_request(CONFIG_GREEN_LED, "green led");
+	gpio_direction_output(CONFIG_GREEN_LED, 0);
+}
+
+void red_led_off(void)
+{
+	gpio_set_value(CONFIG_RED_LED, 0);
+}
+
+void green_led_off(void)
+{
+	gpio_set_value(CONFIG_GREEN_LED, 0);
+}
+
+void red_led_on(void)
+{
+	gpio_set_value(CONFIG_RED_LED, 1);
+}
+
+void green_led_on(void)
+{
+	gpio_set_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/roms/u-boot/board/st/stm32f429-discovery/stm32f429-discovery.c b/roms/u-boot/board/st/stm32f429-discovery/stm32f429-discovery.c
new file mode 100644
index 000000000..46fcf907f
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f429-discovery/stm32f429-discovery.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011, 2012, 2013
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
+ * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
+ * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	int rv;
+	struct udevice *dev;
+
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv) {
+		debug("DRAM init failed: %d\n", rv);
+		return rv;
+	}
+
+	if (fdtdec_setup_mem_size_base() != 0)
+		rv = -EINVAL;
+
+	return rv;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char serialno[25];
+	uint32_t u_id_low, u_id_mid, u_id_high;
+
+	if (!env_get("serial#")) {
+		u_id_low  = readl(&STM32_U_ID->u_id_low);
+		u_id_mid  = readl(&STM32_U_ID->u_id_mid);
+		u_id_high = readl(&STM32_U_ID->u_id_high);
+		sprintf(serialno, "%08x%08x%08x",
+			u_id_high, u_id_mid, u_id_low);
+		env_set("serial#", serialno);
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/st/stm32f429-evaluation/Kconfig b/roms/u-boot/board/st/stm32f429-evaluation/Kconfig
new file mode 100644
index 000000000..ca4bb3d9c
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f429-evaluation/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM32F429_EVALUATION
+
+config SYS_BOARD
+	string
+	default "stm32f429-evaluation"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stm32f4"
+
+config SYS_CONFIG_NAME
+	string
+	default "stm32f429-evaluation"
+
+endif
diff --git a/roms/u-boot/board/st/stm32f429-evaluation/MAINTAINERS b/roms/u-boot/board/st/stm32f429-evaluation/MAINTAINERS
new file mode 100644
index 000000000..29d00ef27
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f429-evaluation/MAINTAINERS
@@ -0,0 +1,6 @@
+STM32F429-EVALUATION BOARD
+M:	Patrice Chotard <patrice.chotard@foss.st.com>
+S:	Maintained
+F:	board/st/stm32f429-evaluation/
+F:	include/configs/stm32f429-evaluation.h
+F:	configs/stm32f429-evaluation_defconfig
diff --git a/roms/u-boot/board/st/stm32f429-evaluation/Makefile b/roms/u-boot/board/st/stm32f429-evaluation/Makefile
new file mode 100644
index 000000000..109fba876
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f429-evaluation/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
+
+obj-y	:= stm32f429-evaluation.o
diff --git a/roms/u-boot/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/roms/u-boot/board/st/stm32f429-evaluation/stm32f429-evaluation.c
new file mode 100644
index 000000000..3b6df1f3a
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f429-evaluation/stm32f429-evaluation.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	int rv;
+	struct udevice *dev;
+
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv) {
+		debug("DRAM init failed: %d\n", rv);
+		return rv;
+	}
+
+	if (fdtdec_setup_mem_size_base() != 0)
+		rv = -EINVAL;
+
+	return rv;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char serialno[25];
+	u32 u_id_low, u_id_mid, u_id_high;
+
+	if (!env_get("serial#")) {
+		u_id_low  = readl(&STM32_U_ID->u_id_low);
+		u_id_mid  = readl(&STM32_U_ID->u_id_mid);
+		u_id_high = readl(&STM32_U_ID->u_id_high);
+		sprintf(serialno, "%08x%08x%08x",
+			u_id_high, u_id_mid, u_id_low);
+		env_set("serial#", serialno);
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/st/stm32f469-discovery/Kconfig b/roms/u-boot/board/st/stm32f469-discovery/Kconfig
new file mode 100644
index 000000000..de61b6f2f
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f469-discovery/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM32F469_DISCOVERY
+
+config SYS_BOARD
+	string
+	default "stm32f469-discovery"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stm32f4"
+
+config SYS_CONFIG_NAME
+	string
+	default "stm32f469-discovery"
+
+endif
diff --git a/roms/u-boot/board/st/stm32f469-discovery/MAINTAINERS b/roms/u-boot/board/st/stm32f469-discovery/MAINTAINERS
new file mode 100644
index 000000000..5a6a78b39
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f469-discovery/MAINTAINERS
@@ -0,0 +1,6 @@
+STM32F469-DISCOVERY BOARD
+M:	Patrice Chotard <patrice.chotard@foss.st.com>
+S:	Maintained
+F:	board/st/stm32f469-discovery/
+F:	include/configs/stm32f469-discovery.h
+F:	configs/stm32f469-discovery_defconfig
diff --git a/roms/u-boot/board/st/stm32f469-discovery/Makefile b/roms/u-boot/board/st/stm32f469-discovery/Makefile
new file mode 100644
index 000000000..45480b72c
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f469-discovery/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) STMicroelectronics SA 2017
+# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
+
+obj-y	:= stm32f469-discovery.o
diff --git a/roms/u-boot/board/st/stm32f469-discovery/stm32f469-discovery.c b/roms/u-boot/board/st/stm32f469-discovery/stm32f469-discovery.c
new file mode 100644
index 000000000..c5df9b0d9
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f469-discovery/stm32f469-discovery.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	int rv;
+	struct udevice *dev;
+
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv) {
+		debug("DRAM init failed: %d\n", rv);
+		return rv;
+	}
+
+	if (fdtdec_setup_mem_size_base() != 0)
+		rv = -EINVAL;
+
+	return rv;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char serialno[25];
+	u32 u_id_low, u_id_mid, u_id_high;
+
+	if (!env_get("serial#")) {
+		u_id_low  = readl(&STM32_U_ID->u_id_low);
+		u_id_mid  = readl(&STM32_U_ID->u_id_mid);
+		u_id_high = readl(&STM32_U_ID->u_id_high);
+		sprintf(serialno, "%08x%08x%08x",
+			u_id_high, u_id_mid, u_id_low);
+		env_set("serial#", serialno);
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/st/stm32f746-disco/Kconfig b/roms/u-boot/board/st/stm32f746-disco/Kconfig
new file mode 100644
index 000000000..09289d232
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f746-disco/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM32F746_DISCO
+
+config SYS_BOARD
+	string
+	default "stm32f746-disco"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stm32f7"
+
+config SYS_CONFIG_NAME
+	string
+	default "stm32f746-disco"
+
+endif
diff --git a/roms/u-boot/board/st/stm32f746-disco/MAINTAINERS b/roms/u-boot/board/st/stm32f746-disco/MAINTAINERS
new file mode 100644
index 000000000..3bbb513ad
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f746-disco/MAINTAINERS
@@ -0,0 +1,7 @@
+STM32F746 DISCOVERY BOARD
+M:	Vikas Manocha <vikas.manocha@st.com>
+S:	Maintained
+F:	board/st/stm32f746-disco
+F:	include/configs/stm32f746-disco.h
+F:	configs/stm32f746-disco_defconfig
+F:	configs/stm32f769-disco_defconfig
diff --git a/roms/u-boot/board/st/stm32f746-disco/Makefile b/roms/u-boot/board/st/stm32f746-disco/Makefile
new file mode 100644
index 000000000..369f17a2d
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f746-disco/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+
+obj-y	:= stm32f746-disco.o
diff --git a/roms/u-boot/board/st/stm32f746-disco/stm32f746-disco.c b/roms/u-boot/board/st/stm32f746-disco/stm32f746-disco.c
new file mode 100644
index 000000000..efa38a0e2
--- /dev/null
+++ b/roms/u-boot/board/st/stm32f746-disco/stm32f746-disco.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <lcd.h>
+#include <log.h>
+#include <miiphy.h>
+#include <phy_interface.h>
+#include <ram.h>
+#include <serial.h>
+#include <spl.h>
+#include <splash.h>
+#include <st_logo_data.h>
+#include <video.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/syscfg.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SUPPORT_SPL
+	int rv;
+	struct udevice *dev;
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv) {
+		debug("DRAM init failed: %d\n", rv);
+		return rv;
+	}
+
+#endif
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	debug("SPL: booting kernel\n");
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+int spl_dram_init(void)
+{
+	struct udevice *dev;
+	int rv;
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv)
+		debug("DRAM init failed: %d\n", rv);
+	return rv;
+}
+void spl_board_init(void)
+{
+	preloader_console_init();
+	spl_dram_init();
+	arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_XIP;
+}
+
+#endif
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct gpio_desc gpio = {};
+	int node;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1");
+	if (node < 0)
+		return -1;
+
+	gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio,
+				   GPIOD_IS_OUT);
+
+	if (dm_gpio_is_valid(&gpio)) {
+		dm_gpio_set_value(&gpio, 0);
+		mdelay(10);
+		dm_gpio_set_value(&gpio, 1);
+	}
+
+	/* read button 1*/
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1");
+	if (node < 0)
+		return -1;
+
+	gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0,
+				   &gpio, GPIOD_IS_IN);
+
+	if (dm_gpio_is_valid(&gpio)) {
+		if (dm_gpio_get_value(&gpio))
+			puts("usr button is at HIGH LEVEL\n");
+		else
+			puts("usr button is at LOW LEVEL\n");
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+#ifdef CONFIG_ETH_DESIGNWARE
+	const char *phy_mode;
+	int node;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,stm32-dwmac");
+	if (node < 0)
+		return -1;
+
+	phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
+
+	switch (phy_get_interface_by_name(phy_mode)) {
+	case PHY_INTERFACE_MODE_RMII:
+		STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
+		break;
+	case PHY_INTERFACE_MODE_MII:
+		STM32_SYSCFG->pmc &= ~SYSCFG_PMC_MII_RMII_SEL;
+		break;
+	default:
+		printf("PHY interface %s not supported !\n", phy_mode);
+	}
+#endif
+
+#if defined(CONFIG_CMD_BMP)
+	bmp_display((ulong)stmicroelectronics_uboot_logo_8bit_rle,
+		    BMP_ALIGN_CENTER, BMP_ALIGN_CENTER);
+#endif /* CONFIG_CMD_BMP */
+
+	return 0;
+}
diff --git a/roms/u-boot/board/st/stm32h743-disco/Kconfig b/roms/u-boot/board/st/stm32h743-disco/Kconfig
new file mode 100644
index 000000000..7d6ec1d95
--- /dev/null
+++ b/roms/u-boot/board/st/stm32h743-disco/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM32H743_DISCO
+
+config SYS_BOARD
+	string
+	default "stm32h743-disco"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stm32h7"
+
+config SYS_CONFIG_NAME
+	string
+	default "stm32h743-disco"
+
+endif
diff --git a/roms/u-boot/board/st/stm32h743-disco/MAINTAINERS b/roms/u-boot/board/st/stm32h743-disco/MAINTAINERS
new file mode 100644
index 000000000..60fbe344f
--- /dev/null
+++ b/roms/u-boot/board/st/stm32h743-disco/MAINTAINERS
@@ -0,0 +1,7 @@
+STM32H743 DISCOVERY BOARD
+M:	Patrice Chotard <patrice.chotard@foss.st.com>
+S:	Maintained
+F:	board/st/stm32h743-disco
+F:	include/configs/stm32h743-disco.h
+F:	configs/stm32h743-disco_defconfig
+F:	arch/arm/dts/stm32h7*
diff --git a/roms/u-boot/board/st/stm32h743-disco/Makefile b/roms/u-boot/board/st/stm32h743-disco/Makefile
new file mode 100644
index 000000000..b6c22be1e
--- /dev/null
+++ b/roms/u-boot/board/st/stm32h743-disco/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
+
+obj-y	:= stm32h743-disco.o
diff --git a/roms/u-boot/board/st/stm32h743-disco/stm32h743-disco.c b/roms/u-boot/board/st/stm32h743-disco/stm32h743-disco.c
new file mode 100644
index 000000000..4091d5f9f
--- /dev/null
+++ b/roms/u-boot/board/st/stm32h743-disco/stm32h743-disco.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+
+	if (fdtdec_setup_mem_size_base() != 0)
+		ret = -EINVAL;
+
+	return ret;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	return 0;
+}
diff --git a/roms/u-boot/board/st/stm32h743-eval/Kconfig b/roms/u-boot/board/st/stm32h743-eval/Kconfig
new file mode 100644
index 000000000..ea879b13c
--- /dev/null
+++ b/roms/u-boot/board/st/stm32h743-eval/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM32H743_EVAL
+
+config SYS_BOARD
+	string
+	default "stm32h743-eval"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stm32h7"
+
+config SYS_CONFIG_NAME
+	string
+	default "stm32h743-eval"
+
+endif
diff --git a/roms/u-boot/board/st/stm32h743-eval/MAINTAINERS b/roms/u-boot/board/st/stm32h743-eval/MAINTAINERS
new file mode 100644
index 000000000..fda93db77
--- /dev/null
+++ b/roms/u-boot/board/st/stm32h743-eval/MAINTAINERS
@@ -0,0 +1,6 @@
+STM32H743 EVALUATION BOARD
+M:	Patrice Chotard <patrice.chotard@foss.st.com>
+S:	Maintained
+F:	board/st/stm32h743-eval
+F:	include/configs/stm32h743-eval.h
+F:	configs/stm32h743-eval_defconfig
diff --git a/roms/u-boot/board/st/stm32h743-eval/Makefile b/roms/u-boot/board/st/stm32h743-eval/Makefile
new file mode 100644
index 000000000..86ef19fc3
--- /dev/null
+++ b/roms/u-boot/board/st/stm32h743-eval/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
+
+obj-y	:= stm32h743-eval.o
diff --git a/roms/u-boot/board/st/stm32h743-eval/stm32h743-eval.c b/roms/u-boot/board/st/stm32h743-eval/stm32h743-eval.c
new file mode 100644
index 000000000..4091d5f9f
--- /dev/null
+++ b/roms/u-boot/board/st/stm32h743-eval/stm32h743-eval.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+
+	if (fdtdec_setup_mem_size_base() != 0)
+		ret = -EINVAL;
+
+	return ret;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	return 0;
+}
diff --git a/roms/u-boot/board/st/stm32h750-art-pi/Kconfig b/roms/u-boot/board/st/stm32h750-art-pi/Kconfig
new file mode 100644
index 000000000..c31b9849f
--- /dev/null
+++ b/roms/u-boot/board/st/stm32h750-art-pi/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM32H750_ART_PI
+
+config SYS_BOARD
+	string
+	default "stm32h750-art-pi"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stm32h7"
+
+config SYS_CONFIG_NAME
+	string
+	default "stm32h750-art-pi"
+
+endif
diff --git a/roms/u-boot/board/st/stm32h750-art-pi/MAINTAINERS b/roms/u-boot/board/st/stm32h750-art-pi/MAINTAINERS
new file mode 100644
index 000000000..957883306
--- /dev/null
+++ b/roms/u-boot/board/st/stm32h750-art-pi/MAINTAINERS
@@ -0,0 +1,7 @@
+STM32H750 ART PI BOARD
+M:	Dillon Min <dillon.minfei@gmail.com>
+S:	Maintained
+F:	board/st/stm32h750-art-pi
+F:	include/configs/stm32h750-art-pi.h
+F:	configs/stm32h750-art-pi_defconfig
+F:	arch/arm/dts/stm32h7*
diff --git a/roms/u-boot/board/st/stm32h750-art-pi/Makefile b/roms/u-boot/board/st/stm32h750-art-pi/Makefile
new file mode 100644
index 000000000..a06de8752
--- /dev/null
+++ b/roms/u-boot/board/st/stm32h750-art-pi/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021, RT-Thread - All Rights Reserved
+# Author(s): Dillon Min, <dillon.minfei@gmail.com> for RT-Thread.
+
+obj-y	:= stm32h750-art-pi.o
diff --git a/roms/u-boot/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/roms/u-boot/board/st/stm32h750-art-pi/stm32h750-art-pi.c
new file mode 100644
index 000000000..5785b2e57
--- /dev/null
+++ b/roms/u-boot/board/st/stm32h750-art-pi/stm32h750-art-pi.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, STMicroelectronics - All Rights Reserved
+ * Author(s): Dillon Min <dillon.minfei@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+
+	if (fdtdec_setup_mem_size_base() != 0)
+		ret = -EINVAL;
+
+	return ret;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	return 0;
+}
diff --git a/roms/u-boot/board/st/stm32mp1/Kconfig b/roms/u-boot/board/st/stm32mp1/Kconfig
new file mode 100644
index 000000000..c5ab7553d
--- /dev/null
+++ b/roms/u-boot/board/st/stm32mp1/Kconfig
@@ -0,0 +1,13 @@
+if TARGET_ST_STM32MP15x
+
+config SYS_BOARD
+	default "stm32mp1"
+
+config SYS_VENDOR
+	default "st"
+
+config SYS_CONFIG_NAME
+	default "stm32mp1"
+
+source "board/st/common/Kconfig"
+endif
diff --git a/roms/u-boot/board/st/stm32mp1/MAINTAINERS b/roms/u-boot/board/st/stm32mp1/MAINTAINERS
new file mode 100644
index 000000000..fe8fc6f48
--- /dev/null
+++ b/roms/u-boot/board/st/stm32mp1/MAINTAINERS
@@ -0,0 +1,10 @@
+STM32MP1 BOARD
+M:	Patrick Delaunay <patrick.delaunay@foss.st.com>
+L:	uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
+T:	git https://source.denx.de/u-boot/custodians/u-boot-stm.git
+S:	Maintained
+F:	arch/arm/dts/stm32mp15*
+F:	board/st/stm32mp1/
+F:	configs/stm32mp15_basic_defconfig
+F:	configs/stm32mp15_trusted_defconfig
+F:	include/configs/stm32mp1.h
diff --git a/roms/u-boot/board/st/stm32mp1/Makefile b/roms/u-boot/board/st/stm32mp1/Makefile
new file mode 100644
index 000000000..65560df29
--- /dev/null
+++ b/roms/u-boot/board/st/stm32mp1/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += stm32mp1.o
+endif
diff --git a/roms/u-boot/board/st/stm32mp1/README b/roms/u-boot/board/st/stm32mp1/README
new file mode 100644
index 000000000..8172d26a6
--- /dev/null
+++ b/roms/u-boot/board/st/stm32mp1/README
@@ -0,0 +1 @@
+see doc/board/st/stm32mp1.rst
diff --git a/roms/u-boot/board/st/stm32mp1/extlinux.conf b/roms/u-boot/board/st/stm32mp1/extlinux.conf
new file mode 100644
index 000000000..2b4632804
--- /dev/null
+++ b/roms/u-boot/board/st/stm32mp1/extlinux.conf
@@ -0,0 +1,20 @@
+# Generic Distro Configuration for STM32MP157
+menu title Select the boot mode
+TIMEOUT 20
+DEFAULT stm32mp157c-ev1
+
+LABEL stm32mp157c-ev1
+	KERNEL /fit_kernel_dtb.itb#ev1
+	APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200
+
+LABEL stm32mp157c-ev1-m4
+	KERNEL /fit_copro_kernel_dtb.itb#ev1-m4
+	APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200
+
+LABEL stm32mp157c-dk2
+	KERNEL /fit_kernel_dtb.itb#dk2
+	APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200
+
+LABEL stm32mp157c-dk2-m4
+	KERNEL /fit_copro_kernel_dtb.itb#dk2-m4
+	APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200
diff --git a/roms/u-boot/board/st/stm32mp1/fit_copro_kernel_dtb.its b/roms/u-boot/board/st/stm32mp1/fit_copro_kernel_dtb.its
new file mode 100644
index 000000000..dc43639af
--- /dev/null
+++ b/roms/u-boot/board/st/stm32mp1/fit_copro_kernel_dtb.its
@@ -0,0 +1,117 @@
+/*
+ * Compilation:
+ * mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb
+ *
+ * M4 firmware to load with remoteproc: rproc-m4-fw.elf
+ *
+ * Files in linux build dir:
+ * - arch/arm/boot/zImage
+ * - arch/arm/boot/dts/stm32mp157c-dk2.dtb
+ * - arch/arm/boot/dts/stm32mp157c-ev1.dtb
+ *
+ * load mmc 0:4 $kernel_addr_r fit_copro_kernel_dtb.itb
+ * bootm $kernel_addr_r
+ * bootm $kernel_addr_r#dk2
+ * bootm $kernel_addr_r#ev1
+ * bootm $kernel_addr_r#dk2-m4
+ * bootm $kernel_addr_r#ev1-m4
+ */
+
+/dts-v1/;
+/ {
+	description = "U-Boot fitImage for stm32mp157";
+	#address-cells = <1>;
+
+	images {
+
+		copro {
+			description = "M4 copro";
+			data = /incbin/("rproc-m4-fw.elf");
+			type = "copro";
+			arch = "arm";
+			compression = "none";
+			load = <0xC0800000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		kernel {
+			description = "Linux kernel";
+			data = /incbin/("zImage");
+			type = "kernel";
+			arch = "arm";
+			os = "linux";
+			compression = "none";
+			load = <0xC4000000>;
+			entry = <0xC4000000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		fdt-dk2 {
+			description = "FDT dk2";
+			data = /incbin/("stm32mp157c-dk2.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		fdt-ev1 {
+			description = "FDT ev1";
+			data = /incbin/("stm32mp157c-ev1.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+	};
+
+	configurations {
+		default = "dk2-m4";
+
+		dk2-m4 {
+			description = "dk2-m4";
+			loadables = "copro";
+			kernel = "kernel";
+			fdt = "fdt-dk2";
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		dk2 {
+			description = "dk2";
+			kernel = "kernel";
+			fdt = "fdt-dk2";
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		ev1-m4 {
+			description = "ev1-m4";
+			loadables = "copro";
+			kernel = "kernel";
+			fdt = "fdt-ev1";
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		ev1 {
+			description = "ev1";
+			kernel = "kernel";
+			fdt = "fdt-ev1";
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+	};
+};
diff --git a/roms/u-boot/board/st/stm32mp1/fit_kernel_dtb.its b/roms/u-boot/board/st/stm32mp1/fit_kernel_dtb.its
new file mode 100644
index 000000000..8456a3c46
--- /dev/null
+++ b/roms/u-boot/board/st/stm32mp1/fit_kernel_dtb.its
@@ -0,0 +1,82 @@
+/*
+ * Compilation:
+ * mkimage -f fit_kernel_dtb.its fit_kernel_dtb.itb
+ *
+ * Files in linux build dir:
+ * - arch/arm/boot/Image (gzipped in Image.gz)
+ * - arch/arm/boot/dts/stm32mp157c-dk2.dtb
+ * - arch/arm/boot/dts/stm32mp157c-ev1.dtb
+ *
+ * load mmc 0:4 $kernel_addr_r fit_kernel_dtb.itb
+ * bootm $kernel_addr_r
+ * bootm $kernel_addr_r#dk2
+ * bootm $kernel_addr_r#ev1
+ *
+ * or use extlinux.conf in this directory
+ */
+
+/dts-v1/;
+/ {
+	description = "U-Boot fitImage for stm32mp157";
+	#address-cells = <1>;
+
+	images {
+		kernel {
+			description = "Linux kernel";
+			data = /incbin/("Image.gz");
+			type = "kernel";
+			arch = "arm";
+			os = "linux";
+			compression = "gzip";
+			load = <0xC0008000>;
+			entry = <0xC0008000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		fdt-dk2 {
+			description = "FDT dk2";
+			data = /incbin/("stm32mp157c-dk2.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		fdt-ev1 {
+			description = "FDT ev1";
+			data = /incbin/("stm32mp157c-ev1.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+	};
+
+	configurations {
+		default = "dk2";
+
+		dk2 {
+			description = "dk2";
+			kernel = "kernel";
+			fdt = "fdt-dk2";
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		ev1 {
+			description = "ev1";
+			kernel = "kernel";
+			fdt = "fdt-ev1";
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+	};
+};
diff --git a/roms/u-boot/board/st/stm32mp1/spl.c b/roms/u-boot/board/st/stm32mp1/spl.c
new file mode 100644
index 000000000..a6a41780c
--- /dev/null
+++ b/roms/u-boot/board/st/stm32mp1/spl.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include "../common/stpmic1.h"
+
+/* board early initialisation in board_f: need to use global variable */
+static u32 opp_voltage_mv __section(".data");
+
+void board_vddcore_init(u32 voltage_mv)
+{
+	if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER_SUPPORT))
+		opp_voltage_mv = voltage_mv;
+}
+
+int board_early_init_f(void)
+{
+	if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER_SUPPORT))
+		stpmic1_init(opp_voltage_mv);
+
+	return 0;
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
+
+#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
+#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
+
+	/* UART4 clock enable */
+	setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
+
+#define GPIOG_BASE 0x50008000
+	/* GPIOG clock enable */
+	writel(BIT(6), RCC_MP_AHB4ENSETR);
+	/* GPIO configuration for ST boards: Uart4 TX = G11 */
+	writel(0xffbfffff, GPIOG_BASE + 0x00);
+	writel(0x00006000, GPIOG_BASE + 0x24);
+#else
+
+#error("CONFIG_DEBUG_UART_BASE: not supported value")
+
+#endif
+}
+#endif
diff --git a/roms/u-boot/board/st/stm32mp1/stm32mp1.c b/roms/u-boot/board/st/stm32mp1/stm32mp1.c
new file mode 100644
index 000000000..261ec15e1
--- /dev/null
+++ b/roms/u-boot/board/st/stm32mp1/stm32mp1.c
@@ -0,0 +1,916 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_BOARD
+
+#include <common.h>
+#include <adc.h>
+#include <bootm.h>
+#include <clk.h>
+#include <config.h>
+#include <dm.h>
+#include <env.h>
+#include <env_internal.h>
+#include <fdt_support.h>
+#include <g_dnl.h>
+#include <generic-phy.h>
+#include <hang.h>
+#include <i2c.h>
+#include <init.h>
+#include <led.h>
+#include <log.h>
+#include <malloc.h>
+#include <misc.h>
+#include <mtd_node.h>
+#include <net.h>
+#include <netdev.h>
+#include <phy.h>
+#include <remoteproc.h>
+#include <reset.h>
+#include <syscon.h>
+#include <usb.h>
+#include <watchdog.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+#include <jffs2/load_kernel.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <power/regulator.h>
+#include <usb/dwc2_udc.h>
+
+#include "../../st/common/stusb160x.h"
+
+/* SYSCFG registers */
+#define SYSCFG_BOOTR		0x00
+#define SYSCFG_PMCSETR		0x04
+#define SYSCFG_IOCTRLSETR	0x18
+#define SYSCFG_ICNR		0x1C
+#define SYSCFG_CMPCR		0x20
+#define SYSCFG_CMPENSETR	0x24
+#define SYSCFG_PMCCLRR		0x44
+
+#define SYSCFG_BOOTR_BOOT_MASK		GENMASK(2, 0)
+#define SYSCFG_BOOTR_BOOTPD_SHIFT	4
+
+#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE		BIT(0)
+#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI	BIT(1)
+#define SYSCFG_IOCTRLSETR_HSLVEN_ETH		BIT(2)
+#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC		BIT(3)
+#define SYSCFG_IOCTRLSETR_HSLVEN_SPI		BIT(4)
+
+#define SYSCFG_CMPCR_SW_CTRL		BIT(1)
+#define SYSCFG_CMPCR_READY		BIT(8)
+
+#define SYSCFG_CMPENSETR_MPU_EN		BIT(0)
+
+#define SYSCFG_PMCSETR_ETH_CLK_SEL	BIT(16)
+#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL	BIT(17)
+
+#define SYSCFG_PMCSETR_ETH_SELMII	BIT(20)
+
+#define SYSCFG_PMCSETR_ETH_SEL_MASK	GENMASK(23, 21)
+#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII	0
+#define SYSCFG_PMCSETR_ETH_SEL_RGMII	BIT(21)
+#define SYSCFG_PMCSETR_ETH_SEL_RMII	BIT(23)
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+#define USB_LOW_THRESHOLD_UV		200000
+#define USB_WARNING_LOW_THRESHOLD_UV	660000
+#define USB_START_LOW_THRESHOLD_UV	1230000
+#define USB_START_HIGH_THRESHOLD_UV	2150000
+
+int board_early_init_f(void)
+{
+	/* nothing to do, only used in SPL */
+	return 0;
+}
+
+int checkboard(void)
+{
+	int ret;
+	char *mode;
+	u32 otp;
+	struct udevice *dev;
+	const char *fdt_compat;
+	int fdt_compat_len;
+
+	if (IS_ENABLED(CONFIG_TFABOOT))
+		mode = "trusted";
+	else
+		mode = "basic";
+
+	fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
+				 &fdt_compat_len);
+
+	log_info("Board: stm32mp1 in %s mode (%s)\n", mode,
+		 fdt_compat && fdt_compat_len ? fdt_compat : "");
+
+	/* display the STMicroelectronics board identification */
+	if (CONFIG_IS_ENABLED(CMD_STBOARD)) {
+		ret = uclass_get_device_by_driver(UCLASS_MISC,
+						  DM_DRIVER_GET(stm32mp_bsec),
+						  &dev);
+		if (!ret)
+			ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
+					&otp, sizeof(otp));
+		if (ret > 0 && otp)
+			log_info("Board: MB%04x Var%d.%d Rev.%c-%02d\n",
+				 otp >> 16,
+				 (otp >> 12) & 0xF,
+				 (otp >> 4) & 0xF,
+				 ((otp >> 8) & 0xF) - 1 + 'A',
+				 otp & 0xF);
+	}
+
+	return 0;
+}
+
+static void board_key_check(void)
+{
+	ofnode node;
+	struct gpio_desc gpio;
+	enum forced_boot_mode boot_mode = BOOT_NORMAL;
+
+	if (!IS_ENABLED(CONFIG_FASTBOOT) && !IS_ENABLED(CONFIG_CMD_STM32PROG))
+		return;
+
+	node = ofnode_path("/config");
+	if (!ofnode_valid(node)) {
+		log_debug("no /config node?\n");
+		return;
+	}
+	if (IS_ENABLED(CONFIG_FASTBOOT)) {
+		if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
+					       &gpio, GPIOD_IS_IN)) {
+			log_debug("could not find a /config/st,fastboot-gpios\n");
+		} else {
+			if (dm_gpio_get_value(&gpio)) {
+				log_notice("Fastboot key pressed, ");
+				boot_mode = BOOT_FASTBOOT;
+			}
+
+			dm_gpio_free(NULL, &gpio);
+		}
+	}
+	if (IS_ENABLED(CONFIG_CMD_STM32PROG)) {
+		if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
+					       &gpio, GPIOD_IS_IN)) {
+			log_debug("could not find a /config/st,stm32prog-gpios\n");
+		} else {
+			if (dm_gpio_get_value(&gpio)) {
+				log_notice("STM32Programmer key pressed, ");
+				boot_mode = BOOT_STM32PROG;
+			}
+			dm_gpio_free(NULL, &gpio);
+		}
+	}
+	if (boot_mode != BOOT_NORMAL) {
+		log_notice("entering download mode...\n");
+		clrsetbits_le32(TAMP_BOOT_CONTEXT,
+				TAMP_BOOT_FORCED_MASK,
+				boot_mode);
+	}
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+	struct udevice *dwc2_udc_otg;
+	int ret;
+
+	if (!IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG))
+		return -ENODEV;
+
+	/* if typec stusb160x is present, means DK1 or DK2 board */
+	ret = stusb160x_cable_connected();
+	if (ret >= 0)
+		return ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
+					  DM_DRIVER_GET(dwc2_udc_otg),
+					  &dwc2_udc_otg);
+	if (ret) {
+		log_debug("dwc2_udc_otg init failed\n");
+		return ret;
+	}
+
+	return dwc2_udc_B_session_valid(dwc2_udc_otg);
+}
+
+#ifdef CONFIG_USB_GADGET_DOWNLOAD
+#define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
+#define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	if (IS_ENABLED(CONFIG_DFU_OVER_USB) &&
+	    !strcmp(name, "usb_dnl_dfu"))
+		put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
+	else if (IS_ENABLED(CONFIG_FASTBOOT) &&
+		 !strcmp(name, "usb_dnl_fastboot"))
+		put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
+			      &dev->idProduct);
+	else
+		put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
+
+	return 0;
+}
+#endif /* CONFIG_USB_GADGET_DOWNLOAD */
+
+static int get_led(struct udevice **dev, char *led_string)
+{
+	char *led_name;
+	int ret;
+
+	led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
+	if (!led_name) {
+		log_debug("could not find %s config string\n", led_string);
+		return -ENOENT;
+	}
+	ret = led_get_by_label(led_name, dev);
+	if (ret) {
+		log_debug("get=%d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int setup_led(enum led_state_t cmd)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (!CONFIG_IS_ENABLED(LED))
+		return 0;
+
+	ret = get_led(&dev, "u-boot,boot-led");
+	if (ret)
+		return ret;
+
+	ret = led_set_state(dev, cmd);
+	return ret;
+}
+
+static void __maybe_unused led_error_blink(u32 nb_blink)
+{
+	int ret;
+	struct udevice *led;
+	u32 i;
+
+	if (!nb_blink)
+		return;
+
+	if (CONFIG_IS_ENABLED(LED)) {
+		ret = get_led(&led, "u-boot,error-led");
+		if (!ret) {
+			/* make u-boot,error-led blinking */
+			/* if U32_MAX and 125ms interval, for 17.02 years */
+			for (i = 0; i < 2 * nb_blink; i++) {
+				led_set_state(led, LEDST_TOGGLE);
+				mdelay(125);
+				WATCHDOG_RESET();
+			}
+			led_set_state(led, LEDST_ON);
+		}
+	}
+
+	/* infinite: the boot process must be stopped */
+	if (nb_blink == U32_MAX)
+		hang();
+}
+
+static int adc_measurement(ofnode node, int adc_count, int *min_uV, int *max_uV)
+{
+	struct ofnode_phandle_args adc_args;
+	struct udevice *adc;
+	unsigned int raw;
+	int ret, uV;
+	int i;
+
+	for (i = 0; i < adc_count; i++) {
+		if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd",
+						   "#io-channel-cells", 0, i,
+						   &adc_args)) {
+			log_debug("can't find /config/st,adc_usb_pd\n");
+			return 0;
+		}
+
+		ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node,
+						  &adc);
+
+		if (ret) {
+			log_err("Can't get adc device(%d)\n", ret);
+			return ret;
+		}
+
+		ret = adc_channel_single_shot(adc->name, adc_args.args[0],
+					      &raw);
+		if (ret) {
+			log_err("single shot failed for %s[%d]!\n",
+				adc->name, adc_args.args[0]);
+			return ret;
+		}
+		/* Convert to uV */
+		if (!adc_raw_to_uV(adc, raw, &uV)) {
+			if (uV > *max_uV)
+				*max_uV = uV;
+			if (uV < *min_uV)
+				*min_uV = uV;
+			log_debug("%s[%02d] = %u, %d uV\n",
+				  adc->name, adc_args.args[0], raw, uV);
+		} else {
+			log_err("Can't get uV value for %s[%d]\n",
+				adc->name, adc_args.args[0]);
+		}
+	}
+
+	return 0;
+}
+
+static int board_check_usb_power(void)
+{
+	ofnode node;
+	int max_uV = 0;
+	int min_uV = USB_START_HIGH_THRESHOLD_UV;
+	int adc_count, ret;
+	u32 nb_blink;
+	u8 i;
+
+	if (!IS_ENABLED(CONFIG_ADC))
+		return -ENODEV;
+
+	node = ofnode_path("/config");
+	if (!ofnode_valid(node)) {
+		log_debug("no /config node?\n");
+		return -ENOENT;
+	}
+
+	/*
+	 * Retrieve the ADC channels devices and get measurement
+	 * for each of them
+	 */
+	adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd",
+						   "#io-channel-cells", 0);
+	if (adc_count < 0) {
+		if (adc_count == -ENOENT)
+			return 0;
+
+		log_err("Can't find adc channel (%d)\n", adc_count);
+
+		return adc_count;
+	}
+
+	/* perform maximum of 2 ADC measurements to detect power supply current */
+	for (i = 0; i < 2; i++) {
+		ret = adc_measurement(node, adc_count, &min_uV, &max_uV);
+		if (ret)
+			return ret;
+
+		/*
+		 * If highest value is inside 1.23 Volts and 2.10 Volts, that means
+		 * board is plugged on an USB-C 3A power supply and boot process can
+		 * continue.
+		 */
+		if (max_uV > USB_START_LOW_THRESHOLD_UV &&
+		    max_uV <= USB_START_HIGH_THRESHOLD_UV &&
+		    min_uV <= USB_LOW_THRESHOLD_UV)
+			return 0;
+
+		if (i == 0) {
+			log_err("Previous ADC measurements was not the one expected, retry in 20ms\n");
+			mdelay(20);  /* equal to max tPDDebounce duration (min 10ms - max 20ms) */
+		}
+	}
+
+	log_notice("****************************************************\n");
+	/*
+	 * If highest and lowest value are either both below
+	 * USB_LOW_THRESHOLD_UV or both above USB_LOW_THRESHOLD_UV, that
+	 * means USB TYPE-C is in unattached mode, this is an issue, make
+	 * u-boot,error-led blinking and stop boot process.
+	 */
+	if ((max_uV > USB_LOW_THRESHOLD_UV &&
+	     min_uV > USB_LOW_THRESHOLD_UV) ||
+	     (max_uV <= USB_LOW_THRESHOLD_UV &&
+	     min_uV <= USB_LOW_THRESHOLD_UV)) {
+		log_notice("* ERROR USB TYPE-C connection in unattached mode   *\n");
+		log_notice("* Check that USB TYPE-C cable is correctly plugged *\n");
+		/* with 125ms interval, led will blink for 17.02 years ....*/
+		nb_blink = U32_MAX;
+	}
+
+	if (max_uV > USB_LOW_THRESHOLD_UV &&
+	    max_uV <= USB_WARNING_LOW_THRESHOLD_UV &&
+	    min_uV <= USB_LOW_THRESHOLD_UV) {
+		log_notice("*        WARNING 500mA power supply detected       *\n");
+		nb_blink = 2;
+	}
+
+	if (max_uV > USB_WARNING_LOW_THRESHOLD_UV &&
+	    max_uV <= USB_START_LOW_THRESHOLD_UV &&
+	    min_uV <= USB_LOW_THRESHOLD_UV) {
+		log_notice("*       WARNING 1.5A power supply detected        *\n");
+		nb_blink = 3;
+	}
+
+	/*
+	 * If highest value is above 2.15 Volts that means that the USB TypeC
+	 * supplies more than 3 Amp, this is not compliant with TypeC specification
+	 */
+	if (max_uV > USB_START_HIGH_THRESHOLD_UV) {
+		log_notice("*      USB TYPE-C charger not compliant with       *\n");
+		log_notice("*                   specification                  *\n");
+		log_notice("****************************************************\n\n");
+		/* with 125ms interval, led will blink for 17.02 years ....*/
+		nb_blink = U32_MAX;
+	} else {
+		log_notice("*     Current too low, use a 3A power supply!      *\n");
+		log_notice("****************************************************\n\n");
+	}
+
+	led_error_blink(nb_blink);
+
+	return 0;
+}
+
+static void sysconf_init(void)
+{
+	u8 *syscfg;
+	struct udevice *pwr_dev;
+	struct udevice *pwr_reg;
+	struct udevice *dev;
+	u32 otp = 0;
+	int ret;
+	u32 bootr, val;
+
+	syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+
+	/* interconnect update : select master using the port 1 */
+	/* LTDC = AXI_M9 */
+	/* GPU  = AXI_M8 */
+	/* today information is hardcoded in U-Boot */
+	writel(BIT(9), syscfg + SYSCFG_ICNR);
+
+	/* disable Pull-Down for boot pin connected to VDD */
+	bootr = readl(syscfg + SYSCFG_BOOTR);
+	bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
+	bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
+	writel(bootr, syscfg + SYSCFG_BOOTR);
+
+	/* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
+	 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
+	 * The customer will have to disable this for low frequencies
+	 * or if AFMUX is selected but the function not used, typically for
+	 * TRACE. Otherwise, impact on power consumption.
+	 *
+	 * WARNING:
+	 *   enabling High Speed mode while VDD>2.7V
+	 *   with the OTP product_below_2v5 (OTP 18, BIT 13)
+	 *   erroneously set to 1 can damage the IC!
+	 *   => U-Boot set the register only if VDD < 2.7V (in DT)
+	 *      but this value need to be consistent with board design
+	 */
+	ret = uclass_get_device_by_driver(UCLASS_PMIC,
+					  DM_DRIVER_GET(stm32mp_pwr_pmic),
+					  &pwr_dev);
+	if (!ret && IS_ENABLED(CONFIG_DM_REGULATOR)) {
+		ret = uclass_get_device_by_driver(UCLASS_MISC,
+						  DM_DRIVER_GET(stm32mp_bsec),
+						  &dev);
+		if (ret) {
+			log_err("Can't find stm32mp_bsec driver\n");
+			return;
+		}
+
+		ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
+		if (ret > 0)
+			otp = otp & BIT(13);
+
+		/* get VDD = vdd-supply */
+		ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
+						  &pwr_reg);
+
+		/* check if VDD is Low Voltage */
+		if (!ret) {
+			if (regulator_get_value(pwr_reg) < 2700000) {
+				writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
+				       SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
+				       SYSCFG_IOCTRLSETR_HSLVEN_ETH |
+				       SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
+				       SYSCFG_IOCTRLSETR_HSLVEN_SPI,
+				       syscfg + SYSCFG_IOCTRLSETR);
+
+				if (!otp)
+					log_err("product_below_2v5=0: HSLVEN protected by HW\n");
+			} else {
+				if (otp)
+					log_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
+			}
+		} else {
+			log_debug("VDD unknown");
+		}
+	}
+
+	/* activate automatic I/O compensation
+	 * warning: need to ensure CSI enabled and ready in clock driver
+	 */
+	writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
+
+	/* poll until ready (1s timeout) */
+	ret = readl_poll_timeout(syscfg + SYSCFG_CMPCR, val,
+				 val & SYSCFG_CMPCR_READY,
+				 1000000);
+	if (ret) {
+		log_err("SYSCFG: I/O compensation failed, timeout.\n");
+		led_error_blink(10);
+	}
+
+	clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+}
+
+/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
+static int dk2_i2c1_fix(void)
+{
+	ofnode node;
+	struct gpio_desc hdmi, audio;
+	int ret = 0;
+
+	if (!IS_ENABLED(CONFIG_DM_REGULATOR))
+		return -ENODEV;
+
+	node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
+	if (!ofnode_valid(node)) {
+		log_debug("no hdmi-transmitter@39 ?\n");
+		return -ENOENT;
+	}
+
+	if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
+				       &hdmi, GPIOD_IS_OUT)) {
+		log_debug("could not find reset-gpios\n");
+		return -ENOENT;
+	}
+
+	node = ofnode_path("/soc/i2c@40012000/cs42l51@4a");
+	if (!ofnode_valid(node)) {
+		log_debug("no cs42l51@4a ?\n");
+		return -ENOENT;
+	}
+
+	if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
+				       &audio, GPIOD_IS_OUT)) {
+		log_debug("could not find reset-gpios\n");
+		return -ENOENT;
+	}
+
+	/* before power up, insure that HDMI and AUDIO IC is under reset */
+	ret = dm_gpio_set_value(&hdmi, 1);
+	if (ret) {
+		log_err("can't set_value for hdmi_nrst gpio");
+		goto error;
+	}
+	ret = dm_gpio_set_value(&audio, 1);
+	if (ret) {
+		log_err("can't set_value for audio_nrst gpio");
+		goto error;
+	}
+
+	/* power-up audio IC */
+	regulator_autoset_by_name("v1v8_audio", NULL);
+
+	/* power-up HDMI IC */
+	regulator_autoset_by_name("v1v2_hdmi", NULL);
+	regulator_autoset_by_name("v3v3_hdmi", NULL);
+
+error:
+	return ret;
+}
+
+static bool board_is_dk2(void)
+{
+	if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
+	    of_machine_is_compatible("st,stm32mp157c-dk2"))
+		return true;
+
+	return false;
+}
+
+static bool board_is_ev1(void)
+{
+	if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
+	    (of_machine_is_compatible("st,stm32mp157a-ev1") ||
+	     of_machine_is_compatible("st,stm32mp157c-ev1") ||
+	     of_machine_is_compatible("st,stm32mp157d-ev1") ||
+	     of_machine_is_compatible("st,stm32mp157f-ev1")))
+		return true;
+
+	return false;
+}
+
+/* touchscreen driver: only used for pincontrol configuration */
+static const struct udevice_id goodix_ids[] = {
+	{ .compatible = "goodix,gt9147", },
+	{ }
+};
+
+U_BOOT_DRIVER(goodix) = {
+	.name		= "goodix",
+	.id		= UCLASS_NOP,
+	.of_match	= goodix_ids,
+};
+
+static void board_ev1_init(void)
+{
+	struct udevice *dev;
+
+	/* configure IRQ line on EV1 for touchscreen before LCD reset */
+	uclass_get_device_by_driver(UCLASS_NOP, DM_DRIVER_GET(goodix), &dev);
+}
+
+/* board dependent setup after realloc */
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
+
+	if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
+		gpio_hog_probe_all();
+
+	board_key_check();
+
+	if (board_is_ev1())
+		board_ev1_init();
+
+	if (board_is_dk2())
+		dk2_i2c1_fix();
+
+	if (IS_ENABLED(CONFIG_DM_REGULATOR))
+		regulators_enable_boot_on(_DEBUG);
+
+	if (!IS_ENABLED(CONFIG_TFABOOT))
+		sysconf_init();
+
+	if (CONFIG_IS_ENABLED(LED))
+		led_default_state();
+
+	setup_led(LEDST_ON);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	const void *fdt_compat;
+	int fdt_compat_len;
+	int ret;
+	u32 otp;
+	struct udevice *dev;
+	char buf[10];
+	char dtb_name[256];
+	int buf_len;
+
+	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+		fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
+					 &fdt_compat_len);
+		if (fdt_compat && fdt_compat_len) {
+			if (strncmp(fdt_compat, "st,", 3) != 0) {
+				env_set("board_name", fdt_compat);
+			} else {
+				env_set("board_name", fdt_compat + 3);
+
+				buf_len = sizeof(dtb_name);
+				strncpy(dtb_name, fdt_compat + 3, buf_len);
+				buf_len -= strlen(fdt_compat + 3);
+				strncat(dtb_name, ".dtb", buf_len);
+				env_set("fdtfile", dtb_name);
+			}
+		}
+		ret = uclass_get_device_by_driver(UCLASS_MISC,
+						  DM_DRIVER_GET(stm32mp_bsec),
+						  &dev);
+
+		if (!ret)
+			ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
+					&otp, sizeof(otp));
+		if (ret > 0 && otp) {
+			snprintf(buf, sizeof(buf), "0x%04x", otp >> 16);
+			env_set("board_id", buf);
+
+			snprintf(buf, sizeof(buf), "0x%04x",
+				 ((otp >> 8) & 0xF) - 1 + 0xA);
+			env_set("board_rev", buf);
+		}
+	}
+
+	/* for DK1/DK2 boards */
+	board_check_usb_power();
+
+	return 0;
+}
+
+void board_quiesce_devices(void)
+{
+	setup_led(LEDST_OFF);
+}
+
+/* eth init function : weak called in eqos driver */
+int board_interface_eth_init(struct udevice *dev,
+			     phy_interface_t interface_type)
+{
+	u8 *syscfg;
+	u32 value;
+	bool eth_clk_sel_reg = false;
+	bool eth_ref_clk_sel_reg = false;
+
+	/* Gigabit Ethernet 125MHz clock selection. */
+	eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
+
+	/* Ethernet 50Mhz RMII clock selection */
+	eth_ref_clk_sel_reg =
+		dev_read_bool(dev, "st,eth_ref_clk_sel");
+
+	syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+
+	if (!syscfg)
+		return -ENODEV;
+
+	switch (interface_type) {
+	case PHY_INTERFACE_MODE_MII:
+		value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
+			SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
+		log_debug("PHY_INTERFACE_MODE_MII\n");
+		break;
+	case PHY_INTERFACE_MODE_GMII:
+		if (eth_clk_sel_reg)
+			value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
+				SYSCFG_PMCSETR_ETH_CLK_SEL;
+		else
+			value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
+		log_debug("PHY_INTERFACE_MODE_GMII\n");
+		break;
+	case PHY_INTERFACE_MODE_RMII:
+		if (eth_ref_clk_sel_reg)
+			value = SYSCFG_PMCSETR_ETH_SEL_RMII |
+				SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
+		else
+			value = SYSCFG_PMCSETR_ETH_SEL_RMII;
+		log_debug("PHY_INTERFACE_MODE_RMII\n");
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		if (eth_clk_sel_reg)
+			value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
+				SYSCFG_PMCSETR_ETH_CLK_SEL;
+		else
+			value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
+		log_debug("PHY_INTERFACE_MODE_RGMII\n");
+		break;
+	default:
+		log_debug("Do not manage %d interface\n",
+			  interface_type);
+		/* Do not manage others interfaces */
+		return -EINVAL;
+	}
+
+	/* clear and set ETH configuration bits */
+	writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
+	       SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
+	       syscfg + SYSCFG_PMCCLRR);
+	writel(value, syscfg + SYSCFG_PMCSETR);
+
+	return 0;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	u32 bootmode = get_bootmode();
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
+	case BOOT_FLASH_SD:
+	case BOOT_FLASH_EMMC:
+		if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
+			return ENVL_MMC;
+		else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4))
+			return ENVL_EXT4;
+		else
+			return ENVL_NOWHERE;
+
+	case BOOT_FLASH_NAND:
+	case BOOT_FLASH_SPINAND:
+		if (CONFIG_IS_ENABLED(ENV_IS_IN_UBI))
+			return ENVL_UBI;
+		else
+			return ENVL_NOWHERE;
+
+	case BOOT_FLASH_NOR:
+		if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		else
+			return ENVL_NOWHERE;
+
+	default:
+		return ENVL_NOWHERE;
+	}
+}
+
+const char *env_ext4_get_intf(void)
+{
+	u32 bootmode = get_bootmode();
+
+	switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
+	case BOOT_FLASH_SD:
+	case BOOT_FLASH_EMMC:
+		return "mmc";
+	default:
+		return "";
+	}
+}
+
+const char *env_ext4_get_dev_part(void)
+{
+	static char *const env_dev_part =
+#ifdef CONFIG_ENV_EXT4_DEVICE_AND_PART
+		CONFIG_ENV_EXT4_DEVICE_AND_PART;
+#else
+		"";
+#endif
+	static char *const dev_part[] = {"0:auto", "1:auto", "2:auto"};
+
+	if (strlen(env_dev_part) > 0)
+		return env_dev_part;
+
+	u32 bootmode = get_bootmode();
+
+	return dev_part[(bootmode & TAMP_BOOT_INSTANCE_MASK) - 1];
+}
+
+int mmc_get_env_dev(void)
+{
+	u32 bootmode;
+
+	if (CONFIG_SYS_MMC_ENV_DEV >= 0)
+		return CONFIG_SYS_MMC_ENV_DEV;
+
+	bootmode = get_bootmode();
+
+	/* use boot instance to select the correct mmc device identifier */
+	return (bootmode & TAMP_BOOT_INSTANCE_MASK) - 1;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	static const struct node_info nodes[] = {
+		{ "st,stm32f469-qspi",		MTD_DEV_TYPE_NOR,  },
+		{ "st,stm32f469-qspi",		MTD_DEV_TYPE_SPINAND},
+		{ "st,stm32mp15-fmc2",		MTD_DEV_TYPE_NAND, },
+		{ "st,stm32mp1-fmc2-nfc",	MTD_DEV_TYPE_NAND, },
+	};
+	char *boot_device;
+
+	/* Check the boot-source and don't update MTD for serial or usb boot */
+	boot_device = env_get("boot_device");
+	if (!boot_device ||
+	    (strcmp(boot_device, "serial") && strcmp(boot_device, "usb")))
+		if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS))
+			fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+	return 0;
+}
+#endif
+
+static void board_copro_image_process(ulong fw_image, size_t fw_size)
+{
+	int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
+
+	if (!rproc_is_initialized())
+		if (rproc_init()) {
+			log_err("Remote Processor %d initialization failed\n",
+				id);
+			return;
+		}
+
+	ret = rproc_load(id, fw_image, fw_size);
+	log_err("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
+		id, fw_image, fw_size, ret ? " Failed!" : " Success!");
+
+	if (!ret)
+		rproc_start(id);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);
diff --git a/roms/u-boot/board/st/stv0991/Kconfig b/roms/u-boot/board/st/stv0991/Kconfig
new file mode 100644
index 000000000..007712f9c
--- /dev/null
+++ b/roms/u-boot/board/st/stv0991/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_STV0991
+
+config SYS_BOARD
+	default "stv0991"
+
+config SYS_VENDOR
+	default "st"
+
+config SYS_SOC
+	default "stv0991"
+
+config SYS_CONFIG_NAME
+	default "stv0991"
+
+endif
diff --git a/roms/u-boot/board/st/stv0991/MAINTAINERS b/roms/u-boot/board/st/stv0991/MAINTAINERS
new file mode 100644
index 000000000..e7a2ccaa1
--- /dev/null
+++ b/roms/u-boot/board/st/stv0991/MAINTAINERS
@@ -0,0 +1,6 @@
+STV0991 APPLICATION BOARD
+M:	Vikas Manocha <vikas.manocha@st.com>
+S:	Maintained
+F:	board/st/stv0991/
+F:	include/configs/stv0991.h
+F:	configs/stv0991_defconfig
diff --git a/roms/u-boot/board/st/stv0991/Makefile b/roms/u-boot/board/st/stv0991/Makefile
new file mode 100644
index 000000000..7f6d719c3
--- /dev/null
+++ b/roms/u-boot/board/st/stv0991/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+
+obj-y	:= stv0991.o
diff --git a/roms/u-boot/board/st/stv0991/stv0991.c b/roms/u-boot/board/st/stv0991/stv0991.c
new file mode 100644
index 000000000..3b0de82db
--- /dev/null
+++ b/roms/u-boot/board/st/stv0991/stv0991.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <dm.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/arch/stv0991_periph.h>
+#include <asm/arch/stv0991_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dm/platform_data/serial_pl01x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct gpio_regs *const gpioa_regs =
+		(struct gpio_regs *) GPIOA_BASE_ADDR;
+
+#ifndef CONFIG_OF_CONTROL
+static const struct pl01x_serial_plat serial_plat = {
+	.base = 0x80406000,
+	.type = TYPE_PL011,
+	.clock = 2700 * 1000,
+};
+
+U_BOOT_DRVINFO(stv09911_serials) = {
+	.name = "serial_pl01x",
+	.plat = &serial_plat,
+};
+#endif
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int progress)
+{
+	printf("%i\n", progress);
+}
+#endif
+
+void enable_eth_phy(void)
+{
+	/* Set GPIOA_06 pad HIGH (Appli board)*/
+	writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
+	writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
+}
+int board_eth_enable(void)
+{
+	stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
+	clock_setup(ETH_CLOCK_CFG);
+	enable_eth_phy();
+	return 0;
+}
+
+int board_qspi_enable(void)
+{
+	stv0991_pinmux_config(QSPI_CS_CLK_PAD);
+	clock_setup(QSPI_CLOCK_CFG);
+	return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	board_eth_enable();
+	board_qspi_enable();
+	return 0;
+}
+
+int board_uart_init(void)
+{
+	stv0991_pinmux_config(UART_GPIOC_30_31);
+	clock_setup(UART_CLOCK_CFG);
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	board_uart_init();
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(struct bd_info *bis)
+{
+	int ret = 0;
+
+#if defined(CONFIG_ETH_DESIGNWARE)
+	u32 interface = PHY_INTERFACE_MODE_MII;
+	if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
+		ret++;
+#endif
+	return ret;
+}
+#endif
diff --git a/roms/u-boot/board/ste/stemmy/Kconfig b/roms/u-boot/board/ste/stemmy/Kconfig
new file mode 100644
index 000000000..b890ba51c
--- /dev/null
+++ b/roms/u-boot/board/ste/stemmy/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_STEMMY
+
+config SYS_BOARD
+	default "stemmy"
+
+config SYS_VENDOR
+	default "ste"
+
+config SYS_CONFIG_NAME
+	default "stemmy"
+
+endif
diff --git a/roms/u-boot/board/ste/stemmy/MAINTAINERS b/roms/u-boot/board/ste/stemmy/MAINTAINERS
new file mode 100644
index 000000000..37daabea9
--- /dev/null
+++ b/roms/u-boot/board/ste/stemmy/MAINTAINERS
@@ -0,0 +1,6 @@
+STEMMY BOARD
+M:	Stephan Gerhold <stephan@gerhold.net>
+S:	Maintained
+F:	board/ste/stemmy/
+F:	include/configs/stemmy.h
+F:	configs/stemmy_defconfig
diff --git a/roms/u-boot/board/ste/stemmy/Makefile b/roms/u-boot/board/ste/stemmy/Makefile
new file mode 100644
index 000000000..1245099bc
--- /dev/null
+++ b/roms/u-boot/board/ste/stemmy/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+obj-y	:= stemmy.o
diff --git a/roms/u-boot/board/ste/stemmy/README b/roms/u-boot/board/ste/stemmy/README
new file mode 100644
index 000000000..81f72426f
--- /dev/null
+++ b/roms/u-boot/board/ste/stemmy/README
@@ -0,0 +1,49 @@
+ST-Ericsson U8500 Samsung "stemmy" board
+========================================
+
+The "stemmy" board supports Samsung smartphones released with
+the ST-Ericsson NovaThor U8500 SoC, e.g.
+
+	- Samsung Galaxy S III mini (GT-I8190)	"golden"
+	- Samsung Galaxy S Advance (GT-I9070)	"janice"
+	- Samsung Galaxy Xcover 2 (GT-S7710)	"skomer"
+
+and likely others as well (untested).
+
+At the moment, U-Boot is intended to be chain-loaded from
+the original Samsung bootloader, not replacing it entirely.
+
+Installation
+------------
+
+1. Setup cross compiler, e.g. export CROSS_COMPILE=arm-none-eabi-
+2. make stemmy_defconfig
+3. make
+
+For newer devices (golden and skomer), the U-Boot binary has to be packed into
+an Android boot image. janice boots the raw U-Boot binary from the boot partition.
+
+4. Obtain mkbootimg, e.g. https://android.googlesource.com/platform/system/core/+/refs/tags/android-7.1.2_r37/mkbootimg/mkbootimg
+5. mkbootimg \
+    --kernel=u-boot.bin \
+    --base=0x00000000 \
+    --kernel_offset=0x00100000 \
+    --ramdisk_offset=0x02000000 \
+    --tags_offset=0x00000100 \
+    --output=u-boot.img
+
+6. Enter Samsung download mode (press Power + Home + Volume Down)
+7. Flash U-Boot image to Android boot partition using Heimdall:
+     https://gitlab.com/BenjaminDobell/Heimdall
+
+   heimdall flash --Kernel u-boot.(bin|img)
+
+8. After reboot U-Boot prompt should appear via UART.
+
+UART
+----
+
+UART is available through the micro USB port, similar to the Carkit standard.
+With a ~619kOhm resistor between ID and GND, 1.8V RX/TX is available at D+/D-.
+
+Make sure to connect the UART cable *before* turning on the phone.
diff --git a/roms/u-boot/board/ste/stemmy/stemmy.c b/roms/u-boot/board/ste/stemmy/stemmy.c
new file mode 100644
index 000000000..b9b2a6fdd
--- /dev/null
+++ b/roms/u-boot/board/ste/stemmy/stemmy.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2019 Stephan Gerhold <stephan@gerhold.net>
+ */
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/board/storopack/smegw01/Kconfig b/roms/u-boot/board/storopack/smegw01/Kconfig
new file mode 100644
index 000000000..4503b6541
--- /dev/null
+++ b/roms/u-boot/board/storopack/smegw01/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SMEGW01
+
+config SYS_BOARD
+	default "smegw01"
+
+config SYS_VENDOR
+	default "storopack"
+
+config SYS_CONFIG_NAME
+	default "smegw01"
+
+endif
diff --git a/roms/u-boot/board/storopack/smegw01/MAINTAINERS b/roms/u-boot/board/storopack/smegw01/MAINTAINERS
new file mode 100644
index 000000000..6acb8b934
--- /dev/null
+++ b/roms/u-boot/board/storopack/smegw01/MAINTAINERS
@@ -0,0 +1,7 @@
+SMEGW01 BOARD
+M:	Fabio Estevam <festevam@denx.de>
+S:	Maintained
+F:	board/storopack/
+F:	arch/arm/dts/imx7d-smegw01.dts
+F:	configs/smegw01_defconfig
+F:	include/configs/smegw01.h
diff --git a/roms/u-boot/board/storopack/smegw01/Makefile b/roms/u-boot/board/storopack/smegw01/Makefile
new file mode 100644
index 000000000..f02e7bb8b
--- /dev/null
+++ b/roms/u-boot/board/storopack/smegw01/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2016 NXP Semiconductors
+
+obj-y  := smegw01.o
diff --git a/roms/u-boot/board/storopack/smegw01/imximage.cfg b/roms/u-boot/board/storopack/smegw01/imximage.cfg
new file mode 100644
index 000000000..c7fa06996
--- /dev/null
+++ b/roms/u-boot/board/storopack/smegw01/imximage.cfg
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 PHYTEC America, LLC
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+IMAGE_VERSION	2
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* DDR initialization came from Phytec */
+DATA 4 0x30340004 0x4F400005
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x0040002b
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x090b1109
+DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000802
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0184 0x02000100
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00001f15
+DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x07070707
+DATA 4 0x307a0218 0x0f0f0707
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000d6e
+DATA 4 0x30790020 0x0a0a0a0a
+DATA 4 0x30790030 0x06060606
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+CHECK_BITS_SET 4 0x307900c4 0x1
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+CHECK_BITS_SET 4 0x307a0004 0x1
diff --git a/roms/u-boot/board/storopack/smegw01/smegw01.c b/roms/u-boot/board/storopack/smegw01/smegw01.c
new file mode 100644
index 000000000..e6bff80e5
--- /dev/null
+++ b/roms/u-boot/board/storopack/smegw01/smegw01.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/hab.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/setup.h>
+#include <asm/bootm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
+			PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+};
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
+			(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+	int ret;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
+			IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
+
+	ret = set_clk_enet(ENET_125MHZ);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_fec();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	/*
+	 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+	 * since we use PMIC_PWRON to reset the board.
+	 */
+	clrsetbits_le16(&wdog->wcr, 0, 0x10);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/sunxi/MAINTAINERS b/roms/u-boot/board/sunxi/MAINTAINERS
new file mode 100644
index 000000000..76eba2ad2
--- /dev/null
+++ b/roms/u-boot/board/sunxi/MAINTAINERS
@@ -0,0 +1,531 @@
+SUNXI BOARD
+M:	Hans de Goede <hdegoede@redhat.com>
+S:	Maintained
+F:	board/sunxi/
+F:	include/configs/sun4i.h
+F:	configs/A10-OLinuXino-Lime_defconfig
+F:	configs/ba10_tv_box_defconfig
+F:	configs/Chuwi_V7_CW0825_defconfig
+F:	configs/Cubieboard_defconfig
+F:	configs/dserve_dsrv9703c_defconfig
+F:	configs/Hyundai_A7HD_defconfig
+F:	configs/inet1_defconfig
+F:	configs/inet97fv2_defconfig
+F:	configs/inet9f_rev03_defconfig
+F:	configs/jesurun_q5_defconfig
+F:	configs/Mele_A1000_defconfig
+F:	configs/Mele_M3_defconfig
+F:	configs/Mini-X_defconfig
+F:	configs/mk802_defconfig
+F:	configs/mk802ii_defconfig
+F:	configs/pov_protab2_ips9_defconfig
+F:	include/configs/sun5i.h
+F:	configs/A10s-OLinuXino-M_defconfig
+F:	configs/A13-OLinuXino_defconfig
+F:	configs/A13-OLinuXinoM_defconfig
+F:	configs/Auxtek-T003_defconfig
+F:	configs/Auxtek-T004_defconfig
+F:	configs/CHIP_defconfig
+F:	configs/CHIP_pro_defconfig
+F:	configs/difrnce_dit4350_defconfig
+F:	configs/Empire_electronix_d709_defconfig
+F:	configs/Empire_electronix_m712_defconfig
+F:	configs/inet98v_rev2_defconfig
+F:	configs/mk802_a10s_defconfig
+F:	configs/q8_a13_tablet_defconfig
+F:	configs/r7-tv-dongle_defconfig
+F:	configs/UTOO_P66_defconfig
+F:	configs/Wobo_i5_defconfig
+F:	include/configs/sun6i.h
+F:	configs/colorfly_e708_q1_defconfig
+F:	configs/CSQ_CS908_defconfig
+F:	configs/inet_q972_defconfig
+F:	configs/Mele_A1000G_quad_defconfig
+F:	configs/Mele_M9_defconfig
+F:	configs/Sinovoip_BPI_M2_defconfig
+F:	include/configs/sun7i.h
+F:	configs/A20-OLinuXino_MICRO_defconfig
+F:	configs/A20-OLinuXino_MICRO-eMMC_defconfig
+F:	configs/Bananapi_defconfig
+F:	configs/Bananapro_defconfig
+F:	configs/i12-tvbox_defconfig
+F:	configs/Linksprite_pcDuino3_defconfig
+F:	configs/Linksprite_pcDuino3_fdt_defconfig
+F:	configs/Orangepi_defconfig
+F:	configs/Orangepi_mini_defconfig
+F:	configs/qt840a_defconfig
+F:	configs/Wits_Pro_A20_DKT_defconfig
+F:	include/configs/sun8i.h
+F:	configs/sun8i_a23_evb_defconfig
+F:	configs/ga10h_v1_1_defconfig
+F:	configs/gt90h_v4_defconfig
+F:	configs/inet86dz_defconfig
+F:	configs/orangepi_2_defconfig
+F:	configs/orangepi_lite_defconfig
+F:	configs/orangepi_one_defconfig
+F:	configs/orangepi_pc_defconfig
+F:	configs/orangepi_pc_plus_defconfig
+F:	configs/orangepi_plus_defconfig
+F:	configs/orangepi_plus2e_defconfig
+F:	configs/polaroid_mid2407pxe03_defconfig
+F:	configs/polaroid_mid2809pxe04_defconfig
+F:	configs/q8_a23_tablet_800x480_defconfig
+F:	configs/q8_a33_tablet_800x480_defconfig
+F:	configs/q8_a33_tablet_1024x600_defconfig
+F:	include/configs/sun9i.h
+F:	configs/Merrii_A80_Optimus_defconfig
+F:	include/configs/sun50i.h
+
+A20-OLIMEX-SOM-EVB BOARD
+M:	Marcus Cooper <codekipper@gmail.com>
+S:	Maintained
+F:	configs/A20-Olimex-SOM-EVB_defconfig
+
+A20-OLINUXINO-LIME BOARD
+M:	FUKAUMI Naoki <naobsd@gmail.com>
+S:	Maintained
+F:	configs/A20-OLinuXino-Lime_defconfig
+
+A20-OLINUXINO-LIME2 BOARD
+M:	Iain Paton <ipaton0@gmail.com>
+S:	Maintained
+F:	configs/A20-OLinuXino-Lime2_defconfig
+
+A20-OLINUXINO-LIME2-EMMC BOARD
+M:	Olliver Schinagl <oliver@schinagl.nl>
+S:	Maintained
+F:	configs/A20-OLinuXino-Lime2-eMMC_defconfig
+
+A33-OLINUXINO BOARD
+M:	Stefan Mavrodiev <stefan.mavrodiev@gmail.com>
+S:	Maintained
+F:	configs/A33-OLinuXino_defconfig
+
+A64-OLINUXINO BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/a64-olinuxino_defconfig
+
+A64-OLINUXINO-EMMC BOARD
+M:	Sunil Mohan Adapa <sunil@medhas.org>
+S:	Maintained
+F:	configs/a64-olinuxino-emmc_defconfig
+
+A80 OPTIMUS BOARD
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/Merrii_A80_Optimus_defconfig
+
+AINOL AW1 BOARD
+M:	Paul Kocialkowski <contact@paulk.fr>
+S:	Maintained
+F:	configs/Ainol_AW1_defconfig
+
+AMARULA A64-RELIC
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/amarula_a64_relic_defconfig
+F:	arch/arm/dts/sun50i-a64-amarula-relic.dts
+
+AMPE A76 BOARD
+M:	Paul Kocialkowski <contact@paulk.fr>
+S:	Maintained
+F:	configs/Ampe_A76_defconfig
+
+BANANAPI M1 PLUS
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/bananapi_m1_plus_defconfig
+
+BANANAPI M2 BERRY
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/bananapi_m2_berry_defconfig
+
+BANANAPI M2 PLUS BOARDS
+M:	Icenowy Zheng <icenowy@aosc.io>
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/bananapi_m2_plus_h3_defconfig
+F:	configs/bananapi_m2_plus_h5_defconfig
+
+BANANAPI M2 ULTRA BOARD
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/Bananapi_M2_Ultra_defconfig
+F:	arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
+
+BANANAPI M2 MAGIC BOARD
+M:	Maxime Ripard <mripard@kernel.org>
+S:	Maintained
+F:	configs/Bananapi_m2m_defconfig
+F:	arch/arm/dts/sun8i-r16-bananapi-m2m.dts
+
+BANANAPI M2 ZERO BOARD
+M:	Icenowy Zheng <icenowy@aosc.io>
+S:	Maintained
+F:	configs/bananapi_m2_zero_defconfig
+
+BANANAPI M64
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/bananapi_m64_defconfig
+
+BEELINK GS1
+M:	Clément Péron <peron.clem@gmail.com>
+S:	Maintained
+F:	configs/beelink_gs1_defconfig
+F:	arch/arm/dts/sun50i-h6-beelink-gs1.dts
+
+BEELINK X2 BOARD
+M:	Marcus Cooper <codekipper@gmail.com>
+S:	Maintained
+F:	configs/beelink_x2_defconfig
+F:	arch/arm/dts/sun8i-h3-beelink-x2.dts
+
+COLOMBUS BOARD
+M:	Maxime Ripard <mripard@kernel.org>
+S:	Maintained
+F:	configs/Colombus_defconfig
+
+CUBIEBOARD2 BOARD
+M:	Ian Campbell <ijc@hellion.org.uk>
+M:	Hans de Goede <hdegoede@redhat.com>
+S:	Maintained
+F:	include/configs/sun7i.h
+F:	configs/Cubieboard2_defconfig
+F:	configs/Cubietruck_defconfig
+
+CUBIEBOARD4 BOARD
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/Cubieboard4_defconfig
+
+CUBIETRUCK-PLUS BOARD
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/Cubietruck_plus_defconfig
+
+EMLID NEUTIS N5 DEV BOARD
+M:	Aleksandr Aleksandrov <aleksandr.aleksandrov@emlid.com>
+S:	Maintained
+F:	configs/emlid_neutis_n5_devboard_defconfig
+
+GEMEI-G9 TABLET
+M:	Priit Laes <plaes@plaes.org>
+S:	Maintained
+F:	configs/sunxi_Gemei_G9_defconfig
+
+H8HOMLET PROTO A83T BOARD
+M:	VishnuPatekar <vishnupatekar0510@gmail.com>
+S:	Maintained
+F:	configs/h8_homlet_v2_defconfig
+
+HUMMINGBIRD-A31 BOARD
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/Hummingbird_A31_defconfig
+
+ICnova-A20-SWAC BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	configs/icnova-a20-swac_defconfig
+
+ITEAD IBOX BOARD
+M:	Marcus Cooper <codekipper@gmail.com>
+S:	Maintained
+F:	configs/Itead_Ibox_A20_defconfig
+
+INET 3F BOARD
+M:	Paul Kocialkowski <contact@paulk.fr>
+S:	Maintained
+F:	configs/iNet_3F_defconfig
+
+INET 3W BOARD
+M:	Paul Kocialkowski <contact@paulk.fr>
+S:	Maintained
+F:	configs/iNet_3W_defconfig
+
+INET 86VS BOARD
+M:	Michal Suchanek <hramrach@gmail.com>
+S:	Maintained
+F:	configs/iNet_86VS_defconfig
+
+INET D978 BOARD
+M:	Icenowy Zheng <icenowy@aosc.xyz>
+S:	Maintained
+F:	configs/iNet_D978_rev2_defconfig
+
+LAMOBO-R1 BOARD
+M:	Jelle de Jong <jelledejong@powercraft.nl>
+S:	Maintained
+F:	configs/Lamobo_R1_defconfig
+
+LICHEEPI-ZERO BOARD
+M:	Icenowy Zheng <icenowy@aosc.xyz>
+S:	Maintained
+F:	configs/LicheePi_Zero_defconfig
+
+LINKSPRITE-PCDUINO BOARD
+M:	Zoltan Herpai <wigyori@uid0.hu>
+S:	Maintained
+F:	configs/Linksprite_pcDuino_defconfig
+
+LINKSPRITE-PCDUINO3-NANO BOARD
+M:	Adam Sampson <ats@offog.org>
+S:	Maintained
+F:	configs/Linksprite_pcDuino3_Nano_defconfig
+
+MARSBOARD-A10 BOARD
+M:	Aleksei Mamlin <mamlinav@gmail.com>
+S:	Maintained
+F:	configs/Marsboard_A10_defconfig
+
+MELE I7 BOARD
+M:	Marcus Cooper <codekipper@gmail.com>
+S:	Maintained
+F:	configs/Mele_I7_defconfig
+
+MELE M5 BOARD
+M:	Ian Campbell <ijc@hellion.org.uk>
+S:	Maintained
+F:	configs/Mele_M5_defconfig
+
+MIXTILE-LOFTQ BOARD
+M:  Phil Han <pengphei@sina.com>
+S:  Maintained
+F:  configs/mixtile_loftq_defconfig
+
+MK808C BOARD
+M:	Marcus Cooper <codekipper@gmail.com>
+S:	Maintained
+F:	configs/MK808C_defconfig
+
+MSI-PRIMO73 BOARD
+M:	Siarhei Siamashka <siarhei.siamashka@gmail.com>
+S:	Maintained
+F:	configs/MSI_Primo73_defconfig
+
+MSI-PRIMO81 BOARD
+M:	Siarhei Siamashka <siarhei.siamashka@gmail.com>
+S:	Maintained
+F:	configs/MSI_Primo81_defconfig
+
+LIBRETECH ALL-H3-CC BOARDS
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/libretech_all_h3_cc_h2_plus_defconfig
+F:	configs/libretech_all_h3_cc_h3_defconfig
+F:	configs/libretech_all_h3_cc_h5_defconfig
+
+LIBRETECH ALL-H3-IT BOARDS
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/libretech_all_h3_it_h5_defconfig
+
+LIBRETECH ALL-H5-CC BOARDS
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/libretech_all_h5_cc_h5_defconfig
+
+NANOPI-M1 BOARD
+M:	Mylène Josserand <mylene.josserand@free-electrons.com>
+S:	Maintained
+F:	configs/nanopi_m1_defconfig
+
+NANOPI-M1 PLUS BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/nanopi_m1_plus_defconfig
+
+NANOPI-NEO BOARD
+M:	Jelle van der Waa <jelle@vdwaa.nl>
+S:	Maintained
+F:	configs/nanopi_neo_defconfig
+
+NANOPI-NEO2 BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/nanopi_neo2_defconfig
+
+NANOPI-NEO-PLUS2 BOARD
+M:	Antony Antony <antony@phenome.org>
+S:	Maintained
+F:	configs/nanopi_neo_plus2_defconfig
+
+NANOPI-NEO-AIR BOARD
+M:	Jelle van der Waa <jelle@vdwaa.nl>
+S:	Maintained
+F:	configs/nanopi_neo_air_defconfig
+
+NANOPI-A64 BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/nanopi_a64_defconfig
+
+NINTENDO NES CLASSIC EDITION BOARD
+M:	FUKAUMI Naoki <naobsd@gmail.com>
+S:	Maintained
+F:	configs/Nintendo_NES_Classic_Edition_defconfig
+
+OCEANIC 5205 5INMFD BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/oceanic_5205_5inmfd_defconfig
+
+OLIMEX A20-SOM204 BOARD
+M:	Stefan Mavrodiev <stefan@olimex.com>
+S:	Maintained
+F:	configs/A20-Olimex-SOM204-EVB_defconfig
+F:	configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+
+OLIMEX TERES-I BOARD
+M:	Jonas Smedegaard <dr@jones.dk>
+M:	Icenowy Zheng <icenowy@aosc.io>
+S:	Maintained
+F:	configs/teres_i_defconfig
+
+ORANGEPI 3 BOARD
+M:	Andre Heider <a.heider@gmail.com>
+S:	Maintained
+F:	configs/orangepi_3_defconfig
+
+ORANGEPI LITE2 BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/orangepi_lite2_defconfig
+
+ORANGEPI ONE PLUS BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/orangepi_one_plus_defconfig
+
+ORANGEPI WIN/WIN PLUS BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/orangepi_win_defconfig
+
+ORANGEPI ZERO BOARD
+M:	Icenowy Zheng <icenowy@aosc.xyz>
+S:	Maintained
+F:	configs/orangepi_zero_defconfig
+
+ORANGEPI ZERO PLUS BOARD
+M:	Hauke Mehrtens <hauke@hauke-m.de>
+S:	Maintained
+F:	configs/orangepi_zero_plus_defconfig
+
+ORANGEPI ZERO PLUS 2 BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/orangepi_zero_plus2_defconfig
+
+ORANGEPI ZERO PLUS 2 H3 BOARD
+M:	Diego Rondini <diego.rondini@kynetics.com>
+S:	Maintained
+F:	configs/orangepi_zero_plus2_h3_defconfig
+
+ORANGEPI ZERO 2 BOARD
+M:	Jernej Skrabec <jernej.skrabec@siol.net>
+S:	Maintained
+F:	configs/orangepi_zero2_defconfig
+
+ORANGEPI PC 2 BOARD
+M:	Andre Przywara <andre.przywara@arm.com>
+S:	Maintained
+F:	configs/orangepi_pc2_defconfig
+
+ORANGEPI PRIME BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/orangepi_prime_defconfig
+
+ORANGEPI R1 BOARD
+M:	Hauke Mehrtens <hauke@hauke-m.de>
+S:	Maintained
+F:	configs/orangepi_r1_defconfig
+
+PINEBOOK BOARD:
+M:	Vasily Khoruzhick <anarsoul@gmail.com>
+S:	Maintained
+F:	configs/pinebook_defconfig
+
+PINECUBE BOARD:
+M:	Icenowy Zheng <icenowy@aosc.io>
+S:	Maintained
+F:	configs/pinecube_defconfig
+
+PINE64 BOARDS
+M:	Andre Przywara <andre.przywara@arm.com>
+S:	Maintained
+F:	configs/pine64_plus_defconfig
+F:	configs/pine64-lts_defconfig
+
+PINE H64 BOARD
+M:	Icenowy Zheng <icenowy@aosc.io>
+S:	Maintained
+F:	configs/pine_h64_defconfig
+
+PINEPHONE BOARD
+M:	Samuel Holland <samuel@sholland.org>
+S:	Maintained
+F:	configs/pinephone_defconfig
+
+R16 EVB PARROT BOARD
+M:	Quentin Schulz <quentin.schulz@free-electrons.com>
+S:	Maintained
+F:	configs/parrot_r16_defconfig
+
+SINLINX SINA31s BOARD
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/Sinlinx_SinA31s_defconfig
+W:	http://linux-sunxi.org/Sinlinx_SinA31s
+
+SINLINX SINA33 BOARD
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/Sinlinx_SinA33_defconfig
+W:	http://linux-sunxi.org/Sinlinx_SinA33
+
+SINOVOIP BPI M3 A83T BOARD
+M:	VishnuPatekar <vishnupatekar0510@gmail.com>
+S:	Maintained
+F:	configs/Sinovoip_BPI_M3_defconfig
+
+SOPINE BOARD
+M:	Icenowy Zheng <icenowy@aosc.io>
+S:	Maintained
+F:	configs/sopine_baseboard_defconfig
+
+SUNCHIP CX-A99 BOARD
+M:	Rask Ingemann Lambertsen <rask@formelder.dk>
+S:	Maintained
+F:	configs/Sunchip_CX-A99_defconfig
+W:	https://linux-sunxi.org/Sunchip_CX-A99
+
+TANIX TX6 BOARD
+M:	Jernej Skrabec <jernej.skrabec@siol.net>
+S:	Maintained
+F:	configs/tanix_tx6_defconfig
+W:	https://linux-sunxi.org/Tanix_TX6
+
+TBS A711 BOARD
+M:	Maxime Ripard <mripard@kernel.org>
+S:	Maintained
+F:	configs/tbs_a711_defconfig
+
+WEXLER-TAB7200 BOARD
+M:	Aleksei Mamlin <mamlinav@gmail.com>
+S:	Maintained
+F:	configs/Wexler_TAB7200_defconfig
+
+YONES TOPTECH BD1078 BOARD
+M:	Paul Kocialkowski <contact@paulk.fr>
+S:	Maintained
+F:	configs/Yones_Toptech_BD1078_defconfig
+
+YONES TOPTECH BS1078 V2 BOARD
+M:	Peter Korsgaard <peter@korsgaard.com>
+S:	Maintained
+F:	configs/Yones_Toptech_BS1078_V2_defconfig
diff --git a/roms/u-boot/board/sunxi/Makefile b/roms/u-boot/board/sunxi/Makefile
new file mode 100644
index 000000000..d96b7897b
--- /dev/null
+++ b/roms/u-boot/board/sunxi/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+#
+# Based on some other board Makefile
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+obj-y	+= board.o
+obj-$(CONFIG_SUN7I_GMAC)	+= gmac.o
+obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i_auto.o
+obj-$(CONFIG_MACH_SUN5I)	+= dram_sun5i_auto.o
+obj-$(CONFIG_MACH_SUN7I)	+= dram_sun5i_auto.o
+obj-$(CONFIG_CHIP_DIP_SCAN)	+= chip.o
diff --git a/roms/u-boot/board/sunxi/README.nand b/roms/u-boot/board/sunxi/README.nand
new file mode 100644
index 000000000..0e97316ae
--- /dev/null
+++ b/roms/u-boot/board/sunxi/README.nand
@@ -0,0 +1,54 @@
+Allwinner NAND flashing
+=======================
+
+A lot of Allwinner devices, especially the older ones (pre-H3 era),
+comes with a NAND. NANDs storages are a pretty weak choice when it
+comes to the reliability, and it comes with a number of flaws like
+read and write disturbs, data retention issues, bloks becoming
+unusable, etc.
+
+In order to mitigate that, various strategies have been found to be
+able to recover from those issues like ECC, hardware randomization,
+and of course, redundancy for the critical parts.
+
+This is obviously something that we will take into account when
+creating our images. However, the BROM will use a quite weird pattern
+when accessing the NAND, and will access only at most 4kB per page,
+which means that we also have to split that binary accross several
+pages.
+
+In order to accomodate that, we create a tool that will generate an
+SPL image that is ready to be programmed directly embedding the ECCs,
+randomized, and with the necessary bits needed to reduce the number of
+bitflips. The U-Boot build system, when configured for the NAND (with
+CONFIG_MTD_RAW_NAND=y) will also generate the image sunxi-spl-with-ecc.bin
+that will have been generated by that tool.
+
+In order to flash your U-Boot image onto a board, assuming that the
+board is in FEL mode, you'll need the sunxi-tools that you can find at
+this repository: https://github.com/linux-sunxi/sunxi-tools
+
+Then, you'll need to first load an SPL to initialise the RAM:
+sunxi-fel spl spl/sunxi-spl.bin
+
+Load the binaries we'll flash into RAM:
+sunxi-fel write 0x4a000000 u-boot-dtb.bin
+sunxi-fel write 0x43000000 spl/sunxi-spl-with-ecc.bin
+
+And execute U-Boot
+sunxi-fel exe 0x4a000000
+
+On your board, you'll now have all the needed binaries into RAM, so
+you only need to erase the NAND...
+
+nand erase.chip
+
+Then write the SPL and its backup:
+
+nand write.raw.noverify 0x43000000 0 40
+nand write.raw.noverify 0x43000000 0x400000 40
+
+And finally write the U-Boot binary:
+nand write 0x4a000000 0x800000 0xc0000
+
+You can now reboot and enjoy your NAND.
\ No newline at end of file
diff --git a/roms/u-boot/board/sunxi/README.sunxi64 b/roms/u-boot/board/sunxi/README.sunxi64
new file mode 100644
index 000000000..4803bc9ff
--- /dev/null
+++ b/roms/u-boot/board/sunxi/README.sunxi64
@@ -0,0 +1,216 @@
+Allwinner 64-bit boards README
+==============================
+
+Newer Allwinner SoCs feature ARMv8 cores (ARM Cortex-A53) with support for
+both the 64-bit AArch64 mode and the ARMv7 compatible 32-bit AArch32 mode.
+Examples are the Allwinner A64 (used for instance on the Pine64 board) or
+the Allwinner H5 SoC (as used on the OrangePi PC 2).
+These SoCs are wired to start in AArch32 mode on reset and execute 32-bit
+code from the Boot ROM (BROM). As this has some implications on U-Boot, this
+file describes how to make full use of the 64-bit capabilities.
+
+Quick Start / Overview
+======================
+- Build the ARM Trusted Firmware binary (see "ARM Trusted Firmware (ATF)" below)
+  $ cd /src/arm-trusted-firmware
+  $ make PLAT=sun50i_a64 DEBUG=1 bl31
+- Build the SCP firmware binary (see "SCP firmware (Crust)" below)
+  $ cd /src/crust
+  $ make pine64_plus_defconfig && make -j5 scp
+- Build U-Boot (see "SPL/U-Boot" below)
+  $ export BL31=/path/to/bl31.bin
+  $ export SCP=/src/crust/build/scp/scp.bin
+  $ make pine64_plus_defconfig && make -j5
+- Transfer to an uSD card (see "microSD card" below)
+  $ dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1
+- Boot and enjoy!
+
+Building the firmware
+=====================
+
+The Allwinner A64/H5/H6 firmware consists of several parts: U-Boot's SPL,
+ARM Trusted Firmware (ATF), optional System Control Processor (SCP) firmware
+(e.g. Crust), and the U-Boot proper.
+
+The SPL will load all of the other firmware binaries into RAM, along with the
+right device tree blob (.dtb), and will pass execution to ATF (in EL3). If SCP
+firmware was loaded, ATF will power on the SCP and wait for it to boot.
+ATF will then drop into U-Boot proper (in EL2).
+
+As the ATF binary and SCP firmware will become part of the U-Boot image file,
+you will need to build them first.
+
+ ARM Trusted Firmware (ATF)
+----------------------------
+Checkout the latest master branch from the official ATF repository [1] and
+build it:
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make PLAT=sun50i_a64 DEBUG=1 bl31
+The resulting binary is build/sun50i_a64/debug/bl31.bin. Either put the
+location of this file into the BL31 environment variable or copy this to
+the root of your U-Boot build directory (or create a symbolic link).
+$ export BL31=/src/arm-trusted-firmware/build/sun50i_a64/debug/bl31.bin
+  (adjust the actual path accordingly)
+The platform target "sun50i_a64" covers all boards with either an Allwinner
+A64 or H5 SoC (since they are very similar). For boards with an Allwinner H6
+SoC use "sun50i_h6".
+
+If you run into size issues with the resulting U-Boot image file, it might
+help to use a release build, by using "DEBUG=0" when building bl31.bin.
+As sometimes the ATF build process is a bit picky about the toolchain used,
+or if you can't be bothered with building ATF, there are known working
+binaries in the firmware repository[3], purely for convenience reasons.
+
+ SCP firmware (Crust)
+----------------------
+SCP firmware is responsible for implementing system suspend/resume, and (on
+boards without a PMIC) soft poweroff/on. ATF contains fallback code for CPU
+power control, so SCP firmware is optional if you don't need either of these
+features. It runs on the AR100, with is an or1k CPU, not ARM, so it needs a
+different cross toolchain.
+
+There is one SCP firmware implementation currently available, Crust:
+$ git clone https://github.com/crust-firmware/crust
+$ cd crust
+$ export CROSS_COMPILE=or1k-linux-musl-
+$ make pine64_plus_defconfig
+$ make scp
+
+The same configuration generally works on any board with the same SoC (A64, H5,
+or H6), so if there is no config for your board, use one for a similar board.
+
+Like for ATF, U-Boot finds the SCP firmware binary via an environment variable:
+$ export SCP=/src/crust/build/scp/scp.bin
+
+If you do not want to use SCP firmware, you can silence the warning from binman
+by pointing it to an empty file:
+$ export SCP=/dev/null
+
+ SPL/U-Boot
+------------
+Both U-Boot proper and the SPL are using the 64-bit mode. As the boot ROM
+enters the SPL still in AArch32 secure SVC mode, there is some shim code to
+enter AArch64 very early. The rest of the SPL runs in AArch64 EL3.
+U-Boot proper runs in EL2 and can load any AArch64 code (using the "go"
+command), EFI applications (with "bootefi") or arm64 Linux kernel images
+(often named "Image"), using the "booti" command.
+
+$ make clean
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make pine64_plus_defconfig
+$ make
+
+This will build the SPL in spl/sunxi-spl.bin and a FIT image called u-boot.itb,
+which contains the rest of the firmware. u-boot-sunxi-with-spl.bin joins those
+two components in one convenient image file.
+
+
+Boot process
+============
+The on-die BROM code will try several methods to load and execute the firmware.
+On a typical board like the Pine64 this will result in the following boot order:
+
+1) Reading 32KB from sector 16 (@8K) of the microSD card to SRAM A1. If the
+BROM finds the magic "eGON" header in the first bytes, it will execute that
+code. If not (no SD card at all or invalid magic), it will:
+2) Try to read 32KB from sector 16 (@8K) of memory connected to the MMC2
+controller, typically an on-board eMMC chip. If there is no eMMC or it does
+not contain a valid boot header, it will:
+3) Initialize the SPI0 controller and try to access a NOR flash connected to
+it (using the CS0 pin). If a flash chip is found, the BROM will load the
+first 32KB (from offset 0) into SRAM A1. Now it checks for the magic eGON
+header and checksum and will execute the code upon finding it. If not, it will:
+4) Initialize the USB OTG controller and will wait for a host to connect to
+it, speaking the Allwinner proprietary (but deciphered) "FEL" USB protocol.
+
+
+To boot the Pine64 board, you can use U-Boot and any of the described methods.
+
+FEL boot (USB OTG)
+------------------
+FEL is the name of the Allwinner defined USB boot protocol built in the
+mask ROM of most Allwinner SoCs. It allows to bootstrap a board solely
+by using the USB-OTG interface and a host port on another computer.
+As the FEL mode is controlled by the boot ROM, it expects to be running in
+AArch32. For now the AArch64 SPL cannot properly return into FEL mode, so the
+feature is disabled in the configuration at the moment.
+The repository in [3] contains FEL capable SPL binaries, built using an
+off-tree branch to generate 32-bit ARM code (along with instructions
+how to re-create them).
+
+microSD card
+------------
+Transfer the SPL and the U-Boot FIT image directly to an uSD card:
+# dd if=spl/sunxi-spl.bin of=/dev/sdx bs=8k seek=1
+# dd if=u-boot.itb of=/dev/sdx bs=8k seek=5
+# sync
+(replace /dev/sdx with you SD card device file name, which could be
+/dev/mmcblk[x] as well).
+
+Alternatively you can use the SPL and the U-Boot FIT image combined into a
+single file and transfer that instead:
+# dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1
+
+You can partition the microSD card, but leave the first MB unallocated (most
+partitioning tools will do this anyway).
+
+NOR flash
+---------
+Some boards (like the SoPine, Pinebook or the OrangePi PC2) come with a
+soldered SPI NOR flash chip. On other boards like the Pine64 such a chip
+can be connected to the SPI0/CS0 pins on the PI-2 headers.
+Create the SPL and FIT image like described above for the SD card.
+Now connect either an "A to A" USB cable to the upper USB port on the Pine64
+or get an adaptor and use a regular A-microB cable connected to it. Other
+boards often have a proper micro-B USB socket connected to the USB OTB port.
+Remove a microSD card from the slot and power on the board.
+On your host computer download and build the sunxi-tools package[2], then
+use "sunxi-fel" to access the board:
+$ ./sunxi-fel ver -v -p
+This should give you an output starting with: AWUSBFEX soc=00001689(A64) ...
+Now use the sunxi-fel tool to write to the NOR flash:
+$ ./sunxi-fel spiflash-write 0 spl/sunxi-spl.bin
+$ ./sunxi-fel spiflash-write 32768 u-boot.itb
+Now boot the board without an SD card inserted and you should see the
+U-Boot prompt on the serial console.
+
+(Legacy) boot0 method
+---------------------
+boot0 is Allwinner's secondary program loader and it can be used as some kind
+of SPL replacement to get U-Boot up and running from an microSD card.
+For some time using boot0 was the only option to get the Pine64 booted.
+With working DRAM init code in U-Boot's SPL this is no longer necessary,
+but this method is described here for the sake of completeness.
+Please note that this method works only with the boot0 files shipped with
+A64 based boards, the H5 uses an incompatible layout which is not supported
+by this method.
+
+The boot0 binary is a 32 KByte blob and contained in the official Pine64 images
+distributed by Pine64 or Allwinner. It can be easily extracted from a micro
+SD card or an image file:
+# dd if=/dev/sd<x> of=boot0.bin bs=8k skip=1 count=4
+where /dev/sd<x> is the device name of the uSD card or the name of the image
+file. Apparently Allwinner allows re-distribution of this proprietary code
+"as-is".
+This boot0 blob takes care of DRAM initialisation and loads the remaining
+firmware parts, then switches the core into AArch64 mode.
+The original boot0 code looks for U-Boot at a certain place on an uSD card
+(at 19096 KB), also it expects a header with magic bytes and a checksum.
+There is a tool called boot0img[3] which takes a boot0.bin image and a compiled
+U-Boot binary (plus other binaries) and will populate that header accordingly.
+To make space for the magic header, the pine64_plus_defconfig will make sure
+there is sufficient space at the beginning of the U-Boot binary.
+boot0img will also take care of putting the different binaries at the right
+places on the uSD card and works around unused, but mandatory parts by using
+trampoline code. See the output of "boot0img -h" for more information.
+boot0img can also patch boot0 to avoid loading U-Boot from 19MB, instead
+fetching it from just behind the boot0 binary (-B option).
+$ ./boot0img -o firmware.img -B boot0.img -u u-boot-dtb.bin -e -s bl31.bin \
+-a 0x44008 -d trampoline64:0x44000
+Then write this image to a microSD card, replacing /dev/sdx with the right
+device file (see above):
+$ dd if=firmware.img of=/dev/sdx bs=8k seek=1
+
+[1] https://github.com/ARM-software/arm-trusted-firmware.git
+[2] git://github.com/linux-sunxi/sunxi-tools.git
+[3] https://github.com/apritzel/pine64/
diff --git a/roms/u-boot/board/sunxi/board.c b/roms/u-boot/board/sunxi/board.c
new file mode 100644
index 000000000..21651a1bf
--- /dev/null
+++ b/roms/u-boot/board/sunxi/board.c
@@ -0,0 +1,1057 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Some board init for the Allwinner A10-evb board.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <mmc.h>
+#include <axp_pmic.h>
+#include <generic-phy.h>
+#include <phy-sun4i-usb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/display.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/spl.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <u-boot/crc.h>
+#ifndef CONFIG_ARM64
+#include <asm/armv7.h>
+#endif
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <u-boot/crc.h>
+#include <env_internal.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <nand.h>
+#include <net.h>
+#include <spl.h>
+#include <sy8106a.h>
+#include <asm/setup.h>
+
+#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
+/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
+int soft_i2c_gpio_sda;
+int soft_i2c_gpio_scl;
+
+static int soft_i2c_board_init(void)
+{
+	int ret;
+
+	soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
+	if (soft_i2c_gpio_sda < 0) {
+		printf("Error invalid soft i2c sda pin: '%s', err %d\n",
+		       CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
+		return soft_i2c_gpio_sda;
+	}
+	ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
+	if (ret) {
+		printf("Error requesting soft i2c sda pin: '%s', err %d\n",
+		       CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
+		return ret;
+	}
+
+	soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
+	if (soft_i2c_gpio_scl < 0) {
+		printf("Error invalid soft i2c scl pin: '%s', err %d\n",
+		       CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
+		return soft_i2c_gpio_scl;
+	}
+	ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
+	if (ret) {
+		printf("Error requesting soft i2c scl pin: '%s', err %d\n",
+		       CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
+		return ret;
+	}
+
+	return 0;
+}
+#else
+static int soft_i2c_board_init(void) { return 0; }
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void i2c_init_board(void)
+{
+#ifdef CONFIG_I2C0_ENABLE
+#if defined(CONFIG_MACH_SUN4I) || \
+    defined(CONFIG_MACH_SUN5I) || \
+    defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
+	clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
+	clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUN8I_V3S)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
+	clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
+	clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUN50I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
+	clock_twi_onoff(0, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C1_ENABLE
+#if defined(CONFIG_MACH_SUN4I) || \
+    defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
+	clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN5I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
+	clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
+	clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
+	clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN50I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
+	clock_twi_onoff(1, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C2_ENABLE
+#if defined(CONFIG_MACH_SUN4I) || \
+    defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
+	clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN5I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
+	clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
+	clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
+	clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN50I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
+	clock_twi_onoff(2, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C3_ENABLE
+#if defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
+	clock_twi_onoff(3, 1);
+#elif defined(CONFIG_MACH_SUN7I) || \
+      defined(CONFIG_MACH_SUN8I_R40)
+	sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
+	sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
+	clock_twi_onoff(3, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C4_ENABLE
+#if defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
+	sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
+	sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
+	clock_twi_onoff(4, 1);
+#endif
+#endif
+
+#ifdef CONFIG_R_I2C_ENABLE
+#ifdef CONFIG_MACH_SUN50I
+	clock_twi_onoff(5, 1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
+#elif CONFIG_MACH_SUN50I_H616
+	clock_twi_onoff(5, 1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
+#else
+	clock_twi_onoff(5, 1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
+#endif
+#endif
+}
+
+#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	switch (prio) {
+	case 0:
+		return ENVL_FAT;
+
+	case 1:
+		return ENVL_MMC;
+
+	default:
+		return ENVL_UNKNOWN;
+	}
+}
+#endif
+
+#ifdef CONFIG_DM_MMC
+static void mmc_pinmux_setup(int sdc);
+#endif
+
+/* add board specific code here */
+int board_init(void)
+{
+	__maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
+
+	gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
+
+#ifndef CONFIG_ARM64
+	asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
+	debug("id_pfr1: 0x%08x\n", id_pfr1);
+	/* Generic Timer Extension available? */
+	if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
+		uint32_t freq;
+
+		debug("Setting CNTFRQ\n");
+
+		/*
+		 * CNTFRQ is a secure register, so we will crash if we try to
+		 * write this from the non-secure world (read is OK, though).
+		 * In case some bootcode has already set the correct value,
+		 * we avoid the risk of writing to it.
+		 */
+		asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
+		if (freq != COUNTER_FREQUENCY) {
+			debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
+			      freq, COUNTER_FREQUENCY);
+#ifdef CONFIG_NON_SECURE
+			printf("arch timer frequency is wrong, but cannot adjust it\n");
+#else
+			asm volatile("mcr p15, 0, %0, c14, c0, 0"
+				     : : "r"(COUNTER_FREQUENCY));
+#endif
+		}
+	}
+#endif /* !CONFIG_ARM64 */
+
+	ret = axp_gpio_init();
+	if (ret)
+		return ret;
+
+	/* strcmp() would look better, but doesn't get optimised away. */
+	if (CONFIG_SATAPWR[0]) {
+		satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
+		if (satapwr_pin >= 0) {
+			gpio_request(satapwr_pin, "satapwr");
+			gpio_direction_output(satapwr_pin, 1);
+
+			/*
+			 * Give the attached SATA device time to power-up
+			 * to avoid link timeouts
+			 */
+			mdelay(500);
+		}
+	}
+
+	if (CONFIG_MACPWR[0]) {
+		macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
+		if (macpwr_pin >= 0) {
+			gpio_request(macpwr_pin, "macpwr");
+			gpio_direction_output(macpwr_pin, 1);
+		}
+	}
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	/*
+	 * Temporary workaround for enabling I2C clocks until proper sunxi DM
+	 * clk, reset and pinctrl drivers land.
+	 */
+	i2c_init_board();
+#endif
+
+#ifdef CONFIG_DM_MMC
+	/*
+	 * Temporary workaround for enabling MMC clocks until a sunxi DM
+	 * pinctrl driver lands.
+	 */
+	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
+#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
+	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
+#endif
+#endif	/* CONFIG_DM_MMC */
+
+	/* Uses dm gpio code so do this here and not in i2c_init_board() */
+	return soft_i2c_board_init();
+}
+
+/*
+ * On older SoCs the SPL is actually at address zero, so using NULL as
+ * an error value does not work.
+ */
+#define INVALID_SPL_HEADER ((void *)~0UL)
+
+static struct boot_file_head * get_spl_header(uint8_t req_version)
+{
+	struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
+	uint8_t spl_header_version = spl->spl_signature[3];
+
+	/* Is there really the SPL header (still) there? */
+	if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
+		return INVALID_SPL_HEADER;
+
+	if (spl_header_version < req_version) {
+		printf("sunxi SPL version mismatch: expected %u, got %u\n",
+		       req_version, spl_header_version);
+		return INVALID_SPL_HEADER;
+	}
+
+	return spl;
+}
+
+static const char *get_spl_dt_name(void)
+{
+	struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
+
+	/* Check if there is a DT name stored in the SPL header. */
+	if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
+		return (char *)spl + spl->dt_name_offset;
+
+	return NULL;
+}
+
+int dram_init(void)
+{
+	struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
+
+	if (spl == INVALID_SPL_HEADER)
+		gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
+					    PHYS_SDRAM_0_SIZE);
+	else
+		gd->ram_size = (phys_addr_t)spl->dram_size << 20;
+
+	if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
+		gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
+
+	return 0;
+}
+
+#if defined(CONFIG_NAND_SUNXI)
+static void nand_pinmux_setup(void)
+{
+	unsigned int pin;
+
+	for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
+		sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
+
+#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
+	for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
+		sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
+#endif
+	/* sun4i / sun7i do have a PC23, but it is not used for nand,
+	 * only sun7i has a PC24 */
+#ifdef CONFIG_MACH_SUN7I
+	sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
+#endif
+}
+
+static void nand_clock_setup(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
+    defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
+	setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
+#endif
+	setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
+}
+
+void board_nand_init(void)
+{
+	nand_pinmux_setup();
+	nand_clock_setup();
+#ifndef CONFIG_SPL_BUILD
+	sunxi_nand_init();
+#endif
+}
+#endif
+
+#ifdef CONFIG_MMC
+static void mmc_pinmux_setup(int sdc)
+{
+	unsigned int pin;
+	__maybe_unused int pins;
+
+	switch (sdc) {
+	case 0:
+		/* SDC0: PF0-PF5 */
+		for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+		break;
+
+	case 1:
+		pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
+		if (pins == SUNXI_GPIO_H) {
+			/* SDC1: PH22-PH-27 */
+			for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		} else {
+			/* SDC1: PG0-PG5 */
+			for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		}
+#elif defined(CONFIG_MACH_SUN5I)
+		/* SDC1: PG3-PG8 */
+		for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+#elif defined(CONFIG_MACH_SUN6I)
+		/* SDC1: PG0-PG5 */
+		for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+#elif defined(CONFIG_MACH_SUN8I)
+		if (pins == SUNXI_GPIO_D) {
+			/* SDC1: PD2-PD7 */
+			for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		} else {
+			/* SDC1: PG0-PG5 */
+			for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		}
+#endif
+		break;
+
+	case 2:
+		pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+		/* SDC2: PC6-PC11 */
+		for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+#elif defined(CONFIG_MACH_SUN5I)
+		if (pins == SUNXI_GPIO_E) {
+			/* SDC2: PE4-PE9 */
+			for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		} else {
+			/* SDC2: PC6-PC15 */
+			for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		}
+#elif defined(CONFIG_MACH_SUN6I)
+		if (pins == SUNXI_GPIO_A) {
+			/* SDC2: PA9-PA14 */
+			for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		} else {
+			/* SDC2: PC6-PC15, PC24 */
+			for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+
+			sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
+			sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+		}
+#elif defined(CONFIG_MACH_SUN8I_R40)
+		/* SDC2: PC6-PC15, PC24 */
+		for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+
+		sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
+		sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+		sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
+		/* SDC2: PC5-PC6, PC8-PC16 */
+		for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+
+		for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+#elif defined(CONFIG_MACH_SUN50I_H6)
+		/* SDC2: PC4-PC14 */
+		for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+#elif defined(CONFIG_MACH_SUN9I)
+		/* SDC2: PC6-PC16 */
+		for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+#endif
+		break;
+
+	case 3:
+		pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
+		/* SDC3: PI4-PI9 */
+		for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+#elif defined(CONFIG_MACH_SUN6I)
+		if (pins == SUNXI_GPIO_A) {
+			/* SDC3: PA9-PA14 */
+			for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+		} else {
+			/* SDC3: PC6-PC15, PC24 */
+			for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+				sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
+				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+				sunxi_gpio_set_drv(pin, 2);
+			}
+
+			sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
+			sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+		}
+#endif
+		break;
+
+	default:
+		printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
+		break;
+	}
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	__maybe_unused struct mmc *mmc0, *mmc1;
+
+	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
+	mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
+	if (!mmc0)
+		return -1;
+
+#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
+	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
+	mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
+	if (!mmc1)
+		return -1;
+#endif
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+
+static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
+{
+	struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
+
+	if (spl == INVALID_SPL_HEADER)
+		return;
+
+	/* Promote the header version for U-Boot proper, if needed. */
+	if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
+		spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
+
+	spl->dram_size = dram_size >> 20;
+}
+
+void sunxi_board_init(void)
+{
+	int power_failed = 0;
+
+#ifdef CONFIG_SY8106A_POWER
+	power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
+#endif
+
+#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
+	defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
+	defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+	power_failed = axp_init();
+
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
+	power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
+#endif
+#if !defined(CONFIG_AXP305_POWER)
+	power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
+	power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
+#endif
+#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
+	power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
+#endif
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
+	power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
+#endif
+
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
+	power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
+#endif
+#if !defined(CONFIG_AXP305_POWER)
+	power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
+#endif
+#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
+	power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
+#endif
+#ifdef CONFIG_AXP209_POWER
+	power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
+#endif
+
+#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
+	defined(CONFIG_AXP818_POWER)
+	power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
+	power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
+#if !defined CONFIG_AXP809_POWER
+	power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
+	power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
+#endif
+	power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
+	power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
+	power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
+#endif
+
+#ifdef CONFIG_AXP818_POWER
+	power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
+	power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
+	power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
+#endif
+
+#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+	power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
+#endif
+#endif
+	printf("DRAM:");
+	gd->ram_size = sunxi_dram_init();
+	printf(" %d MiB\n", (int)(gd->ram_size >> 20));
+	if (!gd->ram_size)
+		hang();
+
+	sunxi_spl_store_dram_size(gd->ram_size);
+
+	/*
+	 * Only clock up the CPU to full speed if we are reasonably
+	 * assured it's being powered with suitable core voltage
+	 */
+	if (!power_failed)
+		clock_set_pll1(CONFIG_SYS_CLK_FREQ);
+	else
+		printf("Failed to set core voltage! Can't set CPU frequency\n");
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+int g_dnl_board_usb_cable_connected(void)
+{
+	struct udevice *dev;
+	struct phy phy;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
+	if (ret) {
+		pr_err("%s: Cannot find USB device\n", __func__);
+		return ret;
+	}
+
+	ret = generic_phy_get_by_name(dev, "usb", &phy);
+	if (ret) {
+		pr_err("failed to get %s USB PHY\n", dev->name);
+		return ret;
+	}
+
+	ret = generic_phy_init(&phy);
+	if (ret) {
+		pr_debug("failed to init %s USB PHY\n", dev->name);
+		return ret;
+	}
+
+	ret = sun4i_usb_phy_vbus_detect(&phy);
+	if (ret == 1) {
+		pr_err("A charger is plugged into the OTG\n");
+		return -ENODEV;
+	}
+
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *serial_string;
+	unsigned long long serial;
+
+	serial_string = env_get("serial#");
+
+	if (serial_string) {
+		serial = simple_strtoull(serial_string, NULL, 16);
+
+		serialnr->high = (unsigned int) (serial >> 32);
+		serialnr->low = (unsigned int) (serial & 0xffffffff);
+	} else {
+		serialnr->high = 0;
+		serialnr->low = 0;
+	}
+}
+#endif
+
+/*
+ * Check the SPL header for the "sunxi" variant. If found: parse values
+ * that might have been passed by the loader ("fel" utility), and update
+ * the environment accordingly.
+ */
+static void parse_spl_header(const uint32_t spl_addr)
+{
+	struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
+
+	if (spl == INVALID_SPL_HEADER)
+		return;
+
+	if (!spl->fel_script_address)
+		return;
+
+	if (spl->fel_uEnv_length != 0) {
+		/*
+		 * data is expected in uEnv.txt compatible format, so "env
+		 * import -t" the string(s) at fel_script_address right away.
+		 */
+		himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
+			  spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
+		return;
+	}
+	/* otherwise assume .scr format (mkimage-type script) */
+	env_set_hex("fel_scriptaddr", spl->fel_script_address);
+}
+
+static bool get_unique_sid(unsigned int *sid)
+{
+	if (sunxi_get_sid(sid) != 0)
+		return false;
+
+	if (!sid[0])
+		return false;
+
+	/*
+	 * The single words 1 - 3 of the SID have quite a few bits
+	 * which are the same on many models, so we take a crc32
+	 * of all 3 words, to get a more unique value.
+	 *
+	 * Note we only do this on newer SoCs as we cannot change
+	 * the algorithm on older SoCs since those have been using
+	 * fixed mac-addresses based on only using word 3 for a
+	 * long time and changing a fixed mac-address with an
+	 * u-boot update is not good.
+	 */
+#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
+    !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
+    !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
+	sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
+#endif
+
+	/* Ensure the NIC specific bytes of the mac are not all 0 */
+	if ((sid[3] & 0xffffff) == 0)
+		sid[3] |= 0x800000;
+
+	return true;
+}
+
+/*
+ * Note this function gets called multiple times.
+ * It must not make any changes to env variables which already exist.
+ */
+static void setup_environment(const void *fdt)
+{
+	char serial_string[17] = { 0 };
+	unsigned int sid[4];
+	uint8_t mac_addr[6];
+	char ethaddr[16];
+	int i;
+
+	if (!get_unique_sid(sid))
+		return;
+
+	for (i = 0; i < 4; i++) {
+		sprintf(ethaddr, "ethernet%d", i);
+		if (!fdt_get_alias(fdt, ethaddr))
+			continue;
+
+		if (i == 0)
+			strcpy(ethaddr, "ethaddr");
+		else
+			sprintf(ethaddr, "eth%daddr", i);
+
+		if (env_get(ethaddr))
+			continue;
+
+		/* Non OUI / registered MAC address */
+		mac_addr[0] = (i << 4) | 0x02;
+		mac_addr[1] = (sid[0] >>  0) & 0xff;
+		mac_addr[2] = (sid[3] >> 24) & 0xff;
+		mac_addr[3] = (sid[3] >> 16) & 0xff;
+		mac_addr[4] = (sid[3] >>  8) & 0xff;
+		mac_addr[5] = (sid[3] >>  0) & 0xff;
+
+		eth_env_set_enetaddr(ethaddr, mac_addr);
+	}
+
+	if (!env_get("serial#")) {
+		snprintf(serial_string, sizeof(serial_string),
+			"%08x%08x", sid[0], sid[3]);
+
+		env_set("serial#", serial_string);
+	}
+}
+
+int misc_init_r(void)
+{
+	const char *spl_dt_name;
+	uint boot;
+
+	env_set("fel_booted", NULL);
+	env_set("fel_scriptaddr", NULL);
+	env_set("mmc_bootdev", NULL);
+
+	boot = sunxi_get_boot_device();
+	/* determine if we are running in FEL mode */
+	if (boot == BOOT_DEVICE_BOARD) {
+		env_set("fel_booted", "1");
+		parse_spl_header(SPL_ADDR);
+	/* or if we booted from MMC, and which one */
+	} else if (boot == BOOT_DEVICE_MMC1) {
+		env_set("mmc_bootdev", "0");
+	} else if (boot == BOOT_DEVICE_MMC2) {
+		env_set("mmc_bootdev", "1");
+	}
+
+	/* Set fdtfile to match the FIT configuration chosen in SPL. */
+	spl_dt_name = get_spl_dt_name();
+	if (spl_dt_name) {
+		char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
+		char str[64];
+
+		snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
+		env_set("fdtfile", str);
+	}
+
+	setup_environment(gd->fdt_blob);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_USB_ETHER
+	usb_ether_init();
+#endif
+
+	return 0;
+}
+
+static void bluetooth_dt_fixup(void *blob)
+{
+	/* Some devices ship with a Bluetooth controller default address.
+	 * Set a valid address through the device tree.
+	 */
+	uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
+	unsigned int sid[4];
+	int i;
+
+	if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
+		return;
+
+	if (eth_env_get_enetaddr("bdaddr", tmp)) {
+		/* Convert between the binary formats of the corresponding stacks */
+		for (i = 0; i < ETH_ALEN; ++i)
+			bdaddr[i] = tmp[ETH_ALEN - i - 1];
+	} else {
+		if (!get_unique_sid(sid))
+			return;
+
+		bdaddr[0] = ((sid[3] >>  0) & 0xff) ^ 1;
+		bdaddr[1] = (sid[3] >>  8) & 0xff;
+		bdaddr[2] = (sid[3] >> 16) & 0xff;
+		bdaddr[3] = (sid[3] >> 24) & 0xff;
+		bdaddr[4] = (sid[0] >>  0) & 0xff;
+		bdaddr[5] = 0x02;
+	}
+
+	do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
+			   "local-bd-address", bdaddr, ETH_ALEN, 1);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int __maybe_unused r;
+
+	/*
+	 * Call setup_environment again in case the boot fdt has
+	 * ethernet aliases the u-boot copy does not have.
+	 */
+	setup_environment(blob);
+
+	bluetooth_dt_fixup(blob);
+
+#ifdef CONFIG_VIDEO_DT_SIMPLEFB
+	r = sunxi_simplefb_setup(blob);
+	if (r)
+		return r;
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+
+static void set_spl_dt_name(const char *name)
+{
+	struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
+
+	if (spl == INVALID_SPL_HEADER)
+		return;
+
+	/* Promote the header version for U-Boot proper, if needed. */
+	if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
+		spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
+
+	strcpy((char *)&spl->string_pool, name);
+	spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	const char *best_dt_name = get_spl_dt_name();
+	int ret;
+
+#ifdef CONFIG_DEFAULT_DEVICE_TREE
+	if (best_dt_name == NULL)
+		best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
+#endif
+
+	if (best_dt_name == NULL) {
+		/* No DT name was provided, so accept the first config. */
+		return 0;
+	}
+#ifdef CONFIG_PINE64_DT_SELECTION
+	if (strstr(best_dt_name, "-pine64-plus")) {
+		/* Differentiate the Pine A64 boards by their DRAM size. */
+		if ((gd->ram_size == 512 * 1024 * 1024))
+			best_dt_name = "sun50i-a64-pine64";
+	}
+#endif
+#ifdef CONFIG_PINEPHONE_DT_SELECTION
+	if (strstr(best_dt_name, "-pinephone")) {
+		/* Differentiate the PinePhone revisions by GPIO inputs. */
+		prcm_apb0_enable(PRCM_APB0_GATE_PIO);
+		sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
+		sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
+		udelay(100);
+
+		/* PL6 is pulled low by the modem on v1.2. */
+		if (gpio_get_value(SUNXI_GPL(6)) == 0)
+			best_dt_name = "sun50i-a64-pinephone-1.2";
+		else
+			best_dt_name = "sun50i-a64-pinephone-1.1";
+
+		sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
+		sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
+		prcm_apb0_disable(PRCM_APB0_GATE_PIO);
+	}
+#endif
+
+	ret = strcmp(name, best_dt_name);
+
+	/*
+	 * If one of the FIT configurations matches the most accurate DT name,
+	 * update the SPL header to provide that DT name to U-Boot proper.
+	 */
+	if (ret == 0)
+		set_spl_dt_name(best_dt_name);
+
+	return ret;
+}
+#endif
diff --git a/roms/u-boot/board/sunxi/chip.c b/roms/u-boot/board/sunxi/chip.c
new file mode 100644
index 000000000..cde04bebe
--- /dev/null
+++ b/roms/u-boot/board/sunxi/chip.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021
+ * Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
+ * Based on initial code from Maxime Ripard
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm.h>
+#include <w1.h>
+#include <w1-eeprom.h>
+#include <dm/device-internal.h>
+
+#include <asm/arch/gpio.h>
+
+#include <extension_board.h>
+
+#define for_each_w1_device(b, d) \
+	for (device_find_first_child(b, d); *d; device_find_next_child(d))
+
+#define dip_convert(field)						\
+	(								\
+		(sizeof(field) == 1) ? field :				\
+		(sizeof(field) == 2) ? be16_to_cpu(field) :		\
+		(sizeof(field) == 4) ? be32_to_cpu(field) :		\
+		-1							\
+	)
+
+#define DIP_MAGIC	0x50494843	/* CHIP */
+
+struct dip_w1_header {
+	u32     magic;                  /* CHIP */
+	u8      version;                /* spec version */
+	u32     vendor_id;
+	u16     product_id;
+	u8      product_version;
+	char    vendor_name[32];
+	char    product_name[32];
+	u8      rsvd[36];               /* rsvd for future spec versions */
+	u8      data[16];               /* user data, per-dip specific */
+} __packed;
+
+int extension_board_scan(struct list_head *extension_list)
+{
+	struct extension *dip;
+	struct dip_w1_header w1_header;
+	struct udevice *bus, *dev;
+	u32 vid;
+	u16 pid;
+	int ret;
+
+	int num_dip = 0;
+
+	sunxi_gpio_set_pull(SUNXI_GPD(2), SUNXI_GPIO_PULL_UP);
+
+	ret = w1_get_bus(0, &bus);
+	if (ret) {
+		printf("one wire interface not found\n");
+		return 0;
+	}
+
+	for_each_w1_device(bus, &dev) {
+		if (w1_get_device_family(dev) != W1_FAMILY_DS2431)
+			continue;
+
+		ret = device_probe(dev);
+		if (ret) {
+			printf("Couldn't probe device %s: error %d",
+			       dev->name, ret);
+			continue;
+		}
+
+		w1_eeprom_read_buf(dev, 0, (u8 *)&w1_header, sizeof(w1_header));
+
+		if (w1_header.magic != DIP_MAGIC)
+			continue;
+
+		vid = dip_convert(w1_header.vendor_id);
+		pid = dip_convert(w1_header.product_id);
+
+		printf("DIP: %s (0x%x) from %s (0x%x)\n",
+		       w1_header.product_name, pid,
+		       w1_header.vendor_name, vid);
+
+		dip = calloc(1, sizeof(struct extension));
+		if (!dip) {
+			printf("Error in memory allocation\n");
+			return num_dip;
+		}
+
+		snprintf(dip->overlay, sizeof(dip->overlay), "dip-%x-%x.dtbo",
+			 vid, pid);
+		strncpy(dip->name, w1_header.product_name, 32);
+		strncpy(dip->owner, w1_header.vendor_name, 32);
+		list_add_tail(&dip->list, extension_list);
+		num_dip++;
+	}
+	return num_dip;
+}
diff --git a/roms/u-boot/board/sunxi/dram_sun4i_auto.c b/roms/u-boot/board/sunxi/dram_sun4i_auto.c
new file mode 100644
index 000000000..e8bbee4ee
--- /dev/null
+++ b/roms/u-boot/board/sunxi/dram_sun4i_auto.c
@@ -0,0 +1,36 @@
+#include <common.h>
+#include <init.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+	.clock = CONFIG_DRAM_CLK,
+	.type = 3,
+	.rank_num = 1,
+	.density = 0,
+	.io_width = 0,
+	.bus_width = 0,
+	.zq = CONFIG_DRAM_ZQ,
+	.odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
+	.size = 0,
+#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
+	.cas = 6,
+	.tpr0 = 0x30926692,
+	.tpr1 = 0x1090,
+	.tpr2 = 0x1a0c8,
+	.emr2 = 0,
+#else
+#	include "dram_timings_sun4i.h"
+	.active_windowing = 1,
+#endif
+	.tpr3 = CONFIG_DRAM_TPR3,
+	.tpr4 = 0,
+	.tpr5 = 0,
+	.emr1 = CONFIG_DRAM_EMR1,
+	.emr3 = 0,
+	.dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+	return dramc_init(&dram_para);
+}
diff --git a/roms/u-boot/board/sunxi/dram_sun5i_auto.c b/roms/u-boot/board/sunxi/dram_sun5i_auto.c
new file mode 100644
index 000000000..a5f4f8b74
--- /dev/null
+++ b/roms/u-boot/board/sunxi/dram_sun5i_auto.c
@@ -0,0 +1,39 @@
+/* DRAM parameters for auto dram configuration on sun5i and sun7i */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+	.clock = CONFIG_DRAM_CLK,
+	.mbus_clock = CONFIG_DRAM_MBUS_CLK,
+	.type = 3,
+	.rank_num = 1,
+	.density = 0,
+	.io_width = 0,
+	.bus_width = 0,
+	.zq = CONFIG_DRAM_ZQ,
+	.odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
+	.size = 0,
+#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
+	.cas = 9,
+	.tpr0 = 0x42d899b7,
+	.tpr1 = 0xa090,
+	.tpr2 = 0x22a00,
+	.emr2 = 0x10,
+#else
+#	include "dram_timings_sun4i.h"
+	.active_windowing = 1,
+#endif
+	.tpr3 = CONFIG_DRAM_TPR3,
+	.tpr4 = 0,
+	.tpr5 = 0,
+	.emr1 = CONFIG_DRAM_EMR1,
+	.emr3 = 0,
+	.dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+	return dramc_init(&dram_para);
+}
diff --git a/roms/u-boot/board/sunxi/dram_timings_sun4i.h b/roms/u-boot/board/sunxi/dram_timings_sun4i.h
new file mode 100644
index 000000000..29b934da6
--- /dev/null
+++ b/roms/u-boot/board/sunxi/dram_timings_sun4i.h
@@ -0,0 +1,205 @@
+/* This file is automatically generated, do not edit */
+
+#if defined(CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H)
+# if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */
+	.cas  = 6,
+	.tpr0 = 0x268e5590,
+	.tpr1 = 0xa090,
+	.tpr2 = 0x22a00,
+	.emr2 = 0x0,
+# elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */
+	.cas  = 6,
+	.tpr0 = 0x288f6690,
+	.tpr1 = 0xa0a0,
+	.tpr2 = 0x22a00,
+	.emr2 = 0x0,
+# elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */
+	.cas  = 6,
+	.tpr0 = 0x2a8f6690,
+	.tpr1 = 0xa0a0,
+	.tpr2 = 0x22a00,
+	.emr2 = 0x0,
+# elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */
+	.cas  = 7,
+	.tpr0 = 0x2ab06690,
+	.tpr1 = 0xa0a8,
+	.tpr2 = 0x22a00,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */
+	.cas  = 7,
+	.tpr0 = 0x2cb16690,
+	.tpr1 = 0xa0b0,
+	.tpr2 = 0x22e00,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */
+	.cas  = 7,
+	.tpr0 = 0x30b26690,
+	.tpr1 = 0xa0b8,
+	.tpr2 = 0x22e00,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */
+	.cas  = 7,
+	.tpr0 = 0x30b27790,
+	.tpr1 = 0xa0c0,
+	.tpr2 = 0x23200,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */
+	.cas  = 7,
+	.tpr0 = 0x32b27790,
+	.tpr1 = 0xa0c0,
+	.tpr2 = 0x23200,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */
+	.cas  = 7,
+	.tpr0 = 0x34d37790,
+	.tpr1 = 0xa0d0,
+	.tpr2 = 0x23600,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */
+	.cas  = 7,
+	.tpr0 = 0x36d47790,
+	.tpr1 = 0xa0d8,
+	.tpr2 = 0x23600,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333H @540MHz, timings: 9-8-8-20 */
+	.cas  = 9,
+	.tpr0 = 0x36b488b4,
+	.tpr1 = 0xa0c8,
+	.tpr2 = 0x2b600,
+	.emr2 = 0x10,
+# elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333H @552MHz, timings: 9-8-8-20 */
+	.cas  = 9,
+	.tpr0 = 0x38b488b4,
+	.tpr1 = 0xa0c8,
+	.tpr2 = 0x2ba00,
+	.emr2 = 0x10,
+# elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333H @576MHz, timings: 9-8-8-21 */
+	.cas  = 9,
+	.tpr0 = 0x3ab588b4,
+	.tpr1 = 0xa0d0,
+	.tpr2 = 0x2ba00,
+	.emr2 = 0x10,
+# elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333H @600MHz, timings: 9-9-9-22 */
+	.cas  = 9,
+	.tpr0 = 0x3cb699b4,
+	.tpr1 = 0xa0d8,
+	.tpr2 = 0x2be00,
+	.emr2 = 0x10,
+# elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333H @624MHz, timings: 9-9-9-23 */
+	.cas  = 9,
+	.tpr0 = 0x3eb799b4,
+	.tpr1 = 0xa0e8,
+	.tpr2 = 0x2be00,
+	.emr2 = 0x10,
+# elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333H @648MHz, timings: 9-9-9-24 */
+	.cas  = 9,
+	.tpr0 = 0x42b899b4,
+	.tpr1 = 0xa0f0,
+	.tpr2 = 0x2c200,
+	.emr2 = 0x10,
+# else
+#   error CONFIG_DRAM_CLK is set too high
+# endif
+#elif defined(CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J)
+# if CONFIG_DRAM_CLK <= 360 /* DDR3-800E @360MHz, timings: 6-6-6-14 */
+	.cas  = 6,
+	.tpr0 = 0x268e6690,
+	.tpr1 = 0xa090,
+	.tpr2 = 0x22a00,
+	.emr2 = 0x0,
+# elif CONFIG_DRAM_CLK <= 384 /* DDR3-800E @384MHz, timings: 6-6-6-15 */
+	.cas  = 6,
+	.tpr0 = 0x2a8f6690,
+	.tpr1 = 0xa0a0,
+	.tpr2 = 0x22a00,
+	.emr2 = 0x0,
+# elif CONFIG_DRAM_CLK <= 396 /* DDR3-800E @396MHz, timings: 6-6-6-15 */
+	.cas  = 6,
+	.tpr0 = 0x2a8f6690,
+	.tpr1 = 0xa0a0,
+	.tpr2 = 0x22a00,
+	.emr2 = 0x0,
+# elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066G @408MHz, timings: 8-7-7-16 */
+	.cas  = 8,
+	.tpr0 = 0x2cb07790,
+	.tpr1 = 0xa0a8,
+	.tpr2 = 0x22a00,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066G @432MHz, timings: 8-7-7-17 */
+	.cas  = 8,
+	.tpr0 = 0x2eb17790,
+	.tpr1 = 0xa0b0,
+	.tpr2 = 0x22e00,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066G @456MHz, timings: 8-7-7-18 */
+	.cas  = 8,
+	.tpr0 = 0x30b27790,
+	.tpr1 = 0xa0b8,
+	.tpr2 = 0x22e00,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066G @468MHz, timings: 8-8-8-18 */
+	.cas  = 8,
+	.tpr0 = 0x32b28890,
+	.tpr1 = 0xa0c0,
+	.tpr2 = 0x23200,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066G @480MHz, timings: 8-8-8-18 */
+	.cas  = 8,
+	.tpr0 = 0x34b28890,
+	.tpr1 = 0xa0c0,
+	.tpr2 = 0x23200,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066G @504MHz, timings: 8-8-8-19 */
+	.cas  = 8,
+	.tpr0 = 0x36d38890,
+	.tpr1 = 0xa0d0,
+	.tpr2 = 0x23600,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066G @528MHz, timings: 8-8-8-20 */
+	.cas  = 8,
+	.tpr0 = 0x38d48890,
+	.tpr1 = 0xa0d8,
+	.tpr2 = 0x23600,
+	.emr2 = 0x8,
+# elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333J @540MHz, timings: 10-9-9-20 */
+	.cas  = 10,
+	.tpr0 = 0x38b499b4,
+	.tpr1 = 0xa0c8,
+	.tpr2 = 0x2b600,
+	.emr2 = 0x10,
+# elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333J @552MHz, timings: 10-9-9-20 */
+	.cas  = 10,
+	.tpr0 = 0x3ab499b4,
+	.tpr1 = 0xa0c8,
+	.tpr2 = 0x2ba00,
+	.emr2 = 0x10,
+# elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333J @576MHz, timings: 10-9-9-21 */
+	.cas  = 10,
+	.tpr0 = 0x3cb599b4,
+	.tpr1 = 0xa0d0,
+	.tpr2 = 0x2ba00,
+	.emr2 = 0x10,
+# elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333J @600MHz, timings: 10-9-9-22 */
+	.cas  = 10,
+	.tpr0 = 0x3eb699b4,
+	.tpr1 = 0xa0d8,
+	.tpr2 = 0x2be00,
+	.emr2 = 0x10,
+# elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333J @624MHz, timings: 10-10-10-23 */
+	.cas  = 10,
+	.tpr0 = 0x40b7aab4,
+	.tpr1 = 0xa0e8,
+	.tpr2 = 0x2be00,
+	.emr2 = 0x10,
+# elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333J @648MHz, timings: 10-10-10-24 */
+	.cas  = 10,
+	.tpr0 = 0x44b8aab4,
+	.tpr1 = 0xa0f0,
+	.tpr2 = 0x2c200,
+	.emr2 = 0x10,
+# else
+#   error CONFIG_DRAM_CLK is set too high
+# endif
+#else
+# error CONFIG_DRAM_TIMINGS_* is not defined
+#endif
diff --git a/roms/u-boot/board/sunxi/gmac.c b/roms/u-boot/board/sunxi/gmac.c
new file mode 100644
index 000000000..d8fdf7728
--- /dev/null
+++ b/roms/u-boot/board/sunxi/gmac.c
@@ -0,0 +1,78 @@
+#include <common.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+
+void eth_init_board(void)
+{
+	int pin;
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* Set MII clock */
+#ifdef CONFIG_RGMII
+	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+		CCM_GMAC_CTRL_GPIT_RGMII);
+	setbits_le32(&ccm->gmac_clk_cfg,
+		     CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
+#else
+	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
+		CCM_GMAC_CTRL_GPIT_MII);
+#endif
+
+#ifndef CONFIG_MACH_SUN6I
+	/* Configure pin mux settings for GMAC */
+#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
+	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
+#else
+	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#endif
+#ifdef CONFIG_RGMII
+		/* skip unused pins in RGMII mode */
+		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
+			continue;
+#endif
+		sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
+		sunxi_gpio_set_drv(pin, 3);
+	}
+#elif defined CONFIG_RGMII
+	/* Configure sun6i RGMII mode pin mux settings */
+	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
+		sunxi_gpio_set_drv(pin, 3);
+	}
+	for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
+		sunxi_gpio_set_drv(pin, 3);
+	}
+	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
+		sunxi_gpio_set_drv(pin, 3);
+	}
+	for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
+		sunxi_gpio_set_drv(pin, 3);
+	}
+#elif defined CONFIG_GMII
+	/* Configure sun6i GMII mode pin mux settings */
+	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
+		sunxi_gpio_set_drv(pin, 2);
+	}
+#else
+	/* Configure sun6i MII mode pin mux settings */
+	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
+	for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
+	for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
+	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
+	for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
+		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
+#endif
+}
diff --git a/roms/u-boot/board/synopsys/MAINTAINERS b/roms/u-boot/board/synopsys/MAINTAINERS
new file mode 100644
index 000000000..b9bfd3c2e
--- /dev/null
+++ b/roms/u-boot/board/synopsys/MAINTAINERS
@@ -0,0 +1,8 @@
+- BOARD
+M:	Alexey Brodkin <abrodkin@synopsys.com>
+S:	Maintained
+F:	include/configs/nsim.h
+F:	configs/nsim_700_defconfig
+F:	configs/nsim_700be_defconfig
+F:	configs/nsim_hs38_defconfig
+F:	configs/nsim_hs38be_defconfig
diff --git a/roms/u-boot/board/synopsys/axs10x/Kconfig b/roms/u-boot/board/synopsys/axs10x/Kconfig
new file mode 100644
index 000000000..dd1305adc
--- /dev/null
+++ b/roms/u-boot/board/synopsys/axs10x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AXS101 || TARGET_AXS103
+
+config SYS_BOARD
+	default "axs10x"
+
+config SYS_VENDOR
+	default "synopsys"
+
+config SYS_CONFIG_NAME
+	default "axs10x"
+
+endif
diff --git a/roms/u-boot/board/synopsys/axs10x/MAINTAINERS b/roms/u-boot/board/synopsys/axs10x/MAINTAINERS
new file mode 100644
index 000000000..abb890b71
--- /dev/null
+++ b/roms/u-boot/board/synopsys/axs10x/MAINTAINERS
@@ -0,0 +1,7 @@
+AXS10X BOARD
+M:	Alexey Brodkin <abrodkin@synopsys.com>
+S:	Maintained
+F:	board/synopsys/axs10x/
+F:	include/configs/axs10x.h
+F:	configs/axs101_defconfig
+F:	configs/axs103_defconfig
diff --git a/roms/u-boot/board/synopsys/axs10x/Makefile b/roms/u-boot/board/synopsys/axs10x/Makefile
new file mode 100644
index 000000000..dd5ee680e
--- /dev/null
+++ b/roms/u-boot/board/synopsys/axs10x/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved.
+
+obj-y	+= axs10x.o
diff --git a/roms/u-boot/board/synopsys/axs10x/axs10x.c b/roms/u-boot/board/synopsys/axs10x/axs10x.c
new file mode 100644
index 000000000..75e4d0376
--- /dev/null
+++ b/roms/u-boot/board/synopsys/axs10x/axs10x.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dwmmc.h>
+#include <init.h>
+#include <malloc.h>
+#include <asm/arcregs.h>
+#include <asm/global_data.h>
+#include "axs10x.h"
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AXS_MB_CREG	0xE0011000
+
+int board_early_init_f(void)
+{
+	if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
+		gd->board_type = AXS_MB_V3;
+	else
+		gd->board_type = AXS_MB_V2;
+
+	return 0;
+}
+
+#ifdef CONFIG_ISA_ARCV2
+
+void board_jump_and_run(ulong entry, int zero, int arch, uint params)
+{
+	void (*kernel_entry)(int zero, int arch, uint params);
+
+	kernel_entry = (void (*)(int, int, uint))entry;
+
+	smp_set_core_boot_addr(entry, -1);
+	smp_kick_all_cpus();
+	kernel_entry(zero, arch, params);
+}
+
+#define RESET_VECTOR_ADDR	0x0
+
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+	/* All cores have reset vector pointing to 0 */
+	writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
+
+	/* Make sure other cores see written value in memory */
+	flush_dcache_all();
+}
+
+void smp_kick_all_cpus(void)
+{
+/* CPU start CREG */
+#define AXC003_CREG_CPU_START	0xF0001400
+/* Bits positions in CPU start CREG */
+#define BITS_START	0
+#define BITS_START_MODE	4
+#define BITS_CORE_SEL	9
+
+/*
+ * In axs103 v1.1 START bits semantics has changed quite a bit.
+ * We used to have a generic START bit for all cores selected by CORE_SEL mask.
+ * But now we don't touch CORE_SEL at all because we have a dedicated START bit
+ * for each core:
+ *     bit 0: Core 0 (master)
+ *     bit 1: Core 1 (slave)
+ */
+#define BITS_START_CORE1	1
+
+#define ARCVER_HS38_3_0	0x53
+
+	int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
+	int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
+
+	if (core_family < ARCVER_HS38_3_0) {
+		cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
+		cmd &= ~(1 << BITS_START_MODE);
+	} else {
+		cmd |= (1 << BITS_START_CORE1);
+	}
+	writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
+}
+#endif
+
+int checkboard(void)
+{
+	printf("Board: ARC Software Development Platform AXS%s\n",
+	     is_isa_arcv2() ? "103" : "101");
+
+	return 0;
+};
diff --git a/roms/u-boot/board/synopsys/axs10x/axs10x.h b/roms/u-boot/board/synopsys/axs10x/axs10x.h
new file mode 100644
index 000000000..69541cc57
--- /dev/null
+++ b/roms/u-boot/board/synopsys/axs10x/axs10x.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef _BOARD_SYNOPSYS_AXS10X_H
+#define _BOARD_SYNOPSYS_AXS10X_H
+
+enum {
+	AXS_MB_V2,
+	AXS_MB_V3
+};
+
+#endif /* _BOARD_SYNOPSYS_AXS10X_H */
+
diff --git a/roms/u-boot/board/synopsys/axs10x/config.mk b/roms/u-boot/board/synopsys/axs10x/config.mk
new file mode 100644
index 000000000..ccac54429
--- /dev/null
+++ b/roms/u-boot/board/synopsys/axs10x/config.mk
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+
+ifdef CONFIG_TARGET_AXS103
+  PLATFORM_CPPFLAGS += -mcpu=archs
+else
+  PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape
+endif
+
+bsp-generate: u-boot u-boot.bin
+ifdef CONFIG_ISA_ARCV2
+	$(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-axs.py \
+		--header-type v2 \
+		--arc-id 0x53 \
+		--spi-flash-offset 0x200000 \
+		--image $(srctree)/u-boot.bin \
+		--elf $(srctree)/u-boot
+else
+	$(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-axs.py \
+		--header-type v1 \
+		--arc-id 0x434 \
+		--spi-flash-offset 0x0 \
+		--image $(srctree)/u-boot.bin \
+		--elf $(srctree)/u-boot
+endif
+	$(Q)tools/mkimage -T script -C none -n 'uboot update script' \
+		-d $(srctree)/u-boot-update.txt \
+		$(srctree)/u-boot-update.img &> /dev/null
diff --git a/roms/u-boot/board/synopsys/axs10x/headerize-axs.py b/roms/u-boot/board/synopsys/axs10x/headerize-axs.py
new file mode 100644
index 000000000..fa6aaf350
--- /dev/null
+++ b/roms/u-boot/board/synopsys/axs10x/headerize-axs.py
@@ -0,0 +1,176 @@
+#!/usr/bin/env python3
+
+#we can use binascii instead of zlib
+import os, getopt, sys, zlib
+from elftools.elf.elffile import ELFFile
+
+
+def usage(exit_code):
+    print("typical usage:")
+    print("AXS101:")
+    print(sys.argv[0] + \
+        " --header-type v1 --arc-id 0x434 --spi-flash-offset 0x0 --image u-boot.bin --elf u-boot")
+    print("AXS103:")
+    print(sys.argv[0] + \
+        " --header-type v2 --arc-id 0x53 --spi-flash-offset 0x200000 --image u-boot.bin --elf u-boot")
+    sys.exit(exit_code)
+
+
+def elf_get_entry(filename):
+    with open(filename, 'rb') as f:
+        elffile = ELFFile(f)
+        return elffile.header['e_entry']
+
+
+def calc_check_sum(filename):
+    # Calculate u-boot image check_sum: it is sum of all u-boot binary bytes
+    with open(filename, "rb") as file:
+        ba = bytearray(file.read())
+    return sum(ba) & 0xFF
+
+
+def arg_verify(uboot_bin_filename, uboot_elf_filename, header_type):
+    if not os.path.isfile(uboot_bin_filename):
+        print("uboot bin file not exists: " + uboot_bin_filename)
+        sys.exit(2)
+
+    if not os.path.isfile(uboot_elf_filename):
+        print("uboot elf file not exists: " + uboot_elf_filename)
+        sys.exit(2)
+
+    if header_type not in ("v1", "v2"):
+        print("unknown header type: " + header_type)
+        print("choose between 'v1' (most likely AXS101) and 'v2' (most likely AXS103)")
+        sys.exit(2)
+
+
+def main():
+    try:
+        opts, args = getopt.getopt(sys.argv[1:],
+            "ht:a:s:i:l:e:",
+            ["help", "header-type=", "arc-id=", "spi-flash-offset=", "image=", "elf="])
+    except getopt.GetoptError as err:
+        print(err)
+        usage(2)
+
+    # default filenames
+    uboot_elf_filename  = "u-boot"
+    uboot_bin_filename  = "u-boot.bin"
+    headerised_filename = "u-boot.head"
+    uboot_scrypt_file   = "u-boot-update.txt"
+
+    # default values
+    spi_flash_offset    = 0x200000
+    header_type         = "v2"
+    arc_id              = 0x53
+
+    # initial header values: place where preloader will store u-boot binary,
+    # should be equal to CONFIG_SYS_TEXT_BASE
+    image_copy_adr  = 0x81000000
+
+    # initial constant header values, do not change these values
+    magic1          = 0xdeadbeafaf # big endian byte order
+    magic2          = [            # big endian byte order
+    0x20202a2020202020202020202a20202020207c5c2e20202020202e2f7c20202020207c2d,
+    0x2e5c2020202f2e2d7c20202020205c2020602d2d2d6020202f20202020202f205f202020,
+    0x205f20205c20202020207c205f60712070205f207c2020202020272e5f3d2f205c3d5f2e,
+    0x272020202020202020605c202f60202020202020202020202020206f2020202020202020]
+
+    for opt, arg in opts:
+        if opt in ('-h', "--help"):        usage(0)
+        if opt in ('-t', "--header-type"): header_type           = arg
+        if opt in ('-a', "--arc-id"):      arc_id                = int(arg, 16)
+        if opt in ('-s', "--spi-flash-offset"): spi_flash_offset = int(arg, 16)
+        if opt in ('-i', "--image"):       uboot_bin_filename    = arg
+        if opt in ('-e', "--elf"):         uboot_elf_filename    = arg
+
+    arg_verify(uboot_bin_filename, uboot_elf_filename, header_type)
+
+    uboot_img_size = os.path.getsize(uboot_bin_filename)
+    jump_address = elf_get_entry(uboot_elf_filename)
+    check_sum = calc_check_sum(uboot_bin_filename)
+
+    # Calculate header adresses depend on header type
+    if header_type == "v2":
+        image_copy_adr -= 0x4
+        uboot_img_size += 0x4
+        # we append image so we need to append checksum
+        jmpchk_sum = sum(jump_address.to_bytes(4, byteorder='big'))
+        check_sum = (check_sum + jmpchk_sum) & 0xFF
+        imade_jump_append = True
+    else:
+        imade_jump_append = False
+
+    # write header to file
+    with open(headerised_filename, "wb") as file:
+        file.write(arc_id.to_bytes(2, byteorder='little'))
+        file.write(uboot_img_size.to_bytes(4, byteorder='little'))
+        file.write(check_sum.to_bytes(1, byteorder='little'))
+        file.write(image_copy_adr.to_bytes(4, byteorder='little'))
+        file.write(magic1.to_bytes(5, byteorder='big'))
+        for i in range(16): file.write(0x00.to_bytes(1, byteorder='little'))
+        for byte in magic2: file.write(byte.to_bytes(36, byteorder='big'))
+        for i in range(224 - len(magic2) * 36):
+            file.write(0x00.to_bytes(1, byteorder='little'))
+        if imade_jump_append:
+            file.write(jump_address.to_bytes(4, byteorder='little'))
+
+    # append u-boot image to header
+    with open(headerised_filename, "ab") as fo:
+        with open(uboot_bin_filename,'rb') as fi:
+            fo.write(fi.read())
+
+    # calc u-boot headerised image CRC32 (will be used by uboot update
+    # command for check)
+    headerised_image_crc = ""
+    with open(headerised_filename, "rb") as fi:
+        headerised_image_crc = hex(zlib.crc32(fi.read()) & 0xffffffff)
+
+    load_addr = 0x81000000
+    crc_store_adr = load_addr - 0x8
+    crc_calc_adr = crc_store_adr - 0x4
+    load_size = os.path.getsize(headerised_filename)
+    crc_calc_cmd = \
+        "crc32 " + hex(load_addr) + " " + hex(load_size) + " " + hex(crc_calc_adr)
+    crc_check_cmd = \
+        "mw.l " + hex(crc_store_adr) + " " + headerised_image_crc + " && " + \
+        crc_calc_cmd + " && " + \
+        "cmp.l " + hex(crc_store_adr) + " " + hex(crc_calc_adr) + " 1"
+
+    # make errase size to be allighned by 64K
+    if load_size & 0xFFFF == 0:
+        errase_size = load_size
+    else:
+        errase_size = load_size - (load_size & 0xFFFF) + 0x10000
+
+    # Hack to handle n25*** flash protect ops weirdness:
+    # protect unlock return fail status is region is already unlock (entire or
+    # partially). Same for lock ops.
+    # As there is no possibility to check current flash status pretend
+    # unlock & lock always success.
+    sf_unlock_cmd = \
+        "if sf protect unlock 0x0 0x4000000 ; then true ; else true ; fi"
+    sf_lock_cmd = \
+        "if sf protect lock 0x0 0x4000000 ; then true ; else true ; fi"
+
+    # u-bood CMD to load u-bood with header to SPI flash
+    sf_load_image_cmd = \
+        "fatload mmc 0:1 " + hex(load_addr) + " " + headerised_filename + " && " + \
+        "sf probe 0:0 && " + \
+        sf_unlock_cmd + " && " + \
+        "sf erase " + hex(spi_flash_offset) + " " + hex(errase_size) + " && " + \
+        "sf write " + hex(load_addr) + " " + hex(spi_flash_offset) + " " + hex(load_size) + " && " + \
+        sf_lock_cmd
+
+    update_uboot_cmd = sf_load_image_cmd + " && echo \"u-boot update: OK\""
+
+    with open(uboot_scrypt_file, "wb") as fo:
+        fo.write(update_uboot_cmd.encode('ascii'))
+
+
+if __name__ == "__main__":
+    try:
+        main()
+    except Exception as err:
+        print(err)
+        sys.exit(2)
diff --git a/roms/u-boot/board/synopsys/emsdp/Kconfig b/roms/u-boot/board/synopsys/emsdp/Kconfig
new file mode 100644
index 000000000..8228bb5c7
--- /dev/null
+++ b/roms/u-boot/board/synopsys/emsdp/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_EMSDP
+
+config SYS_BOARD
+	default "emsdp"
+
+config SYS_VENDOR
+	default "synopsys"
+
+config SYS_CONFIG_NAME
+	default "emsdp"
+
+endif
diff --git a/roms/u-boot/board/synopsys/emsdp/MAINTAINERS b/roms/u-boot/board/synopsys/emsdp/MAINTAINERS
new file mode 100644
index 000000000..640401395
--- /dev/null
+++ b/roms/u-boot/board/synopsys/emsdp/MAINTAINERS
@@ -0,0 +1,6 @@
+EM DEVELOPMENT KIT BOARD
+M:	Alexey Brodkin <abrodkin@synopsys.com>
+S:	Maintained
+F:	arch/arc/dts/emsdp.dts
+F:	board/synopsys/emsdp/
+F:	configs/emsdp_defconfig
diff --git a/roms/u-boot/board/synopsys/emsdp/Makefile b/roms/u-boot/board/synopsys/emsdp/Makefile
new file mode 100644
index 000000000..733a48c46
--- /dev/null
+++ b/roms/u-boot/board/synopsys/emsdp/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= emsdp.o
diff --git a/roms/u-boot/board/synopsys/emsdp/README b/roms/u-boot/board/synopsys/emsdp/README
new file mode 100644
index 000000000..036554c4d
--- /dev/null
+++ b/roms/u-boot/board/synopsys/emsdp/README
@@ -0,0 +1,83 @@
+================================================================================
+Useful notes on bulding and using of U-Boot on
+ARC EM Software Development Platform (AKA EMSDP)
+================================================================================
+
+   BOARD OVERVIEW
+
+   The DesignWare ARC EM Software Development Platform is FPGA-bases platform
+   for rapid software development on the ARC EM family of processors.
+
+   Since this board is based on FPGA it's possible to load and use different
+   versions of ARC EM CPUs. U-Boot is built to be run on the simplest
+   possible configuration which means the same one binary will work on more
+   advanced configurations as well.
+
+   The board has the following features useful for U-Boot:
+    * On-board 2-channel FTDI TTL-to-USB converter
+      - The first channel is used for serial debug port (which makes it possible
+        to use a serial connection on pretty much any host machine be it
+        Windows, Linux or Mac).
+        On Linux machine typucally FTDI serial port would be /dev/ttyUSB0.
+        There's no HW flow-control and baud-rate is 115200.
+
+      - The second channel is used for built-in Digilent USB JTAG probe.
+        That means no extra hardware is required to access ARC core from a
+        debugger on development host. Both proprietary MetaWare debugger and
+        open source OpenOCD + GDB client are supported.
+
+      - Also with help of this FTDI chip it is possible to reset entire
+        board with help of a special `rff-ftdi-reset` utility, see:
+        https://github.com/foss-for-synopsys-dwc-arc-processors/rff-ftdi-reset
+
+    * Micro SD-card slot
+      - U-Boot expects to see the very first partition on the card formatted as
+        FAT file-system and uses it for keeping its environment in `uboot.env`
+        file. Note uboot.env is not just a text file but it is auto-generated
+        file created by U-Boot on invocation of `saveenv` command.
+        It contains a checksum which makes this saved environment invalid in
+        case of maual modification.
+
+      - There might be more useful files on that first FAT partition like
+        user applications, data files etc.
+
+    * 256 KiB of "ROM"
+      - This so-called "ROM" is a part of FPGA image and even though it
+        might be unlocked for writes its initial content will be restored
+        on the next power-on.
+
+
+   BUILDING U-BOOT
+
+   1. Configure U-Boot:
+      ------------------------->8----------------------
+      make emsdp_defconfig
+      ------------------------->8----------------------
+
+   2. To build Elf file (for example to be used with host debugger via JTAG
+      connection to the target board):
+      ------------------------->8----------------------
+      make mdbtrick
+      ------------------------->8----------------------
+
+      This will produce `u-boot` Elf file.
+
+   3. To build binary image to be put in "ROM":
+      ------------------------->8----------------------
+      make u-boot.bin
+      ------------------------->8----------------------
+
+
+   EXECUTING U-BOOT
+
+   1. The EMSDP board is supposed to auto-start U-Boot image stored in ROM on
+      power-on. For that make sure VCCIO DIP-switches are all in "off" state.
+
+   2. Though it is possible to load U-Boot as a simple Elf file via JTAG right
+      in "ROM" and start it from the debugger. One important note here we first
+      need to enable writes into "ROM" by writing 1 to 0xf0001000.
+
+      2.1. In case of proprietary MetaWare debugger run:
+      ------------------------->8----------------------
+      mdb -digilent -OK -preloadexec="eval *(int*)0xf0001000=0" u-boot
+      ------------------------->8----------------------
diff --git a/roms/u-boot/board/synopsys/emsdp/config.mk b/roms/u-boot/board/synopsys/emsdp/config.mk
new file mode 100644
index 000000000..5bd10442a
--- /dev/null
+++ b/roms/u-boot/board/synopsys/emsdp/config.mk
@@ -0,0 +1,2 @@
+PLATFORM_CPPFLAGS += -mcpu=arcem -mlittle-endian -mnorm -mswap -mmpy-option=3 \
+                     -mbarrel-shifter -mfpu=fpuda_all -mcode-density
diff --git a/roms/u-boot/board/synopsys/emsdp/emsdp.c b/roms/u-boot/board/synopsys/emsdp/emsdp.c
new file mode 100644
index 000000000..a3cee2341
--- /dev/null
+++ b/roms/u-boot/board/synopsys/emsdp/emsdp.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <dwmmc.h>
+#include <init.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+#include <linux/bitops.h>
+
+#include <asm/arcregs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARC_PERIPHERAL_BASE		0xF0000000
+
+#define CGU_ARC_FMEAS_ARC		(void *)(ARC_PERIPHERAL_BASE + 0x84)
+#define CGU_ARC_FMEAS_ARC_START		BIT(31)
+#define CGU_ARC_FMEAS_ARC_DONE		BIT(30)
+#define CGU_ARC_FMEAS_ARC_CNT_MASK	GENMASK(14, 0)
+#define CGU_ARC_FMEAS_ARC_RCNT_OFFSET	0
+#define CGU_ARC_FMEAS_ARC_FCNT_OFFSET	15
+
+#define SDIO_BASE			(void *)(ARC_PERIPHERAL_BASE + 0x10000)
+
+int mach_cpu_init(void)
+{
+	int rcnt, fcnt;
+	u32 data;
+
+	/* Start frequency measurement */
+	writel(CGU_ARC_FMEAS_ARC_START, CGU_ARC_FMEAS_ARC);
+
+	/* Poll DONE bit */
+	do {
+		data = readl(CGU_ARC_FMEAS_ARC);
+	} while (!(data & CGU_ARC_FMEAS_ARC_DONE));
+
+	/* Amount of reference 100 MHz clocks */
+	rcnt = ((data >> CGU_ARC_FMEAS_ARC_RCNT_OFFSET) &
+	       CGU_ARC_FMEAS_ARC_CNT_MASK);
+
+	/* Amount of CPU clocks */
+	fcnt = ((data >> CGU_ARC_FMEAS_ARC_FCNT_OFFSET) &
+	       CGU_ARC_FMEAS_ARC_CNT_MASK);
+
+	gd->cpu_clk = ((100 * fcnt) / rcnt) * 1000000;
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+#define EMSDP_PSRAM_BASE		0xf2001000
+#define PSRAM_FLASH_CONFIG_REG_0	(void *)(EMSDP_PSRAM_BASE + 0x10)
+#define PSRAM_FLASH_CONFIG_REG_1	(void *)(EMSDP_PSRAM_BASE + 0x14)
+#define CRE_ENABLE			BIT(31)
+#define CRE_DRIVE_CMD			BIT(6)
+
+#define PSRAM_RCR_DPD			BIT(1)
+#define PSRAM_RCR_PAGE_MODE		BIT(7)
+
+/*
+ * PSRAM_FLASH_CONFIG_REG_x[30:15] to the address lines[16:1] of flash,
+ * thus "<< 1".
+ */
+#define PSRAM_RCR_SETUP		((PSRAM_RCR_DPD | PSRAM_RCR_PAGE_MODE) << 1)
+
+	// Switch PSRAM controller to command mode
+	writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_0);
+	// Program Refresh Configuration Register (RCR) for BANK0
+	writew(0, (void *)(0x10000000 + PSRAM_RCR_SETUP));
+	// Switch PSRAM controller back to memory mode
+	writel(0, PSRAM_FLASH_CONFIG_REG_0);
+
+
+	// Switch PSRAM controller to command mode
+	writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1);
+	// Program Refresh Configuration Register (RCR) for BANK1
+	writew(0, (void *)(0x10800000 + PSRAM_RCR_SETUP));
+	// Switch PSRAM controller back to memory mode
+	writel(0, PSRAM_FLASH_CONFIG_REG_1);
+
+	printf("PSRAM initialized.\n");
+
+	return 0;
+}
+
+#define CREG_BASE		0xF0001000
+#define CREG_BOOT		(void *)(CREG_BASE + 0x0FF0)
+#define CREG_IP_SW_RESET	(void *)(CREG_BASE + 0x0FF0)
+#define CREG_IP_VERSION		(void *)(CREG_BASE + 0x0FF8)
+
+/* Bits in CREG_BOOT register */
+#define CREG_BOOT_WP_BIT	BIT(8)
+
+void reset_cpu(void)
+{
+	writel(1, CREG_IP_SW_RESET);
+	while (1)
+		; /* loop forever till reset */
+}
+
+static int do_emsdp_rom(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	u32 creg_boot = readl(CREG_BOOT);
+
+	if (!strcmp(argv[1], "unlock"))
+		creg_boot &= ~CREG_BOOT_WP_BIT;
+	else if (!strcmp(argv[1], "lock"))
+		creg_boot |= CREG_BOOT_WP_BIT;
+	else
+		return CMD_RET_USAGE;
+
+	writel(creg_boot, CREG_BOOT);
+
+	return CMD_RET_SUCCESS;
+}
+
+struct cmd_tbl cmd_emsdp[] = {
+	U_BOOT_CMD_MKENT(rom, 2, 0, do_emsdp_rom, "", ""),
+};
+
+static int do_emsdp(struct cmd_tbl *cmdtp, int flag, int argc,
+		    char *const argv[])
+{
+	struct cmd_tbl *c;
+
+	c = find_cmd_tbl(argv[1], cmd_emsdp, ARRAY_SIZE(cmd_emsdp));
+
+	/* Strip off leading 'emsdp' command */
+	argc--;
+	argv++;
+
+	if (c == NULL || argc > c->maxargs)
+		return CMD_RET_USAGE;
+
+	return c->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+	emsdp, CONFIG_SYS_MAXARGS, 0, do_emsdp,
+	"Synopsys EMSDP specific commands",
+	"rom unlock - Unlock non-volatile memory for writing\n"
+	"emsdp rom lock - Lock non-volatile memory to prevent writing\n"
+);
+
+int checkboard(void)
+{
+	int version = readl(CREG_IP_VERSION);
+
+	printf("Board: ARC EM Software Development Platform v%d.%d\n",
+	       (version >> 16) & 0xff, version & 0xff);
+	return 0;
+};
diff --git a/roms/u-boot/board/synopsys/hsdk/Kconfig b/roms/u-boot/board/synopsys/hsdk/Kconfig
new file mode 100644
index 000000000..d9c0e27a4
--- /dev/null
+++ b/roms/u-boot/board/synopsys/hsdk/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_HSDK
+
+config SYS_BOARD
+	default "hsdk"
+
+config SYS_VENDOR
+	default "synopsys"
+
+config SYS_CONFIG_NAME
+	default "hsdk" if BOARD_HSDK
+	default "hsdk-4xd" if BOARD_HSDK_4XD
+
+choice
+	prompt "HSDK board type"
+	default BOARD_HSDK
+
+config BOARD_HSDK
+	bool "ARC HS Development Kit"
+	help
+	  ARC HS Development Kit based on quard core ARC HS38 processor
+
+config BOARD_HSDK_4XD
+	bool "ARC HS4x/HS4xD Development Kit"
+	help
+	  ARC HS4x/HS4xD Development Kit based on quard core ARC HS48/HS47D
+	  processor
+
+endchoice
+
+endif
diff --git a/roms/u-boot/board/synopsys/hsdk/MAINTAINERS b/roms/u-boot/board/synopsys/hsdk/MAINTAINERS
new file mode 100644
index 000000000..73f71fd06
--- /dev/null
+++ b/roms/u-boot/board/synopsys/hsdk/MAINTAINERS
@@ -0,0 +1,8 @@
+HSDK BOARDs
+M:	Eugeniy Paltsev <paltsev@synopsys.com>
+S:	Maintained
+F:	board/synopsys/hsdk/
+F:	configs/hsdk_defconfig
+F:	configs/hsdk_4xd_defconfig
+F:	include/configs/hsdk-4xd.h
+F:	include/configs/hsdk.h
diff --git a/roms/u-boot/board/synopsys/hsdk/Makefile b/roms/u-boot/board/synopsys/hsdk/Makefile
new file mode 100644
index 000000000..e9cd6a63e
--- /dev/null
+++ b/roms/u-boot/board/synopsys/hsdk/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+
+obj-y	+= hsdk.o
+obj-y	+= env-lib.o
+obj-y	+= clk-lib.o
diff --git a/roms/u-boot/board/synopsys/hsdk/README b/roms/u-boot/board/synopsys/hsdk/README
new file mode 100644
index 000000000..9155f17c6
--- /dev/null
+++ b/roms/u-boot/board/synopsys/hsdk/README
@@ -0,0 +1,128 @@
+================================================================================
+Useful notes on bulding and using of U-Boot on ARC HS Development Kit (AKA HSDK)
+================================================================================
+
+   BOARD OVERVIEW
+
+   The DesignWare ARC HS Development Kit is a ready-to-use platform for rapid
+   software development on the ARC HS3x family of processors.
+
+   For more information please visit:
+   https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit
+
+   User guide is availalble here:
+   https://github.com/foss-for-synopsys-dwc-arc-processors/ARC-Development-Systems-Forum/wiki/docs/ARC_HSDK_User_Guide.pdf
+
+   It has the following features useful for U-Boot:
+    * On-board 2-channel FTDI TTL-to-USB converter
+      - The first channel is used for serial debug port (which makes it possible
+        to use a serial connection on pretty much any host machine be it
+        Windows, Linux or Mac).
+        On Linux machine typucally FTDI serial port would be /dev/ttyUSB0.
+        There's no HW flow-control and baud-rate is 115200.
+
+      - The second channel is used for built-in Digilent USB JTAG probe.
+        That means no extra hardware is required to access ARC core from a
+        debugger on development host. Both proprietary MetaWare debugger and
+        open source OpenOCD + GDB client are supported.
+
+      - Also with help of this FTDI chip it is possible to reset entire
+        board with help of a special `rff-ftdi-reset` utility, see:
+        https://github.com/foss-for-synopsys-dwc-arc-processors/rff-ftdi-reset
+
+    * Micro SD-card slot
+      - U-Boot expects to see the very first partition on the card formatted as
+        FAT file-system and uses it for keeping its environment in `uboot.env`
+        file. Note uboot.env is not just a text file but it is auto-generated
+        file created by U-Boot on invocation of `saveenv` command.
+        It contains a checksum which makes this saved environment invalid in
+        case of maual modification.
+
+      - There might be more useful files on that first FAT partition like
+        Linux kernl image in form of uImage (with or without built-in
+        initramfs), device tree blob (.dtb) etc.
+
+      - Except FAT partition there might be others following the first FAT one
+        like Ext file-system with rootfs etc.
+
+    * 1 Gb Ethernet socket
+      - U-Boot might get payload from TFTP server. This might be uImage, rootfs
+        image and anything else.
+
+    * 2 MiB of SPI-flash
+      - SPI-flahs is used as a storage for image of an application auto-executed
+        by bootROM on power-on. Typically U-Boot gets programmed there but
+        there might be other uses. But note bootROM expects to find a special
+        header preceeding application image itself so before flashing anything
+        make sure required image is prepended. In case of U-Boot this is done
+        by invocation of `headerize-hsdk.py` with `make bsp-generate` command.
+
+
+   BUILDING U-BOOT
+
+   1. Configure U-Boot:
+      ------------------------->8----------------------
+      make hsdk_defconfig
+      ------------------------->8----------------------
+
+   2. To build Elf file (for example to be used with host debugger via JTAG
+      connection to the target board):
+      ------------------------->8----------------------
+      make mdbtrick
+      ------------------------->8----------------------
+
+      This will produce `u-boot` Elf file.
+
+   3. To build artifacts required for U-Boot update in n-board SPI-flash:
+      ------------------------->8----------------------
+      make bsp-generate
+      ------------------------->8----------------------
+
+      This will produce `u-boot.head` and `u-boot-update.scr` which should
+      be put on the first FAT partition of micro SD-card to be inserted in the
+      HSDK board.
+
+      Note that Python3 script is used for generation of a header, thus
+      to get that done it's required to have Python3 with "pyelftools" installed.
+
+      "pyelftools" could be installed with help of "pip" even w/o root rights:
+      ------------------------->8----------------------
+      python3 -m pip install --user pyelftools
+      ------------------------->8----------------------
+
+   EXECUTING U-BOOT
+
+   1. The HSDK board is supposed to auto-start U-Boot image stored in on-board
+      SPI-flash on power-on. For that make sure DIP-switches in the corner of
+      the board are in their default positions: BIM in 1:off, 2:on state
+      while both BMC and BCS should be in 1:on, 2:on state.
+
+   2. Though it is possible to load U-Boot as a simple Elf file via JTAG right
+      in DDR and start it from the debugger.
+
+      2.1. In case of proprietary MetaWare debugger run:
+      ------------------------->8----------------------
+      mdb -digilent -run -cl u-boot
+      ------------------------->8----------------------
+
+
+   UPDATION U-BOOT IMAGE IN ON-BOARD SPI-FLASH
+
+   1. Create `u-boot.head` and `u-boot-update.scr` as discribed above with
+      `make bsp-generate` command.
+
+   2. Copy `u-boot.head` and `u-boot-update.scr` to the first FAT partition
+      of micro SD-card.
+
+   3. Connect USB cable from the HSDK board to the developemnt host and
+      fire-up serial terminal.
+
+   3. Insert prepared micro SD-card in the HSDK board, press reset button
+      and stop auto-execution of existing `bootcmd` pressing any key in serial
+      terminal and enter the following command:
+      ------------------------->8----------------------
+      mmc rescan && fatload mmc 0:1 ${loadaddr} u-boot-update.scr && source ${loadaddr}
+      ------------------------->8----------------------
+      Wait before you see "u-boot update: OK" message.
+
+   4. Press RESET button and enjoy updated U-Boot version.
diff --git a/roms/u-boot/board/synopsys/hsdk/clk-lib.c b/roms/u-boot/board/synopsys/hsdk/clk-lib.c
new file mode 100644
index 000000000..bd43179fc
--- /dev/null
+++ b/roms/u-boot/board/synopsys/hsdk/clk-lib.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+
+#include <clk.h>
+#include <log.h>
+#include <malloc.h>
+#include <dm/device.h>
+
+#include "clk-lib.h"
+
+#define HZ_IN_MHZ	1000000
+#define ceil(x, y)	({ ulong __x = (x), __y = (y); (__x + __y - 1) / __y; })
+
+int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl)
+{
+	int ret;
+	ulong mhz_rate, priv_rate;
+	struct clk clk;
+
+	/* Dummy fmeas device, just to be able to use standard clk_* api */
+	struct udevice fmeas = {
+		.name = "clk-fmeas",
+	};
+	dev_set_ofnode(&fmeas, ofnode_path("/clk-fmeas"));
+
+	ret = clk_get_by_name(&fmeas, name, &clk);
+	if (ret) {
+		pr_err("clock '%s' not found, err=%d\n", name, ret);
+		return ret;
+	}
+
+	if (ctl & CLK_ON) {
+		ret = clk_enable(&clk);
+		if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
+			return ret;
+	}
+
+	if ((ctl & CLK_SET) && rate) {
+		priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate;
+		ret = clk_set_rate(&clk, priv_rate);
+		if (ret)
+			return ret;
+	}
+
+	if (ctl & CLK_OFF) {
+		ret = clk_disable(&clk);
+		if (ret) {
+			pr_err("clock '%s' can't be disabled, err=%d\n", name, ret);
+			return ret;
+		}
+	}
+
+	priv_rate = clk_get_rate(&clk);
+
+	clk_free(&clk);
+
+	mhz_rate = ceil(priv_rate, HZ_IN_MHZ);
+
+	if (ctl & CLK_MHZ)
+		priv_rate = mhz_rate;
+
+	if ((ctl & CLK_GET) && rate)
+		*rate = priv_rate;
+
+	if ((ctl & CLK_PRINT) && (ctl & CLK_MHZ))
+		printf("HSDK: clock '%s' rate %lu MHz\n", name, priv_rate);
+	else if (ctl & CLK_PRINT)
+		printf("HSDK: clock '%s' rate %lu Hz\n", name, priv_rate);
+	else
+		debug("HSDK: clock '%s' rate %lu MHz\n", name, mhz_rate);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/synopsys/hsdk/clk-lib.h b/roms/u-boot/board/synopsys/hsdk/clk-lib.h
new file mode 100644
index 000000000..970bcd4a1
--- /dev/null
+++ b/roms/u-boot/board/synopsys/hsdk/clk-lib.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+
+#ifndef __BOARD_CLK_LIB_H
+#define __BOARD_CLK_LIB_H
+
+#include <common.h>
+#include <linux/bitops.h>
+
+enum clk_ctl_ops {
+	CLK_SET		= BIT(0), /* set frequency */
+	CLK_GET		= BIT(1), /* get frequency */
+	CLK_ON		= BIT(2), /* enable clock */
+	CLK_OFF		= BIT(3), /* disable clock */
+	CLK_PRINT	= BIT(4), /* print frequency */
+	CLK_MHZ		= BIT(5)  /* all values in MHZ instead of HZ */
+};
+
+/*
+ * Depending on the clk_ctl_ops enable / disable /
+ * set clock rate from 'rate' argument / read clock to 'rate' argument /
+ * print clock rate. If CLK_MHZ flag set in clk_ctl_ops 'rate' is in MHz,
+ * otherwise - in Hz.
+ *
+ * This function expects "clk-fmeas" node in device tree:
+ * / {
+ *	clk-fmeas {
+ *		clocks = <&cpu_pll>, <&sys_pll>;
+ *		clock-names = "cpu-pll", "sys-pll";
+ *	};
+ * };
+ */
+int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl);
+
+#endif /* __BOARD_CLK_LIB_H */
diff --git a/roms/u-boot/board/synopsys/hsdk/config.mk b/roms/u-boot/board/synopsys/hsdk/config.mk
new file mode 100644
index 000000000..def944aad
--- /dev/null
+++ b/roms/u-boot/board/synopsys/hsdk/config.mk
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+
+ifdef CONFIG_BOARD_HSDK
+PLATFORM_CPPFLAGS += -mcpu=hs38_linux -mlittle-endian -matomic -mll64 \
+                     -mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \
+                     -mfpu=fpud_all
+
+bsp-generate: u-boot u-boot.bin
+	$(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \
+		--arc-id 0x52 --image $(srctree)/u-boot.bin \
+		--elf $(srctree)/u-boot
+	$(Q)tools/mkimage -T script -C none -n 'uboot update script' \
+		-d $(srctree)/u-boot-update.txt \
+		$(srctree)/u-boot-update.scr &> /dev/null
+endif
+
+ifdef CONFIG_BOARD_HSDK_4XD
+PLATFORM_CPPFLAGS += -mcpu=hs4x_rel31 -mlittle-endian -matomic -mll64 \
+                     -mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \
+                     -mfpu=fpud_all
+
+bsp-generate: u-boot u-boot.bin
+	$(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \
+		--arc-id 0x54 --image $(srctree)/u-boot.bin \
+		--elf $(srctree)/u-boot
+	$(Q)tools/mkimage -T script -C none -n 'uboot update script' \
+		-d $(srctree)/u-boot-update.txt \
+		$(srctree)/u-boot-update.scr &> /dev/null
+endif
diff --git a/roms/u-boot/board/synopsys/hsdk/env-lib.c b/roms/u-boot/board/synopsys/hsdk/env-lib.c
new file mode 100644
index 000000000..235f29565
--- /dev/null
+++ b/roms/u-boot/board/synopsys/hsdk/env-lib.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+
+#include "env-lib.h"
+#include <env.h>
+#include <log.h>
+
+#define MAX_CMD_LEN	25
+
+static void env_clear_common(u32 index, const struct env_map_common *map)
+{
+	map[index].val->val = 0;
+	map[index].val->set = false;
+}
+
+static int env_read_common(u32 index, const struct env_map_common *map)
+{
+	u32 val;
+
+	if (!env_get_yesno(map[index].env_name)) {
+		if (map[index].type == ENV_HEX) {
+			val = (u32)env_get_hex(map[index].env_name, 0);
+			debug("ENV: %s: = %#x\n", map[index].env_name, val);
+		} else {
+			val = (u32)env_get_ulong(map[index].env_name, 10, 0);
+			debug("ENV: %s: = %d\n", map[index].env_name, val);
+		}
+
+		map[index].val->val = val;
+		map[index].val->set = true;
+	}
+
+	return 0;
+}
+
+static void env_clear_core(u32 index, const struct env_map_percpu *map)
+{
+	for (u32 i = 0; i < NR_CPUS; i++) {
+		(*map[index].val)[i].val = 0;
+		(*map[index].val)[i].set = false;
+	}
+}
+
+static int env_read_core(u32 index, const struct env_map_percpu *map)
+{
+	u32 val;
+	char command[MAX_CMD_LEN];
+
+	for (u32 i = 0; i < NR_CPUS; i++) {
+		sprintf(command, "%s_%u", map[index].env_name, i);
+		if (!env_get_yesno(command)) {
+			if (map[index].type == ENV_HEX) {
+				val = (u32)env_get_hex(command, 0);
+				debug("ENV: %s: = %#x\n", command, val);
+			} else {
+				val = (u32)env_get_ulong(command, 10, 0);
+				debug("ENV: %s: = %d\n", command, val);
+			}
+
+			(*map[index].val)[i].val = val;
+			(*map[index].val)[i].set = true;
+		}
+	}
+
+	return 0;
+}
+
+static int env_validate_common(u32 index, const struct env_map_common *map)
+{
+	u32 value = map[index].val->val;
+	bool set = map[index].val->set;
+	u32 min = map[index].min;
+	u32 max = map[index].max;
+
+	/* Check if environment is mandatory */
+	if (map[index].mandatory && !set) {
+		pr_err("Variable \'%s\' is mandatory, but it is not defined\n",
+		       map[index].env_name);
+
+		return -EINVAL;
+	}
+
+	/* Check environment boundary */
+	if (set && (value < min || value > max)) {
+		if (map[index].type == ENV_HEX)
+			pr_err("Variable \'%s\' must be between %#x and %#x\n",
+			       map[index].env_name, min, max);
+		else
+			pr_err("Variable \'%s\' must be between %u and %u\n",
+			       map[index].env_name, min, max);
+
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int env_validate_core(u32 index, const struct env_map_percpu *map,
+			     bool (*cpu_used)(u32))
+{
+	u32 value;
+	bool set;
+	bool mandatory = map[index].mandatory;
+	u32 min, max;
+
+	for (u32 i = 0; i < NR_CPUS; i++) {
+		set = (*map[index].val)[i].set;
+		value = (*map[index].val)[i].val;
+
+		/* Check if environment is mandatory */
+		if (cpu_used(i) && mandatory && !set) {
+			pr_err("CPU %u is used, but \'%s_%u\' is not defined\n",
+			       i, map[index].env_name, i);
+
+			return -EINVAL;
+		}
+
+		min = map[index].min[i];
+		max = map[index].max[i];
+
+		/* Check environment boundary */
+		if (set && (value < min || value > max)) {
+			if (map[index].type == ENV_HEX)
+				pr_err("Variable \'%s_%u\' must be between %#x and %#x\n",
+				       map[index].env_name, i, min, max);
+			else
+				pr_err("Variable \'%s_%u\' must be between %d and %d\n",
+				       map[index].env_name, i, min, max);
+
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+void envs_cleanup_core(const struct env_map_percpu *map)
+{
+	/* Cleanup env struct first */
+	for (u32 i = 0; map[i].env_name; i++)
+		env_clear_core(i, map);
+}
+
+void envs_cleanup_common(const struct env_map_common *map)
+{
+	/* Cleanup env struct first */
+	for (u32 i = 0; map[i].env_name; i++)
+		env_clear_common(i, map);
+}
+
+int envs_read_common(const struct env_map_common *map)
+{
+	int ret;
+
+	for (u32 i = 0; map[i].env_name; i++) {
+		ret = env_read_common(i, map);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int envs_validate_common(const struct env_map_common *map)
+{
+	int ret;
+
+	for (u32 i = 0; map[i].env_name; i++) {
+		ret = env_validate_common(i, map);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int envs_read_validate_common(const struct env_map_common *map)
+{
+	int ret;
+
+	envs_cleanup_common(map);
+
+	ret = envs_read_common(map);
+	if (ret)
+		return ret;
+
+	ret = envs_validate_common(map);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int envs_read_validate_core(const struct env_map_percpu *map,
+			    bool (*cpu_used)(u32))
+{
+	int ret;
+
+	envs_cleanup_core(map);
+
+	for (u32 i = 0; map[i].env_name; i++) {
+		ret = env_read_core(i, map);
+		if (ret)
+			return ret;
+	}
+
+	for (u32 i = 0; map[i].env_name; i++) {
+		ret = env_validate_core(i, map, cpu_used);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int envs_process_and_validate(const struct env_map_common *common,
+			      const struct env_map_percpu *core,
+			      bool (*cpu_used)(u32))
+{
+	int ret;
+
+	ret = envs_read_validate_common(common);
+	if (ret)
+		return ret;
+
+	ret = envs_read_validate_core(core, cpu_used);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int args_envs_read_search(const struct env_map_common *map,
+				 int argc, char *const argv[])
+{
+	for (int i = 0; map[i].env_name; i++) {
+		if (!strcmp(argv[0], map[i].env_name))
+			return i;
+	}
+
+	pr_err("Unexpected argument '%s', can't parse\n", argv[0]);
+
+	return -ENOENT;
+}
+
+static int arg_read_set(const struct env_map_common *map, u32 i, int argc,
+			char *const argv[])
+{
+	char *endp = argv[1];
+
+	if (map[i].type == ENV_HEX)
+		map[i].val->val = simple_strtoul(argv[1], &endp, 16);
+	else
+		map[i].val->val = simple_strtoul(argv[1], &endp, 10);
+
+	map[i].val->set = true;
+
+	if (*endp == '\0')
+		return 0;
+
+	pr_err("Unexpected argument '%s', can't parse\n", argv[1]);
+
+	map[i].val->set = false;
+
+	return -EINVAL;
+}
+
+int args_envs_enumerate(const struct env_map_common *map, int enum_by,
+			int argc, char *const argv[])
+{
+	u32 i;
+
+	if (argc % enum_by) {
+		pr_err("unexpected argument number: %d\n", argc);
+		return -EINVAL;
+	}
+
+	while (argc > 0) {
+		i = args_envs_read_search(map, argc, argv);
+		if (i < 0)
+			return i;
+
+		debug("ARG: found '%s' with index %d\n", map[i].env_name, i);
+
+		if (i < 0) {
+			pr_err("unknown arg: %s\n", argv[0]);
+			return -EINVAL;
+		}
+
+		if (arg_read_set(map, i, argc, argv))
+			return -EINVAL;
+
+		debug("ARG: value.s '%s' == %#x\n", argv[1], map[i].val->val);
+
+		argc -= enum_by;
+		argv += enum_by;
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/synopsys/hsdk/env-lib.h b/roms/u-boot/board/synopsys/hsdk/env-lib.h
new file mode 100644
index 000000000..48c17c4d4
--- /dev/null
+++ b/roms/u-boot/board/synopsys/hsdk/env-lib.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+
+#ifndef __BOARD_ENV_LIB_H
+#define __BOARD_ENV_LIB_H
+
+#include <common.h>
+#include <config.h>
+#include <linux/kernel.h>
+
+enum env_type {
+	ENV_DEC,
+	ENV_HEX
+};
+
+typedef struct {
+	u32 val;
+	bool set;
+} u32_env;
+
+struct env_map_common {
+	const char *const env_name;
+	enum env_type type;
+	bool mandatory;
+	u32 min;
+	u32 max;
+	u32_env *val;
+};
+
+struct env_map_percpu {
+	const char *const env_name;
+	enum env_type type;
+	bool mandatory;
+	u32 min[NR_CPUS];
+	u32 max[NR_CPUS];
+	u32_env (*val)[NR_CPUS];
+};
+
+void envs_cleanup_common(const struct env_map_common *map);
+int envs_read_common(const struct env_map_common *map);
+int envs_validate_common(const struct env_map_common *map);
+int envs_read_validate_common(const struct env_map_common *map);
+
+void envs_cleanup_core(const struct env_map_percpu *map);
+int envs_read_validate_core(const struct env_map_percpu *map,
+			    bool (*cpu_used)(u32));
+int envs_process_and_validate(const struct env_map_common *common,
+			      const struct env_map_percpu *core,
+			      bool (*cpu_used)(u32));
+
+int args_envs_enumerate(const struct env_map_common *map,
+			int enum_by, int argc, char *const argv[]);
+
+#endif /* __BOARD_ENV_LIB_H */
diff --git a/roms/u-boot/board/synopsys/hsdk/headerize-hsdk.py b/roms/u-boot/board/synopsys/hsdk/headerize-hsdk.py
new file mode 100644
index 000000000..7b047cf4a
--- /dev/null
+++ b/roms/u-boot/board/synopsys/hsdk/headerize-hsdk.py
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+# Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+
+import os, getopt, sys, zlib
+from elftools.elf.elffile import ELFFile
+
+
+def usage(exit_code):
+    print("usage:")
+    print(sys.argv[0] + " --arc-id 0x52 --image u-boot.bin --elf u-boot")
+    sys.exit(exit_code)
+
+
+def elf_get_entry(filename):
+    with open(filename, 'rb') as f:
+        elffile = ELFFile(f)
+        return elffile.header['e_entry']
+
+
+def calc_check_sum(filename):
+    # u-boot.head check_sum for preloader - it is sum of all u-boot binary bytes
+    with open(filename, "rb") as file:
+        ba = bytearray(file.read())
+    return sum(ba) & 0xFF
+
+
+def arg_verify(uboot_bin_filename, uboot_elf_filename, arc_id):
+    if arc_id not in [0x52, 0x53, 0x54]:
+        print("unknown ARC ID: " + hex(arc_id))
+        sys.exit(2)
+
+    if not os.path.isfile(uboot_bin_filename):
+        print("uboot bin file not exists: " + uboot_bin_filename)
+        sys.exit(2)
+
+    if not os.path.isfile(uboot_elf_filename):
+        print("uboot elf file not exists: " + uboot_elf_filename)
+        sys.exit(2)
+
+
+def main():
+    try:
+        opts, args = getopt.getopt(sys.argv[1:],
+            "ha:i:l:e:", ["help", "arc-id=", "image=", "elf="])
+    except getopt.GetoptError as err:
+        print(err)
+        usage(2)
+
+    # default filenames
+    uboot_elf_filename  = "u-boot"
+    uboot_bin_filename  = "u-boot.bin"
+    headerised_filename = "u-boot.head"
+    uboot_scrypt_file   = "u-boot-update.txt"
+
+    # initial header values: place where preloader will store u-boot binary,
+    # should be equal to CONFIG_SYS_TEXT_BASE
+    image_copy_adr  = 0x81000000
+
+    # initial constant header values, do not change these values
+    arc_id          = 0x52         # 0x52 for 1st HSDK release (hardcoded in RTL)
+    magic1          = 0xdeadbeafaf # big endian byte order
+    flash_address   = 0x0
+    flash_type      = 0x0          # 0 - SPI flash, 1 - NOR flash
+    magic2          = [            # big endian byte order
+    0x20202a2020202020202020202a20202020207c5c2e20202020202e2f7c20202020207c2d,
+    0x2e5c2020202f2e2d7c20202020205c2020602d2d2d6020202f20202020202f205f202020,
+    0x205f20205c20202020207c205f60712070205f207c2020202020272e5f3d2f205c3d5f2e,
+    0x272020202020202020605c202f60202020202020202020202020206f2020202020202020]
+
+    for opt, arg in opts:
+        if opt in ('-h', "--help"):   usage(0)
+        if opt in ('-a', "--arc-id"): arc_id             = int(arg, 16)
+        if opt in ('-i', "--image"):  uboot_bin_filename = arg
+        if opt in ('-e', "--elf"):    uboot_elf_filename = arg
+
+    arg_verify(uboot_bin_filename, uboot_elf_filename, arc_id)
+
+    uboot_img_size = os.path.getsize(uboot_bin_filename)
+    jump_address = elf_get_entry(uboot_elf_filename)
+    check_sum = calc_check_sum(uboot_bin_filename)
+
+    # write header to file
+    with open(headerised_filename, "wb") as file:
+        file.write(arc_id.to_bytes(2, byteorder='little'))
+        file.write(uboot_img_size.to_bytes(4, byteorder='little'))
+        file.write(check_sum.to_bytes(1, byteorder='little'))
+        file.write(image_copy_adr.to_bytes(4, byteorder='little'))
+        file.write(magic1.to_bytes(5, byteorder='big'))
+        file.write(jump_address.to_bytes(4, byteorder='little'))
+        for i in range(12): file.write(0xFF.to_bytes(1, byteorder='little'))
+        for byte in magic2: file.write(byte.to_bytes(36, byteorder='big'))
+        for i in range(208 - len(magic2) * 36):
+            file.write(0xFF.to_bytes(1, byteorder='little'))
+        file.write(flash_address.to_bytes(4, byteorder='little'))
+        for i in range(11): file.write(0xFF.to_bytes(1, byteorder='little'))
+        file.write(flash_type.to_bytes(1, byteorder='little'))
+
+    # append u-boot image to header
+    with open(headerised_filename, "ab") as fo:
+        with open(uboot_bin_filename,'rb') as fi:
+            fo.write(fi.read())
+
+    # calc u-boot headerized image CRC32 (will be used by uboot update
+    # command for check)
+    headerised_image_crc = ""
+    with open(headerised_filename, "rb") as fi:
+        headerised_image_crc = hex(zlib.crc32(fi.read()) & 0xffffffff)
+
+    load_addr = 0x81000000
+    crc_store_adr = load_addr - 0x8
+    crc_calc_adr = crc_store_adr - 0x4
+    load_size = os.path.getsize(headerised_filename)
+    crc_calc_cmd = \
+        "crc32 " + hex(load_addr) + " " + hex(load_size) + " " + hex(crc_calc_adr)
+    crc_check_cmd = \
+        "mw.l " + hex(crc_store_adr) + " " + headerised_image_crc + " && " + \
+        crc_calc_cmd + " && " + \
+        "cmp.l " + hex(crc_store_adr) + " " + hex(crc_calc_adr) + " 1"
+
+    # make errase size to be allighned by 64K
+    if load_size & 0xFFFF == 0:
+        errase_size = load_size
+    else:
+        errase_size = load_size - (load_size & 0xFFFF) + 0x10000
+
+    # u-bood CMD to load u-bood with header to SPI flash
+    sf_load_image_cmd = \
+        "fatload mmc 0:1 " + hex(load_addr) + " " + headerised_filename + " && " + \
+        "sf probe 0:0 && " + \
+        crc_check_cmd + " && " + \
+        "sf protect unlock 0x0 " + hex(errase_size) + " && " + \
+        "sf erase 0x0 " + hex(errase_size) + " && " + \
+        "sf write " + hex(load_addr) + " 0x0 " + hex(load_size) + " && " + \
+        "sf protect lock 0x0 " + hex(errase_size)
+
+    update_uboot_cmd = sf_load_image_cmd + " && echo \"u-boot update: OK\""
+
+    with open(uboot_scrypt_file, "wb") as fo:
+        fo.write(update_uboot_cmd.encode('ascii'))
+
+
+if __name__ == "__main__":
+    try:
+        main()
+    except Exception as err:
+        print(err)
+        sys.exit(2)
diff --git a/roms/u-boot/board/synopsys/hsdk/hsdk.c b/roms/u-boot/board/synopsys/hsdk/hsdk.c
new file mode 100644
index 000000000..892b94bb0
--- /dev/null
+++ b/roms/u-boot/board/synopsys/hsdk/hsdk.c
@@ -0,0 +1,1268 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <config.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <image.h>
+#include <init.h>
+#include <irq_func.h>
+#include <log.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/printk.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/arcregs.h>
+#include <fdt_support.h>
+#include <dwmmc.h>
+#include <malloc.h>
+#include <usb.h>
+
+#include "clk-lib.h"
+#include "env-lib.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ALL_CPU_MASK		GENMASK(NR_CPUS - 1, 0)
+#define MASTER_CPU_ID		0
+#define APERTURE_SHIFT		28
+#define NO_CCM			0x10
+#define SLAVE_CPU_READY		0x12345678
+#define BOOTSTAGE_1		1 /* after SP, FP setup, before HW init */
+#define BOOTSTAGE_2		2 /* after HW init, before self halt */
+#define BOOTSTAGE_3		3 /* after self halt */
+#define BOOTSTAGE_4		4 /* before app launch */
+#define BOOTSTAGE_5		5 /* after app launch, unreachable */
+
+#define RESET_VECTOR_ADDR	0x0
+
+#define CREG_BASE		(ARC_PERIPHERAL_BASE + 0x1000)
+#define CREG_CPU_START		(CREG_BASE + 0x400)
+#define CREG_CPU_START_MASK	0xF
+#define CREG_CPU_START_POL	BIT(4)
+
+#define CREG_CORE_BOOT_IMAGE	GENMASK(5, 4)
+
+#define CREG_CPU_0_ENTRY	(CREG_BASE + 0x404)
+
+#define SDIO_BASE		(ARC_PERIPHERAL_BASE + 0xA000)
+#define SDIO_UHS_REG_EXT	(SDIO_BASE + 0x108)
+#define SDIO_UHS_REG_EXT_DIV_2	(2 << 30)
+
+/* Uncached access macros */
+#define arc_read_uncached_32(ptr)	\
+({					\
+	unsigned int __ret;		\
+	__asm__ __volatile__(		\
+	"	ld.di %0, [%1]	\n"	\
+	: "=r"(__ret)			\
+	: "r"(ptr));			\
+	__ret;				\
+})
+
+#define arc_write_uncached_32(ptr, data)\
+({					\
+	__asm__ __volatile__(		\
+	"	st.di %0, [%1]	\n"	\
+	:				\
+	: "r"(data), "r"(ptr));		\
+})
+
+struct hsdk_env_core_ctl {
+	u32_env entry[NR_CPUS];
+	u32_env iccm[NR_CPUS];
+	u32_env dccm[NR_CPUS];
+};
+
+struct hsdk_env_common_ctl {
+	bool halt_on_boot;
+	u32_env core_mask;
+	u32_env cpu_freq;
+	u32_env axi_freq;
+	u32_env tun_freq;
+	u32_env nvlim;
+	u32_env icache;
+	u32_env dcache;
+	u32_env csm_location;
+	u32_env l2_cache;
+	u32_env haps_apb;
+};
+
+/*
+ * Uncached cross-cpu structure. All CPUs must access to this structure fields
+ * only with arc_read_uncached_32() / arc_write_uncached_32() accessors (which
+ * implement ld.di / st.di instructions). Simultaneous cached and uncached
+ * access to this area will lead to data loss.
+ * We flush all data caches in board_early_init_r() as we don't want to have
+ * any dirty line in L1d$ or SL$ in this area.
+ */
+struct hsdk_cross_cpu {
+	/* slave CPU ready flag */
+	u32 ready_flag;
+	/* address of the area, which can be used for stack by slave CPU */
+	u32 stack_ptr;
+	/* slave CPU status - bootstage number */
+	s32 status[NR_CPUS];
+
+	/*
+	 * Slave CPU data - it is copy of corresponding fields in
+	 * hsdk_env_core_ctl and hsdk_env_common_ctl structures which are
+	 * required for slave CPUs initialization.
+	 * This fields can be populated by copying from hsdk_env_core_ctl
+	 * and hsdk_env_common_ctl structures with sync_cross_cpu_data()
+	 * function.
+	 */
+	u32 entry[NR_CPUS];
+	u32 iccm[NR_CPUS];
+	u32 dccm[NR_CPUS];
+
+	u32 core_mask;
+	u32 icache;
+	u32 dcache;
+
+	u8 cache_padding[ARCH_DMA_MINALIGN];
+} __aligned(ARCH_DMA_MINALIGN);
+
+/* Place for slave CPUs temporary stack */
+static u32 slave_stack[256 * NR_CPUS] __aligned(ARCH_DMA_MINALIGN);
+
+static struct hsdk_env_common_ctl env_common = {};
+static struct hsdk_env_core_ctl env_core = {};
+static struct hsdk_cross_cpu cross_cpu_data;
+
+static const struct env_map_common env_map_common[] = {
+	{ "core_mask",	ENV_HEX, true,	0x1, 0xF,	&env_common.core_mask },
+	{ "non_volatile_limit", ENV_HEX, true, 0, 0xF,	&env_common.nvlim },
+	{ "icache_ena",	ENV_HEX, true,	0, 1,		&env_common.icache },
+	{ "dcache_ena",	ENV_HEX, true,	0, 1,		&env_common.dcache },
+#if defined(CONFIG_BOARD_HSDK_4XD)
+	{ "l2_cache_ena",	ENV_HEX, true,	0, 1,		&env_common.l2_cache },
+	{ "csm_location",	ENV_HEX, true,	0, NO_CCM,	&env_common.csm_location },
+	{ "haps_apb_location",	ENV_HEX, true,	0, 1,		&env_common.haps_apb },
+#endif /* CONFIG_BOARD_HSDK_4XD */
+	{}
+};
+
+static const struct env_map_common env_map_clock[] = {
+	{ "cpu_freq",	ENV_DEC, false,	100, 1000,	&env_common.cpu_freq },
+	{ "axi_freq",	ENV_DEC, false,	200, 800,	&env_common.axi_freq },
+	{ "tun_freq",	ENV_DEC, false,	0, 150,		&env_common.tun_freq },
+	{}
+};
+
+static const struct env_map_percpu env_map_core[] = {
+	{ "core_iccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.iccm },
+	{ "core_dccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.dccm },
+	{}
+};
+
+static const struct env_map_common env_map_mask[] = {
+	{ "core_mask",	ENV_HEX, false,	0x1, 0xF,	&env_common.core_mask },
+	{}
+};
+
+static const struct env_map_percpu env_map_go[] = {
+	{ "core_entry", ENV_HEX, true, {0, 0, 0, 0}, {U32_MAX, U32_MAX, U32_MAX, U32_MAX}, &env_core.entry },
+	{}
+};
+
+enum board_type {
+	T_BOARD_NONE,
+	T_BOARD_HSDK,
+	T_BOARD_HSDK_4XD
+};
+
+static inline enum board_type get_board_type_runtime(void)
+{
+	u32 arc_id = read_aux_reg(ARC_AUX_IDENTITY) & 0xFF;
+
+	if (arc_id == 0x52)
+		return T_BOARD_HSDK;
+	else if (arc_id == 0x54)
+		return T_BOARD_HSDK_4XD;
+	else
+		return T_BOARD_NONE;
+}
+
+static inline enum board_type get_board_type_config(void)
+{
+	if (IS_ENABLED(CONFIG_BOARD_HSDK))
+		return T_BOARD_HSDK;
+	else if (IS_ENABLED(CONFIG_BOARD_HSDK_4XD))
+		return T_BOARD_HSDK_4XD;
+	else
+		return T_BOARD_NONE;
+}
+
+static bool is_board_match_runtime(enum board_type type_req)
+{
+	return get_board_type_runtime() == type_req;
+}
+
+static bool is_board_match_config(enum board_type type_req)
+{
+	return get_board_type_config() == type_req;
+}
+
+static const char * board_name(enum board_type type)
+{
+	switch (type) {
+		case T_BOARD_HSDK:
+			return "ARC HS Development Kit";
+		case T_BOARD_HSDK_4XD:
+			return "ARC HS4x/HS4xD Development Kit";
+		default:
+			return "?";
+	}
+}
+
+static bool board_mismatch(void)
+{
+	return get_board_type_config() != get_board_type_runtime();
+}
+
+static void sync_cross_cpu_data(void)
+{
+	u32 value;
+
+	for (u32 i = 0; i < NR_CPUS; i++) {
+		value = env_core.entry[i].val;
+		arc_write_uncached_32(&cross_cpu_data.entry[i], value);
+	}
+
+	for (u32 i = 0; i < NR_CPUS; i++) {
+		value = env_core.iccm[i].val;
+		arc_write_uncached_32(&cross_cpu_data.iccm[i], value);
+	}
+
+	for (u32 i = 0; i < NR_CPUS; i++) {
+		value = env_core.dccm[i].val;
+		arc_write_uncached_32(&cross_cpu_data.dccm[i], value);
+	}
+
+	value = env_common.core_mask.val;
+	arc_write_uncached_32(&cross_cpu_data.core_mask, value);
+
+	value = env_common.icache.val;
+	arc_write_uncached_32(&cross_cpu_data.icache, value);
+
+	value = env_common.dcache.val;
+	arc_write_uncached_32(&cross_cpu_data.dcache, value);
+}
+
+/* Can be used only on master CPU */
+static bool is_cpu_used(u32 cpu_id)
+{
+	return !!(env_common.core_mask.val & BIT(cpu_id));
+}
+
+/* TODO: add ICCM BCR and DCCM BCR runtime check */
+static void init_slave_cpu_func(u32 core)
+{
+	u32 val;
+
+	/* Remap ICCM to another memory region if it exists */
+	val = arc_read_uncached_32(&cross_cpu_data.iccm[core]);
+	if (val != NO_CCM)
+		write_aux_reg(ARC_AUX_ICCM_BASE, val << APERTURE_SHIFT);
+
+	/* Remap DCCM to another memory region if it exists */
+	val = arc_read_uncached_32(&cross_cpu_data.dccm[core]);
+	if (val != NO_CCM)
+		write_aux_reg(ARC_AUX_DCCM_BASE, val << APERTURE_SHIFT);
+
+	if (arc_read_uncached_32(&cross_cpu_data.icache))
+		icache_enable();
+	else
+		icache_disable();
+
+	if (arc_read_uncached_32(&cross_cpu_data.dcache))
+		dcache_enable();
+	else
+		dcache_disable();
+}
+
+static void init_cluster_nvlim(void)
+{
+	u32 val = env_common.nvlim.val << APERTURE_SHIFT;
+
+	flush_dcache_all();
+	write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val);
+	/* AUX_AUX_CACHE_LIMIT reg is missing starting from HS48 */
+	if (is_board_match_runtime(T_BOARD_HSDK))
+		write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
+	flush_n_invalidate_dcache_all();
+}
+
+static void init_cluster_slc(void)
+{
+	/* ARC HS38 doesn't support SLC disabling */
+	if (!is_board_match_config(T_BOARD_HSDK_4XD))
+		return;
+
+	if (env_common.l2_cache.val)
+		slc_enable();
+	else
+		slc_disable();
+}
+
+#define CREG_CSM_BASE		(CREG_BASE + 0x210)
+
+static void init_cluster_csm(void)
+{
+	/* ARC HS38 in HSDK SoC doesn't include CSM */
+	if (!is_board_match_config(T_BOARD_HSDK_4XD))
+		return;
+
+	if (env_common.csm_location.val == NO_CCM) {
+		write_aux_reg(ARC_AUX_CSM_ENABLE, 0);
+	} else {
+		/*
+		 * CSM base address is 256kByte aligned but we allow to map
+		 * CSM only to aperture start (256MByte aligned)
+		 * The field in CREG_CSM_BASE is in 17:2 bits itself so we need
+		 * to shift it.
+		 */
+		u32 csm_base = (env_common.csm_location.val * SZ_1K) << 2;
+
+		write_aux_reg(ARC_AUX_CSM_ENABLE, 1);
+		writel(csm_base, (void __iomem *)CREG_CSM_BASE);
+	}
+}
+
+static void init_master_icache(void)
+{
+	if (icache_status()) {
+		/* I$ is enabled - we need to disable it */
+		if (!env_common.icache.val)
+			icache_disable();
+	} else {
+		/* I$ is disabled - we need to enable it */
+		if (env_common.icache.val) {
+			icache_enable();
+
+			/* invalidate I$ right after enable */
+			invalidate_icache_all();
+		}
+	}
+}
+
+static void init_master_dcache(void)
+{
+	if (dcache_status()) {
+		/* D$ is enabled - we need to disable it */
+		if (!env_common.dcache.val)
+			dcache_disable();
+	} else {
+		/* D$ is disabled - we need to enable it */
+		if (env_common.dcache.val)
+			dcache_enable();
+
+		/* TODO: probably we need ti invalidate D$ right after enable */
+	}
+}
+
+static int cleanup_before_go(void)
+{
+	disable_interrupts();
+	sync_n_cleanup_cache_all();
+
+	return 0;
+}
+
+void slave_cpu_set_boot_addr(u32 addr)
+{
+	/* All cores have reset vector pointing to 0 */
+	writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
+
+	/* Make sure other cores see written value in memory */
+	sync_n_cleanup_cache_all();
+}
+
+static inline void halt_this_cpu(void)
+{
+	__builtin_arc_flag(1);
+}
+
+static u32 get_masked_cpu_ctart_reg(void)
+{
+	int cmd = readl((void __iomem *)CREG_CPU_START);
+
+	/*
+	 * Quirk for HSDK-4xD - due to HW issues HSDK can use any pulse polarity
+	 * and HSDK-4xD require active low polarity of cpu_start pulse.
+	 */
+	cmd &= ~CREG_CPU_START_POL;
+
+	cmd &= ~CREG_CPU_START_MASK;
+
+	return cmd;
+}
+
+static void smp_kick_cpu_x(u32 cpu_id)
+{
+	int cmd;
+
+	if (cpu_id > NR_CPUS)
+		return;
+
+	cmd = get_masked_cpu_ctart_reg();
+	cmd |= (1 << cpu_id);
+	writel(cmd, (void __iomem *)CREG_CPU_START);
+}
+
+static u32 prepare_cpu_ctart_reg(void)
+{
+	return get_masked_cpu_ctart_reg() | env_common.core_mask.val;
+}
+
+/* slave CPU entry for configuration */
+__attribute__((naked, noreturn, flatten)) noinline void hsdk_core_init_f(void)
+{
+	__asm__ __volatile__(
+		"ld.di	r8,	[%0]\n"
+		"mov	%%sp,	r8\n"
+		"mov	%%fp,	%%sp\n"
+		: /* no output */
+		: "r" (&cross_cpu_data.stack_ptr));
+
+	invalidate_icache_all();
+
+	arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_1);
+	init_slave_cpu_func(CPU_ID_GET());
+
+	arc_write_uncached_32(&cross_cpu_data.ready_flag, SLAVE_CPU_READY);
+	arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_2);
+
+	/* Halt the processor until the master kick us again */
+	halt_this_cpu();
+
+	/*
+	 * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
+	 * cores but we leave them for gebug purposes.
+	 */
+	__builtin_arc_nop();
+	__builtin_arc_nop();
+	__builtin_arc_nop();
+
+	arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_3);
+
+	/* get the updated entry - invalidate i$ */
+	invalidate_icache_all();
+
+	arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_4);
+
+	/* Run our program */
+	((void (*)(void))(arc_read_uncached_32(&cross_cpu_data.entry[CPU_ID_GET()])))();
+
+	/* This bootstage is unreachable as we don't return from app we launch */
+	arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_5);
+
+	/* Something went terribly wrong */
+	while (true)
+		halt_this_cpu();
+}
+
+static void clear_cross_cpu_data(void)
+{
+	arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
+	arc_write_uncached_32(&cross_cpu_data.stack_ptr, 0);
+
+	for (u32 i = 0; i < NR_CPUS; i++)
+		arc_write_uncached_32(&cross_cpu_data.status[i], 0);
+}
+
+static noinline void do_init_slave_cpu(u32 cpu_id)
+{
+	/* attempts number for check clave CPU ready_flag */
+	u32 attempts = 100;
+	u32 stack_ptr = (u32)(slave_stack + (64 * cpu_id));
+
+	if (cpu_id >= NR_CPUS)
+		return;
+
+	arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
+
+	/* Use global unique place for each slave cpu stack */
+	arc_write_uncached_32(&cross_cpu_data.stack_ptr, stack_ptr);
+
+	debug("CPU %u: stack pool base: %p\n", cpu_id, slave_stack);
+	debug("CPU %u: current slave stack base: %x\n", cpu_id, stack_ptr);
+	slave_cpu_set_boot_addr((u32)hsdk_core_init_f);
+
+	smp_kick_cpu_x(cpu_id);
+
+	debug("CPU %u: cross-cpu flag: %x [before timeout]\n", cpu_id,
+	      arc_read_uncached_32(&cross_cpu_data.ready_flag));
+
+	while (!arc_read_uncached_32(&cross_cpu_data.ready_flag) && attempts--)
+		mdelay(10);
+
+	/* Just to be sure that slave cpu is halted after it set ready_flag */
+	mdelay(20);
+
+	/*
+	 * Only print error here if we reach timeout as there is no option to
+	 * halt slave cpu (or check that slave cpu is halted)
+	 */
+	if (!attempts)
+		pr_err("CPU %u is not responding after init!\n", cpu_id);
+
+	/* Check current stage of slave cpu */
+	if (arc_read_uncached_32(&cross_cpu_data.status[cpu_id]) != BOOTSTAGE_2)
+		pr_err("CPU %u status is unexpected: %d\n", cpu_id,
+		       arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
+
+	debug("CPU %u: cross-cpu flag: %x [after timeout]\n", cpu_id,
+	      arc_read_uncached_32(&cross_cpu_data.ready_flag));
+	debug("CPU %u: status: %d [after timeout]\n", cpu_id,
+	      arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
+}
+
+static void do_init_slave_cpus(void)
+{
+	clear_cross_cpu_data();
+	sync_cross_cpu_data();
+
+	debug("cross_cpu_data location: %#x\n", (u32)&cross_cpu_data);
+
+	for (u32 i = MASTER_CPU_ID + 1; i < NR_CPUS; i++)
+		if (is_cpu_used(i))
+			do_init_slave_cpu(i);
+}
+
+static void do_init_master_cpu(void)
+{
+	/*
+	 * Setup master caches even if master isn't used as we want to use
+	 * same cache configuration on all running CPUs
+	 */
+	init_master_icache();
+	init_master_dcache();
+}
+
+enum hsdk_axi_masters {
+	M_HS_CORE = 0,
+	M_HS_RTT,
+	M_AXI_TUN,
+	M_HDMI_VIDEO,
+	M_HDMI_AUDIO,
+	M_USB_HOST,
+	M_ETHERNET,
+	M_SDIO,
+	M_GPU,
+	M_DMAC_0,
+	M_DMAC_1,
+	M_DVFS
+};
+
+#define UPDATE_VAL	1
+
+/*
+ * m	master		AXI_M_m_SLV0	AXI_M_m_SLV1	AXI_M_m_OFFSET0	AXI_M_m_OFFSET1
+ * 0	HS (CBU)	0x11111111	0x63111111	0xFEDCBA98	0x0E543210
+ * 1	HS (RTT)	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 2	AXI Tunnel	0x88888888	0x88888888	0xFEDCBA98	0x76543210
+ * 3	HDMI-VIDEO	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 4	HDMI-ADUIO	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 5	USB-HOST	0x77777777	0x77999999	0xFEDCBA98	0x76DCBA98
+ * 6	ETHERNET	0x77777777	0x77999999	0xFEDCBA98	0x76DCBA98
+ * 7	SDIO		0x77777777	0x77999999	0xFEDCBA98	0x76DCBA98
+ * 8	GPU		0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 9	DMAC (port #1)	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 10	DMAC (port #2)	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 11	DVFS		0x00000000	0x60000000	0x00000000	0x00000000
+ *
+ * Please read ARC HS Development IC Specification, section 17.2 for more
+ * information about apertures configuration.
+ * NOTE: we intentionally modify default settings in U-boot. Default settings
+ * are specified in "Table 111 CREG Address Decoder register reset values".
+ */
+
+#define CREG_AXI_M_SLV0(m)  ((void __iomem *)(CREG_BASE + 0x020 * (m)))
+#define CREG_AXI_M_SLV1(m)  ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x004))
+#define CREG_AXI_M_OFT0(m)  ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x008))
+#define CREG_AXI_M_OFT1(m)  ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x00C))
+#define CREG_AXI_M_UPDT(m)  ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x014))
+
+#define CREG_AXI_M_HS_CORE_BOOT	((void __iomem *)(CREG_BASE + 0x010))
+
+#define CREG_PAE	((void __iomem *)(CREG_BASE + 0x180))
+#define CREG_PAE_UPDT	((void __iomem *)(CREG_BASE + 0x194))
+
+void init_memory_bridge(void)
+{
+	u32 reg;
+
+	/*
+	 * M_HS_CORE has one unic register - BOOT.
+	 * We need to clean boot mirror (BOOT[1:0]) bits in them.
+	 */
+	reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
+	writel(reg, CREG_AXI_M_HS_CORE_BOOT);
+	writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
+	writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
+	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
+	writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
+
+	writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
+	writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
+	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
+	writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
+
+	writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
+	writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
+	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
+	writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
+
+	writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
+	writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
+	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
+	writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
+
+	writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
+	writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
+	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
+	writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
+
+	writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
+	writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
+	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
+	writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
+
+	writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
+	writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
+	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
+	writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
+
+	writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
+	writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
+	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
+	writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
+
+	writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
+	writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
+	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
+	writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
+
+	writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
+	writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
+	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
+	writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
+
+	writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
+	writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
+	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
+	writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
+
+	writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
+	writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
+	writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
+	writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
+
+	writel(0x00000000, CREG_PAE);
+	writel(UPDATE_VAL, CREG_PAE_UPDT);
+}
+
+/*
+ * For HSDK-4xD we do additional AXI bridge tweaking in hsdk_init command:
+ * - we shrink IOC region.
+ * - we configure HS CORE SLV1 aperture depending on haps_apb_location
+ *   environment variable.
+ *
+ * As we've already configured AXI bridge in init_memory_bridge we don't
+ * do full configuration here but reconfigure changed part.
+ *
+ * m	master		AXI_M_m_SLV0	AXI_M_m_SLV1	AXI_M_m_OFFSET0	AXI_M_m_OFFSET1
+ * 0	HS (CBU)	0x11111111	0x63111111	0xFEDCBA98	0x0E543210	[haps_apb_location = 0]
+ * 0	HS (CBU)	0x11111111	0x61111111	0xFEDCBA98	0x06543210	[haps_apb_location = 1]
+ * 1	HS (RTT)	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 2	AXI Tunnel	0x88888888	0x88888888	0xFEDCBA98	0x76543210
+ * 3	HDMI-VIDEO	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 4	HDMI-ADUIO	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 5	USB-HOST	0x77777777	0x77779999	0xFEDCBA98	0x7654BA98
+ * 6	ETHERNET	0x77777777	0x77779999	0xFEDCBA98	0x7654BA98
+ * 7	SDIO		0x77777777	0x77779999	0xFEDCBA98	0x7654BA98
+ * 8	GPU		0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 9	DMAC (port #1)	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 10	DMAC (port #2)	0x77777777	0x77777777	0xFEDCBA98	0x76543210
+ * 11	DVFS		0x00000000	0x60000000	0x00000000	0x00000000
+ */
+void tweak_memory_bridge_cfg(void)
+{
+	/*
+	 * Only HSDK-4xD requre additional AXI bridge tweaking depending on
+	 * haps_apb_location environment variable
+	 */
+	if (!is_board_match_config(T_BOARD_HSDK_4XD))
+		return;
+
+	if (env_common.haps_apb.val) {
+		writel(0x61111111, CREG_AXI_M_SLV1(M_HS_CORE));
+		writel(0x06543210, CREG_AXI_M_OFT1(M_HS_CORE));
+	} else {
+		writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
+		writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
+	}
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
+
+	writel(0x77779999, CREG_AXI_M_SLV1(M_USB_HOST));
+	writel(0x7654BA98, CREG_AXI_M_OFT1(M_USB_HOST));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
+
+	writel(0x77779999, CREG_AXI_M_SLV1(M_ETHERNET));;
+	writel(0x7654BA98, CREG_AXI_M_OFT1(M_ETHERNET));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
+
+	writel(0x77779999, CREG_AXI_M_SLV1(M_SDIO));
+	writel(0x7654BA98, CREG_AXI_M_OFT1(M_SDIO));
+	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
+}
+
+static void setup_clocks(void)
+{
+	ulong rate;
+
+	/* Setup CPU clock */
+	if (env_common.cpu_freq.set) {
+		rate = env_common.cpu_freq.val;
+		soc_clk_ctl("cpu-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
+	}
+
+	/* Setup TUN clock */
+	if (env_common.tun_freq.set) {
+		rate = env_common.tun_freq.val;
+		if (rate)
+			soc_clk_ctl("tun-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
+		else
+			soc_clk_ctl("tun-clk", NULL, CLK_OFF);
+	}
+
+	if (env_common.axi_freq.set) {
+		rate = env_common.axi_freq.val;
+		soc_clk_ctl("axi-clk", &rate, CLK_SET | CLK_ON | CLK_MHZ);
+	}
+}
+
+static void do_init_cluster(void)
+{
+	/*
+	 * A multi-core ARC HS configuration always includes only one
+	 * ARC_AUX_NON_VOLATILE_LIMIT register, which is shared by all the
+	 * cores.
+	 */
+	init_cluster_nvlim();
+	init_cluster_csm();
+	init_cluster_slc();
+	tweak_memory_bridge_cfg();
+}
+
+static int check_master_cpu_id(void)
+{
+	if (CPU_ID_GET() == MASTER_CPU_ID)
+		return 0;
+
+	pr_err("u-boot runs on non-master cpu with id: %lu\n", CPU_ID_GET());
+
+	return -ENOENT;
+}
+
+static noinline int prepare_cpus(void)
+{
+	int ret;
+
+	ret = check_master_cpu_id();
+	if (ret)
+		return ret;
+
+	ret = envs_process_and_validate(env_map_common, env_map_core, is_cpu_used);
+	if (ret)
+		return ret;
+
+	printf("CPU start mask is %#x\n", env_common.core_mask.val);
+
+	do_init_slave_cpus();
+	do_init_master_cpu();
+	do_init_cluster();
+
+	return 0;
+}
+
+static int hsdk_go_run(u32 cpu_start_reg)
+{
+	/* Cleanup caches, disable interrupts */
+	cleanup_before_go();
+
+	if (env_common.halt_on_boot)
+		halt_this_cpu();
+
+	/*
+	 * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
+	 * cores but we leave them for gebug purposes.
+	 */
+	__builtin_arc_nop();
+	__builtin_arc_nop();
+	__builtin_arc_nop();
+
+	/* Kick chosen slave CPUs */
+	writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
+
+	if (is_cpu_used(MASTER_CPU_ID))
+		((void (*)(void))(env_core.entry[MASTER_CPU_ID].val))();
+	else
+		halt_this_cpu();
+
+	pr_err("u-boot still runs on cpu [%ld]\n", CPU_ID_GET());
+
+	/*
+	 * We will never return after executing our program if master cpu used
+	 * otherwise halt master cpu manually.
+	 */
+	while (true)
+		halt_this_cpu();
+
+	return 0;
+}
+
+int board_prep_linux(bootm_headers_t *images)
+{
+	int ret, ofst;
+	char mask[15];
+
+	ret = envs_read_validate_common(env_map_mask);
+	if (ret)
+		return ret;
+
+	/* Rollback to default values */
+	if (!env_common.core_mask.set) {
+		env_common.core_mask.val = ALL_CPU_MASK;
+		env_common.core_mask.set = true;
+	}
+
+	printf("CPU start mask is %#x\n", env_common.core_mask.val);
+
+	if (!is_cpu_used(MASTER_CPU_ID))
+		pr_err("ERR: try to launch linux with CPU[0] disabled! It doesn't work for ARC.\n");
+
+	/*
+	 * If we want to launch linux on all CPUs we don't need to patch
+	 * linux DTB as it is default configuration
+	 */
+	if (env_common.core_mask.val == ALL_CPU_MASK)
+		return 0;
+
+	if (!IMAGE_ENABLE_OF_LIBFDT || !images->ft_len) {
+		pr_err("WARN: core_mask setup will work properly only with external DTB!\n");
+		return 0;
+	}
+
+	/* patch '/possible-cpus' property according to cpu mask */
+	ofst = fdt_path_offset(images->ft_addr, "/");
+	sprintf(mask, "%s%s%s%s",
+		is_cpu_used(0) ? "0," : "",
+		is_cpu_used(1) ? "1," : "",
+		is_cpu_used(2) ? "2," : "",
+		is_cpu_used(3) ? "3," : "");
+	ret = fdt_setprop_string(images->ft_addr, ofst, "possible-cpus", mask);
+	/*
+	 * If we failed to patch '/possible-cpus' property we don't need break
+	 * linux loading process: kernel will handle it but linux will print
+	 * warning like "Timeout: CPU1 FAILED to comeup !!!".
+	 * So warn here about error, but return 0 like no error had occurred.
+	 */
+	if (ret)
+		pr_err("WARN: failed to patch '/possible-cpus' property, ret=%d\n",
+		       ret);
+
+	return 0;
+}
+
+void board_jump_and_run(ulong entry, int zero, int arch, uint params)
+{
+	void (*kernel_entry)(int zero, int arch, uint params);
+	u32 cpu_start_reg;
+
+	kernel_entry = (void (*)(int, int, uint))entry;
+
+	/* Prepare CREG_CPU_START for kicking chosen CPUs */
+	cpu_start_reg = prepare_cpu_ctart_reg();
+
+	/* In case of run without hsdk_init */
+	slave_cpu_set_boot_addr(entry);
+
+	/* In case of run with hsdk_init */
+	for (u32 i = 0; i < NR_CPUS; i++) {
+		env_core.entry[i].val = entry;
+		env_core.entry[i].set = true;
+	}
+	/* sync cross_cpu struct as we updated core-entry variables */
+	sync_cross_cpu_data();
+
+	/* Kick chosen slave CPUs */
+	writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
+
+	if (is_cpu_used(0))
+		kernel_entry(zero, arch, params);
+}
+
+static int hsdk_go_prepare_and_run(void)
+{
+	/* Prepare CREG_CPU_START for kicking chosen CPUs */
+	u32 reg = prepare_cpu_ctart_reg();
+
+	if (env_common.halt_on_boot)
+		printf("CPU will halt before application start, start application with debugger.\n");
+
+	return hsdk_go_run(reg);
+}
+
+static int do_hsdk_go(struct cmd_tbl *cmdtp, int flag, int argc,
+		      char *const argv[])
+{
+	int ret;
+
+	if (board_mismatch()) {
+		printf("ERR: U-boot is not configured for this board!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	/*
+	 * Check for 'halt' parameter. 'halt' = enter halt-mode just before
+	 * starting the application; can be used for debug.
+	 */
+	if (argc > 1) {
+		env_common.halt_on_boot = !strcmp(argv[1], "halt");
+		if (!env_common.halt_on_boot) {
+			pr_err("Unrecognised parameter: \'%s\'\n", argv[1]);
+			return CMD_RET_FAILURE;
+		}
+	}
+
+	ret = check_master_cpu_id();
+	if (ret)
+		return ret;
+
+	ret = envs_process_and_validate(env_map_mask, env_map_go, is_cpu_used);
+	if (ret)
+		return ret;
+
+	/* sync cross_cpu struct as we updated core-entry variables */
+	sync_cross_cpu_data();
+
+	ret = hsdk_go_prepare_and_run();
+
+	return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	hsdk_go, 3, 0, do_hsdk_go,
+	"Synopsys HSDK specific command",
+	"     - Boot stand-alone application on HSDK\n"
+	"hsdk_go halt - Boot stand-alone application on HSDK, halt CPU just before application run\n"
+);
+
+/*
+ * We may simply use static variable here to store init status, but we also want
+ * to avoid the situation when we reload U-boot via MDB after previous
+ * init is done but HW reset (board reset) isn't done. So let's store the
+ * init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will
+ * survive after U-boot is reloaded via MDB.
+ */
+#define INIT_MARKER_REGISTER		((void __iomem *)CREG_CPU_0_ENTRY)
+/* must be equal to INIT_MARKER_REGISTER reset value */
+#define INIT_MARKER_PENDING		0
+
+static bool init_marker_get(void)
+{
+	return readl(INIT_MARKER_REGISTER) != INIT_MARKER_PENDING;
+}
+
+static void init_mark_done(void)
+{
+	writel(~INIT_MARKER_PENDING, INIT_MARKER_REGISTER);
+}
+
+static int do_hsdk_init(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	int ret;
+
+	if (board_mismatch()) {
+		printf("ERR: U-boot is not configured for this board!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	/* hsdk_init can be run only once */
+	if (init_marker_get()) {
+		printf("HSDK HW is already initialized! Please reset the board if you want to change the configuration.\n");
+		return CMD_RET_FAILURE;
+	}
+
+	ret = prepare_cpus();
+	if (!ret)
+		init_mark_done();
+
+	return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	hsdk_init, 1, 0, do_hsdk_init,
+	"Synopsys HSDK specific command",
+	"- Init HSDK HW\n"
+);
+
+static int do_hsdk_clock_set(struct cmd_tbl *cmdtp, int flag, int argc,
+			     char *const argv[])
+{
+	int ret = 0;
+
+	/* Strip off leading subcommand argument */
+	argc--;
+	argv++;
+
+	envs_cleanup_common(env_map_clock);
+
+	if (!argc) {
+		printf("Set clocks to values specified in environment\n");
+		ret = envs_read_common(env_map_clock);
+	} else {
+		printf("Set clocks to values specified in args\n");
+		ret = args_envs_enumerate(env_map_clock, 2, argc, argv);
+	}
+
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	ret = envs_validate_common(env_map_clock);
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	/* Setup clock tree HW */
+	setup_clocks();
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_hsdk_clock_get(struct cmd_tbl *cmdtp, int flag, int argc,
+			     char *const argv[])
+{
+	ulong rate;
+
+	if (soc_clk_ctl("cpu-clk", &rate, CLK_GET | CLK_MHZ))
+		return CMD_RET_FAILURE;
+
+	if (env_set_ulong("cpu_freq", rate))
+		return CMD_RET_FAILURE;
+
+	if (soc_clk_ctl("tun-clk", &rate, CLK_GET | CLK_MHZ))
+		return CMD_RET_FAILURE;
+
+	if (env_set_ulong("tun_freq", rate))
+		return CMD_RET_FAILURE;
+
+	if (soc_clk_ctl("axi-clk", &rate, CLK_GET | CLK_MHZ))
+		return CMD_RET_FAILURE;
+
+	if (env_set_ulong("axi_freq", rate))
+		return CMD_RET_FAILURE;
+
+	printf("Clock values are saved to environment\n");
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_hsdk_clock_print(struct cmd_tbl *cmdtp, int flag, int argc,
+			       char *const argv[])
+{
+	/* Main clocks */
+	soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_hsdk_clock_print_all(struct cmd_tbl *cmdtp, int flag, int argc,
+				   char *const argv[])
+{
+	/*
+	 * NOTE: as of today we don't use some peripherals like HDMI / EBI
+	 * so we don't want to print their clocks ("hdmi-sys-clk", "hdmi-pll",
+	 * "hdmi-clk", "ebi-clk"). Nevertheless their clock subsystems is fully
+	 * functional and we can print their clocks if it is required
+	 */
+
+	/* CPU clock domain */
+	soc_clk_ctl("cpu-pll", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
+	printf("\n");
+
+	/* SYS clock domain */
+	soc_clk_ctl("sys-pll", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("apb-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("eth-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("usb-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("sdio-clk", NULL, CLK_PRINT | CLK_MHZ);
+	if (is_board_match_runtime(T_BOARD_HSDK_4XD))
+		soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
+	if (is_board_match_runtime(T_BOARD_HSDK)) {
+		soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
+		soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
+	}
+	soc_clk_ctl("dmac-core-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("dmac-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("sdio-ref-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("spi-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("i2c-clk", NULL, CLK_PRINT | CLK_MHZ);
+/*	soc_clk_ctl("ebi-clk", NULL, CLK_PRINT | CLK_MHZ); */
+	soc_clk_ctl("uart-clk", NULL, CLK_PRINT | CLK_MHZ);
+	printf("\n");
+
+	/* DDR clock domain */
+	soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
+	printf("\n");
+
+	/* HDMI clock domain */
+	if (is_board_match_runtime(T_BOARD_HSDK_4XD)) {
+		soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ);
+		soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ);
+		printf("\n");
+	}
+
+	/* TUN clock domain */
+	soc_clk_ctl("tun-pll", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("rom-clk", NULL, CLK_PRINT | CLK_MHZ);
+	soc_clk_ctl("pwm-clk", NULL, CLK_PRINT | CLK_MHZ);
+	if (is_board_match_runtime(T_BOARD_HSDK_4XD))
+		soc_clk_ctl("timer-clk", NULL, CLK_PRINT | CLK_MHZ);
+	printf("\n");
+
+	return CMD_RET_SUCCESS;
+}
+
+struct cmd_tbl cmd_hsdk_clock[] = {
+	U_BOOT_CMD_MKENT(set, 3, 0, do_hsdk_clock_set, "", ""),
+	U_BOOT_CMD_MKENT(get, 3, 0, do_hsdk_clock_get, "", ""),
+	U_BOOT_CMD_MKENT(print, 4, 0, do_hsdk_clock_print, "", ""),
+	U_BOOT_CMD_MKENT(print_all, 4, 0, do_hsdk_clock_print_all, "", ""),
+};
+
+static int do_hsdk_clock(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	struct cmd_tbl *c;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	/* Strip off leading 'hsdk_clock' command argument */
+	argc--;
+	argv++;
+
+	c = find_cmd_tbl(argv[0], cmd_hsdk_clock, ARRAY_SIZE(cmd_hsdk_clock));
+	if (!c)
+		return CMD_RET_USAGE;
+
+	return c->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+	hsdk_clock, CONFIG_SYS_MAXARGS, 0, do_hsdk_clock,
+	"Synopsys HSDK specific clock command",
+	"set   - Set clock to values specified in environment / command line arguments\n"
+	"hsdk_clock get   - Save clock values to environment\n"
+	"hsdk_clock print - Print main clock values to console\n"
+	"hsdk_clock print_all - Print all clock values to console\n"
+);
+
+/* init calls */
+int board_early_init_f(void)
+{
+	/*
+	 * Setup AXI apertures unconditionally as we want to have DDR
+	 * in 0x00000000 region when we are kicking slave cpus.
+	 */
+	init_memory_bridge();
+
+	/*
+	 * Switch SDIO external ciu clock divider from default div-by-8 to
+	 * minimum possible div-by-2.
+	 */
+	writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	/*
+	 * TODO: Init USB here to be able read environment from USB MSD.
+	 * It can be done with usb_init() call. We can't do it right now
+	 * due to brocken USB IP SW reset and lack of USB IP HW reset in
+	 * linux kernel (if we init USB here we will break USB in linux)
+	 */
+
+	/*
+	 * Flush all d$ as we want to use uncached area with st.di / ld.di
+	 * instructions and we don't want to have any dirty line in L1d$ or SL$
+	 * in this area. It is enough to flush all d$ once here as we access to
+	 * uncached area with regular st (non .di) instruction only when we copy
+	 * data during u-boot relocation.
+	 */
+	flush_dcache_all();
+
+	printf("Relocation Offset is: %08lx\n", gd->reloc_off);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	/*
+	 * Populate environment with clock frequency values -
+	 * run hsdk_clock get callback without uboot command run.
+	 */
+	do_hsdk_clock_get(NULL, 0, 0, NULL);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	u32 reg;
+
+	printf("Board: Synopsys %s\n", board_name(get_board_type_runtime()));
+
+	if (board_mismatch())
+		printf("WARN: U-boot is configured NOT for this board but for %s!\n",
+		       board_name(get_board_type_config()));
+
+	reg = readl(CREG_AXI_M_HS_CORE_BOOT) & CREG_CORE_BOOT_IMAGE;
+	printf("U-boot autostart: %s\n", reg ? "enabled" : "disabled");
+
+	return 0;
+};
diff --git a/roms/u-boot/board/synopsys/iot_devkit/Kconfig b/roms/u-boot/board/synopsys/iot_devkit/Kconfig
new file mode 100644
index 000000000..ad956b20f
--- /dev/null
+++ b/roms/u-boot/board/synopsys/iot_devkit/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IOT_DEVKIT
+
+config SYS_BOARD
+	default "iot_devkit"
+
+config SYS_VENDOR
+	default "synopsys"
+
+config SYS_CONFIG_NAME
+	default "iot_devkit"
+
+endif
diff --git a/roms/u-boot/board/synopsys/iot_devkit/MAINTAINERS b/roms/u-boot/board/synopsys/iot_devkit/MAINTAINERS
new file mode 100644
index 000000000..06457cfa6
--- /dev/null
+++ b/roms/u-boot/board/synopsys/iot_devkit/MAINTAINERS
@@ -0,0 +1,5 @@
+IOT DEVKIT BOARD
+M:	Alexey Brodkin <abrodkin@synopsys.com>
+S:	Maintained
+F:	board/synopsys/iot_devkit/
+F:	configs/iot_devkit_defconfig
diff --git a/roms/u-boot/board/synopsys/iot_devkit/Makefile b/roms/u-boot/board/synopsys/iot_devkit/Makefile
new file mode 100644
index 000000000..161602464
--- /dev/null
+++ b/roms/u-boot/board/synopsys/iot_devkit/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= iot_devkit.o
diff --git a/roms/u-boot/board/synopsys/iot_devkit/README b/roms/u-boot/board/synopsys/iot_devkit/README
new file mode 100644
index 000000000..20c140d93
--- /dev/null
+++ b/roms/u-boot/board/synopsys/iot_devkit/README
@@ -0,0 +1,145 @@
+================================================================================
+Useful notes on bulding and using of U-Boot on
+ARC IoT Development Kit (AKA IoTDK)
+================================================================================
+
+   BOARD OVERVIEW
+
+   The DesignWare ARC IoT Development Kit is a versatile platform that includes
+   the necessary hardware and software to accelerate software development and
+   debugging of sensor fusion, voice recognition and face detection designs.
+
+   The ARC IoT Development Kit includes a silicon implementation of the
+   ARC Data Fusion IP Subsystem running at 144 MHz on SMIC's
+   55-nm ultra-low power process, and a rich set of peripherals commonly used
+   in IoT designs such as USB, UART, SPI, I2C, PWM, SDIO and ADCs.
+
+   The board is shipped with pre-installed U-Boot in non-volatile memory
+   (eFlash) so on power-on user sees U-Boot start header and command line
+   prompt which might be used for U-Boot environment fine-tuning, manual
+   loading and execution of user application binaries etc.
+
+   The board has the following features useful for U-Boot:
+    * On-board 2-channel FTDI TTL-to-USB converter
+      - The first channel is used for serial debug port (which makes it possible
+        to use a serial connection on pretty much any host machine be it
+        Windows, Linux or Mac).
+        On Linux machine typucally FTDI serial port would be /dev/ttyUSB0.
+        There's no HW flow-control and baud-rate is 115200.
+
+      - The second channel is used for built-in Digilent USB JTAG probe.
+        That means no extra hardware is required to access ARC core from a
+        debugger on development host. Both proprietary MetaWare debugger and
+        open source OpenOCD + GDB client are supported.
+
+      - Also with help of this FTDI chip it is possible to reset entire
+        board with help of a special `rff-ftdi-reset` utility, see:
+        https://github.com/foss-for-synopsys-dwc-arc-processors/rff-ftdi-reset
+
+    * Micro SD-card slot
+      - U-Boot expects to see the very first partition on the card formatted as
+        FAT file-system and uses it for keeping its environment in `uboot.env`
+        file. Note uboot.env is not just a text file but it is auto-generated
+        file created by U-Boot on invocation of `saveenv` command.
+        It contains a checksum which makes this saved environment invalid in
+        case of maual modification.
+
+      - There might be more useful files on that first FAT partition like
+        user applications, data files etc.
+
+    * USB OTG connector
+      - U-Boot may access USB mass-storage devices attached to this connector.
+        Note only FAT file-system is supported. It might be used for storing
+        user application binaries as well as micro SD-card mentioned above.
+
+    * The following memories are avaialble on the board:
+      - eFlash:	256 KiB @ 0x0000_0000
+        A non-volatile memory from which ARC core may execute code directly.
+        Still is is not direcly writable, thus this is not an ordinary RAM.
+
+      - ICCM:	256 KiB @ 0x2000_0000
+        Instruction Closely Coupled Memory - fast on-chip memory primary used
+        for code being executed, still data could be placed in this memory too.
+        In that sense it's just a general purpose RAM.
+
+      - SRAM:	128 KiB @ 0x3000_0000
+        On-chip SRAM. From user perspective is the same as ICCM above.
+
+      - DCCM:	128 KiB @ 0x8000_0000
+        Data Closely Coupled Memory is similar to ICCM with a major difference -
+        ARC core cannot execute code from DCCM. So this is very special RAM
+        only suitable for data.
+
+   BUILDING U-BOOT
+
+   1. Configure U-Boot:
+      ------------------------->8----------------------
+      make iot_devkit_defconfig
+      ------------------------->8----------------------
+
+   2. To build Elf file (for example to be used with host debugger via JTAG
+      connection to the target board):
+      ------------------------->8----------------------
+      make mdbtrick
+      ------------------------->8----------------------
+
+      This will produce `u-boot` Elf file.
+
+   3. To build binary image to be put in "ROM":
+      ------------------------->8----------------------
+      make u-boot.bin
+      ------------------------->8----------------------
+
+
+   EXECUTING U-BOOT
+
+   1. The IoTDK board is supposed to auto-start U-Boot image stored in eFlash on
+      power-on. Note it's possible to update that image - follow instructions in
+      user's manual.
+
+   2. Though it is possible to load and start U-Boot as a simple Elf file
+      via JTAG right in ICCM. For that it's required to re-configure U-Boot
+      so it gets linked to ICCM address 0x2000_0000 (remember eFlash is not
+      direcly writable).
+      Run U-Boot's configuration utility with "make menuconfig", go to
+      "Boot images" and change "Text Base" from default 0x00000000 to
+      0x20000000. Exit & save new configuration. Now run "make mdbtrick" to
+      build new Elf.
+
+      2.1. In case of proprietary MetaWare debugger run:
+      ------------------------->8----------------------
+      mdb -digilent u-boot
+      ------------------------->8----------------------
+
+   USING U-BOOT
+
+   Note due to limited memory size it's supposed that user will run binary
+   images of their applications instead of loading Elf files.
+
+   1. To load and start application binary from micro SD-card execute
+      the following commands in U-Boot's shell:
+      ------------------------->8----------------------
+      fatload mmc 0 0x20000000 yourapp.bin
+      go 0x20000000
+      ------------------------->8----------------------
+
+   2. To load and start application binary from USB mass-storage device execute
+      the following commands in U-Boot's shell:
+      ------------------------->8----------------------
+      usb start
+      fatload usb 0x20000000 yourapp.bin
+      go 0x20000000
+      ------------------------->8----------------------
+
+   3. To have a sequence of commands executed on U-Boot start put those
+      commands in "bootcmd" with semicolon between them.
+      For example to get (1) done automatically:
+      ------------------------->8----------------------
+      setenv bootcmd fatload mmc 0 0x20000000 yourapp.bin\; go 0x20000000
+      saveenv
+      ------------------------->8----------------------
+
+   4. To reboot the board just run:
+      ------------------------->8----------------------
+      reset
+      ------------------------->8----------------------
diff --git a/roms/u-boot/board/synopsys/iot_devkit/config.mk b/roms/u-boot/board/synopsys/iot_devkit/config.mk
new file mode 100644
index 000000000..bd8f09ec7
--- /dev/null
+++ b/roms/u-boot/board/synopsys/iot_devkit/config.mk
@@ -0,0 +1,3 @@
+PLATFORM_CPPFLAGS += -mcpu=arcem -mlittle-endian -mcode-density -mdiv-rem \
+                     -mswap -mnorm -mmpy-option=6 -mbarrel-shifter
+LDSCRIPT = $(srctree)/board/synopsys/iot_devkit/u-boot.lds
diff --git a/roms/u-boot/board/synopsys/iot_devkit/iot_devkit.c b/roms/u-boot/board/synopsys/iot_devkit/iot_devkit.c
new file mode 100644
index 000000000..650958f94
--- /dev/null
+++ b/roms/u-boot/board/synopsys/iot_devkit/iot_devkit.c
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <malloc.h>
+#include <dwmmc.h>
+#include <asm/global_data.h>
+#include <linux/bitops.h>
+#include <linux/libfdt.h>
+#include <fdtdec.h>
+
+#include <asm/arcregs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SYSCON_BASE	0xf000a000
+#define AHBCKDIV	(void *)(SYSCON_BASE + 0x04)
+#define APBCKDIV	(void *)(SYSCON_BASE + 0x08)
+#define APBCKEN		(void *)(SYSCON_BASE + 0x0C)
+#define RESET_REG	(void *)(SYSCON_BASE + 0x18)
+#define CLKSEL		(void *)(SYSCON_BASE + 0x24)
+#define CLKSTAT		(void *)(SYSCON_BASE + 0x28)
+#define PLLCON		(void *)(SYSCON_BASE + 0x2C)
+#define APBCKSEL	(void *)(SYSCON_BASE + 0x30)
+#define AHBCKEN		(void *)(SYSCON_BASE + 0x34)
+#define USBPHY_PLL	(void *)(SYSCON_BASE + 0x78)
+#define USBCFG		(void *)(SYSCON_BASE + 0x7c)
+
+#define PLL_MASK_0	0xffcfffff
+#define PLL_MASK_1	0xffcfff00
+#define PLL_MASK_2	0xfbcfff00
+
+#define CLKSEL_DEFAULT	0x5a690000
+
+static int set_cpu_freq(unsigned int clk)
+{
+	clk /= 1000000;
+
+	/* Set clk to ext Xtal (LSN value 0) */
+	writel(CLKSEL_DEFAULT, CLKSEL);
+
+	switch (clk) {
+	case 16:
+		/* Bypass mode */
+		return 0;
+
+	case 50:
+		writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
+		/* pll_off=1, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
+		writel((readl(PLLCON) & PLL_MASK_1) | 0x300191, PLLCON);
+		/* pll_off=0, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
+		writel((readl(PLLCON) & PLL_MASK_2) | 0x300191, PLLCON);
+		break;
+
+	case 72:
+		writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
+		/* pll_off=1, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
+		writel((readl(PLLCON) & PLL_MASK_1) | 0x200121, PLLCON);
+		/* pll_off=0, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
+		writel((readl(PLLCON) & PLL_MASK_2) | 0x200121, PLLCON);
+		break;
+
+	case 100:
+		writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
+		/* pll_off=1,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
+		writel((readl(PLLCON) & PLL_MASK_1) | 0x200191, PLLCON);
+		/* pll_off=0,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
+		writel((readl(PLLCON) & PLL_MASK_2) | 0x200191, PLLCON);
+		break;
+
+	case 136:
+		writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
+		/* pll_off=1, M=17, N=1, OD=1, PLL_OUT_CLK=136M */
+		writel((readl(PLLCON) & PLL_MASK_1) | 0x100111, PLLCON);
+		/* pll_off=0, M=17, N=1, OD=1, PLL_OUT_CLK=136M */
+		writel((readl(PLLCON) & PLL_MASK_2) | 0x100111, PLLCON);
+		break;
+
+	case 144:
+		writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
+		/* pll_off=1, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
+		writel((readl(PLLCON) & PLL_MASK_1) | 0x100121, PLLCON);
+		/* pll_off=0, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
+		writel((readl(PLLCON) & PLL_MASK_2) | 0x100121, PLLCON);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	while (!(readl(CLKSTAT) & 0x4))
+		;
+
+	/* Set clk from PLL on bus (LSN = 1) */
+	writel(CLKSEL_DEFAULT | BIT(0), CLKSEL);
+
+	return 0;
+}
+
+extern u8 __rom_end[];
+extern u8 __ram_start[];
+extern u8 __ram_end[];
+
+/*
+ * Use mach_cpu_init() for .data section copy as board_early_init_f() will be
+ * too late: initf_dm() will use a value of "av_" variable from not yet
+ * initialized (by copy) area.
+ */
+int mach_cpu_init(void)
+{
+	int offset;
+
+	/* Don't relocate U-Boot */
+	gd->flags |= GD_FLG_SKIP_RELOC;
+
+	/* Copy data from ROM to RAM */
+	u8 *src = __rom_end;
+	u8 *dst = __ram_start;
+
+	while (dst < __ram_end)
+		*dst++ = *src++;
+
+	/* Enable debug uart */
+#define DEBUG_UART_BASE		0x80014000
+#define DEBUG_UART_DLF_OFFSET	0xc0
+	write_aux_reg(DEBUG_UART_BASE + DEBUG_UART_DLF_OFFSET, 1);
+
+	offset = fdt_path_offset(gd->fdt_blob, "/cpu_card/core_clk");
+	if (offset < 0)
+		return offset;
+
+	gd->cpu_clk = fdtdec_get_int(gd->fdt_blob, offset, "clock-frequency", 0);
+	if (!gd->cpu_clk)
+		return -EINVAL;
+
+	/* If CPU freq > 100 MHz, divide eFLASH clock by 2 */
+	if (gd->cpu_clk > 100000000) {
+		u32 reg = readl(AHBCKDIV);
+
+		reg &= ~(0xF << 8);
+		reg |= 2 << 8;
+		writel(reg, AHBCKDIV);
+	}
+
+	return set_cpu_freq(gd->cpu_clk);
+}
+
+#define IOTDK_RESET_SEQ		0x55AA6699
+
+void reset_cpu(void)
+{
+	writel(IOTDK_RESET_SEQ, RESET_REG);
+}
+
+int checkboard(void)
+{
+	puts("Board: Synopsys IoT Development Kit\n");
+	return 0;
+};
diff --git a/roms/u-boot/board/synopsys/iot_devkit/u-boot.lds b/roms/u-boot/board/synopsys/iot_devkit/u-boot.lds
new file mode 100644
index 000000000..d08316870
--- /dev/null
+++ b/roms/u-boot/board/synopsys/iot_devkit/u-boot.lds
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+MEMORY {
+	ROM : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
+	RAM : ORIGIN = RAM_DATA_BASE, LENGTH = RAM_DATA_SIZE
+}
+
+OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
+OUTPUT_ARCH(arc)
+ENTRY(_start)
+SECTIONS
+{
+	. = CONFIG_SYS_MONITOR_BASE;
+	__image_copy_start = .;
+	.ivt :
+	{
+		__ivt_start = .;
+		KEEP(*(.ivt));
+		__ivt_end = .;
+	} > ROM
+
+	. = ALIGN(1024);
+	.text :	{
+		__text_start = .;
+		arch/arc/lib/start.o (.text*)
+		*(.text*)
+		__text_end = .;
+	} > ROM
+
+	. = ALIGN(4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} > ROM
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+
+		/* Mark RAM's LMA */
+		. = ALIGN(4);
+		__rom_end = .;
+	} > ROM
+
+	.data : {
+		/* Mark RAM's VMA */
+		. = ALIGN(4);
+
+		/*
+		 * Everything between __ram_start and __ram_start will be
+		 * copied from ROM to RAM in board_early_init_f().
+		 */
+		__ram_start = .;
+
+		*(.data*)
+
+		__ram_end = .;
+	} > RAM AT > ROM
+
+	.bss : {
+		. = ALIGN(1024);
+		__bss_start = .;
+		*(.bss*)
+		__bss_end = .;
+	} > RAM
+
+	/* Keep relocation-related symbols to make linker happy */
+	__rel_dyn_start = .;
+	__rel_dyn_end = .;
+	__image_copy_end = .;
+	__init_end = .;
+}
diff --git a/roms/u-boot/board/synopsys/nsim/Kconfig b/roms/u-boot/board/synopsys/nsim/Kconfig
new file mode 100644
index 000000000..b6966b299
--- /dev/null
+++ b/roms/u-boot/board/synopsys/nsim/Kconfig
@@ -0,0 +1,21 @@
+if TARGET_NSIM
+
+config SYS_BOARD
+	default "nsim"
+
+config SYS_VENDOR
+	default "synopsys"
+
+config SYS_CONFIG_NAME
+	default "nsim"
+
+config NSIM_BOARD_CPPFLAGS
+	string "board arc-specific compiler options"
+	help
+	  For nSIM we allow to set custom arc-specific compiler options
+	  (like -mcpu=) instead of hardcoding them in its makefile as nSIM
+	  target is used for representing targets without fixed CPU version
+	  like FPGA-based boards and software simulators.
+	  This variable takes space separated compiler options list.
+
+endif
diff --git a/roms/u-boot/board/synopsys/nsim/MAINTAINERS b/roms/u-boot/board/synopsys/nsim/MAINTAINERS
new file mode 100644
index 000000000..ad23c8338
--- /dev/null
+++ b/roms/u-boot/board/synopsys/nsim/MAINTAINERS
@@ -0,0 +1,6 @@
+ARC SIMULATION & PROTOTYPING PLATFORMS
+M:	Alexey Brodkin <abrodkin@synopsys.com>
+S:	Maintained
+F:	arch/arc/dts/nsim.dts
+F:	board/synopsys/nsim/
+F:	configs/nsim_*_defconfig
diff --git a/roms/u-boot/board/synopsys/nsim/Makefile b/roms/u-boot/board/synopsys/nsim/Makefile
new file mode 100644
index 000000000..6aaffffa7
--- /dev/null
+++ b/roms/u-boot/board/synopsys/nsim/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2020 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= nsim.o
diff --git a/roms/u-boot/board/synopsys/nsim/config.mk b/roms/u-boot/board/synopsys/nsim/config.mk
new file mode 100644
index 000000000..40f9578a2
--- /dev/null
+++ b/roms/u-boot/board/synopsys/nsim/config.mk
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Synopsys, Inc. All rights reserved.
+
+# CONFIG_NSIM_BOARD_CPPFLAGS is a string variable which comes from defconfig
+# with double quotes. We use echo to remove them so CONFIG_NSIM_BOARD_CPPFLAGS
+# won't be treated by compiler as a single option.
+PLATFORM_CPPFLAGS += $(shell echo $(CONFIG_NSIM_BOARD_CPPFLAGS))
diff --git a/roms/u-boot/board/synopsys/nsim/nsim.c b/roms/u-boot/board/synopsys/nsim/nsim.c
new file mode 100644
index 000000000..00e5cc364
--- /dev/null
+++ b/roms/u-boot/board/synopsys/nsim/nsim.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <dm/device.h>
+#include <virtio_types.h>
+#include <virtio.h>
+
+int board_early_init_r(void)
+{
+	/*
+	 * Make sure virtio bus is enumerated so that peripherals
+	 * on the virtio bus can be discovered by their drivers
+	 */
+	virtio_init();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: ARC virtual or prototyping platform\n");
+	return 0;
+};
diff --git a/roms/u-boot/board/sysam/amcore/Kconfig b/roms/u-boot/board/sysam/amcore/Kconfig
new file mode 100644
index 000000000..dd9816ec2
--- /dev/null
+++ b/roms/u-boot/board/sysam/amcore/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_AMCORE
+
+config SYS_CPU
+        string
+        default "mcf530x"
+
+config SYS_BOARD
+        string
+        default "amcore"
+
+config SYS_VENDOR
+        string
+        default "sysam"
+
+config SYS_CONFIG_NAME
+        string
+        default "amcore"
+
+endif
+
+
+
diff --git a/roms/u-boot/board/sysam/amcore/MAINTAINERS b/roms/u-boot/board/sysam/amcore/MAINTAINERS
new file mode 100644
index 000000000..fe5dd9bf3
--- /dev/null
+++ b/roms/u-boot/board/sysam/amcore/MAINTAINERS
@@ -0,0 +1,6 @@
+AMCORE BOARD
+M:	Angelo Dureghello <angelo@sysam.it>
+S:	Maintained
+F:	board/sysam/amcore/
+F:	include/configs/amcore.h
+F:      configs/amcore_defconfig
diff --git a/roms/u-boot/board/sysam/amcore/Makefile b/roms/u-boot/board/sysam/amcore/Makefile
new file mode 100644
index 000000000..051186f0d
--- /dev/null
+++ b/roms/u-boot/board/sysam/amcore/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	= amcore.o
diff --git a/roms/u-boot/board/sysam/amcore/amcore.c b/roms/u-boot/board/sysam/amcore/amcore.c
new file mode 100644
index 000000000..beab4e9d1
--- /dev/null
+++ b/roms/u-boot/board/sysam/amcore/amcore.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for Sysam AMCORE (MCF5307 based) board
+ *
+ * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
+ *
+ * This file copies memory testdram() from sandburst/common/sb_common.c
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/platform_data/serial_coldfire.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void init_lcd(void)
+{
+	/* setup for possible K0108 lcd connected on the parallel port */
+	sim_t *sim = (sim_t *)(MMAP_SIM);
+
+	out_be16(&sim->par, 0x300);
+
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+
+	out_be16(&gpio->paddr, 0xfcff);
+	out_be16(&gpio->padat, 0x0c00);
+}
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("AMCORE v.001(alpha)\n");
+
+	init_lcd();
+
+	return 0;
+}
+
+/*
+ * in dram_init we are here executing from flash
+ * case 1:
+ * is with no ACR/flash cache enabled
+ * nop = 40ns (scope measured)
+ */
+void fudelay(int usec)
+{
+	while (usec--)
+		asm volatile ("nop");
+}
+
+int dram_init(void)
+{
+	u32 dramsize, RC;
+
+	sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
+
+	/*
+	 * SDRAM  MT48LC4M32B2 details
+	 * Memory block 0: 16 MB of SDRAM at address $00000000
+	 * Port size: 32-bit port
+	 *
+	 * Memory block 0 wired as follows:
+	 * CPU   : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
+	 * SDRAM :  A0  A1  A2  A3  A4  A5  A6 A7  A8  A9 A10 A11 BA0 BA1
+	 *
+	 * Ensure that there is a delay of at least 100 microseconds from
+	 * processor reset to the following code so that the SDRAM is ready
+	 * for commands.
+	 */
+	fudelay(100);
+
+	/*
+	 * DCR
+	 * set proper  RC as per specification
+	 */
+	RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
+	RC = (RC * 15) >> 4;
+
+	/* 0x8000 is the faster option */
+	out_be16(&dc->dcr, 0x8200 | RC);
+
+	/*
+	 * DACR0, page mode continuous, CMD on A20 0x0300
+	 */
+	out_be32(&dc->dacr0, 0x00003304);
+
+	dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
+	out_be32(&dc->dmr0,  dramsize|1);
+
+	/* issue a PRECHARGE ALL */
+	out_be32(&dc->dacr0, 0x0000330c);
+	out_be32((u32 *)0x00000004, 0xbeaddeed);
+	/* issue AUTOREFRESH */
+	out_be32(&dc->dacr0, 0x0000b304);
+	/* let refresh occur */
+	fudelay(1);
+
+	out_be32(&dc->dacr0, 0x0000b344);
+	out_be32((u32 *)0x00000c00, 0xbeaddeed);
+
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static struct coldfire_serial_plat mcf5307_serial_plat = {
+	.base = CONFIG_SYS_UART_BASE,
+	.port = 0,
+	.baudrate = CONFIG_BAUDRATE,
+};
+
+U_BOOT_DRVINFO(coldfire_serial) = {
+	.name = "serial_coldfire",
+	.plat = &mcf5307_serial_plat,
+};
diff --git a/roms/u-boot/board/sysam/stmark2/Kconfig b/roms/u-boot/board/sysam/stmark2/Kconfig
new file mode 100644
index 000000000..87ab7ab7b
--- /dev/null
+++ b/roms/u-boot/board/sysam/stmark2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_STMARK2
+
+config SYS_CPU
+	default "mcf5445x"
+
+config SYS_BOARD
+	default "stmark2"
+
+config SYS_VENDOR
+	default "sysam"
+
+config SYS_CONFIG_NAME
+	default "stmark2"
+
+endif
diff --git a/roms/u-boot/board/sysam/stmark2/MAINTAINERS b/roms/u-boot/board/sysam/stmark2/MAINTAINERS
new file mode 100644
index 000000000..b87f432bb
--- /dev/null
+++ b/roms/u-boot/board/sysam/stmark2/MAINTAINERS
@@ -0,0 +1,6 @@
+STMARK2 BOARD
+M:	Angelo Dureghello <angelo@sysam.it>
+S:	Maintained
+F:	board/sysam/stmark2/
+F:	include/configs/stmark2.h
+F:	configs/stmark2_defconfig
diff --git a/roms/u-boot/board/sysam/stmark2/Makefile b/roms/u-boot/board/sysam/stmark2/Makefile
new file mode 100644
index 000000000..064a57ea0
--- /dev/null
+++ b/roms/u-boot/board/sysam/stmark2/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y = stmark2.o
+extra-y += sbf_dram_init.o
diff --git a/roms/u-boot/board/sysam/stmark2/sbf_dram_init.S b/roms/u-boot/board/sysam/stmark2/sbf_dram_init.S
new file mode 100644
index 000000000..984b31b9d
--- /dev/null
+++ b/roms/u-boot/board/sysam/stmark2/sbf_dram_init.S
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board-specific early ddr/sdram init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ */
+
+.equ	PPMCR0, 	0xfc04002d
+.equ	MSCR_SDRAMC,	0xec094060
+.equ	MISCCR2,	0xec09001a
+.equ	DDR_RCR,	0xfc0b8180
+.equ	DDR_PADCR,	0xfc0b81ac
+.equ	DDR_CR00,	0xfc0b8000
+.equ	DDR_CR06,	0xfc0b8018
+.equ	DDR_CR09,	0xfc0b8024
+.equ	DDR_CR40,	0xfc0b80a0
+.equ	DDR_CR45,	0xfc0b80b4
+.equ	DDR_CR56,	0xfc0b80e0
+
+.global sbf_dram_init
+.text
+
+sbf_dram_init:
+	/* CD46 = DDR on */
+	move.l	#PPMCR0, %a1
+	move.b	#46, (%a1)
+
+	/* stmark 2, max drive strength */
+	move.l	#MSCR_SDRAMC, %a1
+	move.b	#1, (%a1)
+
+	/*
+	 * use cpu clock, seems more realiable
+	 *
+	 * DDR2 clock is serviced from DDR controller as input clock / 2
+	 * so, if clock comes from
+	 *   vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
+	 *   cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
+	 *
+	 *     .
+	 *    / \    DDR2 can't be clocked lower than 125Mhz
+	 *   / ! \   DDR2 init must pass further i/dcache enable test
+	 *  /_____\
+	 *  WARNING
+	 */
+
+	/* cpu / 2 = 125 Mhz for 480 Mhz pll */
+	move.l	#MISCCR2, %a1
+	move.w	#0xa01d, (%a1)
+
+	/* DDR force sw reset settings */
+	move.l	#DDR_RCR, %a1
+	move.l	#0x00000000, (%a1)
+	move.l	#0x40000000, (%a1)
+
+	/*
+	 * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good,
+	 * 500/700 mV are ok
+	 */
+	move.l	#DDR_PADCR, %a1
+	move.l	#0x01030203, (%a1)	/* as freescale tower */
+
+	move.l	#DDR_CR00, %a1
+	move.l	#0x01010101, (%a1)+	/* 0x00 */
+	move.l	#0x00000101, (%a1)+	/* 0x04 */
+	move.l	#0x01010100, (%a1)+	/* 0x08 */
+	move.l	#0x01010000, (%a1)+	/* 0x0C */
+	move.l	#0x00010101, (%a1)+	/* 0x10 */
+	move.l	#DDR_CR06, %a1
+	move.l	#0x00010100, (%a1)+	/* 0x18 */
+	move.l	#0x00000001, (%a1)+	/* 0x1C */
+	move.l	#0x01000001, (%a1)+	/* 0x20 */
+	move.l	#0x00000100, (%a1)+	/* 0x24 */
+	move.l	#0x00010001, (%a1)+	/* 0x28 */
+	move.l	#0x00000200, (%a1)+	/* 0x2C */
+	move.l	#0x01000002, (%a1)+	/* 0x30 */
+	move.l	#0x00000000, (%a1)+	/* 0x34 */
+	move.l	#0x00000100, (%a1)+	/* 0x38 */
+	move.l	#0x02000100, (%a1)+	/* 0x3C */
+	move.l	#0x02000407, (%a1)+	/* 0x40 */
+	move.l	#0x02030007, (%a1)+	/* 0x44 */
+	move.l	#0x02000100, (%a1)+	/* 0x48 */
+	move.l	#0x0A030203, (%a1)+	/* 0x4C */
+	move.l	#0x00020708, (%a1)+	/* 0x50 */
+	move.l	#0x00050008, (%a1)+	/* 0x54 */
+	move.l	#0x04030002, (%a1)+	/* 0x58 */
+	move.l	#0x00000004, (%a1)+	/* 0x5C */
+	move.l	#0x020A0000, (%a1)+	/* 0x60 */
+	move.l	#0x0C00000E, (%a1)+	/* 0x64 */
+	move.l	#0x00002004, (%a1)+	/* 0x68 */
+	move.l	#0x00000000, (%a1)+	/* 0x6C */
+	move.l	#0x00100010, (%a1)+	/* 0x70 */
+	move.l	#0x00100010, (%a1)+	/* 0x74 */
+	move.l	#0x00000000, (%a1)+	/* 0x78 */
+	move.l	#0x07990000, (%a1)+	/* 0x7C */
+	move.l	#DDR_CR40, %a1
+	move.l	#0x00000000, (%a1)+	/* 0xA0 */
+	move.l	#0x00C80064, (%a1)+	/* 0xA4 */
+	move.l	#0x44520002, (%a1)+	/* 0xA8 */
+	move.l	#0x00C80023, (%a1)+	/* 0xAC */
+	move.l	#DDR_CR45, %a1
+	move.l	#0x0000C350, (%a1)	/* 0xB4 */
+	move.l	#DDR_CR56, %a1
+	move.l	#0x04000000, (%a1)+	/* 0xE0 */
+	move.l	#0x03000304, (%a1)+	/* 0xE4 */
+	move.l	#0x40040000, (%a1)+	/* 0xE8 */
+	move.l	#0xC0004004, (%a1)+	/* 0xEC */
+	move.l	#0x0642C000, (%a1)+	/* 0xF0 */
+	move.l	#0x00000642, (%a1)+	/* 0xF4 */
+	move.l	#DDR_CR09, %a1
+	tpf
+	move.l	#0x01000100, (%a1)	/* 0x24 */
+
+	move.l	#0x2000, %d1
+	bsr	asm_delay
+
+
+	rts
diff --git a/roms/u-boot/board/sysam/stmark2/stmark2.c b/roms/u-boot/board/sysam/stmark2/stmark2.c
new file mode 100644
index 000000000..d48da48b6
--- /dev/null
+++ b/roms/u-boot/board/sysam/stmark2/stmark2.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board-specific init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spi.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	/*
+	 * need to to:
+	 * Check serial flash size. if 2mb evb, else 8mb demo
+	 */
+	puts("Board: ");
+	puts("Sysam stmark2\n");
+	return 0;
+}
+
+int dram_init(void)
+{
+	u32 dramsize;
+
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	gd->ram_size = dramsize;
+
+	return 0;
+}
+
+int testdram(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/board/syteco/zmx25/Kconfig b/roms/u-boot/board/syteco/zmx25/Kconfig
new file mode 100644
index 000000000..59a415d65
--- /dev/null
+++ b/roms/u-boot/board/syteco/zmx25/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ZMX25
+
+config SYS_BOARD
+	default "zmx25"
+
+config SYS_VENDOR
+	default "syteco"
+
+config SYS_SOC
+	default "mx25"
+
+config SYS_CONFIG_NAME
+	default "zmx25"
+
+endif
diff --git a/roms/u-boot/board/syteco/zmx25/MAINTAINERS b/roms/u-boot/board/syteco/zmx25/MAINTAINERS
new file mode 100644
index 000000000..90f9fab7b
--- /dev/null
+++ b/roms/u-boot/board/syteco/zmx25/MAINTAINERS
@@ -0,0 +1,6 @@
+ZMX25 BOARD
+M:	Matthias Weisser <weisserm@arcor.de>
+S:	Maintained
+F:	board/syteco/zmx25/
+F:	include/configs/zmx25.h
+F:	configs/zmx25_defconfig
diff --git a/roms/u-boot/board/syteco/zmx25/Makefile b/roms/u-boot/board/syteco/zmx25/Makefile
new file mode 100644
index 000000000..49b3a8f18
--- /dev/null
+++ b/roms/u-boot/board/syteco/zmx25/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (c) 2010 Graf-Syteco, Matthias Weisser
+# <weisserm@arcor.de>
+
+obj-y	+= zmx25.o
+obj-y	+= lowlevel_init.o
diff --git a/roms/u-boot/board/syteco/zmx25/lowlevel_init.S b/roms/u-boot/board/syteco/zmx25/lowlevel_init.S
new file mode 100644
index 000000000..7df939884
--- /dev/null
+++ b/roms/u-boot/board/syteco/zmx25/lowlevel_init.S
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on U-Boot and RedBoot sources for several different i.mx
+ * platforms.
+ */
+
+#include <asm/macro.h>
+#include <asm/arch/macro.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * clocks
+ */
+.macro init_clocks
+
+	/* disable clock output */
+	write32	IMX_CCM_BASE + CCM_MCR, 0x00000000
+	write32	IMX_CCM_BASE + CCM_CCTL, 0x50030000
+
+	/*
+	 * enable all implemented clocks in all three
+	 * clock control registers
+	 */
+	write32	IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
+	write32	IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
+	write32	IMX_CCM_BASE + CCM_CGCR2, 0xfffff
+
+	/* Devide NAND clock by 32 */
+	write32	IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
+.endm
+
+/*
+ * sdram controller init
+ */
+.macro init_lpddr
+	ldr	r0, =IMX_ESDRAMC_BASE
+	ldr	r2, =IMX_SDRAM_BANK0_BASE
+
+	/*
+	 * reset SDRAM controller
+	 * then wait for initialization to complete
+	 */
+	ldr	r1, =(1 << 1) | (1 << 2)
+	str	r1, [r0, #ESDRAMC_ESDMISC]
+1:	ldr	r3, [r0, #ESDRAMC_ESDMISC]
+	tst	r3, #(1 << 31)
+	beq	1b
+	ldr	r1, =(1 << 2)
+	str	r1, [r0, #ESDRAMC_ESDMISC]
+
+	ldr	r1, =0x002a7420
+	str	r1, [r0, #ESDRAMC_ESDCFG0]
+
+	/* control | precharge */
+	ldr	r1, =0x92216008
+	str	r1, [r0, #ESDRAMC_ESDCTL0]
+	/* dram command encoded in address */
+	str	r1, [r2, #0x400]
+
+	/* auto refresh */
+	ldr	r1, =0xa2216008
+	str	r1, [r0, #ESDRAMC_ESDCTL0]
+	/* read dram twice to auto refresh */
+	ldr	    r3, [r2]
+	ldr     r3, [r2]
+
+	/* control | load mode */
+	ldr	r1, =0xb2216008
+	str	r1, [r0, #ESDRAMC_ESDCTL0]
+
+	/* mode register of lpddram */
+	strb	r1, [r2, #0x33]
+
+	/* extended mode register of lpddrram */
+	ldr		r2, =0x81000000
+	strb	r1, [r2]
+
+	/* control | normal */
+	ldr	r1, =0x82216008
+	str	r1, [r0, #ESDRAMC_ESDCTL0]
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+	init_aips
+	init_max
+	init_clocks
+	init_lpddr
+	mov	pc, lr
diff --git a/roms/u-boot/board/syteco/zmx25/zmx25.c b/roms/u-boot/board/syteco/zmx25/zmx25.c
new file mode 100644
index 000000000..2d4c5cce8
--- /dev/null
+++ b/roms/u-boot/board/syteco/zmx25/zmx25.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) 2011 Graf-Syteco, Matthias Weisser
+ * <weisserm@arcor.de>
+ *
+ * Based on tx25.c:
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on imx27lite.c:
+ *   Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
+ *   Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ * And:
+ *   RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
+ */
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx25.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init()
+{
+	static const iomux_v3_cfg_t sdhc1_pads[] = {
+		NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
+	};
+
+	static const iomux_v3_cfg_t dig_out_pads[] = {
+		MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */
+		MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */
+		NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */
+		NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */
+	};
+
+	static const iomux_v3_cfg_t led_pads[] = {
+		MX25_PAD_CSI_D9__GPIO_4_21,
+		MX25_PAD_CSI_D4__GPIO_1_29,
+	};
+
+	static const iomux_v3_cfg_t can_pads[] = {
+		NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL),
+	};
+
+	static const iomux_v3_cfg_t i2c3_pads[] = {
+		MX25_PAD_CSPI1_SS1__I2C3_DAT,
+		MX25_PAD_GPIO_E__I2C3_CLK,
+	};
+
+	icache_enable();
+
+	/* Setup of core voltage selection pin to run at 1.4V */
+	imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */
+	gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
+
+	/* Setup of SD card pins*/
+	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
+
+	/* Setup of digital output for USB power and OC */
+	imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */
+	gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
+
+	imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */
+	gpio_direction_input(IMX_GPIO_NR(1, 18));
+
+	/* Setup of digital output control pins */
+	imx_iomux_v3_setup_multiple_pads(dig_out_pads,
+						ARRAY_SIZE(dig_out_pads));
+
+	/* Switch both output drivers off */
+	gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
+	gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
+
+	/* Setup of key input pin */
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0));
+	gpio_direction_input(IMX_GPIO_NR(2, 29));
+
+	/* Setup of status LED outputs */
+	imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
+
+	/* Switch both LEDs off */
+	gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
+	gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
+
+	/* Setup of CAN1 and CAN2 signals */
+	imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads));
+
+	/* Setup of I2C3 signals */
+	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
+
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	const char *e;
+
+#ifdef CONFIG_FEC_MXC
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ *	0 for no pull
+ * or:
+ *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define FEC_OUT_PAD_CTRL	0
+
+	static const iomux_v3_cfg_t fec_pads[] = {
+		MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+		MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+		MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
+		MX25_PAD_FEC_MDIO__FEC_MDIO,
+		MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
+
+		MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */
+		MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */
+	};
+
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+
+	/* assert PHY reset (low) */
+	gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
+
+	udelay(5000);
+
+	/* deassert PHY reset */
+	gpio_set_value(IMX_GPIO_NR(3, 16), 1);
+
+	udelay(5000);
+#endif
+
+	e = env_get("gs_base_board");
+	if (e != NULL) {
+		if (strcmp(e, "G283") == 0) {
+			int key = gpio_get_value(IMX_GPIO_NR(2, 29));
+
+			if (key) {
+				/* Switch on both LEDs to inidcate boot mode */
+				gpio_set_value(IMX_GPIO_NR(1, 29), 0);
+				gpio_set_value(IMX_GPIO_NR(4, 21), 0);
+
+				env_set("preboot", "run gs_slow_boot");
+			} else
+				env_set("preboot", "run gs_fast_boot");
+		}
+	}
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+				PHYS_SDRAM_SIZE);
+	return 0;
+}
diff --git a/roms/u-boot/board/tbs/tbs2910/Kconfig b/roms/u-boot/board/tbs/tbs2910/Kconfig
new file mode 100644
index 000000000..d0ff2191a
--- /dev/null
+++ b/roms/u-boot/board/tbs/tbs2910/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TBS2910
+
+config SYS_BOARD
+	default "tbs2910"
+
+config SYS_VENDOR
+	default "tbs"
+
+config SYS_CONFIG_NAME
+	default "tbs2910"
+
+config IMX_CONFIG
+	default "board/tbs/tbs2910/tbs2910.cfg"
+
+endif
diff --git a/roms/u-boot/board/tbs/tbs2910/MAINTAINERS b/roms/u-boot/board/tbs/tbs2910/MAINTAINERS
new file mode 100644
index 000000000..1e3c0d0ec
--- /dev/null
+++ b/roms/u-boot/board/tbs/tbs2910/MAINTAINERS
@@ -0,0 +1,8 @@
+TBS2910 BOARD
+M:	Soeren Moch <smoch@web.de>
+S:	Maintained
+F:	arch/arm/dts/imx6q-tbs2910.dts
+F:	board/tbs/tbs2910/
+F:	configs/tbs2910_defconfig
+F:	doc/board/tbs/
+F:	include/configs/tbs2910.h
diff --git a/roms/u-boot/board/tbs/tbs2910/Makefile b/roms/u-boot/board/tbs/tbs2910/Makefile
new file mode 100644
index 000000000..78f4a3eec
--- /dev/null
+++ b/roms/u-boot/board/tbs/tbs2910/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014 Soeren Moch <smoch@web.de>
+
+obj-y  := tbs2910.o
diff --git a/roms/u-boot/board/tbs/tbs2910/tbs2910.c b/roms/u-boot/board/tbs/tbs2910/tbs2910.c
new file mode 100644
index 000000000..faf73cc21
--- /dev/null
+++ b/roms/u-boot/board/tbs/tbs2910/tbs2910.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Soeren Moch <smoch@web.de>
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int dram_init(void)
+{
+	gd->ram_size = 2048ul * 1024 * 1024;
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+/* set environment device to boot device when booting from SD */
+int board_mmc_get_env_dev(int devno)
+{
+	return devno - 1;
+}
+
+int board_mmc_get_env_part(int devno)
+{
+	return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
+}
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+#ifdef CONFIG_VIDEO_IPUV3
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		/* 1024x768@60Hz (VESA)*/
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15384,
+		.left_margin    = 160,
+		.right_margin   = 24,
+		.upper_margin   = 29,
+		.lower_margin   = 3,
+		.hsync_len      = 136,
+		.vsync_len      = 6,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+	s32 timeout = 100000;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
+	reg = readl(&ccm->analog_pll_video);
+	reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
+	writel(reg, &ccm->analog_pll_video);
+
+	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
+	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
+	writel(reg, &ccm->analog_pll_video);
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
+	writel(reg, &ccm->analog_pll_video);
+
+	while (timeout--)
+		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+			break;
+	if (timeout < 0)
+		printf("Warning: video pll lock timeout!\n");
+
+	reg = readl(&ccm->analog_pll_video);
+	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
+	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
+	writel(reg, &ccm->analog_pll_video);
+
+	/* gate ipu1_di0_clk */
+	reg = readl(&ccm->CCGR3);
+	reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &ccm->CCGR3);
+
+	/* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
+	reg = readl(&ccm->chsccdr);
+	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
+		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
+		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
+	       (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
+	       (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &ccm->chsccdr);
+
+	/* enable ipu1_di0_clk */
+	reg = readl(&ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &ccm->CCGR3);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_VIDEO_IPUV3
+	setup_display();
+#endif
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
diff --git a/roms/u-boot/board/tbs/tbs2910/tbs2910.cfg b/roms/u-boot/board/tbs/tbs2910/tbs2910.cfg
new file mode 100644
index 000000000..3ca807b31
--- /dev/null
+++ b/roms/u-boot/board/tbs/tbs2910/tbs2910.cfg
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Soeren Moch <smoch@web.de>
+ */
+
+#define __ASSEMBLY__
+#include "asm/arch/crm_regs.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/mx6-ddr.h"
+
+/* image version 2 for imx6 */
+IMAGE_VERSION 2
+BOOT_FROM sd
+
+/* set the default clock gates to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+/* set CKO1 (used as AUDIO_MCLK) to ahb_clk_root/8 = 16.5 MHz */
+DATA 4, CCM_CCOSR, 0x000000fb
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x77177717
+DATA 4, MX6_IOMUXC_GPR7, 0x77177717
+
+
+/*
+ * DDR3/DDR3L settings
+ * use default 40 Ohm pad drive strength, no odt
+ * 4x256Mx16 DDR3L-1066 7-7-7
+ */
+
+/* disable dq pullup */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* disable dqs pullup */
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+/* set ddr input mode for dq signals */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* set ddr input mode for dqs signals */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* set pad calibration type to DDR3 */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+/* dqs write delay */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001f001f
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001f001f
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f001f
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001f001f
+/* dqs read delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+/* dqs read gating control */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43000300
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03000300
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43000300
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03000300
+/* start delay line calibration */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+/* tRFC=0x89+1,tXS=0x8e+1,tXP=3+1,tXPDLL=0xc+1,tFAW=0x17+1,tCL=0x4+3 */
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
+/* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
+/* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+/* RTW_SAME=2,WTR_DIFF=3,WTW_DIFF=3,RTW_DIFF=2,RTR_DIFF=2 */
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+/* tXPR=0x8e+1,SDE2RST=0x10-2,RST2CKE=0x23-2 */
+DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
+/* ODT timing */
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+/* read odt settings, 120 Ohm */
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
+/* cs0, 15-bit row, 10-bit column, BL 8, 64-bit bus */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
+/* interleaved bank access (row/bank/col), 5 cycles additional read delay */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+/* 2GiByte RAM at cs0 */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+/* load mode registers of external ddr chips */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+/* externel chip ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+/* configure and start refreshes, 8 refresh commands at 32 kHz */
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+/* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+/* set automatic self refresh */
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+/* controller configuration finished */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/roms/u-boot/board/tcl/sl50/Kconfig b/roms/u-boot/board/tcl/sl50/Kconfig
new file mode 100644
index 000000000..1b3f5cfc6
--- /dev/null
+++ b/roms/u-boot/board/tcl/sl50/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AM335X_SL50
+
+config SYS_BOARD
+	default "sl50"
+
+config SYS_VENDOR
+	default "tcl"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "am335x_sl50"
+
+endif
diff --git a/roms/u-boot/board/tcl/sl50/MAINTAINERS b/roms/u-boot/board/tcl/sl50/MAINTAINERS
new file mode 100644
index 000000000..29f1e3d05
--- /dev/null
+++ b/roms/u-boot/board/tcl/sl50/MAINTAINERS
@@ -0,0 +1,6 @@
+SL50 BOARD
+M:	Enric Balletbo i Serra <enric.balletbo@collabora.com>
+S:	Maintained
+F:	board/tcl/sl50/
+F:	include/configs/am335x_sl50.h
+F:	configs/am335x_sl50_defconfig
diff --git a/roms/u-boot/board/tcl/sl50/Makefile b/roms/u-boot/board/tcl/sl50/Makefile
new file mode 100644
index 000000000..c2977d777
--- /dev/null
+++ b/roms/u-boot/board/tcl/sl50/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/roms/u-boot/board/tcl/sl50/board.c b/roms/u-boot/board/tcl/sl50/board.c
new file mode 100644
index 000000000..4821925c0
--- /dev/null
+++ b/roms/u-boot/board/tcl/sl50/board.c
@@ -0,0 +1,389 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for TCL SL50 board
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <net.h>
+#include <serial.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65910.h>
+#include <env_internal.h>
+#include <watchdog.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+static const struct ddr_data ddr3_sl50_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_sl50_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	env_init();
+	env_load();
+	if (env_get_yesno("boot_os") != 1)
+		return 1;
+#endif
+
+	return 0;
+}
+#endif
+
+#define OSC	(V_OSCK/1000000)
+const struct dpll_params dpll_ddr_sl50 = {
+		400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	int mpu_vdd;
+
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/* BeagleBone PMIC Code */
+	int usb_cur_lim;
+
+	if (i2c_probe(TPS65217_CHIP_PM))
+		return;
+
+	/*
+	 * Increase USB current limit to 1300mA or 1800mA and set
+	 * the MPU voltage controller as needed.
+	 */
+	if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+	} else {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+	}
+
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+			       TPS65217_POWER_PATH,
+			       usb_cur_lim,
+			       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set DCDC3 (CORE) voltage to 1.125V */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+				    TPS65217_DCDC_VOLT_SEL_1125MV)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/*
+	 * Set LDO3 to 1.8V and LDO4 to 3.3V
+	 */
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS1,
+			       TPS65217_LDO_VOLTAGE_OUT_1_8,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS2,
+			       TPS65217_LDO_VOLTAGE_OUT_3_3,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+	return &dpll_ddr_sl50;
+}
+
+void set_uart_mux_conf(void)
+{
+#if CONFIG_CONS_INDEX == 1
+	enable_uart0_pin_mux();
+#elif CONFIG_CONS_INDEX == 2
+	enable_uart1_pin_mux();
+#elif CONFIG_CONS_INDEX == 3
+	enable_uart2_pin_mux();
+#elif CONFIG_CONS_INDEX == 4
+	enable_uart3_pin_mux();
+#elif CONFIG_CONS_INDEX == 5
+	enable_uart4_pin_mux();
+#elif CONFIG_CONS_INDEX == 6
+	enable_uart5_pin_mux();
+#endif
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs_evmsk = {
+	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_bonelt = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_evm15 = {
+	.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+	config_ddr(400, &ioregs_bonelt,
+		   &ddr3_sl50_data,
+		   &ddr3_sl50_cmd_ctrl_data,
+		   &ddr3_sl50_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	return 0;
+}
+#endif
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif
+
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards.  We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
+		&& defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+	 !defined(CONFIG_SPL_BUILD))
+int board_eth_init(struct bd_info *bis)
+{
+	int rv, n = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	if (!env_get("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+	}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!env_get("eth1addr")) {
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("eth1addr", mac_addr);
+	}
+
+
+	writel(MII_MODE_ENABLE, &cdev->miisel);
+	cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+				PHY_INTERFACE_MODE_MII;
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+#endif
+
+	/*
+	 *
+	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
+	 * operating points.  So we must set the TX clock delay feature
+	 * in the AR8051 PHY.  Since we only support a single ethernet
+	 * device in U-Boot, we only do this for the first instance.
+	 */
+#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
+#define AR8051_PHY_DEBUG_DATA_REG	0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
+#define AR8051_RGMII_TX_CLK_DLY		0x100
+
+#endif
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
+	if (is_valid_ether_addr(mac_addr))
+		eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
+
+	rv = usb_eth_initialize(bis);
+	if (rv < 0)
+		printf("Error %d registering USB_ETHER\n", rv);
+	else
+		n += rv;
+#endif
+	return n;
+}
+#endif
diff --git a/roms/u-boot/board/tcl/sl50/board.h b/roms/u-boot/board/tcl/sl50/board.h
new file mode 100644
index 000000000..b8b9ed7e7
--- /dev/null
+++ b/roms/u-boot/board/tcl/sl50/board.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * TCL SL50 boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/roms/u-boot/board/tcl/sl50/mux.c b/roms/u-boot/board/tcl/sl50/mux.c
new file mode 100644
index 000000000..b0a1dad3a
--- /dev/null
+++ b/roms/u-boot/board/tcl/sl50/mux.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART1_RXD */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},		/* UART1_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART2_RXD */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_CD */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+	{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)},	/* I2C_DATA */
+	{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)},	/* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+	configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+	configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c1_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(mmc1_pin_mux);
+}
diff --git a/roms/u-boot/board/technexion/pico-imx6/Kconfig b/roms/u-boot/board/technexion/pico-imx6/Kconfig
new file mode 100644
index 000000000..4af18e53b
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PICO_IMX6
+
+config SYS_BOARD
+	default "pico-imx6"
+
+config SYS_VENDOR
+	default "technexion"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "pico-imx6"
+
+endif
diff --git a/roms/u-boot/board/technexion/pico-imx6/MAINTAINERS b/roms/u-boot/board/technexion/pico-imx6/MAINTAINERS
new file mode 100644
index 000000000..dd6fb96e4
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6/MAINTAINERS
@@ -0,0 +1,9 @@
+TECHNEXION PICO-IMX6 BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	arch/arm/dts/imx6qdl-pico.dtsi
+F:	arch/arm/dts/imx6q-pico.dts
+F:	arch/arm/dts/imx6dl-pico.dts
+F:	board/technexion/pico-imx6/
+F:	include/configs/pico-imx6.h
+F:	configs/pico-imx6_defconfig
diff --git a/roms/u-boot/board/technexion/pico-imx6/Makefile b/roms/u-boot/board/technexion/pico-imx6/Makefile
new file mode 100644
index 000000000..ddb1604f1
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+
+obj-y  := pico-imx6.o spl.o
diff --git a/roms/u-boot/board/technexion/pico-imx6/README b/roms/u-boot/board/technexion/pico-imx6/README
new file mode 100644
index 000000000..f49708650
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6/README
@@ -0,0 +1,73 @@
+How to Update U-Boot on pico-imx6q/dl boards
+--------------------------------------------
+
+Required software on the host PC:
+
+- UUU: https://github.com/NXPmicro/mfgtools
+
+Build U-Boot for pico:
+
+$ make mrproper
+$ make pico-imx6_defconfig
+$ make
+
+This generates the SPL and u-boot-dtb.img binaries.
+
+1. Loading U-Boot via USB Serial Download Protocol
+
+Note: This method is convenient for development purposes.
+If the eMMC has already a U-Boot flashed then the user can
+go to step 2 below in order to update U-Boot.
+
+Put pico board in USB download mode (Refer to the following link for details:
+https://developer.technexion.com/docs/pico-evaluation-kit-boot-mode-settings )
+
+Connect a USB to serial adapter between the host PC and pico.
+
+Connect a USB cable between the OTG pico port and the host PC.
+
+Open a terminal program such as minicom.
+
+Copy SPL and u-boot-dtb.img to the uuu folder.
+
+Load the U-Boot via USB:
+
+$ sudo ./uuu -v uuu_script
+
+where uuu_script contains the following:
+
+SDP:  boot -f SPL
+SDPU: write -f u-boot-dtb.img -addr 0x10000000
+SDPU: jump -addr 0x10000000
+
+Then U-Boot starts and its messages appear in the console program.
+
+Use the default environment variables:
+
+=> env default -f -a
+=> saveenv
+
+2. Flashing U-Boot into the eMMC
+
+The  default  U-Boot   environment  expects  the  use   of  eMMC  user
+partition. To ensure we are using  the proper eMMC partition for boot,
+please run:
+
+=> mmc partconf 0 0 0 0
+
+Next, run the DFU agent so we can flash the new images using dfu-util
+tool:
+
+=> dfu 0 mmc 0
+
+Flash SPL and u-boot-dtb.img into the eMMC running the following commands on a PC:
+
+$ sudo dfu-util -D SPL -a spl
+
+$ sudo dfu-util -D u-boot-dtb.img -a u-boot
+
+Remove power from the pico board.
+
+Put pico board into normal boot mode.
+
+Power up the board and the new updated U-Boot should boot from eMMC.
diff --git a/roms/u-boot/board/technexion/pico-imx6/pico-imx6.c b/roms/u-boot/board/technexion/pico-imx6/pico-imx6.c
new file mode 100644
index 000000000..6b9c4f437
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6/pico-imx6.c
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014 O.S. Systems Software LTDA.
+ *
+ * Author: Fabio Estevam <festevam@gmail.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/mach-imx/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ETH_PHY_RESET		IMX_GPIO_NR(1, 26)
+#define LVDS0_EN		IMX_GPIO_NR(2, 8)
+#define LVDS0_BL_EN		IMX_GPIO_NR(2, 9)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+static iomux_v3_cfg_t const lvds_pads[] = {
+	/* lvds */
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+		   MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
+		   MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	/* AR8035 PHY Reset */
+        IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_enet(void)
+{
+	SETUP_IOMUX_PADS(enet_pads);
+
+	/* Reset AR8031 PHY */
+	gpio_request(ETH_PHY_RESET, "enet_phy_reset");
+	gpio_direction_output(ETH_PHY_RESET, 0);
+	udelay(500);
+	gpio_set_value(ETH_PHY_RESET, 1);
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static iomux_v3_cfg_t const ft5x06_wvga_pads[] = {
+	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
+	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
+	IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04	| MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
+	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
+	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
+	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
+	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
+	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
+	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
+	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
+	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
+	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
+	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
+	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
+	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
+	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
+	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
+	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
+	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
+	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
+	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
+	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
+	IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18),
+	IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19),
+	IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20),
+	IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21),
+	IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22),
+	IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23),
+	IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)
+				IOMUXC_BASE_ADDR;
+
+	/* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
+	u32 reg = readl(&iomux->gpr[2]);
+	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+	writel(reg, &iomux->gpr[2]);
+
+	/* Enable Backlight - use GPIO for Brightness adjustment */
+	SETUP_IOMUX_PAD(PAD_SD4_DAT1__GPIO2_IO09);
+	gpio_request(IMX_GPIO_NR(2, 9), "backlight_enable");
+	gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+
+	gpio_request(IMX_GPIO_NR(2, 8), "brightness");
+	SETUP_IOMUX_PAD(PAD_SD4_DAT0__GPIO2_IO08);
+	gpio_direction_output(IMX_GPIO_NR(2, 8), 1);
+}
+
+static void enable_ft5x06_wvga(struct display_info_t const *dev)
+{
+	SETUP_IOMUX_PADS(ft5x06_wvga_pads);
+
+	gpio_request(IMX_GPIO_NR(2, 10), "parallel_enable");
+	gpio_request(IMX_GPIO_NR(2, 11), "parallel_brightness");
+	gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
+	gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= 1,
+	.addr	= 0x38,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= NULL,
+	.enable	= enable_ft5x06_wvga,
+	.mode	= {
+		.name           = "FT5x06-WVGA",
+		.refresh        = 60,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 30303,
+		.left_margin    = 45,
+		.right_margin   = 210,
+		.upper_margin   = 22,
+		.lower_margin   = 22,
+		.hsync_len      = 1,
+		.vsync_len      = 1,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt = IPU_PIX_FMT_RGB24,
+	.detect = NULL,
+	.enable = enable_lvds,
+	.mode	= {
+		.name		= "hj070na",
+		.refresh	= 60,
+		.xres		= 1024,
+		.yres		= 600,
+		.pixclock	= 15385,
+		.left_margin	= 220,
+		.right_margin	= 40,
+		.upper_margin	= 21,
+		.lower_margin	= 7,
+		.hsync_len	= 60,
+		.vsync_len	= 10,
+		.sync		= FB_SYNC_EXT,
+		.vmode		= FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
+	SETUP_IOMUX_PADS(lvds_pads);
+	gpio_request(LVDS0_EN, "lvds0_enable");
+	gpio_request(LVDS0_BL_EN, "lvds0_bl_enable");
+	gpio_direction_output(LVDS0_EN, 1);
+	gpio_direction_output(LVDS0_BL_EN, 1);
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+		 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+		| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
+		| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+		| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+		| IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
+		| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+		| IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+		| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
+		| IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+	reg = readl(&iomux->gpr[3]);
+
+	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+		| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+		| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+		<< IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+
+	writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	setup_iomux_enet();
+
+	return cpu_eth_init(bis);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe7;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_late_init(void)
+{
+	if (is_mx6dq())
+		env_set("board_rev", "MX6Q");
+	else
+		env_set("board_rev", "MX6DL");
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: PICO-IMX6\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/technexion/pico-imx6/spl.c b/roms/u-boot/board/technexion/pico-imx6/spl.c
new file mode 100644
index 000000000..3b36bb8df
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6/spl.c
@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Technexion Ltd.
+ *
+ * Author: Richard Hu <richard.hu@technexion.com>
+ *	   Fabio Estevam <festevam@gmail.com>
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+#if defined(CONFIG_SPL_BUILD)
+#include <asm/arch/mx6-ddr.h>
+
+#define IMX6DQ_DRIVE_STRENGTH		0x30
+#define IMX6SDL_DRIVE_STRENGTH		0x28
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* Break into full U-Boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
+	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
+	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
+	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
+	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* H5T04G63AFR-PB for i.mx6Solo/DL operating DDR at 400MHz */
+static struct mx6_ddr3_cfg h5t04g63afr = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1500,
+	.trcmin = 5250,
+	.trasmin = 3750,
+};
+
+/* H5TQ2G63FFR-H9 for i.mx6Solo/DL operating DDR at 400MHz */
+static struct mx6_ddr3_cfg h5tq2g63ffr = {
+	.mem_speed = 800,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1500,
+	.trcmin = 5250,
+	.trasmin = 3750,
+};
+
+static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpwldectrl1 = 0x00000000,
+	.p1_mpwldectrl0 = 0x00000000,
+	.p1_mpwldectrl1 = 0x00000000,
+	.p0_mpdgctrl0 = 0x032C0340,
+	.p0_mpdgctrl1 = 0x03300324,
+	.p1_mpdgctrl0 = 0x032C0338,
+	.p1_mpdgctrl1 = 0x03300274,
+	.p0_mprddlctl = 0x423A383E,
+	.p1_mprddlctl = 0x3638323E,
+	.p0_mpwrdlctl = 0x363C4640,
+	.p1_mpwrdlctl = 0x4034423C,
+};
+
+/* DDR 32bit */
+static struct mx6_ddr_sysinfo mem_s = {
+	.dsize		= 1,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x001f001f,
+	.p0_mpwldectrl1 = 0x001f001f,
+	.p1_mpwldectrl0 = 0x001f001f,
+	.p1_mpwldectrl1 = 0x001f001f,
+	.p0_mpdgctrl0 = 0x420e020e,
+	.p0_mpdgctrl1 = 0x02000200,
+	.p1_mpdgctrl0 = 0x42020202,
+	.p1_mpdgctrl1 = 0x01720172,
+	.p0_mprddlctl = 0x494c4f4c,
+	.p1_mprddlctl = 0x4a4c4c49,
+	.p0_mpwrdlctl = 0x3f3f3133,
+	.p1_mpwrdlctl = 0x39373f2e,
+};
+
+static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x0040003c,
+	.p0_mpwldectrl1 = 0x0032003e,
+	.p0_mpdgctrl0 = 0x42350231,
+	.p0_mpdgctrl1 = 0x021a0218,
+	.p0_mprddlctl = 0x4b4b4e49,
+	.p0_mpwrdlctl = 0x3f3f3035,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF03000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_mx6solo()) {
+		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63ffr);
+	} else if (is_mx6dl()) {
+		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_s, &mx6dl_1g_mmdc_calib, &h5t04g63afr);
+	} else if (is_mx6dq()) {
+		mx6dq_dram_iocfg(32, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+		mx6_dram_cfg(&mem_s, &mx6q_1g_mmdc_calib, &h5t04g63afr);
+	}
+
+	udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* iomux */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC3_BASE_ADDR},
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* SOM MicroSD Card Detect */
+	IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	SETUP_IOMUX_PADS(usdhc3_pads);
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_mx6dq() && !strcmp(name, "imx6q-pico"))
+		return 0;
+	else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-pico"))
+		return 0;
+
+	return -EINVAL;
+}
+#endif
diff --git a/roms/u-boot/board/technexion/pico-imx6ul/Kconfig b/roms/u-boot/board/technexion/pico-imx6ul/Kconfig
new file mode 100644
index 000000000..81acd611f
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6ul/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PICO_IMX6UL
+
+config SYS_BOARD
+	default "pico-imx6ul"
+
+config SYS_VENDOR
+	default "technexion"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "pico-imx6ul"
+
+endif
diff --git a/roms/u-boot/board/technexion/pico-imx6ul/MAINTAINERS b/roms/u-boot/board/technexion/pico-imx6ul/MAINTAINERS
new file mode 100644
index 000000000..f94a011ee
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6ul/MAINTAINERS
@@ -0,0 +1,10 @@
+TechNexion PICO-IMX6UL board
+M:	Richard Hu <richard.hu@technexion.com>
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/technexion/pico-imx6ul/
+F:	include/configs/pico-imx6ul.h
+F:	configs/pico-imx6ul_defconfig
+F:	configs/pico-dwarf-imx6ul_defconfig
+F:	configs/pico-hobbit-imx6ul_defconfig
+F:	configs/pico-pi-imx6ul_defconfig
diff --git a/roms/u-boot/board/technexion/pico-imx6ul/Makefile b/roms/u-boot/board/technexion/pico-imx6ul/Makefile
new file mode 100644
index 000000000..b7493df01
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6ul/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2015 Technexion Ltd.
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+
+obj-y  := pico-imx6ul.o spl.o
diff --git a/roms/u-boot/board/technexion/pico-imx6ul/README b/roms/u-boot/board/technexion/pico-imx6ul/README
new file mode 100644
index 000000000..e58640c55
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6ul/README
@@ -0,0 +1,159 @@
+How to Update U-Boot on Pico-imx6ul board
+-----------------------------------------
+
+Required software on the host PC:
+
+- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
+
+- dfu-util: http://dfu-util.sourceforge.net/releases/
+
+Build U-Boot for Pico:
+
+$ make mrproper
+$ make pico-imx6ul_defconfig
+$ make
+
+This generates the SPL and u-boot-dtb.img binaries.
+
+1. Loading U-Boot via USB Serial Download Protocol
+
+Note: This method is convenient for development purposes.
+If the eMMC has already a U-Boot flashed with DFU support then
+the user can go to step 2 below in order to update U-Boot.
+
+Put pico board in USB download mode (refer to the document
+https://www.nxp.com/files-static/32bit/doc/quick_start_guide/PICO-IMX6UL-QSG.pdf
+Figure 6a at page 7).
+
+Connect a USB to serial adapter between the host PC and pico.
+
+Connect a USB cable between the OTG pico port and the host PC.
+
+Open a terminal program such as minicom.
+
+Copy SPL and u-boot-dtb.img to the imx_usb_loader folder.
+
+Load the SPL binary via USB:
+
+$ sudo ./imx_usb SPL
+
+Load the u-boot-dtb.img binary via USB:
+
+$ sudo ./imx_usb u-boot-dtb.img
+
+Then U-Boot starts and its messages appear in the console program.
+
+Use the default environment variables:
+
+=> env default -f -a
+=> saveenv
+
+2. Flashing U-Boot into the eMMC
+
+Run the DFU agent so we can flash the new images using dfu-util tool:
+
+=> dfu 0 mmc 0
+
+Flash SPL and u-boot-dtb.img into the eMMC running the following commands on a PC:
+
+$ sudo dfu-util -D SPL -a spl
+
+$ sudo dfu-util -D u-boot-dtb.img -a u-boot
+
+Remove power from the pico board.
+
+Put pico board into normal boot mode.
+
+Power up the board and the new updated U-Boot should boot from eMMC.
+
+Booting in Falcon mode
+======================
+
+Generate a uImage kernel:
+
+$ make imx_v6_v7_defconfig (Using the default imx_v6_v7_defconfig configuration
+just for an example. In order to boot faster the user should customize the
+defconfig by only enabling the minimal required drivers).
+
+$ make -j4 uImage LOADADDR=0x80008000
+
+$ cp arch/arm/boot/uImage /tftpboot
+$ cp arch/arm/boot/dts/imx6ul-pico-hobbit.dtb /tftpboot
+
+In the U-Boot prompt:
+
+Setup the server and board IP addresses:
+=> setenv serverip 192.168.0.10
+=> setenv ipaddr 192.168.0.11
+
+Get the dtb file:
+=> tftp ${fdt_addr} imx6ul-pico-hobbit.dtb
+
+Get the kernel:
+=> tftp ${loadaddr} uImage
+
+Write the kernel at 2MB offset:
+=> mmc write ${loadaddr} 0x1000 0x5000
+
+Setup the bootargs:
+=> setenv bootargs 'console=ttymxc5,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait rw'
+
+Prepare args:
+=> spl export fdt ${loadaddr} - ${fdt_addr}
+## Booting kernel from Legacy Image at 82000000 ...
+   Image Name:   Linux-4.19.0-rc2-next-20180905-0
+   Image Type:   ARM Linux Kernel Image (uncompressed)
+   Data Size:    8365608 Bytes = 8 MiB
+   Load Address: 80008000
+   Entry Point:  80008000
+   Verifying Checksum ... OK
+## Flattened Device Tree blob at 83000000
+   Booting using the fdt blob at 0x83000000
+   Loading Kernel Image ... OK
+   Using Device Tree in place at 83000000, end 83009c63
+subcommand not supported
+subcommand not supported
+   Using Device Tree in place at 83000000, end 8300cc63
+Argument image is now in RAM: 0x83000000
+
+Write 1MB of args data (0x800 sectors) to 1MB offset (0x800 sectors):
+
+=> mmc write ${fdt_addr} 0x800 0x800
+
+In order to boot with Falcon mode, activate the CONFIG_SPL_OS_BOOT
+option in the defconfig
+
+--- a/configs/pico-hobbit-imx6ul_defconfig
++++ b/configs/pico-hobbit-imx6ul_defconfig
+@@ -53,3 +53,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+ CONFIG_CI_UDC=y
+ CONFIG_OF_LIBFDT=y
++CONFIG_SPL_OS_BOOT=y
+
+Then rebuild U-Boot:
+
+$ make pico-hobbit-imx6ul_defconfig
+$ make -j4
+
+Launch UMS:
+=> ums 0 mmc 0
+
+Flash the new binaries:
+
+$ sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync
+$ sudo dd if=u-boot-dtb.img  of=/dev/sdX bs=1k seek=69; sync
+
+And then SPL binary will load and jump directly to the kernel:
+
+U-Boot SPL 2018.09-rc2-00156-g8c46f15-dirty (Sep 05 2018 - 16:24:05 -0300)
+Trying to boot from MMC1
+[    0.000000] Booting Linux on physical CPU 0x0
+[    0.000000] Linux version 4.19.0-rc2-next-20180905-00001-gb805e2d (fabio@fabio-Latitude-E5450) (gcc version 5.4.0 20160609 (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.9)) #533 SMP Wed Sep 5 16:21:03 -03 2018
+[    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
+[    0.000000] CPU: div instructions available: patching division code
+[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
+[    0.000000] OF: fdt: Machine model: Technexion Pico i.MX6UL Board
+[    0.000000] Memory policy: Data cache writealloc
+[    0.000000] cma: Reserved 64 MiB at 0x8c000000
+...
diff --git a/roms/u-boot/board/technexion/pico-imx6ul/imximage.cfg b/roms/u-boot/board/technexion/pico-imx6ul/imximage.cfg
new file mode 100644
index 000000000..993c1da67
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6ul/imximage.cfg
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x00000030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000000
+DATA 4 0x021B083C 0x01380134
+DATA 4 0x021B0848 0x40404244
+DATA 4 0x021B0850 0x40405050
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00921012
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x00333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D8B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x00000047
+DATA 4 0x021B0000 0x83180000
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
diff --git a/roms/u-boot/board/technexion/pico-imx6ul/pico-imx6ul.c b/roms/u-boot/board/technexion/pico-imx6ul/pico-imx6ul.c
new file mode 100644
index 000000000..682c88dee
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6ul/pico-imx6ul.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Technexion Ltd.
+ *
+ * Author: Richard Hu <richard.hu@technexion.com>
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <common.h>
+#include <miiphy.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <usb.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../../freescale/common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+static int setup_fec(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	/* LCD_BLT_CTRL: GPIO for Brightness adjustment  */
+	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* LCD_VDD_EN: LCD enabled */
+	MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_lcd(void)
+{
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+	gpio_request(IMX_GPIO_NR(4, 10), "lcd_brightness");
+	gpio_request(IMX_GPIO_NR(1, 11), "lcd_enable");
+	/* Set Brightness to high */
+	gpio_direction_output(IMX_GPIO_NR(4, 10) , 1);
+	/* Set LCD enable to high */
+	gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart6_pads[] = {
+	MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pad[] = {
+	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
+}
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad));
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret, dev_id, rev_id;
+
+	ret = pmic_get("pfuze3000@8", &dev);
+	if (ret == -ENODEV)
+		return 0;
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	pmic_reg_write(dev, PFUZE3000_LDOGCTL, 0x1);
+
+	/* SW1B step ramp up time from 2us to 4us/25mV */
+	pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
+
+	/* SW1B mode to APS/PFM */
+	pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
+
+	/* SW1B standby voltage set to 0.975V */
+	pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
+
+	return 0;
+}
+#endif
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return USB_INIT_DEVICE;
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_fec();
+	setup_usb();
+#ifdef CONFIG_VIDEO_MXS
+	setup_lcd();
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: PICO-IMX6UL-EMMC\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/technexion/pico-imx6ul/spl.c b/roms/u-boot/board/technexion/pico-imx6ul/spl.c
new file mode 100644
index 000000000..251f5a1b7
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx6ul/spl.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/libfdt.h>
+#include <spl.h>
+
+#if defined(CONFIG_SPL_BUILD)
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* Break into full U-Boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif
+
+#include <asm/arch/mx6-ddr.h>
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x00080000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x01380134,
+	.p0_mprddlctl = 0x40404244,
+	.p0_mpwrdlctl = 0x40405050,
+};
+
+static struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize		= 0,
+	.cs1_mirror	= 0,
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+	.refsel = 1,
+	.refr = 3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 1333,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1350,
+	.trcmin = 4950,
+	.trasmin = 3600,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+}
+
+static void imx6ul_spl_dram_cfg_size(u32 ram_size)
+{
+	if (ram_size == SZ_256M)
+		mem_ddr.rowaddr = 14;
+	else
+		mem_ddr.rowaddr = 15;
+
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+static void imx6ul_spl_dram_cfg(void)
+{
+	ulong ram_size_test, ram_size = 0;
+
+	for (ram_size = SZ_512M; ram_size >= SZ_256M; ram_size >>= 1) {
+		imx6ul_spl_dram_cfg_size(ram_size);
+		ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
+		if (ram_size_test == ram_size)
+			break;
+	}
+
+	if (ram_size < SZ_256M) {
+		puts("ERROR: DRAM size detection failed\n");
+		hang();
+	}
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+	arch_cpu_init();
+	board_early_init_f();
+	timer_init();
+	preloader_console_init();
+	imx6ul_spl_dram_cfg();
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	board_init_r(NULL, 0);
+}
+
+void reset_cpu(void)
+{
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
diff --git a/roms/u-boot/board/technexion/pico-imx7d/Kconfig b/roms/u-boot/board/technexion/pico-imx7d/Kconfig
new file mode 100644
index 000000000..f4ae18ca6
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx7d/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PICO_IMX7D
+
+config SYS_BOARD
+	default "pico-imx7d"
+
+config SYS_VENDOR
+	default "technexion"
+
+config SYS_SOC
+	default "mx7"
+
+config SYS_CONFIG_NAME
+	default "pico-imx7d"
+
+endif
diff --git a/roms/u-boot/board/technexion/pico-imx7d/MAINTAINERS b/roms/u-boot/board/technexion/pico-imx7d/MAINTAINERS
new file mode 100644
index 000000000..325e1735c
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx7d/MAINTAINERS
@@ -0,0 +1,12 @@
+TechNexion PICO-IMX7D board
+M:	Vanessa Maegima <vanessa.maegima@nxp.com>
+M:	Otavio Salvador <otavio@ossystems.com.br>
+S:	Maintained
+F:	board/technexion/pico-imx7d/
+F:	include/configs/pico-imx7d.h
+F:	configs/pico-imx7d_defconfig
+F:	configs/pico-imx7d_bl33_defconfig
+F:	configs/pico-hobbit-imx7d_defconfig
+F:	configs/pico-pi-imx7d_defconfig
+F:	configs/pico-nymph-imx7d_defconfig
+F:	configs/pico-dwarf-imx7d_defconfig
diff --git a/roms/u-boot/board/technexion/pico-imx7d/Makefile b/roms/u-boot/board/technexion/pico-imx7d/Makefile
new file mode 100644
index 000000000..4ae3d606b
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx7d/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2017 NXP Semiconductors
+
+obj-y  := pico-imx7d.o spl.o
diff --git a/roms/u-boot/board/technexion/pico-imx7d/README b/roms/u-boot/board/technexion/pico-imx7d/README
new file mode 100644
index 000000000..4d57cdbfa
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx7d/README
@@ -0,0 +1,159 @@
+How to update U-Boot on pico-imx7d board
+----------------------------------------
+
+Required software on the host PC:
+
+- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
+
+Build U-Boot for pico:
+
+$ make mrproper
+$ make pico-imx7d_defconfig
+$ make
+
+This generates the SPL and u-boot-dtb.img binaries.
+
+1. Loading U-Boot via USB Serial Download Protocol
+
+Note: This method is convenient for development purposes.
+If the eMMC has already a U-Boot flashed with DFU support then
+the user can go to step 2 below in order to update U-Boot.
+
+Put pico board in USB download mode (refer to the PICO-iMX7D Quick Start Guide
+page 3)
+
+Connect a USB to serial adapter between the host PC and pico.
+
+Connect a USB cable between the OTG pico port and the host PC.
+
+Note: Some computers may be a bit strict with USB current draw and will
+shut down their ports if the draw is too high. The solution for that is
+to use an externally powered USB hub between the board and the host computer.
+
+Open a terminal program such as minicom.
+
+Copy SPL and u-boot-dtb.img to the imx_usb_loader folder.
+
+Load the SPL binary via USB:
+
+$ sudo ./imx_usb SPL
+
+Load the u-boot-dtb.img binary via USB:
+
+$ sudo ./imx_usb u-boot-dtb.img
+
+Then U-Boot starts and its messages appear in the console program.
+
+Use the default environment variables:
+
+=> env default -f -a
+=> saveenv
+
+2. Flashing U-Boot into the eMMC
+
+Run the DFU agent so we can flash the new images using dfu-util tool:
+
+=> dfu 0 mmc 0
+
+Flash SPL and u-boot-dtb.img into the eMMC running the following commands on a PC:
+
+$ sudo dfu-util -D SPL -a spl
+
+$ sudo dfu-util -D u-boot-dtb.img -a u-boot
+
+Remove power from the pico board.
+
+Put pico board into normal boot mode.
+
+Power up the board and the new updated U-Boot should boot from eMMC.
+
+Booting in Falcon mode
+======================
+
+Generate a uImage kernel:
+
+$ make imx_v6_v7_defconfig (Using the default imx_v6_v7_defconfig configuration
+just for an example. In order to boot faster the user should customize the
+defconfig by only enabling the minimal required drivers).
+
+$ make -j4 uImage LOADADDR=0x80008000
+
+$ cp arch/arm/boot/uImage /tftpboot
+$ cp arch/arm/boot/dts/imx7d-pico-pi.dtb /tftpboot
+
+In the U-Boot prompt:
+
+Setup the server and board IP addresses:
+=> setenv serverip 192.168.0.10
+=> setenv ipaddr 192.168.0.11
+
+Get the dtb file:
+=> tftp ${fdt_addr} imx7d-pico-pi.dtb
+
+Get the kernel:
+=> tftp ${loadaddr} uImage
+
+Write the kernel at 2MB offset:
+=> mmc write ${loadaddr} 0x1000 0x5000
+
+Setup the bootargs:
+=> setenv bootargs 'console=ttymxc4,115200 root=/dev/mmcblk2p1 rootfstype=ext4 rootwait rw'
+
+Prepare args:
+=> spl export fdt ${loadaddr} - ${fdt_addr}
+## Booting kernel from Legacy Image at 80800000 ...
+   Image Name:   Linux-5.2.14
+   Image Type:   ARM Linux Kernel Image (uncompressed)
+   Data Size:    9077544 Bytes = 8.7 MiB
+   Load Address: 80008000
+   Entry Point:  80008000
+   Verifying Checksum ... OK
+## Flattened Device Tree blob at 83000000
+   Booting using the fdt blob at 0x83000000
+   Loading Kernel Image
+   Using Device Tree in place at 83000000, end 8300b615
+subcommand not supported
+subcommand not supported
+   Using Device Tree in place at 83000000, end 8300e615
+Argument image is now in RAM: 0x83000000
+=>
+
+Write 1MB of args data (0x800 sectors) to 1MB offset (0x800 sectors):
+
+=> mmc write ${fdt_addr} 0x800 0x800
+
+In order to boot with Falcon mode, activate the CONFIG_SPL_OS_BOOT
+option in the defconfig
+
+--- a/configs/pico-imx7d_defconfig
++++ b/configs/pico-imx7d_defconfig
+@@ -67,3 +67,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+ CONFIG_CI_UDC=y
+ CONFIG_VIDEO=y
++CONFIG_SPL_OS_BOOT=y
+
+Then rebuild U-Boot:
+
+$ make pico-imx7d_defconfig
+$ make -j4
+
+Launch UMS:
+=> ums 0 mmc 0
+
+Flash the new binaries:
+
+$ sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync
+$ sudo dd if=u-boot-dtb.img  of=/dev/sdX bs=1k seek=69; sync
+
+And then SPL binary will load and jump directly to the kernel:
+
+U-Boot SPL 2019.10-rc3-00284-g001c8ea94a-dirty (Sep 10 2019 - 12:46:01 -0300)
+Trying to boot from MMC1
+[    0.000000] Booting Linux on physical CPU 0x0
+[    0.000000] Linux version 5.2.14 (fabio@fabio-OptiPlex-7010) (gcc version 7.4.0 (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1)) #30 SMP Wed Sep 10 12:36:27 -03 2019
+[    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
+[    0.000000] CPU: div instructions available: patching division code
+[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
+[    0.000000] OF: fdt: Machine model: TechNexion PICO-IMX7D Board and PI baseboard
+...
diff --git a/roms/u-boot/board/technexion/pico-imx7d/README.pico-imx7d_BL33 b/roms/u-boot/board/technexion/pico-imx7d/README.pico-imx7d_BL33
new file mode 100644
index 000000000..1b346093b
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx7d/README.pico-imx7d_BL33
@@ -0,0 +1,44 @@
+This document describes the instruction to build and flash ATF/OPTEE/U-Boot on
+pico-imx7d board. U-Boot is loaded as part of FIP image by ATF in this setup.
+The boot sequence is ATF -> OPTEE -> U-Boot -> Linux. U-Boot is in non-secure
+world in this case.
+
+- Build u-boot
+    Set environment variable of CROSS_COMPILE for your toolchain
+    $ make pico-imx7d_bl33_defconfig
+    $ make all
+
+- Download and build OPTEE
+    $ git clone git@github.com:OP-TEE/optee_os.git
+    $ make PLATFORM=imx PLATFORM_FLAVOR=mx7dpico_mbl CFG_BOOT_SECONDARY_REQUEST=y ARCH=arm
+
+- Download and build ATF
+    $ git clone https://git.linaro.org/landing-teams/working/mbl/arm-trusted-firmware.git -b linaro-imx7
+    $ make DEBUG=1 PLAT=picopi ARCH=aarch32 ARM_ARCH_MAJOR=7 \
+            CROSS_COMPILE=arm-linux-gnueabihf- LOG_LEVEL=50 V=1 \
+            CRASH_REPORTING=1 AARCH32_SP=optee all
+    Save file content in this link to file pico-imx7d.cfg:
+      http://git.linaro.org/landing-teams/working/mbl/u-boot.git/tree/board/technexion/pico-imx7d/pico-imx7d.cfg?h=linaro-imx
+    $ u-boot/tools/mkimage -n pico-imx7d.cfg -T imximage -e 0x9df00000 -d \
+            build/picopi/debug/bl2.bin bl2.imx
+
+- Create FIP image
+    Create a  fiptool_images/ folder in ATF folder, copy u-boot.bin in u-boot
+folder and tee*.bin in optee out/arm-plat-imx/core/tee/ folder to
+fiptool_images. Run below command in ATF folder to generate FIP image.
+    $ make -C tools/fiptool/
+    $ tools/fiptool/fiptool create --tos-fw fiptool_images/tee-header_v2.bin \
+          --tos-fw-extra1 fiptool_images/tee-pager_v2.bin \
+          --tos-fw-extra2 fiptool_images/tee-pageable_v2.bin \
+          --nt-fw fiptool_images/u-boot.bin \
+          fip.bin
+
+- Burn the images to eMMC for test.
+    Run below command in atf folder:
+    $ dd if=build/picopi/debug/bl2.bin.imx of=/dev/disk/by-id/usb-<your device>  bs=1024 seek=1;sync
+    $ dd if=fip.bin of=/dev/disk/by-id/usb-<your device>  bs=1024 seek=1;sync
+
+- Test
+    Just boot up your board and wait for u-boot start up after ATF's log.
+    For booting Linux in FIT image, please reference the FIT files in
+    u-boot doc/uImage.FIT/ folder.
diff --git a/roms/u-boot/board/technexion/pico-imx7d/pico-imx7d.c b/roms/u-boot/board/technexion/pico-imx7d/pico-imx7d.c
new file mode 100644
index 000000000..2d749dac1
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx7d/pico-imx7d.c
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 NXP Semiconductors
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../../freescale/common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
+	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C4 for PMIC */
+static struct i2c_pads_info i2c_pad_info4 = {
+	.scl = {
+		.i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
+		.gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
+		.gp = IMX_GPIO_NR(6, 16),
+	},
+	.sda = {
+		.i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
+		.gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
+		.gp = IMX_GPIO_NR(6, 17),
+	},
+};
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	/* Subtract the defined OPTEE runtime firmware length */
+#ifdef CONFIG_OPTEE_TZDRAM_SIZE
+		gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC	3
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg, rev_id;
+
+	ret = power_pfuze3000_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE3000");
+	ret = pmic_probe(p);
+	if (ret) {
+		printf("Warning:  Cannot find PMIC PFUZE3000\n");
+		printf("\tPower consumption is not optimized.\n");
+		return 0;
+	}
+
+	pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
+	pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
+	printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
+	reg |= 0x1;
+	pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
+
+	/* SW1A/1B mode set to APS/APS */
+	reg = 0x8;
+	pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
+	pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
+
+	/* SW1A/1B standby voltage set to 1.025V */
+	reg = 0xd;
+	pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
+	pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
+
+	/* decrease SW1B normal voltage to 0.975V */
+	pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
+	reg &= ~0x1f;
+	reg |= PFUZE3000_SW1AB_SETP(975);
+	pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
+
+	return 0;
+}
+#endif
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart5_pads[] = {
+	MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
+			IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
+
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe7;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+#ifdef CONFIG_SYS_I2C_MXC
+	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_DM_VIDEO
+void setup_lcd(void)
+{
+	gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness");
+	gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable");
+	/* Set Brightness to high */
+	gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
+	/* Set LCD enable to high */
+	gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_DM_VIDEO
+	setup_lcd();
+#endif
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	/*
+	 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+	 * since we use PMIC_PWRON to reset the board.
+	 */
+	clrsetbits_le16(&wdog->wcr, 0, 0x10);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: i.MX7D PICOSOM\n");
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const usb_otg2_pads[] = {
+	MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+	switch (port) {
+	case 0:
+		break;
+	case 1:
+		imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
+						 ARRAY_SIZE(usb_otg2_pads));
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
diff --git a/roms/u-boot/board/technexion/pico-imx7d/spl.c b/roms/u-boot/board/technexion/pico-imx7d/spl.c
new file mode 100644
index 000000000..df5f05857
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx7d/spl.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Technexion Ltd.
+ *
+ * Author: Richard Hu <richard.hu@technexion.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch-mx7/mx7-ddr.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <spl.h>
+
+#if defined(CONFIG_SPL_BUILD)
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* Break into full U-Boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif
+
+static struct ddrc ddrc_regs_val = {
+	.mstr		= 0x01040001,
+	.rfshtmg	= 0x00400046,
+	.init1		= 0x00690000,
+	.init0		= 0x00020083,
+	.init3		= 0x09300004,
+	.init4		= 0x04080000,
+	.init5		= 0x00100004,
+	.rankctl	= 0x0000033F,
+	.dramtmg0	= 0x09081109,
+	.dramtmg1	= 0x0007020d,
+	.dramtmg2	= 0x03040407,
+	.dramtmg3	= 0x00002006,
+	.dramtmg4	= 0x04020205,
+	.dramtmg5	= 0x03030202,
+	.dramtmg8	= 0x00000803,
+	.zqctl0		= 0x00800020,
+	.dfitmg0	= 0x02098204,
+	.dfitmg1	= 0x00030303,
+	.dfiupd0	= 0x80400003,
+	.dfiupd1	= 0x00100020,
+	.dfiupd2	= 0x80100004,
+	.addrmap4	= 0x00000F0F,
+	.odtcfg		= 0x06000604,
+	.odtmap		= 0x00000001,
+	.rfshtmg	= 0x00400046,
+	.dramtmg0	= 0x09081109,
+	.addrmap0	= 0x0000001f,
+	.addrmap1	= 0x00080808,
+	.addrmap4	= 0x00000f0f,
+	.addrmap5	= 0x07070707,
+	.addrmap6	= 0x0f0f0707,
+};
+
+static struct ddrc_mp ddrc_mp_val = {
+	.pctrl_0	= 0x00000001,
+};
+
+static struct ddr_phy ddr_phy_regs_val = {
+	.phy_con0	= 0x17420f40,
+	.phy_con1	= 0x10210100,
+	.phy_con4	= 0x00060807,
+	.mdll_con0	= 0x1010007e,
+	.drvds_con0	= 0x00000d6e,
+	.cmd_sdll_con0	= 0x00000010,
+	.offset_lp_con0	= 0x0000000f,
+	.offset_rd_con0	= 0x08080808,
+	.offset_wr_con0	= 0x08080808,
+};
+
+static struct mx7_calibration calib_param = {
+	.num_val	= 5,
+	.values		= {
+		0x0E407304,
+		0x0E447304,
+		0x0E447306,
+		0x0E447304,
+		0x0E447304,
+	},
+};
+
+static void gpr_init(void)
+{
+	struct iomuxc_gpr_base_regs *gpr_regs =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+	writel(0x4F400005, &gpr_regs->gpr[1]);
+}
+
+static bool is_1g(void)
+{
+	gpio_direction_input(IMX_GPIO_NR(1, 12));
+	return !gpio_get_value(IMX_GPIO_NR(1, 12));
+}
+
+static void ddr_init(void)
+{
+	if (is_1g())
+		ddrc_regs_val.addrmap6	= 0x0f070707;
+
+	mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
+		     &calib_param);
+}
+
+void board_init_f(ulong dummy)
+{
+	arch_cpu_init();
+	gpr_init();
+	board_early_init_f();
+	timer_init();
+	preloader_console_init();
+	ddr_init();
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	board_init_r(NULL, 0);
+}
+
+void reset_cpu(void)
+{
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* Assume uSDHC3 emmc is always present */
+	return 1;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
diff --git a/roms/u-boot/board/technexion/pico-imx8mq/Kconfig b/roms/u-boot/board/technexion/pico-imx8mq/Kconfig
new file mode 100644
index 000000000..031fc1d56
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx8mq/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PICO_IMX8MQ
+
+config SYS_BOARD
+	default "pico-imx8mq"
+
+config SYS_VENDOR
+	default "technexion"
+
+config SYS_CONFIG_NAME
+	default "pico-imx8mq"
+
+endif
diff --git a/roms/u-boot/board/technexion/pico-imx8mq/MAINTAINERS b/roms/u-boot/board/technexion/pico-imx8mq/MAINTAINERS
new file mode 100644
index 000000000..626e7337a
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx8mq/MAINTAINERS
@@ -0,0 +1,6 @@
+PICOPI IMX8MQ BOARD
+M:	Marek Vasut <marek.vasut@gmail.com>
+S:	Maintained
+F:	board/technexion/pico-imx8mq/
+F:	include/configs/pico-imx8mq.h
+F:	configs/pico-imx8mq_defconfig
diff --git a/roms/u-boot/board/technexion/pico-imx8mq/Makefile b/roms/u-boot/board/technexion/pico-imx8mq/Makefile
new file mode 100644
index 000000000..7cfe1e02e
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx8mq/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += pico-imx8mq.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_1gb.o lpddr4_timing_2gb.o lpddr4_timing_3gb.o lpddr4_timing_4gb.o
+endif
diff --git a/roms/u-boot/board/technexion/pico-imx8mq/README b/roms/u-boot/board/technexion/pico-imx8mq/README
new file mode 100644
index 000000000..99fa33287
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx8mq/README
@@ -0,0 +1,52 @@
+U-Boot for the Technexion Pico i.MX8MQ
+
+Quick Start
+===========
+- Build the TFA binary
+- Get DDR and HDMI firmware
+- Build U-Boot
+- Boot
+
+Get and Build the TFA blob
+==========================
+Note: srctree is U-Boot source directory
+Get ATF from: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+branch: master
+$ CROSS_COMPILE=aarch64-linux-gnu- make PLAT=imx8mq bl31
+$ cp build/imx8mq/release/bl31.bin $(builddir)
+
+Get the DDR and HDMI firmware
+=============================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
+$ chmod +x firmware-imx-7.9.bin
+$ ./firmware-imx-7.9.bin
+# Or use this to avoid running random scripts from the internet,
+# but note that you must agree to the license the script displays:
+# $ dd if=firmware-imx-7.9.bin of=firmware-imx-7.9.tar.bz2 bs=38868 skip=1
+# $ tar -xf firmware-imx-7.9.tar.bz2
+$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
+$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+============
+$ export CROSS_COMPILE=aarch64-poky-linux-
+$ make pico-imx8mq_defconfig
+$ make flash.bin
+
+Burn the flash.bin to MicroSD card offset 33KB
+$ dd if=flash.bin of=/dev/mmcblkX bs=1024 seek=33
+Or into eMMC from a running system
+$ dhcp flash.bin && mmc write $loadaddr 0x42 0x800
+
+Boot
+====
+"o" denotes a pin
+"[]" denotes two pins bridged by a jumper
+
+eMMC boot:
+J1 o[] []o J2
+   []o o[]
+
+USB upload via USB-C connector:
+J1 ooo ooo J2
+   o[] []o
diff --git a/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing.h b/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing.h
new file mode 100644
index 000000000..89b0b927b
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+extern struct dram_timing_info dram_timing_1gb;
+extern struct dram_timing_info dram_timing_2gb;
+extern struct dram_timing_info dram_timing_3gb;
+extern struct dram_timing_info dram_timing_4gb;
+
+#endif /* __LPDDR4_TIMING_H__ */
diff --git a/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c b/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c
new file mode 100644
index 000000000..bcb852668
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c
@@ -0,0 +1,1734 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa1080020},
+	{0x3d400028, 0x0},
+	{0x3d400020, 0x203},
+	{0x3d400024, 0x3e800},
+	{0x3d400064, 0x610090},
+	{0x3d4000d0, 0xc003061c},
+	{0x3d4000d4, 0x9e0000},
+	{0x3d4000dc, 0xd4002d},
+	{0x3d4000e0, 0x310008},
+	{0x3d4000e8, 0x66004a},
+	{0x3d4000ec, 0x16004a},
+	{0x3d400100, 0x1a201b22},
+	{0x3d400104, 0x60633},
+	{0x3d40010c, 0xc0c000},
+	{0x3d400110, 0xf04080f},
+	{0x3d400114, 0x2040c0c},
+	{0x3d400118, 0x1010007},
+	{0x3d40011c, 0x401},
+	{0x3d400130, 0x20600},
+	{0x3d400134, 0xc100002},
+	{0x3d400138, 0x96},
+	{0x3d400144, 0xa00050},
+	{0x3d400180, 0xc3200018},
+	{0x3d400184, 0x28061a8},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x497820a},
+	{0x3d400194, 0x80303},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001b4, 0x170a},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x1},
+	{0x3d4000f4, 0x639},
+	{0x3d400108, 0x70e1617},
+	{0x3d400200, 0x1f},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0xf070707},
+	{0x3d402020, 0x1},
+	{0x3d402024, 0xd0c0},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0x14001f},
+	{0x3d4020dc, 0x940009},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004a},
+	{0x3d4020ec, 0x16004a},
+	{0x3d402100, 0xb070508},
+	{0x3d402104, 0x3040b},
+	{0x3d402108, 0x305090c},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x4040204},
+	{0x3d402114, 0x2030303},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x20},
+	{0x3d402144, 0x220011},
+	{0x3d402180, 0xc0a70006},
+	{0x3d402190, 0x3858202},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x502},
+	{0x3d400244, 0x0},
+	{0x3d400250, 0x29001505},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x5900575b},
+	{0x3d400264, 0x90000096},
+	{0x3d40026c, 0x1000012c},
+	{0x3d400300, 0x16},
+	{0x3d400304, 0x0},
+	{0x3d40030c, 0x0},
+	{0x3d400320, 0x1},
+	{0x3d40036c, 0x11},
+	{0x3d400400, 0x111},
+	{0x3d400404, 0x10f3},
+	{0x3d400408, 0x72ff},
+	{0x3d400490, 0x1},
+	{0x3d400494, 0xe00},
+	{0x3d400498, 0x62ffff},
+	{0x3d40049c, 0xe00},
+	{0x3d4004a0, 0xffff},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x2},
+	{0x110a3, 0x3},
+	{0x110a4, 0x4},
+	{0x110a5, 0x5},
+	{0x110a6, 0x6},
+	{0x110a7, 0x7},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x2},
+	{0x120a3, 0x3},
+	{0x120a4, 0x4},
+	{0x120a5, 0x5},
+	{0x120a6, 0x6},
+	{0x120a7, 0x7},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x20110, 0x2},
+	{0x20111, 0x3},
+	{0x20112, 0x4},
+	{0x20113, 0x5},
+	{0x20114, 0x0},
+	{0x20115, 0x1},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x19},
+	{0x1200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x1},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x3},
+	{0x120056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x43, 0x63},
+	{0x1043, 0x63},
+	{0x2043, 0x63},
+	{0x3043, 0x63},
+	{0x4043, 0x63},
+	{0x5043, 0x63},
+	{0x6043, 0x63},
+	{0x7043, 0x63},
+	{0x8043, 0x63},
+	{0x9043, 0x63},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x320},
+	{0x120008, 0xa7},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x200f0, 0x0},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5555},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x200c7, 0x80},
+	{0x1200c7, 0x80},
+	{0x200ca, 0x106},
+	{0x1200ca, 0x106},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
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+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xc80},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x1},
+	{0x54003, 0x29c},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x994},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x994},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x9400},
+	{0x54033, 0x3109},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0x9400},
+	{0x54039, 0x3109},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xc80},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x64},
+	{0x2000c, 0xc8},
+	{0x2000d, 0x7d0},
+	{0x2000e, 0x2c},
+	{0x12000b, 0x14},
+	{0x12000c, 0x29},
+	{0x12000d, 0x1a1},
+	{0x12000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_1gb = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
+
diff --git a/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c b/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c
new file mode 100644
index 000000000..9a8a323d6
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c
@@ -0,0 +1,1734 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa1080020},
+	{0x3d400028, 0x0},
+	{0x3d400020, 0x203},
+	{0x3d400024, 0x3e800},
+	{0x3d400064, 0x6100e0},
+	{0x3d4000d0, 0xc003061c},
+	{0x3d4000d4, 0x9e0000},
+	{0x3d4000dc, 0xd4002d},
+	{0x3d4000e0, 0x310008},
+	{0x3d4000e8, 0x66004a},
+	{0x3d4000ec, 0x16004a},
+	{0x3d400100, 0x1a201b22},
+	{0x3d400104, 0x60633},
+	{0x3d40010c, 0xc0c000},
+	{0x3d400110, 0xf04080f},
+	{0x3d400114, 0x2040c0c},
+	{0x3d400118, 0x1010007},
+	{0x3d40011c, 0x401},
+	{0x3d400130, 0x20600},
+	{0x3d400134, 0xc100002},
+	{0x3d400138, 0xe6},
+	{0x3d400144, 0xa00050},
+	{0x3d400180, 0xc3200018},
+	{0x3d400184, 0x28061a8},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x497820a},
+	{0x3d400194, 0x80303},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001b4, 0x170a},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x1},
+	{0x3d4000f4, 0x639},
+	{0x3d400108, 0x70e1617},
+	{0x3d400200, 0x1f},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0x7070707},
+	{0x3d402020, 0x1},
+	{0x3d402024, 0xd0c0},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0x14002f},
+	{0x3d4020dc, 0x940009},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004a},
+	{0x3d4020ec, 0x16004a},
+	{0x3d402100, 0xb070508},
+	{0x3d402104, 0x3040b},
+	{0x3d402108, 0x305090c},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x4040204},
+	{0x3d402114, 0x2030303},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x31},
+	{0x3d402144, 0x220011},
+	{0x3d402180, 0xc0a70006},
+	{0x3d402190, 0x3858202},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x502},
+	{0x3d400244, 0x0},
+	{0x3d400250, 0x29001505},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x5900575b},
+	{0x3d400264, 0x90000096},
+	{0x3d40026c, 0x1000012c},
+	{0x3d400300, 0x16},
+	{0x3d400304, 0x0},
+	{0x3d40030c, 0x0},
+	{0x3d400320, 0x1},
+	{0x3d40036c, 0x11},
+	{0x3d400400, 0x111},
+	{0x3d400404, 0x10f3},
+	{0x3d400408, 0x72ff},
+	{0x3d400490, 0x1},
+	{0x3d400494, 0xe00},
+	{0x3d400498, 0x62ffff},
+	{0x3d40049c, 0xe00},
+	{0x3d4004a0, 0xffff},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x2},
+	{0x110a3, 0x3},
+	{0x110a4, 0x4},
+	{0x110a5, 0x5},
+	{0x110a6, 0x6},
+	{0x110a7, 0x7},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x2},
+	{0x120a3, 0x3},
+	{0x120a4, 0x4},
+	{0x120a5, 0x5},
+	{0x120a6, 0x6},
+	{0x120a7, 0x7},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x20110, 0x2},
+	{0x20111, 0x3},
+	{0x20112, 0x4},
+	{0x20113, 0x5},
+	{0x20114, 0x0},
+	{0x20115, 0x1},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x19},
+	{0x1200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x1},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x3},
+	{0x120056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x43, 0x63},
+	{0x1043, 0x63},
+	{0x2043, 0x63},
+	{0x3043, 0x63},
+	{0x4043, 0x63},
+	{0x5043, 0x63},
+	{0x6043, 0x63},
+	{0x7043, 0x63},
+	{0x8043, 0x63},
+	{0x9043, 0x63},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x320},
+	{0x120008, 0xa7},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x200f0, 0x0},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5555},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x200c7, 0x80},
+	{0x1200c7, 0x80},
+	{0x200ca, 0x106},
+	{0x1200ca, 0x106},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
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+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xc80},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x1},
+	{0x54003, 0x29c},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x994},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x994},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x9400},
+	{0x54033, 0x3109},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0x9400},
+	{0x54039, 0x3109},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xc80},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x64},
+	{0x2000c, 0xc8},
+	{0x2000d, 0x7d0},
+	{0x2000e, 0x2c},
+	{0x12000b, 0x14},
+	{0x12000c, 0x29},
+	{0x12000d, 0x1a1},
+	{0x12000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_2gb = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
+
diff --git a/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c b/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c
new file mode 100644
index 000000000..0f74ce581
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c
@@ -0,0 +1,1734 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa3080020},
+	{0x3d400028, 0x0},
+	{0x3d400020, 0x203},
+	{0x3d400024, 0x3e800},
+	{0x3d400064, 0x6100e0},
+	{0x3d4000d0, 0xc003061c},
+	{0x3d4000d4, 0x9e0000},
+	{0x3d4000dc, 0xd4002d},
+	{0x3d4000e0, 0x310008},
+	{0x3d4000e8, 0x66004a},
+	{0x3d4000ec, 0x16004a},
+	{0x3d400100, 0x1a201b22},
+	{0x3d400104, 0x60633},
+	{0x3d40010c, 0xc0c000},
+	{0x3d400110, 0xf04080f},
+	{0x3d400114, 0x2040c0c},
+	{0x3d400118, 0x1010007},
+	{0x3d40011c, 0x401},
+	{0x3d400130, 0x20600},
+	{0x3d400134, 0xc100002},
+	{0x3d400138, 0xe6},
+	{0x3d400144, 0xa00050},
+	{0x3d400180, 0xc3200018},
+	{0x3d400184, 0x28061a8},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x497820a},
+	{0x3d400194, 0x80303},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001b4, 0x170a},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x1},
+	{0x3d4000f4, 0x639},
+	{0x3d400108, 0x70e1617},
+	{0x3d400200, 0x15},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0x48080707},
+	{0x3d402020, 0x1},
+	{0x3d402024, 0xd0c0},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0x14002f},
+	{0x3d4020dc, 0x940009},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004a},
+	{0x3d4020ec, 0x16004a},
+	{0x3d402100, 0xb070508},
+	{0x3d402104, 0x3040b},
+	{0x3d402108, 0x305090c},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x4040204},
+	{0x3d402114, 0x2030303},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x31},
+	{0x3d402144, 0x220011},
+	{0x3d402180, 0xc0a70006},
+	{0x3d402190, 0x3858202},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x502},
+	{0x3d400244, 0x0},
+	{0x3d400250, 0x29001505},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x5900575b},
+	{0x3d400264, 0x90000096},
+	{0x3d40026c, 0x1000012c},
+	{0x3d400300, 0x16},
+	{0x3d400304, 0x0},
+	{0x3d40030c, 0x0},
+	{0x3d400320, 0x1},
+	{0x3d40036c, 0x11},
+	{0x3d400400, 0x111},
+	{0x3d400404, 0x10f3},
+	{0x3d400408, 0x72ff},
+	{0x3d400490, 0x1},
+	{0x3d400494, 0xe00},
+	{0x3d400498, 0x62ffff},
+	{0x3d40049c, 0xe00},
+	{0x3d4004a0, 0xffff},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x2},
+	{0x110a3, 0x3},
+	{0x110a4, 0x4},
+	{0x110a5, 0x5},
+	{0x110a6, 0x6},
+	{0x110a7, 0x7},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x2},
+	{0x120a3, 0x3},
+	{0x120a4, 0x4},
+	{0x120a5, 0x5},
+	{0x120a6, 0x6},
+	{0x120a7, 0x7},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x20110, 0x2},
+	{0x20111, 0x3},
+	{0x20112, 0x4},
+	{0x20113, 0x5},
+	{0x20114, 0x0},
+	{0x20115, 0x1},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x19},
+	{0x1200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x1},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x3},
+	{0x120056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x43, 0x63},
+	{0x1043, 0x63},
+	{0x2043, 0x63},
+	{0x3043, 0x63},
+	{0x4043, 0x63},
+	{0x5043, 0x63},
+	{0x6043, 0x63},
+	{0x7043, 0x63},
+	{0x8043, 0x63},
+	{0x9043, 0x63},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x320},
+	{0x120008, 0xa7},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x200f0, 0x0},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5555},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x200c7, 0x80},
+	{0x1200c7, 0x80},
+	{0x200ca, 0x106},
+	{0x1200ca, 0x106},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xc80},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x310},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x1},
+	{0x54003, 0x29c},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x310},
+	{0x54019, 0x994},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x994},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0x9400},
+	{0x54033, 0x3109},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0x9400},
+	{0x54039, 0x3109},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xc80},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x310},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x64},
+	{0x2000c, 0xc8},
+	{0x2000d, 0x7d0},
+	{0x2000e, 0x2c},
+	{0x12000b, 0x14},
+	{0x12000c, 0x29},
+	{0x12000d, 0x1a1},
+	{0x12000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_3gb = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
+
diff --git a/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c b/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c
new file mode 100644
index 000000000..b1d1c5223
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c
@@ -0,0 +1,1734 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa3080020},
+	{0x3d400028, 0x0},
+	{0x3d400020, 0x203},
+	{0x3d400024, 0x3e800},
+	{0x3d400064, 0x6100e0},
+	{0x3d4000d0, 0xc003061c},
+	{0x3d4000d4, 0x9e0000},
+	{0x3d4000dc, 0xd4002d},
+	{0x3d4000e0, 0x310008},
+	{0x3d4000e8, 0x66004a},
+	{0x3d4000ec, 0x16004a},
+	{0x3d400100, 0x1a201b22},
+	{0x3d400104, 0x60633},
+	{0x3d40010c, 0xc0c000},
+	{0x3d400110, 0xf04080f},
+	{0x3d400114, 0x2040c0c},
+	{0x3d400118, 0x1010007},
+	{0x3d40011c, 0x401},
+	{0x3d400130, 0x20600},
+	{0x3d400134, 0xc100002},
+	{0x3d400138, 0xe6},
+	{0x3d400144, 0xa00050},
+	{0x3d400180, 0xc3200018},
+	{0x3d400184, 0x28061a8},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x497820a},
+	{0x3d400194, 0x80303},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001b4, 0x170a},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x1},
+	{0x3d4000f4, 0x639},
+	{0x3d400108, 0x70e1617},
+	{0x3d400200, 0x17},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0x7070707},
+	{0x3d402020, 0x1},
+	{0x3d402024, 0xd0c0},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0x14002f},
+	{0x3d4020dc, 0x940009},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004a},
+	{0x3d4020ec, 0x16004a},
+	{0x3d402100, 0xb070508},
+	{0x3d402104, 0x3040b},
+	{0x3d402108, 0x305090c},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x4040204},
+	{0x3d402114, 0x2030303},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x31},
+	{0x3d402144, 0x220011},
+	{0x3d402180, 0xc0a70006},
+	{0x3d402190, 0x3858202},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x502},
+	{0x3d400244, 0x0},
+	{0x3d400250, 0x29001505},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x5900575b},
+	{0x3d400264, 0x90000096},
+	{0x3d40026c, 0x1000012c},
+	{0x3d400300, 0x16},
+	{0x3d400304, 0x0},
+	{0x3d40030c, 0x0},
+	{0x3d400320, 0x1},
+	{0x3d40036c, 0x11},
+	{0x3d400400, 0x111},
+	{0x3d400404, 0x10f3},
+	{0x3d400408, 0x72ff},
+	{0x3d400490, 0x1},
+	{0x3d400494, 0xe00},
+	{0x3d400498, 0x62ffff},
+	{0x3d40049c, 0xe00},
+	{0x3d4004a0, 0xffff},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x2},
+	{0x110a3, 0x3},
+	{0x110a4, 0x4},
+	{0x110a5, 0x5},
+	{0x110a6, 0x6},
+	{0x110a7, 0x7},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x2},
+	{0x120a3, 0x3},
+	{0x120a4, 0x4},
+	{0x120a5, 0x5},
+	{0x120a6, 0x6},
+	{0x120a7, 0x7},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x20110, 0x2},
+	{0x20111, 0x3},
+	{0x20112, 0x4},
+	{0x20113, 0x5},
+	{0x20114, 0x0},
+	{0x20115, 0x1},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x19},
+	{0x1200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x1},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x3},
+	{0x120056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x43, 0x63},
+	{0x1043, 0x63},
+	{0x2043, 0x63},
+	{0x3043, 0x63},
+	{0x4043, 0x63},
+	{0x5043, 0x63},
+	{0x6043, 0x63},
+	{0x7043, 0x63},
+	{0x8043, 0x63},
+	{0x9043, 0x63},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x320},
+	{0x120008, 0xa7},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x200f0, 0x0},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5555},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x200c7, 0x80},
+	{0x1200c7, 0x80},
+	{0x200ca, 0x106},
+	{0x1200ca, 0x106},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xc80},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x310},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x1},
+	{0x54003, 0x29c},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x310},
+	{0x54019, 0x994},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x994},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0x9400},
+	{0x54033, 0x3109},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0x9400},
+	{0x54039, 0x3109},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xc80},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x310},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x3},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x64},
+	{0x2000c, 0xc8},
+	{0x2000d, 0x7d0},
+	{0x2000e, 0x2c},
+	{0x12000b, 0x14},
+	{0x12000c, 0x29},
+	{0x12000d, 0x1a1},
+	{0x12000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_4gb = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
+
diff --git a/roms/u-boot/board/technexion/pico-imx8mq/pico-imx8mq.c b/roms/u-boot/board/technexion/pico-imx8mq/pico-imx8mq.c
new file mode 100644
index 000000000..951e3e198
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx8mq/pico-imx8mq.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <linux/delay.h>
+#include <spl.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+	int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
+
+	if (ddr_size == 0x4) {
+		*size = 0x100000000;
+	} else if (ddr_size == 0x3) {
+		*size = 0xc0000000;
+	} else if (ddr_size == 0x2) {
+		*size = 0x80000000;
+	} else if (ddr_size == 0x1) {
+		*size = 0x40000000;
+	} else {
+		printf("Unknown DDR type!!!\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
+#define FEC_PWR_PAD IMX_GPIO_NR(1, 0)
+static iomux_v3_cfg_t const fec1_pads[] = {
+	/* Reset */
+	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* Power */
+	IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+
+	gpio_request(IMX_GPIO_NR(1, 0), "fec1_pwr");
+	gpio_direction_output(IMX_GPIO_NR(1, 0), 1);
+	udelay(500);
+
+	gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
+	gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
+	udelay(500);
+	gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	setup_iomux_fec();
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_rev", "iMX8MQ");
+#endif
+	return 0;
+}
diff --git a/roms/u-boot/board/technexion/pico-imx8mq/spl.c b/roms/u-boot/board/technexion/pico-imx8mq/spl.c
new file mode 100644
index 000000000..8b853a914
--- /dev/null
+++ b/roms/u-boot/board/technexion/pico-imx8mq/spl.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <linux/delay.h>
+#include <errno.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <spl.h>
+
+#include "lpddr4_timing.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_DET_1		IMX_GPIO_NR(3, 11)
+#define DDR_DET_2		IMX_GPIO_NR(3, 12)
+#define DDR_DET_3		IMX_GPIO_NR(3, 13)
+
+static iomux_v3_cfg_t const verdet_pads[] = {
+	IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*
+ * DDR_DET_1    DDR_DET_2   DDR_DET_3
+ *    0            0            1       4G LPDDR4
+ *    1            1            1       3G LPDDR4
+ *    1            1            0       2G LPDDR4
+ *    1            0            1       1G LPDDR4
+ */
+static void spl_dram_init(void)
+{
+	struct dram_timing_info *dram_timing;
+	u8 ddr = 0, size;
+
+	imx_iomux_v3_setup_multiple_pads(verdet_pads, ARRAY_SIZE(verdet_pads));
+
+	gpio_request(DDR_DET_1, "ddr_det_1");
+	gpio_direction_input(DDR_DET_1);
+	gpio_request(DDR_DET_2, "ddr_det_2");
+	gpio_direction_input(DDR_DET_2);
+	gpio_request(DDR_DET_3, "ddr_det_3");
+	gpio_direction_input(DDR_DET_3);
+
+	ddr |= !!gpio_get_value(DDR_DET_3) << 0;
+	ddr |= !!gpio_get_value(DDR_DET_2) << 1;
+	ddr |= !!gpio_get_value(DDR_DET_1) << 2;
+
+	switch (ddr) {
+	case 0x1:
+		size = 4;
+		dram_timing = &dram_timing_4gb;
+		break;
+	case 0x7:
+		size = 3;
+		dram_timing = &dram_timing_3gb;
+		break;
+	case 0x6:
+		size = 2;
+		dram_timing = &dram_timing_2gb;
+		break;
+	case 0x5:
+		size = 1;
+		dram_timing = &dram_timing_1gb;
+		break;
+	default:
+		puts("Unknown DDR type!!!\n");
+		return;
+	}
+
+	printf("%s: LPDDR4 %d GiB\n", __func__, size);
+	ddr_init(dram_timing);
+	writel(size, M4_BOOTROM_BASE_ADDR);
+}
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	init_clk_usdhc(0);
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+	imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+	gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+	gpio_direction_output(USDHC1_PWR_GPIO, 0);
+	udelay(500);
+	gpio_direction_output(USDHC1_PWR_GPIO, 1);
+	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	if (ret)
+		return ret;
+
+	init_clk_usdhc(1);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+	gpio_direction_output(USDHC2_PWR_GPIO, 0);
+	udelay(500);
+	gpio_direction_output(USDHC2_PWR_GPIO, 1);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/terasic/de0-nano-soc/MAINTAINERS b/roms/u-boot/board/terasic/de0-nano-soc/MAINTAINERS
new file mode 100644
index 000000000..7f4cf1e7f
--- /dev/null
+++ b/roms/u-boot/board/terasic/de0-nano-soc/MAINTAINERS
@@ -0,0 +1,5 @@
+SOCFPGA ATLAS BOARD
+M:	Dinh Nguyen <dinguyen@kernel.org>
+S:	Maintained
+F:	include/configs/socfpga_de0_nano_soc.h
+F:	configs/socfpga_de0_nano_soc_defconfig
diff --git a/roms/u-boot/board/terasic/de0-nano-soc/Makefile b/roms/u-boot/board/terasic/de0-nano-soc/Makefile
new file mode 100644
index 000000000..e1c8a6b3c
--- /dev/null
+++ b/roms/u-boot/board/terasic/de0-nano-soc/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/terasic/de0-nano-soc/qts/iocsr_config.h b/roms/u-boot/board/terasic/de0-nano-soc/qts/iocsr_config.h
new file mode 100644
index 000000000..6ff5bd571
--- /dev/null
+++ b/roms/u-boot/board/terasic/de0-nano-soc/qts/iocsr_config.h
@@ -0,0 +1,657 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00020080,
+	0x18060000,
+	0x08000000,
+	0x00018020,
+	0x00000000,
+	0x00004000,
+	0x00010040,
+	0x04010000,
+	0x04000000,
+	0x00000010,
+	0x00004010,
+	0x00002000,
+	0x00020000,
+	0x02008000,
+	0x02000000,
+	0x00000008,
+	0x00002008,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00100000,
+	0x10040000,
+	0x100000C0,
+	0x00000040,
+	0x00010040,
+	0x00008000,
+	0x00060180,
+	0x20000000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x00010040,
+	0x10000000,
+	0x04000000,
+	0x00000010,
+	0x00004010,
+	0x00002000,
+	0x00020000,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x00010000,
+	0x04000000,
+	0x00000000,
+	0x00000010,
+	0x00004000,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000008,
+	0x00002000,
+	0x00000400,
+	0x00000000,
+	0x00401000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00600802,
+	0x00000000,
+	0x80200000,
+	0x80000600,
+	0x00000200,
+	0x00000100,
+	0x00300401,
+	0xC0100400,
+	0x40100000,
+	0x40000300,
+	0x000C0100,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x300C0300,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x0C0300C0,
+	0x00008000,
+	0x00080000,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00020000,
+	0x00004000,
+	0x200300C0,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00002000,
+	0x10018060,
+	0x06018000,
+	0x06000000,
+	0x00010018,
+	0x00006018,
+	0x00001000,
+	0x00010000,
+	0x00000000,
+	0x03000000,
+	0x0000800C,
+	0x00C01004,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x4D034071,
+	0x1A681A03,
+	0x806180D0,
+	0x34071C06,
+	0x01A034D0,
+	0x380D0000,
+	0x0820680E,
+	0x034D0340,
+	0xD000001A,
+	0x0680E380,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x4D034071,
+	0x1A681A03,
+	0x806180D0,
+	0x34071C06,
+	0x01A00040,
+	0x180D0002,
+	0x71C06806,
+	0x034D0340,
+	0xD01A681A,
+	0x06806180,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xD32CA3D6,
+	0xF551451E,
+	0x034CD348,
+	0x821A0000,
+	0x0000D000,
+	0x030C0680,
+	0xD659647A,
+	0x1ED32CA3,
+	0x48F55145,
+	0x00034CD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x0C864000,
+	0x59647A03,
+	0x932CA3DE,
+	0xF651451E,
+	0x035CD348,
+	0x821A0041,
+	0x0000D000,
+	0x00000680,
+	0xDE59647A,
+	0x1ED32CA3,
+	0x48F55145,
+	0x00035492,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x0C864000,
+	0x59647A03,
+	0xD32CA3DE,
+	0xF551451E,
+	0x035CB2C8,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDE59647A,
+	0x1ED2AAA3,
+	0xC8F55965,
+	0x00035CB2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xD32CA3DE,
+	0xF551451E,
+	0x035CD348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDE59647A,
+	0x1ED32CA3,
+	0x48F55145,
+	0x00035CD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/de0-nano-soc/qts/pinmux_config.h b/roms/u-boot/board/terasic/de0-nano-soc/qts/pinmux_config.h
new file mode 100644
index 000000000..3058ee3a5
--- /dev/null
+++ b/roms/u-boot/board/terasic/de0-nano-soc/qts/pinmux_config.h
@@ -0,0 +1,219 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+/* pin MUX configuration data */
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	1, /* GENERALIO15 */
+	1, /* GENERALIO16 */
+	1, /* GENERALIO17 */
+	1, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	0, /* MIXED1IO15 */
+	0, /* MIXED1IO16 */
+	0, /* MIXED1IO17 */
+	0, /* MIXED1IO18 */
+	0, /* MIXED1IO19 */
+	0, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/de0-nano-soc/qts/pll_config.h b/roms/u-boot/board/terasic/de0-nano-soc/qts/pll_config.h
new file mode 100644
index 000000000..68dc3bc27
--- /dev/null
+++ b/roms/u-boot/board/terasic/de0-nano-soc/qts/pll_config.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef _PRELOADER_PLL_CONFIG_H_
+#define _PRELOADER_PLL_CONFIG_H_
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 3613281
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+
+#endif /* _PRELOADER_PLL_CONFIG_H_ */
+
diff --git a/roms/u-boot/board/terasic/de0-nano-soc/qts/sdram_config.h b/roms/u-boot/board/terasic/de0-nano-soc/qts/sdram_config.h
new file mode 100644
index 000000000..0504dd688
--- /dev/null
+++ b/roms/u-boot/board/terasic/de0-nano-soc/qts/sdram_config.h
@@ -0,0 +1,344 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+#ifndef __SDRAM_CONFIG_H
+#define __SDRAM_CONFIG_H
+
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED	0x1
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED	0x1
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED	0x3
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x311
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1   0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2   0x10
+#define RW_MGR_ACTIVATE_1       0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE 0x49
+#define RW_MGR_GUARANTEED_READ  0x4C
+#define RW_MGR_GUARANTEED_READ_CONT     0x54
+#define RW_MGR_GUARANTEED_WRITE 0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0   0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1   0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2   0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3   0x1D
+#define RW_MGR_IDLE     0x00
+#define RW_MGR_IDLE_LOOP1       0x7B
+#define RW_MGR_IDLE_LOOP2       0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0       0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0       0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0        0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA   0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS    0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP    0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT   0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1   0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0     0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA        0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT        0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1        0x35
+#define RW_MGR_MRS0_DLL_RESET   0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR      0x08
+#define RW_MGR_MRS0_USER        0x07
+#define RW_MGR_MRS0_USER_MIRR   0x0C
+#define RW_MGR_MRS1     0x03
+#define RW_MGR_MRS1_MIRR        0x09
+#define RW_MGR_MRS2     0x04
+#define RW_MGR_MRS2_MIRR        0x0A
+#define RW_MGR_MRS3     0x05
+#define RW_MGR_MRS3_MIRR        0x0B
+#define RW_MGR_PRECHARGE_ALL    0x12
+#define RW_MGR_READ_B2B 0x59
+#define RW_MGR_READ_B2B_WAIT1   0x61
+#define RW_MGR_READ_B2B_WAIT2   0x6B
+#define RW_MGR_REFRESH_ALL      0x14
+#define RW_MGR_RETURN   0x01
+#define RW_MGR_SGLE_READ        0x7D
+#define RW_MGR_ZQCL     0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO  1
+#define CALIB_LFIFO_OFFSET      8
+#define CALIB_VFIFO_OFFSET      6
+#define ENABLE_SUPER_QUICK_CALIBRATION  0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP  25
+#define IO_DELAY_PER_OPA_TAP    312
+#define IO_DLL_CHAIN_LENGTH     8
+#define IO_DQDQS_OUT_PHASE_MAX  0
+#define IO_DQS_EN_DELAY_MAX     31
+#define IO_DQS_EN_DELAY_OFFSET  0
+#define IO_DQS_EN_PHASE_MAX     7
+#define IO_DQS_IN_DELAY_MAX     31
+#define IO_DQS_IN_RESERVE       4
+#define IO_DQS_OUT_RESERVE      4
+#define IO_IO_IN_DELAY_MAX      31
+#define IO_IO_OUT1_DELAY_MAX    31
+#define IO_IO_OUT2_DELAY_MAX    0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS  0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE    16
+#define REG_FILE_INIT_SEQ_SIGNATURE     0x5555048d
+#define RW_MGR_MEM_ADDRESS_MIRRORING    0
+#define RW_MGR_MEM_DATA_MASK_WIDTH      4
+#define RW_MGR_MEM_DATA_WIDTH   32
+#define RW_MGR_MEM_DQ_PER_READ_DQS      8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS     8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH    4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH   4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM        1
+#define RW_MGR_MEM_NUMBER_OF_RANKS      1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS  1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define TINIT_CNTR0_VAL 99
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TRESET_CNTR0_VAL        99
+#define TRESET_CNTR1_VAL        99
+#define TRESET_CNTR2_VAL        10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080431,
+	0x10080530,
+	0x10090044,
+	0x100a0010,
+	0x100b0000,
+	0x10380400,
+	0x10080449,
+	0x100804c8,
+	0x100a0024,
+	0x10090008,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+#endif /*#ifndef__SDRAM_CONFIG_H */
diff --git a/roms/u-boot/board/terasic/de0-nano-soc/socfpga.c b/roms/u-boot/board/terasic/de0-nano-soc/socfpga.c
new file mode 100644
index 000000000..48bfe3295
--- /dev/null
+++ b/roms/u-boot/board/terasic/de0-nano-soc/socfpga.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+#include <common.h>
diff --git a/roms/u-boot/board/terasic/de1-soc/MAINTAINERS b/roms/u-boot/board/terasic/de1-soc/MAINTAINERS
new file mode 100644
index 000000000..bd7a8d5f4
--- /dev/null
+++ b/roms/u-boot/board/terasic/de1-soc/MAINTAINERS
@@ -0,0 +1,5 @@
+DE1-SoC BOARD
+M:	Anatolij Gustschin <agust@denx.de>
+S:	Maintained
+F:	include/configs/socfpga_de1_soc.h
+F:	configs/socfpga_de1_soc_defconfig
diff --git a/roms/u-boot/board/terasic/de1-soc/Makefile b/roms/u-boot/board/terasic/de1-soc/Makefile
new file mode 100644
index 000000000..e1c8a6b3c
--- /dev/null
+++ b/roms/u-boot/board/terasic/de1-soc/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/terasic/de1-soc/qts/iocsr_config.h b/roms/u-boot/board/terasic/de1-soc/qts/iocsr_config.h
new file mode 100644
index 000000000..c65183ed8
--- /dev/null
+++ b/roms/u-boot/board/terasic/de1-soc/qts/iocsr_config.h
@@ -0,0 +1,659 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00000000,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00020000,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00100000,
+	0x300C0000,
+	0x300000C0,
+	0x000000C0,
+	0x000300C0,
+	0x00008000,
+	0x00060180,
+	0x20000000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x000300C0,
+	0x10000000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x01800000,
+	0x00000006,
+	0x00002000,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x300C0300,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x000300C0,
+	0x00008000,
+	0x00080000,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00020000,
+	0x00004000,
+	0x200300C0,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00002000,
+	0x10018060,
+	0x06018000,
+	0x06000000,
+	0x00010018,
+	0x00006018,
+	0x00001000,
+	0x0000C030,
+	0x00000000,
+	0x03000000,
+	0x0000800C,
+	0x00C0300C,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680208,
+	0x41034051,
+	0x02081A00,
+	0x802080D0,
+	0x34010406,
+	0x01A02490,
+	0x080D0000,
+	0x51406802,
+	0x00410340,
+	0xD000001A,
+	0x06802080,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680C30,
+	0x49034010,
+	0x12481A02,
+	0x802080D0,
+	0x34051406,
+	0x01A00040,
+	0x080D0002,
+	0x51406802,
+	0x02490340,
+	0xD012481A,
+	0x06802080,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xE3CF23DA,
+	0xF796591E,
+	0x0344E388,
+	0x821A0000,
+	0x0000D000,
+	0x01040680,
+	0xD271C47A,
+	0x1EE3CF23,
+	0x88F79659,
+	0x000344E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xA3CF23DA,
+	0xF796591E,
+	0x0344E388,
+	0x821A028A,
+	0x0000D000,
+	0x00000680,
+	0xD271C47A,
+	0x1EA2CB23,
+	0x88F79A69,
+	0x000344E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x04864000,
+	0x69A47A01,
+	0x9228A3D6,
+	0xF456591E,
+	0x03549248,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD669A47A,
+	0x1EE3CF23,
+	0x48F45659,
+	0x00035492,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x08864000,
+	0x71C47A02,
+	0xA2CB23D2,
+	0xF796591E,
+	0x0344A288,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDA49247A,
+	0x1EE3CF23,
+	0x88F79659,
+	0x000344E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/de1-soc/qts/pinmux_config.h b/roms/u-boot/board/terasic/de1-soc/qts/pinmux_config.h
new file mode 100644
index 000000000..c75635005
--- /dev/null
+++ b/roms/u-boot/board/terasic/de1-soc/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	1, /* GENERALIO15 */
+	1, /* GENERALIO16 */
+	1, /* GENERALIO17 */
+	1, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/de1-soc/qts/pll_config.h b/roms/u-boot/board/terasic/de1-soc/qts/pll_config.h
new file mode 100644
index 000000000..4544f9269
--- /dev/null
+++ b/roms/u-boot/board/terasic/de1-soc/qts/pll_config.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/de1-soc/qts/sdram_config.h b/roms/u-boot/board/terasic/de1-soc/qts/sdram_config.h
new file mode 100644
index 000000000..c60426f2f
--- /dev/null
+++ b/roms/u-boot/board/terasic/de1-soc/qts/sdram_config.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			18
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		200
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	8
+#define CALIB_VFIFO_OFFSET	6
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x5555048d
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080431,
+	0x10080530,
+	0x10090044,
+	0x100a0010,
+	0x100b0000,
+	0x10380400,
+	0x10080449,
+	0x100804c8,
+	0x100a0024,
+	0x10090008,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/de1-soc/socfpga.c b/roms/u-boot/board/terasic/de1-soc/socfpga.c
new file mode 100644
index 000000000..22fbee40a
--- /dev/null
+++ b/roms/u-boot/board/terasic/de1-soc/socfpga.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+#include <common.h>
+#include <spl.h>
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+
+	switch (spl_boot_list[0]) {
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[0] = BOOT_DEVICE_MMC1;
+		spl_boot_list[1] = BOOT_DEVICE_UART;
+		break;
+	}
+}
diff --git a/roms/u-boot/board/terasic/de10-nano/MAINTAINERS b/roms/u-boot/board/terasic/de10-nano/MAINTAINERS
new file mode 100644
index 000000000..f4dd0dff3
--- /dev/null
+++ b/roms/u-boot/board/terasic/de10-nano/MAINTAINERS
@@ -0,0 +1,5 @@
+DE10-NANO BOARD
+M:	Dalon Westergreen <dwesterg@gmail.com>
+S:	Maintained
+F:	include/configs/socfpga_de10_nano.h
+F:	configs/socfpga_de10_nano_defconfig
diff --git a/roms/u-boot/board/terasic/de10-nano/Makefile b/roms/u-boot/board/terasic/de10-nano/Makefile
new file mode 100644
index 000000000..2cf924084
--- /dev/null
+++ b/roms/u-boot/board/terasic/de10-nano/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2017, Intel Corporation
+#
+#
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/terasic/de10-nano/qts/iocsr_config.h b/roms/u-boot/board/terasic/de10-nano/qts/iocsr_config.h
new file mode 100644
index 000000000..bc5b7a07c
--- /dev/null
+++ b/roms/u-boot/board/terasic/de10-nano/qts/iocsr_config.h
@@ -0,0 +1,659 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00020080,
+	0x18060000,
+	0x08000000,
+	0x00018020,
+	0x00000000,
+	0x00004000,
+	0x00010040,
+	0x04010000,
+	0x04000000,
+	0x00000010,
+	0x00004010,
+	0x00002000,
+	0x00020000,
+	0x02008000,
+	0x02000000,
+	0x00000008,
+	0x00002008,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00100000,
+	0x10040000,
+	0x100000C0,
+	0x00000040,
+	0x00010040,
+	0x00008000,
+	0x00060180,
+	0x20000000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x00010040,
+	0x10000000,
+	0x04000000,
+	0x00000010,
+	0x00004010,
+	0x00002000,
+	0x00020000,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x00010000,
+	0x04000000,
+	0x00000000,
+	0x00000010,
+	0x00004000,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000008,
+	0x00002000,
+	0x00000400,
+	0x00000000,
+	0x00401000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00600802,
+	0x00000000,
+	0x80200000,
+	0x80000600,
+	0x00000200,
+	0x00000100,
+	0x00300401,
+	0xC0100400,
+	0x40100000,
+	0x40000300,
+	0x000C0100,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x300C0300,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x0C0300C0,
+	0x00008000,
+	0x00080000,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00020000,
+	0x00004000,
+	0x200300C0,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00002000,
+	0x10018060,
+	0x06018000,
+	0x06000000,
+	0x00010018,
+	0x00006018,
+	0x00001000,
+	0x00010000,
+	0x00000000,
+	0x03000000,
+	0x0000800C,
+	0x00C01004,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x45034071,
+	0x0A281A01,
+	0x806180D0,
+	0x34071C06,
+	0x01A034D0,
+	0x180D0000,
+	0x71C06806,
+	0x01450340,
+	0xD000001A,
+	0x0680E380,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x45034071,
+	0x0A281A01,
+	0x806180D0,
+	0x34071C06,
+	0x01A00040,
+	0x180D0002,
+	0x71C06806,
+	0x01450340,
+	0xD00A281A,
+	0x06806180,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x0C864000,
+	0x79E47A03,
+	0xCAAAA3DD,
+	0xF6D5551E,
+	0x0352D348,
+	0x821A0000,
+	0x0000D000,
+	0x030C0680,
+	0xD559647A,
+	0x1ECAAAA3,
+	0xC8F6D965,
+	0x00034AB2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x0C864000,
+	0x79E47A03,
+	0x8B2CA3DD,
+	0xF6D9651E,
+	0x034AB2C8,
+	0x821A0041,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8B2CA3,
+	0xC8F6D965,
+	0x00034AB2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8AAAA3D5,
+	0xF6D9651E,
+	0x034AB2C8,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8B2CA3,
+	0xC8F6D965,
+	0x00034AB2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8B2CA3D5,
+	0xF6D9651E,
+	0x0352D348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8B2CA3,
+	0x48F6D965,
+	0x000352D3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/de10-nano/qts/pinmux_config.h b/roms/u-boot/board/terasic/de10-nano/qts/pinmux_config.h
new file mode 100644
index 000000000..6a9c41502
--- /dev/null
+++ b/roms/u-boot/board/terasic/de10-nano/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	1, /* GENERALIO15 */
+	1, /* GENERALIO16 */
+	1, /* GENERALIO17 */
+	1, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	0, /* MIXED1IO15 */
+	0, /* MIXED1IO16 */
+	0, /* MIXED1IO17 */
+	0, /* MIXED1IO18 */
+	0, /* MIXED1IO19 */
+	0, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	1, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	1, /* I2C3USEFPGA */
+	1, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	1 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/de10-nano/qts/pll_config.h b/roms/u-boot/board/terasic/de10-nano/qts/pll_config.h
new file mode 100644
index 000000000..854936b2a
--- /dev/null
+++ b/roms/u-boot/board/terasic/de10-nano/qts/pll_config.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 3125000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/de10-nano/qts/sdram_config.h b/roms/u-boot/board/terasic/de10-nano/qts/sdram_config.h
new file mode 100644
index 000000000..26910ef34
--- /dev/null
+++ b/roms/u-boot/board/terasic/de10-nano/qts/sdram_config.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x1FF
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x10441
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x78
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	8
+#define CALIB_VFIFO_OFFSET	6
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x555504a1
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080431,
+	0x10080530,
+	0x10090044,
+	0x100a0010,
+	0x100b0000,
+	0x10380400,
+	0x10080449,
+	0x100804c8,
+	0x100a0024,
+	0x10090008,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/de10-nano/socfpga.c b/roms/u-boot/board/terasic/de10-nano/socfpga.c
new file mode 100644
index 000000000..f9173f192
--- /dev/null
+++ b/roms/u-boot/board/terasic/de10-nano/socfpga.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, Intel Corporation
+ */
+#include <common.h>
diff --git a/roms/u-boot/board/terasic/sockit/MAINTAINERS b/roms/u-boot/board/terasic/sockit/MAINTAINERS
new file mode 100644
index 000000000..792f18474
--- /dev/null
+++ b/roms/u-boot/board/terasic/sockit/MAINTAINERS
@@ -0,0 +1,5 @@
+SOCKIT BOARD
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+F:	include/configs/socfpga_sockit.h
+F:	configs/socfpga_sockit_defconfig
diff --git a/roms/u-boot/board/terasic/sockit/Makefile b/roms/u-boot/board/terasic/sockit/Makefile
new file mode 100644
index 000000000..e1c8a6b3c
--- /dev/null
+++ b/roms/u-boot/board/terasic/sockit/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+
+obj-y	:= socfpga.o
diff --git a/roms/u-boot/board/terasic/sockit/qts/iocsr_config.h b/roms/u-boot/board/terasic/sockit/qts/iocsr_config.h
new file mode 100644
index 000000000..b8cb5f08a
--- /dev/null
+++ b/roms/u-boot/board/terasic/sockit/qts/iocsr_config.h
@@ -0,0 +1,659 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00000000,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00018060,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00100000,
+	0x300C0000,
+	0x300000C0,
+	0x000000C0,
+	0x000300C0,
+	0x00008000,
+	0x00080000,
+	0x20000000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x000300C0,
+	0x10000000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x01800000,
+	0x00000006,
+	0x00002000,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x300C0300,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x0C0300C0,
+	0x00008000,
+	0x18060180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00018060,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x00000030,
+	0x00000000,
+	0x0300C030,
+	0x00002000,
+	0x00018060,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+	0x0000C030,
+	0x00000000,
+	0x03000000,
+	0x0000000C,
+	0x00C0300C,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xE0680B2C,
+	0x20834038,
+	0x11441A00,
+	0x80B2C0D0,
+	0x34038E06,
+	0x01A00208,
+	0x2C0D0000,
+	0x38E0680B,
+	0x00208340,
+	0xD000001A,
+	0x0680B2C0,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xE0680B2C,
+	0x20834038,
+	0x11441A00,
+	0x80B2C0D0,
+	0x34038E06,
+	0x01A00040,
+	0x2C0D0002,
+	0x38E0680B,
+	0x00208340,
+	0xD001041A,
+	0x0680B2C0,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xABCF23D7,
+	0xF7DE791E,
+	0x0356E388,
+	0x821A0000,
+	0x0000D000,
+	0x05960680,
+	0xD749247A,
+	0x1EABCF23,
+	0x88F7DE79,
+	0x000356E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xABCF23D7,
+	0xF7DE791E,
+	0x0356E388,
+	0x821A01C7,
+	0x0000D000,
+	0x00000680,
+	0xD749247A,
+	0x1EABCF23,
+	0x88F7DE79,
+	0x000356E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xABCF23D7,
+	0xF7DE791E,
+	0x0356E388,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD749247A,
+	0x1EABCF23,
+	0x88F7DE79,
+	0x000356E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xABCF23D7,
+	0xF7DE791E,
+	0x0356E388,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD749247A,
+	0x1EABCF23,
+	0x88F7DE79,
+	0x000356E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/sockit/qts/pinmux_config.h b/roms/u-boot/board/terasic/sockit/qts/pinmux_config.h
new file mode 100644
index 000000000..f8e458f3d
--- /dev/null
+++ b/roms/u-boot/board/terasic/sockit/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	0, /* GENERALIO7 */
+	0, /* GENERALIO8 */
+	3, /* GENERALIO9 */
+	3, /* GENERALIO10 */
+	3, /* GENERALIO11 */
+	3, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	1, /* GENERALIO15 */
+	1, /* GENERALIO16 */
+	1, /* GENERALIO17 */
+	1, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/sockit/qts/pll_config.h b/roms/u-boot/board/terasic/sockit/qts/pll_config.h
new file mode 100644
index 000000000..f6ffa0865
--- /dev/null
+++ b/roms/u-boot/board/terasic/sockit/qts/pll_config.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/sockit/qts/sdram_config.h b/roms/u-boot/board/terasic/sockit/qts/sdram_config.h
new file mode 100644
index 000000000..96cc35703
--- /dev/null
+++ b/roms/u-boot/board/terasic/sockit/qts/sdram_config.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			11
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			12
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			104
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x1FF
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	12
+#define CALIB_VFIFO_OFFSET	10
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x5555048c
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080471,
+	0x10080570,
+	0x10090006,
+	0x100a0218,
+	0x100b0000,
+	0x10380400,
+	0x10080469,
+	0x100804e8,
+	0x100a0006,
+	0x10090218,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/roms/u-boot/board/terasic/sockit/socfpga.c b/roms/u-boot/board/terasic/sockit/socfpga.c
new file mode 100644
index 000000000..48bfe3295
--- /dev/null
+++ b/roms/u-boot/board/terasic/sockit/socfpga.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+#include <common.h>
diff --git a/roms/u-boot/board/theadorable/MAINTAINERS b/roms/u-boot/board/theadorable/MAINTAINERS
new file mode 100644
index 000000000..1e8df93d3
--- /dev/null
+++ b/roms/u-boot/board/theadorable/MAINTAINERS
@@ -0,0 +1,6 @@
+THEADORABLE BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/theadorable/
+F:	include/configs/theadorable.h
+F:	configs/theadorable_debug_defconfig
diff --git a/roms/u-boot/board/theadorable/Makefile b/roms/u-boot/board/theadorable/Makefile
new file mode 100644
index 000000000..b85faa676
--- /dev/null
+++ b/roms/u-boot/board/theadorable/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+
+obj-y	:= theadorable.o
+obj-y	+= fpga.o
diff --git a/roms/u-boot/board/theadorable/fpga.c b/roms/u-boot/board/theadorable/fpga.c
new file mode 100644
index 000000000..bc8379ccc
--- /dev/null
+++ b/roms/u-boot/board/theadorable/fpga.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <altera.h>
+#include <errno.h>
+#include <log.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-mvebu/spi.h>
+#include "theadorable.h"
+
+/*
+ * FPGA programming support
+ */
+static int fpga_pre_fn(int cookie)
+{
+	int gpio_config = COOKIE2CONFIG(cookie);
+	int gpio_done = COOKIE2DONE(cookie);
+	int ret;
+
+	debug("%s (%d): cookie=%08x gpio_config=%d gpio_done=%d\n",
+	      __func__, __LINE__, cookie, gpio_config, gpio_done);
+
+	/* Configure config pin */
+	/* Set to output */
+	ret = gpio_request(gpio_config, "CONFIG");
+	if (ret < 0)
+		return ret;
+	gpio_direction_output(gpio_config, 1);
+
+	/* Configure done pin */
+	/* Set to input */
+	ret = gpio_request(gpio_done, "DONE");
+	if (ret < 0)
+		return ret;
+
+	gpio_direction_input(gpio_done);
+
+	return 0;
+}
+
+static int fpga_config_fn(int assert, int flush, int cookie)
+{
+	int gpio_config = COOKIE2CONFIG(cookie);
+
+	debug("%s (%d): cookie=%08x gpio_config=%d\n",
+	      __func__, __LINE__, cookie, gpio_config);
+
+	if (assert)
+		gpio_set_value(gpio_config, 1);
+	else
+		gpio_set_value(gpio_config, 0);
+
+	return 0;
+}
+
+static int fpga_write_fn(const void *buf, size_t len, int flush, int cookie)
+{
+	int spi_bus = COOKIE2SPI_BUS(cookie);
+	int spi_dev = COOKIE2SPI_DEV(cookie);
+	struct kwspi_registers *reg;
+	u32 control_reg;
+	u32 config_reg;
+	void *dst;
+
+	/*
+	 * Write data to FPGA attached to SPI bus via SPI direct write.
+	 * This results in the fastest and easiest way to program the
+	 * bitstream into the FPGA.
+	 */
+	debug("%s (%d): cookie=%08x spi_bus=%d spi_dev=%d\n",
+	      __func__, __LINE__, cookie, spi_bus, spi_dev);
+
+	if (spi_bus == 0) {
+		reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10600);
+		dst = (void *)SPI_BUS0_DEV1_BASE;
+	} else {
+		reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10680);
+		dst = (void *)SPI_BUS1_DEV2_BASE;
+	}
+
+	/* Configure SPI controller for direct access mode */
+	control_reg = readl(&reg->ctrl);
+	config_reg = readl(&reg->cfg);
+	writel(0x00000214, &reg->cfg);		/* 27MHz clock */
+	writel(0x00000000, &reg->dw_cfg);	/* don't de-asset CS */
+	writel(KWSPI_CSN_ACT, &reg->ctrl);	/* activate CS */
+
+	/* Copy data to the SPI direct mapped window */
+	memcpy(dst, buf, len);
+
+	/* Restore original register values */
+	writel(control_reg, &reg->ctrl);
+	writel(config_reg, &reg->cfg);
+
+	return 0;
+}
+
+/* Returns the state of CONF_DONE Pin */
+static int fpga_done_fn(int cookie)
+{
+	int gpio_done = COOKIE2DONE(cookie);
+	unsigned long ts;
+
+	debug("%s (%d): cookie=%08x gpio_done=%d\n",
+	      __func__, __LINE__, cookie, gpio_done);
+
+	ts = get_timer(0);
+	do {
+		if (gpio_get_value(gpio_done))
+			return 0;
+	} while (get_timer(ts) < 1000);
+
+	/* timeout so return error */
+	return -ENODEV;
+}
+
+static altera_board_specific_func stratixv_fns = {
+	.pre = fpga_pre_fn,
+	.config = fpga_config_fn,
+	.write = fpga_write_fn,
+	.done = fpga_done_fn,
+};
+
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_StratixV,
+		/* Interface type */
+		passive_serial,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* Device function table */
+		(void *)&stratixv_fns,
+		/* Base interface address specified in driver */
+		NULL,
+		/* Cookie implementation */
+		/*
+		 * In this 32bit word the following information is coded:
+		 * Bit 31 ... Bit 0
+		 * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
+		 */
+		FPGA_COOKIE(0, 1, 26, 7)
+	},
+	{
+		/* Family */
+		Altera_StratixV,
+		/* Interface type */
+		passive_serial,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* Device function table */
+		(void *)&stratixv_fns,
+		/* Base interface address specified in driver */
+		NULL,
+		/* Cookie implementation */
+		/*
+		 * In this 32bit word the following information is coded:
+		 * Bit 31 ... Bit 0
+		 * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
+		 */
+		FPGA_COOKIE(1, 2, 29, 9)
+	},
+};
+
+/* Add device descriptor to FPGA device table */
+void board_fpga_add(void)
+{
+	int i;
+
+	fpga_init();
+	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
+		fpga_add(fpga_altera, &altera_fpga[i]);
+}
diff --git a/roms/u-boot/board/theadorable/theadorable.c b/roms/u-boot/board/theadorable/theadorable.c
new file mode 100644
index 000000000..bb2d51495
--- /dev/null
+++ b/roms/u-boot/board/theadorable/theadorable.c
@@ -0,0 +1,443 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2019 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <dm.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <pci.h>
+#if !defined(CONFIG_SPL_BUILD)
+#include <bootcount.h>
+#endif
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/delay.h>
+#include <linux/mbus.h>
+#ifdef CONFIG_NET
+#include <netdev.h>
+#endif
+#include <u-boot/crc.h>
+#include "theadorable.h"
+
+#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MV_USB_PHY_BASE			(MVEBU_AXP_USB_BASE + 0x800)
+#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
+	(MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
+
+#define THEADORABLE_GPP_OUT_ENA_LOW	0x00336780
+#define THEADORABLE_GPP_OUT_ENA_MID	0x00003cf0
+#define THEADORABLE_GPP_OUT_ENA_HIGH	(~(0x0))
+
+#define THEADORABLE_GPP_OUT_VAL_LOW	0x2c0c983f
+#define THEADORABLE_GPP_OUT_VAL_MID	0x0007000c
+#define THEADORABLE_GPP_OUT_VAL_HIGH	0x00000000
+
+#define GPIO_USB0_PWR_ON		18
+#define GPIO_USB1_PWR_ON		19
+
+#define PEX_SWITCH_NOT_FOUNT_LIMIT	3
+
+#define STM_I2C_BUS	1
+#define STM_I2C_ADDR	0x27
+#define REBOOT_DELAY	1000		/* reboot-delay in ms */
+#define ABORT_TIMEOUT	3000		/* 3 seconds reboot abort timeout */
+
+/* DDR3 static configuration */
+static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
+	{0x00001400, 0x7301ca28},	/* DDR SDRAM Configuration Register */
+	{0x00001404, 0x30000800},	/* Dunit Control Low Register */
+	{0x00001408, 0x44149887},	/* DDR SDRAM Timing (Low) Register */
+	{0x0000140C, 0x38d93fc7},	/* DDR SDRAM Timing (High) Register */
+	{0x00001410, 0x1b100001},	/* DDR SDRAM Address Control Register */
+	{0x00001424, 0x0000f3ff},	/* Dunit Control High Register */
+	{0x00001428, 0x000f8830},	/* ODT Timing (Low) Register */
+	{0x0000142C, 0x014c50f4},	/* DDR3 Timing Register */
+	{0x0000147C, 0x0000c671},	/* ODT Timing (High) Register */
+
+	{0x00001494, 0x00010000},	/* DDR SDRAM ODT Control (Low) Reg */
+	{0x0000149C, 0x00000001},	/* DDR Dunit ODT Control Register */
+	{0x000014A0, 0x00000001},	/* DRAM FIFO Control Register */
+	{0x000014A8, 0x00000101},	/* AXI Control Register */
+
+	/*
+	 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
+	 * training sequence
+	 */
+	{0x000200e8, 0x3fff0e01},
+	{0x00020184, 0x3fffffe0},	/* Close fast path Window to - 2G */
+
+	{0x0001504, 0x7fffffe1},	/* CS0 Size */
+	{0x000150C, 0x00000000},	/* CS1 Size */
+	{0x0001514, 0x00000000},	/* CS2 Size */
+	{0x000151C, 0x00000000},	/* CS3 Size */
+
+	{0x00020220, 0x00000007},	/* Reserved */
+
+	{0x00001538, 0x00000009},	/* Read Data Sample Delays Register */
+	{0x0000153C, 0x00000009},	/* Read Data Ready Delay Register */
+
+	{0x000015D0, 0x00000650},	/* MR0 */
+	{0x000015D4, 0x00000044},	/* MR1 */
+	{0x000015D8, 0x00000010},	/* MR2 */
+	{0x000015DC, 0x00000000},	/* MR3 */
+	{0x000015E0, 0x00000001},
+	{0x000015E4, 0x00203c18},	/* ZQDS Configuration Register */
+	{0x000015EC, 0xf800a225},	/* DDR PHY */
+
+	/* Recommended Settings from Marvell for 4 x 16 bit devices: */
+	{0x000014C0, 0x192424c9},	/* DRAM addr and Ctrl Driving Strenght*/
+	{0x000014C4, 0x0aaa24c9},	/* DRAM Data and DQS Driving Strenght */
+
+	{0x0, 0x0}
+};
+
+static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
+	{"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable,  NULL},
+};
+
+extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
+
+/*
+ * Lane0 - PCIE0.0 X1 (to WIFI Module)
+ * Lane5 - SATA0
+ * Lane6 - SATA1
+ * Lane7 - SGMII0 (to Ethernet Phy)
+ * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
+ * all other lanes are disabled
+ */
+MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
+	{ MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
+	  { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
+	    PEX_BUS_DISABLED },
+	  0x0060, serdes_change_m_phy
+	},
+};
+
+/*
+ * Define a board-specific detection pulse-width array for the SerDes PCIe
+ * interfaces. If not defined in the board code, the default of currently 2
+ * is used. Values from 0...3 are possible (2 bits).
+ */
+u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
+
+MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
+{
+	/* Only one mode supported for this board */
+	return &board_ddr_modes[0];
+}
+
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
+{
+	return &theadorable_serdes_cfg[0];
+}
+
+u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+	/* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */
+	return 0xe;	/* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */
+}
+
+#define PCIE_LNK_CTRL_STAT_2_OFF	0x0090
+#define PCIE_LNK_CTRL_STAT_2_DEEM_BIT	BIT(6)
+
+static void pcie_set_deemphasis(u32 base)
+{
+	u32 reg;
+
+	reg = readl((void *)base + PCIE_LNK_CTRL_STAT_2_OFF);
+	reg |= PCIE_LNK_CTRL_STAT_2_DEEM_BIT;
+	writel(reg, (void *)base + PCIE_LNK_CTRL_STAT_2_OFF);
+}
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x00000000, MVEBU_MPP_BASE + 0x00);
+	writel(0x03300000, MVEBU_MPP_BASE + 0x04);
+	writel(0x00000033, MVEBU_MPP_BASE + 0x08);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
+	writel(0x11110000, MVEBU_MPP_BASE + 0x10);
+	writel(0x00221100, MVEBU_MPP_BASE + 0x14);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x18);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x20);
+
+	/* Configure GPIO */
+	writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+	writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+	writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
+	writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
+
+	/*
+	 * Set deephasis bit in the PCIe configuration of both PCIe ports
+	 * used on this board.
+	 *
+	 * This needs to be done very early, even before the SERDES setup
+	 * code is run. This way, the first link will already be established
+	 * with this setup. Testing has shown, that this results in a more
+	 * stable PCIe link with better signal quality.
+	 */
+	pcie_set_deemphasis(MVEBU_REG_PCIE_BASE);		/* Port 0 */
+	pcie_set_deemphasis(MVEBU_REG_PCIE_BASE + 0x2000);	/* Port 2 */
+
+	return 0;
+}
+
+int board_init(void)
+{
+	int ret;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/*
+	 * Map SPI devices via MBUS so that they can be accessed via
+	 * the SPI direct access mode
+	 */
+	mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
+	mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
+
+	/*
+	 * Set RX Channel Control 0 Register:
+	 * Tests have shown, that setting the LPF_COEF from 0 (1/8)
+	 * to 3 (1/1) results in a more stable USB connection.
+	 */
+	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
+	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
+	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
+
+	/* Toggle USB power */
+	ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
+	if (ret < 0)
+		return ret;
+	gpio_direction_output(GPIO_USB0_PWR_ON, 0);
+	ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
+	if (ret < 0)
+		return ret;
+	gpio_direction_output(GPIO_USB1_PWR_ON, 0);
+	mdelay(1);
+	gpio_set_value(GPIO_USB0_PWR_ON, 1);
+	gpio_set_value(GPIO_USB1_PWR_ON, 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	board_fpga_add();
+
+	return 0;
+}
+
+#ifdef CONFIG_NET
+int board_eth_init(struct bd_info *bis)
+{
+	cpu_eth_init(bis); /* Built in controller(s) come first */
+	return pci_eth_init(bis);
+}
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT)
+int board_late_init(void)
+{
+	pci_dev_t bdf;
+	ulong bootcount;
+
+	/*
+	 * Check if the PEX switch is detected (somtimes its not available
+	 * on the PCIe bus). In this case, try to recover by issuing a
+	 * soft-reset or even a power-cycle, depending on the bootcounter
+	 * value.
+	 */
+	bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
+	if (bdf == -1) {
+		unsigned long start_time = get_timer(0);
+		u8 i2c_buf[8];
+		int ret;
+
+		/* PEX switch not found! */
+		bootcount = bootcount_load();
+		printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
+		       bootcount);
+
+		/*
+		 * The user can exit this boot-loop in the error case by
+		 * hitting Ctrl-C. So wait some time for this key here.
+		 */
+		printf("Continue booting with Ctrl-C, otherwise rebooting\n");
+		do {
+			/* Handle control-c and timeouts */
+			if (ctrlc()) {
+				printf("PEX error boot-loop aborted!\n");
+				return 0;
+			}
+		} while (get_timer(start_time) < ABORT_TIMEOUT);
+
+
+		/*
+		 * At this stage the bootcounter has not been incremented
+		 * yet. We need to do this manually here to get an actually
+		 * working bootcounter in this error case.
+		 */
+		bootcount_inc();
+
+		if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
+			printf("Issuing power-switch via uC!\n");
+
+			printf("Issuing power-switch via uC!\n");
+			i2c_set_bus_num(STM_I2C_BUS);
+			i2c_buf[0] = STM_I2C_ADDR << 1;
+			i2c_buf[1] = 0xc5;	/* cmd */
+			i2c_buf[2] = 0x01;	/* enable */
+			/* Delay before reboot */
+			i2c_buf[3] = REBOOT_DELAY & 0x00ff;
+			i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
+			/* Delay before shutdown */
+			i2c_buf[5] = 0x00;
+			i2c_buf[6] = 0x00;
+			i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
+
+			ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
+			if (ret) {
+				printf("I2C write error (ret=%d)\n", ret);
+				printf("Issuing soft-reset...\n");
+				/* default handling: SOFT reset */
+				do_reset(NULL, 0, 0, NULL);
+			}
+
+			/* Wait for power-cycle to occur... */
+			printf("Waiting for power-cycle via uC...\n");
+			while (1)
+				;
+		} else {
+			printf("Issuing soft-reset...\n");
+			/* default handling: SOFT reset */
+			do_reset(NULL, 0, 0, NULL);
+		}
+	}
+
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
+static int pcie_get_link_speed_width(pci_dev_t bdf, int *speed, int *width)
+{
+	struct udevice *dev;
+	u16 ven_id, dev_id;
+	u16 lnksta;
+	int ret;
+	int pos;
+
+	/*
+	 * Check if the PCIe device is detected (sometimes its not available
+	 * on the PCIe bus)
+	 */
+	ret = dm_pci_bus_find_bdf(bdf, &dev);
+	if (ret)
+		return -ENODEV;
+
+	/* PCIe device found */
+	dm_pci_read_config16(dev, PCI_VENDOR_ID, &ven_id);
+	dm_pci_read_config16(dev, PCI_DEVICE_ID, &dev_id);
+	printf("Detected PCIe device: VendorID 0x%04x DeviceId 0x%04x @ BDF %d.%d.%d\n",
+	       ven_id, dev_id, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+
+	/* Now read EXP_LNKSTA register */
+	pos = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
+	dm_pci_read_config16(dev, pos + PCI_EXP_LNKSTA, &lnksta);
+	*speed = lnksta & PCI_EXP_LNKSTA_CLS;
+	*width = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
+
+	return 0;
+}
+
+/*
+ * U-Boot cmd to test for the presence of the directly connected PCIe devices
+ * the theadorable board. This cmd can be used by U-Boot scripts for automated
+ * testing, if the PCIe setup is correct. Meaning, that all PCIe devices are
+ * correctly detected and the link speed and width is corrent.
+ *
+ * Here a short script that may be used for an automated test. It results in
+ * an endless reboot loop, if the PCIe devices are detected correctly. If at
+ * any time a problem is detected (PCIe device not available or link is
+ * incorrect), then booting will halt. So just use this "bootcmd" and let the
+ * board run over a longer time (e.g. one night) and if the board still reboots
+ * after this time, then everything is okay.
+ *
+ * bootcmd=echo bootcount=$bootcount; pcie ;if test $? -eq 0;
+ *         then echo PCIe status okay, resetting...; reset; else;
+ *         echo PCIe status NOT okay, hanging (bootcount=$bootcount); fi;
+ */
+int do_pcie_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	pci_dev_t bdf;
+	int speed;
+	int width;
+	int ret;
+
+	if (argc != 1)
+		return cmd_usage(cmdtp);
+
+	/*
+	 * Check if the PCIe device is detected (sometimes its not available
+	 * on the PCIe bus)
+	 */
+
+	/* Check for PCIe device on PCIe port/bus 0 */
+	bdf = PCI_BDF(0, 1, 0);
+	ret = pcie_get_link_speed_width(bdf, &speed, &width);
+	if (ret) {
+		/* PCIe device not found! */
+		printf("Failed to find PCIe device @ BDF %d.%d.%d\n",
+		       PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+		return CMD_RET_FAILURE;
+	}
+
+	printf("Established speed=%d width=%d\n", speed, width);
+	if ((speed != 1 || width != 1)) {
+		printf("Detected incorrect speed/width!!!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	/* Check for PCIe device on PCIe port/bus 1 */
+	bdf = PCI_BDF(1, 1, 0);
+	ret = pcie_get_link_speed_width(bdf, &speed, &width);
+	if (ret) {
+		/* PCIe device not found! */
+		printf("Failed to find PCIe device @ BDF %d.%d.%d\n",
+		       PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+		return CMD_RET_FAILURE;
+	}
+
+	printf("Established speed=%d width=%d\n", speed, width);
+	if ((speed != 2 || width != 4)) {
+		printf("Detected incorrect speed/width!!!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	pcie,   1,   0,     do_pcie_test,
+	"Test for presence of a PCIe devices with correct link",
+	""
+);
+#endif
diff --git a/roms/u-boot/board/theadorable/theadorable.h b/roms/u-boot/board/theadorable/theadorable.h
new file mode 100644
index 000000000..d3c959de9
--- /dev/null
+++ b/roms/u-boot/board/theadorable/theadorable.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+/* Base addresses for the SPI direct access mode */
+#define SPI_BUS0_DEV1_BASE	0xe0000000
+#define SPI_BUS0_DEV1_SIZE	(1 << 20)
+#define SPI_BUS1_DEV2_BASE	(SPI_BUS0_DEV1_BASE + SPI_BUS0_DEV1_SIZE)
+
+void board_fpga_add(void);
diff --git a/roms/u-boot/board/theobroma-systems/lion_rk3368/Kconfig b/roms/u-boot/board/theobroma-systems/lion_rk3368/Kconfig
new file mode 100644
index 000000000..fddbf826d
--- /dev/null
+++ b/roms/u-boot/board/theobroma-systems/lion_rk3368/Kconfig
@@ -0,0 +1,21 @@
+if TARGET_LION_RK3368
+
+config SYS_BOARD
+	default "lion_rk3368"
+
+config SYS_VENDOR
+	default "theobroma-systems"
+
+config SYS_CONFIG_NAME
+	default "lion_rk3368"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+config ENV_SIZE
+	default 0x2000
+
+config ENV_OFFSET
+	default 0x3c000 if ENV_IS_IN_SPI_FLASH
+
+endif
diff --git a/roms/u-boot/board/theobroma-systems/lion_rk3368/MAINTAINERS b/roms/u-boot/board/theobroma-systems/lion_rk3368/MAINTAINERS
new file mode 100644
index 000000000..857f784d2
--- /dev/null
+++ b/roms/u-boot/board/theobroma-systems/lion_rk3368/MAINTAINERS
@@ -0,0 +1,10 @@
+LION-RK3368 (RK3368-uQ7 system-on-module)
+M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+M:	Klaus Goger <klaus.goger@theobroma-systems.com>
+S:	Maintained
+F:	board/theobroma-systems/lion_rk3368
+F:	include/configs/lion_rk3368.h
+F:	arch/arm/dts/rk3368-lion.dts
+F:	configs/lion-rk3368_defconfig
+W:	https://www.theobroma-systems.com/rk3368-uq7/tech-specs
+T:	git git://git.theobroma-systems.com/lion-u-boot.git
diff --git a/roms/u-boot/board/theobroma-systems/lion_rk3368/Makefile b/roms/u-boot/board/theobroma-systems/lion_rk3368/Makefile
new file mode 100644
index 000000000..fc8df2714
--- /dev/null
+++ b/roms/u-boot/board/theobroma-systems/lion_rk3368/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+
+obj-y += lion_rk3368.o
diff --git a/roms/u-boot/board/theobroma-systems/lion_rk3368/README b/roms/u-boot/board/theobroma-systems/lion_rk3368/README
new file mode 100644
index 000000000..7488b1832
--- /dev/null
+++ b/roms/u-boot/board/theobroma-systems/lion_rk3368/README
@@ -0,0 +1,78 @@
+Here is the step-by-step to boot to U-Boot on RK3368-uQ7
+
+Get the Source and build ATF
+============================
+
+  > git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
+  > cd arm-trusted-firmware
+  > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3368 bl31
+  > cp build/rk3368/release/bl31.bin ../u-boot/bl31-rk3368.bin
+
+Configure U-Boot
+================
+
+  > cd ../u-boot
+  > make lion-rk3368_defconfig
+
+Build the TPL/SPL stage
+=======================
+
+  > make CROSS_COMPILE=aarch64-unknown-elf-
+
+Build the full U-Boot and a FIT image including the ATF
+=======================================================
+
+  > make CROSS_COMPILE=aarch64-unknown-elf- u-boot.itb
+
+Flash the image
+===============
+
+Copy the SPL to offset 32k and the FIT image containing the payloads
+(U-Boot proper, ATF, devicetree) to offset 256k card.
+
+SD-Card
+-------
+
+  > dd if=idbloader.img of=/dev/sdb seek=64
+  > dd if=u-boot.itb of=/dev/sdb seek=512
+
+eMMC
+----
+
+rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with
+help of the Rockchip loader binary.
+
+  > git clone https://github.com/rockchip-linux/rkdeveloptool
+  > cd rkdeveloptool
+  > autoreconf -i && && ./configure && make
+  > git clone https://github.com/rockchip-linux/rkbin.git
+  > ./rkdeveloptool db rkbin/rk33/rk3368_loader_v2.00.256.bin
+  > ./rkdeveloptool wl 64 ../spl.img
+  > ./rkdeveloptool wl 512 ../u-boot.itb
+
+
+If everything went according to plan, you should see the following
+output on UART0:
+
+<debug_uart> U-Boot TPL board init
+Trying to boot from BOOTROM
+Returning to boot ROM...
+Trying to boot from MMC1
+NOTICE:  BL31: v1.3(release):v1.2-1320-gbf43a443
+NOTICE:  BL31: Built : 18:04:47, Jul  5 2017
+
+
+U-Boot 2017.07-00158-g2395e99858 (Jul 18 2017 - 21:03:31 +0200)
+
+Model: Theobroma Systems RK3368-uQ7 SoM
+DRAM:  2 GiB
+MMC:   dwmmc@ff0c0000: 1, dwmmc@ff0f0000: 0
+Using default environment
+
+In:    serial@ff180000
+Out:   serial@ff180000
+Err:   serial@ff180000
+Net:
+Warning: ethernet@ff290000 (eth0) using random MAC address - d2:69:35:7e:d0:1e
+eth0: ethernet@ff290000
+Hit any key to stop autoboot:  2
diff --git a/roms/u-boot/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/roms/u-boot/board/theobroma-systems/lion_rk3368/lion_rk3368.c
new file mode 100644
index 000000000..1b0d50463
--- /dev/null
+++ b/roms/u-boot/board/theobroma-systems/lion_rk3368/lion_rk3368.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+ */
diff --git a/roms/u-boot/board/theobroma-systems/puma_rk3399/Kconfig b/roms/u-boot/board/theobroma-systems/puma_rk3399/Kconfig
new file mode 100644
index 000000000..21946d984
--- /dev/null
+++ b/roms/u-boot/board/theobroma-systems/puma_rk3399/Kconfig
@@ -0,0 +1,36 @@
+if TARGET_PUMA_RK3399
+
+config SYS_BOARD
+	default "puma_rk3399"
+
+config SYS_VENDOR
+	default "theobroma-systems"
+
+config SYS_CONFIG_NAME
+	default "puma_rk3399"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+config ENV_SIZE
+	default 0x4000
+
+config ENV_OFFSET
+	default 0x3fc000 if ENV_IS_IN_SPI_FLASH
+
+choice
+	prompt "Theobroma Systems RK3399-Q7 DDR Option"
+	default TARGET_PUMA_RK3399_RAM_DDR3_1333
+
+config TARGET_PUMA_RK3399_RAM_DDR3_1333
+	bool "DDR3-1333MHz"
+
+config TARGET_PUMA_RK3399_RAM_DDR3_1600
+	bool "DDR3-1600MHz"
+
+config TARGET_PUMA_RK3399_RAM_DDR3_1866
+	bool "DDR3-1866MHz"
+
+endchoice
+
+endif
diff --git a/roms/u-boot/board/theobroma-systems/puma_rk3399/MAINTAINERS b/roms/u-boot/board/theobroma-systems/puma_rk3399/MAINTAINERS
new file mode 100644
index 000000000..ccec09c38
--- /dev/null
+++ b/roms/u-boot/board/theobroma-systems/puma_rk3399/MAINTAINERS
@@ -0,0 +1,10 @@
+PUMA-RK3399
+M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+M:	Klaus Goger <klaus.goger@theobroma-systems.com>
+S:	Maintained
+F:	board/theobroma-systems/puma_rk3399
+F:	include/configs/puma_rk3399.h
+F:	arch/arm/dts/rk3399-puma.dts
+F:	configs/puma-rk3399_defconfig
+W:	https://www.theobroma-systems.com/rk3399-q7/tech-specs
+T:	git git://git.theobroma-systems.com/puma-u-boot.git
diff --git a/roms/u-boot/board/theobroma-systems/puma_rk3399/Makefile b/roms/u-boot/board/theobroma-systems/puma_rk3399/Makefile
new file mode 100644
index 000000000..d962b56f1
--- /dev/null
+++ b/roms/u-boot/board/theobroma-systems/puma_rk3399/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= puma-rk3399.o
diff --git a/roms/u-boot/board/theobroma-systems/puma_rk3399/README b/roms/u-boot/board/theobroma-systems/puma_rk3399/README
new file mode 100644
index 000000000..9b31b0b37
--- /dev/null
+++ b/roms/u-boot/board/theobroma-systems/puma_rk3399/README
@@ -0,0 +1,107 @@
+Introduction
+============
+
+The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip
+RK3399 in a Qseven-compatible form-factor.
+
+RK3399-Q7 features:
+	* CPU: ARMv8 64bit Big-Little architecture,
+		* Big: dual-core Cortex-A72
+		* Little: quad-core Cortex-A53
+		* IRAM: 200KB
+	* DRAM: 4GB-128MB dual-channel
+	* eMMC: onboard eMMC
+	* SD/MMC
+	* GbE (onboard Micrel KSZ9031) Gigabit ethernet PHY
+	* USB:
+		* USB3.0 dual role port
+		* 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub
+	* Display: HDMI/eDP/MIPI
+	* Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF)
+	* NOR Flash: onboard SPI NOR
+	* Companion Controller: onboard additional Cortex-M0 microcontroller
+		* RTC
+		* fan controller
+		* CAN
+
+Here is the step-by-step to boot to U-Boot on rk3399.
+
+Get the Source and build ATF/Cortex-M0 binaries
+===============================================
+
+  > git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
+  > git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git
+
+Compile the ATF
+===============
+
+  > cd arm-trusted-firmware
+  > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
+  > cp build/rk3399/release/bl31.bin ../u-boot/bl31-rk3399.bin
+
+Compile the M0 firmware
+=======================
+
+  > cd ../rk3399-cortex-m0
+  > make CROSS_COMPILE=arm-cortex_m0-eabi-
+  > cp rk3399m0.bin ../u-boot
+
+Compile the U-Boot
+==================
+
+  > cd ../u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- puma-rk3399_defconfig all
+
+Package the image
+=================
+
+Creating a SPL image for SD-Card/eMMC
+  > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl_mmc.img
+Creating a SPL image for SPI-NOR
+  > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img
+Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree
+  > make CROSS_COMPILE=aarch64-linux-gnu-
+
+Flash the image
+===============
+
+Copy the SPL to offset 32k for SD/eMMC, offset 0 for NOR-Flash and the FIT
+image to offset 256k card.
+
+SD-Card
+-------
+
+  > dd if=spl_mmc.img of=/dev/sdb seek=64
+  > dd if=u-boot.itb of=/dev/sdb seek=512
+
+eMMC
+----
+
+rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with
+help of the Rockchip loader binary.
+
+  > git clone https://github.com/rockchip-linux/rkdeveloptool
+  > cd rkdeveloptool
+  > autoreconf -i && ./configure && make
+  > git clone https://github.com/rockchip-linux/rkbin.git
+  > ./rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
+  > ./rkdeveloptool wl 64 ../spl_mmc.img
+  > ./rkdeveloptool wl 512 ../u-boot.itb
+
+NOR-Flash
+---------
+
+Writing the SPI NOR Flash requires a running U-Boot. For the sake of simplicity
+we assume you have a SD-Card with a partition containing the required files
+ready.
+
+  > load mmc 1:1 ${kernel_addr_r} spl_nor.img
+  > sf probe
+  > sf erase 0 +$filesize
+  > sf write $kernel_addr_r 0 ${filesize}
+  > load mmc 1:1 ${kernel_addr_r} u-boot.itb
+  > sf erase 0x40000 +$filesize
+  > sf write $kernel_addr_r 0x40000 ${filesize}
+
+
+Reboot the system and you should see a U-Boot console on UART0 (115200n8).
diff --git a/roms/u-boot/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/roms/u-boot/board/theobroma-systems/puma_rk3399/puma-rk3399.c
new file mode 100644
index 000000000..deeba3084
--- /dev/null
+++ b/roms/u-boot/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <log.h>
+#include <misc.h>
+#include <spl.h>
+#include <syscon.h>
+#include <u-boot/crc.h>
+#include <usb.h>
+#include <dm/pinctrl.h>
+#include <dm/uclass-internal.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/misc.h>
+#include <power/regulator.h>
+#include <u-boot/sha256.h>
+
+static void setup_iodomain(void)
+{
+	const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3;
+	struct rk3399_grf_regs *grf =
+	    syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+	/*
+	 * Set bit 3 in GRF_IO_VSEL so PCIE_RST# works (pin GPIO4_C6).
+	 * Linux assumes that PCIE_RST# works out of the box as it probes
+	 * PCIe before loading the iodomain driver.
+	 */
+	rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT);
+}
+
+/*
+ * Swap mmc0 and mmc1 in boot_targets if booted from SD-Card.
+ *
+ * If bootsource is uSD-card we can assume that we want to use the
+ * SD-Card instead of the eMMC as first boot_target for distroboot.
+ * We only want to swap the defaults and not any custom environment a
+ * user has set. We exit early if a changed boot_targets environment
+ * is detected.
+ */
+static int setup_boottargets(void)
+{
+	const char *boot_device =
+		ofnode_read_chosen_string("u-boot,spl-boot-device");
+	char *env_default, *env;
+
+	if (!boot_device) {
+		debug("%s: /chosen/u-boot,spl-boot-device not set\n",
+		      __func__);
+		return -1;
+	}
+	debug("%s: booted from %s\n", __func__, boot_device);
+
+	env_default = env_get_default("boot_targets");
+	env = env_get("boot_targets");
+	if (!env) {
+		debug("%s: boot_targets does not exist\n", __func__);
+		return -1;
+	}
+	debug("%s: boot_targets current: %s - default: %s\n",
+	      __func__, env, env_default);
+
+	if (strcmp(env_default, env) != 0) {
+		debug("%s: boot_targets not default, don't change it\n",
+		      __func__);
+		return 0;
+	}
+
+	/*
+	 * Only run, if booting from mmc1 (i.e. /mmc@fe320000) and
+	 * only consider cases where the default boot-order first
+	 * tries to boot from mmc0 (eMMC) and then from mmc1
+	 * (i.e. external SD).
+	 *
+	 * In other words: the SD card will be moved to earlier in the
+	 * order, if U-Boot was also loaded from the SD-card.
+	 */
+	if (!strcmp(boot_device, "/mmc@fe320000")) {
+		char *mmc0, *mmc1;
+
+		debug("%s: booted from SD-Card\n", __func__);
+		mmc0 = strstr(env, "mmc0");
+		mmc1 = strstr(env, "mmc1");
+
+		if (!mmc0 || !mmc1) {
+			debug("%s: only one mmc boot_target found\n", __func__);
+			return -1;
+		}
+
+		/*
+		 * If mmc0 comes first in the boot order, we need to change
+		 * the strings to make mmc1 first.
+		 */
+		if (mmc0 < mmc1) {
+			mmc0[3] = '1';
+			mmc1[3] = '0';
+			debug("%s: set boot_targets to: %s\n", __func__, env);
+			env_set("boot_targets", env);
+		}
+	}
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	const u32 cpuid_offset = 0x7;
+	const u32 cpuid_length = 0x10;
+	u8 cpuid[cpuid_length];
+	int ret;
+
+	ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+	if (ret)
+		return ret;
+
+	ret = rockchip_cpuid_set(cpuid, cpuid_length);
+	if (ret)
+		return ret;
+
+	ret = rockchip_setup_macaddr();
+	if (ret)
+		return ret;
+
+	setup_iodomain();
+	setup_boottargets();
+
+	return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *serial_string;
+	u64 serial = 0;
+
+	serial_string = env_get("serial#");
+
+	if (serial_string)
+		serial = simple_strtoull(serial_string, NULL, 16);
+
+	serialnr->high = (u32)(serial >> 32);
+	serialnr->low = (u32)(serial & 0xffffffff);
+}
+#endif
diff --git a/roms/u-boot/board/ti/am335x/Kconfig b/roms/u-boot/board/ti/am335x/Kconfig
new file mode 100644
index 000000000..b66ca1a57
--- /dev/null
+++ b/roms/u-boot/board/ti/am335x/Kconfig
@@ -0,0 +1,24 @@
+if TARGET_AM335X_EVM
+
+config SYS_BOARD
+	default "am335x"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "am335x_evm"
+
+config NOR
+	bool "Support for NOR flash"
+	help
+	  The AM335x SoC supports having a NOR flash connected to the GPMC.
+	  In practice this is seen as a NOR flash module connected to the
+	  "memory cape" for the BeagleBone family.
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/ti/am335x/MAINTAINERS b/roms/u-boot/board/ti/am335x/MAINTAINERS
new file mode 100644
index 000000000..219c8715b
--- /dev/null
+++ b/roms/u-boot/board/ti/am335x/MAINTAINERS
@@ -0,0 +1,8 @@
+AM335X BOARD
+M:	Tom Rini <trini@konsulko.com>
+S:	Maintained
+F:	board/ti/am335x/
+F:	include/configs/am335x_evm.h
+F:	configs/am335x_boneblack_vboot_defconfig
+F:	configs/am335x_evm_defconfig
+F:	configs/am335x_evm_spiboot_defconfig
diff --git a/roms/u-boot/board/ti/am335x/Makefile b/roms/u-boot/board/ti/am335x/Makefile
new file mode 100644
index 000000000..c34b9b1dd
--- /dev/null
+++ b/roms/u-boot/board/ti/am335x/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/roms/u-boot/board/ti/am335x/README b/roms/u-boot/board/ti/am335x/README
new file mode 100644
index 000000000..19e0eccba
--- /dev/null
+++ b/roms/u-boot/board/ti/am335x/README
@@ -0,0 +1,205 @@
+Summary
+=======
+
+This document covers various features of the 'am335x_evm' build, and some of
+the related build targets (am335x_evm_uartN, etc).
+
+Hardware
+========
+
+The binary produced by this board supports, based on parsing of the EEPROM
+documented in TI's reference designs:
+- AM335x GP EVM
+- AM335x EVM SK
+- Beaglebone White
+- Beaglebone Black
+
+Customization
+=============
+
+Given that all of the above boards are reference platforms (and the
+Beaglebone platforms are OSHA), it is likely that this platform code and
+configuration will be used as the basis of a custom platform.  It is
+worth noting that aside from things such as NAND or MMC only being
+required if a custom platform makes use of these blocks, the following
+are required, depending on design:
+
+- GPIO is only required if DDR3 power is controlled in a way similar to
+  EVM SK
+- SPI is only required for SPI flash, or exposing the SPI bus.
+
+The following blocks are required:
+- I2C, to talk with the PMIC and ensure that we do not run afoul of
+  errata 1.0.24.
+
+When removing options as part of customization,
+CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
+needs and to remove no longer relevant options as in some cases we
+define additional text blocks (such as for NAND or DFU strings).  Also
+note that all of the SPL options are grouped together, rather than with
+the IP blocks, so both areas will need their choices updated to reflect
+the custom design.
+
+NAND
+====
+
+The AM335x GP EVM ships with a 256MiB NAND available in most profiles.  In
+this example to program the NAND we assume that an SD card has been
+inserted with the files to write in the first SD slot and that mtdparts
+have been configured correctly for the board. All images are first loaded
+into memory, then written to NAND.
+
+Step-1: Building u-boot for NAND boot
+	Set following CONFIGxx options for NAND device.
+	CONFIG_SYS_NAND_PAGE_SIZE	number of main bytes in NAND page
+	CONFIG_SYS_NAND_OOBSIZE		number of OOB bytes in NAND page
+	CONFIG_SYS_NAND_BLOCK_SIZE	number of bytes in NAND erase-block
+	CONFIG_SYS_NAND_ECCPOS		ECC map for NAND page
+	CONFIG_NAND_OMAP_ECCSCHEME	(refer doc/README.nand)
+
+Step-2: Flashing NAND via MMC/SD
+	# select BOOTSEL to MMC/SD boot and boot from MMC/SD card
+	U-Boot # mmc rescan
+	# erase flash
+	U-Boot # nand erase.chip
+	U-Boot # env default -f -a
+	U-Boot # saveenv
+	# flash MLO. Redundant copies of MLO are kept for failsafe
+	U-Boot # load mmc 0 0x82000000 MLO
+	U-Boot # nand write 0x82000000 0x00000 0x20000
+	U-Boot # nand write 0x82000000 0x20000 0x20000
+	U-Boot # nand write 0x82000000 0x40000 0x20000
+	U-Boot # nand write 0x82000000 0x60000 0x20000
+	# flash u-boot.img
+	U-Boot # load mmc 0 0x82000000 u-boot.img
+	U-Boot # nand write 0x82000000 0x80000 0x60000
+	# flash kernel image
+	U-Boot # load mmc 0 0x82000000 uImage
+	U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize}
+	# flash filesystem image
+	U-Boot # load mmc 0 0x82000000 filesystem.img
+	U-Boot # nand write 0x82000000 ${loadaddress} 0x300000
+
+Step-3: Set BOOTSEL pin to select NAND boot, and POR the device.
+	The device should boot from images flashed on NAND device.
+
+NOR
+===
+
+The Beaglebone White can be equipped with a "memory cape" that in turn can
+have a NOR module plugged into it.  In this case it is then possible to
+program and boot from NOR.  Note that due to how U-Boot is designed we
+must build a specific version of U-Boot that knows we have NOR flash.  This
+build is named 'am335x_evm_nor'.  Further, we have a 'am335x_evm_norboot'
+build that will assume that the environment is on NOR rather than NAND.  In
+the following example we assume that and SD card has been populated with
+MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the
+'u-boot.bin' from a 'am335x_evm_norboot' build.  When booting from NOR, a
+binary must be written to the start of NOR, with no header or similar
+prepended.  In the following example we use a size of 512KiB (0x80000)
+as that is how much space we set aside before the environment, as per
+the config file.
+
+U-Boot # mmc rescan
+U-Boot # load mmc 0 ${loadaddr} u-boot.bin
+U-Boot # protect off 08000000 +80000
+U-Boot # erase 08000000 +80000
+U-Boot # cp.b ${loadaddr} 08000000 ${filesize}
+
+Falcon Mode
+===========
+
+The default build includes "Falcon Mode" (see doc/README.falcon) via NAND,
+eMMC (or raw SD cards) and FAT SD cards.  Our default behavior currently is
+to read a 'c' on the console while in SPL at any point prior to loading the
+OS payload (so as soon as possible) to opt to booting full U-Boot.  Also
+note that while one can program Falcon Mode "in place" great care needs to
+be taken by the user to not 'brick' their setup.  As these are all eval
+boards with multiple boot methods, recovery should not be an issue in this
+worst-case however.
+
+Falcon Mode: eMMC
+=================
+
+The recommended layout in this case is:
+
+MMC BLOCKS      |--------------------------------| LOCATION IN BYTES
+0x0000 - 0x007F : MBR or GPT table               : 0x000000 - 0x020000
+0x0080 - 0x00FF : ARGS or FDT file               : 0x010000 - 0x020000
+0x0100 - 0x01FF : SPL.backup1 (first copy used)  : 0x020000 - 0x040000
+0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000
+0x0300 - 0x06FF : U-Boot                         : 0x060000 - 0x0e0000
+0x0700 - 0x08FF : U-Boot Env + Redundant         : 0x0e0000 - 0x120000
+0x0900 - 0x28FF : Kernel                         : 0x120000 - 0x520000
+
+Note that when we run 'spl export' it will prepare to boot the kernel.
+This includes relocation of the uImage from where we loaded it to the entry
+point defined in the header.  As these locations overlap by default, it
+would leave us with an image that if written to MMC will not boot, so
+instead of using the loadaddr variable we use 0x81000000 in the following
+example.  In this example we are loading from the network, for simplicity,
+and assume a valid partition table already exists and 'mmc dev' has already
+been run to select the correct device.  Also note that if you previously
+had a FAT partition (such as on a Beaglebone Black) it is not enough to
+write garbage into the area, you must delete it from the partition table
+first.
+
+# Ensure we are able to talk with this mmc device
+U-Boot # mmc rescan
+U-Boot # tftp 81000000 am335x/MLO
+# Write to two of the backup locations ROM uses
+U-Boot # mmc write 81000000 100 100
+U-Boot # mmc write 81000000 200 100
+# Write U-Boot to the location set in the config
+U-Boot # tftp 81000000 am335x/u-boot.img
+U-Boot # mmc write 81000000 300 400
+# Load kernel and device tree into memory, perform export
+U-Boot # tftp 81000000 am335x/uImage
+U-Boot # run findfdt
+U-Boot # tftp ${fdtaddr} am335x/${fdtfile}
+U-Boot # run mmcargs
+U-Boot # spl export fdt 81000000 - ${fdtaddr}
+# Write the updated device tree to MMC
+U-Boot # mmc write ${fdtaddr} 80 80
+# Write the uImage to MMC
+U-Boot # mmc write 81000000 900 2000
+
+Falcon Mode: FAT SD cards
+=========================
+
+In this case the additional file is written to the filesystem.  In this
+example we assume that the uImage and device tree to be used are already on
+the FAT filesystem (only the uImage MUST be for this to function
+afterwards) along with a Falcon Mode aware MLO and the FAT partition has
+already been created and marked bootable:
+
+U-Boot # mmc rescan
+# Load kernel and device tree into memory, perform export
+U-Boot # load mmc 0:1 ${loadaddr} uImage
+U-Boot # run findfdt
+U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile}
+U-Boot # run mmcargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+
+This will print a number of lines and then end with something like:
+   Using Device Tree in place at 80f80000, end 80f85928
+   Using Device Tree in place at 80f80000, end 80f88928
+So then you:
+
+U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928
+
+Falcon Mode: NAND
+=================
+
+In this case the additional data is written to another partition of the
+NAND.  In this example we assume that the uImage and device tree to be are
+already located on the NAND somewhere (such as filesystem or mtd partition)
+along with a Falcon Mode aware MLO written to the correct locations for
+booting and mtdparts have been configured correctly for the board:
+
+U-Boot # nand read ${loadaddr} kernel
+U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
+U-Boot # run nandargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+U-Boot # nand erase.part u-boot-spl-os
+U-Boot # nand write ${fdtaddr} u-boot-spl-os
diff --git a/roms/u-boot/board/ti/am335x/board.c b/roms/u-boot/board/ti/am335x/board.c
new file mode 100644
index 000000000..5959ff73d
--- /dev/null
+++ b/roms/u-boot/board/ti/am335x/board.c
@@ -0,0 +1,997 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <errno.h>
+#include <image.h>
+#include <init.h>
+#include <malloc.h>
+#include <net.h>
+#include <spl.h>
+#include <serial.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk_synthesizer.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
+#include <asm/omap_mmc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <power/tps65217.h>
+#include <power/tps65910.h>
+#include <env_internal.h>
+#include <watchdog.h>
+#include "../common/board_detect.h"
+#include "../common/cape_detect.h"
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#define GPIO_DDR_VTT_EN		GPIO_TO_PIN(0, 7)
+#define ICE_GPIO_DDR_VTT_EN	GPIO_TO_PIN(0, 18)
+#define GPIO_PR1_MII_CTRL	GPIO_TO_PIN(3, 4)
+#define GPIO_MUX_MII_CTRL	GPIO_TO_PIN(3, 10)
+#define GPIO_FET_SWITCH_CTRL	GPIO_TO_PIN(0, 7)
+#define GPIO_PHY_RESET		GPIO_TO_PIN(2, 5)
+#define GPIO_ETH0_MODE		GPIO_TO_PIN(0, 11)
+#define GPIO_ETH1_MODE		GPIO_TO_PIN(1, 26)
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#define GPIO0_RISINGDETECT	(AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
+#define GPIO1_RISINGDETECT	(AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
+
+#define GPIO0_IRQSTATUS1	(AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
+#define GPIO1_IRQSTATUS1	(AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
+
+#define GPIO0_IRQSTATUSRAW	(AM33XX_GPIO0_BASE + 0x024)
+#define GPIO1_IRQSTATUSRAW	(AM33XX_GPIO1_BASE + 0x024)
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+void do_board_detect(void)
+{
+	enable_i2c0_pin_mux();
+	enable_i2c2_pin_mux();
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED2, CONFIG_SYS_OMAP24_I2C_SLAVE2);
+#endif
+	if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+				 CONFIG_EEPROM_CHIP_ADDRESS))
+		printf("ti_i2c_eeprom_init failed\n");
+}
+#endif
+
+#ifndef CONFIG_DM_SERIAL
+struct serial_device *default_serial_console(void)
+{
+	if (board_is_icev2())
+		return &eserial4_device;
+	else
+		return &eserial1_device;
+}
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static const struct ddr_data ddr2_data = {
+	.datardsratio0 = MT47H128M16RT25E_RD_DQS,
+	.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+	.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+	.cmd0csratio = MT47H128M16RT25E_RATIO,
+
+	.cmd1csratio = MT47H128M16RT25E_RATIO,
+
+	.cmd2csratio = MT47H128M16RT25E_RATIO,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
+static const struct emif_regs ddr2_evm_emif_reg_data = {
+	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
+	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41J128MJT125_RD_DQS,
+	.datawdsratio0 = MT41J128MJT125_WR_DQS,
+	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
+	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
+};
+
+static const struct ddr_data ddr3_beagleblack_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct ddr_data ddr3_evm_data = {
+	.datardsratio0 = MT41J512M8RH125_RD_DQS,
+	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
+	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
+	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
+};
+
+static const struct ddr_data ddr3_icev2_data = {
+	.datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
+	.datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
+	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
+	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41J128MJT125_RATIO,
+	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41J128MJT125_RATIO,
+	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41J128MJT125_RATIO,
+	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
+};
+
+static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
+	.cmd0csratio = MT41J512M8RH125_RATIO,
+	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41J512M8RH125_RATIO,
+	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41J512M8RH125_RATIO,
+	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+};
+
+static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
+	.cmd0csratio = MT41J128MJT125_RATIO_400MHz,
+	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+
+	.cmd1csratio = MT41J128MJT125_RATIO_400MHz,
+	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+
+	.cmd2csratio = MT41J128MJT125_RATIO_400MHz,
+	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
+	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
+	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
+	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
+	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
+	.zq_config = MT41J128MJT125_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
+};
+
+static struct emif_regs ddr3_beagleblack_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static struct emif_regs ddr3_evm_emif_reg_data = {
+	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
+	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
+	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
+	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
+	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
+	.zq_config = MT41J512M8RH125_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
+};
+
+static struct emif_regs ddr3_icev2_emif_reg_data = {
+	.sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
+	.ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
+	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
+	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
+	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
+	.zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
+	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
+				PHY_EN_DYN_PWRDN,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+#endif
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	env_init();
+	env_load();
+	if (env_get_yesno("boot_os") != 1)
+		return 1;
+#endif
+
+	return 0;
+}
+#endif
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	int ind = get_sys_clk_index();
+
+	if (board_is_evm_sk())
+		return &dpll_ddr3_303MHz[ind];
+	else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
+		return &dpll_ddr3_400MHz[ind];
+	else if (board_is_evm_15_or_later())
+		return &dpll_ddr3_303MHz[ind];
+	else
+		return &dpll_ddr2_266MHz[ind];
+}
+
+static u8 bone_not_connected_to_ac_power(void)
+{
+	if (board_is_bone()) {
+		uchar pmic_status_reg;
+		if (tps65217_reg_read(TPS65217_STATUS,
+				      &pmic_status_reg))
+			return 1;
+		if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
+			puts("No AC power, switching to default OPP\n");
+			return 1;
+		}
+	}
+	return 0;
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	int ind = get_sys_clk_index();
+	int freq = am335x_get_efuse_mpu_max_freq(cdev);
+
+	if (bone_not_connected_to_ac_power())
+		freq = MPUPLL_M_600;
+
+	if (board_is_pb() || board_is_bone_lt())
+		freq = MPUPLL_M_1000;
+
+	switch (freq) {
+	case MPUPLL_M_1000:
+		return &dpll_mpu_opp[ind][5];
+	case MPUPLL_M_800:
+		return &dpll_mpu_opp[ind][4];
+	case MPUPLL_M_720:
+		return &dpll_mpu_opp[ind][3];
+	case MPUPLL_M_600:
+		return &dpll_mpu_opp[ind][2];
+	case MPUPLL_M_500:
+		return &dpll_mpu_opp100;
+	case MPUPLL_M_300:
+		return &dpll_mpu_opp[ind][0];
+	}
+
+	return &dpll_mpu_opp[ind][0];
+}
+
+static void scale_vcores_bone(int freq)
+{
+	int usb_cur_lim, mpu_vdd;
+
+	/*
+	 * Only perform PMIC configurations if board rev > A1
+	 * on Beaglebone White
+	 */
+	if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
+		return;
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	if (i2c_probe(TPS65217_CHIP_PM))
+		return;
+#else
+	if (power_tps65217_init(0))
+		return;
+#endif
+
+
+	/*
+	 * On Beaglebone White we need to ensure we have AC power
+	 * before increasing the frequency.
+	 */
+	if (bone_not_connected_to_ac_power())
+		freq = MPUPLL_M_600;
+
+	/*
+	 * Override what we have detected since we know if we have
+	 * a Beaglebone Black it supports 1GHz.
+	 */
+	if (board_is_pb() || board_is_bone_lt())
+		freq = MPUPLL_M_1000;
+
+	switch (freq) {
+	case MPUPLL_M_1000:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		break;
+	case MPUPLL_M_800:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		break;
+	case MPUPLL_M_720:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		break;
+	case MPUPLL_M_600:
+	case MPUPLL_M_500:
+	case MPUPLL_M_300:
+	default:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		break;
+	}
+
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+			       TPS65217_POWER_PATH,
+			       usb_cur_lim,
+			       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set DCDC3 (CORE) voltage to 1.10V */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+				    TPS65217_DCDC_VOLT_SEL_1100MV)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/*
+	 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
+	 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
+	 */
+	if (board_is_bone()) {
+		if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+				       TPS65217_DEFLS1,
+				       TPS65217_LDO_VOLTAGE_OUT_3_3,
+				       TPS65217_LDO_MASK))
+			puts("tps65217_reg_write failure\n");
+	} else {
+		if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+				       TPS65217_DEFLS1,
+				       TPS65217_LDO_VOLTAGE_OUT_1_8,
+				       TPS65217_LDO_MASK))
+			puts("tps65217_reg_write failure\n");
+	}
+
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS2,
+			       TPS65217_LDO_VOLTAGE_OUT_3_3,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+}
+
+void scale_vcores_generic(int freq)
+{
+	int sil_rev, mpu_vdd;
+
+	/*
+	 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
+	 * MPU frequencies we support we use a CORE voltage of
+	 * 1.10V.  For MPU voltage we need to switch based on
+	 * the frequency we are running at.
+	 */
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
+		return;
+#else
+	if (power_tps65910_init(0))
+		return;
+#endif
+	/*
+	 * Depending on MPU clock and PG we will need a different
+	 * VDD to drive at that speed.
+	 */
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
+
+	/* Tell the TPS65910 to use i2c */
+	tps65910_set_i2c_control();
+
+	/* First update MPU voltage. */
+	if (tps65910_voltage_update(MPU, mpu_vdd))
+		return;
+
+	/* Second, update the CORE voltage. */
+	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
+		return;
+
+}
+
+void gpi2c_init(void)
+{
+	/* When needed to be invoked prior to BSS initialization */
+	static bool first_time = true;
+
+	if (first_time) {
+		enable_i2c0_pin_mux();
+#if !CONFIG_IS_ENABLED(DM_I2C)
+		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
+			 CONFIG_SYS_OMAP24_I2C_SLAVE);
+#endif
+		first_time = false;
+	}
+}
+
+void scale_vcores(void)
+{
+	int freq;
+
+	gpi2c_init();
+	freq = am335x_get_efuse_mpu_max_freq(cdev);
+
+	if (board_is_beaglebonex())
+		scale_vcores_bone(freq);
+	else
+		scale_vcores_generic(freq);
+}
+
+void set_uart_mux_conf(void)
+{
+#if CONFIG_CONS_INDEX == 1
+	enable_uart0_pin_mux();
+#elif CONFIG_CONS_INDEX == 2
+	enable_uart1_pin_mux();
+#elif CONFIG_CONS_INDEX == 3
+	enable_uart2_pin_mux();
+#elif CONFIG_CONS_INDEX == 4
+	enable_uart3_pin_mux();
+#elif CONFIG_CONS_INDEX == 5
+	enable_uart4_pin_mux();
+#elif CONFIG_CONS_INDEX == 6
+	enable_uart5_pin_mux();
+#endif
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs_evmsk = {
+	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_bonelt = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_evm15 = {
+	.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+	if (board_is_evm_sk()) {
+		/*
+		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
+		 * This is safe enough to do on older revs.
+		 */
+		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+	}
+
+	if (board_is_icev2()) {
+		gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
+		gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
+	}
+
+	if (board_is_evm_sk())
+		config_ddr(303, &ioregs_evmsk, &ddr3_data,
+			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+	else if (board_is_pb() || board_is_bone_lt())
+		config_ddr(400, &ioregs_bonelt,
+			   &ddr3_beagleblack_data,
+			   &ddr3_beagleblack_cmd_ctrl_data,
+			   &ddr3_beagleblack_emif_reg_data, 0);
+	else if (board_is_evm_15_or_later())
+		config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
+			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
+	else if (board_is_icev2())
+		config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
+			   &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
+			   0);
+	else if (board_is_gp_evm())
+		config_ddr(266, &ioregs, &ddr2_data,
+			   &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
+	else
+		config_ddr(266, &ioregs, &ddr2_data,
+			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
+}
+#endif
+
+#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
+static void request_and_set_gpio(int gpio, char *name, int val)
+{
+	int ret;
+
+	ret = gpio_request(gpio, name);
+	if (ret < 0) {
+		printf("%s: Unable to request %s\n", __func__, name);
+		return;
+	}
+
+	ret = gpio_direction_output(gpio, 0);
+	if (ret < 0) {
+		printf("%s: Unable to set %s  as output\n", __func__, name);
+		goto err_free_gpio;
+	}
+
+	gpio_set_value(gpio, val);
+
+	return;
+
+err_free_gpio:
+	gpio_free(gpio);
+}
+
+#define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N, 1);
+#define REQUEST_AND_CLR_GPIO(N)	request_and_set_gpio(N, #N, 0);
+
+/**
+ * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
+ * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
+ * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
+ * give 50MHz output for Eth0 and 1.
+ */
+static struct clk_synth cdce913_data = {
+	.id = 0x81,
+	.capacitor = 0x90,
+	.mux = 0x6d,
+	.pdiv2 = 0x2,
+	.pdiv3 = 0x2,
+};
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
+	defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
+
+#define MAX_CPSW_SLAVES	2
+
+/* At the moment, we do not want to stop booting for any failures here */
+int ft_board_setup(void *fdt, struct bd_info *bd)
+{
+	const char *slave_path, *enet_name;
+	int enetnode, slavenode, phynode;
+	struct udevice *ethdev;
+	char alias[16];
+	u32 phy_id[2];
+	int phy_addr;
+	int i, ret;
+
+	/* phy address fixup needed only on beagle bone family */
+	if (!board_is_beaglebonex())
+		goto done;
+
+	for (i = 0; i < MAX_CPSW_SLAVES; i++) {
+		sprintf(alias, "ethernet%d", i);
+
+		slave_path = fdt_get_alias(fdt, alias);
+		if (!slave_path)
+			continue;
+
+		slavenode = fdt_path_offset(fdt, slave_path);
+		if (slavenode < 0)
+			continue;
+
+		enetnode = fdt_parent_offset(fdt, slavenode);
+		enet_name = fdt_get_name(fdt, enetnode, NULL);
+
+		ethdev = eth_get_dev_by_name(enet_name);
+		if (!ethdev)
+			continue;
+
+		phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
+
+		/* check for phy_id as well as phy-handle properties */
+		ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
+						 phy_id, 2);
+		if (ret == 2) {
+			if (phy_id[1] != phy_addr) {
+				printf("fixing up phy_id for %s, old: %d, new: %d\n",
+				       alias, phy_id[1], phy_addr);
+
+				phy_id[0] = cpu_to_fdt32(phy_id[0]);
+				phy_id[1] = cpu_to_fdt32(phy_addr);
+				do_fixup_by_path(fdt, slave_path, "phy_id",
+						 phy_id, sizeof(phy_id), 0);
+			}
+		} else {
+			phynode = fdtdec_lookup_phandle(fdt, slavenode,
+							"phy-handle");
+			if (phynode < 0)
+				continue;
+
+			ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
+			if (ret < 0)
+				continue;
+
+			if (ret != phy_addr) {
+				printf("fixing up phy-handle for %s, old: %d, new: %d\n",
+				       alias, ret, phy_addr);
+
+				fdt_setprop_u32(fdt, phynode, "reg",
+						cpu_to_fdt32(phy_addr));
+			}
+		}
+	}
+
+done:
+	return 0;
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
+	gpmc_init();
+#endif
+
+#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
+	if (board_is_icev2()) {
+		int rv;
+		u32 reg;
+
+		REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
+		/* Make J19 status available on GPIO1_26 */
+		REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
+
+		REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
+		/*
+		 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
+		 * jumpers near the port. Read the jumper value and set
+		 * the pinmux, external mux and PHY clock accordingly.
+		 * As jumper line is overridden by PHY RX_DV pin immediately
+		 * after bootstrap (power-up/reset), we need to sample
+		 * it during PHY reset using GPIO rising edge detection.
+		 */
+		REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
+		/* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
+		reg = readl(GPIO0_RISINGDETECT) | BIT(11);
+		writel(reg, GPIO0_RISINGDETECT);
+		reg = readl(GPIO1_RISINGDETECT) | BIT(26);
+		writel(reg, GPIO1_RISINGDETECT);
+		/* Reset PHYs to capture the Jumper setting */
+		gpio_set_value(GPIO_PHY_RESET, 0);
+		udelay(2);	/* PHY datasheet states 1uS min. */
+		gpio_set_value(GPIO_PHY_RESET, 1);
+
+		reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
+		if (reg) {
+			writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
+			/* RMII mode */
+			printf("ETH0, CPSW\n");
+		} else {
+			/* MII mode */
+			printf("ETH0, PRU\n");
+			cdce913_data.pdiv3 = 4;	/* 25MHz PHY clk */
+		}
+
+		reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
+		if (reg) {
+			writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
+			/* RMII mode */
+			printf("ETH1, CPSW\n");
+			gpio_set_value(GPIO_MUX_MII_CTRL, 1);
+		} else {
+			/* MII mode */
+			printf("ETH1, PRU\n");
+			cdce913_data.pdiv2 = 4;	/* 25MHz PHY clk */
+		}
+
+		/* disable rising edge IRQs */
+		reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
+		writel(reg, GPIO0_RISINGDETECT);
+		reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
+		writel(reg, GPIO1_RISINGDETECT);
+
+		rv = setup_clock_synthesizer(&cdce913_data);
+		if (rv) {
+			printf("Clock synthesizer setup failed %d\n", rv);
+			return rv;
+		}
+
+		/* reset PHYs */
+		gpio_set_value(GPIO_PHY_RESET, 0);
+		udelay(2);	/* PHY datasheet states 1uS min. */
+		gpio_set_value(GPIO_PHY_RESET, 1);
+	}
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	struct udevice *dev;
+#if !defined(CONFIG_SPL_BUILD)
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	char *name = NULL;
+
+	if (board_is_bone_lt()) {
+		/* BeagleBoard.org BeagleBone Black Wireless: */
+		if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
+			name = "BBBW";
+		}
+		/* SeeedStudio BeagleBone Green Wireless */
+		if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
+			name = "BBGW";
+		}
+		/* BeagleBoard.org BeagleBone Blue */
+		if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
+			name = "BBBL";
+		}
+	}
+
+	if (board_is_bbg1())
+		name = "BBG1";
+	if (board_is_bben())
+		name = "BBEN";
+	set_board_info_env(name);
+
+	/*
+	 * Default FIT boot on HS devices. Non FIT images are not allowed
+	 * on HS devices.
+	 */
+	if (get_device_type() == HS_DEVICE)
+		env_set("boot_fit", "1");
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!env_get("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+	}
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!env_get("eth1addr")) {
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("eth1addr", mac_addr);
+	}
+#endif
+
+	if (!env_get("serial#")) {
+		char *board_serial = env_get("board_serial");
+		char *ethaddr = env_get("ethaddr");
+
+		if (!board_serial || !strncmp(board_serial, "unknown", 7))
+			env_set("serial#", ethaddr);
+		else
+			env_set("serial#", board_serial);
+	}
+
+	/* Just probe the potentially supported cdce913 device */
+	uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
+
+	return 0;
+}
+#endif
+
+/* CPSW plat */
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+struct cpsw_slave_data slave_data[] = {
+	{
+		.slave_reg_ofs  = CPSW_SLAVE0_OFFSET,
+		.sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
+		.phy_addr       = 0,
+	},
+	{
+		.slave_reg_ofs  = CPSW_SLAVE1_OFFSET,
+		.sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
+		.phy_addr       = 1,
+	},
+};
+
+struct cpsw_platform_data am335_eth_data = {
+	.cpsw_base		= CPSW_BASE,
+	.version		= CPSW_CTRL_VERSION_2,
+	.bd_ram_ofs		= CPSW_BD_OFFSET,
+	.ale_reg_ofs		= CPSW_ALE_OFFSET,
+	.cpdma_reg_ofs		= CPSW_CPDMA_OFFSET,
+	.mdio_div		= CPSW_MDIO_DIV,
+	.host_port_reg_ofs	= CPSW_HOST_PORT_OFFSET,
+	.channels		= 8,
+	.slaves			= 2,
+	.slave_data		= slave_data,
+	.ale_entries		= 1024,
+	.mac_control		= 0x20,
+	.active_slave		= 0,
+	.mdio_base		= 0x4a101000,
+	.gmii_sel		= 0x44e10650,
+	.phy_sel_compat		= "ti,am3352-cpsw-phy-sel",
+	.syscon_addr		= 0x44e10630,
+	.macid_sel_compat	= "cpsw,am33xx",
+};
+
+struct eth_pdata cpsw_pdata = {
+	.iobase = 0x4a100000,
+	.phy_interface = 0,
+	.priv_pdata = &am335_eth_data,
+};
+
+U_BOOT_DRVINFO(am335x_eth) = {
+	.name = "eth_cpsw",
+	.plat = &cpsw_pdata,
+};
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
+		return 0;
+	else if (board_is_bone() && !strcmp(name, "am335x-bone"))
+		return 0;
+	else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
+		return 0;
+	else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
+		return 0;
+	else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
+		return 0;
+	else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
+		return 0;
+	else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
+		return 0;
+	else
+		return -1;
+}
+#endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+	secure_boot_verify_image(p_image, p_size);
+}
+#endif
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct omap_hsmmc_plat am335x_mmc0_plat = {
+	.base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
+	.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
+	.cfg.f_min = 400000,
+	.cfg.f_max = 52000000,
+	.cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
+	.cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+
+U_BOOT_DRVINFO(am335x_mmc0) = {
+	.name = "omap_hsmmc",
+	.plat = &am335x_mmc0_plat,
+};
+
+static const struct omap_hsmmc_plat am335x_mmc1_plat = {
+	.base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
+	.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
+	.cfg.f_min = 400000,
+	.cfg.f_max = 52000000,
+	.cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
+	.cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+
+U_BOOT_DRVINFO(am335x_mmc1) = {
+	.name = "omap_hsmmc",
+	.plat = &am335x_mmc1_plat,
+};
+#endif
diff --git a/roms/u-boot/board/ti/am335x/board.h b/roms/u-boot/board/ti/am335x/board.h
new file mode 100644
index 000000000..c2962111c
--- /dev/null
+++ b/roms/u-boot/board/ti/am335x/board.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/**
+ * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and
+ * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame
+ * Synchronization Lost errors. The values are the biggest that work
+ * reliably with offered video modes and the memory subsystem on the
+ * boards. These register have are briefly documented in "7.3.3.5.2
+ * Command Starvation" section of AM335x TRM. The REG_COS_COUNT_1 and
+ * REG_COS_COUNT_2 do not have any effect on current versions of
+ * AM335x.
+ */
+#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK       0x00141414
+#define EMIF_OCP_CONFIG_AM335X_EVM             0x003d3d3d
+
+static inline int board_is_bone(void)
+{
+	return board_ti_is("A335BONE");
+}
+
+static inline int board_is_bone_lt(void)
+{
+	return board_ti_is("A335BNLT");
+}
+
+static inline int board_is_pb(void)
+{
+	return board_ti_is("A335PBGL");
+}
+
+static inline int board_is_bbg1(void)
+{
+	return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4);
+}
+
+static inline int board_is_bben(void)
+{
+	return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "SE", 2);
+}
+
+static inline int board_is_beaglebonex(void)
+{
+	return board_is_pb() || board_is_bone() || board_is_bone_lt() ||
+	       board_is_bbg1() || board_is_bben();
+}
+
+static inline int board_is_evm_sk(void)
+{
+	return board_ti_is("A335X_SK");
+}
+
+static inline int board_is_idk(void)
+{
+	return !strncmp(board_ti_get_config(), "SKU#02", 6);
+}
+
+static inline int board_is_gp_evm(void)
+{
+	return board_ti_is("A33515BB");
+}
+
+static inline int board_is_evm_15_or_later(void)
+{
+	return (board_is_gp_evm() &&
+		strncmp("1.5", board_ti_get_rev(), 3) <= 0);
+}
+
+static inline int board_is_icev2(void)
+{
+	return board_ti_is("A335_ICE") && !strncmp("2", board_ti_get_rev(), 1);
+}
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_i2c2_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/roms/u-boot/board/ti/am335x/mux.c b/roms/u-boot/board/ti/am335x/mux.c
new file mode 100644
index 000000000..e450ff64d
--- /dev/null
+++ b/roms/u-boot/board/ti/am335x/mux.c
@@ -0,0 +1,442 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "../common/board_detect.h"
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART1_RXD */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},		/* UART1_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART2_RXD */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
+	{OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* GPIO0_6 */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_CD */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+	{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)},	/* I2C_DATA */
+	{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)},	/* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux i2c2_pin_mux[] = {
+	{OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE |
+			PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* I2C_DATA */
+	{OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE |
+			PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_SCLK */
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_D0 */
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
+	{-1},
+};
+
+static struct module_pin_mux gpio0_7_pin_mux[] = {
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)},	/* GPIO0_7 */
+	{-1},
+};
+
+static struct module_pin_mux gpio0_18_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)},	/* GPIO0_18 */
+	{-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1)},			/* MII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* MII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REFCLK */
+	{-1},
+};
+
+#ifdef CONFIG_MTD_RAW_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0  */
+	{OFFSET(gpmc_ad1),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1  */
+	{OFFSET(gpmc_ad2),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2  */
+	{OFFSET(gpmc_ad3),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3  */
+	{OFFSET(gpmc_ad4),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4  */
+	{OFFSET(gpmc_ad5),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5  */
+	{OFFSET(gpmc_ad6),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6  */
+	{OFFSET(gpmc_ad7),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7  */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+	{OFFSET(gpmc_ad8),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8  */
+	{OFFSET(gpmc_ad9),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9  */
+	{OFFSET(gpmc_ad10),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
+	{OFFSET(gpmc_ad11),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
+	{OFFSET(gpmc_ad12),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
+	{OFFSET(gpmc_ad13),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
+	{OFFSET(gpmc_ad14),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
+	{OFFSET(gpmc_ad15),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
+#endif
+	{OFFSET(gpmc_wait0),	(MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
+	{OFFSET(gpmc_wpn),	(MODE(7) | PULLUP_EN)},		   /* nWP */
+	{OFFSET(gpmc_csn0),	(MODE(0) | PULLUP_EN)},		   /* nCS */
+	{OFFSET(gpmc_wen),	(MODE(0) | PULLDOWN_EN)},	   /* WEN */
+	{OFFSET(gpmc_oen_ren),	(MODE(0) | PULLDOWN_EN)},	   /* OE */
+	{OFFSET(gpmc_advn_ale),	(MODE(0) | PULLDOWN_EN)},	   /* ADV_ALE */
+	{OFFSET(gpmc_be0n_cle),	(MODE(0) | PULLDOWN_EN)},	   /* BE_CLE */
+	{-1},
+};
+#elif defined(CONFIG_NOR)
+static struct module_pin_mux bone_norcape_pin_mux[] = {
+	{OFFSET(gpmc_a0), MODE(0) | PULLUDDIS},			/* NOR_A0 */
+	{OFFSET(gpmc_a1), MODE(0) | PULLUDDIS},			/* NOR_A1 */
+	{OFFSET(gpmc_a2), MODE(0) | PULLUDDIS},			/* NOR_A2 */
+	{OFFSET(gpmc_a3), MODE(0) | PULLUDDIS},			/* NOR_A3 */
+	{OFFSET(gpmc_a4), MODE(0) | PULLUDDIS},			/* NOR_A4 */
+	{OFFSET(gpmc_a5), MODE(0) | PULLUDDIS},			/* NOR_A5 */
+	{OFFSET(gpmc_a6), MODE(0) | PULLUDDIS},			/* NOR_A6 */
+	{OFFSET(gpmc_a7), MODE(0) | PULLUDDIS},			/* NOR_A7 */
+	{OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD0 */
+	{OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD1 */
+	{OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD2 */
+	{OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD3 */
+	{OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD4 */
+	{OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD5 */
+	{OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD6 */
+	{OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD7 */
+	{OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD8 */
+	{OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD9 */
+	{OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD10 */
+	{OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD11 */
+	{OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD12 */
+	{OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD13 */
+	{OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD14 */
+	{OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD15 */
+	{OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN},     /* CE */
+	{OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
+	{OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
+	{OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
+	{OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN},    /* WEN */
+	{OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
+	{-1},
+};
+#endif
+
+static struct module_pin_mux uart3_icev2_pin_mux[] = {
+	{OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(mii1_rxd2), MODE(1) | PULLUDEN},		/* UART3_TXD */
+	{-1},
+};
+
+#if defined(CONFIG_NOR_BOOT)
+void enable_norboot_pin_mux(void)
+{
+	configure_module_pin_mux(bone_norcape_pin_mux);
+}
+#endif
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+	configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+	configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_i2c2_pin_mux(void)
+{
+	configure_module_pin_mux(i2c2_pin_mux);
+}
+
+/*
+ * The AM335x GP EVM, if daughter card(s) are connected, can have 8
+ * different profiles.  These profiles determine what peripherals are
+ * valid and need pinmux to be configured.
+ */
+#define PROFILE_NONE	0x0
+#define PROFILE_0	(1 << 0)
+#define PROFILE_1	(1 << 1)
+#define PROFILE_2	(1 << 2)
+#define PROFILE_3	(1 << 3)
+#define PROFILE_4	(1 << 4)
+#define PROFILE_5	(1 << 5)
+#define PROFILE_6	(1 << 6)
+#define PROFILE_7	(1 << 7)
+#define PROFILE_MASK	0x7
+#define PROFILE_ALL	0xFF
+
+/* CPLD registers */
+#define I2C_CPLD_ADDR	0x35
+#define CFG_REG		0x10
+
+static unsigned short detect_daughter_board_profile(void)
+{
+	unsigned short val;
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	if (i2c_probe(I2C_CPLD_ADDR))
+		return PROFILE_NONE;
+
+	if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
+		return PROFILE_NONE;
+#else
+	struct udevice *dev = NULL;
+	int rc;
+
+	rc = i2c_get_chip_for_busnum(0, I2C_CPLD_ADDR, 1, &dev);
+	if (rc)
+		return PROFILE_NONE;
+	rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2);
+	if (rc)
+		return PROFILE_NONE;
+#endif
+	return (1 << (val & PROFILE_MASK));
+}
+
+void enable_board_pin_mux(void)
+{
+	/* Do board-specific muxes. */
+	if (board_is_bone()) {
+		/* Beaglebone pinmux */
+		configure_module_pin_mux(mii1_pin_mux);
+		configure_module_pin_mux(mmc0_pin_mux);
+#if defined(CONFIG_MTD_RAW_NAND)
+		configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_NOR)
+		configure_module_pin_mux(bone_norcape_pin_mux);
+#else
+		configure_module_pin_mux(mmc1_pin_mux);
+#endif
+		configure_module_pin_mux(i2c2_pin_mux);
+	} else if (board_is_gp_evm()) {
+		/* General Purpose EVM */
+		unsigned short profile = detect_daughter_board_profile();
+		configure_module_pin_mux(rgmii1_pin_mux);
+		configure_module_pin_mux(mmc0_pin_mux);
+		/* In profile #2 i2c1 and spi0 conflict. */
+		if (profile & ~PROFILE_2)
+			configure_module_pin_mux(i2c1_pin_mux);
+		/* Profiles 2 & 3 don't have NAND */
+#ifdef CONFIG_MTD_RAW_NAND
+		if (profile & ~(PROFILE_2 | PROFILE_3))
+			configure_module_pin_mux(nand_pin_mux);
+#endif
+		else if (profile == PROFILE_2) {
+			configure_module_pin_mux(mmc1_pin_mux);
+			configure_module_pin_mux(spi0_pin_mux);
+		}
+	} else if (board_is_idk()) {
+		/* Industrial Motor Control (IDK) */
+		configure_module_pin_mux(mii1_pin_mux);
+		configure_module_pin_mux(mmc0_no_cd_pin_mux);
+	} else if (board_is_evm_sk()) {
+		/* Starter Kit EVM */
+		configure_module_pin_mux(i2c1_pin_mux);
+		configure_module_pin_mux(gpio0_7_pin_mux);
+		configure_module_pin_mux(rgmii1_pin_mux);
+		configure_module_pin_mux(mmc0_pin_mux_sk_evm);
+	} else if (board_is_bone_lt()) {
+		if (board_is_bben()) {
+			/* SanCloud Beaglebone LT Enhanced pinmux */
+			configure_module_pin_mux(rgmii1_pin_mux);
+		} else {
+			/* Beaglebone LT pinmux */
+			configure_module_pin_mux(mii1_pin_mux);
+		}
+		/* Beaglebone LT pinmux */
+		configure_module_pin_mux(mmc0_pin_mux);
+#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_EMMC_BOOT)
+		configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
+		configure_module_pin_mux(bone_norcape_pin_mux);
+#else
+		configure_module_pin_mux(mmc1_pin_mux);
+#endif
+		configure_module_pin_mux(i2c2_pin_mux);
+	} else if (board_is_pb()) {
+		configure_module_pin_mux(mii1_pin_mux);
+		configure_module_pin_mux(mmc0_pin_mux);
+	} else if (board_is_icev2()) {
+		configure_module_pin_mux(mmc0_pin_mux);
+		configure_module_pin_mux(gpio0_18_pin_mux);
+		configure_module_pin_mux(uart3_icev2_pin_mux);
+		configure_module_pin_mux(rmii1_pin_mux);
+		configure_module_pin_mux(spi0_pin_mux);
+	} else {
+		/* Unknown board. We might still be able to boot. */
+		puts("Bad EEPROM or unknown board, cannot configure pinmux.");
+	}
+}
diff --git a/roms/u-boot/board/ti/am335x/u-boot.lds b/roms/u-boot/board/ti/am335x/u-boot.lds
new file mode 100644
index 000000000..03c1d5f73
--- /dev/null
+++ b/roms/u-boot/board/ti/am335x/u-boot.lds
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+		board/ti/am335x/built-in.o (.text*)
+	}
+
+	/* This needs to come before *(.text*) */
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(.text.efi_runtime*)
+		*(.rodata.efi_runtime*)
+		*(.data.efi_runtime*)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.text_rest :
+	{
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.rel*.efi_runtime)
+		*(.rel*.efi_runtime.*)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}
diff --git a/roms/u-boot/board/ti/am43xx/Kconfig b/roms/u-boot/board/ti/am43xx/Kconfig
new file mode 100644
index 000000000..9cb80cc3f
--- /dev/null
+++ b/roms/u-boot/board/ti/am43xx/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_AM43XX_EVM
+
+config SYS_BOARD
+	default "am43xx"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "am43xx_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/ti/am43xx/MAINTAINERS b/roms/u-boot/board/ti/am43xx/MAINTAINERS
new file mode 100644
index 000000000..ab9da22c6
--- /dev/null
+++ b/roms/u-boot/board/ti/am43xx/MAINTAINERS
@@ -0,0 +1,10 @@
+AM43XX BOARD
+M:	Lokesh Vutla <lokeshvutla@ti.com>
+S:	Maintained
+F:	board/ti/am43xx/
+F:	include/configs/am43xx_evm.h
+F:	configs/am43xx_evm_defconfig
+F:	configs/am43xx_evm_qspiboot_defconfig
+F:	configs/am43xx_evm_usbhost_boot_defconfig
+F:	configs/am43xx_evm_rtconly_defconfig
+F:	configs/am43xx_hs_evm_defconfig
diff --git a/roms/u-boot/board/ti/am43xx/Makefile b/roms/u-boot/board/ti/am43xx/Makefile
new file mode 100644
index 000000000..60a11d8c0
--- /dev/null
+++ b/roms/u-boot/board/ti/am43xx/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/roms/u-boot/board/ti/am43xx/board.c b/roms/u-boot/board/ti/am43xx/board.c
new file mode 100644
index 000000000..e9febb959
--- /dev/null
+++ b/roms/u-boot/board/ti/am43xx/board.c
@@ -0,0 +1,910 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for TI AM43XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <eeprom.h>
+#include <image.h>
+#include <asm/global_data.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <linux/errno.h>
+#include <spl.h>
+#include <usb.h>
+#include <asm/omap_sec_common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/emif.h>
+#include <asm/omap_common.h>
+#include "../common/board_detect.h"
+#include "board.h"
+#include <power/pmic.h>
+#include <power/tps65218.h>
+#include <power/tps62362.h>
+#include <linux/usb/gadget.h>
+#include <dwc3-uboot.h>
+#include <dwc3-omap-uboot.h>
+#include <ti-usb-phy-uboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+void do_board_detect(void)
+{
+	/* Ensure I2C is initialized for EEPROM access*/
+	gpi2c_init();
+	if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+				 CONFIG_EEPROM_CHIP_ADDRESS))
+		printf("ti_i2c_eeprom_init failed\n");
+}
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
+	{	/* 19.2 MHz */
+		{125, 3, 2, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{125, 3, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{150, 3, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{125, 2, 1, -1, -1, -1, -1},	/* OPP TB */
+		{625, 11, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 24 MHz */
+		{300, 23, 1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{600, 23, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{720, 23, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{800, 23, 1, -1, -1, -1, -1},	/* OPP TB */
+		{1000, 23, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 25 MHz */
+		{300, 24, 1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{600, 24, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{720, 24, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{800, 24, 1, -1, -1, -1, -1},	/* OPP TB */
+		{1000, 24, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 26 MHz */
+		{300, 25, 1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{600, 25, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{720, 25, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{800, 25, 1, -1, -1, -1, -1},	/* OPP TB */
+		{1000, 25, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+};
+
+const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
+		{625, 11, -1, -1, 10, 8, 4},	/* 19.2 MHz */
+		{1000, 23, -1, -1, 10, 8, 4},	/* 24 MHz */
+		{1000, 24, -1, -1, 10, 8, 4},	/* 25 MHz */
+		{1000, 25, -1, -1, 10, 8, 4}	/* 26 MHz */
+};
+
+const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
+		{400, 7, 5, -1, -1, -1, -1},	/* 19.2 MHz */
+		{400, 9, 5, -1, -1, -1, -1},	/* 24 MHz */
+		{384, 9, 5, -1, -1, -1, -1},	/* 25 MHz */
+		{480, 12, 5, -1, -1, -1, -1}	/* 26 MHz */
+};
+
+const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
+		{665, 47, 1, -1, 4, -1, -1}, /*19.2*/
+		{133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
+		{266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
+		{133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
+};
+
+const struct dpll_params gp_evm_dpll_ddr = {
+		50, 2, 1, -1, 2, -1, -1};
+
+static const struct dpll_params idk_dpll_ddr = {
+	400, 23, 1, -1, 2, -1, -1
+};
+
+static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
+	0x00500050,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x40001000,
+	0x08102040
+};
+
+const struct ctrl_ioregs ioregs_lpddr2 = {
+	.cm0ioctl		= LPDDR2_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0x1,
+};
+
+const struct emif_regs emif_regs_lpddr2 = {
+	.sdram_config			= 0x808012BA,
+	.ref_ctrl			= 0x0000040D,
+	.sdram_tim1			= 0xEA86B411,
+	.sdram_tim2			= 0x103A094A,
+	.sdram_tim3			= 0x0F6BA37F,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
+	.emif_rd_wr_lvl_ctl		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E284006,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04010040,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00500050,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config			= 0x000FFFFF
+};
+
+const struct ctrl_ioregs ioregs_ddr3 = {
+	.cm0ioctl		= DDR3_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0xc163,
+};
+
+const struct emif_regs ddr3_emif_regs_400Mhz = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00400040,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
+	.emif_rd_wr_lvl_ctl		= 0x0,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000065,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
+	.emif_ddr_ext_phy_ctrl_4	= 0x000000B5,
+	.emif_ddr_ext_phy_ctrl_5	= 0x000000E5,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_production = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x00048008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000066,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
+	.emif_ddr_ext_phy_ctrl_4	= 0x000000B9,
+	.emif_ddr_ext_phy_ctrl_5	= 0x000000E6,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
+	.sdram_config			= 0x638413b2,
+	.sdram_config2			= 0x00000000,
+	.ref_ctrl			= 0x00000c30,
+	.sdram_tim1			= 0xeaaad4db,
+	.sdram_tim2			= 0x266b7fda,
+	.sdram_tim3			= 0x107f8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074be4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0e084008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x89,
+	.emif_ddr_ext_phy_ctrl_3	= 0x90,
+	.emif_ddr_ext_phy_ctrl_4	= 0x8e,
+	.emif_ddr_ext_phy_ctrl_5	= 0x8d,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x00000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x80000000,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
+	.sdram_config			= 0x61a11b32,
+	.sdram_config2			= 0x00000000,
+	.ref_ctrl			= 0x00000c30,
+	.sdram_tim1			= 0xeaaad4db,
+	.sdram_tim2			= 0x266b7fda,
+	.sdram_tim3			= 0x107f8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074be4,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1		= 0x00008009,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000040,
+	.emif_ddr_ext_phy_ctrl_3	= 0x0000003e,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00000051,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00000051,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x00000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000405,
+	.emif_prio_class_serv_map	= 0x00000000,
+	.emif_connect_id_serv_1_map	= 0x00000000,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x00ffffff
+};
+
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+	if (board_is_eposevm()) {
+		*regs = ext_phy_ctrl_const_base_lpddr2;
+		*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+	}
+
+	return;
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	int ind = get_sys_clk_index();
+
+	if (board_is_eposevm())
+		return &epos_evm_dpll_ddr[ind];
+	else if (board_is_evm() || board_is_sk())
+		return &gp_evm_dpll_ddr;
+	else if (board_is_idk())
+		return &idk_dpll_ddr;
+
+	printf(" Board '%s' not supported\n", board_ti_get_name());
+	return NULL;
+}
+
+
+/*
+ * get_opp_offset:
+ * Returns the index for safest OPP of the device to boot.
+ * max_off:	Index of the MAX OPP in DEV ATTRIBUTE register.
+ * min_off:	Index of the MIN OPP in DEV ATTRIBUTE register.
+ * This data is read from dev_attribute register which is e-fused.
+ * A'1' in bit indicates OPP disabled and not available, a '0' indicates
+ * OPP available. Lowest OPP starts with min_off. So returning the
+ * bit with rightmost '0'.
+ */
+static int get_opp_offset(int max_off, int min_off)
+{
+	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+	int opp, offset, i;
+
+	/* Bits 0:11 are defined to be the MPU_MAX_FREQ */
+	opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
+
+	for (i = max_off; i >= min_off; i--) {
+		offset = opp & (1 << i);
+		if (!offset)
+			return i;
+	}
+
+	return min_off;
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
+	u32 ind = get_sys_clk_index();
+
+	return &dpll_mpu[ind][opp];
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+	int ind = get_sys_clk_index();
+
+	return &dpll_core[ind];
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+	int ind = get_sys_clk_index();
+
+	return &dpll_per[ind];
+}
+
+void scale_vcores_generic(u32 m)
+{
+	int mpu_vdd, ddr_volt;
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	if (i2c_probe(TPS65218_CHIP_PM))
+		return;
+#else
+	if (power_tps65218_init(0))
+		return;
+#endif
+
+	switch (m) {
+	case 1000:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
+		break;
+	case 800:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
+		break;
+	case 720:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
+		break;
+	case 600:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
+		break;
+	case 300:
+		mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
+		break;
+	default:
+		puts("Unknown MPU clock, not scaling\n");
+		return;
+	}
+
+	/* Set DCDC1 (CORE) voltage to 1.1V */
+	if (tps65218_voltage_update(TPS65218_DCDC1,
+				    TPS65218_DCDC_VOLT_SEL_1100MV)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
+
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
+
+	if (board_is_eposevm())
+		ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
+	else
+		ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
+
+	/* Set DCDC3 (DDR) voltage */
+	if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
+}
+
+void scale_vcores_idk(u32 m)
+{
+	int mpu_vdd;
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	if (i2c_probe(TPS62362_I2C_ADDR))
+		return;
+#else
+	if (power_tps62362_init(0))
+		return;
+#endif
+
+	switch (m) {
+	case 1000:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
+		break;
+	case 800:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
+		break;
+	case 720:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
+		break;
+	case 600:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
+		break;
+	case 300:
+		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
+		break;
+	default:
+		puts("Unknown MPU clock, not scaling\n");
+		return;
+	}
+	/* Set VDD_MPU voltage */
+	if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
+}
+void gpi2c_init(void)
+{
+	/* When needed to be invoked prior to BSS initialization */
+	static bool first_time = true;
+
+	if (first_time) {
+		enable_i2c0_pin_mux();
+#if !CONFIG_IS_ENABLED(DM_I2C)
+		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
+			 CONFIG_SYS_OMAP24_I2C_SLAVE);
+#endif
+		first_time = false;
+	}
+}
+
+void scale_vcores(void)
+{
+	const struct dpll_params *mpu_params;
+
+	/* Ensure I2C is initialized for PMIC configuration */
+	gpi2c_init();
+
+	/* Get the frequency */
+	mpu_params = get_dpll_mpu_params();
+
+	if (board_is_idk())
+		scale_vcores_idk(mpu_params->m);
+	else
+		scale_vcores_generic(mpu_params->m);
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+static void enable_vtt_regulator(void)
+{
+	u32 temp;
+
+	/* enable module */
+	writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
+
+	/* enable output for GPIO5_7 */
+	writel(GPIO_SETDATAOUT(7),
+	       AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
+	temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+	temp = temp & ~(GPIO_OE_ENABLE(7));
+	writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+}
+
+enum {
+	RTC_BOARD_EPOS = 1,
+	RTC_BOARD_EVM14,
+	RTC_BOARD_EVM12,
+	RTC_BOARD_GPEVM,
+	RTC_BOARD_SK,
+};
+
+/*
+ * In the rtc_only+DRR in self-refresh boot path we have the board type info
+ * in the rtc scratch pad register hence we bypass the costly i2c reads to
+ * eeprom and directly programthe board name string
+ */
+void rtc_only_update_board_type(u32 btype)
+{
+	const char *name = "";
+	const char *rev = "1.0";
+
+	switch (btype) {
+	case RTC_BOARD_EPOS:
+		name = "AM43EPOS";
+		break;
+	case RTC_BOARD_EVM14:
+		name = "AM43__GP";
+		rev = "1.4";
+		break;
+	case RTC_BOARD_EVM12:
+		name = "AM43__GP";
+		rev = "1.2";
+		break;
+	case RTC_BOARD_GPEVM:
+		name = "AM43__GP";
+		break;
+	case RTC_BOARD_SK:
+		name = "AM43__SK";
+		break;
+	}
+	ti_i2c_eeprom_am_set(name, rev);
+}
+
+u32 rtc_only_get_board_type(void)
+{
+	if (board_is_eposevm())
+		return RTC_BOARD_EPOS;
+	else if (board_is_evm_14_or_later())
+		return RTC_BOARD_EVM14;
+	else if (board_is_evm_12_or_later())
+		return RTC_BOARD_EVM12;
+	else if (board_is_gpevm())
+		return RTC_BOARD_GPEVM;
+	else if (board_is_sk())
+		return RTC_BOARD_SK;
+
+	return 0;
+}
+
+void sdram_init(void)
+{
+	/*
+	 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
+	 * GP EMV has 1GB DDR3 connected to EMIF
+	 * along with VTT regulator.
+	 */
+	if (board_is_eposevm()) {
+		config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
+	} else if (board_is_evm_14_or_later()) {
+		enable_vtt_regulator();
+		config_ddr(0, &ioregs_ddr3, NULL, NULL,
+			   &ddr3_emif_regs_400Mhz_production, 0);
+	} else if (board_is_evm_12_or_later()) {
+		enable_vtt_regulator();
+		config_ddr(0, &ioregs_ddr3, NULL, NULL,
+			   &ddr3_emif_regs_400Mhz_beta, 0);
+	} else if (board_is_evm()) {
+		enable_vtt_regulator();
+		config_ddr(0, &ioregs_ddr3, NULL, NULL,
+			   &ddr3_emif_regs_400Mhz, 0);
+	} else if (board_is_sk()) {
+		config_ddr(400, &ioregs_ddr3, NULL, NULL,
+			   &ddr3_sk_emif_regs_400Mhz, 0);
+	} else if (board_is_idk()) {
+		config_ddr(400, &ioregs_ddr3, NULL, NULL,
+			   &ddr3_idk_emif_regs_400Mhz, 0);
+	}
+}
+#endif
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	int rc;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	struct pmic *p = NULL;
+#endif
+	if (board_is_idk()) {
+		rc = power_tps62362_init(0);
+		if (rc)
+			goto done;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+		p = pmic_get("TPS62362");
+		if (!p || pmic_probe(p))
+			goto done;
+#endif
+		puts("PMIC:  TPS62362\n");
+	} else {
+		rc = power_tps65218_init(0);
+		if (rc)
+			goto done;
+#if !CONFIG_IS_ENABLED(DM_I2C)
+		p = pmic_get("TPS65218_PMIC");
+		if (!p || pmic_probe(p))
+			goto done;
+#endif
+		puts("PMIC:  TPS65218\n");
+	}
+done:
+	return 0;
+}
+
+int board_init(void)
+{
+	struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
+	u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
+	    modena_init0_bw_integer, modena_init0_watermark_0;
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+
+	/*
+	 * Call this to initialize *ctrl again
+	 */
+	hw_data_init();
+
+	/* Clear all important bits for DSS errata that may need to be tweaked*/
+	mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
+	                   MREQPRIO_0_SAB_INIT0_MASK;
+
+	mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
+
+	modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
+	                                   BW_LIMITER_BW_FRAC_MASK;
+
+	modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
+	                                BW_LIMITER_BW_INT_MASK;
+
+	modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
+	                                 BW_LIMITER_BW_WATERMARK_MASK;
+
+	/* Setting MReq Priority of the DSS*/
+	mreqprio_0 |= 0x77;
+
+	/*
+	 * Set L3 Fast Configuration Register
+	 * Limiting bandwith for ARM core to 700 MBPS
+	 */
+	modena_init0_bw_fractional |= 0x10;
+	modena_init0_bw_integer |= 0x3;
+
+	writel(mreqprio_0, &cdev->mreqprio_0);
+	writel(mreqprio_1, &cdev->mreqprio_1);
+
+	writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
+	writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
+	writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+static int device_okay(const char *path)
+{
+	int node;
+
+	node = fdt_path_offset(gd->fdt_blob, path);
+	if (node < 0)
+		return 0;
+
+	return fdtdec_get_is_enabled(gd->fdt_blob, node);
+}
+#endif
+
+int board_late_init(void)
+{
+	struct udevice *dev;
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info_env(NULL);
+
+	/*
+	 * Default FIT boot on HS devices. Non FIT images are not allowed
+	 * on HS devices.
+	 */
+	if (get_device_type() == HS_DEVICE)
+		env_set("boot_fit", "1");
+#endif
+
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+	if (device_okay("/ocp/omap_dwc3@48380000"))
+		enable_usb_clocks(0);
+	if (device_okay("/ocp/omap_dwc3@483c0000"))
+		enable_usb_clocks(1);
+#endif
+
+	/* Just probe the potentially supported cdce913 device */
+	uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
+
+	return 0;
+}
+#endif
+
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device usb_otg_ss1 = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = USB_OTG_SS1_BASE,
+	.tx_fifo_resize = false,
+	.index = 0,
+};
+
+static struct dwc3_omap_device usb_otg_ss1_glue = {
+	.base = (void *)USB_OTG_SS1_GLUE_BASE,
+	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
+	.index = 0,
+};
+
+static struct ti_usb_phy_device usb_phy1_device = {
+	.usb2_phy_power = (void *)USB2_PHY1_POWER,
+	.index = 0,
+};
+
+static struct dwc3_device usb_otg_ss2 = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = USB_OTG_SS2_BASE,
+	.tx_fifo_resize = false,
+	.index = 1,
+};
+
+static struct dwc3_omap_device usb_otg_ss2_glue = {
+	.base = (void *)USB_OTG_SS2_GLUE_BASE,
+	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
+	.index = 1,
+};
+
+static struct ti_usb_phy_device usb_phy2_device = {
+	.usb2_phy_power = (void *)USB2_PHY2_POWER,
+	.index = 1,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+	u32 status;
+
+	status = dwc3_omap_uboot_interrupt_status(index);
+	if (status)
+		dwc3_uboot_handle_interrupt(index);
+
+	return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
+int board_usb_init(int index, enum usb_init_type init)
+{
+	enable_usb_clocks(index);
+#ifdef CONFIG_USB_DWC3
+	switch (index) {
+	case 0:
+		if (init == USB_INIT_DEVICE) {
+			usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
+			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+			dwc3_omap_uboot_init(&usb_otg_ss1_glue);
+			ti_usb_phy_uboot_init(&usb_phy1_device);
+			dwc3_uboot_init(&usb_otg_ss1);
+		}
+		break;
+	case 1:
+		if (init == USB_INIT_DEVICE) {
+			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
+			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+			ti_usb_phy_uboot_init(&usb_phy2_device);
+			dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+			dwc3_uboot_init(&usb_otg_ss2);
+		}
+		break;
+	default:
+		printf("Invalid Controller Index\n");
+	}
+#endif
+
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+#ifdef CONFIG_USB_DWC3
+	switch (index) {
+	case 0:
+	case 1:
+		if (init == USB_INIT_DEVICE) {
+			ti_usb_phy_uboot_exit(index);
+			dwc3_uboot_exit(index);
+			dwc3_omap_uboot_exit(index);
+		}
+		break;
+	default:
+		printf("Invalid Controller Index\n");
+	}
+#endif
+	disable_usb_clocks(index);
+
+	return 0;
+}
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
+#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
+int board_fit_config_name_match(const char *name)
+{
+	bool eeprom_read = board_ti_was_eeprom_read();
+
+	if (!strcmp(name, "am4372-generic") && !eeprom_read)
+		return 0;
+	else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
+		return 0;
+	else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
+		return 0;
+	else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
+		return 0;
+	else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
+		return 0;
+	else
+		return -1;
+}
+#endif
+
+#ifdef CONFIG_DTB_RESELECT
+int embedded_dtb_select(void)
+{
+	do_board_detect();
+	fdtdec_setup();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+	secure_boot_verify_image(p_image, p_size);
+}
+
+void board_tee_image_process(ulong tee_image, size_t tee_size)
+{
+	secure_tee_install((u32)tee_image);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
+#endif
diff --git a/roms/u-boot/board/ti/am43xx/board.h b/roms/u-boot/board/ti/am43xx/board.h
new file mode 100644
index 000000000..06b737445
--- /dev/null
+++ b/roms/u-boot/board/ti/am43xx/board.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * TI AM437x boards information header
+ * Derived from AM335x board.
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include <asm/arch/omap.h>
+
+#define DEV_ATTR_MAX_OFFSET    5
+#define DEV_ATTR_MIN_OFFSET    0
+
+static inline int board_is_eposevm(void)
+{
+	return board_ti_is("AM43EPOS");
+}
+
+static inline int board_is_gpevm(void)
+{
+	return board_ti_is("AM43__GP");
+}
+
+static inline int board_is_sk(void)
+{
+	return board_ti_is("AM43__SK");
+}
+
+static inline int board_is_idk(void)
+{
+	return board_ti_is("AM43_IDK");
+}
+
+static inline int board_is_hsevm(void)
+{
+	return board_ti_is("AM43XXHS");
+}
+
+static inline int board_is_evm(void)
+{
+	return board_is_gpevm() || board_is_hsevm();
+}
+
+static inline int board_is_evm_14_or_later(void)
+{
+	return board_is_evm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0;
+}
+
+static inline int board_is_evm_12_or_later(void)
+{
+	return board_is_evm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0;
+}
+
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+#endif
diff --git a/roms/u-boot/board/ti/am43xx/mux.c b/roms/u-boot/board/ti/am43xx/mux.c
new file mode 100644
index 000000000..f59e93a0e
--- /dev/null
+++ b/roms/u-boot/board/ti/am43xx/mux.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include "../common/board_detect.h"
+#include "board.h"
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RD0 */
+	{OFFSET(mii1_rxdv), MODE(1) | RXACTIVE},	/* RMII1_RXDV */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_refclk */
+	{-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)},  /* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux gpio5_7_pin_mux[] = {
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)},	/* GPIO5_7 */
+	{-1},
+};
+
+#ifdef CONFIG_MTD_RAW_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
+	{OFFSET(gpmc_ad1),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
+	{OFFSET(gpmc_ad2),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
+	{OFFSET(gpmc_ad3),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
+	{OFFSET(gpmc_ad4),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
+	{OFFSET(gpmc_ad5),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
+	{OFFSET(gpmc_ad6),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
+	{OFFSET(gpmc_ad7),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+	{OFFSET(gpmc_ad8),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8  */
+	{OFFSET(gpmc_ad9),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9  */
+	{OFFSET(gpmc_ad10),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
+	{OFFSET(gpmc_ad11),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
+	{OFFSET(gpmc_ad12),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
+	{OFFSET(gpmc_ad13),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
+	{OFFSET(gpmc_ad14),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
+	{OFFSET(gpmc_ad15),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
+#endif
+	{OFFSET(gpmc_wait0),	(MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */
+	{OFFSET(gpmc_wpn),	(MODE(7) | PULLUP_EN)},	/* Write Protect */
+	{OFFSET(gpmc_csn0),	(MODE(0) | PULLUP_EN)},	/* Chip-Select */
+	{OFFSET(gpmc_wen),	(MODE(0) | PULLDOWN_EN)}, /* Write Enable */
+	{OFFSET(gpmc_oen_ren),	(MODE(0) | PULLDOWN_EN)}, /* Read Enable */
+	{OFFSET(gpmc_advn_ale),	(MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/
+	{OFFSET(gpmc_be0n_cle),	(MODE(0) | PULLDOWN_EN)}, /* Byte Enable */
+	{-1},
+};
+#endif
+
+static __maybe_unused struct module_pin_mux qspi_pin_mux[] = {
+	{OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
+	{OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
+	{OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
+	{OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
+	{OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
+	{OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mdio_pin_mux);
+
+	if (board_is_evm()) {
+		configure_module_pin_mux(gpio5_7_pin_mux);
+		configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_MTD_RAW_NAND)
+		configure_module_pin_mux(nand_pin_mux);
+#endif
+	} else if (board_is_sk() || board_is_idk()) {
+		configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_MTD_RAW_NAND)
+		printf("Error: NAND flash not present on this board\n");
+#endif
+		configure_module_pin_mux(qspi_pin_mux);
+	} else if (board_is_eposevm()) {
+		configure_module_pin_mux(rmii1_pin_mux);
+#if defined(CONFIG_MTD_RAW_NAND)
+		configure_module_pin_mux(nand_pin_mux);
+#else
+		configure_module_pin_mux(qspi_pin_mux);
+#endif
+	}
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
diff --git a/roms/u-boot/board/ti/am57xx/Kconfig b/roms/u-boot/board/ti/am57xx/Kconfig
new file mode 100644
index 000000000..0c5668201
--- /dev/null
+++ b/roms/u-boot/board/ti/am57xx/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_AM57XX_EVM
+
+config SYS_BOARD
+	default "am57xx"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_CONFIG_NAME
+	default "am57xx_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/ti/am57xx/MAINTAINERS b/roms/u-boot/board/ti/am57xx/MAINTAINERS
new file mode 100644
index 000000000..47b694eb4
--- /dev/null
+++ b/roms/u-boot/board/ti/am57xx/MAINTAINERS
@@ -0,0 +1,7 @@
+AM57XX EVM
+M:	Lokesh Vutla <lokeshvutla@ti.com>
+S:	Maintained
+F:	board/ti/am57xx/
+F:	include/configs/am57xx_evm.h
+F:	configs/am57xx_evm_defconfig
+F:	configs/am57xx_hs_evm_defconfig
diff --git a/roms/u-boot/board/ti/am57xx/Makefile b/roms/u-boot/board/ti/am57xx/Makefile
new file mode 100644
index 000000000..2a6fb9e42
--- /dev/null
+++ b/roms/u-boot/board/ti/am57xx/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2014
+# Texas Instruments, <www.ti.com>
+
+obj-y	:= board.o
diff --git a/roms/u-boot/board/ti/am57xx/board.c b/roms/u-boot/board/ti/am57xx/board.c
new file mode 100644
index 000000000..05c26c74d
--- /dev/null
+++ b/roms/u-boot/board/ti/am57xx/board.c
@@ -0,0 +1,1213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * Based on board/ti/dra7xx/evm.c
+ */
+
+#include <common.h>
+#include <env.h>
+#include <fastboot.h>
+#include <fdt_support.h>
+#include <image.h>
+#include <init.h>
+#include <malloc.h>
+#include <net.h>
+#include <palmas.h>
+#include <sata.h>
+#include <serial.h>
+#include <usb.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dra7xx_iodelay.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sata.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/omap.h>
+#include <usb.h>
+#include <linux/usb/gadget.h>
+#include <dwc3-uboot.h>
+#include <dwc3-omap-uboot.h>
+#include <ti-usb-phy-uboot.h>
+#include <mmc.h>
+#include <dm/uclass.h>
+#include <hang.h>
+
+#include "../common/board_detect.h"
+#include "../common/cape_detect.h"
+#include "mux_data.h"
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+static int board_bootmode_has_emmc(void);
+#endif
+
+#define board_is_x15()		board_ti_is("BBRDX15_")
+#define board_is_x15_revb1()	(board_ti_is("BBRDX15_") && \
+				 !strncmp("B.10", board_ti_get_rev(), 3))
+#define board_is_x15_revc()	(board_ti_is("BBRDX15_") && \
+				 !strncmp("C.00", board_ti_get_rev(), 3))
+#define board_is_am572x_evm()	board_ti_is("AM572PM_")
+#define board_is_am572x_evm_reva3()	\
+				(board_ti_is("AM572PM_") && \
+				 !strncmp("A.30", board_ti_get_rev(), 3))
+#define board_is_am574x_idk()	board_ti_is("AM574IDK")
+#define board_is_am572x_idk()	board_ti_is("AM572IDK")
+#define board_is_am571x_idk()	board_ti_is("AM571IDK")
+#define board_is_bbai()		board_ti_is("BBONE-AI")
+
+#define board_is_ti_idk()	board_is_am574x_idk() || \
+				board_is_am572x_idk() || \
+				board_is_am571x_idk()
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+#include <cpsw.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_ETH_LCD		GPIO_TO_PIN(2, 22)
+#define GPIO_DDR_VTT_EN		GPIO_TO_PIN(7, 11)
+
+/* Touch screen controller to identify the LCD */
+#define OSD_TS_FT_BUS_ADDRESS	0
+#define OSD_TS_FT_CHIP_ADDRESS	0x38
+#define OSD_TS_FT_REG_ID	0xA3
+/*
+ * Touchscreen IDs for various OSD panels
+ * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
+ */
+/* Used on newer osd101t2587 Panels */
+#define OSD_TS_FT_ID_5x46	0x54
+/* Used on older osd101t2045 Panels */
+#define OSD_TS_FT_ID_5606	0x08
+
+#define SYSINFO_BOARD_NAME_MAX_LEN	45
+
+#define TPS65903X_PRIMARY_SECONDARY_PAD2	0xFB
+#define TPS65903X_PAD2_POWERHOLD_MASK		0x20
+
+const struct omap_sysinfo sysinfo = {
+	"Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
+};
+
+static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
+	.dmm_lisa_map_3 = 0x80740300,
+	.is_ma_present  = 0x1
+};
+
+static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
+	.dmm_lisa_map_3 = 0x80640100,
+	.is_ma_present  = 0x1
+};
+
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
+	.dmm_lisa_map_2 = 0xc0600200,
+	.dmm_lisa_map_3 = 0x80600100,
+	.is_ma_present  = 0x1
+};
+
+static const struct dmm_lisa_map_regs bbai_lisa_regs = {
+	.dmm_lisa_map_3 = 0x80640100,
+	.is_ma_present  = 0x1
+};
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+{
+	if (board_is_am571x_idk())
+		*dmm_lisa_regs = &am571x_idk_lisa_regs;
+	else if (board_is_am574x_idk())
+		*dmm_lisa_regs = &am574x_idk_lisa_regs;
+	else if (board_is_bbai())
+		*dmm_lisa_regs = &bbai_lisa_regs;
+	else
+		*dmm_lisa_regs = &beagle_x15_lisa_regs;
+}
+
+static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
+	.sdram_config_init		= 0x61851b32,
+	.sdram_config			= 0x61851b32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1			= 0xcccf36ab,
+	.sdram_tim2			= 0x308f7fda,
+	.sdram_tim3			= 0x409f88a8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init 	= 0x0024400b,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400b,
+	.emif_ddr_ext_phy_ctrl_1 	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2 	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3 	= 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4 	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5 	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305
+};
+
+/* Ext phy ctrl regs 1-35 */
+static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
+	0x10040100,
+	0x00910091,
+	0x00950095,
+	0x009B009B,
+	0x009E009E,
+	0x00980098,
+	0x00340034,
+	0x00350035,
+	0x00340034,
+	0x00310031,
+	0x00340034,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x00480048,
+	0x004A004A,
+	0x00520052,
+	0x00550055,
+	0x00500050,
+	0x00000000,
+	0x00600020,
+	0x40011080,
+	0x08102040,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0
+};
+
+static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
+	.sdram_config_init		= 0x61851b32,
+	.sdram_config			= 0x61851b32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1			= 0xcccf36b3,
+	.sdram_tim2			= 0x308f7fda,
+	.sdram_tim3			= 0x407f88a8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init 	= 0x0024400b,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400b,
+	.emif_ddr_ext_phy_ctrl_1 	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2 	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3 	= 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4 	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5 	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305
+};
+
+static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
+	0x10040100,
+	0x00910091,
+	0x00950095,
+	0x009B009B,
+	0x009E009E,
+	0x00980098,
+	0x00340034,
+	0x00350035,
+	0x00340034,
+	0x00310031,
+	0x00340034,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x00480048,
+	0x004A004A,
+	0x00520052,
+	0x00550055,
+	0x00500050,
+	0x00000000,
+	0x00600020,
+	0x40011080,
+	0x08102040,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0
+};
+
+static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
+	.sdram_config_init		= 0x61863332,
+	.sdram_config			= 0x61863332,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x0000514d,
+	.ref_ctrl_final			= 0x0000144a,
+	.sdram_tim1			= 0xd333887c,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init	= 0x0024400f,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400f,
+	.emif_ddr_ext_phy_ctrl_1	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305
+};
+
+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
+	.sdram_config_init		= 0x61863332,
+	.sdram_config			= 0x61863332,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x0000514d,
+	.ref_ctrl_final			= 0x0000144a,
+	.sdram_tim1			= 0xd333887c,
+	.sdram_tim2			= 0x30b37fe3,
+	.sdram_tim3			= 0x409f8ad8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init	= 0x0024400f,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400f,
+	.emif_ddr_ext_phy_ctrl_1	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305,
+	.emif_ecc_ctrl_reg		= 0xD0000001,
+	.emif_ecc_address_range_1	= 0x3FFF0000,
+	.emif_ecc_address_range_2	= 0x00000000
+};
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+	switch (emif_nr) {
+	case 1:
+		if (board_is_am571x_idk())
+			*regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+		else if (board_is_am574x_idk())
+			*regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
+		else
+			*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
+		break;
+	case 2:
+		if (board_is_am574x_idk())
+			*regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+		else
+			*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
+		break;
+	}
+}
+
+void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
+{
+	switch (emif_nr) {
+	case 1:
+		*regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
+		*size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
+		break;
+	case 2:
+		*regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
+		*size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
+		break;
+	}
+}
+
+struct vcores_data beagle_x15_volts = {
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
+	.mpu.pmic		= &tps659038,
+	.mpu.abb_tx_done_mask	= OMAP_ABB_MPU_TXDONE_MASK,
+
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
+	.eve.pmic		= &tps659038,
+	.eve.abb_tx_done_mask	= OMAP_ABB_EVE_TXDONE_MASK,
+
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr		= TPS659038_REG_ADDR_SMPS45,
+	.gpu.pmic		= &tps659038,
+	.gpu.abb_tx_done_mask	= OMAP_ABB_GPU_TXDONE_MASK,
+
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.core.addr		= TPS659038_REG_ADDR_SMPS6,
+	.core.pmic		= &tps659038,
+
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr		= TPS659038_REG_ADDR_SMPS45,
+	.iva.pmic		= &tps659038,
+	.iva.abb_tx_done_mask	= OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+struct vcores_data am572x_idk_volts = {
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
+	.mpu.pmic		= &tps659038,
+	.mpu.abb_tx_done_mask	= OMAP_ABB_MPU_TXDONE_MASK,
+
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
+	.eve.pmic		= &tps659038,
+	.eve.abb_tx_done_mask	= OMAP_ABB_EVE_TXDONE_MASK,
+
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr		= TPS659038_REG_ADDR_SMPS6,
+	.gpu.pmic		= &tps659038,
+	.gpu.abb_tx_done_mask	= OMAP_ABB_GPU_TXDONE_MASK,
+
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.core.addr		= TPS659038_REG_ADDR_SMPS7,
+	.core.pmic		= &tps659038,
+
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr		= TPS659038_REG_ADDR_SMPS8,
+	.iva.pmic		= &tps659038,
+	.iva.abb_tx_done_mask	= OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+struct vcores_data am571x_idk_volts = {
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
+	.mpu.pmic		= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
+	.eve.pmic		= &tps659038,
+	.eve.abb_tx_done_mask	= OMAP_ABB_EVE_TXDONE_MASK,
+
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr		= TPS659038_REG_ADDR_SMPS6,
+	.gpu.pmic		= &tps659038,
+	.gpu.abb_tx_done_mask	= OMAP_ABB_GPU_TXDONE_MASK,
+
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.core.addr		= TPS659038_REG_ADDR_SMPS7,
+	.core.pmic		= &tps659038,
+
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr		= TPS659038_REG_ADDR_SMPS45,
+	.iva.pmic		= &tps659038,
+	.iva.abb_tx_done_mask	= OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+int get_voltrail_opp(int rail_offset)
+{
+	int opp;
+
+	switch (rail_offset) {
+	case VOLT_MPU:
+		opp = DRA7_MPU_OPP;
+		break;
+	case VOLT_CORE:
+		opp = DRA7_CORE_OPP;
+		break;
+	case VOLT_GPU:
+		opp = DRA7_GPU_OPP;
+		break;
+	case VOLT_EVE:
+		opp = DRA7_DSPEVE_OPP;
+		break;
+	case VOLT_IVA:
+		opp = DRA7_IVA_OPP;
+		break;
+	default:
+		opp = OPP_NOM;
+	}
+
+	return opp;
+}
+
+
+#ifdef CONFIG_SPL_BUILD
+/* No env to setup for SPL */
+static inline void setup_board_eeprom_env(void) { }
+
+/* Override function to read eeprom information */
+void do_board_detect(void)
+{
+	int rc;
+
+	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+				  CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+	rc = board_bootmode_has_emmc();
+	if (!rc)
+		rc = ti_emmc_boardid_get();
+	if (rc)
+		printf("ti_emmc_boardid_get failed %d\n", rc);
+#endif
+}
+
+#else	/* CONFIG_SPL_BUILD */
+
+/* Override function to read eeprom information: actual i2c read done by SPL*/
+void do_board_detect(void)
+{
+	char *bname = NULL;
+	int rc;
+
+	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+				  CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+	rc = board_bootmode_has_emmc();
+	if (!rc)
+		rc = ti_emmc_boardid_get();
+	if (rc)
+		printf("ti_emmc_boardid_get failed %d\n", rc);
+#endif
+
+	if (board_is_x15())
+		bname = "BeagleBoard X15";
+	else if (board_is_am572x_evm())
+		bname = "AM572x EVM";
+	else if (board_is_am574x_idk())
+		bname = "AM574x IDK";
+	else if (board_is_am572x_idk())
+		bname = "AM572x IDK";
+	else if (board_is_am571x_idk())
+		bname = "AM571x IDK";
+	else if (board_is_bbai())
+		bname = "BeagleBone AI";
+
+	if (bname)
+		snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
+			 "Board: %s REV %s\n", bname, board_ti_get_rev());
+}
+
+static void setup_board_eeprom_env(void)
+{
+	char *name = "beagle_x15";
+	int rc;
+
+	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+				  CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		goto invalid_eeprom;
+
+	if (board_is_x15()) {
+		if (board_is_x15_revb1())
+			name = "beagle_x15_revb1";
+		else if (board_is_x15_revc())
+			name = "beagle_x15_revc";
+		else
+			name = "beagle_x15";
+	} else if (board_is_am572x_evm()) {
+		if (board_is_am572x_evm_reva3())
+			name = "am57xx_evm_reva3";
+		else
+			name = "am57xx_evm";
+	} else if (board_is_am574x_idk()) {
+		name = "am574x_idk";
+	} else if (board_is_am572x_idk()) {
+		name = "am572x_idk";
+	} else if (board_is_am571x_idk()) {
+		name = "am571x_idk";
+	} else if (board_is_bbai()) {
+		name = "am5729_beagleboneai";
+	} else {
+		printf("Unidentified board claims %s in eeprom header\n",
+		       board_ti_get_name());
+	}
+
+invalid_eeprom:
+	set_board_info_env(name);
+}
+
+#endif	/* CONFIG_SPL_BUILD */
+
+void vcores_init(void)
+{
+	if (board_is_am572x_idk() || board_is_am574x_idk())
+		*omap_vcores = &am572x_idk_volts;
+	else if (board_is_am571x_idk())
+		*omap_vcores = &am571x_idk_volts;
+	else
+		*omap_vcores = &beagle_x15_volts;
+}
+
+void hw_data_init(void)
+{
+	*prcm = &dra7xx_prcm;
+	if (is_dra72x())
+		*dplls_data = &dra72x_dplls;
+	else if (is_dra76x())
+		*dplls_data = &dra76x_dplls;
+	else
+		*dplls_data = &dra7xx_dplls;
+	*ctrl = &dra7xx_ctrl;
+}
+
+bool am571x_idk_needs_lcd(void)
+{
+	bool needs_lcd;
+
+	gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
+	if (gpio_get_value(GPIO_ETH_LCD))
+		needs_lcd = false;
+	else
+		needs_lcd = true;
+
+	gpio_free(GPIO_ETH_LCD);
+
+	return needs_lcd;
+}
+
+int board_init(void)
+{
+	gpmc_init();
+	gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+	return 0;
+}
+
+void am57x_idk_lcd_detect(void)
+{
+	int r = -ENODEV;
+	char *idk_lcd = "no";
+	struct udevice *dev;
+
+	/* Only valid for IDKs */
+	if (!board_is_ti_idk())
+		return;
+
+	/* Only AM571x IDK has gpio control detect.. so check that */
+	if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
+		goto out;
+
+	r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
+				    OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
+	if (r) {
+		printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
+		       __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
+		       r);
+		/* AM572x IDK has no explicit settings for optional LCD kit */
+		if (board_is_am571x_idk())
+			printf("%s: Touch screen detect failed: %d!\n",
+			       __func__, r);
+		goto out;
+	}
+
+	/* Read FT ID */
+	r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
+	if (r < 0) {
+		printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
+		       __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
+		       OSD_TS_FT_REG_ID, r);
+		goto out;
+	}
+
+	switch (r) {
+	case OSD_TS_FT_ID_5606:
+		idk_lcd = "osd101t2045";
+		break;
+	case OSD_TS_FT_ID_5x46:
+		idk_lcd = "osd101t2587";
+		break;
+	default:
+		printf("%s: Unidentifed Touch screen ID 0x%02x\n",
+		       __func__, r);
+		/* we will let default be "no lcd" */
+	}
+out:
+	env_set("idk_lcd", idk_lcd);
+
+	/*
+	 * On AM571x_IDK, no Display with J51 set to LCD is considered as an
+	 * invalid configuration and we prevent boot to get user attention.
+	 */
+	if (board_is_am571x_idk() && am571x_idk_needs_lcd() &&
+	    !strncmp(idk_lcd, "no", 2)) {
+		printf("%s: Invalid HW configuration: display not detected/supported but J51 is set. Remove J51 to boot without display.\n",
+		       __func__);
+		hang();
+	}
+
+	return;
+}
+
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+static int device_okay(const char *path)
+{
+	int node;
+
+	node = fdt_path_offset(gd->fdt_blob, path);
+	if (node < 0)
+		return 0;
+
+	return fdtdec_get_is_enabled(gd->fdt_blob, node);
+}
+#endif
+
+int board_late_init(void)
+{
+	setup_board_eeprom_env();
+	u8 val;
+	struct udevice *dev;
+
+	/*
+	 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
+	 * This is the POWERHOLD-in-Low behavior.
+	 */
+	palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
+
+	/*
+	 * Default FIT boot on HS devices. Non FIT images are not allowed
+	 * on HS devices.
+	 */
+	if (get_device_type() == HS_DEVICE)
+		env_set("boot_fit", "1");
+
+	/*
+	 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
+	 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
+	 * PMIC Power off. So to be on the safer side set it back
+	 * to POWERHOLD mode irrespective of the current state.
+	 */
+	palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
+			   &val);
+	val = val | TPS65903X_PAD2_POWERHOLD_MASK;
+	palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
+			    val);
+
+	omap_die_id_serial();
+	omap_set_fastboot_vars();
+
+	am57x_idk_lcd_detect();
+
+	/* Just probe the potentially supported cdce913 device */
+	uclass_get_device(UCLASS_CLK, 0, &dev);
+
+	if (board_is_bbai())
+		env_set("console", "ttyS0,115200n8");
+
+#if !defined(CONFIG_SPL_BUILD)
+	board_ti_set_ethaddr(2);
+#endif
+
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+	if (device_okay("/ocp/omap_dwc3_1@48880000"))
+		enable_usb_clocks(0);
+	if (device_okay("/ocp/omap_dwc3_2@488c0000"))
+		enable_usb_clocks(1);
+#endif
+	return 0;
+}
+
+void set_muxconf_regs(void)
+{
+	do_set_mux32((*ctrl)->control_padconf_core_base,
+		     early_padconf, ARRAY_SIZE(early_padconf));
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+	do_set_mux32((*ctrl)->control_padconf_core_base,
+		     emmc_padconf, ARRAY_SIZE(emmc_padconf));
+#endif
+}
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void recalibrate_iodelay(void)
+{
+	const struct pad_conf_entry *pconf;
+	const struct iodelay_cfg_entry *iod, *delta_iod;
+	int pconf_sz, iod_sz, delta_iod_sz = 0;
+	int ret;
+
+	if (board_is_am572x_idk()) {
+		pconf = core_padconf_array_essential_am572x_idk;
+		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
+		iod = iodelay_cfg_array_am572x_idk;
+		iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
+	} else if (board_is_am574x_idk()) {
+		pconf = core_padconf_array_essential_am574x_idk;
+		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
+		iod = iodelay_cfg_array_am574x_idk;
+		iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
+	} else if (board_is_am571x_idk()) {
+		pconf = core_padconf_array_essential_am571x_idk;
+		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
+		iod = iodelay_cfg_array_am571x_idk;
+		iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
+	} else if (board_is_bbai()) {
+		pconf = core_padconf_array_essential_bbai;
+		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_bbai);
+		iod = iodelay_cfg_array_bbai;
+		iod_sz = ARRAY_SIZE(iodelay_cfg_array_bbai);
+	} else {
+		/* Common for X15/GPEVM */
+		pconf = core_padconf_array_essential_x15;
+		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
+		/* There never was an SR1.0 X15.. So.. */
+		if (omap_revision() == DRA752_ES1_1) {
+			iod = iodelay_cfg_array_x15_sr1_1;
+			iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
+		} else {
+			/* Since full production should switch to SR2.0  */
+			iod = iodelay_cfg_array_x15_sr2_0;
+			iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
+		}
+	}
+
+	/* Setup I/O isolation */
+	ret = __recalibrate_iodelay_start();
+	if (ret)
+		goto err;
+
+	/* Do the muxing here */
+	do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
+
+	/* Now do the weird minor deltas that should be safe */
+	if (board_is_x15() || board_is_am572x_evm()) {
+		if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
+		    board_is_x15_revc()) {
+			pconf = core_padconf_array_delta_x15_sr2_0;
+			pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
+		} else {
+			pconf = core_padconf_array_delta_x15_sr1_1;
+			pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
+		}
+		do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
+	}
+
+	if (board_is_am571x_idk()) {
+		if (am571x_idk_needs_lcd()) {
+			pconf = core_padconf_array_vout_am571x_idk;
+			pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
+			delta_iod = iodelay_cfg_array_am571x_idk_4port;
+			delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
+
+		} else {
+			pconf = core_padconf_array_icss1eth_am571x_idk;
+			pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
+		}
+		do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
+	}
+
+	/* Setup IOdelay configuration */
+	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
+	if (delta_iod_sz)
+		ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
+				     delta_iod_sz);
+
+err:
+	/* Closeup.. remove isolation */
+	__recalibrate_iodelay_end(ret);
+}
+#endif
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(struct bd_info *bis)
+{
+	omap_mmc_init(0, 0, 0, -1, -1);
+	omap_mmc_init(1, 0, 0, -1, -1);
+	return 0;
+}
+
+static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
+	.hw_rev = "rev11",
+	.unsupported_caps = MMC_CAP(MMC_HS_200) |
+			    MMC_CAP(UHS_SDR104),
+	.max_freq = 96000000,
+};
+
+static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
+	.hw_rev = "rev11",
+	.unsupported_caps = MMC_CAP(MMC_HS_200) |
+			    MMC_CAP(UHS_SDR104) |
+			    MMC_CAP(UHS_SDR50),
+	.max_freq = 48000000,
+};
+
+const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
+{
+	switch (omap_revision()) {
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+		if (addr == OMAP_HSMMC1_BASE)
+			return &am57x_es1_1_mmc1_fixups;
+		else
+			return &am57x_es1_1_mmc23_fixups;
+	default:
+		return NULL;
+	}
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	env_init();
+	env_load();
+	if (env_get_yesno("boot_os") != 1)
+		return 1;
+#endif
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+/* Delay value to add to calibrated value */
+#define RGMII0_TXCTL_DLY_VAL		((0x3 << 5) + 0x8)
+#define RGMII0_TXD0_DLY_VAL		((0x3 << 5) + 0x8)
+#define RGMII0_TXD1_DLY_VAL		((0x3 << 5) + 0x2)
+#define RGMII0_TXD2_DLY_VAL		((0x4 << 5) + 0x0)
+#define RGMII0_TXD3_DLY_VAL		((0x4 << 5) + 0x0)
+#define VIN2A_D13_DLY_VAL		((0x3 << 5) + 0x8)
+#define VIN2A_D17_DLY_VAL		((0x3 << 5) + 0x8)
+#define VIN2A_D16_DLY_VAL		((0x3 << 5) + 0x2)
+#define VIN2A_D15_DLY_VAL		((0x4 << 5) + 0x0)
+#define VIN2A_D14_DLY_VAL		((0x4 << 5) + 0x0)
+
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 1,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 2,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+static u64 mac_to_u64(u8 mac[6])
+{
+	int i;
+	u64 addr = 0;
+
+	for (i = 0; i < 6; i++) {
+		addr <<= 8;
+		addr |= mac[i];
+	}
+
+	return addr;
+}
+
+static void u64_to_mac(u64 addr, u8 mac[6])
+{
+	mac[5] = addr;
+	mac[4] = addr >> 8;
+	mac[3] = addr >> 16;
+	mac[2] = addr >> 24;
+	mac[1] = addr >> 32;
+	mac[0] = addr >> 40;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int ret;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+	uint32_t ctrl_val;
+	int i;
+	u64 mac1, mac2;
+	u8 mac_addr1[6], mac_addr2[6];
+	int num_macs;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
+	mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
+	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = mac_hi & 0xFF;
+	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+	mac_addr[5] = mac_lo & 0xFF;
+
+	if (!env_get("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+	}
+
+	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = mac_hi & 0xFF;
+	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+	mac_addr[5] = mac_lo & 0xFF;
+
+	if (!env_get("eth1addr")) {
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("eth1addr", mac_addr);
+	}
+
+	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
+	ctrl_val |= 0x22;
+	writel(ctrl_val, (*ctrl)->control_core_control_io1);
+
+	/* The phy address for the AM57xx IDK are different than x15 */
+	if (board_is_am572x_idk() || board_is_am571x_idk() ||
+	    board_is_am574x_idk()) {
+		cpsw_data.slave_data[0].phy_addr = 0;
+		cpsw_data.slave_data[1].phy_addr = 1;
+	}
+
+	ret = cpsw_register(&cpsw_data);
+	if (ret < 0)
+		printf("Error %d registering CPSW switch\n", ret);
+
+	/*
+	 * Export any Ethernet MAC addresses from EEPROM.
+	 * On AM57xx the 2 MAC addresses define the address range
+	 */
+	board_ti_get_eth_mac_addr(0, mac_addr1);
+	board_ti_get_eth_mac_addr(1, mac_addr2);
+
+	if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
+		mac1 = mac_to_u64(mac_addr1);
+		mac2 = mac_to_u64(mac_addr2);
+
+		/* must contain an address range */
+		num_macs = mac2 - mac1 + 1;
+		/* <= 50 to protect against user programming error */
+		if (num_macs > 0 && num_macs <= 50) {
+			for (i = 0; i < num_macs; i++) {
+				u64_to_mac(mac1 + i, mac_addr);
+				if (is_valid_ethaddr(mac_addr)) {
+					eth_env_set_enetaddr_by_index("eth",
+								      i + 2,
+								      mac_addr);
+				}
+			}
+		}
+	}
+
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+/* VTT regulator enable */
+static inline void vtt_regulator_enable(void)
+{
+	if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+		return;
+
+	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+}
+
+int board_early_init_f(void)
+{
+	vtt_regulator_enable();
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (board_is_x15()) {
+		if (board_is_x15_revb1()) {
+			if (!strcmp(name, "am57xx-beagle-x15-revb1"))
+				return 0;
+		} else if (board_is_x15_revc()) {
+			if (!strcmp(name, "am57xx-beagle-x15-revc"))
+				return 0;
+		} else if (!strcmp(name, "am57xx-beagle-x15")) {
+			return 0;
+		}
+	} else if (board_is_am572x_evm() &&
+		   !strcmp(name, "am57xx-beagle-x15")) {
+		return 0;
+	} else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
+		return 0;
+	} else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
+		return 0;
+	} else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
+		return 0;
+	} else if (board_is_bbai() && !strcmp(name, "am5729-beagleboneai")) {
+		return 0;
+	}
+
+	return -1;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
+int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
+{
+	if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
+		return -ENOTSUPP;
+
+	printf("Setting reboot to fastboot flag ...\n");
+	env_set("dofastboot", "1");
+	env_save();
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+static int board_bootmode_has_emmc(void)
+{
+	/* Check that boot mode is same as BBAI */
+	if (gd->arch.omap_boot_mode != 2)
+		return -EIO;
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+	secure_boot_verify_image(p_image, p_size);
+}
+
+void board_tee_image_process(ulong tee_image, size_t tee_size)
+{
+	secure_tee_install((u32)tee_image);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
+#endif
diff --git a/roms/u-boot/board/ti/am57xx/mux_data.h b/roms/u-boot/board/ti/am57xx/mux_data.h
new file mode 100644
index 000000000..212799c93
--- /dev/null
+++ b/roms/u-boot/board/ti/am57xx/mux_data.h
@@ -0,0 +1,1694 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * Based on board/ti/dra7xx/evm.c
+ */
+#ifndef _MUX_DATA_BEAGLE_X15_H_
+#define _MUX_DATA_BEAGLE_X15_H_
+
+#include <asm/arch/mux_dra7xx.h>
+
+const struct pad_conf_entry core_padconf_array_essential_x15[] = {
+	{GPMC_AD0, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad0.vin3a_d0 */
+	{GPMC_AD1, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad1.vin3a_d1 */
+	{GPMC_AD2, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad2.vin3a_d2 */
+	{GPMC_AD3, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad3.vin3a_d3 */
+	{GPMC_AD4, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad4.vin3a_d4 */
+	{GPMC_AD5, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad5.vin3a_d5 */
+	{GPMC_AD6, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad6.vin3a_d6 */
+	{GPMC_AD7, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad7.vin3a_d7 */
+	{GPMC_AD8, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad8.vin3a_d8 */
+	{GPMC_AD9, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad9.vin3a_d9 */
+	{GPMC_AD10, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad10.vin3a_d10 */
+	{GPMC_AD11, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad11.vin3a_d11 */
+	{GPMC_AD12, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad12.vin3a_d12 */
+	{GPMC_AD13, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad13.vin3a_d13 */
+	{GPMC_AD14, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad14.vin3a_d14 */
+	{GPMC_AD15, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad15.vin3a_d15 */
+	{GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a0.vin3a_d16 */
+	{GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a1.vin3a_d17 */
+	{GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a2.vin3a_d18 */
+	{GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a3.vin3a_d19 */
+	{GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a4.vin3a_d20 */
+	{GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a5.vin3a_d21 */
+	{GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a6.vin3a_d22 */
+	{GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a7.vin3a_d23 */
+	{GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a8.vin3a_hsync0 */
+	{GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a9.vin3a_vsync0 */
+	{GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a10.vin3a_de0 */
+	{GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a11.vin3a_fld0 */
+	{GPMC_A12, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a12.gpio2_2 */
+	{GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a13.gpio2_3 */
+	{GPMC_A14, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a14.gpio2_4 */
+	{GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a15.gpio2_5 */
+	{GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a16.gpio2_6 */
+	{GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a17.gpio2_7 */
+	{GPMC_A18, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a18.gpio2_8 */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_cs0.gpio2_19 */
+	{GPMC_CS2, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_cs2.gpio2_20 */
+	{GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_cs3.vin3a_clk0 */
+	{GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)},	/* gpmc_clk.dma_evt1 */
+	{GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_advn_ale.gpio2_23 */
+	{GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_oen_ren.gpio2_24 */
+	{GPMC_WEN, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_wen.gpio2_25 */
+	{GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)},	/* gpmc_ben0.dma_evt3 */
+	{GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)},	/* gpmc_ben1.dma_evt4 */
+	{GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* gpmc_wait0.gpio2_28 */
+	{VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)},	/* vin1b_clk1.gpio2_31 */
+	{VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d2.gpio3_6 */
+	{VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d3.gpio3_7 */
+	{VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d4.gpio3_8 */
+	{VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d5.gpio3_9 */
+	{VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d6.gpio3_10 */
+	{VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d7.gpio3_11 */
+	{VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d8.gpio3_12 */
+	{VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d10.gpio3_14 */
+	{VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d11.gpio3_15 */
+	{VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d12.gpio3_16 */
+	{VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d14.gpio3_18 */
+	{VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d16.gpio3_20 */
+	{VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d19.gpio3_23 */
+	{VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d20.gpio3_24 */
+	{VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d22.gpio3_26 */
+	{VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_clk0.gpio3_28 */
+	{VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_de0.gpio3_29 */
+	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_fld0.gpio3_30 */
+	{VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLUP)},	/* vin2a_hsync0.pr1_uart0_cts_n */
+	{VIN2A_VSYNC0, (M11 | PIN_OUTPUT_PULLUP)},	/* vin2a_vsync0.pr1_uart0_rts_n */
+	{VIN2A_D0, (M11 | PIN_INPUT_PULLUP)},	/* vin2a_d0.pr1_uart0_rxd */
+	{VIN2A_D1, (M11 | PIN_OUTPUT)},	/* vin2a_d1.pr1_uart0_txd */
+	{VIN2A_D2, (M8 | PIN_INPUT_PULLUP)},	/* vin2a_d2.uart10_rxd */
+	{VIN2A_D3, (M8 | PIN_OUTPUT)},	/* vin2a_d3.uart10_txd */
+	{VIN2A_D4, (M8 | PIN_INPUT_PULLUP)},	/* vin2a_d4.uart10_ctsn */
+	{VIN2A_D5, (M8 | PIN_OUTPUT_PULLUP)},	/* vin2a_d5.uart10_rtsn */
+	{VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d6.gpio4_7 */
+	{VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d7.gpio4_8 */
+	{VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d8.gpio4_9 */
+	{VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d9.gpio4_10 */
+	{VIN2A_D10, (M10 | PIN_OUTPUT_PULLDOWN)},	/* vin2a_d10.ehrpwm2B */
+	{VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)},	/* vin2a_d11.ehrpwm2_tripzone_input */
+	{VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_FLD, (M14 | PIN_INPUT)},	/* vout1_fld.gpio4_21 */
+	{MDIO_MCLK, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)},	/* RMII_MHZ_50_CLK.gpio5_17 */
+	{UART3_RXD, (M14 | PIN_INPUT_SLEW)},	/* uart3_rxd.gpio5_18 */
+	{UART3_TXD, (M14 | PIN_INPUT_SLEW)},	/* uart3_txd.gpio5_19 */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M10 | PIN_INPUT_PULLUP)},	/* gpio6_14.timer1 */
+	{GPIO6_15, (M10 | PIN_INPUT_PULLUP)},	/* gpio6_15.timer2 */
+	{GPIO6_16, (M10 | PIN_INPUT_PULLUP)},	/* gpio6_16.timer3 */
+	{XREF_CLK0, (M9 | PIN_OUTPUT_PULLDOWN)},	/* xref_clk0.clkout2 */
+	{XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.gpio6_18 */
+	{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.gpio6_19 */
+	{XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)},	/* xref_clk3.clkout3 */
+	{MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkx.i2c3_sda */
+	{MCASP1_FSX, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_fsx.i2c3_scl */
+	{MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkr.i2c4_sda */
+	{MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_fsr.i2c4_scl */
+	{MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.i2c5_sda */
+	{MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr1.i2c5_scl */
+	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR8, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_axr8.gpio5_10 */
+	{MCASP1_AXR9, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_axr9.gpio5_11 */
+	{MCASP1_AXR10, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_axr10.gpio5_12 */
+	{MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr11.gpio4_17 */
+	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr12.mcasp7_axr0 */
+	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr13.mcasp7_axr1 */
+	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr14.mcasp7_aclkx */
+	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr15.mcasp7_fsx */
+	{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.mcasp3_aclkx */
+	{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.mcasp3_fsx */
+	{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_axr0.mcasp3_axr0 */
+	{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_axr1.mcasp3_axr1 */
+	{MCASP4_ACLKX, (M3 | PIN_INPUT_PULLUP)},	/* mcasp4_aclkx.uart8_rxd */
+	{MCASP4_FSX, (M3 | PIN_OUTPUT)},	/* mcasp4_fsx.uart8_txd */
+	{MCASP4_AXR0, (M3 | PIN_INPUT_PULLUP)},	/* mcasp4_axr0.uart8_ctsn */
+	{MCASP4_AXR1, (M3 | PIN_OUTPUT_PULLUP)},	/* mcasp4_axr1.uart8_rtsn */
+	{MCASP5_ACLKX, (M3 | PIN_INPUT_PULLUP)},	/* mcasp5_aclkx.uart9_rxd */
+	{MCASP5_FSX, (M3 | PIN_OUTPUT)},	/* mcasp5_fsx.uart9_txd */
+	{MCASP5_AXR0, (M3 | PIN_INPUT_PULLUP)},	/* mcasp5_axr0.uart9_ctsn */
+	{MCASP5_AXR1, (M3 | PIN_OUTPUT_PULLUP)},	/* mcasp5_axr1.uart9_rtsn */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mmc1_sdcd.gpio6_27 */
+	{GPIO6_10, (M10 | PIN_OUTPUT_PULLDOWN)},	/* gpio6_10.ehrpwm2A */
+	{GPIO6_11, (M0 | PIN_INPUT_PULLUP)},	/* gpio6_11.gpio6_11 */
+	{MMC3_CLK, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_clk.mmc3_clk */
+	{MMC3_CMD, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_cmd.mmc3_cmd */
+	{MMC3_DAT0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat0.mmc3_dat0 */
+	{MMC3_DAT1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat1.mmc3_dat1 */
+	{MMC3_DAT2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat2.mmc3_dat2 */
+	{MMC3_DAT3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat3.mmc3_dat3 */
+	{MMC3_DAT4, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat4.mmc3_dat4 */
+	{MMC3_DAT5, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat5.mmc3_dat5 */
+	{MMC3_DAT6, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat6.mmc3_dat6 */
+	{MMC3_DAT7, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat7.mmc3_dat7 */
+	{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.gpio7_7 */
+	{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.gpio7_8 */
+	{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.gpio7_9 */
+	{SPI1_CS0, (M14 | PIN_INPUT)},	/* spi1_cs0.gpio7_10 */
+	{SPI1_CS1, (M14 | PIN_INPUT)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_SLEW)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)},	/* spi2_sclk.gpio7_14 */
+	{SPI2_D1, (M14 | PIN_INPUT_SLEW)},	/* spi2_d1.gpio7_15 */
+	{SPI2_D0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_d0.gpio7_16 */
+	{SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.gpio7_17 */
+	{DCAN1_TX, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* dcan1_tx.dcan1_tx */
+	{DCAN1_RX, (M0 | PIN_INPUT | SLEWCONTROL)},	/* dcan1_rx.dcan1_rx */
+	{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* uart1_txd.uart1_txd */
+	{UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)},	/* uart1_ctsn.gpio7_24 */
+	{UART1_RTSN, (M14 | PIN_INPUT)},	/* uart1_rtsn.gpio7_25 */
+	{UART2_RXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart2_rxd.gpio7_26 */
+	{UART2_TXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart2_txd.gpio7_27 */
+	{UART2_CTSN, (M2 | PIN_INPUT_PULLUP)},	/* uart2_ctsn.uart3_rxd */
+	{UART2_RTSN, (M1 | PIN_OUTPUT)},	/* uart2_rtsn.uart3_txd */
+	{I2C1_SDA, (M0 | PIN_INPUT_PULLUP)},	/* i2c1_sda.i2c1_sda */
+	{I2C1_SCL, (M0 | PIN_INPUT_PULLUP)},	/* i2c1_scl.i2c1_scl */
+	{I2C2_SDA, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M0 | PIN_INPUT)},	/* Wakeup0.Wakeup0 */
+	{WAKEUP1, (M0 | PIN_INPUT)},	/* Wakeup1.Wakeup1 */
+	{WAKEUP2, (M0 | PIN_INPUT)},	/* Wakeup2.Wakeup2 */
+	{WAKEUP3, (M0 | PIN_INPUT)},	/* Wakeup3.Wakeup3 */
+	{ON_OFF, (M0 | PIN_OUTPUT)},	/* on_off.on_off */
+	{RTC_PORZ, (M0 | PIN_INPUT)},	/* rtc_porz.rtc_porz */
+	{TMS, (M0 | PIN_INPUT_PULLUP)},	/* tms.tms */
+	{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* tdi.tdi */
+	{TDO, (M0 | PIN_OUTPUT)},	/* tdo.tdo */
+	{TCLK, (M0 | PIN_INPUT_PULLDOWN)},	/* tclk.tclk */
+	{TRSTN, (M0 | PIN_INPUT)},	/* trstn.trstn */
+	{RTCK, (M0 | PIN_OUTPUT)},	/* rtck.rtck */
+	{EMU0, (M0 | PIN_INPUT)},	/* emu0.emu0 */
+	{EMU1, (M0 | PIN_INPUT)},	/* emu1.emu1 */
+	{NMIN_DSP, (M0 | PIN_INPUT)},	/* nmin_dsp.nmin_dsp */
+	{RSTOUTN, (M0 | PIN_OUTPUT)},	/* rstoutn.rstoutn */
+};
+
+const struct pad_conf_entry core_padconf_array_essential_bbai[] = {
+	/* Cape Bus i2c */
+	/* NOTE: For the i2cj_scl and i2ci_scl signals to work properly, the INPUTENABLE bit of the
+	 * appropriate CTRL_CORE_PAD_x registers should be set to 0x1 because of retiming
+	 * purposes.
+	 */
+	{GPMC_A0, (M7 | PIN_INPUT_PULLUP)},		     /* P9_19A: R6_GPIO7_3: gpmc_a0.i2c4_scl (Shared with F4_UART10_RTSN) */
+	{GPMC_A1, (M7 | PIN_INPUT_PULLUP)},		     /* P9_20A: T9_GPIO7_4: gpmc_a1.i2c4_sda (Shared with D2_UART10_CTSN) */
+
+	/* Bluetooth UART */
+	{GPMC_A4, (M8 | PIN_INPUT)},			    /* P6 UART6_RXD: gpmc_a4.uart6_rxd */
+	{GPMC_A5, (M8 | PIN_OUTPUT)},			   /* R9 UART6_TXD: gpmc_a5.uart6_txd */
+	{GPMC_A6, (M8 | PIN_INPUT)},			    /* R5 UART6_CTSN: gpmc_a6.uart6_ctsn */
+	{GPMC_A7, (M8 | PIN_OUTPUT)},			   /* P5 UART6_RTSN: gpmc_a7.uart6_rtsn */
+
+	/* eMMC */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},      /*  K7: gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},      /*  M7: gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},      /*  J5: gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},      /*  K6: gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},      /*  J7: gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},      /*  J4: gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},      /*  J6: gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},      /*  H4: gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},      /*  H5: gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},      /*  H6: gpmc_cs1.mmc2_cmd */
+
+	{GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)},	      /* N1 RGMII_RST: gpmc_advn_ale.gpio2_23 */
+
+	{VIN1A_CLK0, (M14 | PIN_INPUT_PULLUP)},		 /* AG8 INT_ADC: vin1a_clk0.gpio2_30 */
+	{VIN1A_DE0, (M10 | PIN_INPUT_PULLDOWN)},		/* P8_35B: AD9_EQEP1A_IN: vin1a_de0.eQEP1A_in */
+	{VIN1A_FLD0, (M10 | PIN_INPUT_PULLDOWN)},	       /* P8_33B: AF9_EQEP1B_IN: vin1a_fld0.eQEP1B_in */
+	{VIN1A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)},	     /* P9_21A: AF8_TIMER13: vin1a_vsync0.gpio3_3 */
+
+	{VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)},		 /* AH6 USR4: vin1a_d3.gpio3_7 */
+
+	{VIN1A_D6, (M10 | PIN_INPUT_PULLDOWN)},		 /* P8_12: AG6: vin1a_d6.eQEP2A_in */
+	{VIN1A_D7, (M10 | PIN_INPUT_PULLDOWN)},		 /* P8_11: AH4: vin1a_d7.eQEP2B_in */
+	{VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)},		 /* P9_15: AG4: vin1a_d8.gpio3_12 */
+	{VIN1A_D9, (M14 | PIN_INPUT)},			  /* AG2 USB ID: vin1a_d9.gpio3_13 */
+	{VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)},		/* AG3 USR3: vin1a_d10.gpio3_14 */
+	{VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)},		/* AG5 USR2: vin1a_d11.gpio3_15 */
+	{VIN1A_D13, (M14 | PIN_OUTPUT_PULLDOWN)},	       /* AF6 USR0: vin1a_d13.gpio3_17 */
+	{VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)},		/* AF3 WL_REG_ON: vin1a_d14.gpio3_18 */
+	{VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)},		/* AF1 BT_HOST_WAKE: vin1a_d16.gpio3_20 */
+	{VIN1A_D17, (M14 | PIN_OUTPUT_PULLDOWN)},	       /* AE3 BT_WAKE: vin1a_d17.gpio3_21 */
+	{VIN1A_D18, (M14 | PIN_OUTPUT_PULLUP)},		 /* AE5 BT_REG_ON: vin1a_d18.gpio3_22 */
+	{VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)},		/* AE1 WL_HOST_WAKE: vin1a_d19.gpio3_23 */
+	{VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)},		/* P9_26B: AE2: vin1a_d20.gpio3_24 */
+	{VIN1A_D23, (M14 | PIN_OUTPUT_PULLDOWN)},	       /* AD3 VDD_ADC_SEL: vin1a_d23.gpio3_27 */
+
+	{VIN2A_D2, (M14 | PIN_INPUT_PULLDOWN)},		 /* P8_15A: D1: vin2a_d2.gpio4_3 */
+
+	/* Cape Bus i2c (gpio shared) */
+	{VIN2A_D4, (M14 | PIN_INPUT)},			  /* P9_20B: D2_UART10_CTSN: vin2a_d4. (Shared with T9_GPIO7_4) */
+	{VIN2A_D5, (M14 | PIN_INPUT)},			  /* P9_19B: F4_UART10_RTSN: vin2a_d5. (Shared with R6_GPIO7_3) */
+
+	{VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)},		 /* P8_18: F5_GPIO4_9: vin2a_d8.gpio4_9 */
+	{VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)},		 /* P8_19: E6_EHRPWM2A: vin2a_d9.gpio4_10 */
+	{VIN2A_D10, (M14 | PIN_INPUT_PULLDOWN)},		/* P8_13: D3_EHRPWM2B: vin2a_d10.gpio4_11 */
+	{VIN2A_D12, (M14 | PIN_INPUT_PULLDOWN)},		/* P8_14: D5_GPIO4_13: vin2a_d12.gpio4_13 */
+	{VIN2A_D13, (M10 | PIN_INPUT_PULLDOWN)},		/* P9_42B: C2_GPIO4_14: vin2a_d13.eQEP3A_in */
+	{VIN2A_D14, (M10 | PIN_INPUT_PULLDOWN)},		/* P9_27A: C3_GPIO4_15: vin2a_d14.eQEP3B_in */
+	{VIN2A_D17, (M14 | PIN_INPUT_PULLDOWN)},		/* P9_14: D6_EHRPWM3A: vin2a_d17.gpio4_25 */
+	{VIN2A_D18, (M14 | PIN_INPUT_PULLDOWN)},		/* P9_16: C5_EHRPWM3B: vin2a_d18.gpio4_26 */
+	{VIN2A_D19, (M12 | PIN_INPUT | MANUAL_MODE)},	   /* P8_15B: A3_GPIO4_27: vin2a_d19.pr1_pru1_gpi16 */
+	{VIN2A_D20, (M14 | PIN_INPUT_PULLDOWN)},		/* P8_26: B3_GPIO4_28: vin2a_d20.gpio4_28 */
+	{VIN2A_D21, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},  /* P8_16: B4_GPIO4_29: vin2a_d21.pr1_pru1_gpi18 */
+	{VOUT1_CLK, (M14 | PIN_INPUT_PULLDOWN)},		/* P8_28A: D11_VOUT1_CLK: vout1_clk.gpio4_19 */
+	{VOUT1_DE, (M14 | PIN_INPUT_PULLDOWN)},		 /* P8_30A: B10_VOUT1_DE: vout1_de.gpio4_20 */
+	{VOUT1_HSYNC, (M14 | PIN_INPUT_PULLDOWN)},	      /* P8_29A: C11_VOUT1_HSYNC: vout1_hsync.gpio4_22 */
+	{VOUT1_VSYNC, (M14 | PIN_INPUT_PULLDOWN)},	      /* P8_27A: E11_VOUT1_VSYNC: vout1_vsync.gpio4_23 */
+	{VOUT1_D0, (M14 | PIN_INPUT_PULLDOWN)},		 /* P8_45A: F11_VOUT1_D0: vout1_d0.gpio8_0 */
+	{VOUT1_D1, (M14 | PIN_INPUT_PULLDOWN)},		 /* P8_46A: G10_VOUT1_D1: vout1_d1.gpio8_1 */
+	{VOUT1_D2, (M14 | PIN_INPUT_PULLDOWN)},		 /* P8_43: F10_LCD_DATA2: vout1_d2.gpio8_2 */
+	{VOUT1_D3, (M14 | PIN_INPUT_PULLDOWN)},		 /* P8_44: G11_LCD_DATA3: vout1_d3.gpio8_3 */
+	{VOUT1_D4, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* P8_41: E9_LCD_DATA4: vout1_d4.pr2_pru0_gpi1 */
+	{VOUT1_D5, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* P8_42: F9_LCD_DATA5: vout1_d5.pr2_pru0_gpi2 */
+	{VOUT1_D6, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* P8_39: F8_LCD_DATA6: vout1_d6.pr2_pru0_gpi3 */
+	{VOUT1_D7, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* P8_40: E7_LCD_DATA7: vout1_d7.pr2_pru0_gpi4 */
+	{VOUT1_D8, (M14 | PIN_INPUT_PULLDOWN)},		 /* P8_37A: E8_VOUT1_D8: vout1_d8.gpio8_8 */
+	{VOUT1_D9, (M14 | PIN_INPUT_PULLDOWN)},		 /* P8_38A: D9_VOUT1_D9: vout1_d9.gpio8_9 */
+	{VOUT1_D10, (M14 | PIN_INPUT)},			 /* P8_36A: D7_VOUT1_D10: vout1_d10.gpio8_10 */
+	{VOUT1_D11, (M14 | PIN_INPUT_PULLDOWN)},		/* P8_34A: D8_VOUT1_D11: vout1_d11.gpio8_11 */
+	{VOUT1_D14, (M14 | PIN_INPUT_PULLDOWN)},		/* P8_31A: C8_VOUT1_D14: vout1_d14.gpio8_14 */
+	{VOUT1_D15, (M14 | PIN_INPUT_PULLDOWN)},		/* P8_32A: C7_VOUT1_D15: vout1_d15.gpio8_15 */
+	{VOUT1_D17, (M14 | PIN_INPUT_PULLDOWN)},		/* P9_11B: B8_GPIO8_17: vout1_d17.gpio8_17 */
+	{VOUT1_D18, (M14 | PIN_INPUT_PULLDOWN)},		/* P8_17: A7_GPIO8_18: vout1_d18.gpio8_18 */
+	{VOUT1_D19, (M12 | PIN_INPUT | MANUAL_MODE)},	   /* P8_27B: A8_GPIO8_19: vout1_d19.pr2_pru0_gpi16 */
+	{VOUT1_D20, (M12 | PIN_INPUT | MANUAL_MODE)},	   /* P8_28B: C9_GPIO8_20: vout1_d20.pr2_pru0_gpi17 */
+	{VOUT1_D21, (M12 | PIN_INPUT | MANUAL_MODE)},	   /* P8_29B: A9_GPIO8_21: vout1_d21.pr2_pru0_gpi18 */
+	{VOUT1_D22, (M12 | PIN_INPUT | MANUAL_MODE)},	   /* P8_30B: B9_GPIO8_22: vout1_d22.pr2_pru0_gpi19 */
+
+	/* Ethernet (and USB A overcurrent) */
+	{MDIO_MCLK, (M0 | PIN_OUTPUT | SLEWCONTROL)},	   /* V1 MDIO_CLK: mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)},	       /* U4 MDIO_D: mdio_d.mdio_d */
+	{UART3_RXD, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},  /* V2 GPIO5_18 (USB A overcurrent): uart3_rxd.gpio5_18 */
+	{UART3_TXD, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},  /* Y1 MII0_INT: uart3_txd.gpio5_19 */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)},	  /* W9 RGMII0_TXC: rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* V9 RGMII0_TXCTL: rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)},	 /* V7 RGMII0_TXD3: rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)},	 /* U7 RGMII0_TXD2: rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)},	 /* V6 RGMII0_TXD1: rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)},	 /* U6 RGMII0_TXD0: rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)},	   /* U5 RGMII0_RXC: rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)},	 /* V5 RGMII0_RXCTL: rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)},	  /* V4 RGMII0_RXD3: rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)},	  /* V3 RGMII0_RXD2: rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)},	  /* Y2 RGMII0_RXD1: rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)},	  /* W2 RGMII0_RXD0: rgmii0_rxd0.rgmii0_rxd0 */
+
+	{USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},       /* AC10 USB2_DRVVBUS: usb2_drvvbus.usb2_drvvbus */
+
+	{GPIO6_14, (M3 | PIN_INPUT)},			   /* P9_26A: E21_UART10_RXD: gpio6_14.uart10_rxd */
+	{GPIO6_15, (M0 | PIN_INPUT_PULLDOWN)},		  /* P9_24: F20_UART10_TXD: gpio6_15.gpio6_15 */
+	{GPIO6_16, (M0 | PIN_INPUT_PULLUP)},		    /* F21 PMIC_INT: gpio6_16.gpio6_16 */
+	{XREF_CLK0, (M14 | PIN_INPUT_PULLDOWN)},		/* P9_25: D18_GPIO6_17: xref_clk0.gpio6_17 */
+	{XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)},		/* P8_09: E17_TIMER14: xref_clk1.gpio6_18 */
+	{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)},		/* P9_22A: B26_TIMER15: xref_clk2.gpio6_19 */
+	{XREF_CLK3, (M14 | PIN_INPUT_PULLDOWN)},		/* P9_41A: C23_CLKOUT3: xref_clk3.gpio6_20 */
+	{MCASP1_ACLKR, (M14 | PIN_INPUT_PULLDOWN)},	     /* P9_12: B14_MCASP_ACLKR: mcasp1_aclkr.gpio5_0 */
+	{MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* P9_18B: G12_GPIO5_2: mcasp1_axr0.i2c5_sda */
+	{MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},  /* P9_17B: F12_GPIO5_3: mcasp1_axr1.i2c5_scl */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	      /* J11 USR1: mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)},	       /* F13 eMMC_RSTn (missing on schematic): mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR8, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},	/* P9_31A: B12_SPI3_SCLK: mcasp1_axr8.gpio5_10 */
+	{MCASP1_AXR9, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},	/* P9_29A: A11_SPI3_D1: mcasp1_axr9.gpio5_11 */
+	{MCASP1_AXR10, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},       /* P9_30: B13_SPI3_D0: mcasp1_axr10.gpio5_12 */
+	{MCASP1_AXR11, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},       /* P9_28: A12_SPI3_CS0: mcasp1_axr11.gpio4_17 */
+	{MCASP1_AXR12, (M14 | PIN_INPUT | SLEWCONTROL)},		/* P9_42A: E14_GPIO4_18: mcasp1_axr12.gpio4_18 */
+	{MCASP1_AXR13, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},       /* P8_10: A13_TIMER10: mcasp1_axr13.gpio6_4 */
+	{MCASP1_AXR14, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},       /* P8_07: G14_TIMER11: mcasp1_axr14.gpio6_5 */
+	{MCASP1_AXR15, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},       /* P8_08: F14_TIMER12: mcasp1_axr15.gpio6_6 */
+	{MCASP3_AXR0, (M4 | PIN_INPUT | SLEWCONTROL)},		  /* P9_11A: B19_UART5_RXD: mcasp3_axr0.uart5_rxd */
+
+	/* microSD Socket */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},		    /*  W6: mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},		    /*  Y6: mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},		   /* AA6: mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},		   /*  Y4: mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},		   /* AA5: mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},		   /*  Y3: mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},    /*  W7: mmc1_sdcd.gpio6_27 */
+
+	{MMC3_CLK, (M14 | PIN_INPUT_PULLUP)},		   /* P8_21: AD4_MMC3_CLK: mmc3_clk.gpio6_29 */
+	{MMC3_CMD, (M14 | PIN_INPUT_PULLUP)},		   /* P8_20: AC4_MMC3_CMD: mmc3_cmd.gpio6_30 */
+	{MMC3_DAT0, (M14 | PIN_INPUT_PULLUP)},		  /* P8_25: AC7_MMC3_DATA0: mmc3_dat0.gpio6_31 */
+	{MMC3_DAT1, (M14 | PIN_INPUT_PULLUP)},		  /* P8_24: AC6_MMC3_DATA1: mmc3_dat1.gpio7_0 */
+	{MMC3_DAT2, (M14 | PIN_INPUT_PULLUP)},		  /* P8_05: AC9_MMC3_DATA2: mmc3_dat2.gpio7_1 */
+	{MMC3_DAT3, (M14 | PIN_INPUT_PULLUP)},		  /* P8_06: AC3_MMC3_DATA3: mmc3_dat3.gpio7_2 */
+	{MMC3_DAT4, (M14 | PIN_INPUT_PULLUP)},		  /* P8_23: AC8_MMC3_DATA4: mmc3_dat4.gpio1_22 */
+	{MMC3_DAT5, (M14 | PIN_INPUT_PULLUP)},		  /* P8_22: AD6_MMC3_DATA5: mmc3_dat5.gpio1_23 */
+	{MMC3_DAT6, (M14 | PIN_INPUT_PULLUP)},		  /* P8_03: AB8_MMC3_DATA6: mmc3_dat6.gpio1_24 */
+	{MMC3_DAT7, (M14 | PIN_INPUT_PULLUP)},		  /* P8_04: AB5_MMC3_DATA7: mmc3_dat7.gpio1_25 */
+	{SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)},		 /* P9_23: A22_SPI2_CS1: spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M6 | PIN_INPUT | SLEWCONTROL)},	     /* B21 HDMI_DDC_HPD: spi1_cs2.hdmi1_hpd */
+	{SPI2_SCLK, (M1 | PIN_INPUT)},			  /* P9_22B: A26_UART3_RXD: spi2_sclk.uart3_rxd */
+	{SPI2_D0, (M14 | PIN_INPUT | SLEWCONTROL)},	     /* P9_18A: G17_SPI2_D0: spi2_d0.gpio7_16 */
+	{SPI2_CS0, (M14 | PIN_INPUT | SLEWCONTROL)},	    /* P9_17A: B24_SPI2_CS0: spi2_cs0.gpio7_17 */
+	{DCAN1_TX, (M2 | PIN_INPUT | SLEWCONTROL)},	     /* G20 unused: dcan1_tx.uart8_rxd */
+	{DCAN1_RX, (M6 | PIN_INPUT | SLEWCONTROL)},	     /* G19 unused: dcan1_rx.hdmi1_cec */
+
+	/* BeagleBone AI: Debug UART */
+	{UART1_RXD, (M0 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},   /* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},  /* uart1_txd.uart1_txd */
+
+	/* WiFi MMC */
+	{UART1_CTSN, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},    /* uart1_ctsn.mmc4_clk */
+	{UART1_RTSN, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},    /* uart1_rtsn.mmc4_cmd */
+	{UART2_RXD, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* uart2_rxd.mmc4_dat0 */
+	{UART2_TXD, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},     /* uart2_txd.mmc4_dat1 */
+	{UART2_CTSN, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},    /* uart2_ctsn.mmc4_dat2 */
+	{UART2_RTSN, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},    /* uart2_rtsn.mmc4_dat3 */
+
+	/* On-board I2C */
+	{I2C1_SDA, (M0 | PIN_INPUT_PULLUP)},    /* i2c1_sda.i2c1_sda */
+	{I2C1_SCL, (M0 | PIN_INPUT_PULLUP)},    /* i2c1_scl.i2c1_scl */
+
+	/* HDMI I2C */
+	{I2C2_SDA, (M1 | PIN_INPUT_PULLUP)},    /* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)},    /* i2c2_scl.hdmi1_ddc_sda */
+
+	{ON_OFF, (M0 | PIN_OUTPUT)},		    /*  Y11: on_off.on_off */
+	{RTC_PORZ, (M0 | PIN_INPUT)},		   /* AB17: rtc_porz.rtc_porz */
+	{TMS, (M0 | PIN_INPUT_PULLUP)},		 /*  F18: tms.tms */
+	{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},   /*  D23: tdi.tdi */
+	{TDO, (M0 | PIN_OUTPUT)},		       /*  F19: tdo.tdo */
+	{TCLK, (M0 | PIN_INPUT_PULLDOWN)},	      /*  E20: tclk.tclk */
+	{TRSTN, (M0 | PIN_INPUT)},		      /*  D20: trstn.trstn */
+	{RTCK, (M0 | PIN_OUTPUT)},		      /*  E18: rtck.rtck */
+	{EMU0, (M0 | PIN_INPUT)},		       /*  G21: emu0.emu0 */
+	{EMU1, (M0 | PIN_INPUT)},		       /*  D24: emu1.emu1 */
+	{RESETN, (M0 | PIN_INPUT_PULLUP)},	      /*  E23: resetn.resetn */
+	{NMIN_DSP, (M0 | PIN_INPUT)},		   /*  D21: nmin_dsp.nmin_dsp */
+	{RSTOUTN, (M0 | PIN_OUTPUT)},		   /*  F23: rstoutn.rstoutn */
+};
+
+const struct pad_conf_entry core_padconf_array_delta_x15_sr1_1[] = {
+	{MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdwp.gpio6_28 */
+	{VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_de.vout1_de */
+	{VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d23.vout1_d23 */
+};
+
+const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0[] = {
+	{VIN1A_CLK0, (M14 | PIN_INPUT)},	/* vin1a_clk0.gpio2_30 */
+	{VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_de.vout1_de */
+	{VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d23.vout1_d23 */
+};
+
+const struct iodelay_cfg_entry iodelay_cfg_array_bbai[] = {
+	{0x0190, 274, 0},       /* CFG_GPMC_A19_OEN */
+	{0x0194, 162, 0},       /* CFG_GPMC_A19_OUT */
+	{0x01A8, 401, 0},       /* CFG_GPMC_A20_OEN */
+	{0x01AC, 73, 0},        /* CFG_GPMC_A20_OUT */
+	{0x01B4, 465, 0},       /* CFG_GPMC_A21_OEN */
+	{0x01B8, 115, 0},       /* CFG_GPMC_A21_OUT */
+	{0x01C0, 633, 0},       /* CFG_GPMC_A22_OEN */
+	{0x01C4, 47, 0},        /* CFG_GPMC_A22_OUT */
+	{0x01D0, 935, 280},     /* CFG_GPMC_A23_OUT */
+	{0x01D8, 621, 0},       /* CFG_GPMC_A24_OEN */
+	{0x01DC, 0, 0},         /* CFG_GPMC_A24_OUT */
+	{0x01E4, 183, 0},       /* CFG_GPMC_A25_OEN */
+	{0x01E8, 0, 0},         /* CFG_GPMC_A25_OUT */
+	{0x01F0, 467, 0},       /* CFG_GPMC_A26_OEN */
+	{0x01F4, 0, 0},         /* CFG_GPMC_A26_OUT */
+	{0x01FC, 262, 0},       /* CFG_GPMC_A27_OEN */
+	{0x0200, 46, 0},        /* CFG_GPMC_A27_OUT */
+	{0x0364, 684, 0},       /* CFG_GPMC_CS1_OEN */
+	{0x0368, 76, 0},        /* CFG_GPMC_CS1_OUT */
+	{0x06F0, 260, 0},       /* CFG_RGMII0_RXC_IN */
+	{0x06FC, 0, 1412},      /* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 123, 1047},    /* CFG_RGMII0_RXD0_IN */
+	{0x0714, 139, 1081},    /* CFG_RGMII0_RXD1_IN */
+	{0x0720, 195, 1100},    /* CFG_RGMII0_RXD2_IN */
+	{0x072C, 239, 1216},    /* CFG_RGMII0_RXD3_IN */
+	{0x0740, 89, 0},        /* CFG_RGMII0_TXC_OUT */
+	{0x074C, 15, 125},      /* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 339, 162},     /* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 146, 94},      /* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 27},        /* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 291, 205},     /* CFG_RGMII0_TXD3_OUT */
+	{0x0840, 0, 0},         /* CFG_UART1_CTSN_IN */
+	{0x0848, 0, 0},         /* CFG_UART1_CTSN_OUT */
+	{0x084C, 307, 0},       /* CFG_UART1_RTSN_IN */
+	{0x0850, 0, 0},         /* CFG_UART1_RTSN_OEN */
+	{0x0854, 0, 0},         /* CFG_UART1_RTSN_OUT */
+	{0x0870, 785, 0},       /* CFG_UART2_CTSN_IN */
+	{0x0874, 0, 0},         /* CFG_UART2_CTSN_OEN */
+	{0x0878, 0, 0},         /* CFG_UART2_CTSN_OUT */
+	{0x087C, 613, 0},       /* CFG_UART2_RTSN_IN */
+	{0x0880, 0, 0},         /* CFG_UART2_RTSN_OEN */
+	{0x0884, 0, 0},         /* CFG_UART2_RTSN_OUT */
+	{0x0888, 683, 0},       /* CFG_UART2_RXD_IN */
+	{0x088C, 0, 0},         /* CFG_UART2_RXD_OEN */
+	{0x0890, 0, 0},	 	/* CFG_UART2_RXD_OUT */
+	{0x0894, 835, 0},       /* CFG_UART2_TXD_IN */
+	{0x0898, 0, 0},         /* CFG_UART2_TXD_OEN */
+	{0x089C, 0, 0},         /* CFG_UART2_TXD_OUT */
+	{0x0ABC, 0, 1100},      /* CFG_VIN2A_D19_IN */
+	{0x0AE0, 0, 1300},      /* CFG_VIN2A_D21_IN */
+	{0x0B1C, 0, 1000},      /* CFG_VIN2A_D4_IN */
+	{0x0B28, 0, 1700},      /* CFG_VIN2A_D5_IN */
+	{0x0C18, 0, 500},       /* CFG_VOUT1_D19_IN */
+	{0x0C30, 0, 716},       /* CFG_VOUT1_D20_IN */
+	{0x0C3C, 0, 0},         /* CFG_VOUT1_D21_IN */
+	{0x0C48, 0, 404},       /* CFG_VOUT1_D22_IN */
+	{0x0C78, 0, 0},         /* CFG_VOUT1_D4_IN */
+	{0x0C84, 0, 365},       /* CFG_VOUT1_D5_IN */
+	{0x0C90, 0, 0},	 	/* CFG_VOUT1_D6_IN */
+	{0x0C9C, 0, 218},       /* CFG_VOUT1_D7_IN */
+};
+
+const struct pad_conf_entry core_padconf_array_essential_am574x_idk[] = {
+	{GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a0.vin4b_d0 */
+	{GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a1.vin4b_d1 */
+	{GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a2.vin4b_d2 */
+	{GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a3.vin4b_d3 */
+	{GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a4.vin4b_d4 */
+	{GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a5.vin4b_d5 */
+	{GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a6.vin4b_d6 */
+	{GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a7.vin4b_d7 */
+	{GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a8.vin4b_hsync1 */
+	{GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a9.vin4b_vsync1 */
+	{GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a10.vin4b_clk1 */
+	{GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a11.vin4b_de1 */
+	{GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a12.vin4b_fld1 */
+	{GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
+	{VIN1A_D5, (M14 | PIN_OUTPUT)},	/* vin1a_d5.gpio3_9 */
+	{VIN1A_D6, (M14 | PIN_OUTPUT)},	/* vin1a_d6.gpio3_10 */
+	{VIN1A_D7, (M14 | PIN_OUTPUT)},	/* vin1a_d7.gpio3_11 */
+	{VIN1A_D8, (M14 | PIN_OUTPUT)},	/* vin1a_d8.gpio3_12 */
+	{VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d10.gpio3_14 */
+	{VIN1A_D12, (M14 | PIN_INPUT)},	/* vin1a_d12.gpio3_16 */
+	{VIN1A_D13, (M14 | PIN_OUTPUT)},	/* vin1a_d13.gpio3_17 */
+	{VIN1A_D14, (M14 | PIN_OUTPUT)},	/* vin1a_d14.gpio3_18 */
+	{VIN1A_D15, (M14 | PIN_OUTPUT)},	/* vin1a_d15.gpio3_19 */
+	{VIN1A_D17, (M14 | PIN_OUTPUT)},	/* vin1a_d17.gpio3_21 */
+	{VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)},	/* vin1a_d18.gpio3_22 */
+	{VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)},	/* vin1a_d19.gpio3_23 */
+	{VIN1A_D22, (M14 | PIN_INPUT)},	/* vin1a_d22.gpio3_26 */
+	{VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_clk0.gpio3_28 */
+	{VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_de0.gpio3_29 */
+	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_fld0.gpio3_30 */
+	{VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_hsync0.gpio3_31 */
+	{VIN2A_VSYNC0, (M14 | PIN_INPUT)},	/* vin2a_vsync0.gpio4_0 */
+	{VIN2A_D0, (M11 | PIN_INPUT)},	/* vin2a_d0.pr1_uart0_rxd */
+	{VIN2A_D1, (M11 | PIN_OUTPUT)},	/* vin2a_d1.pr1_uart0_txd */
+	{VIN2A_D2, (M10 | PIN_OUTPUT)},	/* vin2a_d2.eCAP1_in_PWM1_out */
+	{VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d3.pr1_edc_latch0_in */
+	{VIN2A_D4, (M11 | PIN_OUTPUT)},	/* vin2a_d4.pr1_edc_sync0_out */
+	{VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d5.pr1_pru1_gpo2 */
+	{VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)},	/* vin2a_d10.pr1_mdio_mdclk */
+	{VIN2A_D11, (M11 | PIN_INPUT)},	/* vin2a_d11.pr1_mdio_data */
+	{VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_de.vout1_de */
+	{VOUT1_FLD, (M14 | PIN_OUTPUT)},	/* vout1_fld.gpio4_21 */
+	{VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d23.vout1_d23 */
+	{MDIO_MCLK, (M0 | PIN_INPUT_SLEW)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M0 | PIN_OUTPUT)},	/* gpio6_14.gpio6_14 */
+	{GPIO6_15, (M0 | PIN_OUTPUT)},	/* gpio6_15.gpio6_15 */
+	{GPIO6_16, (M0 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
+	{XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk0.pr2_mii1_col */
+	{XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.pr2_mii1_crs */
+	{XREF_CLK2, (M14 | PIN_OUTPUT)},	/* xref_clk2.gpio6_19 */
+	{XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)},	/* xref_clk3.clkout3 */
+	{MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)},	/* mcasp1_aclkx.pr2_mdio_mdclk */
+	{MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_fsx.pr2_mdio_data */
+	{MCASP1_ACLKR, (M14 | PIN_INPUT)},	/* mcasp1_aclkr.gpio5_0 */
+	{MCASP1_FSR, (M14 | PIN_INPUT)},	/* mcasp1_fsr.gpio5_1 */
+	{MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.pr2_mii0_rxer */
+	{MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr1.pr2_mii_mt0_clk */
+	{MCASP1_AXR2, (M14 | PIN_INPUT)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_OUTPUT)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_OUTPUT)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_OUTPUT)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_OUTPUT)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr8.pr2_mii0_txen */
+	{MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr9.pr2_mii0_txd3 */
+	{MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr10.pr2_mii0_txd2 */
+	{MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr11.pr2_mii0_txd1 */
+	{MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr12.pr2_mii0_txd0 */
+	{MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr13.pr2_mii_mr0_clk */
+	{MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr14.pr2_mii0_rxdv */
+	{MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr15.pr2_mii0_rxd3 */
+	{MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkx.pr2_mii0_rxd2 */
+	{MCASP2_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_fsx.pr2_mii0_rxd1 */
+	{MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr2.pr2_mii0_rxd0 */
+	{MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr3.pr2_mii0_rxlink */
+	{MCASP2_AXR4, (M14 | PIN_INPUT)},	/* mcasp2_axr4.gpio1_4 */
+	{MCASP2_AXR5, (M14 | PIN_OUTPUT)},	/* mcasp2_axr5.gpio6_7 */
+	{MCASP2_AXR6, (M14 | PIN_OUTPUT)},	/* mcasp2_axr6.gpio2_29 */
+	{MCASP2_AXR7, (M14 | PIN_INPUT)},	/* mcasp2_axr7.gpio1_5 */
+	{MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.pr2_mii0_crs */
+	{MCASP3_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.pr2_mii0_col */
+	{MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr0.pr2_mii1_rxer */
+	{MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr1.pr2_mii1_rxlink */
+	{MCASP4_ACLKX, (M2 | PIN_INPUT)},	/* mcasp4_aclkx.spi3_sclk */
+	{MCASP4_FSX, (M2 | PIN_INPUT)},	/* mcasp4_fsx.spi3_d1 */
+	{MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)},	/* mcasp4_axr1.spi3_cs0 */
+	{MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)},	/* mcasp5_aclkx.pr2_pru1_gpo1 */
+	{MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)},	/* mcasp5_fsx.pr2_pru1_gpi2 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdcd.gpio6_27 */
+	{MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdwp.gpio6_28 */
+	{GPIO6_10, (M11 | PIN_INPUT_PULLUP)},	/* gpio6_10.pr2_mii_mt1_clk */
+	{GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)},	/* gpio6_11.pr2_mii1_txen */
+	{MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_clk.pr2_mii1_txd3 */
+	{MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_cmd.pr2_mii1_txd2 */
+	{MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat0.pr2_mii1_txd1 */
+	{MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat1.pr2_mii1_txd0 */
+	{MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat2.pr2_mii_mr1_clk */
+	{MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat3.pr2_mii1_rxdv */
+	{MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat4.pr2_mii1_rxd3 */
+	{MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat5.pr2_mii1_rxd2 */
+	{MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat6.pr2_mii1_rxd1 */
+	{MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat7.pr2_mii1_rxd0 */
+	{SPI1_SCLK, (M14 | PIN_OUTPUT)},	/* spi1_sclk.gpio7_7 */
+	{SPI1_D1, (M14 | PIN_OUTPUT)},	/* spi1_d1.gpio7_8 */
+	{SPI1_D0, (M14 | PIN_OUTPUT)},	/* spi1_d0.gpio7_9 */
+	{SPI1_CS0, (M14 | PIN_OUTPUT)},	/* spi1_cs0.gpio7_10 */
+	{SPI1_CS1, (M14 | PIN_OUTPUT)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_SLEW)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M0 | PIN_INPUT)},	/* spi2_sclk.spi2_sclk */
+	{SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_d1.spi2_d1 */
+	{SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_d0.spi2_d0 */
+	{SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_cs0.spi2_cs0 */
+	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
+	{DCAN1_RX, (M15 | PULL_UP)},	/* dcan1_rx.safe for dcan1_rx */
+	{UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)},	/* uart1_rxd.gpio7_22 */
+	{UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)},	/* uart1_txd.gpio7_23 */
+	{UART2_RXD, (M4 | PIN_INPUT)},	/* uart2_rxd.uart2_rxd */
+	{UART2_TXD, (M0 | PIN_OUTPUT)},	/* uart2_txd.uart2_txd */
+	{UART2_CTSN, (M2 | PIN_INPUT)},	/* uart2_ctsn.uart3_rxd */
+	{UART2_RTSN, (M1 | PIN_OUTPUT)},	/* uart2_rtsn.uart3_txd */
+	{I2C1_SDA, (M0 | PIN_INPUT)},	/* i2c1_sda.i2c1_sda */
+	{I2C1_SCL, (M0 | PIN_INPUT)},	/* i2c1_scl.i2c1_scl */
+	{I2C2_SDA, (M1 | PIN_INPUT)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M0 | PIN_INPUT)},	/* Wakeup0.Wakeup0 */
+	{WAKEUP1, (M0 | PIN_INPUT)},	/* Wakeup1.Wakeup1 */
+	{WAKEUP2, (M0 | PIN_INPUT)},	/* Wakeup2.Wakeup2 */
+	{WAKEUP3, (M0 | PIN_INPUT)},	/* Wakeup3.Wakeup3 */
+	{ON_OFF, (M0 | PIN_OUTPUT)},	/* on_off.on_off */
+	{RTC_PORZ, (M0 | PIN_INPUT)},	/* rtc_porz.rtc_porz */
+	{TMS, (M0 | PIN_INPUT_PULLUP)},	/* tms.tms */
+	{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* tdi.tdi */
+	{TDO, (M0 | PIN_OUTPUT_PULLUP)},	/* tdo.tdo */
+	{TCLK, (M0 | PIN_INPUT_PULLUP)},	/* tclk.tclk */
+	{TRSTN, (M0 | PIN_INPUT_PULLDOWN)},	/* trstn.trstn */
+	{RTCK, (M0 | PIN_OUTPUT_PULLUP)},	/* rtck.rtck */
+	{EMU0, (M0 | PIN_INPUT_PULLUP)},	/* emu0.emu0 */
+	{EMU1, (M0 | PIN_INPUT_PULLUP)},	/* emu1.emu1 */
+	{RESETN, (M0 | PIN_INPUT)},	/* resetn.resetn */
+	{NMIN_DSP, (M0 | PIN_INPUT)},	/* nmin_dsp.nmin_dsp */
+	{RSTOUTN, (M0 | PIN_OUTPUT)},	/* rstoutn.rstoutn */
+};
+
+const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
+	{GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a0.vin4b_d0 */
+	{GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a1.vin4b_d1 */
+	{GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a2.vin4b_d2 */
+	{GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a3.vin4b_d3 */
+	{GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a4.vin4b_d4 */
+	{GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a5.vin4b_d5 */
+	{GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a6.vin4b_d6 */
+	{GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a7.vin4b_d7 */
+	{GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a8.vin4b_hsync1 */
+	{GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a9.vin4b_vsync1 */
+	{GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a10.vin4b_clk1 */
+	{GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a11.vin4b_de1 */
+	{GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a12.vin4b_fld1 */
+	{GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
+	{VIN1A_D5, (M14 | PIN_OUTPUT)},	/* vin1a_d5.gpio3_9 */
+	{VIN1A_D6, (M14 | PIN_OUTPUT)},	/* vin1a_d6.gpio3_10 */
+	{VIN1A_D7, (M14 | PIN_OUTPUT)},	/* vin1a_d7.gpio3_11 */
+	{VIN1A_D8, (M14 | PIN_OUTPUT)},	/* vin1a_d8.gpio3_12 */
+	{VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d10.gpio3_14 */
+	{VIN1A_D12, (M14 | PIN_INPUT)},	/* vin1a_d12.gpio3_16 */
+	{VIN1A_D13, (M14 | PIN_OUTPUT)},	/* vin1a_d13.gpio3_17 */
+	{VIN1A_D14, (M14 | PIN_OUTPUT)},	/* vin1a_d14.gpio3_18 */
+	{VIN1A_D15, (M14 | PIN_OUTPUT)},	/* vin1a_d15.gpio3_19 */
+	{VIN1A_D17, (M14 | PIN_OUTPUT)},	/* vin1a_d17.gpio3_21 */
+	{VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)},	/* vin1a_d18.gpio3_22 */
+	{VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)},	/* vin1a_d19.gpio3_23 */
+	{VIN1A_D22, (M14 | PIN_INPUT)},	/* vin1a_d22.gpio3_26 */
+	{VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_clk0.gpio3_28 */
+	{VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_de0.gpio3_29 */
+	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_fld0.gpio3_30 */
+	{VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_hsync0.gpio3_31 */
+	{VIN2A_VSYNC0, (M14 | PIN_INPUT)},	/* vin2a_vsync0.gpio4_0 */
+	{VIN2A_D0, (M11 | PIN_INPUT)},	/* vin2a_d0.pr1_uart0_rxd */
+	{VIN2A_D1, (M11 | PIN_OUTPUT)},	/* vin2a_d1.pr1_uart0_txd */
+	{VIN2A_D2, (M10 | PIN_OUTPUT)},	/* vin2a_d2.eCAP1_in_PWM1_out */
+	{VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d3.pr1_edc_latch0_in */
+	{VIN2A_D4, (M11 | PIN_OUTPUT)},	/* vin2a_d4.pr1_edc_sync0_out */
+	{VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d5.pr1_pru1_gpo2 */
+	{VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)},	/* vin2a_d10.pr1_mdio_mdclk */
+	{VIN2A_D11, (M11 | PIN_INPUT)},	/* vin2a_d11.pr1_mdio_data */
+	{VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_de.vout1_de */
+	{VOUT1_FLD, (M14 | PIN_OUTPUT)},	/* vout1_fld.gpio4_21 */
+	{VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d23.vout1_d23 */
+	{MDIO_MCLK, (M0 | PIN_INPUT_SLEW)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M0 | PIN_OUTPUT)},	/* gpio6_14.gpio6_14 */
+	{GPIO6_15, (M0 | PIN_OUTPUT)},	/* gpio6_15.gpio6_15 */
+	{GPIO6_16, (M0 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
+	{XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk0.pr2_mii1_col */
+	{XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.pr2_mii1_crs */
+	{XREF_CLK2, (M14 | PIN_OUTPUT)},	/* xref_clk2.gpio6_19 */
+	{XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)},	/* xref_clk3.clkout3 */
+	{MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)},	/* mcasp1_aclkx.pr2_mdio_mdclk */
+	{MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_fsx.pr2_mdio_data */
+	{MCASP1_ACLKR, (M14 | PIN_INPUT)},	/* mcasp1_aclkr.gpio5_0 */
+	{MCASP1_FSR, (M14 | PIN_INPUT)},	/* mcasp1_fsr.gpio5_1 */
+	{MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.pr2_mii0_rxer */
+	{MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr1.pr2_mii_mt0_clk */
+	{MCASP1_AXR2, (M14 | PIN_INPUT)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_OUTPUT)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_OUTPUT)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_OUTPUT)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_OUTPUT)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr8.pr2_mii0_txen */
+	{MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr9.pr2_mii0_txd3 */
+	{MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr10.pr2_mii0_txd2 */
+	{MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr11.pr2_mii0_txd1 */
+	{MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr12.pr2_mii0_txd0 */
+	{MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr13.pr2_mii_mr0_clk */
+	{MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr14.pr2_mii0_rxdv */
+	{MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr15.pr2_mii0_rxd3 */
+	{MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkx.pr2_mii0_rxd2 */
+	{MCASP2_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_fsx.pr2_mii0_rxd1 */
+	{MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr2.pr2_mii0_rxd0 */
+	{MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr3.pr2_mii0_rxlink */
+	{MCASP2_AXR4, (M14 | PIN_OUTPUT)},	/* mcasp2_axr4.gpio1_4 */
+	{MCASP2_AXR5, (M14 | PIN_OUTPUT)},	/* mcasp2_axr5.gpio6_7 */
+	{MCASP2_AXR6, (M14 | PIN_OUTPUT)},	/* mcasp2_axr6.gpio2_29 */
+	{MCASP2_AXR7, (M14 | PIN_OUTPUT)},	/* mcasp2_axr7.gpio1_5 */
+	{MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.pr2_mii0_crs */
+	{MCASP3_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.pr2_mii0_col */
+	{MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr0.pr2_mii1_rxer */
+	{MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr1.pr2_mii1_rxlink */
+	{MCASP4_ACLKX, (M2 | PIN_INPUT)},	/* mcasp4_aclkx.spi3_sclk */
+	{MCASP4_FSX, (M2 | PIN_INPUT)},	/* mcasp4_fsx.spi3_d1 */
+	{MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)},	/* mcasp4_axr1.spi3_cs0 */
+	{MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)},	/* mcasp5_aclkx.pr2_pru1_gpo1 */
+	{MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)},	/* mcasp5_fsx.pr2_pru1_gpi2 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdcd.gpio6_27 */
+	{MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdwp.gpio6_28 */
+	{GPIO6_10, (M11 | PIN_INPUT_PULLUP)},	/* gpio6_10.pr2_mii_mt1_clk */
+	{GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)},	/* gpio6_11.pr2_mii1_txen */
+	{MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_clk.pr2_mii1_txd3 */
+	{MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_cmd.pr2_mii1_txd2 */
+	{MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat0.pr2_mii1_txd1 */
+	{MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat1.pr2_mii1_txd0 */
+	{MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat2.pr2_mii_mr1_clk */
+	{MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat3.pr2_mii1_rxdv */
+	{MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat4.pr2_mii1_rxd3 */
+	{MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat5.pr2_mii1_rxd2 */
+	{MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat6.pr2_mii1_rxd1 */
+	{MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat7.pr2_mii1_rxd0 */
+	{SPI1_SCLK, (M14 | PIN_OUTPUT)},	/* spi1_sclk.gpio7_7 */
+	{SPI1_D1, (M14 | PIN_OUTPUT)},	/* spi1_d1.gpio7_8 */
+	{SPI1_D0, (M14 | PIN_OUTPUT)},	/* spi1_d0.gpio7_9 */
+	{SPI1_CS0, (M14 | PIN_OUTPUT)},	/* spi1_cs0.gpio7_10 */
+	{SPI1_CS1, (M14 | PIN_OUTPUT)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_SLEW)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M0 | PIN_INPUT)},	/* spi2_sclk.spi2_sclk */
+	{SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_d1.spi2_d1 */
+	{SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_d0.spi2_d0 */
+	{SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_cs0.spi2_cs0 */
+	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
+	{DCAN1_RX, (M15 | PULL_UP)},	/* dcan1_rx.safe for dcan1_rx */
+	{UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)},	/* uart1_rxd.gpio7_22 */
+	{UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)},	/* uart1_txd.gpio7_23 */
+	{UART2_RXD, (M4 | PIN_INPUT)},	/* uart2_rxd.uart2_rxd */
+	{UART2_TXD, (M0 | PIN_OUTPUT)},	/* uart2_txd.uart2_txd */
+	{UART2_CTSN, (M2 | PIN_INPUT)},	/* uart2_ctsn.uart3_rxd */
+	{UART2_RTSN, (M1 | PIN_OUTPUT)},	/* uart2_rtsn.uart3_txd */
+	{I2C1_SDA, (M0 | PIN_INPUT)},	/* i2c1_sda.i2c1_sda */
+	{I2C1_SCL, (M0 | PIN_INPUT)},	/* i2c1_scl.i2c1_scl */
+	{I2C2_SDA, (M1 | PIN_INPUT)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M0 | PIN_INPUT)},	/* Wakeup0.Wakeup0 */
+	{WAKEUP1, (M0 | PIN_INPUT)},	/* Wakeup1.Wakeup1 */
+	{WAKEUP2, (M0 | PIN_INPUT)},	/* Wakeup2.Wakeup2 */
+	{WAKEUP3, (M0 | PIN_INPUT)},	/* Wakeup3.Wakeup3 */
+	{ON_OFF, (M0 | PIN_OUTPUT)},	/* on_off.on_off */
+	{RTC_PORZ, (M0 | PIN_INPUT)},	/* rtc_porz.rtc_porz */
+	{TMS, (M0 | PIN_INPUT_PULLUP)},	/* tms.tms */
+	{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* tdi.tdi */
+	{TDO, (M0 | PIN_OUTPUT_PULLUP)},	/* tdo.tdo */
+	{TCLK, (M0 | PIN_INPUT_PULLUP)},	/* tclk.tclk */
+	{TRSTN, (M0 | PIN_INPUT_PULLDOWN)},	/* trstn.trstn */
+	{RTCK, (M0 | PIN_OUTPUT_PULLUP)},	/* rtck.rtck */
+	{EMU0, (M0 | PIN_INPUT_PULLUP)},	/* emu0.emu0 */
+	{EMU1, (M0 | PIN_INPUT_PULLUP)},	/* emu1.emu1 */
+	{RESETN, (M0 | PIN_INPUT)},	/* resetn.resetn */
+	{NMIN_DSP, (M0 | PIN_INPUT)},	/* nmin_dsp.nmin_dsp */
+	{RSTOUTN, (M0 | PIN_OUTPUT)},	/* rstoutn.rstoutn */
+};
+
+const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
+	{GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a0.vin1b_d0 */
+	{GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a1.vin1b_d1 */
+	{GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a2.vin1b_d2 */
+	{GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a3.vin1b_d3 */
+	{GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a4.vin1b_d4 */
+	{GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a5.vin1b_d5 */
+	{GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a6.vin1b_d6 */
+	{GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a7.vin1b_d7 */
+	{GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a8.vin1b_hsync1 */
+	{GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a9.vin1b_vsync1 */
+	{GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a10.vin1b_clk1 */
+	{GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a11.vin1b_de1 */
+	{GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a12.vin1b_fld1 */
+	{GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS0, (M14 | PIN_OUTPUT)},	/* gpmc_cs0.gpio2_19 */
+	{GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
+	{GPMC_CS3, (M14 | PIN_OUTPUT)},	/* gpmc_cs3.gpio2_21 */
+	{GPMC_CLK, (M14 | PIN_INPUT)},	/* gpmc_clk.gpio2_22 */
+	{GPMC_ADVN_ALE, (M14 | PIN_OUTPUT)},	/* gpmc_advn_ale.gpio2_23 */
+	{GPMC_OEN_REN, (M14 | PIN_OUTPUT)},	/* gpmc_oen_ren.gpio2_24 */
+	{GPMC_WEN, (M14 | PIN_OUTPUT)},	/* gpmc_wen.gpio2_25 */
+	{GPMC_BEN0, (M14 | PIN_OUTPUT)},	/* gpmc_ben0.gpio2_26 */
+	{GPMC_BEN1, (M14 | PIN_OUTPUT)},	/* gpmc_ben1.gpio2_27 */
+	{GPMC_WAIT0, (M14 | PIN_OUTPUT | SLEWCONTROL)},	/* gpmc_wait0.gpio2_28 */
+	{VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_clk0.gpio3_28 */
+	{VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_de0.gpio3_29 */
+	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_fld0.gpio3_30 */
+	{VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_hsync0.gpio3_31 */
+	{VIN2A_VSYNC0, (M14 | PIN_OUTPUT)},	/* vin2a_vsync0.gpio4_0 */
+	{VIN2A_D0, (M11 | PIN_INPUT)},	/* vin2a_d0.pr1_uart0_rxd */
+	{VIN2A_D1, (M11 | PIN_OUTPUT)},	/* vin2a_d1.pr1_uart0_txd */
+	{VIN2A_D2, (M10 | PIN_OUTPUT)},	/* vin2a_d2.eCAP1_in_PWM1_out */
+	{VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)},	/* vin2a_d10.pr1_mdio_mdclk */
+	{VIN2A_D11, (M11 | PIN_INPUT)},	/* vin2a_d11.pr1_mdio_data */
+	{VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_FLD, (M14 | PIN_OUTPUT)},	/* vout1_fld.gpio4_21 */
+	{MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{UART3_RXD, (M14 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* uart3_rxd.gpio5_18 */
+	{UART3_TXD, (M14 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},	/* uart3_txd.gpio5_19 */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M0 | PIN_OUTPUT)},	/* gpio6_14.gpio6_14 */
+	{GPIO6_15, (M0 | PIN_OUTPUT)},	/* gpio6_15.gpio6_15 */
+	{GPIO6_16, (M0 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
+	{XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk0.pr2_mii1_col */
+	{XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.pr2_mii1_crs */
+	{XREF_CLK2, (M14 | PIN_OUTPUT)},	/* xref_clk2.gpio6_19 */
+	{XREF_CLK3, (M7 | PIN_INPUT)},	/* xref_clk3.hdq0 */
+	{MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)},	/* mcasp1_aclkx.pr2_mdio_mdclk */
+	{MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_fsx.pr2_mdio_data */
+	{MCASP1_ACLKR, (M14 | PIN_INPUT)},	/* mcasp1_aclkr.gpio5_0 */
+	{MCASP1_FSR, (M14 | PIN_INPUT)},	/* mcasp1_fsr.gpio5_1 */
+	{MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.pr2_mii0_rxer */
+	{MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr1.pr2_mii_mt0_clk */
+	{MCASP1_AXR2, (M14 | PIN_INPUT)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_INPUT)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_OUTPUT)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_OUTPUT)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr8.pr2_mii0_txen */
+	{MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr9.pr2_mii0_txd3 */
+	{MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr10.pr2_mii0_txd2 */
+	{MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr11.pr2_mii0_txd1 */
+	{MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr12.pr2_mii0_txd0 */
+	{MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr13.pr2_mii_mr0_clk */
+	{MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr14.pr2_mii0_rxdv */
+	{MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr15.pr2_mii0_rxd3 */
+	{MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkx.pr2_mii0_rxd2 */
+	{MCASP2_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_fsx.pr2_mii0_rxd1 */
+	{MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr2.pr2_mii0_rxd0 */
+	{MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr3.pr2_mii0_rxlink */
+	{MCASP2_AXR4, (M14 | PIN_OUTPUT)},	/* mcasp2_axr4.gpio1_4 */
+	{MCASP2_AXR5, (M14 | PIN_OUTPUT)},	/* mcasp2_axr5.gpio6_7 */
+	{MCASP2_AXR6, (M14 | PIN_OUTPUT)},	/* mcasp2_axr6.gpio2_29 */
+	{MCASP2_AXR7, (M14 | PIN_OUTPUT)},	/* mcasp2_axr7.gpio1_5 */
+	{MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.pr2_mii0_crs */
+	{MCASP3_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.pr2_mii0_col */
+	{MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr0.pr2_mii1_rxer */
+	{MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr1.pr2_mii1_rxlink */
+	{MCASP4_ACLKX, (M2 | PIN_OUTPUT)},	/* mcasp4_aclkx.spi3_sclk */
+	{MCASP4_FSX, (M2 | PIN_INPUT)},	/* mcasp4_fsx.spi3_d1 */
+	{MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)},	/* mcasp4_axr1.spi3_cs0 */
+	{MCASP5_AXR0, (M4 | PIN_INPUT)},	/* mcasp5_axr0.uart3_rxd */
+	{MCASP5_AXR1, (M4 | PIN_OUTPUT)},	/* mcasp5_axr1.uart3_txd */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdcd.gpio6_27 */
+	{MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdwp.gpio6_28 */
+	{GPIO6_10, (M11 | PIN_INPUT_PULLUP)},	/* gpio6_10.pr2_mii_mt1_clk */
+	{GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)},	/* gpio6_11.pr2_mii1_txen */
+	{MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_clk.pr2_mii1_txd3 */
+	{MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_cmd.pr2_mii1_txd2 */
+	{MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat0.pr2_mii1_txd1 */
+	{MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat1.pr2_mii1_txd0 */
+	{MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat2.pr2_mii_mr1_clk */
+	{MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat3.pr2_mii1_rxdv */
+	{MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat4.pr2_mii1_rxd3 */
+	{MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat5.pr2_mii1_rxd2 */
+	{MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat6.pr2_mii1_rxd1 */
+	{MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat7.pr2_mii1_rxd0 */
+	{SPI1_SCLK, (M14 | PIN_OUTPUT)},	/* spi1_sclk.gpio7_7 */
+	{SPI1_D1, (M14 | PIN_OUTPUT)},	/* spi1_d1.gpio7_8 */
+	{SPI1_D0, (M14 | PIN_OUTPUT)},	/* spi1_d0.gpio7_9 */
+	{SPI1_CS0, (M14 | PIN_OUTPUT)},	/* spi1_cs0.gpio7_10 */
+	{SPI1_CS1, (M14 | PIN_OUTPUT)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_SLEW)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M0 | PIN_INPUT)},	/* spi2_sclk.spi2_sclk */
+	{SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_d1.spi2_d1 */
+	{SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_d0.spi2_d0 */
+	{SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_cs0.spi2_cs0 */
+	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
+	{DCAN1_RX, (M15 | PULL_UP)},	/* dcan1_rx.safe for dcan1_rx */
+	{UART1_RXD, (M14 | PIN_INPUT | SLEWCONTROL)},	/* uart1_rxd.gpio7_22 */
+	{UART1_CTSN, (M14 | PIN_OUTPUT)},	/* uart1_ctsn.gpio7_24 */
+	{UART1_RTSN, (M14 | PIN_OUTPUT)},	/* uart1_rtsn.gpio7_25 */
+	{I2C1_SDA, (M0 | PIN_INPUT)},	/* i2c1_sda.i2c1_sda */
+	{I2C1_SCL, (M0 | PIN_INPUT)},	/* i2c1_scl.i2c1_scl */
+	{I2C2_SDA, (M1 | PIN_INPUT)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M0 | PIN_INPUT)},	/* Wakeup0.Wakeup0 */
+	{WAKEUP3, (M0 | PIN_INPUT)},	/* Wakeup3.Wakeup3 */
+	{ON_OFF, (M0 | PIN_OUTPUT)},	/* on_off.on_off */
+	{RTC_PORZ, (M0 | PIN_INPUT)},	/* rtc_porz.rtc_porz */
+	{TMS, (M0 | PIN_INPUT_PULLUP)},	/* tms.tms */
+	{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* tdi.tdi */
+	{TDO, (M0 | PIN_OUTPUT_PULLUP)},	/* tdo.tdo */
+	{TCLK, (M0 | PIN_INPUT_PULLUP)},	/* tclk.tclk */
+	{TRSTN, (M0 | PIN_INPUT)},	/* trstn.trstn */
+	{RTCK, (M0 | PIN_OUTPUT_PULLUP)},	/* rtck.rtck */
+	{EMU0, (M0 | PIN_INPUT)},	/* emu0.emu0 */
+	{EMU1, (M0 | PIN_INPUT)},	/* emu1.emu1 */
+	{RESETN, (M0 | PIN_INPUT)},	/* resetn.resetn */
+	{RSTOUTN, (M0 | PIN_OUTPUT)},	/* rstoutn.rstoutn */
+};
+
+const struct pad_conf_entry core_padconf_array_icss1eth_am571x_idk[] = {
+	/* PR1 MII0 */
+	{VOUT1_D8, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d8.pr1_mii_mt0_clk */
+	{VOUT1_D9, (M13 | PIN_OUTPUT_PULLUP)},	/* vout1_d9.pr1_mii0_txd3 */
+	{VOUT1_D10, (M13 | PIN_OUTPUT_PULLUP)},	/* vout1_d10.pr1_mii0_txd2 */
+	{VOUT1_D11, (M13 | PIN_OUTPUT_PULLUP)},	/* vout1_d11.pr1_mii0_txen */
+	{VOUT1_D12, (M13 | PIN_OUTPUT_PULLUP)},	/* vout1_d12.pr1_mii0_txd1 */
+	{VOUT1_D13, (M13 | PIN_OUTPUT_PULLUP)},	/* vout1_d13.pr1_mii0_txd0 */
+	{VOUT1_D14, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d14.pr1_mii_mr0_clk */
+	{VOUT1_D15, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d15.pr1_mii0_rxdv */
+	{VOUT1_D16, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d16.pr1_mii0_rxd3 */
+	{VOUT1_D17, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d17.pr1_mii0_rxd2 */
+	{VOUT1_D18, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d18.pr1_mii0_rxd1 */
+	{VOUT1_D19, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d19.pr1_mii0_rxd0 */
+	{VOUT1_D20, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d20.pr1_mii0_rxer */
+	{VOUT1_D21, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d21.pr1_mii0_rxlink */
+	{VOUT1_D22, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d22.pr1_mii0_col */
+	{VOUT1_D23, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d23.pr1_mii0_crs */
+
+	/* PR1 MII1 */
+	{VIN2A_D3, (M12 | PIN_INPUT_PULLDOWN)},	/* vin2a_d3.pr1_mii1_col */
+	{VIN2A_D4, (M13 | PIN_OUTPUT_PULLUP)},	/* vin2a_d4.pr1_mii1_txd1 */
+	{VIN2A_D5, (M13 | PIN_OUTPUT_PULLUP)},	/* vin2a_d5.pr1_mii1_txd0 */
+	{VIN2A_D6, (M11 | PIN_INPUT_PULLUP)},	/* vin2a_d6.pr1_mii_mt1_clk */
+	{VIN2A_D7, (M11 | PIN_OUTPUT_PULLUP)},	/* vin2a_d7.pr1_mii1_txen */
+	{VIN2A_D8, (M11 | PIN_OUTPUT_PULLUP)},	/* vin2a_d8.pr1_mii1_txd3 */
+	{VIN2A_D9, (M11 | PIN_OUTPUT_PULLUP)},	/* vin2a_d9.pr1_mii1_txd2 */
+	{VOUT1_VSYNC, (M12 | PIN_INPUT_PULLUP)},	/* vout1_vsync.pr1_mii1_rxer */
+	{VOUT1_D0, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d0.pr1_mii1_rxlink */
+	{VOUT1_D1, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d1.pr1_mii1_crs */
+	{VOUT1_D2, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d2.pr1_mii_mr1_clk */
+	{VOUT1_D3, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d3.pr1_mii1_rxdv */
+	{VOUT1_D4, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d4.pr1_mii1_rxd3 */
+	{VOUT1_D5, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d5.pr1_mii1_rxd2 */
+	{VOUT1_D6, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d6.pr1_mii1_rxd1 */
+	{VOUT1_D7, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d7.pr1_mii1_rxd0 */
+};
+
+const struct pad_conf_entry core_padconf_array_vout_am571x_idk[] = {
+	{VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_de.vout1_de */
+	{VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d23.vout1_d23 */
+
+	{MCASP5_ACLKX, (M12 | PIN_INPUT | MANUAL_MODE)},	/* mcasp5_aclkx.pr2_pru1_gpi1 */
+	{MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)},	/* mcasp5_fsx.pr2_pru1_gpi2 */
+	{UART2_RXD, (M0 | PIN_INPUT)},	/* uart2_rxd.uart2_rxd */
+	{UART2_TXD, (M0 | PIN_OUTPUT)},	/* uart2_txd.uart2_txd */
+	{VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d5.pr1_pru1_gpo2 */
+};
+
+const struct pad_conf_entry early_padconf[] = {
+	{UART2_CTSN, (M2 | PIN_INPUT_SLEW)},	/* uart2_ctsn.uart3_rxd */
+	{UART2_RTSN, (M1 | PIN_INPUT_SLEW)},	/* uart2_rtsn.uart3_txd */
+	{I2C1_SDA, (PIN_INPUT_PULLUP | M0)},	/* I2C1_SDA */
+	{I2C1_SCL, (PIN_INPUT_PULLUP | M0)},	/* I2C1_SCL */
+
+	/* BeagleBone AI: Debug UART */
+	{UART1_RXD, (M0 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},   /* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},  /* uart1_txd.uart1_txd */
+};
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+const struct pad_conf_entry emmc_padconf[] = {
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},		    /*  K7: gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},		    /*  M7: gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},		    /*  J5: gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},		    /*  K6: gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},		    /*  J7: gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},		    /*  J4: gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},		    /*  J6: gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},		    /*  H4: gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},		    /*  H5: gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},		    /*  H6: gpmc_cs1.mmc2_cmd */
+	{MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)},	       /* F13: eMMC_RSTn (missing on schematic): mcasp1_axr5.gpio5_7 */
+};
+#endif
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = {
+	{0x0114, 2980, 0},	/* CFG_GPMC_A0_IN */
+	{0x0120, 2648, 0},	/* CFG_GPMC_A10_IN */
+	{0x012C, 2918, 0},	/* CFG_GPMC_A11_IN */
+	{0x0198, 2917, 0},	/* CFG_GPMC_A1_IN */
+	{0x0204, 3156, 178},	/* CFG_GPMC_A2_IN */
+	{0x0210, 3109, 246},	/* CFG_GPMC_A3_IN */
+	{0x021C, 3142, 100},	/* CFG_GPMC_A4_IN */
+	{0x0228, 3084, 33},	/* CFG_GPMC_A5_IN */
+	{0x0234, 2778, 0},	/* CFG_GPMC_A6_IN */
+	{0x0240, 3110, 0},	/* CFG_GPMC_A7_IN */
+	{0x024C, 2874, 0},	/* CFG_GPMC_A8_IN */
+	{0x0258, 3072, 0},	/* CFG_GPMC_A9_IN */
+	{0x0264, 2466, 0},	/* CFG_GPMC_AD0_IN */
+	{0x0270, 2523, 0},	/* CFG_GPMC_AD10_IN */
+	{0x027C, 2453, 0},	/* CFG_GPMC_AD11_IN */
+	{0x0288, 2285, 0},	/* CFG_GPMC_AD12_IN */
+	{0x0294, 2206, 0},	/* CFG_GPMC_AD13_IN */
+	{0x02A0, 1898, 0},	/* CFG_GPMC_AD14_IN */
+	{0x02AC, 2473, 0},	/* CFG_GPMC_AD15_IN */
+	{0x02B8, 2307, 0},	/* CFG_GPMC_AD1_IN */
+	{0x02C4, 2691, 0},	/* CFG_GPMC_AD2_IN */
+	{0x02D0, 2384, 0},	/* CFG_GPMC_AD3_IN */
+	{0x02DC, 2462, 0},	/* CFG_GPMC_AD4_IN */
+	{0x02E8, 2335, 0},	/* CFG_GPMC_AD5_IN */
+	{0x02F4, 2370, 0},	/* CFG_GPMC_AD6_IN */
+	{0x0300, 2389, 0},	/* CFG_GPMC_AD7_IN */
+	{0x030C, 2672, 0},	/* CFG_GPMC_AD8_IN */
+	{0x0318, 2334, 0},	/* CFG_GPMC_AD9_IN */
+	{0x0378, 0, 0},	/* CFG_GPMC_CS3_IN */
+	{0x0678, 406, 0},	/* CFG_MMC3_CLK_IN */
+	{0x0680, 659, 0},	/* CFG_MMC3_CLK_OUT */
+	{0x0684, 0, 0},	/* CFG_MMC3_CMD_IN */
+	{0x0688, 0, 0},	/* CFG_MMC3_CMD_OEN */
+	{0x068C, 0, 0},	/* CFG_MMC3_CMD_OUT */
+	{0x0690, 130, 0},	/* CFG_MMC3_DAT0_IN */
+	{0x0694, 0, 0},	/* CFG_MMC3_DAT0_OEN */
+	{0x0698, 0, 0},	/* CFG_MMC3_DAT0_OUT */
+	{0x069C, 169, 0},	/* CFG_MMC3_DAT1_IN */
+	{0x06A0, 0, 0},	/* CFG_MMC3_DAT1_OEN */
+	{0x06A4, 0, 0},	/* CFG_MMC3_DAT1_OUT */
+	{0x06A8, 0, 0},	/* CFG_MMC3_DAT2_IN */
+	{0x06AC, 0, 0},	/* CFG_MMC3_DAT2_OEN */
+	{0x06B0, 0, 0},	/* CFG_MMC3_DAT2_OUT */
+	{0x06B4, 457, 0},	/* CFG_MMC3_DAT3_IN */
+	{0x06B8, 0, 0},	/* CFG_MMC3_DAT3_OEN */
+	{0x06BC, 0, 0},	/* CFG_MMC3_DAT3_OUT */
+	{0x06C0, 702, 0},	/* CFG_MMC3_DAT4_IN */
+	{0x06C4, 0, 0},	/* CFG_MMC3_DAT4_OEN */
+	{0x06C8, 0, 0},	/* CFG_MMC3_DAT4_OUT */
+	{0x06CC, 738, 0},	/* CFG_MMC3_DAT5_IN */
+	{0x06D0, 0, 0},	/* CFG_MMC3_DAT5_OEN */
+	{0x06D4, 0, 0},	/* CFG_MMC3_DAT5_OUT */
+	{0x06D8, 856, 0},	/* CFG_MMC3_DAT6_IN */
+	{0x06DC, 0, 0},	/* CFG_MMC3_DAT6_OEN */
+	{0x06E0, 0, 0},	/* CFG_MMC3_DAT6_OUT */
+	{0x06E4, 610, 0},	/* CFG_MMC3_DAT7_IN */
+	{0x06E8, 0, 0},	/* CFG_MMC3_DAT7_OEN */
+	{0x06EC, 0, 0},	/* CFG_MMC3_DAT7_OUT */
+	{0x06F0, 480, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 111, 1641},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 272, 1116},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 243, 1260},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 0, 1614},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 105, 1673},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 531, 120},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 201, 60},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 229, 120},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 141, 0},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 495, 120},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 660, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 1551, 115},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 816, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 876, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 312, 0},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 58, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 0, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 702, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 136, 976},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 210, 1357},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 189, 1462},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 232, 1278},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1397},	/* CFG_VIN2A_D23_IN */
+};
+
+const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = {
+	{0x0114, 2519, 702},	/* CFG_GPMC_A0_IN */
+	{0x0120, 2435, 411},	/* CFG_GPMC_A10_IN */
+	{0x012C, 2379, 755},	/* CFG_GPMC_A11_IN */
+	{0x0198, 2384, 778},	/* CFG_GPMC_A1_IN */
+	{0x0204, 2499, 1127},	/* CFG_GPMC_A2_IN */
+	{0x0210, 2455, 1181},	/* CFG_GPMC_A3_IN */
+	{0x021C, 2486, 1039},	/* CFG_GPMC_A4_IN */
+	{0x0228, 2456, 938},	/* CFG_GPMC_A5_IN */
+	{0x0234, 2463, 573},	/* CFG_GPMC_A6_IN */
+	{0x0240, 2608, 783},	/* CFG_GPMC_A7_IN */
+	{0x024C, 2430, 656},	/* CFG_GPMC_A8_IN */
+	{0x0258, 2465, 850},	/* CFG_GPMC_A9_IN */
+	{0x0264, 2316, 301},	/* CFG_GPMC_AD0_IN */
+	{0x0270, 2324, 406},	/* CFG_GPMC_AD10_IN */
+	{0x027C, 2278, 352},	/* CFG_GPMC_AD11_IN */
+	{0x0288, 2297, 160},	/* CFG_GPMC_AD12_IN */
+	{0x0294, 2278, 108},	/* CFG_GPMC_AD13_IN */
+	{0x02A0, 2035, 0},	/* CFG_GPMC_AD14_IN */
+	{0x02AC, 2279, 378},	/* CFG_GPMC_AD15_IN */
+	{0x02B8, 2440, 70},	/* CFG_GPMC_AD1_IN */
+	{0x02C4, 2404, 446},	/* CFG_GPMC_AD2_IN */
+	{0x02D0, 2343, 212},	/* CFG_GPMC_AD3_IN */
+	{0x02DC, 2355, 322},	/* CFG_GPMC_AD4_IN */
+	{0x02E8, 2337, 192},	/* CFG_GPMC_AD5_IN */
+	{0x02F4, 2270, 314},	/* CFG_GPMC_AD6_IN */
+	{0x0300, 2339, 259},	/* CFG_GPMC_AD7_IN */
+	{0x030C, 2308, 577},	/* CFG_GPMC_AD8_IN */
+	{0x0318, 2334, 166},	/* CFG_GPMC_AD9_IN */
+	{0x0378, 0, 0},	/* CFG_GPMC_CS3_IN */
+	{0x0678, 0, 386},	/* CFG_MMC3_CLK_IN */
+	{0x0680, 605, 0},	/* CFG_MMC3_CLK_OUT */
+	{0x0684, 0, 0},	/* CFG_MMC3_CMD_IN */
+	{0x0688, 0, 0},	/* CFG_MMC3_CMD_OEN */
+	{0x068C, 0, 0},	/* CFG_MMC3_CMD_OUT */
+	{0x0690, 171, 0},	/* CFG_MMC3_DAT0_IN */
+	{0x0694, 0, 0},	/* CFG_MMC3_DAT0_OEN */
+	{0x0698, 0, 0},	/* CFG_MMC3_DAT0_OUT */
+	{0x069C, 221, 0},	/* CFG_MMC3_DAT1_IN */
+	{0x06A0, 0, 0},	/* CFG_MMC3_DAT1_OEN */
+	{0x06A4, 0, 0},	/* CFG_MMC3_DAT1_OUT */
+	{0x06A8, 0, 0},	/* CFG_MMC3_DAT2_IN */
+	{0x06AC, 0, 0},	/* CFG_MMC3_DAT2_OEN */
+	{0x06B0, 0, 0},	/* CFG_MMC3_DAT2_OUT */
+	{0x06B4, 474, 0},	/* CFG_MMC3_DAT3_IN */
+	{0x06B8, 0, 0},	/* CFG_MMC3_DAT3_OEN */
+	{0x06BC, 0, 0},	/* CFG_MMC3_DAT3_OUT */
+	{0x06C0, 792, 0},	/* CFG_MMC3_DAT4_IN */
+	{0x06C4, 0, 0},	/* CFG_MMC3_DAT4_OEN */
+	{0x06C8, 0, 0},	/* CFG_MMC3_DAT4_OUT */
+	{0x06CC, 782, 0},	/* CFG_MMC3_DAT5_IN */
+	{0x06D0, 0, 0},	/* CFG_MMC3_DAT5_OEN */
+	{0x06D4, 0, 0},	/* CFG_MMC3_DAT5_OUT */
+	{0x06D8, 942, 0},	/* CFG_MMC3_DAT6_IN */
+	{0x06DC, 0, 0},	/* CFG_MMC3_DAT6_OEN */
+	{0x06E0, 0, 0},	/* CFG_MMC3_DAT6_OUT */
+	{0x06E4, 636, 0},	/* CFG_MMC3_DAT7_IN */
+	{0x06E8, 0, 0},	/* CFG_MMC3_DAT7_OEN */
+	{0x06EC, 0, 0},	/* CFG_MMC3_DAT7_OUT */
+	{0x06F0, 260, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 0, 1412},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 123, 1047},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 139, 1081},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 195, 1100},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 239, 1216},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 89, 0},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 15, 125},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 339, 162},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 146, 94},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 27},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 291, 205},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 0, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 219, 101},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 92, 58},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 135, 100},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 154, 101},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 78, 27},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 411, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 0, 382},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 320, 750},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 192, 836},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 294, 669},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 50, 700},	/* CFG_VIN2A_D23_IN */
+	{0x0B9C, 0, 706},	/* CFG_VOUT1_CLK_OUT */
+	{0x0BA8, 2313, 0},	/* CFG_VOUT1_D0_OUT */
+	{0x0BB4, 2199, 0},	/* CFG_VOUT1_D10_OUT */
+	{0x0BC0, 2266, 0},	/* CFG_VOUT1_D11_OUT */
+	{0x0BCC, 3159, 0},	/* CFG_VOUT1_D12_OUT */
+	{0x0BD8, 2100, 0},	/* CFG_VOUT1_D13_OUT */
+	{0x0BE4, 2229, 0},	/* CFG_VOUT1_D14_OUT */
+	{0x0BF0, 2202, 0},	/* CFG_VOUT1_D15_OUT */
+	{0x0BFC, 2084, 0},	/* CFG_VOUT1_D16_OUT */
+	{0x0C08, 2195, 0},	/* CFG_VOUT1_D17_OUT */
+	{0x0C14, 2342, 0},	/* CFG_VOUT1_D18_OUT */
+	{0x0C20, 2463, 0},	/* CFG_VOUT1_D19_OUT */
+	{0x0C2C, 2439, 0},	/* CFG_VOUT1_D1_OUT */
+	{0x0C38, 2304, 0},	/* CFG_VOUT1_D20_OUT */
+	{0x0C44, 2103, 0},	/* CFG_VOUT1_D21_OUT */
+	{0x0C50, 2145, 0},	/* CFG_VOUT1_D22_OUT */
+	{0x0C5C, 1932, 0},	/* CFG_VOUT1_D23_OUT */
+	{0x0C68, 2200, 0},	/* CFG_VOUT1_D2_OUT */
+	{0x0C74, 2355, 0},	/* CFG_VOUT1_D3_OUT */
+	{0x0C80, 3215, 0},	/* CFG_VOUT1_D4_OUT */
+	{0x0C8C, 2314, 0},	/* CFG_VOUT1_D5_OUT */
+	{0x0C98, 2238, 0},	/* CFG_VOUT1_D6_OUT */
+	{0x0CA4, 2381, 0},	/* CFG_VOUT1_D7_OUT */
+	{0x0CB0, 2138, 0},	/* CFG_VOUT1_D8_OUT */
+	{0x0CBC, 2383, 0},	/* CFG_VOUT1_D9_OUT */
+	{0x0CC8, 1984, 0},	/* CFG_VOUT1_DE_OUT */
+	{0x0CE0, 1947, 0},	/* CFG_VOUT1_HSYNC_OUT */
+	{0x0CEC, 2739, 0},	/* CFG_VOUT1_VSYNC_OUT */
+};
+
+const struct iodelay_cfg_entry iodelay_cfg_array_am574x_idk[] = {
+	{0x0114, 2199, 621},	/* CFG_GPMC_A0_IN */
+	{0x0120, 0, 0},	/* CFG_GPMC_A10_IN */
+	{0x012C, 2133, 859},	/* CFG_GPMC_A11_IN */
+	{0x0138, 2258, 562},	/* CFG_GPMC_A12_IN */
+	{0x0144, 0, 0},	/* CFG_GPMC_A13_IN */
+	{0x0150, 2149, 1052},	/* CFG_GPMC_A14_IN */
+	{0x015C, 2121, 997},	/* CFG_GPMC_A15_IN */
+	{0x0168, 2159, 1134},	/* CFG_GPMC_A16_IN */
+	{0x0170, 0, 0},	/* CFG_GPMC_A16_OUT */
+	{0x0174, 2135, 1085},	/* CFG_GPMC_A17_IN */
+	{0x0188, 0, 0},	/* CFG_GPMC_A18_OUT */
+	{0x0198, 1989, 612},	/* CFG_GPMC_A1_IN */
+	{0x0204, 2218, 912},	/* CFG_GPMC_A2_IN */
+	{0x0210, 2168, 963},	/* CFG_GPMC_A3_IN */
+	{0x021C, 2196, 813},	/* CFG_GPMC_A4_IN */
+	{0x0228, 2082, 782},	/* CFG_GPMC_A5_IN */
+	{0x0234, 2098, 407},	/* CFG_GPMC_A6_IN */
+	{0x0240, 2343, 585},	/* CFG_GPMC_A7_IN */
+	{0x024C, 2030, 685},	/* CFG_GPMC_A8_IN */
+	{0x0258, 2116, 832},	/* CFG_GPMC_A9_IN */
+	{0x0374, 0, 0},	/* CFG_GPMC_CS2_OUT */
+	{0x0590, 1000, 3900},	/* CFG_MCASP5_ACLKX_OUT */
+	{0x05AC, 1000, 3800},	/* CFG_MCASP5_FSX_IN */
+	{0x06F0, 451, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 127, 1571},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 165, 1178},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 136, 1302},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 0, 1520},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 28, 1690},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 121, 0},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 60, 0},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 153, 0},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 35, 0},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 0},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 172, 0},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 147, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 110, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 18, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 82, 0},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 33, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 0, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 417, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 156, 843},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 223, 1413},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 169, 1415},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 43, 1150},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1210},	/* CFG_VIN2A_D23_IN */
+	{0x0B30, 0, 200},	/* CFG_VIN2A_D5_OUT */
+	{0x0B9C, 1281, 497},	/* CFG_VOUT1_CLK_OUT */
+	{0x0BA8, 379, 0},	/* CFG_VOUT1_D0_OUT */
+	{0x0BB4, 441, 0},	/* CFG_VOUT1_D10_OUT */
+	{0x0BC0, 461, 0},	/* CFG_VOUT1_D11_OUT */
+	{0x0BCC, 1189, 0},	/* CFG_VOUT1_D12_OUT */
+	{0x0BD8, 312, 0},	/* CFG_VOUT1_D13_OUT */
+	{0x0BE4, 298, 0},	/* CFG_VOUT1_D14_OUT */
+	{0x0BF0, 284, 0},	/* CFG_VOUT1_D15_OUT */
+	{0x0BFC, 152, 0},	/* CFG_VOUT1_D16_OUT */
+	{0x0C08, 216, 0},	/* CFG_VOUT1_D17_OUT */
+	{0x0C14, 408, 0},	/* CFG_VOUT1_D18_OUT */
+	{0x0C20, 519, 0},	/* CFG_VOUT1_D19_OUT */
+	{0x0C2C, 475, 0},	/* CFG_VOUT1_D1_OUT */
+	{0x0C38, 316, 0},	/* CFG_VOUT1_D20_OUT */
+	{0x0C44, 59, 0},	/* CFG_VOUT1_D21_OUT */
+	{0x0C50, 221, 0},	/* CFG_VOUT1_D22_OUT */
+	{0x0C5C, 96, 0},	/* CFG_VOUT1_D23_OUT */
+	{0x0C68, 264, 0},	/* CFG_VOUT1_D2_OUT */
+	{0x0C74, 421, 0},	/* CFG_VOUT1_D3_OUT */
+	{0x0C80, 1257, 0},	/* CFG_VOUT1_D4_OUT */
+	{0x0C8C, 432, 0},	/* CFG_VOUT1_D5_OUT */
+	{0x0C98, 436, 0},	/* CFG_VOUT1_D6_OUT */
+	{0x0CA4, 440, 0},	/* CFG_VOUT1_D7_OUT */
+	{0x0CB0, 81, 100},	/* CFG_VOUT1_D8_OUT */
+	{0x0CBC, 471, 0},	/* CFG_VOUT1_D9_OUT */
+	{0x0CC8, 0, 0},	/* CFG_VOUT1_DE_OUT */
+	{0x0CE0, 0, 0},	/* CFG_VOUT1_HSYNC_OUT */
+	{0x0CEC, 815, 0},	/* CFG_VOUT1_VSYNC_OUT */
+};
+
+const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
+	{0x0114, 1861, 901},	/* CFG_GPMC_A0_IN */
+	{0x0120, 0, 0},	/* CFG_GPMC_A10_IN */
+	{0x012C, 1783, 1178},	/* CFG_GPMC_A11_IN */
+	{0x0138, 1903, 853},	/* CFG_GPMC_A12_IN */
+	{0x0144, 0, 0},	/* CFG_GPMC_A13_IN */
+	{0x0150, 2575, 966},	/* CFG_GPMC_A14_IN */
+	{0x015C, 2503, 889},	/* CFG_GPMC_A15_IN */
+	{0x0168, 2528, 1007},	/* CFG_GPMC_A16_IN */
+	{0x0170, 0, 0},	/* CFG_GPMC_A16_OUT */
+	{0x0174, 2533, 980},	/* CFG_GPMC_A17_IN */
+	{0x0188, 590, 0},	/* CFG_GPMC_A18_OUT */
+	{0x0198, 1652, 891},	/* CFG_GPMC_A1_IN */
+	{0x0204, 1888, 1212},	/* CFG_GPMC_A2_IN */
+	{0x0210, 1839, 1274},	/* CFG_GPMC_A3_IN */
+	{0x021C, 1868, 1113},	/* CFG_GPMC_A4_IN */
+	{0x0228, 1757, 1079},	/* CFG_GPMC_A5_IN */
+	{0x0234, 1800, 670},	/* CFG_GPMC_A6_IN */
+	{0x0240, 1967, 898},	/* CFG_GPMC_A7_IN */
+	{0x024C, 1731, 959},	/* CFG_GPMC_A8_IN */
+	{0x0258, 1766, 1150},	/* CFG_GPMC_A9_IN */
+	{0x0374, 0, 0},	/* CFG_GPMC_CS2_OUT */
+	{0x0590, 1000, 4200},	/* CFG_MCASP5_ACLKX_OUT */
+	{0x05AC, 800, 3800},	/* CFG_MCASP5_FSX_IN */
+	{0x06F0, 260, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 0, 1412},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 123, 1047},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 139, 1081},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 195, 1100},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 239, 1216},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 89, 0},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 15, 125},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 339, 162},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 146, 94},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 27},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 291, 205},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 0, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 219, 101},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 92, 58},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 135, 100},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 154, 101},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 78, 27},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 411, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 0, 382},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 320, 750},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 192, 836},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 294, 669},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 50, 700},	/* CFG_VIN2A_D23_IN */
+	{0x0B30, 0, 0},	/* CFG_VIN2A_D5_OUT */
+	{0x0B9C, 1126, 751},	/* CFG_VOUT1_CLK_OUT */
+	{0x0BA8, 395, 0},	/* CFG_VOUT1_D0_OUT */
+	{0x0BB4, 282, 0},	/* CFG_VOUT1_D10_OUT */
+	{0x0BC0, 348, 0},	/* CFG_VOUT1_D11_OUT */
+	{0x0BCC, 1240, 0},	/* CFG_VOUT1_D12_OUT */
+	{0x0BD8, 182, 0},	/* CFG_VOUT1_D13_OUT */
+	{0x0BE4, 311, 0},	/* CFG_VOUT1_D14_OUT */
+	{0x0BF0, 285, 0},	/* CFG_VOUT1_D15_OUT */
+	{0x0BFC, 166, 0},	/* CFG_VOUT1_D16_OUT */
+	{0x0C08, 278, 0},	/* CFG_VOUT1_D17_OUT */
+	{0x0C14, 425, 0},	/* CFG_VOUT1_D18_OUT */
+	{0x0C20, 516, 0},	/* CFG_VOUT1_D19_OUT */
+	{0x0C2C, 521, 0},	/* CFG_VOUT1_D1_OUT */
+	{0x0C38, 386, 0},	/* CFG_VOUT1_D20_OUT */
+	{0x0C44, 111, 0},	/* CFG_VOUT1_D21_OUT */
+	{0x0C50, 227, 0},	/* CFG_VOUT1_D22_OUT */
+	{0x0C5C, 0, 0},	/* CFG_VOUT1_D23_OUT */
+	{0x0C68, 282, 0},	/* CFG_VOUT1_D2_OUT */
+	{0x0C74, 438, 0},	/* CFG_VOUT1_D3_OUT */
+	{0x0C80, 1298, 0},	/* CFG_VOUT1_D4_OUT */
+	{0x0C8C, 397, 0},	/* CFG_VOUT1_D5_OUT */
+	{0x0C98, 321, 0},	/* CFG_VOUT1_D6_OUT */
+	{0x0CA4, 155, 309},	/* CFG_VOUT1_D7_OUT */
+	{0x0CB0, 212, 0},	/* CFG_VOUT1_D8_OUT */
+	{0x0CBC, 466, 0},	/* CFG_VOUT1_D9_OUT */
+	{0x0CC8, 0, 0},	/* CFG_VOUT1_DE_OUT */
+	{0x0CE0, 0, 0},	/* CFG_VOUT1_HSYNC_OUT */
+	{0x0CEC, 139, 701},	/* CFG_VOUT1_VSYNC_OUT */
+};
+
+const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = {
+	{0x0114, 1873, 702},	/* CFG_GPMC_A0_IN */
+	{0x0120, 0, 0},	/* CFG_GPMC_A10_IN */
+	{0x012C, 1851, 1011},	/* CFG_GPMC_A11_IN */
+	{0x0138, 2009, 601},	/* CFG_GPMC_A12_IN */
+	{0x0144, 0, 0},	/* CFG_GPMC_A13_IN */
+	{0x0150, 2247, 1186},	/* CFG_GPMC_A14_IN */
+	{0x015C, 2176, 1197},	/* CFG_GPMC_A15_IN */
+	{0x0168, 2229, 1268},	/* CFG_GPMC_A16_IN */
+	{0x0170, 0, 0},	/* CFG_GPMC_A16_OUT */
+	{0x0174, 2251, 1217},	/* CFG_GPMC_A17_IN */
+	{0x0188, 0, 0},	/* CFG_GPMC_A18_OUT */
+	{0x0198, 1629, 772},	/* CFG_GPMC_A1_IN */
+	{0x0204, 1734, 898},	/* CFG_GPMC_A2_IN */
+	{0x0210, 1757, 1076},	/* CFG_GPMC_A3_IN */
+	{0x021C, 1794, 893},	/* CFG_GPMC_A4_IN */
+	{0x0228, 1726, 853},	/* CFG_GPMC_A5_IN */
+	{0x0234, 1792, 612},	/* CFG_GPMC_A6_IN */
+	{0x0240, 2117, 610},	/* CFG_GPMC_A7_IN */
+	{0x024C, 1758, 653},	/* CFG_GPMC_A8_IN */
+	{0x0258, 1705, 899},	/* CFG_GPMC_A9_IN */
+	{0x0374, 0, 0},	/* CFG_GPMC_CS2_OUT */
+	{0x06F0, 413, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 27, 2296},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 3, 1721},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 134, 1786},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 40, 1966},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 0, 2057},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 0, 60},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 0, 60},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 0, 60},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 0, 0},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 60},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 0, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 0, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 170, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 150, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 0, 0},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 60, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 60, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 530, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 71, 1099},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 142, 1337},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 114, 1517},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 171, 1331},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1328},	/* CFG_VIN2A_D23_IN */
+};
+
+const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk_4port[] = {
+	{0x0588, 2100, 1959},	/* CFG_MCASP5_ACLKX_IN */
+	{0x05AC, 2100, 1780},	/* CFG_MCASP5_FSX_IN */
+	{0x0B30, 0, 400},	/* CFG_VIN2A_D5_OUT */
+};
+#endif
+#endif /* _MUX_DATA_BEAGLE_X15_H_ */
diff --git a/roms/u-boot/board/ti/am64x/Kconfig b/roms/u-boot/board/ti/am64x/Kconfig
new file mode 100644
index 000000000..d4ec759d7
--- /dev/null
+++ b/roms/u-boot/board/ti/am64x/Kconfig
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+
+choice
+	prompt "K3 AM64 based boards"
+	optional
+
+config TARGET_AM642_A53_EVM
+	bool "TI K3 based AM642 EVM running on A53"
+	select ARM64
+	select SOC_K3_AM642
+	imply BOARD
+	imply SPL_BOARD
+	imply TI_I2C_BOARD_DETECT
+
+config TARGET_AM642_R5_EVM
+	bool "TI K3 based AM642 EVM running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select K3_LOAD_SYSFW
+	select SOC_K3_AM642
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	imply SYS_K3_SPL_ATF
+	imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+if TARGET_AM642_A53_EVM
+
+config SYS_BOARD
+       default "am64x"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "am64x_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_AM642_R5_EVM
+
+config SYS_BOARD
+       default "am64x"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "am64x_evm"
+
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/ti/am64x/MAINTAINERS b/roms/u-boot/board/ti/am64x/MAINTAINERS
new file mode 100644
index 000000000..d384a330d
--- /dev/null
+++ b/roms/u-boot/board/ti/am64x/MAINTAINERS
@@ -0,0 +1,8 @@
+AM64x BOARD
+M:	Dave Gerlach <d-gerlach@ti.com>
+M:	Lokesh Vutla <lokeshvutla@ti.com>
+S:	Maintained
+F:	board/ti/am64x/
+F:	include/configs/am64x_evm.h
+F:	configs/am64x_evm_r5_defconfig
+F:	configs/am64x_evm_a53_defconfig
diff --git a/roms/u-boot/board/ti/am64x/Makefile b/roms/u-boot/board/ti/am64x/Makefile
new file mode 100644
index 000000000..8b98e6f5f
--- /dev/null
+++ b/roms/u-boot/board/ti/am64x/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+#	Keerthy <j-keerthy@ti.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evm.o
diff --git a/roms/u-boot/board/ti/am64x/evm.c b/roms/u-boot/board/ti/am64x/evm.c
new file mode 100644
index 000000000..35cd9e027
--- /dev/null
+++ b/roms/u-boot/board/ti/am64x/evm.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for AM642 EVM
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ *	Keerthy <j-keerthy@ti.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <env.h>
+
+#include "../common/board_detect.h"
+
+#define board_is_am64x_gpevm()	board_ti_k3_is("AM64-GPEVM")
+#define board_is_am64x_skevm()	board_ti_k3_is("AM64-SKEVM")
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = 0x80000000;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	/* Bank 0 declares the memory available in the DDR low region */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = 0x80000000;
+	gd->ram_size = 0x80000000;
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	bool eeprom_read = board_ti_was_eeprom_read();
+
+	if (!eeprom_read || board_is_am64x_gpevm()) {
+		if (!strcmp(name, "k3-am642-r5-evm") || !strcmp(name, "k3-am642-evm"))
+			return 0;
+	} else if (board_is_am64x_skevm()) {
+		if (!strcmp(name, "k3-am642-r5-sk") || !strcmp(name, "k3-am642-sk"))
+			return 0;
+	}
+
+	return -1;
+}
+#endif
+
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+int do_board_detect(void)
+{
+	int ret;
+
+	ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+					 CONFIG_EEPROM_CHIP_ADDRESS);
+	if (ret) {
+		printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n",
+			CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1);
+		ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+						 CONFIG_EEPROM_CHIP_ADDRESS + 1);
+		if (ret)
+			pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+			       CONFIG_EEPROM_CHIP_ADDRESS + 1, ret);
+	}
+
+	return ret;
+}
+
+int checkboard(void)
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+	if (!do_board_detect())
+		printf("Board: %s rev %s\n", ep->name, ep->version);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+static void setup_board_eeprom_env(void)
+{
+	char *name = "am64x_gpevm";
+
+	if (do_board_detect())
+		goto invalid_eeprom;
+
+	if (board_is_am64x_gpevm())
+		name = "am64x_gpevm";
+	else if (board_is_am64x_skevm())
+		name = "am64x_skevm";
+	else
+		printf("Unidentified board claims %s in eeprom header\n",
+		       board_ti_get_name());
+
+invalid_eeprom:
+	set_board_info_env_am6(name);
+}
+
+static void setup_serial(void)
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+	unsigned long board_serial;
+	char *endp;
+	char serial_string[17] = { 0 };
+
+	if (env_get("serial#"))
+		return;
+
+	board_serial = simple_strtoul(ep->serial, &endp, 16);
+	if (*endp != '\0') {
+		pr_err("Error: Can't set serial# to %s\n", ep->serial);
+		return;
+	}
+
+	snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
+	env_set("serial#", serial_string);
+}
+#endif
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
+		struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+		setup_board_eeprom_env();
+		setup_serial();
+		/*
+		 * The first MAC address for ethernet a.k.a. ethernet0 comes from
+		 * efuse populated via the am654 gigabit eth switch subsystem driver.
+		 * All the other ones are populated via EEPROM, hence continue with
+		 * an index of 1.
+		 */
+		board_ti_am6_set_ethaddr(1, ep->mac_addr_cnt);
+	}
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/ti/am65x/Kconfig b/roms/u-boot/board/ti/am65x/Kconfig
new file mode 100644
index 000000000..47b41cd6a
--- /dev/null
+++ b/roms/u-boot/board/ti/am65x/Kconfig
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+#	Lokesh Vutla <lokeshvutla@ti.com>
+
+choice
+	prompt "K3 AM65 based boards"
+	optional
+
+config TARGET_AM654_A53_EVM
+	bool "TI K3 based AM654 EVM running on A53"
+	select ARM64
+	select SOC_K3_AM6
+	select SYS_DISABLE_DCACHE_OPS
+	select BOARD_LATE_INIT
+	imply TI_I2C_BOARD_DETECT
+
+config TARGET_AM654_R5_EVM
+	bool "TI K3 based AM654 EVM running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select SOC_K3_AM6
+	select K3_LOAD_SYSFW
+	select K3_AM654_DDRSS
+	imply SYS_K3_SPL_ATF
+	imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+if TARGET_AM654_A53_EVM
+
+config SYS_BOARD
+       default "am65x"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "am65x_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_AM654_R5_EVM
+
+config SYS_BOARD
+       default "am65x"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "am65x_evm"
+
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/ti/am65x/MAINTAINERS b/roms/u-boot/board/ti/am65x/MAINTAINERS
new file mode 100644
index 000000000..6da4182d9
--- /dev/null
+++ b/roms/u-boot/board/ti/am65x/MAINTAINERS
@@ -0,0 +1,9 @@
+AM65x BOARD
+M:	Lokesh Vutla <lokeshvutla@ti.com>
+S:	Maintained
+F:	board/ti/am65x/
+F:	include/configs/am65x_evm.h
+F:	configs/am65x_evm_a53_defconfig
+F:	configs/am65x_evm_r5_defconfig
+F:	configs/am65x_evm_r5_usbdfu_defconfig
+F:	configs/am65x_evm_r5_usbmsc_defconfig
diff --git a/roms/u-boot/board/ti/am65x/Makefile b/roms/u-boot/board/ti/am65x/Makefile
new file mode 100644
index 000000000..94dddfcc4
--- /dev/null
+++ b/roms/u-boot/board/ti/am65x/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+#	Lokesh Vutla <lokeshvutla@ti.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := evm.o
diff --git a/roms/u-boot/board/ti/am65x/README b/roms/u-boot/board/ti/am65x/README
new file mode 100644
index 000000000..67081ce34
--- /dev/null
+++ b/roms/u-boot/board/ti/am65x/README
@@ -0,0 +1,350 @@
+Introduction:
+-------------
+The AM65x family of SoCs is the first device family from K3 Multicore
+SoC architecture, targeted for broad market and industrial control with
+aim to meet the complex processing needs of modern embedded products.
+
+The device is built over three domains, each containing specific processing
+cores, voltage domains and peripherals:
+1. Wake-up (WKUP) domain:
+	- Device Management and Security Controller (DMSC)
+2. Microcontroller (MCU) domain:
+	- Dual Core ARM Cortex-R5F processor
+3. MAIN domain:
+	- Quad core 64-bit ARM Cortex-A53
+
+More info can be found in TRM: http://www.ti.com/lit/pdf/spruid7
+
+Boot Flow:
+----------
+On AM65x family devices, ROM supports boot only via MCU(R5). This means that
+bootloader has to run on R5 core. In order to meet this constraint, and for
+the following reasons the boot flow is designed as mentioned:
+1. Need to move away from R5 asap, so that we want to start *any*
+firmware on the r5 cores like.... autosar can be loaded to receive CAN
+response and other safety operations to be started. This operation is
+very time critical and is applicable for all automotive use cases.
+2. U-Boot on A53 should start other remotecores for various
+applications. This should happen before running Linux.
+3. In production boot flow, we might not like to use full u-boot,
+instead use Flacon boot flow to reduce boot time.
+
++------------------------------------------------------------------------+
+|        DMSC            |         R5            |        A53            |
++------------------------------------------------------------------------+
+|    +--------+          |                       |                       |
+|    |  Reset |          |                       |                       |
+|    +--------+          |                       |                       |
+|         :              |                       |                       |
+|    +--------+          |   +-----------+       |                       |
+|    | *ROM*  |----------|-->| Reset rls |       |                       |
+|    +--------+          |   +-----------+       |                       |
+|    |        |          |         :             |                       |
+|    |  ROM   |          |         :             |                       |
+|    |services|          |         :             |                       |
+|    |        |          |   +-------------+     |                       |
+|    |        |          |   |  *R5 ROM*   |     |                       |
+|    |        |          |   +-------------+     |                       |
+|    |        |<---------|---|Load and auth|     |                       |
+|    |        |          |   | tiboot3.bin |     |                       |
+|    |        |          |   +-------------+     |                       |
+|    |        |          |         :             |                       |
+|    |        |          |         :             |                       |
+|    |        |          |         :             |                       |
+|    |        |          |   +-------------+     |                       |
+|    |        |          |   |  *R5 SPL*   |     |                       |
+|    |        |          |   +-------------+     |                       |
+|    |        |          |   |    Load     |     |                       |
+|    |        |          |   |  sysfw.itb  |     |                       |
+|    | Start  |          |   +-------------+     |                       |
+|    | System |<---------|---|    Start    |     |                       |
+|    |Firmware|          |   |    SYSFW    |     |                       |
+|    +--------+          |   +-------------+     |                       |
+|        :               |   |             |     |                       |
+|    +---------+         |   |   Load      |     |                       |
+|    | *SYSFW* |         |   |   system    |     |                       |
+|    +---------+         |   | Config data |     |                       |
+|    |         |<--------|---|             |     |                       |
+|    |         |         |   +-------------+     |                       |
+|    |         |         |   |             |     |                       |
+|    |         |         |   |    DDR      |     |                       |
+|    |         |         |   |   config    |     |                       |
+|    |         |         |   +-------------+     |                       |
+|    |         |         |   |             |     |                       |
+|    |         |<--------|---| Start A53   |     |                       |
+|    |         |         |   |  and Reset  |     |                       |
+|    |         |         |   +-------------+     |                       |
+|    |         |         |                       |     +-----------+     |
+|    |         |---------|-----------------------|---->| Reset rls |     |
+|    |         |         |                       |     +-----------+     |
+|    |  DMSC   |         |                       |          :            |
+|    |Services |         |                       |     +-----------+     |
+|    |         |<--------|-----------------------|---->|*ATF/OPTEE*|     |
+|    |         |         |                       |     +-----------+     |
+|    |         |         |                       |          :            |
+|    |         |         |                       |     +-----------+     |
+|    |         |<--------|-----------------------|---->| *A53 SPL* |     |
+|    |         |         |                       |     +-----------+     |
+|    |         |         |                       |     |   Load    |     |
+|    |         |         |                       |     | u-boot.img|     |
+|    |         |         |                       |     +-----------+     |
+|    |         |         |                       |          :            |
+|    |         |         |                       |     +-----------+     |
+|    |         |<--------|-----------------------|---->| *U-Boot*  |     |
+|    |         |         |                       |     +-----------+     |
+|    |         |         |                       |     |  prompt   |     |
+|    |         |         |                       |     +-----------+     |
+|    +---------+         |                       |                       |
+|                        |                       |                       |
++------------------------------------------------------------------------+
+
+- Here DMSC acts as master and provides all the critical services. R5/A53
+requests DMSC to get these services done as shown in the above diagram.
+
+Sources:
+--------
+1. SYSFW:
+	Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git
+	Branch: master
+
+2. ATF:
+	Tree: https://github.com/ARM-software/arm-trusted-firmware.git
+	Branch: master
+
+3. OPTEE:
+	Tree: https://github.com/OP-TEE/optee_os.git
+	Branch: master
+
+4. U-Boot:
+	Tree: http://git.denx.de/u-boot.git
+	Branch: master
+
+Build procedure:
+----------------
+1. SYSFW:
+$ make CROSS_COMPILE=arm-linux-gnueabihf-
+
+2. ATF:
+$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed
+
+3. OPTEE:
+$ make PLATFORM=k3-am65x CFG_ARM64_core=y
+
+4. U-Boot:
+
+4.1. R5:
+$ make CROSS_COMPILE=arm-linux-gnueabihf- am65x_evm_r5_defconfig O=/tmp/r5
+$ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
+
+4.2. A53:
+$ make CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig O=/tmp/a53
+$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a53
+
+Target Images
+--------------
+Copy the below images to an SD card and boot:
+- sysfw.itb from step 1
+- tiboot3.bin from step 4.1
+- tispl.bin, u-boot.img from 4.2
+
+Image formats:
+--------------
+
+- tiboot3.bin:
+                +-----------------------+
+                |        X.509          |
+                |      Certificate      |
+                | +-------------------+ |
+                | |                   | |
+                | |        R5         | |
+                | |   u-boot-spl.bin  | |
+                | |                   | |
+                | +-------------------+ |
+                | |                   | |
+                | |     FIT header    | |
+                | | +---------------+ | |
+                | | |               | | |
+                | | |   DTB 1...N   | | |
+                | | +---------------+ | |
+                | +-------------------+ |
+                +-----------------------+
+
+- tispl.bin
+                +-----------------------+
+                |                       |
+                |       FIT HEADER      |
+                | +-------------------+ |
+                | |                   | |
+                | |      A53 ATF      | |
+                | +-------------------+ |
+                | |                   | |
+                | |     A53 OPTEE     | |
+                | +-------------------+ |
+                | |                   | |
+                | |      A53 SPL      | |
+                | +-------------------+ |
+                | |                   | |
+                | |   SPL DTB 1...N   | |
+                | +-------------------+ |
+                +-----------------------+
+
+- sysfw.itb
+                +-----------------------+
+                |                       |
+                |       FIT HEADER      |
+                | +-------------------+ |
+                | |                   | |
+                | |     sysfw.bin     | |
+                | +-------------------+ |
+                | |                   | |
+                | |    board config   | |
+                | +-------------------+ |
+                | |                   | |
+                | |     PM config     | |
+                | +-------------------+ |
+                | |                   | |
+                | |     RM config     | |
+                | +-------------------+ |
+                | |                   | |
+                | |    Secure config  | |
+                | +-------------------+ |
+                +-----------------------+
+
+eMMC:
+-----
+ROM supports booting from eMMC from boot0 partition offset 0x0
+
+Flashing images to eMMC:
+
+The following commands can be used to download tiboot3.bin, tispl.bin,
+u-boot.img, and sysfw.itb from an SD card and write them to the eMMC boot0
+partition at respective addresses.
+
+=> mmc dev 0 1
+=> fatload mmc 1 ${loadaddr} tiboot3.bin
+=> mmc write ${loadaddr} 0x0 0x400
+=> fatload mmc 1 ${loadaddr} tispl.bin
+=> mmc write ${loadaddr} 0x400 0x1000
+=> fatload mmc 1 ${loadaddr} u-boot.img
+=> mmc write ${loadaddr} 0x1400 0x2000
+=> fatload mmc 1 ${loadaddr} sysfw.itb
+=> mmc write ${loadaddr} 0x3600 0x800
+
+To give the ROM access to the boot partition, the following commands must be
+used for the first time:
+=> mmc partconf 0 1 1 1
+=> mmc bootbus 0 1 0 0
+
+To create a software partition for the rootfs, the following command can be
+used:
+=> gpt write mmc 0 ${partitions}
+
+eMMC layout:
+
+           boot0 partition (8 MB)                        user partition
+   0x0+----------------------------------+      0x0+-------------------------+
+      |     tiboot3.bin (512 KB)         |         |                         |
+ 0x400+----------------------------------+         |                         |
+      |       tispl.bin (2 MB)           |         |                         |
+0x1400+----------------------------------+         |        rootfs           |
+      |       u-boot.img (4 MB)          |         |                         |
+0x3400+----------------------------------+         |                         |
+      |      environment (128 KB)        |         |                         |
+0x3500+----------------------------------+         |                         |
+      |   backup environment (128 KB)    |         |                         |
+0x3600+----------------------------------+         |                         |
+      |          sysfw (1 MB)            |         |                         |
+0x3E00+----------------------------------+         +-------------------------+
+
+Kernel image and DT are expected to be present in the /boot folder of rootfs.
+To boot kernel from eMMC, use the following commands:
+=> setenv mmcdev 0
+=> setenv bootpart 0
+=> boot
+
+OSPI:
+-----
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
+and sysfw.itb over tftp and then flash those to OSPI at their respective
+addresses.
+
+=> sf probe
+=> tftp ${loadaddr} tiboot3.bin
+=> sf update $loadaddr 0x0 $filesize
+=> tftp ${loadaddr} tispl.bin
+=> sf update $loadaddr 0x80000 $filesize
+=> tftp ${loadaddr} u-boot.img
+=> sf update $loadaddr 0x280000 $filesize
+=> tftp ${loadaddr} sysfw.itb
+=> sf update $loadaddr 0x6C0000 $filesize
+
+Flash layout for OSPI:
+
+         0x0 +----------------------------+
+             |     ospi.tiboot3(512K)     |
+             |                            |
+     0x80000 +----------------------------+
+             |     ospi.tispl(2M)         |
+             |                            |
+    0x280000 +----------------------------+
+             |     ospi.u-boot(4M)        |
+             |                            |
+    0x680000 +----------------------------+
+             |     ospi.env(128K)         |
+             |                            |
+    0x6A0000 +----------------------------+
+	     |	 ospi.env.backup (128K)   |
+	     |                            |
+    0x6C0000 +----------------------------+
+             |      ospi.sysfw(1M)        |
+             |                            |
+    0x7C0000 +----------------------------+
+	     |      padding (256k)        |
+    0x800000 +----------------------------+
+             |     ospi.rootfs(UBIFS)     |
+             |                            |
+             +----------------------------+
+
+Kernel Image and DT are expected to be present in the /boot folder of UBIFS
+ospi.rootfs just like in SD card case. U-Boot looks for UBI volume named
+"rootfs" for rootfs.
+
+To boot kernel from OSPI, at the U-Boot prompt:
+=> setenv boot ubi
+=> boot
+
+UART:
+-----
+ROM supports booting from MCU_UART0 via X-Modem protocol. The entire UART-based
+boot process up to U-Boot (proper) prompt goes through different stages and uses
+different UART peripherals as follows:
+
+  WHO     | Loading WHAT  |  HW Module  |  Protocol
+----------+---------------+-------------+------------
+Boot ROM  |  tiboot3.bin  |  MCU_UART0  |  X-Modem(*)
+R5 SPL    |  sysfw.itb    |  MCU_UART0  |  Y-Modem(*)
+R5 SPL    |  tispl.bin    |  MAIN_UART0 |  Y-Modem
+A53 SPL   |  u-boot.img   |  MAIN_UART0 |  Y-Modem
+
+(*) Note that in addition to X/Y-Modem related protocol timeouts the DMSC
+    watchdog timeout of 3min (typ.) needs to be observed until System Firmware
+    is fully loaded (from sysfw.itb) and started.
+
+Example bash script sequence for running on a Linux host PC feeding all boot
+artifacts needed to the device:
+
+MCU_DEV=/dev/ttyUSB1
+MAIN_DEV=/dev/ttyUSB0
+
+stty -F $MCU_DEV 115200 cs8 -cstopb -parenb
+stty -F $MAIN_DEV 115200 cs8 -cstopb -parenb
+
+sb --xmodem tiboot3.bin > $MCU_DEV < $MCU_DEV
+sb --ymodem sysfw.itb > $MCU_DEV < $MCU_DEV
+sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV
+sleep 1
+sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV
diff --git a/roms/u-boot/board/ti/am65x/evm.c b/roms/u-boot/board/ti/am65x/evm.c
new file mode 100644
index 000000000..fbe33cbea
--- /dev/null
+++ b/roms/u-boot/board/ti/am65x/evm.c
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for AM654 EVM
+ *
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <image.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/omap_common.h>
+#include <env.h>
+#include <spl.h>
+#include <asm/arch/sys_proto.h>
+
+#include "../common/board_detect.h"
+
+#define board_is_am65x_base_board()	board_ti_is("AM6-COMPROCEVM")
+
+/* Daughter card presence detection signals */
+enum {
+	AM65X_EVM_APP_BRD_DET,
+	AM65X_EVM_LCD_BRD_DET,
+	AM65X_EVM_SERDES_BRD_DET,
+	AM65X_EVM_HDMI_GPMC_BRD_DET,
+	AM65X_EVM_BRD_DET_COUNT,
+};
+
+/* Max number of MAC addresses that are parsed/processed per daughter card */
+#define DAUGHTER_CARD_NO_OF_MAC_ADDR	8
+
+/* Regiter that controls the SERDES0 lane and clock assignment */
+#define CTRLMMR_SERDES0_CTRL    0x00104080
+#define PCIE_LANE0              0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+#ifdef CONFIG_PHYS_64BIT
+	gd->ram_size = 0x100000000;
+#else
+	gd->ram_size = 0x80000000;
+#endif
+
+	return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_PHYS_64BIT
+	/* Limit RAM used by U-Boot to the DDR low region */
+	if (gd->ram_top > 0x100000000)
+		return 0x100000000;
+#endif
+
+	return gd->ram_top;
+}
+
+int dram_init_banksize(void)
+{
+	/* Bank 0 declares the memory available in the DDR low region */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = 0x80000000;
+	gd->ram_size = 0x80000000;
+
+#ifdef CONFIG_PHYS_64BIT
+	/* Bank 1 declares the memory available in the DDR high region */
+	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+	gd->bd->bi_dram[1].size = 0x80000000;
+	gd->ram_size = 0x100000000;
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+#ifdef CONFIG_TARGET_AM654_A53_EVM
+	if (!strcmp(name, "k3-am654-base-board"))
+		return 0;
+#endif
+
+	return -1;
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int ret;
+
+	ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
+	if (ret < 0)
+		ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
+					 "sram@70000000");
+	if (ret) {
+		printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
+		return ret;
+	}
+
+#if defined(CONFIG_TI_SECURE_DEVICE)
+	/* Make Crypto HW reserved for secure world use */
+	ret = fdt_disable_node(blob, "/bus@100000/crypto@4e00000");
+	if (ret < 0)
+		ret = fdt_disable_node(blob,
+				       "/interconnect@100000/crypto@4E00000");
+	if (ret)
+		printf("%s: disabling SA2UL failed %d\n", __func__, ret);
+#endif
+
+	return 0;
+}
+#endif
+
+int do_board_detect(void)
+{
+	int ret;
+
+	ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+					 CONFIG_EEPROM_CHIP_ADDRESS);
+	if (ret)
+		pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+		       CONFIG_EEPROM_CHIP_ADDRESS, ret);
+
+	return ret;
+}
+
+int checkboard(void)
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+	if (do_board_detect())
+		/* EEPROM not populated */
+		printf("Board: %s rev %s\n", "AM6-COMPROCEVM", "E3");
+	else
+		printf("Board: %s rev %s\n", ep->name, ep->version);
+
+	return 0;
+}
+
+static void setup_board_eeprom_env(void)
+{
+	char *name = "am65x";
+
+	if (do_board_detect())
+		goto invalid_eeprom;
+
+	if (board_is_am65x_base_board())
+		name = "am65x";
+	else
+		printf("Unidentified board claims %s in eeprom header\n",
+		       board_ti_get_name());
+
+invalid_eeprom:
+	set_board_info_env_am6(name);
+}
+
+static int init_daughtercard_det_gpio(char *gpio_name, struct gpio_desc *desc)
+{
+	int ret;
+
+	memset(desc, 0, sizeof(*desc));
+
+	ret = dm_gpio_lookup_name(gpio_name, desc);
+	if (ret < 0)
+		return ret;
+
+	/* Request GPIO, simply re-using the name as label */
+	ret = dm_gpio_request(desc, gpio_name);
+	if (ret < 0)
+		return ret;
+
+	return dm_gpio_set_dir_flags(desc, GPIOD_IS_IN);
+}
+
+static int probe_daughtercards(void)
+{
+	struct ti_am6_eeprom ep;
+	struct gpio_desc board_det_gpios[AM65X_EVM_BRD_DET_COUNT];
+	char mac_addr[DAUGHTER_CARD_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+	u8 mac_addr_cnt;
+	char name_overlays[1024] = { 0 };
+	int i, j;
+	int ret;
+
+	/*
+	 * Daughter card presence detection signal name to GPIO (via I2C I/O
+	 * expander @ address 0x38) name and EEPROM I2C address mapping.
+	 */
+	const struct {
+		char *gpio_name;
+		u8 i2c_addr;
+	} slot_map[AM65X_EVM_BRD_DET_COUNT] = {
+		{ "gpio@38_0", 0x52, },	/* AM65X_EVM_APP_BRD_DET */
+		{ "gpio@38_1", 0x55, },	/* AM65X_EVM_LCD_BRD_DET */
+		{ "gpio@38_2", 0x54, },	/* AM65X_EVM_SERDES_BRD_DET */
+		{ "gpio@38_3", 0x53, },	/* AM65X_EVM_HDMI_GPMC_BRD_DET */
+	};
+
+	/* Declaration of daughtercards to probe */
+	const struct {
+		u8 slot_index;		/* Slot the card is installed */
+		char *card_name;	/* EEPROM-programmed card name */
+		char *dtbo_name;	/* Device tree overlay to apply */
+		u8 eth_offset;		/* ethXaddr MAC address index offset */
+	} cards[] = {
+		{
+			AM65X_EVM_APP_BRD_DET,
+			"AM6-GPAPPEVM",
+			"k3-am654-gp.dtbo",
+			0,
+		},
+		{
+			AM65X_EVM_APP_BRD_DET,
+			"AM6-IDKAPPEVM",
+			"k3-am654-idk.dtbo",
+			3,
+		},
+		{
+			AM65X_EVM_SERDES_BRD_DET,
+			"SER-PCIE2LEVM",
+			"k3-am654-pcie-usb2.dtbo",
+			0,
+		},
+		{
+			AM65X_EVM_SERDES_BRD_DET,
+			"SER-PCIEUSBEVM",
+			"k3-am654-pcie-usb3.dtbo",
+			0,
+		},
+		{
+			AM65X_EVM_LCD_BRD_DET,
+			"OLDI-LCD1EVM",
+			"k3-am654-evm-oldi-lcd1evm.dtbo",
+			0,
+		},
+	};
+
+	/*
+	 * Initialize GPIO used for daughtercard slot presence detection and
+	 * keep the resulting handles in local array for easier access.
+	 */
+	for (i = 0; i < AM65X_EVM_BRD_DET_COUNT; i++) {
+		ret = init_daughtercard_det_gpio(slot_map[i].gpio_name,
+						 &board_det_gpios[i]);
+		if (ret < 0)
+			return ret;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(cards); i++) {
+		/* Obtain card-specific slot index and associated I2C address */
+		u8 slot_index = cards[i].slot_index;
+		u8 i2c_addr = slot_map[slot_index].i2c_addr;
+
+		/*
+		 * The presence detection signal is active-low, hence skip
+		 * over this card slot if anything other than 0 is returned.
+		 */
+		ret = dm_gpio_get_value(&board_det_gpios[slot_index]);
+		if (ret < 0)
+			return ret;
+		else if (ret)
+			continue;
+
+		/* Get and parse the daughter card EEPROM record */
+		ret = ti_i2c_eeprom_am6_get(CONFIG_EEPROM_BUS_ADDRESS, i2c_addr,
+					    &ep,
+					    (char **)mac_addr,
+					    DAUGHTER_CARD_NO_OF_MAC_ADDR,
+					    &mac_addr_cnt);
+		if (ret) {
+			pr_err("Reading daughtercard EEPROM at 0x%02x failed %d\n",
+			       i2c_addr, ret);
+			/*
+			 * Even this is pretty serious let's just skip over
+			 * this particular daughtercard, rather than ending
+			 * the probing process altogether.
+			 */
+			continue;
+		}
+
+		/* Only process the parsed data if we found a match */
+		if (strncmp(ep.name, cards[i].card_name, sizeof(ep.name)))
+			continue;
+
+		printf("Detected: %s rev %s\n", ep.name, ep.version);
+
+		/*
+		 * Populate any MAC addresses from daughtercard into the U-Boot
+		 * environment, starting with a card-specific offset so we can
+		 * have multiple cards contribute to the MAC pool in a well-
+		 * defined manner.
+		 */
+		for (j = 0; j < mac_addr_cnt; j++) {
+			if (!is_valid_ethaddr((u8 *)mac_addr[j]))
+				continue;
+
+			eth_env_set_enetaddr_by_index("eth",
+						      cards[i].eth_offset + j,
+						      (uchar *)mac_addr[j]);
+		}
+
+		/*
+		 * It has been observed that setting SERDES0 lane mux to USB prevents USB
+		 * 2.0 operation on USB0. Setting SERDES0 lane mux to non-USB when USB0 is
+		 * used in USB 2.0 only mode solves this issue. For USB3.0+2.0 operation
+		 * this issue is not present.
+		 *
+		 * Implement this workaround by writing 1 to LANE_FUNC_SEL field in
+		 * CTRLMMR_SERDES0_CTRL register.
+		 */
+		if (!strncmp(ep.name, "SER-PCIE2LEVM", sizeof(ep.name)))
+			writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
+
+		/* Skip if no overlays are to be added */
+		if (!strlen(cards[i].dtbo_name))
+			continue;
+
+		/*
+		 * Make sure we are not running out of buffer space by checking
+		 * if we can fit the new overlay, a trailing space to be used
+		 * as a separator, plus the terminating zero.
+		 */
+		if (strlen(name_overlays) + strlen(cards[i].dtbo_name) + 2 >
+		    sizeof(name_overlays))
+			return -ENOMEM;
+
+		/* Append to our list of overlays */
+		strcat(name_overlays, cards[i].dtbo_name);
+		strcat(name_overlays, " ");
+	}
+
+	/* Apply device tree overlay(s) to the U-Boot environment, if any */
+	if (strlen(name_overlays))
+		return env_set("name_overlays", name_overlays);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+	setup_board_eeprom_env();
+
+	/*
+	 * The first MAC address for ethernet a.k.a. ethernet0 comes from
+	 * efuse populated via the am654 gigabit eth switch subsystem driver.
+	 * All the other ones are populated via EEPROM, hence continue with
+	 * an index of 1.
+	 */
+	board_ti_am6_set_ethaddr(1, ep->mac_addr_cnt);
+
+	/* Check for and probe any plugged-in daughtercards */
+	probe_daughtercards();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/ti/beagle/Kconfig b/roms/u-boot/board/ti/beagle/Kconfig
new file mode 100644
index 000000000..c2eff9e71
--- /dev/null
+++ b/roms/u-boot/board/ti/beagle/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP3_BEAGLE
+
+config SYS_BOARD
+	default "beagle"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_CONFIG_NAME
+	default "omap3_beagle"
+
+endif
diff --git a/roms/u-boot/board/ti/beagle/MAINTAINERS b/roms/u-boot/board/ti/beagle/MAINTAINERS
new file mode 100644
index 000000000..c1d81d417
--- /dev/null
+++ b/roms/u-boot/board/ti/beagle/MAINTAINERS
@@ -0,0 +1,6 @@
+BEAGLE BOARD
+M:	Tom Rini <trini@konsulko.com>
+S:	Maintained
+F:	board/ti/beagle/
+F:	include/configs/omap3_beagle.h
+F:	configs/omap3_beagle_defconfig
diff --git a/roms/u-boot/board/ti/beagle/Makefile b/roms/u-boot/board/ti/beagle/Makefile
new file mode 100644
index 000000000..fc9288cf1
--- /dev/null
+++ b/roms/u-boot/board/ti/beagle/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= beagle.o
+obj-$(CONFIG_LED_STATUS) += led.o
diff --git a/roms/u-boot/board/ti/beagle/beagle.c b/roms/u-boot/board/ti/beagle/beagle.c
new file mode 100644
index 000000000..888a95849
--- /dev/null
+++ b/roms/u-boot/board/ti/beagle/beagle.c
@@ -0,0 +1,515 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2004-2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ */
+#include <common.h>
+#include <bootstage.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <ns16550.h>
+#include <serial.h>
+#ifdef CONFIG_LED_STATUS
+#include <status_led.h>
+#endif
+#include <twl4030.h>
+#include <asm/global_data.h>
+#include <linux/mtd/rawnand.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/omap_musb.h>
+#include <linux/errno.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include "beagle.h"
+#include <command.h>
+
+#define TWL4030_I2C_BUS			0
+#define EXPANSION_EEPROM_I2C_BUS	1
+#define EXPANSION_EEPROM_I2C_ADDRESS	0x50
+
+#define TINCANTOOLS_ZIPPY		0x01000100
+#define TINCANTOOLS_ZIPPY2		0x02000100
+#define TINCANTOOLS_TRAINER		0x04000100
+#define TINCANTOOLS_SHOWDOG		0x03000100
+#define KBADC_BEAGLEFPGA		0x01000600
+#define LW_BEAGLETOUCH			0x01000700
+#define BRAINMUX_LCDOG			0x01000800
+#define BRAINMUX_LCDOGTOUCH		0x02000800
+#define BBTOYS_WIFI			0x01000B00
+#define BBTOYS_VGA			0x02000B00
+#define BBTOYS_LCD			0x03000B00
+#define BCT_BRETTL3			0x01000F00
+#define BCT_BRETTL4			0x02000F00
+#define LSR_COM6L_ADPT			0x01001300
+#define BEAGLE_NO_EEPROM		0xffffffff
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct {
+	unsigned int device_vendor;
+	unsigned char revision;
+	unsigned char content;
+	char fab_revision[8];
+	char env_var[16];
+	char env_setting[64];
+} expansion_config;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
+	status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
+#endif
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+/*
+ * Routine: get_board_revision
+ * Description: Detect if we are running on a Beagle revision Ax/Bx,
+ *		C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading
+ *		the level of GPIO173, GPIO172 and GPIO171. This should
+ *		result in
+ *		GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
+ *		GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
+ *		GPIO173, GPIO172, GPIO171: 1 0 1 => C4
+ *		GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx
+ *		GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx
+ */
+static int get_board_revision(void)
+{
+	static int revision = -1;
+
+	if (revision == -1) {
+		if (!gpio_request(171, "rev0") &&
+		    !gpio_request(172, "rev1") &&
+		    !gpio_request(173, "rev2")) {
+			gpio_direction_input(171);
+			gpio_direction_input(172);
+			gpio_direction_input(173);
+
+			revision = gpio_get_value(173) << 2 |
+				gpio_get_value(172) << 1 |
+				gpio_get_value(171);
+		} else {
+			printf("Error: unable to acquire board revision GPIOs\n");
+		}
+	}
+
+	return revision;
+}
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+	int pop_mfr, pop_id;
+
+	/*
+	 * We need to identify what PoP memory is on the board so that
+	 * we know what timings to use.  If we can't identify it then
+	 * we know it's an xM.  To map the ID values please see nand_ids.c
+	 */
+	identify_nand_chip(&pop_mfr, &pop_id);
+
+	timings->mr = MICRON_V_MR_165;
+	switch (get_board_revision()) {
+	case REVISION_C4:
+		if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
+			/* 512MB DDR */
+			timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+			timings->ctrla = NUMONYX_V_ACTIMA_165;
+			timings->ctrlb = NUMONYX_V_ACTIMB_165;
+			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+			break;
+		} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
+			/* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
+			timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+			timings->ctrla = MICRON_V_ACTIMA_165;
+			timings->ctrlb = MICRON_V_ACTIMB_165;
+			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+			break;
+		} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
+			/* Beagleboard Rev C5, 256MB DDR */
+			timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+			timings->ctrla = MICRON_V_ACTIMA_200;
+			timings->ctrlb = MICRON_V_ACTIMB_200;
+			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+			break;
+		}
+	case REVISION_XM_AB:
+	case REVISION_XM_C:
+		if (pop_mfr == 0) {
+			/* 256MB DDR */
+			timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+			timings->ctrla = MICRON_V_ACTIMA_200;
+			timings->ctrlb = MICRON_V_ACTIMB_200;
+			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+		} else {
+			/* 512MB DDR */
+			timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+			timings->ctrla = NUMONYX_V_ACTIMA_165;
+			timings->ctrlb = NUMONYX_V_ACTIMB_165;
+			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+		}
+		break;
+	default:
+		/* Assume 128MB and Micron/165MHz timings to be safe */
+		timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+		timings->ctrla = MICRON_V_ACTIMA_165;
+		timings->ctrlb = MICRON_V_ACTIMB_165;
+		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+	}
+}
+#endif
+
+/*
+ * Routine: get_expansion_id
+ * Description: This function checks for expansion board by checking I2C
+ *		bus 1 for the availability of an AT24C01B serial EEPROM.
+ *		returns the device_vendor field from the EEPROM
+ */
+static unsigned int get_expansion_id(void)
+{
+	i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
+
+	/* return BEAGLE_NO_EEPROM if eeprom doesn't respond */
+	if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
+		i2c_set_bus_num(TWL4030_I2C_BUS);
+		return BEAGLE_NO_EEPROM;
+	}
+
+	/* read configuration data */
+	i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
+		 sizeof(expansion_config));
+
+	/* retry reading configuration data with 16bit addressing */
+	if ((expansion_config.device_vendor == 0xFFFFFF00) ||
+	    (expansion_config.device_vendor == 0xFFFFFFFF)) {
+		printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n");
+		i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config,
+			 sizeof(expansion_config));
+	}
+
+	i2c_set_bus_num(TWL4030_I2C_BUS);
+
+	return expansion_config.device_vendor;
+}
+
+#ifdef CONFIG_VIDEO_OMAP3
+/*
+ * Configure DSS to display background color on DVID
+ * Configure VENC to display color bar on S-Video
+ */
+static void beagle_display_init(void)
+{
+	omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
+	switch (get_board_revision()) {
+	case REVISION_AXBX:
+	case REVISION_CX:
+	case REVISION_C4:
+		omap3_dss_panel_config(&dvid_cfg);
+		break;
+	case REVISION_XM_AB:
+	case REVISION_XM_C:
+	default:
+		omap3_dss_panel_config(&dvid_cfg_xm);
+		break;
+	}
+}
+
+/*
+ * Enable DVI power
+ */
+static void beagle_dvi_pup(void)
+{
+	uchar val;
+
+	switch (get_board_revision()) {
+	case REVISION_AXBX:
+	case REVISION_CX:
+	case REVISION_C4:
+		gpio_request(170, "dvi");
+		gpio_direction_output(170, 0);
+		gpio_set_value(170, 1);
+		break;
+	case REVISION_XM_AB:
+	case REVISION_XM_C:
+	default:
+		#define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3)
+		#define GPIODATAOUT1 (TWL4030_BASEADD_GPIO+6)
+
+		i2c_read(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
+		val |= 4;
+		i2c_write(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
+
+		i2c_read(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
+		val |= 4;
+		i2c_write(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
+		break;
+	}
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+	struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
+	bool generate_fake_mac = false;
+	u32 value;
+
+	/* Enable i2c2 pullup resisters */
+	value = readl(&prog_io_base->io1);
+	value &= ~(PRG_I2C2_PULLUPRESX);
+	writel(value, &prog_io_base->io1);
+
+	switch (get_board_revision()) {
+	case REVISION_AXBX:
+		printf("Beagle Rev Ax/Bx\n");
+		env_set("beaglerev", "AxBx");
+		break;
+	case REVISION_CX:
+		printf("Beagle Rev C1/C2/C3\n");
+		env_set("beaglerev", "Cx");
+		MUX_BEAGLE_C();
+		break;
+	case REVISION_C4:
+		printf("Beagle Rev C4\n");
+		env_set("beaglerev", "C4");
+		MUX_BEAGLE_C();
+		/* Set VAUX2 to 1.8V for EHCI PHY */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+					TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+					TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+					TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		break;
+	case REVISION_XM_AB:
+		printf("Beagle xM Rev A/B\n");
+		env_set("beaglerev", "xMAB");
+		MUX_BEAGLE_XM();
+		/* Set VAUX2 to 1.8V for EHCI PHY */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+					TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+					TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+					TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		generate_fake_mac = true;
+		break;
+	case REVISION_XM_C:
+		printf("Beagle xM Rev C\n");
+		env_set("beaglerev", "xMC");
+		MUX_BEAGLE_XM();
+		/* Set VAUX2 to 1.8V for EHCI PHY */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+					TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+					TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+					TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		generate_fake_mac = true;
+		break;
+	default:
+		printf("Beagle unknown 0x%02x\n", get_board_revision());
+		MUX_BEAGLE_XM();
+		/* Set VAUX2 to 1.8V for EHCI PHY */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+					TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+					TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+					TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		generate_fake_mac = true;
+	}
+
+	switch (get_expansion_id()) {
+	case TINCANTOOLS_ZIPPY:
+		printf("Recognized Tincantools Zippy board (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		MUX_TINCANTOOLS_ZIPPY();
+		env_set("buddy", "zippy");
+		break;
+	case TINCANTOOLS_ZIPPY2:
+		printf("Recognized Tincantools Zippy2 board (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		MUX_TINCANTOOLS_ZIPPY();
+		env_set("buddy", "zippy2");
+		break;
+	case TINCANTOOLS_TRAINER:
+		printf("Recognized Tincantools Trainer board (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		MUX_TINCANTOOLS_ZIPPY();
+		MUX_TINCANTOOLS_TRAINER();
+		env_set("buddy", "trainer");
+		break;
+	case TINCANTOOLS_SHOWDOG:
+		printf("Recognized Tincantools Showdow board (rev %d %s)\n",
+			expansion_config.revision,
+			expansion_config.fab_revision);
+		/* Place holder for DSS2 definition for showdog lcd */
+		env_set("defaultdisplay", "showdoglcd");
+		env_set("buddy", "showdog");
+		break;
+	case KBADC_BEAGLEFPGA:
+		printf("Recognized KBADC Beagle FPGA board\n");
+		MUX_KBADC_BEAGLEFPGA();
+		env_set("buddy", "beaglefpga");
+		break;
+	case LW_BEAGLETOUCH:
+		printf("Recognized Liquidware BeagleTouch board\n");
+		env_set("buddy", "beagletouch");
+		break;
+	case BRAINMUX_LCDOG:
+		printf("Recognized Brainmux LCDog board\n");
+		env_set("buddy", "lcdog");
+		break;
+	case BRAINMUX_LCDOGTOUCH:
+		printf("Recognized Brainmux LCDog Touch board\n");
+		env_set("buddy", "lcdogtouch");
+		break;
+	case BBTOYS_WIFI:
+		printf("Recognized BeagleBoardToys WiFi board\n");
+		MUX_BBTOYS_WIFI()
+		env_set("buddy", "bbtoys-wifi");
+		break;
+	case BBTOYS_VGA:
+		printf("Recognized BeagleBoardToys VGA board\n");
+		break;
+	case BBTOYS_LCD:
+		printf("Recognized BeagleBoardToys LCD board\n");
+		break;
+	case BCT_BRETTL3:
+		printf("Recognized bct electronic GmbH brettl3 board\n");
+		break;
+	case BCT_BRETTL4:
+		printf("Recognized bct electronic GmbH brettl4 board\n");
+		break;
+	case LSR_COM6L_ADPT:
+		printf("Recognized LSR COM6L Adapter Board\n");
+		MUX_BBTOYS_WIFI()
+		env_set("buddy", "lsr-com6l-adpt");
+		break;
+	case BEAGLE_NO_EEPROM:
+		printf("No EEPROM on expansion board\n");
+		env_set("buddy", "none");
+		break;
+	default:
+		printf("Unrecognized expansion board: %x\n",
+			expansion_config.device_vendor);
+		env_set("buddy", "unknown");
+	}
+
+	if (expansion_config.content == 1)
+		env_set(expansion_config.env_var, expansion_config.env_setting);
+
+	twl4030_power_init();
+	switch (get_board_revision()) {
+	case REVISION_XM_AB:
+		twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
+		break;
+	default:
+		twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+		break;
+	}
+
+	/* Set GPIO states before they are made outputs */
+	writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
+		&gpio6_base->setdataout);
+	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+		GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
+
+	/* Configure GPIOs to output */
+	writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
+	writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+		GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
+
+	omap_die_id_display();
+
+#ifdef CONFIG_VIDEO_OMAP3
+	beagle_dvi_pup();
+	beagle_display_init();
+	omap3_dss_enable();
+#endif
+
+	if (generate_fake_mac)
+		omap_die_id_usbethaddr();
+
+#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
+	if (strlen(CONFIG_MTDIDS_DEFAULT))
+		env_set("mtdids", CONFIG_MTDIDS_DEFAULT);
+
+	if (strlen(CONFIG_MTDPARTS_DEFAULT))
+		env_set("mtdparts", CONFIG_MTDPARTS_DEFAULT);
+#endif
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_BEAGLE();
+}
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(struct bd_info *bis)
+{
+	return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_MMC)
+void board_mmc_power_init(void)
+{
+	twl4030_power_mmc_init(0);
+}
+#endif
diff --git a/roms/u-boot/board/ti/beagle/beagle.h b/roms/u-boot/board/ti/beagle/beagle.h
new file mode 100644
index 000000000..ce78ea661
--- /dev/null
+++ b/roms/u-boot/board/ti/beagle/beagle.h
@@ -0,0 +1,545 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ */
+#ifndef _BEAGLE_H_
+#define _BEAGLE_H_
+
+#include <asm/arch/dss.h>
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 Beagle board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	"OneNAND",
+#else
+	"NAND",
+#endif
+};
+
+/* BeagleBoard revisions */
+#define REVISION_AXBX	0x7
+#define REVISION_CX	0x6
+#define REVISION_C4	0x5
+#define REVISION_XM_AB	0x0
+#define REVISION_XM_C	0x2
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_BEAGLE() \
+ /*SDRC*/\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M1)) /*SYS_nDMA_REQ3*/\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+ /*DSS*/\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card */\
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M1)) /*UART2_RX*/\
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | DIS | M4)) /*GPIO_144*/\
+	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145*/\
+	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M4)) /*GPIO_146*/\
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/\
+ /*Modem Interface */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+	MUX_VAL(CP(UART1_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
+	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
+	MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
+	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M4)) /*GPIO_157*/\
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+	MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+	MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_171*/\
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTU | EN  | M4)) /*GPIO_172*/\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTU | EN  | M4)) /*GPIO_173*/\
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+ /* USB EHCI (port 2) */\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA2*/\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA7*/\
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA4*/\
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA5*/\
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA6*/\
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA3*/\
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DIR*/\
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_NXT*/\
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA0*/\
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA1*/\
+ /*Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M4)) /*GPIO_186*/\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
+
+#define MUX_BEAGLE_C() \
+	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_141*/\
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+	MUX_VAL(CP(UART2_RX),		(IDIS | PTU | EN  | M4)) /*GPIO_147*/
+
+#define MUX_BEAGLE_XM() \
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | EN  | M4)) /*GPIO_56*/\
+	MUX_VAL(CP(GPMC_WAIT1),		(IDIS | PTU | EN  | M4)) /*GPIO_63*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IDIS | PTU | EN  | M4)) /*GPIO_129*/\
+	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
+	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_141*/\
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+	MUX_VAL(CP(SYS_BOOT0),		(IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+	MUX_VAL(CP(SYS_BOOT1),		(IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
+
+#define MUX_TINCANTOOLS_ZIPPY() \
+	MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
+	MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+	MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+	MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+	MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_CMD*/\
+	MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
+	MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTU | EN  | M1)) /*MCSPI4_CLK*/\
+	MUX_VAL(CP(MCBSP1_FSR),     (IEN  | PTU | EN  | M4)) /*GPIO_157*/\
+	MUX_VAL(CP(MCBSP1_DX),      (IEN  | PTD | EN  | M1)) /*MCSPI4_SIMO*/\
+	MUX_VAL(CP(MCBSP1_DR),      (IEN  | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
+	MUX_VAL(CP(MCBSP1_FSX),     (IEN  | PTD | EN  | M1)) /*MCSPI4_CS0*/\
+	MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_162*/\
+	MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+	MUX_VAL(CP(MCBSP3_DR),      (IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+	MUX_VAL(CP(MCBSP3_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_141*/
+
+#define MUX_TINCANTOOLS_TRAINER() \
+	MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+	MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+	MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+	MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+	MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+	MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+	MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+	MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+	MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+	MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+	MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTU | EN  | M4)) /*GPIO_140*/\
+	MUX_VAL(CP(MCBSP3_CLKX),    (IEN  | PTU | EN  | M4)) /*GPIO_141*/\
+	MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTU | EN  | M4)) /*GPIO_162*/
+
+#define MUX_KBADC_BEAGLEFPGA() \
+	MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTU | DIS | M1)) /*MCSPI4_CLK*/\
+	MUX_VAL(CP(MCBSP1_DX),      (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
+	MUX_VAL(CP(MCBSP1_DR),      (IEN  | PTU | EN  | M1)) /*MCSPI4_SOMI*/\
+	MUX_VAL(CP(MCBSP1_FSX),     (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
+
+#define MUX_BBTOYS_WIFI() \
+	MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
+	MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+	MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+	MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+	MUX_VAL(CP(MMC2_DAT4),      (IDIS | PTU | EN  | M4)) /*GPIO_136 FM_EN/BT_WU*/\
+	MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M4)) /*GPIO_137 WLAN_IRQ*/\
+	MUX_VAL(CP(MMC2_DAT6),      (IDIS | PTU | EN  | M4)) /*GPIO_138 BT_EN*/\
+	MUX_VAL(CP(MMC2_DAT7),      (IDIS | PTU | EN  | M4)) /*GPIO_139 WLAN_EN*/
+
+/*
+ * Display Configuration
+ */
+
+#define DVI_BEAGLE_ORANGE_COL		0x00FF8000
+#define VENC_HEIGHT			0x00ef
+#define VENC_WIDTH			0x027f
+
+/*
+ * Configure VENC in DSS for Beagle to generate Color Bar
+ *
+ * Kindly refer to OMAP TRM for definition of these values.
+ */
+static const struct venc_regs venc_config_std_tv = {
+	.status					= 0x0000001B,
+	.f_control				= 0x00000040,
+	.vidout_ctrl				= 0x00000000,
+	.sync_ctrl				= 0x00008000,
+	.llen					= 0x00008359,
+	.flens					= 0x0000020C,
+	.hfltr_ctrl				= 0x00000000,
+	.cc_carr_wss_carr			= 0x043F2631,
+	.c_phase				= 0x00000024,
+	.gain_u					= 0x00000130,
+	.gain_v					= 0x00000198,
+	.gain_y					= 0x000001C0,
+	.black_level				= 0x0000006A,
+	.blank_level				= 0x0000005C,
+	.x_color				= 0x00000000,
+	.m_control				= 0x00000001,
+	.bstamp_wss_data			= 0x0000003F,
+	.s_carr					= 0x21F07C1F,
+	.line21					= 0x00000000,
+	.ln_sel					= 0x00000015,
+	.l21__wc_ctl				= 0x00001400,
+	.htrigger_vtrigger			= 0x00000000,
+	.savid__eavid				= 0x069300F4,
+	.flen__fal				= 0x0016020C,
+	.lal__phase_reset			= 0x00060107,
+	.hs_int_start_stop_x			= 0x008D034E,
+	.hs_ext_start_stop_x			= 0x000F0359,
+	.vs_int_start_x				= 0x01A00000,
+	.vs_int_stop_x__vs_int_start_y		= 0x020501A0,
+	.vs_int_stop_y__vs_ext_start_x		= 0x01AC0024,
+	.vs_ext_stop_x__vs_ext_start_y		= 0x020D01AC,
+	.vs_ext_stop_y				= 0x00000006,
+	.avid_start_stop_x			= 0x03480079,
+	.avid_start_stop_y			= 0x02040024,
+	.fid_int_start_x__fid_int_start_y	= 0x0001008A,
+	.fid_int_offset_y__fid_ext_start_x	= 0x01AC0106,
+	.fid_ext_start_y__fid_ext_offset_y	= 0x01060006,
+	.tvdetgp_int_start_stop_x		= 0x00140001,
+	.tvdetgp_int_start_stop_y		= 0x00010001,
+	.gen_ctrl				= 0x00FF0000,
+	.output_control				= 0x0000000D,
+	.dac_b__dac_c				= 0x00000000
+};
+
+/*
+ * Configure Timings for DVI D
+ */
+static const struct panel_config dvid_cfg = {
+	.timing_h	= 0x0ff03f31, /* Horizontal timing */
+	.timing_v	= 0x01400504, /* Vertical timing */
+	.pol_freq	= 0x00007028, /* Pol Freq */
+	.divisor	= 0x00010006, /* 72Mhz Pixel Clock */
+	.lcd_size	= 0x02ff03ff, /* 1024x768 */
+	.panel_type	= 0x01, /* TFT */
+	.data_lines	= 0x03, /* 24 Bit RGB */
+	.load_mode	= 0x02, /* Frame Mode */
+	.panel_color	= DVI_BEAGLE_ORANGE_COL, /* ORANGE */
+	.gfx_format	= GFXFORMAT_RGB24_UNPACKED,
+};
+
+static const struct panel_config dvid_cfg_xm = {
+	.timing_h	= 0x1a4024c9, /* Horizontal timing */
+	.timing_v	= 0x02c00509, /* Vertical timing */
+	.pol_freq	= 0x00007028, /* Pol Freq */
+	.divisor	= 0x00010001, /* 96MHz Pixel Clock */
+	.lcd_size	= 0x02ff03ff, /* 1024x768 */
+	.panel_type	= 0x01, /* TFT */
+	.data_lines	= 0x03, /* 24 Bit RGB */
+	.load_mode	= 0x02, /* Frame Mode */
+	.panel_color	= DVI_BEAGLE_ORANGE_COL, /* ORANGE */
+	.gfx_format	= GFXFORMAT_RGB24_UNPACKED,
+};
+#endif
diff --git a/roms/u-boot/board/ti/beagle/led.c b/roms/u-boot/board/ti/beagle/led.c
new file mode 100644
index 000000000..e21c0169d
--- /dev/null
+++ b/roms/u-boot/board/ti/beagle/led.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2010 Texas Instruments, Inc.
+ * Jason Kridner <jkridner@beagleboard.org>
+ */
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+
+/* GPIO pins for the LEDs */
+#define BEAGLE_LED_USR0	150
+#define BEAGLE_LED_USR1	149
+
+#ifdef CONFIG_LED_STATUS_GREEN
+void green_led_off(void)
+{
+	__led_set(CONFIG_LED_STATUS_GREEN, 0);
+}
+
+void green_led_on(void)
+{
+	__led_set(CONFIG_LED_STATUS_GREEN, 1);
+}
+#endif
+
+static int get_led_gpio(led_id_t mask)
+{
+#ifdef CONFIG_LED_STATUS0
+	if (CONFIG_LED_STATUS_BIT & mask)
+		return BEAGLE_LED_USR0;
+#endif
+#ifdef CONFIG_LED_STATUS1
+	if (CONFIG_LED_STATUS_BIT1 & mask)
+		return BEAGLE_LED_USR1;
+#endif
+
+	return 0;
+}
+
+void __led_init (led_id_t mask, int state)
+{
+	int toggle_gpio;
+
+	toggle_gpio = get_led_gpio(mask);
+
+	if (toggle_gpio && !gpio_request(toggle_gpio, "led"))
+		__led_set(mask, state);
+}
+
+void __led_toggle (led_id_t mask)
+{
+	int state, toggle_gpio;
+
+	toggle_gpio = get_led_gpio(mask);
+	if (toggle_gpio) {
+		state = gpio_get_value(toggle_gpio);
+		gpio_direction_output(toggle_gpio, !state);
+	}
+}
+
+void __led_set (led_id_t mask, int state)
+{
+	int toggle_gpio;
+
+	toggle_gpio = get_led_gpio(mask);
+	if (toggle_gpio)
+		gpio_direction_output(toggle_gpio, state);
+}
diff --git a/roms/u-boot/board/ti/common/Kconfig b/roms/u-boot/board/ti/common/Kconfig
new file mode 100644
index 000000000..49edd9801
--- /dev/null
+++ b/roms/u-boot/board/ti/common/Kconfig
@@ -0,0 +1,51 @@
+config TI_I2C_BOARD_DETECT
+	bool "Support for Board detection for TI platforms"
+	help
+	   Support for detection board information on Texas Instrument's
+	   Evaluation Boards which have I2C based EEPROM detection
+
+config EEPROM_BUS_ADDRESS
+	int "Board EEPROM's I2C bus address"
+	range 0 8
+	default 0
+	depends on TI_I2C_BOARD_DETECT
+
+config EEPROM_CHIP_ADDRESS
+	hex "Board EEPROM's I2C chip address"
+	range 0 0xff
+	default 0x50
+	depends on TI_I2C_BOARD_DETECT
+
+config CAPE_EEPROM_BUS_NUM
+	int "Cape EEPROM's I2C bus address"
+	range 0 8
+	default 2
+	depends on CMD_EXTENSION
+
+config TI_COMMON_CMD_OPTIONS
+	bool "Enable cmd options on TI platforms"
+	imply CMD_ASKENV
+	imply CMD_BOOTZ
+	imply CRC32_VERIFY if ARCH_KEYSTONE
+	imply CMD_DFU if USB_GADGET_DOWNLOAD
+	imply CMD_DHCP
+	imply CMD_EEPROM
+	imply CMD_EXT2
+	imply CMD_EXT4
+	imply CMD_EXT4_WRITE
+	imply CMD_FAT
+	imply FAT_WRITE if CMD_FAT
+	imply CMD_FS_GENERIC
+	imply CMD_GPIO
+	imply CMD_GPT
+	imply CMD_I2C
+	imply CMD_MII
+	imply CMD_MMC
+	imply CMD_PART
+	imply CMD_PING
+	imply CMD_PMIC if DM_PMIC
+	imply CMD_REGULATOR if DM_REGULATOR
+	imply CMD_SF if SPI_FLASH
+	imply CMD_SPI
+	imply CMD_TIME
+	imply CMD_USB if USB
diff --git a/roms/u-boot/board/ti/common/Makefile b/roms/u-boot/board/ti/common/Makefile
new file mode 100644
index 000000000..3172d87b4
--- /dev/null
+++ b/roms/u-boot/board/ti/common/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+
+obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o
+obj-${CONFIG_CMD_EXTENSION} += cape_detect.o
diff --git a/roms/u-boot/board/ti/common/board_detect.c b/roms/u-boot/board/ti/common/board_detect.c
new file mode 100644
index 000000000..de92eb098
--- /dev/null
+++ b/roms/u-boot/board/ti/common/board_detect.c
@@ -0,0 +1,793 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Library to support early TI EVM EEPROM handling
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla
+ *	Steve Kipisz
+ */
+
+#include <common.h>
+#include <eeprom.h>
+#include <log.h>
+#include <net.h>
+#include <asm/arch/hardware.h>
+#include <asm/omap_common.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <errno.h>
+#include <malloc.h>
+
+#include "board_detect.h"
+
+#if !CONFIG_IS_ENABLED(DM_I2C)
+/**
+ * ti_i2c_eeprom_init - Initialize an i2c bus and probe for a device
+ * @i2c_bus: i2c bus number to initialize
+ * @dev_addr: Device address to probe for
+ *
+ * Return: 0 on success or corresponding error on failure.
+ */
+static int __maybe_unused ti_i2c_eeprom_init(int i2c_bus, int dev_addr)
+{
+	int rc;
+
+	if (i2c_bus >= 0) {
+		rc = i2c_set_bus_num(i2c_bus);
+		if (rc)
+			return rc;
+	}
+
+	return i2c_probe(dev_addr);
+}
+
+/**
+ * ti_i2c_eeprom_read - Read data from an EEPROM
+ * @dev_addr: The device address of the EEPROM
+ * @offset: Offset to start reading in the EEPROM
+ * @ep: Pointer to a buffer to read into
+ * @epsize: Size of buffer
+ *
+ * Return: 0 on success or corresponding result of i2c_read
+ */
+static int __maybe_unused ti_i2c_eeprom_read(int dev_addr, int offset,
+					     uchar *ep, int epsize)
+{
+	return i2c_read(dev_addr, offset, 2, ep, epsize);
+}
+#endif
+
+/**
+ * ti_eeprom_string_cleanup() - Handle eeprom programming errors
+ * @s:	eeprom string (should be NULL terminated)
+ *
+ * Some Board manufacturers do not add a NULL termination at the
+ * end of string, instead some binary information is kludged in, hence
+ * convert the string to just printable characters of ASCII chart.
+ */
+static void __maybe_unused ti_eeprom_string_cleanup(char *s)
+{
+	int i, l;
+
+	l = strlen(s);
+	for (i = 0; i < l; i++, s++)
+		if (*s < ' ' || *s > '~') {
+			*s = 0;
+			break;
+		}
+}
+
+__weak void gpi2c_init(void)
+{
+}
+
+static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
+					    u32 header, u32 size, uint8_t *ep)
+{
+	u32 hdr_read;
+	int rc;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *dev;
+	struct udevice *bus;
+
+	rc = uclass_get_device_by_seq(UCLASS_I2C, bus_addr, &bus);
+	if (rc)
+		return rc;
+	rc = dm_i2c_probe(bus, dev_addr, 0, &dev);
+	if (rc)
+		return rc;
+
+	/*
+	 * Read the header first then only read the other contents.
+	 */
+	rc = i2c_set_chip_offset_len(dev, 2);
+	if (rc)
+		return rc;
+
+	rc = dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4);
+	if (rc)
+		return rc;
+
+	/* Corrupted data??? */
+	if (hdr_read != header) {
+		/*
+		 * read the eeprom header using i2c again, but use only a
+		 * 1 byte address (some legacy boards need this..)
+		 */
+		rc = i2c_set_chip_offset_len(dev, 1);
+		if (rc)
+			return rc;
+
+		rc = dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4);
+		if (rc)
+			return rc;
+	}
+	if (hdr_read != header)
+		return -1;
+
+	rc = dm_i2c_read(dev, 0, ep, size);
+	if (rc)
+		return rc;
+#else
+	u32 byte;
+
+	gpi2c_init();
+	rc = ti_i2c_eeprom_init(bus_addr, dev_addr);
+	if (rc)
+		return rc;
+
+	/*
+	 * Read the header first then only read the other contents.
+	 */
+	byte = 2;
+
+	rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4);
+	if (rc)
+		return rc;
+
+	/* Corrupted data??? */
+	if (hdr_read != header) {
+		/*
+		 * read the eeprom header using i2c again, but use only a
+		 * 1 byte address (some legacy boards need this..)
+		 */
+		byte = 1;
+		rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read,
+			      4);
+		if (rc)
+			return rc;
+	}
+	if (hdr_read != header)
+		return -1;
+
+	rc = i2c_read(dev_addr, 0x0, byte, ep, size);
+	if (rc)
+		return rc;
+#endif
+	return 0;
+}
+
+int __maybe_unused ti_emmc_boardid_get(void)
+{
+	int rc;
+	struct udevice *dev;
+	struct mmc *mmc;
+	struct ti_common_eeprom *ep;
+	struct ti_am_eeprom brdid;
+	struct blk_desc *bdesc;
+	uchar *buffer;
+
+	ep = TI_EEPROM_DATA;
+	if (ep->header == TI_EEPROM_HEADER_MAGIC)
+		return 0;       /* EEPROM has already been read */
+
+	/* Initialize with a known bad marker for emmc fails.. */
+	ep->header = TI_DEAD_EEPROM_MAGIC;
+	ep->name[0] = 0x0;
+	ep->version[0] = 0x0;
+	ep->serial[0] = 0x0;
+	ep->config[0] = 0x0;
+
+	/* uclass object initialization */
+	rc = mmc_initialize(NULL);
+	if (rc)
+		return rc;
+
+	/* Set device to /dev/mmcblk1 */
+	rc = uclass_get_device(UCLASS_MMC, 1, &dev);
+	if (rc)
+		return rc;
+
+	/* Grab the mmc device */
+	mmc = mmc_get_mmc_dev(dev);
+	if (!mmc)
+		return -ENODEV;
+
+	/* mmc hardware initialization routine */
+	mmc_init(mmc);
+
+	/* Set partition to /dev/mmcblk1boot1 */
+	rc = mmc_switch_part(mmc, 2);
+	if (rc)
+		return rc;
+
+	buffer = malloc(mmc->read_bl_len);
+	if (!buffer)
+		return -ENOMEM;
+
+	bdesc = mmc_get_blk_desc(mmc);
+
+	/* blk_dread returns the number of blocks read*/
+	if (blk_dread(bdesc, 0L, 1, buffer) != 1) {
+		rc = -EIO;
+		goto cleanup;
+	}
+
+	memcpy(&brdid, buffer, sizeof(brdid));
+
+	/* Write out the ep struct values */
+	ep->header = brdid.header;
+	strlcpy(ep->name, brdid.name, TI_EEPROM_HDR_NAME_LEN + 1);
+	ti_eeprom_string_cleanup(ep->name);
+	strlcpy(ep->version, brdid.version, TI_EEPROM_HDR_REV_LEN + 1);
+	ti_eeprom_string_cleanup(ep->version);
+	strlcpy(ep->serial, brdid.serial, TI_EEPROM_HDR_SERIAL_LEN + 1);
+	ti_eeprom_string_cleanup(ep->serial);
+
+cleanup:
+	free(buffer);
+
+	return rc;
+}
+
+int __maybe_unused ti_i2c_eeprom_am_set(const char *name, const char *rev)
+{
+	struct ti_common_eeprom *ep;
+
+	if (!name || !rev)
+		return -1;
+
+	ep = TI_EEPROM_DATA;
+	if (ep->header == TI_EEPROM_HEADER_MAGIC)
+		goto already_set;
+
+	/* Set to 0 all fields */
+	memset(ep, 0, sizeof(*ep));
+	strncpy(ep->name, name, TI_EEPROM_HDR_NAME_LEN);
+	strncpy(ep->version, rev, TI_EEPROM_HDR_REV_LEN);
+	/* Some dummy serial number to identify the platform */
+	strncpy(ep->serial, "0000", TI_EEPROM_HDR_SERIAL_LEN);
+	/* Mark it with a valid header */
+	ep->header = TI_EEPROM_HEADER_MAGIC;
+
+already_set:
+	return 0;
+}
+
+int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
+{
+	int rc;
+	struct ti_am_eeprom am_ep;
+	struct ti_common_eeprom *ep;
+
+	ep = TI_EEPROM_DATA;
+#ifndef CONFIG_SPL_BUILD
+	if (ep->header == TI_EEPROM_HEADER_MAGIC)
+		return 0; /* EEPROM has already been read */
+#endif
+
+	/* Initialize with a known bad marker for i2c fails.. */
+	ep->header = TI_DEAD_EEPROM_MAGIC;
+	ep->name[0] = 0x0;
+	ep->version[0] = 0x0;
+	ep->serial[0] = 0x0;
+	ep->config[0] = 0x0;
+
+	rc = ti_i2c_eeprom_get(bus_addr, dev_addr, TI_EEPROM_HEADER_MAGIC,
+			       sizeof(am_ep), (uint8_t *)&am_ep);
+	if (rc)
+		return rc;
+
+	ep->header = am_ep.header;
+	strlcpy(ep->name, am_ep.name, TI_EEPROM_HDR_NAME_LEN + 1);
+	ti_eeprom_string_cleanup(ep->name);
+
+	/* BeagleBone Green '1' eeprom, board_rev: 0x1a 0x00 0x00 0x00 */
+	if (am_ep.version[0] == 0x1a && am_ep.version[1] == 0x00 &&
+	    am_ep.version[2] == 0x00 && am_ep.version[3] == 0x00)
+		strlcpy(ep->version, "BBG1", TI_EEPROM_HDR_REV_LEN + 1);
+	else
+		strlcpy(ep->version, am_ep.version, TI_EEPROM_HDR_REV_LEN + 1);
+	ti_eeprom_string_cleanup(ep->version);
+	strlcpy(ep->serial, am_ep.serial, TI_EEPROM_HDR_SERIAL_LEN + 1);
+	ti_eeprom_string_cleanup(ep->serial);
+	strlcpy(ep->config, am_ep.config, TI_EEPROM_HDR_CONFIG_LEN + 1);
+	ti_eeprom_string_cleanup(ep->config);
+
+	memcpy(ep->mac_addr, am_ep.mac_addr,
+	       TI_EEPROM_HDR_NO_OF_MAC_ADDR * TI_EEPROM_HDR_ETH_ALEN);
+
+	return 0;
+}
+
+int __maybe_unused ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr)
+{
+	int rc, offset = 0;
+	struct dra7_eeprom dra7_ep;
+	struct ti_common_eeprom *ep;
+
+	ep = TI_EEPROM_DATA;
+#ifndef CONFIG_SPL_BUILD
+	if (ep->header == DRA7_EEPROM_HEADER_MAGIC)
+		return 0; /* EEPROM has already been read */
+#endif
+
+	/* Initialize with a known bad marker for i2c fails.. */
+	ep->header = TI_DEAD_EEPROM_MAGIC;
+	ep->name[0] = 0x0;
+	ep->version[0] = 0x0;
+	ep->serial[0] = 0x0;
+	ep->config[0] = 0x0;
+	ep->emif1_size = 0;
+	ep->emif2_size = 0;
+
+	rc = ti_i2c_eeprom_get(bus_addr, dev_addr, DRA7_EEPROM_HEADER_MAGIC,
+			       sizeof(dra7_ep), (uint8_t *)&dra7_ep);
+	if (rc)
+		return rc;
+
+	ep->header = dra7_ep.header;
+	strlcpy(ep->name, dra7_ep.name, TI_EEPROM_HDR_NAME_LEN + 1);
+	ti_eeprom_string_cleanup(ep->name);
+
+	offset = dra7_ep.version_major - 1;
+
+	/* Rev F is skipped */
+	if (offset >= 5)
+		offset = offset + 1;
+	snprintf(ep->version, TI_EEPROM_HDR_REV_LEN + 1, "%c.%d",
+		 'A' + offset, dra7_ep.version_minor);
+	ti_eeprom_string_cleanup(ep->version);
+	ep->emif1_size = (u64)dra7_ep.emif1_size;
+	ep->emif2_size = (u64)dra7_ep.emif2_size;
+	strlcpy(ep->config, dra7_ep.config, TI_EEPROM_HDR_CONFIG_LEN + 1);
+	ti_eeprom_string_cleanup(ep->config);
+
+	return 0;
+}
+
+static int ti_i2c_eeprom_am6_parse_record(struct ti_am6_eeprom_record *record,
+					  struct ti_am6_eeprom *ep,
+					  char **mac_addr,
+					  u8 mac_addr_max_cnt,
+					  u8 *mac_addr_cnt)
+{
+	switch (record->header.id) {
+	case TI_AM6_EEPROM_RECORD_BOARD_INFO:
+		if (record->header.len != sizeof(record->data.board_info))
+			return -EINVAL;
+
+		if (!ep)
+			break;
+
+		/* Populate (and clean, if needed) the board name */
+		strlcpy(ep->name, record->data.board_info.name,
+			sizeof(ep->name));
+		ti_eeprom_string_cleanup(ep->name);
+
+		/* Populate selected other fields from the board info record */
+		strlcpy(ep->version, record->data.board_info.version,
+			sizeof(ep->version));
+		strlcpy(ep->software_revision,
+			record->data.board_info.software_revision,
+			sizeof(ep->software_revision));
+		strlcpy(ep->serial, record->data.board_info.serial,
+			sizeof(ep->serial));
+		break;
+	case TI_AM6_EEPROM_RECORD_MAC_INFO:
+		if (record->header.len != sizeof(record->data.mac_info))
+			return -EINVAL;
+
+		if (!mac_addr || !mac_addr_max_cnt)
+			break;
+
+		*mac_addr_cnt = ((record->data.mac_info.mac_control &
+				 TI_AM6_EEPROM_MAC_ADDR_COUNT_MASK) >>
+				 TI_AM6_EEPROM_MAC_ADDR_COUNT_SHIFT) + 1;
+
+		/*
+		 * The EEPROM can (but may not) hold a very large amount
+		 * of MAC addresses, by far exceeding what we want/can store
+		 * in the common memory array, so only grab what we can fit.
+		 * Note that a value of 0 means 1 MAC address, and so on.
+		 */
+		*mac_addr_cnt = min(*mac_addr_cnt, mac_addr_max_cnt);
+
+		memcpy(mac_addr, record->data.mac_info.mac_addr,
+		       *mac_addr_cnt * TI_EEPROM_HDR_ETH_ALEN);
+		break;
+	case 0x00:
+		/* Illegal value... Fall through... */
+	case 0xFF:
+		/* Illegal value... Something went horribly wrong... */
+		return -EINVAL;
+	default:
+		pr_warn("%s: Ignoring record id %u\n", __func__,
+			record->header.id);
+	}
+
+	return 0;
+}
+
+int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
+					 struct ti_am6_eeprom *ep,
+					 char **mac_addr,
+					 u8 mac_addr_max_cnt,
+					 u8 *mac_addr_cnt)
+{
+	struct udevice *dev;
+	struct udevice *bus;
+	unsigned int eeprom_addr;
+	struct ti_am6_eeprom_record_board_id board_id;
+	struct ti_am6_eeprom_record record;
+	int rc;
+
+	/* Initialize with a known bad marker for i2c fails.. */
+	memset(ep, 0, sizeof(*ep));
+	ep->header = TI_DEAD_EEPROM_MAGIC;
+
+	/* Read the board ID record which is always the first EEPROM record */
+	rc = ti_i2c_eeprom_get(bus_addr, dev_addr, TI_EEPROM_HEADER_MAGIC,
+			       sizeof(board_id), (uint8_t *)&board_id);
+	if (rc)
+		return rc;
+
+	if (board_id.header.id != TI_AM6_EEPROM_RECORD_BOARD_ID) {
+		pr_err("%s: Invalid board ID record!\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Establish DM handle to board config EEPROM */
+	rc = uclass_get_device_by_seq(UCLASS_I2C, bus_addr, &bus);
+	if (rc)
+		return rc;
+	rc = i2c_get_chip(bus, dev_addr, 1, &dev);
+	if (rc)
+		return rc;
+
+	ep->header = TI_EEPROM_HEADER_MAGIC;
+
+	/* Ready to parse TLV structure. Initialize variables... */
+	*mac_addr_cnt = 0;
+
+	/*
+	 * After the all-encompassing board ID record all other records follow
+	 * a TLV-type scheme. Point to the first such record and then start
+	 * parsing those one by one.
+	 */
+	eeprom_addr = sizeof(board_id);
+
+	while (true) {
+		rc = dm_i2c_read(dev, eeprom_addr, (uint8_t *)&record.header,
+				 sizeof(record.header));
+		if (rc)
+			return rc;
+
+		/*
+		 * Check for end of list marker. If we reached it don't go
+		 * any further and stop parsing right here.
+		 */
+		if (record.header.id == TI_AM6_EEPROM_RECORD_END_LIST)
+			break;
+
+		eeprom_addr += sizeof(record.header);
+
+		debug("%s: dev_addr=0x%02x header.id=%u header.len=%u\n",
+		      __func__, dev_addr, record.header.id,
+		      record.header.len);
+
+		/* Read record into memory if it fits */
+		if (record.header.len <= sizeof(record.data)) {
+			rc = dm_i2c_read(dev, eeprom_addr,
+					 (uint8_t *)&record.data,
+					 record.header.len);
+			if (rc)
+				return rc;
+
+			/* Process record */
+			rc = ti_i2c_eeprom_am6_parse_record(&record, ep,
+							    mac_addr,
+							    mac_addr_max_cnt,
+							    mac_addr_cnt);
+			if (rc) {
+				pr_err("%s: EEPROM parsing error!\n", __func__);
+				return rc;
+			}
+		} else {
+			/*
+			 * We may get here in case of larger records which
+			 * are not yet understood.
+			 */
+			pr_err("%s: Ignoring record id %u\n", __func__,
+			       record.header.id);
+		}
+
+		eeprom_addr += record.header.len;
+	}
+
+	return 0;
+}
+
+int __maybe_unused ti_i2c_eeprom_am6_get_base(int bus_addr, int dev_addr)
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+	int ret;
+
+	/*
+	 * Always execute EEPROM read by not allowing to bypass it during the
+	 * first invocation of SPL which happens on the R5 core.
+	 */
+#if !(defined(CONFIG_SPL_BUILD) && defined(CONFIG_CPU_V7R))
+	if (ep->header == TI_EEPROM_HEADER_MAGIC) {
+		debug("%s: EEPROM has already been read\n", __func__);
+		return 0;
+	}
+#endif
+
+	ret = ti_i2c_eeprom_am6_get(bus_addr, dev_addr, ep,
+				    (char **)ep->mac_addr,
+				    AM6_EEPROM_HDR_NO_OF_MAC_ADDR,
+				    &ep->mac_addr_cnt);
+	return ret;
+}
+
+bool __maybe_unused board_ti_k3_is(char *name_tag)
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+	if (ep->header == TI_DEAD_EEPROM_MAGIC)
+		return false;
+	return !strncmp(ep->name, name_tag, AM6_EEPROM_HDR_NAME_LEN);
+}
+
+bool __maybe_unused board_ti_is(char *name_tag)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header == TI_DEAD_EEPROM_MAGIC)
+		return false;
+	return !strncmp(ep->name, name_tag, TI_EEPROM_HDR_NAME_LEN);
+}
+
+bool __maybe_unused board_ti_rev_is(char *rev_tag, int cmp_len)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+	int l;
+
+	if (ep->header == TI_DEAD_EEPROM_MAGIC)
+		return false;
+
+	l = cmp_len > TI_EEPROM_HDR_REV_LEN ? TI_EEPROM_HDR_REV_LEN : cmp_len;
+	return !strncmp(ep->version, rev_tag, l);
+}
+
+char * __maybe_unused board_ti_get_rev(void)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	/* if ep->header == TI_DEAD_EEPROM_MAGIC, this is empty already */
+	return ep->version;
+}
+
+char * __maybe_unused board_ti_get_config(void)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	/* if ep->header == TI_DEAD_EEPROM_MAGIC, this is empty already */
+	return ep->config;
+}
+
+char * __maybe_unused board_ti_get_name(void)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	/* if ep->header == TI_DEAD_EEPROM_MAGIC, this is empty already */
+	return ep->name;
+}
+
+void __maybe_unused
+board_ti_get_eth_mac_addr(int index,
+			  u8 mac_addr[TI_EEPROM_HDR_ETH_ALEN])
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header == TI_DEAD_EEPROM_MAGIC)
+		goto fail;
+
+	if (index < 0 || index >= TI_EEPROM_HDR_NO_OF_MAC_ADDR)
+		goto fail;
+
+	memcpy(mac_addr, ep->mac_addr[index], TI_EEPROM_HDR_ETH_ALEN);
+	return;
+
+fail:
+	memset(mac_addr, 0, TI_EEPROM_HDR_ETH_ALEN);
+}
+
+void __maybe_unused
+board_ti_am6_get_eth_mac_addr(int index,
+			      u8 mac_addr[TI_EEPROM_HDR_ETH_ALEN])
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+	if (ep->header == TI_DEAD_EEPROM_MAGIC)
+		goto fail;
+
+	if (index < 0 || index >= ep->mac_addr_cnt)
+		goto fail;
+
+	memcpy(mac_addr, ep->mac_addr[index], TI_EEPROM_HDR_ETH_ALEN);
+	return;
+
+fail:
+	memset(mac_addr, 0, TI_EEPROM_HDR_ETH_ALEN);
+}
+
+u64 __maybe_unused board_ti_get_emif1_size(void)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header != DRA7_EEPROM_HEADER_MAGIC)
+		return 0;
+
+	return ep->emif1_size;
+}
+
+u64 __maybe_unused board_ti_get_emif2_size(void)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header != DRA7_EEPROM_HEADER_MAGIC)
+		return 0;
+
+	return ep->emif2_size;
+}
+
+void __maybe_unused set_board_info_env(char *name)
+{
+	char *unknown = "unknown";
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (name)
+		env_set("board_name", name);
+	else if (strlen(ep->name) != 0)
+		env_set("board_name", ep->name);
+	else
+		env_set("board_name", unknown);
+
+	if (strlen(ep->version) != 0)
+		env_set("board_rev", ep->version);
+	else
+		env_set("board_rev", unknown);
+
+	if (strlen(ep->serial) != 0)
+		env_set("board_serial", ep->serial);
+	else
+		env_set("board_serial", unknown);
+}
+
+void __maybe_unused set_board_info_env_am6(char *name)
+{
+	char *unknown = "unknown";
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+	if (name)
+		env_set("board_name", name);
+	else if (strlen(ep->name) != 0)
+		env_set("board_name", ep->name);
+	else
+		env_set("board_name", unknown);
+
+	if (strlen(ep->version) != 0)
+		env_set("board_rev", ep->version);
+	else
+		env_set("board_rev", unknown);
+
+	if (strlen(ep->software_revision) != 0)
+		env_set("board_software_revision", ep->software_revision);
+	else
+		env_set("board_software_revision", unknown);
+
+	if (strlen(ep->serial) != 0)
+		env_set("board_serial", ep->serial);
+	else
+		env_set("board_serial", unknown);
+}
+
+static u64 mac_to_u64(u8 mac[6])
+{
+	int i;
+	u64 addr = 0;
+
+	for (i = 0; i < 6; i++) {
+		addr <<= 8;
+		addr |= mac[i];
+	}
+
+	return addr;
+}
+
+static void u64_to_mac(u64 addr, u8 mac[6])
+{
+	mac[5] = addr;
+	mac[4] = addr >> 8;
+	mac[3] = addr >> 16;
+	mac[2] = addr >> 24;
+	mac[1] = addr >> 32;
+	mac[0] = addr >> 40;
+}
+
+void board_ti_set_ethaddr(int index)
+{
+	uint8_t mac_addr[6];
+	int i;
+	u64 mac1, mac2;
+	u8 mac_addr1[6], mac_addr2[6];
+	int num_macs;
+	/*
+	 * Export any Ethernet MAC addresses from EEPROM.
+	 * The 2 MAC addresses in EEPROM define the address range.
+	 */
+	board_ti_get_eth_mac_addr(0, mac_addr1);
+	board_ti_get_eth_mac_addr(1, mac_addr2);
+
+	if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
+		mac1 = mac_to_u64(mac_addr1);
+		mac2 = mac_to_u64(mac_addr2);
+
+		/* must contain an address range */
+		num_macs = mac2 - mac1 + 1;
+		if (num_macs <= 0)
+			return;
+
+		if (num_macs > 50) {
+			printf("%s: Too many MAC addresses: %d. Limiting to 50\n",
+			       __func__, num_macs);
+			num_macs = 50;
+		}
+
+		for (i = 0; i < num_macs; i++) {
+			u64_to_mac(mac1 + i, mac_addr);
+			if (is_valid_ethaddr(mac_addr)) {
+				eth_env_set_enetaddr_by_index("eth", i + index,
+							      mac_addr);
+			}
+		}
+	}
+}
+
+void board_ti_am6_set_ethaddr(int index, int count)
+{
+	u8 mac_addr[6];
+	int i;
+
+	for (i = 0; i < count; i++) {
+		board_ti_am6_get_eth_mac_addr(i, mac_addr);
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr_by_index("eth", i + index,
+						      mac_addr);
+	}
+}
+
+bool __maybe_unused board_ti_was_eeprom_read(void)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header == TI_EEPROM_HEADER_MAGIC)
+		return true;
+	else
+		return false;
+}
diff --git a/roms/u-boot/board/ti/common/board_detect.h b/roms/u-boot/board/ti/common/board_detect.h
new file mode 100644
index 000000000..de7cb52df
--- /dev/null
+++ b/roms/u-boot/board/ti/common/board_detect.h
@@ -0,0 +1,471 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Library to support early TI EVM EEPROM handling
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com
+ */
+
+#ifndef __BOARD_DETECT_H
+#define __BOARD_DETECT_H
+
+/* TI EEPROM MAGIC Header identifier */
+#include <linux/bitops.h>
+#define TI_EEPROM_HEADER_MAGIC	0xEE3355AA
+#define TI_DEAD_EEPROM_MAGIC	0xADEAD12C
+
+#define TI_EEPROM_HDR_NAME_LEN		8
+#define TI_EEPROM_HDR_REV_LEN		4
+#define TI_EEPROM_HDR_SERIAL_LEN	12
+#define TI_EEPROM_HDR_CONFIG_LEN	32
+#define TI_EEPROM_HDR_NO_OF_MAC_ADDR	3
+#define TI_EEPROM_HDR_ETH_ALEN		6
+
+/**
+ * struct ti_am_eeprom - This structure holds data read in from the
+ *                     AM335x, AM437x, AM57xx TI EVM EEPROMs.
+ * @header: This holds the magic number
+ * @name: The name of the board
+ * @version: Board revision
+ * @serial: Board serial number
+ * @config: Reserved
+ * @mac_addr: Any MAC addresses written in the EEPROM
+ *
+ * The data is this structure is read from the EEPROM on the board.
+ * It is used for board detection which is based on name. It is used
+ * to configure specific TI boards. This allows booting of multiple
+ * TI boards with a single MLO and u-boot.
+ */
+struct ti_am_eeprom {
+	unsigned int header;
+	char name[TI_EEPROM_HDR_NAME_LEN];
+	char version[TI_EEPROM_HDR_REV_LEN];
+	char serial[TI_EEPROM_HDR_SERIAL_LEN];
+	char config[TI_EEPROM_HDR_CONFIG_LEN];
+	char mac_addr[TI_EEPROM_HDR_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+} __attribute__ ((__packed__));
+
+/* AM6x TI EVM EEPROM Definitions */
+#define TI_AM6_EEPROM_RECORD_BOARD_ID		0x01
+#define TI_AM6_EEPROM_RECORD_BOARD_INFO		0x10
+#define TI_AM6_EEPROM_RECORD_DDR_INFO		0x11
+#define TI_AM6_EEPROM_RECORD_DDR_SPD		0x12
+#define TI_AM6_EEPROM_RECORD_MAC_INFO		0x13
+#define TI_AM6_EEPROM_RECORD_END_LIST		0xFE
+
+/*
+ * Common header for AM6x TI EVM EEPROM records. Used to encapsulate the config
+ * EEPROM in its entirety as well as for individual records contained within.
+ */
+struct ti_am6_eeprom_record_header {
+	u8 id;
+	u16 len;
+} __attribute__ ((__packed__));
+
+/* AM6x TI EVM EEPROM board ID structure */
+struct ti_am6_eeprom_record_board_id {
+	u32 magic_number;
+	struct ti_am6_eeprom_record_header header;
+} __attribute__ ((__packed__));
+
+/* AM6x TI EVM EEPROM board info structure */
+#define AM6_EEPROM_HDR_NAME_LEN			16
+#define AM6_EEPROM_HDR_VERSION_LEN		2
+#define AM6_EEPROM_HDR_PROC_NR_LEN		4
+#define AM6_EEPROM_HDR_VARIANT_LEN		2
+#define AM6_EEPROM_HDR_PCB_REV_LEN		2
+#define AM6_EEPROM_HDR_SCH_BOM_REV_LEN		2
+#define AM6_EEPROM_HDR_SW_REV_LEN		2
+#define AM6_EEPROM_HDR_VID_LEN			2
+#define AM6_EEPROM_HDR_BLD_WK_LEN		2
+#define AM6_EEPROM_HDR_BLD_YR_LEN		2
+#define AM6_EEPROM_HDR_4P_NR_LEN		6
+#define AM6_EEPROM_HDR_SERIAL_LEN		4
+
+struct ti_am6_eeprom_record_board_info {
+	char name[AM6_EEPROM_HDR_NAME_LEN];
+	char version[AM6_EEPROM_HDR_VERSION_LEN];
+	char proc_number[AM6_EEPROM_HDR_PROC_NR_LEN];
+	char variant[AM6_EEPROM_HDR_VARIANT_LEN];
+	char pcb_revision[AM6_EEPROM_HDR_PCB_REV_LEN];
+	char schematic_bom_revision[AM6_EEPROM_HDR_SCH_BOM_REV_LEN];
+	char software_revision[AM6_EEPROM_HDR_SW_REV_LEN];
+	char vendor_id[AM6_EEPROM_HDR_VID_LEN];
+	char build_week[AM6_EEPROM_HDR_BLD_WK_LEN];
+	char build_year[AM6_EEPROM_HDR_BLD_YR_LEN];
+	char board_4p_number[AM6_EEPROM_HDR_4P_NR_LEN];
+	char serial[AM6_EEPROM_HDR_SERIAL_LEN];
+} __attribute__ ((__packed__));
+
+/* Memory location to keep a copy of the AM6 board info record */
+#define TI_AM6_EEPROM_BD_INFO_DATA ((struct ti_am6_eeprom_record_board_info *) \
+					     TI_SRAM_SCRATCH_BOARD_EEPROM_START)
+
+/* AM6x TI EVM EEPROM DDR info structure */
+#define TI_AM6_EEPROM_DDR_CTRL_INSTANCE_MASK		GENMASK(1, 0)
+#define TI_AM6_EEPROM_DDR_CTRL_INSTANCE_SHIFT		0
+#define TI_AM6_EEPROM_DDR_CTRL_SPD_DATA_LOC_MASK	GENMASK(3, 2)
+#define TI_AM6_EEPROM_DDR_CTRL_SPD_DATA_LOC_NA		(0 << 2)
+#define TI_AM6_EEPROM_DDR_CTRL_SPD_DATA_LOC_BOARDID	(2 << 2)
+#define TI_AM6_EEPROM_DDR_CTRL_SPD_DATA_LOC_I2C51	(3 << 2)
+#define TI_AM6_EEPROM_DDR_CTRL_MEM_TYPE_MASK		GENMASK(5, 4)
+#define TI_AM6_EEPROM_DDR_CTRL_MEM_TYPE_DDR3		(0 << 4)
+#define TI_AM6_EEPROM_DDR_CTRL_MEM_TYPE_DDR4		(1 << 4)
+#define TI_AM6_EEPROM_DDR_CTRL_MEM_TYPE_LPDDR4		(2 << 4)
+#define TI_AM6_EEPROM_DDR_CTRL_IF_DATA_WIDTH_MASK	GENMASK(7, 6)
+#define TI_AM6_EEPROM_DDR_CTRL_IF_DATA_WIDTH_16		(0 << 6)
+#define TI_AM6_EEPROM_DDR_CTRL_IF_DATA_WIDTH_32		(1 << 6)
+#define TI_AM6_EEPROM_DDR_CTRL_IF_DATA_WIDTH_64		(2 << 6)
+#define TI_AM6_EEPROM_DDR_CTRL_DEV_DATA_WIDTH_MASK	GENMASK(9, 8)
+#define TI_AM6_EEPROM_DDR_CTRL_DEV_DATA_WIDTH_8		(0 << 8)
+#define TI_AM6_EEPROM_DDR_CTRL_DEV_DATA_WIDTH_16	(1 << 8)
+#define TI_AM6_EEPROM_DDR_CTRL_DEV_DATA_WIDTH_32	(2 << 8)
+#define TI_AM6_EEPROM_DDR_CTRL_RANKS_2			BIT(10)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_MASK		GENMASK(13, 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_1GB			(0 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_2GB			(1 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_4GB			(2 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_8GB			(3 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_12GB		(4 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_16GB		(5 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_24GB		(6 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_32GB		(7 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_ECC			BIT(14)
+
+struct ti_am6_eeprom_record_ddr_info {
+	u16 ddr_control;
+} __attribute__ ((__packed__));
+
+/* AM6x TI EVM EEPROM DDR SPD structure */
+#define TI_AM6_EEPROM_DDR_SPD_INSTANCE_MASK		GENMASK(1, 0)
+#define TI_AM6_EEPROM_DDR_SPD_INSTANCE_SHIFT		0
+#define TI_AM6_EEPROM_DDR_SPD_MEM_TYPE_MASK		GENMASK(4, 3)
+#define TI_AM6_EEPROM_DDR_SPD_MEM_TYPE_DDR3		(0 << 3)
+#define TI_AM6_EEPROM_DDR_SPD_MEM_TYPE_DDR4		(1 << 3)
+#define TI_AM6_EEPROM_DDR_SPD_MEM_TYPE_LPDDR4		(2 << 3)
+#define TI_AM6_EEPROM_DDR_SPD_DATA_LEN			512
+
+struct ti_am6_eeprom_record_ddr_spd {
+	u16 spd_control;
+	u8 data[TI_AM6_EEPROM_DDR_SPD_DATA_LEN];
+} __attribute__ ((__packed__));
+
+/* AM6x TI EVM EEPROM MAC info structure */
+#define TI_AM6_EEPROM_MAC_INFO_INSTANCE_MASK		GENMASK(2, 0)
+#define TI_AM6_EEPROM_MAC_INFO_INSTANCE_SHIFT		0
+#define TI_AM6_EEPROM_MAC_ADDR_COUNT_MASK		GENMASK(7, 3)
+#define TI_AM6_EEPROM_MAC_ADDR_COUNT_SHIFT		3
+#define TI_AM6_EEPROM_MAC_ADDR_MAX_COUNT		32
+
+struct ti_am6_eeprom_record_mac_info {
+	u16 mac_control;
+	u8 mac_addr[TI_AM6_EEPROM_MAC_ADDR_MAX_COUNT][TI_EEPROM_HDR_ETH_ALEN];
+} __attribute__ ((__packed__));
+
+struct ti_am6_eeprom_record {
+	struct ti_am6_eeprom_record_header header;
+	union {
+		struct ti_am6_eeprom_record_board_info board_info;
+		struct ti_am6_eeprom_record_ddr_info ddr_info;
+		struct ti_am6_eeprom_record_ddr_spd ddr_spd;
+		struct ti_am6_eeprom_record_mac_info mac_info;
+	} data;
+} __attribute__ ((__packed__));
+
+/* DRA7 EEPROM MAGIC Header identifier */
+#define DRA7_EEPROM_HEADER_MAGIC	0xAA5533EE
+#define DRA7_EEPROM_HDR_NAME_LEN	16
+#define DRA7_EEPROM_HDR_CONFIG_LEN	4
+
+/**
+ * struct dra7_eeprom - This structure holds data read in from the DRA7 EVM
+ *			EEPROMs.
+ * @header: This holds the magic number
+ * @name: The name of the board
+ * @version_major: Board major version
+ * @version_minor: Board minor version
+ * @config: Board specific config options
+ * @emif1_size: Size of DDR attached to EMIF1
+ * @emif2_size: Size of DDR attached to EMIF2
+ *
+ * The data is this structure is read from the EEPROM on the board.
+ * It is used for board detection which is based on name. It is used
+ * to configure specific DRA7 boards. This allows booting of multiple
+ * DRA7 boards with a single MLO and u-boot.
+ */
+struct dra7_eeprom {
+	u32 header;
+	char name[DRA7_EEPROM_HDR_NAME_LEN];
+	u16 version_major;
+	u16 version_minor;
+	char config[DRA7_EEPROM_HDR_CONFIG_LEN];
+	u32 emif1_size;
+	u32 emif2_size;
+} __attribute__ ((__packed__));
+
+/**
+ * struct ti_common_eeprom - Null terminated, usable EEPROM contents.
+ * header:	Magic number
+ * @name:	NULL terminated name
+ * @version:	NULL terminated version
+ * @serial:	NULL terminated serial number
+ * @config:	NULL terminated Board specific config options
+ * @mac_addr:	MAC addresses
+ * @emif1_size:	Size of the ddr available on emif1
+ * @emif2_size:	Size of the ddr available on emif2
+ */
+struct ti_common_eeprom {
+	u32 header;
+	char name[TI_EEPROM_HDR_NAME_LEN + 1];
+	char version[TI_EEPROM_HDR_REV_LEN + 1];
+	char serial[TI_EEPROM_HDR_SERIAL_LEN + 1];
+	char config[TI_EEPROM_HDR_CONFIG_LEN + 1];
+	char mac_addr[TI_EEPROM_HDR_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+	u64 emif1_size;
+	u64 emif2_size;
+};
+
+#define TI_EEPROM_DATA ((struct ti_common_eeprom *)\
+				TI_SRAM_SCRATCH_BOARD_EEPROM_START)
+
+/*
+ * Maximum number of Ethernet MAC addresses extracted from the AM6x on-board
+ * EEPROM during the initial probe and carried forward in SRAM.
+ */
+#define AM6_EEPROM_HDR_NO_OF_MAC_ADDR	8
+
+/**
+ * struct ti_am6_eeprom - Null terminated, usable EEPROM contents, as extracted
+ *	from the AM6 on-board EEPROM. Note that we only carry a subset of data
+ *	at this time to be considerate about memory consumption.
+ * @header:		Magic number for data validity indication
+ * @name:		NULL terminated name
+ * @version:		NULL terminated version
+ * @software_revision:	NULL terminated software revision
+ * @serial:		Board serial number
+ * @mac_addr_cnt:	Number of MAC addresses stored in this object
+ * @mac_addr:		MAC addresses
+ */
+struct ti_am6_eeprom {
+	u32 header;
+	char name[AM6_EEPROM_HDR_NAME_LEN + 1];
+	char version[AM6_EEPROM_HDR_VERSION_LEN + 1];
+	char software_revision[AM6_EEPROM_HDR_SW_REV_LEN + 1];
+	char serial[AM6_EEPROM_HDR_SERIAL_LEN + 1];
+	u8 mac_addr_cnt;
+	char mac_addr[AM6_EEPROM_HDR_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+};
+
+#define TI_AM6_EEPROM_DATA ((struct ti_am6_eeprom *) \
+				TI_SRAM_SCRATCH_BOARD_EEPROM_START)
+
+/**
+ * ti_i2c_eeprom_am_get() - Consolidated eeprom data collection for AM* TI EVMs
+ * @bus_addr:	I2C bus address
+ * @dev_addr:	I2C slave address
+ *
+ * ep in SRAM is populated by the this AM generic function that consolidates
+ * the basic initialization logic common across all AM* platforms.
+ */
+int ti_i2c_eeprom_am_get(int bus_addr, int dev_addr);
+
+/**
+ * ti_emmc_boardid_get() - Fetch board ID information from eMMC
+ *
+ * ep in SRAM is populated by the this function that is currently
+ * based on BeagleBone AI, but could be made more general across AM*
+ * platforms.
+ */
+int __maybe_unused ti_emmc_boardid_get(void);
+
+/**
+ * ti_i2c_eeprom_dra7_get() - Consolidated eeprom data for DRA7 TI EVMs
+ * @bus_addr:	I2C bus address
+ * @dev_addr:	I2C slave address
+ */
+int ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr);
+
+/**
+ * ti_i2c_eeprom_am6_get() - Consolidated eeprom data for AM6x TI EVMs and
+ *			     associated daughter cards, parsed into user-
+ *			     provided data structures
+ * @bus_addr:	I2C bus address
+ * @dev_addr:	I2C slave address
+ * @ep:		Pointer to structure receiving AM6-specific header data
+ * @mac_addr:	Pointer to memory receiving parsed MAC addresses. May be
+ *		NULL to skip MAC parsing.
+ * @mac_addr_max_cnt: Maximum number of MAC addresses that can be stored into
+ *		      mac_addr. May be NULL to skip MAC parsing.
+ * @mac_addr_cnt: Pointer to a location returning how many MAC addressed got
+ *		  actually parsed.
+ */
+int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
+					 struct ti_am6_eeprom *ep,
+					 char **mac_addr,
+					 u8 mac_addr_max_cnt,
+					 u8 *mac_addr_cnt);
+
+/**
+ * ti_i2c_eeprom_am6_get_base() - Consolidated eeprom data for AM6x TI EVMs
+ * @bus_addr:	I2C bus address
+ * @dev_addr:	I2C slave address
+ */
+int __maybe_unused ti_i2c_eeprom_am6_get_base(int bus_addr, int dev_addr);
+
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+/**
+ * board_ti_is() - Board detection logic for TI EVMs
+ * @name_tag:	Tag used in eeprom for the board
+ *
+ * Return: false if board information does not match OR eeprom wasn't read.
+ *	   true otherwise
+ */
+bool board_ti_is(char *name_tag);
+
+/**
+ * board_ti_k3_is() - Board detection logic for TI K3 EVMs
+ * @name_tag:	Tag used in eeprom for the board
+ *
+ * Return: false if board information does not match OR eeprom wasn't read.
+ *	   true otherwise
+ */
+bool board_ti_k3_is(char *name_tag);
+
+/**
+ * board_ti_rev_is() - Compare board revision for TI EVMs
+ * @rev_tag:	Revision tag to check in eeprom
+ * @cmp_len:	How many chars to compare?
+ *
+ * NOTE: revision information is often messed up (hence the str len match) :(
+ *
+ * Return: false if board information does not match OR eeprom wasn't read.
+ *	   true otherwise
+ */
+bool board_ti_rev_is(char *rev_tag, int cmp_len);
+
+/**
+ * board_ti_get_rev() - Get board revision for TI EVMs
+ *
+ * Return: Empty string if eeprom wasn't read.
+ *	   Board revision otherwise
+ */
+char *board_ti_get_rev(void);
+
+/**
+ * board_ti_get_config() - Get board config for TI EVMs
+ *
+ * Return: Empty string if eeprom wasn't read.
+ *	   Board config otherwise
+ */
+char *board_ti_get_config(void);
+
+/**
+ * board_ti_get_name() - Get board name for TI EVMs
+ *
+ * Return: Empty string if eeprom wasn't read.
+ *	   Board name otherwise
+ */
+char *board_ti_get_name(void);
+
+/**
+ * board_ti_get_eth_mac_addr() - Get Ethernet MAC address from EEPROM MAC list
+ * @index:	0 based index within the list of MAC addresses
+ * @mac_addr:	MAC address contained at the index is returned here
+ *
+ * Does not sanity check the mac_addr. Whatever is stored in EEPROM is returned.
+ */
+void board_ti_get_eth_mac_addr(int index, u8 mac_addr[TI_EEPROM_HDR_ETH_ALEN]);
+
+/**
+ * board_ti_get_emif1_size() - Get size of the DDR on emif1 for TI EVMs
+ *
+ * Return: NULL if eeprom wasn't read or emif1_size is not available.
+ */
+u64 board_ti_get_emif1_size(void);
+
+/**
+ * board_ti_get_emif2_size() - Get size of the DDR on emif2 for TI EVMs
+ *
+ * Return: NULL if eeprom wasn't read or emif2_size is not available.
+ */
+u64 board_ti_get_emif2_size(void);
+
+/**
+ * set_board_info_env() - Setup commonly used board information environment vars
+ * @name:	Name of the board
+ *
+ * If name is NULL, default_name is used.
+ */
+void set_board_info_env(char *name);
+
+/**
+ * set_board_info_env_am6() - Setup commonly used board information environment
+ *			      vars for AM6-type boards
+ * @name:	Name of the board
+ *
+ * If name is NULL, default_name is used.
+ */
+void set_board_info_env_am6(char *name);
+
+/**
+ * board_ti_set_ethaddr- Sets the ethaddr environment from EEPROM
+ * @index: The first eth<index>addr environment variable to set
+ *
+ * EEPROM should be already read before calling this function.
+ * The EEPROM contains 2 MAC addresses which define the MAC address
+ * range (i.e. first and last MAC address).
+ * This function sets the ethaddr environment variable for all
+ * the available MAC addresses starting from eth<index>addr.
+ */
+void board_ti_set_ethaddr(int index);
+
+/**
+ * board_ti_am6_set_ethaddr- Sets the ethaddr environment from EEPROM
+ * @index: The first eth<index>addr environment variable to set
+ * @count: The number of MAC addresses to process
+ *
+ * EEPROM should be already read before calling this function. The EEPROM
+ * contains n dedicated MAC addresses. This function sets the ethaddr
+ * environment variable for all the available MAC addresses starting
+ * from eth<index>addr.
+ */
+void board_ti_am6_set_ethaddr(int index, int count);
+
+/**
+ * board_ti_was_eeprom_read() - Check to see if the eeprom contents have been read
+ *
+ * This function is useful to determine if the eeprom has already been read and
+ * its contents have already been loaded into memory. It utiltzes the magic
+ * number that the header value is set to upon successful eeprom read.
+ */
+bool board_ti_was_eeprom_read(void);
+
+/**
+ * ti_i2c_eeprom_am_set() - Setup the eeprom data with predefined values
+ * @name:	Name of the board
+ * @rev:	Revision of the board
+ *
+ * In some cases such as in RTC-only mode, we are able to skip reading eeprom
+ * and wasting i2c based initialization time by using predefined flags for
+ * detecting what platform we are booting on. For those platforms, provide
+ * a handy function to pre-program information.
+ *
+ * NOTE: many eeprom information such as serial number, mac address etc is not
+ * available.
+ *
+ * Return: 0 if all went fine, else return error.
+ */
+int ti_i2c_eeprom_am_set(const char *name, const char *rev);
+#else
+static inline bool board_ti_is(char *name_tag) { return false; };
+static inline bool board_ti_k3_is(char *name_tag) { return false; };
+static inline bool board_ti_rev_is(char *rev_tag, int cmp_len)
+{ return false; };
+static inline char *board_ti_get_rev(void) { return NULL; };
+static inline char *board_ti_get_config(void) { return NULL; };
+static inline char *board_ti_get_name(void) { return NULL; };
+static inline bool board_ti_was_eeprom_read(void) { return false; };
+static inline int ti_i2c_eeprom_am_set(const char *name, const char *rev)
+{ return -EINVAL; };
+#endif
+
+#endif	/* __BOARD_DETECT_H */
diff --git a/roms/u-boot/board/ti/common/cape_detect.c b/roms/u-boot/board/ti/common/cape_detect.c
new file mode 100644
index 000000000..2e6105cfb
--- /dev/null
+++ b/roms/u-boot/board/ti/common/cape_detect.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021
+ * Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <extension_board.h>
+
+#include "cape_detect.h"
+
+static void sanitize_field(char *text, size_t size)
+{
+	char *c = NULL;
+
+	for (c = text; c < text + (int)size; c++) {
+		if (*c == 0xFF)
+			*c = 0;
+	}
+}
+
+int extension_board_scan(struct list_head *extension_list)
+{
+	struct extension *cape;
+	struct am335x_cape_eeprom_id eeprom_header;
+
+	int num_capes = 0;
+	int ret, i;
+	struct udevice *dev;
+	unsigned char addr;
+
+	char process_cape_part_number[17] = {'0'};
+	char process_cape_version[5] = {'0'};
+	uint8_t cursor = 0;
+
+	for (addr = CAPE_EEPROM_FIRST_ADDR; addr <= CAPE_EEPROM_LAST_ADDR; addr++) {
+		ret = i2c_get_chip_for_busnum(CONFIG_CAPE_EEPROM_BUS_NUM, addr, 1, &dev);
+		if (ret)
+			continue;
+
+		/* Move the read cursor to the beginning of the EEPROM */
+		dm_i2c_write(dev, 0, &cursor, 1);
+		ret = dm_i2c_read(dev, 0, (uint8_t *)&eeprom_header,
+				  sizeof(struct am335x_cape_eeprom_id));
+		if (ret) {
+			printf("Cannot read i2c EEPROM\n");
+			continue;
+		}
+
+		if (eeprom_header.header != CAPE_MAGIC)
+			continue;
+
+		sanitize_field(eeprom_header.board_name, sizeof(eeprom_header.board_name));
+		sanitize_field(eeprom_header.version, sizeof(eeprom_header.version));
+		sanitize_field(eeprom_header.manufacturer, sizeof(eeprom_header.manufacturer));
+		sanitize_field(eeprom_header.part_number, sizeof(eeprom_header.part_number));
+
+		/* Process cape part_number */
+		memset(process_cape_part_number, 0, sizeof(process_cape_part_number));
+		strncpy(process_cape_part_number, eeprom_header.part_number, 16);
+		/* Some capes end with '.' */
+		for (i = 15; i >= 0; i--) {
+			if (process_cape_part_number[i] == '.')
+				process_cape_part_number[i] = '\0';
+			else
+				break;
+		}
+
+		/* Process cape version */
+		memset(process_cape_version, 0, sizeof(process_cape_version));
+		strncpy(process_cape_version, eeprom_header.version, 4);
+		for (i = 0; i < 4; i++) {
+			if (process_cape_version[i] == 0)
+				process_cape_version[i] = '0';
+		}
+
+		printf("BeagleBone Cape: %s (0x%x)\n", eeprom_header.board_name, addr);
+
+		cape = calloc(1, sizeof(struct extension));
+		if (!cape) {
+			printf("Error in memory allocation\n");
+			return num_capes;
+		}
+
+		snprintf(cape->overlay, sizeof(cape->overlay), "%s-%s.dtbo",
+			 process_cape_part_number, process_cape_version);
+		strncpy(cape->name, eeprom_header.board_name, 32);
+		strncpy(cape->version, process_cape_version, 4);
+		strncpy(cape->owner, eeprom_header.manufacturer, 16);
+		list_add_tail(&cape->list, extension_list);
+		num_capes++;
+	}
+	return num_capes;
+}
diff --git a/roms/u-boot/board/ti/common/cape_detect.h b/roms/u-boot/board/ti/common/cape_detect.h
new file mode 100644
index 000000000..b0d5c9f18
--- /dev/null
+++ b/roms/u-boot/board/ti/common/cape_detect.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021
+ * Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
+ */
+
+#ifndef __CAPE_DETECT_H
+#define __CAPE_DETECT_H
+
+struct am335x_cape_eeprom_id {
+	unsigned int header;
+	char eeprom_rev[2];
+	char board_name[32];
+	char version[4];
+	char manufacturer[16];
+	char part_number[16];
+};
+
+#define CAPE_EEPROM_FIRST_ADDR	0x54
+#define CAPE_EEPROM_LAST_ADDR	0x57
+
+#define CAPE_EEPROM_ADDR_LEN 0x10
+
+#define CAPE_MAGIC 0xEE3355AA
+
+int extension_board_scan(struct list_head *extension_list);
+
+#endif /* __CAPE_DETECT_H */
diff --git a/roms/u-boot/board/ti/dra7xx/Kconfig b/roms/u-boot/board/ti/dra7xx/Kconfig
new file mode 100644
index 000000000..f6a8e07c5
--- /dev/null
+++ b/roms/u-boot/board/ti/dra7xx/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_DRA7XX_EVM
+
+config SYS_BOARD
+	default "dra7xx"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_CONFIG_NAME
+	default "dra7xx_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/ti/dra7xx/MAINTAINERS b/roms/u-boot/board/ti/dra7xx/MAINTAINERS
new file mode 100644
index 000000000..46b6e82b3
--- /dev/null
+++ b/roms/u-boot/board/ti/dra7xx/MAINTAINERS
@@ -0,0 +1,7 @@
+DRA7XX BOARD
+M:	Lokesh Vutla <lokeshvutla@ti.com>
+S:	Maintained
+F:	board/ti/dra7xx/
+F:	include/configs/dra7xx_evm.h
+F:	configs/dra7xx_evm_defconfig
+F:	configs/dra7xx_hs_evm_defconfig
diff --git a/roms/u-boot/board/ti/dra7xx/Makefile b/roms/u-boot/board/ti/dra7xx/Makefile
new file mode 100644
index 000000000..8d0ca56ad
--- /dev/null
+++ b/roms/u-boot/board/ti/dra7xx/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2013
+# Texas Instruments, <www.ti.com>
+
+obj-y	:= evm.o
diff --git a/roms/u-boot/board/ti/dra7xx/README b/roms/u-boot/board/ti/dra7xx/README
new file mode 100644
index 000000000..533da01a3
--- /dev/null
+++ b/roms/u-boot/board/ti/dra7xx/README
@@ -0,0 +1,26 @@
+Summary
+=======
+
+This document covers various features of the 'dra7xx_evm' build and some
+related uses.
+
+eMMC boot partition use
+=======================
+
+It is possible, depending on SYSBOOT configuration to boot from the eMMC
+boot partitions using (name depending on documentation referenced)
+Alternative Boot operation mode or Boot Sequence Option 1/2.  In this
+example we load MLO and u-boot.img from the build into DDR and then use
+'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
+set boot0 as the boot device.
+U-Boot # setenv autoload no
+U-Boot # usb start
+U-Boot # dhcp
+U-Boot # mmc dev 1 1
+U-Boot # tftp ${loadaddr} dra7xx/MLO
+U-Boot # mmc write ${loadaddr} 0 100
+U-Boot # tftp ${loadaddr} dra7xx/u-boot.img
+U-Boot # mmc write ${loadaddr} 300 400
+U-Boot # mmc bootbus 1 2 0 2
+U-Boot # mmc partconf 1 1 1 0
+U-Boot # mmc rst-function 1 1
diff --git a/roms/u-boot/board/ti/dra7xx/evm.c b/roms/u-boot/board/ti/dra7xx/evm.c
new file mode 100644
index 000000000..05f251f77
--- /dev/null
+++ b/roms/u-boot/board/ti/dra7xx/evm.c
@@ -0,0 +1,1079 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * Based on previous work by:
+ * Aneesh V       <aneesh@ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ */
+#include <common.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <fastboot.h>
+#include <image.h>
+#include <init.h>
+#include <spl.h>
+#include <net.h>
+#include <palmas.h>
+#include <sata.h>
+#include <serial.h>
+#include <asm/global_data.h>
+#include <linux/string.h>
+#include <asm/gpio.h>
+#include <usb.h>
+#include <linux/usb/gadget.h>
+#include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/dra7xx_iodelay.h>
+#include <asm/emif.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sata.h>
+#include <dwc3-uboot.h>
+#include <dwc3-omap-uboot.h>
+#include <i2c.h>
+#include <ti-usb-phy-uboot.h>
+
+#include "mux_data.h"
+#include "../common/board_detect.h"
+
+#define board_is_dra76x_evm()		board_ti_is("DRA76/7x")
+#define board_is_dra74x_evm()		board_ti_is("5777xCPU")
+#define board_is_dra72x_evm()		board_ti_is("DRA72x-T")
+#define board_is_dra71x_evm()		board_ti_is("DRA79x,D")
+#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() &&	\
+				(strncmp("H", board_ti_get_rev(), 1) <= 0))
+#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() &&	\
+				(strncmp("C", board_ti_get_rev(), 1) <= 0))
+#define board_ti_get_emif_size()	board_ti_get_emif1_size() +	\
+					board_ti_get_emif2_size()
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO 7_11 */
+#define GPIO_DDR_VTT_EN 203
+
+#define SYSINFO_BOARD_NAME_MAX_LEN	37
+
+/* I2C I/O Expander */
+#define NAND_PCF8575_ADDR	0x21
+#define NAND_PCF8575_I2C_BUS_NUM	0
+
+const struct omap_sysinfo sysinfo = {
+	"Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
+};
+
+static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
+	.sdram_config_init              = 0x61851ab2,
+	.sdram_config                   = 0x61851ab2,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl                       = 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1                     = 0xCCCF36B3,
+	.sdram_tim2                     = 0x308F7FDA,
+	.sdram_tim3                     = 0x427F88A8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x0007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
+	.sdram_config_init              = 0x61851B32,
+	.sdram_config                   = 0x61851B32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl                       = 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1                     = 0xCCCF36B3,
+	.sdram_tim2                     = 0x308F7FDA,
+	.sdram_tim3                     = 0x427F88A8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x0007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
+	.sdram_config_init              = 0x61862B32,
+	.sdram_config                   = 0x61862B32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl                       = 0x0000514C,
+	.ref_ctrl_final			= 0x0000144A,
+	.sdram_tim1                     = 0xD113781C,
+	.sdram_tim2                     = 0x30717FE3,
+	.sdram_tim3                     = 0x409F86A8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x5007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400D,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400D,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
+	.emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
+	.sdram_config_init              = 0x61862BB2,
+	.sdram_config                   = 0x61862BB2,
+	.sdram_config2			= 0x00000000,
+	.ref_ctrl                       = 0x0000514D,
+	.ref_ctrl_final			= 0x0000144A,
+	.sdram_tim1                     = 0xD1137824,
+	.sdram_tim2                     = 0x30B37FE3,
+	.sdram_tim3                     = 0x409F8AD8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x5007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0824400E,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400E,
+	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
+	.emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
+	.emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
+	.emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
+	.sdram_config_init              = 0x61851ab2,
+	.sdram_config                   = 0x61851ab2,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl                       = 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1                     = 0xCCCF36B3,
+	.sdram_tim2                     = 0x30BF7FDA,
+	.sdram_tim3                     = 0x427F8BA8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x0007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
+	.sdram_config_init              = 0x61851B32,
+	.sdram_config                   = 0x61851B32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl                       = 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1                     = 0xCCCF36B3,
+	.sdram_tim2                     = 0x308F7FDA,
+	.sdram_tim3                     = 0x427F88A8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x0007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
+	.sdram_config_init              = 0x61862B32,
+	.sdram_config                   = 0x61862B32,
+	.sdram_config2			= 0x00000000,
+	.ref_ctrl                       = 0x0000514C,
+	.ref_ctrl_final			= 0x0000144A,
+	.sdram_tim1                     = 0xD113783C,
+	.sdram_tim2                     = 0x30B47FE3,
+	.sdram_tim3                     = 0x409F8AD8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x5007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0824400D,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400D,
+	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
+	.emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
+	.emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
+	.emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
+	.sdram_config_init              = 0x61862B32,
+	.sdram_config                   = 0x61862B32,
+	.sdram_config2			= 0x00000000,
+	.ref_ctrl                       = 0x0000514C,
+	.ref_ctrl_final			= 0x0000144A,
+	.sdram_tim1                     = 0xD113781C,
+	.sdram_tim2                     = 0x30B47FE3,
+	.sdram_tim3                     = 0x409F8AD8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x5007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0824400D,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400D,
+	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
+	.emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
+	.emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
+	.emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+	u64 ram_size;
+
+	ram_size = board_ti_get_emif_size();
+
+	switch (omap_revision()) {
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+	case DRA752_ES2_0:
+		switch (emif_nr) {
+		case 1:
+			if (ram_size > CONFIG_MAX_MEM_MAPPED)
+				*regs = &emif1_ddr3_532_mhz_1cs_2G;
+			else
+				*regs = &emif1_ddr3_532_mhz_1cs;
+			break;
+		case 2:
+			if (ram_size > CONFIG_MAX_MEM_MAPPED)
+				*regs = &emif2_ddr3_532_mhz_1cs_2G;
+			else
+				*regs = &emif2_ddr3_532_mhz_1cs;
+			break;
+		}
+		break;
+	case DRA762_ABZ_ES1_0:
+	case DRA762_ACD_ES1_0:
+	case DRA762_ES1_0:
+		if (emif_nr == 1)
+			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
+		else
+			*regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
+		break;
+	case DRA722_ES1_0:
+	case DRA722_ES2_0:
+	case DRA722_ES2_1:
+		if (ram_size < CONFIG_MAX_MEM_MAPPED)
+			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+		else
+			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
+		break;
+	default:
+		*regs = &emif1_ddr3_532_mhz_1cs;
+	}
+}
+
+static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
+	.dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x80640300,
+	.dmm_lisa_map_2 = 0xC0500220,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1
+};
+
+static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
+	.dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x0,
+	.dmm_lisa_map_2 = 0x80600100,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1
+};
+
+const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
+	.dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x0,
+	.dmm_lisa_map_2 = 0x80740300,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1
+};
+
+/*
+ * DRA722 EVM EMIF1 2GB CONFIGURATION
+ * EMIF1 4 devices of 512Mb x 8 Micron
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
+	.dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x0,
+	.dmm_lisa_map_2 = 0x80700100,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1
+};
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+{
+	u64 ram_size;
+
+	ram_size = board_ti_get_emif_size();
+
+	switch (omap_revision()) {
+	case DRA762_ABZ_ES1_0:
+	case DRA762_ACD_ES1_0:
+	case DRA762_ES1_0:
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+	case DRA752_ES2_0:
+		if (ram_size > CONFIG_MAX_MEM_MAPPED)
+			*dmm_lisa_regs = &lisa_map_dra7_2GB;
+		else
+			*dmm_lisa_regs = &lisa_map_dra7_1536MB;
+		break;
+	case DRA722_ES1_0:
+	case DRA722_ES2_0:
+	case DRA722_ES2_1:
+	default:
+		if (ram_size < CONFIG_MAX_MEM_MAPPED)
+			*dmm_lisa_regs = &lisa_map_2G_x_2;
+		else
+			*dmm_lisa_regs = &lisa_map_2G_x_4;
+		break;
+	}
+}
+
+struct vcores_data dra752_volts = {
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.mpu.addr	= TPS659038_REG_ADDR_SMPS12,
+	.mpu.pmic	= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr	= TPS659038_REG_ADDR_SMPS45,
+	.eve.pmic	= &tps659038,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr	= TPS659038_REG_ADDR_SMPS6,
+	.gpu.pmic	= &tps659038,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.core.addr	= TPS659038_REG_ADDR_SMPS7,
+	.core.pmic	= &tps659038,
+
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr	= TPS659038_REG_ADDR_SMPS8,
+	.iva.pmic	= &tps659038,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+struct vcores_data dra76x_volts = {
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.mpu.addr	= LP87565_REG_ADDR_BUCK01,
+	.mpu.pmic	= &lp87565,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr	= TPS65917_REG_ADDR_SMPS1,
+	.eve.pmic	= &tps659038,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr	= LP87565_REG_ADDR_BUCK23,
+	.gpu.pmic	= &lp87565,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.core.addr	= TPS65917_REG_ADDR_SMPS3,
+	.core.pmic	= &tps659038,
+
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr	= TPS65917_REG_ADDR_SMPS4,
+	.iva.pmic	= &tps659038,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+struct vcores_data dra722_volts = {
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.mpu.addr	= TPS65917_REG_ADDR_SMPS1,
+	.mpu.pmic	= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.core.addr	= TPS65917_REG_ADDR_SMPS2,
+	.core.pmic	= &tps659038,
+
+	/*
+	 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
+	 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
+	 */
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
+	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.gpu.addr	= TPS65917_REG_ADDR_SMPS3,
+	.gpu.pmic	= &tps659038,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.eve.addr	= TPS65917_REG_ADDR_SMPS3,
+	.eve.pmic	= &tps659038,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
+	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.iva.addr	= TPS65917_REG_ADDR_SMPS3,
+	.iva.pmic	= &tps659038,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+struct vcores_data dra718_volts = {
+	/*
+	 * In the case of dra71x GPU MPU and CORE
+	 * are all powered up by BUCK0 of LP873X PMIC
+	 */
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.mpu.addr	= LP873X_REG_ADDR_BUCK0,
+	.mpu.pmic	= &lp8733,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+	.core.value[OPP_NOM]		= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.core.addr	= LP873X_REG_ADDR_BUCK0,
+	.core.pmic	= &lp8733,
+
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.gpu.addr	= LP873X_REG_ADDR_BUCK0,
+	.gpu.pmic	= &lp8733,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+	/*
+	 * The DSPEVE and IVA rails are grouped on DRA71x-evm
+	 * and are powered by BUCK1 of LP873X PMIC
+	 */
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.eve.addr	= LP873X_REG_ADDR_BUCK1,
+	.eve.pmic	= &lp8733,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
+	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.iva.addr	= LP873X_REG_ADDR_BUCK1,
+	.iva.pmic	= &lp8733,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+int get_voltrail_opp(int rail_offset)
+{
+	int opp;
+
+	switch (rail_offset) {
+	case VOLT_MPU:
+		opp = DRA7_MPU_OPP;
+		/* DRA71x supports only OPP_NOM for MPU */
+		if (board_is_dra71x_evm())
+			opp = OPP_NOM;
+		break;
+	case VOLT_CORE:
+		opp = DRA7_CORE_OPP;
+		/* DRA71x supports only OPP_NOM for CORE */
+		if (board_is_dra71x_evm())
+			opp = OPP_NOM;
+		break;
+	case VOLT_GPU:
+		opp = DRA7_GPU_OPP;
+		/* DRA71x supports only OPP_NOM for GPU */
+		if (board_is_dra71x_evm())
+			opp = OPP_NOM;
+		break;
+	case VOLT_EVE:
+		opp = DRA7_DSPEVE_OPP;
+		/*
+		 * DRA71x does not support OPP_OD for EVE.
+		 * If OPP_OD is selected by menuconfig, fallback
+		 * to OPP_NOM.
+		 */
+		if (board_is_dra71x_evm() && opp == OPP_OD)
+			opp = OPP_NOM;
+		break;
+	case VOLT_IVA:
+		opp = DRA7_IVA_OPP;
+		/*
+		 * DRA71x does not support OPP_OD for IVA.
+		 * If OPP_OD is selected by menuconfig, fallback
+		 * to OPP_NOM.
+		 */
+		if (board_is_dra71x_evm() && opp == OPP_OD)
+			opp = OPP_NOM;
+		break;
+	default:
+		opp = OPP_NOM;
+	}
+
+	return opp;
+}
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+	gpmc_init();
+	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	u64 ram_size;
+
+	ram_size = board_ti_get_emif_size();
+
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = get_effective_memsize();
+	if (ram_size > CONFIG_MAX_MEM_MAPPED) {
+		gd->bd->bi_dram[1].start = 0x200000000;
+		gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
+	}
+
+	return 0;
+}
+
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+static int device_okay(const char *path)
+{
+	int node;
+
+	node = fdt_path_offset(gd->fdt_blob, path);
+	if (node < 0)
+		return 0;
+
+	return fdtdec_get_is_enabled(gd->fdt_blob, node);
+}
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	char *name = "unknown";
+
+	if (is_dra72x()) {
+		if (board_is_dra72x_revc_or_later())
+			name = "dra72x-revc";
+		else if (board_is_dra71x_evm())
+			name = "dra71x";
+		else
+			name = "dra72x";
+	} else if (is_dra76x_abz()) {
+		name = "dra76x_abz";
+	} else if (is_dra76x_acd()) {
+		name = "dra76x_acd";
+	} else {
+		name = "dra7xx";
+	}
+
+	set_board_info_env(name);
+
+	/*
+	 * Default FIT boot on HS devices. Non FIT images are not allowed
+	 * on HS devices.
+	 */
+	if (get_device_type() == HS_DEVICE)
+		env_set("boot_fit", "1");
+
+	omap_die_id_serial();
+	omap_set_fastboot_vars();
+
+	/*
+	 * Hook the LDO1 regulator to EN pin. This applies only to LP8733
+	 * Rest all regulators are hooked to EN Pin at reset.
+	 */
+	if (board_is_dra71x_evm())
+		palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
+#endif
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+	if (device_okay("/ocp/omap_dwc3_1@48880000"))
+		enable_usb_clocks(0);
+	if (device_okay("/ocp/omap_dwc3_2@488c0000"))
+		enable_usb_clocks(1);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void do_board_detect(void)
+{
+	int rc;
+
+	rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
+				    CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		printf("ti_i2c_eeprom_init failed %d\n", rc);
+}
+
+#else
+
+void do_board_detect(void)
+{
+	char *bname = NULL;
+	int rc;
+
+	rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
+				    CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+	if (board_is_dra74x_evm()) {
+		bname = "DRA74x EVM";
+	} else if (board_is_dra72x_evm()) {
+		bname = "DRA72x EVM";
+	} else if (board_is_dra71x_evm()) {
+		bname = "DRA71x EVM";
+	} else if (board_is_dra76x_evm()) {
+		bname = "DRA76x EVM";
+	} else {
+		/* If EEPROM is not populated */
+		if (is_dra72x())
+			bname = "DRA72x EVM";
+		else
+			bname = "DRA74x EVM";
+	}
+
+	if (bname)
+		snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
+			 "Board: %s REV %s\n", bname, board_ti_get_rev());
+}
+#endif	/* CONFIG_SPL_BUILD */
+
+void vcores_init(void)
+{
+	if (board_is_dra74x_evm()) {
+		*omap_vcores = &dra752_volts;
+	} else if (board_is_dra72x_evm()) {
+		*omap_vcores = &dra722_volts;
+	} else if (board_is_dra71x_evm()) {
+		*omap_vcores = &dra718_volts;
+	} else if (board_is_dra76x_evm()) {
+		*omap_vcores = &dra76x_volts;
+	} else {
+		/* If EEPROM is not populated */
+		if (is_dra72x())
+			*omap_vcores = &dra722_volts;
+		else
+			*omap_vcores = &dra752_volts;
+	}
+}
+
+void set_muxconf_regs(void)
+{
+	do_set_mux32((*ctrl)->control_padconf_core_base,
+		     early_padconf, ARRAY_SIZE(early_padconf));
+}
+
+#if defined(CONFIG_MTD_RAW_NAND)
+static int nand_sw_detect(void)
+{
+	int rc;
+	uchar data[2];
+	struct udevice *dev;
+
+	rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM,
+				     NAND_PCF8575_ADDR, 0, &dev);
+	if (rc)
+		return -1;
+
+	rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data));
+	if (rc)
+		return -1;
+
+	/* We are only interested in P10 and P11 on PCF8575 which is equal to
+	 * bits 8 and 9.
+	 */
+	data[1] = data[1] & 0x3;
+
+	/* Ensure only P11 is set and P10 is cleared. This ensures only
+	 * NAND (P10) is configured and not NOR (P11) which are both low
+	 * true signals. NAND and NOR settings should not be enabled at
+	 * the same time.
+	 */
+	if (data[1] == 0x2)
+		return 0;
+
+	return -1;
+}
+#else
+int nand_sw_detect(void)
+{
+	return -1;
+}
+#endif
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void recalibrate_iodelay(void)
+{
+	struct pad_conf_entry const *pads, *delta_pads = NULL;
+	struct iodelay_cfg_entry const *iodelay;
+	int npads, niodelays, delta_npads = 0;
+	int ret;
+
+	switch (omap_revision()) {
+	case DRA722_ES1_0:
+	case DRA722_ES2_0:
+	case DRA722_ES2_1:
+		pads = dra72x_core_padconf_array_common;
+		npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
+		if (board_is_dra71x_evm()) {
+			pads = dra71x_core_padconf_array;
+			npads = ARRAY_SIZE(dra71x_core_padconf_array);
+			iodelay = dra71_iodelay_cfg_array;
+			niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
+			/* If SW8 on the EVM is set to enable NAND then
+			 * overwrite the pins used by VOUT3 with NAND.
+			 */
+			if (!nand_sw_detect()) {
+				delta_pads = dra71x_nand_padconf_array;
+				delta_npads =
+					ARRAY_SIZE(dra71x_nand_padconf_array);
+			} else {
+				delta_pads = dra71x_vout3_padconf_array;
+				delta_npads =
+					ARRAY_SIZE(dra71x_vout3_padconf_array);
+			}
+
+		} else if (board_is_dra72x_revc_or_later()) {
+			delta_pads = dra72x_rgmii_padconf_array_revc;
+			delta_npads =
+				ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
+			iodelay = dra72_iodelay_cfg_array_revc;
+			niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
+		} else {
+			delta_pads = dra72x_rgmii_padconf_array_revb;
+			delta_npads =
+				ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
+			iodelay = dra72_iodelay_cfg_array_revb;
+			niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
+		}
+		break;
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+		pads = dra74x_core_padconf_array;
+		npads = ARRAY_SIZE(dra74x_core_padconf_array);
+		iodelay = dra742_es1_1_iodelay_cfg_array;
+		niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
+		break;
+	case DRA762_ACD_ES1_0:
+	case DRA762_ES1_0:
+		pads = dra76x_core_padconf_array;
+		npads = ARRAY_SIZE(dra76x_core_padconf_array);
+		iodelay = dra76x_es1_0_iodelay_cfg_array;
+		niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
+		break;
+	default:
+	case DRA752_ES2_0:
+	case DRA762_ABZ_ES1_0:
+		pads = dra74x_core_padconf_array;
+		npads = ARRAY_SIZE(dra74x_core_padconf_array);
+		iodelay = dra742_es2_0_iodelay_cfg_array;
+		niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
+		/* Setup port1 and port2 for rgmii with 'no-id' mode */
+		clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
+				      RGMII1_ID_MODE_N_MASK);
+		break;
+	}
+	/* Setup I/O isolation */
+	ret = __recalibrate_iodelay_start();
+	if (ret)
+		goto err;
+
+	/* Do the muxing here */
+	do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
+
+	/* Now do the weird minor deltas that should be safe */
+	if (delta_npads)
+		do_set_mux32((*ctrl)->control_padconf_core_base,
+			     delta_pads, delta_npads);
+
+	if (is_dra76x())
+		/* Set mux for MCAN instead of DCAN1 */
+		clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
+				MCAN_SEL_ALT_MASK, MCAN_SEL);
+
+	/* Setup IOdelay configuration */
+	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
+err:
+	/* Closeup.. remove isolation */
+	__recalibrate_iodelay_end(ret);
+}
+#endif
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(struct bd_info *bis)
+{
+	omap_mmc_init(0, 0, 0, -1, -1);
+	omap_mmc_init(1, 0, 0, -1, -1);
+	return 0;
+}
+
+void board_mmc_poweron_ldo(uint voltage)
+{
+	if (board_is_dra71x_evm()) {
+		if (voltage == LDO_VOLT_3V0)
+			voltage = 0x19;
+		else if (voltage == LDO_VOLT_1V8)
+			voltage = 0xa;
+		lp873x_mmc1_poweron_ldo(voltage);
+	} else if (board_is_dra76x_evm()) {
+		palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
+	} else {
+		palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
+	}
+}
+
+static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
+	.hw_rev = "rev11",
+	.unsupported_caps = MMC_CAP(MMC_HS_200) |
+			    MMC_CAP(UHS_SDR104),
+	.max_freq = 96000000,
+};
+
+static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
+	.hw_rev = "rev11",
+	.unsupported_caps = MMC_CAP(MMC_HS_200) |
+			    MMC_CAP(UHS_SDR104) |
+			    MMC_CAP(UHS_SDR50),
+	.max_freq = 48000000,
+};
+
+const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
+{
+	switch (omap_revision()) {
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+		if (addr == OMAP_HSMMC1_BASE)
+			return &dra7x_es1_1_mmc1_fixups;
+		else
+			return &dra7x_es1_1_mmc23_fixups;
+	default:
+		return NULL;
+	}
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	env_init();
+	env_load();
+	if (env_get_yesno("boot_os") != 1)
+		return 1;
+#endif
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+/* VTT regulator enable */
+static inline void vtt_regulator_enable(void)
+{
+	if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+		return;
+
+	/* Do not enable VTT for DRA722 or DRA76x */
+	if (is_dra72x() || is_dra76x())
+		return;
+
+	/*
+	 * EVM Rev G and later use gpio7_11 for DDR3 termination.
+	 * This is safe enough to do on older revs.
+	 */
+	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+}
+
+int board_early_init_f(void)
+{
+	vtt_regulator_enable();
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_dra72x()) {
+		if (board_is_dra71x_evm()) {
+			if (!strcmp(name, "dra71-evm"))
+				return 0;
+		}else if(board_is_dra72x_revc_or_later()) {
+			if (!strcmp(name, "dra72-evm-revc"))
+				return 0;
+		} else if (!strcmp(name, "dra72-evm")) {
+			return 0;
+		}
+	} else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
+		return 0;
+	} else if (!is_dra72x() && !is_dra76x_acd() &&
+		   !strcmp(name, "dra7-evm")) {
+		return 0;
+	}
+
+	return -1;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
+int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
+{
+	if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
+		return -ENOTSUPP;
+
+	printf("Setting reboot to fastboot flag ...\n");
+	env_set("dofastboot", "1");
+	env_save();
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+	secure_boot_verify_image(p_image, p_size);
+}
+
+void board_tee_image_process(ulong tee_image, size_t tee_size)
+{
+	secure_tee_install((u32)tee_image);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
+#endif
diff --git a/roms/u-boot/board/ti/dra7xx/mux_data.h b/roms/u-boot/board/ti/dra7xx/mux_data.h
new file mode 100644
index 000000000..75da5cb60
--- /dev/null
+++ b/roms/u-boot/board/ti/dra7xx/mux_data.h
@@ -0,0 +1,1149 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Sricharan R	<r.sricharan@ti.com>
+ * Nishant Kamat <nskamat@ti.com>
+ */
+#ifndef _MUX_DATA_DRA7XX_H_
+#define _MUX_DATA_DRA7XX_H_
+
+#include <asm/arch/mux_dra7xx.h>
+
+const struct pad_conf_entry dra72x_core_padconf_array_common[] = {
+	{GPMC_AD0, (M3 | PIN_INPUT)},	/* gpmc_ad0.vout3_d0 */
+	{GPMC_AD1, (M3 | PIN_INPUT)},	/* gpmc_ad1.vout3_d1 */
+	{GPMC_AD2, (M3 | PIN_INPUT)},	/* gpmc_ad2.vout3_d2 */
+	{GPMC_AD3, (M3 | PIN_INPUT)},	/* gpmc_ad3.vout3_d3 */
+	{GPMC_AD4, (M3 | PIN_INPUT)},	/* gpmc_ad4.vout3_d4 */
+	{GPMC_AD5, (M3 | PIN_INPUT)},	/* gpmc_ad5.vout3_d5 */
+	{GPMC_AD6, (M3 | PIN_INPUT)},	/* gpmc_ad6.vout3_d6 */
+	{GPMC_AD7, (M3 | PIN_INPUT)},	/* gpmc_ad7.vout3_d7 */
+	{GPMC_AD8, (M3 | PIN_INPUT)},	/* gpmc_ad8.vout3_d8 */
+	{GPMC_AD9, (M3 | PIN_INPUT)},	/* gpmc_ad9.vout3_d9 */
+	{GPMC_AD10, (M3 | PIN_INPUT)},	/* gpmc_ad10.vout3_d10 */
+	{GPMC_AD11, (M3 | PIN_INPUT)},	/* gpmc_ad11.vout3_d11 */
+	{GPMC_AD12, (M3 | PIN_INPUT)},	/* gpmc_ad12.vout3_d12 */
+	{GPMC_AD13, (M3 | PIN_INPUT)},	/* gpmc_ad13.vout3_d13 */
+	{GPMC_AD14, (M3 | PIN_INPUT)},	/* gpmc_ad14.vout3_d14 */
+	{GPMC_AD15, (M3 | PIN_INPUT)},	/* gpmc_ad15.vout3_d15 */
+	{GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a0.vout3_d16 */
+	{GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a1.vout3_d17 */
+	{GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a2.vout3_d18 */
+	{GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a3.vout3_d19 */
+	{GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a4.vout3_d20 */
+	{GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a5.vout3_d21 */
+	{GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a6.vout3_d22 */
+	{GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a7.vout3_d23 */
+	{GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a8.vout3_hsync */
+	{GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a9.vout3_vsync */
+	{GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a10.vout3_de */
+	{GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a11.gpio2_1 */
+	{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
+	{GPMC_CS3, (M3 | PIN_INPUT_PULLUP)},	/* gpmc_cs3.vout3_clk */
+	{VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)},	/* vin2a_clk0.vin2a_clk0 */
+	{VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)},	/* vin2a_hsync0.vin2a_hsync0 */
+	{VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)},	/* vin2a_vsync0.vin2a_vsync0 */
+	{VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},	/* vin2a_d0.vin2a_d0 */
+	{VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},	/* vin2a_d1.vin2a_d1 */
+	{VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},	/* vin2a_d2.vin2a_d2 */
+	{VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)},	/* vin2a_d3.vin2a_d3 */
+	{VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)},	/* vin2a_d4.vin2a_d4 */
+	{VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)},	/* vin2a_d5.vin2a_d5 */
+	{VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)},	/* vin2a_d6.vin2a_d6 */
+	{VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)},	/* vin2a_d7.vin2a_d7 */
+	{VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)},	/* vin2a_d8.vin2a_d8 */
+	{VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)},	/* vin2a_d9.vin2a_d9 */
+	{VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)},	/* vin2a_d10.vin2a_d10 */
+	{VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)},	/* vin2a_d11.vin2a_d11 */
+	{VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_de.vout1_de */
+	{VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d23.vout1_d23 */
+	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_14.i2c3_sda */
+	{GPIO6_15, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_15.i2c3_scl */
+	{GPIO6_16, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
+	{MCASP1_AXR0, (M10 | PIN_INPUT_SLEW)},	/* mcasp1_axr0.i2c5_sda */
+	{MCASP1_AXR1, (M10 | PIN_INPUT_SLEW)},	/* mcasp1_axr1.i2c5_scl */
+	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr12.mcasp7_axr0 */
+	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.mcasp7_axr1 */
+	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr14.mcasp7_aclkx */
+	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr15.mcasp7_fsx */
+	{MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkr.mcasp2_aclkr */
+	{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.mcasp3_aclkx */
+	{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.mcasp3_fsx */
+	{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_axr0.mcasp3_axr0 */
+	{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)},	/* mcasp3_axr1.mcasp3_axr1 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)},	/* mmc1_sdcd.gpio6_27 */
+	{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)},	/* mmc1_sdwp.gpio6_28 */
+	{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.spi1_sclk */
+	{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.spi1_d1 */
+	{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.spi1_d0 */
+	{SPI1_CS0, (M0 | PIN_INPUT_PULLUP)},	/* spi1_cs0.spi1_cs0 */
+	{SPI1_CS1, (M14 | PIN_OUTPUT)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)},	/* spi2_sclk.uart3_rxd */
+	{SPI2_D1, (M1 | PIN_INPUT_SLEW)},	/* spi2_d1.uart3_txd */
+	{SPI2_D0, (M1 | PIN_INPUT_SLEW)},	/* spi2_d0.uart3_ctsn */
+	{SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.uart3_rtsn */
+	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
+	{DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.gpio1_15 */
+	{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_txd.uart1_txd */
+	{UART1_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_ctsn.mmc4_clk */
+	{UART1_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_rtsn.mmc4_cmd */
+	{UART2_RXD, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rxd.mmc4_dat0 */
+	{UART2_TXD, (M3 | PIN_INPUT_PULLUP)},	/* uart2_txd.mmc4_dat1 */
+	{UART2_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_ctsn.mmc4_dat2 */
+	{UART2_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rtsn.mmc4_dat3 */
+	{I2C2_SDA, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M15 | PULL_UP)},	/* Wakeup0.safe for dcan1_rx */
+	{WAKEUP3, (M1 | PULL_ENA | PULL_UP)},	/* Wakeup3.sys_nirq1 */
+};
+
+const struct pad_conf_entry dra72x_rgmii_padconf_array_revb[] = {
+	{GPIO6_11, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_11.gpio6_11 */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d0.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d1.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d2.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d3.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d4.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d5.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d6.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d7.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d8.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d9.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d10.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d11.rgmii1_rxd0 */
+	{XREF_CLK1, (M5 | PIN_OUTPUT)},	/* xref_clk1.atl_clk1 */
+	{XREF_CLK2, (M5 | PIN_OUTPUT)},	/* xref_clk2.atl_clk2 */
+};
+
+const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = {
+	{VIN2A_FLD0, (M14 | PIN_INPUT)},	/* vin2a_fld0.gpio3_30 */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.atl_clk2 */
+};
+
+const struct pad_conf_entry dra71x_core_padconf_array[] = {
+	{GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a0.vout3_d16 */
+	{GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a1.vout3_d17 */
+	{GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a2.vout3_d18 */
+	{GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a3.vout3_d19 */
+	{GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a4.vout3_d20 */
+	{GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a5.vout3_d21 */
+	{GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a6.vout3_d22 */
+	{GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a7.vout3_d23 */
+	{GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a8.vout3_hsync */
+	{GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a9.vout3_vsync */
+	{GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a10.vout3_de */
+	{GPMC_A11, (M14 | PIN_INPUT)},	/* gpmc_a11.gpio2_1 */
+	{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
+	{GPMC_CS3, (M3 | PIN_INPUT_PULLUP)},	/* gpmc_cs3.vout3_clk */
+	{VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)},	/* vin2a_clk0.vin2a_clk0 */
+	{VIN2A_FLD0, (M14 | PIN_INPUT)},	/* vin2a_fld0.gpio3_30 */
+	{VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)},	/* vin2a_hsync0.vin2a_hsync0 */
+	{VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)},	/* vin2a_vsync0.vin2a_vsync0 */
+	{VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},	/* vin2a_d0.vin2a_d0 */
+	{VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},	/* vin2a_d1.vin2a_d1 */
+	{VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},	/* vin2a_d2.vin2a_d2 */
+	{VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)},	/* vin2a_d3.vin2a_d3 */
+	{VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)},	/* vin2a_d4.vin2a_d4 */
+	{VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)},	/* vin2a_d5.vin2a_d5 */
+	{VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)},	/* vin2a_d6.vin2a_d6 */
+	{VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)},	/* vin2a_d7.vin2a_d7 */
+	{VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)},	/* vin2a_d8.vin2a_d8 */
+	{VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)},	/* vin2a_d9.vin2a_d9 */
+	{VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)},	/* vin2a_d10.vin2a_d10 */
+	{VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)},	/* vin2a_d11.vin2a_d11 */
+	{VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)},	/* N/A.N/A */
+	{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)},	/* N/A.N/A */
+	{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)},	/* N/A.N/A */
+	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_14.i2c3_sda */
+	{GPIO6_15, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_15.i2c3_scl */
+	{GPIO6_16, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
+	{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.atl_clk2 */
+	{MCASP1_ACLKX, (M14 | PIN_INPUT)},	/* mcasp1_aclkx.gpio7_31 */
+	{MCASP1_FSX, (M14 | 0x000d0000)},	/* mcasp1_fsx.gpio7_30 */
+	{MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.i2c5_sda */
+	{MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr1.i2c5_scl */
+	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr12.mcasp7_axr0 */
+	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.mcasp7_axr1 */
+	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr14.mcasp7_aclkx */
+	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr15.mcasp7_fsx */
+	{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.mcasp3_aclkx */
+	{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.mcasp3_fsx */
+	{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_axr0.mcasp3_axr0 */
+	{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)},	/* mcasp3_axr1.mcasp3_axr1 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mmc1_sdcd.gpio6_27 */
+	{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)},	/* mmc1_sdwp.gpio6_28 */
+	{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.spi1_sclk */
+	{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.spi1_d1 */
+	{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.spi1_d0 */
+	{SPI1_CS0, (M0 | PIN_INPUT_PULLUP)},	/* spi1_cs0.spi1_cs0 */
+	{SPI1_CS1, (M14 | PIN_INPUT_PULLUP)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)},	/* spi2_sclk.uart3_rxd */
+	{SPI2_D1, (M1 | PIN_INPUT_SLEW)},	/* spi2_d1.uart3_txd */
+	{SPI2_D0, (M1 | PIN_INPUT_SLEW)},	/* spi2_d0.uart3_ctsn */
+	{SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.uart3_rtsn */
+	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
+	{DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.gpio1_15 */
+	{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_txd.uart1_txd */
+	{UART1_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_ctsn.mmc4_clk */
+	{UART1_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_rtsn.mmc4_cmd */
+	{UART2_RXD, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rxd.mmc4_dat0 */
+	{UART2_TXD, (M3 | PIN_INPUT_PULLUP)},	/* uart2_txd.mmc4_dat1 */
+	{UART2_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_ctsn.mmc4_dat2 */
+	{UART2_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rtsn.mmc4_dat3 */
+	{I2C2_SDA, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M15 | PULL_UP)},	/* Wakeup0.safe for dcan1_rx */
+	{WAKEUP3, (M1 | PULL_ENA | PULL_UP)},	/* Wakeup3.sys_nirq1 */
+};
+
+const struct pad_conf_entry dra71x_vout3_padconf_array[] = {
+	{GPMC_AD0, (M3 | PIN_INPUT)},	/* gpmc_ad0.vout3_d0 */
+	{GPMC_AD1, (M3 | PIN_INPUT)},	/* gpmc_ad1.vout3_d1 */
+	{GPMC_AD2, (M3 | PIN_INPUT)},	/* gpmc_ad2.vout3_d2 */
+	{GPMC_AD3, (M3 | PIN_INPUT)},	/* gpmc_ad3.vout3_d3 */
+	{GPMC_AD4, (M3 | PIN_INPUT)},	/* gpmc_ad4.vout3_d4 */
+	{GPMC_AD5, (M3 | PIN_INPUT)},	/* gpmc_ad5.vout3_d5 */
+	{GPMC_AD6, (M3 | PIN_INPUT)},	/* gpmc_ad6.vout3_d6 */
+	{GPMC_AD7, (M3 | PIN_INPUT)},	/* gpmc_ad7.vout3_d7 */
+	{GPMC_AD8, (M3 | PIN_INPUT)},	/* gpmc_ad8.vout3_d8 */
+	{GPMC_AD9, (M3 | PIN_INPUT)},	/* gpmc_ad9.vout3_d9 */
+	{GPMC_AD10, (M3 | PIN_INPUT)},	/* gpmc_ad10.vout3_d10 */
+	{GPMC_AD11, (M3 | PIN_INPUT)},	/* gpmc_ad11.vout3_d11 */
+	{GPMC_AD12, (M3 | PIN_INPUT)},	/* gpmc_ad12.vout3_d12 */
+	{GPMC_AD13, (M3 | PIN_INPUT)},	/* gpmc_ad13.vout3_d13 */
+	{GPMC_AD14, (M3 | PIN_INPUT)},	/* gpmc_ad14.vout3_d14 */
+	{GPMC_AD15, (M3 | PIN_INPUT)},	/* gpmc_ad15.vout3_d15 */
+};
+
+const struct pad_conf_entry dra71x_nand_padconf_array[] = {
+	{GPMC_AD0, (M0 | PIN_INPUT)},	/* gpmc_ad0.gpmc_ad0 */
+	{GPMC_AD1, (M0 | PIN_INPUT)},	/* gpmc_ad1.gpmc_ad1 */
+	{GPMC_AD2, (M0 | PIN_INPUT)},	/* gpmc_ad2.gpmc_ad2 */
+	{GPMC_AD3, (M0 | PIN_INPUT)},	/* gpmc_ad3.gpmc_ad3 */
+	{GPMC_AD4, (M0 | PIN_INPUT)},	/* gpmc_ad4.gpmc_ad4 */
+	{GPMC_AD5, (M0 | PIN_INPUT)},	/* gpmc_ad5.gpmc_ad5 */
+	{GPMC_AD6, (M0 | PIN_INPUT)},	/* gpmc_ad6.gpmc_ad6 */
+	{GPMC_AD7, (M0 | PIN_INPUT)},	/* gpmc_ad7.gpmc_ad7 */
+	{GPMC_AD8, (M0 | PIN_INPUT)},	/* gpmc_ad8.gpmc_ad8 */
+	{GPMC_AD9, (M0 | PIN_INPUT)},	/* gpmc_ad9.gpmc_ad9 */
+	{GPMC_AD10, (M0 | PIN_INPUT)},	/* gpmc_ad10.gpmc_ad10 */
+	{GPMC_AD11, (M0 | PIN_INPUT)},	/* gpmc_ad11.gpmc_ad11 */
+	{GPMC_AD12, (M0 | PIN_INPUT)},	/* gpmc_ad12.gpmc_ad12 */
+	{GPMC_AD13, (M0 | PIN_INPUT)},	/* gpmc_ad13.gpmc_ad13 */
+	{GPMC_AD14, (M0 | PIN_INPUT)},	/* gpmc_ad14.gpmc_ad14 */
+	{GPMC_AD15, (M0 | PIN_INPUT)},	/* gpmc_ad15.gpmc_ad15 */
+	{GPMC_CS0, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_cs0.gpmc_cs0 */
+	{GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLDOWN)},	/* gpmc_advn_ale.gpmc_advn_ale */
+	{GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_oen_ren.gpmc_oen_ren */
+	{GPMC_WEN, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_wen.gpmc_wen */
+	{GPMC_BEN0, (M0 | PIN_INPUT_PULLDOWN)},	/* gpmc_ben0.gpmc_ben0 */
+	{GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* gpmc_wait0.gpmc_wait0 */
+};
+
+const struct pad_conf_entry early_padconf[] = {
+	{UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
+	{UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */
+	{UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */
+	{UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */
+	{I2C1_SDA, (PIN_INPUT | M0)},	/* I2C1_SDA */
+	{I2C1_SCL, (PIN_INPUT | M0)},	/* I2C1_SCL */
+};
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revb[] = {
+	{0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
+	{0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */
+	{0x708, 80, 1391}, /* RGMMI0_RXD0_IN */
+	{0x714, 196, 1522}, /* RGMMI0_RXD1_IN */
+	{0x720, 40, 1860}, /* RGMMI0_RXD2_IN */
+	{0x72C, 0, 1956}, /* RGMMI0_RXD3_IN */
+	{0x740, 0, 220}, /* RGMMI0_TXC_OUT */
+	{0x74C, 1820, 180}, /* RGMMI0_TXCTL_OUT */
+	{0x758, 1740, 440}, /* RGMMI0_TXD0_OUT */
+	{0x764, 1740, 240}, /* RGMMI0_TXD1_OUT */
+	{0x770, 1680, 380}, /* RGMMI0_TXD2_OUT */
+	{0x77C, 1740, 440}, /* RGMMI0_TXD3_OUT */
+	/* These values are for using RGMII1 configuration on VIN2a_x pins. */
+	{0xAB0, 596, 0}, /* CFG_VIN2A_D18_IN */
+	{0xABC, 314, 980}, /* CFG_VIN2A_D19_IN */
+	{0xAD4, 241, 1536}, /* CFG_VIN2A_D20_IN */
+	{0xAE0, 103, 1689}, /* CFG_VIN2A_D21_IN */
+	{0xAEC, 161, 1563}, /* CFG_VIN2A_D22_IN */
+	{0xAF8, 0, 1613}, /* CFG_VIN2A_D23_IN */
+	{0xA70, 0, 200}, /* CFG_VIN2A_D12_OUT */
+	{0xA7C, 1560, 140}, /* CFG_VIN2A_D13_OUT */
+	{0xA88, 1700, 0}, /* CFG_VIN2A_D14_OUT */
+	{0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */
+	{0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */
+	{0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */
+	{0x144, 0, 0}, /* CFG_GPMC_A13_IN */
+	{0x150, 2062, 2277}, /* CFG_GPMC_A14_IN */
+	{0x15C, 1960, 2289}, /* CFG_GPMC_A15_IN */
+	{0x168, 2058, 2386}, /* CFG_GPMC_A16_IN */
+	{0x170, 0, 0 },	/* CFG_GPMC_A16_OUT */
+	{0x174, 2062, 2350}, /* CFG_GPMC_A17_IN */
+	{0x188, 0, 0}, /* CFG_GPMC_A18_OUT */
+	{0x374, 121, 0}, /* CFG_GPMC_CS2_OUT */
+};
+
+const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revc[] = {
+	{0x0144, 0, 0},	/* CFG_GPMC_A13_IN */
+	{0x0150, 2247, 1186},	/* CFG_GPMC_A14_IN */
+	{0x015C, 2176, 1197},	/* CFG_GPMC_A15_IN */
+	{0x0168, 2229, 1268},	/* CFG_GPMC_A16_IN */
+	{0x0170, 0, 0},	/* CFG_GPMC_A16_OUT */
+	{0x0174, 2251, 1217},	/* CFG_GPMC_A17_IN */
+	{0x0188, 0, 0},	/* CFG_GPMC_A18_OUT */
+	{0x0374, 121, 0},	/* CFG_GPMC_CS2_OUT */
+	{0x06F0, 413, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 27, 2296},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 3, 1721},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 134, 1786},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 40, 1966},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 0, 2057},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 0, 60},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 0, 60},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 0, 60},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 0, 0},		/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 60},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 0, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 0, 0},		/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 170, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 150, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 0, 0},		/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 60, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 60, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 530, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 71, 1099},	/* CFG_VIN2A_D19_IN */
+	{0x0AC8, 2229, 10},	/* CFG_VIN2A_D1_IN */
+	{0x0AD4, 142, 1337},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 114, 1517},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 171, 1331},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1328},	/* CFG_VIN2A_D23_IN */
+};
+
+const struct iodelay_cfg_entry dra71_iodelay_cfg_array[] = {
+	{0x0144, 0, 0},	/* CFG_GPMC_A13_IN */
+	{0x0150, 2247, 1186},	/* CFG_GPMC_A14_IN */
+	{0x015C, 2176, 1197},	/* CFG_GPMC_A15_IN */
+	{0x0168, 2229, 1268},	/* CFG_GPMC_A16_IN */
+	{0x0170, 0, 0},	/* CFG_GPMC_A16_OUT */
+	{0x0174, 2251, 1217},	/* CFG_GPMC_A17_IN */
+	{0x0188, 0, 0},	/* CFG_GPMC_A18_OUT */
+	{0x0374, 0, 0},	/* CFG_GPMC_CS2_OUT */
+	{0x06F0, 413, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 27, 2296},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 3, 1721},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 134, 1786},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 40, 1966},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 0, 2057},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 0, 60},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 0, 60},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 0, 60},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 0, 0},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 60},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 0, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A38, 0, 0},	/* CFG_VIN2A_CLK0_IN */
+	{0x0A44, 1936, 0},	/* CFG_VIN2A_D0_IN */
+	{0x0A50, 2031, 0},	/* CFG_VIN2A_D10_IN */
+	{0x0A5C, 1702, 0},	/* CFG_VIN2A_D11_IN */
+	{0x0A70, 0, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 170, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 150, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 0, 0},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 60, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 60, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 530, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 71, 1099},	/* CFG_VIN2A_D19_IN */
+	{0x0AC8, 2229, 10},	/* CFG_VIN2A_D1_IN */
+	{0x0AD4, 142, 1337},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 114, 1517},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 171, 1331},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1328},	/* CFG_VIN2A_D23_IN */
+	{0x0B04, 1736, 0},	/* CFG_VIN2A_D2_IN */
+	{0x0B10, 1943, 0},	/* CFG_VIN2A_D3_IN */
+	{0x0B1C, 1601, 0},	/* CFG_VIN2A_D4_IN */
+	{0x0B28, 2052, 0},	/* CFG_VIN2A_D5_IN */
+	{0x0B34, 1571, 0},	/* CFG_VIN2A_D6_IN */
+	{0x0B40, 1855, 0},	/* CFG_VIN2A_D7_IN */
+	{0x0B4C, 1224, 618},	/* CFG_VIN2A_D8_IN */
+	{0x0B58, 1373, 509},	/* CFG_VIN2A_D9_IN */
+	{0x0B7C, 1943, 0},	/* CFG_VIN2A_HSYNC0_IN */
+	{0x0B88, 1612, 0},	/* CFG_VIN2A_VSYNC0_IN */
+};
+#endif
+
+const struct pad_conf_entry dra74x_core_padconf_array[] = {
+	{GPMC_AD0, (M3 | PIN_INPUT)},	/* gpmc_ad0.vout3_d0 */
+	{GPMC_AD1, (M3 | PIN_INPUT)},	/* gpmc_ad1.vout3_d1 */
+	{GPMC_AD2, (M3 | PIN_INPUT)},	/* gpmc_ad2.vout3_d2 */
+	{GPMC_AD3, (M3 | PIN_INPUT)},	/* gpmc_ad3.vout3_d3 */
+	{GPMC_AD4, (M3 | PIN_INPUT)},	/* gpmc_ad4.vout3_d4 */
+	{GPMC_AD5, (M3 | PIN_INPUT)},	/* gpmc_ad5.vout3_d5 */
+	{GPMC_AD6, (M3 | PIN_INPUT)},	/* gpmc_ad6.vout3_d6 */
+	{GPMC_AD7, (M3 | PIN_INPUT)},	/* gpmc_ad7.vout3_d7 */
+	{GPMC_AD8, (M3 | PIN_INPUT)},	/* gpmc_ad8.vout3_d8 */
+	{GPMC_AD9, (M3 | PIN_INPUT)},	/* gpmc_ad9.vout3_d9 */
+	{GPMC_AD10, (M3 | PIN_INPUT)},	/* gpmc_ad10.vout3_d10 */
+	{GPMC_AD11, (M3 | PIN_INPUT)},	/* gpmc_ad11.vout3_d11 */
+	{GPMC_AD12, (M3 | PIN_INPUT)},	/* gpmc_ad12.vout3_d12 */
+	{GPMC_AD13, (M3 | PIN_INPUT)},	/* gpmc_ad13.vout3_d13 */
+	{GPMC_AD14, (M3 | PIN_INPUT)},	/* gpmc_ad14.vout3_d14 */
+	{GPMC_AD15, (M3 | PIN_INPUT)},	/* gpmc_ad15.vout3_d15 */
+	{GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a0.vout3_d16 */
+	{GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a1.vout3_d17 */
+	{GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a2.vout3_d18 */
+	{GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a3.vout3_d19 */
+	{GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a4.vout3_d20 */
+	{GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a5.vout3_d21 */
+	{GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a6.vout3_d22 */
+	{GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a7.vout3_d23 */
+	{GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a8.vout3_hsync */
+	{GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a9.vout3_vsync */
+	{GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a10.vout3_de */
+	{GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a11.gpio2_1 */
+	{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
+	{GPMC_CS3, (M3 | PIN_INPUT_PULLUP)},	/* gpmc_cs3.vout3_clk */
+	{VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_clk0.vin1a_clk0 */
+	{VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_de0.vin1a_de0 */
+	{VIN1A_FLD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_fld0.vin1a_fld0 */
+	{VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_hsync0.vin1a_hsync0 */
+	{VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_vsync0.vin1a_vsync0 */
+	{VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d0.vin1a_d0 */
+	{VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d1.vin1a_d1 */
+	{VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d2.vin1a_d2 */
+	{VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d3.vin1a_d3 */
+	{VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d4.vin1a_d4 */
+	{VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d5.vin1a_d5 */
+	{VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d6.vin1a_d6 */
+	{VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d7.vin1a_d7 */
+	{VIN1A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d8.vin1a_d8 */
+	{VIN1A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d9.vin1a_d9 */
+	{VIN1A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d10.vin1a_d10 */
+	{VIN1A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d11.vin1a_d11 */
+	{VIN1A_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d12.vin1a_d12 */
+	{VIN1A_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d13.vin1a_d13 */
+	{VIN1A_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d14.vin1a_d14 */
+	{VIN1A_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d15.vin1a_d15 */
+	{VIN1A_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d16.vin1a_d16 */
+	{VIN1A_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d17.vin1a_d17 */
+	{VIN1A_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d18.vin1a_d18 */
+	{VIN1A_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d19.vin1a_d19 */
+	{VIN1A_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d20.vin1a_d20 */
+	{VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d21.vin1a_d21 */
+	{VIN1A_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d22.vin1a_d22 */
+	{VIN1A_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin1a_d23.vin1a_d23 */
+	{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_de.vout1_de */
+	{VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d23.vout1_d23 */
+	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_14.i2c3_sda */
+	{GPIO6_15, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_15.i2c3_scl */
+	{GPIO6_16, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
+	{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.atl_clk2 */
+	{MCASP1_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp1_aclkx.mcasp1_aclkx */
+	{MCASP1_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp1_fsx.mcasp1_fsx */
+	{MCASP1_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)},	/* mcasp1_axr0.mcasp1_axr0 */
+	{MCASP1_AXR1, (M0 | PIN_INPUT_SLEW)},	/* mcasp1_axr1.mcasp1_axr1 */
+	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr12.mcasp7_axr0 */
+	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.mcasp7_axr1 */
+	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr14.mcasp7_aclkx */
+	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr15.mcasp7_fsx */
+	{MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkr.mcasp2_aclkr */
+	{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.mcasp3_aclkx */
+	{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.mcasp3_fsx */
+	{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_axr0.mcasp3_axr0 */
+	{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)},	/* mcasp3_axr1.mcasp3_axr1 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)},	/* mmc1_sdcd.gpio6_27 */
+	{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)},	/* mmc1_sdwp.gpio6_28 */
+	{GPIO6_11, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_11.gpio6_11 */
+	{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.spi1_sclk */
+	{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.spi1_d1 */
+	{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.spi1_d0 */
+	{SPI1_CS0, (M0 | PIN_INPUT_PULLUP)},	/* spi1_cs0.spi1_cs0 */
+	{SPI1_CS1, (M14 | PIN_OUTPUT)},		/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)},	/* spi2_sclk.uart3_rxd */
+	{SPI2_D1, (M1 | PIN_INPUT_SLEW)},	/* spi2_d1.uart3_txd */
+	{SPI2_D0, (M1 | PIN_INPUT_SLEW)},	/* spi2_d0.uart3_ctsn */
+	{SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.uart3_rtsn */
+	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
+	{DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.gpio1_15 */
+	{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_txd.uart1_txd */
+	{UART1_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_ctsn.mmc4_clk */
+	{UART1_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_rtsn.mmc4_cmd */
+	{UART2_RXD, (M3 | PIN_INPUT_PULLUP)},	/* N/A.mmc4_dat0 */
+	{UART2_TXD, (M3 | PIN_INPUT_PULLUP)},	/* uart2_txd.mmc4_dat1 */
+	{UART2_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_ctsn.mmc4_dat2 */
+	{UART2_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rtsn.mmc4_dat3 */
+	{I2C2_SDA, (M0 | PIN_INPUT_PULLUP)},	/* i2c2_sda.i2c2_sda */
+	{I2C2_SCL, (M0 | PIN_INPUT_PULLUP)},	/* i2c2_scl.i2c2_scl */
+	{WAKEUP0, (M15 | PULL_UP)},	/* Wakeup0.safe for dcan1_rx */
+	{WAKEUP2, (M14)},		/* Wakeup2.gpio1_2 */
+};
+
+const struct pad_conf_entry dra76x_core_padconf_array[] = {
+	{GPMC_AD0, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad0.vout3_d0 */
+	{GPMC_AD1, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad1.vout3_d1 */
+	{GPMC_AD2, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad2.vout3_d2 */
+	{GPMC_AD3, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad3.vout3_d3 */
+	{GPMC_AD4, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad4.vout3_d4 */
+	{GPMC_AD5, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad5.vout3_d5 */
+	{GPMC_AD6, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad6.vout3_d6 */
+	{GPMC_AD7, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad7.vout3_d7 */
+	{GPMC_AD8, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad8.vout3_d8 */
+	{GPMC_AD9, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad9.vout3_d9 */
+	{GPMC_AD10, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad10.vout3_d10 */
+	{GPMC_AD11, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad11.vout3_d11 */
+	{GPMC_AD12, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad12.vout3_d12 */
+	{GPMC_AD13, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad13.vout3_d13 */
+	{GPMC_AD14, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad14.vout3_d14 */
+	{GPMC_AD15, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad15.vout3_d15 */
+	{GPMC_A0, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a0.vout3_d16 */
+	{GPMC_A1, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a1.vout3_d17 */
+	{GPMC_A2, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a2.vout3_d18 */
+	{GPMC_A3, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a3.vout3_d19 */
+	{GPMC_A4, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a4.vout3_d20 */
+	{GPMC_A5, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a5.vout3_d21 */
+	{GPMC_A6, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a6.vout3_d22 */
+	{GPMC_A7, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a7.vout3_d23 */
+	{GPMC_A8, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a8.vout3_hsync */
+	{GPMC_A9, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a9.vout3_vsync */
+	{GPMC_A10, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a10.vout3_de */
+	{GPMC_A11, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a11.gpio2_1 */
+	{GPMC_A12, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a12.gpio2_2 */
+	{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS0, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_cs0.gpmc_cs0 */
+	{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
+	{GPMC_CS3, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_cs3.vout3_clk */
+	{GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_advn_ale.gpmc_advn_ale */
+	{GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_oen_ren.gpmc_oen_ren */
+	{GPMC_WEN, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_wen.gpmc_wen */
+	{GPMC_BEN0, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_ben0.gpmc_ben0 */
+	{GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* gpmc_wait0.gpmc_wait0 */
+	{VIN1A_FLD0, (M14 | PIN_INPUT_PULLUP)},	/* vin1a_fld0.gpio3_1 */
+	{VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_clk0.vin2a_clk0 */
+	{VIN2A_DE0, (M15 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_de0.Driveroff */
+	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_fld0.gpio3_30 */
+	{VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_hsync0.vin2a_hsync0 */
+	{VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_vsync0.vin2a_vsync0 */
+	{VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d0.vin2a_d0 */
+	{VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d1.vin2a_d1 */
+	{VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d2.vin2a_d2 */
+	{VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d3.vin2a_d3 */
+	{VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d4.vin2a_d4 */
+	{VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d5.vin2a_d5 */
+	{VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d6.vin2a_d6 */
+	{VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d7.vin2a_d7 */
+	{VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d8.vin2a_d8 */
+	{VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d9.vin2a_d9 */
+	{VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d10.vin2a_d10 */
+	{VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d11.vin2a_d11 */
+	{VIN2A_D12, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_de.vout1_de */
+	{VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)},	/* vout1_fld.gpio4_21 */
+	{VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d23.vout1_d23 */
+	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{RGMII0_TXC, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_14.i2c3_sda */
+	{GPIO6_15, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_15.i2c3_scl */
+	{GPIO6_16, (M0 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
+	{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.atl_clk2 */
+	{MCASP1_ACLKX, (M14 | 0x00070000)},	/* mcasp1_aclkx.gpio7_31 */
+	{MCASP1_FSX, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_fsx.gpio7_30 */
+	{MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.i2c5_sda */
+	{MCASP1_AXR1, (M10 | 0x000f0000)},	/* mcasp1_axr1.i2c5_scl */
+	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr12.mcasp7_axr0 */
+	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.mcasp7_axr1 */
+	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr14.mcasp7_aclkx */
+	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr15.mcasp7_fsx */
+	{MCASP2_ACLKR, (M15 | PIN_INPUT_PULLUP)},	/* mcasp2_aclkr.Driveroff */
+	{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.mcasp3_aclkx */
+	{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.mcasp3_fsx */
+	{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_axr0.mcasp3_axr0 */
+	{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)},	/* mcasp3_axr1.mcasp3_axr1 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mmc1_sdcd.mmc1_sdcd */
+	{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)},	/* mmc1_sdwp.gpio6_28 */
+	{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.spi1_sclk */
+	{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.spi1_d1 */
+	{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.spi1_d0 */
+	{SPI1_CS0, (M0 | PIN_INPUT_PULLUP)},	/* spi1_cs0.spi1_cs0 */
+	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)},	/* spi2_sclk.uart3_rxd */
+	{SPI2_D1, (M1 | PIN_INPUT_SLEW)},	/* spi2_d1.uart3_txd */
+	{SPI2_D0, (M1 | PIN_INPUT_SLEW)},	/* spi2_d0.uart3_ctsn */
+	{SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.uart3_rtsn */
+	{DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_tx.dcan1_tx */
+	{DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.dcan1_rx */
+	{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_txd.uart1_txd */
+	{UART1_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_ctsn.mmc4_clk */
+	{UART1_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_rtsn.mmc4_cmd */
+	{UART2_RXD, (M3 | PIN_INPUT_PULLUP)},	/* N/A.mmc4_dat0 */
+	{UART2_TXD, (M3 | PIN_INPUT_PULLUP)},	/* uart2_txd.mmc4_dat1 */
+	{UART2_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_ctsn.mmc4_dat2 */
+	{UART2_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rtsn.mmc4_dat3 */
+	{I2C2_SDA, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M14 | PIN_OUTPUT)},	/* N/A.gpio1_0 */
+	{WAKEUP1, (M14 | PIN_OUTPUT)},	/* N/A.gpio1_1 */
+	{WAKEUP2, (M14 | PIN_INPUT)},	/* N/A.gpio1_2 */
+	{WAKEUP3, (M1 | PIN_OUTPUT)},	/* N/A.sys_nirq1 */
+};
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {
+	{0x06F0, 480, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 111, 1641},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 272, 1116},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 243, 1260},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 0, 1614},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 105, 1673},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 0, 0},		/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 1560, 120},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 1570, 120},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 1500, 120},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 1775, 120},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 1875, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x08D0, 0, 0},		/* CFG_VIN1A_CLK0_IN */
+	{0x08DC, 2600, 0},	/* CFG_VIN1A_D0_IN */
+	{0x08E8, 2652, 46},	/* CFG_VIN1A_D10_IN */
+	{0x08F4, 2541, 0},	/* CFG_VIN1A_D11_IN */
+	{0x0900, 2603, 574},	/* CFG_VIN1A_D12_IN */
+	{0x090C, 2548, 443},	/* CFG_VIN1A_D13_IN */
+	{0x0918, 2624, 598},	/* CFG_VIN1A_D14_IN */
+	{0x0924, 2535, 1027},	/* CFG_VIN1A_D15_IN */
+	{0x0930, 2526, 818},	/* CFG_VIN1A_D16_IN */
+	{0x093C, 2623, 797},	/* CFG_VIN1A_D17_IN */
+	{0x0948, 2578, 888},	/* CFG_VIN1A_D18_IN */
+	{0x0954, 2574, 1008},	/* CFG_VIN1A_D19_IN */
+	{0x0960, 2527, 123},	/* CFG_VIN1A_D1_IN */
+	{0x096C, 2577, 737},	/* CFG_VIN1A_D20_IN */
+	{0x0978, 2627, 616},	/* CFG_VIN1A_D21_IN */
+	{0x0984, 2573, 777},	/* CFG_VIN1A_D22_IN */
+	{0x0990, 2730, 67},	/* CFG_VIN1A_D23_IN */
+	{0x099C, 2509, 303},	/* CFG_VIN1A_D2_IN */
+	{0x09A8, 2494, 267},	/* CFG_VIN1A_D3_IN */
+	{0x09B4, 2474, 0},	/* CFG_VIN1A_D4_IN */
+	{0x09C0, 2556, 181},	/* CFG_VIN1A_D5_IN */
+	{0x09CC, 2516, 195},	/* CFG_VIN1A_D6_IN */
+	{0x09D8, 2589, 210},	/* CFG_VIN1A_D7_IN */
+	{0x09E4, 2624, 75},	/* CFG_VIN1A_D8_IN */
+	{0x09F0, 2704, 14},	/* CFG_VIN1A_D9_IN */
+	{0x09FC, 2469, 55},	/* CFG_VIN1A_DE0_IN */
+	{0x0A08, 2557, 264},	/* CFG_VIN1A_FLD0_IN */
+	{0x0A14, 2465, 269},	/* CFG_VIN1A_HSYNC0_IN */
+	{0x0A20, 2411, 348},	/* CFG_VIN1A_VSYNC0_IN */
+	{0x0A70, 150, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 1500, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 1600, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 900, 0},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 680, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 500, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 702, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 136, 976},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 210, 1357},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 189, 1462},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 232, 1278},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1397},	/* CFG_VIN2A_D23_IN */
+	{0x0144, 0, 0},         /* CFG_GPMC_A13_IN */
+	{0x0150, 1976, 1389},   /* CFG_GPMC_A14_IN */
+	{0x015C, 1872, 1408},   /* CFG_GPMC_A15_IN */
+	{0x0168, 1914, 1506},   /* CFG_GPMC_A16_IN */
+	{0x0170, 57, 0},        /* CFG_GPMC_A16_OUT */
+	{0x0174, 1904, 1471},   /* CFG_GPMC_A17_IN */
+	{0x0188, 1690, 0},      /* CFG_GPMC_A18_OUT */
+	{0x0374, 0, 0},         /* CFG_GPMC_CS2_OUT */
+};
+
+const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
+	{0x06F0, 471, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 30, 1919},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 74, 1688},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 94, 1697},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 0, 1703},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 70, 1804},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 70, 70},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 35, 70},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 100, 130},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 0, 70},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 0},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 100, 130},	/* CFG_RGMII0_TXD3_OUT */
+	{0x08D0, 0, 0},	/* CFG_VIN1A_CLK0_IN */
+	{0x08DC, 2105, 619},	/* CFG_VIN1A_D0_IN */
+	{0x08E8, 2107, 739},	/* CFG_VIN1A_D10_IN */
+	{0x08F4, 2005, 788},	/* CFG_VIN1A_D11_IN */
+	{0x0900, 2059, 1297},	/* CFG_VIN1A_D12_IN */
+	{0x090C, 2027, 1141},	/* CFG_VIN1A_D13_IN */
+	{0x0918, 2071, 1332},	/* CFG_VIN1A_D14_IN */
+	{0x0924, 1995, 1764},	/* CFG_VIN1A_D15_IN */
+	{0x0930, 1999, 1542},	/* CFG_VIN1A_D16_IN */
+	{0x093C, 2072, 1540},	/* CFG_VIN1A_D17_IN */
+	{0x0948, 2034, 1629},	/* CFG_VIN1A_D18_IN */
+	{0x0954, 2026, 1761},	/* CFG_VIN1A_D19_IN */
+	{0x0960, 2017, 757},	/* CFG_VIN1A_D1_IN */
+	{0x096C, 2037, 1469},	/* CFG_VIN1A_D20_IN */
+	{0x0978, 2077, 1349},	/* CFG_VIN1A_D21_IN */
+	{0x0984, 2022, 1545},	/* CFG_VIN1A_D22_IN */
+	{0x0990, 2168, 784},	/* CFG_VIN1A_D23_IN */
+	{0x099C, 1996, 962},	/* CFG_VIN1A_D2_IN */
+	{0x09A8, 1993, 901},	/* CFG_VIN1A_D3_IN */
+	{0x09B4, 2098, 499},	/* CFG_VIN1A_D4_IN */
+	{0x09C0, 2038, 844},	/* CFG_VIN1A_D5_IN */
+	{0x09CC, 2002, 863},	/* CFG_VIN1A_D6_IN */
+	{0x09D8, 2063, 873},	/* CFG_VIN1A_D7_IN */
+	{0x09E4, 2088, 759},	/* CFG_VIN1A_D8_IN */
+	{0x09F0, 2152, 701},	/* CFG_VIN1A_D9_IN */
+	{0x09FC, 1926, 728},	/* CFG_VIN1A_DE0_IN */
+	{0x0A08, 2043, 937},	/* CFG_VIN1A_FLD0_IN */
+	{0x0A14, 1978, 909},	/* CFG_VIN1A_HSYNC0_IN */
+	{0x0A20, 1926, 987},	/* CFG_VIN1A_VSYNC0_IN */
+	{0x0A70, 140, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 90, 70},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 0, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 0, 0},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 0, 70},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 0, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 612, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 4, 927},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 136, 1340},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 130, 1450},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 144, 1269},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1330},	/* CFG_VIN2A_D23_IN */
+	{0x0144, 0, 0},         /* CFG_GPMC_A13_IN */
+	{0x0150, 2575, 966},    /* CFG_GPMC_A14_IN */
+	{0x015C, 2503, 889},    /* CFG_GPMC_A15_IN */
+	{0x0168, 2528, 1007},   /* CFG_GPMC_A16_IN */
+	{0x0170, 0, 0},         /* CFG_GPMC_A16_OUT */
+	{0x0174, 2533, 980},    /* CFG_GPMC_A17_IN */
+	{0x0188, 590, 0},       /* CFG_GPMC_A18_OUT */
+	{0x0374, 0, 0},         /* CFG_GPMC_CS2_OUT */
+};
+
+const struct iodelay_cfg_entry dra76x_es1_0_iodelay_cfg_array[] = {
+	{0x011C, 787, 0},	/* CFG_GPMC_A0_OUT */
+	{0x0128, 1181, 0},	/* CFG_GPMC_A10_OUT */
+	{0x0144, 0, 0},	/* CFG_GPMC_A13_IN */
+	{0x0150, 2149, 1052},	/* CFG_GPMC_A14_IN */
+	{0x015C, 2121, 997},	/* CFG_GPMC_A15_IN */
+	{0x0168, 2159, 1134},	/* CFG_GPMC_A16_IN */
+	{0x0170, 0, 0},	/* CFG_GPMC_A16_OUT */
+	{0x0174, 2135, 1085},	/* CFG_GPMC_A17_IN */
+	{0x0188, 0, 0},	/* CFG_GPMC_A18_OUT */
+	{0x01A0, 592, 0},	/* CFG_GPMC_A1_OUT */
+	{0x020C, 641, 0},	/* CFG_GPMC_A2_OUT */
+	{0x0218, 1481, 0},	/* CFG_GPMC_A3_OUT */
+	{0x0224, 1775, 0},	/* CFG_GPMC_A4_OUT */
+	{0x0230, 785, 0},	/* CFG_GPMC_A5_OUT */
+	{0x023C, 848, 0},	/* CFG_GPMC_A6_OUT */
+	{0x0248, 851, 0},	/* CFG_GPMC_A7_OUT */
+	{0x0254, 1783, 0},	/* CFG_GPMC_A8_OUT */
+	{0x0260, 951, 0},	/* CFG_GPMC_A9_OUT */
+	{0x026C, 1091, 0},	/* CFG_GPMC_AD0_OUT */
+	{0x0278, 1027, 0},	/* CFG_GPMC_AD10_OUT */
+	{0x0284, 824, 0},	/* CFG_GPMC_AD11_OUT */
+	{0x0290, 1196, 0},	/* CFG_GPMC_AD12_OUT */
+	{0x029C, 754, 0},	/* CFG_GPMC_AD13_OUT */
+	{0x02A8, 665, 0},	/* CFG_GPMC_AD14_OUT */
+	{0x02B4, 1027, 0},	/* CFG_GPMC_AD15_OUT */
+	{0x02C0, 937, 0},	/* CFG_GPMC_AD1_OUT */
+	{0x02CC, 1168, 0},	/* CFG_GPMC_AD2_OUT */
+	{0x02D8, 872, 0},	/* CFG_GPMC_AD3_OUT */
+	{0x02E4, 1092, 0},	/* CFG_GPMC_AD4_OUT */
+	{0x02F0, 576, 0},	/* CFG_GPMC_AD5_OUT */
+	{0x02FC, 1113, 0},	/* CFG_GPMC_AD6_OUT */
+	{0x0308, 943, 0},	/* CFG_GPMC_AD7_OUT */
+	{0x0314, 0, 0},	/* CFG_GPMC_AD8_OUT */
+	{0x0320, 0, 0},	/* CFG_GPMC_AD9_OUT */
+	{0x0374, 0, 0},	/* CFG_GPMC_CS2_OUT */
+	{0x0380, 1801, 948},	/* CFG_GPMC_CS3_OUT */
+	{0x06F0, 451, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 127, 1571},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 165, 1178},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 136, 1302},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 0, 1520},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 28, 1690},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 121, 0},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 60, 0},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 153, 0},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 35, 0},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 0},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 172, 0},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A38, 0, 0},	/* CFG_VIN2A_CLK0_IN */
+	{0x0A44, 2180, 0},	/* CFG_VIN2A_D0_IN */
+	{0x0A50, 2297, 110},	/* CFG_VIN2A_D10_IN */
+	{0x0A5C, 1938, 0},	/* CFG_VIN2A_D11_IN */
+	{0x0A70, 147, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 110, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 18, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 82, 0},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 33, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 0, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 417, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 156, 843},	/* CFG_VIN2A_D19_IN */
+	{0x0AC8, 2326, 309},	/* CFG_VIN2A_D1_IN */
+	{0x0AD4, 223, 1413},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 169, 1415},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 43, 1150},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1210},	/* CFG_VIN2A_D23_IN */
+	{0x0B04, 2057, 0},	/* CFG_VIN2A_D2_IN */
+	{0x0B10, 2440, 257},	/* CFG_VIN2A_D3_IN */
+	{0x0B1C, 2142, 0},	/* CFG_VIN2A_D4_IN */
+	{0x0B28, 2455, 252},	/* CFG_VIN2A_D5_IN */
+	{0x0B34, 1883, 0},	/* CFG_VIN2A_D6_IN */
+	{0x0B40, 2229, 0},	/* CFG_VIN2A_D7_IN */
+	{0x0B4C, 2250, 151},	/* CFG_VIN2A_D8_IN */
+	{0x0B58, 2279, 27},	/* CFG_VIN2A_D9_IN */
+	{0x0B7C, 2233, 0},	/* CFG_VIN2A_HSYNC0_IN */
+	{0x0B88, 1936, 0},	/* CFG_VIN2A_VSYNC0_IN */
+	{0x0B9C, 1281, 497},	/* CFG_VOUT1_CLK_OUT */
+	{0x0BA8, 379, 0},	/* CFG_VOUT1_D0_OUT */
+	{0x0BB4, 441, 0},	/* CFG_VOUT1_D10_OUT */
+	{0x0BC0, 461, 0},	/* CFG_VOUT1_D11_OUT */
+	{0x0BCC, 1189, 0},	/* CFG_VOUT1_D12_OUT */
+	{0x0BD8, 312, 0},	/* CFG_VOUT1_D13_OUT */
+	{0x0BE4, 298, 0},	/* CFG_VOUT1_D14_OUT */
+	{0x0BF0, 284, 0},	/* CFG_VOUT1_D15_OUT */
+	{0x0BFC, 152, 0},	/* CFG_VOUT1_D16_OUT */
+	{0x0C08, 216, 0},	/* CFG_VOUT1_D17_OUT */
+	{0x0C14, 408, 0},	/* CFG_VOUT1_D18_OUT */
+	{0x0C20, 519, 0},	/* CFG_VOUT1_D19_OUT */
+	{0x0C2C, 475, 0},	/* CFG_VOUT1_D1_OUT */
+	{0x0C38, 316, 0},	/* CFG_VOUT1_D20_OUT */
+	{0x0C44, 59, 0},	/* CFG_VOUT1_D21_OUT */
+	{0x0C50, 221, 0},	/* CFG_VOUT1_D22_OUT */
+	{0x0C5C, 96, 0},	/* CFG_VOUT1_D23_OUT */
+	{0x0C68, 264, 0},	/* CFG_VOUT1_D2_OUT */
+	{0x0C74, 421, 0},	/* CFG_VOUT1_D3_OUT */
+	{0x0C80, 1257, 0},	/* CFG_VOUT1_D4_OUT */
+	{0x0C8C, 432, 0},	/* CFG_VOUT1_D5_OUT */
+	{0x0C98, 436, 0},	/* CFG_VOUT1_D6_OUT */
+	{0x0CA4, 440, 0},	/* CFG_VOUT1_D7_OUT */
+	{0x0CB0, 81, 100},	/* CFG_VOUT1_D8_OUT */
+	{0x0CBC, 471, 0},	/* CFG_VOUT1_D9_OUT */
+	{0x0CC8, 0, 0},	/* CFG_VOUT1_DE_OUT */
+	{0x0CE0, 0, 0},	/* CFG_VOUT1_HSYNC_OUT */
+	{0x0CEC, 815, 0},	/* CFG_VOUT1_VSYNC_OUT */
+};
+#endif
+
+#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/roms/u-boot/board/ti/evm/Kconfig b/roms/u-boot/board/ti/evm/Kconfig
new file mode 100644
index 000000000..4f490ddd9
--- /dev/null
+++ b/roms/u-boot/board/ti/evm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP3_EVM
+
+config SYS_BOARD
+	default "evm"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_CONFIG_NAME
+	default "omap3_evm"
+
+endif
diff --git a/roms/u-boot/board/ti/evm/MAINTAINERS b/roms/u-boot/board/ti/evm/MAINTAINERS
new file mode 100644
index 000000000..cd315c163
--- /dev/null
+++ b/roms/u-boot/board/ti/evm/MAINTAINERS
@@ -0,0 +1,6 @@
+EVM BOARD
+M:	Derald D. Woods <woods.technical@gmail.com>
+S:	Maintained
+F:	board/ti/evm/
+F:	include/configs/omap3_evm.h
+F:	configs/omap3_evm_defconfig
diff --git a/roms/u-boot/board/ti/evm/Makefile b/roms/u-boot/board/ti/evm/Makefile
new file mode 100644
index 000000000..17ee516d2
--- /dev/null
+++ b/roms/u-boot/board/ti/evm/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= evm.o
diff --git a/roms/u-boot/board/ti/evm/evm.c b/roms/u-boot/board/ti/evm/evm.c
new file mode 100644
index 000000000..96434b3ba
--- /dev/null
+++ b/roms/u-boot/board/ti/evm/evm.c
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2004-2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ */
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <ns16550.h>
+#include <serial.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/gpio.h>
+#include <twl4030.h>
+#include <asm/mach-types.h>
+#include <linux/delay.h>
+#include <linux/mtd/rawnand.h>
+#include "evm.h"
+
+#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
+#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
+
+#define CONFIG_SMC911X_BASE 0x2C000000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 omap3_evm_version;
+
+u32 get_omap3_evm_rev(void)
+{
+	return omap3_evm_version;
+}
+
+static void omap3_evm_get_revision(void)
+{
+#if defined(CONFIG_SMC911X)
+	/*
+	 * Board revision can be ascertained only by identifying
+	 * the Ethernet chipset.
+	 */
+	unsigned int smsc_id;
+
+	/* Ethernet PHY ID is stored at ID_REV register */
+	smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
+	printf("Read back SMSC id 0x%x\n", smsc_id);
+
+	switch (smsc_id) {
+	/* SMSC9115 chipset */
+	case 0x01150000:
+		omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
+		break;
+	/* SMSC 9220 chipset */
+	case 0x92200000:
+	default:
+		omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
+       }
+#else /* !CONFIG_SMC911X */
+#if defined(CONFIG_STATIC_BOARD_REV)
+	/* Look for static defintion of the board revision */
+	omap3_evm_version = CONFIG_STATIC_BOARD_REV;
+#else
+	/* Fallback to the default above */
+	omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
+#endif /* CONFIG_STATIC_BOARD_REV */
+#endif /* CONFIG_SMC911X */
+}
+
+#if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
+/* MUSB port on OMAP3EVM Rev >= E requires extvbus programming. */
+u8 omap3_evm_need_extvbus(void)
+{
+	u8 retval = 0;
+
+	if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
+		retval = 1;
+
+	return retval;
+}
+#endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#if defined(CONFIG_SPL_BUILD)
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank.  This
+ * provides the timing values back to the function that configures
+ * the memory.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+	int pop_mfr, pop_id;
+
+	/*
+	 * We need to identify what PoP memory is on the board so that
+	 * we know what timings to use.  To map the ID values please see
+	 * nand_ids.c
+	 */
+	identify_nand_chip(&pop_mfr, &pop_id);
+
+	if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
+		/* 256MB DDR */
+		timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+		timings->ctrla = HYNIX_V_ACTIMA_200;
+		timings->ctrlb = HYNIX_V_ACTIMB_200;
+	} else {
+		/* 128MB DDR */
+		timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+		timings->ctrla = MICRON_V_ACTIMA_165;
+		timings->ctrlb = MICRON_V_ACTIMB_165;
+	}
+	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+	timings->mr = MICRON_V_MR_165;
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/*
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+	twl4030_power_init();
+
+#if defined(CONFIG_SMC911X)
+	setup_net_chip();
+#endif
+	omap3_evm_get_revision();
+
+#if defined(CONFIG_SMC911X)
+	reset_net_chip();
+#endif
+	omap_die_id_display();
+
+#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && \
+						!defined(CONFIG_SMC911X)
+	omap_die_id_usbethaddr();
+#endif
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_EVM();
+}
+
+#if defined(CONFIG_SMC911X)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *		Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	/* Configure GPMC registers */
+	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
+	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
+	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
+	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
+	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
+	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
+	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+}
+
+/**
+ * Reset the ethernet chip.
+ */
+static void reset_net_chip(void)
+{
+	int ret;
+	int rst_gpio;
+
+	if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
+		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
+	} else {
+		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
+	}
+
+	ret = gpio_request(rst_gpio, "");
+	if (ret < 0) {
+		printf("Unable to get GPIO %d\n", rst_gpio);
+		return ;
+	}
+
+	/* Configure as output */
+	gpio_direction_output(rst_gpio, 0);
+
+	/* Send a pulse on the GPIO pin */
+	gpio_set_value(rst_gpio, 1);
+	udelay(1);
+	gpio_set_value(rst_gpio, 0);
+	udelay(1);
+	gpio_set_value(rst_gpio, 1);
+}
+#endif /* CONFIG_SMC911X */
+
+#if defined(CONFIG_MMC)
+void board_mmc_power_init(void)
+{
+	twl4030_power_mmc_init(0);
+}
+#endif /* CONFIG_MMC */
diff --git a/roms/u-boot/board/ti/evm/evm.h b/roms/u-boot/board/ti/evm/evm.h
new file mode 100644
index 000000000..09b08b490
--- /dev/null
+++ b/roms/u-boot/board/ti/evm/evm.h
@@ -0,0 +1,394 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008
+ * Nishanth Menon <menon.nishanth@gmail.com>
+ */
+#ifndef _EVM_H_
+#define _EVM_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"OMAP3 EVM board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	"OneNAND",
+#else
+	"NAND",
+#endif
+};
+
+/*
+ * OMAP35x EVM revision
+ * Run time detection of EVM revision is done by reading Ethernet
+ * PHY ID -
+ *      GEN_1   = 0x01150000
+ *      GEN_2   = 0x92200000
+ */
+enum {
+	OMAP3EVM_BOARD_GEN_1 = 0,	/* EVM Rev between  A - D */
+	OMAP3EVM_BOARD_GEN_2,		/* EVM Rev >= Rev E */
+};
+
+u32 get_omap3_evm_rev(void);
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+static void reset_net_chip(void);
+#endif
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_EVM() \
+ /*SDRC*/\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) /*GPMC_A8*/\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) /*GPMC_A9*/\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) /*GPMC_A10*/\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)) /*GPMC_nCS4*/\
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) /*GPMC_nCS6*/\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) /*GPMC_nCS7*/\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) /*GPMC_CLK*/\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) /*GPMC_nBE0_CLE*/\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) /*GPMC_nBE1*/\
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+								 /* - ETH_nRESET*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+ /*DSS*/\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+								 /* - CAM_RESET*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card  */\
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | DIS | M0)) /*MMC2_CLK*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IDIS | PTD | DIS | M0)) /*MMC2_DAT4*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IDIS | PTD | DIS | M0)) /*MMC2_DAT5*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IDIS | PTD | DIS | M0)) /*MMC2_DAT6 */\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT7*/\
+ /*Bluetooth*/\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) /*McBSP3_DR*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP3_CLKX  */\
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP3_FSX*/\
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) /*UART2_RX*/\
+ /*Modem Interface */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) /*UART1_CTS*/\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+								 /* - LCD_INI*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+								 /* - LCD_ENVDD */\
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+								 /* - LCD_QVGA/nVGA */\
+	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+								 /* - LCD_RESB */\
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) /*MCBSP1_CLKR  */\
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) /*MCBSP1_FSR*/\
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) /*MCBSP1_DX*/\
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) /*MCBSP1_DR*/\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*MCBSP_CLKS  */\
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) /*MCBSP1_FSX*/\
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) /*MCBSP1_CLKX  */\
+ /*Serial Interface*/\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_*/\
+								 /* RCTX*/\
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) /*HDQ_SIO*/\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI1_SIMO  */\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI  */\
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
+								 /* TS_PEN_IRQ */\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
+								 /* - LAN_INTR*/\
+ /* USB EHCI (port 2) */\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA2*/\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA7*/\
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA4*/\
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA5*/\
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA6*/\
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA3*/\
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DIR*/\
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_NXT*/\
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA0*/\
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA1*/\
+ /*Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+								 /* - PEN_IRQ */\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+								 /* - VIO_1V8*/\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) /*SYS_CLKOUT2*/\
+	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) /*JTAG_NTRST*/\
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) /*JTAG_TCK*/\
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) /*JTAG_TMS*/\
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) /*JTAG_TDI*/\
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU0*/\
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU1*/\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M0)) /*ETK_CLK*/\
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M0)) /*ETK_CTL*/\
+	MUX_VAL(CP(ETK_D0_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D0*/\
+	MUX_VAL(CP(ETK_D1_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D1*/\
+	MUX_VAL(CP(ETK_D2_ES2 ),	(IEN  | PTD | EN  | M0)) /*ETK_D2*/\
+	MUX_VAL(CP(ETK_D3_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D3*/\
+	MUX_VAL(CP(ETK_D4_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D4*/\
+	MUX_VAL(CP(ETK_D5_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D5*/\
+	MUX_VAL(CP(ETK_D6_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D6*/\
+	MUX_VAL(CP(ETK_D7_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D7*/\
+	MUX_VAL(CP(ETK_D8_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D8*/\
+	MUX_VAL(CP(ETK_D9_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D9*/\
+ /*Die to Die */\
+	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\
+
+#endif
diff --git a/roms/u-boot/board/ti/j721e/Kconfig b/roms/u-boot/board/ti/j721e/Kconfig
new file mode 100644
index 000000000..c28752a65
--- /dev/null
+++ b/roms/u-boot/board/ti/j721e/Kconfig
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+#	Lokesh Vutla <lokeshvutla@ti.com>
+
+choice
+	prompt "K3 J721E based boards"
+	optional
+
+config TARGET_J721E_A72_EVM
+	bool "TI K3 based J721E EVM running on A72"
+	select ARM64
+	select SOC_K3_J721E
+	select BOARD_LATE_INIT
+	imply TI_I2C_BOARD_DETECT
+	select SYS_DISABLE_DCACHE_OPS
+
+config TARGET_J721E_R5_EVM
+	bool "TI K3 based J721E EVM running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select SOC_K3_J721E
+	select K3_LOAD_SYSFW
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	imply SYS_K3_SPL_ATF
+	imply TI_I2C_BOARD_DETECT
+
+config TARGET_J7200_A72_EVM
+	bool "TI K3 based J7200 EVM running on A72"
+	select ARM64
+	select SOC_K3_J721E
+	select BOARD_LATE_INIT
+	imply TI_I2C_BOARD_DETECT
+	select SYS_DISABLE_DCACHE_OPS
+
+config TARGET_J7200_R5_EVM
+	bool "TI K3 based J7200 EVM running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select SOC_K3_J721E
+	select K3_LOAD_SYSFW
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	imply SYS_K3_SPL_ATF
+	imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+if TARGET_J721E_A72_EVM
+
+config SYS_BOARD
+       default "j721e"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "j721e_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J721E_R5_EVM
+
+config SYS_BOARD
+       default "j721e"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "j721e_evm"
+
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J7200_A72_EVM
+
+config SYS_BOARD
+       default "j721e"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "j721e_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J7200_R5_EVM
+
+config SYS_BOARD
+       default "j721e"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "j721e_evm"
+
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/ti/j721e/MAINTAINERS b/roms/u-boot/board/ti/j721e/MAINTAINERS
new file mode 100644
index 000000000..4b13f46dd
--- /dev/null
+++ b/roms/u-boot/board/ti/j721e/MAINTAINERS
@@ -0,0 +1,9 @@
+J721E BOARD
+M:	Lokesh Vutla <lokeshvutla@ti.com>
+S:	Maintained
+F:	board/ti/j721e
+F:	include/configs/j721e_evm.h
+F:	configs/j721e_evm_r5_defconfig
+F:	configs/j721e_evm_a72_defconfig
+F:	configs/j7200_evm_r5_defconfig
+F:	configs/j7200_evm_a72_defconfig
diff --git a/roms/u-boot/board/ti/j721e/Makefile b/roms/u-boot/board/ti/j721e/Makefile
new file mode 100644
index 000000000..97535f5d8
--- /dev/null
+++ b/roms/u-boot/board/ti/j721e/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+#	Lokesh Vutla <lokeshvutla@ti.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evm.o
diff --git a/roms/u-boot/board/ti/j721e/README b/roms/u-boot/board/ti/j721e/README
new file mode 100644
index 000000000..c33afa496
--- /dev/null
+++ b/roms/u-boot/board/ti/j721e/README
@@ -0,0 +1,274 @@
+Introduction:
+-------------
+The J721e family of SoCs are part of K3 Multicore SoC architecture platform
+targeting automotive applications. They are designed as a low power, high
+performance and highly integrated device architecture, adding significant
+enhancement on processing power, graphics capability, video and imaging
+processing, virtualization and coherent memory support.
+
+The device is partitioned into three functional domains, each containing
+specific processing cores and peripherals:
+1. Wake-up (WKUP) domain:
+	- Device Management and Security Controller (DMSC)
+2. Microcontroller (MCU) domain:
+	- Dual Core ARM Cortex-R5F processor
+3. MAIN domain:
+	- Dual core 64-bit ARM Cortex-A72
+	- 2 x Dual cortex ARM Cortex-R5 subsystem
+	- 2 x C66x Digital signal processor sub system
+	- C71x Digital signal processor sub-system with MMA.
+
+More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1
+
+Boot Flow:
+----------
+Boot flow is similar to that of AM65x SoC and extending it with remoteproc
+support. Below is the pictorial representation of boot flow:
+
++------------------------------------------------------------------------+-----------------------+
+|        DMSC            |      MCU R5           |        A72            |  MAIN R5/C66x/C7x     |
++------------------------------------------------------------------------+-----------------------+
+|    +--------+          |                       |                       |                       |
+|    |  Reset |          |                       |                       |                       |
+|    +--------+          |                       |                       |                       |
+|         :              |                       |                       |                       |
+|    +--------+          |   +-----------+       |                       |                       |
+|    | *ROM*  |----------|-->| Reset rls |       |                       |                       |
+|    +--------+          |   +-----------+       |                       |                       |
+|    |        |          |         :             |                       |                       |
+|    |  ROM   |          |         :             |                       |                       |
+|    |services|          |         :             |                       |                       |
+|    |        |          |   +-------------+     |                       |                       |
+|    |        |          |   |  *R5 ROM*   |     |                       |                       |
+|    |        |          |   +-------------+     |                       |                       |
+|    |        |<---------|---|Load and auth|     |                       |                       |
+|    |        |          |   | tiboot3.bin |     |                       |                       |
+|    |        |          |   +-------------+     |                       |                       |
+|    |        |          |         :             |                       |                       |
+|    |        |          |         :             |                       |                       |
+|    |        |          |         :             |                       |                       |
+|    |        |          |   +-------------+     |                       |                       |
+|    |        |          |   |  *R5 SPL*   |     |                       |                       |
+|    |        |          |   +-------------+     |                       |                       |
+|    |        |          |   |    Load     |     |                       |                       |
+|    |        |          |   |  sysfw.itb  |     |                       |                       |
+|    | Start  |          |   +-------------+     |                       |                       |
+|    | System |<---------|---|    Start    |     |                       |                       |
+|    |Firmware|          |   |    SYSFW    |     |                       |                       |
+|    +--------+          |   +-------------+     |                       |                       |
+|        :               |   |             |     |                       |                       |
+|    +---------+         |   |   Load      |     |                       |                       |
+|    | *SYSFW* |         |   |   system    |     |                       |                       |
+|    +---------+         |   | Config data |     |                       |                       |
+|    |         |<--------|---|             |     |                       |                       |
+|    |         |         |   +-------------+     |                       |                       |
+|    |         |         |   |    DDR      |     |                       |                       |
+|    |         |         |   |   config    |     |                       |                       |
+|    |         |         |   +-------------+     |                       |                       |
+|    |         |         |   |    Load     |     |                       |                       |
+|    |         |         |   |  tispl.bin  |     |                       |                       |
+|    |         |         |   +-------------+     |                       |                       |
+|    |         |         |   |   Load R5   |     |                       |                       |
+|    |         |         |   |   firmware  |     |                       |                       |
+|    |         |         |   +-------------+     |                       |                       |
+|    |         |<--------|---| Start A72   |     |                       |                       |
+|    |         |         |   | and jump to |     |                       |                       |
+|    |         |         |   | next image  |     |                       |                       |
+|    |         |         |   +-------------+     |                       |                       |
+|    |         |         |                       |     +-----------+     |                       |
+|    |         |---------|-----------------------|---->| Reset rls |     |                       |
+|    |         |         |                       |     +-----------+     |                       |
+|    |  DMSC   |         |                       |          :            |                       |
+|    |Services |         |                       |     +-----------+     |                       |
+|    |         |<--------|-----------------------|---->|*ATF/OPTEE*|     |                       |
+|    |         |         |                       |     +-----------+     |                       |
+|    |         |         |                       |          :            |                       |
+|    |         |         |                       |     +-----------+     |                       |
+|    |         |<--------|-----------------------|---->| *A72 SPL* |     |                       |
+|    |         |         |                       |     +-----------+     |                       |
+|    |         |         |                       |     |   Load    |     |                       |
+|    |         |         |                       |     | u-boot.img|     |                       |
+|    |         |         |                       |     +-----------+     |                       |
+|    |         |         |                       |          :            |                       |
+|    |         |         |                       |     +-----------+     |                       |
+|    |         |<--------|-----------------------|---->| *U-Boot*  |     |                       |
+|    |         |         |                       |     +-----------+     |                       |
+|    |         |         |                       |     |  prompt   |     |                       |
+|    |         |         |                       |     +-----------+     |                       |
+|    |         |         |                       |     |  Load R5  |     |                       |
+|    |         |         |                       |     |  Firmware |     |                       |
+|    |         |         |                       |     +-----------+     |                       |
+|    |         |<--------|-----------------------|-----|  Start R5 |     |      +-----------+    |
+|    |         |---------|-----------------------|-----+-----------+-----|----->| R5 starts |    |
+|    |         |         |                       |     |  Load C6  |     |      +-----------+    |
+|    |         |         |                       |     |  Firmware |     |                       |
+|    |         |         |                       |     +-----------+     |                       |
+|    |         |<--------|-----------------------|-----|  Start C6 |     |      +-----------+    |
+|    |         |---------|-----------------------|-----+-----------+-----|----->| C6 starts |    |
+|    |         |         |                       |     |  Load C7  |     |      +-----------+    |
+|    |         |         |                       |     |  Firmware |     |                       |
+|    |         |         |                       |     +-----------+     |                       |
+|    |         |<--------|-----------------------|-----|  Start C7 |     |      +-----------+    |
+|    |         |---------|-----------------------|-----+-----------+-----|----->| C7 starts |    |
+|    +---------+         |                       |                       |      +-----------+    |
+|                        |                       |                       |                       |
++------------------------------------------------------------------------+-----------------------+
+
+- Here DMSC acts as master and provides all the critical services. R5/A72
+requests DMSC to get these services done as shown in the above diagram.
+
+Sources:
+--------
+1. SYSFW:
+	Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git
+	Branch: master
+
+2. ATF:
+	Tree: https://github.com/ARM-software/arm-trusted-firmware.git
+	Branch: master
+
+3. OPTEE:
+	Tree: https://github.com/OP-TEE/optee_os.git
+	Branch: master
+
+4. U-Boot:
+	Tree: https://source.denx.de/u-boot/u-boot
+	Branch: master
+
+Build procedure:
+----------------
+1. SYSFW:
+$ make CROSS_COMPILE=arm-linux-gnueabihf-
+
+2. ATF:
+$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed
+
+3. OPTEE:
+$ make PLATFORM=k3-j721e CFG_ARM64_core=y
+
+4. U-Boot:
+
+4.1. R5:
+$ make CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=/tmp/r5
+$ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
+
+4.2. A72:
+$ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72
+$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a72
+
+Target Images
+--------------
+Copy the below images to an SD card and boot:
+- sysfw.itb from step 1
+- tiboot3.bin from step 4.1
+- tispl.bin, u-boot.img from 4.2
+
+Image formats:
+--------------
+
+- tiboot3.bin:
+                +-----------------------+
+                |        X.509          |
+                |      Certificate      |
+                | +-------------------+ |
+                | |                   | |
+                | |        R5         | |
+                | |   u-boot-spl.bin  | |
+                | |                   | |
+                | +-------------------+ |
+                | |                   | |
+                | |     FIT header    | |
+                | | +---------------+ | |
+                | | |               | | |
+                | | |   DTB 1...N   | | |
+                | | +---------------+ | |
+                | +-------------------+ |
+                +-----------------------+
+
+- tispl.bin
+                +-----------------------+
+                |                       |
+                |       FIT HEADER      |
+                | +-------------------+ |
+                | |                   | |
+                | |      A72 ATF      | |
+                | +-------------------+ |
+                | |                   | |
+                | |     A72 OPTEE     | |
+                | +-------------------+ |
+                | |                   | |
+                | |      A72 SPL      | |
+                | +-------------------+ |
+                | |                   | |
+                | |   SPL DTB 1...N   | |
+                | +-------------------+ |
+                +-----------------------+
+
+- sysfw.itb
+                +-----------------------+
+                |                       |
+                |       FIT HEADER      |
+                | +-------------------+ |
+                | |                   | |
+                | |     sysfw.bin     | |
+                | +-------------------+ |
+                | |                   | |
+                | |    board config   | |
+                | +-------------------+ |
+                | |                   | |
+                | |     PM config     | |
+                | +-------------------+ |
+                | |                   | |
+                | |     RM config     | |
+                | +-------------------+ |
+                | |                   | |
+                | |    Secure config  | |
+                | +-------------------+ |
+                +-----------------------+
+
+OSPI:
+-----
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
+and sysfw.itb over tftp and then flash those to OSPI at their respective
+addresses.
+
+=> sf probe
+=> tftp ${loadaddr} tiboot3.bin
+=> sf update $loadaddr 0x0 $filesize
+=> tftp ${loadaddr} tispl.bin
+=> sf update $loadaddr 0x80000 $filesize
+=> tftp ${loadaddr} u-boot.img
+=> sf update $loadaddr 0x280000 $filesize
+=> tftp ${loadaddr} sysfw.itb
+=> sf update $loadaddr 0x6C0000 $filesize
+
+Flash layout for OSPI:
+
+         0x0 +----------------------------+
+             |     ospi.tiboot3(512K)     |
+             |                            |
+     0x80000 +----------------------------+
+             |     ospi.tispl(2M)         |
+             |                            |
+    0x280000 +----------------------------+
+             |     ospi.u-boot(4M)        |
+             |                            |
+    0x680000 +----------------------------+
+             |     ospi.env(128K)         |
+             |                            |
+    0x6A0000 +----------------------------+
+	     |	 ospi.env.backup (128K)   |
+	     |                            |
+    0x6C0000 +----------------------------+
+             |      ospi.sysfw(1M)        |
+             |                            |
+    0x7C0000 +----------------------------+
+	     |      padding (256k)        |
+    0x800000 +----------------------------+
+             |     ospi.rootfs(UBIFS)     |
+             |                            |
+             +----------------------------+
diff --git a/roms/u-boot/board/ti/j721e/evm.c b/roms/u-boot/board/ti/j721e/evm.c
new file mode 100644
index 000000000..b9a9f1955
--- /dev/null
+++ b/roms/u-boot/board/ti/j721e/evm.c
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for J721E EVM
+ *
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ */
+
+#include <common.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <spl.h>
+#include <asm/arch/sys_proto.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+
+#include "../common/board_detect.h"
+
+#define board_is_j721e_som()	(board_ti_k3_is("J721EX-PM1-SOM") || \
+				 board_ti_k3_is("J721EX-PM2-SOM"))
+
+#define board_is_j7200_som()	board_ti_k3_is("J7200X-PM1-SOM")
+
+/* Max number of MAC addresses that are parsed/processed per daughter card */
+#define DAUGHTER_CARD_NO_OF_MAC_ADDR	8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+#ifdef CONFIG_PHYS_64BIT
+	gd->ram_size = 0x100000000;
+#else
+	gd->ram_size = 0x80000000;
+#endif
+
+	return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_PHYS_64BIT
+	/* Limit RAM used by U-Boot to the DDR low region */
+	if (gd->ram_top > 0x100000000)
+		return 0x100000000;
+#endif
+
+	return gd->ram_top;
+}
+
+int dram_init_banksize(void)
+{
+	/* Bank 0 declares the memory available in the DDR low region */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = 0x80000000;
+	gd->ram_size = 0x80000000;
+
+#ifdef CONFIG_PHYS_64BIT
+	/* Bank 1 declares the memory available in the DDR high region */
+	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+	gd->bd->bi_dram[1].size = 0x80000000;
+	gd->ram_size = 0x100000000;
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (!strcmp(name, "k3-j721e-common-proc-board"))
+		return 0;
+
+	return -1;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(OF_LIBFDT)
+/* Returns 1, if onboard mux is set to hyperflash */
+static void __maybe_unused detect_enable_hyperflash(void *blob)
+{
+	struct gpio_desc desc = {0};
+
+	if (dm_gpio_lookup_name("6", &desc))
+		return;
+
+	if (dm_gpio_request(&desc, "6"))
+		return;
+
+	if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN))
+		return;
+
+	if (dm_gpio_get_value(&desc)) {
+		int offset;
+
+		do_fixup_by_compat(blob, "ti,am654-hbmc", "status",
+				   "okay", sizeof("okay"), 0);
+		offset = fdt_node_offset_by_compatible(blob, -1,
+						       "ti,am654-ospi");
+		fdt_setprop(blob, offset, "status", "disabled",
+			    sizeof("disabled"));
+	}
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	detect_enable_hyperflash(spl_image->fdt_addr);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int ret;
+
+	ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
+	if (ret < 0)
+		ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
+					 "sram@70000000");
+	if (ret)
+		printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
+
+	detect_enable_hyperflash(blob);
+
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+int do_board_detect(void)
+{
+	int ret;
+
+	ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+					 CONFIG_EEPROM_CHIP_ADDRESS);
+	if (ret)
+		pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+		       CONFIG_EEPROM_CHIP_ADDRESS, ret);
+
+	return ret;
+}
+
+int checkboard(void)
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+	if (do_board_detect())
+		/* EEPROM not populated */
+		printf("Board: %s rev %s\n", "J721EX-PM1-SOM", "E2");
+	else
+		printf("Board: %s rev %s\n", ep->name, ep->version);
+
+	return 0;
+}
+
+static void setup_board_eeprom_env(void)
+{
+	char *name = "j721e";
+
+	if (do_board_detect())
+		goto invalid_eeprom;
+
+	if (board_is_j721e_som())
+		name = "j721e";
+	else if (board_is_j7200_som())
+		name = "j7200";
+	else
+		printf("Unidentified board claims %s in eeprom header\n",
+		       board_ti_get_name());
+
+invalid_eeprom:
+	set_board_info_env_am6(name);
+}
+
+static void setup_serial(void)
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+	unsigned long board_serial;
+	char *endp;
+	char serial_string[17] = { 0 };
+
+	if (env_get("serial#"))
+		return;
+
+	board_serial = simple_strtoul(ep->serial, &endp, 16);
+	if (*endp != '\0') {
+		pr_err("Error: Can't set serial# to %s\n", ep->serial);
+		return;
+	}
+
+	snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
+	env_set("serial#", serial_string);
+}
+
+/*
+ * Declaration of daughtercards to probe. Note that when adding more
+ * cards they should be grouped by the 'i2c_addr' field to allow for a
+ * more efficient probing process.
+ */
+static const struct {
+	u8 i2c_addr;		/* I2C address of card EEPROM */
+	char *card_name;	/* EEPROM-programmed card name */
+	char *dtbo_name;	/* Device tree overlay to apply */
+	u8 eth_offset;		/* ethXaddr MAC address index offset */
+} ext_cards[] = {
+	{
+		0x51,
+		"J7X-BASE-CPB",
+		"",		/* No dtbo for this board */
+		0,
+	},
+	{
+		0x52,
+		"J7X-INFOTAN-EXP",
+		"",		/* No dtbo for this board */
+		0,
+	},
+	{
+		0x52,
+		"J7X-GESI-EXP",
+		"",		/* No dtbo for this board */
+		5,		/* Start populating from eth5addr */
+	},
+	{
+		0x54,
+		"J7X-VSC8514-ETH",
+		"",		/* No dtbo for this board */
+		1,		/* Start populating from eth1addr */
+	},
+};
+
+static bool daughter_card_detect_flags[ARRAY_SIZE(ext_cards)];
+
+const char *board_fit_get_additionnal_images(int index, const char *type)
+{
+	int i, j;
+
+	if (strcmp(type, FIT_FDT_PROP))
+		return NULL;
+
+	j = 0;
+	for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+		if (daughter_card_detect_flags[i]) {
+			if (j == index) {
+				/*
+				 * Return dtbo name only if populated,
+				 * otherwise stop parsing here.
+				 */
+				if (strlen(ext_cards[i].dtbo_name))
+					return ext_cards[i].dtbo_name;
+				else
+					return NULL;
+			};
+
+			j++;
+		}
+	}
+
+	return NULL;
+}
+
+static int probe_daughtercards(void)
+{
+	char mac_addr[DAUGHTER_CARD_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+	bool eeprom_read_success;
+	struct ti_am6_eeprom ep;
+	u8 previous_i2c_addr;
+	u8 mac_addr_cnt;
+	int i;
+	int ret;
+
+	/* Mark previous I2C address variable as not populated */
+	previous_i2c_addr = 0xff;
+
+	/* No EEPROM data was read yet */
+	eeprom_read_success = false;
+
+	/* Iterate through list of daughtercards */
+	for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+		/* Obtain card-specific I2C address */
+		u8 i2c_addr = ext_cards[i].i2c_addr;
+
+		/* Read card EEPROM if not already read previously */
+		if (i2c_addr != previous_i2c_addr) {
+			/* Store I2C address so we can avoid reading twice */
+			previous_i2c_addr = i2c_addr;
+
+			/* Get and parse the daughter card EEPROM record */
+			ret = ti_i2c_eeprom_am6_get(CONFIG_EEPROM_BUS_ADDRESS,
+						    i2c_addr,
+						    &ep,
+						    (char **)mac_addr,
+						    DAUGHTER_CARD_NO_OF_MAC_ADDR,
+						    &mac_addr_cnt);
+			if (ret) {
+				debug("%s: No daughtercard EEPROM at 0x%02x found %d\n",
+				      __func__, i2c_addr, ret);
+				eeprom_read_success = false;
+				/* Skip to the next daughtercard to probe */
+				continue;
+			}
+
+			/* EEPROM read successful, okay to further process. */
+			eeprom_read_success = true;
+		}
+
+		/* Only continue processing if EEPROM data was read */
+		if (!eeprom_read_success)
+			continue;
+
+		/* Only process the parsed data if we found a match */
+		if (strncmp(ep.name, ext_cards[i].card_name, sizeof(ep.name)))
+			continue;
+
+		printf("Detected: %s rev %s\n", ep.name, ep.version);
+		daughter_card_detect_flags[i] = true;
+
+#ifndef CONFIG_SPL_BUILD
+		int j;
+		/*
+		 * Populate any MAC addresses from daughtercard into the U-Boot
+		 * environment, starting with a card-specific offset so we can
+		 * have multiple ext_cards contribute to the MAC pool in a well-
+		 * defined manner.
+		 */
+		for (j = 0; j < mac_addr_cnt; j++) {
+			if (!is_valid_ethaddr((u8 *)mac_addr[j]))
+				continue;
+
+			eth_env_set_enetaddr_by_index("eth",
+						      ext_cards[i].eth_offset + j,
+						      (uchar *)mac_addr[j]);
+		}
+#endif
+	}
+#ifndef CONFIG_SPL_BUILD
+	char name_overlays[1024] = { 0 };
+
+	for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+		if (!daughter_card_detect_flags[i])
+			continue;
+
+		/* Skip if no overlays are to be added */
+		if (!strlen(ext_cards[i].dtbo_name))
+			continue;
+
+		/*
+		 * Make sure we are not running out of buffer space by checking
+		 * if we can fit the new overlay, a trailing space to be used
+		 * as a separator, plus the terminating zero.
+		 */
+		if (strlen(name_overlays) + strlen(ext_cards[i].dtbo_name) + 2 >
+		    sizeof(name_overlays))
+			return -ENOMEM;
+
+		/* Append to our list of overlays */
+		strcat(name_overlays, ext_cards[i].dtbo_name);
+		strcat(name_overlays, " ");
+	}
+
+	/* Apply device tree overlay(s) to the U-Boot environment, if any */
+	if (strlen(name_overlays))
+		return env_set("name_overlays", name_overlays);
+#endif
+
+	return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
+		setup_board_eeprom_env();
+		setup_serial();
+
+		/* Check for and probe any plugged-in daughtercards */
+		probe_daughtercards();
+	}
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+#if defined(CONFIG_ESM_K3) || defined(CONFIG_ESM_PMIC)
+	struct udevice *dev;
+	int ret;
+#endif
+
+	if ((IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM) ||
+	     IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM)) &&
+	    IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
+		probe_daughtercards();
+
+#ifdef CONFIG_ESM_K3
+	if (board_ti_k3_is("J721EX-PM2-SOM")) {
+		ret = uclass_get_device_by_driver(UCLASS_MISC,
+						  DM_DRIVER_GET(k3_esm), &dev);
+		if (ret)
+			printf("ESM init failed: %d\n", ret);
+	}
+#endif
+
+#ifdef CONFIG_ESM_PMIC
+	if (board_ti_k3_is("J721EX-PM2-SOM")) {
+		ret = uclass_get_device_by_driver(UCLASS_MISC,
+						  DM_DRIVER_GET(pmic_esm),
+						  &dev);
+		if (ret)
+			printf("ESM PMIC init failed: %d\n", ret);
+	}
+#endif
+}
diff --git a/roms/u-boot/board/ti/ks2_evm/Kconfig b/roms/u-boot/board/ti/ks2_evm/Kconfig
new file mode 100644
index 000000000..9477f5336
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/Kconfig
@@ -0,0 +1,53 @@
+if TARGET_K2E_EVM
+
+config SYS_BOARD
+	default "ks2_evm"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_CONFIG_NAME
+	default "k2e_evm"
+
+endif
+
+if TARGET_K2HK_EVM
+
+config SYS_BOARD
+	default "ks2_evm"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_CONFIG_NAME
+	default "k2hk_evm"
+
+endif
+
+if TARGET_K2L_EVM
+
+config SYS_BOARD
+	default "ks2_evm"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_CONFIG_NAME
+	default "k2l_evm"
+
+endif
+
+if TARGET_K2G_EVM
+
+config SYS_BOARD
+	default "ks2_evm"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_CONFIG_NAME
+	default "k2g_evm"
+
+endif
+
+source "board/ti/common/Kconfig"
diff --git a/roms/u-boot/board/ti/ks2_evm/MAINTAINERS b/roms/u-boot/board/ti/ks2_evm/MAINTAINERS
new file mode 100644
index 000000000..999ef0ae3
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/MAINTAINERS
@@ -0,0 +1,12 @@
+KS2_EVM BOARD
+M:	Vitaly Andrianov <vitalya@ti.com>
+S:	Maintained
+F:	board/ti/ks2_evm/
+F:	include/configs/k2hk_evm.h
+F:	configs/k2hk_evm_defconfig
+F:	include/configs/k2e_evm.h
+F:	configs/k2e_evm_defconfig
+F:	include/configs/k2l_evm.h
+F:	configs/k2l_evm_defconfig
+F:	include/configs/k2g_evm.h
+F:	configs/k2g_evm_defconfig
diff --git a/roms/u-boot/board/ti/ks2_evm/Makefile b/roms/u-boot/board/ti/ks2_evm/Makefile
new file mode 100644
index 000000000..879f8b598
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/Makefile
@@ -0,0 +1,17 @@
+#
+# KS2-EVM: board Makefile
+# (C) Copyright 2012-2015
+#     Texas Instruments Incorporated, <www.ti.com>
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += board.o
+obj-$(CONFIG_TARGET_K2HK_EVM) += board_k2hk.o
+obj-$(CONFIG_TARGET_K2HK_EVM) += ddr3_k2hk.o
+obj-$(CONFIG_TARGET_K2E_EVM) += board_k2e.o
+obj-$(CONFIG_TARGET_K2E_EVM) += ddr3_k2e.o
+obj-$(CONFIG_TARGET_K2L_EVM) += board_k2l.o
+obj-$(CONFIG_TARGET_K2L_EVM) += ddr3_k2l.o
+obj-$(CONFIG_TARGET_K2L_EVM) += ddr3_cfg.o
+obj-$(CONFIG_TARGET_K2G_EVM) += board_k2g.o
+obj-$(CONFIG_TARGET_K2G_EVM) += ddr3_k2g.o
diff --git a/roms/u-boot/board/ti/ks2_evm/README b/roms/u-boot/board/ti/ks2_evm/README
new file mode 100644
index 000000000..ff0ec5a36
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/README
@@ -0,0 +1,194 @@
+U-Boot port for Texas Instruments Keystone II EVM boards
+========================================================
+
+Author: Murali Karicheri <m-karicheri2@ti.com>
+
+This README has information on the U-Boot port for K2HK, K2E, and K2L EVM boards.
+Documentation for this board can be found at
+http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
+https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html
+https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html
+
+The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K.
+More details on these SoCs are available at company websites
+ K2K: http://www.ti.com/product/tci6638k2k
+ K2H: http://www.ti.com/product/tci6638k2h
+
+The K2E SoC details are available at
+ http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
+
+The K2L SoC details are available at
+ http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf
+
+The K2G SoC details are available at
+ http://www.ti.com/lit/ds/symlink/66ak2g02.pdf
+
+Board configuration:
+====================
+
+Some of the peripherals that are configured by U-Boot
++------+-------+-------+-----------+-----------+-------+-------+----+
+|      |DDR3   |NAND   |MSM SRAM   |ETH ports  |UART   |I2C    |SPI |
++------+-------+-------+-----------+-----------+-------+-------+----+
+|K2HK  |2      |512MB  |6MB	   |4(2)       |2      |3      |3   |
+|K2E   |4      |512MB  |2MB	   |8(2)       |2      |3      |3   |
+|K2L   |2      |512MB  |2MB	   |4(2)       |4      |3      |3   |
+|K2G   |2      |256MB  |1MB	   |1          |1      |1      |1   |
++------+-------+-------+-----------+-----------+-------+-------+----+
+
+There are only 2 eth port installed on the boards.
+
+There are separate PLLs to drive clocks to Tetris ARM and Peripherals.
+To bring up SMP Linux on this board, there is a boot monitor
+code that will be installed in MSMC SRAM. There is command available
+to install this image from U-Boot.
+
+The port related files can be found at following folders
+ keystone2 SoC related files: arch/arm/cpu/armv7/keystone/
+ EVMs board files: board/ti/k2s_evm/
+
+Board configuration files:
+include/configs/k2hk_evm.h
+include/configs/k2e_evm.h
+include/configs/k2l_evm.h
+include/configs/k2g_evm.h
+
+As U-Boot is migrating to Kconfig there is also board defconfig files
+configs/k2e_evm_defconfig
+configs/k2hk_evm_defconfig
+configs/k2l_evm_defconfig
+configs/k2g_evm_defconfig
+
+Supported boot modes:
+ - SPI NOR boot
+ - AEMIF NAND boot (K2E, K2L and K2HK)
+ - UART boot
+ - MMC boot (Only on K2G)
+
+Supported image formats:
+ - u-boot.bin: for loading and running u-boot.bin through
+		Texas Instruments code composure studio (CCS) and for UART boot.
+ - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
+ - MLO: gpimage for programming NAND flash for NAND boot, MMC boot.
+
+Build instructions:
+===================
+Examples for k2hk, for k2e, k2l and k2g just replace k2hk prefix accordingly.
+Don't forget to add CROSS_COMPILE.
+
+To build u-boot.bin, u-boot-spi.gph, MLO:
+  >make k2hk_evm_defconfig
+  >make
+
+Load and Run U-Boot on keystone EVMs using CCS
+=========================================
+
+Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin
+on EVM. See instructions at below link for installing CCS on a Windows PC.
+http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started#
+Installing_Code_Composer_Studio
+Use u-boot.bin from the build folder for loading and running U-Boot binary
+on EVM. Follow instructions at
+K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
+K2E  http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup
+K2L  http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup
+K2G  http://processors.wiki.ti.com/index.php/66AK2G02_GP_EVM_Hardware_Setup
+
+to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
+and Power ON the EVM.  Follow instructions to connect serial port of EVM to
+PC and start TeraTerm or Hyper Terminal.
+
+Start CCS on a Windows machine and Launch Target
+configuration as instructed at http://processors.wiki.ti.com/index.php/
+MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS.
+The instructions provided in the above link uses a script for
+loading the U-Boot binary on the target EVM. Instead do the following:-
+
+1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D
+   is connected: Unknown)" at the debug window (This is created once Target
+   configuration is launched) and select "Connect Target".
+2. Once target connect is successful, choose Tools->Load Memory option from the
+   top level menu. At the Load Memory window, choose the file u-boot.bin
+   through "Browse" button and click "next >" button. In the next window, enter
+   Start address as 0xc000000, choose Type-size "32 bits" and click "Finish"
+   button.
+3. Click View -> Registers from the top level menu to view registers window.
+4. From Registers, window expand "Core Registers" to view PC. Edit PC value
+   to be 0xc000000. From the "Run" top level menu, select "Free Run"
+5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as
+   below and type any key to stop autoboot as instructed :=
+
+U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59)
+
+I2C:   ready
+Detected SO-DIMM [SQR-SD3T-2G1333SED]
+DRAM:  1.1 GiB
+NAND:  512 MiB
+Net:   K2HK_EMAC
+Warning: K2HK_EMAC using MAC address from net device
+, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3
+Hit any key to stop autoboot:  0
+
+SPI NOR Flash programming instructions
+======================================
+U-Boot image can be flashed to first 512KB of the NOR flash using following
+instructions:
+
+1. Start CCS and run U-Boot as described above.
+2. Suspend Target. Select Run -> Suspend from top level menu
+   CortexA15_1 (Free Running)"
+3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
+   through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L
+   EVM using CCS", but using address 0x87000000.
+4. Free Run the target as described earlier (step 4) to get U-Boot prompt
+5. At the U-Boot console type following to setup U-Boot environment variables.
+   setenv addr_uboot 0x87000000
+   setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
+   run burn_uboot_spi
+   Once U-Boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
+   to "SPI Little Endian Boot mode" as per instruction at
+   http://processors.wiki.ti.com/index.php/*_Hardware_Setup.
+6. Power ON the EVM. The EVM now boots with U-Boot image on the NOR flash.
+
+AEMIF NAND Flash programming instructions
+======================================
+U-Boot image can be flashed to first 1024KB of the NAND flash using following
+instructions:
+
+1. Start CCS and run U-Boot as described above.
+2. Suspend Target. Select Run -> Suspend from top level menu
+   CortexA15_1 (Free Running)"
+3. Load MLO binary from build folder on to DDR address 0x87000000
+   through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
+   using CCS", but using address 0x87000000.
+4. Free Run the target as described earlier (step 4) to get U-Boot prompt
+5. At the U-Boot console type following to setup U-Boot environment variables.
+   setenv filesize <size in hex of MLO rounded to hex 0x10000>
+   run burn_uboot_nand
+   Once U-Boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
+   to "ARM NAND Boot mode" as per instruction at
+   http://processors.wiki.ti.com/index.php/*_Hardware_Setup.
+6. Power ON the EVM. The EVM now boots with U-Boot image on the NAND flash.
+
+Load and Run U-Boot on keystone EVMs using UART download
+========================================================
+
+Open BMC and regular UART terminals.
+
+1. On the regular UART port start xmodem transfer of the u-boot.bin
+2. Using BMC terminal set the ARM-UART bootmode and reboot the EVM
+   BMC> bootmode #4
+   MBC> reboot
+3. When xmodem is complete you should see the U-Boot starts on the UART port
+
+Load and Run U-Boot on K2G EVMs using MMC
+========================================================
+
+Open BMC and regular UART terminals.
+
+1. Set the SW3 dip switch to "ARM MMC Boot mode" as per instruction at
+   http://processors.wiki.ti.com/index.php/66AK2G02_GP_EVM_Hardware_Setup
+2. Create SD card partitions as per steps given in Hardware Setup Guide.
+3. Copy MLO to Boot Partition.
+4. Insert SD card and Power on the EVM.
+   The EVM now boots with U-Boot image from SD card.
diff --git a/roms/u-boot/board/ti/ks2_evm/board.c b/roms/u-boot/board/ti/ks2_evm/board.c
new file mode 100644
index 000000000..0c5c2c914
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/board.c
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Keystone : Board initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+#include "board.h"
+#include <env.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <spl.h>
+#include <exports.h>
+#include <fdt_support.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/ti-common/ti-aemif.h>
+#include <asm/ti-common/keystone_net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_TI_AEMIF)
+static struct aemif_config aemif_configs[] = {
+	{			/* CS0 */
+		.mode		= AEMIF_MODE_NAND,
+		.wr_setup	= 0xf,
+		.wr_strobe	= 0x3f,
+		.wr_hold	= 7,
+		.rd_setup	= 0xf,
+		.rd_strobe	= 0x3f,
+		.rd_hold	= 7,
+		.turn_around	= 3,
+		.width		= AEMIF_WIDTH_8,
+	},
+};
+#endif
+
+int dram_init(void)
+{
+	u32 ddr3_size;
+
+	ddr3_size = ddr3_init();
+
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_MAX_RAM_BANK_SIZE);
+#if defined(CONFIG_TI_AEMIF)
+	if (!(board_is_k2g_ice() || board_is_k2g_i1()))
+		aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+#endif
+
+	if (!(board_is_k2g_ice() || board_is_k2g_i1())) {
+		if (ddr3_size)
+			ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+		else
+			ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
+				      gd->ram_size >> 30);
+	}
+
+	return 0;
+}
+
+struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+	return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+	spl_init_keystone_plls();
+	preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+#if defined(CONFIG_SPL_SPI_LOAD)
+	return BOOT_DEVICE_SPI;
+#else
+	puts("Unknown boot device\n");
+	hang();
+#endif
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int lpae;
+	char *env;
+	char *endp;
+	int nbanks;
+	u64 size[2];
+	u64 start[2];
+	u32 ddr3a_size;
+
+	env = env_get("mem_lpae");
+	lpae = env && simple_strtol(env, NULL, 0);
+
+	ddr3a_size = 0;
+	if (lpae) {
+		ddr3a_size = ddr3_get_size();
+		if ((ddr3a_size != 8) && (ddr3a_size != 4))
+			ddr3a_size = 0;
+	}
+
+	nbanks = 1;
+	start[0] = bd->bi_dram[0].start;
+	size[0]  = bd->bi_dram[0].size;
+
+	/* adjust memory start address for LPAE */
+	if (lpae) {
+		start[0] -= CONFIG_SYS_SDRAM_BASE;
+		start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
+	}
+
+	if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
+		size[1] = ((u64)ddr3a_size - 2) << 30;
+		start[1] = 0x880000000;
+		nbanks++;
+	}
+
+	/* reserve memory at start of bank */
+	env = env_get("mem_reserve_head");
+	if (env) {
+		start[0] += ustrtoul(env, &endp, 0);
+		size[0] -= ustrtoul(env, &endp, 0);
+	}
+
+	env = env_get("mem_reserve");
+	if (env)
+		size[0] -= ustrtoul(env, &endp, 0);
+
+	fdt_fixup_memory_banks(blob, start, size, nbanks);
+
+	return 0;
+}
+
+void ft_board_setup_ex(void *blob, struct bd_info *bd)
+{
+	int lpae;
+	u64 size;
+	char *env;
+	u64 *reserve_start;
+	int unitrd_fixup = 0;
+
+	env = env_get("mem_lpae");
+	lpae = env && simple_strtol(env, NULL, 0);
+	env = env_get("uinitrd_fixup");
+	unitrd_fixup = env && simple_strtol(env, NULL, 0);
+
+	/* Fix up the initrd */
+	if (lpae && unitrd_fixup) {
+		int nodeoffset;
+		int err;
+		u64 *prop1, *prop2;
+		u64 initrd_start, initrd_end;
+
+		nodeoffset = fdt_path_offset(blob, "/chosen");
+		if (nodeoffset >= 0) {
+			prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
+					    "linux,initrd-start", NULL);
+			prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
+					    "linux,initrd-end", NULL);
+			if (prop1 && prop2) {
+				initrd_start = __be64_to_cpu(*prop1);
+				initrd_start -= CONFIG_SYS_SDRAM_BASE;
+				initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
+				initrd_start = __cpu_to_be64(initrd_start);
+				initrd_end = __be64_to_cpu(*prop2);
+				initrd_end -= CONFIG_SYS_SDRAM_BASE;
+				initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
+				initrd_end = __cpu_to_be64(initrd_end);
+
+				err = fdt_delprop(blob, nodeoffset,
+						  "linux,initrd-start");
+				if (err < 0)
+					puts("error deleting initrd-start\n");
+
+				err = fdt_delprop(blob, nodeoffset,
+						  "linux,initrd-end");
+				if (err < 0)
+					puts("error deleting initrd-end\n");
+
+				err = fdt_setprop(blob, nodeoffset,
+						  "linux,initrd-start",
+						  &initrd_start,
+						  sizeof(initrd_start));
+				if (err < 0)
+					puts("error adding initrd-start\n");
+
+				err = fdt_setprop(blob, nodeoffset,
+						  "linux,initrd-end",
+						  &initrd_end,
+						  sizeof(initrd_end));
+				if (err < 0)
+					puts("error adding linux,initrd-end\n");
+			}
+		}
+	}
+
+	if (lpae) {
+		/*
+		 * the initrd and other reserved memory areas are
+		 * embedded in in the DTB itslef. fix up these addresses
+		 * to 36 bit format
+		 */
+		reserve_start = (u64 *)((char *)blob +
+				       fdt_off_mem_rsvmap(blob));
+		while (1) {
+			*reserve_start = __cpu_to_be64(*reserve_start);
+			size = __cpu_to_be64(*(reserve_start + 1));
+			if (size) {
+				*reserve_start -= CONFIG_SYS_SDRAM_BASE;
+				*reserve_start +=
+					CONFIG_SYS_LPAE_SDRAM_BASE;
+				*reserve_start =
+					__cpu_to_be64(*reserve_start);
+			} else {
+				break;
+			}
+			reserve_start += 2;
+		}
+	}
+
+	ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+#if defined(CONFIG_DTB_RESELECT)
+int __weak embedded_dtb_select(void)
+{
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/ti/ks2_evm/board.h b/roms/u-boot/board/ti/ks2_evm/board.h
new file mode 100644
index 000000000..93fc3887f
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/board.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K2HK EVM : Board common header
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef _KS2_BOARD
+#define _KS2_BOARD
+
+#include <asm/ti-common/keystone_net.h>
+#include "../common/board_detect.h"
+
+#if defined(CONFIG_TI_I2C_BOARD_DETECT)
+static inline int board_is_k2g_gp(void)
+{
+	return board_ti_is("66AK2GGP");
+}
+static inline int board_is_k2g_g1(void)
+{
+	return board_ti_is("66AK2GG1");
+}
+static inline int board_is_k2g_ice(void)
+{
+	return board_ti_is("66AK2GIC");
+}
+static inline int board_is_k2g_i1(void)
+{
+	return board_ti_is("66AK2GI1");
+}
+#else
+static inline int board_is_k2g_gp(void)
+{
+	return false;
+}
+static inline int board_is_k2g_ice(void)
+{
+	return false;
+}
+static inline int board_is_k2g_i1(void)
+{
+	return false;
+}
+#endif
+
+void spl_init_keystone_plls(void);
+
+#endif
diff --git a/roms/u-boot/board/ti/ks2_evm/board_k2e.c b/roms/u-boot/board/ti/ks2_evm/board_k2e.c
new file mode 100644
index 000000000..39abb24e1
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/board_k2e.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K2E EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/keystone_net.h>
+
+unsigned int get_external_clk(u32 clk)
+{
+	unsigned int clk_freq;
+
+	switch (clk) {
+	case sys_clk:
+		clk_freq = 100000000;
+		break;
+	case alt_core_clk:
+		clk_freq = 100000000;
+		break;
+	case pa_clk:
+		clk_freq = 100000000;
+		break;
+	case ddr3a_clk:
+		clk_freq = 100000000;
+		break;
+	default:
+		clk_freq = 0;
+		break;
+	}
+
+	return clk_freq;
+}
+
+static struct pll_init_data core_pll_config[NUM_SPDS] = {
+	[SPD800]	= CORE_PLL_800,
+	[SPD850]	= CORE_PLL_850,
+	[SPD1000]	= CORE_PLL_1000,
+	[SPD1250]	= CORE_PLL_1250,
+	[SPD1350]	= CORE_PLL_1350,
+	[SPD1400]	= CORE_PLL_1400,
+	[SPD1500]	= CORE_PLL_1500,
+};
+
+/* DEV and ARM speed definitions as specified in DEVSPEED register */
+int speeds[DEVSPEED_NUMSPDS] = {
+	SPD850,
+	SPD1000,
+	SPD1250,
+	SPD1350,
+	SPD1400,
+	SPD1500,
+	SPD1400,
+	SPD1350,
+	SPD1250,
+	SPD1000,
+	SPD850,
+	SPD800,
+};
+
+s16 divn_val[16] = {
+	0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+static struct pll_init_data pa_pll_config =
+	PASS_PLL_1000;
+
+struct pll_init_data *get_pll_init_data(int pll)
+{
+	int speed;
+	struct pll_init_data *data;
+
+	switch (pll) {
+	case MAIN_PLL:
+		speed = get_max_dev_speed(speeds);
+		data = &core_pll_config[speed];
+		break;
+	case PASS_PLL:
+		data = &pa_pll_config;
+		break;
+	default:
+		data = NULL;
+	}
+
+	return data;
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	if (!strcmp(name, "keystone-k2e-evm"))
+		return 0;
+
+	return -1;
+}
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+	init_plls();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void spl_init_keystone_plls(void)
+{
+	init_plls();
+}
+#endif
diff --git a/roms/u-boot/board/ti/ks2_evm/board_k2g.c b/roms/u-boot/board/ti/ks2_evm/board_k2g.c
new file mode 100644
index 000000000..5229afad6
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/board_k2g.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K2G EVM : Board initialization
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+#include <common.h>
+#include <eeprom.h>
+#include <env.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/ti-common/keystone_net.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/mmc_host_def.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <remoteproc.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include "mux-k2g.h"
+#include "../common/board_detect.h"
+
+#define K2G_GP_AUDIO_CODEC_ADDRESS	0x1B
+
+const unsigned int sysclk_array[MAX_SYSCLK] = {
+	19200000,
+	24000000,
+	25000000,
+	26000000,
+};
+
+unsigned int get_external_clk(u32 clk)
+{
+	unsigned int clk_freq;
+	u8 sysclk_index = get_sysclk_index();
+
+	switch (clk) {
+	case sys_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	case pa_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	case tetris_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	case ddr3a_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	case uart_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	default:
+		clk_freq = 0;
+		break;
+	}
+
+	return clk_freq;
+}
+
+int speeds[DEVSPEED_NUMSPDS] = {
+	SPD400,
+	SPD600,
+	SPD800,
+	SPD900,
+	SPD1000,
+	SPD900,
+	SPD800,
+	SPD600,
+	SPD400,
+	SPD200,
+};
+
+static int dev_speeds[DEVSPEED_NUMSPDS] = {
+	SPD600,
+	SPD800,
+	SPD900,
+	SPD1000,
+	SPD900,
+	SPD800,
+	SPD600,
+	SPD400,
+};
+
+static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
+	[SYSCLK_19MHz] = {
+		[SPD400]	= {MAIN_PLL, 125, 3, 2},
+		[SPD600]	= {MAIN_PLL, 125, 2, 2},
+		[SPD800]	= {MAIN_PLL, 250, 3, 2},
+		[SPD900]	= {MAIN_PLL, 187, 2, 2},
+		[SPD1000]	= {MAIN_PLL, 104, 1, 2},
+	},
+	[SYSCLK_24MHz] = {
+		[SPD400]	= {MAIN_PLL, 100, 3, 2},
+		[SPD600]	= {MAIN_PLL, 300, 6, 2},
+		[SPD800]	= {MAIN_PLL, 200, 3, 2},
+		[SPD900]	= {MAIN_PLL, 75, 1, 2},
+		[SPD1000]	= {MAIN_PLL, 250, 3, 2},
+	},
+	[SYSCLK_25MHz] = {
+		[SPD400]	= {MAIN_PLL, 32, 1, 2},
+		[SPD600]	= {MAIN_PLL, 48, 1, 2},
+		[SPD800]	= {MAIN_PLL, 64, 1, 2},
+		[SPD900]	= {MAIN_PLL, 72, 1, 2},
+		[SPD1000]	= {MAIN_PLL, 80, 1, 2},
+	},
+	[SYSCLK_26MHz] = {
+		[SPD400]	= {MAIN_PLL, 400, 13, 2},
+		[SPD600]	= {MAIN_PLL, 230, 5, 2},
+		[SPD800]	= {MAIN_PLL, 123, 2, 2},
+		[SPD900]	= {MAIN_PLL, 69, 1, 2},
+		[SPD1000]	= {MAIN_PLL, 384, 5, 2},
+	},
+};
+
+static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
+	[SYSCLK_19MHz] = {
+		[SPD200]	= {TETRIS_PLL, 625, 6, 10},
+		[SPD400]	= {TETRIS_PLL, 125, 1, 6},
+		[SPD600]	= {TETRIS_PLL, 125, 1, 4},
+		[SPD800]	= {TETRIS_PLL, 333, 2, 4},
+		[SPD900]	= {TETRIS_PLL, 187, 2, 2},
+		[SPD1000]	= {TETRIS_PLL, 104, 1, 2},
+	},
+	[SYSCLK_24MHz] = {
+		[SPD200]	= {TETRIS_PLL, 250, 3, 10},
+		[SPD400]	= {TETRIS_PLL, 100, 1, 6},
+		[SPD600]	= {TETRIS_PLL, 100, 1, 4},
+		[SPD800]	= {TETRIS_PLL, 400, 3, 4},
+		[SPD900]	= {TETRIS_PLL, 75, 1, 2},
+		[SPD1000]	= {TETRIS_PLL, 250, 3, 2},
+	},
+	[SYSCLK_25MHz] = {
+		[SPD200]	= {TETRIS_PLL, 80, 1, 10},
+		[SPD400]	= {TETRIS_PLL, 96, 1, 6},
+		[SPD600]	= {TETRIS_PLL, 96, 1, 4},
+		[SPD800]	= {TETRIS_PLL, 128, 1, 4},
+		[SPD900]	= {TETRIS_PLL, 72, 1, 2},
+		[SPD1000]	= {TETRIS_PLL, 80, 1, 2},
+	},
+	[SYSCLK_26MHz] = {
+		[SPD200]	= {TETRIS_PLL, 307, 4, 10},
+		[SPD400]	= {TETRIS_PLL, 369, 4, 6},
+		[SPD600]	= {TETRIS_PLL, 369, 4, 4},
+		[SPD800]	= {TETRIS_PLL, 123, 1, 4},
+		[SPD900]	= {TETRIS_PLL, 69, 1, 2},
+		[SPD1000]	= {TETRIS_PLL, 384, 5, 2},
+	},
+};
+
+static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
+	[SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
+	[SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
+	[SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
+	[SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
+};
+
+static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
+	[SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
+	[SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
+	[SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
+	[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
+};
+
+static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
+	[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
+	[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
+	[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
+	[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
+};
+
+static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
+	[SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
+	[SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
+	[SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
+	[SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
+};
+
+struct pll_init_data *get_pll_init_data(int pll)
+{
+	int speed;
+	struct pll_init_data *data = NULL;
+	u8 sysclk_index = get_sysclk_index();
+
+	switch (pll) {
+	case MAIN_PLL:
+		speed = get_max_dev_speed(dev_speeds);
+		data = &main_pll_config[sysclk_index][speed];
+		break;
+	case TETRIS_PLL:
+		speed = get_max_arm_speed(speeds);
+		data = &tetris_pll_config[sysclk_index][speed];
+		break;
+	case NSS_PLL:
+		data = &nss_pll_config[sysclk_index];
+		break;
+	case UART_PLL:
+		data = &uart_pll_config[sysclk_index];
+		break;
+	case DDR3_PLL:
+		if (cpu_revision() & CPU_66AK2G1x) {
+			speed = get_max_arm_speed(speeds);
+			if (speed == SPD1000)
+				data = &ddr3_pll_config_1066[sysclk_index];
+			else
+				data = &ddr3_pll_config_800[sysclk_index];
+		} else {
+			data = &ddr3_pll_config_800[sysclk_index];
+		}
+		break;
+	default:
+		data = NULL;
+	}
+
+	return data;
+}
+
+s16 divn_val[16] = {
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(struct bd_info *bis)
+{
+	if (psc_enable_module(KS2_LPSC_MMC)) {
+		printf("%s module enabled failed\n", __func__);
+		return -1;
+	}
+
+	if (board_is_k2g_gp() || board_is_k2g_g1())
+		omap_mmc_init(0, 0, 0, -1, -1);
+
+	omap_mmc_init(1, 0, 0, -1, -1);
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	bool eeprom_read = board_ti_was_eeprom_read();
+
+	if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
+		return 0;
+	else if (!strcmp(name, "keystone-k2g-evm") &&
+		(board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
+		return 0;
+	else if (!strcmp(name, "keystone-k2g-ice") &&
+		 (board_ti_is("66AK2GIC") || board_is_k2g_i1()))
+		return 0;
+	else
+		return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+static int k2g_alt_board_detect(void)
+{
+#if !CONFIG_IS_ENABLED(DM_I2C)
+	int rc;
+
+	rc = i2c_set_bus_num(1);
+	if (rc)
+		return rc;
+
+	rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
+	if (rc)
+		return rc;
+#else
+	struct udevice *bus, *dev;
+	int rc;
+
+	rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
+	if (rc)
+		return rc;
+	rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
+	if (rc)
+		return rc;
+#endif
+	ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
+
+	return 0;
+}
+
+static void k2g_reset_mux_config(void)
+{
+	/* Unlock the reset mux register */
+	clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+
+	/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
+	clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
+			RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
+
+	/* lock the reset mux register to prevent any spurious writes. */
+	setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+}
+
+int embedded_dtb_select(void)
+{
+	int rc;
+	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+			CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc) {
+		rc = k2g_alt_board_detect();
+		if (rc) {
+			printf("Unable to do board detection\n");
+			return -1;
+		}
+	}
+
+	fdtdec_setup();
+
+	k2g_mux_config();
+
+	k2g_reset_mux_config();
+
+	if (board_is_k2g_gp() || board_is_k2g_g1()) {
+		/* deassert FLASH_HOLD */
+		clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
+			     BIT(9));
+		setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
+			     BIT(9));
+	} else if (board_is_k2g_ice() || board_is_k2g_i1()) {
+		/* GBE Phy workaround. For Phy to latch the input
+		 * configuration, a GPIO reset is asserted at the
+		 * Phy reset pin to latch configuration correctly after SoC
+		 * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
+		 * board. Just do a low to high transition.
+		 */
+		clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
+			     BIT(10));
+		setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
+			     BIT(10));
+		/* Delay just to get a transition to high */
+		udelay(100);
+		setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
+			     BIT(10));
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+	int rc;
+
+	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+			CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+	board_ti_set_ethaddr(1);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (board_is_k2g_gp())
+		env_set("board_name", "66AK2GGP\0");
+	else if (board_is_k2g_g1())
+		env_set("board_name", "66AK2GG1\0");
+	else if (board_is_k2g_ice())
+		env_set("board_name", "66AK2GIC\0");
+	else if (board_is_k2g_i1())
+		env_set("board_name", "66AK2GI1\0");
+#endif
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	init_plls();
+
+	k2g_mux_config();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void spl_init_keystone_plls(void)
+{
+	init_plls();
+}
+#endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
+{
+	int id = env_get_ulong("dev_pmmc", 10, 0);
+	int ret;
+
+	if (!rproc_is_initialized())
+		rproc_init();
+
+	ret = rproc_load(id, pmmc_image, pmmc_size);
+	printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
+	       id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
+
+	if (!ret)
+		rproc_start(id);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
+#endif
diff --git a/roms/u-boot/board/ti/ks2_evm/board_k2hk.c b/roms/u-boot/board/ti/ks2_evm/board_k2hk.c
new file mode 100644
index 000000000..12c4649c3
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/board_k2hk.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K2HK EVM : Board initialization
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/keystone_net.h>
+
+unsigned int external_clk[ext_clk_count] = {
+	[sys_clk]	=	122880000,
+	[alt_core_clk]	=	125000000,
+	[pa_clk]	=	122880000,
+	[tetris_clk]	=	125000000,
+	[ddr3a_clk]	=	100000000,
+	[ddr3b_clk]	=	100000000,
+};
+
+unsigned int get_external_clk(u32 clk)
+{
+	unsigned int clk_freq;
+
+	switch (clk) {
+	case sys_clk:
+		clk_freq = 122880000;
+		break;
+	case alt_core_clk:
+		clk_freq = 125000000;
+		break;
+	case pa_clk:
+		clk_freq = 122880000;
+		break;
+	case tetris_clk:
+		clk_freq = 125000000;
+		break;
+	case ddr3a_clk:
+		clk_freq = 100000000;
+		break;
+	case ddr3b_clk:
+		clk_freq = 100000000;
+		break;
+	default:
+		clk_freq = 0;
+		break;
+	}
+
+	return clk_freq;
+}
+
+static struct pll_init_data core_pll_config[NUM_SPDS] = {
+	[SPD800]	= CORE_PLL_799,
+	[SPD1000]	= CORE_PLL_999,
+	[SPD1200]	= CORE_PLL_1200,
+};
+
+s16 divn_val[16] = {
+	0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+static struct pll_init_data tetris_pll_config[] = {
+	[SPD800]	= TETRIS_PLL_800,
+	[SPD1000]	= TETRIS_PLL_1000,
+	[SPD1200]	= TETRIS_PLL_1200,
+	[SPD1350]	= TETRIS_PLL_1350,
+	[SPD1400]	= TETRIS_PLL_1400,
+};
+
+static struct pll_init_data pa_pll_config =
+	PASS_PLL_983;
+
+struct pll_init_data *get_pll_init_data(int pll)
+{
+	int speed;
+	struct pll_init_data *data;
+
+	switch (pll) {
+	case MAIN_PLL:
+		speed = get_max_dev_speed(speeds);
+		data = &core_pll_config[speed];
+		break;
+	case TETRIS_PLL:
+		speed = get_max_arm_speed(speeds);
+		data = &tetris_pll_config[speed];
+		break;
+	case PASS_PLL:
+		data = &pa_pll_config;
+		break;
+	default:
+		data = NULL;
+	}
+
+	return data;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	init_plls();
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	if (!strcmp(name, "keystone-k2hk-evm"))
+		return 0;
+
+	return -1;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void spl_init_keystone_plls(void)
+{
+	init_plls();
+}
+#endif
diff --git a/roms/u-boot/board/ti/ks2_evm/board_k2l.c b/roms/u-boot/board/ti/ks2_evm/board_k2l.c
new file mode 100644
index 000000000..f759ee364
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/board_k2l.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K2L EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/keystone_net.h>
+
+unsigned int get_external_clk(u32 clk)
+{
+	unsigned int clk_freq;
+
+	switch (clk) {
+	case sys_clk:
+		clk_freq = 122880000;
+		break;
+	case alt_core_clk:
+		clk_freq = 100000000;
+		break;
+	case pa_clk:
+		clk_freq = 122880000;
+		break;
+	case tetris_clk:
+		clk_freq = 122880000;
+		break;
+	case ddr3a_clk:
+		clk_freq = 100000000;
+		break;
+	default:
+		clk_freq = 0;
+		break;
+	}
+
+	return clk_freq;
+}
+
+static struct pll_init_data core_pll_config[NUM_SPDS] = {
+	[SPD800]	= CORE_PLL_799,
+	[SPD1000]	= CORE_PLL_1000,
+	[SPD1200]	= CORE_PLL_1198,
+};
+
+s16 divn_val[16] = {
+	0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+static struct pll_init_data tetris_pll_config[] = {
+	[SPD800]	= TETRIS_PLL_799,
+	[SPD1000]	= TETRIS_PLL_1000,
+	[SPD1200]	= TETRIS_PLL_1198,
+	[SPD1350]	= TETRIS_PLL_1352,
+	[SPD1400]	= TETRIS_PLL_1401,
+};
+
+static struct pll_init_data pa_pll_config =
+	PASS_PLL_983;
+
+struct pll_init_data *get_pll_init_data(int pll)
+{
+	int speed;
+	struct pll_init_data *data;
+
+	switch (pll) {
+	case MAIN_PLL:
+		speed = get_max_dev_speed(speeds);
+		data = &core_pll_config[speed];
+		break;
+	case TETRIS_PLL:
+		speed = get_max_arm_speed(speeds);
+		data = &tetris_pll_config[speed];
+		break;
+	case PASS_PLL:
+		data = &pa_pll_config;
+		break;
+	default:
+		data = NULL;
+	}
+
+	return data;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	init_plls();
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	if (!strcmp(name, "keystone-k2l-evm"))
+		return 0;
+
+	return -1;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void spl_init_keystone_plls(void)
+{
+	init_plls();
+}
+#endif
diff --git a/roms/u-boot/board/ti/ks2_evm/ddr3_cfg.c b/roms/u-boot/board/ti/ks2_evm/ddr3_cfg.c
new file mode 100644
index 000000000..0ade75263
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/ddr3_cfg.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+
+#include <asm/arch/ddr3.h>
+#include "ddr3_cfg.h"
+
+struct ddr3_phy_config ddr3phy_1600_2g = {
+	.pllcr          = 0x0001C000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0, /* not set in gel */
+	.ptr3           = 0x0D861A80ul,
+	.ptr4           = 0x0C827100ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0x9D5CBB66ul,
+	.dtpr1          = 0x12868300ul,
+	.dtpr2          = 0x5002D200ul,
+	.mr0            = 0x00001C70ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000018ul,
+	.dtcr           = 0x710035C7ul,
+	.pgcr2          = 0x00F07A12ul,
+	.zq0cr1         = 0x0001005Dul,
+	.zq1cr1         = 0x0001005Bul,
+	.zq2cr1         = 0x0001005Bul,
+	.pir_v1         = 0x00000033ul,
+	.pir_v2         = 0x0000FF81ul,
+};
+
+struct ddr3_emif_config ddr3_1600_2g = {
+	.sdcfg          = 0x6200CE62ul,
+	.sdtim1         = 0x166C9855ul,
+	.sdtim2         = 0x00001D4Aul,
+	.sdtim3         = 0x435DFF53ul,
+	.sdtim4         = 0x543F0CFFul,
+	.zqcfg          = 0x70073200ul,
+	.sdrfc          = 0x00001869ul,
+};
diff --git a/roms/u-boot/board/ti/ks2_evm/ddr3_cfg.h b/roms/u-boot/board/ti/ks2_evm/ddr3_cfg.h
new file mode 100644
index 000000000..4f7462dec
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/ddr3_cfg.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef __DDR3_CFG_H
+#define __DDR3_CFG_H
+
+#include <asm/arch/ddr3.h>
+
+extern struct ddr3_phy_config ddr3phy_1600_2g;
+extern struct ddr3_emif_config ddr3_1600_2g;
+
+int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb);
+
+#endif /* __DDR3_CFG_H */
diff --git a/roms/u-boot/board/ti/ks2_evm/ddr3_k2e.c b/roms/u-boot/board/ti/ks2_evm/ddr3_k2e.c
new file mode 100644
index 000000000..95fe3a902
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/ddr3_k2e.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2014-2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+static struct pll_init_data ddr3_333 = DDR3_PLL_333;
+
+u32 ddr3_init(void)
+{
+	struct ddr3_spd_cb spd_cb;
+
+	if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
+		printf("Sorry, I don't know how to configure DDR3A.\n"
+		       "Bye :(\n");
+		for (;;)
+			;
+	}
+
+	printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
+
+	printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
+	if (spd_cb.ddrspdclock == 1600)
+		init_pll(&ddr3_400);
+	else
+		init_pll(&ddr3_333);
+
+	/* Reset DDR3 PHY after PLL enabled */
+	ddr3_reset_ddrphy();
+
+	spd_cb.phy_cfg.zq0cr1 |= 0x10000;
+	spd_cb.phy_cfg.zq1cr1 |= 0x10000;
+	spd_cb.phy_cfg.zq2cr1 |= 0x10000;
+	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
+	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
+
+	printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte);
+
+	return (u32)spd_cb.ddr_size_gbyte;
+}
diff --git a/roms/u-boot/board/ti/ks2_evm/ddr3_k2g.c b/roms/u-boot/board/ti/ks2_evm/ddr3_k2g.c
new file mode 100644
index 000000000..3000d7245
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/ddr3_k2g.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K2G: DDR3 initialization
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+#include "board.h"
+
+/* K2G GP EVM DDR3 Configuration */
+static struct ddr3_phy_config ddr3phy_800_2g = {
+	.pllcr          = 0x000DC000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0,
+	.ptr3           = 0x06C30D40ul,
+	.ptr4           = 0x06413880ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0x550F6644ul,
+	.dtpr1          = 0x328341E0ul,
+	.dtpr2          = 0x50022A00ul,
+	.mr0            = 0x00001430ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000000ul,
+	.dtcr           = 0x710035C7ul,
+	.pgcr2          = 0x00F03D09ul,
+	.zq0cr1         = 0x0001005Dul,
+	.zq1cr1         = 0x0001005Bul,
+	.zq2cr1         = 0x0001005Bul,
+	.pir_v1         = 0x00000033ul,
+	.datx8_2_mask   = 0,
+	.datx8_2_val    = 0,
+	.datx8_3_mask   = 0,
+	.datx8_3_val    = 0,
+	.datx8_4_mask   = 0,
+	.datx8_4_val    = ((1 << 0)),
+	.datx8_5_mask   = DXEN_MASK,
+	.datx8_5_val    = 0,
+	.datx8_6_mask   = DXEN_MASK,
+	.datx8_6_val    = 0,
+	.datx8_7_mask   = DXEN_MASK,
+	.datx8_7_val    = 0,
+	.datx8_8_mask   = DXEN_MASK,
+	.datx8_8_val    = 0,
+	.pir_v2         = 0x00000F81ul,
+};
+
+static struct ddr3_phy_config ddr3phy_1066_2g = {
+	.pllcr          = 0x000DC000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (2 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0,
+	.ptr3           = 0x0904111Dul,
+	.ptr4           = 0x0859A072ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0x6D147744ul,
+	.dtpr1          = 0x32845A80ul,
+	.dtpr2          = 0x50023600ul,
+	.mr0            = 0x00001830ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000000ul,
+	.dtcr           = 0x710035C7ul,
+	.pgcr2          = 0x00F05159ul,
+	.zq0cr1         = 0x0001005Dul,
+	.zq1cr1         = 0x0001005Bul,
+	.zq2cr1         = 0x0001005Bul,
+	.pir_v1         = 0x00000033ul,
+	.datx8_2_mask   = 0,
+	.datx8_2_val    = 0,
+	.datx8_3_mask   = 0,
+	.datx8_3_val    = 0,
+	.datx8_4_mask   = 0,
+	.datx8_4_val    = ((1 << 0)),
+	.datx8_5_mask   = DXEN_MASK,
+	.datx8_5_val    = 0,
+	.datx8_6_mask   = DXEN_MASK,
+	.datx8_6_val    = 0,
+	.datx8_7_mask   = DXEN_MASK,
+	.datx8_7_val    = 0,
+	.datx8_8_mask   = DXEN_MASK,
+	.datx8_8_val    = 0,
+	.pir_v2         = 0x00000F81ul,
+};
+
+static struct ddr3_emif_config ddr3_800_2g = {
+	.sdcfg          = 0x62005662ul,
+	.sdtim1         = 0x0A385033ul,
+	.sdtim2         = 0x00001CA5ul,
+	.sdtim3         = 0x21ADFF32ul,
+	.sdtim4         = 0x533F067Ful,
+	.zqcfg          = 0x70073200ul,
+	.sdrfc          = 0x00000C34ul,
+};
+
+static struct ddr3_emif_config ddr3_1066_2g = {
+	.sdcfg          = 0x62005662ul,
+	.sdtim1         = 0x0E4C6843ul,
+	.sdtim2         = 0x00001CC6ul,
+	.sdtim3         = 0x323DFF32ul,
+	.sdtim4         = 0x533F08AFul,
+	.zqcfg          = 0x70073200ul,
+	.sdrfc          = 0x00001044ul,
+};
+
+/* K2G ICE evm DDR3 Configuration */
+static struct ddr3_phy_config ddr3phy_800_512mb = {
+	.pllcr          = 0x000DC000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (2 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0,
+	.ptr3           = 0x06C30D40ul,
+	.ptr4           = 0x06413880ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0x550E6644ul,
+	.dtpr1          = 0x32834200ul,
+	.dtpr2          = 0x50022A00ul,
+	.mr0            = 0x00001430ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000008ul,
+	.dtcr           = 0x710035C7ul,
+	.pgcr2          = 0x00F03D09ul,
+	.zq0cr1         = 0x0001005Dul,
+	.zq1cr1         = 0x0001005Bul,
+	.zq2cr1         = 0x0001005Bul,
+	.pir_v1         = 0x00000033ul,
+	.datx8_2_mask   = DXEN_MASK,
+	.datx8_2_val    = 0,
+	.datx8_3_mask   = DXEN_MASK,
+	.datx8_3_val    = 0,
+	.datx8_4_mask   = DXEN_MASK,
+	.datx8_4_val    = 0,
+	.datx8_5_mask   = DXEN_MASK,
+	.datx8_5_val    = 0,
+	.datx8_6_mask   = DXEN_MASK,
+	.datx8_6_val    = 0,
+	.datx8_7_mask   = DXEN_MASK,
+	.datx8_7_val    = 0,
+	.datx8_8_mask   = DXEN_MASK,
+	.datx8_8_val    = 0,
+	.pir_v2         = 0x00000F81ul,
+};
+
+static struct ddr3_emif_config ddr3_800_512mb = {
+	.sdcfg          = 0x62006662ul,
+	.sdtim1         = 0x0A385033ul,
+	.sdtim2         = 0x00001CA5ul,
+	.sdtim3         = 0x21ADFF32ul,
+	.sdtim4         = 0x533F067Ful,
+	.zqcfg          = 0x70073200ul,
+	.sdrfc          = 0x00000C34ul,
+};
+
+u32 ddr3_init(void)
+{
+	/* Reset DDR3 PHY after PLL enabled */
+	ddr3_reset_ddrphy();
+	if (board_is_k2g_g1()) {
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1066_2g);
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1066_2g);
+	} else if (board_is_k2g_gp()) {
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
+	} else if (board_is_k2g_ice() || board_is_k2g_i1()) {
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb);
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb);
+	}
+
+	return 0;
+}
+
+inline int ddr3_get_size(void)
+{
+	return 2;
+}
diff --git a/roms/u-boot/board/ti/ks2_evm/ddr3_k2hk.c b/roms/u-boot/board/ti/ks2_evm/ddr3_k2hk.c
new file mode 100644
index 000000000..198c5da0e
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/ddr3_k2hk.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
+struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
+
+u32 ddr3_init(void)
+{
+	u32 ddr3_size;
+	struct ddr3_spd_cb spd_cb;
+
+	if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
+		printf("Sorry, I don't know how to configure DDR3A.\n"
+		       "Bye :(\n");
+		for (;;)
+			;
+	}
+
+	printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
+
+	if ((cpu_revision() > 1) ||
+	    (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) {
+		printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
+		if (spd_cb.ddrspdclock == 1600)
+			init_pll(&ddr3a_400);
+		else
+			init_pll(&ddr3a_333);
+	}
+
+	if (cpu_revision() > 0) {
+		if (cpu_revision() > 1) {
+			/* PG 2.0 */
+			/* Reset DDR3A PHY after PLL enabled */
+			ddr3_reset_ddrphy();
+			spd_cb.phy_cfg.zq0cr1 |= 0x10000;
+			spd_cb.phy_cfg.zq1cr1 |= 0x10000;
+			spd_cb.phy_cfg.zq2cr1 |= 0x10000;
+		}
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
+
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
+
+		ddr3_size = spd_cb.ddr_size_gbyte;
+	} else {
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
+		spd_cb.emif_cfg.sdcfg |= 0x1000;
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
+		ddr3_size = spd_cb.ddr_size_gbyte / 2;
+	}
+	printf("DRAM: %d GiB (includes reported below)\n", ddr3_size);
+
+	/* Apply the workaround for PG 1.0 and 1.1 Silicons */
+	if (cpu_revision() <= 1)
+		ddr3_err_reset_workaround();
+
+	return ddr3_size;
+}
diff --git a/roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c b/roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c
new file mode 100644
index 000000000..805bf81f6
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+
+u32 ddr3_init(void)
+{
+	init_pll(&ddr3_400);
+
+	/* No SO-DIMM, 2GB discreet DDR */
+	printf("DRAM: 2 GiB\n");
+
+	/* Reset DDR3 PHY after PLL enabled */
+	ddr3_reset_ddrphy();
+
+	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
+	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
+
+	return 2;
+}
diff --git a/roms/u-boot/board/ti/ks2_evm/mux-k2g.h b/roms/u-boot/board/ti/ks2_evm/mux-k2g.h
new file mode 100644
index 000000000..fa6c92cbd
--- /dev/null
+++ b/roms/u-boot/board/ti/ks2_evm/mux-k2g.h
@@ -0,0 +1,386 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K2G EVM: Pinmux configuration
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <asm/io.h>
+#include <asm/arch/mux-k2g.h>
+#include <asm/arch/hardware.h>
+#include "board.h"
+
+struct pin_cfg k2g_generic_pin_cfg[] = {
+	/* UART0 */
+	{ 115,  MODE(0) },	/* SOC_UART0_RXD */
+	{ 116,  MODE(0) },	/* SOC_UART0_TXD */
+
+	/* I2C 0 */
+	{ 223,  MODE(0) },	/* SOC_I2C0_SCL */
+	{ 224,  MODE(0) },	/* SOC_I2C0_SDA */
+
+	/* I2C 1 */
+	{ 225,  MODE(0) },	/* SOC_I2C1_SCL */
+	{ 226,  MODE(0) },	/* SOC_I2C1_SDA */
+	{ MAX_PIN_N, }
+};
+
+struct pin_cfg k2g_evm_pin_cfg[] = {
+	/* GPMC */
+	{ 0,	MODE(0) },	/* GPMCAD0 */
+	{ 1,	MODE(0) },	/* GPMCAD1 */
+	{ 2,	MODE(0) },	/* GPMCAD2 */
+	{ 3,	MODE(0) },	/* GPMCAD3 */
+	{ 4,	MODE(0) },	/* GPMCAD4 */
+	{ 5,	MODE(0) },	/* GPMCAD5 */
+	{ 6,	MODE(0) },	/* GPMCAD6 */
+	{ 7,	MODE(0) },	/* GPMCAD7 */
+	{ 8,	MODE(0) },	/* GPMCAD8 */
+	{ 9,	MODE(0) },	/* GPMCAD9 */
+	{ 10,	MODE(0) },	/* GPMCAD10 */
+	{ 11,	MODE(0) },	/* GPMCAD11 */
+	{ 12,	MODE(0) },	/* GPMCAD12 */
+	{ 13,	MODE(0) },	/* GPMCAD13 */
+	{ 14,	MODE(0) },	/* GPMCAD14 */
+	{ 15,	MODE(0) },	/* GPMCAD15 */
+	{ 17,	MODE(0) },	/* GPMCADVNALE */
+	{ 18,	MODE(0) },	/* GPMCOENREN */
+	{ 19,	MODE(0) },	/* GPMCWEN */
+	{ 20,	MODE(0) },	/* GPMCBE0NCLE */
+	{ 22,	MODE(0) },	/* GPMCWAIT0 */
+	{ 24,	MODE(0) },	/* GPMCWPN */
+	{ 26,	MODE(0) },	/* GPMCCSN0 */
+
+	/* GPIOs */
+	{ 16,	MODE(3) | PIN_IEN },	/* GPIO0_16 - PRSNT1# */
+	{ 21,	MODE(3) | PIN_IEN },	/* GPIO0_21 - DC_BRD_DET */
+	{ 82,	MODE(3) | PIN_IEN },	/* GPIO0_82 - TPS_INT1 */
+	{ 83,	MODE(3) },		/* GPIO0_83 - TPS_SLEEP */
+	{ 84,	MODE(3) },		/* GPIO0_84 - SEL_HDMIn_GPIO */
+	{ 87,	MODE(3) },		/* GPIO0_87 - SD_LP2996A */
+	{ 106,	MODE(3) | PIN_IEN},	/* GPIO0_100 - SOC_INT */
+	{ 201,	MODE(3) | PIN_IEN},	/* GPIO1_26 - GPIO_EXP_INT */
+	{ 202,	MODE(3) },		/* GPIO1_27 - SEL_LCDn_GPIO */
+	{ 203,	MODE(3) | PIN_IEN},	/* GPIO1_28 - SOC_MLB_GPIO2 */
+	{ 204,	MODE(3) | PIN_IEN},	/* GPIO1_29 - SOC_PCIE_WAKEn */
+	{ 205,	MODE(3) | PIN_IEN},	/* GPIO1_30 - BMC_INT1 */
+	{ 206,	MODE(3) | PIN_IEN},	/* GPIO1_31 - HDMI_INTn*/
+	{ 207,	MODE(3) | PIN_IEN},	/* GPIO1_32 - CS2000_AUX_OUT */
+	{ 208,	MODE(3) | PIN_IEN},	/* GPIO1_33 - TEMP_INT */
+	{ 209,	MODE(3) | PIN_IEN},	/* GPIO1_34 - WLAN_IRQ */
+	{ 216,	MODE(3) },		/* GPIO1_41 - FLASH_HOLD */
+	{ 217,	MODE(3) | PIN_IEN},	/* GPIO1_42 - TOUCH_INTn */
+
+	/* MLB */
+	{ 23,	MODE(2) },	/* SOC_MLBCLK */
+	{ 25,	MODE(2) },	/* SOC_MLBSIG */
+	{ 27,	MODE(2) },	/* SOC_MLBDAT */
+
+	/* DSS */
+	{ 30,	MODE(0) },	/* SOC_DSSDATA23 */
+	{ 31,	MODE(0) },	/* SOC_DSSDATA22 */
+	{ 32,	MODE(0) },	/* SOC_DSSDATA21 */
+	{ 33,	MODE(0) },	/* SOC_DSSDATA20 */
+	{ 34,	MODE(0) },	/* SOC_DSSDATA19 */
+	{ 35,	MODE(0) },	/* SOC_DSSDATA18 */
+	{ 36,	MODE(0) },	/* SOC_DSSDATA17 */
+	{ 37,	MODE(0) },	/* SOC_DSSDATA16 */
+	{ 38,	MODE(0) },	/* SOC_DSSDATA15 */
+	{ 39,	MODE(0) },	/* SOC_DSSDATA14 */
+	{ 40,	MODE(0) },	/* SOC_DSSDATA13 */
+	{ 41,	MODE(0) },	/* SOC_DSSDATA12 */
+	{ 42,	MODE(0) },	/* SOC_DSSDATA11 */
+	{ 43,	MODE(0) },	/* SOC_DSSDATA10 */
+	{ 44,	MODE(0) },	/* SOC_DSSDATA9 */
+	{ 45,	MODE(0) },	/* SOC_DSSDATA8 */
+	{ 46,	MODE(0) },	/* SOC_DSSDATA7 */
+	{ 47,	MODE(0) },	/* SOC_DSSDATA6 */
+	{ 48,	MODE(0) },	/* SOC_DSSDATA5 */
+	{ 49,	MODE(0) },	/* SOC_DSSDATA4 */
+	{ 50,	MODE(0) },	/* SOC_DSSDATA3 */
+	{ 51,	MODE(0) },	/* SOC_DSSDATA2 */
+	{ 52,	MODE(0) },	/* SOC_DSSDATA1 */
+	{ 53,	MODE(0) },	/* SOC_DSSDATA0 */
+	{ 54,	MODE(0) },	/* SOC_DSSVSYNC */
+	{ 55,	MODE(0) },	/* SOC_DSSHSYNC */
+	{ 56,	MODE(0) },	/* SOC_DSSPCLK */
+	{ 57,	MODE(0) },	/* SOC_DSS_DE */
+	{ 58,	MODE(0) },	/* SOC_DSS_FID */
+	{ 221,	MODE(4) },	/* PWM0 - SOC_BACKLIGHT_PWM */
+
+	/* MMC1 */
+	{ 59,	MODE(0) },	/* SOC_MMC1_DAT7 */
+	{ 60,	MODE(0) },	/* SOC_MMC1_DAT6 */
+	{ 61,	MODE(0) },	/* SOC_MMC1_DAT5 */
+	{ 62,	MODE(0) },	/* SOC_MMC1_DAT4 */
+	{ 63,	MODE(0) },	/* SOC_MMC1_DAT3 */
+	{ 64,	MODE(0) },	/* SOC_MMC1_DAT2 */
+	{ 65,	MODE(0) },	/* SOC_MMC1_DAT1 */
+	{ 66,	MODE(0) },	/* SOC_MMC1_DAT0 */
+	{ 67,	MODE(0) },	/* SOC_MMC1_CLK */
+	{ 68,	MODE(0) },	/* SOC_MMC1_CMD */
+	{ 69,	MODE(0) },	/* MMC1SDCD TP125 */
+	{ 70,	MODE(0) },	/* SOC_MMC1_SDWP */
+	{ 71,	MODE(0) },	/* MMC1POW TP124 */
+
+		/* EMAC */
+	{ 72,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_RXC */
+	{ 77,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_RXD3 */
+	{ 78,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_RXD2 */
+	{ 79,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_RXD1 */
+	{ 80,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_RXD0 */
+	{ 81,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_RXCTL */
+	{ 85,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_TXC */
+	{ 91,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_TXD3 */
+	{ 92,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_TXD2 */
+	{ 93,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_TXD1 */
+	{ 94,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_TXD0 */
+	{ 95,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_TXCTL */
+
+	/* MDIO */
+	{ 98,	BUFFER_CLASS_B | PIN_PDIS | MODE(0) },	/* MDIO_DATA */
+	{ 99,	BUFFER_CLASS_B | PIN_PDIS | MODE(0) },	/* MDIO_CLK */
+
+	/* PWM */
+	{ 73,	MODE(4) },	/* SOC_EHRPWM3A */
+	{ 74,	MODE(4) },	/* SOC_EHRPWM3B */
+	{ 75,	MODE(4) },	/* SOC_EHRPWM3_SYNCI */
+	{ 76,	MODE(4) },	/* SOC_EHRPWM3_SYNCO */
+	{ 96,	MODE(4) },	/* SOC_EHRPWM_TRIPZONE_INPUT3 */
+	{ 198,	MODE(4) },	/* SOC_EHRPWM_TRIPZONE_INPUT4 */
+	{ 199,	MODE(4) },	/* SOC_EHRPWM4A */
+	{ 200,	MODE(4) },	/* SOC_EHRPWM4B */
+	{ 218,	MODE(4) },	/* SOC_EHRPWM_TRIPZONE_INPUT5 */
+	{ 219,	MODE(4) },	/* SOC_EHRPWM5A */
+	{ 220,	MODE(4) },	/* SOC_EHRPWM5B */
+	{ 222,	MODE(4) },	/* SOC_ECAP1_IN_PWM1_OUT */
+
+	/* SPI3 */
+	{ 86,	MODE(1) },	/* SOC_SPI3_SCS0 */
+	{ 88,	MODE(1) },	/* SOC_SPI3_CLK */
+	{ 89,	MODE(1) },	/* SOC_SPI3_MISO */
+	{ 90,	MODE(1) },	/* SOC_SPI3_MOSI */
+
+	/* CLK */
+	{ 97,	MODE(0) },	/* SMD - TP132 */
+
+	/* SPI0 */
+	{ 100,	MODE(0) },	/* SOC_SPI0_SCS0 */
+	{ 101,	MODE(0) },	/* SOC_SPI0_SCS1 */
+	{ 102,	MODE(0) },	/* SOC_SPI0_CLK */
+	{ 103,	MODE(0) },	/* SOC_SPI0_MISO */
+	{ 104,	MODE(0) },	/* SOC_SPI0_MOSI */
+
+	/* SPI1 NORFLASH */
+	{ 105,	MODE(0) },	/* SOC_SPI1_SCS0 */
+	{ 107,	MODE(0) },	/* SOC_SPI1_CLK */
+	{ 108,	MODE(0) },	/* SOC_SPI1_MISO */
+	{ 109,	MODE(0) },	/* SOC_SPI1_MOSI */
+
+	/* SPI2 */
+	{ 110,	MODE(0) },	/* SOC_SPI2_SCS0 */
+	{ 111,	MODE(1) },	/* SOC_HOUT */
+	{ 112,	MODE(0) },	/* SOC_SPI2_CLK */
+	{ 113,	MODE(0) },	/* SOC_SPI2_MISO */
+	{ 114,	MODE(0) },	/* SOC_SPI2_MOSI */
+
+	/* UART0 */
+	{ 115,	MODE(0) },	/* SOC_UART0_RXD */
+	{ 116,	MODE(0) },	/* SOC_UART0_TXD */
+	{ 117,	MODE(0) },	/* SOC_UART0_CTSn */
+	{ 118,	MODE(0) },	/* SOC_UART0_RTSn */
+
+	/* UART1 */
+	{ 119,	MODE(0) },	/* SOC_UART1_RXD */
+	{ 120,	MODE(0) },	/* SOC_UART1_TXD */
+	{ 121,	MODE(0) },	/* SOC_UART1_CTSn */
+	{ 122,	MODE(0) },	/* SOC_UART1_RTSn */
+
+	/* UART2 */
+	{ 123,	MODE(0) },	/* SOC_UART2_RXD */
+	{ 124,	MODE(0) },	/* SOC_UART2_TXD */
+	{ 125,	MODE(0) },	/* UART0_TXVR_EN */
+	{ 126,	MODE(4) },	/* SOC_CPTS_TS_COMP */
+
+	/* DCAN */
+	{ 127,	MODE(0) },	/* SOC_DCAN0_TX */
+	{ 128,	MODE(0) },	/* SOC_DCAN0_RX */
+	{ 137,	MODE(1) },	/* SOC_DCAN1_TX */
+	{ 138,	MODE(1) },	/* SOC_DCAN1_RX */
+
+	/* QSPI */
+	{ 129,	MODE(0) },	/* SOC_QSPI_CLK */
+	{ 130,	MODE(0) },	/* SOC_QSPI_RTCLK */
+	{ 131,	MODE(0) },	/* SOC_QSPI_D0 */
+	{ 132,	MODE(0) },	/* SOC_QSPI_D1 */
+	{ 133,	MODE(0) },	/* SOC_QSPI_D2 */
+	{ 134,	MODE(0) },	/* SOC_QSPI_D3 */
+	{ 135,	MODE(0) },	/* SOC_QSPI_CSN0 */
+	{ 136,	MODE(1) },	/* DNI <-> WLAN_SLOW_CLK */
+
+	/* MCASP2 */
+	{ 139,	MODE(3) },	/* SOC_MCASP2AXR0 - (GPIO0_108)SOC_LED0 */
+	{ 140,	MODE(4) },	/* SOC_MCASP2AXR1 */
+	{ 141,	MODE(4) },	/* SOC_MCASP2AXR2 */
+	{ 142,	MODE(4) },	/* SOC_MCASP2AXR3 */
+	{ 143,	MODE(4) },	/* SOC_MCASP2AXR4 */
+	{ 144,	MODE(4) },	/* SOC_MCASP2AXR5 */
+	{ 145,	MODE(4) },	/* SOC_McASP2ACLKR */
+	{ 146,	MODE(4) },	/* SOC_McASP2FSR */
+	{ 147,	MODE(4) },	/* SOC_McASP2AHCLKR */
+	{ 148,	MODE(3) },	/* GPIO0_117 - WLAN_TRANS_EN */
+	{ 149,	MODE(4) },	/* SOC_McASP2FSX */
+	{ 150,	MODE(4) },	/* SOC_McASP2AHCLKX */
+	{ 151,	MODE(4) },	/* SOC_McASP2ACLKX */
+
+	/* MCASP1 */
+	{ 152,	MODE(4) },	/* SOC_MCASP1ACLKR */
+	{ 153,	MODE(4) },	/* SOC_MCASP1FSR */
+	{ 154,	MODE(4) },	/* SOC_MCASP1AHCLKR */
+	{ 155,	MODE(4) },	/* SOC_MCASP1ACLKX */
+	{ 156,	MODE(4) },	/* SOC_MCASP1FSX */
+	{ 157,	MODE(4) },	/* SOC_MCASP1AHCLKX */
+	{ 158,	MODE(4) },	/* SOC_MCASP1AMUTE */
+	{ 159,	MODE(4) },	/* SOC_MCASP1AXR0 */
+	{ 160,	MODE(4) },	/* SOC_MCASP1AXR1 */
+	{ 161,	MODE(4) },	/* SOC_MCASP1AXR2 */
+	{ 162,	MODE(4) },	/* SOC_MCASP1AXR3 */
+	{ 163,	MODE(4) },	/* SOC_MCASP1AXR4 */
+	{ 164,	MODE(4) },	/* SOC_MCASP1AXR5 */
+	{ 165,	MODE(4) },	/* SOC_MCASP1AXR6 */
+	{ 166,	MODE(4) },	/* SOC_MCASP1AXR7 */
+	{ 167,	MODE(4) },	/* SOC_MCASP1AXR8 */
+	{ 168,	MODE(4) },	/* SOC_MCASP1AXR9 */
+
+	/* MCASP0 */
+	{ 169,	MODE(4) },	/* SOC_MCASP0AMUTE */
+	{ 170,	MODE(4) },	/* SOC_MCASP0ACLKR */
+	{ 171,	MODE(4) },	/* SOC_MCASP0FSR */
+	{ 172,	MODE(4) },	/* SOC_MCASP0AHCLKR */
+	{ 173,	MODE(4) },	/* SOC_MCASP0ACLKX */
+	{ 174,	MODE(4) },	/* SOC_MCASP0FSX */
+	{ 175,	MODE(4) },	/* SOC_MCASP0AHCLKX */
+	{ 176,	MODE(4) },	/* SOC_MCASP0AXR0 */
+	{ 177,	MODE(4) },	/* SOC_MCASP0AXR1 */
+	{ 178,	MODE(4) },	/* SOC_MCASP0AXR2 */
+	{ 179,	MODE(4) },	/* SOC_MCASP0AXR3 */
+	{ 180,	MODE(4) },	/* SOC_MCASP0AXR4 */
+	{ 181,	MODE(4) },	/* SOC_MCASP0AXR5 */
+	{ 182,	MODE(4) },	/* SOC_MCASP0AXR6 */
+	{ 183,	MODE(4) },	/* SOC_MCASP0AXR7 */
+	{ 184,	MODE(4) },	/* SOC_MCASP0AXR8 */
+	{ 185,	MODE(4) },	/* SOC_MCASP0AXR9 */
+	{ 186,	MODE(3) },	/* SOC_MCASP0AXR10 - (GPIO1_11)SOC_LED1 */
+	{ 188,	MODE(4) },	/* SOC_MCASP0AXR12 */
+	{ 189,	MODE(4) },	/* SOC_MCASP0AXR13 */
+	{ 190,	MODE(4) },	/* SOC_MCASP0AXR14 */
+	{ 191,	MODE(4) },	/* SOC_MCASP0AXR15 */
+
+	/* MMC0 */
+	{ 192,	MODE(2) },	/* SOC_MMC0_DAT3 */
+	{ 193,	MODE(2) },	/* SOC_MMC0_DAT2 */
+	{ 194,	MODE(2) },	/* SOC_MMC0_DAT1 */
+	{ 195,	MODE(2) },	/* SOC_MMC0_DAT0 */
+	{ 196,	MODE(2) },	/* SOC_MMC0_CLK */
+	{ 197,	MODE(2) },	/* SOC_MMC0_CMD */
+	{ 187,	MODE(2) },	/* SOC_MMC0_SDCD */
+
+	/* McBSP */
+	{ 28,	MODE(2) | PIN_IEN },	/* SOC_TIMI1 */
+	{ 29,	MODE(2) },		/* SOC_TIMO1 */
+	{ 210,	MODE(2) },	/* SOC_MCBSPDR */
+	{ 211,	MODE(2) },	/* SOC_MCBSPDX */
+	{ 212,	MODE(2) },	/* SOC_MCBSPFSX */
+	{ 213,	MODE(2) },	/* SOC_MCBSPCLKX */
+	{ 214,	MODE(2) },	/* SOC_MCBSPFSR */
+	{ 215,	MODE(2) },	/* SOC_MCBSPCLKR */
+
+	/* I2C */
+	{ 223,	MODE(0) },	/* SOC_I2C0_SCL */
+	{ 224,	MODE(0) },	/* SOC_I2C0_SDA */
+	{ 225,	MODE(0) },	/* SOC_I2C1_SCL */
+	{ 226,	MODE(0) },	/* SOC_I2C1_SDA */
+	{ 227,	MODE(0) },	/* SOC_I2C2_SCL */
+	{ 228,	MODE(0) },	/* SOC_I2C2_SDA */
+	{ 229,	MODE(0) },	/* NMIz */
+	{ 230,	MODE(0) },	/* LRESETz */
+	{ 231,	MODE(0) },	/* LRESETNMIENz */
+
+	{ 235,	MODE(0) },
+	{ 236,	MODE(0) },
+	{ 237,	MODE(0) },
+	{ 238,	MODE(0) },
+	{ 239,	MODE(0) },
+	{ 240,	MODE(0) },
+	{ 241,	MODE(0) },
+	{ 242,	MODE(0) },
+	{ 243,	MODE(0) },
+	{ 244,	MODE(0) },
+
+	{ 258,	MODE(0) },	/* USB0DRVVBUS */
+	{ 259,	MODE(0) },	/* USB1DRVVBUS */
+	{ MAX_PIN_N, }
+};
+
+struct pin_cfg k2g_ice_evm_pin_cfg[] = {
+	/* MMC 1 */
+	{ 63, MODE(0) | PIN_PTD },	/* MMC1_DAT3.MMC1_DAT3 */
+	{ 64, MODE(0) | PIN_PTU },	/* MMC1_DAT2.MMC1_DAT2 */
+	{ 65, MODE(0) | PIN_PTU },	/* MMC1_DAT1.MMC1_DAT1 */
+	{ 66, MODE(0) | PIN_PTD },	/* MMC1_DAT0.MMC1_DAT0 */
+	{ 67, MODE(0) | PIN_PTD },	/* MMC1_CLK.MMC1_CLK   */
+	{ 68, MODE(0) | PIN_PTD },	/* MMC1_CMD.MMC1_CMD   */
+	{ 69, MODE(3) | PIN_PTU },	/* MMC1_SDCD.GPIO0_69  */
+	{ 70, MODE(0) | PIN_PTU },	/* MMC1_SDWP.MMC1_SDWP */
+	{ 71, MODE(0) | PIN_PTD },	/* MMC1_POW.MMC1_POW   */
+
+	/* I2C 0 */
+	{ 223,  MODE(0) },		/* SOC_I2C0_SCL */
+	{ 224,  MODE(0) },		/* SOC_I2C0_SDA */
+
+	/* QSPI */
+	{ 129,	MODE(0) },	/* SOC_QSPI_CLK */
+	{ 130,	MODE(0) },	/* SOC_QSPI_RTCLK */
+	{ 131,	MODE(0) },	/* SOC_QSPI_D0 */
+	{ 132,	MODE(0) },	/* SOC_QSPI_D1 */
+	{ 133,	MODE(0) },	/* SOC_QSPI_D2 */
+	{ 134,	MODE(0) },	/* SOC_QSPI_D3 */
+	{ 135,	MODE(0) },	/* SOC_QSPI_CSN0 */
+
+	/* EMAC */
+	{ 72,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_RXC */
+	{ 77,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_RXD3 */
+	{ 78,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_RXD2 */
+	{ 79,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_RXD1 */
+	{ 80,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_RXD0 */
+	{ 81,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_RXCTL */
+	{ 85,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_TXC */
+	{ 91,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_TXD3 */
+	{ 92,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_TXD2 */
+	{ 93,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_TXD1 */
+	{ 94,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_TXD0 */
+	{ 95,	BUFFER_CLASS_D | PIN_PDIS | MODE(1) },	/* RGMII_TXCTL */
+
+	/* MDIO */
+	{ 98,	BUFFER_CLASS_B | PIN_PDIS | MODE(0) },	/* MDIO_DATA */
+	{ 99,	BUFFER_CLASS_B | PIN_PDIS | MODE(0) },	/* MDIO_CLK */
+
+	{ MAX_PIN_N, }
+};
+
+void k2g_mux_config(void)
+{
+	if (!board_ti_was_eeprom_read()) {
+		configure_pin_mux(k2g_generic_pin_cfg);
+	} else if (board_is_k2g_gp() || board_is_k2g_g1()) {
+		configure_pin_mux(k2g_evm_pin_cfg);
+	} else if (board_is_k2g_ice() || board_is_k2g_i1()) {
+		configure_pin_mux(k2g_ice_evm_pin_cfg);
+	} else {
+		puts("Unknown board, cannot configure pinmux.");
+		hang();
+	}
+}
diff --git a/roms/u-boot/board/ti/omap5_uevm/Kconfig b/roms/u-boot/board/ti/omap5_uevm/Kconfig
new file mode 100644
index 000000000..aa1384454
--- /dev/null
+++ b/roms/u-boot/board/ti/omap5_uevm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP5_UEVM
+
+config SYS_BOARD
+	default "omap5_uevm"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_CONFIG_NAME
+	default "omap5_uevm"
+
+endif
diff --git a/roms/u-boot/board/ti/omap5_uevm/MAINTAINERS b/roms/u-boot/board/ti/omap5_uevm/MAINTAINERS
new file mode 100644
index 000000000..280ea2f91
--- /dev/null
+++ b/roms/u-boot/board/ti/omap5_uevm/MAINTAINERS
@@ -0,0 +1,6 @@
+OMAP5_UEVM BOARD
+M:	Lokesh Vutla <lokeshvutla@ti.com>
+S:	Maintained
+F:	board/ti/omap5_uevm/
+F:	include/configs/omap5_uevm.h
+F:	configs/omap5_uevm_defconfig
diff --git a/roms/u-boot/board/ti/omap5_uevm/Makefile b/roms/u-boot/board/ti/omap5_uevm/Makefile
new file mode 100644
index 000000000..17ee516d2
--- /dev/null
+++ b/roms/u-boot/board/ti/omap5_uevm/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= evm.o
diff --git a/roms/u-boot/board/ti/omap5_uevm/README b/roms/u-boot/board/ti/omap5_uevm/README
new file mode 100644
index 000000000..970e2eceb
--- /dev/null
+++ b/roms/u-boot/board/ti/omap5_uevm/README
@@ -0,0 +1,25 @@
+Summary
+=======
+
+This document covers various features of the 'omap5_uevm' build and some
+related uses.
+
+eMMC boot partition use
+=======================
+
+It is possible, depending on SYSBOOT configuration to boot from the eMMC
+boot partitions using (name depending on documentation referenced)
+Alternative Boot operation mode or Boot Sequence Option 1/2.  In this
+example we load MLO and u-boot.img from the build into DDR and then use
+'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
+set boot0 as the boot device.
+U-Boot # setenv autoload no
+U-Boot # usb start
+U-Boot # dhcp
+U-Boot # mmc dev 1 1
+U-Boot # tftp ${loadaddr} omap5uevm/MLO
+U-Boot # mmc write ${loadaddr} 0 100
+U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img
+U-Boot # mmc write ${loadaddr} 300 400
+U-Boot # mmc bootbus 1 2 0 2
+U-Boot # mmc partconf 1 1 1 0
diff --git a/roms/u-boot/board/ti/omap5_uevm/evm.c b/roms/u-boot/board/ti/omap5_uevm/evm.c
new file mode 100644
index 000000000..477762215
--- /dev/null
+++ b/roms/u-boot/board/ti/omap5_uevm/evm.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Aneesh V       <aneesh@ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ */
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <palmas.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <serial.h>
+#include <tca642x.h>
+#include <usb.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/usb/gadget.h>
+#include <dwc3-uboot.h>
+#include <dwc3-omap-uboot.h>
+#include <ti-usb-phy-uboot.h>
+
+#include "mux_data.h"
+
+#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
+#include <sata.h>
+#include <usb.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ehci.h>
+#include <asm/ehci-omap.h>
+#include <asm/arch/sata.h>
+
+#define DIE_ID_REG_BASE     (OMAP54XX_L4_CORE_BASE + 0x2000)
+#define DIE_ID_REG_OFFSET	0x200
+
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+	"Board: OMAP5432 uEVM\n"
+};
+
+/**
+ * @brief tca642x_init - uEVM default values for the GPIO expander
+ * input reg, output reg, polarity reg, configuration reg
+ */
+struct tca642x_bank_info tca642x_init[] = {
+	{ .input_reg = 0x00,
+	  .output_reg = 0x04,
+	  .polarity_reg = 0x00,
+	  .configuration_reg = 0x80 },
+	{ .input_reg = 0x00,
+	  .output_reg = 0x00,
+	  .polarity_reg = 0x00,
+	  .configuration_reg = 0xff },
+	{ .input_reg = 0x00,
+	  .output_reg = 0x00,
+	  .polarity_reg = 0x00,
+	  .configuration_reg = 0x40 },
+};
+
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device usb_otg_ss = {
+	.maximum_speed = USB_SPEED_SUPER,
+	.base = OMAP5XX_USB_OTG_SS_BASE,
+	.tx_fifo_resize = false,
+	.index = 0,
+};
+
+static struct dwc3_omap_device usb_otg_ss_glue = {
+	.base = (void *)OMAP5XX_USB_OTG_SS_GLUE_BASE,
+	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
+	.index = 0,
+};
+
+static struct ti_usb_phy_device usb_phy_device = {
+	.pll_ctrl_base = (void *)OMAP5XX_USB3_PHY_PLL_CTRL,
+	.usb2_phy_power = (void *)OMAP5XX_USB2_PHY_POWER,
+	.usb3_phy_power = (void *)OMAP5XX_USB3_PHY_POWER,
+	.index = 0,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	if (index) {
+		printf("Invalid Controller Index\n");
+		return -EINVAL;
+	}
+
+	if (init == USB_INIT_DEVICE) {
+		usb_otg_ss.dr_mode = USB_DR_MODE_PERIPHERAL;
+		usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+	} else {
+		usb_otg_ss.dr_mode = USB_DR_MODE_HOST;
+		usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+	}
+
+	enable_usb_clocks(index);
+	ti_usb_phy_uboot_init(&usb_phy_device);
+	dwc3_omap_uboot_init(&usb_otg_ss_glue);
+	dwc3_uboot_init(&usb_otg_ss);
+
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	if (index) {
+		printf("Invalid Controller Index\n");
+		return -EINVAL;
+	}
+
+	ti_usb_phy_uboot_exit(index);
+	dwc3_uboot_exit(index);
+	dwc3_omap_uboot_exit(index);
+	disable_usb_clocks(index);
+
+	return 0;
+}
+
+int usb_gadget_handle_interrupts(int index)
+{
+	u32 status;
+
+	status = dwc3_omap_uboot_interrupt_status(index);
+	if (status)
+		dwc3_uboot_handle_interrupt(index);
+
+	return 0;
+}
+#endif
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+	gpmc_init();
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
+	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+	tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+int board_eth_init(struct bd_info *bis)
+{
+	return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure EVM board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_PALMAS_POWER
+	palmas_init_settings();
+#endif
+
+	omap_die_id_usbethaddr();
+
+	return 0;
+}
+
+void set_muxconf_regs(void)
+{
+	do_set_mux((*ctrl)->control_padconf_core_base,
+		   core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux((*ctrl)->control_padconf_wkup_base,
+		   wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+}
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(struct bd_info *bis)
+{
+	omap_mmc_init(0, 0, 0, -1, -1);
+	omap_mmc_init(1, 0, 0, -1, -1);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_OMAP
+/**
+ * @brief board_usb_init - Configure EVM board specific configurations
+ * for the LDO's and clocks for the USB blocks.
+ *
+ * @return 0
+ */
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret;
+#ifdef CONFIG_PALMAS_USB_SS_PWR
+	ret = palmas_enable_ss_ldo();
+#endif
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/ti/omap5_uevm/mux_data.h b/roms/u-boot/board/ti/omap5_uevm/mux_data.h
new file mode 100644
index 000000000..3c4ba4749
--- /dev/null
+++ b/roms/u-boot/board/ti/omap5_uevm/mux_data.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Sricharan R		<r.sricharan@ti.com>
+ */
+#ifndef _EVM5430_MUX_DATA_H
+#define _EVM5430_MUX_DATA_H
+
+#include <asm/arch/mux_omap5.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+	{EMMC_CLK, (PTU | IEN | M0)}, /*  EMMC_CLK   */
+	{EMMC_CMD, (PTU | IEN | M0)}, /*  EMMC_CMD   */
+	{EMMC_DATA0, (PTU | IEN | M0)}, /*  EMMC_DATA0 */
+	{EMMC_DATA1, (PTU | IEN | M0)}, /*  EMMC_DATA1 */
+	{EMMC_DATA2, (PTU | IEN | M0)}, /*  EMMC_DATA2 */
+	{EMMC_DATA3, (PTU | IEN | M0)}, /*  EMMC_DATA3 */
+	{EMMC_DATA4, (PTU | IEN | M0)}, /*  EMMC_DATA4 */
+	{EMMC_DATA5, (PTU | IEN | M0)}, /*  EMMC_DATA5 */
+	{EMMC_DATA6, (PTU | IEN | M0)}, /*  EMMC_DATA6 */
+	{EMMC_DATA7, (PTU | IEN | M0)}, /*  EMMC_DATA7 */
+	{SDCARD_CLK, (PTU | IEN | M0)}, /*  SDCARD_CLK  */
+	{SDCARD_CMD, (PTU | IEN | M0)}, /*  SDCARD_CMD  */
+	{SDCARD_DATA0, (PTU | IEN | M0)}, /*  SDCARD_DATA0*/
+	{SDCARD_DATA1, (PTU | IEN | M0)}, /*  SDCARD_DATA1*/
+	{SDCARD_DATA2, (PTU | IEN | M0)}, /*  SDCARD_DATA2*/
+	{SDCARD_DATA3, (PTU | IEN | M0)}, /*  SDCARD_DATA3*/
+	{UART3_RX_IRRX, (PTU | IEN | M0)}, /*  UART3_RX_IRRX    */
+	{UART3_TX_IRTX, (M0)},    /*  UART3_TX_IRTX    */
+	{USBB1_HSIC_STROBE, (PTU | IEN | M0)},    /*  USBB1_HSIC_STROBE */
+	{USBB1_HSIC_DATA, (PTU | IEN | M0)},    /*  USBB1_HSIC_DATA */
+	{USBB2_HSIC_STROBE, (PTU | IEN | M0)},    /*  USBB2_HSIC_STROBE */
+	{USBB2_HSIC_DATA, (PTU | IEN | M0)},    /*  USBB2_HSIC_DATA  */
+	{USBB3_HSIC_STROBE, (PTU | IEN | M0)},    /*  USBB3_HSIC_STROBE*/
+	{USBB3_HSIC_DATA, (PTU | IEN | M0)},    /*  USBB3_HSIC_DATA  */
+	{USBD0_HS_DP, (IEN | M0)},	/*  USBD0_HS_DP */
+	{USBD0_HS_DM, (IEN | M0)},	/*  USBD0_HS_DM */
+	{USBD0_SS_RX, (IEN | M0)},	/*  USBD0_SS_RX */
+	{I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
+	{I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
+	{HSI2_ACWAKE, (PTU | M6)},    /*  HSI2_ACWAKE */
+	{HSI2_CAFLAG, (PTU | M6)},    /*  HSI2_CAFLAG */
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+	{SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
+	{SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
+	{SYS_32K, (IEN | M0)}, /*  SYS_32K     */
+	{FREF_CLK1_OUT, (PTD | IEN | M0)},    /*  FREF_CLK1_OUT  */
+
+};
+
+#endif /* _EVM4430_MUX_DATA_H */
diff --git a/roms/u-boot/board/ti/panda/Kconfig b/roms/u-boot/board/ti/panda/Kconfig
new file mode 100644
index 000000000..8f277b612
--- /dev/null
+++ b/roms/u-boot/board/ti/panda/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP4_PANDA
+
+config SYS_BOARD
+	default "panda"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_CONFIG_NAME
+	default "omap4_panda"
+
+endif
diff --git a/roms/u-boot/board/ti/panda/MAINTAINERS b/roms/u-boot/board/ti/panda/MAINTAINERS
new file mode 100644
index 000000000..214236827
--- /dev/null
+++ b/roms/u-boot/board/ti/panda/MAINTAINERS
@@ -0,0 +1,6 @@
+PANDA BOARD
+M:	Lokesh Vutla <lokeshvutla@ti.com>
+S:	Maintained
+F:	board/ti/panda/
+F:	include/configs/omap4_panda.h
+F:	configs/omap4_panda_defconfig
diff --git a/roms/u-boot/board/ti/panda/Makefile b/roms/u-boot/board/ti/panda/Makefile
new file mode 100644
index 000000000..dd2ff33af
--- /dev/null
+++ b/roms/u-boot/board/ti/panda/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= panda.o
diff --git a/roms/u-boot/board/ti/panda/panda.c b/roms/u-boot/board/ti/panda/panda.c
new file mode 100644
index 000000000..fda8d5f3c
--- /dev/null
+++ b/roms/u-boot/board/ti/panda/panda.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ */
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <serial.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <env.h>
+#include <twl6030.h>
+
+#include "panda_mux_data.h"
+
+#define PANDA_ULPI_PHY_TYPE_GPIO       182
+#define PANDA_BOARD_ID_1_GPIO          101
+#define PANDA_ES_BOARD_ID_1_GPIO        48
+#define PANDA_BOARD_ID_2_GPIO          171
+#define PANDA_ES_BOARD_ID_3_GPIO         3
+#define PANDA_ES_BOARD_ID_4_GPIO         2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+	"Board: OMAP4 Panda\n"
+};
+
+struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+	gpmc_init();
+
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
+	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+int board_eth_init(struct bd_info *bis)
+{
+	return 0;
+}
+
+/*
+* Routine: get_board_revision
+* Description: Detect if we are running on a panda revision A1-A6,
+*              or an ES panda board. This can be done by reading
+*              the level of GPIOs and checking the processor revisions.
+*              This should result in:
+*			Panda 4430:
+*              GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
+*              GPIO171, GPIO101, GPIO182: 1 0 1 => A6
+*			Panda ES:
+*              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
+*              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
+*/
+int get_board_revision(void)
+{
+	int board_id0, board_id1, board_id2;
+	int board_id3, board_id4;
+	int board_id;
+
+	int processor_rev = omap_revision();
+
+	/* Setup the mux for the common board ID pins (gpio 171 and 182) */
+	writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
+	writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
+
+	board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
+	board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
+
+	if ((processor_rev >= OMAP4460_ES1_0 &&
+	     processor_rev <= OMAP4460_ES1_1)) {
+		/*
+		 * Setup the mux for the ES specific board ID pins (gpio 101,
+		 * 2 and 3.
+		 */
+		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+				GPMC_A24);
+		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+				UNIPRO_RY0);
+		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+				UNIPRO_RX1);
+
+		board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
+		board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
+		board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+		env_set("board_name", "panda-es");
+#endif
+		board_id = ((board_id4 << 4) | (board_id3 << 3) |
+			(board_id2 << 2) | (board_id1 << 1) | (board_id0));
+	} else {
+		/* Setup the mux for the Ax specific board ID pins (gpio 101) */
+		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+				FREF_CLK2_OUT);
+
+		board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
+		board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+		if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
+			env_set("board_name", "panda-a4");
+#endif
+	}
+
+	return board_id;
+}
+
+/**
+ * is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES
+ *
+ *
+ * Detect if we are running on B3 version of ES panda board,
+ * This can be done by reading the level of GPIO 171 and checking the
+ * processor revisions.
+ * GPIO171: 1 => Panda ES Rev B3
+ *
+ * Return : return 1 if Panda ES Rev B3 , else return 0
+ */
+u8 is_panda_es_rev_b3(void)
+{
+        int processor_rev = omap_revision();
+        int ret = 0;
+
+        if ((processor_rev >= OMAP4460_ES1_0 &&
+             processor_rev <= OMAP4460_ES1_1)) {
+
+                /* Setup the mux for the common board ID pins (gpio 171) */
+                writew((IEN | M3),
+			(*ctrl)->control_padconf_core_base + UNIPRO_TX0);
+
+                /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */
+                ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
+        }
+        return ret;
+}
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+/*
+ * emif_get_reg_dump() - emif_get_reg_dump strong function
+ *
+ * @emif_nr - emif base
+ * @regs - reg dump of timing values
+ *
+ * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c
+ */
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+	u32 omap4_rev = omap_revision();
+
+	/* Same devices and geometry on both EMIFs */
+	if (omap4_rev == OMAP4430_ES1_0)
+		*regs = &emif_regs_elpida_380_mhz_1cs;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		*regs = &emif_regs_elpida_200_mhz_2cs;
+	else if (omap4_rev == OMAP4430_ES2_3)
+		*regs = &emif_regs_elpida_400_mhz_1cs;
+	else if (omap4_rev < OMAP4470_ES1_0) {
+		if(is_panda_es_rev_b3())
+			*regs = &emif_regs_elpida_400_mhz_1cs;
+		else
+			*regs = &emif_regs_elpida_400_mhz_2cs;
+	}
+	else
+		*regs = &emif_regs_elpida_400_mhz_1cs;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs
+						**dmm_lisa_regs)
+{
+	u32 omap_rev = omap_revision();
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
+	else if (omap_rev == OMAP4430_ES2_3)
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+	else if (omap_rev < OMAP4460_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+	else
+		*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
+}
+
+#endif
+
+/**
+ * @brief misc_init_r - Configure Panda board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+	int phy_type;
+	u32 auxclk, altclksrc;
+
+	/* EHCI is not supported on ES1.0 */
+	if (omap_revision() == OMAP4430_ES1_0)
+		return 0;
+
+	get_board_revision();
+
+	gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
+	phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
+
+	if (phy_type == 1) {
+		/* ULPI PHY supplied by auxclk3 derived from sys_clk */
+		debug("ULPI PHY supplied by auxclk3\n");
+
+		auxclk = readl(&scrm->auxclk3);
+		/* Select sys_clk */
+		auxclk &= ~AUXCLK_SRCSELECT_MASK;
+		auxclk |=  AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
+		/* Set the divisor to 2 */
+		auxclk &= ~AUXCLK_CLKDIV_MASK;
+		auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
+		/* Request auxilary clock #3 */
+		auxclk |= AUXCLK_ENABLE_MASK;
+
+		writel(auxclk, &scrm->auxclk3);
+	} else {
+		/* ULPI PHY supplied by auxclk1 derived from PER dpll */
+		debug("ULPI PHY supplied by auxclk1\n");
+
+		auxclk = readl(&scrm->auxclk1);
+		/* Select per DPLL */
+		auxclk &= ~AUXCLK_SRCSELECT_MASK;
+		auxclk |=  AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
+		/* Set the divisor to 16 */
+		auxclk &= ~AUXCLK_CLKDIV_MASK;
+		auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
+		/* Request auxilary clock #3 */
+		auxclk |= AUXCLK_ENABLE_MASK;
+
+		writel(auxclk, &scrm->auxclk1);
+	}
+
+	altclksrc = readl(&scrm->altclksrc);
+
+	/* Activate alternate system clock supplier */
+	altclksrc &= ~ALTCLKSRC_MODE_MASK;
+	altclksrc |= ALTCLKSRC_MODE_ACTIVE;
+
+	/* enable clocks */
+	altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
+
+	writel(altclksrc, &scrm->altclksrc);
+
+	omap_die_id_usbethaddr();
+
+	return 0;
+}
+
+void set_muxconf_regs(void)
+{
+	do_set_mux((*ctrl)->control_padconf_core_base,
+		   core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux((*ctrl)->control_padconf_wkup_base,
+		   wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	if (omap_revision() >= OMAP4460_ES1_0)
+		do_set_mux((*ctrl)->control_padconf_wkup_base,
+			   wkup_padconf_array_essential_4460,
+			   sizeof(wkup_padconf_array_essential_4460) /
+			   sizeof(struct pad_conf_entry));
+}
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(struct bd_info *bis)
+{
+	return omap_mmc_init(0, 0, 0, -1, -1);
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+void board_mmc_power_init(void)
+{
+	twl6030_power_mmc_init(0);
+}
+#endif
+#endif
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+	return 0x20;
+}
diff --git a/roms/u-boot/board/ti/panda/panda_mux_data.h b/roms/u-boot/board/ti/panda/panda_mux_data.h
new file mode 100644
index 000000000..ad9e36525
--- /dev/null
+++ b/roms/u-boot/board/ti/panda/panda_mux_data.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ */
+#ifndef _PANDA_MUX_DATA_H_
+#define _PANDA_MUX_DATA_H_
+
+#include <asm/arch/mux_omap4.h>
+
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
+{UART3_TX_IRTX, (M0)},					/* uart3_tx */
+{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
+{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
+{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
+{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
+{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
+{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
+{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
+{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
+{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
+{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
+{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
+{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
+{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
+{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
+{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
+{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
+{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
+{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)},	 /* sys_32k */
+{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
+
+{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
+
+};
+
+#endif /* _PANDA_MUX_DATA_H_ */
diff --git a/roms/u-boot/board/ti/sdp4430/Kconfig b/roms/u-boot/board/ti/sdp4430/Kconfig
new file mode 100644
index 000000000..36f185282
--- /dev/null
+++ b/roms/u-boot/board/ti/sdp4430/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_OMAP4_SDP4430
+
+config SYS_BOARD
+	default "sdp4430"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_CONFIG_NAME
+	default "omap4_sdp4430"
+
+config CMD_BAT
+	bool "Enable board-specific battery command"
+
+endif
diff --git a/roms/u-boot/board/ti/sdp4430/MAINTAINERS b/roms/u-boot/board/ti/sdp4430/MAINTAINERS
new file mode 100644
index 000000000..ac4d0ccc1
--- /dev/null
+++ b/roms/u-boot/board/ti/sdp4430/MAINTAINERS
@@ -0,0 +1,6 @@
+SDP4430 BOARD
+M:	Lokesh Vutla <lokeshvutla@ti.com>
+S:	Maintained
+F:	board/ti/sdp4430/
+F:	include/configs/omap4_sdp4430.h
+F:	configs/omap4_sdp4430_defconfig
diff --git a/roms/u-boot/board/ti/sdp4430/Makefile b/roms/u-boot/board/ti/sdp4430/Makefile
new file mode 100644
index 000000000..ae0694561
--- /dev/null
+++ b/roms/u-boot/board/ti/sdp4430/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= sdp.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y	+= cmd_bat.o
+endif
diff --git a/roms/u-boot/board/ti/sdp4430/cmd_bat.c b/roms/u-boot/board/ti/sdp4430/cmd_bat.c
new file mode 100644
index 000000000..6c1e6ca39
--- /dev/null
+++ b/roms/u-boot/board/ti/sdp4430/cmd_bat.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010 Texas Instruments
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CMD_BAT
+#include <twl6030.h>
+
+int do_vbat(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	if (argc == 2) {
+		if (strncmp(argv[1], "startcharge", 12) == 0)
+			twl6030_start_usb_charging();
+		else if (strncmp(argv[1], "stopcharge", 11) == 0)
+			twl6030_stop_usb_charging();
+		else if (strncmp(argv[1], "status", 7) == 0) {
+			twl6030_get_battery_voltage();
+			twl6030_get_battery_current();
+		} else {
+			goto bat_cmd_usage;
+		}
+	} else {
+		goto bat_cmd_usage;
+	}
+	return 0;
+
+bat_cmd_usage:
+	return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+	bat, 2, 1, do_vbat,
+	"battery charging, voltage/current measurements",
+	"status - display battery voltage and current\n"
+	"bat startcharge - start charging via USB\n"
+	"bat stopcharge - stop charging\n"
+);
+#endif /* CONFIG_CMD_BAT */
diff --git a/roms/u-boot/board/ti/sdp4430/sdp.c b/roms/u-boot/board/ti/sdp4430/sdp.c
new file mode 100644
index 000000000..4895bfafd
--- /dev/null
+++ b/roms/u-boot/board/ti/sdp4430/sdp.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Aneesh V       <aneesh@ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ */
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <twl6030.h>
+#include <serial.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/global_data.h>
+
+#include "sdp4430_mux_data.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+	"Board: OMAP4430 SDP\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+	gpmc_init();
+
+	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure SDP board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_TWL6030_POWER
+	twl6030_init_battery_charging();
+#endif
+	return 0;
+}
+
+void set_muxconf_regs(void)
+{
+	do_set_mux((*ctrl)->control_padconf_core_base,
+		   core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux((*ctrl)->control_padconf_wkup_base,
+		   wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	if ((omap_revision() >= OMAP4460_ES1_0) &&
+			(omap_revision() < OMAP4470_ES1_0))
+		do_set_mux((*ctrl)->control_padconf_wkup_base,
+				 wkup_padconf_array_essential_4460,
+				 sizeof(wkup_padconf_array_essential_4460) /
+				 sizeof(struct pad_conf_entry));
+}
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(struct bd_info *bis)
+{
+	omap_mmc_init(0, 0, 0, -1, -1);
+	omap_mmc_init(1, 0, 0, -1, -1);
+	return 0;
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+void board_mmc_power_init(void)
+{
+	twl6030_power_mmc_init(0);
+	twl6030_power_mmc_init(1);
+}
+#endif
+#endif
+
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+	return 0x20;
+}
diff --git a/roms/u-boot/board/ti/sdp4430/sdp4430_mux_data.h b/roms/u-boot/board/ti/sdp4430/sdp4430_mux_data.h
new file mode 100644
index 000000000..934419f40
--- /dev/null
+++ b/roms/u-boot/board/ti/sdp4430/sdp4430_mux_data.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
+
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
+{UART3_TX_IRTX, (M0)},					/* uart3_tx */
+{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
+{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
+{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
+{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
+{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
+{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
+{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
+{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
+{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
+{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
+{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
+
+{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
+
+};
+
+#endif /* _SDP4430_MUX_DATA_H */
diff --git a/roms/u-boot/board/ti/ti816x/Kconfig b/roms/u-boot/board/ti/ti816x/Kconfig
new file mode 100644
index 000000000..95973b47f
--- /dev/null
+++ b/roms/u-boot/board/ti/ti816x/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TI816X_EVM
+
+config SYS_BOARD
+	default "ti816x"
+
+config SYS_VENDOR
+	default "ti"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "ti816x_evm"
+
+endif
diff --git a/roms/u-boot/board/ti/ti816x/MAINTAINERS b/roms/u-boot/board/ti/ti816x/MAINTAINERS
new file mode 100644
index 000000000..fd9a98fc7
--- /dev/null
+++ b/roms/u-boot/board/ti/ti816x/MAINTAINERS
@@ -0,0 +1,6 @@
+TI816X BOARD
+M:	Tom Rini <trini@konsulko.com>
+S:	Maintained
+F:	board/ti/ti816x/
+F:	include/configs/ti816x_evm.h
+F:	configs/ti816x_evm_defconfig
diff --git a/roms/u-boot/board/ti/ti816x/Makefile b/roms/u-boot/board/ti/ti816x/Makefile
new file mode 100644
index 000000000..f12712aea
--- /dev/null
+++ b/roms/u-boot/board/ti/ti816x/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+# Antoine Tenart, <atenart@adeneo-embedded.com>
+#
+# Based on TI-PSP-04.00.02.14 :
+#
+# Copyright (C) 2009, Texas Instruments, Incorporated
+
+obj-y	:= evm.o
diff --git a/roms/u-boot/board/ti/ti816x/evm.c b/roms/u-boot/board/ti/ti816x/evm.c
new file mode 100644
index 000000000..2d42af6b8
--- /dev/null
+++ b/roms/u-boot/board/ti/ti816x/evm.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * evm.c
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <spl.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_MTD_RAW_NAND)
+	gpmc_init();
+#endif
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+		printf("<ethaddr> not set. Reading from E-fuse\n");
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+		else
+			printf("Unable to read MAC address. Set <ethaddr>\n");
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+static struct module_pin_mux mmc_pin_mux[] = {
+	{ OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
+	{ OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
+	{ OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+	{ OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+	{ OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+	{ OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+	{ OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+	{ -1 },
+};
+
+void set_uart_mux_conf(void) {}
+
+void set_mux_conf_regs(void)
+{
+	configure_module_pin_mux(mmc_pin_mux);
+}
+
+/*
+ * EMIF Paramters.  Refer the EMIF register documentation and the
+ * memory datasheet for details.  This is for 796 MHz.
+ */
+#define EMIF_TIM1   0x1779C9FE
+#define EMIF_TIM2   0x50608074
+#define EMIF_TIM3   0x009F857F
+#define EMIF_SDREF  0x10001841
+#define EMIF_SDCFG  0x62A73832
+#define EMIF_PHYCFG 0x00000110
+static const struct emif_regs ddr3_emif_regs = {
+	.sdram_config		= EMIF_SDCFG,
+	.ref_ctrl		= EMIF_SDREF,
+	.sdram_tim1		= EMIF_TIM1,
+	.sdram_tim2		= EMIF_TIM2,
+	.sdram_tim3		= EMIF_TIM3,
+	.emif_ddr_phy_ctlr_1	= EMIF_PHYCFG,
+};
+
+static const struct cmd_control ddr3_ctrl = {
+	.cmd0csratio	= 0x100,
+	.cmd0iclkout	= 0x001,
+	.cmd1csratio	= 0x100,
+	.cmd1iclkout	= 0x001,
+	.cmd2csratio	= 0x100,
+	.cmd2iclkout	= 0x001,
+};
+
+/* These values are obtained from the CCS app */
+#define RD_DQS_GATE	(0x1B3)
+#define RD_DQS		(0x35)
+#define WR_DQS		(0x93)
+static struct ddr_data ddr3_data = {
+	.datardsratio0		= ((RD_DQS<<10) | (RD_DQS<<0)),
+	.datawdsratio0		= ((WR_DQS<<10) | (WR_DQS<<0)),
+	.datawiratio0		= ((0x20<<10) | 0x20<<0),
+	.datagiratio0		= ((0x20<<10) | 0x20<<0),
+	.datafwsratio0		= ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
+	.datawrsratio0		= (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
+};
+
+static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
+	.dmm_lisa_map_0 = 0x00000000,
+	.dmm_lisa_map_1 = 0x00000000,
+	.dmm_lisa_map_2 = 0x80640300,
+	.dmm_lisa_map_3 = 0xC0640320,
+};
+
+void sdram_init(void)
+{
+	/*
+	 * Pass in our DDR3 config information and that we have 2 EMIFs to
+	 * configure.
+	 */
+	config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
+			&evm_lisa_map_regs, 2);
+}
+#endif /* CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/timll/devkit3250/Kconfig b/roms/u-boot/board/timll/devkit3250/Kconfig
new file mode 100644
index 000000000..5129c2dca
--- /dev/null
+++ b/roms/u-boot/board/timll/devkit3250/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DEVKIT3250
+
+config SYS_BOARD
+	default "devkit3250"
+
+config SYS_VENDOR
+	default "timll"
+
+config SYS_CONFIG_NAME
+	default "devkit3250"
+
+endif
diff --git a/roms/u-boot/board/timll/devkit3250/MAINTAINERS b/roms/u-boot/board/timll/devkit3250/MAINTAINERS
new file mode 100644
index 000000000..cb93563fe
--- /dev/null
+++ b/roms/u-boot/board/timll/devkit3250/MAINTAINERS
@@ -0,0 +1,6 @@
+DEVKIT3250 BOARD
+M:	Vladimir Zapolskiy <vz@mleia.com>
+S:	Maintained
+F:	board/timll/devkit3250/
+F:	include/configs/devkit3250.h
+F:	configs/devkit3250_defconfig
diff --git a/roms/u-boot/board/timll/devkit3250/Makefile b/roms/u-boot/board/timll/devkit3250/Makefile
new file mode 100644
index 000000000..056813995
--- /dev/null
+++ b/roms/u-boot/board/timll/devkit3250/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+
+obj-y	:= devkit3250.o
+obj-$(CONFIG_SPL_BUILD) += devkit3250_spl.o
diff --git a/roms/u-boot/board/timll/devkit3250/devkit3250.c b/roms/u-boot/board/timll/devkit3250/devkit3250.c
new file mode 100644
index 000000000..3c744b943
--- /dev/null
+++ b/roms/u-boot/board/timll/devkit3250/devkit3250.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Embest/Timll DevKit3250 board support
+ *
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/emc.h>
+#include <asm/arch/wdt.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
+
+void reset_periph(void)
+{
+	/* This function resets peripherals by triggering RESOUT_N */
+	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+	writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
+	udelay(300);
+
+	writel(0, &wdt->mctrl);
+	clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+
+	/* Such a long delay is needed to initialize SMSC phy */
+	udelay(10000);
+}
+
+int board_early_init_f(void)
+{
+	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+	lpc32xx_i2c_init(1);
+	lpc32xx_i2c_init(2);
+	lpc32xx_ssp_init();
+	lpc32xx_mac_init();
+
+	/*
+	 * nWP may be controlled by GPO19, but unpopulated by default R23
+	 * makes no sense to configure this GPIO level, nWP is always high
+	 */
+	lpc32xx_slc_nand_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params  = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_SYS_FLASH_CFI
+	/* Use 16-bit memory interface for NOR Flash */
+	emc->stat[0].config	= EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
+
+	/* Change the NOR timings to optimum value to get maximum bandwidth */
+	emc->stat[0].waitwen	= EMC_STAT_WAITWEN(1);
+	emc->stat[0].waitoen	= EMC_STAT_WAITOEN(0);
+	emc->stat[0].waitrd	= EMC_STAT_WAITRD(12);
+	emc->stat[0].waitpage	= EMC_STAT_WAITPAGE(12);
+	emc->stat[0].waitwr	= EMC_STAT_WAITWR(5);
+	emc->stat[0].waitturn	= EMC_STAT_WAITTURN(2);
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/timll/devkit3250/devkit3250_spl.c b/roms/u-boot/board/timll/devkit3250/devkit3250_spl.c
new file mode 100644
index 000000000..47af78ae0
--- /dev/null
+++ b/roms/u-boot/board/timll/devkit3250/devkit3250_spl.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Timll DevKit3250 board support, SPL board configuration
+ *
+ * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/emc.h>
+#include <asm/arch-lpc32xx/gpio.h>
+#include <spl.h>
+
+static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+/*
+ * SDRAM K4S561632N-LC60 settings are selected in assumption that
+ * SDRAM clock may be set up to 166 MHz, however at the moment
+ * it is 104 MHz. Most delay values are converted to be a multiple of
+ * base clock, and precise pinned values are not needed here.
+ */
+struct emc_dram_settings dram_64mb = {
+	.cmddelay	= 0x0001C000,
+	.config0	= 0x00005682,
+	.rascas0	= 0x00000302,
+	.rdconfig	= 0x00000011,	/* undocumented but crucial value */
+
+	.trp	= 83333333,
+	.tras	= 23809524,
+	.tsrex	= 12500000,
+	.twr	= 83000000,		/* tWR = tRDL = 2 CLK */
+	.trc	= 15384616,
+	.trfc	= 15384616,
+	.txsr	= 12500000,
+	.trrd	= 1,
+	.tmrd	= 1,
+	.tcdlr	= 0,
+
+	.refresh	= 130000,	/* 800 clock cycles */
+
+	.mode	= 0x00018000,
+	.emode	= 0x02000000,
+};
+
+void spl_board_init(void)
+{
+	/* First of all silence buzzer controlled by GPO_20 */
+	writel((1 << 20), &gpio->p3_outp_clr);
+
+	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+	preloader_console_init();
+
+	ddr_init(&dram_64mb);
+
+	/*
+	 * NAND initialization is done by nand_init(),
+	 * here just enable NAND SLC clocks
+	 */
+	lpc32xx_slc_nand_init();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NAND;
+}
diff --git a/roms/u-boot/board/timll/devkit8000/Kconfig b/roms/u-boot/board/timll/devkit8000/Kconfig
new file mode 100644
index 000000000..3c63ced9a
--- /dev/null
+++ b/roms/u-boot/board/timll/devkit8000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DEVKIT8000
+
+config SYS_BOARD
+	default "devkit8000"
+
+config SYS_VENDOR
+	default "timll"
+
+config SYS_CONFIG_NAME
+	default "devkit8000"
+
+endif
diff --git a/roms/u-boot/board/timll/devkit8000/MAINTAINERS b/roms/u-boot/board/timll/devkit8000/MAINTAINERS
new file mode 100644
index 000000000..c490757d6
--- /dev/null
+++ b/roms/u-boot/board/timll/devkit8000/MAINTAINERS
@@ -0,0 +1,6 @@
+DEVKIT8000 BOARD
+M:	Thomas Weber <weber@corscience.de>
+S:	Maintained
+F:	board/timll/devkit8000/
+F:	include/configs/devkit8000.h
+F:	configs/devkit8000_defconfig
diff --git a/roms/u-boot/board/timll/devkit8000/Makefile b/roms/u-boot/board/timll/devkit8000/Makefile
new file mode 100644
index 000000000..4d681701c
--- /dev/null
+++ b/roms/u-boot/board/timll/devkit8000/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009
+# Frederik Kriewitz <frederik@kriewitz.eu>
+
+obj-y	:= devkit8000.o
diff --git a/roms/u-boot/board/timll/devkit8000/README b/roms/u-boot/board/timll/devkit8000/README
new file mode 100644
index 000000000..609bf51ae
--- /dev/null
+++ b/roms/u-boot/board/timll/devkit8000/README
@@ -0,0 +1,15 @@
+DevKit8000
+==========
+
+The OMAP3 DevKit8000 from Embest/Timll is a clone of the OMAP3 beagle board
+with Ethernet and Touch Screen controller on board.
+
+For more information go to:
+http://www.embedinfo.com/English/Product/devkit8000.asp
+
+There's no real MAC address available.
+If ethaddr is not set, 5 Bytes of the OMAP Die ID will be used.
+
+Build:
+make devkit8000_config
+make
diff --git a/roms/u-boot/board/timll/devkit8000/devkit8000.c b/roms/u-boot/board/timll/devkit8000/devkit8000.c
new file mode 100644
index 000000000..0808ca1a5
--- /dev/null
+++ b/roms/u-boot/board/timll/devkit8000/devkit8000.c
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ */
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <twl4030.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/mach-types.h>
+#include "devkit8000.h"
+#include <asm/gpio.h>
+#ifdef CONFIG_DRIVER_DM9000
+#include <net.h>
+#include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 gpmc_net_config[GPMC_MAX_REG] = {
+	NET_GPMC_CONFIG1,
+	NET_GPMC_CONFIG2,
+	NET_GPMC_CONFIG3,
+	NET_GPMC_CONFIG4,
+	NET_GPMC_CONFIG5,
+	NET_GPMC_CONFIG6,
+	0
+};
+
+static const struct ns16550_plat devkit8000_serial = {
+	.base = OMAP34XX_UART3,
+	.reg_shift = 2,
+	.clock = V_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
+};
+
+U_BOOT_DRVINFO(devkit8000_uart) = {
+	"ns16550_serial",
+	&devkit8000_serial
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/* Configure GPMC registers for DM9000 */
+static void gpmc_dm9000_config(void)
+{
+	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
+		CONFIG_DM9000_BASE, GPMC_SIZE_16M);
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
+#ifdef CONFIG_DRIVER_DM9000
+	uchar enetaddr[6];
+	u32 die_id_0;
+#endif
+
+	twl4030_power_init();
+#ifdef CONFIG_TWL4030_LED
+	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+	/* Configure GPMC registers for DM9000 */
+	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
+			CONFIG_DM9000_BASE, GPMC_SIZE_16M);
+
+	/* Use OMAP DIE_ID as MAC address */
+	if (!eth_env_get_enetaddr("ethaddr", enetaddr)) {
+		printf("ethaddr not set, using Die ID\n");
+		die_id_0 = readl(&id_base->die_id_0);
+		enetaddr[0] = 0x02; /* locally administered */
+		enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
+		enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
+		enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
+		enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
+		enetaddr[5] = (die_id_0 & 0x000000ff);
+		eth_env_set_enetaddr("ethaddr", enetaddr);
+	}
+#endif
+
+	omap_die_id_display();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_DEVKIT8000();
+}
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(struct bd_info *bis)
+{
+	return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_MMC)
+void board_mmc_power_init(void)
+{
+	twl4030_power_mmc_init(0);
+}
+#endif
+
+#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
+/*
+ * Routine: board_eth_init
+ * Description: Setting up the Ethernet hardware.
+ */
+int board_eth_init(struct bd_info *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * Do board specific preparation before SPL
+ * Linux boot
+ */
+void spl_board_prepare_for_linux(void)
+{
+	gpmc_dm9000_config();
+}
+
+/*
+ * devkit8000 specific implementation of spl_start_uboot()
+ *
+ * RETURN
+ * 0 if the button is not pressed
+ * 1 if the button is pressed
+ */
+int spl_start_uboot(void)
+{
+	int val = 0;
+	if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
+		gpio_direction_input(SPL_OS_BOOT_KEY);
+		val = gpio_get_value(SPL_OS_BOOT_KEY);
+		gpio_free(SPL_OS_BOOT_KEY);
+	}
+	return !val;
+}
+#endif
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank.  This
+ * provides the timing values back to the function that configures
+ * the memory.  We have either one or two banks of 128MB DDR.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+	/* General SDRC config */
+	timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+	/* AC timings */
+	timings->ctrla = MICRON_V_ACTIMA_165;
+	timings->ctrlb = MICRON_V_ACTIMB_165;
+
+	timings->mr = MICRON_V_MR_165;
+}
diff --git a/roms/u-boot/board/timll/devkit8000/devkit8000.h b/roms/u-boot/board/timll/devkit8000/devkit8000.h
new file mode 100644
index 000000000..c8d57d167
--- /dev/null
+++ b/roms/u-boot/board/timll/devkit8000/devkit8000.h
@@ -0,0 +1,359 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ */
+#ifndef _DEVKIT8000_H_
+#define _DEVKIT8000_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 DevKit8000",
+	"NAND",
+};
+
+/* GPIO used to select between U-Boot and kernel */
+#define SPL_OS_BOOT_KEY	26
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+#define MUX_DEVKIT8000() \
+ /* SDRC */\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0 NAND*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
+	MUX_VAL(CP(GPMC_NCS6),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS6 DM9000*/\
+	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS7*/\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+ /* DSS */\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /* CAMERA */\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /* Audio Interface */\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /* MMC Slot */\
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+ /* Expansion Header */\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_140*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_141*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_142*/\
+	MUX_VAL(CP(MCBSP3_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_143*/\
+	MUX_VAL(CP(UART2_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_144*/\
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_145*/\
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M4)) /*GPIO_146*/\
+	MUX_VAL(CP(UART2_RX),		(IDIS | PTD | DIS | M4)) /*GPIO_147*/\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*GPIO_148*/\
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+	MUX_VAL(CP(UART1_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*GPIO_151*/\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M1)) /*GPIO_152*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M1)) /*GPIO_153*/\
+	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M1)) /*GPIO_154*/\
+	MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M1)) /*GPIO_155*/\
+	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M4)) /*GPIO_157*/\
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*GPIO_160*/\
+	MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+	MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /* Serial Interface */\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IDIS | PTD | EN  | M4)) /*GPIO_163 - LED2*/\
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTU | EN  | M4)) /*GPIO_164 - LED3*/\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ /* Host USB0 */\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+	MUX_VAL(CP(I2C2_SCL),		(IDIS | PTU | DIS | M4)) /*GPIO_168*/\
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M4)) /*GPIO_183*/\
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | DIS | M0)) /*I2C4_SDA*/\
+	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTD | DIS | M4)) /*GPIO_170*/\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M4)) /*GPIO_171*/\
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M4)) /*GPIO_172*/\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*MCSPI1_SOMI*/\
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | DIS | M0)) /*MCSPI1_CS0*/\
+	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+ /* USB EHCI (port 2) */\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) /*HSUSB2_DATA2*/\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB2_DATA7*/\
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) /*HSUSB2_DATA4*/\
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /*HSUSB2_DATA5*/\
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0)) /*HSUSB2_DATA6*/\
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) /*HSUSB2_DATA3*/\
+ /*Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+	MUX_VAL(CP(SYS_CLKOUT1),	(IDIS | PTD | EN  | M0)) /*SYS_CLKOUT1*/\
+	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | EN  | M4)) /*GPIO_186 - LED1*/\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB1_STP*/\
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | EN  | M3)) /*HSUSB1_CLK*/\
+	MUX_VAL(CP(ETK_D0_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA0*/\
+	MUX_VAL(CP(ETK_D1_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA1*/\
+	MUX_VAL(CP(ETK_D2_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA2*/\
+	MUX_VAL(CP(ETK_D3_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA7*/\
+	MUX_VAL(CP(ETK_D4_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA4*/\
+	MUX_VAL(CP(ETK_D5_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA5*/\
+	MUX_VAL(CP(ETK_D6_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA6*/\
+	MUX_VAL(CP(ETK_D7_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA3*/\
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M3)) /*HSUSB1_DIR*/\
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | DIS | M3)) /*HSUSB1_NXT*/\
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | EN  | M4)) /*GPIO_24*/\
+	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_25*/\
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_26*/\
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_27*/\
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_28*/\
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_29*/\
+	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD1*/\
+	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD2*/\
+	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD3*/\
+	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD4*/\
+	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD5*/\
+	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD6*/\
+	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD7*/\
+	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD8*/\
+	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD9*/\
+	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD10*/\
+	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD11*/\
+	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD12*/\
+	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD13*/\
+	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD14*/\
+	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD15*/\
+	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD16*/\
+	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD17*/\
+	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD18*/\
+	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD19*/\
+	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD20*/\
+	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD21*/\
+	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD22*/\
+	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD23*/\
+	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD24*/\
+	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD25*/\
+	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD26*/\
+	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD27*/\
+	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD28*/\
+	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD29*/\
+	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD30*/\
+	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD31*/\
+	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD32*/\
+	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD33*/\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD34*/\
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD35*/\
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD36*/\
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*D2D_clk26mi*/\
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*D2D_nrespwron*/\
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*D2D_nreswarm */\
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*D2D_arm9nirq */\
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*D2D_spint*/\
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*D2D_frint*/\
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq0*/\
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq1*/\
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq2*/\
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq3*/\
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*D2D_n3gtrst*/\
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtdi*/\
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtdo*/\
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtms*/\
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtck*/\
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*D2D_n3grtck*/\
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*D2D_mstdby*/\
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*D2D_swakeup*/\
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*D2D_idlereq*/\
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*D2D_idleack*/\
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*D2D_mwrite*/\
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*D2D_swrite*/\
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*D2D_mread*/\
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*D2D_sread*/\
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*D2D_mbusflag*/\
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*D2D_sbusflag*/\
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+
+#endif
diff --git a/roms/u-boot/board/topic/zynq/MAINTAINERS b/roms/u-boot/board/topic/zynq/MAINTAINERS
new file mode 100644
index 000000000..d795b304e
--- /dev/null
+++ b/roms/u-boot/board/topic/zynq/MAINTAINERS
@@ -0,0 +1,6 @@
+TOPIC BOARD
+M:	Mike Looijmans <mike.looijmans@topic.nl>
+S:	Maintained
+F:	board/topic/zynq/
+F:	include/configs/topic*.h
+F:	configs/topic_*_defconfig
diff --git a/roms/u-boot/board/topic/zynq/Makefile b/roms/u-boot/board/topic/zynq/Makefile
new file mode 100644
index 000000000..cc100b0f4
--- /dev/null
+++ b/roms/u-boot/board/topic/zynq/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	:= board.o
+obj-y	+= ../../xilinx/common/board.o
+
+# Remove quotes
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
diff --git a/roms/u-boot/board/topic/zynq/board.c b/roms/u-boot/board/topic/zynq/board.c
new file mode 100644
index 000000000..a95c9d1ef
--- /dev/null
+++ b/roms/u-boot/board/topic/zynq/board.c
@@ -0,0 +1 @@
+#include "../../xilinx/zynq/board.c"
diff --git a/roms/u-boot/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/roms/u-boot/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
new file mode 100644
index 000000000..e7cc2c2de
--- /dev/null
+++ b/roms/u-boot/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100800U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00025010U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00026400U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029418U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00027820U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000090U),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000098U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x000000A0U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E9U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000EEU),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000FAU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F3U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000D0U),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000D8U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000E0U),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000E60U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
diff --git a/roms/u-boot/board/topic/zynq/zynq-topic-miami/ps7_regs.txt b/roms/u-boot/board/topic/zynq/zynq-topic-miami/ps7_regs.txt
new file mode 100644
index 000000000..2ad9da697
--- /dev/null
+++ b/roms/u-boot/board/topic/zynq/zynq-topic-miami/ps7_regs.txt
@@ -0,0 +1,61 @@
+0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
+0xf8000700 0x1210     // MIO configuration
+0xf8000704 0x202
+0xf8000708 0x202
+0xf800070c 0x202
+0xf8000710 0x202
+0xf8000714 0x202
+0xf8000718 0x202
+0xf800071c 0x210
+0xf8000720 0x202
+0xf8000724 0x1210
+0xf8000728 0x1210
+0xf800072c 0x1210
+0xf8000730 0x1210
+0xf8000734 0x1210
+0xf8000738 0x1211
+0xf800073c 0x1200
+0xf8000740 0x1210
+0xf8000744 0x1210
+0xf8000748 0x1210
+0xf800074c 0x1210
+0xf8000750 0x1210
+0xf8000754 0x1210
+0xf8000758 0x1210
+0xf800075c 0x1210
+0xf8000760 0x1201
+0xf8000764 0x200
+0xf8000768 0x12e1
+0xf800076c 0x2e0
+0xf8000770 0x304
+0xf8000774 0x305
+0xf8000778 0x304
+0xf800077c 0x305
+0xf8000780 0x304
+0xf8000784 0x304
+0xf8000788 0x304
+0xf800078c 0x304
+0xf8000790 0x305
+0xf8000794 0x304
+0xf8000798 0x304
+0xf800079c 0x304
+0xf80007a0 0x380
+0xf80007a4 0x380
+0xf80007a8 0x380
+0xf80007ac 0x380
+0xf80007b0 0x380
+0xf80007b4 0x380
+0xf80007b8 0x1261
+0xf80007bc 0x1260
+0xf80007c0 0x1261
+0xf80007c4 0x1261
+0xf80007c8 0x1240
+0xf80007cc 0x1240
+0xf80007d0 0x1240
+0xf80007d4 0x1240
+0xf8000830 0x180037
+0xf8000834 0x3a0039
+0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz)
+0xE000D000 0x800238C1 // QSPI config - divide-by-2
+0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
+0xE000D0A0 0x82FF04EB // LQSPI_CFG - QIOREAD mode, Numonyx/Micron
diff --git a/roms/u-boot/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/roms/u-boot/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
new file mode 100644
index 000000000..0f141260f
--- /dev/null
+++ b/roms/u-boot/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x00113220U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x00024000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000C01U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001803U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000C03U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100800U),
+	EMIT_MASKWRITE(0xF8000190, 0x03F03F30U, 0x00100600U),
+	EMIT_MASKWRITE(0xF80001A0, 0x03F03F30U, 0x00101800U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003482CU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00033032U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0002E81FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x0002F81AU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ACU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009AU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000127U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000121U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000010FU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000113U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000ECU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DAU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x1002E080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000E60U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
diff --git a/roms/u-boot/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt b/roms/u-boot/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt
new file mode 100644
index 000000000..db6e64289
--- /dev/null
+++ b/roms/u-boot/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt
@@ -0,0 +1,61 @@
+0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
+0xf8000700 0x202
+0xf8000704 0x202
+0xf8000708 0x202
+0xf800070c 0x202
+0xf8000710 0x202
+0xf8000714 0x202
+0xf8000718 0x202
+0xf800071c 0x200
+0xf8000720 0x202
+0xf8000724 0x202
+0xf8000728 0x202
+0xf800072c 0x202
+0xf8000730 0x202
+0xf8000734 0x202
+0xf8000738 0x12e1
+0xf800073c 0x12e0
+0xf8000740 0x1200
+0xf8000744 0x1200
+0xf8000748 0x1200
+0xf800074c 0x1200
+0xf8000750 0x1200
+0xf8000754 0x1200
+0xf8000758 0x1200
+0xf800075c 0x1200
+0xf8000760 0x1200
+0xf8000764 0x200
+0xf8000768 0x1200
+0xf800076c 0x200
+0xf8000770 0x304
+0xf8000774 0x305
+0xf8000778 0x304
+0xf800077c 0x305
+0xf8000780 0x304
+0xf8000784 0x304
+0xf8000788 0x304
+0xf800078c 0x304
+0xf8000790 0x305
+0xf8000794 0x304
+0xf8000798 0x304
+0xf800079c 0x304
+0xf80007a0 0x380
+0xf80007a4 0x380
+0xf80007a8 0x380
+0xf80007ac 0x380
+0xf80007b0 0x380
+0xf80007b4 0x380
+0xf80007b8 0x1200
+0xf80007bc 0x1200
+0xf80007c0 0x1240
+0xf80007c4 0x1240
+0xf80007c8 0x1240
+0xf80007cc 0x1240
+0xf80007d0 0x1200
+0xf80007d4 0x1200
+0xf8000830 0x380037
+0xf8000834 0x3a0039
+0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz)
+0xE000D000 0x800238C1 // QSPI config - divide-by-2
+0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
+0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash
diff --git a/roms/u-boot/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/roms/u-boot/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
new file mode 100644
index 000000000..717955808
--- /dev/null
+++ b/roms/u-boot/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA240U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00030000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A03U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00200500U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB52U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00025010U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00026400U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029418U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00027820U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000090U),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000098U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x000000A0U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E9U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000EEU),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000FAU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F3U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000D0U),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000D8U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000E0U),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000E60U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
diff --git a/roms/u-boot/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt b/roms/u-boot/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt
new file mode 100644
index 000000000..7b102de37
--- /dev/null
+++ b/roms/u-boot/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt
@@ -0,0 +1,61 @@
+0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz)
+0xf8000700 0x1202     // MIO configuration
+0xf8000704 0x1202
+0xf8000708 0x202
+0xf800070c 0x202
+0xf8000710 0x202
+0xf8000714 0x202
+0xf8000718 0x202
+0xf800071c 0x200
+0xf8000720 0x202
+0xf8000724 0x202
+0xf8000728 0x202
+0xf800072c 0x202
+0xf8000730 0x202
+0xf8000734 0x202
+0xf8000738 0x12e1
+0xf800073c 0x12e0
+0xf8000740 0x1202
+0xf8000744 0x1202
+0xf8000748 0x1202
+0xf800074c 0x1202
+0xf8000750 0x1202
+0xf8000754 0x1202
+0xf8000758 0x1203
+0xf800075c 0x1203
+0xf8000760 0x1203
+0xf8000764 0x203
+0xf8000768 0x1203
+0xf800076c 0x203
+0xf8000770 0x304
+0xf8000774 0x305
+0xf8000778 0x304
+0xf800077c 0x305
+0xf8000780 0x304
+0xf8000784 0x304
+0xf8000788 0x304
+0xf800078c 0x304
+0xf8000790 0x305
+0xf8000794 0x304
+0xf8000798 0x304
+0xf800079c 0x304
+0xf80007a0 0x380
+0xf80007a4 0x380
+0xf80007a8 0x380
+0xf80007ac 0x380
+0xf80007b0 0x380
+0xf80007b4 0x380
+0xf80007b8 0x1200
+0xf80007bc 0x1201
+0xf80007c0 0x1240
+0xf80007c4 0x1240
+0xf80007c8 0x1240
+0xf80007cc 0x1240
+0xf80007d0 0x1280
+0xf80007d4 0x1280
+0xf8000830 0x2f0037
+0xf8000834 0x3a0039
+0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6
+0xE000D000 0x800238C1 // QSPI config - divide-by-2
+0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
+0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash
diff --git a/roms/u-boot/board/toradex/apalis-imx8/Kconfig b/roms/u-boot/board/toradex/apalis-imx8/Kconfig
new file mode 100644
index 000000000..c680d63fa
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-imx8/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_APALIS_IMX8
+
+config SYS_BOARD
+	default "apalis-imx8"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "apalis-imx8"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/apalis-imx8/MAINTAINERS b/roms/u-boot/board/toradex/apalis-imx8/MAINTAINERS
new file mode 100644
index 000000000..7fbd1be10
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-imx8/MAINTAINERS
@@ -0,0 +1,10 @@
+Apalis iMX8
+M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+S:	Maintained
+F:	arch/arm/dts/fsl-imx8-apalis.dts
+F:	arch/arm/dts/fsl-imx8-apalis-u-boot.dtsi
+F:	board/toradex/apalis-imx8/
+F:	configs/apalis-imx8_defconfig
+F:	doc/board/toradex/apalix-imx8.rst
+F:	include/configs/apalis-imx8.h
diff --git a/roms/u-boot/board/toradex/apalis-imx8/Makefile b/roms/u-boot/board/toradex/apalis-imx8/Makefile
new file mode 100644
index 000000000..a8c3eb724
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-imx8/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Toradex
+#
+
+obj-y += apalis-imx8.o
diff --git a/roms/u-boot/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg b/roms/u-boot/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg
new file mode 100644
index 000000000..b8f0f3dc1
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Toradex
+ *
+ * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM EMMC_FASTBOOT 0x400
+/* SoC type IMX8QM */
+SOC_TYPE IMX8QM
+/* Append seco container image */
+APPEND mx8qm-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qm-apalis-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/roms/u-boot/board/toradex/apalis-imx8/apalis-imx8.c b/roms/u-boot/board/toradex/apalis-imx8/apalis-imx8.c
new file mode 100644
index 000000000..04877fcd9
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-imx8/apalis-imx8.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Toradex
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/global_data.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <env.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart1_pads[] = {
+	SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+			  u64 *phys_sdram_1_size,
+			  u64 *phys_sdram_2_start,
+			  u64 *phys_sdram_2_size)
+{
+	u32 is_quadplus = 0, val = 0;
+	sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+	if (scierr == SC_ERR_NONE) {
+		/* QP has one A72 core disabled */
+		is_quadplus = ((val >> 4) & 0x3) != 0x0;
+	}
+
+	*phys_sdram_1_start = PHYS_SDRAM_1;
+	*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+	*phys_sdram_2_start = PHYS_SDRAM_2;
+	if (is_quadplus)
+		/* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */
+		*phys_sdram_2_size = 0x0UL;
+	else
+		*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	sc_err_t err = 0;
+
+	/* Set UART1 clock root to 80 MHz and enable it */
+	err = sc_pm_setup_uart(SC_R_UART_1, rate);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
+static void board_gpio_init(void)
+{
+	/* TODO */
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Model: Toradex Apalis iMX8\n");
+
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	board_gpio_init();
+
+	return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+	/* TODO */
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+/* TODO move to common */
+	env_set("board_name", "Apalis iMX8QM");
+	env_set("board_rev", "v1.0");
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/toradex/apalis-imx8x/Kconfig b/roms/u-boot/board/toradex/apalis-imx8x/Kconfig
new file mode 100644
index 000000000..ee61e0973
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-imx8x/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_APALIS_IMX8X
+
+config SYS_BOARD
+	default "apalis-imx8x"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "apalis-imx8x"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/apalis-imx8x/MAINTAINERS b/roms/u-boot/board/toradex/apalis-imx8x/MAINTAINERS
new file mode 100644
index 000000000..527215444
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-imx8x/MAINTAINERS
@@ -0,0 +1,10 @@
+Apalis iMX8X
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+S:	Maintained
+F:	arch/arm/dts/fsl-imx8x-apalis.dts
+F:	arch/arm/dts/fsl-imx8x-apalis-u-boot.dtsi
+F:	board/toradex/apalis-imx8x/
+F:	configs/apalis-imx8x_defconfig
+F:	doc/board/toradex/apalis-imx8x.rst
+F:	include/configs/apalis-imx8x.h
diff --git a/roms/u-boot/board/toradex/apalis-imx8x/Makefile b/roms/u-boot/board/toradex/apalis-imx8x/Makefile
new file mode 100644
index 000000000..9d6e85b74
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-imx8x/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 Toradex
+#
+
+obj-y += apalis-imx8x.o
diff --git a/roms/u-boot/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg b/roms/u-boot/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg
new file mode 100644
index 000000000..58c62d0a6
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Toradex
+ *
+ * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM EMMC_FASTBOOT 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND mx8qx-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qx-apalis-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/roms/u-boot/board/toradex/apalis-imx8x/apalis-imx8x.c b/roms/u-boot/board/toradex/apalis-imx8x/apalis-imx8x.c
new file mode 100644
index 000000000..ac3bac66a
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-imx8x/apalis-imx8x.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Toradex
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <env.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart1_pads[] = {
+	SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+			  u64 *phys_sdram_1_size,
+			  u64 *phys_sdram_2_start,
+			  u64 *phys_sdram_2_size)
+{
+	u32 is_dualx = 0, val = 0;
+	sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+	if (scierr == SC_ERR_NONE) {
+		/* DX has two A35 cores disabled */
+		is_dualx = (val & 0xf) != 0x0;
+	}
+
+	*phys_sdram_1_start = PHYS_SDRAM_1;
+	if (is_dualx)
+		/* Our DX based SKUs only have 1 GB RAM */
+		*phys_sdram_1_size = SZ_1G;
+	else
+		*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+	*phys_sdram_2_start = PHYS_SDRAM_2;
+	*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate;
+	sc_err_t err = 0;
+
+	/*
+	 * This works around that having only UART3 up the baudrate is 1.2M
+	 * instead of 115.2k. Set UART0 clock root to 80 MHz
+	 */
+	rate = 80000000;
+	err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	/* Set UART3 clock root to 80 MHz and enable it */
+	rate = SC_80MHZ;
+	err = sc_pm_setup_uart(SC_R_UART_1, rate);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_DM_GPIO)
+static void board_gpio_init(void)
+{
+	/* TODO */
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Model: Toradex Apalis iMX8X\n");
+
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	board_gpio_init();
+
+	return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+	/* TODO */
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+/* TODO move to common */
+	env_set("board_name", "Apalis iMX8X");
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/toradex/apalis-tk1/Kconfig b/roms/u-boot/board/toradex/apalis-tk1/Kconfig
new file mode 100644
index 000000000..159b8fb19
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-tk1/Kconfig
@@ -0,0 +1,38 @@
+if TARGET_APALIS_TK1
+
+config SYS_BOARD
+	default "apalis-tk1"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "apalis-tk1"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+config APALIS_TK1_PCIE_EVALBOARD_INIT
+	bool "Apalis Evaluation Board PCIe Initialisation"
+	help
+	  Bring up the Apalis PCIe port with the PCIe switch as found on the
+	  Apalis Evaluation board. Note that by default the PCIe port is also
+	  left disabled in the device tree which needs changing as well for this
+	  to actually work.
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/apalis-tk1/MAINTAINERS b/roms/u-boot/board/toradex/apalis-tk1/MAINTAINERS
new file mode 100644
index 000000000..3c908e119
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-tk1/MAINTAINERS
@@ -0,0 +1,7 @@
+Apalis TK1
+M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
+S:	Maintained
+F:	board/toradex/apalis-tk1/
+F:	include/configs/apalis-tk1.h
+F:	configs/apalis-tk1_defconfig
+F:	arch/arm/dts/tegra124-apalis.dtb
diff --git a/roms/u-boot/board/toradex/apalis-tk1/Makefile b/roms/u-boot/board/toradex/apalis-tk1/Makefile
new file mode 100644
index 000000000..9ef06dd61
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-tk1/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2016 Toradex, Inc.
+# SPDX-License-Identifier:      GPL-2.0+
+
+obj-y	+= as3722_init.o
+obj-y	+= apalis-tk1.o
diff --git a/roms/u-boot/board/toradex/apalis-tk1/apalis-tk1.c b/roms/u-boot/board/toradex/apalis-tk1/apalis-tk1.c
new file mode 100644
index 000000000..b97617cfc
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-tk1/apalis-tk1.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016-2018 Toradex, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <env_internal.h>
+#include <pci_tegra.h>
+#include <linux/delay.h>
+#include <power/as3722.h>
+#include <power/pmic.h>
+
+#include "../common/tdx-common.h"
+#include "pinmux-config-apalis-tk1.h"
+
+#define LAN_DEV_OFF_N	TEGRA_GPIO(O, 6)
+#define LAN_RESET_N	TEGRA_GPIO(S, 2)
+#define FAN_EN		TEGRA_GPIO(DD, 2)
+#define LAN_WAKE_N	TEGRA_GPIO(O, 5)
+#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
+#define PEX_PERST_N	TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
+#define RESET_MOCI_CTRL	TEGRA_GPIO(U, 4)
+#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
+#define VCC_USBH	TEGRA_GPIO(T, 6)
+#define VCC_USBH_V1_0	TEGRA_GPIO(N, 5)
+#define VCC_USBO1	TEGRA_GPIO(T, 5)
+#define VCC_USBO1_V1_0	TEGRA_GPIO(N, 4)
+
+int arch_misc_init(void)
+{
+	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
+	    NVBOOTTYPE_RECOVERY)
+		printf("USB recovery mode\n");
+
+	/* PCB Version Indication: V1.2 and later have GPIO_PV0 wired to GND */
+	gpio_request(TEGRA_GPIO(V, 0), "PCB Version Indication");
+	gpio_direction_input(TEGRA_GPIO(V, 0));
+	if (gpio_get_value(TEGRA_GPIO(V, 0))) {
+		/*
+		 * if using the default device tree for new V1.2 and later HW,
+		 * use version for older V1.0 and V1.1 HW
+		 */
+		char *fdt_env = env_get("fdt_module");
+
+		if (fdt_env && !strcmp(FDT_MODULE, fdt_env)) {
+			env_set("fdt_module", FDT_MODULE_V1_0);
+			printf("patching fdt_module to " FDT_MODULE_V1_0
+			       " for older V1.0 and V1.1 HW\n");
+#ifndef CONFIG_ENV_IS_NOWHERE
+			env_save();
+#endif
+		}
+
+		/* activate USB power enable GPIOs */
+		gpio_request(VCC_USBH_V1_0, "VCC_USBH");
+		gpio_direction_output(VCC_USBH_V1_0, 1);
+		gpio_request(VCC_USBO1_V1_0, "VCC_USBO1");
+		gpio_direction_output(VCC_USBO1_V1_0, 1);
+	} else {
+		/* activate USB power enable GPIOs */
+		gpio_request(VCC_USBH, "VCC_USBH");
+		gpio_direction_output(VCC_USBH, 1);
+		gpio_request(VCC_USBO1, "VCC_USBO1");
+		gpio_direction_output(VCC_USBO1, 1);
+	}
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Model: Toradex Apalis TK1 2GB\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_clear_tristate_input_clamping();
+
+	gpio_config_table(apalis_tk1_gpio_inits,
+			  ARRAY_SIZE(apalis_tk1_gpio_inits));
+
+	pinmux_config_pingrp_table(apalis_tk1_pingrps,
+				   ARRAY_SIZE(apalis_tk1_pingrps));
+
+	pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
+				   ARRAY_SIZE(apalis_tk1_drvgrps));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+/* TODO: Convert to driver model */
+static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
+{
+	int err;
+
+	if (sd > 6)
+		return -EINVAL;
+
+	err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
+	if (err) {
+		pr_err("failed to update SD control register: %d", err);
+		return err;
+	}
+
+	return 0;
+}
+
+/* TODO: Convert to driver model */
+static int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo)
+{
+	int err;
+	u8 ctrl_reg = AS3722_LDO_CONTROL0;
+
+	if (ldo > 11)
+		return -EINVAL;
+
+	if (ldo > 7) {
+		ctrl_reg = AS3722_LDO_CONTROL1;
+		ldo -= 8;
+	}
+
+	err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo);
+	if (err) {
+		pr_err("failed to update LDO control register: %d", err);
+		return err;
+	}
+
+	return 0;
+}
+
+int tegra_pcie_board_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_PMIC,
+					  DM_DRIVER_GET(pmic_as3722), &dev);
+	if (ret) {
+		pr_err("failed to find AS3722 PMIC: %d\n", ret);
+		return ret;
+	}
+
+	ret = as3722_sd_enable(dev, 4);
+	if (ret < 0) {
+		pr_err("failed to enable SD4: %d\n", ret);
+		return ret;
+	}
+
+	ret = as3722_sd_set_voltage(dev, 4, 0x24);
+	if (ret < 0) {
+		pr_err("failed to set SD4 voltage: %d\n", ret);
+		return ret;
+	}
+
+	gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N");
+	gpio_request(LAN_RESET_N, "LAN_RESET_N");
+	gpio_request(LAN_WAKE_N, "LAN_WAKE_N");
+
+#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
+	gpio_request(PEX_PERST_N, "PEX_PERST_N");
+	gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
+#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
+
+	return 0;
+}
+
+void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
+{
+	int index = tegra_pcie_port_index_of_port(port);
+
+	if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */
+		struct udevice *dev;
+		int ret;
+
+		ret = uclass_get_device_by_driver(UCLASS_PMIC,
+						  DM_DRIVER_GET(pmic_as3722),
+						  &dev);
+		if (ret) {
+			debug("%s: Failed to find PMIC\n", __func__);
+			return;
+		}
+
+		/* Reset I210 Gigabit Ethernet Controller */
+		gpio_direction_output(LAN_RESET_N, 0);
+
+		/*
+		 * Make sure we don't get any back feeding from DEV_OFF_N resp.
+		 * LAN_WAKE_N
+		 */
+		gpio_direction_output(LAN_DEV_OFF_N, 0);
+		gpio_direction_output(LAN_WAKE_N, 0);
+
+		/* Make sure LDO9 and LDO10 are initially enabled @ 0V */
+		ret = as3722_ldo_enable(dev, 9);
+		if (ret < 0) {
+			pr_err("failed to enable LDO9: %d\n", ret);
+			return;
+		}
+		ret = as3722_ldo_enable(dev, 10);
+		if (ret < 0) {
+			pr_err("failed to enable LDO10: %d\n", ret);
+			return;
+		}
+		ret = as3722_ldo_set_voltage(dev, 9, 0x80);
+		if (ret < 0) {
+			pr_err("failed to set LDO9 voltage: %d\n", ret);
+			return;
+		}
+		ret = as3722_ldo_set_voltage(dev, 10, 0x80);
+		if (ret < 0) {
+			pr_err("failed to set LDO10 voltage: %d\n", ret);
+			return;
+		}
+
+		/* Make sure controller gets enabled by disabling DEV_OFF_N */
+		gpio_set_value(LAN_DEV_OFF_N, 1);
+
+		/*
+		 * Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype
+		 * V1.0A and sample V1.0B and newer modules
+		 */
+		ret = as3722_ldo_set_voltage(dev, 9, 0xff);
+		if (ret < 0) {
+			pr_err("failed to set LDO9 voltage: %d\n", ret);
+			return;
+		}
+		ret = as3722_ldo_set_voltage(dev, 10, 0xff);
+		if (ret < 0) {
+			pr_err("failed to set LDO10 voltage: %d\n", ret);
+			return;
+		}
+
+		/*
+		 * Must be asserted for 100 ms after power and clocks are stable
+		 */
+		mdelay(100);
+
+		gpio_set_value(LAN_RESET_N, 1);
+	} else if (index == 0) { /* Apalis PCIe */
+#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
+		/*
+		 * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis
+		 * Evaluation Board
+		 */
+		gpio_direction_output(PEX_PERST_N, 0);
+		gpio_direction_output(RESET_MOCI_CTRL, 0);
+
+		/*
+		 * Must be asserted for 100 ms after power and clocks are stable
+		 */
+		mdelay(100);
+
+		gpio_set_value(PEX_PERST_N, 1);
+		/*
+		 * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed
+		 * Until 900 us After PEX_PERST# De-assertion
+		 */
+		mdelay(1);
+		gpio_set_value(RESET_MOCI_CTRL, 1);
+#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
+	}
+}
+#endif /* CONFIG_PCI_TEGRA */
+
+/*
+ * Enable/start PWM CPU fan
+ */
+void start_cpu_fan(void)
+{
+	gpio_request(FAN_EN, "FAN_EN");
+	gpio_direction_output(FAN_EN, 1);
+}
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+	gpio_request(TEGRA_GPIO(BB, 5), "BL_ON");
+	gpio_direction_output(TEGRA_GPIO(BB, 5), 0);
+}
diff --git a/roms/u-boot/board/toradex/apalis-tk1/as3722_init.c b/roms/u-boot/board/toradex/apalis-tk1/as3722_init.c
new file mode 100644
index 000000000..68169f554
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-tk1/as3722_init.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2012-2016 Toradex, Inc.
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+#include "as3722_init.h"
+
+/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(addr, &reg->cmd_addr0);
+	writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(data, &reg->cmd_data1);
+	writel(config, &reg->cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+	debug("%s entry\n", __func__);
+
+#ifdef AS3722_SD1VOLTAGE_DATA
+	/* Set up VDD_CORE, for boards where OTP is incorrect*/
+	debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
+	/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+#endif
+
+	/*
+	 * Make sure all non-fused regulators are down.
+	 * That way we're in known state after software reboot from linux
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES);
+	udelay(10 * 1000);
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES);
+	udelay(10 * 1000);
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES);
+	udelay(10 * 1000);
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES);
+	udelay(10 * 1000);
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES);
+	udelay(10 * 1000);
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES);
+	udelay(10 * 1000);
+
+	debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
+	/*
+	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
+	/*
+	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
+	/*
+	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.2V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
+	/*
+	 * Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to value closest to 3.3V, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
+	/*
+	 * Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to bypass 3.3V straight thru, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+}
diff --git a/roms/u-boot/board/toradex/apalis-tk1/as3722_init.h b/roms/u-boot/board/toradex/apalis-tk1/as3722_init.h
new file mode 100644
index 000000000..99836de96
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-tk1/as3722_init.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012-2016 Toradex, Inc.
+ */
+
+/* AS3722-PMIC-specific early init regs */
+
+#define AS3722_I2C_ADDR		0x80
+
+#define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
+#define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
+#define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
+#define AS3722_SDCONTROL_REG	0x4D
+
+#define AS3722_LDO1VOLTAGE_REG	0x11	/* VDD_SDMMC1 */
+#define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
+#define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC3 */
+#define AS3722_LDCONTROL_REG	0x4E
+
+#define AS3722_SD0VOLTAGE_DATA	(0x3C00 | AS3722_SD0VOLTAGE_REG)
+#define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD1VOLTAGE_DATA	(0x3200 | AS3722_SD1VOLTAGE_REG)
+#define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
+#define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
+
+#define AS3722_LDO1CONTROL_DATA	(0x0200 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO1VOLTAGE_DATA	(0x7F00 | AS3722_LDO1VOLTAGE_REG)
+
+#define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
+
+#define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
+
+#define I2C_SEND_2_BYTES	0x0A02
+
+void pmic_enable_cpu_vdd(void);
diff --git a/roms/u-boot/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h b/roms/u-boot/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
new file mode 100644
index 000000000..6778a41e0
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
@@ -0,0 +1,285 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016-2019, Toradex, Inc.
+ */
+
+#ifndef _PINMUX_CONFIG_APALIS_TK1_H_
+#define _PINMUX_CONFIG_APALIS_TK1_H_
+
+#define GPIO_INIT(_port, _gpio, _init)			\
+	{						\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
+		.init	= TEGRA_GPIO_INIT_##_init,	\
+	}
+
+static const struct tegra_gpio_config apalis_tk1_gpio_inits[] = {
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    1,   IN),
+	GPIO_INIT(B,    1,   IN),
+	GPIO_INIT(C,    0,   OUT0),
+	GPIO_INIT(I,    5,   IN),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(J,    2,   IN),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(N,    2,   OUT1),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(O,    5,   IN),
+	GPIO_INIT(Q,    0,   OUT0), /* Shift_CTRL_OE[0] */
+	GPIO_INIT(Q,    1,   OUT0), /* Shift_CTRL_OE[1] */
+	GPIO_INIT(Q,    2,   OUT0), /* Shift_CTRL_OE[2] */
+	GPIO_INIT(Q,    4,   OUT0), /* Shift_CTRL_OE[4] */
+	GPIO_INIT(Q,    5,   OUT1), /* Shift_CTRL_Dir_Out[0] */
+	GPIO_INIT(Q,    6,   OUT1), /* Shift_CTRL_Dir_Out[1] */
+	GPIO_INIT(Q,    7,   OUT1), /* Shift_CTRL_Dir_Out[2] */
+	GPIO_INIT(R,    0,   OUT0), /* Shift_CTRL_Dir_In[0] */
+	GPIO_INIT(R,    1,   OUT0), /* Shift_CTRL_Dir_In[1] */
+	GPIO_INIT(R,    2,   OUT0), /* Shift_CTRL_OE[3] */
+	GPIO_INIT(S,    3,   OUT0), /* Shift_CTRL_Dir_In[2] */
+	GPIO_INIT(U,    4,   OUT0), /* RESET_MOCI_CTRL */
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(W,    3,   IN),
+	GPIO_INIT(W,    5,   IN),
+	GPIO_INIT(BB,   0,  IN),
+	GPIO_INIT(BB,   3,  OUT0),
+	GPIO_INIT(BB,   4,  IN),
+	GPIO_INIT(BB,   5,  OUT1),
+	GPIO_INIT(BB,   6,  OUT0),
+	GPIO_INIT(CC,   5,  IN),
+	GPIO_INIT(DD,   3,  IN),
+	GPIO_INIT(EE,   3,  IN),
+	GPIO_INIT(EE,   5,  IN),
+	GPIO_INIT(FF,   1,  IN),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+static const struct pmux_pingrp_config apalis_tk1_pingrps[] = {
+	/*     pingrp,                 mux,          pull,   tri,      e_input, od,      rcv_sel */
+	PINCFG(CLK_32K_OUT_PA0,        SOC,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_CTS_N_PA1,        GMI,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_FS_PA2,            HDA,          NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_SCLK_PA3,          HDA,          NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_DIN_PA4,           HDA,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_DOUT_PA5,          HDA,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_PA6,         SDMMC3,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CMD_PA7,         SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PB0,                    UARTD,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PB1,                    RSVD2,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT3_PB4,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT2_PB5,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT1_PB6,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT0_PB7,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_RTS_N_PC0,        GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_TXD_PC2,          IRDA,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_RXD_PC3,          IRDA,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GEN1_I2C_SCL_PC4,       I2C1,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN1_I2C_SDA_PC5,       I2C1,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PC7,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG0,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG1,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG2,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG3,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG4,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG5,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG6,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG7,                    SPI4,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH0,                    PWM0,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH1,                    PWM1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH2,                    PWM2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH3,                    PWM3,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH4,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH5,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH6,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH7,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI0,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI1,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI2,                    RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI3,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI4,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI5,                    RSVD2,        UP,     TRISTATE, INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PI6,                    RSVD1,        UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI7,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ0,                    RSVD1,        UP,     TRISTATE, INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PJ2,                    RSVD1,        UP,     TRISTATE, INPUT,   ENABLE,  DEFAULT),
+	PINCFG(UART2_CTS_N_PJ5,        UARTB,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART2_RTS_N_PJ6,        UARTB,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ7,                    UARTD,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK0,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK1,                    RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK2,                    RSVD1,        UP,     TRISTATE, INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PK3,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK4,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_OUT_PK5,          SPDIF,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_IN_PK6,           SPDIF,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PK7,                    RSVD2,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP1_FS_PN0,            RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_DIN_PN1,           RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_DOUT_PN2,          SATA,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_SCLK_PN3,          RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN0_PN4,       RSVD2,        NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(USB_VBUS_EN1_PN5,       RSVD2,        NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(HDMI_INT_PN7,           RSVD1,        DOWN,   TRISTATE, INPUT,   DEFAULT, NORMAL),
+	PINCFG(ULPI_DATA7_PO0,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA0_PO1,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA1_PO2,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA2_PO3,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA3_PO4,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA4_PO5,         ULPI,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA5_PO6,         ULPI,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA6_PO7,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_FS_PP0,            I2S2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_DIN_PP1,           I2S2,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP3_DOUT_PP2,          I2S2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_SCLK_PP3,          I2S2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_FS_PP4,            RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DIN_PP5,           RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DOUT_PP6,          RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_SCLK_PP7,          RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL0_PQ0,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL1_PQ1,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL2_PQ2,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL3_PQ3,            KBC,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL4_PQ4,            KBC,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL5_PQ5,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL6_PQ6,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL7_PQ7,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW0_PR0,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW1_PR1,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW2_PR2,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW3_PR3,            KBC,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW4_PR4,            RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW5_PR5,            RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW6_PR6,            KBC,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW7_PR7,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW8_PS0,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW9_PS1,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW10_PS2,           RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW11_PS3,           RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW12_PS4,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW13_PS5,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW14_PS6,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW15_PS7,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW16_PT0,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW17_PT1,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GEN2_I2C_SCL_PT5,       RSVD2,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(GEN2_I2C_SDA_PT6,       RSVD2,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(SDMMC4_CMD_PT7,         SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU0,                    UARTA,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU1,                    UARTA,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU2,                    UARTA,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU3,                    UARTA,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU4,                    GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU5,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU6,                    PWM3,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PV0,                    RSVD1,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PV1,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CD_N_PV2,        RSVD3,        UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_WP_N_PV3,        SDMMC1,       UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DDC_SCL_PV4,            I2C4,         NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+	PINCFG(DDC_SDA_PV5,            I2C4,         NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+	PINCFG(GPIO_W2_AUD_PW2,        SPI2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_W3_AUD_PW3,        SPI6,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_PW4,          EXTPERIPH1,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK2_OUT_PW5,           RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_TXD_PW6,          UARTC,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART3_RXD_PW7,          UARTC,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DVFS_PWM_PX0,           CLDVFS,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X1_AUD_PX1,        RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DVFS_CLK_PX2,           CLDVFS,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X3_AUD_PX3,        RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X4_AUD_PX4,        SPI2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X5_AUD_PX5,        SPI2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X6_AUD_PX6,        SPI2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X7_AUD_PX7,        SPI2,         NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_CLK_PY0,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DIR_PY1,           SPI1,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_NXT_PY2,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_STP_PY3,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT3_PY4,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT2_PY5,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT1_PY6,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT0_PY7,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CLK_PZ0,         SDMMC1,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CMD_PZ1,         SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PWR_I2C_SCL_PZ6,        I2CPWR,       NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PWR_I2C_SDA_PZ7,        I2CPWR,       NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_DAT0_PAA0,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT1_PAA1,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT2_PAA2,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT3_PAA3,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT4_PAA4,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT5_PAA5,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT6_PAA6,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT7_PAA7,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PBB0,                   VGP6,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CAM_I2C_SCL_PBB1,       I2C3,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(CAM_I2C_SDA_PBB2,       I2C3,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PBB3,                   VGP3,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB4,                   VGP4,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PBB5,                   VGP5,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB6,                   RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB7,                   RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CAM_MCLK_PCC0,          VI_ALT3,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PCC1,                   RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PCC2,                   RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_CLK_PCC4,        SDMMC4,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK2_REQ_PCC5,          RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_RST_N_PDD1,      RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_CLKREQ_N_PDD2,   RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_WAKE_N_PDD3,        RSVD2,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_RST_N_PDD5,      RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_CLKREQ_N_PDD6,   RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK3_OUT_PEE0,          EXTPERIPH3,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK3_REQ_PEE1,          RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_REQ_PEE2,     RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(HDMI_CEC_PEE3,          CEC,          NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	/*
+	 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka not
+	 * tristated and input driver enabled as well as it features some magic
+	 * properties even though the external loopback is disabled and the internal
+	 * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
+	 * being set to 0xfffd according to the TRM!
+	 */
+	PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_LB_IN_PEE5,  RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DP_HPD_PFF0,            DP,           NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN2_PFF1,      RSVD2,        NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(PFF2,                   RSVD2,        NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(CORE_PWR_REQ,           PWRON,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CPU_PWR_REQ,            CPU,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PWR_INT_N,              PMI,          UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(RESET_OUT_N,            RESET_OUT_N,  NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(OWR,                    RSVD2,        NORMAL, TRISTATE, OUTPUT,  DEFAULT, NORMAL),
+	PINCFG(CLK_32K_IN,             CLK,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(JTAG_RTCK,              RTCK,         UP,     NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{						\
+		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
+		.slwf   = _slwf,			\
+		.slwr   = _slwr,			\
+		.drvup  = _drvup,			\
+		.drvdn  = _drvdn,			\
+		.lpmd   = PMUX_LPMD_##_lpmd,		\
+		.schmt  = PMUX_SCHMT_##_schmt,		\
+		.hsm    = PMUX_HSM_##_hsm,		\
+	}
+
+static const struct pmux_drvgrp_config apalis_tk1_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_APALIS_TK1_H */
diff --git a/roms/u-boot/board/toradex/apalis_imx6/Kconfig b/roms/u-boot/board/toradex/apalis_imx6/Kconfig
new file mode 100644
index 000000000..14f8c10c6
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_imx6/Kconfig
@@ -0,0 +1,55 @@
+if TARGET_APALIS_IMX6
+
+config SYS_BOARD
+	default "apalis_imx6"
+
+config SYS_CONFIG_NAME
+	default "apalis_imx6"
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_VENDOR
+	default "toradex"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+config TDX_CMD_IMX_MFGR
+	bool "Enable factory testing commands for Toradex iMX 6 modules"
+	help
+	  This adds the commands
+	    pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
+	  If executed on already fused modules it doesn't change any fuse setting.
+	default y
+
+config TDX_APALIS_IMX6_V1_0
+	bool "Apalis iMX6 V1.0 HW"
+	help
+	  Apalis iMX6 V1.0 HW has a different pinout for the UART.
+	    The UARTs must be used in DCE mode, RTS/CTS are swapped and
+	    thus unusable on standard carrier boards.
+	    This option configures DCE mode unconditionally. Whithout this
+	    option the config block stating V1.0 HW selects DCE mode,
+	    otherwise the UARTs are configuered in DTE mode.
+	default n
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/apalis_imx6/MAINTAINERS b/roms/u-boot/board/toradex/apalis_imx6/MAINTAINERS
new file mode 100644
index 000000000..fde4d92dc
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_imx6/MAINTAINERS
@@ -0,0 +1,9 @@
+Apalis iMX6
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+W:      https://www.toradex.com/community
+S:	Maintained
+F:	board/toradex/apalis_imx6/
+F:	include/configs/apalis_imx6.h
+F:	configs/apalis_imx6_defconfig
+F:	arch/arm/dts/imx6-apalis.dts
diff --git a/roms/u-boot/board/toradex/apalis_imx6/Makefile b/roms/u-boot/board/toradex/apalis_imx6/Makefile
new file mode 100644
index 000000000..128f1794d
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_imx6/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2012-2014 Toradex, Inc.
+# SPDX-License-Identifier:      GPL-2.0+
+
+obj-y  := apalis_imx6.o do_fuse.o
+obj-$(CONFIG_TDX_CMD_IMX_MFGR)  += pf0100.o
diff --git a/roms/u-boot/board/toradex/apalis_imx6/apalis_imx6.c b/roms/u-boot/board/toradex/apalis_imx6/apalis_imx6.c
new file mode 100644
index 000000000..74060daad
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_imx6/apalis_imx6.c
@@ -0,0 +1,1156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ * Copyright (C) 2014-2019, Toradex AG
+ * copied from nitrogen6x
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <image.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+#include <ahci.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/bootm.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
+#include <dm/device-internal.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <dwc_ahsata.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
+#include <imx_thermal.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include "../common/tdx-cfg-block.h"
+#ifdef CONFIG_TDX_CMD_IMX_MFGR
+#include "pf0100.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |		\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_SRE_SLOW)
+
+#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+#define TRISTATE	(PAD_CTL_HYS | PAD_CTL_SPEED_MED)
+
+#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
+
+#define APALIS_IMX6_SATA_INIT_RETRIES	10
+
+int dram_init(void)
+{
+	/* use the DDR controllers configured size */
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    (ulong)imx_ddr_size());
+
+	return 0;
+}
+
+/* Apalis UART1 */
+iomux_v3_cfg_t const uart1_pads_dce[] = {
+	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+iomux_v3_cfg_t const uart1_pads_dte[] = {
+	MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
+/* Apalis MMC1 */
+iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+#	define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
+};
+
+/* Apalis SD1 */
+iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+#	define GPIO_SD_CD IMX_GPIO_NR(6, 14)
+};
+
+/* eMMC */
+iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
+};
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	int tmp;
+
+	switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
+	case PHY_ID_KSZ9131:
+		/* read rxc dll control - devaddr = 0x02, register = 0x4c */
+		tmp = ksz9031_phy_extended_read(phydev, 0x02,
+					   MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC);
+		/* disable rxdll bypass (enable 2ns skew delay on RXC) */
+		tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+		/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   tmp);
+		/* read txc dll control - devaddr = 0x02, register = 0x4d */
+		tmp = ksz9031_phy_extended_read(phydev, 0x02,
+					   MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC);
+		/* disable rxdll bypass (enable 2ns skew delay on TXC) */
+		tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+		/* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   tmp);
+
+		/* control data pad skew - devaddr = 0x02, register = 0x04 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x007d);
+		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x7777);
+		/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0xdddd);
+		/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0007);
+		break;
+	case PHY_ID_KSZ9031:
+	default:
+		/* control data pad skew - devaddr = 0x02, register = 0x04 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x03FF);
+		break;
+	}
+
+	return 0;
+}
+
+iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* KSZ9031 PHY Reset */
+	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL) |
+						  MUX_MODE_SION,
+#	define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
+};
+
+/* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
+iomux_v3_cfg_t const gpio_pads[] = {
+	/* Apalis GPIO1 - GPIO8 */
+	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D5__GPIO2_IO05	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D7__GPIO2_IO07	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLDOWN) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_6__GPIO1_IO06	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+};
+
+static void setup_iomux_gpio(void)
+{
+	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+}
+
+iomux_v3_cfg_t const usb_pads[] = {
+	/* USBH_EN */
+	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
+#	define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
+	/* USB_VBUS_DET */
+	MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#	define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
+	/* USBO1_ID */
+	MX6_PAD_ENET_RX_ER__USB_OTG_ID	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* USBO1_EN */
+	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
+#	define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
+};
+
+/*
+ * UARTs are used in DTE mode, switch the mode on all UARTs before
+ * any pinmuxing connects a (DCE) output to a transceiver output.
+ */
+#define UCR3		0x88	/* FIFO Control Register */
+#define UCR3_RI		BIT(8)	/* RIDELT DTE mode */
+#define UCR3_DCD	BIT(9)	/* DCDDELT DTE mode */
+#define UFCR		0x90	/* FIFO Control Register */
+#define UFCR_DCEDTE	BIT(6)	/* DCE=0 */
+
+static void setup_dtemode_uart(void)
+{
+	setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
+	setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
+	setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
+	setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
+
+	clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
+}
+static void setup_dcemode_uart(void)
+{
+	clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
+	clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
+	clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
+	clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
+}
+
+static void setup_iomux_dte_uart(void)
+{
+	setup_dtemode_uart();
+	imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
+					 ARRAY_SIZE(uart1_pads_dte));
+}
+static void setup_iomux_dce_uart(void)
+{
+	setup_dcemode_uart();
+	imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
+					 ARRAY_SIZE(uart1_pads_dce));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
+/* use the following sequence: eMMC, MMC1, SD1 */
+struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC1_BASE_ADDR},
+	{USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = true; /* default: assume inserted */
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		gpio_request(GPIO_MMC_CD, "MMC_CD");
+		gpio_direction_input(GPIO_MMC_CD);
+		ret = !gpio_get_value(GPIO_MMC_CD);
+		break;
+	case USDHC2_BASE_ADDR:
+		gpio_request(GPIO_MMC_CD, "SD_CD");
+		gpio_direction_input(GPIO_SD_CD);
+		ret = !gpio_get_value(GPIO_SD_CD);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned reg = readl(&psrc->sbmr1) >> 11;
+	/*
+	 * Upon reading BOOT_CFG register the following map is done:
+	 * Bit 11 and 12 of BOOT_CFG register can determine the current
+	 * mmc port
+	 * 0x1                  SD1
+	 * 0x2                  SD2
+	 * 0x3                  SD4
+	 */
+
+	switch (reg & 0x3) {
+	case 0x0:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x1:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x2:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	default:
+		puts("MMC boot device not available");
+	}
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const pwr_intb_pads[] = {
+	/*
+	 * the bootrom sets the iomux to vselect, potentially connecting
+	 * two outputs. Set this back to GPIO
+	 */
+	MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+	/* Backlight on RGB connector: J15 */
+	MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+				       MUX_MODE_SION,
+#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
+	/* additional CPU pin on BKL_PWM, keep in tristate */
+	MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
+	/* Backlight PWM, used as GPIO in U-Boot */
+	MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+				       MUX_MODE_SION,
+#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
+	/* buffer output enable 0: buffer enabled */
+	MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
+#define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
+	/* PSAVE# integrated VDAC */
+	MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+				       MUX_MODE_SION,
+#define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+	MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)
+				IOMUXC_BASE_ADDR;
+	u32 reg = readl(&iomux->gpr[2]);
+	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+	writel(reg, &iomux->gpr[2]);
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+	gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
+}
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+	imx_iomux_v3_setup_multiple_pads(
+		rgb_pads,
+		ARRAY_SIZE(rgb_pads));
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+	gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
+}
+
+static int detect_default(struct display_info_t const *dev)
+{
+	(void) dev;
+	return 1;
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.di	= 1,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_default,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "vga-rgb",
+		.refresh        = 60,
+		.xres           = 640,
+		.yres           = 480,
+		.pixclock       = 33000,
+		.left_margin    = 48,
+		.right_margin   = 16,
+		.upper_margin   = 31,
+		.lower_margin   = 11,
+		.hsync_len      = 96,
+		.vsync_len      = 2,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.di	= 1,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "wvga-rgb",
+		.refresh        = 60,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 25000,
+		.left_margin    = 40,
+		.right_margin   = 88,
+		.upper_margin   = 33,
+		.lower_margin   = 10,
+		.hsync_len      = 128,
+		.vsync_len      = 2,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "wsvga-lvds",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 600,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+	/* Turn on LDB0,IPU,IPU DI0 clocks */
+	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+	      |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	     |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+	     |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+	     |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+	     |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+			|IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+
+	/* backlight unconditionally on for now */
+	imx_iomux_v3_setup_multiple_pads(backlight_pads,
+					 ARRAY_SIZE(backlight_pads));
+	/* use 0 for EDT 7", use 1 for LG fullHD panel */
+	gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
+	gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
+	gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+	gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+}
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
+	gpio_direction_output(RGB_BACKLIGHT_GP, 0);
+}
+#endif /* defined(CONFIG_VIDEO_IPUV3) */
+
+int board_early_init_f(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
+					 ARRAY_SIZE(pwr_intb_pads));
+#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
+	setup_iomux_dte_uart();
+#else
+	setup_iomux_dce_uart();
+#endif
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+
+#ifdef CONFIG_TDX_CMD_IMX_MFGR
+	(void) pmic_init();
+#endif
+
+#ifdef CONFIG_SATA
+	setup_sata();
+#endif
+
+	setup_iomux_gpio();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if defined(CONFIG_REVISION_TAG) && \
+    defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+	char env_str[256];
+	u32 rev;
+
+	rev = get_board_rev();
+	snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
+	env_set("board_rev", env_str);
+
+#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
+	if ((rev & 0xfff0) == 0x0100) {
+		char *fdt_env;
+
+		/* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
+		setup_iomux_dce_uart();
+
+		/* if using the default device tree, use version for V1.0 HW */
+		fdt_env = env_get("fdt_file");
+		if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
+			env_set("fdt_file", FDT_FILE_V1_0);
+			printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
+#ifndef CONFIG_ENV_IS_NOWHERE
+			env_save();
+#endif
+		}
+	}
+#endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
+#endif /* CONFIG_REVISION_TAG */
+
+#ifdef CONFIG_CMD_USB_SDP
+	if (is_boot_from_usb()) {
+		printf("Serial Downloader recovery mode, using sdp command\n");
+		env_set("bootdelay", "0");
+		env_set("bootcmd", "sdp 0");
+	}
+#endif /* CONFIG_CMD_USB_SDP */
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+int checkboard(void)
+{
+	char it[] = " IT";
+	int minc, maxc;
+
+	switch (get_cpu_temp_grade(&minc, &maxc)) {
+	case TEMP_AUTOMOTIVE:
+	case TEMP_INDUSTRIAL:
+		break;
+	case TEMP_EXTCOMMERCIAL:
+	default:
+		it[0] = 0;
+	};
+	printf("Model: Toradex Apalis iMX6 %s %s%s\n",
+	       is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
+	       (gd->ram_size == 0x80000000) ? "2GB" :
+	       (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4-bit bus width */
+	{"mmc",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{"sd",	MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{NULL,	0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+/* TODO, use external pmic, for now always ldo_enable */
+void ldo_mode_set(int ldo_bypass)
+{
+	return;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <linux/libfdt.h>
+#include "asm/arch/mx6q-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+static int mx6_com_dcd_table[] = {
+/* ddr-setup.cfg */
+MX6_IOM_DRAM_SDQS0, 0x00000030,
+MX6_IOM_DRAM_SDQS1, 0x00000030,
+MX6_IOM_DRAM_SDQS2, 0x00000030,
+MX6_IOM_DRAM_SDQS3, 0x00000030,
+MX6_IOM_DRAM_SDQS4, 0x00000030,
+MX6_IOM_DRAM_SDQS5, 0x00000030,
+MX6_IOM_DRAM_SDQS6, 0x00000030,
+MX6_IOM_DRAM_SDQS7, 0x00000030,
+
+MX6_IOM_GRP_B0DS, 0x00000030,
+MX6_IOM_GRP_B1DS, 0x00000030,
+MX6_IOM_GRP_B2DS, 0x00000030,
+MX6_IOM_GRP_B3DS, 0x00000030,
+MX6_IOM_GRP_B4DS, 0x00000030,
+MX6_IOM_GRP_B5DS, 0x00000030,
+MX6_IOM_GRP_B6DS, 0x00000030,
+MX6_IOM_GRP_B7DS, 0x00000030,
+MX6_IOM_GRP_ADDDS, 0x00000030,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_CTLDS, 0x00000030,
+
+MX6_IOM_DRAM_DQM0, 0x00020030,
+MX6_IOM_DRAM_DQM1, 0x00020030,
+MX6_IOM_DRAM_DQM2, 0x00020030,
+MX6_IOM_DRAM_DQM3, 0x00020030,
+MX6_IOM_DRAM_DQM4, 0x00020030,
+MX6_IOM_DRAM_DQM5, 0x00020030,
+MX6_IOM_DRAM_DQM6, 0x00020030,
+MX6_IOM_DRAM_DQM7, 0x00020030,
+
+MX6_IOM_DRAM_CAS, 0x00020030,
+MX6_IOM_DRAM_RAS, 0x00020030,
+MX6_IOM_DRAM_SDCLK_0, 0x00020030,
+MX6_IOM_DRAM_SDCLK_1, 0x00020030,
+
+MX6_IOM_DRAM_RESET, 0x00020030,
+MX6_IOM_DRAM_SDCKE0, 0x00003000,
+MX6_IOM_DRAM_SDCKE1, 0x00003000,
+
+MX6_IOM_DRAM_SDODT0, 0x00003030,
+MX6_IOM_DRAM_SDODT1, 0x00003030,
+
+/* (differential input) */
+MX6_IOM_DDRMODE_CTL, 0x00020000,
+/* (differential input) */
+MX6_IOM_GRP_DDRMODE, 0x00020000,
+/* disable ddr pullups */
+MX6_IOM_GRP_DDRPKE, 0x00000000,
+MX6_IOM_DRAM_SDBA2, 0x00000000,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+
+/* Read data DQ Byte0-3 delay */
+MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+MX6_MMDC_P0_MDMISC, 0x00081740,
+
+/*
+ * MDSCR	con_req
+ */
+MX6_MMDC_P0_MDSCR, 0x00008000,
+
+/* 1066mhz_4x128mx16.cfg */
+
+MX6_MMDC_P0_MDPDC, 0x00020036,
+MX6_MMDC_P0_MDCFG0, 0x555A7954,
+MX6_MMDC_P0_MDCFG1, 0xDB328F64,
+MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+MX6_MMDC_P0_MDRWD, 0x000026D2,
+MX6_MMDC_P0_MDOR, 0x005A1023,
+MX6_MMDC_P0_MDOTC, 0x09555050,
+MX6_MMDC_P0_MDPDC, 0x00025576,
+MX6_MMDC_P0_MDASP, 0x00000027,
+MX6_MMDC_P0_MDCTL, 0x831A0000,
+MX6_MMDC_P0_MDSCR, 0x04088032,
+MX6_MMDC_P0_MDSCR, 0x00008033,
+MX6_MMDC_P0_MDSCR, 0x00428031,
+MX6_MMDC_P0_MDSCR, 0x19308030,
+MX6_MMDC_P0_MDSCR, 0x04008040,
+MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P0_MDREF, 0x00005800,
+MX6_MMDC_P0_MPODTCTRL, 0x00000000,
+MX6_MMDC_P1_MPODTCTRL, 0x00000000,
+
+MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
+MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
+MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
+MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
+
+MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
+MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
+
+MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
+MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
+
+MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
+MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
+MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
+MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
+
+MX6_MMDC_P0_MPMUR0, 0x00000800,
+MX6_MMDC_P1_MPMUR0, 0x00000800,
+MX6_MMDC_P0_MDSCR, 0x00000000,
+MX6_MMDC_P0_MAPSR, 0x00011006,
+};
+
+static int mx6_it_dcd_table[] = {
+/* ddr-setup.cfg */
+MX6_IOM_DRAM_SDQS0, 0x00000030,
+MX6_IOM_DRAM_SDQS1, 0x00000030,
+MX6_IOM_DRAM_SDQS2, 0x00000030,
+MX6_IOM_DRAM_SDQS3, 0x00000030,
+MX6_IOM_DRAM_SDQS4, 0x00000030,
+MX6_IOM_DRAM_SDQS5, 0x00000030,
+MX6_IOM_DRAM_SDQS6, 0x00000030,
+MX6_IOM_DRAM_SDQS7, 0x00000030,
+
+MX6_IOM_GRP_B0DS, 0x00000030,
+MX6_IOM_GRP_B1DS, 0x00000030,
+MX6_IOM_GRP_B2DS, 0x00000030,
+MX6_IOM_GRP_B3DS, 0x00000030,
+MX6_IOM_GRP_B4DS, 0x00000030,
+MX6_IOM_GRP_B5DS, 0x00000030,
+MX6_IOM_GRP_B6DS, 0x00000030,
+MX6_IOM_GRP_B7DS, 0x00000030,
+MX6_IOM_GRP_ADDDS, 0x00000030,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_CTLDS, 0x00000030,
+
+MX6_IOM_DRAM_DQM0, 0x00020030,
+MX6_IOM_DRAM_DQM1, 0x00020030,
+MX6_IOM_DRAM_DQM2, 0x00020030,
+MX6_IOM_DRAM_DQM3, 0x00020030,
+MX6_IOM_DRAM_DQM4, 0x00020030,
+MX6_IOM_DRAM_DQM5, 0x00020030,
+MX6_IOM_DRAM_DQM6, 0x00020030,
+MX6_IOM_DRAM_DQM7, 0x00020030,
+
+MX6_IOM_DRAM_CAS, 0x00020030,
+MX6_IOM_DRAM_RAS, 0x00020030,
+MX6_IOM_DRAM_SDCLK_0, 0x00020030,
+MX6_IOM_DRAM_SDCLK_1, 0x00020030,
+
+MX6_IOM_DRAM_RESET, 0x00020030,
+MX6_IOM_DRAM_SDCKE0, 0x00003000,
+MX6_IOM_DRAM_SDCKE1, 0x00003000,
+
+MX6_IOM_DRAM_SDODT0, 0x00003030,
+MX6_IOM_DRAM_SDODT1, 0x00003030,
+
+/* (differential input) */
+MX6_IOM_DDRMODE_CTL, 0x00020000,
+/* (differential input) */
+MX6_IOM_GRP_DDRMODE, 0x00020000,
+/* disable ddr pullups */
+MX6_IOM_GRP_DDRPKE, 0x00000000,
+MX6_IOM_DRAM_SDBA2, 0x00000000,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+
+/* Read data DQ Byte0-3 delay */
+MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+MX6_MMDC_P0_MDMISC, 0x00081740,
+
+/*
+ * MDSCR	con_req
+ */
+MX6_MMDC_P0_MDSCR, 0x00008000,
+
+/* 1066mhz_4x256mx16.cfg */
+
+MX6_MMDC_P0_MDPDC, 0x00020036,
+MX6_MMDC_P0_MDCFG0, 0x898E78f5,
+MX6_MMDC_P0_MDCFG1, 0xff328f64,
+MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+MX6_MMDC_P0_MDRWD, 0x000026D2,
+MX6_MMDC_P0_MDOR, 0x008E1023,
+MX6_MMDC_P0_MDOTC, 0x09444040,
+MX6_MMDC_P0_MDPDC, 0x00025576,
+MX6_MMDC_P0_MDASP, 0x00000047,
+MX6_MMDC_P0_MDCTL, 0x841A0000,
+MX6_MMDC_P0_MDSCR, 0x02888032,
+MX6_MMDC_P0_MDSCR, 0x00008033,
+MX6_MMDC_P0_MDSCR, 0x00048031,
+MX6_MMDC_P0_MDSCR, 0x19408030,
+MX6_MMDC_P0_MDSCR, 0x04008040,
+MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P0_MDREF, 0x00007800,
+MX6_MMDC_P0_MPODTCTRL, 0x00022227,
+MX6_MMDC_P1_MPODTCTRL, 0x00022227,
+
+MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
+MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
+MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
+MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
+
+MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
+MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
+
+MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
+MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
+
+MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
+MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
+MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
+MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
+
+MX6_MMDC_P0_MPMUR0, 0x00000800,
+MX6_MMDC_P1_MPMUR0, 0x00000800,
+MX6_MMDC_P0_MDSCR, 0x00000000,
+MX6_MMDC_P0_MAPSR, 0x00011006,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFFFF3, &ccm->CCGR2);
+	writel(0x3FF0300F, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000F3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+	writel(0x000000FB, &ccm->ccosr);
+}
+
+static void ddr_init(int *table, int size)
+{
+	int i;
+
+	for (i = 0; i < size / 2 ; i++)
+		writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+	int minc, maxc;
+
+	switch (get_cpu_temp_grade(&minc, &maxc)) {
+	case TEMP_COMMERCIAL:
+	case TEMP_EXTCOMMERCIAL:
+		puts("Commercial temperature grade DDR3 timings.\n");
+		ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
+		break;
+	case TEMP_INDUSTRIAL:
+	case TEMP_AUTOMOTIVE:
+	default:
+		puts("Industrial temperature grade DDR3 timings.\n");
+		ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
+		break;
+	};
+	udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* iomux */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
+	/* Make sure we use dte mode */
+	setup_dtemode_uart();
+#endif
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (!strcmp(name, "imx6-apalis"))
+		return 0;
+
+	return -1;
+}
+#endif
+
+void reset_cpu(void)
+{
+}
+
+#endif /* CONFIG_SPL_BUILD */
+
+static struct mxc_serial_plat mxc_serial_plat = {
+	.reg = (struct mxc_uart *)UART1_BASE,
+	.use_dte = true,
+};
+
+U_BOOT_DRVINFO(mxc_serial) = {
+	.name = "serial_mxc",
+	.plat = &mxc_serial_plat,
+};
diff --git a/roms/u-boot/board/toradex/apalis_imx6/do_fuse.c b/roms/u-boot/board/toradex/apalis_imx6/do_fuse.c
new file mode 100644
index 000000000..6991b1bc1
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_imx6/do_fuse.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ */
+
+/*
+ * Helpers for i.MX OTP fusing during module production
+*/
+
+#include <common.h>
+#ifndef CONFIG_SPL_BUILD
+#include <command.h>
+#include <console.h>
+#include <fuse.h>
+
+static int mfgr_fuse(void)
+{
+	unsigned val, val6;
+
+	fuse_sense(0, 5, &val);
+	printf("Fuse 0, 5: %8x\n", val);
+	fuse_sense(0, 6, &val6);
+	printf("Fuse 0, 6: %8x\n", val6);
+	fuse_sense(4, 3, &val);
+	printf("Fuse 4, 3: %8x\n", val);
+	fuse_sense(4, 2, &val);
+	printf("Fuse 4, 2: %8x\n", val);
+	if (val6 & 0x10) {
+		puts("BT_FUSE_SEL already fused, will do nothing\n");
+		return CMD_RET_FAILURE;
+	}
+	/* boot cfg */
+	fuse_prog(0, 5, 0x00005062);
+	/* BT_FUSE_SEL */
+	fuse_prog(0, 6, 0x00000010);
+	return CMD_RET_SUCCESS;
+}
+
+int do_mfgr_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
+		 char *const argv[])
+{
+	int ret;
+	puts("Fusing...\n");
+	ret = mfgr_fuse();
+	if (ret == CMD_RET_SUCCESS)
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return ret;
+}
+
+int do_updt_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
+		 char *const argv[])
+{
+	unsigned val;
+	int ret;
+	int confirmed = argc >= 1 && !strcmp(argv[1], "-y");
+
+	/* can be used in scripts for command availability check */
+	if (argc >= 1 && !strcmp(argv[1], "-n"))
+		return CMD_RET_SUCCESS;
+
+	/* boot cfg */
+	fuse_sense(0, 5, &val);
+	printf("Fuse 0, 5: %8x\n", val);
+	if (val & 0x10) {
+		puts("Fast boot mode already fused, no need to fuse\n");
+		return CMD_RET_SUCCESS;
+	}
+	if (!confirmed) {
+		puts("Warning: Programming fuses is an irreversible operation!\n"
+				"         Updating to fast boot mode prevents easy\n"
+				"         downgrading to previous BSP versions.\n"
+				"\nReally perform this fuse programming? <y/N>\n");
+		if (!confirm_yesno())
+			return CMD_RET_FAILURE;
+	}
+	puts("Fusing fast boot mode...\n");
+	ret = fuse_prog(0, 5, 0x00005072);
+	if (ret == CMD_RET_SUCCESS)
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return ret;
+}
+
+U_BOOT_CMD(
+	mfgr_fuse, 1, 0, do_mfgr_fuse,
+	"OTP fusing during module production",
+	""
+);
+
+U_BOOT_CMD(
+	updt_fuse, 2, 0, do_updt_fuse,
+	"OTP fusing during module update",
+	"updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
+);
+#endif /* CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/toradex/apalis_imx6/pf0100.c b/roms/u-boot/board/toradex/apalis_imx6/pf0100.c
new file mode 100644
index 000000000..c89052ff5
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_imx6/pf0100.c
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014-2019, Toradex AG
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <linux/delay.h>
+
+#include "pf0100_otp.inc"
+#include "pf0100.h"
+
+/* define for PMIC register dump */
+/*#define DEBUG */
+
+#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n"
+
+/* use Apalis GPIO1 to switch on VPGM, ON: 1 */
+static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
+	MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#	define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 4)
+};
+
+unsigned pmic_init(void)
+{
+	int rc;
+	struct udevice *dev = NULL;
+	unsigned programmed = 0;
+	uchar bus = 1;
+	uchar devid, revid, val;
+
+	puts("PMIC:  ");
+	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
+	if (rc) {
+		printf("failed to get device for PMIC at address 0x%x\n",
+		       PFUZE100_I2C_ADDR);
+		return 0;
+	}
+
+	/* check for errors in PMIC fuses */
+	if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) {
+		puts("i2c pmic INTSTAT3 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BIT_OTP_ECCI) {
+		puts("\n" WARNBAR);
+		puts("WARNING: ecc errors found in pmic fuse banks\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) {
+		puts("i2c pmic ECC_SE1 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_SE1) {
+		puts(WARNBAR);
+		puts("WARNING: ecc has made bit corrections in banks 1 to 5\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) {
+		puts("i2c pmic ECC_SE2 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_SE2) {
+		puts(WARNBAR);
+		puts("WARNING: ecc has made bit corrections in banks 6 to 10\n"
+		    );
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) {
+		puts("i2c pmic ECC_DE register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_DE1) {
+		puts(WARNBAR);
+		puts("ERROR: banks 1 to 5 have uncorrectable bits\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) {
+		puts("i2c pmic ECC_DE register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_DE2) {
+		puts(WARNBAR);
+		puts("ERROR: banks 6 to 10 have uncorrectable bits\n");
+		puts(WARNBAR);
+	}
+
+	/* get device ident */
+	if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) {
+		puts("i2c pmic devid read failed\n");
+		return 0;
+	}
+	if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) {
+		puts("i2c pmic revid read failed\n");
+		return 0;
+	}
+	printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid);
+
+	/* get device programmed state */
+	val = PFUZE100_PAGE_REGISTER_PAGE1;
+	if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+		puts("i2c write failed\n");
+		return 0;
+	}
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return programmed;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return programmed;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	switch (programmed) {
+	case 0:
+		puts("not programmed\n");
+		break;
+	case 3:
+		puts("programmed\n");
+		break;
+	default:
+		puts("undefined programming state\n");
+		break;
+	}
+
+	/* The following is needed during production */
+	if (programmed != 3) {
+		/* set VGEN1 to 1.2V */
+		val = PFUZE100_VGEN1_VAL;
+		if (dm_i2c_write(dev, PFUZE100_VGEN1CTL, &val, 1)) {
+			puts("i2c write failed\n");
+			return programmed;
+		}
+
+		/* set SWBST to 5.0V */
+		val = PFUZE100_SWBST_VAL;
+		if (dm_i2c_write(dev, PFUZE100_SWBSTCTL, &val, 1))
+			puts("i2c write failed\n");
+	}
+
+#ifdef DEBUG
+	{
+		unsigned int i, j;
+
+		for (i = 0; i < 16; i++)
+			printf("\t%x", i);
+		for (j = 0; j < 0x80; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 1");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE1;
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 2");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE2;
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\n");
+	}
+#endif /* DEBUG */
+
+	return programmed;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int pf0100_prog(void)
+{
+	int rc;
+	struct udevice *dev = NULL;
+	unsigned char bus = 1;
+	unsigned char val;
+	unsigned int i;
+
+	if (pmic_init() == 3) {
+		puts("PMIC already programmed, exiting\n");
+		return CMD_RET_FAILURE;
+	}
+	/* set up gpio to manipulate vprog, initially off */
+	imx_iomux_v3_setup_multiple_pads(pmic_prog_pads,
+					 ARRAY_SIZE(pmic_prog_pads));
+	gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
+
+	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
+	if (rc) {
+		printf("failed to get device for PMIC at address 0x%x\n",
+		       PFUZE100_I2C_ADDR);
+		return CMD_RET_FAILURE;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) {
+		switch (pmic_otp_prog[i].cmd) {
+		case pmic_i2c:
+			val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
+			if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) {
+				printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
+				       pmic_otp_prog[i].reg, val);
+				return CMD_RET_FAILURE;
+			}
+			break;
+		case pmic_delay:
+			udelay(pmic_otp_prog[i].value * 1000);
+			break;
+		case pmic_vpgm:
+			gpio_direction_output(PMIC_PROG_VOLTAGE,
+					      pmic_otp_prog[i].value);
+			break;
+		case pmic_pwr:
+			/* TODO */
+			break;
+		}
+	}
+	return CMD_RET_SUCCESS;
+}
+
+static int do_pf0100_prog(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	int ret;
+	puts("Programming PMIC OTP...");
+	ret = pf0100_prog();
+	if (ret == CMD_RET_SUCCESS)
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return ret;
+}
+
+U_BOOT_CMD(
+	pf0100_otp_prog, 1, 0, do_pf0100_prog,
+	"Program the OTP fuses on the PMIC PF0100",
+	""
+);
+#endif /* CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/toradex/apalis_imx6/pf0100.h b/roms/u-boot/board/toradex/apalis_imx6/pf0100.h
new file mode 100644
index 000000000..925762051
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_imx6/pf0100.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014-2019, Toradex AG
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#ifndef PF0100_H_
+#define PF0100_H_
+
+/* bit definitions */
+#define PFUZE100_BIT_0			(0x01 << 0)
+#define PFUZE100_BIT_1			(0x01 << 1)
+#define PFUZE100_BIT_2			(0x01 << 2)
+#define PFUZE100_BIT_3			(0x01 << 3)
+#define PFUZE100_BIT_4			(0x01 << 4)
+#define PFUZE100_BIT_5			(0x01 << 5)
+#define PFUZE100_BIT_6			(0x01 << 6)
+#define PFUZE100_BIT_7			(0x01 << 7)
+
+/* 7-bit I2C bus slave address */
+#define PFUZE100_I2C_ADDR		(0x08)
+/* Register Addresses */
+#define PFUZE100_DEVICEID		(0x0)
+#define PFUZE100_REVID			(0x3)
+#define PFUZE100_INTSTAT3		(0xe)
+#define PFUZE100_BIT_OTP_ECCI		PFUZE100_BIT_7
+#define PFUZE100_SW1AMODE		(0x23)
+#define PFUZE100_SW1ACON		36
+#define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1CCON		49
+#define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1AVOL		32
+#define PFUZE100_SW1AVOL_VSEL_M		(0x3f<<0)
+#define PFUZE100_SW1CVOL		46
+#define PFUZE100_SW1CVOL_VSEL_M		(0x3f<<0)
+#define PFUZE100_VGEN1CTL		(0x6c)
+#define PFUZE100_VGEN1_VAL		(0x30 + 0x08) /* Always ON, 1.2V */
+#define PFUZE100_SWBSTCTL		(0x66)
+/* Always ON, Auto Switching Mode, 5.0V */
+#define PFUZE100_SWBST_VAL		(0x40 + 0x08 + 0x00)
+
+/* chooses the extended page (registers 0x80..0xff) */
+#define PFUZE100_PAGE_REGISTER		0x7f
+#define PFUZE100_PAGE_REGISTER_PAGE_M	(0x1f << 0)
+#define PFUZE100_PAGE_REGISTER_PAGE1	(0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
+#define PFUZE100_PAGE_REGISTER_PAGE2	(0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
+
+/* extended page 1 */
+#define PFUZE100_OTP_ECC_SE1		0x8a
+#define PFUZE100_BIT_ECC1_SE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC2_SE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC3_SE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC4_SE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC5_SE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_SE1		((PFUZE100_BIT_ECC1_SE) | \
+					(PFUZE100_BIT_ECC2_SE) | \
+					(PFUZE100_BIT_ECC3_SE) | \
+					(PFUZE100_BIT_ECC4_SE) | \
+					(PFUZE100_BIT_ECC5_SE))
+#define PFUZE100_OTP_ECC_SE2		0x8b
+#define PFUZE100_BIT_ECC6_SE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC7_SE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC8_SE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC9_SE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC10_SE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_SE2		((PFUZE100_BIT_ECC6_SE) | \
+					(PFUZE100_BIT_ECC7_SE) | \
+					(PFUZE100_BIT_ECC8_SE) | \
+					(PFUZE100_BIT_ECC9_SE) | \
+					(PFUZE100_BIT_ECC10_SE))
+#define PFUZE100_OTP_ECC_DE1		0x8c
+#define PFUZE100_BIT_ECC1_DE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC2_DE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC3_DE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC4_DE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC5_DE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_DE1		((PFUZE100_BIT_ECC1_DE) | \
+					(PFUZE100_BIT_ECC2_DE) | \
+					(PFUZE100_BIT_ECC3_DE) | \
+					(PFUZE100_BIT_ECC4_DE) | \
+					(PFUZE100_BIT_ECC5_DE))
+#define PFUZE100_OTP_ECC_DE2		0x8d
+#define PFUZE100_BIT_ECC6_DE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC7_DE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC8_DE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC9_DE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC10_DE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_DE2		((PFUZE100_BIT_ECC6_DE) | \
+					(PFUZE100_BIT_ECC7_DE) | \
+					(PFUZE100_BIT_ECC8_DE) | \
+					(PFUZE100_BIT_ECC9_DE) | \
+					(PFUZE100_BIT_ECC10_DE))
+#define PFUZE100_FUSE_POR1		0xe4
+#define PFUZE100_FUSE_POR2		0xe5
+#define PFUZE100_FUSE_POR3		0xe6
+#define PFUZE100_FUSE_POR_M		(0x1 << 1)
+
+/* output some informational messages, return the number FUSE_POR=1 */
+/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
+unsigned pmic_init(void);
+
+#endif /* PF0100_H_ */
diff --git a/roms/u-boot/board/toradex/apalis_imx6/pf0100_otp.inc b/roms/u-boot/board/toradex/apalis_imx6/pf0100_otp.inc
new file mode 100644
index 000000000..a7790fd6c
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_imx6/pf0100_otp.inc
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ */
+
+// Register Output for PF0100 programmer
+// Customer: Toradex AG
+// Program: Apalis iMX6
+// Sample marking:
+// Date: 12.02.2014
+// Time: 17:16:41
+// Generated from Spreadsheet Revision: P1.8
+
+/* sed commands to get from programmer script to struct */
+/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc
+   sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
+   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
+
+enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
+struct pmic_otp_prog_t{
+	unsigned char cmd;
+	unsigned char reg;
+	unsigned short value;
+};
+
+struct pmic_otp_prog_t pmic_otp_prog[] = {
+{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
+{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
+{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
+{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
+{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
+{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
+{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
+{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
+{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
+{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
+{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
+{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
+{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
+{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
+{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
+{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
+{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
+{pmic_i2c, 0xBD, 0x1F}, // Auto gen from Row123
+{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
+{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
+{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
+{pmic_i2c, 0xC9, 0x08}, // Auto gen from Row135
+{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
+{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
+{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
+{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
+{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
+{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
+{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
+{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
+{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
+{pmic_i2c, 0xE0, 0x07}, // Auto gen from Row158
+
+#if 0 /* TBB mode */
+{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
+{pmic_delay, 0, 10},
+#else
+// Write OTP
+{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
+{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
+{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
+{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
+{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
+{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
+{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
+{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
+//VPGM:DOWN:n
+//VPGM:UP:n
+{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
+//-----------------------------------------------------------------------------------
+// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
+//-----------------------------------------------------------------------------------
+// BANK 1
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 2
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 3
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 4
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 5
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 6
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 7
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 8
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 9
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 10
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
+{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
+{pmic_i2c, 0xD0, 0x00}, // Clear
+{pmic_i2c, 0xD1, 0x00}, // Clear
+{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
+{pmic_delay, 0, 500},
+{pmic_pwr, 0, 1},
+#endif
+};
\ No newline at end of file
diff --git a/roms/u-boot/board/toradex/apalis_t30/Kconfig b/roms/u-boot/board/toradex/apalis_t30/Kconfig
new file mode 100644
index 000000000..9cd497091
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_t30/Kconfig
@@ -0,0 +1,39 @@
+if TARGET_APALIS_T30
+
+config SYS_BOARD
+	default "apalis_t30"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "apalis_t30"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+config APALIS_T30_PCIE_EVALBOARD_INIT
+	bool "Apalis Evaluation Board PCIe Initialisation"
+	help
+	  Bring up the Apalis type specific 4 lane PCIe port as well as the
+	  Apalis PCIe port with the PCIe switch as found on the Apalis
+	  Evaluation board. Note that by default both those ports are also left
+	  disabled in the device tree which needs changing as well for this to
+	  actually work.
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/apalis_t30/MAINTAINERS b/roms/u-boot/board/toradex/apalis_t30/MAINTAINERS
new file mode 100644
index 000000000..01bc73e46
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_t30/MAINTAINERS
@@ -0,0 +1,7 @@
+Apalis T30
+M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
+S:	Maintained
+F:	board/toradex/apalis_t30/
+F:	include/configs/apalis_t30.h
+F:	configs/apalis_t30_defconfig
+F:	arch/arm/dts/tegra30-apalis.dtb
diff --git a/roms/u-boot/board/toradex/apalis_t30/Makefile b/roms/u-boot/board/toradex/apalis_t30/Makefile
new file mode 100644
index 000000000..0ea3d8f21
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_t30/Makefile
@@ -0,0 +1,4 @@
+# Copyright (c) 2014 Marcel Ziswiler
+# SPDX-License-Identifier:      GPL-2.0+
+
+obj-y	+= apalis_t30.o
diff --git a/roms/u-boot/board/toradex/apalis_t30/apalis_t30.c b/roms/u-boot/board/toradex/apalis_t30/apalis_t30.c
new file mode 100644
index 000000000..0396eea56
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_t30/apalis_t30.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2014-2018
+ *  Marcel Ziswiler <marcel@ziswiler.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/tegra.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <i2c.h>
+#include <pci_tegra.h>
+#include <linux/delay.h>
+#include "../common/tdx-common.h"
+
+#include "pinmux-config-apalis_t30.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PMU_I2C_ADDRESS		0x2D
+#define MAX_I2C_RETRY		3
+
+#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
+#define PEX_PERST_N	TEGRA_GPIO(S, 7) /* Apalis GPIO7 */
+#define RESET_MOCI_CTRL	TEGRA_GPIO(I, 4)
+
+static int pci_reset_status;
+#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
+
+int arch_misc_init(void)
+{
+	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
+	    NVBOOTTYPE_RECOVERY)
+		printf("USB recovery mode\n");
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Model: Toradex Apalis T30 %dGB\n",
+	       (gd->ram_size == 0x40000000) ? 1 : 2);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_pingrp_table(tegra3_pinmux_common,
+				   ARRAY_SIZE(tegra3_pinmux_common));
+
+	pinmux_config_pingrp_table(unused_pins_lowpower,
+				   ARRAY_SIZE(unused_pins_lowpower));
+
+	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
+	pinmux_config_drvgrp_table(apalis_t30_padctrl,
+				   ARRAY_SIZE(apalis_t30_padctrl));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+	struct udevice *dev;
+	u8 addr, data[1];
+	int err;
+
+	err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
+	if (err) {
+		debug("%s: Cannot find PMIC I2C chip\n", __func__);
+		return err;
+	}
+
+	/* TPS659110: VDD2_OP_REG = 1.05V */
+	data[0] = 0x27;
+	addr = 0x25;
+
+	err = dm_i2c_write(dev, addr, data, 1);
+	if (err) {
+		debug("failed to set VDD supply\n");
+		return err;
+	}
+
+	/* TPS659110: VDD2_REG 7.5 mV/us, ACTIVE */
+	data[0] = 0x0D;
+	addr = 0x24;
+
+	err = dm_i2c_write(dev, addr, data, 1);
+	if (err) {
+		debug("failed to enable VDD supply\n");
+		return err;
+	}
+
+	/* TPS659110: LDO6_REG = 1.1V, ACTIVE */
+	data[0] = 0x0D;
+	addr = 0x35;
+
+	err = dm_i2c_write(dev, addr, data, 1);
+	if (err) {
+		debug("failed to set AVDD supply\n");
+		return err;
+	}
+
+#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
+	gpio_request(PEX_PERST_N, "PEX_PERST_N");
+	gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
+#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
+
+	return 0;
+}
+
+void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
+{
+	int index = tegra_pcie_port_index_of_port(port);
+
+	if (index == 2) { /* I210 Gigabit Ethernet Controller (On-module) */
+		tegra_pcie_port_reset(port);
+	}
+#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
+	/*
+	 * Apalis PCIe aka port 1 and Apalis Type Specific 4 Lane PCIe aka port
+	 * 0 share the same RESET_MOCI therefore only assert it once for both
+	 * ports to avoid losing the previously brought up port again.
+	 */
+	else if ((index == 1) || (index == 0)) {
+		/* only do it once per init cycle */
+		if (pci_reset_status % 2 == 0) {
+			/*
+			 * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on
+			 * Apalis Evaluation Board
+			 */
+			gpio_direction_output(PEX_PERST_N, 0);
+			gpio_direction_output(RESET_MOCI_CTRL, 0);
+
+			/*
+			 * Must be asserted for 100 ms after power and clocks
+			 * are stable
+			 */
+			mdelay(100);
+
+			gpio_set_value(PEX_PERST_N, 1);
+			/*
+			 * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not
+			 * Guaranteed Until 900 us After PEX_PERST# De-assertion
+			 */
+			mdelay(1);
+			gpio_set_value(RESET_MOCI_CTRL, 1);
+		}
+		pci_reset_status++;
+	}
+#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
+}
+#endif /* CONFIG_PCI_TEGRA */
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+	gpio_request(TEGRA_GPIO(V, 2), "BKL1_ON");
+	gpio_direction_output(TEGRA_GPIO(V, 2), 0);
+}
diff --git a/roms/u-boot/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/roms/u-boot/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
new file mode 100644
index 000000000..3a2cf4606
--- /dev/null
+++ b/roms/u-boot/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2014, Marcel Ziswiler
+ */
+
+#ifndef _PINMUX_CONFIG_APALIS_T30_H_
+#define _PINMUX_CONFIG_APALIS_T30_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io)		\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+/* TRISTATE here means output driver is tri-stated */ \
+		.tristate	= PMUX_TRI_##_tri,		\
+/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{							\
+		.drvgrp		= PMUX_DRVGRP_##_drvgrp,	\
+		.slwf		= _slwf,			\
+		.slwr		= _slwr,			\
+		.drvup		= _drvup,			\
+		.drvdn		= _drvdn,			\
+		.lpmd		= PMUX_LPMD_##_lpmd,		\
+		.schmt		= PMUX_SCHMT_##_schmt,		\
+		.hsm		= PMUX_HSM_##_hsm,		\
+	}
+
+static struct pmux_pingrp_config tegra3_pinmux_common[] = {
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, NORMAL, NORMAL, INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, NORMAL, NORMAL, INPUT),
+
+	/* SDMMC4 pinmux (eMMC) */
+	LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL_PT5, RSVD3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(GEN2_I2C_SDA_PT6, RSVD3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+	/* UARTA RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
+	/* UARTD RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
+	LV_PINMUX(VI_D0_PT4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D1_PD5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D10_PT2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D11_PT3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	/* UARTB RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+	/* UARTC RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(PU1, RSVD1, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(PU2, RSVD1, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(PU3, PWM0, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU6, PWM3, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_AD10_PH2, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_A17_PB0, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_A19_PK7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
+
+	DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, OUTPUT),
+
+	DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
+
+	/* multiplexed VI_D2, VI_D3, VI_D4, VI_D5, VI_D6, VI_D7, VI_D8 and VI_D9
+	 */
+	DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT),
+
+	/* GPIOs */
+	DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL2_PQ2, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT),
+	/* multiplexed KB_COL0 */
+	DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, TRISTATE, OUTPUT),
+
+	DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, RSVD2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC */
+
+	DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_AD12_PH4, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_AD14_PH6, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
+
+	DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, INPUT),
+};
+
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CLK_PK1, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD0_PG0, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD1_PG1, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD2_PG2, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD3_PG3, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD4_PG4, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD5_PG5, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD6_PG6, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD7_PG7, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11_PH3, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD13_PH5, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_DQS_PI2, NAND, DOWN, TRISTATE, OUTPUT),
+};
+
+static struct pmux_drvgrp_config apalis_t30_padctrl[] = {
+	/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+	DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+		SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif	/* _PINMUX_CONFIG_APALIS_T30_H_ */
diff --git a/roms/u-boot/board/toradex/colibri-imx6ull/Kconfig b/roms/u-boot/board/toradex/colibri-imx6ull/Kconfig
new file mode 100644
index 000000000..3ce9885c1
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri-imx6ull/Kconfig
@@ -0,0 +1,29 @@
+if TARGET_COLIBRI_IMX6ULL
+
+config SYS_BOARD
+	default "colibri-imx6ull"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "colibri-imx6ull"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "2048"
+
+config TDX_CFG_BLOCK_OFFSET2
+	default "133120"
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	default y
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/colibri-imx6ull/MAINTAINERS b/roms/u-boot/board/toradex/colibri-imx6ull/MAINTAINERS
new file mode 100644
index 000000000..899b1ff55
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri-imx6ull/MAINTAINERS
@@ -0,0 +1,11 @@
+Colibri iMX6ULL
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+W:	https://www.toradex.com/community
+S:	Maintained
+F:	arch/arm/dts/imx6ull-colibri.dts
+F:	arch/arm/dts/imx6ull-colibri-u-boot.dtsi
+F:	arch/arm/dts/imx6ull-colibri.dtsi
+F:	board/toradex/colibri-imx6ull/
+F:	configs/colibri-imx6ull_defconfig
+F:	include/configs/colibri-imx6ull.h
diff --git a/roms/u-boot/board/toradex/colibri-imx6ull/Makefile b/roms/u-boot/board/toradex/colibri-imx6ull/Makefile
new file mode 100644
index 000000000..f478e6804
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri-imx6ull/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2018 Toradex AG
+
+obj-y  := colibri-imx6ull.o
diff --git a/roms/u-boot/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/roms/u-boot/board/toradex/colibri-imx6ull/colibri-imx6ull.c
new file mode 100644
index 000000000..01f556159
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2019 Toradex AG
+ */
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch-mx6/clock.h>
+#include <asm/arch-mx6/imx-regs.h>
+#include <asm/arch-mx6/mx6ull_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <imx_thermal.h>
+#include <jffs2/load_kernel.h>
+#include <linux/sizes.h>
+#include <miiphy.h>
+#include <mtd_node.h>
+#include <netdev.h>
+
+#include "../common/tdx-common.h"
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
+		PAD_CTL_DSE_48ohm)
+
+#define MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR 0x2290040
+
+#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+#ifdef CONFIG_NAND_MXS
+static void setup_gpmi_nand(void)
+{
+	setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
+			  (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+}
+#endif /* CONFIG_NAND_MXS */
+
+#ifdef CONFIG_DM_VIDEO
+static iomux_v3_cfg_t const backlight_pads[] = {
+	/* Backlight On */
+	MX6_PAD_JTAG_TMS__GPIO1_IO11		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* Backlight PWM<A> (multiplexed pin) */
+	MX6_PAD_NAND_WP_B__GPIO4_IO11		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define GPIO_BL_ON IMX_GPIO_NR(1, 11)
+#define GPIO_PWM_A IMX_GPIO_NR(4, 11)
+
+static int setup_lcd(void)
+{
+	imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
+
+	/* Set BL_ON */
+	gpio_request(GPIO_BL_ON, "BL_ON");
+	gpio_direction_output(GPIO_BL_ON, 1);
+
+	/* Set PWM<A> to full brightness (assuming inversed polarity) */
+	gpio_request(GPIO_PWM_A, "PWM<A>");
+	gpio_direction_output(GPIO_PWM_A, 0);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	/* provide the PHY clock from the i.MX 6 */
+	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	/* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */
+	clrsetbits_le32(&iomuxc_regs->gpr[1],
+			IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
+			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+	/* give new Ethernet PHY power save mode circuitry time to settle */
+	mdelay(300);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif /* CONFIG_FEC_MXC */
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+/* TODO */
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
+	{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
+	{NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_TDX_CFG_BLOCK
+	/*
+	 * If we have a valid config block and it says we are a module with
+	 * Wi-Fi/Bluetooth make sure we use the -wifi device tree.
+	 */
+	if (tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT_IT ||
+	    tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT)
+		env_set("variant", "-wifi");
+#endif
+
+	/*
+	 * Disable output driver of PAD CCM_PMIC_STBY_REQ. This prevents the
+	 * SOC to request for a lower voltage during sleep. This is necessary
+	 * because the voltage is changing too slow for the SOC to wake up
+	 * properly.
+	 */
+	__raw_writel(0x8080, MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR);
+
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_CMD_USB_SDP
+	if (is_boot_from_usb()) {
+		printf("Serial Downloader recovery mode, using sdp command\n");
+		env_set("bootdelay", "0");
+		env_set("bootcmd", "sdp 0");
+	}
+#endif /* CONFIG_CMD_USB_SDP */
+
+#if defined(CONFIG_DM_VIDEO)
+	setup_lcd();
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Model: Toradex Colibri iMX6ULL\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
+	static struct node_info nodes[] = {
+		{ "fsl,imx6ull-gpmi-nand", MTD_DEV_TYPE_NAND, },
+		{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
+	};
+
+	/* Update partition nodes using info from mtdparts env var */
+	puts("   Updating MTD partitions...\n");
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+static struct mxc_serial_plat mxc_serial_plat = {
+	.reg = (struct mxc_uart *)UART1_BASE,
+	.use_dte = 1,
+};
+
+U_BOOT_DRVINFO(mxc_serial) = {
+	.name = "serial_mxc",
+	.plat = &mxc_serial_plat,
+};
diff --git a/roms/u-boot/board/toradex/colibri-imx6ull/imximage.cfg b/roms/u-boot/board/toradex/colibri-imx6ull/imximage.cfg
new file mode 100644
index 000000000..8d869d9f7
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri-imx6ull/imximage.cfg
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2018 Toradex AG
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : nand
+ */
+
+BOOT_FROM	nand
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x000C0030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000004
+DATA 4 0x021B083C 0x41640158
+DATA 4 0x021B0848 0x40403237
+DATA 4 0x021B0850 0x40403C33
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00944009
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D0B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0x84180000
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+
diff --git a/roms/u-boot/board/toradex/colibri-imx8x/Kconfig b/roms/u-boot/board/toradex/colibri-imx8x/Kconfig
new file mode 100644
index 000000000..d97fed020
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri-imx8x/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_COLIBRI_IMX8X
+
+config SYS_BOARD
+	default "colibri-imx8x"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "colibri-imx8x"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/colibri-imx8x/MAINTAINERS b/roms/u-boot/board/toradex/colibri-imx8x/MAINTAINERS
new file mode 100644
index 000000000..de62f87a5
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri-imx8x/MAINTAINERS
@@ -0,0 +1,10 @@
+Colibri iMX8X
+M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+S:	Maintained
+F:	arch/arm/dts/fsl-imx8x-colibri.dts
+F:	arch/arm/dts/fsl-imx8x-colibri-u-boot.dtsi
+F:	board/toradex/colibri-imx8x/
+F:	configs/colibri-imx8x_defconfig
+F:	doc/board/toradex/colibri-imx8x.rst
+F:	include/configs/colibri-imx8x.h
diff --git a/roms/u-boot/board/toradex/colibri-imx8x/Makefile b/roms/u-boot/board/toradex/colibri-imx8x/Makefile
new file mode 100644
index 000000000..e3945c8f1
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri-imx8x/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Toradex
+#
+
+obj-y += colibri-imx8x.o
diff --git a/roms/u-boot/board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg b/roms/u-boot/board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg
new file mode 100644
index 000000000..44f6c0c45
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Toradex
+ *
+ * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM EMMC_FASTBOOT 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND mx8qx-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qx-colibri-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/roms/u-boot/board/toradex/colibri-imx8x/colibri-imx8x.c b/roms/u-boot/board/toradex/colibri-imx8x/colibri-imx8x.c
new file mode 100644
index 000000000..169d4d04b
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Toradex
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/global_data.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <env.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart3_pads[] = {
+	SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
+	/* Transceiver FORCEOFF# signal, mux to use pull-up */
+	SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+}
+
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+			  u64 *phys_sdram_1_size,
+			  u64 *phys_sdram_2_start,
+			  u64 *phys_sdram_2_size)
+{
+	u32 is_dualx = 0, val = 0;
+	sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+	if (scierr == SC_ERR_NONE) {
+		/* DX has two A35 cores disabled */
+		is_dualx = (val & 0xf) != 0x0;
+	}
+
+	*phys_sdram_1_start = PHYS_SDRAM_1;
+	if (is_dualx)
+		/* Our DX based SKUs only have 1 GB RAM */
+		*phys_sdram_1_size = SZ_1G;
+	else
+		*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+	*phys_sdram_2_start = PHYS_SDRAM_2;
+	*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate;
+	sc_err_t err = 0;
+
+	/*
+	 * This works around that having only UART3 up the baudrate is 1.2M
+	 * instead of 115.2k. Set UART0 clock root to 80 MHz
+	 */
+	rate = 80000000;
+	err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	/* Set UART3 clock root to 80 MHz and enable it */
+	rate = SC_80MHZ;
+	err = sc_pm_setup_uart(SC_R_UART_3, rate);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_DM_GPIO)
+static void board_gpio_init(void)
+{
+	/* TODO */
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Model: Toradex Colibri iMX8X\n");
+
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	board_gpio_init();
+
+	return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+	/* TODO */
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+/* TODO move to common */
+	env_set("board_name", "Colibri iMX8QXP");
+	env_set("board_rev", "v1.0");
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/toradex/colibri_imx6/Kconfig b/roms/u-boot/board/toradex/colibri_imx6/Kconfig
new file mode 100644
index 000000000..d2ad1ce2a
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx6/Kconfig
@@ -0,0 +1,44 @@
+if TARGET_COLIBRI_IMX6
+
+config SYS_BOARD
+	default "colibri_imx6"
+
+config SYS_CONFIG_NAME
+	default "colibri_imx6"
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_VENDOR
+	default "toradex"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+config TDX_CMD_IMX_MFGR
+	bool "Enable factory testing commands for Toradex iMX 6 modules"
+	help
+	  This adds the commands
+	    pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
+	  If executed on already fused modules it doesn't change any fuse setting.
+	default y
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/colibri_imx6/MAINTAINERS b/roms/u-boot/board/toradex/colibri_imx6/MAINTAINERS
new file mode 100644
index 000000000..2cbf65433
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx6/MAINTAINERS
@@ -0,0 +1,9 @@
+Colibri iMX6
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+W:      https://www.toradex.com/community
+S:	Maintained
+F:	board/toradex/colibri_imx6/
+F:	include/configs/colibri_imx6.h
+F:	configs/colibri_imx6_defconfig
+F:	arch/arm/dts/imx6-colibri.dts
diff --git a/roms/u-boot/board/toradex/colibri_imx6/Makefile b/roms/u-boot/board/toradex/colibri_imx6/Makefile
new file mode 100644
index 000000000..c81bc2d74
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx6/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2012-2014 Toradex, Inc.
+# SPDX-License-Identifier:      GPL-2.0+
+
+obj-y  := colibri_imx6.o do_fuse.o
+obj-$(CONFIG_TDX_CMD_IMX_MFGR)  += pf0100.o
diff --git a/roms/u-boot/board/toradex/colibri_imx6/colibri_imx6.c b/roms/u-boot/board/toradex/colibri_imx6/colibri_imx6.c
new file mode 100644
index 000000000..c0e775446
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx6/colibri_imx6.c
@@ -0,0 +1,1098 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ * Copyright (C) 2014-2019, Toradex AG
+ * copied from nitrogen6x
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/bootm.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
+#include <cpu.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <fsl_esdhc_imx.h>
+#include <imx_thermal.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <cpu.h>
+
+#include "../common/tdx-cfg-block.h"
+#ifdef CONFIG_TDX_CMD_IMX_MFGR
+#include "pf0100.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |		\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_SRE_SLOW)
+
+#define NO_PULLUP	(					\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_SRE_SLOW)
+
+#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+	/* use the DDR controllers configured size */
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    (ulong)imx_ddr_size());
+
+	return 0;
+}
+
+/* Colibri UARTA */
+iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
+/* Colibri MMC */
+iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+#	define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
+};
+
+/* eMMC */
+iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
+
+/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
+iomux_v3_cfg_t const gpio_pads[] = {
+	/* ADDRESS[17:18] [25] used as GPIO */
+	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_KEY_COL2__GPIO4_IO10	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D1__GPIO2_IO01	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	/* ADDRESS[19:24] used as GPIO */
+	MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	/* DATA[16:29] [31]	 used as GPIO */
+	MX6_PAD_EIM_LBA__GPIO2_IO27	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CS3__GPIO6_IO16	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CS1__GPIO6_IO14	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_ALE__GPIO6_IO08	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CS0__GPIO6_IO11	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CLE__GPIO6_IO07	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_19__GPIO4_IO05	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_CSI0_MCLK__GPIO5_IO19	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_5__GPIO1_IO05	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	/* DQM[0:3]	 used as GPIO */
+	MX6_PAD_EIM_EB0__GPIO2_IO28	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_EB1__GPIO2_IO29	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD2_DAT2__GPIO1_IO13	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D0__GPIO2_IO00	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	/* RDY	used as GPIO */
+	MX6_PAD_EIM_WAIT__GPIO5_IO00	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	/* ADDRESS[16] DATA[30]	 used as GPIO */
+	MX6_PAD_KEY_ROW4__GPIO4_IO15	| MUX_PAD_CTRL(WEAK_PULLDOWN) |
+					  MUX_MODE_SION,
+	MX6_PAD_KEY_COL4__GPIO4_IO14	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	/* CSI pins used as GPIO */
+	MX6_PAD_EIM_A24__GPIO5_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD2_CMD__GPIO1_IO11	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_D18__GPIO3_IO18	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A19__GPIO2_IO19	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_D29__GPIO3_IO29	| MUX_PAD_CTRL(WEAK_PULLDOWN) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A23__GPIO6_IO06	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A20__GPIO2_IO18	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A17__GPIO2_IO21	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A18__GPIO2_IO20	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_EB3__GPIO2_IO31	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_D17__GPIO3_IO17	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD2_DAT0__GPIO1_IO15	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	/* GPIO */
+	MX6_PAD_EIM_D26__GPIO3_IO26	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_D27__GPIO3_IO27	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D3__GPIO2_IO03	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DI0_PIN4__GPIO4_IO20	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD4_DAT3__GPIO2_IO11	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD4_DAT0__GPIO2_IO08	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_7__GPIO1_IO07	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_8__GPIO1_IO08	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	/* USBH_OC */
+	MX6_PAD_EIM_D30__GPIO3_IO30	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* USBC_ID */
+	MX6_PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* USBC_DET */
+	MX6_PAD_GPIO_17__GPIO7_IO12	| MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+static void setup_iomux_gpio(void)
+{
+	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+}
+
+iomux_v3_cfg_t const usb_pads[] = {
+	/* USBH_PEN */
+	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
+#	define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
+};
+
+/*
+ * UARTs are used in DTE mode, switch the mode on all UARTs before
+ * any pinmuxing connects a (DCE) output to a transceiver output.
+ */
+#define UCR3		0x88	/* FIFO Control Register */
+#define UCR3_RI		BIT(8)	/* RIDELT DTE mode */
+#define UCR3_DCD	BIT(9)	/* DCDDELT DTE mode */
+#define UFCR		0x90	/* FIFO Control Register */
+#define UFCR_DCEDTE	BIT(6)	/* DCE=0 */
+
+static void setup_dtemode_uart(void)
+{
+	setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
+	setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
+	setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
+
+	clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
+}
+
+static void setup_iomux_uart(void)
+{
+	setup_dtemode_uart();
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
+/* use the following sequence: eMMC, MMC */
+struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = true; /* default: assume inserted */
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		gpio_request(GPIO_MMC_CD, "MMC_CD");
+		gpio_direction_input(GPIO_MMC_CD);
+		ret = !gpio_get_value(GPIO_MMC_CD);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned reg = readl(&psrc->sbmr1) >> 11;
+	/*
+	 * Upon reading BOOT_CFG register the following map is done:
+	 * Bit 11 and 12 of BOOT_CFG register can determine the current
+	 * mmc port
+	 * 0x1                  SD1
+	 * 0x2                  SD2
+	 * 0x3                  SD4
+	 */
+
+	switch (reg & 0x3) {
+	case 0x0:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x2:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	default:
+		puts("MMC boot device not available");
+	}
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int setup_fec(void)
+{
+	int ret;
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* provide the PHY clock from the i.MX 6 */
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const pwr_intb_pads[] = {
+	/*
+	 * the bootrom sets the iomux to vselect, potentially connecting
+	 * two outputs. Set this back to GPIO
+	 */
+	MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+	/* Backlight On */
+	MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
+#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
+	/* Backlight PWM, used as GPIO in U-Boot */
+	MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
+	MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+				       MUX_MODE_SION,
+#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+	imx_iomux_v3_setup_multiple_pads(
+		rgb_pads,
+		ARRAY_SIZE(rgb_pads));
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+}
+
+static int detect_default(struct display_info_t const *dev)
+{
+	(void) dev;
+	return 1;
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= detect_default,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "vga-rgb",
+		.refresh        = 60,
+		.xres           = 640,
+		.yres           = 480,
+		.pixclock       = 33000,
+		.left_margin    = 48,
+		.right_margin   = 16,
+		.upper_margin   = 31,
+		.lower_margin   = 11,
+		.hsync_len      = 96,
+		.vsync_len      = 2,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "wvga-rgb",
+		.refresh        = 60,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 25000,
+		.left_margin    = 40,
+		.right_margin   = 88,
+		.upper_margin   = 33,
+		.lower_margin   = 10,
+		.hsync_len      = 128,
+		.vsync_len      = 2,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+	/* Turn on LDB0,IPU,IPU DI0 clocks */
+	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+	      |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	     |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+	     |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+	     |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+	     |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+			|IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+
+	/* backlight unconditionally on for now */
+	imx_iomux_v3_setup_multiple_pads(backlight_pads,
+					 ARRAY_SIZE(backlight_pads));
+	/* use 0 for EDT 7", use 1 for LG fullHD panel */
+	gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
+	gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+}
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
+	gpio_direction_output(RGB_BACKLIGHT_GP, 0);
+}
+#endif /* defined(CONFIG_VIDEO_IPUV3) */
+
+int board_early_init_f(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
+					 ARRAY_SIZE(pwr_intb_pads));
+	setup_iomux_uart();
+
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#if defined(CONFIG_FEC_MXC)
+	setup_fec();
+#endif
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+
+#ifdef CONFIG_TDX_CMD_IMX_MFGR
+	(void) pmic_init();
+#endif
+
+#ifdef CONFIG_SATA
+	setup_sata();
+#endif
+
+	setup_iomux_gpio();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if defined(CONFIG_REVISION_TAG) && \
+    defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+	char env_str[256];
+	u32 rev;
+
+	rev = get_board_rev();
+	snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
+	env_set("board_rev", env_str);
+#endif
+
+#ifdef CONFIG_CMD_USB_SDP
+	if (is_boot_from_usb()) {
+		printf("Serial Downloader recovery mode, using sdp command\n");
+		env_set("bootdelay", "0");
+		env_set("bootcmd", "sdp 0");
+	}
+#endif /* CONFIG_CMD_USB_SDP */
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+int checkboard(void)
+{
+	char it[] = " IT";
+	int minc, maxc;
+
+	switch (get_cpu_temp_grade(&minc, &maxc)) {
+	case TEMP_AUTOMOTIVE:
+	case TEMP_INDUSTRIAL:
+		break;
+	case TEMP_EXTCOMMERCIAL:
+	default:
+		it[0] = 0;
+	};
+	printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
+	       is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
+	       (gd->ram_size == 0x20000000) ? "512" : "256", it);
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u32 cma_size;
+
+	ft_common_board_setup(blob, bd);
+
+	cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
+	cma_size = min((u32)(gd->ram_size >> 1), cma_size);
+
+	fdt_setprop_u32(blob,
+			fdt_path_offset(blob, "/reserved-memory/linux,cma"),
+			"size",
+			cma_size);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	{"mmc",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{NULL,	0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+/* TODO, use external pmic, for now always ldo_enable */
+void ldo_mode_set(int ldo_bypass)
+{
+	return;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <linux/libfdt.h>
+#include "asm/arch/mx6dl-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+static int mx6s_dcd_table[] = {
+/* ddr-setup.cfg */
+
+MX6_IOM_DRAM_SDQS0, 0x00000030,
+MX6_IOM_DRAM_SDQS1, 0x00000030,
+MX6_IOM_DRAM_SDQS2, 0x00000030,
+MX6_IOM_DRAM_SDQS3, 0x00000030,
+MX6_IOM_DRAM_SDQS4, 0x00000030,
+MX6_IOM_DRAM_SDQS5, 0x00000030,
+MX6_IOM_DRAM_SDQS6, 0x00000030,
+MX6_IOM_DRAM_SDQS7, 0x00000030,
+
+MX6_IOM_GRP_B0DS, 0x00000030,
+MX6_IOM_GRP_B1DS, 0x00000030,
+MX6_IOM_GRP_B2DS, 0x00000030,
+MX6_IOM_GRP_B3DS, 0x00000030,
+MX6_IOM_GRP_B4DS, 0x00000030,
+MX6_IOM_GRP_B5DS, 0x00000030,
+MX6_IOM_GRP_B6DS, 0x00000030,
+MX6_IOM_GRP_B7DS, 0x00000030,
+MX6_IOM_GRP_ADDDS, 0x00000030,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_CTLDS, 0x00000030,
+
+MX6_IOM_DRAM_DQM0, 0x00020030,
+MX6_IOM_DRAM_DQM1, 0x00020030,
+MX6_IOM_DRAM_DQM2, 0x00020030,
+MX6_IOM_DRAM_DQM3, 0x00020030,
+MX6_IOM_DRAM_DQM4, 0x00020030,
+MX6_IOM_DRAM_DQM5, 0x00020030,
+MX6_IOM_DRAM_DQM6, 0x00020030,
+MX6_IOM_DRAM_DQM7, 0x00020030,
+
+MX6_IOM_DRAM_CAS, 0x00020030,
+MX6_IOM_DRAM_RAS, 0x00020030,
+MX6_IOM_DRAM_SDCLK_0, 0x00020030,
+MX6_IOM_DRAM_SDCLK_1, 0x00020030,
+
+MX6_IOM_DRAM_RESET, 0x00020030,
+MX6_IOM_DRAM_SDCKE0, 0x00003000,
+MX6_IOM_DRAM_SDCKE1, 0x00003000,
+
+MX6_IOM_DRAM_SDODT0, 0x00003030,
+MX6_IOM_DRAM_SDODT1, 0x00003030,
+
+/* (differential input) */
+MX6_IOM_DDRMODE_CTL, 0x00020000,
+/* (differential input) */
+MX6_IOM_GRP_DDRMODE, 0x00020000,
+/* disable ddr pullups */
+MX6_IOM_GRP_DDRPKE, 0x00000000,
+MX6_IOM_DRAM_SDBA2, 0x00000000,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+
+/* Read data DQ Byte0-3 delay */
+MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+/* TODO: check what the RALAT field does */
+MX6_MMDC_P0_MDMISC, 0x00081740,
+
+/*
+ * MDSCR	con_req
+ */
+MX6_MMDC_P0_MDSCR, 0x00008000,
+
+
+/* 800mhz_2x64mx16.cfg */
+
+MX6_MMDC_P0_MDPDC, 0x0002002D,
+MX6_MMDC_P0_MDCFG0, 0x2C305503,
+MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
+MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+MX6_MMDC_P0_MDRWD, 0x000026D2,
+MX6_MMDC_P0_MDOR, 0x00301023,
+MX6_MMDC_P0_MDOTC, 0x00333030,
+MX6_MMDC_P0_MDPDC, 0x0002556D,
+/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
+MX6_MMDC_P0_MDASP, 0x00000017,
+/* DDR3 DATA BUS SIZE: 64BIT */
+/* MX6_MMDC_P0_MDCTL, 0x821A0000, */
+/* DDR3 DATA BUS SIZE: 32BIT */
+MX6_MMDC_P0_MDCTL, 0x82190000,
+
+/* Write commands to DDR */
+/* Load Mode Registers */
+/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
+/* MX6_MMDC_P0_MDSCR, 0x04408032, */
+MX6_MMDC_P0_MDSCR, 0x04008032,
+MX6_MMDC_P0_MDSCR, 0x00008033,
+MX6_MMDC_P0_MDSCR, 0x00048031,
+MX6_MMDC_P0_MDSCR, 0x13208030,
+/* ZQ calibration */
+MX6_MMDC_P0_MDSCR, 0x04008040,
+
+MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P0_MDREF, 0x00005800,
+
+MX6_MMDC_P0_MPODTCTRL, 0x00000000,
+MX6_MMDC_P1_MPODTCTRL, 0x00000000,
+
+MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
+MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
+MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
+MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
+
+MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
+MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
+MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
+MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
+
+MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
+MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
+MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
+MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
+
+MX6_MMDC_P0_MPMUR0, 0x00000800,
+MX6_MMDC_P1_MPMUR0, 0x00000800,
+MX6_MMDC_P0_MDSCR, 0x00000000,
+MX6_MMDC_P0_MAPSR, 0x00011006,
+};
+
+static int mx6dl_dcd_table[] = {
+/* ddr-setup.cfg */
+
+MX6_IOM_DRAM_SDQS0, 0x00000030,
+MX6_IOM_DRAM_SDQS1, 0x00000030,
+MX6_IOM_DRAM_SDQS2, 0x00000030,
+MX6_IOM_DRAM_SDQS3, 0x00000030,
+MX6_IOM_DRAM_SDQS4, 0x00000030,
+MX6_IOM_DRAM_SDQS5, 0x00000030,
+MX6_IOM_DRAM_SDQS6, 0x00000030,
+MX6_IOM_DRAM_SDQS7, 0x00000030,
+
+MX6_IOM_GRP_B0DS, 0x00000030,
+MX6_IOM_GRP_B1DS, 0x00000030,
+MX6_IOM_GRP_B2DS, 0x00000030,
+MX6_IOM_GRP_B3DS, 0x00000030,
+MX6_IOM_GRP_B4DS, 0x00000030,
+MX6_IOM_GRP_B5DS, 0x00000030,
+MX6_IOM_GRP_B6DS, 0x00000030,
+MX6_IOM_GRP_B7DS, 0x00000030,
+MX6_IOM_GRP_ADDDS, 0x00000030,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_CTLDS, 0x00000030,
+
+MX6_IOM_DRAM_DQM0, 0x00020030,
+MX6_IOM_DRAM_DQM1, 0x00020030,
+MX6_IOM_DRAM_DQM2, 0x00020030,
+MX6_IOM_DRAM_DQM3, 0x00020030,
+MX6_IOM_DRAM_DQM4, 0x00020030,
+MX6_IOM_DRAM_DQM5, 0x00020030,
+MX6_IOM_DRAM_DQM6, 0x00020030,
+MX6_IOM_DRAM_DQM7, 0x00020030,
+
+MX6_IOM_DRAM_CAS, 0x00020030,
+MX6_IOM_DRAM_RAS, 0x00020030,
+MX6_IOM_DRAM_SDCLK_0, 0x00020030,
+MX6_IOM_DRAM_SDCLK_1, 0x00020030,
+
+MX6_IOM_DRAM_RESET, 0x00020030,
+MX6_IOM_DRAM_SDCKE0, 0x00003000,
+MX6_IOM_DRAM_SDCKE1, 0x00003000,
+
+MX6_IOM_DRAM_SDODT0, 0x00003030,
+MX6_IOM_DRAM_SDODT1, 0x00003030,
+
+/* (differential input) */
+MX6_IOM_DDRMODE_CTL, 0x00020000,
+/* (differential input) */
+MX6_IOM_GRP_DDRMODE, 0x00020000,
+/* disable ddr pullups */
+MX6_IOM_GRP_DDRPKE, 0x00000000,
+MX6_IOM_DRAM_SDBA2, 0x00000000,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+
+/* Read data DQ Byte0-3 delay */
+MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+/* TODO: check what the RALAT field does */
+MX6_MMDC_P0_MDMISC, 0x00081740,
+
+/*
+ * MDSCR	con_req
+ */
+MX6_MMDC_P0_MDSCR, 0x00008000,
+
+
+/* 800mhz_2x64mx16.cfg */
+
+MX6_MMDC_P0_MDPDC, 0x0002002D,
+MX6_MMDC_P0_MDCFG0, 0x2C305503,
+MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
+MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+MX6_MMDC_P0_MDRWD, 0x000026D2,
+MX6_MMDC_P0_MDOR, 0x00301023,
+MX6_MMDC_P0_MDOTC, 0x00333030,
+MX6_MMDC_P0_MDPDC, 0x0002556D,
+/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
+MX6_MMDC_P0_MDASP, 0x00000017,
+/* DDR3 DATA BUS SIZE: 64BIT */
+MX6_MMDC_P0_MDCTL, 0x821A0000,
+/* DDR3 DATA BUS SIZE: 32BIT */
+/* MX6_MMDC_P0_MDCTL, 0x82190000, */
+
+/* Write commands to DDR */
+/* Load Mode Registers */
+/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
+/* MX6_MMDC_P0_MDSCR, 0x04408032, */
+MX6_MMDC_P0_MDSCR, 0x04008032,
+MX6_MMDC_P0_MDSCR, 0x00008033,
+MX6_MMDC_P0_MDSCR, 0x00048031,
+MX6_MMDC_P0_MDSCR, 0x13208030,
+/* ZQ calibration */
+MX6_MMDC_P0_MDSCR, 0x04008040,
+
+MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P0_MDREF, 0x00005800,
+
+MX6_MMDC_P0_MPODTCTRL, 0x00000000,
+MX6_MMDC_P1_MPODTCTRL, 0x00000000,
+
+MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
+MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
+MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
+MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
+
+MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
+MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
+MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
+MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
+
+MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
+MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
+MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
+MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
+
+MX6_MMDC_P0_MPMUR0, 0x00000800,
+MX6_MMDC_P1_MPMUR0, 0x00000800,
+MX6_MMDC_P0_MDSCR, 0x00000000,
+MX6_MMDC_P0_MAPSR, 0x00011006,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFFFF3, &ccm->CCGR2);
+	writel(0x3FF0300F, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000F3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+	writel(0x000000FB, &ccm->ccosr);
+}
+
+static void ddr_init(int *table, int size)
+{
+	int i;
+
+	for (i = 0; i < size / 2 ; i++)
+		writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+	int minc, maxc;
+
+	switch (get_cpu_temp_grade(&minc, &maxc)) {
+	case TEMP_COMMERCIAL:
+	case TEMP_EXTCOMMERCIAL:
+		if (is_cpu_type(MXC_CPU_MX6DL)) {
+			puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
+			ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+		} else {
+			puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
+			ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
+		}
+		break;
+	case TEMP_INDUSTRIAL:
+	case TEMP_AUTOMOTIVE:
+	default:
+		if (is_cpu_type(MXC_CPU_MX6DL)) {
+			puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
+			ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+		} else {
+			puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
+			ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
+		}
+		break;
+	};
+	udelay(100);
+}
+
+static iomux_v3_cfg_t const gpio_reset_pad[] = {
+	MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+					MUX_MODE_SION
+#define GPIO_NRESET IMX_GPIO_NR(6, 27)
+};
+
+#define IMX_RESET_CAUSE_POR 0x00011
+static void nreset_out(void)
+{
+	int reset_cause = get_imx_reset_cause();
+
+	if (reset_cause != IMX_RESET_CAUSE_POR) {
+		imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
+						 ARRAY_SIZE(gpio_reset_pad));
+		gpio_direction_output(GPIO_NRESET, 1);
+		udelay(100);
+		gpio_direction_output(GPIO_NRESET, 0);
+	}
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* iomux */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* Make sure we use dte mode */
+	setup_dtemode_uart();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* Assert nReset_Out */
+	nreset_out();
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+void reset_cpu(void)
+{
+}
+
+#endif /* CONFIG_SPL_BUILD */
+
+static struct mxc_serial_plat mxc_serial_plat = {
+	.reg = (struct mxc_uart *)UART1_BASE,
+	.use_dte = true,
+};
+
+U_BOOT_DRVINFO(mxc_serial) = {
+	.name = "serial_mxc",
+	.plat = &mxc_serial_plat,
+};
diff --git a/roms/u-boot/board/toradex/colibri_imx6/do_fuse.c b/roms/u-boot/board/toradex/colibri_imx6/do_fuse.c
new file mode 100644
index 000000000..6991b1bc1
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx6/do_fuse.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ */
+
+/*
+ * Helpers for i.MX OTP fusing during module production
+*/
+
+#include <common.h>
+#ifndef CONFIG_SPL_BUILD
+#include <command.h>
+#include <console.h>
+#include <fuse.h>
+
+static int mfgr_fuse(void)
+{
+	unsigned val, val6;
+
+	fuse_sense(0, 5, &val);
+	printf("Fuse 0, 5: %8x\n", val);
+	fuse_sense(0, 6, &val6);
+	printf("Fuse 0, 6: %8x\n", val6);
+	fuse_sense(4, 3, &val);
+	printf("Fuse 4, 3: %8x\n", val);
+	fuse_sense(4, 2, &val);
+	printf("Fuse 4, 2: %8x\n", val);
+	if (val6 & 0x10) {
+		puts("BT_FUSE_SEL already fused, will do nothing\n");
+		return CMD_RET_FAILURE;
+	}
+	/* boot cfg */
+	fuse_prog(0, 5, 0x00005062);
+	/* BT_FUSE_SEL */
+	fuse_prog(0, 6, 0x00000010);
+	return CMD_RET_SUCCESS;
+}
+
+int do_mfgr_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
+		 char *const argv[])
+{
+	int ret;
+	puts("Fusing...\n");
+	ret = mfgr_fuse();
+	if (ret == CMD_RET_SUCCESS)
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return ret;
+}
+
+int do_updt_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
+		 char *const argv[])
+{
+	unsigned val;
+	int ret;
+	int confirmed = argc >= 1 && !strcmp(argv[1], "-y");
+
+	/* can be used in scripts for command availability check */
+	if (argc >= 1 && !strcmp(argv[1], "-n"))
+		return CMD_RET_SUCCESS;
+
+	/* boot cfg */
+	fuse_sense(0, 5, &val);
+	printf("Fuse 0, 5: %8x\n", val);
+	if (val & 0x10) {
+		puts("Fast boot mode already fused, no need to fuse\n");
+		return CMD_RET_SUCCESS;
+	}
+	if (!confirmed) {
+		puts("Warning: Programming fuses is an irreversible operation!\n"
+				"         Updating to fast boot mode prevents easy\n"
+				"         downgrading to previous BSP versions.\n"
+				"\nReally perform this fuse programming? <y/N>\n");
+		if (!confirm_yesno())
+			return CMD_RET_FAILURE;
+	}
+	puts("Fusing fast boot mode...\n");
+	ret = fuse_prog(0, 5, 0x00005072);
+	if (ret == CMD_RET_SUCCESS)
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return ret;
+}
+
+U_BOOT_CMD(
+	mfgr_fuse, 1, 0, do_mfgr_fuse,
+	"OTP fusing during module production",
+	""
+);
+
+U_BOOT_CMD(
+	updt_fuse, 2, 0, do_updt_fuse,
+	"OTP fusing during module update",
+	"updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
+);
+#endif /* CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/toradex/colibri_imx6/pf0100.c b/roms/u-boot/board/toradex/colibri_imx6/pf0100.c
new file mode 100644
index 000000000..8f08d8c73
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx6/pf0100.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014-2019, Toradex AG
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <linux/delay.h>
+
+#include "pf0100_otp.inc"
+#include "pf0100.h"
+
+/* define for PMIC register dump */
+/*#define DEBUG */
+
+#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n"
+
+/* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */
+static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
+	MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#	define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3)
+};
+
+unsigned pmic_init(void)
+{
+	int rc;
+	struct udevice *dev = NULL;
+	unsigned programmed = 0;
+	uchar bus = 1;
+	uchar devid, revid, val;
+
+	puts("PMIC:  ");
+	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
+	if (rc) {
+		printf("failed to get device for PMIC at address 0x%x\n",
+		       PFUZE100_I2C_ADDR);
+		return 0;
+	}
+
+	/* check for errors in PMIC fuses */
+	if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) {
+		puts("i2c pmic INTSTAT3 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BIT_OTP_ECCI) {
+		puts("\n" WARNBAR);
+		puts("WARNING: ecc errors found in pmic fuse banks\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) {
+		puts("i2c pmic ECC_SE1 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_SE1) {
+		puts(WARNBAR);
+		puts("WARNING: ecc has made bit corrections in banks 1 to 5\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) {
+		puts("i2c pmic ECC_SE2 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_SE2) {
+		puts(WARNBAR);
+		puts("WARNING: ecc has made bit corrections in banks 6 to 10\n"
+		    );
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) {
+		puts("i2c pmic ECC_DE register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_DE1) {
+		puts(WARNBAR);
+		puts("ERROR: banks 1 to 5 have uncorrectable bits\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) {
+		puts("i2c pmic ECC_DE register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_DE2) {
+		puts(WARNBAR);
+		puts("ERROR: banks 6 to 10 have uncorrectable bits\n");
+		puts(WARNBAR);
+	}
+
+	/* get device ident */
+	if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) {
+		puts("i2c pmic devid read failed\n");
+		return 0;
+	}
+	if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) {
+		puts("i2c pmic revid read failed\n");
+		return 0;
+	}
+	printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid);
+
+	/* get device programmed state */
+	val = PFUZE100_PAGE_REGISTER_PAGE1;
+	if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+		puts("i2c write failed\n");
+		return 0;
+	}
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return programmed;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return programmed;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	switch (programmed) {
+	case 0:
+		puts("not programmed\n");
+		break;
+	case 3:
+		puts("programmed\n");
+		break;
+	default:
+		puts("undefined programming state\n");
+		break;
+	}
+
+#ifdef DEBUG
+	{
+		unsigned int i, j;
+
+		for (i = 0; i < 16; i++)
+			printf("\t%x", i);
+		for (j = 0; j < 0x80; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 1");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE1;
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 2");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE2;
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\n");
+	}
+#endif /* DEBUG */
+
+	return programmed;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int pf0100_prog(void)
+{
+	int rc;
+	struct udevice *dev = NULL;
+	unsigned char bus = 1;
+	unsigned char val;
+	unsigned int i;
+
+	if (pmic_init() == 3) {
+		puts("PMIC already programmed, exiting\n");
+		return CMD_RET_FAILURE;
+	}
+	/* set up gpio to manipulate vprog, initially off */
+	imx_iomux_v3_setup_multiple_pads(pmic_prog_pads,
+					 ARRAY_SIZE(pmic_prog_pads));
+	gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
+
+	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
+	if (rc) {
+		printf("failed to get device for PMIC at address 0x%x\n",
+		       PFUZE100_I2C_ADDR);
+		return CMD_RET_FAILURE;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) {
+		switch (pmic_otp_prog[i].cmd) {
+		case pmic_i2c:
+			val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
+			if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) {
+				printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
+				       pmic_otp_prog[i].reg, val);
+				return CMD_RET_FAILURE;
+			}
+			break;
+		case pmic_delay:
+			udelay(pmic_otp_prog[i].value * 1000);
+			break;
+		case pmic_vpgm:
+			gpio_direction_output(PMIC_PROG_VOLTAGE,
+					      pmic_otp_prog[i].value);
+			break;
+		case pmic_pwr:
+			/* TODO */
+			break;
+		}
+	}
+	return CMD_RET_SUCCESS;
+}
+
+static int do_pf0100_prog(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	int ret;
+	puts("Programming PMIC OTP...");
+	ret = pf0100_prog();
+	if (ret == CMD_RET_SUCCESS)
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return ret;
+}
+
+U_BOOT_CMD(
+	pf0100_otp_prog, 1, 0, do_pf0100_prog,
+	"Program the OTP fuses on the PMIC PF0100",
+	""
+);
+#endif /* CONFIG_SPL_BUILD */
diff --git a/roms/u-boot/board/toradex/colibri_imx6/pf0100.h b/roms/u-boot/board/toradex/colibri_imx6/pf0100.h
new file mode 100644
index 000000000..925762051
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx6/pf0100.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014-2019, Toradex AG
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#ifndef PF0100_H_
+#define PF0100_H_
+
+/* bit definitions */
+#define PFUZE100_BIT_0			(0x01 << 0)
+#define PFUZE100_BIT_1			(0x01 << 1)
+#define PFUZE100_BIT_2			(0x01 << 2)
+#define PFUZE100_BIT_3			(0x01 << 3)
+#define PFUZE100_BIT_4			(0x01 << 4)
+#define PFUZE100_BIT_5			(0x01 << 5)
+#define PFUZE100_BIT_6			(0x01 << 6)
+#define PFUZE100_BIT_7			(0x01 << 7)
+
+/* 7-bit I2C bus slave address */
+#define PFUZE100_I2C_ADDR		(0x08)
+/* Register Addresses */
+#define PFUZE100_DEVICEID		(0x0)
+#define PFUZE100_REVID			(0x3)
+#define PFUZE100_INTSTAT3		(0xe)
+#define PFUZE100_BIT_OTP_ECCI		PFUZE100_BIT_7
+#define PFUZE100_SW1AMODE		(0x23)
+#define PFUZE100_SW1ACON		36
+#define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1CCON		49
+#define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1AVOL		32
+#define PFUZE100_SW1AVOL_VSEL_M		(0x3f<<0)
+#define PFUZE100_SW1CVOL		46
+#define PFUZE100_SW1CVOL_VSEL_M		(0x3f<<0)
+#define PFUZE100_VGEN1CTL		(0x6c)
+#define PFUZE100_VGEN1_VAL		(0x30 + 0x08) /* Always ON, 1.2V */
+#define PFUZE100_SWBSTCTL		(0x66)
+/* Always ON, Auto Switching Mode, 5.0V */
+#define PFUZE100_SWBST_VAL		(0x40 + 0x08 + 0x00)
+
+/* chooses the extended page (registers 0x80..0xff) */
+#define PFUZE100_PAGE_REGISTER		0x7f
+#define PFUZE100_PAGE_REGISTER_PAGE_M	(0x1f << 0)
+#define PFUZE100_PAGE_REGISTER_PAGE1	(0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
+#define PFUZE100_PAGE_REGISTER_PAGE2	(0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
+
+/* extended page 1 */
+#define PFUZE100_OTP_ECC_SE1		0x8a
+#define PFUZE100_BIT_ECC1_SE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC2_SE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC3_SE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC4_SE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC5_SE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_SE1		((PFUZE100_BIT_ECC1_SE) | \
+					(PFUZE100_BIT_ECC2_SE) | \
+					(PFUZE100_BIT_ECC3_SE) | \
+					(PFUZE100_BIT_ECC4_SE) | \
+					(PFUZE100_BIT_ECC5_SE))
+#define PFUZE100_OTP_ECC_SE2		0x8b
+#define PFUZE100_BIT_ECC6_SE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC7_SE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC8_SE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC9_SE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC10_SE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_SE2		((PFUZE100_BIT_ECC6_SE) | \
+					(PFUZE100_BIT_ECC7_SE) | \
+					(PFUZE100_BIT_ECC8_SE) | \
+					(PFUZE100_BIT_ECC9_SE) | \
+					(PFUZE100_BIT_ECC10_SE))
+#define PFUZE100_OTP_ECC_DE1		0x8c
+#define PFUZE100_BIT_ECC1_DE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC2_DE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC3_DE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC4_DE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC5_DE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_DE1		((PFUZE100_BIT_ECC1_DE) | \
+					(PFUZE100_BIT_ECC2_DE) | \
+					(PFUZE100_BIT_ECC3_DE) | \
+					(PFUZE100_BIT_ECC4_DE) | \
+					(PFUZE100_BIT_ECC5_DE))
+#define PFUZE100_OTP_ECC_DE2		0x8d
+#define PFUZE100_BIT_ECC6_DE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC7_DE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC8_DE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC9_DE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC10_DE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_DE2		((PFUZE100_BIT_ECC6_DE) | \
+					(PFUZE100_BIT_ECC7_DE) | \
+					(PFUZE100_BIT_ECC8_DE) | \
+					(PFUZE100_BIT_ECC9_DE) | \
+					(PFUZE100_BIT_ECC10_DE))
+#define PFUZE100_FUSE_POR1		0xe4
+#define PFUZE100_FUSE_POR2		0xe5
+#define PFUZE100_FUSE_POR3		0xe6
+#define PFUZE100_FUSE_POR_M		(0x1 << 1)
+
+/* output some informational messages, return the number FUSE_POR=1 */
+/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
+unsigned pmic_init(void);
+
+#endif /* PF0100_H_ */
diff --git a/roms/u-boot/board/toradex/colibri_imx6/pf0100_otp.inc b/roms/u-boot/board/toradex/colibri_imx6/pf0100_otp.inc
new file mode 100644
index 000000000..c3b1f67f8
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx6/pf0100_otp.inc
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ */
+
+// Register Output for PF0100 programmer
+// Customer: Toradex AG
+// Program: Colibri iMX6 V1.1
+// Sample marking:
+// Date: 01.05.2017
+// Time: 16:22:32
+// Generated from Spreadsheet Revision: P1.8
+
+/* sed commands to get from programmer script to struct content */
+/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc
+   sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
+   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc
+*/
+
+enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
+struct pmic_otp_prog_t{
+	unsigned char cmd;
+	unsigned char reg;
+	unsigned short value;
+};
+
+struct pmic_otp_prog_t pmic_otp_prog[] = {
+{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
+{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
+{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
+{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
+{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
+{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
+{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
+{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
+{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
+{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
+{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
+{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
+{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
+{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
+{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
+{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
+{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
+{pmic_i2c, 0xBD, 0x0E}, // Auto gen from Row123
+{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
+{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
+{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
+{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
+{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
+{pmic_i2c, 0xD0, 0x0F}, // Auto gen from Row142
+{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
+{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
+{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
+{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
+{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
+{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
+{pmic_i2c, 0xE0, 0x05}, // Auto gen from Row158
+
+#if 0 /* TBB mode */
+{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
+{pmic_delay, 0, 10},
+#else
+// Write OTP
+{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
+{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
+{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
+{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
+{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
+{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
+{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
+{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
+//VPGM:DOWN:n
+//VPGM:UP:n
+{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
+//-----------------------------------------------------------------------------------
+// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
+//-----------------------------------------------------------------------------------
+// BANK 1
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 2
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 3
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 4
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 5
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 6
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 7
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 8
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 9
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 10
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
+{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
+{pmic_i2c, 0xD0, 0x00}, // Clear
+{pmic_i2c, 0xD1, 0x00}, // Clear
+{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
+{pmic_delay, 0, 500},
+{pmic_pwr, 0, 1},
+#endif
+};
diff --git a/roms/u-boot/board/toradex/colibri_imx7/Kconfig b/roms/u-boot/board/toradex/colibri_imx7/Kconfig
new file mode 100644
index 000000000..d33ec6352
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx7/Kconfig
@@ -0,0 +1,76 @@
+if TARGET_COLIBRI_IMX7
+
+choice
+	prompt "Colibri iMX7S/D variant"
+
+config TARGET_COLIBRI_IMX7_NAND
+	bool "Support Colibri iMX7 Solo 256MB/Dual 512MB (raw NAND) modules"
+	imply NAND_MXS
+	help
+	  Choose this option if you build for a Toradex Colibri iMX7S
+	  256MB or Colibri iMX7D 512MB module which do have raw NAND
+	  on-module.
+
+config TARGET_COLIBRI_IMX7_EMMC
+	bool "Support Colibri iMX7 Dual 1GB (eMMC) modules"
+	help
+	  Choose this option if you build for a Toradex Colibri iMX7D
+	  1GB module which does have eMMC on-module.
+
+endchoice
+
+config SYS_BOARD
+	default "colibri_imx7"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "colibri_imx7"
+
+config COLIBRI_IMX7_EXT_PHYCLK
+	bool "External oscillator for Ethernet PHY clock provided"
+	help
+	  Select this if your module provides a external Ethernet PHY
+	  clock source.
+	default y
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	default y
+
+if TARGET_COLIBRI_IMX7_NAND
+
+config TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "2048"
+
+config TDX_CFG_BLOCK_OFFSET2
+	default "133120"
+
+endif
+
+if TARGET_COLIBRI_IMX7_EMMC
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+endif
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/colibri_imx7/MAINTAINERS b/roms/u-boot/board/toradex/colibri_imx7/MAINTAINERS
new file mode 100644
index 000000000..3d7d010d8
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx7/MAINTAINERS
@@ -0,0 +1,14 @@
+Colibri iMX7
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+W:	https://www.toradex.com/community
+S:	Maintained
+F:	board/toradex/colibri_imx7/
+F:	doc/board/toradex/colibri_imx7.rst
+F:	include/configs/colibri_imx7.h
+F:	configs/colibri_imx7_defconfig
+F:	configs/colibri_imx7_emmc_defconfig
+F:	arch/arm/dts/imx7-colibri.dtsi
+F:	arch/arm/dts/imx7-colibri-u-boot.dtsi
+F:	arch/arm/dts/imx7-colibri-emmc.dts
+F:	arch/arm/dts/imx7-colibri-rawnand.dts
diff --git a/roms/u-boot/board/toradex/colibri_imx7/Makefile b/roms/u-boot/board/toradex/colibri_imx7/Makefile
new file mode 100644
index 000000000..b212ff0f2
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx7/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2016 Toradex AG
+
+obj-y  := colibri_imx7.o
diff --git a/roms/u-boot/board/toradex/colibri_imx7/colibri_imx7.c b/roms/u-boot/board/toradex/colibri_imx7/colibri_imx7.c
new file mode 100644
index 000000000..301b07d5b
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx7/colibri_imx7.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016-2018 Toradex AG
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <fdt_support.h>
+#include <fsl_esdhc_imx.h>
+#include <jffs2/load_kernel.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <mtd_node.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/rn5t567_pmic.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include "../common/tdx-common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
+	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+#define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
+	PAD_CTL_DSE_3P3V_49OHM)
+
+#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
+
+#define USB_CDET_GPIO	IMX_GPIO_NR(7, 14)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#ifdef CONFIG_USB_EHCI_MX7
+static iomux_v3_cfg_t const usb_cdet_pads[] = {
+	MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_CLK__NAND_CLE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_CMD__NAND_ALE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_STROBE__NAND_RE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_RESET_B__NAND_WE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+	/* NAND_USDHC_BUS_CLK is set in rom */
+	set_clk_nand();
+}
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+static iomux_v3_cfg_t const backlight_pads[] = {
+	/* Backlight On */
+	MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* Backlight PWM<A> (multiplexed pin) */
+	MX7D_PAD_GPIO1_IO08__GPIO1_IO8   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define GPIO_BL_ON IMX_GPIO_NR(5, 1)
+#define GPIO_PWM_A IMX_GPIO_NR(1, 8)
+
+static int setup_lcd(void)
+{
+	imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
+
+	/* Set BL_ON */
+	gpio_request(GPIO_BL_ON, "BL_ON");
+	gpio_direction_output(GPIO_BL_ON, 1);
+
+	/* Set PWM<A> to full brightness (assuming inversed polarity) */
+	gpio_request(GPIO_PWM_A, "PWM<A>");
+	gpio_direction_output(GPIO_PWM_A, 0);
+
+	return 0;
+}
+#endif
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+#ifdef CONFIG_DM_VIDEO
+	gpio_direction_output(GPIO_PWM_A, 1);
+	gpio_direction_output(GPIO_BL_ON, 0);
+#endif
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
+	/*
+	 * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
+	 * and output it on the pin
+	 */
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
+			IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
+#else
+	/* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
+			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
+#endif
+
+	return set_clk_enet(ENET_50MHZ);
+}
+
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX7
+	imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
+	gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int reg, ver;
+	int ret;
+
+
+	ret = pmic_get("rn5t567@33", &dev);
+	if (ret)
+		return ret;
+	ver = pmic_reg_read(dev, RN5T567_LSIVER);
+	reg = pmic_reg_read(dev, RN5T567_OTPVER);
+
+	printf("PMIC:  RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
+
+	/* set judge and press timer of N_OE to minimal values */
+	pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
+
+	/* configure sleep slot for 3.3V Ethernet */
+	reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
+	reg = (reg & 0xf0) | reg >> 4;
+	pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
+
+	/* disable DCDC2 discharge to avoid backfeeding through VFB2 */
+	pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
+
+	/* configure sleep slot for ARM rail */
+	reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
+	reg = (reg & 0xf0) | reg >> 4;
+	pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
+
+	/* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
+	pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	struct udevice *dev;
+
+	pmic_get("rn5t567@33", &dev);
+
+	/* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
+	pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
+	pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
+
+	/*
+	 * Re-power factor detection on PMIC side is not instant. 1ms
+	 * proved to be enough time until reset takes effect.
+	 */
+	mdelay(1);
+}
+#endif
+
+int checkboard(void)
+{
+	printf("Model: Toradex Colibri iMX7%c\n",
+	       is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
+	int up;
+
+	up = arch_auxiliary_core_check_up(0);
+	if (up) {
+		int ret;
+		int areas = 1;
+		u64 start[2], size[2];
+
+		/*
+		 * Reserve 1MB of memory for M4 (1MiB is also the minimum
+		 * alignment for Linux due to MMU section size restrictions).
+		 */
+		start[0] = gd->bd->bi_dram[0].start;
+		size[0] = SZ_256M - SZ_1M;
+
+		/* If needed, create a second entry for memory beyond 256M */
+		if (gd->bd->bi_dram[0].size > SZ_256M) {
+			start[1] = gd->bd->bi_dram[0].start + SZ_256M;
+			size[1] = gd->bd->bi_dram[0].size - SZ_256M;
+			areas = 2;
+		}
+
+		ret = fdt_set_usable_memory(blob, start, size, areas);
+		if (ret) {
+			eprintf("Cannot set usable memory\n");
+			return ret;
+		}
+	} else {
+		int off;
+
+		off = fdt_node_offset_by_compatible(blob, -1,
+						    "fsl,imx7d-rpmsg");
+		if (off > 0)
+			fdt_status_disabled(blob, off);
+	}
+#endif
+#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
+	static const struct node_info nodes[] = {
+		{ "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+		{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
+	};
+
+	/* Update partition nodes using info from mtdparts env var */
+	puts("   Updating MTD partitions...\n");
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX7
+static iomux_v3_cfg_t const usb_otg2_pads[] = {
+	MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+	switch (port) {
+	case 0:
+		break;
+	case 1:
+		if (is_cpu_type(MXC_CPU_MX7S))
+			return -ENODEV;
+
+		imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
+						 ARRAY_SIZE(usb_otg2_pads));
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+int board_usb_phy_mode(int port)
+{
+	switch (port) {
+	case 0:
+		if (gpio_get_value(USB_CDET_GPIO))
+			return USB_INIT_DEVICE;
+		else
+			return USB_INIT_HOST;
+	case 1:
+	default:
+		return USB_INIT_HOST;
+	}
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_DM_VIDEO)
+	setup_lcd();
+#endif
+	return 0;
+}
+
+#endif
diff --git a/roms/u-boot/board/toradex/colibri_imx7/imximage.cfg b/roms/u-boot/board/toradex/colibri_imx7/imximage.cfg
new file mode 100644
index 000000000..bdce48b7f
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_imx7/imximage.cfg
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *               2015 Toradex AG
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : sd
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* IOMUXC_GPR_GPR1 */
+DATA 4 0x30340004 0x4F400005
+
+/* DDR3L */
+/* assuming MEMC_FREQ_RATIO = 2 */
+/* SRC_DDRC_RCR */
+DATA 4 0x30391000 0x00000002
+/* DDRC_MSTR */
+DATA 4 0x307a0000 0x01040001
+/* DDRC_DFIUPD0 */
+DATA 4 0x307a01a0 0x80400003
+/* DDRC_DFIUPD1 */
+DATA 4 0x307a01a4 0x00100020
+/* DDRC_DFIUPD2 */
+DATA 4 0x307a01a8 0x80100004
+/* DDRC_RFSHTMG */
+DATA 4 0x307a0064 0x00400046
+/* DDRC_MP_PCTRL_0 */
+DATA 4 0x307a0490 0x00000001
+/* DDRC_INIT0 */
+DATA 4 0x307a00d0 0x00020083
+/* DDRC_INIT1 */
+DATA 4 0x307a00d4 0x00690000
+/* DDRC_INIT3 MR0/MR1 */
+DATA 4 0x307a00dc 0x09300004
+/* DDRC_INIT4 MR2/MR3 */
+DATA 4 0x307a00e0 0x04480000
+/* DDRC_INIT5 */
+DATA 4 0x307a00e4 0x00100004
+/* DDRC_RANKCTL */
+DATA 4 0x307a00f4 0x0000033f
+/* DDRC_DRAMTMG0 */
+DATA 4 0x307a0100 0x0910090a
+/* DDRC_DRAMTMG1 */
+DATA 4 0x307a0104 0x000d020e
+/* DDRC_DRAMTMG2 */
+DATA 4 0x307a0108 0x03040307
+/* DDRC_DRAMTMG3 */
+DATA 4 0x307a010c 0x00002006
+/* DDRC_DRAMTMG4 */
+DATA 4 0x307a0110 0x04020204
+/* DDRC_DRAMTMG5 */
+DATA 4 0x307a0114 0x03030202
+/* DDRC_DRAMTMG8 */
+DATA 4 0x307a0120 0x00000803
+/* DDRC_ZQCTL0 */
+DATA 4 0x307a0180 0x00800020
+/* DDRC_ZQCTL1 */
+DATA 4 0x307a0184 0x02001000
+/* DDRC_DFITMG0 */
+DATA 4 0x307a0190 0x02098204
+/* DDRC_DFITMG1 */
+DATA 4 0x307a0194 0x00030303
+/* DDRC_ADDRMAP0 */
+DATA 4 0x307a0200 0x0000001f
+/* DDRC_ADDRMAP1 */
+DATA 4 0x307a0204 0x00080808
+/* DDRC_ADDRMAP5 */
+DATA 4 0x307a0214 0x07070707
+/* DDRC_ADDRMAP6 */
+DATA 4 0x307a0218 0x07070707
+/* DDRC_ODTCFG */
+DATA 4 0x307a0240 0x06000601
+/* DDRC_ODTMAP */
+DATA 4 0x307a0244 0x00000001
+/* SRC_DDRC_RCR */
+DATA 4 0x30391000 0x00000000
+/* DDR_PHY_PHY_CON0 */
+DATA 4 0x30790000 0x17420f40
+/* DDR_PHY_PHY_CON1 */
+DATA 4 0x30790004 0x10210100
+/* DDR_PHY_PHY_CON4 */
+DATA 4 0x30790010 0x00060807
+/* DDR_PHY_MDLL_CON0 */
+DATA 4 0x307900b0 0x1010007e
+/* DDR_PHY_DRVDS_CON0 */
+DATA 4 0x3079009c 0x00000d6e
+/* DDR_PHY_OFFSET_RD_CON0 */
+DATA 4 0x30790020 0x08080808
+/* DDR_PHY_OFFSET_WR_CON0 */
+DATA 4 0x30790030 0x08080808
+/* DDR_PHY_CMD_SDLL_CON0 */
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+/* DDR_PHY_ZQ_CON0 */
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+/* DDR_PHY_ZQ_CON1 */
+CHECK_BITS_SET 4 0x307900c4 0x1
+/* DDR_PHY_ZQ_CON0 */
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e407304
+
+/* CCM_CCGRn */
+DATA 4 0x30384130 0x00000000
+/* IOMUXC_GPR_GPR8 */
+DATA 4 0x30340020 0x00000178
+/* CCM_CCGRn */
+DATA 4 0x30384130 0x00000002
+/* DDR_PHY_LP_CON0 */
+DATA 4 0x30790018 0x0000000f
+
+/* DDRC_STAT */
+CHECK_BITS_SET 4 0x307a0004 0x1
diff --git a/roms/u-boot/board/toradex/colibri_pxa270/Kconfig b/roms/u-boot/board/toradex/colibri_pxa270/Kconfig
new file mode 100644
index 000000000..f646baa3f
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_pxa270/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_COLIBRI_PXA270
+
+config SYS_BOARD
+	default "colibri_pxa270"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "colibri_pxa270"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_NOR
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "262144"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/colibri_pxa270/MAINTAINERS b/roms/u-boot/board/toradex/colibri_pxa270/MAINTAINERS
new file mode 100644
index 000000000..b378d7be5
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_pxa270/MAINTAINERS
@@ -0,0 +1,6 @@
+COLIBRI_PXA270 BOARD
+M:	Marek Vasut <marek.vasut@gmail.com>
+S:	Maintained
+F:	board/toradex/colibri_pxa270/
+F:	include/configs/colibri_pxa270.h
+F:	configs/colibri_pxa270_defconfig
diff --git a/roms/u-boot/board/toradex/colibri_pxa270/Makefile b/roms/u-boot/board/toradex/colibri_pxa270/Makefile
new file mode 100644
index 000000000..ea610cfea
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_pxa270/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Toradex Colibri PXA270 Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+
+obj-y	:= colibri_pxa270.o
diff --git a/roms/u-boot/board/toradex/colibri_pxa270/colibri_pxa270.c b/roms/u-boot/board/toradex/colibri_pxa270/colibri_pxa270.c
new file mode 100644
index 000000000..25fbf4120
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_pxa270/colibri_pxa270.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Toradex Colibri PXA270 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2016-2019 Marcel Ziswiler <marcel.ziswiler@toradex.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
+#include <asm/arch/regs-uart.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/pxa_mmc_gen.h>
+#include <dm/platform_data/serial_pxa.h>
+#include <netdev.h>
+#include <serial.h>
+#include <usb.h>
+#include <asm/mach-types.h>
+#include <linux/delay.h>
+#include "../common/tdx-common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of Toradex Colibri PXA270 */
+	gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Model: Toradex Colibri PXA270\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+int dram_init(void)
+{
+	pxa2xx_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+#ifdef	CONFIG_CMD_USB
+int board_usb_init(int index, enum usb_init_type init)
+{
+	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
+
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+	while (UHCHR & UHCHR_FSBIR)
+		;
+
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+	/* Clear any OTG Pin Hold */
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+	/* Set port power control mask bits, only 3 ports. */
+	writel(readl(UHCRHDB) | (0x7 << 17), UHCRHDB);
+
+	/* enable port 2 */
+	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
+
+void usb_board_stop(void)
+{
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	udelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
+	udelay(10);
+
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(struct bd_info *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
+
+#ifdef	CONFIG_CMD_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
+int board_mmc_init(struct bd_info *bis)
+{
+	pxa_mmc_register(0);
+	return 0;
+}
+#else /* !CONFIG_IS_ENABLED(DM_MMC) */
+static const struct pxa_mmc_plat mmc_plat = {
+	.base = (struct pxa_mmc_regs *)MMC0_BASE,
+};
+
+U_BOOT_DRVINFO(pxa_mmcs) = {
+	.name = "pxa_mmc",
+	.plat = &mmc_plat,
+};
+#endif /* !CONFIG_IS_ENABLED(DM_MMC) */
+#endif
+
+static const struct pxa_serial_plat serial_plat = {
+	.base = (struct pxa_uart_regs *)FFUART_BASE,
+	.port = FFUART_INDEX,
+	.baudrate = CONFIG_BAUDRATE,
+};
+
+U_BOOT_DRVINFO(pxa_serials) = {
+	.name = "serial_pxa",
+	.plat = &serial_plat,
+};
diff --git a/roms/u-boot/board/toradex/colibri_t20/Kconfig b/roms/u-boot/board/toradex/colibri_t20/Kconfig
new file mode 100644
index 000000000..a43acddb8
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_t20/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_COLIBRI_T20
+
+config SYS_BOARD
+	default "colibri_t20"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "colibri_t20"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "3145728"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/colibri_t20/MAINTAINERS b/roms/u-boot/board/toradex/colibri_t20/MAINTAINERS
new file mode 100644
index 000000000..61fbd2c1e
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_t20/MAINTAINERS
@@ -0,0 +1,7 @@
+COLIBRI_T20
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+S:	Maintained
+F:	board/toradex/colibri_t20/
+F:	include/configs/colibri_t20.h
+F:	configs/colibri_t20_defconfig
+F:	arch/arm/dts/tegra20-colibri.dtb
diff --git a/roms/u-boot/board/toradex/colibri_t20/Makefile b/roms/u-boot/board/toradex/colibri_t20/Makefile
new file mode 100644
index 000000000..c5528b37b
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_t20/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2012 Lucas Stach
+
+obj-y	+= colibri_t20.o
diff --git a/roms/u-boot/board/toradex/colibri_t20/colibri_t20.c b/roms/u-boot/board/toradex/colibri_t20/colibri_t20.c
new file mode 100644
index 000000000..73ef4d2db
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_t20/colibri_t20.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012 Lucas Stach
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/tegra.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <nand.h>
+#include <linux/delay.h>
+#include "../common/tdx-common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PMU_I2C_ADDRESS		0x34
+#define MAX_I2C_RETRY		3
+#define PMU_SUPPLYENE		0x14
+#define PMU_SUPPLYENE_SYSINEN	(1<<5)
+#define PMU_SUPPLYENE_EXITSLREQ	(1<<1)
+
+int arch_misc_init(void)
+{
+	/* Disable PMIC sleep mode on low supply voltage */
+	struct udevice *dev;
+	u8 addr, data[1];
+	int err;
+
+	err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
+	if (err) {
+		debug("%s: Cannot find PMIC I2C chip\n", __func__);
+		return err;
+	}
+
+	addr = PMU_SUPPLYENE;
+
+	err = dm_i2c_read(dev, addr, data, 1);
+	if (err) {
+		debug("failed to get PMU_SUPPLYENE\n");
+		return err;
+	}
+
+	data[0] &= ~PMU_SUPPLYENE_SYSINEN;
+	data[0] |= PMU_SUPPLYENE_EXITSLREQ;
+
+	err = dm_i2c_write(dev, addr, data, 1);
+	if (err) {
+		debug("failed to set PMU_SUPPLYENE\n");
+		return err;
+	}
+
+	/* make sure SODIMM pin 87 nRESET_OUT is released properly */
+	pinmux_set_func(PMUX_PINGRP_ATA, PMUX_FUNC_GMI);
+
+	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
+	    NVBOOTTYPE_RECOVERY)
+		printf("USB recovery mode\n");
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Model: Toradex Colibri T20 %dMB V%s\n",
+	       (gd->ram_size == 0x10000000) ? 256 : 512,
+	       (get_nand_dev_by_index(0)->erasesize >> 10 == 512) ?
+	       ((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+	pinmux_tristate_disable(PMUX_PINGRP_GMB);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_NAND
+void pin_mux_nand(void)
+{
+	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
+
+	/*
+	 * configure pingroup ATC to something unrelated to
+	 * avoid ATC overriding KBC
+	 */
+	pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI);
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+void pin_mux_usb(void)
+{
+	/* module internal USB bus to connect ethernet chipset */
+	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+
+	/* ULPI reference clock output */
+	pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+	pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+
+	/* PHY reset GPIO */
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
+
+	/* VBus GPIO */
+	pinmux_tristate_disable(PMUX_PINGRP_DTE);
+
+	/* Reset ASIX using LAN_RESET */
+	gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
+	gpio_direction_output(TEGRA_GPIO(V, 4), 0);
+	pinmux_tristate_disable(PMUX_PINGRP_GPV);
+	udelay(5);
+	gpio_set_value(TEGRA_GPIO(V, 4), 1);
+
+	/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
+	pinmux_tristate_disable(PMUX_PINGRP_SPIG);
+}
+#endif
+
+#ifdef CONFIG_VIDEO_TEGRA20
+/*
+ * Routine: pin_mux_display
+ * Description: setup the pin muxes/tristate values for the LCD interface)
+ */
+void pin_mux_display(void)
+{
+	/*
+	 * Manually untristate BL_ON (PT4 - SODIMM 71) as specified through
+	 * device-tree
+	 */
+	pinmux_tristate_disable(PMUX_PINGRP_DTA);
+
+	pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
+	pinmux_tristate_disable(PMUX_PINGRP_SDC);
+}
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+	gpio_request(TEGRA_GPIO(T, 4), "BL_ON");
+	gpio_direction_output(TEGRA_GPIO(T, 4), 0);
+}
+#endif
diff --git a/roms/u-boot/board/toradex/colibri_t30/Kconfig b/roms/u-boot/board/toradex/colibri_t30/Kconfig
new file mode 100644
index 000000000..68ef82b09
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_t30/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_COLIBRI_T30
+
+config SYS_BOARD
+	default "colibri_t30"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "colibri_t30"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/colibri_t30/MAINTAINERS b/roms/u-boot/board/toradex/colibri_t30/MAINTAINERS
new file mode 100644
index 000000000..ded9e2829
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_t30/MAINTAINERS
@@ -0,0 +1,7 @@
+Colibri T30
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+S:	Maintained
+F:	board/toradex/colibri_t30/
+F:	include/configs/colibri_t30.h
+F:	configs/colibri_t30_defconfig
+F:	arch/arm/dts/tegra30-colibri.dtb
diff --git a/roms/u-boot/board/toradex/colibri_t30/Makefile b/roms/u-boot/board/toradex/colibri_t30/Makefile
new file mode 100644
index 000000000..4242902da
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_t30/Makefile
@@ -0,0 +1,4 @@
+# Copyright (c) 2013-2014 Stefan Agner
+# SPDX-License-Identifier:      GPL-2.0+
+
+obj-y	+= colibri_t30.o
diff --git a/roms/u-boot/board/toradex/colibri_t30/colibri_t30.c b/roms/u-boot/board/toradex/colibri_t30/colibri_t30.c
new file mode 100644
index 000000000..20cbb75a3
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_t30/colibri_t30.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2014-2016
+ *  Stefan Agner <stefan@agner.ch>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/tegra.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <linux/delay.h>
+#include "pinmux-config-colibri_t30.h"
+#include "../common/tdx-common.h"
+
+int arch_misc_init(void)
+{
+	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
+	    NVBOOTTYPE_RECOVERY)
+		printf("USB recovery mode\n");
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Model: Toradex Colibri T30 1GB\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_pingrp_table(tegra3_pinmux_common,
+				   ARRAY_SIZE(tegra3_pinmux_common));
+
+	pinmux_config_pingrp_table(unused_pins_lowpower,
+				   ARRAY_SIZE(unused_pins_lowpower));
+
+	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
+	pinmux_config_drvgrp_table(colibri_t30_padctrl,
+				   ARRAY_SIZE(colibri_t30_padctrl));
+}
+
+/*
+ * Disable RS232 serial transceiver ForceOFF# pins on Iris
+ */
+void gpio_early_init_uart(void)
+{
+	gpio_request(TEGRA_GPIO(X, 6), "Force OFF# X13");
+	gpio_direction_output(TEGRA_GPIO(X, 6), 1);
+	gpio_request(TEGRA_GPIO(X, 7), "Force OFF# X14");
+	gpio_direction_output(TEGRA_GPIO(X, 7), 1);
+}
+
+/*
+ * Enable AX88772B USB to LAN controller
+ */
+void pin_mux_usb(void)
+{
+	/* Reset ASIX using LAN_RESET */
+	gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET");
+	gpio_direction_output(TEGRA_GPIO(DD, 0), 0);
+	udelay(5);
+	gpio_set_value(TEGRA_GPIO(DD, 0), 1);
+}
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+	gpio_request(TEGRA_GPIO(V, 2), "BL_ON");
+	gpio_direction_output(TEGRA_GPIO(V, 2), 0);
+}
diff --git a/roms/u-boot/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/roms/u-boot/board/toradex/colibri_t30/pinmux-config-colibri_t30.h
new file mode 100644
index 000000000..5ac1a6da9
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_t30/pinmux-config-colibri_t30.h
@@ -0,0 +1,353 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2013-2014, Stefan Agner
+ */
+
+#ifndef _PINMUX_CONFIG_COLIBRI_T30_H_
+#define _PINMUX_CONFIG_COLIBRI_T30_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io)		\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+/* TRISTATE here means output driver is tri-stated */ \
+		.tristate	= PMUX_TRI_##_tri,		\
+/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{							\
+		.drvgrp		= PMUX_DRVGRP_##_drvgrp,	\
+		.slwf		= _slwf,			\
+		.slwr		= _slwr,			\
+		.drvup		= _drvup,			\
+		.drvdn		= _drvdn,			\
+		.lpmd		= PMUX_LPMD_##_lpmd,		\
+		.schmt		= PMUX_SCHMT_##_schmt,		\
+		.hsm		= PMUX_HSM_##_hsm,		\
+	}
+
+static struct pmux_pingrp_config tegra3_pinmux_common[] = {
+	/* SDMMC1 disabled */
+	DEFAULT_PINMUX(SDMMC1_CLK_PZ0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD_PZ1, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3_PY4, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2_PY5, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1_PY6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0_PY7, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* SDMMC4 pinmux (eMMC) */
+	LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C2 pinmux */
+	DEFAULT_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT),
+
+	/* I2C3 pinmux, muliplexed with KB_ROW13/KB_ROW14 */
+	I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+	/* UARTA RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
+	LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	/* UARTC RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_RTS_N_PJ6, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_CTS_N_PJ5, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_TXD_PW6, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RXD_PW7, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N_PA1, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N_PC0, GMI, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
+	DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
+	DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
+	DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, INPUT),
+	/* UARTB RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(GMI_A17_PB0, UARTD, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, INPUT),
+
+	/* Multiplexed with KB_ROW10/KB_ROW11/KB_ROW12/KB_ROW15 */
+	DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, TRISTATE, INPUT),
+	DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(PBB3, VGP3, NORMAL, TRISTATE, INPUT),
+
+	DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
+
+	/* KBC keys */
+	DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT),
+
+	/* SDMMC2 pinmux */
+	DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, UP, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MOSI_PX4, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_SCK_PX5, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, INPUT),
+
+	/* LAN_RESET */
+	DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, OUTPUT),
+
+	DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
+
+	/* LAN_VBUS */
+	DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, OUTPUT),
+
+	DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
+
+	/* GPIOs */
+	/* SDMMC1 CD gpio */
+	DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
+	/* SDMMC1 WP gpio */
+	LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* Touch panel GPIO */
+	/* Touch IRQ */
+	DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
+
+	/* Touch RESET */
+	DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
+
+	/* Power rails GPIO */
+	DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
+
+	LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+};
+
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+static struct pmux_drvgrp_config colibri_t30_padctrl[] = {
+	/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+	DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+		SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif	/* _PINMUX_CONFIG_COLIBRI_T30_H_ */
diff --git a/roms/u-boot/board/toradex/colibri_vf/Kconfig b/roms/u-boot/board/toradex/colibri_vf/Kconfig
new file mode 100644
index 000000000..5f7129dd3
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_vf/Kconfig
@@ -0,0 +1,26 @@
+if TARGET_COLIBRI_VF
+
+config SYS_BOARD
+	default "colibri_vf"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "colibri_vf"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "2048"
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	default y
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/colibri_vf/MAINTAINERS b/roms/u-boot/board/toradex/colibri_vf/MAINTAINERS
new file mode 100644
index 000000000..c6627654a
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_vf/MAINTAINERS
@@ -0,0 +1,12 @@
+Colibri VFxx
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+W:	https://www.toradex.com/community
+S:	Maintained
+F:	board/toradex/colibri_vf/
+F:	include/configs/colibri_vf.h
+F:	configs/colibri_vf_defconfig
+F:	arch/arm/dts/vf-colibri.dtsi
+F:	arch/arm/dts/vf-colibri-u-boot.dtsi
+F:	arch/arm/dts/vf500-colibri.dts
+F:	arch/arm/dts/vf610-colibri.dts
diff --git a/roms/u-boot/board/toradex/colibri_vf/Makefile b/roms/u-boot/board/toradex/colibri_vf/Makefile
new file mode 100644
index 000000000..6272a7749
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_vf/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+
+obj-y	:= colibri_vf.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
diff --git a/roms/u-boot/board/toradex/colibri_vf/colibri_vf.c b/roms/u-boot/board/toradex/colibri_vf/colibri_vf.c
new file mode 100644
index 000000000..e9c5bc063
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_vf/colibri_vf.c
@@ -0,0 +1,465 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015-2019 Toradex, Inc.
+ *
+ * Based on vf610twr.c:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/ddrmc-vf610.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <fsl_dcu_fb.h>
+#include <g_dnl.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+#include <usb.h>
+
+#include "../common/tdx-common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PTC0_GPIO_45		45
+
+static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
+	{ DDRMC_CR79_CTLUPD_AREF(1), 79 },
+	/* sets manual values for read lvl. (gate) delay of data slice 0/1 */
+	{ DDRMC_CR105_RDLVL_DL_0(28), 105 },
+	{ DDRMC_CR106_RDLVL_GTDL_0(24), 106 },
+	{ DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 },
+	{ DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 },
+
+	/* AXI */
+	{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
+	{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
+	{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
+		   DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
+	{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
+		   DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
+	{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+		   DDRMC_CR122_AXI0_PRIRLX(100), 122 },
+	{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
+		   DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
+	{ DDRMC_CR124_AXI1_PRIRLX(100), 124 },
+	{ DDRMC_CR126_PHY_RDLAT(8), 126 },
+	{ DDRMC_CR132_WRLAT_ADJ(5) |
+		   DDRMC_CR132_RDLAT_ADJ(6), 132 },
+	{ DDRMC_CR137_PHYCTL_DL(2), 137 },
+	{ DDRMC_CR138_PHY_WRLV_MXDL(256) |
+		   DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
+	{ DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+		   DDRMC_CR139_PHY_WRLV_DLL(3) |
+		   DDRMC_CR139_PHY_WRLV_EN(3), 139 },
+	{ DDRMC_CR140_PHY_WRLV_WW(64), 140 },
+	{ DDRMC_CR143_RDLV_GAT_MXDL(1536) |
+		   DDRMC_CR143_RDLV_MXDL(128), 143 },
+	{ DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
+		   DDRMC_CR144_PHY_RDLV_DLL(3) |
+		   DDRMC_CR144_PHY_RDLV_EN(3), 144 },
+	{ DDRMC_CR145_PHY_RDLV_RR(64), 145 },
+	{ DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
+	{ DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
+	{ DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
+	{ DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
+		   DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
+
+	{ DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+		   DDRMC_CR154_PAD_ZQ_MODE(1) |
+		   DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
+		   DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
+	{ DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 },
+	{ DDRMC_CR158_TWR(6), 158 },
+	{ DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
+		   DDRMC_CR161_TODTH_WR(2), 161 },
+	/* end marker */
+	{ 0, -1 }
+};
+
+int dram_init(void)
+{
+	static const struct ddr3_jedec_timings timings = {
+		.tinit             = 5,
+		.trst_pwron        = 80000,
+		.cke_inactive      = 200000,
+		.wrlat             = 5,
+		.caslat_lin        = 12,
+		.trc               = 21,
+		.trrd              = 4,
+		.tccd              = 4,
+		.tbst_int_interval = 0,
+		.tfaw              = 20,
+		.trp               = 6,
+		.twtr              = 4,
+		.tras_min          = 15,
+		.tmrd              = 4,
+		.trtp              = 4,
+		.tras_max          = 28080,
+		.tmod              = 12,
+		.tckesr            = 4,
+		.tcke              = 3,
+		.trcd_int          = 6,
+		.tras_lockout      = 0,
+		.tdal              = 12,
+		.bstlen            = 3,
+		.tdll              = 512, /* not applicable since freq. scaling
+					   * is not used
+					   */
+		.trp_ab            = 6,
+		.tref              = 3120,
+		.trfc              = 64,
+		.tref_int          = 0,
+		.tpdex             = 3,
+		.txpdll            = 10,
+		.txsnr             = 68,  /* changed to conform to JEDEC
+					   * specifications
+					   */
+		.txsr              = 506, /* changed to conform to JEDEC
+					   * specifications
+					   */
+		.cksrx             = 5,
+		.cksre             = 5,
+		.freq_chg_en       = 0,
+		.zqcl              = 256,
+		.zqinit            = 512,
+		.zqcs              = 64,
+		.ref_per_zq        = 64,
+		.zqcs_rotate       = 0,
+		.aprebit           = 10,
+		.cmd_age_cnt       = 64,
+		.age_cnt           = 64,
+		.q_fullness        = 7,
+		.odt_rd_mapcs0     = 0,
+		.odt_wr_mapcs0     = 1,
+		.wlmrd             = 40,
+		.wldqsen           = 25,
+	};
+
+	ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+#ifdef CONFIG_VYBRID_GPIO
+static void setup_iomux_gpio(void)
+{
+	static const iomux_v3_cfg_t gpio_pads[] = {
+		VF610_PAD_PTA17__GPIO_7,
+		VF610_PAD_PTA20__GPIO_10,
+		VF610_PAD_PTA21__GPIO_11,
+		VF610_PAD_PTA30__GPIO_20,
+		VF610_PAD_PTA31__GPIO_21,
+		VF610_PAD_PTB0__GPIO_22,
+		VF610_PAD_PTB1__GPIO_23,
+		VF610_PAD_PTB6__GPIO_28,
+		VF610_PAD_PTB7__GPIO_29,
+		VF610_PAD_PTB8__GPIO_30,
+		VF610_PAD_PTB9__GPIO_31,
+		VF610_PAD_PTB12__GPIO_34,
+		VF610_PAD_PTB13__GPIO_35,
+		VF610_PAD_PTB16__GPIO_38,
+		VF610_PAD_PTB17__GPIO_39,
+		VF610_PAD_PTB18__GPIO_40,
+		VF610_PAD_PTB21__GPIO_43,
+		VF610_PAD_PTB22__GPIO_44,
+		VF610_PAD_PTC0__GPIO_45,
+		VF610_PAD_PTC1__GPIO_46,
+		VF610_PAD_PTC2__GPIO_47,
+		VF610_PAD_PTC3__GPIO_48,
+		VF610_PAD_PTC4__GPIO_49,
+		VF610_PAD_PTC5__GPIO_50,
+		VF610_PAD_PTC6__GPIO_51,
+		VF610_PAD_PTC7__GPIO_52,
+		VF610_PAD_PTC8__GPIO_53,
+		VF610_PAD_PTD31__GPIO_63,
+		VF610_PAD_PTD30__GPIO_64,
+		VF610_PAD_PTD29__GPIO_65,
+		VF610_PAD_PTD28__GPIO_66,
+		VF610_PAD_PTD27__GPIO_67,
+		VF610_PAD_PTD26__GPIO_68,
+		VF610_PAD_PTD25__GPIO_69,
+		VF610_PAD_PTD24__GPIO_70,
+		VF610_PAD_PTD9__GPIO_88,
+		VF610_PAD_PTD10__GPIO_89,
+		VF610_PAD_PTD11__GPIO_90,
+		VF610_PAD_PTD12__GPIO_91,
+		VF610_PAD_PTD13__GPIO_92,
+		VF610_PAD_PTB23__GPIO_93,
+		VF610_PAD_PTB26__GPIO_96,
+		VF610_PAD_PTB28__GPIO_98,
+		VF610_PAD_PTC30__GPIO_103,
+		VF610_PAD_PTA7__GPIO_134,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+}
+#endif
+
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+static void setup_iomux_fsl_dcu(void)
+{
+	static const iomux_v3_cfg_t dcu0_pads[] = {
+		VF610_PAD_PTE0__DCU0_HSYNC,
+		VF610_PAD_PTE1__DCU0_VSYNC,
+		VF610_PAD_PTE2__DCU0_PCLK,
+		VF610_PAD_PTE4__DCU0_DE,
+		VF610_PAD_PTE5__DCU0_R0,
+		VF610_PAD_PTE6__DCU0_R1,
+		VF610_PAD_PTE7__DCU0_R2,
+		VF610_PAD_PTE8__DCU0_R3,
+		VF610_PAD_PTE9__DCU0_R4,
+		VF610_PAD_PTE10__DCU0_R5,
+		VF610_PAD_PTE11__DCU0_R6,
+		VF610_PAD_PTE12__DCU0_R7,
+		VF610_PAD_PTE13__DCU0_G0,
+		VF610_PAD_PTE14__DCU0_G1,
+		VF610_PAD_PTE15__DCU0_G2,
+		VF610_PAD_PTE16__DCU0_G3,
+		VF610_PAD_PTE17__DCU0_G4,
+		VF610_PAD_PTE18__DCU0_G5,
+		VF610_PAD_PTE19__DCU0_G6,
+		VF610_PAD_PTE20__DCU0_G7,
+		VF610_PAD_PTE21__DCU0_B0,
+		VF610_PAD_PTE22__DCU0_B1,
+		VF610_PAD_PTE23__DCU0_B2,
+		VF610_PAD_PTE24__DCU0_B3,
+		VF610_PAD_PTE25__DCU0_B4,
+		VF610_PAD_PTE26__DCU0_B5,
+		VF610_PAD_PTE27__DCU0_B6,
+		VF610_PAD_PTE28__DCU0_B7,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
+}
+
+static void setup_tcon(void)
+{
+	setbits_le32(TCON0_BASE_ADDR, (1 << 29));
+}
+#endif
+
+static inline int is_colibri_vf61(void)
+{
+	struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
+
+	/*
+	 * Detect board type by Level 2 Cache: VF50 don't have any
+	 * Level 2 Cache.
+	 */
+	return !!mscm->cpxcfg1;
+}
+
+static void clock_init(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+	u32 pfd_clk_sel, ddr_clk_sel;
+
+	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+			CCM_CCGR0_UART0_CTRL_MASK);
+#ifdef CONFIG_FSL_DSPI
+	setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
+#endif
+	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+			CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+			CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+			CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+			CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+			CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+			CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+			CCM_CCGR4_GPC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+			CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+			CCM_CCGR7_SDHC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+			CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+			CCM_CCGR10_NFC_CTRL_MASK);
+
+#ifdef CONFIG_USB_EHCI_VF
+	setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
+	setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
+
+	clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
+			ANADIG_PLL3_CTRL_POWERDOWN |
+			ANADIG_PLL3_CTRL_DIV_SELECT,
+			ANADIG_PLL3_CTRL_ENABLE);
+	clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
+			ANADIG_PLL7_CTRL_POWERDOWN |
+			ANADIG_PLL7_CTRL_DIV_SELECT,
+			ANADIG_PLL7_CTRL_ENABLE);
+#endif
+
+	clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
+			ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
+			ANADIG_PLL5_CTRL_DIV_SELECT);
+
+	if (is_colibri_vf61()) {
+		clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
+				ANADIG_PLL2_CTRL_POWERDOWN,
+				ANADIG_PLL2_CTRL_ENABLE |
+				ANADIG_PLL2_CTRL_DIV_SELECT);
+	}
+
+	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+			ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+			CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+
+	/* See "Typical PLL Configuration" */
+	if (is_colibri_vf61()) {
+		pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
+		ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
+	} else {
+		pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
+		ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
+	}
+
+	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
+			CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
+			CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
+			CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
+			CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
+			ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
+			CCM_CCSR_SYS_CLK_SEL(4));
+
+	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+			CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+			CCM_CACRR_ARM_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+			CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
+			CCM_CSCMR1_NFC_CLK_SEL(0));
+	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+			CCM_CSCDR1_RMII_CLK_EN);
+	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+			CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
+			CCM_CSCDR2_NFC_EN);
+	clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
+			CCM_CSCDR3_NFC_PRE_DIV(3));
+	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+			CCM_CSCMR2_RMII_CLK_SEL(2));
+
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+		setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
+		setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
+#endif
+}
+
+static void mscm_init(void)
+{
+	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+	int i;
+
+	for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_early_init_f(void)
+{
+	clock_init();
+	mscm_init();
+
+#ifdef CONFIG_VYBRID_GPIO
+	setup_iomux_gpio();
+#endif
+
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+	setup_tcon();
+	setup_iomux_fsl_dcu();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	struct src *src = (struct src *)SRC_BASE_ADDR;
+
+	if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
+			== SRC_SBMR2_BMOD_SERIAL) {
+		printf("Serial Downloader recovery mode, disable autoboot\n");
+		env_set("bootdelay", "-1");
+	}
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+int board_init(void)
+{
+	struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/*
+	 * Enable external 32K Oscillator
+	 *
+	 * The internal clock experiences significant drift
+	 * so we must use the external oscillator in order
+	 * to maintain correct time in the hwclock
+	 */
+	setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	if (is_colibri_vf61())
+		puts("Model: Toradex Colibri VF61\n");
+	else
+		puts("Model: Toradex Colibri VF50\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifndef CONFIG_DM_VIDEO
+	int ret = 0;
+#endif
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+	static const struct node_info nodes[] = {
+		{ "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+	};
+
+	/* Update partition nodes using info from mtdparts env var */
+	puts("   Updating MTD partitions...\n");
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO)
+	ret = fsl_dcu_fixedfb_setup(blob);
+	if (ret)
+		return ret;
+#endif
+
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+	gpio_request(PTC0_GPIO_45, "BL_ON");
+	gpio_direction_output(PTC0_GPIO_45, 0);
+}
diff --git a/roms/u-boot/board/toradex/colibri_vf/dcu.c b/roms/u-boot/board/toradex/colibri_vf/dcu.c
new file mode 100644
index 000000000..c688ed79f
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_vf/dcu.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * FSL DCU platform driver
+ */
+
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	unsigned long long div;
+
+	clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
+	clrsetbits_le32(&ccm->cscdr3,
+			CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
+			CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
+	div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
+	do_div(div, pixclock);
+
+	return div;
+}
+
+int platform_dcu_init(struct fb_info *fbinfo,
+		      unsigned int xres,
+		      unsigned int yres,
+		      const char *port,
+		      struct fb_videomode *dcu_fb_videomode)
+{
+	fsl_dcu_init(fbinfo, xres, yres, 32);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/toradex/colibri_vf/imximage.cfg b/roms/u-boot/board/toradex/colibri_vf/imximage.cfg
new file mode 100644
index 000000000..7e629d2f9
--- /dev/null
+++ b/roms/u-boot/board/toradex/colibri_vf/imximage.cfg
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Toradex, Inc.
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/mach-imx/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET	FLASH_OFFSET_STANDARD
diff --git a/roms/u-boot/board/toradex/common/Kconfig b/roms/u-boot/board/toradex/common/Kconfig
new file mode 100644
index 000000000..36068d2e3
--- /dev/null
+++ b/roms/u-boot/board/toradex/common/Kconfig
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2016 Toradex, Inc.
+
+menuconfig TDX_CFG_BLOCK
+	bool "Enable Toradex config block support"
+	select OF_BOARD_SETUP
+	help
+	  The Toradex config block stored production data on the on-module
+	  flash device (NAND, NOR or eMMC). The area is normally preserved by
+	  software and contains the serial number (out of which the MAC
+	  address is generated) and the exact module type.
+
+# Helper config to determine the correct default location of the cfg block
+config TDX_HAVE_MMC
+	bool
+
+config TDX_HAVE_NAND
+	bool
+
+config TDX_HAVE_NOR
+	bool
+
+config TDX_HAVE_EEPROM
+	bool
+
+config TDX_HAVE_EEPROM_EXTRA
+	bool
+
+if TDX_CFG_BLOCK
+
+config TDX_CFG_BLOCK_IS_IN_MMC
+	bool
+	depends on TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_IS_IN_NAND
+	bool
+	depends on TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_IS_IN_NOR
+	bool
+	depends on TDX_HAVE_NOR
+	default y
+
+config TDX_CFG_BLOCK_IS_IN_EEPROM
+	bool
+	depends on TDX_HAVE_EEPROM
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	int "Toradex config block eMMC device ID"
+	depends on TDX_CFG_BLOCK_IS_IN_MMC
+
+config TDX_CFG_BLOCK_PART
+	int "Toradex config block eMMC partition ID"
+	depends on TDX_CFG_BLOCK_IS_IN_MMC
+
+config TDX_CFG_BLOCK_OFFSET
+	int "Toradex config block offset"
+	help
+	  Specify the byte offset of the Toradex config block within the flash
+	  device the config block is stored on.
+
+config TDX_CFG_BLOCK_OFFSET2
+	int "Toradex config block offset, second instance"
+	default 0
+	help
+	  Specify the byte offset of the 2nd instance of the Toradex config block
+	  within the flash device the config block is stored on.
+	  Set to 0 on modules which have no 2nd instance.
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	bool "Set the second Ethernet address"
+	help
+	  For each serial number two Ethernet addresses are available for dual
+	  Ethernet carrier boards. This options enables the code to set the
+	  second Ethernet address as environment variable (eth1addr).
+
+config TDX_CFG_BLOCK_EXTRA
+	bool "Support for additional EEPROMs (carrier board, display adapter)"
+	depends on TDX_HAVE_EEPROM_EXTRA
+	help
+	  Enables fetching auxilary config blocks from carrier board/display
+	  adapter EEPROMs.
+
+endif
diff --git a/roms/u-boot/board/toradex/common/Makefile b/roms/u-boot/board/toradex/common/Makefile
new file mode 100644
index 000000000..7b19b6e4c
--- /dev/null
+++ b/roms/u-boot/board/toradex/common/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2016 Toradex, Inc.
+
+# Common for all Toradex modules
+ifeq ($(CONFIG_SPL_BUILD),y)
+# Necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-$(CONFIG_TDX_CFG_BLOCK) += tdx-cfg-block.o
+obj-y += tdx-common.o
+obj-y += tdx-eeprom.o
+endif
diff --git a/roms/u-boot/board/toradex/common/tdx-cfg-block.c b/roms/u-boot/board/toradex/common/tdx-cfg-block.c
new file mode 100644
index 000000000..93eb20cf6
--- /dev/null
+++ b/roms/u-boot/board/toradex/common/tdx-cfg-block.c
@@ -0,0 +1,1011 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016-2020 Toradex
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+#include "tdx-cfg-block.h"
+#include "tdx-eeprom.h"
+
+#include <command.h>
+#include <asm/cache.h>
+
+#if defined(CONFIG_TARGET_APALIS_IMX6) || \
+	defined(CONFIG_TARGET_APALIS_IMX8) || \
+	defined(CONFIG_TARGET_APALIS_IMX8X) || \
+	defined(CONFIG_TARGET_COLIBRI_IMX6) || \
+	defined(CONFIG_TARGET_COLIBRI_IMX8X) || \
+	defined(CONFIG_TARGET_VERDIN_IMX8MM) || \
+	defined(CONFIG_TARGET_VERDIN_IMX8MN) || \
+	defined(CONFIG_TARGET_VERDIN_IMX8MP)
+#include <asm/arch/sys_proto.h>
+#else
+#define is_cpu_type(cpu) (0)
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+#include <asm/arch-pxa/pxa.h>
+#else
+#define cpu_is_pxa27x(cpu) (0)
+#endif
+#include <cli.h>
+#include <console.h>
+#include <env.h>
+#include <flash.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TAG_VALID	0xcf01
+#define TAG_MAC		0x0000
+#define TAG_CAR_SERIAL	0x0021
+#define TAG_HW		0x0008
+#define TAG_INVALID	0xffff
+
+#define TAG_FLAG_VALID	0x1
+
+#define TDX_EEPROM_ID_MODULE		0
+#define TDX_EEPROM_ID_CARRIER		1
+
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
+#define TDX_CFG_BLOCK_MAX_SIZE 512
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+#define TDX_CFG_BLOCK_MAX_SIZE 64
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+#define TDX_CFG_BLOCK_MAX_SIZE 64
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_EEPROM)
+#define TDX_CFG_BLOCK_MAX_SIZE 64
+#else
+#error Toradex config block location not set
+#endif
+
+#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
+#define TDX_CFG_BLOCK_EXTRA_MAX_SIZE 64
+#endif
+
+struct toradex_tag {
+	u32 len:14;
+	u32 flags:2;
+	u32 id:16;
+};
+
+bool valid_cfgblock;
+struct toradex_hw tdx_hw_tag;
+struct toradex_eth_addr tdx_eth_addr;
+u32 tdx_serial;
+#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
+u32 tdx_car_serial;
+bool valid_cfgblock_carrier;
+struct toradex_hw tdx_car_hw_tag;
+#endif
+
+const char * const toradex_modules[] = {
+	 [0] = "UNKNOWN MODULE",
+	 [1] = "Colibri PXA270 312MHz",
+	 [2] = "Colibri PXA270 520MHz",
+	 [3] = "Colibri PXA320 806MHz",
+	 [4] = "Colibri PXA300 208MHz",
+	 [5] = "Colibri PXA310 624MHz",
+	 [6] = "Colibri PXA320 806MHz IT",
+	 [7] = "Colibri PXA300 208MHz XT",
+	 [8] = "Colibri PXA270 312MHz",
+	 [9] = "Colibri PXA270 520MHz",
+	[10] = "Colibri VF50 128MB", /* not currently on sale */
+	[11] = "Colibri VF61 256MB",
+	[12] = "Colibri VF61 256MB IT",
+	[13] = "Colibri VF50 128MB IT",
+	[14] = "Colibri iMX6 Solo 256MB",
+	[15] = "Colibri iMX6 DualLite 512MB",
+	[16] = "Colibri iMX6 Solo 256MB IT",
+	[17] = "Colibri iMX6 DualLite 512MB IT",
+	[18] = "UNKNOWN MODULE",
+	[19] = "UNKNOWN MODULE",
+	[20] = "Colibri T20 256MB",
+	[21] = "Colibri T20 512MB",
+	[22] = "Colibri T20 512MB IT",
+	[23] = "Colibri T30 1GB",
+	[24] = "Colibri T20 256MB IT",
+	[25] = "Apalis T30 2GB",
+	[26] = "Apalis T30 1GB",
+	[27] = "Apalis iMX6 Quad 1GB",
+	[28] = "Apalis iMX6 Quad 2GB IT",
+	[29] = "Apalis iMX6 Dual 512MB",
+	[30] = "Colibri T30 1GB IT",
+	[31] = "Apalis T30 1GB IT",
+	[32] = "Colibri iMX7 Solo 256MB",
+	[33] = "Colibri iMX7 Dual 512MB",
+	[34] = "Apalis TK1 2GB",
+	[35] = "Apalis iMX6 Dual 1GB IT",
+	[36] = "Colibri iMX6ULL 256MB",
+	[37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT",
+	[38] = "Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT",
+	[39] = "Colibri iMX7 Dual 1GB (eMMC)",
+	[40] = "Colibri iMX6ULL 512MB Wi-Fi / BT IT",
+	[41] = "Colibri iMX7 Dual 512MB EPDC",
+	[42] = "Apalis TK1 4GB",
+	[43] = "Colibri T20 512MB IT SETEK",
+	[44] = "Colibri iMX6ULL 512MB IT",
+	[45] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth",
+	[46] = "Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT",
+	[47] = "Apalis iMX8 QuadMax 4GB IT",
+	[48] = "Apalis iMX8 QuadPlus 2GB Wi-Fi / BT",
+	[49] = "Apalis iMX8 QuadPlus 2GB",
+	[50] = "Colibri iMX8 QuadXPlus 2GB IT",
+	[51] = "Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth",
+	[52] = "Colibri iMX8 DualX 1GB",
+	[53] = "Apalis iMX8 QuadXPlus 2GB ECC IT",
+	[54] = "Apalis iMX8 DualXPlus 1GB",
+	[55] = "Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT",
+	[56] = "Verdin iMX8M Nano Quad 1GB Wi-Fi / BT", /* not currently on sale */
+	[57] = "Verdin iMX8M Mini DualLite 1GB",
+	[58] = "Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT",
+	[59] = "Verdin iMX8M Mini Quad 2GB IT",
+	[60] = "Verdin iMX8M Mini DualLite 1GB WB IT",
+	[61] = "Verdin iMX8M Plus Quad 2GB",
+};
+
+const char * const toradex_carrier_boards[] = {
+	[0] = "UNKNOWN CARRIER BOARD",
+	[155] = "Dahlia",
+	[156] = "Verdin Development Board",
+};
+
+const char * const toradex_display_adapters[] = {
+	[0] = "UNKNOWN DISPLAY ADAPTER",
+	[157] = "Verdin DSI to HDMI Adapter",
+	[159] = "Verdin DSI to LVDS Adapter",
+};
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
+static int tdx_cfg_block_mmc_storage(u8 *config_block, int write)
+{
+	struct mmc *mmc;
+	int dev = CONFIG_TDX_CFG_BLOCK_DEV;
+	int offset = CONFIG_TDX_CFG_BLOCK_OFFSET;
+	uint part = CONFIG_TDX_CFG_BLOCK_PART;
+	uint blk_start;
+	int ret = 0;
+
+	/* Read production parameter config block from eMMC */
+	mmc = find_mmc_device(dev);
+	if (!mmc) {
+		puts("No MMC card found\n");
+		ret = -ENODEV;
+		goto out;
+	}
+	if (mmc_init(mmc)) {
+		puts("MMC init failed\n");
+		return -EINVAL;
+	}
+	if (part != mmc_get_blk_desc(mmc)->hwpart) {
+		if (blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part)) {
+			puts("MMC partition switch failed\n");
+			ret = -ENODEV;
+			goto out;
+		}
+	}
+	if (offset < 0)
+		offset += mmc->capacity;
+	blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
+
+	if (!write) {
+		/* Careful reads a whole block of 512 bytes into config_block */
+		if (blk_dread(mmc_get_blk_desc(mmc), blk_start, 1,
+			      (unsigned char *)config_block) != 1) {
+			ret = -EIO;
+			goto out;
+		}
+	} else {
+		/* Just writing one 512 byte block */
+		if (blk_dwrite(mmc_get_blk_desc(mmc), blk_start, 1,
+			       (unsigned char *)config_block) != 1) {
+			ret = -EIO;
+			goto out;
+		}
+	}
+
+out:
+	/* Switch back to regular eMMC user partition */
+	blk_select_hwpart_devnum(IF_TYPE_MMC, 0, 0);
+
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_NAND
+static int read_tdx_cfg_block_from_nand(unsigned char *config_block)
+{
+	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+	struct mtd_info *mtd = get_nand_dev_by_index(0);
+
+	if (!mtd)
+		return -ENODEV;
+
+	/* Read production parameter config block from NAND page */
+	return nand_read_skip_bad(mtd, CONFIG_TDX_CFG_BLOCK_OFFSET,
+				  &size, NULL, TDX_CFG_BLOCK_MAX_SIZE,
+				  config_block);
+}
+
+static int write_tdx_cfg_block_to_nand(unsigned char *config_block)
+{
+	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+
+	/* Write production parameter config block to NAND page */
+	return nand_write_skip_bad(get_nand_dev_by_index(0),
+				   CONFIG_TDX_CFG_BLOCK_OFFSET,
+				   &size, NULL, TDX_CFG_BLOCK_MAX_SIZE,
+				   config_block, WITH_WR_VERIFY);
+}
+#endif
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_NOR
+static int read_tdx_cfg_block_from_nor(unsigned char *config_block)
+{
+	/* Read production parameter config block from NOR flash */
+	memcpy(config_block, (void *)CONFIG_TDX_CFG_BLOCK_OFFSET,
+	       TDX_CFG_BLOCK_MAX_SIZE);
+	return 0;
+}
+
+static int write_tdx_cfg_block_to_nor(unsigned char *config_block)
+{
+	/* Write production parameter config block to NOR flash */
+	return flash_write((void *)config_block, CONFIG_TDX_CFG_BLOCK_OFFSET,
+			   TDX_CFG_BLOCK_MAX_SIZE);
+}
+#endif
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_EEPROM
+static int read_tdx_cfg_block_from_eeprom(unsigned char *config_block)
+{
+	return read_tdx_eeprom_data(TDX_EEPROM_ID_MODULE, 0x0, config_block,
+				    TDX_CFG_BLOCK_MAX_SIZE);
+}
+
+static int write_tdx_cfg_block_to_eeprom(unsigned char *config_block)
+{
+	return write_tdx_eeprom_data(TDX_EEPROM_ID_MODULE, 0x0, config_block,
+				     TDX_CFG_BLOCK_MAX_SIZE);
+}
+#endif
+
+int read_tdx_cfg_block(void)
+{
+	int ret = 0;
+	u8 *config_block = NULL;
+	struct toradex_tag *tag;
+	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+	int offset;
+
+	/* Allocate RAM area for config block */
+	config_block = memalign(ARCH_DMA_MINALIGN, size);
+	if (!config_block) {
+		printf("Not enough malloc space available!\n");
+		return -ENOMEM;
+	}
+
+	memset(config_block, 0, size);
+
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
+	ret = tdx_cfg_block_mmc_storage(config_block, 0);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+	ret = read_tdx_cfg_block_from_nand(config_block);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+	ret = read_tdx_cfg_block_from_nor(config_block);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_EEPROM)
+	ret = read_tdx_cfg_block_from_eeprom(config_block);
+#else
+	ret = -EINVAL;
+#endif
+	if (ret)
+		goto out;
+
+	/* Expect a valid tag first */
+	tag = (struct toradex_tag *)config_block;
+	if (tag->flags != TAG_FLAG_VALID || tag->id != TAG_VALID) {
+		valid_cfgblock = false;
+		ret = -EINVAL;
+		goto out;
+	}
+	valid_cfgblock = true;
+	offset = 4;
+
+	/*
+	 * check if there is enough space for storing tag and value of the
+	 * biggest element
+	 */
+	while (offset + sizeof(struct toradex_tag) +
+	       sizeof(struct toradex_hw) < TDX_CFG_BLOCK_MAX_SIZE) {
+		tag = (struct toradex_tag *)(config_block + offset);
+		offset += 4;
+		if (tag->id == TAG_INVALID)
+			break;
+
+		if (tag->flags == TAG_FLAG_VALID) {
+			switch (tag->id) {
+			case TAG_MAC:
+				memcpy(&tdx_eth_addr, config_block + offset,
+				       6);
+
+				/* NIC part of MAC address is serial number */
+				tdx_serial = ntohl(tdx_eth_addr.nic) >> 8;
+				break;
+			case TAG_HW:
+				memcpy(&tdx_hw_tag, config_block + offset, 8);
+				break;
+			}
+		}
+
+		/* Get to next tag according to current tags length */
+		offset += tag->len * 4;
+	}
+
+	/* Cap product id to avoid issues with a yet unknown one */
+	if (tdx_hw_tag.prodid >= (sizeof(toradex_modules) /
+				  sizeof(toradex_modules[0])))
+		tdx_hw_tag.prodid = 0;
+
+out:
+	free(config_block);
+	return ret;
+}
+
+static int get_cfgblock_interactive(void)
+{
+	char message[CONFIG_SYS_CBSIZE];
+	char *soc;
+	char it = 'n';
+	char wb = 'n';
+	int len = 0;
+
+	/* Unknown module by default */
+	tdx_hw_tag.prodid = 0;
+
+	if (cpu_is_pxa27x())
+		sprintf(message, "Is the module the 312 MHz version? [y/N] ");
+	else
+		it = 'y';
+
+#if defined(CONFIG_TARGET_APALIS_IMX8) || \
+		defined(CONFIG_TARGET_APALIS_IMX8X) || \
+		defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \
+		defined(CONFIG_TARGET_COLIBRI_IMX8X) || \
+		defined(CONFIG_TARGET_VERDIN_IMX8MM) || \
+		defined(CONFIG_TARGET_VERDIN_IMX8MP)
+	sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] ");
+	len = cli_readline(message);
+	wb = console_buffer[0];
+#endif
+
+	soc = env_get("soc");
+	if (!strcmp("mx6", soc)) {
+#ifdef CONFIG_TARGET_APALIS_IMX6
+		if (it == 'y' || it == 'Y') {
+			if (is_cpu_type(MXC_CPU_MX6Q))
+				tdx_hw_tag.prodid = APALIS_IMX6Q_IT;
+			else
+				tdx_hw_tag.prodid = APALIS_IMX6D_IT;
+		} else {
+			if (is_cpu_type(MXC_CPU_MX6Q))
+				tdx_hw_tag.prodid = APALIS_IMX6Q;
+			else
+				tdx_hw_tag.prodid = APALIS_IMX6D;
+		}
+#elif CONFIG_TARGET_COLIBRI_IMX6
+		if (it == 'y' || it == 'Y') {
+			if (is_cpu_type(MXC_CPU_MX6DL))
+				tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT;
+			else if (is_cpu_type(MXC_CPU_MX6SOLO))
+				tdx_hw_tag.prodid = COLIBRI_IMX6S_IT;
+		} else {
+			if (is_cpu_type(MXC_CPU_MX6DL))
+				tdx_hw_tag.prodid = COLIBRI_IMX6DL;
+			else if (is_cpu_type(MXC_CPU_MX6SOLO))
+				tdx_hw_tag.prodid = COLIBRI_IMX6S;
+		}
+#elif CONFIG_TARGET_COLIBRI_IMX6ULL
+		if (it == 'y' || it == 'Y') {
+			if (wb == 'y' || wb == 'Y')
+				tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT_IT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT;
+		} else {
+			if (wb == 'y' || wb == 'Y')
+				tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_IMX6ULL;
+		}
+#endif
+	} else if (!strcmp("imx7d", soc))
+		tdx_hw_tag.prodid = COLIBRI_IMX7D;
+	else if (!strcmp("imx7s", soc))
+		tdx_hw_tag.prodid = COLIBRI_IMX7S;
+	else if (is_cpu_type(MXC_CPU_IMX8QM)) {
+		if (it == 'y' || it == 'Y') {
+			if (wb == 'y' || wb == 'Y')
+				tdx_hw_tag.prodid = APALIS_IMX8QM_WIFI_BT_IT;
+			else
+				tdx_hw_tag.prodid = APALIS_IMX8QM_IT;
+		} else {
+			if (wb == 'y' || wb == 'Y')
+				tdx_hw_tag.prodid = APALIS_IMX8QP_WIFI_BT;
+			else
+				tdx_hw_tag.prodid = APALIS_IMX8QP;
+		}
+	} else if (is_cpu_type(MXC_CPU_IMX8QXP)) {
+#ifdef CONFIG_TARGET_APALIS_IMX8X
+		if (it == 'y' || it == 'Y' || wb == 'y' || wb == 'Y') {
+				tdx_hw_tag.prodid = APALIS_IMX8QXP_WIFI_BT_IT;
+		} else {
+			if (gd->ram_size == 0x40000000)
+				tdx_hw_tag.prodid = APALIS_IMX8DXP;
+			else
+				tdx_hw_tag.prodid = APALIS_IMX8QXP;
+		}
+#elif CONFIG_TARGET_COLIBRI_IMX8X
+		if (it == 'y' || it == 'Y') {
+			if (wb == 'y' || wb == 'Y')
+				tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_IMX8QXP_IT;
+		} else {
+			if (wb == 'y' || wb == 'Y')
+				tdx_hw_tag.prodid = COLIBRI_IMX8DX_WIFI_BT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_IMX8DX;
+		}
+#endif
+	} else if (is_cpu_type(MXC_CPU_IMX8MMDL)) {
+		if (wb == 'y' || wb == 'Y')
+			tdx_hw_tag.prodid = VERDIN_IMX8MMDL_WIFI_BT_IT;
+		else
+			tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
+	} else if (is_cpu_type(MXC_CPU_IMX8MM)) {
+		if (wb == 'y' || wb == 'Y')
+			tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT;
+		else
+			tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT;
+	} else if (is_cpu_type(MXC_CPU_IMX8MN)) {
+		tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT;
+	} else if (is_cpu_type(MXC_CPU_IMX8MP)) {
+		if (wb == 'y' || wb == 'Y')
+			tdx_hw_tag.prodid = VERDIN_IMX8MPQ_WIFI_BT_IT;
+		else
+			tdx_hw_tag.prodid = VERDIN_IMX8MPQ;
+	} else if (!strcmp("tegra20", soc)) {
+		if (it == 'y' || it == 'Y')
+			if (gd->ram_size == 0x10000000)
+				tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_T20_512MB_IT;
+		else
+			if (gd->ram_size == 0x10000000)
+				tdx_hw_tag.prodid = COLIBRI_T20_256MB;
+			else
+				tdx_hw_tag.prodid = COLIBRI_T20_512MB;
+	} else if (cpu_is_pxa27x()) {
+		if (it == 'y' || it == 'Y')
+			tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ;
+		else
+			tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ;
+	}
+#ifdef CONFIG_MACH_TYPE
+	else if (!strcmp("tegra30", soc)) {
+		if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) {
+			if (it == 'y' || it == 'Y')
+				tdx_hw_tag.prodid = APALIS_T30_IT;
+			else
+				if (gd->ram_size == 0x40000000)
+					tdx_hw_tag.prodid = APALIS_T30_1GB;
+				else
+					tdx_hw_tag.prodid = APALIS_T30_2GB;
+		} else {
+			if (it == 'y' || it == 'Y')
+				tdx_hw_tag.prodid = COLIBRI_T30_IT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_T30;
+		}
+	}
+#endif /* CONFIG_MACH_TYPE */
+	else if (!strcmp("tegra124", soc)) {
+		tdx_hw_tag.prodid = APALIS_TK1_2GB;
+	} else if (!strcmp("vf500", soc)) {
+		if (it == 'y' || it == 'Y')
+			tdx_hw_tag.prodid = COLIBRI_VF50_IT;
+		else
+			tdx_hw_tag.prodid = COLIBRI_VF50;
+	} else if (!strcmp("vf610", soc)) {
+		if (it == 'y' || it == 'Y')
+			tdx_hw_tag.prodid = COLIBRI_VF61_IT;
+		else
+			tdx_hw_tag.prodid = COLIBRI_VF61;
+	}
+
+	if (!tdx_hw_tag.prodid) {
+		printf("Module type not detectable due to unknown SoC\n");
+		return -1;
+	}
+
+	while (len < 4) {
+		sprintf(message, "Enter the module version (e.g. V1.1B): V");
+		len = cli_readline(message);
+	}
+
+	tdx_hw_tag.ver_major = console_buffer[0] - '0';
+	tdx_hw_tag.ver_minor = console_buffer[2] - '0';
+	tdx_hw_tag.ver_assembly = console_buffer[3] - 'A';
+
+	if (cpu_is_pxa27x() && tdx_hw_tag.ver_major == 1)
+		tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ -
+				       COLIBRI_PXA270_V1_312MHZ);
+
+	while (len < 8) {
+		sprintf(message, "Enter module serial number: ");
+		len = cli_readline(message);
+	}
+
+	tdx_serial = simple_strtoul(console_buffer, NULL, 10);
+
+	return 0;
+}
+
+static int get_cfgblock_barcode(char *barcode, struct toradex_hw *tag,
+				u32 *serial)
+{
+	char revision[3] = {barcode[6], barcode[7], '\0'};
+
+	if (strlen(barcode) < 16) {
+		printf("Argument too short, barcode is 16 chars long\n");
+		return -1;
+	}
+
+	/* Get hardware information from the first 8 digits */
+	tag->ver_major = barcode[4] - '0';
+	tag->ver_minor = barcode[5] - '0';
+	tag->ver_assembly = simple_strtoul(revision, NULL, 10);
+
+	barcode[4] = '\0';
+	tag->prodid = simple_strtoul(barcode, NULL, 10);
+
+	/* Parse second part of the barcode (serial number */
+	barcode += 8;
+	*serial = simple_strtoul(barcode, NULL, 10);
+
+	return 0;
+}
+
+static int write_tag(u8 *config_block, int *offset, int tag_id,
+		     u8 *tag_data, size_t tag_data_size)
+{
+	struct toradex_tag *tag;
+
+	if (!offset || !config_block)
+		return -EINVAL;
+
+	tag = (struct toradex_tag *)(config_block + *offset);
+	tag->id = tag_id;
+	tag->flags = TAG_FLAG_VALID;
+	/* len is provided as number of 32bit values after the tag */
+	tag->len = (tag_data_size + sizeof(u32) - 1) / sizeof(u32);
+	*offset += sizeof(struct toradex_tag);
+	if (tag_data && tag_data_size) {
+		memcpy(config_block + *offset, tag_data,
+		       tag_data_size);
+		*offset += tag_data_size;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
+int read_tdx_cfg_block_carrier(void)
+{
+	int ret = 0;
+	u8 *config_block = NULL;
+	struct toradex_tag *tag;
+	size_t size = TDX_CFG_BLOCK_EXTRA_MAX_SIZE;
+	int offset;
+
+	/* Allocate RAM area for carrier config block */
+	config_block = memalign(ARCH_DMA_MINALIGN, size);
+	if (!config_block) {
+		printf("Not enough malloc space available!\n");
+		return -ENOMEM;
+	}
+
+	memset(config_block, 0, size);
+
+	ret = read_tdx_eeprom_data(TDX_EEPROM_ID_CARRIER, 0x0, config_block,
+				   size);
+	if (ret)
+		return ret;
+
+	/* Expect a valid tag first */
+	tag = (struct toradex_tag *)config_block;
+	if (tag->flags != TAG_FLAG_VALID || tag->id != TAG_VALID) {
+		valid_cfgblock_carrier = false;
+		ret = -EINVAL;
+		goto out;
+	}
+	valid_cfgblock_carrier = true;
+	offset = 4;
+
+	while (offset + sizeof(struct toradex_tag) +
+	       sizeof(struct toradex_hw) < TDX_CFG_BLOCK_MAX_SIZE) {
+		tag = (struct toradex_tag *)(config_block + offset);
+		offset += 4;
+		if (tag->id == TAG_INVALID)
+			break;
+
+		if (tag->flags == TAG_FLAG_VALID) {
+			switch (tag->id) {
+			case TAG_CAR_SERIAL:
+				memcpy(&tdx_car_serial, config_block + offset,
+				       sizeof(tdx_car_serial));
+				break;
+			case TAG_HW:
+				memcpy(&tdx_car_hw_tag, config_block +
+				       offset, 8);
+				break;
+			}
+		}
+
+		/* Get to next tag according to current tags length */
+		offset += tag->len * 4;
+	}
+out:
+	free(config_block);
+	return ret;
+}
+
+int check_pid8_sanity(char *pid8)
+{
+	char s_carrierid_verdin_dev[5];
+	char s_carrierid_dahlia[5];
+
+	sprintf(s_carrierid_verdin_dev, "0%d", VERDIN_DEVELOPMENT_BOARD);
+	sprintf(s_carrierid_dahlia, "0%d", DAHLIA);
+
+	/* sane value check, first 4 chars which represent carrier id */
+	if (!strncmp(pid8, s_carrierid_verdin_dev, 4))
+		return 0;
+
+	if (!strncmp(pid8, s_carrierid_dahlia, 4))
+		return 0;
+
+	return -EINVAL;
+}
+
+int try_migrate_tdx_cfg_block_carrier(void)
+{
+	char pid8[8];
+	int offset = 0;
+	int ret = CMD_RET_SUCCESS;
+	size_t size = TDX_CFG_BLOCK_EXTRA_MAX_SIZE;
+	u8 *config_block;
+
+	memset(pid8, 0x0, 8);
+	ret = read_tdx_eeprom_data(TDX_EEPROM_ID_CARRIER, 0x0, (u8 *)pid8, 8);
+	if (ret)
+		return ret;
+
+	if (check_pid8_sanity(pid8))
+		return -EINVAL;
+
+	/* Allocate RAM area for config block */
+	config_block = memalign(ARCH_DMA_MINALIGN, size);
+	if (!config_block) {
+		printf("Not enough malloc space available!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	memset(config_block, 0xff, size);
+	/* we try parse PID8 concatenating zeroed serial number */
+	tdx_car_hw_tag.ver_major = pid8[4] - '0';
+	tdx_car_hw_tag.ver_minor = pid8[5] - '0';
+	tdx_car_hw_tag.ver_assembly = pid8[7] - '0';
+
+	pid8[4] = '\0';
+	tdx_car_hw_tag.prodid = simple_strtoul(pid8, NULL, 10);
+
+	/* Valid Tag */
+	write_tag(config_block, &offset, TAG_VALID, NULL, 0);
+
+	/* Product Tag */
+	write_tag(config_block, &offset, TAG_HW, (u8 *)&tdx_car_hw_tag,
+		  sizeof(tdx_car_hw_tag));
+
+	/* Serial Tag */
+	write_tag(config_block, &offset, TAG_CAR_SERIAL, (u8 *)&tdx_car_serial,
+		  sizeof(tdx_car_serial));
+
+	memset(config_block + offset, 0, 32 - offset);
+	ret = write_tdx_eeprom_data(TDX_EEPROM_ID_CARRIER, 0x0, config_block,
+				    size);
+	if (ret) {
+		printf("Failed to write Toradex Extra config block: %d\n",
+		       ret);
+		ret = CMD_RET_FAILURE;
+		goto out;
+	}
+
+	printf("Successfully migrated to Toradex Config Block from PID8\n");
+
+out:
+	free(config_block);
+	return ret;
+}
+
+static int get_cfgblock_carrier_interactive(void)
+{
+	char message[CONFIG_SYS_CBSIZE];
+	int len;
+
+	printf("Supported carrier boards:\n");
+	printf("CARRIER BOARD NAME\t\t [ID]\n");
+	for (int i = 0; i < sizeof(toradex_carrier_boards) /
+			    sizeof(toradex_carrier_boards[0]); i++)
+		if (toradex_carrier_boards[i])
+			printf("%s \t\t [%d]\n", toradex_carrier_boards[i], i);
+
+	sprintf(message, "Choose your carrier board (provide ID): ");
+	len = cli_readline(message);
+	tdx_car_hw_tag.prodid = simple_strtoul(console_buffer, NULL, 10);
+
+	do {
+		sprintf(message, "Enter carrier board version (e.g. V1.1B): V");
+		len = cli_readline(message);
+	} while (len < 4);
+
+	tdx_car_hw_tag.ver_major = console_buffer[0] - '0';
+	tdx_car_hw_tag.ver_minor = console_buffer[2] - '0';
+	tdx_car_hw_tag.ver_assembly = console_buffer[3] - 'A';
+
+	while (len < 8) {
+		sprintf(message, "Enter carrier board serial number: ");
+		len = cli_readline(message);
+	}
+
+	tdx_car_serial = simple_strtoul(console_buffer, NULL, 10);
+
+	return 0;
+}
+
+static int do_cfgblock_carrier_create(struct cmd_tbl *cmdtp, int flag, int argc,
+				      char * const argv[])
+{
+	u8 *config_block;
+	size_t size = TDX_CFG_BLOCK_EXTRA_MAX_SIZE;
+	int offset = 0;
+	int ret = CMD_RET_SUCCESS;
+	int err;
+	int force_overwrite = 0;
+
+	if (argc >= 3) {
+		if (argv[2][0] == '-' && argv[2][1] == 'y')
+			force_overwrite = 1;
+	}
+
+	/* Allocate RAM area for config block */
+	config_block = memalign(ARCH_DMA_MINALIGN, size);
+	if (!config_block) {
+		printf("Not enough malloc space available!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	memset(config_block, 0xff, size);
+	read_tdx_cfg_block_carrier();
+	if (valid_cfgblock_carrier && !force_overwrite) {
+		char message[CONFIG_SYS_CBSIZE];
+
+		sprintf(message, "A valid Toradex Carrier config block is present, still recreate? [y/N] ");
+
+		if (!cli_readline(message))
+			goto out;
+
+		if (console_buffer[0] != 'y' &&
+		    console_buffer[0] != 'Y')
+			goto out;
+	}
+
+	if (argc < 3 || (force_overwrite && argc < 4)) {
+		err = get_cfgblock_carrier_interactive();
+	} else {
+		if (force_overwrite)
+			err = get_cfgblock_barcode(argv[3], &tdx_car_hw_tag,
+						   &tdx_car_serial);
+		else
+			err = get_cfgblock_barcode(argv[2], &tdx_car_hw_tag,
+						   &tdx_car_serial);
+	}
+
+	if (err) {
+		ret = CMD_RET_FAILURE;
+		goto out;
+	}
+
+	/* Valid Tag */
+	write_tag(config_block, &offset, TAG_VALID, NULL, 0);
+
+	/* Product Tag */
+	write_tag(config_block, &offset, TAG_HW, (u8 *)&tdx_car_hw_tag,
+		  sizeof(tdx_car_hw_tag));
+
+	/* Serial Tag */
+	write_tag(config_block, &offset, TAG_CAR_SERIAL, (u8 *)&tdx_car_serial,
+		  sizeof(tdx_car_serial));
+
+	memset(config_block + offset, 0, 32 - offset);
+	err = write_tdx_eeprom_data(TDX_EEPROM_ID_CARRIER, 0x0, config_block,
+				    size);
+	if (err) {
+		printf("Failed to write Toradex Extra config block: %d\n",
+		       ret);
+		ret = CMD_RET_FAILURE;
+		goto out;
+	}
+
+	printf("Toradex Extra config block successfully written\n");
+
+out:
+	free(config_block);
+	return ret;
+}
+
+#endif /* CONFIG_TDX_CFG_BLOCK_EXTRA */
+
+static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc,
+			      char * const argv[])
+{
+	u8 *config_block;
+	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+	int offset = 0;
+	int ret = CMD_RET_SUCCESS;
+	int err;
+	int force_overwrite = 0;
+
+	if (argc >= 3) {
+#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
+		if (!strcmp(argv[2], "carrier"))
+			return do_cfgblock_carrier_create(cmdtp, flag,
+							  --argc, ++argv);
+#endif /* CONFIG_TDX_CFG_BLOCK_EXTRA */
+		if (argv[2][0] == '-' && argv[2][1] == 'y')
+			force_overwrite = 1;
+	}
+
+	/* Allocate RAM area for config block */
+	config_block = memalign(ARCH_DMA_MINALIGN, size);
+	if (!config_block) {
+		printf("Not enough malloc space available!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	memset(config_block, 0xff, size);
+
+	read_tdx_cfg_block();
+	if (valid_cfgblock) {
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+		/*
+		 * On NAND devices, recreation is only allowed if the page is
+		 * empty (config block invalid...)
+		 */
+		printf("NAND erase block %d need to be erased before creating a Toradex config block\n",
+		       CONFIG_TDX_CFG_BLOCK_OFFSET /
+		       get_nand_dev_by_index(0)->erasesize);
+		goto out;
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+		/*
+		 * On NOR devices, recreation is only allowed if the sector is
+		 * empty and write protection is off (config block invalid...)
+		 */
+		printf("NOR sector at offset 0x%02x need to be erased and unprotected before creating a Toradex config block\n",
+		       CONFIG_TDX_CFG_BLOCK_OFFSET);
+		goto out;
+#else
+		if (!force_overwrite) {
+			char message[CONFIG_SYS_CBSIZE];
+
+			sprintf(message,
+				"A valid Toradex config block is present, still recreate? [y/N] ");
+
+			if (!cli_readline(message))
+				goto out;
+
+			if (console_buffer[0] != 'y' &&
+			    console_buffer[0] != 'Y')
+				goto out;
+		}
+#endif
+	}
+
+	/* Parse new Toradex config block data... */
+	if (argc < 3 || (force_overwrite && argc < 4)) {
+		err = get_cfgblock_interactive();
+	} else {
+		if (force_overwrite)
+			err = get_cfgblock_barcode(argv[3], &tdx_hw_tag,
+						   &tdx_serial);
+		else
+			err = get_cfgblock_barcode(argv[2], &tdx_hw_tag,
+						   &tdx_serial);
+	}
+	if (err) {
+		ret = CMD_RET_FAILURE;
+		goto out;
+	}
+
+	/* Convert serial number to MAC address (the storage format) */
+	tdx_eth_addr.oui = htonl(0x00142dUL << 8);
+	tdx_eth_addr.nic = htonl(tdx_serial << 8);
+
+	/* Valid Tag */
+	write_tag(config_block, &offset, TAG_VALID, NULL, 0);
+
+	/* Product Tag */
+	write_tag(config_block, &offset, TAG_HW, (u8 *)&tdx_hw_tag,
+		  sizeof(tdx_hw_tag));
+
+	/* MAC Tag */
+	write_tag(config_block, &offset, TAG_MAC, (u8 *)&tdx_eth_addr,
+		  sizeof(tdx_eth_addr));
+
+	memset(config_block + offset, 0, 32 - offset);
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
+	err = tdx_cfg_block_mmc_storage(config_block, 1);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+	err = write_tdx_cfg_block_to_nand(config_block);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+	err = write_tdx_cfg_block_to_nor(config_block);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_EEPROM)
+	err = write_tdx_cfg_block_to_eeprom(config_block);
+#else
+	err = -EINVAL;
+#endif
+	if (err) {
+		printf("Failed to write Toradex config block: %d\n", ret);
+		ret = CMD_RET_FAILURE;
+		goto out;
+	}
+
+	printf("Toradex config block successfully written\n");
+
+out:
+	free(config_block);
+	return ret;
+}
+
+static int do_cfgblock(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	int ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	if (!strcmp(argv[1], "create")) {
+		return do_cfgblock_create(cmdtp, flag, argc, argv);
+	} else if (!strcmp(argv[1], "reload")) {
+		ret = read_tdx_cfg_block();
+		if (ret) {
+			printf("Failed to reload Toradex config block: %d\n",
+			       ret);
+			return CMD_RET_FAILURE;
+		}
+		return CMD_RET_SUCCESS;
+	}
+
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+	cfgblock, 5, 0, do_cfgblock,
+	"Toradex config block handling commands",
+	"create [-y] [barcode] - (Re-)create Toradex config block\n"
+	"create carrier [-y] [barcode] - (Re-)create Toradex Carrier config block\n"
+	"cfgblock reload - Reload Toradex config block from flash"
+);
diff --git a/roms/u-boot/board/toradex/common/tdx-cfg-block.h b/roms/u-boot/board/toradex/common/tdx-cfg-block.h
new file mode 100644
index 000000000..9debd5f04
--- /dev/null
+++ b/roms/u-boot/board/toradex/common/tdx-cfg-block.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016-2020 Toradex
+ */
+
+#ifndef _TDX_CFG_BLOCK_H
+#define _TDX_CFG_BLOCK_H
+
+#include "tdx-common.h"
+
+struct toradex_hw {
+	u16 ver_major;
+	u16 ver_minor;
+	u16 ver_assembly;
+	u16 prodid;
+};
+
+struct toradex_eth_addr {
+	u32 oui:24;
+	u32 nic:24;
+} __attribute__((__packed__));
+
+enum {
+	COLIBRI_PXA270_V1_312MHZ = 1,
+	COLIBRI_PXA270_V1_520MHZ,
+	COLIBRI_PXA320,
+	COLIBRI_PXA300,
+	COLIBRI_PXA310, /* 5 */
+	COLIBRI_PXA320_IT,
+	COLIBRI_PXA300_XT,
+	COLIBRI_PXA270_312MHZ,
+	COLIBRI_PXA270_520MHZ,
+	COLIBRI_VF50, /* 10 */
+	COLIBRI_VF61, /* not currently on sale */
+	COLIBRI_VF61_IT,
+	COLIBRI_VF50_IT,
+	COLIBRI_IMX6S,
+	COLIBRI_IMX6DL, /* 15 */
+	COLIBRI_IMX6S_IT,
+	COLIBRI_IMX6DL_IT,
+	/* 18 */
+	/* 19 */
+	COLIBRI_T20_256MB = 20,
+	COLIBRI_T20_512MB,
+	COLIBRI_T20_512MB_IT,
+	COLIBRI_T30,
+	COLIBRI_T20_256MB_IT,
+	APALIS_T30_2GB, /* 25 */
+	APALIS_T30_1GB,
+	APALIS_IMX6Q,
+	APALIS_IMX6Q_IT,
+	APALIS_IMX6D,
+	COLIBRI_T30_IT, /* 30 */
+	APALIS_T30_IT,
+	COLIBRI_IMX7S,
+	COLIBRI_IMX7D,
+	APALIS_TK1_2GB,
+	APALIS_IMX6D_IT, /* 35 */
+	COLIBRI_IMX6ULL,
+	APALIS_IMX8QM_WIFI_BT_IT,
+	COLIBRI_IMX8QXP_WIFI_BT_IT,
+	COLIBRI_IMX7D_EMMC,
+	COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */
+	COLIBRI_IMX7D_EPDC,
+	APALIS_TK1_4GB, /* not currently on sale */
+	COLIBRI_T20_512MB_IT_SETEK,
+	COLIBRI_IMX6ULL_IT,
+	COLIBRI_IMX6ULL_WIFI_BT, /* 45 */
+	APALIS_IMX8QXP_WIFI_BT_IT,
+	APALIS_IMX8QM_IT,
+	APALIS_IMX8QP_WIFI_BT,
+	APALIS_IMX8QP,
+	COLIBRI_IMX8QXP_IT, /* 50 */
+	COLIBRI_IMX8DX_WIFI_BT,
+	COLIBRI_IMX8DX,
+	APALIS_IMX8QXP,
+	APALIS_IMX8DXP,
+	VERDIN_IMX8MMQ_WIFI_BT_IT, /* 55 */
+	VERDIN_IMX8MNQ_WIFI_BT,
+	VERDIN_IMX8MMDL,
+	VERDIN_IMX8MPQ_WIFI_BT_IT,
+	VERDIN_IMX8MMQ_IT,
+	VERDIN_IMX8MMDL_WIFI_BT_IT, /* 60 */
+	VERDIN_IMX8MPQ,
+};
+
+enum {
+	DAHLIA = 155,
+	VERDIN_DEVELOPMENT_BOARD = 156,
+};
+
+enum {
+	VERDIN_DSI_TO_HDMI_ADAPTER = 157,
+	VERDIN_DSI_TO_LVDS_ADAPTER = 159,
+};
+
+extern const char * const toradex_modules[];
+extern const char * const toradex_carrier_boards[];
+extern bool valid_cfgblock;
+extern struct toradex_hw tdx_hw_tag;
+extern struct toradex_hw tdx_car_hw_tag;
+extern struct toradex_eth_addr tdx_eth_addr;
+extern u32 tdx_serial;
+extern u32 tdx_car_serial;
+
+int read_tdx_cfg_block(void);
+int read_tdx_cfg_block_carrier(void);
+
+int try_migrate_tdx_cfg_block_carrier(void);
+
+#endif /* _TDX_CFG_BLOCK_H */
diff --git a/roms/u-boot/board/toradex/common/tdx-common.c b/roms/u-boot/board/toradex/common/tdx-common.c
new file mode 100644
index 000000000..a3d287ed5
--- /dev/null
+++ b/roms/u-boot/board/toradex/common/tdx-common.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ */
+
+#include <common.h>
+#include <env.h>
+#include <g_dnl.h>
+#include <init.h>
+#include <linux/libfdt.h>
+
+#ifdef CONFIG_DM_VIDEO
+#include <bmp_logo.h>
+#include <dm.h>
+#include <splash.h>
+#include <video.h>
+#endif
+
+#include "tdx-cfg-block.h"
+#include <asm/setup.h>
+#include "tdx-common.h"
+
+#define TORADEX_OUI 0x00142dUL
+
+#ifdef CONFIG_TDX_CFG_BLOCK
+static char tdx_serial_str[9];
+static char tdx_board_rev_str[6];
+
+#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
+static char tdx_car_serial_str[9];
+static char tdx_car_rev_str[6];
+static char *tdx_carrier_board_name;
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	/* Check validity */
+	if (!tdx_hw_tag.ver_major)
+		return 0;
+
+	return ((tdx_hw_tag.ver_major & 0xff) << 8) |
+		((tdx_hw_tag.ver_minor & 0xf) << 4) |
+		((tdx_hw_tag.ver_assembly & 0xf) + 0xa);
+}
+#endif /* CONFIG_TDX_CFG_BLOCK */
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	int array[8];
+	unsigned int serial = tdx_serial;
+	int i;
+
+	serialnr->low = 0;
+	serialnr->high = 0;
+
+	/* Check validity */
+	if (serial) {
+		/*
+		 * Convert to Linux serial number format (hexadecimal coded
+		 * decimal)
+		 */
+		i = 7;
+		while (serial) {
+			array[i--] = serial % 10;
+			serial /= 10;
+		}
+		while (i >= 0)
+			array[i--] = 0;
+		serial = array[0];
+		for (i = 1; i < 8; i++) {
+			serial *= 16;
+			serial += array[i];
+		}
+
+		serialnr->low = serial;
+	}
+}
+#endif /* CONFIG_SERIAL_TAG */
+
+int show_board_info(void)
+{
+	unsigned char ethaddr[6];
+
+	if (read_tdx_cfg_block()) {
+		printf("MISSING TORADEX CONFIG BLOCK\n");
+		tdx_eth_addr.oui = htonl(TORADEX_OUI << 8);
+		tdx_eth_addr.nic = htonl(tdx_serial << 8);
+		checkboard();
+	} else {
+		sprintf(tdx_serial_str, "%08u", tdx_serial);
+		sprintf(tdx_board_rev_str, "V%1d.%1d%c",
+			tdx_hw_tag.ver_major,
+			tdx_hw_tag.ver_minor,
+			(char)tdx_hw_tag.ver_assembly + 'A');
+
+		env_set("serial#", tdx_serial_str);
+
+		printf("Model: Toradex %s %s, Serial# %s\n",
+		       toradex_modules[tdx_hw_tag.prodid],
+		       tdx_board_rev_str,
+		       tdx_serial_str);
+#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
+		if (read_tdx_cfg_block_carrier()) {
+			printf("MISSING TORADEX CARRIER CONFIG BLOCKS\n");
+			try_migrate_tdx_cfg_block_carrier();
+		} else {
+			tdx_carrier_board_name = (char *)
+				toradex_carrier_boards[tdx_car_hw_tag.prodid];
+
+			sprintf(tdx_car_serial_str, "%08u", tdx_car_serial);
+			sprintf(tdx_car_rev_str, "V%1d.%1d%c",
+				tdx_car_hw_tag.ver_major,
+				tdx_car_hw_tag.ver_minor,
+				(char)tdx_car_hw_tag.ver_assembly +
+				'A');
+
+			env_set("carrier_serial#", tdx_car_serial_str);
+			printf("Carrier: Toradex %s %s, Serial# %s\n",
+			       tdx_carrier_board_name,
+			       tdx_car_rev_str,
+			       tdx_car_serial_str);
+		}
+#endif
+	}
+
+	/*
+	 * Check if environment contains a valid MAC address,
+	 * set the one from config block if not
+	 */
+	if (!eth_env_get_enetaddr("ethaddr", ethaddr))
+		eth_env_set_enetaddr("ethaddr", (u8 *)&tdx_eth_addr);
+
+#ifdef CONFIG_TDX_CFG_BLOCK_2ND_ETHADDR
+	if (!eth_env_get_enetaddr("eth1addr", ethaddr)) {
+		/*
+		 * Secondary MAC address is allocated from block
+		 * 0x100000 higher then the first MAC address
+		 */
+		memcpy(ethaddr, &tdx_eth_addr, 6);
+		ethaddr[3] += 0x10;
+		eth_env_set_enetaddr("eth1addr", ethaddr);
+	}
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_GADGET_DOWNLOAD
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	unsigned short usb_pid;
+
+	usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + tdx_hw_tag.prodid;
+	put_unaligned(usb_pid, &dev->idProduct);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT)
+int ft_common_board_setup(void *blob, struct bd_info *bd)
+{
+	if (tdx_serial) {
+		fdt_setprop(blob, 0, "serial-number", tdx_serial_str,
+			    strlen(tdx_serial_str) + 1);
+	}
+
+	if (tdx_hw_tag.ver_major) {
+		char prod_id[5];
+
+		sprintf(prod_id, "%04u", tdx_hw_tag.prodid);
+		fdt_setprop(blob, 0, "toradex,product-id", prod_id, 5);
+
+		fdt_setprop(blob, 0, "toradex,board-rev", tdx_board_rev_str,
+			    strlen(tdx_board_rev_str) + 1);
+	}
+
+	return 0;
+}
+#endif
+
+#else /* CONFIG_TDX_CFG_BLOCK */
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	return 0;
+}
+#endif /* CONFIG_REVISION_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+u32 get_board_serial(void)
+{
+	return 0;
+}
+#endif /* CONFIG_SERIAL_TAG */
+
+int ft_common_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+
+#endif /* CONFIG_TDX_CFG_BLOCK */
diff --git a/roms/u-boot/board/toradex/common/tdx-common.h b/roms/u-boot/board/toradex/common/tdx-common.h
new file mode 100644
index 000000000..8020df5b4
--- /dev/null
+++ b/roms/u-boot/board/toradex/common/tdx-common.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ */
+
+#ifndef _TDX_COMMON_H
+#define _TDX_COMMON_H
+
+#define TORADEX_USB_PRODUCT_NUM_OFFSET	0x4000
+#define TDX_USB_VID			0x1B67
+
+int ft_common_board_setup(void *blob, struct bd_info *bd);
+
+#if defined(CONFIG_DM_VIDEO)
+int show_boot_logo(void);
+#endif
+
+#endif /* _TDX_COMMON_H */
diff --git a/roms/u-boot/board/toradex/common/tdx-eeprom.c b/roms/u-boot/board/toradex/common/tdx-eeprom.c
new file mode 100644
index 000000000..81bd9e68c
--- /dev/null
+++ b/roms/u-boot/board/toradex/common/tdx-eeprom.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Toradex
+ */
+
+#include <dm.h>
+#include <i2c_eeprom.h>
+#include <asm/global_data.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int get_tdx_eeprom(u32 eeprom_id, struct udevice **devp)
+{
+	int ret = 0;
+	int node;
+	ofnode eeprom;
+	char eeprom_str[16];
+	const char *path;
+
+	if (!gd->fdt_blob) {
+		printf("%s: don't have a valid gd->fdt_blob!\n", __func__);
+		return -EFAULT;
+	}
+
+	node = fdt_path_offset(gd->fdt_blob, "/aliases");
+	if (node < 0)
+		return -ENODEV;
+
+	sprintf(eeprom_str, "eeprom%d", eeprom_id);
+
+	path = fdt_getprop(gd->fdt_blob, node, eeprom_str, NULL);
+	if (!path) {
+		printf("%s: no alias for %s\n", __func__, eeprom_str);
+		return -ENODEV;
+	}
+
+	eeprom = ofnode_path(path);
+	if (!ofnode_valid(eeprom)) {
+		printf("%s: invalid hardware path to EEPROM\n", __func__);
+		return -ENODEV;
+	}
+
+	ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, devp);
+	if (ret) {
+		printf("%s: cannot find EEPROM by node\n", __func__);
+		return ret;
+	}
+
+	return ret;
+}
+
+int read_tdx_eeprom_data(u32 eeprom_id, int offset, u8 *buf,
+			 int size)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = get_tdx_eeprom(eeprom_id, &dev);
+	if (ret)
+		return ret;
+
+	ret = i2c_eeprom_read(dev, 0x0, buf, size);
+	if (ret) {
+		printf("%s: error reading data from EEPROM id: %d!, ret = %d\n",
+		       __func__, eeprom_id, ret);
+		return ret;
+	}
+
+	return ret;
+}
+
+int write_tdx_eeprom_data(u32 eeprom_id, int offset, u8 *buf,
+			  int size)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = get_tdx_eeprom(eeprom_id, &dev);
+	if (ret)
+		return ret;
+
+	ret = i2c_eeprom_write(dev, 0x0, buf, size);
+	if (ret) {
+		printf("%s: error writing data to EEPROM id: %d, ret = %d\n",
+		       __func__, eeprom_id, ret);
+		return ret;
+	}
+
+	return ret;
+}
diff --git a/roms/u-boot/board/toradex/common/tdx-eeprom.h b/roms/u-boot/board/toradex/common/tdx-eeprom.h
new file mode 100644
index 000000000..a6772d2f3
--- /dev/null
+++ b/roms/u-boot/board/toradex/common/tdx-eeprom.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 Toradex
+ */
+
+#ifndef _TDX_EEPROM_H
+#define _TDX_EEPROM_H
+
+#include <i2c_eeprom.h>
+
+int read_tdx_eeprom_data(u32 eeprom_id, int offset, uint8_t *buf, int size);
+int write_tdx_eeprom_data(u32 eeprom_id, int offset, uint8_t *buf, int size);
+
+#endif /* _TDX_EEPROM_H */
diff --git a/roms/u-boot/board/toradex/verdin-imx8mm/Kconfig b/roms/u-boot/board/toradex/verdin-imx8mm/Kconfig
new file mode 100644
index 000000000..149aed6da
--- /dev/null
+++ b/roms/u-boot/board/toradex/verdin-imx8mm/Kconfig
@@ -0,0 +1,36 @@
+if TARGET_VERDIN_IMX8MM
+
+config SYS_BOARD
+	default "verdin-imx8mm"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "verdin-imx8mm"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_CFG_BLOCK_EXTRA
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_HAVE_EEPROM_EXTRA
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/toradex/verdin-imx8mm/MAINTAINERS b/roms/u-boot/board/toradex/verdin-imx8mm/MAINTAINERS
new file mode 100644
index 000000000..08c370178
--- /dev/null
+++ b/roms/u-boot/board/toradex/verdin-imx8mm/MAINTAINERS
@@ -0,0 +1,10 @@
+Verdin iMX8M Mini
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+W:	https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini
+S:	Maintained
+F:	arch/arm/dts/imx8mm-verdin.dts
+F:	arch/arm/dts/imx8mm-verdin-u-boot.dtsi
+F:	board/toradex/verdin-imx8mm/
+F:	configs/verdin-imx8mm_defconfig
+F:	doc/board/toradex/verdin-imx8mm.rst
+F:	include/configs/verdin-imx8mm.h
diff --git a/roms/u-boot/board/toradex/verdin-imx8mm/Makefile b/roms/u-boot/board/toradex/verdin-imx8mm/Makefile
new file mode 100644
index 000000000..b38054254
--- /dev/null
+++ b/roms/u-boot/board/toradex/verdin-imx8mm/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 Toradex
+#
+
+obj-y += verdin-imx8mm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/roms/u-boot/board/toradex/verdin-imx8mm/imximage.cfg b/roms/u-boot/board/toradex/verdin-imx8mm/imximage.cfg
new file mode 100644
index 000000000..b8b25ff42
--- /dev/null
+++ b/roms/u-boot/board/toradex/verdin-imx8mm/imximage.cfg
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Toradex
+ */
+
+#define __ASSEMBLY__
+
+FIT
+BOOT_FROM	emmc_fastboot
+LOADER		spl/u-boot-spl-ddr.bin	0x7E1000
+SECOND_LOADER	u-boot.itb		0x40200000 0x60000
+
+DDR_FW lpddr4_pmu_train_1d_imem.bin
+DDR_FW lpddr4_pmu_train_1d_dmem.bin
+DDR_FW lpddr4_pmu_train_2d_imem.bin
+DDR_FW lpddr4_pmu_train_2d_dmem.bin
diff --git a/roms/u-boot/board/toradex/verdin-imx8mm/lpddr4_timing.c b/roms/u-boot/board/toradex/verdin-imx8mm/lpddr4_timing.c
new file mode 100644
index 000000000..d114abf9d
--- /dev/null
+++ b/roms/u-boot/board/toradex/verdin-imx8mm/lpddr4_timing.c
@@ -0,0 +1,1850 @@
+// SPDX-License-Identifier:     GPL-2.0+
+/*
+ * Copyright 2020 Toradex
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ *
+ * DDR calibration created with mscale_ddr_tool_v210_setup.exe using
+ * MX8M_Mini_LPDDR4_RPA_v14 Verdin iMX8MM V1.0.xlsx as of 1. Nov. 2019.
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa1080020},
+	{0x3d400020, 0x203},
+	{0x3d400024, 0x3a980},
+	{0x3d400064, 0x5b00d2},
+	{0x3d4000d0, 0xc00305ba},
+	{0x3d4000d4, 0x940000},
+	{0x3d4000dc, 0xd4002d},
+	{0x3d4000e0, 0x310000},
+	{0x3d4000e8, 0x66004d},
+	{0x3d4000ec, 0x16004d},
+	{0x3d400100, 0x191e1920},
+	{0x3d400104, 0x60630},
+	{0x3d40010c, 0xb0b000},
+	{0x3d400110, 0xe04080e},
+	{0x3d400114, 0x2040c0c},
+	{0x3d400118, 0x1010007},
+	{0x3d40011c, 0x401},
+	{0x3d400130, 0x20600},
+	{0x3d400134, 0xc100002},
+	{0x3d400138, 0xd8},
+	{0x3d400144, 0x96004b},
+	{0x3d400180, 0x2ee0017},
+	{0x3d400184, 0x2605b8e},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x497820a},
+	{0x3d400194, 0x80303},
+	{0x3d4001b4, 0x170a},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x1},
+	{0x3d4000f4, 0xc99},
+	{0x3d400108, 0x70e1617},
+	{0x3d400200, 0x1f},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0x7070707},
+	{0x3d400250, 0x29001701},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x4000030},
+	{0x3d400264, 0x900093e7},
+	{0x3d40026c, 0x2005574},
+	{0x3d400400, 0x111},
+	{0x3d400408, 0x72ff},
+	{0x3d400494, 0x2100e07},
+	{0x3d400498, 0x620096},
+	{0x3d40049c, 0x1100e07},
+	{0x3d4004a0, 0xc8012c},
+	{0x3d402020, 0x1},
+	{0x3d402024, 0x7d00},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0xc001c},
+	{0x3d4020dc, 0x840000},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004d},
+	{0x3d4020ec, 0x16004d},
+	{0x3d402100, 0xa040305},
+	{0x3d402104, 0x30407},
+	{0x3d402108, 0x203060b},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x2040202},
+	{0x3d402114, 0x2030202},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x1d},
+	{0x3d402144, 0x14000a},
+	{0x3d402180, 0x640004},
+	{0x3d402190, 0x3818200},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x100},
+	{0x3d4020f4, 0xc99},
+	{0x3d403020, 0x1},
+	{0x3d403024, 0x1f40},
+	{0x3d403050, 0x20d040},
+	{0x3d403064, 0x30007},
+	{0x3d4030dc, 0x840000},
+	{0x3d4030e0, 0x310000},
+	{0x3d4030e8, 0x66004d},
+	{0x3d4030ec, 0x16004d},
+	{0x3d403100, 0xa010102},
+	{0x3d403104, 0x30404},
+	{0x3d403108, 0x203060b},
+	{0x3d40310c, 0x505000},
+	{0x3d403110, 0x2040202},
+	{0x3d403114, 0x2030202},
+	{0x3d403118, 0x1010004},
+	{0x3d40311c, 0x301},
+	{0x3d403130, 0x20300},
+	{0x3d403134, 0xa100002},
+	{0x3d403138, 0x8},
+	{0x3d403144, 0x50003},
+	{0x3d403180, 0x190004},
+	{0x3d403190, 0x3818200},
+	{0x3d403194, 0x80303},
+	{0x3d4031b4, 0x100},
+	{0x3d4030f4, 0xc99},
+	{0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x3},
+	{0x110a3, 0x4},
+	{0x110a4, 0x5},
+	{0x110a5, 0x2},
+	{0x110a6, 0x6},
+	{0x110a7, 0x7},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x3},
+	{0x120a3, 0x4},
+	{0x120a4, 0x5},
+	{0x120a5, 0x2},
+	{0x120a6, 0x6},
+	{0x120a7, 0x7},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x21005f, 0x1ff},
+	{0x21015f, 0x1ff},
+	{0x21105f, 0x1ff},
+	{0x21115f, 0x1ff},
+	{0x21205f, 0x1ff},
+	{0x21215f, 0x1ff},
+	{0x21305f, 0x1ff},
+	{0x21315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x19},
+	{0x1200c5, 0x7},
+	{0x2200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x2},
+	{0x22002e, 0x2},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x220024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x3},
+	{0x120056, 0xa},
+	{0x220056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x21004d, 0xe00},
+	{0x21014d, 0xe00},
+	{0x21104d, 0xe00},
+	{0x21114d, 0xe00},
+	{0x21204d, 0xe00},
+	{0x21214d, 0xe00},
+	{0x21304d, 0xe00},
+	{0x21314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x210049, 0xeba},
+	{0x210149, 0xeba},
+	{0x211049, 0xeba},
+	{0x211149, 0xeba},
+	{0x212049, 0xeba},
+	{0x212149, 0xeba},
+	{0x213049, 0xeba},
+	{0x213149, 0xeba},
+	{0x43, 0x63},
+	{0x1043, 0x63},
+	{0x2043, 0x63},
+	{0x3043, 0x63},
+	{0x4043, 0x63},
+	{0x5043, 0x63},
+	{0x6043, 0x63},
+	{0x7043, 0x63},
+	{0x8043, 0x63},
+	{0x9043, 0x63},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x2ee},
+	{0x120008, 0x64},
+	{0x220008, 0x19},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x2200b2, 0xdc},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
+	{0x212043, 0x5a1},
+	{0x212143, 0x5a1},
+	{0x213043, 0x5a1},
+	{0x213143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x2200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
+	{0x200f0, 0x660},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5665},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x200c7, 0x21},
+	{0x1200c7, 0x21},
+	{0x2200c7, 0x21},
+	{0x200ca, 0x24},
+	{0x1200ca, 0x24},
+	{0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xbb8},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x101},
+	{0x54003, 0x190},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x64},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x84},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x84},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x8400},
+	{0x54033, 0x3100},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0x8400},
+	{0x54039, 0x3100},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xbb8},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4d66},
+	{0x5401c, 0x4d00},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4d66},
+	{0x54022, 0x4d00},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x4d},
+	{0x54036, 0x4d},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x4d},
+	{0x5403c, 0x4d},
+	{0x5403d, 0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x5d},
+	{0x2000c, 0xbb},
+	{0x2000d, 0x753},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xc},
+	{0x12000c, 0x19},
+	{0x12000d, 0xfa},
+	{0x12000e, 0x10},
+	{0x22000b, 0x3},
+	{0x22000c, 0x6},
+	{0x22000d, 0x3e},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x220010, 0x5a},
+	{0x220011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
diff --git a/roms/u-boot/board/toradex/verdin-imx8mm/spl.c b/roms/u-boot/board/toradex/verdin-imx8mm/spl.c
new file mode 100644
index 000000000..97d6a31da
--- /dev/null
+++ b/roms/u-boot/board/toradex/verdin-imx8mm/spl.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Toradex
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <cpu_func.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/uclass.h>
+#include <dm/uclass-internal.h>
+#include <hang.h>
+#include <i2c.h>
+#include <power/bd71837.h>
+#include <power/pca9450.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_PMIC_BUS_ID        1
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case MMC1_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC2;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+#define UART_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+/* Verdin UART_3, Console/Debug UART */
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) {
+		ret = pmic_get("pmic", &dev);
+		if (ret == -ENODEV) {
+			puts("No pmic found\n");
+			return ret;
+		}
+
+		if (ret != 0)
+			return ret;
+
+		/* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
+		pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+		/* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */
+		pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
+
+		/* set WDOG_B_CFG to cold reset */
+		pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+
+		pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
+
+		return 0;
+	}
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0) {
+		printf("Failed to find clock node. Check device tree\n");
+		hang();
+	}
+
+	enable_tzc380();
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/roms/u-boot/board/toradex/verdin-imx8mm/verdin-imx8mm.c
new file mode 100644
index 000000000..76f4a1e20
--- /dev/null
+++ b/roms/u-boot/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Toradex
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <micrel.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_PMIC	0
+
+enum pcb_rev_t {
+	PCB_VERSION_1_0,
+	PCB_VERSION_1_1
+};
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	int tmp;
+
+	switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
+	case PHY_ID_KSZ9031:
+		/*
+		 * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by
+		 * default. The MAC and the layout don't add a skew between
+		 * clock and data.
+		 * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for
+		 * the TXC path to get the required clock skews.
+		 */
+		/* control data pad skew - devaddr = 0x02, register = 0x04 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0070);
+		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x7777);
+		/* tx data pad skew - devaddr = 0x02, register = 0x06 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x03f4);
+		break;
+	case PHY_ID_KSZ9131:
+	default:
+		/* read rxc dll control - devaddr = 0x2, register = 0x4c */
+		tmp = ksz9031_phy_extended_read(phydev, 0x02,
+					MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+					MII_KSZ9031_MOD_DATA_NO_POST_INC);
+		/* disable rxdll bypass (enable 2ns skew delay on RXC) */
+		tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+		/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
+		tmp = ksz9031_phy_extended_write(phydev, 0x02,
+					MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+					MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
+		/* read txc dll control - devaddr = 0x02, register = 0x4d */
+		tmp = ksz9031_phy_extended_read(phydev, 0x02,
+					MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+					MII_KSZ9031_MOD_DATA_NO_POST_INC);
+		/* disable txdll bypass (enable 2ns skew delay on TXC) */
+		tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+		/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
+		tmp = ksz9031_phy_extended_write(phydev, 0x02,
+					MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+					MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
+		break;
+	}
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_FEC_MXC))
+		setup_fec();
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+static enum pcb_rev_t get_pcb_revision(void)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+	int ret;
+	u8 is_bd71837 = 0;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_PMIC, &bus);
+	if (!ret)
+		ret = dm_i2c_probe(bus, 0x4b, 0, &i2c_dev);
+	if (!ret)
+		ret = dm_i2c_read(i2c_dev, 0x0, &is_bd71837, 1);
+
+	/* BD71837_REV, High Nibble is major version, fix 1010 */
+	is_bd71837 = !ret && ((is_bd71837 & 0xf0) == 0xa0);
+	return is_bd71837 ? PCB_VERSION_1_0 : PCB_VERSION_1_1;
+}
+
+static void select_dt_from_module_version(void)
+{
+	char variant[32];
+	char *env_variant = env_get("variant");
+	int is_wifi = 0;
+
+	if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) {
+		/*
+		 * If we have a valid config block and it says we are a
+		 * module with Wi-Fi/Bluetooth make sure we use the -wifi
+		 * device tree.
+		 */
+		is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) ||
+			  (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT);
+	}
+
+	switch (get_pcb_revision()) {
+	case PCB_VERSION_1_0:
+		printf("Detected a V1.0 module\n");
+		if (is_wifi)
+			strncpy(&variant[0], "wifi", sizeof(variant));
+		else
+			strncpy(&variant[0], "nonwifi", sizeof(variant));
+		break;
+	default:
+		if (is_wifi)
+			strncpy(&variant[0], "wifi-v1.1", sizeof(variant));
+		else
+			strncpy(&variant[0], "nonwifi-v1.1", sizeof(variant));
+		break;
+	}
+
+	if (strcmp(variant, env_variant)) {
+		printf("Setting variant to %s\n", variant);
+		env_set("variant", variant);
+
+		if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
+			env_save();
+	}
+}
+
+int board_late_init(void)
+{
+	select_dt_from_module_version();
+
+	return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+	if (!size)
+		return -EINVAL;
+
+	*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/tplink/wdr4300/Kconfig b/roms/u-boot/board/tplink/wdr4300/Kconfig
new file mode 100644
index 000000000..67a022877
--- /dev/null
+++ b/roms/u-boot/board/tplink/wdr4300/Kconfig
@@ -0,0 +1,30 @@
+if BOARD_TPLINK_WDR4300
+
+config SYS_VENDOR
+	default "tplink"
+
+config SYS_SOC
+	default "ath79"
+
+config SYS_BOARD
+	default "wdr4300"
+
+config SYS_CONFIG_NAME
+	default "tplink_wdr4300"
+
+config SYS_TEXT_BASE
+	default 0xa1000000
+
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_ICACHE_LINE_SIZE
+	default 32
+
+endif
diff --git a/roms/u-boot/board/tplink/wdr4300/MAINTAINERS b/roms/u-boot/board/tplink/wdr4300/MAINTAINERS
new file mode 100644
index 000000000..db239c291
--- /dev/null
+++ b/roms/u-boot/board/tplink/wdr4300/MAINTAINERS
@@ -0,0 +1,6 @@
+TPLINK_WDR4300 BOARD
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+F:	board/tplink/wdr4300/
+F:	include/configs/tplink_wdr4300.h
+F:	configs/tplink_wdr4300_defconfig
diff --git a/roms/u-boot/board/tplink/wdr4300/Makefile b/roms/u-boot/board/tplink/wdr4300/Makefile
new file mode 100644
index 000000000..323a104bf
--- /dev/null
+++ b/roms/u-boot/board/tplink/wdr4300/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	= wdr4300.o
diff --git a/roms/u-boot/board/tplink/wdr4300/wdr4300.c b/roms/u-boot/board/tplink/wdr4300/wdr4300.c
new file mode 100644
index 000000000..9134d6bf6
--- /dev/null
+++ b/roms/u-boot/board/tplink/wdr4300/wdr4300.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+#ifdef CONFIG_USB
+static void wdr4300_usb_start(void)
+{
+	void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE,
+					      AR71XX_GPIO_SIZE, MAP_NOCACHE);
+	if (!gpio_regs)
+		return;
+
+	/* Power up the USB HUB. */
+	clrbits_be32(gpio_regs + AR71XX_GPIO_REG_OE, BIT(21) | BIT(22));
+	writel(BIT(21) | BIT(22), gpio_regs + AR71XX_GPIO_REG_SET);
+	mdelay(1);
+
+	ath79_usb_reset();
+}
+#else
+static inline void wdr4300_usb_start(void) {}
+#endif
+
+void wdr4300_pinmux_config(void)
+{
+	void __iomem *regs;
+
+	regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+			   MAP_NOCACHE);
+
+	/* Assure JTAG is not disconnected. */
+	writel(0x40, regs + AR934X_GPIO_REG_FUNC);
+
+	/* Configure default GPIO input/output regs. */
+	writel(0x3031b, regs + AR71XX_GPIO_REG_OE);
+	writel(0x0f804, regs + AR71XX_GPIO_REG_OUT);
+
+	/* Configure pin multiplexing. */
+	writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC0);
+	writel(0x0b0a0980, regs + AR934X_GPIO_REG_OUT_FUNC1);
+	writel(0x00180000, regs + AR934X_GPIO_REG_OUT_FUNC2);
+	writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3);
+	writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4);
+	writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5);
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	wdr4300_pinmux_config();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifndef CONFIG_DEBUG_UART_BOARD_INIT
+	wdr4300_pinmux_config();
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	ar934x_pll_init(560, 480, 240);
+	ar934x_ddr_init(560, 480, 240);
+#endif
+
+	wdr4300_usb_start();
+	ath79_eth_reset();
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/tqc/tqm834x/Kconfig b/roms/u-boot/board/tqc/tqm834x/Kconfig
new file mode 100644
index 000000000..028b8466e
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqm834x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TQM834X
+
+config SYS_BOARD
+	default "tqm834x"
+
+config SYS_VENDOR
+	default "tqc"
+
+config SYS_CONFIG_NAME
+	default "TQM834x"
+
+endif
diff --git a/roms/u-boot/board/tqc/tqm834x/MAINTAINERS b/roms/u-boot/board/tqc/tqm834x/MAINTAINERS
new file mode 100644
index 000000000..543ab1b55
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqm834x/MAINTAINERS
@@ -0,0 +1,6 @@
+TQM834X BOARD
+#M:	-
+S:	Maintained
+F:	board/tqc/tqm834x/
+F:	include/configs/TQM834x.h
+F:	configs/TQM834x_defconfig
diff --git a/roms/u-boot/board/tqc/tqm834x/Makefile b/roms/u-boot/board/tqc/tqm834x/Makefile
new file mode 100644
index 000000000..3aafbf792
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqm834x/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+
+obj-y += tqm834x.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/roms/u-boot/board/tqc/tqm834x/pci.c b/roms/u-boot/board/tqc/tqm834x/pci.c
new file mode 100644
index 000000000..92bda6076
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqm834x/pci.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ */
+
+#include <init.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+#include <linux/delay.h>
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
+ * per TQM834x design physical connections to external devices (PCI sockets)
+ * are routed only to the PCI1 we do not account for the second one - this code
+ * supports PCI1 module only. Should support for the PCI2 be required in the
+ * future it needs a separate pci_controller structure (above) and handling -
+ * please refer to other boards' implementation for dual PCI host controllers,
+ * for example board/Marvell/db64360/pci.c, pci_init_board()
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci1_regions };
+	u32 reg32;
+
+	/*
+	 * Configure PCI controller and PCI_CLK_OUTPUT
+	 *
+	 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
+	 * line actually used for clocking all external PCI devices in TQM83xx.
+	 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
+	 * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
+	 * are known to hang the board; this issue is under investigation
+	 * (13 oct 05)
+	 */
+	reg32 = OCCR_PCICOE1;
+#if 0
+	/* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
+	reg32 = 0xff000000;
+#endif
+	if (clk->spmr & SPMR_CKID) {
+		/* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR
+		 * fields accordingly */
+		reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
+
+		reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
+			  | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
+			  | OCCR_PCICD6 | OCCR_PCICD7);
+	}
+
+	clk->occr = reg32;
+	udelay(2000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
+
+	udelay(2000);
+
+	mpc83xx_pci_init(1, reg);
+}
diff --git a/roms/u-boot/board/tqc/tqm834x/tqm834x.c b/roms/u-boot/board/tqc/tqm834x/tqm834x.c
new file mode 100644
index 000000000..17b4662c1
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqm834x/tqm834x.c
@@ -0,0 +1,433 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <ioports.h>
+#include <log.h>
+#include <mpc83xx.h>
+#include <asm/global_data.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/mmu.h>
+#include <pci.h>
+#include <flash.h>
+#include <linux/delay.h>
+#include <mtd/cfi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IOSYNC			asm("eieio")
+#define ISYNC			asm("isync")
+#define SYNC			asm("sync")
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+#define DDR_MAX_SIZE_PER_CS	0x20000000
+
+#if defined(DDR_CASLAT_20)
+#define TIMING_CASLAT		TIMING_CFG1_CASLAT_20
+#define MODE_CASLAT		DDR_MODE_CASLAT_20
+#else
+#define TIMING_CASLAT		TIMING_CFG1_CASLAT_25
+#define MODE_CASLAT		DDR_MODE_CASLAT_25
+#endif
+
+#define INITIAL_CS_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
+				CSCONFIG_COL_BIT_9)
+
+/* External definitions */
+ulong flash_get_size (ulong base, int banknum);
+
+/* Local functions */
+static int detect_num_flash_banks(void);
+static long int get_ddr_bank_size(short cs, long *base);
+static void set_cs_bounds(short cs, ulong base, ulong size);
+static void set_cs_config(short cs, long config);
+static void set_ddr_config(void);
+
+/* Local variable */
+static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+/**************************************************************************
+ * Board initialzation after relocation to RAM. Used to detect the number
+ * of Flash banks on TQM834x.
+ */
+int board_early_init_r (void) {
+	/* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return 0;
+
+	/* detect the number of Flash banks */
+	return detect_num_flash_banks();
+}
+
+/**************************************************************************
+ * DRAM initalization and size detection
+ */
+int dram_init(void)
+{
+	long bank_size;
+	long size;
+	int cs;
+
+	/* during size detection, set up the max DDRLAW size */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE;
+	im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
+
+	/* set CS bounds to maximum size */
+	for(cs = 0; cs < 4; ++cs) {
+		set_cs_bounds(cs,
+			CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS),
+			DDR_MAX_SIZE_PER_CS);
+
+		set_cs_config(cs, INITIAL_CS_CONFIG);
+	}
+
+	/* configure ddr controller */
+	set_ddr_config();
+
+	udelay(200);
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
+		SDRAM_CFG_SREN |
+		SDRAM_CFG_SDRAM_TYPE_DDR1);
+	SYNC;
+
+	/* size detection */
+	debug("\n");
+	size = 0;
+	for(cs = 0; cs < 4; ++cs) {
+		debug("\nDetecting Bank%d\n", cs);
+
+		bank_size = get_ddr_bank_size(cs,
+			(long *)(CONFIG_SYS_SDRAM_BASE + size));
+		size += bank_size;
+
+		debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);
+
+		/* exit if less than one bank */
+		if(size < DDR_MAX_SIZE_PER_CS) break;
+	}
+
+	gd->ram_size = size;
+
+	return 0;
+}
+
+/**************************************************************************
+ * checkboard()
+ */
+int checkboard (void)
+{
+	puts("Board: TQM834x\n");
+
+#ifdef CONFIG_PCI
+	volatile immap_t * immr;
+	u32 w, f;
+
+	immr = (immap_t *)CONFIG_SYS_IMMR;
+	if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {
+		printf("PCI:   NOT in host mode..?!\n");
+		return 0;
+	}
+
+	/* get bus width */
+	w = 32;
+	if (immr->reset.rcwh & HRCWH_64_BIT_PCI)
+		w = 64;
+
+	/* get clock */
+	f = gd->pci_clk;
+
+	printf("PCI1:  %d bit, %d MHz\n", w, f / 1000000);
+#else
+	printf("PCI:   disabled\n");
+#endif
+	return 0;
+}
+
+
+/**************************************************************************
+ *
+ * Local functions
+ *
+ *************************************************************************/
+
+/**************************************************************************
+ * Detect the number of flash banks (1 or 2). Store it in
+ * a global variable tqm834x_num_flash_banks.
+ * Bank detection code based on the Monitor code.
+ */
+static int detect_num_flash_banks(void)
+{
+	typedef unsigned long FLASH_PORT_WIDTH;
+	typedef volatile unsigned long FLASH_PORT_WIDTHV;
+	FPWV *bank1_base;
+	FPWV *bank2_base;
+	FPW bank1_read;
+	FPW bank2_read;
+	ulong bank1_size;
+	ulong bank2_size;
+	ulong total_size;
+
+	cfi_flash_num_flash_banks = 2;	/* assume two banks */
+
+	/* Get bank 1 and 2 information */
+	bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0);
+	debug("Bank1 size: %lu\n", bank1_size);
+	bank2_size = flash_get_size(CONFIG_SYS_FLASH_BASE + bank1_size, 1);
+	debug("Bank2 size: %lu\n", bank2_size);
+	total_size = bank1_size + bank2_size;
+
+	if (bank2_size > 0) {
+		/* Seems like we've got bank 2, but maybe it's mirrored 1 */
+
+		/* Set the base addresses */
+		bank1_base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
+		bank2_base = (FPWV *) (CONFIG_SYS_FLASH_BASE + bank1_size);
+
+		/* Put bank 2 into CFI command mode and read */
+		bank2_base[0x55] = 0x00980098;
+		IOSYNC;
+		ISYNC;
+		bank2_read = bank2_base[0x10];
+
+		/* Read from bank 1 (it's in read mode) */
+		bank1_read = bank1_base[0x10];
+
+		/* Reset Flash */
+		bank1_base[0] = 0x00F000F0;
+		bank2_base[0] = 0x00F000F0;
+
+		if (bank2_read == bank1_read) {
+			/*
+			 * Looks like just one bank, but not sure yet. Let's
+			 * read from bank 2 in autosoelect mode.
+			 */
+			bank2_base[0x0555] = 0x00AA00AA;
+			bank2_base[0x02AA] = 0x00550055;
+			bank2_base[0x0555] = 0x00900090;
+			IOSYNC;
+			ISYNC;
+			bank2_read = bank2_base[0x10];
+
+			/* Read from bank 1 (it's in read mode) */
+			bank1_read = bank1_base[0x10];
+
+			/* Reset Flash */
+			bank1_base[0] = 0x00F000F0;
+			bank2_base[0] = 0x00F000F0;
+
+			if (bank2_read == bank1_read) {
+				/*
+				 * In both CFI command and autoselect modes,
+				 * we got the some data reading from Flash.
+				 * There is only one mirrored bank.
+				 */
+				cfi_flash_num_flash_banks = 1;
+				total_size = bank1_size;
+			}
+		}
+	}
+
+	debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);
+
+	/* set OR0 and BR0 */
+	set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 |
+		   OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM));
+	set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
+		   (BR_MS_GPCM | BR_PS_32 | BR_V));
+
+	return (0);
+}
+
+/*************************************************************************
+ * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
+ */
+static long int get_ddr_bank_size(short cs, long *base)
+{
+	/* This array lists all valid DDR SDRAM configurations, with
+	 * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
+	 * The last entry has to to have size equal 0 and is igonred during
+	 * autodection. Bank sizes must be in increasing order of size
+	 */
+	struct {
+		long row;
+		long col;
+		long size;
+	} conf[] = {
+		{CSCONFIG_ROW_BIT_12,	CSCONFIG_COL_BIT_8,	32 << 20},
+		{CSCONFIG_ROW_BIT_12,	CSCONFIG_COL_BIT_9,	64 << 20},
+		{CSCONFIG_ROW_BIT_12,	CSCONFIG_COL_BIT_10,	128 << 20},
+		{CSCONFIG_ROW_BIT_13,	CSCONFIG_COL_BIT_9,	128 << 20},
+		{CSCONFIG_ROW_BIT_13,	CSCONFIG_COL_BIT_10,	256 << 20},
+		{CSCONFIG_ROW_BIT_13,	CSCONFIG_COL_BIT_11,	512 << 20},
+		{CSCONFIG_ROW_BIT_14,	CSCONFIG_COL_BIT_10,	512 << 20},
+		{CSCONFIG_ROW_BIT_14,	CSCONFIG_COL_BIT_11,	1024 << 20},
+		{0,			0,			0}
+	};
+
+	int i;
+	int detected;
+	long size;
+
+	detected = -1;
+	for(i = 0; conf[i].size != 0; ++i) {
+
+		/* set sdram bank configuration */
+		set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
+
+		debug("Getting RAM size...\n");
+		size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
+
+		if((size == conf[i].size) && (i == detected + 1))
+			detected = i;
+
+		debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
+			conf[i].row,
+			conf[i].col,
+			conf[i].size >> 20,
+			base,
+			size >> 20);
+	}
+
+	if(detected == -1){
+		/* disable empty cs */
+		debug("\nNo valid configurations for CS%d, disabling...\n", cs);
+		set_cs_config(cs, 0);
+		return 0;
+	}
+
+	debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
+			conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
+
+	/* configure cs ro detected params */
+	set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
+			conf[detected].col);
+
+	set_cs_bounds(cs, (long)base, conf[detected].size);
+
+	return(conf[detected].size);
+}
+
+/**************************************************************************
+ * Sets DDR bank CS bounds.
+ */
+static void set_cs_bounds(short cs, ulong base, ulong size)
+{
+	debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs);
+	if(size == 0){
+		im->ddr.csbnds[cs].csbnds = 0x00000000;
+	} else {
+		im->ddr.csbnds[cs].csbnds =
+			((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+			(((base + size - 1) >> CSBNDS_EA_SHIFT) &
+				CSBNDS_EA);
+	}
+	SYNC;
+}
+
+/**************************************************************************
+ * Sets DDR banks CS configuration.
+ * config == 0x00000000 disables the CS.
+ */
+static void set_cs_config(short cs, long config)
+{
+	debug("Setting config %08lx for cs %d\n", config, cs);
+	im->ddr.cs_config[cs] = config;
+	SYNC;
+}
+
+/**************************************************************************
+ * Sets DDR clocks, timings and configuration.
+ */
+static void set_ddr_config(void) {
+	/* clock control */
+	im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
+		DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
+	SYNC;
+
+	/* timing configuration */
+	im->ddr.timing_cfg_1 =
+		(4 << TIMING_CFG1_PRETOACT_SHIFT) |
+		(7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
+		(4 << TIMING_CFG1_ACTTORW_SHIFT)  |
+		(5 << TIMING_CFG1_REFREC_SHIFT)   |
+		(3 << TIMING_CFG1_WRREC_SHIFT)    |
+		(3 << TIMING_CFG1_ACTTOACT_SHIFT) |
+		(1 << TIMING_CFG1_WRTORD_SHIFT)   |
+		(TIMING_CFG1_CASLAT & TIMING_CASLAT);
+
+	im->ddr.timing_cfg_2 =
+		TIMING_CFG2_CPO_DEF |
+		(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
+	SYNC;
+
+	/* don't enable DDR controller yet */
+	im->ddr.sdram_cfg =
+		SDRAM_CFG_SREN |
+		SDRAM_CFG_SDRAM_TYPE_DDR1;
+	SYNC;
+
+	/* Set SDRAM mode */
+	im->ddr.sdram_mode =
+		((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
+			SDRAM_MODE_ESD_SHIFT) |
+		((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
+			SDRAM_MODE_SD_SHIFT) |
+		((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
+			MODE_CASLAT);
+	SYNC;
+
+	/* Set fast SDRAM refresh rate */
+	im->ddr.sdram_interval =
+		(DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
+		(DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
+	SYNC;
+
+	/* Workaround for DDR6 Erratum
+	 * see MPC8349E Device Errata Rev.8, 2/2006
+	 * This workaround influences the MPC internal "input enables"
+	 * dependent on CAS latency and MPC revision. According to errata
+	 * sheet the internal reserved registers for this workaround are
+	 * not available from revision 2.0 and up.
+	 */
+
+	/* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
+	 * (0x200)
+	 */
+	if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
+
+		/* There is a internal reserved register at IMMRBAR+0x2F00
+		 * which has to be written with a certain value defined by
+		 * errata sheet.
+		 */
+		u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00);
+
+#if defined(DDR_CASLAT_20)
+		*reserved_p = 0x201c0000;
+#else
+		*reserved_p = 0x202c0000;
+#endif
+	}
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif	/* CONFIG_PCI */
+
+	return 0;
+}
+#endif	/* CONFIG_OF_BOARD_SETUP */
diff --git a/roms/u-boot/board/tqc/tqma6/Kconfig b/roms/u-boot/board/tqc/tqma6/Kconfig
new file mode 100644
index 000000000..0cf6d8303
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqma6/Kconfig
@@ -0,0 +1,97 @@
+if TARGET_TQMA6
+
+config SYS_BOARD
+	default "tqma6"
+
+config SYS_VENDOR
+	default "tqc"
+
+config SYS_CONFIG_NAME
+	default "tqma6"
+
+choice
+	prompt "TQMa6 SoC variant"
+	default TQMA6Q
+	help
+	  select the TQMa6 module variant. The variants differing in the used
+	  i.MX6 CPU type and DRAM
+
+config TQMA6Q
+	bool "TQMa6Q / TQMa6D"
+	depends on MX6Q
+	help
+	  select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM
+
+config TQMA6DL
+	bool "TQMa6DL"
+	depends on MX6DL
+	help
+	  select TQMa6DL with i.MX6DL and 1GiB DRAM
+
+config TQMA6S
+	bool "TQMa6S"
+	depends on MX6S
+	help
+	  select TQMa6S with i.MX6S and 512 MiB DRAM
+
+endchoice
+
+choice
+	prompt "TQMa6 boot configuration"
+	default TQMA6X_MMC_BOOT
+	help
+	  Configure boot device. This is also used to implement environment
+	  location.
+
+config TQMA6X_MMC_BOOT
+	bool "MMC / SD Boot"
+	help
+	  Boot from eMMC / SD Card
+
+config TQMA6X_SPI_BOOT
+	bool "SPI NOR Boot"
+	help
+	  Boot from on board SPI NOR flash
+
+endchoice
+
+choice
+	prompt "TQMa6 base board variant"
+	default MBA6
+	help
+	  Select base board for TQMa6
+
+config MBA6
+	bool "TQMa6 on MBa6 Starterkit"
+	select DM_ETH
+	select USB
+	select DM_USB
+	select CMD_USB
+	select USB_STORAGE
+	select USB_HOST_ETHER
+	select USB_ETHER_SMSC95XX
+	select PHYLIB
+	select PHY_MICREL
+	select PHY_MICREL_KSZ90X1
+	select MXC_UART
+	help
+	  Select the MBa6 starterkit. This features a GigE Phy, USB, SD-Card
+	  etc.
+
+config WRU4
+	bool "OHB WRU-IV"
+	help
+	  Select the OHB Systems AG WRU-IV baseboard.
+
+endchoice
+
+config SYS_TEXT_BASE
+	default 0x2fc00000 if TQMA6S
+	default 0x4fc00000 if TQMA6Q || TQMA6DL
+
+config IMX_CONFIG
+	default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q
+	default "board/tqc/tqma6/tqma6dl.cfg" if TQMA6DL
+	default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S
+
+endif
diff --git a/roms/u-boot/board/tqc/tqma6/MAINTAINERS b/roms/u-boot/board/tqc/tqma6/MAINTAINERS
new file mode 100644
index 000000000..91cd24449
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqma6/MAINTAINERS
@@ -0,0 +1,6 @@
+TQ SYSTEMS TQMA6 BOARD
+M:	Markus Niebel <Markus.Niebel@tq-group.com>
+S:	Maintained
+F:	board/tqc/tqma6/
+F:	include/configs/tqma6.h
+F:	configs/tqma6*_defconfig
diff --git a/roms/u-boot/board/tqc/tqma6/Makefile b/roms/u-boot/board/tqc/tqma6/Makefile
new file mode 100644
index 000000000..7271297c7
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqma6/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014, Markus Niebel <Markus.Niebel@tq-group.com>
+
+obj-y  := tqma6.o
+
+obj-$(CONFIG_MBA6) += tqma6_mba6.o
+obj-$(CONFIG_WRU4) += tqma6_wru4.o
diff --git a/roms/u-boot/board/tqc/tqma6/README b/roms/u-boot/board/tqc/tqma6/README
new file mode 100644
index 000000000..c47cb21ee
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqma6/README
@@ -0,0 +1,38 @@
+U-Boot for the TQ Systems TQMa6 modules
+
+This file contains information for the port of
+U-Boot to the TQ Systems TQMa6 modules.
+
+1. Boot source
+--------------
+
+The following boot source is supported:
+
+- SD/eMMC
+- SPI NOR
+
+2. Building
+------------
+
+To build U-Boot for the TQ Systems TQMa6 modules:
+
+	make tqma6<x>_<baseboard>_<boot>_config
+	make
+
+x is a placeholder for the CPU variant
+q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D  (i.MX6D)
+dl - means i.MX6DL: TQMa6DL  (i.MX6DL)
+s - means i.MX6S: TQMa6S  (i.MX6S)
+
+baseboard is a placeholder for the boot device
+mmc - means eMMC
+spi - mean SPI NOR
+
+This gives the following configurations:
+
+tqma6q_mba6_mmc_config
+tqma6q_mba6_spi_config
+tqma6dl_mba6_mmc_config
+tqma6dl_mba6_spi_config
+tqma6s_mba6_mmc_config
+tqma6s_mba6_spi_config
diff --git a/roms/u-boot/board/tqc/tqma6/clocks.cfg b/roms/u-boot/board/tqc/tqma6/clocks.cfg
new file mode 100644
index 000000000..1f2001c75
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqma6/clocks.cfg
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
diff --git a/roms/u-boot/board/tqc/tqma6/tqma6.c b/roms/u-boot/board/tqc/tqma6/tqma6.c
new file mode 100644
index 000000000..26d557cec
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqma6/tqma6.c
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
+ * Author: Markus Niebel <markus.niebel@tq-group.com>
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <asm/global_data.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/libfdt.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <power/pfuze100_pmic.h>
+#include <power/pmic.h>
+#include <spi_flash.h>
+
+#include "tqma6_bb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define GPIO_OUT_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define GPIO_IN_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_80ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static const uint16_t tqma6_emmc_dsr = 0x0100;
+
+#ifndef CONFIG_DM_MMC
+/* eMMC on USDHCI3 always present */
+static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
+	NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK,		USDHC_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD,		USDHC_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0,	USDHC_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1,	USDHC_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2,	USDHC_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3,	USDHC_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4,	USDHC_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5,	USDHC_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6,	USDHC_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7,	USDHC_PAD_CTRL),
+	/* eMMC reset */
+	NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET,	GPIO_OUT_PAD_CTRL),
+};
+
+/*
+ * According to board_mmc_init() the following map is done:
+ * (U-Boot device node)    (Physical Port)
+ * mmc0                    eMMC (SD3) on TQMa6
+ * mmc1 .. n               optional slots used on baseboard
+ */
+struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
+	.esdhc_base = USDHC3_BASE_ADDR,
+	.max_bus_width = 8,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+		/* eMMC/uSDHC3 is always present */
+		ret = 1;
+	else
+		ret = tqma6_bb_board_mmc_getcd(mmc);
+
+	return ret;
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+		/* eMMC/uSDHC3 is always present */
+		ret = 0;
+	else
+		ret = tqma6_bb_board_mmc_getwp(mmc);
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
+					 ARRAY_SIZE(tqma6_usdhc3_pads));
+	tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
+		puts("Warning: failed to initialize eMMC dev\n");
+	} else {
+		struct mmc *mmc = find_mmc_device(0);
+		if (mmc)
+			mmc_set_dsr(mmc, tqma6_emmc_dsr);
+	}
+
+	tqma6_bb_board_mmc_init(bis);
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_DM_SPI
+static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
+	/* SS1 */
+	NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
+};
+
+#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
+
+static unsigned const tqma6_ecspi1_cs[] = {
+	TQMA6_SF_CS_GPIO,
+};
+
+__weak void tqma6_iomuxc_spi(void)
+{
+	unsigned i;
+
+	for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
+		gpio_direction_output(tqma6_ecspi1_cs[i], 1);
+	imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
+					 ARRAY_SIZE(tqma6_ecspi1_pads));
+}
+
+#if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return ((bus == CONFIG_SF_DEFAULT_BUS) &&
+		(cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
+}
+#endif
+#endif
+
+#ifdef CONFIG_SYS_I2C
+static struct i2c_pads_info tqma6_i2c3_pads = {
+	/* I2C3: on board LM75, M24C64,  */
+	.scl = {
+		.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
+					 I2C_PAD_CTRL),
+		.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
+					  I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(1, 5)
+	},
+	.sda = {
+		.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
+					 I2C_PAD_CTRL),
+		.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
+					  I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(1, 6)
+	}
+};
+
+static void tqma6_setup_i2c(void)
+{
+	int ret;
+	/*
+	 * use logical index for bus, e.g. I2C1 -> 0
+	 * warn on error
+	 */
+	ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
+	if (ret)
+		printf("setup I2C3 failed: %d\n", ret);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	return tqma6_bb_board_early_init_f();
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifndef CONFIG_DM_SPI
+	tqma6_iomuxc_spi();
+#endif
+#ifdef CONFIG_SYS_I2C
+	tqma6_setup_i2c();
+#endif
+
+	tqma6_bb_board_init();
+
+	return 0;
+}
+
+static const char *tqma6_get_boardname(void)
+{
+	u32 cpurev = get_cpu_rev();
+
+	switch ((cpurev & 0xFF000) >> 12) {
+	case MXC_CPU_MX6SOLO:
+		return "TQMa6S";
+		break;
+	case MXC_CPU_MX6DL:
+		return "TQMa6DL";
+		break;
+	case MXC_CPU_MX6D:
+		return "TQMa6D";
+		break;
+	case MXC_CPU_MX6Q:
+		return "TQMa6Q";
+		break;
+	default:
+		return "??";
+	};
+}
+
+#ifdef CONFIG_POWER
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	struct pmic *p;
+	u32 reg, rev;
+
+	power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
+	p = pmic_get("PFUZE100");
+	if (p && !pmic_probe(p)) {
+		pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+		pmic_reg_read(p, PFUZE100_REVID, &rev);
+		printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
+	}
+
+	return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+	env_set("board_name", tqma6_get_boardname());
+
+	tqma6_bb_board_late_init();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: %s on a %s\n", tqma6_get_boardname(),
+	       tqma6_bb_get_boardname());
+	return 0;
+}
+
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#define MODELSTRLEN 32u
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	char modelstr[MODELSTRLEN];
+
+	snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
+		 tqma6_bb_get_boardname());
+	do_fixup_by_path_string(blob, "/", "model", modelstr);
+	fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
+	/* bring in eMMC dsr settings */
+	do_fixup_by_path_u32(blob,
+			     "/soc/aips-bus@02100000/usdhc@02198000",
+			     "dsr", tqma6_emmc_dsr, 2);
+	tqma6_bb_ft_board_setup(blob, bd);
+
+	return 0;
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/roms/u-boot/board/tqc/tqma6/tqma6_bb.h b/roms/u-boot/board/tqc/tqma6/tqma6_bb.h
new file mode 100644
index 000000000..b0f1f99a8
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqma6/tqma6_bb.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013, 2014 TQ Systems
+ * Author: Markus Niebel <markus.niebel@tq-group.com>
+ */
+
+#ifndef __TQMA6_BB__
+#define __TQMA6_BB__
+
+#include <common.h>
+
+int tqma6_bb_board_mmc_getwp(struct mmc *mmc);
+int tqma6_bb_board_mmc_getcd(struct mmc *mmc);
+int tqma6_bb_board_mmc_init(struct bd_info *bis);
+
+int tqma6_bb_board_early_init_f(void);
+int tqma6_bb_board_init(void);
+int tqma6_bb_board_late_init(void);
+int tqma6_bb_checkboard(void);
+
+const char *tqma6_bb_get_boardname(void);
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd);
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+
+#endif
diff --git a/roms/u-boot/board/tqc/tqma6/tqma6_mba6.c b/roms/u-boot/board/tqc/tqma6/tqma6_mba6.c
new file mode 100644
index 000000000..801619e80
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqma6/tqma6_mba6.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
+ * Author: Markus Niebel <markus.niebel@tq-group.com>
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/libfdt.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+
+#include "tqma6_bb.h"
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define GPIO_OUT_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define GPIO_IN_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_80ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#if defined(CONFIG_TQMA6Q)
+
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII	0x02e0790
+#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM	0x02e07ac
+
+#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
+
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII	0x02e0768
+#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM	0x02e0788
+
+#else
+
+#error "need to select module"
+
+#endif
+
+/* disable on die termination for RGMII */
+#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE	0x00000000
+/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V	0x00080000
+/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V	0x000C0000
+
+static void mba6_setup_iomuxc_enet(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* clear gpr1[ENET_CLK_SEL] for externel clock */
+	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	__raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
+		     (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
+	__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
+		     (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
+}
+
+static iomux_v3_cfg_t const mba6_uart2_pads[] = {
+	NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
+};
+
+static void mba6_setup_iomuxc_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
+					 ARRAY_SIZE(mba6_uart2_pads));
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	/*
+	 * This assumes that the baseboard registered
+	 * the boot device first ...
+	 * Note: SDHC3 == idx2
+	 */
+	return (2 == devno) ? 0 : 1;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+/*
+ * optimized pad skew values depends on CPU variant on the TQMa6x module:
+ * CONFIG_TQMA6Q: i.MX6Q/D
+ * CONFIG_TQMA6S: i.MX6S
+ * CONFIG_TQMA6DL: i.MX6DL
+ */
+#if defined(CONFIG_TQMA6Q)
+#define MBA6X_KSZ9031_CTRL_SKEW	0x0032
+#define MBA6X_KSZ9031_CLK_SKEW	0x03ff
+#define MBA6X_KSZ9031_RX_SKEW	0x3333
+#define MBA6X_KSZ9031_TX_SKEW	0x2036
+#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
+#define MBA6X_KSZ9031_CTRL_SKEW	0x0030
+#define MBA6X_KSZ9031_CLK_SKEW	0x03ff
+#define MBA6X_KSZ9031_RX_SKEW	0x3333
+#define MBA6X_KSZ9031_TX_SKEW	0x2052
+#else
+#error
+#endif
+	/* min rx/tx ctrl delay */
+	ksz9031_phy_extended_write(phydev, 2,
+				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				   MBA6X_KSZ9031_CTRL_SKEW);
+	/* min rx delay */
+	ksz9031_phy_extended_write(phydev, 2,
+				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				   MBA6X_KSZ9031_RX_SKEW);
+	/* max tx delay */
+	ksz9031_phy_extended_write(phydev, 2,
+				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				   MBA6X_KSZ9031_TX_SKEW);
+	/* rx/tx clk skew */
+	ksz9031_phy_extended_write(phydev, 2,
+				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				   MBA6X_KSZ9031_CLK_SKEW);
+
+	phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int tqma6_bb_board_early_init_f(void)
+{
+	mba6_setup_iomuxc_uart();
+
+	return 0;
+}
+
+int tqma6_bb_board_init(void)
+{
+	mba6_setup_iomuxc_enet();
+
+	return 0;
+}
+
+int tqma6_bb_board_late_init(void)
+{
+	return 0;
+}
+
+const char *tqma6_bb_get_boardname(void)
+{
+	return "MBa6x";
+}
+
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* TBD */
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/roms/u-boot/board/tqc/tqma6/tqma6_wru4.c b/roms/u-boot/board/tqc/tqma6/tqma6_wru4.c
new file mode 100644
index 000000000..3b1bc603c
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqma6/tqma6_wru4.c
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
+ * Author: Markus Niebel <markus.niebel@tq-group.com>
+ *
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/libfdt.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+
+#include "tqma6_bb.h"
+
+/* UART */
+#define UART4_PAD_CTRL (			\
+		PAD_CTL_HYS |			\
+		PAD_CTL_PUS_100K_UP |		\
+		PAD_CTL_PUE |			\
+		PAD_CTL_PKE |			\
+		PAD_CTL_SPEED_MED |		\
+		PAD_CTL_DSE_40ohm |		\
+		PAD_CTL_SRE_SLOW		\
+		)
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL),
+};
+
+static void setup_iomuxc_uart4(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+/* MMC */
+#define USDHC2_PAD_CTRL (			\
+		PAD_CTL_HYS |			\
+		PAD_CTL_PUS_47K_UP |		\
+		PAD_CTL_SPEED_LOW |		\
+		PAD_CTL_DSE_80ohm |		\
+		PAD_CTL_SRE_FAST		\
+		)
+
+#define USDHC2_CLK_PAD_CTRL (			\
+		PAD_CTL_HYS |			\
+		PAD_CTL_PUS_47K_UP |		\
+		PAD_CTL_SPEED_LOW |		\
+		PAD_CTL_DSE_40ohm |		\
+		PAD_CTL_SRE_FAST		\
+		)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL),
+
+	NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */
+	NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
+
+static struct fsl_esdhc_cfg usdhc2_cfg = {
+	.esdhc_base = USDHC2_BASE_ADDR,
+	.max_bus_width = 4,
+};
+
+int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+
+	return ret;
+}
+
+int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+		ret = gpio_get_value(USDHC2_WP_GPIO);
+
+	return ret;
+}
+
+int tqma6_bb_board_mmc_init(struct bd_info *bis)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+	ret = gpio_request(USDHC2_CD_GPIO, "mmc-cd");
+	if (!ret)
+		gpio_direction_input(USDHC2_CD_GPIO);
+	ret = gpio_request(USDHC2_WP_GPIO, "mmc-wp");
+	if (!ret)
+		gpio_direction_input(USDHC2_WP_GPIO);
+
+	usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	if(fsl_esdhc_initialize(bis, &usdhc2_cfg))
+		puts("WARNING: failed to initialize SD\n");
+
+	return 0;
+}
+
+/* Ethernet */
+#define ENET_PAD_CTRL (				\
+		PAD_CTL_HYS |			\
+		PAD_CTL_PUS_100K_UP |		\
+		PAD_CTL_PUE |			\
+		PAD_CTL_PKE |			\
+		PAD_CTL_SPEED_MED |		\
+		PAD_CTL_DSE_40ohm |		\
+		PAD_CTL_SRE_SLOW		\
+		)
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL),
+
+	/* ENET1 reset */
+	NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL),
+	/* ENET1 interrupt */
+	NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL),
+};
+
+#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8)
+
+static void setup_iomuxc_enet(void)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+	/* Reset LAN8720 PHY */
+	ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
+	if (!ret)
+		gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
+	udelay(25000);
+	gpio_set_value(ENET_PHY_RESET_GPIO, 1);
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	return cpu_eth_init(bis);
+}
+
+/* GPIO */
+#define GPIO_PAD_CTRL (				\
+		PAD_CTL_HYS |			\
+		PAD_CTL_PUS_100K_UP |		\
+		PAD_CTL_PUE |			\
+		PAD_CTL_SPEED_MED |		\
+		PAD_CTL_DSE_40ohm |		\
+		PAD_CTL_SRE_SLOW		\
+		)
+
+#define GPIO_OD_PAD_CTRL (			\
+		PAD_CTL_HYS |			\
+		PAD_CTL_PUS_100K_UP |		\
+		PAD_CTL_PUE |			\
+		PAD_CTL_ODE |			\
+		PAD_CTL_SPEED_MED |		\
+		PAD_CTL_DSE_40ohm |		\
+		PAD_CTL_SRE_SLOW		\
+		)
+
+static iomux_v3_cfg_t const gpio_pads[] = {
+	/* USB_H_PWR */
+	NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL),
+	/* USB_OTG_PWR */
+	NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL),
+	/* PCIE_RST */
+	NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL),
+	/* UART1_PWRON */
+	NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL),
+	/* UART2_PWRON */
+	NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL),
+	/* UART3_PWRON */
+	NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL),
+};
+
+#define GPIO_USB_H_PWR		IMX_GPIO_NR(1, 0)
+#define GPIO_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
+#define GPIO_PCIE_RST		IMX_GPIO_NR(6, 7)
+#define GPIO_UART1_PWRON	IMX_GPIO_NR(5, 8)
+#define GPIO_UART2_PWRON	IMX_GPIO_NR(5, 10)
+#define GPIO_UART3_PWRON	IMX_GPIO_NR(5, 12)
+
+static void gpio_init(void)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+
+	ret = gpio_request(GPIO_USB_H_PWR, "usb-h-pwr");
+	if (!ret)
+		gpio_direction_output(GPIO_USB_H_PWR, 1);
+	ret = gpio_request(GPIO_USB_OTG_PWR, "usb-otg-pwr");
+	if (!ret)
+		gpio_direction_output(GPIO_USB_OTG_PWR, 1);
+	ret = gpio_request(GPIO_PCIE_RST, "pcie-reset");
+	if (!ret)
+		gpio_direction_output(GPIO_PCIE_RST, 1);
+	ret = gpio_request(GPIO_UART1_PWRON, "uart1-pwr");
+	if (!ret)
+		gpio_direction_output(GPIO_UART1_PWRON, 0);
+	ret = gpio_request(GPIO_UART2_PWRON, "uart2-pwr");
+	if (!ret)
+		gpio_direction_output(GPIO_UART2_PWRON, 0);
+	ret = gpio_request(GPIO_UART3_PWRON, "uart3-pwr");
+	if (!ret)
+		gpio_direction_output(GPIO_UART3_PWRON, 0);
+}
+
+void tqma6_iomuxc_spi(void)
+{
+	/* No SPI on this baseboard */
+}
+
+int tqma6_bb_board_early_init_f(void)
+{
+	setup_iomuxc_uart4();
+
+	return 0;
+}
+
+int tqma6_bb_board_init(void)
+{
+	setup_iomuxc_enet();
+
+	gpio_init();
+
+	/* Turn the UART-couplers on one-after-another */
+	gpio_set_value(GPIO_UART1_PWRON, 1);
+	mdelay(10);
+	gpio_set_value(GPIO_UART2_PWRON, 1);
+	mdelay(10);
+	gpio_set_value(GPIO_UART3_PWRON, 1);
+
+	return 0;
+}
+
+int tqma6_bb_board_late_init(void)
+{
+	return 0;
+}
+
+const char *tqma6_bb_get_boardname(void)
+{
+	return "WRU-IV";
+}
+
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{ NULL, 0 },
+};
+
+int misc_init_r(void)
+{
+	add_board_boot_modes(board_boot_modes);
+
+	return 0;
+}
+
+#define WRU4_USB_H1_PWR		IMX_GPIO_NR(1, 0)
+#define WRU4_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
+
+int board_ehci_hcd_init(int port)
+{
+	int ret;
+
+	ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr");
+	if (!ret)
+		gpio_direction_output(WRU4_USB_H1_PWR, 1);
+
+	ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr");
+	if (!ret)
+		gpio_direction_output(WRU4_USB_OTG_PWR, 1);
+
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	if (port)
+		gpio_set_value(WRU4_USB_OTG_PWR, on);
+	else
+		gpio_set_value(WRU4_USB_H1_PWR, on);
+
+	return 0;
+}
+
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd)
+{
+	/* TBD */
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/roms/u-boot/board/tqc/tqma6/tqma6dl.cfg b/roms/u-boot/board/tqc/tqma6/tqma6dl.cfg
new file mode 100644
index 000000000..80c715031
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqma6/tqma6dl.cfg
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 - 2015 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+#if defined(CONFIG_TQMA6X_MMC_BOOT)
+BOOT_FROM      sd
+#elif defined(CONFIG_TQMA6X_SPI_BOOT)
+BOOT_FROM      spi
+#endif
+
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* TQMa6DL DDR config Rev. 0100E */
+/* IOMUX configuration */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
+
+/* memory interface calibration values */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00440048
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x003D003F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0029002D
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x002B0043
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x424C0250
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02300234
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4234023C
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0224022C
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x48484C4C
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4C4E4E4C
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36382C36
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x34343630
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/* configure memory interface */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00408032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+#include "clocks.cfg"
diff --git a/roms/u-boot/board/tqc/tqma6/tqma6q.cfg b/roms/u-boot/board/tqc/tqma6/tqma6q.cfg
new file mode 100644
index 000000000..82a0a271d
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqma6/tqma6q.cfg
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+#if defined(CONFIG_TQMA6X_MMC_BOOT)
+BOOT_FROM      sd
+#elif defined(CONFIG_TQMA6X_SPI_BOOT)
+BOOT_FROM      spi
+#endif
+
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* TQMa6Q/D DDR config Rev. 0100B */
+/* IOMUX configuration */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
+
+/* memory interface calibration values */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/* configure memory interface */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09308030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025536
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+#include "clocks.cfg"
diff --git a/roms/u-boot/board/tqc/tqma6/tqma6s.cfg b/roms/u-boot/board/tqc/tqma6/tqma6s.cfg
new file mode 100644
index 000000000..9cdbb3c76
--- /dev/null
+++ b/roms/u-boot/board/tqc/tqma6/tqma6s.cfg
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+#if defined(CONFIG_TQMA6X_MMC_BOOT)
+BOOT_FROM      sd
+#elif defined(CONFIG_TQMA6X_SPI_BOOT)
+BOOT_FROM      spi
+#endif
+
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* TQMa6S DDR config Rev. 0100B */
+/* IOMUX configuration */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
+
+/* memory interface calibration values */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00120014
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00000000
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00000000
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x0240023C
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0228022C
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x00000000
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x00000000
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x00000000
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36362A32
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x00000000
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x00000000
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000000
+
+/* configure memory interface */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+#include "clocks.cfg"
diff --git a/roms/u-boot/board/udoo/Kconfig b/roms/u-boot/board/udoo/Kconfig
new file mode 100644
index 000000000..78617a213
--- /dev/null
+++ b/roms/u-boot/board/udoo/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_UDOO
+
+config SYS_BOARD
+	default "udoo"
+
+config SYS_CONFIG_NAME
+	default "udoo"
+
+endif
diff --git a/roms/u-boot/board/udoo/MAINTAINERS b/roms/u-boot/board/udoo/MAINTAINERS
new file mode 100644
index 000000000..195882b4c
--- /dev/null
+++ b/roms/u-boot/board/udoo/MAINTAINERS
@@ -0,0 +1,6 @@
+UDOO BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/udoo/
+F:	include/configs/udoo.h
+F:	configs/udoo_defconfig
diff --git a/roms/u-boot/board/udoo/Makefile b/roms/u-boot/board/udoo/Makefile
new file mode 100644
index 000000000..66f67f7c1
--- /dev/null
+++ b/roms/u-boot/board/udoo/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+
+obj-y  := udoo.o udoo_spl.o
diff --git a/roms/u-boot/board/udoo/README b/roms/u-boot/board/udoo/README
new file mode 100644
index 000000000..6fbcc598f
--- /dev/null
+++ b/roms/u-boot/board/udoo/README
@@ -0,0 +1,21 @@
+How to use U-Boot on MX6Q/DL Udoo boards
+----------------------------------------
+
+- Build U-Boot for MX6Q/DL Udoo boards:
+
+$ make mrproper
+$ make udoo_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Insert the SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/roms/u-boot/board/udoo/neo/Kconfig b/roms/u-boot/board/udoo/neo/Kconfig
new file mode 100644
index 000000000..8f474df24
--- /dev/null
+++ b/roms/u-boot/board/udoo/neo/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_UDOO_NEO
+
+config SYS_VENDOR
+	default "udoo"
+
+config SYS_BOARD
+	default "neo"
+
+config SYS_CONFIG_NAME
+	default "udoo_neo"
+
+endif
diff --git a/roms/u-boot/board/udoo/neo/MAINTAINERS b/roms/u-boot/board/udoo/neo/MAINTAINERS
new file mode 100644
index 000000000..743fe33d0
--- /dev/null
+++ b/roms/u-boot/board/udoo/neo/MAINTAINERS
@@ -0,0 +1,7 @@
+UDOO NEO BOARD
+M:	Breno Lima <breno.lima@nxp.com>
+M:	Francesco Montefoschi <francesco.montefoschi@udoo.org>
+S:	Maintained
+F:	board/udoo/neo/
+F:	include/configs/udoo_neo.h
+F:	configs/udoo_neo_defconfig
diff --git a/roms/u-boot/board/udoo/neo/Makefile b/roms/u-boot/board/udoo/neo/Makefile
new file mode 100644
index 000000000..831c084ce
--- /dev/null
+++ b/roms/u-boot/board/udoo/neo/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2015 UDOO Team
+
+obj-y  := neo.o
diff --git a/roms/u-boot/board/udoo/neo/neo.c b/roms/u-boot/board/udoo/neo/neo.c
new file mode 100644
index 000000000..92a1e084b
--- /dev/null
+++ b/roms/u-boot/board/udoo/neo/neo.c
@@ -0,0 +1,506 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) Jasbir Matharu
+ * Copyright (C) UDOO Team
+ *
+ * Author: Breno Lima <breno.lima@nxp.com>
+ * Author: Francesco Montefoschi <francesco.monte@gmail.com>
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <dm.h>
+#include <env.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	UDOO_NEO_TYPE_BASIC,
+	UDOO_NEO_TYPE_BASIC_KS,
+	UDOO_NEO_TYPE_FULL,
+	UDOO_NEO_TYPE_EXTENDED,
+};
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
+	PAD_CTL_ODE)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_MED   |                                   \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_SPEED_MED   | PAD_CTL_SRE_FAST)
+
+#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm)
+
+#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) |	\
+	MUX_MODE_SION)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+		.gp = IMX_GPIO_NR(1, 0),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+		.gp = IMX_GPIO_NR(1, 1),
+	},
+};
+#endif
+
+#ifdef CONFIG_POWER
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg, rev_id;
+
+	ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE3000");
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
+	pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
+	printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
+	reg |= 0x1;
+	ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
+	if (ret)
+		return ret;
+
+	ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
+	if (ret)
+		return ret;
+
+	ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
+	if (ret)
+		return ret;
+
+	ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
+	if (ret)
+		return ret;
+
+	ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
+	if (ret)
+		return ret;
+
+	/* set SW1A standby voltage 0.975V */
+	pmic_reg_read(p, PFUZE3000_SW1ASTBY, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE3000_SW1AB_SETP(9750);
+	ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
+	if (ret)
+		return ret;
+
+	/* set SW1B standby voltage 0.975V */
+	pmic_reg_read(p, PFUZE3000_SW1BSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE3000_SW1AB_SETP(9750);
+	ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
+	if (ret)
+		return ret;
+
+	/* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE3000_SW1ACONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
+	if (ret)
+		return ret;
+
+	/* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE3000_SW1BCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
+	if (ret)
+		return ret;
+
+	/* set VDD_ARM_IN to 1.350V */
+	pmic_reg_read(p, PFUZE3000_SW1AVOLT, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE3000_SW1AB_SETP(13500);
+	ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
+	if (ret)
+		return ret;
+
+	/* set VDD_SOC_IN to 1.350V */
+	pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE3000_SW1AB_SETP(13500);
+	ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
+	if (ret)
+		return ret;
+
+	/* set DDR_1_5V to 1.350V */
+	pmic_reg_read(p, PFUZE3000_SW3VOLT, &reg);
+	reg &= ~0x0f;
+	reg |= PFUZE3000_SW3_SETP(13500);
+	ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
+	if (ret)
+		return ret;
+
+	/* set VGEN2_1V5 to 1.5V */
+	pmic_reg_read(p, PFUZE3000_VLDO2CTL, &reg);
+	reg &= ~0x0f;
+	reg |= PFUZE3000_VLDO_SETP(15000);
+	/*  enable  */
+	reg |= 0x10;
+	ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+#endif
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const phy_control_pads[] = {
+	/* 25MHz Ethernet PHY Clock */
+	MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
+	MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const board_recognition_pads[] = {
+	/*Connected to R184*/
+	MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
+	/*Connected to R185*/
+	MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
+};
+
+static iomux_v3_cfg_t const wdog_b_pad = {
+	MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const peri_3v3_pads[] = {
+	MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static int setup_fec(void)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	int reg;
+
+	imx_iomux_v3_setup_multiple_pads(phy_control_pads,
+					 ARRAY_SIZE(phy_control_pads));
+
+	/* Reset PHY */
+	gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
+	udelay(10000);
+	gpio_set_value(IMX_GPIO_NR(2, 1), 1);
+	udelay(100);
+
+	reg = readl(&anatop->pll_enet);
+	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
+	writel(reg, &anatop->pll_enet);
+
+	return enable_fec_anatop_clock(0, ENET_25MHZ);
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/*
+	 * Because kernel set WDOG_B mux before pad with the commone pinctrl
+	 * framwork now and wdog reset will be triggered once set WDOG_B mux
+	 * with default pad setting, we set pad setting here to workaround this.
+	 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
+	 * as GPIO mux firstly here to workaround it.
+	 */
+	imx_iomux_v3_setup_pad(wdog_b_pad);
+
+	/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
+	imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
+					 ARRAY_SIZE(peri_3v3_pads));
+
+	/* Active high for ncp692 */
+	gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
+
+#ifdef CONFIG_SYS_I2C_MXC
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+	return 0;
+}
+
+static int get_board_value(void)
+{
+	int r184, r185;
+
+	imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
+					 ARRAY_SIZE(board_recognition_pads));
+
+	gpio_direction_input(IMX_GPIO_NR(4, 13));
+	gpio_direction_input(IMX_GPIO_NR(4, 0));
+
+	r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
+	r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
+
+	/*
+	 * Machine selection -
+	 * Machine          r184,    r185
+	 * ---------------------------------
+	 * Basic              0        0
+	 * Basic Ks           0        1
+	 * Full               1        0
+	 * Extended           1        1
+	 */
+
+	return (r184 << 1) + r185;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_fec();
+
+	return 0;
+}
+
+static char *board_string(void)
+{
+	switch (get_board_value()) {
+	case UDOO_NEO_TYPE_BASIC:
+		return "BASIC";
+	case UDOO_NEO_TYPE_BASIC_KS:
+		return "BASICKS";
+	case UDOO_NEO_TYPE_FULL:
+		return "FULL";
+	case UDOO_NEO_TYPE_EXTENDED:
+		return "EXTENDED";
+	}
+	return "UNDEFINED";
+}
+
+int checkboard(void)
+{
+	printf("Board: UDOO Neo %s\n", board_string());
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", board_string());
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+
+#include <linux/libfdt.h>
+#include <asm/arch/mx6-ddr.h>
+
+static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000028,
+	.dram_dqm1 = 0x00000028,
+	.dram_dqm2 = 0x00000028,
+	.dram_dqm3 = 0x00000028,
+	.dram_ras = 0x00000020,
+	.dram_cas = 0x00000020,
+	.dram_odt0 = 0x00000020,
+	.dram_odt1 = 0x00000020,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00000028,
+	.dram_sdqs1 = 0x00000028,
+	.dram_sdqs2 = 0x00000028,
+	.dram_sdqs3 = 0x00000028,
+	.dram_reset = 0x00000020,
+};
+
+static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000020,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = 0x00000028,
+	.grp_b1ds = 0x00000028,
+	.grp_ctlds = 0x00000020,
+	.grp_ddr_type = 0x000c0000,
+	.grp_b2ds = 0x00000028,
+	.grp_b3ds = 0x00000028,
+};
+
+static const struct mx6_mmdc_calibration neo_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x000E000B,
+	.p0_mpwldectrl1 = 0x000E0010,
+	.p0_mpdgctrl0 = 0x41600158,
+	.p0_mpdgctrl1 = 0x01500140,
+	.p0_mprddlctl = 0x3A383E3E,
+	.p0_mpwrdlctl = 0x3A383C38,
+};
+
+static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x001E0022,
+	.p0_mpwldectrl1 = 0x001C0019,
+	.p0_mpdgctrl0 = 0x41540150,
+	.p0_mpdgctrl1 = 0x01440138,
+	.p0_mprddlctl = 0x403E4644,
+	.p0_mpwrdlctl = 0x3C3A4038,
+};
+
+/* MT41K256M16 */
+static struct mx6_ddr3_cfg neo_mem_ddr = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+/* MT41K128M16 */
+static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+	writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+	int board = get_board_value();
+
+	struct mx6_ddr_sysinfo sysinfo = {
+		.dsize = 1, /* width of data bus: 1 = 32 bits */
+		.cs_density = 24,
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 2,
+		.rtt_nom = 2,		/* RTT_Nom = RZQ/2 */
+		.walat = 1,		/* Write additional latency */
+		.ralat = 5,		/* Read additional latency */
+		.mif3_mode = 3,		/* Command prediction working mode */
+		.bi_on = 1,		/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	};
+
+	mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
+		mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
+			     &neo_basic_mem_ddr);
+	else
+		mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+#endif
diff --git a/roms/u-boot/board/udoo/udoo.c b/roms/u-boot/board/udoo/udoo.c
new file mode 100644
index 000000000..5c49388cb
--- /dev/null
+++ b/roms/u-boot/board/udoo/udoo.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <env.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define WDT_EN		IMX_GPIO_NR(5, 4)
+#define WDT_TRG		IMX_GPIO_NR(3, 19)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+	IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
+};
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	/*
+	 * Bug: Apparently uDoo does not works with Gigabit switches...
+	 * Limiting speed to 10/100Mbps, and setting master mode, seems to
+	 * be the only way to have a successfull PHY auto negotiation.
+	 * How to fix: Understand why Linux kernel do not have this issue.
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
+
+	/* control data pad skew - devaddr = 0x02, register = 0x04 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+	return 0;
+}
+
+static void setup_iomux_enet(void)
+{
+	gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
+
+	gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
+
+	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+	udelay(1000);
+
+	gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
+
+	/* Need 100ms delay to exit from reset. */
+	udelay(1000 * 100);
+
+	gpio_free(IMX_GPIO_NR(6, 24));
+	gpio_free(IMX_GPIO_NR(6, 25));
+	gpio_free(IMX_GPIO_NR(6, 27));
+	gpio_free(IMX_GPIO_NR(6, 28));
+	gpio_free(IMX_GPIO_NR(6, 29));
+}
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart2_pads);
+}
+
+static void setup_iomux_wdog(void)
+{
+	SETUP_IOMUX_PADS(wdog_pads);
+	gpio_direction_output(WDT_TRG, 0);
+	gpio_direction_output(WDT_EN, 1);
+	gpio_direction_input(WDT_TRG);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_wdog();
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (is_cpu_type(MXC_CPU_MX6Q))
+		env_set("board_rev", "MX6Q");
+	else
+		env_set("board_rev", "MX6DL");
+#endif
+	setup_iomux_enet();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	if (is_cpu_type(MXC_CPU_MX6Q))
+		puts("Board: Udoo Quad\n");
+	else
+		puts("Board: Udoo DualLite\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/udoo/udoo_spl.c b/roms/u-boot/board/udoo/udoo_spl.c
new file mode 100644
index 000000000..d9afbbb74
--- /dev/null
+++ b/roms/u-boot/board/udoo/udoo_spl.c
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Udoo
+ * Author: Tungyi Lin <tungyilin1127@gmail.com>
+ *         Richard Hu <hakahu@gmail.com>
+ * Based on board/wandboard/spl.c
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+#if defined(CONFIG_SPL_BUILD)
+#include <asm/arch/mx6-ddr.h>
+
+/*
+ * Driving strength:
+ *   0x30 == 40 Ohm
+ *   0x28 == 48 Ohm
+ */
+#define IMX6DQ_DRIVE_STRENGTH		0x30
+#define IMX6SDL_DRIVE_STRENGTH	0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
+	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
+	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
+	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
+	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* MT41K128M16JT-125 */
+static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+	/* quad = 1066, duallite = 800 */
+	.mem_speed = 1066,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+	.SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x00350035,
+	.p0_mpwldectrl1 = 0x001F001F,
+	.p1_mpwldectrl0 = 0x00010001,
+	.p1_mpwldectrl1 = 0x00010001,
+	.p0_mpdgctrl0 = 0x43510360,
+	.p0_mpdgctrl1 = 0x0342033F,
+	.p1_mpdgctrl0 = 0x033F033F,
+	.p1_mpdgctrl1 = 0x03290266,
+	.p0_mprddlctl = 0x4B3E4141,
+	.p1_mprddlctl = 0x47413B4A,
+	.p0_mpwrdlctl = 0x42404843,
+	.p1_mpwrdlctl = 0x4C3F4C45,
+};
+
+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x002F0038,
+	.p0_mpwldectrl1 = 0x001F001F,
+	.p1_mpwldectrl0 = 0x001F001F,
+	.p1_mpwldectrl1 = 0x001F001F,
+	.p0_mpdgctrl0 = 0x425C0251,
+	.p0_mpdgctrl1 = 0x021B021E,
+	.p1_mpdgctrl0 = 0x021B021E,
+	.p1_mpdgctrl1 = 0x01730200,
+	.p0_mprddlctl = 0x45474C45,
+	.p1_mprddlctl = 0x44464744,
+	.p0_mpwrdlctl = 0x3F3F3336,
+	.p1_mpwrdlctl = 0x32383630,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_qdl = {
+	.dsize = 2,
+	.cs1_mirror = 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density = 32,
+	.ncs = 1,
+	.bi_on = 1,
+	/* quad = 2, duallite = 1 */
+	.rtt_nom = 2,
+	/* quad = 2, duallite = 1 */
+	.rtt_wr = 2,
+	.ralat = 5,
+	.walat = 0,
+	.mif3_mode = 3,
+	.rst_to_cke = 0x23,
+	.sde_to_rst = 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* set the default clock gate to save power */
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_cpu_type(MXC_CPU_MX6DL)) {
+		mt41k128m16jt_125.mem_speed = 800;
+		mem_qdl.rtt_nom = 1;
+		mem_qdl.rtt_wr = 1;
+
+		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
+	} else if (is_cpu_type(MXC_CPU_MX6Q)) {
+		mt41k128m16jt_125.mem_speed = 1066;
+		mem_qdl.rtt_nom = 2;
+		mem_qdl.rtt_wr = 2;
+
+		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+		mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125);
+	}
+
+	udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* iomux */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
+#endif
diff --git a/roms/u-boot/board/vamrs/rock960_rk3399/Kconfig b/roms/u-boot/board/vamrs/rock960_rk3399/Kconfig
new file mode 100644
index 000000000..cacc53f37
--- /dev/null
+++ b/roms/u-boot/board/vamrs/rock960_rk3399/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROCK960_RK3399
+
+config SYS_BOARD
+	default "rock960_rk3399"
+
+config SYS_VENDOR
+	default "vamrs"
+
+config SYS_CONFIG_NAME
+	default "rock960_rk3399"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/roms/u-boot/board/vamrs/rock960_rk3399/MAINTAINERS b/roms/u-boot/board/vamrs/rock960_rk3399/MAINTAINERS
new file mode 100644
index 000000000..5ee525649
--- /dev/null
+++ b/roms/u-boot/board/vamrs/rock960_rk3399/MAINTAINERS
@@ -0,0 +1,11 @@
+ROCK960-RK3399
+M:      Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+S:      Maintained
+F:      board/rockchip/rock960_rk3399
+F:      include/configs/rock960_rk3399.h
+F:      configs/rock960-rk3399_defconfig
+
+FICUS EE
+M:      Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+S:      Maintained
+F:	configs/ficus-rk3399_defconfig
diff --git a/roms/u-boot/board/vamrs/rock960_rk3399/Makefile b/roms/u-boot/board/vamrs/rock960_rk3399/Makefile
new file mode 100644
index 000000000..6c3e475b3
--- /dev/null
+++ b/roms/u-boot/board/vamrs/rock960_rk3399/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+#
+
+obj-y	+= rock960-rk3399.o
diff --git a/roms/u-boot/board/vamrs/rock960_rk3399/README b/roms/u-boot/board/vamrs/rock960_rk3399/README
new file mode 100644
index 000000000..15df027fb
--- /dev/null
+++ b/roms/u-boot/board/vamrs/rock960_rk3399/README
@@ -0,0 +1,150 @@
+Contents
+========
+
+1. Introduction
+2. Get the Source and prebuild binary
+3. Compile the U-Boot
+4. Compile the rkdeveloptool
+5. Package the image
+   5.1. Package the image for U-Boot SPL(option 1)
+   5.2. Package the image for Rockchip miniloader(option 2)
+6. Bootloader storage options
+7. Flash the image to eMMC
+   7.1. Flash the image with U-Boot SPL(option 1)
+   7.2. Flash the image with Rockchip miniloader(option 2)
+8. Create a bootable SD/MMC
+9. And that is it
+
+Introduction
+============
+
+Rock960 board family consists of Rock960 (Consumer Edition) and
+Ficus (Enterprise Edition) 96Boards featuring Rockchip RK3399 SoC.
+
+Common features implemented on both boards:
+	* CPU: ARMv8 64bit Big-Little architecture,
+		* Big: dual-core Cortex-A72
+		* Little: quad-core Cortex-A53
+		* IRAM: 200KB
+	* eMMC: 16/32GB eMMC 5.1
+	* PMU: RK808
+	* SD/MMC
+	* Display: HDMI/DP/MIPI
+	* Low Speed Expansion Connector
+	* High Speed Expansion Connector
+
+Additional features of Rock960:
+	* DRAM: 2GB/4GB LPDDR3 @ 1866MHz
+	* 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only),
+	  1x USB 3.0 type C OTG
+
+Additional features of Ficus:
+	* DRAM: 2GB/4GB DDR3 @ 1600MHz
+	* Ethernet
+	* 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only),
+	  1x USB 3.0 type C OTG
+
+Here is the step-by-step to boot to U-Boot on Rock960 boards.
+
+Get the Source and prebuild binary
+==================================
+
+  > git clone https://github.com/96rocks/rkbin.git
+  > git clone https://github.com/rockchip-linux/rkdeveloptool.git
+
+Compile the U-Boot
+==================
+
+  > cd ../u-boot
+  > cp ../rkbin/rk33/rk3399_bl31_v1.00.elf ./bl31.elf
+  > export CROSS_COMPILE=aarch64-linux-gnu-
+  > make rock960-rk3399_defconfig
+  > make
+
+Compile the rkdeveloptool
+=========================
+
+Follow instructions in latest README
+  > cd ../rkdeveloptool
+  > autoreconf -i
+  > ./configure
+  > make
+  > sudo make install
+
+Package the image
+=================
+
+Package the image for U-Boot SPL(option 1)
+--------------------------------
+  > cd ..
+  > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin idbspl.img
+
+  Get idbspl.img in this step.
+
+Package the image for Rockchip miniloader(option 2)
+------------------------------------------
+  > cd ../rkbin
+  > ./tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img 0x200000
+
+  > ../u-boot/tools/mkimage -n rk3399 -T rksd -d rk3399_ddr_933MHz_v1.08.bin idbloader.img
+  > cat ./rk33/rk3399_miniloader_v1.06.bin >> idbloader.img
+
+  Get uboot.img and idbloader.img in this step.
+
+Bootloader storage options
+==========================
+
+There are a few different storage options for the bootloader.
+This document explores two of these: eMMC and removable SD/MMC.
+
+Flash the image to eMMC
+=======================
+
+Flash the image with U-Boot SPL(option 1)
+-------------------------------
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+  > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
+  > rkdeveloptool wl 64 u-boot/idbspl.img
+  > rkdeveloptool wl 0x4000 u-boot/u-boot.itb
+  > rkdeveloptool rd
+
+Flash the image with Rockchip miniloader(option 2)
+----------------------------------------
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+  > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
+  > rkdeveloptool wl 0x40 idbloader.img
+  > rkdeveloptool wl 0x4000 uboot.img
+  > rkdeveloptool wl 0x6000 ./img/rk3399/trust.img
+  > rkdeveloptool rd
+
+Create a bootable SD/MMC
+========================
+
+The idbspl.img contains the first stage, and the u-boot.img the second stage.
+As explained in the Rockchip partition table reference [1], the first stage
+(aka loader1) start sector is 64, and the second stage start sector is 16384.
+
+Each sector is 512 bytes, which means the first stage offset is 32 KiB,
+and the second stage offset is 8 MiB.
+
+Note: the second stage location is actually not as per the spec,
+but defined by the SPL. Mainline SPL defines an 8 MiB offset for the second
+stage.
+
+Assuming the SD card is exposed by device /dev/mmcblk0, the commands
+to write the two stages are:
+
+  > dd if=idbspl.img of=/dev/mmcblk0 bs=1k seek=32
+  > dd if=u-boot.itb of=/dev/mmcblk0 bs=1k seek=8192
+
+Setting up the kernel and rootfs is beyond the scope of this document.
+
+And that is it
+==============
+
+You should be able to get U-Boot log in console/UART2(baurdrate 1500000)
+
+For more detail, please reference [2].
+
+[1] http://opensource.rock-chips.com/wiki_Partitions
+[2] http://opensource.rock-chips.com/wiki_Boot_option
diff --git a/roms/u-boot/board/vamrs/rock960_rk3399/rock960-rk3399.c b/roms/u-boot/board/vamrs/rock960_rk3399/rock960-rk3399.c
new file mode 100644
index 000000000..a7fc38d42
--- /dev/null
+++ b/roms/u-boot/board/vamrs/rock960_rk3399/rock960-rk3399.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <linux/bitops.h>
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	struct rk3399_grf_regs *grf =
+	    syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+	/**
+	 * Some SSD's to work on rock960 would require explicit
+	 * domain voltage change, so BT565 is in 1.8v domain
+	 */
+	rk_setreg(&grf->io_vsel, BIT(0));
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/variscite/dart_6ul/Kconfig b/roms/u-boot/board/variscite/dart_6ul/Kconfig
new file mode 100644
index 000000000..1765af1d8
--- /dev/null
+++ b/roms/u-boot/board/variscite/dart_6ul/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DART_6UL
+
+config SYS_BOARD
+	default "dart_6ul"
+
+config SYS_VENDOR
+	default "variscite"
+
+config SYS_CONFIG_NAME
+	default "dart_6ul"
+
+endif
diff --git a/roms/u-boot/board/variscite/dart_6ul/MAINTAINERS b/roms/u-boot/board/variscite/dart_6ul/MAINTAINERS
new file mode 100644
index 000000000..339f93fa6
--- /dev/null
+++ b/roms/u-boot/board/variscite/dart_6ul/MAINTAINERS
@@ -0,0 +1,8 @@
+MX6UL_DART BOARD
+M:	Parthiban Nallathambi <parthitce@gmail.com>
+S:	Maintained
+F:	arch/arm/dts/imx6ull-dart-6ul.dts
+F:	arch/arm/dts/imx6ull-dart-6ul.dtsi
+F:	board/variscite/dart_6ul/
+F:	configs/variscite_dart6ul_defconfig
+F:	include/configs/dart_6ul.h
diff --git a/roms/u-boot/board/variscite/dart_6ul/Makefile b/roms/u-boot/board/variscite/dart_6ul/Makefile
new file mode 100644
index 000000000..48aa361bf
--- /dev/null
+++ b/roms/u-boot/board/variscite/dart_6ul/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y  := dart_6ul.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/roms/u-boot/board/variscite/dart_6ul/README b/roms/u-boot/board/variscite/dart_6ul/README
new file mode 100644
index 000000000..d76b997e2
--- /dev/null
+++ b/roms/u-boot/board/variscite/dart_6ul/README
@@ -0,0 +1,41 @@
+How to use U-Boot on variscite DART-6UL Evaluation Kit
+------------------------------------------------------
+
+- Configure and build U-Boot for DART-6UL iMX6ULL:
+
+    $ make mrproper
+    $ make variscite_dart6ul_defconfig
+    $ make
+
+  This will generate SPL and u-boot-dtb.img images.
+
+Boot from MMC/SD:
+- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card:
+
+    $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+    $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Boot mode settings:
+
+  Boot switch position: SW1 -> 0
+			SW2 -> 0
+
+Boot from eMMC:
+- if bootpart is not enabled by default, to enable under Linux
+	echo 0 >/sys/block/mmcblk1boot0/force_ro
+	mmc bootpart enable 1 1 /dev/mmcblk1boot0
+
+- Flash the SPL and u-boot-dtb.img to mmcblk1boot0
+    $ sudo dd if=SPL of=/dev/mmcblk1boot0 bs=1k seek=1; sync
+    $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk1boot0 bs=1k seek=69; sync
+
+- Boot mode settings:
+
+  Boot switch position: SW1 -> 0
+			SW2 -> 1
+
+- Connect the Serial cable to UART0 and the PC for the console.
+
+- Insert the micro SD card in the board and power it up.
+
+- U-Boot messages should come up.
diff --git a/roms/u-boot/board/variscite/dart_6ul/dart_6ul.c b/roms/u-boot/board/variscite/dart_6ul/dart_6ul.c
new file mode 100644
index 000000000..7326daa17
--- /dev/null
+++ b/roms/u-boot/board/variscite/dart_6ul/dart_6ul.c
@@ -0,0 +1,263 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2019 Variscite Ltd.
+ * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
+ * Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <dm.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c_eeprom.h>
+#include <linux/bitops.h>
+#include <malloc.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+#ifdef CONFIG_NAND_MXS
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+static iomux_v3_cfg_t const nand_pads[] = {
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+
+	clrbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+	/*
+	 * config gpmi and bch clock to 100 MHz
+	 * bch/gpmi select PLL2 PFD2 400M
+	 * 100M = 400M / 4
+	 */
+	clrbits_le32(&mxc_ccm->cscmr1,
+		     MXC_CCM_CSCMR1_BCH_CLK_SEL |
+		     MXC_CCM_CSCMR1_GPMI_CLK_SEL);
+	clrsetbits_le32(&mxc_ccm->cscdr1,
+			MXC_CCM_CSCDR1_BCH_PODF_MASK |
+			MXC_CCM_CSCDR1_GPMI_PODF_MASK,
+			(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
+			(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(int fec_id)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	if (fec_id == 0) {
+		/*
+		 * Use 50M anatop loopback REF_CLK1 for ENET1,
+		 * clear gpr1[13], set gpr1[17].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+	} else {
+		/*
+		 * Use 50M anatop loopback REF_CLK2 for ENET2,
+		 * clear gpr1[14], set gpr1[18].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+	}
+
+	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/*
+	 * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
+	 * 50 MHz RMII clock mode.
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif /* CONFIG_FEC_MXC */
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec(CONFIG_FEC_ENET_DEV);
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+	return 0;
+}
+
+/* length of strings stored in the eeprom */
+#define DART6UL_PN_LEN   16
+#define DART6UL_ASSY_LEN 16
+#define DART6UL_DATE_LEN 12
+
+/* eeprom content, 512 bytes */
+struct dart6ul_info {
+	u32 magic;
+	u8 partnumber[DART6UL_PN_LEN];
+	u8 assy[DART6UL_ASSY_LEN];
+	u8 date[DART6UL_DATE_LEN];
+	u32 custom_addr_val[32];
+	struct cmd {
+		u8 addr;
+		u8 index;
+	} custom_cmd[150];
+	u8 res[33];
+	u8 som_info;
+	u8 ddr_size;
+	u8 crc;
+} __attribute__ ((__packed__));
+
+#define DART6UL_INFO_STORAGE_GET(n) ((n) & 0x3)
+#define DART6UL_INFO_WIFI_GET(n)    ((n) >> 2 & 0x1)
+#define DART6UL_INFO_REV_GET(n)     ((n) >> 3 & 0x3)
+#define DART6UL_DDRSIZE(n)          ((n) * SZ_128M)
+#define DART6UL_INFO_MAGIC          0x32524156
+
+static const char *som_info_storage_to_str(u8 som_info)
+{
+	switch (DART6UL_INFO_STORAGE_GET(som_info)) {
+	case 0x0: return "none (SD only)";
+	case 0x1: return "NAND";
+	case 0x2: return "eMMC";
+	default: return "unknown";
+	}
+}
+
+static const char *som_info_rev_to_str(u8 som_info)
+{
+	switch (DART6UL_INFO_REV_GET(som_info)) {
+	case 0x0: return "2.4G";
+	case 0x1: return "5G";
+	default: return "unknown";
+	}
+}
+
+int checkboard(void)
+{
+	const char *path = "eeprom0";
+	struct dart6ul_info *info;
+	struct udevice *dev;
+	int ret, off;
+
+	off = fdt_path_offset(gd->fdt_blob, path);
+	if (off < 0) {
+		printf("%s: fdt_path_offset() failed: %d\n", __func__, off);
+		return off;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+	if (ret) {
+		printf("%s: uclass_get_device_by_of_offset() failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	info = malloc(sizeof(struct dart6ul_info));
+	if (!info)
+		return -ENOMEM;
+
+	ret = i2c_eeprom_read(dev, 0, (uint8_t *)info,
+			      sizeof(struct dart6ul_info));
+	if (ret) {
+		printf("%s: i2c_eeprom_read() failed: %d\n", __func__, ret);
+		free(info);
+		return ret;
+	}
+
+	if (info->magic != DART6UL_INFO_MAGIC) {
+		printf("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n",
+		       info->magic, DART6UL_INFO_MAGIC);
+		/* do not fail if the content is invalid */
+		free(info);
+		return 0;
+	}
+
+	/* make sure strings are null terminated */
+	info->partnumber[DART6UL_PN_LEN - 1] = '\0';
+	info->assy[DART6UL_ASSY_LEN - 1] = '\0';
+	info->date[DART6UL_DATE_LEN - 1] = '\0';
+
+	printf("Board: PN: %s, Assy: %s, Date: %s\n"
+	       "       Storage: %s, Wifi: %s, DDR: %d MiB, Rev: %s\n",
+	       info->partnumber,
+	       info->assy,
+	       info->date,
+	       som_info_storage_to_str(info->som_info),
+	       DART6UL_INFO_WIFI_GET(info->som_info) ? "yes" : "no",
+	       DART6UL_DDRSIZE(info->ddr_size) / SZ_1M,
+	       som_info_rev_to_str(info->som_info));
+
+	free(info);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/variscite/dart_6ul/spl.c b/roms/u-boot/board/variscite/dart_6ul/spl.c
new file mode 100644
index 000000000..91d470f6e
--- /dev/null
+++ b/roms/u-boot/board/variscite/dart_6ul/spl.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2019 Variscite Ltd.
+ * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/crm_regs.h>
+#include <fsl_esdhc_imx.h>
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000008,
+	.dram_sdqs0 = 0x00000038,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0   = 0x414C0158,
+	.p0_mprddlctl   = 0x40403A3A,
+	.p0_mpwrdlctl   = 0x40405A56,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,
+	.cs_density = 20,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 2,
+	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
+	.walat = 1,		/* Write additional latency */
+	.ralat = 5,		/* Read additional latency */
+	.mif3_mode = 3,		/* Command prediction working mode */
+	.bi_on = 1,		/* Bank interleaving enabled */
+	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+	writel(0xFFFFFFFF, &ccm->CCGR7);
+	/* Enable Audio Clock for SOM codec */
+	writel(0x01130100, (long *)CCM_CCOSR);
+}
+
+static void spl_dram_init(void)
+{
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifndef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+	{
+		.esdhc_base = USDHC1_BASE_ADDR,
+		.max_bus_width = 4,
+	},
+#ifndef CONFIG_NAND_MXS
+	{
+		.esdhc_base = USDHC2_BASE_ADDR,
+		.max_bus_width = 8,
+	},
+#endif
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+#ifndef CONFIG_NAND_MXS
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+#endif
+		default:
+			printf("Warning - USDHC%d controller not supporting\n",
+			       i + 1);
+			return 0;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+	setup_iomux_uart();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
diff --git a/roms/u-boot/board/varisys/common/Makefile b/roms/u-boot/board/varisys/common/Makefile
new file mode 100644
index 000000000..b7358c7c6
--- /dev/null
+++ b/roms/u-boot/board/varisys/common/Makefile
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ID_EEPROM)	+= sys_eeprom.o
+endif
+endif
diff --git a/roms/u-boot/board/varisys/common/eeprom.h b/roms/u-boot/board/varisys/common/eeprom.h
new file mode 100644
index 000000000..004816a0f
--- /dev/null
+++ b/roms/u-boot/board/varisys/common/eeprom.h
@@ -0,0 +1,6 @@
+/* EEPROM init functions for Cyrus */
+
+
+void init_eeprom(int bus_num, int addr, int addr_len);
+void mac_read_from_fixed_id(void);
+int mac_read_from_eeprom_common(void);
diff --git a/roms/u-boot/board/varisys/common/sys_eeprom.c b/roms/u-boot/board/varisys/common/sys_eeprom.c
new file mode 100644
index 000000000..251d9fd73
--- /dev/null
+++ b/roms/u-boot/board/varisys/common/sys_eeprom.c
@@ -0,0 +1,500 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Based on board/freescale/common/sys_eeprom.c
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ *
+ * This defines the API for storing board information in the
+ * eeprom. It has been adapted from an earlier version of the
+ * Freescale API, but has a number of key differences. Because
+ * the two APIs are independent and may diverge further, the
+ * Varisys version of the API is implemented separately here.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+#include <linux/delay.h>
+#include <u-boot/crc.h>
+
+#include "eeprom.h"
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC
+#define MAX_NUM_PORTS	CONFIG_SYS_I2C_EEPROM_NXID_MAC
+#else
+#define MAX_NUM_PORTS	8
+#endif
+#define NXID_VERSION	0
+
+/**
+ * static eeprom: EEPROM layout for NXID formats
+ *
+ * See Freescale application note AN3638 for details.
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+	u8 id[4];         /* 0x00 - 0x03 EEPROM Tag 'NXID' */
+	u8 sn[12];        /* 0x04 - 0x0F Serial Number */
+	u8 errata[5];     /* 0x10 - 0x14 Errata Level */
+	u8 date[6];       /* 0x15 - 0x1a Build Date */
+	u8 res_0;         /* 0x1b        Reserved */
+	u32 version;      /* 0x1c - 0x1f NXID Version */
+	u8 tempcal[8];    /* 0x20 - 0x27 Temperature Calibration Factors */
+	u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */
+	u8 tempcalflags;  /* 0x2a        Temperature Calibration Flags */
+	u8 res_1[21];     /* 0x2b - 0x3f Reserved */
+	u8 mac_count;     /* 0x40        Number of MAC addresses */
+	u8 mac_flag;      /* 0x41        MAC table flags */
+	u8 mac[MAX_NUM_PORTS][6];     /* 0x42 - x MAC addresses */
+	u32 crc;          /* x+1         CRC32 checksum */
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/* Is this a valid NXID EEPROM? */
+#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \
+		  (e.id[2] == 'I') || (e.id[3] == 'D'))
+
+/** Fixed ID field in EEPROM */
+static unsigned char uid[16];
+
+static int eeprom_bus_num = -1;
+static int eeprom_addr;
+static int eeprom_addr_len;
+
+/**
+ * This must be called before any eeprom access.
+ */
+void init_eeprom(int bus_num, int addr, int addr_len)
+{
+	eeprom_bus_num = bus_num;
+	eeprom_addr = addr;
+	eeprom_addr_len = addr_len;
+}
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+void show_eeprom(void)
+{
+	int i;
+	unsigned int crc;
+
+	/* EEPROM tag ID, either CCID or NXID */
+	printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
+		be32_to_cpu(e.version));
+
+	/* Serial number */
+	printf("SN: %s\n", e.sn);
+
+	printf("UID: ");
+	for (i = 0; i < 16; i++)
+		printf("%02x", uid[i]);
+	printf("\n");
+
+	/* Errata level. */
+	printf("Errata: %s\n", e.errata);
+
+	/* Build date, BCD date values, as YYMMDDhhmmss */
+	printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+		e.date[0], e.date[1], e.date[2],
+		e.date[3] & 0x7F, e.date[4], e.date[5],
+		e.date[3] & 0x80 ? "PM" : "");
+
+	/* Show MAC addresses  */
+	for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
+		u8 *p = e.mac[i];
+
+		printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
+		       p[0], p[1], p[2], p[3], p[4], p[5]);
+	}
+
+	crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+	if (crc == be32_to_cpu(e.crc))
+		printf("CRC: %08x\n", be32_to_cpu(e.crc));
+	else
+		printf("CRC: %08x (should be %08x)\n",
+		       be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+	printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+	for (i = 0; i < sizeof(e); i++) {
+		if ((i % 16) == 0)
+			printf("%02X: ", i);
+		printf("%02X ", ((u8 *)&e)[i]);
+		if (((i % 16) == 15) || (i == sizeof(e) - 1))
+			printf("\n");
+	}
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+int read_eeprom(void)
+{
+	int ret;
+	unsigned int bus;
+
+	if (eeprom_bus_num < 0) {
+		printf("EEPROM not configured\n");
+		return -1;
+	}
+
+	if (has_been_read)
+		return 0;
+
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(eeprom_bus_num);
+
+	ret = i2c_read(eeprom_addr, 0, eeprom_addr_len,
+		(void *)&e, sizeof(e));
+
+
+	/* Fixed address of ID field */
+	i2c_read(0x5f, 0x80, 1, uid, 16);
+
+	i2c_set_bus_num(bus);
+
+#ifdef DEBUG
+	show_eeprom();
+#endif
+
+	has_been_read = (ret == 0) ? 1 : 0;
+
+	return ret;
+}
+
+/**
+ *  update_crc - update the CRC
+ *
+ *  This function should be called after each update to the EEPROM structure,
+ *  to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+	u32 crc, crc_offset = offsetof(struct eeprom, crc);
+
+	crc = crc32(0, (void *)&e, crc_offset);
+	e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+	int ret = 0;
+	int i;
+	void *p;
+	unsigned int bus;
+
+	if (eeprom_bus_num < 0) {
+		printf("EEPROM not configured\n");
+		return -1;
+	}
+
+	/* Set the reserved values to 0xFF   */
+	e.res_0 = 0xFF;
+	memset(e.res_1, 0xFF, sizeof(e.res_1));
+	update_crc();
+
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(eeprom_bus_num);
+
+	/*
+	 * The AT24C02 datasheet says that data can only be written in page
+	 * mode, which means 8 bytes at a time, and it takes up to 5ms to
+	 * complete a given write.
+	 */
+	for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
+		ret = i2c_write(eeprom_addr, i, eeprom_addr_len,
+			p, min((int)(sizeof(e) - i), 8));
+		if (ret)
+			break;
+		udelay(5000);	/* 5ms write cycle timing */
+	}
+
+	if (!ret) {
+		/* Verify the write by reading back the EEPROM and comparing */
+		struct eeprom e2;
+
+		ret = i2c_read(eeprom_addr, 0,
+			eeprom_addr_len, (void *)&e2, sizeof(e2));
+		if (!ret && memcmp(&e, &e2, sizeof(e)))
+			ret = -1;
+	}
+
+	i2c_set_bus_num(bus);
+
+	if (ret) {
+		printf("Programming failed.\n");
+		has_been_read = 0;
+		return -1;
+	}
+
+	printf("Programming passed.\n");
+	return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+	if ((p >= '0') && (p <= '9'))
+		return p - '0';
+
+	if ((p >= 'A') && (p <= 'F'))
+		return (p - 'A') + 10;
+
+	if ((p >= 'a') && (p <= 'f'))
+		return (p - 'a') + 10;
+
+	return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+	unsigned int i;
+
+	if (strlen(string) != 12) {
+		printf("Usage: mac date YYMMDDhhmmss\n");
+		return;
+	}
+
+	for (i = 0; i < 6; i++)
+		e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+	update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in one of the MAC address fields of the EEPROM local copy.
+ */
+static void set_mac_address(unsigned int index, const char *string)
+{
+	char *p = (char *)string;
+	unsigned int i;
+
+	if ((index >= MAX_NUM_PORTS) || !string) {
+		printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
+		return;
+	}
+
+	for (i = 0; *p && (i < 6); i++) {
+		e.mac[index][i] = simple_strtoul(p, &p, 16);
+		if (*p == ':')
+			p++;
+	}
+
+	update_crc();
+}
+
+int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	char cmd;
+
+	if (argc == 1) {
+		show_eeprom();
+		return 0;
+	}
+
+	cmd = argv[1][0];
+
+	if (cmd == 'r') {
+		read_eeprom();
+		return 0;
+	}
+
+	if (cmd == 'i') {
+		memcpy(e.id, "NXID", sizeof(e.id));
+		e.version = NXID_VERSION;
+		update_crc();
+		return 0;
+	}
+
+	if (!is_valid) {
+		printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n");
+		return 0;
+	}
+
+	if (argc == 2) {
+		switch (cmd) {
+		case 's':	/* save */
+			prog_eeprom();
+			break;
+		default:
+			return cmd_usage(cmdtp);
+		}
+
+		return 0;
+	}
+
+	/* We know we have at least one parameter  */
+
+	switch (cmd) {
+	case 'n':	/* serial number */
+		memset(e.sn, 0, sizeof(e.sn));
+		strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+		update_crc();
+		break;
+	case 'e':	/* errata */
+		memset(e.errata, 0, 5);
+		strncpy((char *)e.errata, argv[2], 4);
+		update_crc();
+		break;
+	case 'd':	/* date BCD format YYMMDDhhmmss */
+		set_date(argv[2]);
+		break;
+	case 'p':	/* MAC table size */
+		e.mac_count = simple_strtoul(argv[2], NULL, 16);
+		update_crc();
+		break;
+	case '0' ... '9':	/* "mac 0" through "mac 22" */
+		set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]);
+		break;
+	case 'h':	/* help */
+	default:
+		return cmd_usage(cmdtp);
+	}
+
+	return 0;
+}
+
+int mac_read_from_generic_eeprom(const char *envvar, int chip,
+	int address, int mac_bus)
+{
+	int ret;
+	unsigned int bus;
+	unsigned char mac[6];
+	char ethaddr[18];
+
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(mac_bus);
+
+	ret = i2c_read(chip, address, 1, mac, 6);
+
+	i2c_set_bus_num(bus);
+
+	if (!ret) {
+		sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+			mac[0],
+			mac[1],
+			mac[2],
+			mac[3],
+			mac[4],
+			mac[5]);
+
+		printf("MAC: %s\n", ethaddr);
+		env_set(envvar, ethaddr);
+	}
+
+	return ret;
+}
+
+void mac_read_from_fixed_id(void)
+{
+#ifdef CONFIG_SYS_I2C_MAC1_CHIP_ADDR
+	mac_read_from_generic_eeprom("ethaddr", CONFIG_SYS_I2C_MAC1_CHIP_ADDR,
+		CONFIG_SYS_I2C_MAC1_DATA_ADDR, CONFIG_SYS_I2C_MAC1_BUS);
+#endif
+#ifdef CONFIG_SYS_I2C_MAC2_CHIP_ADDR
+	mac_read_from_generic_eeprom("eth1addr", CONFIG_SYS_I2C_MAC2_CHIP_ADDR,
+		CONFIG_SYS_I2C_MAC2_DATA_ADDR, CONFIG_SYS_I2C_MAC2_BUS);
+#endif
+}
+
+/**
+ * mac_read_from_eeprom - read the MAC addresses from EEPROM
+ *
+ * This function reads the MAC addresses from EEPROM and sets the
+ * appropriate environment variables for each one read.
+ *
+ * The environment variables are only set if they haven't been set already.
+ * This ensures that any user-saved variables are never overwritten.
+ *
+ * This function must be called after relocation.
+ *
+ * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0
+ * format.  In a v0 EEPROM, there are only eight MAC addresses and the CRC is
+ * located at a different offset.
+ */
+int mac_read_from_eeprom_common(void)
+{
+	unsigned int i;
+	u32 crc, crc_offset = offsetof(struct eeprom, crc);
+	u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+	puts("EEPROM: ");
+
+	if (read_eeprom()) {
+		printf("Read failed.\n");
+		return 0;
+	}
+
+	if (!is_valid) {
+		printf("Invalid ID (%02x %02x %02x %02x)\n",
+		       e.id[0], e.id[1], e.id[2], e.id[3]);
+		return 0;
+	}
+
+	crc = crc32(0, (void *)&e, crc_offset);
+	crcp = (void *)&e + crc_offset;
+	if (crc != be32_to_cpu(*crcp)) {
+		printf("CRC mismatch (%08x != %08x)\n", crc,
+			be32_to_cpu(e.crc));
+		return 0;
+	}
+
+	/*
+	 * MAC address #9 in v1 occupies the same position as the CRC in v0.
+	 * Erase it so that it's not mistaken for a MAC address.  We'll
+	 * update the CRC later.
+	 */
+	if (e.version == 0)
+		memset(e.mac[8], 0xff, 6);
+
+	for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
+		if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
+		    memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+			char ethaddr[18];
+			char enetvar[9];
+
+			sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+				e.mac[i][0],
+				e.mac[i][1],
+				e.mac[i][2],
+				e.mac[i][3],
+				e.mac[i][4],
+				e.mac[i][5]);
+			sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i);
+			/* Only initialize environment variables that are blank
+			 * (i.e. have not yet been set)
+			 */
+			if (!env_get(enetvar))
+				env_set(enetvar, ethaddr);
+		}
+	}
+
+	printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
+		be32_to_cpu(e.version));
+
+	return 0;
+}
diff --git a/roms/u-boot/board/ve8313/Kconfig b/roms/u-boot/board/ve8313/Kconfig
new file mode 100644
index 000000000..a63744b15
--- /dev/null
+++ b/roms/u-boot/board/ve8313/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_VE8313
+
+config SYS_BOARD
+	default "ve8313"
+
+config SYS_CONFIG_NAME
+	default "ve8313"
+
+endif
diff --git a/roms/u-boot/board/ve8313/MAINTAINERS b/roms/u-boot/board/ve8313/MAINTAINERS
new file mode 100644
index 000000000..e3ca3325f
--- /dev/null
+++ b/roms/u-boot/board/ve8313/MAINTAINERS
@@ -0,0 +1,6 @@
+VE8313 BOARD
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	board/ve8313/
+F:	include/configs/ve8313.h
+F:	configs/ve8313_defconfig
diff --git a/roms/u-boot/board/ve8313/Makefile b/roms/u-boot/board/ve8313/Makefile
new file mode 100644
index 000000000..d656bd93a
--- /dev/null
+++ b/roms/u-boot/board/ve8313/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= ve8313.o
diff --git a/roms/u-boot/board/ve8313/ve8313.c b/roms/u-boot/board/ve8313/ve8313.c
new file mode 100644
index 000000000..78d401e95
--- /dev/null
+++ b/roms/u-boot/board/ve8313/ve8313.c
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <ns16550.h>
+#include <nand.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void disable_addr_trans (void);
+extern void enable_addr_trans (void);
+
+int checkboard(void)
+{
+	puts("Board: ve8313\n");
+	return 0;
+}
+
+static long fixed_sdram(void)
+{
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+		(CONFIG_SYS_SDRAM_BASE & 0xfffff000));
+	out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	__udelay(50000);
+
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+	out_be32(&im->ddr.csbnds[0].csbnds,
+		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+			CSBNDS_EA));
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
+
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+
+	/* now check the real size */
+	disable_addr_trans ();
+	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
+	enable_addr_trans ();
+#endif
+
+	return msize;
+}
+
+int dram_init(void)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile fsl_lbc_t *lbc = &im->im_lbc;
+	u32 msize;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	msize = fixed_sdram();
+
+	/* Local Bus setup lbcr and mrtpr */
+	out_be32(&lbc->lbcr, 0x00040000);
+	out_be32(&lbc->mrtpr, 0x20000000);
+	sync();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
+}
+
+#define VE8313_WDT_EN	0x00020000
+#define VE8313_WDT_TRIG	0x00040000
+
+int board_early_init_f (void)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
+
+#if defined(CONFIG_HW_WATCHDOG)
+	/* enable WDT */
+	clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
+#else
+	/* disable WDT */
+	setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
+#endif
+	/* set WDT pins as output */
+	setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
+
+	return 0;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
+	unsigned long reg;
+
+	reg = in_be32(&gpio->dat);
+	if (reg & VE8313_WDT_TRIG)
+		clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
+	else
+		setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
+}
+#endif
+
+
+#if defined(CONFIG_PCI)
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci_regions };
+
+	/* Enable all 3 PCI_CLK_OUTPUTs. */
+	setbits_be32(&clk->occr, 0xe0000000);
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
+	out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
+	out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
+
+	mpc83xx_pci_init(1, reg);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/vocore/vocore2/Kconfig b/roms/u-boot/board/vocore/vocore2/Kconfig
new file mode 100644
index 000000000..baeff31b6
--- /dev/null
+++ b/roms/u-boot/board/vocore/vocore2/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_VOCORE2
+
+config SYS_BOARD
+	default "vocore2"
+
+config SYS_VENDOR
+	default "vocore"
+
+config SYS_CONFIG_NAME
+	default "vocore2"
+
+endif
diff --git a/roms/u-boot/board/vocore/vocore2/MAINTAINERS b/roms/u-boot/board/vocore/vocore2/MAINTAINERS
new file mode 100644
index 000000000..8472351fe
--- /dev/null
+++ b/roms/u-boot/board/vocore/vocore2/MAINTAINERS
@@ -0,0 +1,7 @@
+VOCORE_VOCORE2 BOARD
+M:	Mauro Condarelli <mc5686@mclink.it>
+S:	Maintained
+F: board/vocore/vocore2
+F: include/configs/vocore2.h
+F: configs/vocore2_defconfig
+F: arch/mips/dts/vocore_vocore2.dts
diff --git a/roms/u-boot/board/vocore/vocore2/Makefile b/roms/u-boot/board/vocore/vocore2/Makefile
new file mode 100644
index 000000000..70cd7a8e5
--- /dev/null
+++ b/roms/u-boot/board/vocore/vocore2/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += board.o
diff --git a/roms/u-boot/board/vocore/vocore2/board.c b/roms/u-boot/board/vocore/vocore2/board.c
new file mode 100644
index 000000000..27e42d141
--- /dev/null
+++ b/roms/u-boot/board/vocore/vocore2/board.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Mauro Condarelli <mc5686@mclink.it>
+ *
+ * Nothing actually needed here
+ */
diff --git a/roms/u-boot/board/vscom/baltos/Kconfig b/roms/u-boot/board/vscom/baltos/Kconfig
new file mode 100644
index 000000000..b721ed19d
--- /dev/null
+++ b/roms/u-boot/board/vscom/baltos/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AM335X_BALTOS
+
+config SYS_BOARD
+	default "baltos"
+
+config SYS_VENDOR
+	default "vscom"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "baltos"
+
+endif
diff --git a/roms/u-boot/board/vscom/baltos/MAINTAINERS b/roms/u-boot/board/vscom/baltos/MAINTAINERS
new file mode 100644
index 000000000..e82acfed1
--- /dev/null
+++ b/roms/u-boot/board/vscom/baltos/MAINTAINERS
@@ -0,0 +1,6 @@
+BALTOS BOARD
+M:	Yegor Yefremov <yegorslists@googlemail.com>
+S:	Maintained
+F:	board/vscom/baltos/
+F:	include/configs/baltos.h
+F:	configs/am335x_baltos_defconfig
diff --git a/roms/u-boot/board/vscom/baltos/Makefile b/roms/u-boot/board/vscom/baltos/Makefile
new file mode 100644
index 000000000..c34b9b1dd
--- /dev/null
+++ b/roms/u-boot/board/vscom/baltos/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/roms/u-boot/board/vscom/baltos/README b/roms/u-boot/board/vscom/baltos/README
new file mode 100644
index 000000000..f744ace99
--- /dev/null
+++ b/roms/u-boot/board/vscom/baltos/README
@@ -0,0 +1 @@
+BSP for VScom OnRISC Balios family devices, like Balios iR 5221.
diff --git a/roms/u-boot/board/vscom/baltos/board.c b/roms/u-boot/board/vscom/baltos/board.c
new file mode 100644
index 000000000..4175d4146
--- /dev/null
+++ b/roms/u-boot/board/vscom/baltos/board.c
@@ -0,0 +1,492 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <net.h>
+#include <serial.h>
+#include <asm/global_data.h>
+#include <linux/libfdt.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65910.h>
+#include <watchdog.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO that controls DIP switch and mPCIe slot */
+#define DIP_S1			44
+#define MPCIE_SW		100
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static int baltos_set_console(void)
+{
+	int val, i, dips = 0;
+	char buf[7];
+
+	for (i = 0; i < 4; i++) {
+		sprintf(buf, "dip_s%d", i + 1);
+
+		if (gpio_request(DIP_S1 + i, buf)) {
+			printf("failed to export GPIO %d\n", DIP_S1 + i);
+			return 0;
+		}
+
+		if (gpio_direction_input(DIP_S1 + i)) {
+			printf("failed to set GPIO %d direction\n", DIP_S1 + i);
+			return 0;
+		}
+
+		val = gpio_get_value(DIP_S1 + i);
+		dips |= val << i;
+	}
+
+	printf("DIPs: 0x%1x\n", (~dips) & 0xf);
+
+	if ((dips & 0xf) == 0xe)
+		env_set("console", "ttyUSB0,115200n8");
+
+	return 0;
+}
+
+static int read_eeprom(BSP_VS_HWPARAM *header)
+{
+	i2c_set_bus_num(1);
+
+	/* Check if baseboard eeprom is available */
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		puts("Could not probe the EEPROM; something fundamentally "
+			"wrong on the I2C bus.\n");
+		return -ENODEV;
+	}
+
+	/* read the eeprom using i2c */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+		     sizeof(BSP_VS_HWPARAM))) {
+		puts("Could not read the EEPROM; something fundamentally"
+			" wrong on the I2C bus.\n");
+		return -EIO;
+	}
+
+	if (header->Magic != 0xDEADBEEF) {
+
+		printf("Incorrect magic number (0x%x) in EEPROM\n",
+				header->Magic);
+
+		/* fill default values */
+		header->SystemId = 211;
+		header->MAC1[0] = 0x00;
+		header->MAC1[1] = 0x00;
+		header->MAC1[2] = 0x00;
+		header->MAC1[3] = 0x00;
+		header->MAC1[4] = 0x00;
+		header->MAC1[5] = 0x01;
+
+		header->MAC2[0] = 0x00;
+		header->MAC2[1] = 0x00;
+		header->MAC2[2] = 0x00;
+		header->MAC2[3] = 0x00;
+		header->MAC2[4] = 0x00;
+		header->MAC2[5] = 0x02;
+
+		header->MAC3[0] = 0x00;
+		header->MAC3[1] = 0x00;
+		header->MAC3[2] = 0x00;
+		header->MAC3[3] = 0x00;
+		header->MAC3[4] = 0x00;
+		header->MAC3[5] = 0x03;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+
+static const struct ddr_data ddr3_baltos_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_baltos_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	return (serial_tstc() && serial_getc() == 'c');
+}
+#endif
+
+#define OSC	(V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+		266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_evm_sk = {
+		303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_baltos = {
+		400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	int mpu_vdd;
+	int sil_rev;
+
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/*
+	 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
+	 * MPU frequencies we support we use a CORE voltage of
+	 * 1.1375V.  For MPU voltage we need to switch based on
+	 * the frequency we are running at.
+	 */
+	i2c_set_bus_num(1);
+
+	printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
+
+	if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
+		puts("i2c: cannot access TPS65910\n");
+		return;
+	}
+
+	/*
+	 * Depending on MPU clock and PG we will need a different
+	 * VDD to drive at that speed.
+	 */
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
+					      dpll_mpu_opp100.m);
+
+	/* Tell the TPS65910 to use i2c */
+	tps65910_set_i2c_control();
+
+	/* First update MPU voltage. */
+	if (tps65910_voltage_update(MPU, mpu_vdd))
+		return;
+
+	/* Second, update the CORE voltage. */
+	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
+		return;
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+
+	writel(0x000010ff, PRM_DEVICE_INST + 4);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	enable_i2c1_pin_mux();
+	i2c_set_bus_num(1);
+
+	return &dpll_ddr_baltos;
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs_baltos = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+	config_ddr(400, &ioregs_baltos,
+		   &ddr3_baltos_data,
+		   &ddr3_baltos_cmd_ctrl_data,
+		   &ddr3_baltos_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
+	gpmc_init();
+#endif
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int node, ret;
+	unsigned char mac_addr[6];
+	BSP_VS_HWPARAM header;
+
+	/* get production data */
+	if (read_eeprom(&header))
+		return 0;
+
+	/* setup MAC1 */
+	mac_addr[0] = header.MAC1[0];
+	mac_addr[1] = header.MAC1[1];
+	mac_addr[2] = header.MAC1[2];
+	mac_addr[3] = header.MAC1[3];
+	mac_addr[4] = header.MAC1[4];
+	mac_addr[5] = header.MAC1[5];
+
+
+	node = fdt_path_offset(blob, "ethernet0");
+	if (node < 0) {
+		printf("no ethernet0 path offset\n");
+		return -ENODEV;
+	}
+
+	ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
+	if (ret) {
+		printf("error setting mac-address property\n");
+		return -ENODEV;
+	}
+
+	/* setup MAC2 */
+	mac_addr[0] = header.MAC2[0];
+	mac_addr[1] = header.MAC2[1];
+	mac_addr[2] = header.MAC2[2];
+	mac_addr[3] = header.MAC2[3];
+	mac_addr[4] = header.MAC2[4];
+	mac_addr[5] = header.MAC2[5];
+
+	node = fdt_path_offset(blob, "ethernet1");
+	if (node < 0) {
+		printf("no ethernet1 path offset\n");
+		return -ENODEV;
+	}
+
+	ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
+	if (ret) {
+		printf("error setting mac-address property\n");
+		return -ENODEV;
+	}
+
+	printf("\nFDT was successfully setup\n");
+
+	return 0;
+}
+
+static struct module_pin_mux pcie_sw_pin_mux[] = {
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )},     /* GPIO3_4 */
+	{-1},
+};
+
+static struct module_pin_mux dip_pin_mux[] = {
+	{OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )},	/* GPIO1_12 */
+	{OFFSET(gpmc_ad13), (MODE(7)  | RXACTIVE )},	/* GPIO1_13 */
+	{OFFSET(gpmc_ad14), (MODE(7)  | RXACTIVE )},	/* GPIO1_14 */
+	{OFFSET(gpmc_ad15), (MODE(7)  | RXACTIVE )},	/* GPIO1_15 */
+	{-1},
+};
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	BSP_VS_HWPARAM header;
+	char model[4];
+
+	/* get production data */
+	if (read_eeprom(&header)) {
+		strcpy(model, "211");
+	} else {
+		sprintf(model, "%d", header.SystemId);
+		if (header.SystemId == 215) {
+			configure_module_pin_mux(dip_pin_mux);
+			baltos_set_console();
+		}
+	}
+
+	/* turn power for the mPCIe slot */
+	configure_module_pin_mux(pcie_sw_pin_mux);
+	if (gpio_request(MPCIE_SW, "mpcie_sw")) {
+		printf("failed to export GPIO %d\n", MPCIE_SW);
+		return -ENODEV;
+	}
+	if (gpio_direction_output(MPCIE_SW, 1)) {
+		printf("failed to set GPIO %d direction\n", MPCIE_SW);
+		return -ENODEV;
+	}
+
+	env_set("board_name", model);
+#endif
+
+	return 0;
+}
+#endif
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 7,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 2,
+	.slave_data		= cpsw_slaves,
+	.active_slave		= 1,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif
+
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
+		&& defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
+	 !defined(CONFIG_SPL_BUILD))
+int board_eth_init(struct bd_info *bis)
+{
+	int rv, n = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/*
+	 * Note here that we're using CPSW1 since that has a 1Gbit PHY while
+	 * CSPW0 has a 100Mbit PHY.
+	 *
+	 * On product, CPSW1 maps to port labeled WAN.
+	 */
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	if (!env_get("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+	}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+	writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
+	cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+#endif
+
+	/*
+	 *
+	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
+	 * operating points.  So we must set the TX clock delay feature
+	 * in the AR8051 PHY.  Since we only support a single ethernet
+	 * device in U-Boot, we only do this for the first instance.
+	 */
+#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
+#define AR8051_PHY_DEBUG_DATA_REG	0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
+#define AR8051_RGMII_TX_CLK_DLY		0x100
+	const char *devname;
+	devname = miiphy_get_current_dev();
+
+	miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
+			AR8051_DEBUG_RGMII_CLK_DLY_REG);
+	miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
+			AR8051_RGMII_TX_CLK_DLY);
+#endif
+	return n;
+}
+#endif
diff --git a/roms/u-boot/board/vscom/baltos/board.h b/roms/u-boot/board/vscom/baltos/board.h
new file mode 100644
index 000000000..630c9bba7
--- /dev/null
+++ b/roms/u-boot/board/vscom/baltos/board.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+typedef struct _BSP_VS_HWPARAM    // v1.0
+{
+	uint32_t Magic;
+	uint32_t HwRev;
+	uint32_t SerialNumber;
+	char PrdDate[11];    // as a string ie. "01.01.2006"
+	uint16_t SystemId;
+	uint8_t MAC1[6];        // internal EMAC
+	uint8_t MAC2[6];        // SMSC9514
+	uint8_t MAC3[6];        // WL1271 WLAN
+} __attribute__ ((packed)) BSP_VS_HWPARAM;
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_i2c1_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/roms/u-boot/board/vscom/baltos/mux.c b/roms/u-boot/board/vscom/baltos/mux.c
new file mode 100644
index 000000000..e01899c83
--- /dev/null
+++ b/roms/u-boot/board/vscom/baltos/mux.c
@@ -0,0 +1,118 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+	{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)},	/* I2C_DATA */
+	{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)},	/* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},			/* RGMII1_TCTL */
+	{OFFSET(mii1_txen), MODE(1)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},			/* RGMII1_TCTL */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},			/* RGMII1_TCTL */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux rgmii2_pin_mux[] = {
+	{OFFSET(gpmc_a0), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(gpmc_a1), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(gpmc_a2), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(gpmc_a3), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(gpmc_a4), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(gpmc_a5), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(gpmc_a6), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(gpmc_a7), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(gpmc_a8), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(gpmc_a9), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(gpmc_a10), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(gpmc_a11), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c1_pin_mux(void)
+{
+	configure_module_pin_mux(i2c1_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+	configure_module_pin_mux(i2c1_pin_mux);
+	configure_module_pin_mux(rgmii2_pin_mux);
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+
+#if defined(CONFIG_MTD_RAW_NAND)
+	configure_module_pin_mux(nand_pin_mux);
+#endif
+}
diff --git a/roms/u-boot/board/vscom/baltos/u-boot.lds b/roms/u-boot/board/vscom/baltos/u-boot.lds
new file mode 100644
index 000000000..315ba5b99
--- /dev/null
+++ b/roms/u-boot/board/vscom/baltos/u-boot.lds
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+		board/vscom/baltos/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}
diff --git a/roms/u-boot/board/wandboard/Kconfig b/roms/u-boot/board/wandboard/Kconfig
new file mode 100644
index 000000000..def63696e
--- /dev/null
+++ b/roms/u-boot/board/wandboard/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_WANDBOARD
+
+config SYS_BOARD
+	default "wandboard"
+
+config SYS_CONFIG_NAME
+	default "wandboard"
+
+endif
diff --git a/roms/u-boot/board/wandboard/MAINTAINERS b/roms/u-boot/board/wandboard/MAINTAINERS
new file mode 100644
index 000000000..3c2a06cf0
--- /dev/null
+++ b/roms/u-boot/board/wandboard/MAINTAINERS
@@ -0,0 +1,9 @@
+WANDBOARD BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	arch/arm/dts/imx6qdl-wandboard.dtsi
+F:	arch/arm/dts/imx6qdl-wandboard-revb1.dtsi
+F:	arch/arm/dts/imx6dl-wandboard-revb1.dts
+F:	board/wandboard/
+F:	include/configs/wandboard.h
+F:	configs/wandboard_defconfig
diff --git a/roms/u-boot/board/wandboard/Makefile b/roms/u-boot/board/wandboard/Makefile
new file mode 100644
index 000000000..c3d80536b
--- /dev/null
+++ b/roms/u-boot/board/wandboard/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+
+obj-y  := wandboard.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/roms/u-boot/board/wandboard/README b/roms/u-boot/board/wandboard/README
new file mode 100644
index 000000000..2d514a721
--- /dev/null
+++ b/roms/u-boot/board/wandboard/README
@@ -0,0 +1,49 @@
+U-Boot for Wandboard
+--------------------
+
+This file contains information for the port of U-Boot to the Wandboard.
+
+Wandboard is a development board that has three variants based on the following
+SoCs: mx6 quad, mx6 quad plus, mx6 dual lite and mx6 solo.
+
+For more details about Wandboard, please refer to:
+http://www.wandboard.org/
+
+Building U-Boot for Wandboard
+-----------------------------
+
+To build U-Boot for the Wandboard:
+
+$ make wandboard_config
+$ make
+
+Flashing U-Boot into the SD card
+--------------------------------
+
+- After the 'make' command completes, the generated 'SPL' binary must be
+flashed into the SD card;
+
+$ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+(Note - the SD card node may vary, so adjust this as needed).
+
+- Flash the u-boot.img image into the SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Insert the SD card into the slot located in the bottom of the board (same side
+as the mx6 processor)
+
+- Connect the serial cable to the host PC
+
+- Power up the board and U-Boot messages will appear in the serial console.
+
+Debug UART
+----------
+
+The following settings provide a debug UART for the Wandboard:
+
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_MXC=y
+CONFIG_DEBUG_UART_BASE=0x02020000
+CONFIG_DEBUG_UART_CLOCK=80000000
diff --git a/roms/u-boot/board/wandboard/spl.c b/roms/u-boot/board/wandboard/spl.c
new file mode 100644
index 000000000..0983d1005
--- /dev/null
+++ b/roms/u-boot/board/wandboard/spl.c
@@ -0,0 +1,517 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Wandboard
+ * Author: Tungyi Lin <tungyilin1127@gmail.com>
+ *         Richard Hu <hakahu@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+#include <asm/arch/mx6-ddr.h>
+/*
+ * Driving strength:
+ *   0x30 == 40 Ohm
+ *   0x28 == 48 Ohm
+ */
+
+#define IMX6DQ_DRIVE_STRENGTH		0x30
+#define IMX6SDL_DRIVE_STRENGTH		0x28
+#define IMX6QP_DRIVE_STRENGTH		0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
+	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
+	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6QP mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_cas = IMX6QP_DRIVE_STRENGTH,
+	.dram_ras = IMX6QP_DRIVE_STRENGTH,
+	.dram_reset = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6QP mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6QP_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6QP_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6QP_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
+	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
+	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* H5T04G63AFR-PB */
+static struct mx6_ddr3_cfg h5t04g63afr = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+/* H5TQ2G63DFR-H9 */
+static struct mx6_ddr3_cfg h5tq2g63dfr = {
+	.mem_speed = 1333,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1350,
+	.trcmin = 4950,
+	.trasmin = 3600,
+};
+
+static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x001f001f,
+	.p0_mpwldectrl1 = 0x001f001f,
+	.p1_mpwldectrl0 = 0x001f001f,
+	.p1_mpwldectrl1 = 0x001f001f,
+	.p0_mpdgctrl0 = 0x4301030d,
+	.p0_mpdgctrl1 = 0x03020277,
+	.p1_mpdgctrl0 = 0x4300030a,
+	.p1_mpdgctrl1 = 0x02780248,
+	.p0_mprddlctl = 0x4536393b,
+	.p1_mprddlctl = 0x36353441,
+	.p0_mpwrdlctl = 0x41414743,
+	.p1_mpwrdlctl = 0x462f453f,
+};
+
+/* DDR 64bit 2GB */
+static struct mx6_ddr_sysinfo mem_q = {
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 3,	/* 4 refresh commands per refresh cycle */
+};
+
+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x001f001f,
+	.p0_mpwldectrl1 = 0x001f001f,
+	.p1_mpwldectrl0 = 0x001f001f,
+	.p1_mpwldectrl1 = 0x001f001f,
+	.p0_mpdgctrl0 = 0x420e020e,
+	.p0_mpdgctrl1 = 0x02000200,
+	.p1_mpdgctrl0 = 0x42020202,
+	.p1_mpdgctrl1 = 0x01720172,
+	.p0_mprddlctl = 0x494c4f4c,
+	.p1_mprddlctl = 0x4a4c4c49,
+	.p0_mpwrdlctl = 0x3f3f3133,
+	.p1_mpwrdlctl = 0x39373f2e,
+};
+
+static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x0040003c,
+	.p0_mpwldectrl1 = 0x0032003e,
+	.p0_mpdgctrl0 = 0x42350231,
+	.p0_mpdgctrl1 = 0x021a0218,
+	.p0_mprddlctl = 0x4b4b4e49,
+	.p0_mpwrdlctl = 0x3f3f3035,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 3,	/* 4 refresh commands per refresh cycle */
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+	.dsize		= 1,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 3,	/* 4 refresh commands per refresh cycle */
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF03000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init_imx6qp_lpddr3(void)
+{
+	/* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
+	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
+	/* Calibrations - ZQ */
+	writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
+	/* write leveling */
+	writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
+	writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
+	writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
+	writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
+	/*
+	 * DQS gating, read delay, write delay calibration values
+	 * based on calibration compare of 0x00ffff00
+	 */
+	writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
+	writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
+	writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
+	writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
+	writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
+	writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
+	writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
+	writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
+	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
+	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
+	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
+	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
+	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
+	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
+	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
+	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
+	writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
+	writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
+	writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
+	writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
+	/* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
+	writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
+	writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
+	writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
+	writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
+	writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
+	writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
+	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
+	writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
+	writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
+	writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
+	writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
+	writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
+	/* add NOC DDR configuration */
+	writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
+	writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
+	writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
+	writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
+	writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
+	writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
+	writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
+	writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
+	writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
+	writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
+	writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
+	writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_mx6dqp()) {
+		mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
+		spl_dram_init_imx6qp_lpddr3();
+	} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
+	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
+		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
+	} else if (is_cpu_type(MXC_CPU_MX6Q)) {
+		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+		mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
+	}
+
+	udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* iomux */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
+
+#define USDHC1_CD_GPIO		IMX_GPIO_NR(1, 2)
+#define USDHC3_CD_GPIO		IMX_GPIO_NR(3, 9)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC1_BASE_ADDR},
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* Carrier MicroSD Card Detect */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* SOM MicroSD Card Detect */
+	IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int ret;
+	u32 index = 0;
+
+	/*
+	 * Following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    SOM MicroSD
+	 * mmc1                    Carrier board MicroSD
+	 */
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			usdhc_cfg[0].max_bus_width = 4;
+			gpio_direction_input(USDHC3_CD_GPIO);
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			usdhc_cfg[1].max_bus_width = 4;
+			gpio_direction_input(USDHC1_CD_GPIO);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+			       "(%d) then supported by the board (%d)\n",
+			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/wandboard/wandboard.c b/roms/u-boot/board/wandboard/wandboard.c
new file mode 100644
index 000000000..da995dd0f
--- /dev/null
+++ b/roms/u-boot/board/wandboard/wandboard.c
@@ -0,0 +1,499 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014 O.S. Systems Software LTDA.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <common.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/io.h>
+#include <env.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <phy.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define ETH_PHY_RESET		IMX_GPIO_NR(3, 29)
+#define ETH_PHY_AR8035_POWER	IMX_GPIO_NR(7, 13)
+#define REV_DETECTION		IMX_GPIO_NR(2, 28)
+
+/* Speed defined in Kconfig is only applicable when not using DM_I2C.  */
+#if CONFIG_IS_ENABLED(DM_I2C)
+#define I2C1_SPEED_NON_DM	0
+#define I2C2_SPEED_NON_DM	0
+#else
+#define I2C1_SPEED_NON_DM	CONFIG_SYS_MXC_I2C1_SPEED
+#define I2C2_SPEED_NON_DM	CONFIG_SYS_MXC_I2C2_SPEED
+#endif
+
+static bool with_pmic;
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	/* AR8031 PHY Reset */
+	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
+	/* AR8035 POWER */
+	IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const rev_detection_pad[] = {
+	IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+static void setup_iomux_enet(void)
+{
+	SETUP_IOMUX_PADS(enet_pads);
+
+	if (with_pmic) {
+		SETUP_IOMUX_PADS(enet_ar8035_power_pads);
+		/* enable AR8035 POWER */
+		gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
+		gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
+	}
+	/* wait until 3.3V of PHY and clock become stable */
+	mdelay(10);
+
+	/* Reset AR8031 PHY */
+	gpio_request(ETH_PHY_RESET, "PHY_RESET");
+	gpio_direction_output(ETH_PHY_RESET, 0);
+	mdelay(10);
+	gpio_set_value(ETH_PHY_RESET, 1);
+	udelay(100);
+}
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+	int mask;
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	if (with_pmic)
+		mask = 0xffe7;	/* AR8035 */
+	else
+		mask = 0xffe3;	/* AR8031 */
+
+	val &= mask;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8031_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+struct i2c_pads_info mx6q_i2c2_pad_info = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+struct i2c_pads_info mx6dl_i2c2_pad_info = {
+	.scl = {
+		.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+struct i2c_pads_info mx6q_i2c3_pad_info = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(1, 5)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(7, 11)
+	}
+};
+
+struct i2c_pads_info mx6dl_i2c3_pad_info = {
+	.scl = {
+		.i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(1, 5)
+	},
+	.sda = {
+		.i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(7, 11)
+	}
+};
+
+static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
+	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
+	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
+	IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04	| MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
+	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
+	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
+	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
+	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
+	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
+	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
+	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
+	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
+	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
+	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
+	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
+	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
+	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
+	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
+	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
+	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
+	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
+	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
+	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
+	IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+#if CONFIG_IS_ENABLED(DM_I2C)
+	struct udevice *bus, *udev;
+	int rc;
+
+	rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
+	if (rc)
+		return rc;
+	rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
+	if (rc)
+		return 0;
+	return 1;
+#else
+	return (0 == i2c_set_bus_num(dev->bus)) &&
+			(0 == i2c_probe(dev->addr));
+#endif
+}
+
+static void enable_fwadapt_7wvga(struct display_info_t const *dev)
+{
+	SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
+
+	gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
+	gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
+	gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
+	gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 1,
+	.addr	= 0x10,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= detect_i2c,
+	.enable	= enable_fwadapt_7wvga,
+	.mode	= {
+		.name           = "FWBADAPT-LCD-F07A-0102",
+		.refresh        = 60,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 33260,
+		.left_margin    = 128,
+		.right_margin   = 128,
+		.upper_margin   = 22,
+		.lower_margin   = 22,
+		.hsync_len      = 1,
+		.vsync_len      = 1,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	/* Disable LCD backlight */
+	SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
+	gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
+	gpio_direction_input(IMX_GPIO_NR(4, 20));
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+#ifdef CONFIG_SATA
+	setup_sata();
+#endif
+
+	return 0;
+}
+
+#define PMIC_I2C_BUS		2
+
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int reg, ret;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret < 0) {
+		debug("pmic_get() ret %d\n", ret);
+		return 0;
+	}
+
+	reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	if (reg < 0) {
+		debug("pmic_reg_read() ret %d\n", reg);
+		return 0;
+	}
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+	with_pmic = true;
+
+	/* Set VGEN2 to 1.5V and enable */
+	reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
+	reg &= ~(LDO_VOL_MASK);
+	reg |= (LDOA_1_50V | (1 << (LDO_EN)));
+	pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",	  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{"mmc1",	  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+static bool is_revc1(void)
+{
+	SETUP_IOMUX_PADS(rev_detection_pad);
+	gpio_request(REV_DETECTION, "REV_DETECT");
+	gpio_direction_input(REV_DETECTION);
+
+	if (gpio_get_value(REV_DETECTION))
+		return true;
+	else
+		return false;
+}
+
+static bool is_revd1(void)
+{
+	if (with_pmic)
+		return true;
+	else
+		return false;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (is_mx6dqp())
+		env_set("board_rev", "MX6QP");
+	else if (is_mx6dq())
+		env_set("board_rev", "MX6Q");
+	else
+		env_set("board_rev", "MX6DL");
+
+	if (is_revd1())
+		env_set("board_name", "D1");
+	else if (is_revc1())
+		env_set("board_name", "C1");
+	else
+		env_set("board_name", "B1");
+#endif
+	setup_iomux_enet();
+
+	if (is_revd1())
+		puts("Board: Wandboard rev D1\n");
+	else if (is_revc1())
+		puts("Board: Wandboard rev C1\n");
+	else
+		puts("Board: Wandboard rev B1\n");
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
+	if (is_mx6dq() || is_mx6dqp()) {
+		setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
+		setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
+	} else {
+		setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
+		setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
+	}
+
+	setup_display();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_mx6dq()) {
+		if (!strcmp(name, "imx6q-wandboard-revd1"))
+			return 0;
+	} else if (is_mx6dqp()) {
+		if (!strcmp(name, "imx6qp-wandboard-revd1"))
+			return 0;
+	} else if (is_mx6dl() || is_mx6solo()) {
+		if (!strcmp(name, "imx6dl-wandboard-revd1"))
+			return 0;
+	}
+
+	return -EINVAL;
+}
+#endif
diff --git a/roms/u-boot/board/warp/Kconfig b/roms/u-boot/board/warp/Kconfig
new file mode 100644
index 000000000..dc0263631
--- /dev/null
+++ b/roms/u-boot/board/warp/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_WARP
+
+config SYS_BOARD
+	default "warp"
+
+config SYS_CONFIG_NAME
+	default "warp"
+
+endif
diff --git a/roms/u-boot/board/warp/MAINTAINERS b/roms/u-boot/board/warp/MAINTAINERS
new file mode 100644
index 000000000..ee2114d08
--- /dev/null
+++ b/roms/u-boot/board/warp/MAINTAINERS
@@ -0,0 +1,6 @@
+WaRP BOARD
+M:	Otavio Salvador <otavio@ossystems.com.br>
+S:	Maintained
+F:	board/warp/
+F:	include/configs/warp.h
+F:	configs/warp_defconfig
diff --git a/roms/u-boot/board/warp/Makefile b/roms/u-boot/board/warp/Makefile
new file mode 100644
index 000000000..3a2373d7b
--- /dev/null
+++ b/roms/u-boot/board/warp/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2014 O.S. Systems Software LTDA.
+# Copyright (C) 2014 Kynetics LLC.
+# Copyright (C) 2014 Revolution Robotics, Inc.
+
+obj-y  := warp.o
diff --git a/roms/u-boot/board/warp/README b/roms/u-boot/board/warp/README
new file mode 100644
index 000000000..3cfd22ec7
--- /dev/null
+++ b/roms/u-boot/board/warp/README
@@ -0,0 +1,56 @@
+How to Update U-Boot on Warp board
+----------------------------------
+
+Required software on the host PC:
+
+- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
+
+- dfu-util: http://dfu-util.sourceforge.net/releases/
+
+Build U-Boot for Warp:
+
+$ make mrproper
+$ make warp_config
+$ make
+
+This will generate the U-Boot binary called u-boot.imx.
+
+Put warp board in USB download mode
+
+Connect a USB to serial adapter between the host PC and warp
+
+Connect a USB cable between the OTG warp port and the host PC
+
+Open a terminal program such as minicom
+
+Copy u-boot.imx to the imx_usb_loader folder.
+
+Load u-boot.imx via USB:
+
+$ sudo ./imx_usb u-boot.imx
+
+Then U-Boot should start and its messages will appear in the console program.
+
+Use the default environment variables:
+
+=> env default -f -a
+=> saveenv
+
+Run the DFU command:
+=> dfu 0 mmc 0
+
+Transfer u-boot.imx that will be flashed into the eMMC:
+
+$ sudo dfu-util -D u-boot.imx -a boot
+
+Then on the U-Boot prompt the following message should be seen after a
+successful upgrade:
+
+#DOWNLOAD ... OK
+Ctrl+C to exit ...
+
+Remove power from the warp board.
+
+Put warp board into normal boot mode
+
+Power up the board and the new updated U-Boot should boot from eMMC
diff --git a/roms/u-boot/board/warp/imximage.cfg b/roms/u-boot/board/warp/imximage.cfg
new file mode 100644
index 000000000..619f6aa7b
--- /dev/null
+++ b/roms/u-boot/board/warp/imximage.cfg
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG__IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x020c4018 0x00260324
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020e0344 0x00003030
+DATA 4 0x020e0348 0x00003030
+DATA 4 0x020e034c 0x00003030
+DATA 4 0x020e0350 0x00003030
+DATA 4 0x020e030c 0x00000030
+DATA 4 0x020e0310 0x00000030
+DATA 4 0x020e0314 0x00000030
+DATA 4 0x020e0318 0x00000030
+DATA 4 0x020e0300 0x00000030
+DATA 4 0x020e031c 0x00000030
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e0320 0x00000030
+DATA 4 0x020e032c 0x00000000
+DATA 4 0x020e033c 0x00000008
+DATA 4 0x020e0340 0x00000008
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x020e05cc 0x00000030
+DATA 4 0x020e05d4 0x00000030
+DATA 4 0x020e05d8 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05c8 0x00000030
+DATA 4 0x020e05b0 0x00020000
+DATA 4 0x020e05b4 0x00000000
+DATA 4 0x020e05c0 0x00020000
+DATA 4 0x020e05d0 0x00080000
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b085c 0x1b4700c7
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b0890 0x00400000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b0834 0xf3333333
+DATA 4 0x021b0838 0xf3333333
+DATA 4 0x021b0848 0x4241444a
+DATA 4 0x021b0850 0x3030312b
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x00000000
+DATA 4 0x021b08c0 0x24911492
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b000c 0x33374133
+DATA 4 0x021b0004 0x00020024
+DATA 4 0x021b0010 0x00100A82
+DATA 4 0x021b0014 0x00000093
+DATA 4 0x021b0018 0x00001688
+DATA 4 0x021b002c 0x0f9f26d2
+DATA 4 0x021b0030 0x009f0e10
+DATA 4 0x021b0038 0x00190778
+DATA 4 0x021b0008 0x00000000
+DATA 4 0x021b0040 0x0000004f
+DATA 4 0x021b0000 0x83110000
+DATA 4 0x021b001c 0x003f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0x82018030
+DATA 4 0x021b001c 0x04028030
+DATA 4 0x021b001c 0x02038030
+DATA 4 0x021b001c 0xff0a8038
+DATA 4 0x021b001c 0x82018038
+DATA 4 0x021b001c 0x04028038
+DATA 4 0x021b001c 0x02038038
+DATA 4 0x021b0800 0xa1310003
+DATA 4 0x021b0020 0x00001800
+DATA 4 0x021b0818 0x00000000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b0004 0x00025564
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
diff --git a/roms/u-boot/board/warp/warp.c b/roms/u-boot/board/warp/warp.c
new file mode 100644
index 000000000..c03b64885
--- /dev/null
+++ b/roms/u-boot/board/warp/warp.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014, 2015 O.S. Systems Software LTDA.
+ * Copyright (C) 2014 Kynetics LLC.
+ * Copyright (C) 2014 Revolution Robotics, Inc.
+ *
+ * Author: Otavio Salvador <otavio@ossystems.com.br>
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <watchdog.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <usb.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS | \
+	PAD_CTL_LVE)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS | \
+	PAD_CTL_LVE)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+		      PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
+		      PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
+		      PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define CONFIG_POWER_MAX77696_I2C_ADDR	0x3C
+
+enum {
+	L01_CNFG1 =	0x43,
+	L01_CNFG2,
+	L02_CNFG1,
+	L02_CNFG2,
+	L03_CNFG1,
+	L03_CNFG2,
+	L04_CNFG1,
+	L04_CNFG2,
+	L05_CNFG1,
+	L05_CNFG2,
+	L06_CNFG1,
+	L06_CNFG2,
+	L07_CNFG1,
+	L07_CNFG2,
+	L08_CNFG1,
+	L08_CNFG2,
+	L09_CNFG1,
+	L09_CNFG2,
+	L10_CNFG1,
+	L10_CNFG2,
+	LDO_INT1,
+	LDO_INT2,
+	LDO_INT1M,
+	LDO_INT2M,
+	LDO_CNFG3,
+	SW1_CNTRL,
+	SW2_CNTRL,
+	SW3_CNTRL,
+	SW4_CNTRL,
+	EPDCNFG,
+	EPDINTS,
+	EPDINT,
+	EPDINTM,
+	EPDVCOM,
+	EPDVEE,
+	EPDVNEG,
+	EPDVPOS,
+	EPDVDDH,
+	EPDSEQ,
+	EPDOKINTS,
+	CID =	0x9c,
+	PMIC_NUM_OF_REGS,
+};
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	static iomux_v3_cfg_t const uart1_pads[] = {
+		MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+		MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC2_BASE_ADDR, 0, 0, 0, 1},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;	/* Assume boot SD always present */
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	static iomux_v3_cfg_t const usdhc2_pads[] = {
+		MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_RST__USDHC2_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+		MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+int board_usb_phy_mode(int port)
+{
+	return USB_INIT_DEVICE;
+}
+
+/* I2C1 for PMIC */
+#define I2C_PMIC	0
+#define PC	MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.sda = {
+		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
+		.gp = IMX_GPIO_NR(3, 13),
+	},
+	.scl = {
+		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
+		.gp = IMX_GPIO_NR(3, 12),
+	},
+};
+
+static int power_max77696_init(unsigned char bus)
+{
+	static const char name[] = "MAX77696";
+	struct pmic *p = pmic_alloc();
+
+	if (!p) {
+		printf("%s: POWER allocation error!\n", __func__);
+		return -ENOMEM;
+	}
+
+	p->name = name;
+	p->interface = PMIC_I2C;
+	p->number_of_regs = PMIC_NUM_OF_REGS;
+	p->hw.i2c.addr = CONFIG_POWER_MAX77696_I2C_ADDR;
+	p->hw.i2c.tx_num = 1;
+	p->bus = bus;
+
+	return 0;
+}
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_max77696_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("MAX77696");
+	if (!p)
+		return -EINVAL;
+
+	ret = pmic_reg_read(p, CID, &reg);
+	if (ret)
+		return ret;
+
+	printf("PMIC:  MAX77696 detected, rev=0x%x\n", reg);
+
+	return pmic_probe(p);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+	hw_watchdog_init();
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: WaRP Board\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/warp7/Kconfig b/roms/u-boot/board/warp7/Kconfig
new file mode 100644
index 000000000..c089bca2b
--- /dev/null
+++ b/roms/u-boot/board/warp7/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_WARP7
+
+config SYS_BOARD
+	default "warp7"
+
+config SYS_CONFIG_NAME
+	default "warp7"
+
+config WARP7_ROOT_PART
+	int "Partition number to use for root filesystem"
+	default 2
+	help
+	  The partition number to use for root filesystem this is the
+	  partition that is typically specified with root=/dev/sdaX or
+	  which gets converted into a root=PARTUUID=some_uuid.
+
+config SYS_FDT_ADDR
+	hex "FDT load address"
+	default 0x83000000
+	help
+	  The address the FDT file should be loaded to.
+
+endif
diff --git a/roms/u-boot/board/warp7/MAINTAINERS b/roms/u-boot/board/warp7/MAINTAINERS
new file mode 100644
index 000000000..ebb21f81a
--- /dev/null
+++ b/roms/u-boot/board/warp7/MAINTAINERS
@@ -0,0 +1,7 @@
+WARP7 BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/warp7/
+F:	include/configs/warp7.h
+F:	configs/warp7_defconfig
+F:	configs/warp7_bl33_defconfig
diff --git a/roms/u-boot/board/warp7/Makefile b/roms/u-boot/board/warp7/Makefile
new file mode 100644
index 000000000..92b0ca906
--- /dev/null
+++ b/roms/u-boot/board/warp7/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2016 NXP Semiconductors
+
+obj-y  := warp7.o
diff --git a/roms/u-boot/board/warp7/README b/roms/u-boot/board/warp7/README
new file mode 100644
index 000000000..579bb2de3
--- /dev/null
+++ b/roms/u-boot/board/warp7/README
@@ -0,0 +1,63 @@
+How to Update U-Boot on Warp7 board
+----------------------------------
+
+Required software on the host PC:
+
+- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
+
+- dfu-util: http://dfu-util.sourceforge.net/releases/ (if you are in a
+Debian distribution then you can get it via libdfu-dev package)
+
+- libusb: http://libusb.org/ (if you are in a Debian distribution
+then you can get it via libusb-dev and libusb-1.0-0-dev)
+
+In U-Boot folder, build U-Boot for Warp7:
+
+$ make mrproper
+$ make warp7_config
+$ make
+
+This will generate the U-Boot binary called u-boot-dtb.imx.
+
+Put warp7 board in USB download mode: 
+
+Remove the CPU board from the base board then put switch 2 in the upper
+position
+
+Connect a USB to serial adapter between the host PC and warp7
+
+Connect a USB cable between the OTG warp7 port and the host PC
+
+Copy u-boot-dtb.imx to the imx_usb_loader folder.
+
+Load u-boot-dtb.imx via USB:
+
+$ sudo ./imx_usb u-boot-dtb.imx
+
+Then U-Boot should start and its messages will appear in the console program.
+
+Open a terminal program such as minicom
+
+Use the default environment variables:
+
+=> env default -f -a
+=> saveenv
+
+Run the DFU command:
+=> dfu 0 mmc 0
+
+Transfer u-boot-dtb.imx that will be flashed into the eMMC:
+
+$ sudo dfu-util -D u-boot-dtb.imx -a boot
+
+Then on the U-Boot prompt the following message should be seen after a
+successful upgrade:
+
+#DOWNLOAD ... OK
+Ctrl+C to exit ...
+
+Remove power from the warp7 board.
+
+Put warp7 board into normal boot mode (put the switch 2 in the lower position)
+
+Power up the board and the new updated U-Boot should boot from eMMC
diff --git a/roms/u-boot/board/warp7/imximage.cfg b/roms/u-boot/board/warp7/imximage.cfg
new file mode 100644
index 000000000..9e7d4725e
--- /dev/null
+++ b/roms/u-boot/board/warp7/imximage.cfg
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+IMAGE_VERSION	2
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03040008
+DATA 4 0x307a0064 0x00200038
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00350001
+DATA 4 0x307a00dc 0x00c3000a
+DATA 4 0x307a00e0 0x00010000
+DATA 4 0x307a00e4 0x00110006
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x0a0e110b
+DATA 4 0x307a0104 0x00020211
+DATA 4 0x307a0108 0x03060708
+DATA 4 0x307a010c 0x00a0500c
+DATA 4 0x307a0110 0x05020307
+DATA 4 0x307a0114 0x02020404
+DATA 4 0x307a0118 0x02020003
+DATA 4 0x307a011c 0x00000202
+DATA 4 0x307a0120 0x00000202
+
+DATA 4 0x307a0180 0x00600018
+DATA 4 0x307a0184 0x00e00100
+DATA 4 0x307a0190 0x02098205
+DATA 4 0x307a0194 0x00060303
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+
+DATA 4 0x307a0200 0x00000015
+DATA 4 0x307a0204 0x00161616
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x04040404
+DATA 4 0x307a0218 0x0f0f0404
+
+DATA 4 0x307a0240 0x06000600
+DATA 4 0x307a0244 0x00000000
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17421e40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790008 0x00010000
+DATA 4 0x30790010 0x0007080c
+DATA 4 0x307900b0 0x1010007e
+
+DATA 4 0x3079001C 0x01010000
+DATA 4 0x3079009c 0x00000d6e
+
+DATA 4 0x30790030 0x06060606
+DATA 4 0x30790020 0x0a0a0a0a
+DATA 4 0x30790050 0x01000008
+DATA 4 0x30790050 0x00000008
+DATA 4 0x30790018 0x0000000f
+DATA 4 0x307900c0 0x0e487304
+DATA 4 0x307900c0 0x0e4c7304
+DATA 4 0x307900c0 0x0e4c7306
+DATA 4 0x307900c0 0x0e4c7304
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e487304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+
+CHECK_BITS_SET 4 0x307a0004 0x1
diff --git a/roms/u-boot/board/warp7/warp7.c b/roms/u-boot/board/warp7/warp7.c
new file mode 100644
index 000000000..0f202241d
--- /dev/null
+++ b/roms/u-boot/board/warp7/warp7.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ * Author: Fabio Estevam <fabio.estevam@nxp.com>
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/hab.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env.h>
+#include <asm/arch/crm_regs.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../freescale/common/pfuze.h"
+#include <asm/setup.h>
+#include <asm/bootm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
+			PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	/* Subtract the defined OPTEE runtime firmware length */
+#ifdef CONFIG_OPTEE_TZDRAM_SIZE
+		gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
+#endif
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+};
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret, dev_id, rev_id;
+
+	ret = pmic_get("pfuze3000@8", &dev);
+	if (ret == -ENODEV)
+		return 0;
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	pmic_reg_write(dev, PFUZE3000_LDOGCTL, 1);
+
+	return 0;
+}
+#endif
+
+int board_eth_init(struct bd_info *bis)
+{
+	int ret = 0;
+
+#ifdef CONFIG_USB_ETHER
+	ret = usb_eth_initialize(bis);
+	if (ret < 0)
+		printf("Error %d registering USB ether.\n", ret);
+#endif
+
+	return ret;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *mode;
+
+	if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
+		mode = "secure";
+	else
+		mode = "non-secure";
+
+#ifdef CONFIG_OPTEE_TZDRAM_SIZE
+	unsigned long optee_start, optee_end;
+
+	optee_end = PHYS_SDRAM + PHYS_SDRAM_SIZE;
+	optee_start = optee_end - CONFIG_OPTEE_TZDRAM_SIZE;
+
+	printf("Board: WARP7 in %s mode OPTEE DRAM 0x%08lx-0x%08lx\n",
+	       mode, optee_start, optee_end);
+#else
+	printf("Board: WARP7 in %s mode\n", mode);
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+#ifdef CONFIG_SERIAL_TAG
+	struct tag_serialnr serialnr;
+	char serial_string[0x20];
+#endif
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	/*
+	 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+	 * since we use PMIC_PWRON to reset the board.
+	 */
+	clrsetbits_le16(&wdog->wcr, 0, 0x10);
+
+#ifdef CONFIG_IMX_HAB
+	/* Determine HAB state */
+	env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled());
+#else
+	env_set_ulong(HAB_ENABLED_ENVNAME, 0);
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+	/* Set serial# standard environment variable based on OTP settings */
+	get_board_serial(&serialnr);
+	snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
+		 serialnr.low, serialnr.high);
+	env_set("serial#", serial_string);
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/board/work-microwave/work_92105/Kconfig b/roms/u-boot/board/work-microwave/work_92105/Kconfig
new file mode 100644
index 000000000..380e2dfc2
--- /dev/null
+++ b/roms/u-boot/board/work-microwave/work_92105/Kconfig
@@ -0,0 +1,24 @@
+if TARGET_WORK_92105
+
+config SYS_BOARD
+	default "work_92105"
+
+config SYS_VENDOR
+	default "work-microwave"
+
+config SYS_CONFIG_NAME
+	default "work_92105"
+
+config CMD_HD44760
+	bool "Enable 'hd44780' LCD-control command"
+	help
+	  This controls the LCD driver.
+
+config CMD_MAX6957
+	bool "Enable 'max6957aax' PMIC command"
+	help
+	  DEPRECATED: Needs conversion to driver model.
+
+	  This allows PMIC registers to be read and written.
+
+endif
diff --git a/roms/u-boot/board/work-microwave/work_92105/MAINTAINERS b/roms/u-boot/board/work-microwave/work_92105/MAINTAINERS
new file mode 100644
index 000000000..29a92c5ff
--- /dev/null
+++ b/roms/u-boot/board/work-microwave/work_92105/MAINTAINERS
@@ -0,0 +1,6 @@
+WORK_92105 BOARD
+M:	Albert ARIBAUD <albert.aribaud@3adev.fr>
+S:	Maintained
+F:	board/work-microwave/work_92105/
+F:	include/configs/work_92105.h
+F:	configs/work_92105_defconfig
diff --git a/roms/u-boot/board/work-microwave/work_92105/Makefile b/roms/u-boot/board/work-microwave/work_92105/Makefile
new file mode 100644
index 000000000..b837e7b0d
--- /dev/null
+++ b/roms/u-boot/board/work-microwave/work_92105/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2014  DENX Software Engineering GmbH
+# Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= work_92105_spl.o
+else
+obj-y	+= work_92105.o
+obj-$(CONFIG_DEPRECATED) += work_92105_display.o
+endif
diff --git a/roms/u-boot/board/work-microwave/work_92105/README b/roms/u-boot/board/work-microwave/work_92105/README
new file mode 100644
index 000000000..3c256e0b2
--- /dev/null
+++ b/roms/u-boot/board/work-microwave/work_92105/README
@@ -0,0 +1,91 @@
+Work_92105 from Work Microwave is an LPC3250- based board with the
+following features:
+
+    - 64MB SDR DRAM
+    - 1 GB SLC NAND, managed through MLC controller.
+    - Ethernet
+    - Ethernet + PHY SMSC8710
+    - I2C:
+      - EEPROM (24M01-compatible)
+      - RTC (DS1374-compatible)
+      - Temperature sensor (DS620)
+      - DACs (2 x MAX518)
+    - SPI (through SSP interface)
+      - Port expander MAX6957
+    - LCD display (HD44780-compatible), controlled
+      through the port expander and DACs
+
+Standard SPL and U-Boot binaries
+--------------------------------
+
+The default 'make' (or the 'make all') command will produce the
+following files:
+
+1. spl/u-boot-spl.bin	SPL, intended to run from SRAM at address 0.
+			This file can be loaded in SRAM through a JTAG
+			debugger or through the LPC32XX Service Boot
+			mechanism.
+
+2. u-boot.bin		The raw U-Boot image, which can be loaded in
+			DDR through a JTAG debugger (for instance by
+			breaking SPL after DDR init), or by a running
+			U-Boot through e.g. 'loady' or 'tftp' and then
+			executed with 'go'.
+
+3. u-boot.img		A U-Boot image with a mkimage header prepended.
+			SPL assumes (even when loaded through JTAG or
+			Service Boot) that such an image will be found
+			at offset 0x00040000 in NAND.
+
+NAND cold-boot binaries
+-----------------------
+
+The board can boot entirely from power-on with only SPL and U-Boot in
+NAND. The LPC32XX-specific 'make lpc32xx-full.bin' command will produce
+(in addition to spl/u-boot-spl.bin and u-boot.img if they were not made
+already) the following files:
+
+4. lpc32xx-spl.img	spl/u-boot-spl.bin, with a LPC32XX boot header
+			prepended. This header is required for the ROM
+			code to load SPL into SRAM and branch into it.
+			The content of this file is expected to reside
+			in NAND at addresses 0x00000000 and 0x00020000
+			(two copies).
+
+5. lpc32xx-boot-0.bin	lpc32xx-spl.img, padded with 0xFF bytes to a
+			size of 0x20000 bytes. This file covers exactly
+			the reserved area for the first bootloader copy
+			in NAND.
+
+6. lpc32xx-boot-1.bin	Same as lpc32xx-boot-0.bin. This is intended to
+			be used as the second bootloader copy.
+
+7. lpc32xx-full.bin	lpc32xx-boot-0.bin, lpc32xx-boot-1.bin and
+			u-boot.img concatenated. This file represents
+			the content of whole bootloader as present in
+			NAND at offset 00x00000000.
+
+Flashing instructions
+---------------------
+
+The following assumes a working U-Boot on the target, with the ability
+to load files into DDR.
+
+To update the whole bootloader:
+
+	nand erase 0x00000000 0x80000
+	(load lpc32xx-full.bin at location $loadaddr)
+	nand write $loadaddr 0x00000000 $filesize
+
+To update SPL only (note the double nand write) :
+
+	nand erase 0x00000000 0x40000
+	(load lpc32xx-spl.img or lpc32xx-boot-N.bin at location $loadaddr)
+	nand write $loadaddr 0x00000000 $filesize
+	nand write $loadaddr 0x00020000 $filesize
+
+To update U-Boot only:
+
+	nand erase 0x00040000 0x40000
+	(load u-boot.img at location $loadaddr)
+	nand write $loadaddr 0x00040000 $filesize
diff --git a/roms/u-boot/board/work-microwave/work_92105/work_92105.c b/roms/u-boot/board/work-microwave/work_92105/work_92105.c
new file mode 100644
index 000000000..bdcecff73
--- /dev/null
+++ b/roms/u-boot/board/work-microwave/work_92105/work_92105.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * WORK Microwave work_92105 board support
+ *
+ * (C) Copyright 2014  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/emc.h>
+#include <asm/arch/wdt.h>
+#include <asm/gpio.h>
+#include <spl.h>
+#include <linux/delay.h>
+#include "work_92105_display.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct wdt_regs  *wdt = (struct wdt_regs *)WDT_BASE;
+
+void reset_periph(void)
+{
+	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+	writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
+	udelay(150);
+	writel(0, &wdt->mctrl);
+	clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+}
+
+int board_early_init_f(void)
+{
+	/* initialize serial port for console */
+	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+	/* enable I2C, SSP, MAC, NAND */
+	lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */
+	lpc32xx_ssp_init();
+	lpc32xx_mac_init();
+	lpc32xx_mlc_nand_init();
+	/* Display must wait until after relocation and devices init */
+	return 0;
+}
+
+#define GPO_19 115
+
+int board_early_init_r(void)
+{
+	/* Set NAND !WP to 1 through GPO_19 */
+	gpio_request(GPO_19, "NAND_nWP");
+	gpio_direction_output(GPO_19, 1);
+
+#ifdef CONFIG_DEPRECATED
+	/* initialize display */
+	work_92105_display_init();
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	reset_periph();
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params  = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/work-microwave/work_92105/work_92105_display.c b/roms/u-boot/board/work-microwave/work_92105/work_92105_display.c
new file mode 100644
index 000000000..fecbbbdb5
--- /dev/null
+++ b/roms/u-boot/board/work-microwave/work_92105/work_92105_display.c
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * work_92105 display support
+ *
+ * (C) Copyright 2014  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * The work_92105 display is a HD44780-compatible module
+ * controlled through a MAX6957AAX SPI port expander, two
+ * MAX518 I2C DACs and native LPC32xx GPO 15.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <log.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/emc.h>
+#include <asm/gpio.h>
+#include <env.h>
+#include <spi.h>
+#include <i2c.h>
+#include <version.h>
+#include <vsprintf.h>
+#include <linux/delay.h>
+
+/*
+ * GPO 15 in port 3 is gpio 3*32+15 = 111
+ */
+
+#define GPO_15 111
+
+/**
+ * MAX6957AAX registers that we will be using
+ */
+
+#define MAX6957_CONF		0x04
+
+#define MAX6957_CONF_08_11	0x0A
+#define MAX6957_CONF_12_15	0x0B
+#define MAX6957_CONF_16_19	0x0C
+
+/**
+ * Individual gpio ports (one per gpio) to HD44780
+ */
+
+#define MAX6957AAX_HD44780_RS	0x29
+#define MAX6957AAX_HD44780_R_W	0x2A
+#define MAX6957AAX_HD44780_EN	0x2B
+#define MAX6957AAX_HD44780_DATA	0x4C
+
+/**
+ * Display controller instructions
+ */
+
+/* Function set: eight bits, two lines, 8-dot font */
+#define HD44780_FUNCTION_SET		0x38
+
+/* Display ON / OFF: turn display on */
+#define HD44780_DISPLAY_ON_OFF_CONTROL	0x0C
+
+/* Entry mode: increment */
+#define HD44780_ENTRY_MODE_SET		0x06
+
+/* Clear */
+#define HD44780_CLEAR_DISPLAY		0x01
+
+/* Set DDRAM addr (to be ORed with exact address) */
+#define HD44780_SET_DDRAM_ADDR		0x80
+
+/* Set CGRAM addr (to be ORed with exact address) */
+#define HD44780_SET_CGRAM_ADDR		0x40
+
+/**
+ * Default value for contrats
+ */
+
+#define CONTRAST_DEFAULT  25
+
+/**
+ * Define slave as a module-wide local to save passing it around,
+ * plus we will need it after init for the "hd44780" command.
+ */
+
+static struct spi_slave *slave;
+
+/*
+ * Write a value into a MAX6957AAX register.
+ */
+
+static void max6957aax_write(uint8_t reg, uint8_t value)
+{
+	uint8_t dout[2];
+
+	dout[0] = reg;
+	dout[1] = value;
+	gpio_set_value(GPO_15, 0);
+	/* do SPI read/write (passing din==dout is OK) */
+	spi_xfer(slave, 16, dout, dout, SPI_XFER_BEGIN | SPI_XFER_END);
+	gpio_set_value(GPO_15, 1);
+}
+
+/*
+ * Read a value from a MAX6957AAX register.
+ *
+ * According to the MAX6957AAX datasheet, we should release the chip
+ * select halfway through the read sequence, when the actual register
+ * value is read; but the WORK_92105 hardware prevents the MAX6957AAX
+ * SPI OUT from reaching the LPC32XX SIP MISO if chip is not selected.
+ * so let's release the CS an hold it again while reading the result.
+ */
+
+static uint8_t max6957aax_read(uint8_t reg)
+{
+	uint8_t dout[2], din[2];
+
+	/* send read command */
+	dout[0] = reg | 0x80; /* set bit 7 to indicate read */
+	dout[1] = 0;
+	gpio_set_value(GPO_15, 0);
+	/* do SPI read/write (passing din==dout is OK) */
+	spi_xfer(slave, 16, dout, dout, SPI_XFER_BEGIN | SPI_XFER_END);
+	/* latch read command */
+	gpio_set_value(GPO_15, 1);
+	/* read register -- din = noop on xmit, din[1] = reg on recv */
+	din[0] = 0;
+	din[1] = 0;
+	gpio_set_value(GPO_15, 0);
+	/* do SPI read/write (passing din==dout is OK) */
+	spi_xfer(slave, 16, din, din, SPI_XFER_BEGIN | SPI_XFER_END);
+	/* end of read. */
+	gpio_set_value(GPO_15, 1);
+	return din[1];
+}
+
+static void hd44780_instruction(unsigned long instruction)
+{
+	max6957aax_write(MAX6957AAX_HD44780_RS, 0);
+	max6957aax_write(MAX6957AAX_HD44780_R_W, 0);
+	max6957aax_write(MAX6957AAX_HD44780_EN, 1);
+	max6957aax_write(MAX6957AAX_HD44780_DATA, instruction);
+	max6957aax_write(MAX6957AAX_HD44780_EN, 0);
+	/* HD44780 takes 37 us for most instructions, 1520 for clear */
+	if (instruction == HD44780_CLEAR_DISPLAY)
+		udelay(2000);
+	else
+		udelay(100);
+}
+
+static void hd44780_write_char(char c)
+{
+	max6957aax_write(MAX6957AAX_HD44780_RS, 1);
+	max6957aax_write(MAX6957AAX_HD44780_R_W, 0);
+	max6957aax_write(MAX6957AAX_HD44780_EN, 1);
+	max6957aax_write(MAX6957AAX_HD44780_DATA, c);
+	max6957aax_write(MAX6957AAX_HD44780_EN, 0);
+	/* HD44780 takes 37 us to write to DDRAM or CGRAM */
+	udelay(100);
+}
+
+static void hd44780_write_str(char *s)
+{
+	max6957aax_write(MAX6957AAX_HD44780_RS, 1);
+	max6957aax_write(MAX6957AAX_HD44780_R_W, 0);
+	while (*s) {
+		max6957aax_write(MAX6957AAX_HD44780_EN, 1);
+		max6957aax_write(MAX6957AAX_HD44780_DATA, *s);
+		max6957aax_write(MAX6957AAX_HD44780_EN, 0);
+		s++;
+		/* HD44780 takes 37 us to write to DDRAM or CGRAM */
+		udelay(100);
+	}
+}
+
+/*
+ * Existing user code might expect these custom characters to be
+ * recognized and displayed on the LCD
+ */
+
+static u8 char_gen_chars[] = {
+	/* #8, empty rectangle */
+	0x1F, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x1F,
+	/* #9, filled right arrow */
+	0x10, 0x18, 0x1C, 0x1E, 0x1C, 0x18, 0x10, 0x00,
+	/* #10, filled left arrow */
+	0x01, 0x03, 0x07, 0x0F, 0x07, 0x03, 0x01, 0x00,
+	/* #11, up and down arrow */
+	0x04, 0x0E, 0x1F, 0x00, 0x00, 0x1F, 0x0E, 0x04,
+	/* #12, plus/minus */
+	0x04, 0x04, 0x1F, 0x04, 0x04, 0x00, 0x1F, 0x00,
+	/* #13, fat exclamation mark */
+	0x06, 0x06, 0x06, 0x06, 0x00, 0x06, 0x06, 0x00,
+	/* #14, empty square */
+	0x00, 0x1F, 0x11, 0x11, 0x11, 0x1F, 0x00, 0x00,
+	/* #15, struck out square */
+	0x00, 0x1F, 0x19, 0x15, 0x13, 0x1F, 0x00, 0x00,
+};
+
+static void hd44780_init_char_gen(void)
+{
+	int i;
+
+	hd44780_instruction(HD44780_SET_CGRAM_ADDR);
+
+	for (i = 0; i < sizeof(char_gen_chars); i++)
+		hd44780_write_char(char_gen_chars[i]);
+
+	hd44780_instruction(HD44780_SET_DDRAM_ADDR);
+}
+
+void work_92105_display_init(void)
+{
+	int claim_err;
+	char *display_contrast_str;
+	uint8_t display_contrast = CONTRAST_DEFAULT;
+	uint8_t enable_backlight = 0x96;
+
+	slave = spi_setup_slave(0, 0, 500000, 0);
+
+	if (!slave) {
+		printf("Failed to set up SPI slave\n");
+		return;
+	}
+
+	claim_err = spi_claim_bus(slave);
+
+	if (claim_err)
+		debug("Failed to claim SPI bus: %d\n", claim_err);
+
+	/* enable backlight */
+	i2c_write(0x2c, 0x01, 1, &enable_backlight, 1);
+
+	/* set display contrast */
+	display_contrast_str = env_get("fwopt_dispcontrast");
+	if (display_contrast_str)
+		display_contrast = simple_strtoul(display_contrast_str,
+			NULL, 10);
+	i2c_write(0x2c, 0x00, 1, &display_contrast, 1);
+
+	/* request GPO_15 as an output initially set to 1 */
+	gpio_request(GPO_15, "MAX6957_nCS");
+	gpio_direction_output(GPO_15, 1);
+
+	/* enable MAX6957 portexpander */
+	max6957aax_write(MAX6957_CONF, 0x01);
+	/* configure pin 8 as input, pins 9..19 as outputs */
+	max6957aax_write(MAX6957_CONF_08_11, 0x56);
+	max6957aax_write(MAX6957_CONF_12_15, 0x55);
+	max6957aax_write(MAX6957_CONF_16_19, 0x55);
+
+	/* initialize HD44780 */
+	max6957aax_write(MAX6957AAX_HD44780_EN, 0);
+	hd44780_instruction(HD44780_FUNCTION_SET);
+	hd44780_instruction(HD44780_DISPLAY_ON_OFF_CONTROL);
+	hd44780_instruction(HD44780_ENTRY_MODE_SET);
+
+	/* write custom character glyphs */
+	hd44780_init_char_gen();
+
+	/* Show U-Boot version, date and time as a sign-of-life */
+	hd44780_instruction(HD44780_CLEAR_DISPLAY);
+	hd44780_instruction(HD44780_SET_DDRAM_ADDR | 0);
+	hd44780_write_str(U_BOOT_VERSION);
+	hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64);
+	hd44780_write_str(U_BOOT_DATE);
+	hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64 | 20);
+	hd44780_write_str(U_BOOT_TIME);
+}
+
+#ifdef CONFIG_CMD_MAX6957
+
+static int do_max6957aax(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	int reg, val;
+
+	if (argc != 3)
+		return CMD_RET_USAGE;
+	switch (argv[1][0]) {
+	case 'r':
+	case 'R':
+		reg = simple_strtoul(argv[2], NULL, 0);
+		val = max6957aax_read(reg);
+		printf("MAX6957 reg 0x%02x read 0x%02x\n", reg, val);
+		return 0;
+	default:
+		reg = simple_strtoul(argv[1], NULL, 0);
+		val = simple_strtoul(argv[2], NULL, 0);
+		max6957aax_write(reg, val);
+		printf("MAX6957 reg 0x%02x wrote 0x%02x\n", reg, val);
+		return 0;
+	}
+	return 1;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char max6957aax_help_text[] =
+	"max6957aax - write or read display register:\n"
+		"\tmax6957aax R|r reg - read display register;\n"
+		"\tmax6957aax reg val - write display register.";
+#endif
+
+U_BOOT_CMD(
+	max6957aax, 6, 1, do_max6957aax,
+	"SPI MAX6957 display write/read",
+	max6957aax_help_text
+);
+#endif /* CONFIG_CMD_MAX6957 */
+
+#ifdef CONFIG_CMD_HD44760
+
+/*
+ * We need the HUSH parser because we need string arguments, and
+ * only HUSH can understand them.
+ */
+
+#if !defined(CONFIG_HUSH_PARSER)
+#error CONFIG_CMD_HD44760 requires CONFIG_HUSH_PARSER
+#endif
+
+static int do_hd44780(struct cmd_tbl *cmdtp, int flag, int argc,
+		      char *const argv[])
+{
+	char *cmd;
+
+	if (argc != 3)
+		return CMD_RET_USAGE;
+
+	cmd = argv[1];
+
+	if (strcasecmp(cmd, "cmd") == 0)
+		hd44780_instruction(simple_strtol(argv[2], NULL, 0));
+	else if (strcasecmp(cmd, "data") == 0)
+		hd44780_write_char(simple_strtol(argv[2], NULL, 0));
+	else if (strcasecmp(cmd, "str") == 0)
+		hd44780_write_str(argv[2]);
+	return 0;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char hd44780_help_text[] =
+	"hd44780 - control LCD driver:\n"
+		"\thd44780 cmd <val> - send command <val> to driver;\n"
+		"\thd44780 data <val> - send data <val> to driver;\n"
+		"\thd44780 str \"<text>\" - send \"<text>\" to driver.";
+#endif
+
+U_BOOT_CMD(
+	hd44780, 6, 1, do_hd44780,
+	"HD44780 LCD driver control",
+	hd44780_help_text
+);
+#endif /* CONFIG_CMD_HD44760 */
diff --git a/roms/u-boot/board/work-microwave/work_92105/work_92105_display.h b/roms/u-boot/board/work-microwave/work_92105/work_92105_display.h
new file mode 100644
index 000000000..17a9aa04e
--- /dev/null
+++ b/roms/u-boot/board/work-microwave/work_92105/work_92105_display.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * work_92105 display support interface
+ *
+ * (C) Copyright 2014  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * The work_92105 display is a HD44780-compatible module
+ * controlled through a MAX6957AAX SPI port expander, two
+ * MAX518 I2C DACs and native LPC32xx GPO 15.
+ */
+
+void work_92105_display_init(void);
diff --git a/roms/u-boot/board/work-microwave/work_92105/work_92105_spl.c b/roms/u-boot/board/work-microwave/work_92105/work_92105_spl.c
new file mode 100644
index 000000000..a31553a2d
--- /dev/null
+++ b/roms/u-boot/board/work-microwave/work_92105/work_92105_spl.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * WORK Microwave work_92105 board support
+ *
+ * (C) Copyright 2014  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/emc.h>
+#include <asm/gpio.h>
+#include <spl.h>
+#include "work_92105_display.h"
+
+struct emc_dram_settings dram_64mb = {
+	.cmddelay = 0x0001C000,
+	.config0 = 0x00005682,
+	.rascas0 = 0x00000302,
+	.rdconfig = 0x00000011,
+	.trp = 52631578,
+	.tras = 20833333,
+	.tsrex = 12500000,
+	.twr = 66666666,
+	.trc = 13888888,
+	.trfc = 10256410,
+	.txsr = 12500000,
+	.trrd = 1,
+	.tmrd = 1,
+	.tcdlr = 0,
+	.refresh = 128000,
+	.mode = 0x00018000,
+	.emode = 0x02000000
+};
+
+const struct emc_dram_settings dram_128mb = {
+	.cmddelay = 0x0001C000,
+	.config0 = 0x00005882,
+	.rascas0 = 0x00000302,
+	.rdconfig = 0x00000011,
+	.trp = 52631578,
+	.tras = 22222222,
+	.tsrex = 8333333,
+	.twr = 66666666,
+	.trc = 14814814,
+	.trfc = 10256410,
+	.txsr = 8333333,
+	.trrd = 1,
+	.tmrd = 1,
+	.tcdlr = 0,
+	.refresh = 128000,
+	.mode = 0x00030000,
+	.emode = 0x02000000
+};
+
+void spl_board_init(void)
+{
+	/* initialize serial port for console */
+	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+	/* initialize console */
+	preloader_console_init();
+	/* init DDR and NAND to chainload U-Boot */
+	ddr_init(&dram_128mb);
+	/*
+	 * If this is actually a 64MB module, then the highest column
+	 * bit in any address will be ignored, and thus address 0x80000000
+	 * should be mirrored at address 0x80000800. Test this.
+	 */
+	writel(0x31415926, 0x80000000); /* write Pi at 0x80000000 */
+	writel(0x16180339, 0x80000800); /* write Phi at 0x80000800 */
+	if (readl(0x80000000) == 0x16180339) /* check 0x80000000 */ {
+		/* actually 64MB mirrored: reconfigure controller */
+		ddr_init(&dram_64mb);
+	}
+	/* initialize NAND controller to load U-Boot from NAND */
+	lpc32xx_mlc_nand_init();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NAND;
+}
diff --git a/roms/u-boot/board/xen/xenguest_arm64/Kconfig b/roms/u-boot/board/xen/xenguest_arm64/Kconfig
new file mode 100644
index 000000000..cc131ed5b
--- /dev/null
+++ b/roms/u-boot/board/xen/xenguest_arm64/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XENGUEST_ARM64
+
+config SYS_BOARD
+	default "xenguest_arm64"
+
+config SYS_VENDOR
+	default "xen"
+
+config SYS_CONFIG_NAME
+	default "xenguest_arm64"
+
+endif
diff --git a/roms/u-boot/board/xen/xenguest_arm64/MAINTAINERS b/roms/u-boot/board/xen/xenguest_arm64/MAINTAINERS
new file mode 100644
index 000000000..264920e24
--- /dev/null
+++ b/roms/u-boot/board/xen/xenguest_arm64/MAINTAINERS
@@ -0,0 +1,8 @@
+XEN GUEST FOR ARM64
+M:	Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
+M:	Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
+S:	Maintained
+F:	board/xen/xenguest_arm64/
+F:	doc/board/xen/
+F:	include/configs/xenguest_arm64.h
+F:	configs/xenguest_arm64_defconfig
diff --git a/roms/u-boot/board/xen/xenguest_arm64/Makefile b/roms/u-boot/board/xen/xenguest_arm64/Makefile
new file mode 100644
index 000000000..1cf87a728
--- /dev/null
+++ b/roms/u-boot/board/xen/xenguest_arm64/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# (C) Copyright 2020 EPAM Systems Inc.
+
+obj-y	:= xenguest_arm64.o
diff --git a/roms/u-boot/board/xen/xenguest_arm64/xenguest_arm64.c b/roms/u-boot/board/xen/xenguest_arm64/xenguest_arm64.c
new file mode 100644
index 000000000..21363d878
--- /dev/null
+++ b/roms/u-boot/board/xen/xenguest_arm64/xenguest_arm64.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) 2013
+ * David Feng <fenghua@phytium.com.cn>
+ * Sharma Bhupesh <bhupesh.sharma@freescale.com>
+ *
+ * (C) 2020 EPAM Systems Inc
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <xen.h>
+#include <asm/global_data.h>
+
+#include <asm/io.h>
+#include <asm/armv8/mmu.h>
+#include <asm/xen.h>
+#include <asm/xen/hypercall.h>
+#include <asm/xen/system.h>
+
+#include <linux/compiler.h>
+
+#include <xen/gnttab.h>
+#include <xen/hvm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+/*
+ * Use fdt provided by Xen: according to
+ * https://www.kernel.org/doc/Documentation/arm64/booting.txt
+ * x0 is the physical address of the device tree blob (dtb) in system RAM.
+ * This is stored in rom_pointer during low level init.
+ */
+void *board_fdt_blob_setup(void)
+{
+	if (fdt_magic(rom_pointer[0]) != FDT_MAGIC)
+		return NULL;
+	return (void *)rom_pointer[0];
+}
+
+#define MAX_MEM_MAP_REGIONS 5
+static struct mm_region xen_mem_map[MAX_MEM_MAP_REGIONS];
+struct mm_region *mem_map = xen_mem_map;
+
+static int get_next_memory_node(const void *blob, int mem)
+{
+	do {
+		mem = fdt_node_offset_by_prop_value(blob, mem,
+						    "device_type", "memory", 7);
+	} while (!fdtdec_get_is_enabled(blob, mem));
+
+	return mem;
+}
+
+static int setup_mem_map(void)
+{
+	int i = 0, ret, mem, reg = 0;
+	struct fdt_resource res;
+	const void *blob = gd->fdt_blob;
+	u64 gfn;
+	phys_addr_t gnttab_base;
+	phys_size_t gnttab_sz;
+
+	/*
+	 * Add "magic" region which is used by Xen to provide some essentials
+	 * for the guest: we need console and xenstore.
+	 */
+	ret = hvm_get_parameter_maintain_dcache(HVM_PARAM_CONSOLE_PFN, &gfn);
+	if (ret < 0) {
+		printf("%s: Can't get HVM_PARAM_CONSOLE_PFN, ret %d\n",
+		       __func__, ret);
+		return -EINVAL;
+	}
+
+	xen_mem_map[i].virt = PFN_PHYS(gfn);
+	xen_mem_map[i].phys = PFN_PHYS(gfn);
+	xen_mem_map[i].size = PAGE_SIZE;
+	xen_mem_map[i].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE);
+	i++;
+
+	ret = hvm_get_parameter_maintain_dcache(HVM_PARAM_STORE_PFN, &gfn);
+	if (ret < 0) {
+		printf("%s: Can't get HVM_PARAM_STORE_PFN, ret %d\n",
+		       __func__, ret);
+		return -EINVAL;
+	}
+
+	xen_mem_map[i].virt = PFN_PHYS(gfn);
+	xen_mem_map[i].phys = PFN_PHYS(gfn);
+	xen_mem_map[i].size = PAGE_SIZE;
+	xen_mem_map[i].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE);
+	i++;
+
+	/* Get Xen's suggested physical page assignments for the grant table. */
+	get_gnttab_base(&gnttab_base, &gnttab_sz);
+
+	xen_mem_map[i].virt = gnttab_base;
+	xen_mem_map[i].phys = gnttab_base;
+	xen_mem_map[i].size = gnttab_sz;
+	xen_mem_map[i].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE);
+	i++;
+
+	mem = get_next_memory_node(blob, -1);
+	if (mem < 0) {
+		printf("%s: Missing /memory node\n", __func__);
+		return -EINVAL;
+	}
+
+	for (; i < MAX_MEM_MAP_REGIONS; i++) {
+		ret = fdt_get_resource(blob, mem, "reg", reg++, &res);
+		if (ret == -FDT_ERR_NOTFOUND) {
+			reg = 0;
+			mem = get_next_memory_node(blob, mem);
+			if (mem == -FDT_ERR_NOTFOUND)
+				break;
+
+			ret = fdt_get_resource(blob, mem, "reg", reg++, &res);
+			if (ret == -FDT_ERR_NOTFOUND)
+				break;
+		}
+		if (ret != 0) {
+			printf("No reg property for memory node\n");
+			return -EINVAL;
+		}
+
+		xen_mem_map[i].virt = (phys_addr_t)res.start;
+		xen_mem_map[i].phys = (phys_addr_t)res.start;
+		xen_mem_map[i].size = (phys_size_t)(res.end - res.start + 1);
+		xen_mem_map[i].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+					PTE_BLOCK_INNER_SHARE);
+	}
+	return 0;
+}
+
+void enable_caches(void)
+{
+	/* Re-setup the memory map as BSS gets cleared after relocation. */
+	setup_mem_map();
+	icache_enable();
+	dcache_enable();
+}
+
+/* Read memory settings from the Xen provided device tree. */
+int dram_init(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_mem_size_base();
+	if (ret < 0)
+		return ret;
+	/* Setup memory map, so MMU page table size can be estimated. */
+	return setup_mem_map();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+}
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	printf("Xen virtual CPU\n");
+	return 0;
+}
+
+void board_cleanup_before_linux(void)
+{
+	xen_fini();
+}
+
diff --git a/roms/u-boot/board/xes/common/Makefile b/roms/u-boot/board/xes/common/Makefile
new file mode 100644
index 000000000..b5c690002
--- /dev/null
+++ b/roms/u-boot/board/xes/common/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-$(CONFIG_FSL_PCI_INIT)	+= fsl_8xxx_pci.o
+obj-$(CONFIG_ARCH_MPC8572)		+= fsl_8xxx_clk.o
+obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
+obj-$(CONFIG_ARCH_P2020)		+= fsl_8xxx_clk.o
+obj-$(CONFIG_MPC85xx)		+= fsl_8xxx_misc.o board.o
+obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_misc.o board.o
+obj-$(CONFIG_NAND_ACTL)	+= actl_nand.o
diff --git a/roms/u-boot/board/xes/common/actl_nand.c b/roms/u-boot/board/xes/common/actl_nand.c
new file mode 100644
index 000000000..4e52838c9
--- /dev/null
+++ b/roms/u-boot/board/xes/common/actl_nand.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This driver support NAND devices which have address lines
+ * connected as ALE and CLE inputs.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+/*
+ * Hardware specific access to control-lines
+ */
+static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
+{
+	struct nand_chip *this = mtd_to_nand(mtd);
+	ulong IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		IO_ADDR_W = (ulong)this->IO_ADDR_W;
+
+		IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
+				CONFIG_SYS_NAND_ACTL_ALE |
+				CONFIG_SYS_NAND_ACTL_NCE);
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
+		if (ctrl & NAND_NCE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
+
+		this->IO_ADDR_W = (void *)IO_ADDR_W;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = nand_addr_hwcontrol;
+	nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/xes/common/board.c b/roms/u-boot/board/xes/common/board.c
new file mode 100644
index 000000000..053b07a0b
--- /dev/null
+++ b/roms/u-boot/board/xes/common/board.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ */
+
+#include <common.h>
+#include <env.h>
+#include "fsl_8xxx_misc.h"
+#include <init.h>
+
+int checkboard(void)
+{
+	char name[] = CONFIG_SYS_BOARD_NAME;
+	char buf[64];
+	char *s;
+	int i;
+
+#ifdef CONFIG_SYS_FORM_CUSTOM
+	s = "Custom";
+#elif CONFIG_SYS_FORM_6U_CPCI
+	s = "6U CompactPCI";
+#elif CONFIG_SYS_FORM_ATCA_PMC
+	s = "ATCA w/PMC";
+#elif CONFIG_SYS_FORM_ATCA_AMC
+	s = "ATCA w/AMC";
+#elif CONFIG_SYS_FORM_VME
+	s = "VME";
+#elif CONFIG_SYS_FORM_6U_VPX
+	s = "6U VPX";
+#elif CONFIG_SYS_FORM_PMC
+	s = "PMC";
+#elif CONFIG_SYS_FORM_PCI
+	s = "PCI";
+#elif CONFIG_SYS_FORM_3U_CPCI
+	s = "3U CompactPCI";
+#elif CONFIG_SYS_FORM_AMC
+	s = "AdvancedMC";
+#elif CONFIG_SYS_FORM_XMC
+	s = "XMC";
+#elif CONFIG_SYS_FORM_PMC_XMC
+	s = "PMC/XMC";
+#elif CONFIG_SYS_FORM_PCI_EXPRESS
+	s = "PCI Express";
+#elif CONFIG_SYS_FORM_3U_VPX
+	s = "3U VPX";
+#else
+#error "Form factor not defined"
+#endif
+
+	name[strlen(name) - 1] += get_board_derivative();
+	printf("Board: X-ES %s %s SBC\n", name, s);
+
+	/* Display board specific information */
+	puts("       ");
+	i = env_get_f("board_rev", buf, sizeof(buf));
+	if (i > 0)
+		printf("Rev %s, ", buf);
+	i = env_get_f("serial#", buf, sizeof(buf));
+	if (i > 0)
+		printf("Serial# %s, ", buf);
+	i = env_get_f("board_cfg", buf, sizeof(buf));
+	if (i > 0)
+		printf("Cfg %s", buf);
+	puts("\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/xes/common/fsl_8xxx_clk.c b/roms/u-boot/board/xes/common/fsl_8xxx_clk.c
new file mode 100644
index 000000000..8ca65ca85
--- /dev/null
+++ b/roms/u-boot/board/xes/common/fsl_8xxx_clk.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+/*
+ * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
+ */
+unsigned long get_board_sys_clk(ulong dummy)
+{
+#if defined(CONFIG_MPC85xx)
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#elif defined(CONFIG_MPC86xx)
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
+
+	if (in_be32(&gur->gpporcr) & 0x10000)
+		return 66666666;
+	else
+#ifdef CONFIG_ARCH_P2020
+		return 100000000;
+#else
+		return 50000000;
+#endif
+}
+
+#ifdef CONFIG_MPC85xx
+/*
+ * Return DDR input clock - synchronous with SYSCLK or 66 MHz
+ * Note: 86xx doesn't support asynchronous DDR clk
+ */
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
+
+	if (ddr_ratio == 0x7)
+		return get_board_sys_clk(dummy);
+
+#ifdef CONFIG_ARCH_P2020
+	if (in_be32(&gur->gpporcr) & 0x20000)
+		return 66666666;
+	else
+		return 100000000;
+#else
+	return 66666666;
+#endif
+}
+#endif
diff --git a/roms/u-boot/board/xes/common/fsl_8xxx_misc.c b/roms/u-boot/board/xes/common/fsl_8xxx_misc.c
new file mode 100644
index 000000000..b26810338
--- /dev/null
+++ b/roms/u-boot/board/xes/common/fsl_8xxx_misc.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#ifdef CONFIG_PCA953X
+#include <pca953x.h>
+
+/*
+ * Determine if a board's flashes are write protected
+ */
+int board_flash_wp_on(void)
+{
+	if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_NVM_WP)
+		return 1;
+
+	return 0;
+}
+#endif
+
+/*
+ * Return a board's derivative model number.  For example:
+ * return 2 for the XPedite5372 and return 1 for the XPedite5201.
+ */
+uint get_board_derivative(void)
+{
+#if defined(CONFIG_MPC85xx)
+       volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#elif defined(CONFIG_MPC86xx)
+       volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
+       volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
+
+       /*
+	* The top 4 lines of the local bus address are pulled low/high and
+	* can be read to determine the least significant digit of a board's
+	* model number.
+	*/
+       return gur->gpporcr >> 28;
+}
diff --git a/roms/u-boot/board/xes/common/fsl_8xxx_misc.h b/roms/u-boot/board/xes/common/fsl_8xxx_misc.h
new file mode 100644
index 000000000..6e4858f15
--- /dev/null
+++ b/roms/u-boot/board/xes/common/fsl_8xxx_misc.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ */
+
+#ifndef __FSL_8XXX_MISC_H___
+#define __FSL_8XXX_MISC_H___
+
+uint get_board_derivative(void);
+
+#endif /* __FSL_8XXX_MISC_H__ */
diff --git a/roms/u-boot/board/xes/common/fsl_8xxx_pci.c b/roms/u-boot/board/xes/common/fsl_8xxx_pci.c
new file mode 100644
index 000000000..157aa3282
--- /dev/null
+++ b/roms/u-boot/board/xes/common/fsl_8xxx_pci.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+
+void pci_init_board(void)
+{
+	int first_free_busno = 0;
+
+#ifdef CONFIG_PCI1
+	int pcie_ep;
+	struct fsl_pci_info pci_info;
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 devdisr = in_be32(&gur->devdisr);
+	uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
+	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
+	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
+	uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
+	uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
+		printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
+			pci_32 ? 32 : 64,
+			pcix ? "PCIX" : "PCI",
+			pci_spd_norm ? ">=" : "<=",
+			pcix ? freq * 2 : freq,
+			pcie_ep ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter");
+
+		first_free_busno = fsl_pci_init_port(&pci_info,
+					&pci1_hose, first_free_busno);
+	} else {
+		printf("PCI1: disabled\n");
+	}
+#elif defined CONFIG_ARCH_MPC8548
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	/* PCI1 not present on MPC8572 */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
+#endif
+
+	fsl_pcie_init_board(first_free_busno);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_pci_setup(void *blob, struct bd_info *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/roms/u-boot/board/xes/xpedite517x/Kconfig b/roms/u-boot/board/xes/xpedite517x/Kconfig
new file mode 100644
index 000000000..91bbd2245
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite517x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XPEDITE517X
+
+config SYS_BOARD
+	default "xpedite517x"
+
+config SYS_VENDOR
+	default "xes"
+
+config SYS_CONFIG_NAME
+	default "xpedite517x"
+
+endif
diff --git a/roms/u-boot/board/xes/xpedite517x/MAINTAINERS b/roms/u-boot/board/xes/xpedite517x/MAINTAINERS
new file mode 100644
index 000000000..26e0acccb
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite517x/MAINTAINERS
@@ -0,0 +1,6 @@
+XPEDITE517X BOARD
+M:	Peter Tyser <ptyser@xes-inc.com>
+S:	Maintained
+F:	board/xes/xpedite517x/
+F:	include/configs/xpedite517x.h
+F:	configs/xpedite517x_defconfig
diff --git a/roms/u-boot/board/xes/xpedite517x/Makefile b/roms/u-boot/board/xes/xpedite517x/Makefile
new file mode 100644
index 000000000..10ac76a37
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite517x/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= xpedite517x.o
+obj-y	+= ddr.o
+obj-y	+= law.o
diff --git a/roms/u-boot/board/xes/xpedite517x/ddr.c b/roms/u-boot/board/xes/xpedite517x/ddr.c
new file mode 100644
index 000000000..a3fd2fc8c
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite517x/ddr.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <log.h>
+
+void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
+{
+	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+		sizeof(ddr2_spd_eeprom_t));
+}
+
+/*
+ * There are four board-specific SDRAM timing parameters which must be
+ * calculated based on the particular PCB artwork.  These are:
+ *   1.) CPO (Read Capture Delay)
+ *           - TIMING_CFG_2 register
+ *           Source: Calculation based on board trace lengths and
+ *                   chip-specific internal delays.
+ *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
+ *           - TIMING_CFG_2 register
+ *           Source: Calculation based on board trace lengths.
+ *                   Unless clock and DQ lanes are very different
+ *                   lengths (>2"), this should be set to the nominal value
+ *                   of 1/2 clock delay.
+ *   3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ *           - DDR_SDRAM_CLK_CNTL register
+ *           Source: Signal Integrity Simulations
+ *   4.) 2T Timing on Addr/Ctl
+ *           - TIMING_CFG_2 register
+ *           Source: Signal Integrity Simulations
+ *           Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ *     PCB routing on the XPedite5170 is nearly identical to the XPedite5370
+ *     so we use the XPedite5370 settings as a basis for the XPedite5170.
+ */
+
+typedef struct board_memctl_options {
+	uint16_t datarate_mhz_low;
+	uint16_t datarate_mhz_high;
+	uint8_t clk_adjust;
+	uint8_t cpo_override;
+	uint8_t write_data_delay;
+} board_memctl_options_t;
+
+static struct board_memctl_options bopts_ctrl[][2] = {
+	{
+		/* Controller 0 */
+		{
+			/* DDR2 600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo_override		= 8,
+			.write_data_delay	= 2,
+		},
+		{
+			/* DDR2 800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo_override		= 9,
+			.write_data_delay	= 2,
+		},
+	},
+	{
+		/* Controller 1 */
+		{
+			/* DDR2 600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo_override		= 7,
+			.write_data_delay	= 2,
+		},
+		{
+			/* DDR2 800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo_override		= 8,
+			.write_data_delay	= 2,
+		},
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			dimm_params_t *pdimm,
+			unsigned int ctrl_num)
+{
+	struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
+	sys_info_t sysinfo;
+	int i;
+	unsigned int datarate;
+
+	get_sys_info(&sysinfo);
+	datarate = get_ddr_freq(0) / 1000000;
+
+	for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
+		if ((bopts[i].datarate_mhz_low <= datarate) &&
+		    (bopts[i].datarate_mhz_high >= datarate)) {
+			debug("controller %d:\n", ctrl_num);
+			debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
+			debug(" cpo = %d\n", bopts[i].cpo_override);
+			debug(" write_data_delay = %d\n",
+				bopts[i].write_data_delay);
+			popts->clk_adjust = bopts[i].clk_adjust;
+			popts->cpo_override = bopts[i].cpo_override;
+			popts->write_data_delay = bopts[i].write_data_delay;
+		}
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/roms/u-boot/board/xes/xpedite517x/law.c b/roms/u-boot/board/xes/xpedite517x/law.c
new file mode 100644
index 000000000..b82f9f0d3
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite517x/law.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE
+	/* NAND LAW covers 2 NAND flashes */
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/xes/xpedite517x/xpedite517x.c b/roms/u-boot/board/xes/xpedite517x/xpedite517x.c
new file mode 100644
index 000000000..8a5b52c49
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite517x/xpedite517x.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+#include "../common/fsl_8xxx_misc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
+extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
+#endif
+
+/*
+ * Print out which flash was booted from and if booting from the 2nd flash,
+ * swap flash chip selects to maintain consistent flash numbering/addresses.
+ */
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	phys_size_t dram_size = fsl_ddr_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/* Initialize and enable DDR ECC */
+	ddr_enable_ecc(dram_size);
+#endif
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/xes/xpedite520x/Kconfig b/roms/u-boot/board/xes/xpedite520x/Kconfig
new file mode 100644
index 000000000..9c0c2461f
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite520x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XPEDITE520X
+
+config SYS_BOARD
+	default "xpedite520x"
+
+config SYS_VENDOR
+	default "xes"
+
+config SYS_CONFIG_NAME
+	default "xpedite520x"
+
+endif
diff --git a/roms/u-boot/board/xes/xpedite520x/MAINTAINERS b/roms/u-boot/board/xes/xpedite520x/MAINTAINERS
new file mode 100644
index 000000000..f7bd437cc
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite520x/MAINTAINERS
@@ -0,0 +1,6 @@
+XPEDITE520X BOARD
+M:	Peter Tyser <ptyser@xes-inc.com>
+S:	Maintained
+F:	board/xes/xpedite520x/
+F:	include/configs/xpedite520x.h
+F:	configs/xpedite520x_defconfig
diff --git a/roms/u-boot/board/xes/xpedite520x/Makefile b/roms/u-boot/board/xes/xpedite520x/Makefile
new file mode 100644
index 000000000..12e75da5b
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite520x/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= xpedite520x.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/roms/u-boot/board/xes/xpedite520x/ddr.c b/roms/u-boot/board/xes/xpedite520x/ddr.c
new file mode 100644
index 000000000..c142bec40
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite520x/ddr.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+
+	/* We use soldered memory, but use an SPD EEPROM to describe it.
+	 * The SPD has an unspecified dimm type, but the DDR2 initialization
+	 * code requires a specific type to be specified. This sets the type
+	 * as a standard unregistered SO-DIMM. */
+	if (spd->dimm_type == 0) {
+		spd->dimm_type = 0x4;
+		((uchar *)spd)[63] += 0x4;
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 9;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/roms/u-boot/board/xes/xpedite520x/law.c b/roms/u-boot/board/xes/xpedite520x/law.c
new file mode 100644
index 000000000..10613ead3
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite520x/law.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/xes/xpedite520x/tlb.c b/roms/u-boot/board/xes/xpedite520x/tlb.c
new file mode 100644
index 000000000..d45f53286
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite520x/tlb.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* W**G* - NOR flashes */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - NAND flash */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if CONFIG_PCI1
+	/* *I*G* - PCI MEM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#if CONFIG_PCI2
+	/* *I*G* - PCI MEM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 4, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+	/* *I*G* - PCI IO */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 5, BOOKE_PAGESZ_16M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/xes/xpedite520x/xpedite520x.c b/roms/u-boot/board/xes/xpedite520x/xpedite520x.c
new file mode 100644
index 000000000..63e1e0efe
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite520x/xpedite520x.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
+
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_FLASH_PASS_CS));
+	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+
+	/*
+	 * Remap NOR flash region to caching-inhibited
+	 * so that flash can be erased/programmed properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* Invalidate existing TLB entry for NOR flash */
+	disable_tlb(0);
+	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/xes/xpedite537x/Kconfig b/roms/u-boot/board/xes/xpedite537x/Kconfig
new file mode 100644
index 000000000..35b3917a6
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite537x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XPEDITE537X
+
+config SYS_BOARD
+	default "xpedite537x"
+
+config SYS_VENDOR
+	default "xes"
+
+config SYS_CONFIG_NAME
+	default "xpedite537x"
+
+endif
diff --git a/roms/u-boot/board/xes/xpedite537x/MAINTAINERS b/roms/u-boot/board/xes/xpedite537x/MAINTAINERS
new file mode 100644
index 000000000..b6123acc0
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite537x/MAINTAINERS
@@ -0,0 +1,6 @@
+XPEDITE537X BOARD
+M:	Peter Tyser <ptyser@xes-inc.com>
+S:	Maintained
+F:	board/xes/xpedite537x/
+F:	include/configs/xpedite537x.h
+F:	configs/xpedite537x_defconfig
diff --git a/roms/u-boot/board/xes/xpedite537x/Makefile b/roms/u-boot/board/xes/xpedite537x/Makefile
new file mode 100644
index 000000000..82575cf05
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite537x/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= xpedite537x.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/roms/u-boot/board/xes/xpedite537x/ddr.c b/roms/u-boot/board/xes/xpedite537x/ddr.c
new file mode 100644
index 000000000..f55102a07
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite537x/ddr.c
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <log.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
+{
+	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+		 sizeof(ddr2_spd_eeprom_t));
+}
+
+/*
+ * There are four board-specific SDRAM timing parameters which must be
+ * calculated based on the particular PCB artwork.  These are:
+ *   1.) CPO (Read Capture Delay)
+ *           - TIMING_CFG_2 register
+ *           Source: Calculation based on board trace lengths and
+ *                   chip-specific internal delays.
+ *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
+ *           - TIMING_CFG_2 register
+ *           Source: Calculation based on board trace lengths.
+ *                   Unless clock and DQ lanes are very different
+ *                   lengths (>2"), this should be set to the nominal value
+ *                   of 1/2 clock delay.
+ *   3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ *           - DDR_SDRAM_CLK_CNTL register
+ *           Source: Signal Integrity Simulations
+ *   4.) 2T Timing on Addr/Ctl
+ *           - TIMING_CFG_2 register
+ *           Source: Signal Integrity Simulations
+ *           Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ *     ====== XPedite5370 DDR2-600 read delay calculations ======
+ *
+ *     See Freescale's App Note AN2583 as refrence.  This document also
+ *     contains the chip-specific delays for 8548E, 8572, etc.
+ *
+ *     For MPC8572E
+ *     Minimum chip delay (Ch 0): 1.372ns
+ *     Maximum chip delay (Ch 0): 2.914ns
+ *     Minimum chip delay (Ch 1): 1.220ns
+ *     Maximum chip delay (Ch 1): 2.595ns
+ *
+ *     CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
+ *
+ *     Minimum delay calc (Ch 0):
+ *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ *     2.3" * 180 - 400ps     + 1.9" * 180         + 2080ps     + 1372ps
+ *                                                 = 3808ps
+ *                                                 = 3.808ns
+ *
+ *     Maximum delay calc (Ch 0):
+ *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
+ *     2.3" * 180 + 400ps     + 2.4" * 180         + 2080ps     + 2914ps
+ *                                                 = 6240ps
+ *                                                 = 6.240ns
+ *
+ *     Minimum delay calc (Ch 1):
+ *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ *     1.46" * 180- 400ps     + 0.7" * 180         + 2080ps     + 1220ps
+ *                                                 = 3288ps
+ *                                                 = 3.288ns
+ *
+ *     Maximum delay calc (Ch 1):
+ *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
+ *     1.46" * 180+ 400ps     + 1.1" * 180         + 2080ps     + 2595ps
+ *                                                 = 5536ps
+ *                                                 = 5.536ns
+ *
+ *     Ch.0: 3.808ns to 6.240ns additional delay needed  (pick 5ns as target)
+ *              This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
+ *     Ch.1: 3.288ns to 5.536ns additional delay needed  (pick 4.4ns as target)
+ *              This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
+ *
+ *
+ *     ====== XPedite5370 DDR2-800 read delay calculations ======
+ *
+ *     See Freescale's App Note AN2583 as refrence.  This document also
+ *     contains the chip-specific delays for 8548E, 8572, etc.
+ *
+ *     For MPC8572E
+ *     Minimum chip delay (Ch 0): 1.372ns
+ *     Maximum chip delay (Ch 0): 2.914ns
+ *     Minimum chip delay (Ch 1): 1.220ns
+ *     Maximum chip delay (Ch 1): 2.595ns
+ *
+ *     CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
+ *
+ *     Minimum delay calc (Ch 0):
+ *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ *     2.3" * 180 - 350ps     + 1.9" * 180         + 1563ps     + 1372ps
+ *                                                 = 3341ps
+ *                                                 = 3.341ns
+ *
+ *     Maximum delay calc (Ch 0):
+ *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
+ *     2.3" * 180 + 350ps     + 2.4" * 180         + 1563ps     + 2914ps
+ *                                                 = 5673ps
+ *                                                 = 5.673ns
+ *
+ *     Minimum delay calc (Ch 1):
+ *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ *     1.46" * 180- 350ps     + 0.7" * 180         + 1563ps     + 1220ps
+ *                                                 = 2822ps
+ *                                                 = 2.822ns
+ *
+ *     Maximum delay calc (Ch 1):
+ *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
+ *     1.46" * 180+ 350ps     + 1.1" * 180         + 1563ps     + 2595ps
+ *                                                 = 4968ps
+ *                                                 = 4.968ns
+ *
+ *     Ch.0: 3.341ns to 5.673ns additional delay needed  (pick 4.5ns as target)
+ *              This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
+ *     Ch.1: 2.822ns to 4.968ns additional delay needed  (pick 3.9ns as target)
+ *              This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
+ *
+ * Write latency (WR_DATA_DELAY) is calculated by doing the following:
+ *
+ *      The DDR SDRAM specification requires DQS be received no sooner than
+ *      75% of an SDRAM clock period—and no later than 125% of a clock
+ *      period—from the capturing clock edge of the command/address at the
+ *      SDRAM.
+ *
+ * Based on the above tracelengths, the following are calculated:
+ *      Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 =  0.342ns
+ *      Ch. 0 8572 to DRAM propagation (CLKs) :     2.3" * 180 =  0.414ns
+ *      Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 =  0.126ns
+ *      Ch. 1 8572 to DRAM propagation (CLKs   ) : 1.47" * 180 =  0.264ns
+ *
+ * Difference in arrival time CLK vs. DQS:
+ *      Ch. 0 0.072ns
+ *      Ch. 1 0.138ns
+ *
+ *      Both of these values are much less than 25% of the clock
+ *      period at DDR2-600 or DDR2-800, so no additional delay is needed over
+ *      the 1/2 cycle which normally aligns the first DQS transition
+ *      exactly WL (CAS latency minus one cycle) after the CAS strobe.
+ *      See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
+ *      terminology corresponds to exactly one clock period delay after
+ *      the CAS strobe. (due to the fact that the "delay" is referenced
+ *      from the *falling* edge of the CLK, just after the rising edge
+ *      which the CAS strobe is latched on.
+ */
+
+typedef struct board_memctl_options {
+	uint16_t datarate_mhz_low;
+	uint16_t datarate_mhz_high;
+	uint8_t clk_adjust;
+	uint8_t cpo_override;
+	uint8_t write_data_delay;
+} board_memctl_options_t;
+
+static struct board_memctl_options bopts_ctrl[][2] = {
+	{
+		/* Controller 0 */
+		{
+			/* DDR2 600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo_override		= 8,
+			.write_data_delay	= 2,
+		},
+		{
+			/* DDR2 800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo_override		= 9,
+			.write_data_delay	= 2,
+		},
+	},
+	{
+		/* Controller 1 */
+		{
+			/* DDR2 600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo_override		= 7,
+			.write_data_delay	= 2,
+		},
+		{
+			/* DDR2 800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo_override		= 8,
+			.write_data_delay	= 2,
+		},
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
+	sys_info_t sysinfo;
+	int i;
+	unsigned int datarate;
+
+	get_sys_info(&sysinfo);
+	datarate = sysinfo.freq_ddrbus / 1000 / 1000;
+
+	for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
+		if ((bopts[i].datarate_mhz_low <= datarate) &&
+		    (bopts[i].datarate_mhz_high >= datarate)) {
+			debug("controller %d:\n", ctrl_num);
+			debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
+			debug(" cpo = %d\n", bopts[i].cpo_override);
+			debug(" write_data_delay = %d\n",
+			      bopts[i].write_data_delay);
+			popts->clk_adjust = bopts[i].clk_adjust;
+			popts->cpo_override = bopts[i].cpo_override;
+			popts->write_data_delay = bopts[i].write_data_delay;
+		}
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/roms/u-boot/board/xes/xpedite537x/law.c b/roms/u-boot/board/xes/xpedite537x/law.c
new file mode 100644
index 000000000..a1f375900
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite537x/law.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/xes/xpedite537x/tlb.c b/roms/u-boot/board/xes/xpedite537x/tlb.c
new file mode 100644
index 000000000..6d50360f0
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite537x/tlb.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* W**G* - NOR flashes */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - NAND flash */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 2, BOOKE_PAGESZ_1M, 1),
+
+	/* **M** - Boot page for secondary processors */
+	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		0, 3, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_PCIE1
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 4, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 6, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 7, BOOKE_PAGESZ_64M, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/xes/xpedite537x/xpedite537x.c b/roms/u-boot/board/xes/xpedite537x/xpedite537x.c
new file mode 100644
index 000000000..437b57d4f
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite537x/xpedite537x.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
+
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+	/*
+	 * Remap NOR flash region to caching-inhibited
+	 * so that flash can be erased/programmed properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* Invalidate existing TLB entry for NOR flash */
+	disable_tlb(0);
+	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/xes/xpedite550x/Kconfig b/roms/u-boot/board/xes/xpedite550x/Kconfig
new file mode 100644
index 000000000..1b00137a4
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite550x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XPEDITE550X
+
+config SYS_BOARD
+	default "xpedite550x"
+
+config SYS_VENDOR
+	default "xes"
+
+config SYS_CONFIG_NAME
+	default "xpedite550x"
+
+endif
diff --git a/roms/u-boot/board/xes/xpedite550x/MAINTAINERS b/roms/u-boot/board/xes/xpedite550x/MAINTAINERS
new file mode 100644
index 000000000..017f36875
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite550x/MAINTAINERS
@@ -0,0 +1,6 @@
+XPEDITE550X BOARD
+M:	Peter Tyser <ptyser@xes-inc.com>
+S:	Maintained
+F:	board/xes/xpedite550x/
+F:	include/configs/xpedite550x.h
+F:	configs/xpedite550x_defconfig
diff --git a/roms/u-boot/board/xes/xpedite550x/Makefile b/roms/u-boot/board/xes/xpedite550x/Makefile
new file mode 100644
index 000000000..1aacb375c
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite550x/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2007-2008 Freescale Semiconductor, Inc.
+
+obj-y	+= xpedite550x.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/roms/u-boot/board/xes/xpedite550x/ddr.c b/roms/u-boot/board/xes/xpedite550x/ddr.c
new file mode 100644
index 000000000..ad52c9455
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite550x/ddr.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
+{
+	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+		 sizeof(ddr3_spd_eeprom_t));
+}
+
+/*
+ *     There are traditionally three board-specific SDRAM timing parameters
+ *     which must be calculated based on the particular PCB artwork.  These are:
+ *     1.) CPO (Read Capture Delay)
+ *	       - TIMING_CFG_2 register
+ *	       Source: Calculation based on board trace lengths and
+ *		       chip-specific internal delays.
+ *     2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ *	       - DDR_SDRAM_CLK_CNTL register
+ *	       Source: Signal Integrity Simulations
+ *     3.) 2T Timing on Addr/Ctl
+ *	       - TIMING_CFG_2 register
+ *	       Source: Signal Integrity Simulations
+ *	       Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ *     ====== XPedite550x DDR3-800 read delay calculations ======
+ *
+ *     The P2020 processor provides an autoleveling option. Setting CPO to
+ *     0x1f enables this auto configuration.
+ */
+
+typedef struct {
+	unsigned short datarate_mhz_low;
+	unsigned short datarate_mhz_high;
+	unsigned char clk_adjust;
+	unsigned char cpo;
+} board_specific_parameters_t;
+
+const board_specific_parameters_t board_specific_parameters[][20] = {
+	{
+		/* Controller 0 */
+		{
+			/* DDR3-600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo			= 31,
+		},
+		{
+			/* DDR3-800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo			= 31,
+		},
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const board_specific_parameters_t *pbsp =
+				&(board_specific_parameters[ctrl_num][0]);
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+				sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	ulong ddr_freq;
+
+	/*
+	 * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
+	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+	 */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i&1) {	/* odd CS */
+			popts->cs_local_opts[i].odt_rd_cfg = 0;
+			popts->cs_local_opts[i].odt_wr_cfg = 0;
+		} else {	/* even CS */
+			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+				popts->cs_local_opts[i].odt_rd_cfg = 0;
+				popts->cs_local_opts[i].odt_wr_cfg = 4;
+			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+				popts->cs_local_opts[i].odt_rd_cfg = 3;
+				popts->cs_local_opts[i].odt_wr_cfg = 3;
+			}
+		}
+	}
+
+	/*
+	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+
+	for (i = 0; i < num_params; i++) {
+		if (ddr_freq >= pbsp->datarate_mhz_low &&
+		    ddr_freq <= pbsp->datarate_mhz_high) {
+			popts->clk_adjust = pbsp->clk_adjust;
+			popts->cpo_override = pbsp->cpo;
+			popts->twot_en = 0;
+			break;
+		}
+		pbsp++;
+	}
+
+	if (i == num_params) {
+		printf("Warning: board specific timing not found "
+		"for data rate %lu MT/s!\n", ddr_freq);
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+
+	/*
+	 * Enable on-die termination.
+	 * From the Micron Technical Node TN-41-04, RTT_Nom should typically
+	 * be 30 to 40 ohms, while RTT_WR should be 120 ohms.  Setting RTT_WR
+	 * is handled in the Freescale DDR3 driver.  Set RTT_Nom here.
+	 */
+	popts->rtt_override = 1;
+	popts->rtt_override_value = 3;
+}
diff --git a/roms/u-boot/board/xes/xpedite550x/law.c b/roms/u-boot/board/xes/xpedite550x/law.c
new file mode 100644
index 000000000..1e2d604d9
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite550x/law.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/xes/xpedite550x/tlb.c b/roms/u-boot/board/xes/xpedite550x/tlb.c
new file mode 100644
index 000000000..7cb6cd677
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite550x/tlb.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* W**G* - NOR flashes */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - NAND flash */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 2, BOOKE_PAGESZ_1M, 1),
+
+	/* **M** - Boot page for secondary processors */
+	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		0, 3, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_PCIE1
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 4, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 6, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 7, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/roms/u-boot/board/xes/xpedite550x/xpedite550x.c b/roms/u-boot/board/xes/xpedite550x/xpedite550x.c
new file mode 100644
index 000000000..9089a0cc7
--- /dev/null
+++ b/roms/u-boot/board/xes/xpedite550x/xpedite550x.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
+
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+	/*
+	 * Remap NOR flash region to caching-inhibited
+	 * so that flash can be erased/programmed properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* Invalidate existing TLB entry for NOR flash */
+	disable_tlb(0);
+	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/xilinx/Kconfig b/roms/u-boot/board/xilinx/Kconfig
new file mode 100644
index 000000000..64507b5d8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/Kconfig
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2018, Luca Ceresoli <luca@lucaceresoli.net>
+
+if ARCH_ZYNQ || ARCH_ZYNQMP
+
+config XILINX_PS_INIT_FILE
+	string "Zynq/ZynqMP PS init file(s) location"
+	help
+	  On Zynq and ZynqMP U-Boot SPL (or U-Boot proper if
+	  ZYNQMP_PSU_INIT_ENABLED is set) is responsible for some
+	  basic initializations, such as enabling peripherals and
+	  configuring pinmuxes. The PS init file (called
+	  psu_init_gpl.c on ZynqMP, ps7_init_gpl.c for Zynq-7000)
+	  contains the code for such initializations.
+
+	  U-Boot contains PS init files for some boards, but each of
+	  them describes only one specific configuration. Users of a
+	  different board, or needing a different configuration, can
+	  generate custom files using the Xilinx development tools.
+
+	  There are three ways to give a PS init file to U-Boot:
+
+	  1. Set this variable to the path, either relative to the
+	     source tree or absolute, where the psu_init_gpl.c or
+	     ps7_init_gpl.c file is located. U-Boot will build this
+	     file.
+
+	  2. If you leave an empty string here, U-Boot will use
+	     board/xilinx/zynq/$(CONFIG_DEFAULT_DEVICE_TREE)/ps7_init_gpl.c
+	     for Zynq-7000, or
+	     board/xilinx/zynqmp/$(CONFIG_DEFAULT_DEVICE_TREE)/psu_init_gpl.c
+	     for ZynqMP.
+
+	  3. If the above file does not exist, U-Boot will use
+	     board/xilinx/zynq/ps7_init_gpl.c for Zynq-7000, or
+	     board/xilinx/zynqmp/psu_init_gpl.c for ZynqMP. This file
+	     is not provided by U-Boot, you have to copy it there
+	     before the build.
+
+endif
+
+config XILINX_OF_BOARD_DTB_ADDR
+	hex "Default DTB pickup address"
+	default 0x1000 if ARCH_VERSAL
+	default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
+	depends on OF_BOARD || OF_SEPARATE
+	help
+	  Offset in the memory where the board configuration DTB is placed.
+
+config BOOT_SCRIPT_OFFSET
+	hex "Boot script offset"
+	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || MICROBLAZE
+	default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE
+	default 0x3E80000 if ARCH_ZYNQMP
+	default 0x7F80000 if ARCH_VERSAL
+	help
+	   Specifies distro boot script offset in NAND/QSPI/NOR flash.
+
+config ZYNQ_MAC_IN_EEPROM
+	bool "Reading MAC address from EEPROM"
+	help
+	  Enable this option if your MAC address is saved in eeprom and
+	  xlnx,eeprom DT property in chosen node points to it.
+
+if ZYNQ_MAC_IN_EEPROM
+
+config ZYNQ_GEM_I2C_MAC_OFFSET
+	hex "Set the I2C MAC offset"
+	default 0x0
+	depends on DM_I2C
+	help
+	  Set the MAC offset for i2C.
+
+endif
+
+config CMD_FRU
+	bool "FRU information for product"
+	help
+	  This option enables FRU commands to capture and display FRU
+	  information present in the device. The FRU Information is used
+	  to primarily to provide "inventory" information about the boards
+	  that the FRU Information Device is located on.
diff --git a/roms/u-boot/board/xilinx/bootscripts/qspiboot.cmd b/roms/u-boot/board/xilinx/bootscripts/qspiboot.cmd
new file mode 100644
index 000000000..c10341c4d
--- /dev/null
+++ b/roms/u-boot/board/xilinx/bootscripts/qspiboot.cmd
@@ -0,0 +1,10 @@
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# This example only target for qspi boot, sameway it can be created for boot
+# devices like nand.
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d qspiboot.cmd boot.scr
+#
+# It requires a list of environment variables to be defined before load:
+# fdt_addr, fdt_offset, fdt_size, kernel_addr, kernel_offset, kernel_size
+#
+sf probe 0 0 0 && sf read $fdt_addr $fdt_offset $fdt_size && sf read $kernel_addr $kernel_offset $kernel_size && booti $kernel_addr - $fdt_addr
diff --git a/roms/u-boot/board/xilinx/bootscripts/sdboot.cmd b/roms/u-boot/board/xilinx/bootscripts/sdboot.cmd
new file mode 100644
index 000000000..0031900db
--- /dev/null
+++ b/roms/u-boot/board/xilinx/bootscripts/sdboot.cmd
@@ -0,0 +1,10 @@
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# This example only target for qspi boot, sameway it can be created for boot
+# devices like nand.
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d sdboot.cmd boot.scr
+#
+# It requires a list of environment variables used below to be defined
+# before load
+#
+mmc dev $devnum && mmcinfo && run uenvboot || run sdroot$devnum;load mmc $devnum:$partid $fdt_addr system.dtb && load mmc $devnum:$partid $kernel_addr Image && booti $kernel_addr - $fdt_addr
diff --git a/roms/u-boot/board/xilinx/common/Makefile b/roms/u-boot/board/xilinx/common/Makefile
new file mode 100644
index 000000000..212028478
--- /dev/null
+++ b/roms/u-boot/board/xilinx/common/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# (C) Copyright 2020 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+#
+
+obj-y	+= board.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_FRU) += fru.o fru_ops.o
+endif
diff --git a/roms/u-boot/board/xilinx/common/board.c b/roms/u-boot/board/xilinx/common/board.c
new file mode 100644
index 000000000..92b61d83c
--- /dev/null
+++ b/roms/u-boot/board/xilinx/common/board.c
@@ -0,0 +1,442 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 - 2020 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <malloc.h>
+#include "board.h"
+#include <dm.h>
+#include <i2c_eeprom.h>
+#include <net.h>
+#include <generated/dt.h>
+
+#include "fru.h"
+
+#if defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+	int ret = -EINVAL;
+	struct udevice *dev;
+	ofnode eeprom;
+
+	eeprom = ofnode_get_chosen_node("xlnx,eeprom");
+	if (!ofnode_valid(eeprom))
+		return -ENODEV;
+
+	debug("%s: Path to EEPROM %s\n", __func__,
+	      ofnode_read_chosen_string("xlnx,eeprom"));
+
+	ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
+	if (ret)
+		return ret;
+
+	ret = dm_i2c_read(dev, CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, ethaddr, 6);
+	if (ret)
+		debug("%s: I2C EEPROM MAC address read failed\n", __func__);
+	else
+		debug("%s: I2C EEPROM MAC %pM\n", __func__, ethaddr);
+
+	return ret;
+}
+#endif
+
+#define EEPROM_HEADER_MAGIC		0xdaaddeed
+#define EEPROM_HDR_MANUFACTURER_LEN	16
+#define EEPROM_HDR_NAME_LEN		16
+#define EEPROM_HDR_REV_LEN		8
+#define EEPROM_HDR_SERIAL_LEN		20
+#define EEPROM_HDR_NO_OF_MAC_ADDR	4
+#define EEPROM_HDR_ETH_ALEN		ETH_ALEN
+
+struct xilinx_board_description {
+	u32 header;
+	char manufacturer[EEPROM_HDR_MANUFACTURER_LEN + 1];
+	char name[EEPROM_HDR_NAME_LEN + 1];
+	char revision[EEPROM_HDR_REV_LEN + 1];
+	char serial[EEPROM_HDR_SERIAL_LEN + 1];
+	u8 mac_addr[EEPROM_HDR_NO_OF_MAC_ADDR][EEPROM_HDR_ETH_ALEN + 1];
+};
+
+static int highest_id = -1;
+static struct xilinx_board_description **board_info;
+
+#define XILINX_I2C_DETECTION_BITS	sizeof(struct fru_common_hdr)
+
+/* Variable which stores pointer to array which stores eeprom content */
+struct xilinx_legacy_format {
+	char board_sn[18]; /* 0x0 */
+	char unused0[14]; /* 0x12 */
+	char eth_mac[6]; /* 0x20 */
+	char unused1[170]; /* 0x26 */
+	char board_name[11]; /* 0xd0 */
+	char unused2[5]; /* 0xdc */
+	char board_revision[3]; /* 0xe0 */
+	char unused3[29]; /* 0xe3 */
+};
+
+static void xilinx_eeprom_legacy_cleanup(char *eeprom, int size)
+{
+	int i;
+	char byte;
+
+	for (i = 0; i < size; i++) {
+		byte = eeprom[i];
+
+		/* Remove all ffs and spaces */
+		if (byte == 0xff || byte == ' ')
+			eeprom[i] = 0;
+
+		/* Convert strings to lower case */
+		if (byte >= 'A' && byte <= 'Z')
+			eeprom[i] = byte + 'a' - 'A';
+	}
+}
+
+static int xilinx_read_eeprom_legacy(struct udevice *dev, char *name,
+				     struct xilinx_board_description *desc)
+{
+	int ret, size;
+	struct xilinx_legacy_format *eeprom_content;
+	bool eth_valid = false;
+
+	size = sizeof(*eeprom_content);
+
+	eeprom_content = calloc(1, size);
+	if (!eeprom_content)
+		return -ENOMEM;
+
+	debug("%s: I2C EEPROM read pass data at %p\n", __func__,
+	      eeprom_content);
+
+	ret = dm_i2c_read(dev, 0, (uchar *)eeprom_content, size);
+	if (ret) {
+		debug("%s: I2C EEPROM read failed\n", __func__);
+		free(eeprom_content);
+		return ret;
+	}
+
+	xilinx_eeprom_legacy_cleanup((char *)eeprom_content, size);
+
+	printf("Xilinx I2C Legacy format at %s:\n", name);
+	printf(" Board name:\t%s\n", eeprom_content->board_name);
+	printf(" Board rev:\t%s\n", eeprom_content->board_revision);
+	printf(" Board SN:\t%s\n", eeprom_content->board_sn);
+
+	eth_valid = is_valid_ethaddr((const u8 *)eeprom_content->eth_mac);
+	if (eth_valid)
+		printf(" Ethernet mac:\t%pM\n", eeprom_content->eth_mac);
+
+	/* Terminating \0 chars ensure end of string */
+	strcpy(desc->name, eeprom_content->board_name);
+	strcpy(desc->revision, eeprom_content->board_revision);
+	strcpy(desc->serial, eeprom_content->board_sn);
+	if (eth_valid)
+		memcpy(desc->mac_addr[0], eeprom_content->eth_mac, ETH_ALEN);
+
+	desc->header = EEPROM_HEADER_MAGIC;
+
+	free(eeprom_content);
+
+	return ret;
+}
+
+static bool xilinx_detect_legacy(u8 *buffer)
+{
+	int i;
+	char c;
+
+	for (i = 0; i < XILINX_I2C_DETECTION_BITS; i++) {
+		c = buffer[i];
+
+		if (c < '0' || c > '9')
+			return false;
+	}
+
+	return true;
+}
+
+static int xilinx_read_eeprom_fru(struct udevice *dev, char *name,
+				  struct xilinx_board_description *desc)
+{
+	int ret, eeprom_size;
+	u8 *fru_content;
+
+	/* FIXME this is shortcut - if eeprom type is wrong it will fail */
+	eeprom_size = i2c_eeprom_size(dev);
+
+	fru_content = calloc(1, eeprom_size);
+	if (!fru_content)
+		return -ENOMEM;
+
+	debug("%s: I2C EEPROM read pass data at %p\n", __func__,
+	      fru_content);
+
+	ret = dm_i2c_read(dev, 0, (uchar *)fru_content,
+			  eeprom_size);
+	if (ret) {
+		debug("%s: I2C EEPROM read failed\n", __func__);
+		free(fru_content);
+		return ret;
+	}
+
+	printf("Xilinx I2C FRU format at %s:\n", name);
+	fru_capture((unsigned long)fru_content);
+	ret = fru_display(0);
+	if (ret) {
+		printf("FRU format decoding failed.\n");
+		return ret;
+	}
+
+	if (desc->header == EEPROM_HEADER_MAGIC) {
+		debug("Information already filled\n");
+		return -EINVAL;
+	}
+
+	/* It is clear that FRU was captured and structures were filled */
+	strncpy(desc->manufacturer, (char *)fru_data.brd.manufacturer_name,
+		sizeof(desc->manufacturer));
+	strncpy(desc->name, (char *)fru_data.brd.product_name,
+		sizeof(desc->name));
+	strncpy(desc->revision, (char *)fru_data.brd.rev,
+		sizeof(desc->revision));
+	strncpy(desc->serial, (char *)fru_data.brd.serial_number,
+		sizeof(desc->serial));
+	desc->header = EEPROM_HEADER_MAGIC;
+
+	return 0;
+}
+
+static bool xilinx_detect_fru(u8 *buffer)
+{
+	u8 checksum = 0;
+	int i;
+
+	checksum = fru_checksum((u8 *)buffer, sizeof(struct fru_common_hdr));
+	if (checksum) {
+		debug("%s Common header CRC FAIL\n", __func__);
+		return false;
+	}
+
+	bool all_zeros = true;
+	/* Checksum over all zeros is also zero that's why detect this case */
+	for (i = 0; i < sizeof(struct fru_common_hdr); i++) {
+		if (buffer[i] != 0)
+			all_zeros = false;
+	}
+
+	if (all_zeros)
+		return false;
+
+	debug("%s Common header CRC PASS\n", __func__);
+	return true;
+}
+
+static int xilinx_read_eeprom_single(char *name,
+				     struct xilinx_board_description *desc)
+{
+	int ret;
+	struct udevice *dev;
+	ofnode eeprom;
+	u8 buffer[XILINX_I2C_DETECTION_BITS];
+
+	eeprom = ofnode_get_aliases_node(name);
+	if (!ofnode_valid(eeprom))
+		return -ENODEV;
+
+	ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
+	if (ret)
+		return ret;
+
+	ret = dm_i2c_read(dev, 0, buffer, sizeof(buffer));
+	if (ret) {
+		debug("%s: I2C EEPROM read failed\n", __func__);
+		return ret;
+	}
+
+	debug("%s: i2c memory detected: %s\n", __func__, name);
+
+	if (CONFIG_IS_ENABLED(CMD_FRU) && xilinx_detect_fru(buffer))
+		return xilinx_read_eeprom_fru(dev, name, desc);
+
+	if (xilinx_detect_legacy(buffer))
+		return xilinx_read_eeprom_legacy(dev, name, desc);
+
+	return -ENODEV;
+}
+
+__maybe_unused int xilinx_read_eeprom(void)
+{
+	int id, ret;
+	char name_buf[8]; /* 8 bytes should be enough for nvmem+number */
+	struct xilinx_board_description *desc;
+
+	highest_id = dev_read_alias_highest_id("nvmem");
+	/* No nvmem aliases present */
+	if (highest_id < 0)
+		return -EINVAL;
+
+	board_info = calloc(1, sizeof(desc) * highest_id);
+	if (!board_info)
+		return -ENOMEM;
+
+	debug("%s: Highest ID %d, board_info %p\n", __func__,
+	      highest_id, board_info);
+
+	for (id = 0; id <= highest_id; id++) {
+		snprintf(name_buf, sizeof(name_buf), "nvmem%d", id);
+
+		/* Alloc structure */
+		desc = board_info[id];
+		if (!desc) {
+			desc = calloc(1, sizeof(*desc));
+			if (!desc)
+				return -ENOMEM;
+
+			board_info[id] = desc;
+		}
+
+		/* Ignoring return value for supporting multiple chips */
+		ret = xilinx_read_eeprom_single(name_buf, desc);
+		if (ret) {
+			free(desc);
+			board_info[id] = NULL;
+		}
+	}
+
+	/*
+	 * Consider to clean board_info structure when board/cards are not
+	 * detected.
+	 */
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
+void *board_fdt_blob_setup(void)
+{
+	void *fdt_blob;
+
+	if (!IS_ENABLED(CONFIG_SPL_BUILD) &&
+	    !IS_ENABLED(CONFIG_VERSAL_NO_DDR) &&
+	    !IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) {
+		fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
+
+		if (fdt_magic(fdt_blob) == FDT_MAGIC)
+			return fdt_blob;
+
+		debug("DTB is not passed via %p\n", fdt_blob);
+	}
+
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		/*
+		 * FDT is at end of BSS unless it is in a different memory
+		 * region
+		 */
+		if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
+			fdt_blob = (ulong *)&_image_binary_end;
+		else
+			fdt_blob = (ulong *)&__bss_end;
+	} else {
+		/* FDT is at end of image */
+		fdt_blob = (ulong *)&_end;
+	}
+
+	if (fdt_magic(fdt_blob) == FDT_MAGIC)
+		return fdt_blob;
+
+	debug("DTB is also not passed via %p\n", fdt_blob);
+
+	return NULL;
+}
+#endif
+
+#if defined(CONFIG_BOARD_LATE_INIT)
+static int env_set_by_index(const char *name, int index, char *data)
+{
+	char var[32];
+
+	if (!index)
+		sprintf(var, "board_%s", name);
+	else
+		sprintf(var, "card%d_%s", index, name);
+
+	return env_set(var, data);
+}
+
+int board_late_init_xilinx(void)
+{
+	u32 ret = 0;
+	int i, id, macid = 0;
+	struct xilinx_board_description *desc;
+	phys_size_t bootm_size = gd->ram_size;
+
+	if (!CONFIG_IS_ENABLED(MICROBLAZE)) {
+		ulong scriptaddr;
+
+		scriptaddr = env_get_hex("scriptaddr", 0);
+		ret |= env_set_hex("scriptaddr", gd->ram_base + scriptaddr);
+	}
+
+	if (CONFIG_IS_ENABLED(ARCH_ZYNQ) || CONFIG_IS_ENABLED(MICROBLAZE))
+		bootm_size = min(bootm_size, (phys_size_t)(SZ_512M + SZ_256M));
+
+	ret |= env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
+
+	ret |= env_set_addr("bootm_low", (void *)gd->ram_base);
+	ret |= env_set_addr("bootm_size", (void *)bootm_size);
+
+	for (id = 0; id <= highest_id; id++) {
+		desc = board_info[id];
+		if (desc && desc->header == EEPROM_HEADER_MAGIC) {
+			if (desc->manufacturer[0])
+				ret |= env_set_by_index("manufacturer", id,
+							desc->manufacturer);
+			if (desc->name[0])
+				ret |= env_set_by_index("name", id,
+							desc->name);
+			if (desc->revision[0])
+				ret |= env_set_by_index("rev", id,
+							desc->revision);
+			if (desc->serial[0])
+				ret |= env_set_by_index("serial", id,
+							desc->serial);
+
+			if (!CONFIG_IS_ENABLED(NET))
+				continue;
+
+			for (i = 0; i < EEPROM_HDR_NO_OF_MAC_ADDR; i++) {
+				if (!desc->mac_addr[i])
+					continue;
+
+				if (is_valid_ethaddr((const u8 *)desc->mac_addr[i]))
+					ret |= eth_env_set_enetaddr_by_index("eth",
+							macid++, desc->mac_addr[i]);
+			}
+		}
+	}
+
+	if (ret)
+		printf("%s: Saving run time variables FAILED\n", __func__);
+
+	return 0;
+}
+#endif
+
+int __maybe_unused board_fit_config_name_match(const char *name)
+{
+	debug("%s: Check %s, default %s\n", __func__, name, DEVICE_TREE);
+
+	if (!strcmp(name, DEVICE_TREE))
+		return 0;
+
+	return -1;
+}
diff --git a/roms/u-boot/board/xilinx/common/board.h b/roms/u-boot/board/xilinx/common/board.h
new file mode 100644
index 000000000..69e642429
--- /dev/null
+++ b/roms/u-boot/board/xilinx/common/board.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2020 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#ifndef _BOARD_XILINX_COMMON_BOARD_H
+#define _BOARD_XILINX_COMMON_BOARD_H
+
+int board_late_init_xilinx(void);
+
+int xilinx_read_eeprom(void);
+
+#endif /* BOARD_XILINX_COMMON_BOARD_H */
diff --git a/roms/u-boot/board/xilinx/common/fru.c b/roms/u-boot/board/xilinx/common/fru.c
new file mode 100644
index 000000000..ccf48723f
--- /dev/null
+++ b/roms/u-boot/board/xilinx/common/fru.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019 - 2020 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fdtdec.h>
+#include <malloc.h>
+
+#include "fru.h"
+
+static int do_fru_capture(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	unsigned long addr;
+	char *endp;
+
+	if (argc < cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], &endp, 16);
+	if (*argv[1] == 0 || *endp != 0)
+		return -1;
+
+	return fru_capture(addr);
+}
+
+static int do_fru_display(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	fru_display(1);
+	return CMD_RET_SUCCESS;
+}
+
+static int do_fru_generate(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	unsigned long addr;
+
+	if (argc < cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+
+	return fru_generate(addr, argv[3], argv[4], argv[5], argv[6], argv[7]);
+}
+
+static struct cmd_tbl cmd_fru_sub[] = {
+	U_BOOT_CMD_MKENT(capture, 3, 0, do_fru_capture, "", ""),
+	U_BOOT_CMD_MKENT(display, 2, 0, do_fru_display, "", ""),
+	U_BOOT_CMD_MKENT(board_gen, 8, 0, do_fru_generate, "", ""),
+};
+
+static int do_fru(struct cmd_tbl *cmdtp, int flag, int argc,
+		  char *const argv[])
+{
+	struct cmd_tbl *c;
+	int ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	c = find_cmd_tbl(argv[1], &cmd_fru_sub[0],
+			 ARRAY_SIZE(cmd_fru_sub));
+	if (!c)
+		return CMD_RET_USAGE;
+
+	ret = c->cmd(c, flag, argc, argv);
+
+	return cmd_process_error(c, ret);
+}
+
+/***************************************************/
+#ifdef CONFIG_SYS_LONGHELP
+static char fru_help_text[] =
+	"capture <addr> - Parse and capture FRU table present at address.\n"
+	"fru display - Displays content of FRU table that was captured using\n"
+	"              fru capture command\n"
+	"fru board_gen <addr> <manufacturer> <board name> <serial number>\n"
+	"              <part number> <revision> - Generate FRU format with\n"
+	"              board info area filled based on parameters. <addr> is\n"
+	"              pointing to place where FRU is generated.\n"
+	;
+#endif
+
+U_BOOT_CMD(
+	fru, 8, 1, do_fru,
+	"FRU table info",
+	fru_help_text
+)
diff --git a/roms/u-boot/board/xilinx/common/fru.h b/roms/u-boot/board/xilinx/common/fru.h
new file mode 100644
index 000000000..e7284709d
--- /dev/null
+++ b/roms/u-boot/board/xilinx/common/fru.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ */
+
+#ifndef __FRU_H
+#define __FRU_H
+
+struct fru_common_hdr {
+	u8 version;
+	u8 off_internal;
+	u8 off_chassis;
+	u8 off_board;
+	u8 off_product;
+	u8 off_multirec;
+	u8 pad;
+	u8 crc;
+};
+
+#define FRU_BOARD_MAX_LEN	32
+
+struct __packed fru_board_info_header {
+	u8 ver;
+	u8 len;
+	u8 lang_code;
+	u8 time[3];
+};
+
+struct __packed fru_board_info_member {
+	u8 type_len;
+	u8 *name;
+};
+
+struct fru_board_data {
+	u8 ver;
+	u8 len;
+	u8 lang_code;
+	u8 time[3];
+	u8 manufacturer_type_len;
+	u8 manufacturer_name[FRU_BOARD_MAX_LEN];
+	u8 product_name_type_len;
+	u8 product_name[FRU_BOARD_MAX_LEN];
+	u8 serial_number_type_len;
+	u8 serial_number[FRU_BOARD_MAX_LEN];
+	u8 part_number_type_len;
+	u8 part_number[FRU_BOARD_MAX_LEN];
+	u8 file_id_type_len;
+	u8 file_id[FRU_BOARD_MAX_LEN];
+	/* Xilinx custom fields */
+	u8 rev_type_len;
+	u8 rev[FRU_BOARD_MAX_LEN];
+	u8 pcie_type_len;
+	u8 pcie[FRU_BOARD_MAX_LEN];
+	u8 uuid_type_len;
+	u8 uuid[FRU_BOARD_MAX_LEN];
+};
+
+struct fru_table {
+	struct fru_common_hdr hdr;
+	struct fru_board_data brd;
+	bool captured;
+};
+
+#define FRU_TYPELEN_CODE_MASK	0xC0
+#define FRU_TYPELEN_LEN_MASK	0x3F
+#define FRU_COMMON_HDR_VER_MASK		0xF
+#define FRU_COMMON_HDR_LEN_MULTIPLIER	8
+#define FRU_LANG_CODE_ENGLISH		0
+#define FRU_LANG_CODE_ENGLISH_1		25
+#define FRU_TYPELEN_EOF			0xC1
+
+/* This should be minimum of fields */
+#define FRU_BOARD_AREA_TOTAL_FIELDS	5
+#define FRU_TYPELEN_TYPE_SHIFT		6
+#define FRU_TYPELEN_TYPE_BINARY		0
+#define FRU_TYPELEN_TYPE_ASCII8		3
+
+int fru_display(int verbose);
+int fru_capture(unsigned long addr);
+int fru_generate(unsigned long addr, char *manufacturer, char *board_name,
+		 char *serial_no, char *part_no, char *revision);
+u8 fru_checksum(u8 *addr, u8 len);
+
+extern struct fru_table fru_data;
+
+#endif /* FRU_H */
diff --git a/roms/u-boot/board/xilinx/common/fru_ops.c b/roms/u-boot/board/xilinx/common/fru_ops.c
new file mode 100644
index 000000000..6ed63bb7e
--- /dev/null
+++ b/roms/u-boot/board/xilinx/common/fru_ops.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019 - 2020 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include "fru.h"
+
+struct fru_table fru_data __section(".data");
+
+static u16 fru_cal_area_len(u8 len)
+{
+	return len * FRU_COMMON_HDR_LEN_MULTIPLIER;
+}
+
+static u8 fru_version(u8 ver)
+{
+	return ver & FRU_COMMON_HDR_VER_MASK;
+}
+
+static int fru_check_language(u8 code)
+{
+	if (code != FRU_LANG_CODE_ENGLISH && code != FRU_LANG_CODE_ENGLISH_1) {
+		printf("FRU_ERROR: Only English Language is supported\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+u8 fru_checksum(u8 *addr, u8 len)
+{
+	u8 checksum = 0;
+
+	while (len--) {
+		checksum += *addr;
+		addr++;
+	}
+
+	return checksum;
+}
+
+static int fru_check_type_len(u8 type_len, u8 language, u8 *type)
+{
+	int len;
+
+	if (type_len == FRU_TYPELEN_EOF)
+		return -EINVAL;
+
+	*type = (type_len & FRU_TYPELEN_CODE_MASK) >> FRU_TYPELEN_TYPE_SHIFT;
+
+	len = type_len & FRU_TYPELEN_LEN_MASK;
+
+	return len;
+}
+
+/* Return len */
+static u8 fru_gen_type_len(u8 *addr, char *name)
+{
+	int len = strlen(name);
+	struct fru_board_info_member *member;
+
+	member = (struct fru_board_info_member *)addr;
+	member->type_len = FRU_TYPELEN_TYPE_ASCII8 << FRU_TYPELEN_TYPE_SHIFT;
+	member->type_len |= len;
+
+	debug("%lx/%lx: Add %s to 0x%lx (len 0x%x)\n", (ulong)addr,
+	      (ulong)&member->type_len,  name, (ulong)&member->name, len);
+	memcpy(&member->name, name, len);
+
+	/* Add +1 for type_len parameter */
+	return 1 + len;
+}
+
+int fru_generate(unsigned long addr, char *manufacturer, char *board_name,
+		 char *serial_no, char *part_no, char *revision)
+{
+	struct fru_common_hdr *header = (struct fru_common_hdr *)addr;
+	struct fru_board_info_header *board_info;
+	u8 *member;
+	u8 len, pad, modulo;
+
+	header->version = 1; /* Only version 1.0 is supported now */
+	header->off_internal = 0; /* not present */
+	header->off_chassis = 0; /* not present */
+	header->off_board = (sizeof(*header)) / 8; /* Starting offset 8 */
+	header->off_product = 0; /* not present */
+	header->off_multirec = 0; /* not present */
+	header->pad = 0;
+	/*
+	 * This unsigned byte can be used to calculate a zero checksum
+	 * for the data area following the header. I.e. the modulo 256 sum of
+	 * the record data bytes plus the checksum byte equals zero.
+	 */
+	header->crc = 0; /* Clear before calculation */
+	header->crc = 0 - fru_checksum((u8 *)header, sizeof(*header));
+
+	/* board info is just right after header */
+	board_info = (void *)((u8 *)header + sizeof(*header));
+
+	debug("header %lx, board_info %lx\n", (ulong)header, (ulong)board_info);
+
+	board_info->ver = 1; /* 1.0 spec */
+	board_info->lang_code = 0; /* English */
+	board_info->time[0] = 0; /* unspecified */
+	board_info->time[1] = 0; /* unspecified */
+	board_info->time[2] = 0; /* unspecified */
+
+	/* Member fields are just after board_info header */
+	member = (u8 *)board_info + sizeof(*board_info);
+
+	len = fru_gen_type_len(member, manufacturer); /* Board Manufacturer */
+	member += len;
+	len = fru_gen_type_len(member, board_name); /* Board Product name */
+	member += len;
+	len = fru_gen_type_len(member, serial_no); /* Board Serial number */
+	member += len;
+	len = fru_gen_type_len(member, part_no); /* Board part number */
+	member += len;
+	len = fru_gen_type_len(member, "U-Boot generator"); /* File ID */
+	member += len;
+	len = fru_gen_type_len(member, revision); /* Revision */
+	member += len;
+
+	*member++ = 0xc1; /* Indication of no more fields */
+
+	len = member - (u8 *)board_info; /* Find current length */
+	len += 1; /* Add checksum there too for calculation */
+
+	modulo = len % 8;
+
+	if (modulo) {
+		/* Do not fill last item which is checksum */
+		for (pad = 0; pad < 8 - modulo; pad++)
+			*member++ = 0;
+
+		/* Increase structure size */
+		len += 8 - modulo;
+	}
+
+	board_info->len = len / 8; /* Size in multiples of 8 bytes */
+
+	*member = 0; /* Clear before calculation */
+	*member = 0 - fru_checksum((u8 *)board_info, len);
+
+	debug("checksum %x(addr %x)\n", *member, len);
+
+	env_set_hex("fru_addr", addr);
+	env_set_hex("filesize", (unsigned long)member - addr + 1);
+
+	return 0;
+}
+
+static int fru_parse_board(unsigned long addr)
+{
+	u8 i, type;
+	int len;
+	u8 *data, *term, *limit;
+
+	memcpy(&fru_data.brd.ver, (void *)addr, 6);
+	addr += 6;
+	data = (u8 *)&fru_data.brd.manufacturer_type_len;
+
+	/* Record max structure limit not to write data over allocated space */
+	limit = (u8 *)&fru_data.brd + sizeof(struct fru_board_data);
+
+	for (i = 0; ; i++, data += FRU_BOARD_MAX_LEN) {
+		len = fru_check_type_len(*(u8 *)addr, fru_data.brd.lang_code,
+					 &type);
+		/*
+		 * Stop cature if it end of fields
+		 */
+		if (len == -EINVAL)
+			break;
+
+		/* Stop when amount of chars is more then fields to record */
+		if (data + len > limit)
+			break;
+		/* This record type/len field */
+		*data++ = *(u8 *)addr;
+
+		/* Add offset to match data */
+		addr += 1;
+
+		/* If len is 0 it means empty field that's why skip writing */
+		if (!len)
+			continue;
+
+		/* Record data field */
+		memcpy(data, (u8 *)addr, len);
+		term = data + (u8)len;
+		*term = 0;
+		addr += len;
+	}
+
+	if (i < FRU_BOARD_AREA_TOTAL_FIELDS) {
+		printf("Board area require minimum %d fields\n",
+		       FRU_BOARD_AREA_TOTAL_FIELDS);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int fru_capture(unsigned long addr)
+{
+	struct fru_common_hdr *hdr;
+	u8 checksum = 0;
+
+	checksum = fru_checksum((u8 *)addr, sizeof(struct fru_common_hdr));
+	if (checksum) {
+		printf("%s Common header CRC error\n", __func__);
+		return -EINVAL;
+	}
+
+	hdr = (struct fru_common_hdr *)addr;
+
+	memcpy((void *)&fru_data, (void *)hdr,
+	       sizeof(struct fru_common_hdr));
+
+	fru_data.captured = true;
+
+	if (hdr->off_board) {
+		addr += fru_cal_area_len(hdr->off_board);
+		fru_parse_board(addr);
+	}
+
+	env_set_hex("fru_addr", addr);
+
+	return 0;
+}
+
+static int fru_display_board(struct fru_board_data *brd, int verbose)
+{
+	u32 time = 0;
+	u8 type;
+	int len;
+	u8 *data;
+	static const char * const typecode[] = {
+		"Binary/Unspecified",
+		"BCD plus",
+		"6-bit ASCII",
+		"8-bit ASCII",
+		"2-byte UNICODE"
+	};
+	static const char * const boardinfo[] = {
+		"Manufacturer Name",
+		"Product Name",
+		"Serial No",
+		"Part Number",
+		"File ID",
+		/* Xilinx spec */
+		"Revision Number",
+	};
+
+	if (verbose) {
+		printf("*****BOARD INFO*****\n");
+		printf("Version:%d\n", fru_version(brd->ver));
+		printf("Board Area Length:%d\n", fru_cal_area_len(brd->len));
+	}
+
+	if (fru_check_language(brd->lang_code))
+		return -EINVAL;
+
+	time = brd->time[2] << 16 | brd->time[1] << 8 |
+	       brd->time[0];
+
+	if (verbose)
+		printf("Time in Minutes from 0:00hrs 1/1/96: %d\n", time);
+
+	data = (u8 *)&brd->manufacturer_type_len;
+
+	for (u8 i = 0; i < (sizeof(boardinfo) / sizeof(*boardinfo)); i++) {
+		len = fru_check_type_len(*data++, brd->lang_code,
+					 &type);
+		if (len == -EINVAL) {
+			printf("**** EOF for Board Area ****\n");
+			break;
+		}
+
+		if (type <= FRU_TYPELEN_TYPE_ASCII8 &&
+		    (brd->lang_code == FRU_LANG_CODE_ENGLISH ||
+		     brd->lang_code == FRU_LANG_CODE_ENGLISH_1))
+			debug("Type code: %s\n", typecode[type]);
+		else
+			debug("Type code: %s\n", typecode[type + 1]);
+
+		if (!len) {
+			debug("%s not found\n", boardinfo[i]);
+			continue;
+		}
+
+		switch (type) {
+		case FRU_TYPELEN_TYPE_BINARY:
+			debug("Length: %d\n", len);
+			printf(" %s: 0x%x\n", boardinfo[i], *data);
+			break;
+		case FRU_TYPELEN_TYPE_ASCII8:
+			debug("Length: %d\n", len);
+			printf(" %s: %s\n", boardinfo[i], data);
+			break;
+		default:
+			debug("Unsupported type %x\n", type);
+		}
+
+		data += FRU_BOARD_MAX_LEN;
+	}
+
+	return 0;
+}
+
+static void fru_display_common_hdr(struct fru_common_hdr *hdr, int verbose)
+{
+	if (!verbose)
+		return;
+
+	printf("*****COMMON HEADER*****\n");
+	printf("Version:%d\n", fru_version(hdr->version));
+	if (hdr->off_internal)
+		printf("Internal Use Area Offset:%d\n",
+		       fru_cal_area_len(hdr->off_internal));
+	else
+		printf("*** No Internal Area ***\n");
+
+	if (hdr->off_chassis)
+		printf("Chassis Info Area Offset:%d\n",
+		       fru_cal_area_len(hdr->off_chassis));
+	else
+		printf("*** No Chassis Info Area ***\n");
+
+	if (hdr->off_board)
+		printf("Board Area Offset:%d\n",
+		       fru_cal_area_len(hdr->off_board));
+	else
+		printf("*** No Board Area ***\n");
+
+	if (hdr->off_product)
+		printf("Product Info Area Offset:%d\n",
+		       fru_cal_area_len(hdr->off_product));
+	else
+		printf("*** No Product Info Area ***\n");
+
+	if (hdr->off_multirec)
+		printf("MultiRecord Area Offset:%d\n",
+		       fru_cal_area_len(hdr->off_multirec));
+	else
+		printf("*** No MultiRecord Area ***\n");
+}
+
+int fru_display(int verbose)
+{
+	if (!fru_data.captured) {
+		printf("FRU data not available please run fru parse\n");
+		return -EINVAL;
+	}
+
+	fru_display_common_hdr(&fru_data.hdr, verbose);
+
+	return fru_display_board(&fru_data.brd, verbose);
+}
diff --git a/roms/u-boot/board/xilinx/microblaze-generic/Kconfig b/roms/u-boot/board/xilinx/microblaze-generic/Kconfig
new file mode 100644
index 000000000..f2fa0f72b
--- /dev/null
+++ b/roms/u-boot/board/xilinx/microblaze-generic/Kconfig
@@ -0,0 +1,41 @@
+if TARGET_MICROBLAZE_GENERIC
+
+config SYS_BOARD
+	default "microblaze-generic"
+
+config SYS_VENDOR
+	default "xilinx"
+
+config SYS_CONFIG_NAME
+	string "Board configuration name"
+	default "microblaze-generic"
+	help
+	  This option contains information about board configuration name.
+	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+	  will be used for board configuration.
+
+config XILINX_MICROBLAZE0_USE_MSR_INSTR
+	int "USE_MSR_INSTR range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_PCMP_INSTR
+	int "USE_PCMP_INSTR range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_BARREL
+	int "USE_BARREL range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_DIV
+	int "USE_DIV range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_HW_MUL
+	int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
+	default 0
+
+config XILINX_MICROBLAZE0_HW_VER
+	string "Core version number"
+	default "7.10.d"
+
+endif
diff --git a/roms/u-boot/board/xilinx/microblaze-generic/MAINTAINERS b/roms/u-boot/board/xilinx/microblaze-generic/MAINTAINERS
new file mode 100644
index 000000000..29ed32f78
--- /dev/null
+++ b/roms/u-boot/board/xilinx/microblaze-generic/MAINTAINERS
@@ -0,0 +1,7 @@
+MICROBLAZE-GENERIC BOARD
+M:	Michal Simek <monstr@monstr.eu>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+F:	board/xilinx/microblaze-generic/
+F:	include/configs/microblaze-generic.h
+F:	configs/microblaze-generic_defconfig
diff --git a/roms/u-boot/board/xilinx/microblaze-generic/Makefile b/roms/u-boot/board/xilinx/microblaze-generic/Makefile
new file mode 100644
index 000000000..cfd833752
--- /dev/null
+++ b/roms/u-boot/board/xilinx/microblaze-generic/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= microblaze-generic.o
diff --git a/roms/u-boot/board/xilinx/microblaze-generic/config.mk b/roms/u-boot/board/xilinx/microblaze-generic/config.mk
new file mode 100644
index 000000000..a9539776d
--- /dev/null
+++ b/roms/u-boot/board/xilinx/microblaze-generic/config.mk
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2007 - 2016 Michal Simek
+#
+# Michal SIMEK <monstr@monstr.eu>
+
+CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
+
+# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
+CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
+
+CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
+
+PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
diff --git a/roms/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c b/roms/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c
new file mode 100644
index 000000000..a427ac94a
--- /dev/null
+++ b/roms/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2018 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ */
+
+/*
+ * This is a board specific file.  It's OK to include board specific
+ * header files
+ */
+
+#include <common.h>
+#include <config.h>
+#include <env.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <dm/lists.h>
+#include <fdtdec.h>
+#include <linux/sizes.h>
+#include "../common/board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+};
+
+int board_late_init(void)
+{
+	ulong max_size;
+	u32 status = 0;
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE)
+	int ret;
+
+	ret = device_bind_driver(gd->dm_root, "mb_soft_reset",
+				 "reset_soft", NULL);
+	if (ret)
+		printf("Warning: No reset driver: ret=%d\n", ret);
+#endif
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
+
+	max_size = gd->start_addr_sp - CONFIG_STACK_SIZE;
+	max_size = round_down(max_size, SZ_16M);
+
+	status |= env_set_hex("scriptaddr", max_size + SZ_2M);
+
+	status |= env_set_hex("pxefile_addr_r", max_size + SZ_1M);
+
+	status |= env_set_hex("kernel_addr_r", gd->ram_base + SZ_32M);
+
+	status |= env_set_hex("fdt_addr_r", gd->ram_base + SZ_32M - SZ_1M);
+
+	status |= env_set_hex("ramdisk_addr_r",
+			       gd->ram_base + SZ_32M + SZ_4M + SZ_2M);
+	if (IS_ENABLED(CONFIG_MTD_NOR_FLASH))
+		status |= env_set_hex("script_offset_nor",
+				       gd->bd->bi_flashstart +
+				       CONFIG_BOOT_SCRIPT_OFFSET);
+	if (status)
+		printf("%s: Saving run time variables FAILED\n", __func__);
+
+	return board_late_init_xilinx();
+}
diff --git a/roms/u-boot/board/xilinx/versal/Kconfig b/roms/u-boot/board/xilinx/versal/Kconfig
new file mode 100644
index 000000000..c0cccc206
--- /dev/null
+++ b/roms/u-boot/board/xilinx/versal/Kconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2020, Xilinx, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_VERSAL
+
+config CMD_VERSAL
+	bool "Enable Versal specific commands"
+	default y
+	depends on ZYNQMP_FIRMWARE
+	help
+	  Enable Versal specific commands.
+
+endif
diff --git a/roms/u-boot/board/xilinx/versal/MAINTAINERS b/roms/u-boot/board/xilinx/versal/MAINTAINERS
new file mode 100644
index 000000000..bbab05136
--- /dev/null
+++ b/roms/u-boot/board/xilinx/versal/MAINTAINERS
@@ -0,0 +1,8 @@
+XILINX_VERSAL BOARDS
+M:	Michal Simek <michal.simek@xilinx.com>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+F:	arch/arm/dts/versal*
+F:	board/xilinx/versal/
+F:	include/configs/xilinx_versal*
+F:	configs/xilinx_versal*
diff --git a/roms/u-boot/board/xilinx/versal/Makefile b/roms/u-boot/board/xilinx/versal/Makefile
new file mode 100644
index 000000000..4a46ca02d
--- /dev/null
+++ b/roms/u-boot/board/xilinx/versal/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 - 2018 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+#
+
+obj-y	:= board.o
+obj-$(CONFIG_CMD_VERSAL)	+= cmds.o
diff --git a/roms/u-boot/board/xilinx/versal/board.c b/roms/u-boot/board/xilinx/versal/board.c
new file mode 100644
index 000000000..6045eb2ba
--- /dev/null
+++ b/roms/u-boot/board/xilinx/versal/board.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 - 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <env_internal.h>
+#include <log.h>
+#include <malloc.h>
+#include <time.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <versalpl.h>
+#include "../common/board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA_VERSALPL)
+static xilinx_desc versalpl = XILINX_VERSAL_DESC;
+#endif
+
+int board_init(void)
+{
+	printf("EL Level:\tEL%d\n", current_el());
+
+#if defined(CONFIG_FPGA_VERSALPL)
+	fpga_init();
+	fpga_add(fpga_xilinx, &versalpl);
+#endif
+
+	if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
+		xilinx_read_eeprom();
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	u32 val;
+
+	if (current_el() != 3)
+		return 0;
+
+	debug("iou_switch ctrl div0 %x\n",
+	      readl(&crlapb_base->iou_switch_ctrl));
+
+	writel(IOU_SWITCH_CTRL_CLKACT_BIT |
+	       (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
+	       &crlapb_base->iou_switch_ctrl);
+
+	/* Global timer init - Program time stamp reference clk */
+	val = readl(&crlapb_base->timestamp_ref_ctrl);
+	val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
+	writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+	debug("ref ctrl 0x%x\n",
+	      readl(&crlapb_base->timestamp_ref_ctrl));
+
+	/* Clear reset of timestamp reg */
+	writel(0, &crlapb_base->rst_timestamp);
+
+	/*
+	 * Program freq register in System counter and
+	 * enable system counter.
+	 */
+	writel(COUNTER_FREQUENCY,
+	       &iou_scntr_secure->base_frequency_id_register);
+
+	debug("counter val 0x%x\n",
+	      readl(&iou_scntr_secure->base_frequency_id_register));
+
+	writel(IOU_SCNTRS_CONTROL_EN,
+	       &iou_scntr_secure->counter_control_register);
+
+	debug("scntrs control 0x%x\n",
+	      readl(&iou_scntr_secure->counter_control_register));
+	debug("timer 0x%llx\n", get_ticks());
+	debug("timer 0x%llx\n", get_ticks());
+
+	return 0;
+}
+
+static u8 versal_get_bootmode(void)
+{
+	u8 bootmode;
+	u32 reg = 0;
+
+	reg = readl(&crp_base->boot_mode_usr);
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
+int board_late_init(void)
+{
+	u8 bootmode;
+	struct udevice *dev;
+	int bootseq = -1;
+	int bootseq_len = 0;
+	int env_targets_len = 0;
+	const char *mode;
+	char *new_targets;
+	char *env_targets;
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
+
+	if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
+		return 0;
+
+	bootmode = versal_get_bootmode();
+
+	puts("Bootmode: ");
+	switch (bootmode) {
+	case USB_MODE:
+		puts("USB_MODE\n");
+		mode = "usb_dfu0 usb_dfu1";
+		break;
+	case JTAG_MODE:
+		puts("JTAG_MODE\n");
+		mode = "jtag pxe dhcp";
+		break;
+	case QSPI_MODE_24BIT:
+		puts("QSPI_MODE_24\n");
+		mode = "xspi0";
+		break;
+	case QSPI_MODE_32BIT:
+		puts("QSPI_MODE_32\n");
+		mode = "xspi0";
+		break;
+	case OSPI_MODE:
+		puts("OSPI_MODE\n");
+		mode = "xspi0";
+		break;
+	case EMMC_MODE:
+		puts("EMMC_MODE\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@f1050000", &dev)) {
+			puts("Boot from EMMC but without SD1 enabled!\n");
+			return -1;
+		}
+		debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		break;
+	case SD_MODE:
+		puts("SD_MODE\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@f1040000", &dev)) {
+			puts("Boot from SD0 but without SD0 enabled!\n");
+			return -1;
+		}
+		debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		break;
+	case SD1_LSHFT_MODE:
+		puts("LVL_SHFT_");
+		/* fall through */
+	case SD_MODE1:
+		puts("SD_MODE1\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@f1050000", &dev)) {
+			puts("Boot from SD1 but without SD1 enabled!\n");
+			return -1;
+		}
+		debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		break;
+	default:
+		mode = "";
+		printf("Invalid Boot Mode:0x%x\n", bootmode);
+		break;
+	}
+
+	if (bootseq >= 0) {
+		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
+		debug("Bootseq len: %x\n", bootseq_len);
+	}
+
+	/*
+	 * One terminating char + one byte for space between mode
+	 * and default boot_targets
+	 */
+	env_targets = env_get("boot_targets");
+	if (env_targets)
+		env_targets_len = strlen(env_targets);
+
+	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
+			     bootseq_len);
+	if (!new_targets)
+		return -ENOMEM;
+
+	if (bootseq >= 0)
+		sprintf(new_targets, "%s%x %s", mode, bootseq,
+			env_targets ? env_targets : "");
+	else
+		sprintf(new_targets, "%s %s", mode,
+			env_targets ? env_targets : "");
+
+	env_set("boot_targets", new_targets);
+
+	return board_late_init_xilinx();
+}
+
+int dram_init_banksize(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_memory_banksize();
+	if (ret)
+		return ret;
+
+	mem_map_fill();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base_lowest() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	u32 bootmode = versal_get_bootmode();
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	switch (bootmode) {
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD1_LSHFT_MODE:
+	case SD_MODE1:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+			return ENVL_FAT;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+			return ENVL_EXT4;
+		return ENVL_UNKNOWN;
+	case OSPI_MODE:
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		return ENVL_UNKNOWN;
+	case JTAG_MODE:
+	default:
+		return ENVL_NOWHERE;
+	}
+}
diff --git a/roms/u-boot/board/xilinx/versal/cmds.c b/roms/u-boot/board/xilinx/versal/cmds.c
new file mode 100644
index 000000000..f5735d0c6
--- /dev/null
+++ b/roms/u-boot/board/xilinx/versal/cmds.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2020 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <cpu_func.h>
+#include <command.h>
+#include <common.h>
+#include <log.h>
+#include <memalign.h>
+#include <versalpl.h>
+#include <zynqmp_firmware.h>
+
+static int do_versal_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
+			      char * const argv[])
+{
+	u32 buf_lo, buf_hi;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	ulong addr, *pdi_buf;
+	size_t len;
+	int ret;
+
+	if (argc != cmdtp->maxargs) {
+		debug("pdi_load: incorrect parameters passed\n");
+		return CMD_RET_USAGE;
+	}
+
+	addr = simple_strtol(argv[2], NULL, 16);
+	if (!addr) {
+		debug("pdi_load: zero pdi_data address\n");
+		return CMD_RET_USAGE;
+	}
+
+	len = simple_strtoul(argv[3], NULL, 16);
+	if (!len) {
+		debug("pdi_load: zero size\n");
+		return CMD_RET_USAGE;
+	}
+
+	pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
+	if ((ulong)addr != (ulong)pdi_buf) {
+		memcpy((void *)pdi_buf, (void *)addr, len);
+		debug("Pdi addr:0x%lx aligned to 0x%lx\n",
+		      addr, (ulong)pdi_buf);
+	}
+
+	flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
+
+	buf_lo = lower_32_bits((ulong)pdi_buf);
+	buf_hi = upper_32_bits((ulong)pdi_buf);
+
+	ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
+				buf_hi, 0, ret_payload);
+	if (ret)
+		printf("PDI load failed with err: 0x%08x\n", ret);
+
+	return ret;
+}
+
+static struct cmd_tbl cmd_versal_sub[] = {
+	U_BOOT_CMD_MKENT(loadpdi, 4, 1, do_versal_load_pdi, "", ""),
+};
+
+/**
+ * do_versal - Handle the "versal" command-line command
+ * @cmdtp:      Command data struct pointer
+ * @flag:       Command flag
+ * @argc:       Command-line argument count
+ * @argv:       Array of command-line arguments
+ *
+ * Processes the versal specific commands
+ *
+ * Return: return 0 on success, Error value if command fails.
+ * CMD_RET_USAGE incase of incorrect/missing parameters.
+ */
+static int do_versal(struct cmd_tbl *cmdtp, int flag, int argc,
+		     char *const argv[])
+{
+	struct cmd_tbl *c;
+	int ret = CMD_RET_USAGE;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	c = find_cmd_tbl(argv[1], &cmd_versal_sub[0],
+			 ARRAY_SIZE(cmd_versal_sub));
+	if (c)
+		ret = c->cmd(c, flag, argc, argv);
+
+	return cmd_process_error(c, ret);
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char versal_help_text[] =
+	"loadpdi addr len - Load pdi image\n"
+	"load pdi image at ddr address 'addr' with pdi image size 'len'\n"
+;
+#endif
+
+U_BOOT_CMD(versal, 4, 1, do_versal,
+	   "versal sub-system",
+	   versal_help_text
+)
+
diff --git a/roms/u-boot/board/xilinx/zynq/.gitignore b/roms/u-boot/board/xilinx/zynq/.gitignore
new file mode 100644
index 000000000..ab66a7f2a
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/.gitignore
@@ -0,0 +1 @@
+/ps7_init_gpl.[ch]
diff --git a/roms/u-boot/board/xilinx/zynq/Kconfig b/roms/u-boot/board/xilinx/zynq/Kconfig
new file mode 100644
index 000000000..d6f40631c
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/Kconfig
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2018, Xilinx, Inc.
+
+if ARCH_ZYNQ
+
+config CMD_ZYNQ
+	bool "Enable Zynq specific commands"
+	default y
+	help
+	  Enables Zynq specific commands.
+
+config CMD_ZYNQ_AES
+	bool "Enable zynq aes command for decryption of encrypted images"
+	depends on CMD_ZYNQ
+	depends on FPGA_ZYNQPL
+	help
+	  Decrypts the encrypted image present in source address
+	  and places the decrypted image at destination address.
+
+config CMD_ZYNQ_RSA
+	bool "Enable zynq rsa command for loading secure images"
+	default y
+	depends on CMD_ZYNQ
+	depends on CMD_ZYNQ_AES
+	help
+	  Enabling this will support zynq secure image verification.
+	  The secure image is a xilinx specific BOOT.BIN with
+	  either authentication or encryption or both encryption
+	  and authentication feature enabled while generating
+	  BOOT.BIN using Xilinx bootgen tool.
+
+endif
diff --git a/roms/u-boot/board/xilinx/zynq/MAINTAINERS b/roms/u-boot/board/xilinx/zynq/MAINTAINERS
new file mode 100644
index 000000000..b5b9e2fe4
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/MAINTAINERS
@@ -0,0 +1,9 @@
+ZYNQ BOARD
+M:	Michal Simek <monstr@monstr.eu>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+F:	arch/arm/dts/zynq-*
+F:	board/xilinx/zynq/
+F:	include/configs/zynq*.h
+F:	configs/zynq_*_defconfig
+F:	configs/xilinx_zynq_*
diff --git a/roms/u-boot/board/xilinx/zynq/Makefile b/roms/u-boot/board/xilinx/zynq/Makefile
new file mode 100644
index 000000000..856617158
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/Makefile
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= board.o
+
+ifneq ($(CONFIG_XILINX_PS_INIT_FILE),"")
+PS_INIT_FILE := $(shell cd $(srctree); readlink -f $(CONFIG_XILINX_PS_INIT_FILE))
+init-objs := ps_init_gpl.o
+spl/board/xilinx/zynq/ps_init_gpl.o board/xilinx/zynq/ps_init_gpl.o: $(PS_INIT_FILE)
+	$(CC) $(c_flags) -I $(srctree)/$(src) -c -o $@ $^
+endif
+
+DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
+ifeq ($(DEVICE_TREE),)
+DEVICE_TREE := unset
+endif
+
+ifeq ($(init-objs),)
+hw-platform-y :=$(shell echo $(DEVICE_TREE))
+init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
+	$(hw-platform-y)/ps7_init_gpl.o)
+endif
+
+ifeq ($(init-objs),)
+ifneq ($(wildcard $(srctree)/$(src)/ps7_init_gpl.c),)
+init-objs := ps7_init_gpl.o
+$(if $(CONFIG_SPL_BUILD),\
+$(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custom_hw_platform/))
+endif
+endif
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_ZYNQ) += cmds.o
+obj-$(CONFIG_CMD_ZYNQ_RSA) += bootimg.o
+endif
+
+obj-$(CONFIG_SPL_BUILD) += $(init-objs)
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
+
+# To include xil_io.h
+CFLAGS_ps7_init_gpl.o := -I$(srctree)/$(src)
diff --git a/roms/u-boot/board/xilinx/zynq/board.c b/roms/u-boot/board/xilinx/zynq/board.c
new file mode 100644
index 000000000..e2e9b3f0f
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/board.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ * (C) Copyright 2013 - 2018 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <env_internal.h>
+#include <fdtdec.h>
+#include <fpga.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <watchdog.h>
+#include <wdt.h>
+#include <zynqpl.h>
+#include <asm/global_data.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include "../common/board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		printf("Silicon version:\t%d\n", zynq_get_silicon_version());
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	int env_targets_len = 0;
+	const char *mode;
+	char *new_targets;
+	char *env_targets;
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
+
+	if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
+		return 0;
+
+	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+	case ZYNQ_BM_QSPI:
+		mode = "qspi";
+		env_set("modeboot", "qspiboot");
+		break;
+	case ZYNQ_BM_NAND:
+		mode = "nand";
+		env_set("modeboot", "nandboot");
+		break;
+	case ZYNQ_BM_NOR:
+		mode = "nor";
+		env_set("modeboot", "norboot");
+		break;
+	case ZYNQ_BM_SD:
+		mode = "mmc0";
+		env_set("modeboot", "sdboot");
+		break;
+	case ZYNQ_BM_JTAG:
+		mode = "jtag pxe dhcp";
+		env_set("modeboot", "jtagboot");
+		break;
+	default:
+		mode = "";
+		env_set("modeboot", "");
+		break;
+	}
+
+	/*
+	 * One terminating char + one byte for space between mode
+	 * and default boot_targets
+	 */
+	env_targets = env_get("boot_targets");
+	if (env_targets)
+		env_targets_len = strlen(env_targets);
+
+	new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
+	if (!new_targets)
+		return -ENOMEM;
+
+	sprintf(new_targets, "%s %s", mode,
+		env_targets ? env_targets : "");
+
+	env_set("boot_targets", new_targets);
+
+	return board_late_init_xilinx();
+}
+
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	zynq_ddrc_init();
+
+	return 0;
+}
+#else
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	zynq_ddrc_init();
+
+	return 0;
+}
+#endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	u32 bootmode = zynq_slcr_get_boot_mode() & ZYNQ_BM_MASK;
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	switch (bootmode) {
+	case ZYNQ_BM_SD:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+			return ENVL_FAT;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+			return ENVL_EXT4;
+		return ENVL_UNKNOWN;
+	case ZYNQ_BM_NAND:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
+			return ENVL_NAND;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
+			return ENVL_UBI;
+		return ENVL_UNKNOWN;
+	case ZYNQ_BM_NOR:
+	case ZYNQ_BM_QSPI:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		return ENVL_UNKNOWN;
+	case ZYNQ_BM_JTAG:
+	default:
+		return ENVL_NOWHERE;
+	}
+}
diff --git a/roms/u-boot/board/xilinx/zynq/bootimg.c b/roms/u-boot/board/xilinx/zynq/bootimg.c
new file mode 100644
index 000000000..2f55078dd
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/bootimg.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <log.h>
+#include <part.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <u-boot/md5.h>
+#include <zynq_bootimg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ZYNQ_IMAGE_PHDR_OFFSET		0x09C
+#define ZYNQ_IMAGE_FSBL_LEN_OFFSET	0x040
+#define ZYNQ_PART_HDR_CHKSUM_WORD_COUNT	0x0F
+#define ZYNQ_PART_HDR_WORD_COUNT	0x10
+#define ZYNQ_MAXIMUM_IMAGE_WORD_LEN	0x40000000
+#define MD5_CHECKSUM_SIZE	16
+
+struct headerarray {
+	u32 fields[16];
+};
+
+/*
+ * Check whether the given partition is last partition or not
+ */
+static int zynq_islastpartition(struct headerarray *head)
+{
+	int index;
+
+	debug("%s\n", __func__);
+	if (head->fields[ZYNQ_PART_HDR_CHKSUM_WORD_COUNT] != 0xFFFFFFFF)
+		return -1;
+
+	for (index = 0; index < ZYNQ_PART_HDR_WORD_COUNT - 1; index++) {
+		if (head->fields[index] != 0x0)
+			return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * Get the partition count from the partition header
+ */
+int zynq_get_part_count(struct partition_hdr *part_hdr_info)
+{
+	u32 count;
+	struct headerarray *hap;
+
+	debug("%s\n", __func__);
+
+	for (count = 0; count < ZYNQ_MAX_PARTITION_NUMBER; count++) {
+		hap = (struct headerarray *)&part_hdr_info[count];
+		if (zynq_islastpartition(hap) != -1)
+			break;
+	}
+
+	return count;
+}
+
+/*
+ * Get the partition info of all the partitions available.
+ */
+int zynq_get_partition_info(u32 image_base_addr, u32 *fsbl_len,
+			    struct partition_hdr *part_hdr)
+{
+	u32 parthdroffset;
+
+	*fsbl_len = *((u32 *)(image_base_addr + ZYNQ_IMAGE_FSBL_LEN_OFFSET));
+
+	parthdroffset = *((u32 *)(image_base_addr + ZYNQ_IMAGE_PHDR_OFFSET));
+
+	parthdroffset += image_base_addr;
+
+	memcpy(part_hdr, (u32 *)parthdroffset,
+	       (sizeof(struct partition_hdr) * ZYNQ_MAX_PARTITION_NUMBER));
+
+	return 0;
+}
+
+/*
+ * Check whether the partition header is valid or not
+ */
+int zynq_validate_hdr(struct partition_hdr *header)
+{
+	struct headerarray *hap;
+	u32 index;
+	u32 checksum;
+
+	debug("%s\n", __func__);
+
+	hap = (struct headerarray *)header;
+
+	for (index = 0; index < ZYNQ_PART_HDR_WORD_COUNT; index++) {
+		if (hap->fields[index])
+			break;
+	}
+	if (index == ZYNQ_PART_HDR_WORD_COUNT)
+		return -1;
+
+	checksum = 0;
+	for (index = 0; index < ZYNQ_PART_HDR_CHKSUM_WORD_COUNT; index++)
+		checksum += hap->fields[index];
+
+	checksum ^= 0xFFFFFFFF;
+
+	if (hap->fields[ZYNQ_PART_HDR_CHKSUM_WORD_COUNT] != checksum) {
+		printf("Error: Checksum 0x%8.8x != 0x%8.8x\n",
+		       checksum, hap->fields[ZYNQ_PART_HDR_CHKSUM_WORD_COUNT]);
+		return -1;
+	}
+
+	if (header->imagewordlen > ZYNQ_MAXIMUM_IMAGE_WORD_LEN) {
+		printf("INVALID_PARTITION_LENGTH\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * Validate the partition by calculationg the md5 checksum for the
+ * partition and compare with checksum present in checksum offset of
+ * partition
+ */
+int zynq_validate_partition(u32 start_addr, u32 len, u32 chksum_off)
+{
+	u8 checksum[MD5_CHECKSUM_SIZE];
+	u8 calchecksum[MD5_CHECKSUM_SIZE];
+
+	memcpy(&checksum[0], (u32 *)chksum_off, MD5_CHECKSUM_SIZE);
+
+	md5_wd((u8 *)start_addr, len, &calchecksum[0], 0x10000);
+
+	if (!memcmp(checksum, calchecksum, MD5_CHECKSUM_SIZE))
+		return 0;
+
+	printf("Error: Partition DataChecksum\n");
+	return -1;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/cmds.c b/roms/u-boot/board/xilinx/zynq/cmds.c
new file mode 100644
index 000000000..6c697caa6
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/cmds.c
@@ -0,0 +1,553 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <malloc.h>
+#include <linux/bitops.h>
+#include <u-boot/md5.h>
+#include <u-boot/rsa.h>
+#include <u-boot/rsa-mod-exp.h>
+#include <u-boot/sha256.h>
+#include <zynqpl.h>
+#include <fpga.h>
+#include <zynq_bootimg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_ZYNQ_RSA
+
+#define ZYNQ_EFUSE_RSA_ENABLE_MASK	0x400
+#define ZYNQ_ATTRIBUTE_PL_IMAGE_MASK		0x20
+#define ZYNQ_ATTRIBUTE_CHECKSUM_TYPE_MASK	0x7000
+#define ZYNQ_ATTRIBUTE_RSA_PRESENT_MASK		0x8000
+#define ZYNQ_ATTRIBUTE_RSA_PART_OWNER_MASK	0x30000
+
+#define ZYNQ_RSA_MODULAR_SIZE			256
+#define ZYNQ_RSA_MODULAR_EXT_SIZE		256
+#define ZYNQ_RSA_EXPO_SIZE			64
+#define ZYNQ_RSA_SPK_SIGNATURE_SIZE		256
+#define ZYNQ_RSA_PARTITION_SIGNATURE_SIZE	256
+#define ZYNQ_RSA_SIGNATURE_SIZE			0x6C0
+#define ZYNQ_RSA_HEADER_SIZE			4
+#define ZYNQ_RSA_MAGIC_WORD_SIZE		60
+#define ZYNQ_RSA_PART_OWNER_UBOOT		1
+#define ZYNQ_RSA_ALIGN_PPK_START		64
+
+#define WORD_LENGTH_SHIFT	2
+
+static u8 *ppkmodular;
+static u8 *ppkmodularex;
+
+struct zynq_rsa_public_key {
+	uint len;		/* Length of modulus[] in number of u32 */
+	u32 n0inv;		/* -1 / modulus[0] mod 2^32 */
+	u32 *modulus;	/* modulus as little endian array */
+	u32 *rr;		/* R^2 as little endian array */
+};
+
+static struct zynq_rsa_public_key public_key;
+
+static struct partition_hdr part_hdr[ZYNQ_MAX_PARTITION_NUMBER];
+
+/*
+ * Extract the primary public key components from already autheticated FSBL
+ */
+static void zynq_extract_ppk(u32 fsbl_len)
+{
+	u32 padsize;
+	u8 *ppkptr;
+
+	debug("%s\n", __func__);
+
+	/*
+	 * Extract the authenticated PPK from OCM i.e at end of the FSBL
+	 */
+	ppkptr = (u8 *)(fsbl_len + ZYNQ_OCM_BASEADDR);
+	padsize = ((u32)ppkptr % ZYNQ_RSA_ALIGN_PPK_START);
+	if (padsize)
+		ppkptr += (ZYNQ_RSA_ALIGN_PPK_START - padsize);
+
+	ppkptr += ZYNQ_RSA_HEADER_SIZE;
+
+	ppkptr += ZYNQ_RSA_MAGIC_WORD_SIZE;
+
+	ppkmodular = (u8 *)ppkptr;
+	ppkptr += ZYNQ_RSA_MODULAR_SIZE;
+	ppkmodularex = (u8 *)ppkptr;
+	ppkptr += ZYNQ_RSA_MODULAR_EXT_SIZE;
+}
+
+/*
+ * Calculate the inverse(-1 / modulus[0] mod 2^32 ) for the PPK
+ */
+static u32 zynq_calc_inv(void)
+{
+	u32 modulus = public_key.modulus[0];
+	u32 tmp = BIT(1);
+	u32 inverse;
+
+	inverse = modulus & BIT(0);
+
+	while (tmp) {
+		inverse *= 2 - modulus * inverse;
+		tmp *= tmp;
+	}
+
+	return ~(inverse - 1);
+}
+
+/*
+ * Recreate the signature by padding the bytes and verify with hash value
+ */
+static int zynq_pad_and_check(u8 *signature, u8 *hash)
+{
+	u8 padding[] = {0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48,
+			0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04,
+			0x20};
+	u8 *pad_ptr = signature + 256;
+	u32 pad = 202;
+	u32 ii;
+
+	/*
+	 * Re-Create PKCS#1v1.5 Padding
+	 * MSB  ----------------------------------------------------LSB
+	 * 0x0 || 0x1 || 0xFF(for 202 bytes) || 0x0 || T_padding || SHA256 Hash
+	 */
+	if (*--pad_ptr != 0 || *--pad_ptr != 1)
+		return -1;
+
+	for (ii = 0; ii < pad; ii++) {
+		if (*--pad_ptr != 0xFF)
+			return -1;
+	}
+
+	if (*--pad_ptr != 0)
+		return -1;
+
+	for (ii = 0; ii < sizeof(padding); ii++) {
+		if (*--pad_ptr != padding[ii])
+			return -1;
+	}
+
+	for (ii = 0; ii < 32; ii++) {
+		if (*--pad_ptr != hash[ii])
+			return -1;
+	}
+	return 0;
+}
+
+/*
+ * Verify and extract the hash value from signature using the public key
+ * and compare it with calculated hash value.
+ */
+static int zynq_rsa_verify_key(const struct zynq_rsa_public_key *key,
+			       const u8 *sig, const u32 sig_len, const u8 *hash)
+{
+	int status;
+	void *buf;
+
+	if (!key || !sig || !hash)
+		return -1;
+
+	if (sig_len != (key->len * sizeof(u32))) {
+		printf("Signature is of incorrect length %d\n", sig_len);
+		return -1;
+	}
+
+	/* Sanity check for stack size */
+	if (sig_len > ZYNQ_RSA_SPK_SIGNATURE_SIZE) {
+		printf("Signature length %u exceeds maximum %d\n", sig_len,
+		       ZYNQ_RSA_SPK_SIGNATURE_SIZE);
+		return -1;
+	}
+
+	buf = malloc(sig_len);
+	if (!buf)
+		return -1;
+
+	memcpy(buf, sig, sig_len);
+
+	status = zynq_pow_mod((u32 *)key, (u32 *)buf);
+	if (status == -1) {
+		free(buf);
+		return status;
+	}
+
+	status = zynq_pad_and_check((u8 *)buf, (u8 *)hash);
+
+	free(buf);
+	return status;
+}
+
+/*
+ * Authenticate the partition
+ */
+static int zynq_authenticate_part(u8 *buffer, u32 size)
+{
+	u8 hash_signature[32];
+	u8 *spk_modular;
+	u8 *spk_modular_ex;
+	u8 *signature_ptr;
+	u32 status;
+
+	debug("%s\n", __func__);
+
+	signature_ptr = (u8 *)(buffer + size - ZYNQ_RSA_SIGNATURE_SIZE);
+
+	signature_ptr += ZYNQ_RSA_HEADER_SIZE;
+
+	signature_ptr += ZYNQ_RSA_MAGIC_WORD_SIZE;
+
+	ppkmodular = (u8 *)signature_ptr;
+	signature_ptr += ZYNQ_RSA_MODULAR_SIZE;
+	ppkmodularex = signature_ptr;
+	signature_ptr += ZYNQ_RSA_MODULAR_EXT_SIZE;
+	signature_ptr += ZYNQ_RSA_EXPO_SIZE;
+
+	sha256_csum_wd((const unsigned char *)signature_ptr,
+		       (ZYNQ_RSA_MODULAR_EXT_SIZE + ZYNQ_RSA_EXPO_SIZE +
+		       ZYNQ_RSA_MODULAR_SIZE),
+		       (unsigned char *)hash_signature, 0x1000);
+
+	spk_modular = (u8 *)signature_ptr;
+	signature_ptr += ZYNQ_RSA_MODULAR_SIZE;
+	spk_modular_ex = (u8 *)signature_ptr;
+	signature_ptr += ZYNQ_RSA_MODULAR_EXT_SIZE;
+	signature_ptr += ZYNQ_RSA_EXPO_SIZE;
+
+	public_key.len = ZYNQ_RSA_MODULAR_SIZE / sizeof(u32);
+	public_key.modulus = (u32 *)ppkmodular;
+	public_key.rr = (u32 *)ppkmodularex;
+	public_key.n0inv = zynq_calc_inv();
+
+	status = zynq_rsa_verify_key(&public_key, signature_ptr,
+				     ZYNQ_RSA_SPK_SIGNATURE_SIZE,
+				     hash_signature);
+	if (status)
+		return status;
+
+	signature_ptr += ZYNQ_RSA_SPK_SIGNATURE_SIZE;
+
+	sha256_csum_wd((const unsigned char *)buffer,
+		       (size - ZYNQ_RSA_PARTITION_SIGNATURE_SIZE),
+		       (unsigned char *)hash_signature, 0x1000);
+
+	public_key.len = ZYNQ_RSA_MODULAR_SIZE / sizeof(u32);
+	public_key.modulus = (u32 *)spk_modular;
+	public_key.rr = (u32 *)spk_modular_ex;
+	public_key.n0inv = zynq_calc_inv();
+
+	return zynq_rsa_verify_key(&public_key, (u8 *)signature_ptr,
+				   ZYNQ_RSA_PARTITION_SIGNATURE_SIZE,
+				   (u8 *)hash_signature);
+}
+
+/*
+ * Parses the partition header and verfies the authenticated and
+ * encrypted image.
+ */
+static int zynq_verify_image(u32 src_ptr)
+{
+	u32 silicon_ver, image_base_addr, status;
+	u32 partition_num = 0;
+	u32 efuseval, srcaddr, size, fsbl_len;
+	struct partition_hdr *hdr_ptr;
+	u32 part_data_len, part_img_len, part_attr;
+	u32 part_load_addr, part_dst_addr, part_chksum_offset;
+	u32 part_start_addr, part_total_size, partitioncount;
+	bool encrypt_part_flag = false;
+	bool part_chksum_flag = false;
+	bool signed_part_flag = false;
+
+	image_base_addr = src_ptr;
+
+	silicon_ver = zynq_get_silicon_version();
+
+	/* RSA not supported in silicon versions 1.0 and 2.0 */
+	if (silicon_ver == 0 || silicon_ver == 1)
+		return -1;
+
+	zynq_get_partition_info(image_base_addr, &fsbl_len,
+				&part_hdr[0]);
+
+	/* Extract ppk if efuse was blown Otherwise return error */
+	efuseval = readl(&efuse_base->status);
+	if (!(efuseval & ZYNQ_EFUSE_RSA_ENABLE_MASK))
+		return -1;
+
+	zynq_extract_ppk(fsbl_len);
+
+	partitioncount = zynq_get_part_count(&part_hdr[0]);
+
+	/*
+	 * As the first two partitions are related to fsbl,
+	 * we can ignore those two in bootimage and the below
+	 * code doesn't need to validate it as fsbl is already
+	 * done by now
+	 */
+	if (partitioncount <= 2 ||
+	    partitioncount > ZYNQ_MAX_PARTITION_NUMBER)
+		return -1;
+
+	while (partition_num < partitioncount) {
+		if (((part_hdr[partition_num].partitionattr &
+		   ZYNQ_ATTRIBUTE_RSA_PART_OWNER_MASK) >> 16) !=
+		   ZYNQ_RSA_PART_OWNER_UBOOT) {
+			printf("UBOOT is not Owner for partition %d\n",
+			       partition_num);
+			partition_num++;
+			continue;
+		}
+		hdr_ptr = &part_hdr[partition_num];
+		status = zynq_validate_hdr(hdr_ptr);
+		if (status)
+			return status;
+
+		part_data_len = hdr_ptr->datawordlen;
+		part_img_len = hdr_ptr->imagewordlen;
+		part_attr = hdr_ptr->partitionattr;
+		part_load_addr = hdr_ptr->loadaddr;
+		part_chksum_offset = hdr_ptr->checksumoffset;
+		part_start_addr = hdr_ptr->partitionstart;
+		part_total_size = hdr_ptr->partitionwordlen;
+
+		if (part_data_len != part_img_len) {
+			debug("Encrypted\n");
+			encrypt_part_flag = true;
+		}
+
+		if (part_attr & ZYNQ_ATTRIBUTE_CHECKSUM_TYPE_MASK)
+			part_chksum_flag = true;
+
+		if (part_attr & ZYNQ_ATTRIBUTE_RSA_PRESENT_MASK) {
+			debug("RSA Signed\n");
+			signed_part_flag = true;
+			size = part_total_size << WORD_LENGTH_SHIFT;
+		} else {
+			size = part_img_len;
+		}
+
+		if (!signed_part_flag && !part_chksum_flag) {
+			printf("Partition not signed & no chksum\n");
+			partition_num++;
+			continue;
+		}
+
+		srcaddr = image_base_addr +
+			  (part_start_addr << WORD_LENGTH_SHIFT);
+
+		/*
+		 * This validation is just for PS DDR.
+		 * TODO: Update this for PL DDR check as well.
+		 */
+		if (part_load_addr < gd->bd->bi_dram[0].start &&
+		    ((part_load_addr + part_data_len) >
+		    (gd->bd->bi_dram[0].start +
+		     gd->bd->bi_dram[0].size))) {
+			printf("INVALID_LOAD_ADDRESS_FAIL\n");
+			return -1;
+		}
+
+		if (part_attr & ZYNQ_ATTRIBUTE_PL_IMAGE_MASK)
+			part_load_addr = srcaddr;
+		else
+			memcpy((u32 *)part_load_addr, (u32 *)srcaddr,
+			       size);
+
+		if (part_chksum_flag) {
+			part_chksum_offset = image_base_addr +
+					     (part_chksum_offset <<
+					     WORD_LENGTH_SHIFT);
+			status = zynq_validate_partition(part_load_addr,
+							 (part_total_size <<
+							  WORD_LENGTH_SHIFT),
+							 part_chksum_offset);
+			if (status != 0) {
+				printf("PART_CHKSUM_FAIL\n");
+				return -1;
+			}
+			debug("Partition Validation Done\n");
+		}
+
+		if (signed_part_flag) {
+			status = zynq_authenticate_part((u8 *)part_load_addr,
+							size);
+			if (status != 0) {
+				printf("AUTHENTICATION_FAIL\n");
+				return -1;
+			}
+			debug("Authentication Done\n");
+		}
+
+		if (encrypt_part_flag) {
+			debug("DECRYPTION\n");
+
+			part_dst_addr = part_load_addr;
+
+			if (part_attr & ZYNQ_ATTRIBUTE_PL_IMAGE_MASK) {
+				partition_num++;
+				continue;
+			}
+
+			status = zynq_decrypt_load(part_load_addr,
+						   part_img_len,
+						   part_dst_addr,
+						   part_data_len,
+						   BIT_NONE);
+			if (status != 0) {
+				printf("DECRYPTION_FAIL\n");
+				return -1;
+			}
+		}
+		partition_num++;
+	}
+
+	return 0;
+}
+
+static int do_zynq_rsa(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	u32 src_ptr;
+	char *endp;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_FAILURE;
+
+	src_ptr = simple_strtoul(argv[2], &endp, 16);
+	if (*argv[2] == 0 || *endp != 0)
+		return CMD_RET_USAGE;
+
+	if (zynq_verify_image(src_ptr))
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+#endif
+
+#ifdef CONFIG_CMD_ZYNQ_AES
+static int zynq_decrypt_image(struct cmd_tbl *cmdtp, int flag, int argc,
+			      char *const argv[])
+{
+	char *endp;
+	u32 srcaddr, srclen, dstaddr, dstlen;
+	int status;
+	u8 imgtype = BIT_NONE;
+
+	if (argc < 5 && argc > cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	if (argc == 5) {
+		if (!strcmp("load", argv[2]))
+			imgtype = BIT_FULL;
+		else if (!strcmp("loadp", argv[2]))
+			imgtype = BIT_PARTIAL;
+		else
+			return CMD_RET_USAGE;
+
+		srcaddr = simple_strtoul(argv[3], &endp, 16);
+		if (*argv[3] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		srclen = simple_strtoul(argv[4], &endp, 16);
+		if (*argv[4] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+
+		dstaddr = 0xFFFFFFFF;
+		dstlen = srclen;
+	} else {
+		srcaddr = simple_strtoul(argv[2], &endp, 16);
+		if (*argv[2] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		srclen = simple_strtoul(argv[3], &endp, 16);
+		if (*argv[3] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		dstaddr = simple_strtoul(argv[4], &endp, 16);
+		if (*argv[4] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		dstlen = simple_strtoul(argv[5], &endp, 16);
+		if (*argv[5] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+	}
+
+	/*
+	 * Roundup source and destination lengths to
+	 * word size
+	 */
+	if (srclen % 4)
+		srclen = roundup(srclen, 4);
+	if (dstlen % 4)
+		dstlen = roundup(dstlen, 4);
+
+	status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr,
+				   dstlen >> 2, imgtype);
+	if (status != 0)
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+#endif
+
+static struct cmd_tbl zynq_commands[] = {
+#ifdef CONFIG_CMD_ZYNQ_RSA
+	U_BOOT_CMD_MKENT(rsa, 3, 1, do_zynq_rsa, "", ""),
+#endif
+#ifdef CONFIG_CMD_ZYNQ_AES
+	U_BOOT_CMD_MKENT(aes, 6, 1, zynq_decrypt_image, "", ""),
+#endif
+};
+
+static int do_zynq(struct cmd_tbl *cmdtp, int flag, int argc,
+		   char *const argv[])
+{
+	struct cmd_tbl *zynq_cmd;
+	int ret;
+
+	if (!ARRAY_SIZE(zynq_commands)) {
+		puts("No zynq specific command enabled\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	zynq_cmd = find_cmd_tbl(argv[1], zynq_commands,
+				ARRAY_SIZE(zynq_commands));
+	if (!zynq_cmd)
+		return CMD_RET_USAGE;
+
+	ret = zynq_cmd->cmd(zynq_cmd, flag, argc, argv);
+
+	return cmd_process_error(zynq_cmd, ret);
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char zynq_help_text[] =
+	""
+#ifdef CONFIG_CMD_ZYNQ_RSA
+	"rsa <baseaddr>  - Verifies the authenticated and encrypted\n"
+	"                  zynq images and loads them back to load\n"
+	"                  addresses as specified in BOOT image(BOOT.BIN)\n"
+#endif
+#ifdef CONFIG_CMD_ZYNQ_AES
+	"aes <srcaddr> <srclen> <dstaddr> <dstlen>\n"
+	"                - Decrypts the encrypted image present in source\n"
+	"                  address and places the decrypted image at\n"
+	"                  destination address\n"
+	"aes load <srcaddr> <srclen>\n"
+	"aes loadp <srcaddr> <srclen>\n"
+	"       if operation type is load or loadp, it loads the encrypted\n"
+	"       full or partial bitstream on to PL respectively.\n"
+#endif
+	;
+#endif
+
+U_BOOT_CMD(zynq,	6,	0,	do_zynq,
+	   "Zynq specific commands", zynq_help_text
+);
diff --git a/roms/u-boot/board/xilinx/zynq/xil_io.h b/roms/u-boot/board/xilinx/zynq/xil_io.h
new file mode 100644
index 000000000..e933f7b5f
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/xil_io.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H
+
+/*
+ * This empty file is here because ps7_init_gpl.c exported by hw project
+ * has #include "xil_io.h" line.
+ */
+
+#endif /* XIL_IO_H */
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
new file mode 100644
index 000000000..82f270c2e
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
@@ -0,0 +1,802 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74,  0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054,  0x00000007U),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74,  0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054,  0x00000007U),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74,  0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054,  0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	unsigned long *ps7_mio_init_data;
+	unsigned long *ps7_pll_init_data;
+	unsigned long *ps7_clock_init_data;
+	unsigned long *ps7_ddr_init_data;
+	unsigned long *ps7_peripherals_init_data;
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-cse-nand b/roms/u-boot/board/xilinx/zynq/zynq-cse-nand
new file mode 120000
index 000000000..9d89a9957
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-cse-nand
@@ -0,0 +1 @@
+zynq-zc770-xm011
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-cse-nor b/roms/u-boot/board/xilinx/zynq/zynq-cse-nor
new file mode 120000
index 000000000..bb80693ea
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-cse-nor
@@ -0,0 +1 @@
+zynq-zc770-xm012
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-cse-qspi-single b/roms/u-boot/board/xilinx/zynq/zynq-cse-qspi-single
new file mode 120000
index 000000000..764d14117
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-cse-qspi-single
@@ -0,0 +1 @@
+zynq-zc706
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
new file mode 100644
index 000000000..75095ee3d
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159AU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x000002E0U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x000012E1U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001240U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001240U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00001201U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001218U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	int ret = -1;
+
+	ret = ps7_config(ps7_post_config_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
new file mode 100644
index 000000000..337af2d96
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -0,0 +1,12491 @@
+// SPDX-License-Identifier: GPL-2.0+
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x1e
+    // .. ==> 0XF8000190[13:8] = 0x0000001EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001E00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+    // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+    // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+    // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002EC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+    // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000105U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+    // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000106U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+    // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000111U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+    // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000110U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 50
+    // .. ==> 0XF8000830[5:0] = 0x00000032U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000032U
+    // .. SDIO0_CD_SEL = 46
+    // .. ==> 0XF8000830[21:16] = 0x0000002EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x1e
+    // .. ==> 0XF8000190[13:8] = 0x0000001EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001E00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+    // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+    // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+    // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002EC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+    // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000105U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+    // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000106U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+    // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000111U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+    // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000110U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 50
+    // .. ==> 0XF8000830[5:0] = 0x00000032U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000032U
+    // .. SDIO0_CD_SEL = 46
+    // .. ==> 0XF8000830[21:16] = 0x0000002EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x1e
+    // .. ==> 0XF8000190[13:8] = 0x0000001EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001E00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+    // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+    // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+    // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002EC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+    // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000105U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+    // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000106U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+    // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000111U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+    // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000110U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 50
+    // .. ==> 0XF8000830[5:0] = 0x00000032U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000032U
+    // .. SDIO0_CD_SEL = 46
+    // .. ==> 0XF8000830[21:16] = 0x0000002EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+
+#include "xil_io.h"
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
new file mode 100644
index 000000000..248c72861
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
@@ -0,0 +1,12820 @@
+// SPDX-License-Identifier: GPL-2.0+
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF800015C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF800015C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800015C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xe
+    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF800015C[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+    // .. CAN0_MUX = 0x0
+    // .. ==> 0XF8000160[5:0] = 0x00000000U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+    // .. CAN0_REF_SEL = 0x0
+    // .. ==> 0XF8000160[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. CAN1_MUX = 0x0
+    // .. ==> 0XF8000160[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. CAN1_REF_SEL = 0x0
+    // .. ==> 0XF8000160[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[16:16] = 0x00000001U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B00[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000700[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 0
+    // .. ==> 0XF8000830[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x800
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x800
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF800015C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF800015C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800015C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xe
+    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF800015C[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+    // .. CAN0_MUX = 0x0
+    // .. ==> 0XF8000160[5:0] = 0x00000000U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+    // .. CAN0_REF_SEL = 0x0
+    // .. ==> 0XF8000160[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. CAN1_MUX = 0x0
+    // .. ==> 0XF8000160[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. CAN1_REF_SEL = 0x0
+    // .. ==> 0XF8000160[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[16:16] = 0x00000001U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000700[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 0
+    // .. ==> 0XF8000830[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x800
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x800
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF800015C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF800015C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800015C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xe
+    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF800015C[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+    // .. CAN0_MUX = 0x0
+    // .. ==> 0XF8000160[5:0] = 0x00000000U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+    // .. CAN0_REF_SEL = 0x0
+    // .. ==> 0XF8000160[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. CAN1_MUX = 0x0
+    // .. ==> 0XF8000160[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. CAN1_REF_SEL = 0x0
+    // .. ==> 0XF8000160[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[16:16] = 0x00000001U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000700[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 0
+    // .. ==> 0XF8000830[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x800
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x800
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+
+#include "xil_io.h"
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
new file mode 100644
index 000000000..c84ee6b1f
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
@@ -0,0 +1,12731 @@
+// SPDX-License-Identifier: GPL-2.0+
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x25
+    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
+    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x19
+    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
+    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
+    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
+    // .. .. reg_phy_gatelvl_init_ratio = 0x109
+    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
+    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
+    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
+    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
+    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
+    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
+    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xde
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
+    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xea
+    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B00[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000700[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000724[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000728[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800072C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000730[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000734[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000738[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 14
+    // .. ==> 0XF8000830[21:16] = 0x0000000EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x25
+    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
+    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x19
+    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
+    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
+    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
+    // .. .. reg_phy_gatelvl_init_ratio = 0x109
+    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
+    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
+    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
+    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
+    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
+    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
+    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xde
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
+    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xea
+    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000700[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000724[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000728[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800072C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000730[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000734[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000738[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 14
+    // .. ==> 0XF8000830[21:16] = 0x0000000EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x25
+    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
+    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x19
+    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
+    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
+    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
+    // .. .. reg_phy_gatelvl_init_ratio = 0x109
+    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
+    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
+    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
+    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
+    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
+    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
+    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xde
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
+    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xea
+    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000700[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000724[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000728[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800072C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000730[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000734[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000738[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 14
+    // .. ==> 0XF8000830[21:16] = 0x0000000EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+
+#include "xil_io.h"
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
new file mode 100644
index 000000000..b4663818d
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
@@ -0,0 +1,787 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01ED844DU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B00, 0x00000071U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000221U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000220U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000002E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000002E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000240U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000240U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01ED844DU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B00, 0x00000303U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000221U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000220U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000002E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000002E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000240U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000240U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01ED844DU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B00, 0x00000303U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000221U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000220U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000002E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000002E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000240U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000240U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
new file mode 100644
index 000000000..254a512cc
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
@@ -0,0 +1,769 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001611U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+	EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000001U),
+	EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001611U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+	EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000001U),
+	EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001611U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+	EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000001U),
+	EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
new file mode 100644
index 000000000..f4362b943
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
@@ -0,0 +1,763 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00000611U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000006E1U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000621U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000620U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001660U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+	EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00000611U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000006E1U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000621U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000620U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001660U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+	EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00000611U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000006E1U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000621U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000620U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001660U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+	EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
new file mode 100644
index 000000000..621de09cc
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
@@ -0,0 +1,805 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00100102U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x004C0000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016E800DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
+	EMIT_MASKWRITE(0xE000E010, 0x03EFFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xE2000000, 0x0000FFFFU, 0x000000F0U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A204, 0xFFFFFFFFU, 0x00000001U),
+	EMIT_MASKWRITE(0xE000A000, 0xFFFFFFFFU, 0xFFFE0000U),
+	EMIT_MASKWRITE(0xE000A208, 0xFFFFFFFFU, 0x00000001U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00100102U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x004C0000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016E800DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
+	EMIT_MASKWRITE(0xE000E010, 0x03EFFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xE2000000, 0x0000FFFFU, 0x000000F0U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A204, 0xFFFFFFFFU, 0x00000001U),
+	EMIT_MASKWRITE(0xE000A000, 0xFFFFFFFFU, 0xFFFE0000U),
+	EMIT_MASKWRITE(0xE000A208, 0xFFFFFFFFU, 0x00000001U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00100102U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x004C0000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016E800DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
+	EMIT_MASKWRITE(0xE000E010, 0x03EFFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xE2000000, 0x0000FFFFU, 0x000000F0U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A204, 0xFFFFFFFFU, 0x00000001U),
+	EMIT_MASKWRITE(0xE000A000, 0xFFFFFFFFU, 0xFFFE0000U),
+	EMIT_MASKWRITE(0xE000A208, 0xFFFFFFFFU, 0x00000001U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
new file mode 100644
index 000000000..eefd46d93
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
@@ -0,0 +1,754 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600702U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01DE408DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000006E1U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000720U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000721U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x000007C0U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x000007C1U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000006A0U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000006A0U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600702U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01DE408DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000006E1U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000720U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000721U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x000007C0U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x000007C1U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000006A0U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000006A0U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600702U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01DE408DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000006E1U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000720U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000721U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x000007C0U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x000007C1U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000006A0U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000006A0U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
new file mode 100644
index 000000000..7a15ea572
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
@@ -0,0 +1,12389 @@
+// SPDX-License-Identifier: GPL-2.0+
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x7
+    // .. ==> 0XF8000180[13:8] = 0x00000007U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x18
+    // .. .. ==> 0XF8006018[15:10] = 0x00000018U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
+    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF800612C[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xcf
+    // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00033C00U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006130[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd0
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00034000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbd
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xc1
+    // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00030400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006154[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006158[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
+    // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007FU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
+    // .. .. ==> 0XF8006160[9:0] = 0x00000078U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000078U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x124
+    // .. .. ==> 0XF8006168[10:0] = 0x00000124U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000124U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x125
+    // .. .. ==> 0XF800616C[10:0] = 0x00000125U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000125U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x112
+    // .. .. ==> 0XF8006170[10:0] = 0x00000112U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000112U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x116
+    // .. .. ==> 0XF8006174[10:0] = 0x00000116U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000116U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbf
+    // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BFU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb8
+    // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B8U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000704[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000708[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800070C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000710[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000714[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000718[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000720[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000770[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000774[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000778[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800077C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000780[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000784[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000788[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800078C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000790[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000794[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000798[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800079C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A8[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007AC[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007CC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 46
+    // .. ==> 0XF8000830[5:0] = 0x0000002EU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000002EU
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x7
+    // .. ==> 0XF8000180[13:8] = 0x00000007U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x18
+    // .. .. ==> 0XF8006018[15:10] = 0x00000018U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
+    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF800612C[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xcf
+    // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00033C00U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006130[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd0
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00034000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbd
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xc1
+    // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00030400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006154[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006158[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
+    // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007FU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
+    // .. .. ==> 0XF8006160[9:0] = 0x00000078U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000078U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x124
+    // .. .. ==> 0XF8006168[10:0] = 0x00000124U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000124U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x125
+    // .. .. ==> 0XF800616C[10:0] = 0x00000125U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000125U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x112
+    // .. .. ==> 0XF8006170[10:0] = 0x00000112U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000112U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x116
+    // .. .. ==> 0XF8006174[10:0] = 0x00000116U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000116U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbf
+    // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BFU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb8
+    // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B8U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000704[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000708[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800070C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000710[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000714[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000718[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000720[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000770[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000774[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000778[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800077C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000780[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000784[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000788[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800078C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000790[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000794[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000798[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800079C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A8[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007AC[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007CC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 46
+    // .. ==> 0XF8000830[5:0] = 0x0000002EU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000002EU
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x7
+    // .. ==> 0XF8000180[13:8] = 0x00000007U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x18
+    // .. .. ==> 0XF8006018[15:10] = 0x00000018U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
+    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF800612C[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xcf
+    // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00033C00U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006130[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd0
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00034000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbd
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xc1
+    // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00030400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006154[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006158[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
+    // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007FU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
+    // .. .. ==> 0XF8006160[9:0] = 0x00000078U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000078U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x124
+    // .. .. ==> 0XF8006168[10:0] = 0x00000124U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000124U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x125
+    // .. .. ==> 0XF800616C[10:0] = 0x00000125U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000125U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x112
+    // .. .. ==> 0XF8006170[10:0] = 0x00000112U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000112U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x116
+    // .. .. ==> 0XF8006174[10:0] = 0x00000116U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000116U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbf
+    // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BFU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb8
+    // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B8U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000704[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000708[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800070C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000710[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000714[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000718[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000720[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000770[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000774[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000778[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800077C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000780[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000784[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000788[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800078C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000790[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000794[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000798[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800079C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A8[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007AC[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007CC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 46
+    // .. ==> 0XF8000830[5:0] = 0x0000002EU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000002EU
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+
+#include "xil_io.h"
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c
new file mode 100644
index 000000000..5d573868c
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Xilinx, Inc.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A03U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00200501U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U),
+	EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FD044DU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001082U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004285BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D3U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x7282BCE5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040B30U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0002A81FU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029822U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C10U),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00026013U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000090U),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000093U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000FFU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000FBU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000D0U),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000D3U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U),
+	EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
+	EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00080000U),
+	EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
new file mode 100644
index 000000000..5d573868c
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Xilinx, Inc.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A03U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00200501U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U),
+	EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FD044DU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001082U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004285BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D3U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x7282BCE5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040B30U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0002A81FU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029822U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C10U),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00026013U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000090U),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000093U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000FFU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000FBU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000D0U),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000D3U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U),
+	EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
+	EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00080000U),
+	EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
new file mode 100644
index 000000000..a376ba574
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * Procedure to generate this file (using Vivado Webpack 2018.2):
+ * + Install board files from digilent/vivado-boards repository
+ *   (commit 6a45981 from 2018-06-05)
+ * + Start Vivado and create a new RTL project with the Zybo-z7-20 board
+ * + Create a block design
+ *   - Add "ZYNQ7 Processing System" IP
+ *   - Run "Block Automation" (Check "Apply Board Preset")
+ *   - Connect ports FCLK_CLK0 and M_AXI_GP0_ACLK
+ *   - Save diagram changes
+ *   - Go to sources view, select the block diagram,
+ *     and select "Generate Output Products"
+ * + Copy the generated "ps7_init_gpl.c" file
+ * + Perform manual editions based on existing Zynq boards
+ *   and the checkpatch.pl script
+ *
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00027000U),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00027000U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C00U),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00028800U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000073U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000F1U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000F1U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000F7U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000BCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000B3U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001305U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001305U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001305U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002F0037U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00004000U),
+	EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00004000U),
+	EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	int ret = -1;
+
+	ret = ps7_config(ps7_post_config_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
new file mode 100644
index 000000000..fda6d18dd
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -0,0 +1,12568 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Xilinx, Inc.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: PLL SLCR REGISTERS */
+	/* .. .. START: ARM PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x177 */
+	/* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x1a */
+	/* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. ARM_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. SRCSEL = 0x0 */
+	/* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. .. DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U */
+	/* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U */
+	/* .. .. .. CPU_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. .. CPU_1XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. .. CPU_PERI_CLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	/* .. .. FINISH: ARM PLL INIT */
+	/* .. .. START: DDR PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1db */
+	/* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x15 */
+	/* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. DDR_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. DDR_3XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. DDR_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+	/* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+	/* .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	/* .. .. FINISH: DDR PLL INIT */
+	/* .. .. START: IO PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1f4 */
+	/* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x14 */
+	/* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. IO_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. FINISH: IO PLL INIT */
+	/* .. FINISH: PLL SLCR REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: CLOCK CONTROL SLCR REGISTERS */
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000128[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. DIVISOR0 = 0x34 */
+	/* .. ==> 0XF8000128[13:8] = 0x00000034U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U */
+	/* .. DIVISOR1 = 0x2 */
+	/* .. ==> 0XF8000128[25:20] = 0x00000002U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000138[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000138[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000140[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000140[6:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x8 */
+	/* .. ==> 0XF8000140[13:8] = 0x00000008U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U */
+	/* .. DIVISOR1 = 0x1 */
+	/* .. ==> 0XF8000140[25:20] = 0x00000001U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF800014C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF800014C[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x5 */
+	/* .. ==> 0XF800014C[13:8] = 0x00000005U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	/* .. CLKACT0 = 0x1 */
+	/* .. ==> 0XF8000150[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. CLKACT1 = 0x0 */
+	/* .. ==> 0XF8000150[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000150[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x14 */
+	/* .. ==> 0XF8000150[13:8] = 0x00000014U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+	/* .. CLKACT0 = 0x0 */
+	/* .. ==> 0XF8000154[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. CLKACT1 = 0x1 */
+	/* .. ==> 0XF8000154[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000154[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0xa */
+	/* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
+	/* .. .. START: TRACE CLOCK */
+	/* .. .. FINISH: TRACE CLOCK */
+	/* .. .. CLKACT = 0x1 */
+	/* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR = 0x5 */
+	/* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0xa */
+	/* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x7 */
+	/* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x5 */
+	/* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x14 */
+	/* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	/* .. .. CLK_621_TRUE = 0x1 */
+	/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	/* .. .. DMA_CPU_2XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. USB0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. USB1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U */
+	/* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U */
+	/* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U */
+	/* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. UART0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. UART1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U */
+	/* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U */
+	/* .. .. SMC_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	/* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+	/* .. START: THIS SHOULD BE BLANK */
+	/* .. FINISH: THIS SHOULD BE BLANK */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: DDR INITIALIZATION */
+	/* .. .. START: LOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	/* .. .. FINISH: LOCK DDR */
+	/* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+	/* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU */
+	/* .. .. reserved_reg_ddrc_active_ranks = 0x1 */
+	/* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+	/* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU),
+	/* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU */
+	/* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U */
+	/* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+	/* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	/* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	/* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U */
+	/* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	/* .. .. reg_ddrc_t_rc = 0x1a */
+	/* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+	/* .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU */
+	/* .. .. reg_ddrc_t_rfc_min = 0x54 */
+	/* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+	/* .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U */
+	/* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+	/* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+	/* .. .. reg_ddrc_wr2pre = 0x12 */
+	/* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U */
+	/* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+	/* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_t_faw = 0x15 */
+	/* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+	/* .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U */
+	/* .. .. reg_ddrc_t_ras_max = 0x23 */
+	/* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+	/* .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U */
+	/* .. .. reg_ddrc_t_ras_min = 0x13 */
+	/* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U */
+	/* .. .. reg_ddrc_t_cke = 0x4 */
+	/* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+	/* .. .. reg_ddrc_write_latency = 0x5 */
+	/* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_rd2wr = 0x7 */
+	/* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U */
+	/* .. .. reg_ddrc_wr2rd = 0xe */
+	/* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+	/* .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U */
+	/* .. .. reg_ddrc_t_xp = 0x4 */
+	/* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U */
+	/* .. .. reg_ddrc_pad_pd = 0x0 */
+	/* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd2pre = 0x4 */
+	/* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U */
+	/* .. .. reg_ddrc_t_rcd = 0x7 */
+	/* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	/* .. .. reg_ddrc_t_ccd = 0x4 */
+	/* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_t_rrd = 0x6 */
+	/* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_refresh_margin = 0x2 */
+	/* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_rp = 0x7 */
+	/* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U */
+	/* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+	/* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_mobile = 0x0 */
+	/* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */
+	/* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_read_latency = 0x7 */
+	/* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+	/* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U */
+	/* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+	/* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	/* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+	/* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_prefer_write = 0x0 */
+	/* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_wr = 0x0 */
+	/* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_addr = 0x0 */
+	/* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_data = 0x0 */
+	/* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+	/* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_type = 0x0 */
+	/* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+	/* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	/* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+	/* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+	/* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_t_mrd = 0x4 */
+	/* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	/* .. .. reg_ddrc_emr2 = 0x8 */
+	/* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_emr3 = 0x0 */
+	/* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	/* .. .. reg_ddrc_mr = 0x930 */
+	/* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U */
+	/* .. .. reg_ddrc_emr = 0x4 */
+	/* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	/* .. .. reg_ddrc_burst_rdwr = 0x4 */
+	/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U */
+	/* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+	/* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+	/* .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001670U */
+	/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U */
+	/* .. .. reg_ddrc_burstchop = 0x0 */
+	/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+	/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+	/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_dq = 0x0 */
+	/* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	/* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+	/* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+	/* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U */
+	/* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+	/* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U */
+	/* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+	/* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+	/* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	/* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+	/* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+	/* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+	/* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+	/* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+	/* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+	/* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+	/* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+	/* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	/* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+	/* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+	/* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+	/* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U */
+	/* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+	/* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+	/* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+	/* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+	/* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	/* .. .. reg_phy_rd_local_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U */
+	/* .. .. reg_phy_idle_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U */
+	/* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U */
+	/* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	/* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+	/* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U */
+	/* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+	/* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_fixed_re = 0x1 */
+	/* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+	/* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+	/* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_clk_stall_level = 0x0 */
+	/* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	/* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+	/* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	/* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+	/* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U */
+	/* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+	/* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+	/* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+	/* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	/* .. .. reg_ddrc_pageclose = 0x0 */
+	/* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+	/* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+	/* .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU */
+	/* .. .. reg_ddrc_auto_pre_en = 0x0 */
+	/* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_refresh_update_level = 0x0 */
+	/* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_wc = 0x0 */
+	/* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+	/* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_selfref_en = 0x0 */
+	/* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	/* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+	/* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U */
+	/* .. .. reg_arb_go2critical_en = 0x1 */
+	/* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	/* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+	/* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U */
+	/* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+	/* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U */
+	/* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+	/* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	/* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+	/* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U */
+	/* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+	/* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	/* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
+	/* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
+	/* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
+	/* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U */
+	/* .. .. reg_ddrc_t_cksre = 0x6 */
+	/* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_t_cksrx = 0x6 */
+	/* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_t_ckesr = 0x4 */
+	/* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	/* .. .. reg_ddrc_t_ckpde = 0x2 */
+	/* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_ckpdx = 0x2 */
+	/* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U */
+	/* .. .. reg_ddrc_t_ckdpde = 0x2 */
+	/* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_ckdpdx = 0x2 */
+	/* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U */
+	/* .. .. reg_ddrc_t_ckcsx = 0x3 */
+	/* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	/* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+	/* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_ddr3 = 0x1 */
+	/* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_mod = 0x200 */
+	/* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U */
+	/* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+	/* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+	/* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+	/* .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	/* .. .. t_zq_short_interval_x1024 = 0xc845 */
+	/* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+	/* .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U */
+	/* .. .. dram_rstn_x1024 = 0x67 */
+	/* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+	/* .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+	/* .. .. deeppowerdown_en = 0x0 */
+	/* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. deeppowerdown_to_x1024 = 0xff */
+	/* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+	/* .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	/* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU */
+	/* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U */
+	/* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+	/* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+	/* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	/* .. .. reg_ddrc_skip_ocd = 0x1 */
+	/* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	/* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+	/* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+	/* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+	/* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	/* .. .. START: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	/* .. .. FINISH: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	/* .. .. CORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+	/* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	/* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	/* .. .. STAT_NUM_CORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U */
+	/* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_ecc_mode = 0x0 */
+	/* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_scrub = 0x1 */
+	/* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	/* .. .. reg_phy_dif_on = 0x0 */
+	/* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_dif_off = 0x0 */
+	/* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+	/* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+	/* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+	/* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+	/* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+	/* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+	/* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+	/* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+	/* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+	/* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+	/* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+	/* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+	/* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+	/* .. .. reg_phy_bl2 = 0x0 */
+	/* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_at_spd_atpg = 0x0 */
+	/* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_enable = 0x0 */
+	/* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_force_err = 0x0 */
+	/* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_mode = 0x0 */
+	/* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. .. reg_phy_invert_clkout = 0x1 */
+	/* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. .. reg_phy_sel_logic = 0x0 */
+	/* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+	/* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U */
+	/* .. .. reg_phy_ctrl_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_lpddr = 0x0 */
+	/* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_cmd_latency = 0x0 */
+	/* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	/* .. .. reg_phy_wr_rl_delay = 0x2 */
+	/* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U */
+	/* .. .. reg_phy_rd_rl_delay = 0x4 */
+	/* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U */
+	/* .. .. reg_phy_dll_lock_diff = 0xf */
+	/* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U */
+	/* .. .. reg_phy_use_wr_level = 0x1 */
+	/* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U */
+	/* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U */
+	/* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+	/* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_dis_calib_rst = 0x0 */
+	/* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	/* .. .. reg_arb_page_addr_mask = 0x0 */
+	/* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_ddrc_lpddr2 = 0x0 */
+	/* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_derate_enable = 0x0 */
+	/* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr4_margin = 0x0 */
+	/* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	/* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+	/* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+	/* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U */
+	/* .. .. reg_ddrc_t_mrw = 0x5 */
+	/* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	/* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+	/* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U */
+	/* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+	/* .. .. START: POLL ON DCI STATUS */
+	/* .. .. DONE = 1 */
+	/* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	/* .. .. FINISH: POLL ON DCI STATUS */
+	/* .. .. START: UNLOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0x1 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	/* .. .. FINISH: UNLOCK DDR */
+	/* .. .. START: CHECK DDR STATUS */
+	/* .. .. ddrc_reg_operating_mode = 1 */
+	/* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	/* .. .. FINISH: CHECK DDR STATUS */
+	/* .. FINISH: DDR INITIALIZATION */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: OCM REMAPPING */
+	/* .. VREF_EN = 0x1 */
+	/* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. VREF_SEL = 0x0 */
+	/* .. ==> 0XF8000B00[6:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U),
+	/* .. FINISH: OCM REMAPPING */
+	/* .. START: DDRIOB SETTINGS */
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCI_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCI_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCI_TYPE = 0x3 */
+	/* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCI_TYPE = 0x3 */
+	/* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCI_TYPE = 0x3 */
+	/* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCI_TYPE = 0x3 */
+	/* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCI_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	/* .. reserved_DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. reserved_DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. reserved_SLEW_P = 0x3 */
+	/* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U */
+	/* .. reserved_SLEW_N = 0x3 */
+	/* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U */
+	/* .. reserved_GTL = 0x0 */
+	/* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. reserved_RTERM = 0x0 */
+	/* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	/* .. reserved_DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. reserved_DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. reserved_SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. reserved_SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. reserved_GTL = 0x0 */
+	/* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. reserved_RTERM = 0x0 */
+	/* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. reserved_DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. reserved_DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. reserved_SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. reserved_SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. reserved_GTL = 0x0 */
+	/* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. reserved_RTERM = 0x0 */
+	/* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. reserved_DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. reserved_DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. reserved_SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. reserved_SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. reserved_GTL = 0x0 */
+	/* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. reserved_RTERM = 0x0 */
+	/* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. VREF_INT_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. VREF_SEL = 0x0 */
+	/* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U */
+	/* .. VREF_EXT_EN = 0x3 */
+	/* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. reserved_VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. REFIO_EN = 0x1 */
+	/* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. reserved_REFIO_TEST = 0x0 */
+	/* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U */
+	/* .. reserved_REFIO_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. reserved_DRST_B_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. reserved_CKE_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	/* .. .. START: ASSERT RESET */
+	/* .. .. RESET = 1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	/* .. .. FINISH: ASSERT RESET */
+	/* .. .. START: DEASSERT RESET */
+	/* .. .. RESET = 0 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reserved_VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	/* .. .. FINISH: DEASSERT RESET */
+	/* .. .. RESET = 0x1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. ENABLE = 0x1 */
+	/* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. reserved_VRP_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reserved_VRN_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reserved_VRP_OUT = 0x0 */
+	/* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reserved_VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. NREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT4 = 0x1 */
+	/* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U */
+	/* .. .. PREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
+	/* .. .. PREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U */
+	/* .. .. UPDATE_CONTROL = 0x0 */
+	/* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. reserved_INIT_COMPLETE = 0x0 */
+	/* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. reserved_TST_CLK = 0x0 */
+	/* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. reserved_TST_HLN = 0x0 */
+	/* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. reserved_TST_HLP = 0x0 */
+	/* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. reserved_TST_RST = 0x0 */
+	/* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reserved_INT_DCI_EN = 0x0 */
+	/* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	/* .. FINISH: DDRIOB SETTINGS */
+	/* .. START: MIO PROGRAMMING */
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000700[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000700[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000700[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000700[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000700[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000700[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000700[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000700[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000700[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000704[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000704[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000704[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000704[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000704[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000704[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000704[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000704[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000704[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000708[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000708[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000708[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000708[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000708[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000708[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000708[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000708[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000708[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800070C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800070C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800070C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800070C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800070C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800070C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800070C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800070C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800070C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000710[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000710[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000710[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000710[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000710[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000710[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000710[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000710[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000710[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000714[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000714[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000714[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000714[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000714[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000714[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000714[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000714[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000714[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000718[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000718[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000718[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000718[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000718[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000718[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000718[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000718[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000718[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800071C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800071C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800071C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800071C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800071C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800071C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800071C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800071C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800071C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000720[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000720[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000720[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000720[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000720[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000720[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000720[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000720[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000720[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000724[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000724[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000724[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000724[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000724[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000724[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000724[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000724[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000724[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000728[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000728[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000728[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000728[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000728[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000728[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000728[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000728[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000728[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800072C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800072C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800072C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800072C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800072C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800072C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800072C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800072C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800072C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000730[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000730[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000730[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000730[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000730[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000730[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000730[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000730[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000730[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000734[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000734[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000734[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000734[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000734[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000734[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000734[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000734[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000734[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000738[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000738[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000738[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000738[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000738[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000738[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000738[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000738[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000738[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800073C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800073C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800073C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800073C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800073C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800073C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800073C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800073C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800073C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000740[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000740[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000740[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000740[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000740[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000740[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000740[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000740[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000740[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000744[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000744[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000744[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000744[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000744[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000744[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000744[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000744[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000744[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000748[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000748[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000748[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000748[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000748[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000748[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000748[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000748[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000748[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800074C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800074C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800074C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800074C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800074C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800074C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800074C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800074C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF800074C[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000750[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000750[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000750[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000750[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000750[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000750[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000750[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000750[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000750[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000754[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000754[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000754[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000754[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000754[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000754[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000754[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000754[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000754[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000758[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000758[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000758[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000758[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000758[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000758[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000758[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000758[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000758[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800075C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800075C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800075C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800075C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800075C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800075C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800075C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800075C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800075C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000760[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000760[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000760[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000760[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000760[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000760[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000760[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000760[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000760[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000764[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000764[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000764[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000764[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000764[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000764[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000764[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000764[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000764[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000768[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000768[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000768[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000768[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000768[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000768[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000768[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000768[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000768[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800076C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800076C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800076C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800076C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800076C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800076C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800076C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800076C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800076C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000770[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000770[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000770[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000770[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000770[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000770[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000770[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000770[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000770[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000774[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000774[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000774[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000774[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000774[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000774[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000774[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000774[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000774[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000778[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000778[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000778[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000778[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000778[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000778[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000778[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000778[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000778[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800077C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800077C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800077C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800077C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800077C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800077C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800077C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800077C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800077C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000780[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000780[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000780[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000780[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000780[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000780[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000780[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000780[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000780[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000784[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000784[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000784[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000784[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000784[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000784[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000784[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000784[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000784[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000788[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000788[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000788[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000788[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000788[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000788[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000788[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000788[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000788[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800078C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800078C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800078C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800078C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800078C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800078C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800078C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800078C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800078C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000790[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000790[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000790[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000790[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000790[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000790[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000790[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000790[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000790[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000794[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000794[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000794[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000794[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000794[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000794[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000794[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000794[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000794[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000798[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000798[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000798[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000798[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000798[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000798[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000798[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000798[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000798[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800079C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800079C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800079C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800079C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800079C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800079C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800079C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800079C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800079C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+	/* .. SDIO0_WP_SEL = 55 */
+	/* .. ==> 0XF8000830[5:0] = 0x00000037U */
+	/* ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U */
+	/* .. SDIO0_CD_SEL = 47 */
+	/* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+	/* ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+	/* .. FINISH: MIO PROGRAMMING */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	/* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* .. START: SRAM/NOR SET OPMODE */
+	/* .. FINISH: SRAM/NOR SET OPMODE */
+	/* .. START: QSPI REGISTERS */
+	/* .. Holdb_dr = 1 */
+	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
+	/* ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. */
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	/* .. FINISH: QSPI REGISTERS */
+	/* .. START: PL POWER ON RESET REGISTERS */
+	/* .. PCFG_POR_CNT_4K = 0 */
+	/* .. ==> 0XF8007000[29:29] = 0x00000000U */
+	/* ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	/* .. FINISH: PL POWER ON RESET REGISTERS */
+	/* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* .. .. START: NAND SET CYCLE */
+	/* .. .. FINISH: NAND SET CYCLE */
+	/* .. .. START: OPMODE */
+	/* .. .. FINISH: OPMODE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS0 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS0 BASE ADDRESS */
+	/* .. .. START: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS1 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS1 BASE ADDRESS */
+	/* .. .. START: USB RESET */
+	/* .. .. .. START: USB0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. DIRECTION_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x0 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB0 RESET */
+	/* .. .. .. START: USB1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB1 RESET */
+	/* .. .. FINISH: USB RESET */
+	/* .. .. START: ENET RESET */
+	/* .. .. .. START: ENET0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET0 RESET */
+	/* .. .. .. START: ENET1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET1 RESET */
+	/* .. .. FINISH: ENET RESET */
+	/* .. .. START: I2C RESET */
+	/* .. .. .. START: I2C0 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C0 RESET */
+	/* .. .. .. START: I2C1 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C1 RESET */
+	/* .. .. FINISH: I2C RESET */
+	/* .. .. START: NOR CHIP SELECT */
+	/* .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. FINISH: NOR CHIP SELECT */
+	/* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_post_config_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: ENABLING LEVEL SHIFTER */
+	/* .. USER_LVL_INP_EN_0 = 1 */
+	/* .. ==> 0XF8000900[3:3] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. USER_LVL_OUT_EN_0 = 1 */
+	/* .. ==> 0XF8000900[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. USER_LVL_INP_EN_1 = 1 */
+	/* .. ==> 0XF8000900[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. USER_LVL_OUT_EN_1 = 1 */
+	/* .. ==> 0XF8000900[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	/* .. FINISH: ENABLING LEVEL SHIFTER */
+	/* .. START: FPGA RESETS TO 0 */
+	/* .. reserved_3 = 0 */
+	/* .. ==> 0XF8000240[31:25] = 0x00000000U */
+	/* ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_ACP_RST = 0 */
+	/* .. ==> 0XF8000240[24:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_AXDS3_RST = 0 */
+	/* .. ==> 0XF8000240[23:23] = 0x00000000U */
+	/* ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_AXDS2_RST = 0 */
+	/* .. ==> 0XF8000240[22:22] = 0x00000000U */
+	/* ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_AXDS1_RST = 0 */
+	/* .. ==> 0XF8000240[21:21] = 0x00000000U */
+	/* ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_AXDS0_RST = 0 */
+	/* .. ==> 0XF8000240[20:20] = 0x00000000U */
+	/* ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. reserved_2 = 0 */
+	/* .. ==> 0XF8000240[19:18] = 0x00000000U */
+	/* ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. reserved_FSSW1_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[17:17] = 0x00000000U */
+	/* ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. reserved_FSSW0_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[16:16] = 0x00000000U */
+	/* ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. reserved_1 = 0 */
+	/* .. ==> 0XF8000240[15:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_FMSW1_RST = 0 */
+	/* .. ==> 0XF8000240[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_FMSW0_RST = 0 */
+	/* .. ==> 0XF8000240[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_DMA3_RST = 0 */
+	/* .. ==> 0XF8000240[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_DMA2_RST = 0 */
+	/* .. ==> 0XF8000240[10:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_DMA1_RST = 0 */
+	/* .. ==> 0XF8000240[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_DMA0_RST = 0 */
+	/* .. ==> 0XF8000240[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. reserved = 0 */
+	/* .. ==> 0XF8000240[7:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. FPGA3_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. FPGA2_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. FPGA1_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. FPGA0_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	/* .. FINISH: FPGA RESETS TO 0 */
+	/* .. START: AFI REGISTERS */
+	/* .. .. START: AFI0 REGISTERS */
+	/* .. .. FINISH: AFI0 REGISTERS */
+	/* .. .. START: AFI1 REGISTERS */
+	/* .. .. FINISH: AFI1 REGISTERS */
+	/* .. .. START: AFI2 REGISTERS */
+	/* .. .. FINISH: AFI2 REGISTERS */
+	/* .. .. START: AFI3 REGISTERS */
+	/* .. .. FINISH: AFI3 REGISTERS */
+	/* .. .. START: AFI2 SECURE REGISTER */
+	/* .. .. FINISH: AFI2 SECURE REGISTER */
+	/* .. FINISH: AFI REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+
+unsigned long ps7_pll_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: PLL SLCR REGISTERS */
+	/* .. .. START: ARM PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x177 */
+	/* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x1a */
+	/* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. ARM_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. SRCSEL = 0x0 */
+	/* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. .. DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U */
+	/* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U */
+	/* .. .. .. CPU_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. .. CPU_1XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. .. CPU_PERI_CLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	/* .. .. FINISH: ARM PLL INIT */
+	/* .. .. START: DDR PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1db */
+	/* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x15 */
+	/* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. DDR_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. DDR_3XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. DDR_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+	/* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+	/* .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	/* .. .. FINISH: DDR PLL INIT */
+	/* .. .. START: IO PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1f4 */
+	/* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x14 */
+	/* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. IO_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. FINISH: IO PLL INIT */
+	/* .. FINISH: PLL SLCR REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: CLOCK CONTROL SLCR REGISTERS */
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000128[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. DIVISOR0 = 0x34 */
+	/* .. ==> 0XF8000128[13:8] = 0x00000034U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U */
+	/* .. DIVISOR1 = 0x2 */
+	/* .. ==> 0XF8000128[25:20] = 0x00000002U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000138[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000138[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000140[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000140[6:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x8 */
+	/* .. ==> 0XF8000140[13:8] = 0x00000008U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U */
+	/* .. DIVISOR1 = 0x1 */
+	/* .. ==> 0XF8000140[25:20] = 0x00000001U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF800014C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF800014C[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x5 */
+	/* .. ==> 0XF800014C[13:8] = 0x00000005U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	/* .. CLKACT0 = 0x1 */
+	/* .. ==> 0XF8000150[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. CLKACT1 = 0x0 */
+	/* .. ==> 0XF8000150[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000150[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x14 */
+	/* .. ==> 0XF8000150[13:8] = 0x00000014U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+	/* .. CLKACT0 = 0x0 */
+	/* .. ==> 0XF8000154[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. CLKACT1 = 0x1 */
+	/* .. ==> 0XF8000154[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000154[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0xa */
+	/* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
+	/* .. .. START: TRACE CLOCK */
+	/* .. .. FINISH: TRACE CLOCK */
+	/* .. .. CLKACT = 0x1 */
+	/* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR = 0x5 */
+	/* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0xa */
+	/* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x7 */
+	/* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x5 */
+	/* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x14 */
+	/* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	/* .. .. CLK_621_TRUE = 0x1 */
+	/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	/* .. .. DMA_CPU_2XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. USB0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. USB1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U */
+	/* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U */
+	/* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U */
+	/* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. UART0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. UART1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U */
+	/* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U */
+	/* .. .. SMC_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	/* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+	/* .. START: THIS SHOULD BE BLANK */
+	/* .. FINISH: THIS SHOULD BE BLANK */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: DDR INITIALIZATION */
+	/* .. .. START: LOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	/* .. .. FINISH: LOCK DDR */
+	/* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+	/* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU */
+	/* .. .. reg_ddrc_active_ranks = 0x1 */
+	/* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+	/* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_block = 0x1 */
+	/* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
+	/* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
+	/* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
+	/* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
+	/* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
+	/* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU */
+	/* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U */
+	/* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+	/* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	/* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	/* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U */
+	/* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	/* .. .. reg_ddrc_t_rc = 0x1a */
+	/* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+	/* .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU */
+	/* .. .. reg_ddrc_t_rfc_min = 0x54 */
+	/* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+	/* .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U */
+	/* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+	/* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+	/* .. .. reg_ddrc_wr2pre = 0x12 */
+	/* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U */
+	/* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+	/* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_t_faw = 0x15 */
+	/* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+	/* .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U */
+	/* .. .. reg_ddrc_t_ras_max = 0x23 */
+	/* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+	/* .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U */
+	/* .. .. reg_ddrc_t_ras_min = 0x13 */
+	/* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U */
+	/* .. .. reg_ddrc_t_cke = 0x4 */
+	/* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+	/* .. .. reg_ddrc_write_latency = 0x5 */
+	/* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_rd2wr = 0x7 */
+	/* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U */
+	/* .. .. reg_ddrc_wr2rd = 0xe */
+	/* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+	/* .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U */
+	/* .. .. reg_ddrc_t_xp = 0x4 */
+	/* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U */
+	/* .. .. reg_ddrc_pad_pd = 0x0 */
+	/* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd2pre = 0x4 */
+	/* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U */
+	/* .. .. reg_ddrc_t_rcd = 0x7 */
+	/* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	/* .. .. reg_ddrc_t_ccd = 0x4 */
+	/* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_t_rrd = 0x6 */
+	/* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_refresh_margin = 0x2 */
+	/* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_rp = 0x7 */
+	/* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U */
+	/* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+	/* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_sdram = 0x1 */
+	/* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_mobile = 0x0 */
+	/* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_clock_stop_en = 0x0 */
+	/* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_read_latency = 0x7 */
+	/* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+	/* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U */
+	/* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+	/* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_loopback = 0x0 */
+	/* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+	/* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+	/* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_prefer_write = 0x0 */
+	/* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_max_rank_rd = 0xf */
+	/* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU */
+	/* .. .. reg_ddrc_mr_wr = 0x0 */
+	/* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_addr = 0x0 */
+	/* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_data = 0x0 */
+	/* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+	/* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_type = 0x0 */
+	/* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+	/* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	/* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+	/* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+	/* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_t_mrd = 0x4 */
+	/* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	/* .. .. reg_ddrc_emr2 = 0x8 */
+	/* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_emr3 = 0x0 */
+	/* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	/* .. .. reg_ddrc_mr = 0x930 */
+	/* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U */
+	/* .. .. reg_ddrc_emr = 0x4 */
+	/* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	/* .. .. reg_ddrc_burst_rdwr = 0x4 */
+	/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U */
+	/* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+	/* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+	/* .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001670U */
+	/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U */
+	/* .. .. reg_ddrc_burstchop = 0x0 */
+	/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+	/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+	/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_dq = 0x0 */
+	/* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_debug_mode = 0x0 */
+	/* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_level_start = 0x0 */
+	/* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_level_start = 0x0 */
+	/* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq0_wait_t = 0x0 */
+	/* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+	/* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+	/* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+	/* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U */
+	/* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+	/* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U */
+	/* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+	/* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+	/* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	/* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+	/* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+	/* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+	/* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+	/* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+	/* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+	/* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+	/* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+	/* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	/* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+	/* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+	/* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+	/* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U */
+	/* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+	/* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+	/* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+	/* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+	/* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	/* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U */
+	/* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. .. reg_phy_rd_local_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U */
+	/* .. .. reg_phy_idle_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U */
+	/* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	/* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+	/* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U */
+	/* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+	/* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_fixed_re = 0x1 */
+	/* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+	/* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+	/* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_clk_stall_level = 0x0 */
+	/* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	/* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U */
+	/* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+	/* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+	/* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+	/* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U */
+	/* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+	/* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+	/* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+	/* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	/* .. .. reg_ddrc_pageclose = 0x0 */
+	/* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+	/* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+	/* .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU */
+	/* .. .. reg_ddrc_auto_pre_en = 0x0 */
+	/* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_refresh_update_level = 0x0 */
+	/* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_wc = 0x0 */
+	/* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+	/* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_selfref_en = 0x0 */
+	/* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	/* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+	/* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U */
+	/* .. .. reg_arb_go2critical_en = 0x1 */
+	/* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	/* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+	/* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U */
+	/* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+	/* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U */
+	/* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+	/* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	/* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+	/* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U */
+	/* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+	/* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	/* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
+	/* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
+	/* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
+	/* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U */
+	/* .. .. reg_ddrc_t_cksre = 0x6 */
+	/* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_t_cksrx = 0x6 */
+	/* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_t_ckesr = 0x4 */
+	/* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	/* .. .. reg_ddrc_t_ckpde = 0x2 */
+	/* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_ckpdx = 0x2 */
+	/* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U */
+	/* .. .. reg_ddrc_t_ckdpde = 0x2 */
+	/* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_ckdpdx = 0x2 */
+	/* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U */
+	/* .. .. reg_ddrc_t_ckcsx = 0x3 */
+	/* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	/* .. .. refresh_timer0_start_value_x32 = 0x0 */
+	/* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U */
+	/* .. .. refresh_timer1_start_value_x32 = 0x8 */
+	/* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+	/* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+	/* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_ddr3 = 0x1 */
+	/* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_mod = 0x200 */
+	/* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U */
+	/* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+	/* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+	/* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+	/* .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	/* .. .. t_zq_short_interval_x1024 = 0xc845 */
+	/* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+	/* .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U */
+	/* .. .. dram_rstn_x1024 = 0x67 */
+	/* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+	/* .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+	/* .. .. deeppowerdown_en = 0x0 */
+	/* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. deeppowerdown_to_x1024 = 0xff */
+	/* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+	/* .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	/* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU */
+	/* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U */
+	/* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+	/* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+	/* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	/* .. .. reg_ddrc_2t_delay = 0x0 */
+	/* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_skip_ocd = 0x1 */
+	/* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
+	/* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+	/* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+	/* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+	/* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+	/* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	/* .. .. START: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	/* .. .. FINISH: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	/* .. .. CORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+	/* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	/* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	/* .. .. STAT_NUM_CORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U */
+	/* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_ecc_mode = 0x0 */
+	/* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_scrub = 0x1 */
+	/* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	/* .. .. reg_phy_dif_on = 0x0 */
+	/* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_dif_off = 0x0 */
+	/* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+	/* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+	/* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+	/* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+	/* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+	/* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+	/* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+	/* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+	/* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+	/* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+	/* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+	/* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+	/* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+	/* .. .. reg_phy_loopback = 0x0 */
+	/* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bl2 = 0x0 */
+	/* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_at_spd_atpg = 0x0 */
+	/* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_enable = 0x0 */
+	/* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_force_err = 0x0 */
+	/* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_mode = 0x0 */
+	/* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. .. reg_phy_invert_clkout = 0x1 */
+	/* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
+	/* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_phy_sel_logic = 0x0 */
+	/* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+	/* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U */
+	/* .. .. reg_phy_ctrl_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_rank0_delays = 0x1 */
+	/* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. reg_phy_lpddr = 0x0 */
+	/* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_cmd_latency = 0x0 */
+	/* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_int_lpbk = 0x0 */
+	/* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+	/* .. .. reg_phy_wr_rl_delay = 0x2 */
+	/* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U */
+	/* .. .. reg_phy_rd_rl_delay = 0x4 */
+	/* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U */
+	/* .. .. reg_phy_dll_lock_diff = 0xf */
+	/* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U */
+	/* .. .. reg_phy_use_wr_level = 0x1 */
+	/* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U */
+	/* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U */
+	/* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+	/* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_dis_calib_rst = 0x0 */
+	/* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	/* .. .. reg_arb_page_addr_mask = 0x0 */
+	/* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_ddrc_lpddr2 = 0x0 */
+	/* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_per_bank_refresh = 0x0 */
+	/* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_derate_enable = 0x0 */
+	/* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr4_margin = 0x0 */
+	/* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+	/* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+	/* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+	/* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U */
+	/* .. .. reg_ddrc_t_mrw = 0x5 */
+	/* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	/* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+	/* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U */
+	/* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+	/* .. .. START: POLL ON DCI STATUS */
+	/* .. .. DONE = 1 */
+	/* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	/* .. .. FINISH: POLL ON DCI STATUS */
+	/* .. .. START: UNLOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0x1 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	/* .. .. FINISH: UNLOCK DDR */
+	/* .. .. START: CHECK DDR STATUS */
+	/* .. .. ddrc_reg_operating_mode = 1 */
+	/* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	/* .. .. FINISH: CHECK DDR STATUS */
+	/* .. FINISH: DDR INITIALIZATION */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: OCM REMAPPING */
+	/* .. VREF_EN = 0x1 */
+	/* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. CLK_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. SRSTN_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
+	/* .. FINISH: OCM REMAPPING */
+	/* .. START: DDRIOB SETTINGS */
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x3 */
+	/* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U */
+	/* .. SLEW_N = 0x3 */
+	/* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. VREF_INT_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. VREF_SEL = 0x0 */
+	/* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U */
+	/* .. VREF_EXT_EN = 0x3 */
+	/* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. REFIO_EN = 0x1 */
+	/* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. REFIO_TEST = 0x0 */
+	/* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U */
+	/* .. REFIO_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DRST_B_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. CKE_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	/* .. .. START: ASSERT RESET */
+	/* .. .. RESET = 1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+	/* .. .. FINISH: ASSERT RESET */
+	/* .. .. START: DEASSERT RESET */
+	/* .. .. RESET = 0 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	/* .. .. FINISH: DEASSERT RESET */
+	/* .. .. RESET = 0x1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. ENABLE = 0x1 */
+	/* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. VRP_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. VRN_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. VRP_OUT = 0x0 */
+	/* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. NREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT4 = 0x1 */
+	/* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U */
+	/* .. .. PREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U */
+	/* .. .. PREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U */
+	/* .. .. UPDATE_CONTROL = 0x0 */
+	/* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. INIT_COMPLETE = 0x0 */
+	/* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. TST_CLK = 0x0 */
+	/* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. TST_HLN = 0x0 */
+	/* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. TST_HLP = 0x0 */
+	/* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. TST_RST = 0x0 */
+	/* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. INT_DCI_EN = 0x0 */
+	/* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+	/* .. FINISH: DDRIOB SETTINGS */
+	/* .. START: MIO PROGRAMMING */
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000700[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000700[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000700[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000700[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000700[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000700[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000700[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000700[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000700[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000704[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000704[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000704[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000704[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000704[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000704[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000704[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000704[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000704[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000708[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000708[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000708[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000708[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000708[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000708[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000708[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000708[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000708[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800070C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800070C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800070C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800070C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800070C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800070C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800070C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800070C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800070C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000710[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000710[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000710[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000710[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000710[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000710[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000710[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000710[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000710[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000714[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000714[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000714[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000714[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000714[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000714[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000714[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000714[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000714[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000718[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000718[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000718[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000718[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000718[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000718[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000718[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000718[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000718[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800071C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800071C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800071C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800071C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800071C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800071C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800071C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800071C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800071C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000720[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000720[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000720[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000720[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000720[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000720[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000720[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000720[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000720[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000724[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000724[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000724[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000724[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000724[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000724[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000724[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000724[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000724[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000728[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000728[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000728[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000728[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000728[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000728[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000728[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000728[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000728[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800072C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800072C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800072C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800072C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800072C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800072C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800072C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800072C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800072C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000730[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000730[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000730[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000730[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000730[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000730[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000730[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000730[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000730[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000734[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000734[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000734[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000734[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000734[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000734[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000734[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000734[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000734[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000738[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000738[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000738[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000738[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000738[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000738[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000738[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000738[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000738[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800073C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800073C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800073C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800073C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800073C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800073C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800073C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800073C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800073C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000740[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000740[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000740[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000740[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000740[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000740[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000740[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000740[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000740[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000744[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000744[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000744[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000744[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000744[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000744[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000744[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000744[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000744[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000748[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000748[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000748[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000748[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000748[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000748[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000748[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000748[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000748[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800074C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800074C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800074C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800074C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800074C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800074C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800074C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800074C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF800074C[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000750[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000750[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000750[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000750[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000750[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000750[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000750[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000750[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000750[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000754[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000754[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000754[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000754[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000754[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000754[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000754[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000754[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000754[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000758[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000758[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000758[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000758[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000758[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000758[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000758[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000758[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000758[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800075C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800075C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800075C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800075C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800075C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800075C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800075C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800075C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800075C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000760[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000760[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000760[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000760[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000760[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000760[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000760[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000760[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000760[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000764[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000764[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000764[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000764[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000764[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000764[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000764[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000764[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000764[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000768[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000768[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000768[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000768[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000768[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000768[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000768[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000768[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000768[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800076C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800076C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800076C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800076C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800076C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800076C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800076C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800076C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800076C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000770[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000770[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000770[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000770[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000770[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000770[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000770[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000770[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000770[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000774[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000774[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000774[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000774[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000774[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000774[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000774[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000774[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000774[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000778[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000778[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000778[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000778[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000778[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000778[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000778[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000778[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000778[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800077C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800077C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800077C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800077C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800077C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800077C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800077C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800077C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800077C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000780[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000780[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000780[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000780[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000780[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000780[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000780[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000780[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000780[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000784[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000784[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000784[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000784[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000784[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000784[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000784[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000784[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000784[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000788[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000788[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000788[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000788[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000788[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000788[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000788[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000788[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000788[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800078C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800078C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800078C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800078C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800078C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800078C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800078C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800078C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800078C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000790[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000790[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000790[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000790[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000790[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000790[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000790[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000790[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000790[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000794[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000794[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000794[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000794[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000794[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000794[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000794[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000794[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000794[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000798[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000798[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000798[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000798[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000798[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000798[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000798[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000798[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000798[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800079C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800079C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800079C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800079C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800079C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800079C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800079C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800079C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800079C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+	/* .. SDIO0_WP_SEL = 55 */
+	/* .. ==> 0XF8000830[5:0] = 0x00000037U */
+	/* ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U */
+	/* .. SDIO0_CD_SEL = 47 */
+	/* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+	/* ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+	/* .. FINISH: MIO PROGRAMMING */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	/* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* .. START: SRAM/NOR SET OPMODE */
+	/* .. FINISH: SRAM/NOR SET OPMODE */
+	/* .. START: QSPI REGISTERS */
+	/* .. Holdb_dr = 1 */
+	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
+	/* ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. */
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	/* .. FINISH: QSPI REGISTERS */
+	/* .. START: PL POWER ON RESET REGISTERS */
+	/* .. PCFG_POR_CNT_4K = 0 */
+	/* .. ==> 0XF8007000[29:29] = 0x00000000U */
+	/* ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	/* .. FINISH: PL POWER ON RESET REGISTERS */
+	/* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* .. .. START: NAND SET CYCLE */
+	/* .. .. FINISH: NAND SET CYCLE */
+	/* .. .. START: OPMODE */
+	/* .. .. FINISH: OPMODE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS0 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS0 BASE ADDRESS */
+	/* .. .. START: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS1 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS1 BASE ADDRESS */
+	/* .. .. START: USB RESET */
+	/* .. .. .. START: USB0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. DIRECTION_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x0 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB0 RESET */
+	/* .. .. .. START: USB1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB1 RESET */
+	/* .. .. FINISH: USB RESET */
+	/* .. .. START: ENET RESET */
+	/* .. .. .. START: ENET0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET0 RESET */
+	/* .. .. .. START: ENET1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET1 RESET */
+	/* .. .. FINISH: ENET RESET */
+	/* .. .. START: I2C RESET */
+	/* .. .. .. START: I2C0 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C0 RESET */
+	/* .. .. .. START: I2C1 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C1 RESET */
+	/* .. .. FINISH: I2C RESET */
+	/* .. .. START: NOR CHIP SELECT */
+	/* .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. FINISH: NOR CHIP SELECT */
+	/* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_post_config_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: ENABLING LEVEL SHIFTER */
+	/* .. USER_INP_ICT_EN_0 = 3 */
+	/* .. ==> 0XF8000900[1:0] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000003U    VAL : 0x00000003U */
+	/* .. USER_INP_ICT_EN_1 = 3 */
+	/* .. ==> 0XF8000900[3:2] = 0x00000003U */
+	/* ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	/* .. FINISH: ENABLING LEVEL SHIFTER */
+	/* .. START: FPGA RESETS TO 0 */
+	/* .. reserved_3 = 0 */
+	/* .. ==> 0XF8000240[31:25] = 0x00000000U */
+	/* ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U */
+	/* .. FPGA_ACP_RST = 0 */
+	/* .. ==> 0XF8000240[24:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS3_RST = 0 */
+	/* .. ==> 0XF8000240[23:23] = 0x00000000U */
+	/* ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS2_RST = 0 */
+	/* .. ==> 0XF8000240[22:22] = 0x00000000U */
+	/* ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS1_RST = 0 */
+	/* .. ==> 0XF8000240[21:21] = 0x00000000U */
+	/* ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS0_RST = 0 */
+	/* .. ==> 0XF8000240[20:20] = 0x00000000U */
+	/* ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. reserved_2 = 0 */
+	/* .. ==> 0XF8000240[19:18] = 0x00000000U */
+	/* ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. FSSW1_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[17:17] = 0x00000000U */
+	/* ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. FSSW0_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[16:16] = 0x00000000U */
+	/* ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. reserved_1 = 0 */
+	/* .. ==> 0XF8000240[15:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
+	/* .. FPGA_FMSW1_RST = 0 */
+	/* .. ==> 0XF8000240[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. FPGA_FMSW0_RST = 0 */
+	/* .. ==> 0XF8000240[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. FPGA_DMA3_RST = 0 */
+	/* .. ==> 0XF8000240[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. FPGA_DMA2_RST = 0 */
+	/* .. ==> 0XF8000240[10:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. FPGA_DMA1_RST = 0 */
+	/* .. ==> 0XF8000240[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. FPGA_DMA0_RST = 0 */
+	/* .. ==> 0XF8000240[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. reserved = 0 */
+	/* .. ==> 0XF8000240[7:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. FPGA3_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. FPGA2_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. FPGA1_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. FPGA0_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	/* .. FINISH: FPGA RESETS TO 0 */
+	/* .. START: AFI REGISTERS */
+	/* .. .. START: AFI0 REGISTERS */
+	/* .. .. FINISH: AFI0 REGISTERS */
+	/* .. .. START: AFI1 REGISTERS */
+	/* .. .. FINISH: AFI1 REGISTERS */
+	/* .. .. START: AFI2 REGISTERS */
+	/* .. .. FINISH: AFI2 REGISTERS */
+	/* .. .. START: AFI3 REGISTERS */
+	/* .. .. FINISH: AFI3 REGISTERS */
+	/* .. FINISH: AFI REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+
+unsigned long ps7_pll_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: PLL SLCR REGISTERS */
+	/* .. .. START: ARM PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x177 */
+	/* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x1a */
+	/* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. ARM_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. SRCSEL = 0x0 */
+	/* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. .. DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U */
+	/* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U */
+	/* .. .. .. CPU_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. .. CPU_1XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. .. CPU_PERI_CLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	/* .. .. FINISH: ARM PLL INIT */
+	/* .. .. START: DDR PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1db */
+	/* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x15 */
+	/* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. DDR_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. DDR_3XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. DDR_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+	/* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+	/* .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	/* .. .. FINISH: DDR PLL INIT */
+	/* .. .. START: IO PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1f4 */
+	/* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x14 */
+	/* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. IO_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. FINISH: IO PLL INIT */
+	/* .. FINISH: PLL SLCR REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: CLOCK CONTROL SLCR REGISTERS */
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000128[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. DIVISOR0 = 0x34 */
+	/* .. ==> 0XF8000128[13:8] = 0x00000034U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U */
+	/* .. DIVISOR1 = 0x2 */
+	/* .. ==> 0XF8000128[25:20] = 0x00000002U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000138[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000138[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000140[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000140[6:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x8 */
+	/* .. ==> 0XF8000140[13:8] = 0x00000008U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U */
+	/* .. DIVISOR1 = 0x1 */
+	/* .. ==> 0XF8000140[25:20] = 0x00000001U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF800014C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF800014C[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x5 */
+	/* .. ==> 0XF800014C[13:8] = 0x00000005U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	/* .. CLKACT0 = 0x1 */
+	/* .. ==> 0XF8000150[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. CLKACT1 = 0x0 */
+	/* .. ==> 0XF8000150[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000150[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x14 */
+	/* .. ==> 0XF8000150[13:8] = 0x00000014U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+	/* .. CLKACT0 = 0x0 */
+	/* .. ==> 0XF8000154[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. CLKACT1 = 0x1 */
+	/* .. ==> 0XF8000154[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000154[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0xa */
+	/* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
+	/* .. .. START: TRACE CLOCK */
+	/* .. .. FINISH: TRACE CLOCK */
+	/* .. .. CLKACT = 0x1 */
+	/* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR = 0x5 */
+	/* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0xa */
+	/* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x7 */
+	/* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x5 */
+	/* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x14 */
+	/* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	/* .. .. CLK_621_TRUE = 0x1 */
+	/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	/* .. .. DMA_CPU_2XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. USB0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. USB1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U */
+	/* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U */
+	/* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U */
+	/* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. UART0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. UART1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U */
+	/* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U */
+	/* .. .. SMC_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	/* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+	/* .. START: THIS SHOULD BE BLANK */
+	/* .. FINISH: THIS SHOULD BE BLANK */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: DDR INITIALIZATION */
+	/* .. .. START: LOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	/* .. .. FINISH: LOCK DDR */
+	/* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+	/* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU */
+	/* .. .. reg_ddrc_active_ranks = 0x1 */
+	/* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+	/* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_block = 0x1 */
+	/* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
+	/* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
+	/* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
+	/* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
+	/* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
+	/* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU */
+	/* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U */
+	/* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+	/* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	/* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	/* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U */
+	/* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	/* .. .. reg_ddrc_t_rc = 0x1a */
+	/* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+	/* .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU */
+	/* .. .. reg_ddrc_t_rfc_min = 0x54 */
+	/* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+	/* .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U */
+	/* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+	/* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+	/* .. .. reg_ddrc_wr2pre = 0x12 */
+	/* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U */
+	/* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+	/* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_t_faw = 0x15 */
+	/* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+	/* .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U */
+	/* .. .. reg_ddrc_t_ras_max = 0x23 */
+	/* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+	/* .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U */
+	/* .. .. reg_ddrc_t_ras_min = 0x13 */
+	/* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U */
+	/* .. .. reg_ddrc_t_cke = 0x4 */
+	/* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+	/* .. .. reg_ddrc_write_latency = 0x5 */
+	/* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_rd2wr = 0x7 */
+	/* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U */
+	/* .. .. reg_ddrc_wr2rd = 0xe */
+	/* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+	/* .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U */
+	/* .. .. reg_ddrc_t_xp = 0x4 */
+	/* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U */
+	/* .. .. reg_ddrc_pad_pd = 0x0 */
+	/* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd2pre = 0x4 */
+	/* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U */
+	/* .. .. reg_ddrc_t_rcd = 0x7 */
+	/* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	/* .. .. reg_ddrc_t_ccd = 0x4 */
+	/* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_t_rrd = 0x6 */
+	/* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_refresh_margin = 0x2 */
+	/* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_rp = 0x7 */
+	/* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U */
+	/* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+	/* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_sdram = 0x1 */
+	/* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_mobile = 0x0 */
+	/* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_clock_stop_en = 0x0 */
+	/* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_read_latency = 0x7 */
+	/* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+	/* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U */
+	/* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+	/* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_loopback = 0x0 */
+	/* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+	/* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+	/* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_prefer_write = 0x0 */
+	/* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_max_rank_rd = 0xf */
+	/* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU */
+	/* .. .. reg_ddrc_mr_wr = 0x0 */
+	/* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_addr = 0x0 */
+	/* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_data = 0x0 */
+	/* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+	/* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_type = 0x0 */
+	/* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+	/* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	/* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+	/* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+	/* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_t_mrd = 0x4 */
+	/* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	/* .. .. reg_ddrc_emr2 = 0x8 */
+	/* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_emr3 = 0x0 */
+	/* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	/* .. .. reg_ddrc_mr = 0x930 */
+	/* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U */
+	/* .. .. reg_ddrc_emr = 0x4 */
+	/* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	/* .. .. reg_ddrc_burst_rdwr = 0x4 */
+	/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U */
+	/* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+	/* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+	/* .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001670U */
+	/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U */
+	/* .. .. reg_ddrc_burstchop = 0x0 */
+	/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+	/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+	/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_dq = 0x0 */
+	/* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_debug_mode = 0x0 */
+	/* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_level_start = 0x0 */
+	/* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_level_start = 0x0 */
+	/* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq0_wait_t = 0x0 */
+	/* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+	/* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+	/* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+	/* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U */
+	/* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+	/* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U */
+	/* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+	/* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+	/* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	/* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+	/* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+	/* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+	/* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+	/* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+	/* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+	/* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+	/* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+	/* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	/* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+	/* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+	/* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+	/* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U */
+	/* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+	/* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+	/* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+	/* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+	/* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	/* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U */
+	/* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. .. reg_phy_rd_local_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U */
+	/* .. .. reg_phy_idle_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U */
+	/* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	/* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+	/* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U */
+	/* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+	/* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_fixed_re = 0x1 */
+	/* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+	/* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+	/* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_clk_stall_level = 0x0 */
+	/* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	/* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U */
+	/* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+	/* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+	/* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+	/* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U */
+	/* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+	/* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+	/* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+	/* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	/* .. .. reg_ddrc_pageclose = 0x0 */
+	/* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+	/* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+	/* .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU */
+	/* .. .. reg_ddrc_auto_pre_en = 0x0 */
+	/* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_refresh_update_level = 0x0 */
+	/* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_wc = 0x0 */
+	/* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+	/* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_selfref_en = 0x0 */
+	/* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	/* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+	/* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U */
+	/* .. .. reg_arb_go2critical_en = 0x1 */
+	/* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	/* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+	/* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U */
+	/* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+	/* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U */
+	/* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+	/* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	/* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+	/* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U */
+	/* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+	/* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	/* .. .. refresh_timer0_start_value_x32 = 0x0 */
+	/* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U */
+	/* .. .. refresh_timer1_start_value_x32 = 0x8 */
+	/* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+	/* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+	/* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_ddr3 = 0x1 */
+	/* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_mod = 0x200 */
+	/* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U */
+	/* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+	/* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+	/* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+	/* .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	/* .. .. t_zq_short_interval_x1024 = 0xc845 */
+	/* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+	/* .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U */
+	/* .. .. dram_rstn_x1024 = 0x67 */
+	/* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+	/* .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+	/* .. .. deeppowerdown_en = 0x0 */
+	/* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. deeppowerdown_to_x1024 = 0xff */
+	/* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+	/* .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	/* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU */
+	/* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U */
+	/* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+	/* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+	/* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	/* .. .. reg_ddrc_2t_delay = 0x0 */
+	/* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_skip_ocd = 0x1 */
+	/* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
+	/* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+	/* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+	/* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+	/* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+	/* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	/* .. .. START: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	/* .. .. FINISH: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	/* .. .. CORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+	/* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	/* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	/* .. .. STAT_NUM_CORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U */
+	/* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_ecc_mode = 0x0 */
+	/* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_scrub = 0x1 */
+	/* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	/* .. .. reg_phy_dif_on = 0x0 */
+	/* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_dif_off = 0x0 */
+	/* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+	/* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+	/* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+	/* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+	/* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+	/* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+	/* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+	/* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+	/* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+	/* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+	/* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+	/* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+	/* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+	/* .. .. reg_phy_loopback = 0x0 */
+	/* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bl2 = 0x0 */
+	/* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_at_spd_atpg = 0x0 */
+	/* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_enable = 0x0 */
+	/* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_force_err = 0x0 */
+	/* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_mode = 0x0 */
+	/* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. .. reg_phy_invert_clkout = 0x1 */
+	/* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
+	/* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_phy_sel_logic = 0x0 */
+	/* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+	/* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U */
+	/* .. .. reg_phy_ctrl_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_rank0_delays = 0x1 */
+	/* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. reg_phy_lpddr = 0x0 */
+	/* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_cmd_latency = 0x0 */
+	/* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_int_lpbk = 0x0 */
+	/* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+	/* .. .. reg_phy_wr_rl_delay = 0x2 */
+	/* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U */
+	/* .. .. reg_phy_rd_rl_delay = 0x4 */
+	/* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U */
+	/* .. .. reg_phy_dll_lock_diff = 0xf */
+	/* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U */
+	/* .. .. reg_phy_use_wr_level = 0x1 */
+	/* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U */
+	/* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U */
+	/* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+	/* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_dis_calib_rst = 0x0 */
+	/* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	/* .. .. reg_arb_page_addr_mask = 0x0 */
+	/* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_ddrc_lpddr2 = 0x0 */
+	/* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_per_bank_refresh = 0x0 */
+	/* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_derate_enable = 0x0 */
+	/* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr4_margin = 0x0 */
+	/* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+	/* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+	/* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+	/* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U */
+	/* .. .. reg_ddrc_t_mrw = 0x5 */
+	/* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	/* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+	/* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U */
+	/* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+	/* .. .. START: POLL ON DCI STATUS */
+	/* .. .. DONE = 1 */
+	/* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	/* .. .. FINISH: POLL ON DCI STATUS */
+	/* .. .. START: UNLOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0x1 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	/* .. .. FINISH: UNLOCK DDR */
+	/* .. .. START: CHECK DDR STATUS */
+	/* .. .. ddrc_reg_operating_mode = 1 */
+	/* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	/* .. .. FINISH: CHECK DDR STATUS */
+	/* .. FINISH: DDR INITIALIZATION */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: OCM REMAPPING */
+	/* .. VREF_EN = 0x1 */
+	/* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. CLK_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. SRSTN_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
+	/* .. FINISH: OCM REMAPPING */
+	/* .. START: DDRIOB SETTINGS */
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x3 */
+	/* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U */
+	/* .. SLEW_N = 0x3 */
+	/* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. VREF_INT_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. VREF_SEL = 0x0 */
+	/* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U */
+	/* .. VREF_EXT_EN = 0x3 */
+	/* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. REFIO_EN = 0x1 */
+	/* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. REFIO_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DRST_B_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. CKE_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
+	/* .. .. START: ASSERT RESET */
+	/* .. .. RESET = 1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+	/* .. .. FINISH: ASSERT RESET */
+	/* .. .. START: DEASSERT RESET */
+	/* .. .. RESET = 0 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	/* .. .. FINISH: DEASSERT RESET */
+	/* .. .. RESET = 0x1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. ENABLE = 0x1 */
+	/* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. VRP_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. VRN_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. VRP_OUT = 0x0 */
+	/* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. NREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT4 = 0x1 */
+	/* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U */
+	/* .. .. PREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U */
+	/* .. .. PREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U */
+	/* .. .. UPDATE_CONTROL = 0x0 */
+	/* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. INIT_COMPLETE = 0x0 */
+	/* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. TST_CLK = 0x0 */
+	/* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. TST_HLN = 0x0 */
+	/* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. TST_HLP = 0x0 */
+	/* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. TST_RST = 0x0 */
+	/* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. INT_DCI_EN = 0x0 */
+	/* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+	/* .. FINISH: DDRIOB SETTINGS */
+	/* .. START: MIO PROGRAMMING */
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000700[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000700[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000700[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000700[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000700[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000700[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000700[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000700[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000700[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000704[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000704[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000704[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000704[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000704[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000704[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000704[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000704[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000704[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000708[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000708[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000708[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000708[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000708[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000708[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000708[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000708[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000708[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800070C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800070C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800070C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800070C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800070C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800070C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800070C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800070C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800070C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000710[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000710[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000710[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000710[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000710[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000710[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000710[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000710[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000710[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000714[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000714[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000714[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000714[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000714[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000714[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000714[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000714[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000714[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000718[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000718[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000718[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000718[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000718[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000718[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000718[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000718[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000718[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800071C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800071C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800071C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800071C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800071C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800071C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800071C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800071C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800071C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000720[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000720[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000720[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000720[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000720[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000720[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000720[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000720[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000720[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000724[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000724[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000724[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000724[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000724[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000724[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000724[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000724[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000724[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000728[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000728[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000728[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000728[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000728[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000728[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000728[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000728[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000728[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800072C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800072C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800072C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800072C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800072C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800072C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800072C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800072C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800072C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000730[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000730[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000730[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000730[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000730[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000730[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000730[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000730[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000730[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000734[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000734[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000734[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000734[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000734[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000734[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000734[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000734[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000734[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000738[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000738[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000738[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000738[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000738[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000738[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000738[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000738[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000738[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800073C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800073C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800073C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800073C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800073C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800073C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800073C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800073C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800073C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000740[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000740[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000740[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000740[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000740[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000740[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000740[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000740[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000740[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000744[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000744[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000744[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000744[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000744[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000744[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000744[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000744[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000744[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000748[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000748[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000748[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000748[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000748[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000748[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000748[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000748[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000748[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800074C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800074C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800074C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800074C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800074C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800074C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800074C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800074C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF800074C[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000750[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000750[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000750[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000750[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000750[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000750[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000750[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000750[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000750[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000754[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000754[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000754[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000754[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000754[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000754[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000754[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000754[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000754[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000758[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000758[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000758[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000758[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000758[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000758[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000758[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000758[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000758[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800075C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800075C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800075C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800075C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800075C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800075C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800075C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800075C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800075C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000760[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000760[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000760[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000760[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000760[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000760[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000760[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000760[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000760[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000764[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000764[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000764[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000764[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000764[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000764[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000764[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000764[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000764[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000768[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000768[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000768[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000768[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000768[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000768[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000768[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000768[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000768[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800076C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800076C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800076C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800076C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800076C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800076C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800076C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800076C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800076C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000770[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000770[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000770[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000770[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000770[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000770[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000770[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000770[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000770[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000774[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000774[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000774[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000774[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000774[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000774[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000774[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000774[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000774[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000778[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000778[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000778[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000778[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000778[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000778[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000778[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000778[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000778[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800077C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800077C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800077C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800077C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800077C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800077C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800077C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800077C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800077C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000780[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000780[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000780[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000780[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000780[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000780[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000780[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000780[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000780[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000784[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000784[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000784[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000784[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000784[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000784[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000784[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000784[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000784[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000788[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000788[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000788[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000788[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000788[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000788[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000788[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000788[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000788[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800078C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800078C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800078C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800078C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800078C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800078C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800078C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800078C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800078C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000790[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000790[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000790[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000790[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000790[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000790[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000790[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000790[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000790[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000794[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000794[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000794[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000794[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000794[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000794[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000794[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000794[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000794[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000798[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000798[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000798[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000798[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000798[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000798[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000798[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000798[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000798[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800079C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800079C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800079C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800079C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800079C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800079C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800079C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800079C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800079C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+	/* .. SDIO0_WP_SEL = 55 */
+	/* .. ==> 0XF8000830[5:0] = 0x00000037U */
+	/* ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U */
+	/* .. SDIO0_CD_SEL = 47 */
+	/* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+	/* ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+	/* .. FINISH: MIO PROGRAMMING */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	/* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* .. START: SRAM/NOR SET OPMODE */
+	/* .. FINISH: SRAM/NOR SET OPMODE */
+	/* .. START: QSPI REGISTERS */
+	/* .. Holdb_dr = 1 */
+	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
+	/* ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. */
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	/* .. FINISH: QSPI REGISTERS */
+	/* .. START: PL POWER ON RESET REGISTERS */
+	/* .. PCFG_POR_CNT_4K = 0 */
+	/* .. ==> 0XF8007000[29:29] = 0x00000000U */
+	/* ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	/* .. FINISH: PL POWER ON RESET REGISTERS */
+	/* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* .. .. START: NAND SET CYCLE */
+	/* .. .. FINISH: NAND SET CYCLE */
+	/* .. .. START: OPMODE */
+	/* .. .. FINISH: OPMODE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS0 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS0 BASE ADDRESS */
+	/* .. .. START: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS1 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS1 BASE ADDRESS */
+	/* .. .. START: USB RESET */
+	/* .. .. .. START: USB0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. DIRECTION_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x0 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB0 RESET */
+	/* .. .. .. START: USB1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB1 RESET */
+	/* .. .. FINISH: USB RESET */
+	/* .. .. START: ENET RESET */
+	/* .. .. .. START: ENET0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET0 RESET */
+	/* .. .. .. START: ENET1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET1 RESET */
+	/* .. .. FINISH: ENET RESET */
+	/* .. .. START: I2C RESET */
+	/* .. .. .. START: I2C0 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C0 RESET */
+	/* .. .. .. START: I2C1 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C1 RESET */
+	/* .. .. FINISH: I2C RESET */
+	/* .. .. START: NOR CHIP SELECT */
+	/* .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. FINISH: NOR CHIP SELECT */
+	/* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_post_config_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: ENABLING LEVEL SHIFTER */
+	/* .. USER_INP_ICT_EN_0 = 3 */
+	/* .. ==> 0XF8000900[1:0] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000003U    VAL : 0x00000003U */
+	/* .. USER_INP_ICT_EN_1 = 3 */
+	/* .. ==> 0XF8000900[3:2] = 0x00000003U */
+	/* ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	/* .. FINISH: ENABLING LEVEL SHIFTER */
+	/* .. START: FPGA RESETS TO 0 */
+	/* .. reserved_3 = 0 */
+	/* .. ==> 0XF8000240[31:25] = 0x00000000U */
+	/* ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U */
+	/* .. FPGA_ACP_RST = 0 */
+	/* .. ==> 0XF8000240[24:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS3_RST = 0 */
+	/* .. ==> 0XF8000240[23:23] = 0x00000000U */
+	/* ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS2_RST = 0 */
+	/* .. ==> 0XF8000240[22:22] = 0x00000000U */
+	/* ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS1_RST = 0 */
+	/* .. ==> 0XF8000240[21:21] = 0x00000000U */
+	/* ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS0_RST = 0 */
+	/* .. ==> 0XF8000240[20:20] = 0x00000000U */
+	/* ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. reserved_2 = 0 */
+	/* .. ==> 0XF8000240[19:18] = 0x00000000U */
+	/* ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. FSSW1_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[17:17] = 0x00000000U */
+	/* ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. FSSW0_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[16:16] = 0x00000000U */
+	/* ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. reserved_1 = 0 */
+	/* .. ==> 0XF8000240[15:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
+	/* .. FPGA_FMSW1_RST = 0 */
+	/* .. ==> 0XF8000240[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. FPGA_FMSW0_RST = 0 */
+	/* .. ==> 0XF8000240[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. FPGA_DMA3_RST = 0 */
+	/* .. ==> 0XF8000240[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. FPGA_DMA2_RST = 0 */
+	/* .. ==> 0XF8000240[10:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. FPGA_DMA1_RST = 0 */
+	/* .. ==> 0XF8000240[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. FPGA_DMA0_RST = 0 */
+	/* .. ==> 0XF8000240[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. reserved = 0 */
+	/* .. ==> 0XF8000240[7:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. FPGA3_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. FPGA2_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. FPGA1_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. FPGA0_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	/* .. FINISH: FPGA RESETS TO 0 */
+	/* .. START: AFI REGISTERS */
+	/* .. .. START: AFI0 REGISTERS */
+	/* .. .. FINISH: AFI0 REGISTERS */
+	/* .. .. START: AFI1 REGISTERS */
+	/* .. .. FINISH: AFI1 REGISTERS */
+	/* .. .. START: AFI2 REGISTERS */
+	/* .. .. FINISH: AFI2 REGISTERS */
+	/* .. .. START: AFI3 REGISTERS */
+	/* .. .. FINISH: AFI3 REGISTERS */
+	/* .. FINISH: AFI REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+
+#include "xil_io.h"
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	/* Get the PS_VERSION on run time */
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	/* Get the PS_VERSION on run time */
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+	/*int pcw_ver = 0; */
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+		/*pcw_ver = 1; */
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+		/*pcw_ver = 2; */
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+		/*pcw_ver = 3; */
+	}
+
+	/* MIO init */
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	/* PLL init */
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	/* Clock init */
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	/* DDR init */
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	/* Peripherals init */
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
+
diff --git a/roms/u-boot/board/xilinx/zynqmp/Kconfig b/roms/u-boot/board/xilinx/zynqmp/Kconfig
new file mode 100644
index 000000000..7d1f7398c
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/Kconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Xilinx, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_ZYNQMP
+
+config CMD_ZYNQMP
+	bool "Enable ZynqMP specific commands"
+	default y
+	help
+	  Enable ZynqMP specific commands like "zynqmp secure"
+	  which is used for zynqmp secure image verification.
+	  The secure image is a xilinx specific BOOT.BIN with
+	  either authentication or encryption or both encryption
+	  and authentication feature enabled while generating
+	  BOOT.BIN using Xilinx bootgen tool.
+
+endif
diff --git a/roms/u-boot/board/xilinx/zynqmp/MAINTAINERS b/roms/u-boot/board/xilinx/zynqmp/MAINTAINERS
new file mode 100644
index 000000000..56c637943
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/MAINTAINERS
@@ -0,0 +1,17 @@
+XILINX_ZYNQMP BOARDS
+M:	Michal Simek <michal.simek@xilinx.com>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+F:	arch/arm/dts/zynqmp-*
+F:	arch/arm/dts/avnet-ultra96*
+F:	board/xilinx/common/
+F:	board/xilinx/zynqmp/
+F:	include/configs/xilinx_zynqmp*
+F:	configs/xilinx_zynqmp*
+F:	configs/avnet_ultra96_rev1_defconfig
+
+ARM ZYNQMP AVNET ULTRAZED EV BOARD
+M:	Luca Ceresoli <luca@lucaceresoli.net>
+S:	Maintained
+F:	arch/arm/dts/avnet-ultrazedev-*
+F:	configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
diff --git a/roms/u-boot/board/xilinx/zynqmp/Makefile b/roms/u-boot/board/xilinx/zynqmp/Makefile
new file mode 100644
index 000000000..7d8277ca4
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/Makefile
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2014 - 2016 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+
+obj-y	:= zynqmp.o
+
+ifneq ($(CONFIG_XILINX_PS_INIT_FILE),"")
+PS_INIT_FILE := $(shell cd $(srctree); readlink -f $(CONFIG_XILINX_PS_INIT_FILE))
+init-objs := ps_init_gpl.o
+spl/board/xilinx/zynqmp/ps_init_gpl.o board/xilinx/zynqmp/ps_init_gpl.o: $(PS_INIT_FILE)
+	$(CC) $(c_flags) -I $(srctree)/$(src) -c -o $@ $^
+endif
+
+DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
+ifeq ($(DEVICE_TREE),)
+DEVICE_TREE := unset
+endif
+
+ifeq ($(init-objs),)
+hw-platform-y :=$(shell echo $(DEVICE_TREE))
+init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
+	$(hw-platform-y)/psu_init_gpl.o)
+endif
+
+ifeq ($(init-objs),)
+ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),)
+init-objs := psu_init_gpl.o
+$(if $(CONFIG_SPL_BUILD),\
+$(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/))
+endif
+endif
+
+ifdef_any_of = $(filter-out undefined,$(foreach v,$(1),$(origin $(v))))
+
+ifneq ($(call ifdef_any_of, CONFIG_ZYNQMP_PSU_INIT_ENABLED CONFIG_SPL_BUILD),)
+obj-y += $(init-objs)
+endif
+
+ifdef CONFIG_SPL_BUILD
+ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"")
+obj-$(CONFIG_SPL_BUILD) += pm_cfg_obj.o
+$(obj)/pm_cfg_obj.o: $(shell cd $(srctree); readlink -f $(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE)) FORCE
+endif
+endif
+
+obj-$(CONFIG_MMC_SDHCI_ZYNQ) += tap_delays.o
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_ZYNQMP) += cmds.o
+endif
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
+
+# To include xil_io.h
+CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src)
+
+# To suppress "warning: cast to pointer from integer of different size"
+CFLAGS_psu_init_gpl.o += -Wno-int-to-pointer-cast
diff --git a/roms/u-boot/board/xilinx/zynqmp/avnet-ultra96-rev1 b/roms/u-boot/board/xilinx/zynqmp/avnet-ultra96-rev1
new file mode 120000
index 000000000..f2beed309
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/avnet-ultra96-rev1
@@ -0,0 +1 @@
+zynqmp-zcu100-revC
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c
new file mode 100644
index 000000000..d030e7977
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c
@@ -0,0 +1,655 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U);
+	psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000303U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00409410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x009280D2U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0048051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020126U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002705U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09340301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x131C2813U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041CU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0808050FU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x05050D08U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002040CU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1308010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201C9C2U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820DU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A0BU);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F12090U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x4B025810U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xEA601518U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08261009U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28380008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01A42B08U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00371009U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00001010U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000300U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000834U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AEA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x200E0000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02006U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+	psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
+	mask_delay(5);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/cmds.c b/roms/u-boot/board/xilinx/zynqmp/cmds.c
new file mode 100644
index 000000000..cf63ad97f
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/cmds.c
@@ -0,0 +1,440 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <zynqmp_firmware.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+struct aes {
+	u64 srcaddr;
+	u64 ivaddr;
+	u64 keyaddr;
+	u64 dstaddr;
+	u64 len;
+	u64 op;
+	u64 keysrc;
+};
+
+static int do_zynqmp_verify_secure(struct cmd_tbl *cmdtp, int flag, int argc,
+				   char *const argv[])
+{
+	u64 src_addr, addr;
+	u32 len, src_lo, src_hi;
+	u8 *key_ptr = NULL;
+	int ret;
+	u32 key_lo = 0;
+	u32 key_hi = 0;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+
+	if (argc < 4)
+		return CMD_RET_USAGE;
+
+	src_addr = simple_strtoull(argv[2], NULL, 16);
+	len = simple_strtoul(argv[3], NULL, 16);
+
+	if (argc == 5)
+		key_ptr = (uint8_t *)(uintptr_t)simple_strtoull(argv[4],
+								NULL, 16);
+
+	if ((ulong)src_addr != ALIGN((ulong)src_addr,
+				     CONFIG_SYS_CACHELINE_SIZE)) {
+		printf("Failed: source address not aligned:%lx\n",
+		       (ulong)src_addr);
+		return -EINVAL;
+	}
+
+	src_lo = lower_32_bits((ulong)src_addr);
+	src_hi = upper_32_bits((ulong)src_addr);
+	flush_dcache_range((ulong)src_addr, (ulong)(src_addr + len));
+
+	if (key_ptr) {
+		key_lo = lower_32_bits((ulong)key_ptr);
+		key_hi = upper_32_bits((ulong)key_ptr);
+		flush_dcache_range((ulong)key_ptr,
+				   (ulong)(key_ptr + KEY_PTR_LEN));
+	}
+
+	ret = xilinx_pm_request(PM_SECURE_IMAGE, src_lo, src_hi,
+				key_lo, key_hi, ret_payload);
+	if (ret) {
+		printf("Failed: secure op status:0x%x\n", ret);
+	} else {
+		addr = (u64)ret_payload[1] << 32 | ret_payload[2];
+		printf("Verified image at 0x%llx\n", addr);
+		env_set_hex("zynqmp_verified_img_addr", addr);
+	}
+
+	return ret;
+}
+
+static int do_zynqmp_mmio_read(struct cmd_tbl *cmdtp, int flag, int argc,
+			       char *const argv[])
+{
+	u32 read_val, addr;
+	int ret;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+
+	ret = zynqmp_mmio_read(addr, &read_val);
+	if (!ret)
+		printf("mmio read value at 0x%x = 0x%x\n",
+		       addr, read_val);
+	else
+		printf("Failed: mmio read\n");
+
+	return ret;
+}
+
+static int do_zynqmp_mmio_write(struct cmd_tbl *cmdtp, int flag, int argc,
+				char *const argv[])
+{
+	u32 addr, mask, val;
+	int ret;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	mask = simple_strtoul(argv[3], NULL, 16);
+	val = simple_strtoul(argv[4], NULL, 16);
+
+	ret = zynqmp_mmio_write(addr, mask, val);
+	if (ret != 0)
+		printf("Failed: mmio write\n");
+
+	return ret;
+}
+
+static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char * const argv[])
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct aes, aes, 1);
+	int ret;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+
+	if (zynqmp_firmware_version() <= PMUFW_V1_0) {
+		puts("ERR: PMUFW v1.0 or less is detected\n");
+		puts("ERR: Encrypt/Decrypt feature is not supported\n");
+		puts("ERR: Please upgrade PMUFW\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (argc < cmdtp->maxargs - 1)
+		return CMD_RET_USAGE;
+
+	aes->srcaddr = simple_strtoul(argv[2], NULL, 16);
+	aes->ivaddr = simple_strtoul(argv[3], NULL, 16);
+	aes->len = simple_strtoul(argv[4], NULL, 16);
+	aes->op = simple_strtoul(argv[5], NULL, 16);
+	aes->keysrc = simple_strtoul(argv[6], NULL, 16);
+	aes->dstaddr = simple_strtoul(argv[7], NULL, 16);
+
+	flush_dcache_range((ulong)aes, (ulong)(aes) +
+			   roundup(sizeof(struct aes), ARCH_DMA_MINALIGN));
+
+	if (aes->srcaddr && aes->ivaddr && aes->dstaddr) {
+		flush_dcache_range(aes->srcaddr,
+				   (aes->srcaddr +
+				    roundup(aes->len, ARCH_DMA_MINALIGN)));
+		flush_dcache_range(aes->ivaddr,
+				   (aes->ivaddr +
+				    roundup(IV_SIZE, ARCH_DMA_MINALIGN)));
+		flush_dcache_range(aes->dstaddr,
+				   (aes->dstaddr +
+				    roundup(aes->len, ARCH_DMA_MINALIGN)));
+	}
+
+	if (aes->keysrc == 0) {
+		if (argc < cmdtp->maxargs)
+			return CMD_RET_USAGE;
+
+		aes->keyaddr = simple_strtoul(argv[8], NULL, 16);
+		if (aes->keyaddr)
+			flush_dcache_range(aes->keyaddr,
+					   (aes->keyaddr +
+					    roundup(KEY_PTR_LEN,
+						    ARCH_DMA_MINALIGN)));
+	}
+
+	ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
+				lower_32_bits((ulong)aes), 0, 0, ret_payload);
+	if (ret || ret_payload[1])
+		printf("Failed: AES op status:0x%x, errcode:0x%x\n",
+		       ret, ret_payload[1]);
+
+	return ret;
+}
+
+#ifdef CONFIG_DEFINE_TCM_OCM_MMAP
+static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc,
+			      char *const argv[])
+{
+	u8 mode;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	mode = simple_strtoul(argv[2], NULL, 16);
+	if (mode != TCM_LOCK && mode != TCM_SPLIT) {
+		printf("Mode should be either 0(lock)/1(split)\n");
+		return CMD_RET_FAILURE;
+	}
+
+	dcache_disable();
+	tcm_init(mode);
+	dcache_enable();
+
+	return CMD_RET_SUCCESS;
+}
+#endif
+
+static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char * const argv[])
+{
+	u32 addr, size;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	size = simple_strtoul(argv[3], NULL, 16);
+	flush_dcache_range((ulong)addr, (ulong)(addr + size));
+
+	zynqmp_pmufw_load_config_object((const void *)(uintptr_t)addr,
+					(size_t)size);
+
+	return 0;
+}
+
+static int do_zynqmp_rsa(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char * const argv[])
+{
+	u64 srcaddr, mod, exp;
+	u32 srclen, rsaop, size, ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	if (zynqmp_firmware_version() <= PMUFW_V1_0) {
+		puts("ERR: PMUFW v1.0 or less is detected\n");
+		puts("ERR: Encrypt/Decrypt feature is not supported\n");
+		puts("ERR: Please upgrade PMUFW\n");
+		return CMD_RET_FAILURE;
+	}
+
+	srcaddr = simple_strtoul(argv[2], NULL, 16);
+	srclen = simple_strtoul(argv[3], NULL, 16);
+	if (srclen != RSA_KEY_SIZE) {
+		puts("ERR: srclen should be equal to 0x200(512 bytes)\n");
+		return CMD_RET_USAGE;
+	}
+
+	mod = simple_strtoul(argv[4], NULL, 16);
+	exp = simple_strtoul(argv[5], NULL, 16);
+	rsaop = simple_strtoul(argv[6], NULL, 16);
+	if (!(rsaop == 0 || rsaop == 1)) {
+		puts("ERR: rsaop should be either 0 or 1\n");
+		return CMD_RET_USAGE;
+	}
+
+	memcpy((void *)srcaddr + srclen, (void *)mod, MODULUS_LEN);
+
+	/*
+	 * For encryption we load public exponent (key size 4096-bits),
+	 * for decryption we load private exponent (32-bits)
+	 */
+	if (rsaop) {
+		memcpy((void *)srcaddr + srclen + MODULUS_LEN,
+		       (void *)exp, PUB_EXPO_LEN);
+		size = srclen + MODULUS_LEN + PUB_EXPO_LEN;
+	} else {
+		memcpy((void *)srcaddr + srclen + MODULUS_LEN,
+		       (void *)exp, PRIV_EXPO_LEN);
+		size = srclen + MODULUS_LEN + PRIV_EXPO_LEN;
+	}
+
+	flush_dcache_range((ulong)srcaddr,
+			   (ulong)(srcaddr) + roundup(size, ARCH_DMA_MINALIGN));
+
+	ret = xilinx_pm_request(PM_SECURE_RSA, upper_32_bits((ulong)srcaddr),
+				lower_32_bits((ulong)srcaddr), srclen, rsaop,
+				ret_payload);
+	if (ret || ret_payload[1]) {
+		printf("Failed: RSA status:0x%x, errcode:0x%x\n",
+		       ret, ret_payload[1]);
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_zynqmp_sha3(struct cmd_tbl *cmdtp, int flag,
+			  int argc, char * const argv[])
+{
+	u64 srcaddr, hashaddr;
+	u32 srclen, ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	if (argc > cmdtp->maxargs || argc < (cmdtp->maxargs - 1))
+		return CMD_RET_USAGE;
+
+	if (zynqmp_firmware_version() <= PMUFW_V1_0) {
+		puts("ERR: PMUFW v1.0 or less is detected\n");
+		puts("ERR: Encrypt/Decrypt feature is not supported\n");
+		puts("ERR: Please upgrade PMUFW\n");
+		return CMD_RET_FAILURE;
+	}
+
+	srcaddr = simple_strtoul(argv[2], NULL, 16);
+	srclen = simple_strtoul(argv[3], NULL, 16);
+
+	if (argc == 5) {
+		hashaddr = simple_strtoul(argv[4], NULL, 16);
+		flush_dcache_range(hashaddr,
+				   hashaddr + roundup(ZYNQMP_SHA3_SIZE,
+						      ARCH_DMA_MINALIGN));
+	} else {
+		hashaddr = srcaddr;
+	}
+
+	/* Check srcaddr or srclen != 0 */
+	if (!srcaddr || !srclen) {
+		puts("ERR: srcaddr & srclen should not be 0\n");
+		return CMD_RET_USAGE;
+	}
+
+	flush_dcache_range(srcaddr,
+			   srcaddr + roundup(srclen, ARCH_DMA_MINALIGN));
+
+	ret = xilinx_pm_request(PM_SECURE_SHA, 0, 0, 0,
+				ZYNQMP_SHA3_INIT, ret_payload);
+	if (ret || ret_payload[1]) {
+		printf("Failed: SHA INIT status:0x%x, errcode:0x%x\n",
+		       ret, ret_payload[1]);
+		return CMD_RET_FAILURE;
+	}
+
+	ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)srcaddr),
+				lower_32_bits((ulong)srcaddr),
+				srclen, ZYNQMP_SHA3_UPDATE, ret_payload);
+	if (ret || ret_payload[1]) {
+		printf("Failed: SHA UPDATE status:0x%x, errcode:0x%x\n",
+		       ret, ret_payload[1]);
+		return CMD_RET_FAILURE;
+	}
+
+	ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)hashaddr),
+				lower_32_bits((ulong)hashaddr),
+				ZYNQMP_SHA3_SIZE, ZYNQMP_SHA3_FINAL,
+				ret_payload);
+	if (ret || ret_payload[1]) {
+		printf("Failed: SHA FINAL status:0x%x, errcode:0x%x\n",
+		       ret, ret_payload[1]);
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static struct cmd_tbl cmd_zynqmp_sub[] = {
+	U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""),
+	U_BOOT_CMD_MKENT(pmufw, 4, 0, do_zynqmp_pmufw, "", ""),
+	U_BOOT_CMD_MKENT(mmio_read, 3, 0, do_zynqmp_mmio_read, "", ""),
+	U_BOOT_CMD_MKENT(mmio_write, 5, 0, do_zynqmp_mmio_write, "", ""),
+	U_BOOT_CMD_MKENT(aes, 9, 0, do_zynqmp_aes, "", ""),
+	U_BOOT_CMD_MKENT(rsa, 7, 0, do_zynqmp_rsa, "", ""),
+	U_BOOT_CMD_MKENT(sha3, 5, 0, do_zynqmp_sha3, "", ""),
+#ifdef CONFIG_DEFINE_TCM_OCM_MMAP
+	U_BOOT_CMD_MKENT(tcminit, 3, 0, do_zynqmp_tcm_init, "", ""),
+#endif
+};
+
+/**
+ * do_zynqmp - Handle the "zynqmp" command-line command
+ * @cmdtp:	Command data struct pointer
+ * @flag:	Command flag
+ * @argc:	Command-line argument count
+ * @argv:	Array of command-line arguments
+ *
+ * Processes the zynqmp specific commands
+ *
+ * Return: return 0 on success and CMD_RET_USAGE incase of misuse and error
+ */
+static int do_zynqmp(struct cmd_tbl *cmdtp, int flag, int argc,
+		     char *const argv[])
+{
+	struct cmd_tbl *c;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	c = find_cmd_tbl(argv[1], &cmd_zynqmp_sub[0],
+			 ARRAY_SIZE(cmd_zynqmp_sub));
+
+	if (c)
+		return c->cmd(c, flag, argc, argv);
+	else
+		return CMD_RET_USAGE;
+}
+
+/***************************************************/
+#ifdef CONFIG_SYS_LONGHELP
+static char zynqmp_help_text[] =
+	"secure src len [key_addr] - verifies secure images of $len bytes\n"
+	"                            long at address $src. Optional key_addr\n"
+	"                            can be specified if user key needs to\n"
+	"                            be used for decryption\n"
+	"zynqmp mmio_read address - read from address\n"
+	"zynqmp mmio_write address mask value - write value after masking to\n"
+	"					address\n"
+	"zynqmp aes srcaddr ivaddr len aesop keysrc dstaddr [keyaddr] -\n"
+	"	Encrypts or decrypts blob of data at src address and puts it\n"
+	"	back to dstaddr using key and iv at keyaddr and ivaddr\n"
+	"	respectively. keysrc value specifies from which source key\n"
+	"	has to be used, it can be User/Device/PUF key. A value of 0\n"
+	"	for KUP(user key),1 for DeviceKey and 2 for PUF key. The\n"
+	"	aesop value specifies the operation which can be 0 for\n"
+	"	decrypt and 1 for encrypt operation\n"
+#ifdef CONFIG_DEFINE_TCM_OCM_MMAP
+	"zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n"
+	"		       initialized before accessing to avoid ECC\n"
+	"		       errors. mode specifies in which mode TCM has\n"
+	"		       to be initialized. Supported modes will be\n"
+	"		       lock(0)/split(1)\n"
+#endif
+	"zynqmp pmufw address size - load PMU FW configuration object\n"
+	"zynqmp rsa srcaddr srclen mod exp rsaop -\n"
+	"	Performs RSA encryption and RSA decryption on blob of data\n"
+	"	at srcaddr and puts it back in srcaddr using modulus and\n"
+	"	public or private exponent\n"
+	"	srclen : must be key size(4096 bits)\n"
+	"	exp :	private key exponent for RSA decryption(4096 bits)\n"
+	"		public key exponent for RSA encryption(32 bits)\n"
+	"	rsaop :	0 for RSA Decryption, 1 for RSA Encryption\n"
+	"zynqmp sha3 srcaddr srclen [key_addr] -\n"
+	"	Generates sha3 hash value for data blob at srcaddr and puts\n"
+	"	48 bytes hash value into srcaddr\n"
+	"	Optional key_addr can be specified for saving sha3 hash value\n"
+	"	Note: srcaddr/srclen should not be 0\n"
+	;
+#endif
+
+U_BOOT_CMD(
+	zynqmp, 9, 1, do_zynqmp,
+	"ZynqMP sub-system",
+	zynqmp_help_text
+)
diff --git a/roms/u-boot/board/xilinx/zynqmp/pm_cfg_obj.S b/roms/u-boot/board/xilinx/zynqmp/pm_cfg_obj.S
new file mode 100644
index 000000000..c4ca77e39
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/pm_cfg_obj.S
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+.section .rodata
+
+.global zynqmp_pm_cfg_obj
+.type   zynqmp_pm_cfg_obj, @object
+.global zynqmp_pm_cfg_obj_size
+.type   zynqmp_pm_cfg_obj_size, @object
+
+zynqmp_pm_cfg_obj:
+.align 4
+.incbin CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE
+
+zynqmp_pm_cfg_obj_end:
+
+zynqmp_pm_cfg_obj_size:
+.int zynqmp_pm_cfg_obj_end - zynqmp_pm_cfg_obj
diff --git a/roms/u-boot/board/xilinx/zynqmp/pm_cfg_obj.h b/roms/u-boot/board/xilinx/zynqmp/pm_cfg_obj.h
new file mode 100644
index 000000000..86e785490
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/pm_cfg_obj.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Luca Ceresoli <luca@lucaceresoli.net>
+ *
+ * Declaration of PMU config object binary blob linked in at build time.
+ */
+
+extern const u32 zynqmp_pm_cfg_obj[];
+extern const int zynqmp_pm_cfg_obj_size;
diff --git a/roms/u-boot/board/xilinx/zynqmp/sleep.h b/roms/u-boot/board/xilinx/zynqmp/sleep.h
new file mode 100644
index 000000000..a962319ff
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/sleep.h
@@ -0,0 +1 @@
+/* Intentionally empty file for psu_init* */
diff --git a/roms/u-boot/board/xilinx/zynqmp/tap_delays.c b/roms/u-boot/board/xilinx/zynqmp/tap_delays.c
new file mode 100644
index 000000000..1cab25f00
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/tap_delays.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx ZynqMP SoC Tap Delay Programming
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <zynqmp_tap_delay.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/delay.h>
+#include <mmc.h>
+
+#define SD_DLL_CTRL			0xFF180358
+#define SD_ITAP_DLY			0xFF180314
+#define SD_OTAP_DLY			0xFF180318
+#define SD0_DLL_RST_MASK		0x00000004
+#define SD0_DLL_RST			0x00000004
+#define SD1_DLL_RST_MASK		0x00040000
+#define SD1_DLL_RST			0x00040000
+#define SD0_ITAPCHGWIN_MASK		0x00000200
+#define SD0_ITAPCHGWIN			0x00000200
+#define SD1_ITAPCHGWIN_MASK		0x02000000
+#define SD1_ITAPCHGWIN			0x02000000
+#define SD0_ITAPDLYENA_MASK		0x00000100
+#define SD0_ITAPDLYENA			0x00000100
+#define SD1_ITAPDLYENA_MASK		0x01000000
+#define SD1_ITAPDLYENA			0x01000000
+#define SD0_ITAPDLYSEL_MASK		0x000000FF
+#define SD1_ITAPDLYSEL_MASK		0x00FF0000
+#define SD0_OTAPDLYSEL_MASK		0x0000003F
+#define SD1_OTAPDLYSEL_MASK		0x003F0000
+
+void zynqmp_dll_reset(u8 deviceid)
+{
+	/* Issue DLL Reset */
+	if (deviceid == 0)
+		zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
+				  SD0_DLL_RST);
+	else
+		zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
+				  SD1_DLL_RST);
+
+	mdelay(1);
+
+	/* Release DLL Reset */
+	if (deviceid == 0)
+		zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
+	else
+		zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
+}
+
+void arasan_zynqmp_set_tapdelay(u8 deviceid, u32 itap_delay, u32 otap_delay)
+{
+	if (deviceid == 0) {
+		zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
+				  SD0_DLL_RST);
+		/* Program ITAP */
+		if (itap_delay) {
+			zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
+					  SD0_ITAPCHGWIN);
+			zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
+					  SD0_ITAPDLYENA);
+			zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
+					  itap_delay);
+			zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
+					  0x0);
+		}
+
+		/* Program OTAP */
+		if (otap_delay)
+			zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
+					  otap_delay);
+
+		zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
+	} else {
+		zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
+				  SD1_DLL_RST);
+		/* Program ITAP */
+		if (itap_delay) {
+			zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
+					  SD1_ITAPCHGWIN);
+			zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
+					  SD1_ITAPDLYENA);
+			zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
+					  (itap_delay << 16));
+			zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
+					  0x0);
+		}
+
+		/* Program OTAP */
+		if (otap_delay)
+			zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+					  (otap_delay << 16));
+
+		zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
+	}
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/xil_io.h b/roms/u-boot/board/xilinx/zynqmp/xil_io.h
new file mode 100644
index 000000000..e6caa7c85
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/xil_io.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H
+
+/* FIXME remove this when vivado is fixed */
+#include <asm/io.h>
+#include <common.h>
+#include <linux/delay.h>
+
+#define xil_printf(...)
+
+static void Xil_Out32(unsigned long addr, unsigned long val)
+{
+	writel(val, addr);
+}
+
+static int Xil_In32(unsigned long addr)
+{
+	return readl(addr);
+}
+
+static void __maybe_unused usleep(u32 sleep)
+{
+	udelay(sleep);
+}
+
+#endif /* XIL_IO_H */
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c
new file mode 100644
index 000000000..be9992c90
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c
@@ -0,0 +1,1163 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U);
+	psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000400U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010B02U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000008U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1310U);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0510U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000021U);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0129A4A4U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180204, 0x00FFE000U, 0x00000000U);
+	psu_mask_write(0xFF180208, 0xFFFFE3FCU, 0x00B02240U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000C00U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+	psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD406094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD40506C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4040F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD405990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD405924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD405928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000035U);
+	psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
+
+	return 1;
+}
+
+static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt,
+		      int d_lfhf, int d_cp, int d_res)
+{
+	unsigned int pll_ctrl_regval;
+	unsigned int pll_status_regval;
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U);
+	pll_ctrl_regval = pll_ctrl_regval | (1 << 16);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U);
+	pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U);
+	pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U);
+	pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U);
+	pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU);
+	pll_ctrl_regval = pll_ctrl_regval | (d_res << 0);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U);
+	pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
+	pll_ctrl_regval = pll_ctrl_regval | (1 << 3);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
+	pll_ctrl_regval = pll_ctrl_regval | (1 << 0);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
+	pll_ctrl_regval = pll_ctrl_regval | (0 << 0);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_status_regval = 0x00000000;
+	while ((pll_status_regval & 0x00000002U) != 0x00000002U)
+		pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044));
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
+	pll_ctrl_regval = pll_ctrl_regval | (0 << 3);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+	int cur_PLLCR0;
+
+	cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL0PLLCR0;
+
+	cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL1PLLCR0;
+
+	cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL2PLLCR0;
+
+	cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL3PLLCR0;
+
+	cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL4PLLCR0;
+
+	cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SLBPLLCR0;
+
+	cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+	Xil_Out32(0xFD080068, 0x02120000);
+	Xil_Out32(0xFD081404, 0x02120000);
+	Xil_Out32(0xFD081444, 0x02120000);
+	Xil_Out32(0xFD081484, 0x02120000);
+	Xil_Out32(0xFD0814C4, 0x02120000);
+	Xil_Out32(0xFD081504, 0x02120000);
+	Xil_Out32(0xFD0817C4, 0x02120000);
+	int cur_fbdiv;
+
+	cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U;
+	dpll_prog(48, 63, 625, 3, 3, 2);
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return (0);
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	Xil_Out32(0xFD0701B0U, 0x00000005U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000331U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000B36U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000C21U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000E19U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00001616U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	Xil_Out32(0xFD070010U, 0x80000010U);
+	Xil_Out32(0xFD0701B0U, 0x00000005U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U);
+	prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+	prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U);
+	prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	Xil_Out32(0xFD080068, cur_PLLCR0);
+	Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0);
+	Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0);
+	Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0);
+	Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0);
+	Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0);
+	Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0);
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	dpll_prog(cur_fbdiv, 63, 625, 3, 3, 2);
+	for (int tp = 0; tp < 2000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U);
+	prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	for (int tp = 0; tp < 2000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+	prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U);
+	prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+	for (int tp = 0; tp < 2000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0014FE01);
+
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x8000007E)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x000091C7U);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80008FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return (0);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U);
+	prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U);
+	Xil_Out32(0xFD070180U, 0x02160010U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+	for (int tp = 0; tp < 4000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U);
+	prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U);
+	prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U);
+	prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U);
+	prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU);
+	prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0, count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xC] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-g-a2197-00-revA b/roms/u-boot/board/xilinx/zynqmp/zynqmp-g-a2197-00-revA
new file mode 120000
index 000000000..a64c140b8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-g-a2197-00-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-01-revA b/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-01-revA
new file mode 120000
index 000000000..a64c140b8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-01-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-02-revA b/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-02-revA
new file mode 120000
index 000000000..a64c140b8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-02-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA b/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA
new file mode 120000
index 000000000..a64c140b8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini
new file mode 120000
index 000000000..5a70cd2f5
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini
@@ -0,0 +1 @@
+zynqmp-zcu102-rev1.0
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-emmc0 b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-emmc0
new file mode 120000
index 000000000..f2beed309
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-emmc0
@@ -0,0 +1 @@
+zynqmp-zcu100-revC
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-emmc1 b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-emmc1
new file mode 120000
index 000000000..5a70cd2f5
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-emmc1
@@ -0,0 +1 @@
+zynqmp-zcu102-rev1.0
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-qspi b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-qspi
new file mode 120000
index 000000000..5a70cd2f5
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-qspi
@@ -0,0 +1 @@
+zynqmp-zcu102-rev1.0
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA b/roms/u-boot/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA
new file mode 120000
index 000000000..a64c140b8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c
new file mode 100644
index 000000000..dbed7b789
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c
@@ -0,0 +1,1038 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010602U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02013C00U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF18030C, 0x00070007U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000300U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000600U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000C02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000600U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000103U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011802U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000C00U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000202U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000402U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x008180BBU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07340301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A09U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07241008U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00331008U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E10U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000634U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x1A000000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x023FEF1EU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x02A00F1EU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x01001FFFU);
+	psu_mask_write(0xFF180144, 0x02A00F1EU, 0x02A00F1EU);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x01FFFFFFU);
+	psu_mask_write(0xFF180160, 0x01FFFFFFU, 0x01FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFF7FFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x0007FFF9U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x03FEDFBFU);
+	psu_mask_write(0xFF18017C, 0x01FFFFFFU, 0x01FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x01FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x03FFFFF4U);
+	psu_mask_write(0xFF180404, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000E807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+	psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF2000U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF0000U);
+	mask_delay(5);
+	psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF2000U);
+	psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0001U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0000U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0000U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4058F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4058FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD405990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD405924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD405928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD405900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000011U);
+	psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U);
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U);
+	psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000082U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U);
+	psu_mask_write(0xFD480094, 0x00007E00U, 0x00004A00U);
+	psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED021U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000106U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD48013C, 0x00000020U, 0x00000000U);
+	psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U);
+	psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x0000B000U, 0x00008000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0001U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+	psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD370000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD380000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD390000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3A0000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3B0000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD370014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD380014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD390014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3A0014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3B0014, 0x00000003U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+	int count = 0;
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xc] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+static void psu_init_sdio_pinmux(void)
+{
+	if (Xil_In32(0xFF0A0064U) & (1U << 19)) {
+		psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+
+		psu_mask_write(0xFF18030C, 0x00040000U, 0x00040000U);
+
+		psu_mask_write(0xFF180320, 0x33843384U, 0x02801284U);
+	} else {
+		psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	}
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	psu_init_sdio_pinmux();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c
new file mode 100644
index 000000000..b8ea291f8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c
@@ -0,0 +1,740 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x01240004U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280000U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F0E2412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x000D0419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0507070BU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502008U);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x07020408U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030909U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80AB002BU);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048A8207U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000802U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000610U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08240E08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x281C0404U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070200U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B1AU);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320E08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A0EU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000124U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AA858U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+	psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0x0000003FU, 0x00000000U);
+	psu_mask_write(0xFF180208, 0x0000000CU, 0x00000004U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0000807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40237C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40637C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD402360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD406360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40506C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD4040F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD405990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD405924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD405928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD405900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000022U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401C14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD401C40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40194C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD405C14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD405C40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40594C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD405950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000001U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+	psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD370000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD390000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3A0000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFF9B0000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD370014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD390014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3A0014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFF9B0014, 0x00000003U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	Xil_Out32(0xFD070180U, 0x00AB002BU);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 =
+		L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) | 0x20 | 0x4 |
+		((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 =
+		L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) | 0x40 | 0x8 |
+		((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	unsigned int tmp_regval;
+
+	tmp_regval = Xil_In32(0xFD690040);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690040, tmp_regval);
+
+	tmp_regval = Xil_In32(0xFD690030);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690030, tmp_regval);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c
new file mode 100644
index 000000000..520fff28f
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c
@@ -0,0 +1,462 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E60EC6CU);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013000U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000300U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000900U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010802U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000600U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000203U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000100U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00403210U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00308034U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020063U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00290000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00000E05U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x05200004U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x07080D07U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0005020BU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x03030607U);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502006U);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x13020204U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x03030202U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010003U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000303U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x02020909U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80800020U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02009896U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x04828202U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x003800D4U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x0000003DU);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F05D90U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x64032010U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x38801C20U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04061U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x040E0604U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28100004U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00040200U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00682B0AU);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00152504U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000506U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000520U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x0088E858U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFF180208, 0x0000000CU, 0x00000004U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	Xil_Out32(0xFD070180U, 0x00800020U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
new file mode 100644
index 000000000..6b0705df3
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
@@ -0,0 +1,907 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFC7FE07FU, 0x54000000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03004U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+	psu_mask_write(0xFF180320, 0x33803380U, 0x02801280U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x00000011U);
+	psu_mask_write(0xFD402860, 0x00000084U, 0x00000004U);
+	psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U);
+	psu_mask_write(0xFD402868, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x00000018U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000D3U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000DAU);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x00000096U);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x00000096U);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x00000096U);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184D1BU);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081906U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EEFU);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
new file mode 100644
index 000000000..59de4373b
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
@@ -0,0 +1,891 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0058, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0084, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B4, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000A0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000A0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xEC000C00U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0xFC000642U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000000U);
+	psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0238, 0x00000180U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD480314, 0xFFFFFFFFU, 0x00000004U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000138U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000000U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x00000172U);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000248U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000008U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x00000020U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E04U);
+	psu_mask_write(0xFD480088, 0x0000FFFFU, 0x00000100U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000060U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x00000000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000105U);
+	psu_mask_write(0xFD0E0000, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD4800AC, 0x00000F00U, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+	psu_mask_write(0xFD480094, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EEFU);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
new file mode 100644
index 000000000..59de4373b
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
@@ -0,0 +1,891 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0058, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0084, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B4, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000A0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000A0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xEC000C00U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0xFC000642U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000000U);
+	psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0238, 0x00000180U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD480314, 0xFFFFFFFFU, 0x00000004U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000138U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000000U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x00000172U);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000248U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000008U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x00000020U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E04U);
+	psu_mask_write(0xFD480088, 0x0000FFFFU, 0x00000100U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000060U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x00000000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000105U);
+	psu_mask_write(0xFD0E0000, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD4800AC, 0x00000F00U, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+	psu_mask_write(0xFD480094, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EEFU);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
new file mode 100644
index 000000000..59de4373b
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
@@ -0,0 +1,891 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0058, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0084, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B4, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000A0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000A0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xEC000C00U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0xFC000642U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000000U);
+	psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0238, 0x00000180U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD480314, 0xFFFFFFFFU, 0x00000004U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000138U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000000U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x00000172U);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000248U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000008U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x00000020U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E04U);
+	psu_mask_write(0xFD480088, 0x0000FFFFU, 0x00000100U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000060U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x00000000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000105U);
+	psu_mask_write(0xFD0E0000, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD4800AC, 0x00000F00U, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+	psu_mask_write(0xFD480094, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EEFU);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
new file mode 100644
index 000000000..e0b71abd5
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
@@ -0,0 +1,917 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E514C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00013900U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0054, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U);
+	psu_mask_write(0xFF18030C, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010402U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010302U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xAF000000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x0003F000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000240U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000E807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000020U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x00003380U, 0x00000080U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000800U);
+	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000800U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xF7FF0800U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xF7FF0000U);
+	mask_delay(5);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD402868, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD40286C, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D0CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4058F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4058FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD405990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD405924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD405928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD405900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000011U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000011U);
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U);
+	psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U);
+	psu_mask_write(0xFD480094, 0x00004200U, 0x00004200U);
+	psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000006U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD48013C, 0x00000020U, 0x00000000U);
+	psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U);
+	psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xF7FF0800U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EEFU);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
new file mode 100644
index 000000000..e01915f7e
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
@@ -0,0 +1,989 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000400U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC3081020U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000102U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x0028B090U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00404310U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00208030U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x0002020AU);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00360000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00001205U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00240012U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0E0B010CU);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00030412U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x04070F0DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00A05000U);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x05040306U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01020404U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000201U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030303U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x810B0008U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x00E32DCBU);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8206U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00A00070U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000901U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x00000015U);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F060606U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F03D28U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x85642AD0U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xA0AA0580U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A040A1U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06180C08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x2816050AU);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00080064U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00602B08U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00231008U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x0000080EU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000024U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000012U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000021U);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x810091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00030236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x00894C58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00BD0CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00BD0CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00BD0CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00BD0CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00BD0CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD090000, 0x0000FFFFU, 0x00000845U);
+	psu_mask_write(0xFD090004, 0x002DB5ADU, 0x002DB5ADU);
+	psu_mask_write(0xFD090800, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD09000C, 0x0000007FU, 0x00000010U);
+	psu_mask_write(0xFD090010, 0x0000007FU, 0x00000010U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000003U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000003U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000003U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000003U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000003U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000003U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x51000006U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B00000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x039E1FFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000FC0U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33803380U, 0x00800080U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD402860, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402868, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD40286C, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40E094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40E37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40D06C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40C0F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D0CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000033U);
+	psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+	Xil_Out32(0xFD090000U, 0x00000845U);
+	Xil_Out32(0xFD090004U, 0x003FFFFFU);
+	Xil_Out32(0xFD09000CU, 0x00000010U);
+	Xil_Out32(0xFD090010U, 0x00000010U);
+	Xil_Out32(0xFD090800U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+
+	Xil_Out32(0xFD070010U, 0x80000038U);
+	Xil_Out32(0xFD0701B0U, 0x00000005U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000331U);
+	Xil_Out32(0xFD070010U, 0x80000038U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000B36U);
+	Xil_Out32(0xFD070010U, 0x80000038U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000C21U);
+	Xil_Out32(0xFD070010U, 0x80000038U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000E19U);
+	Xil_Out32(0xFD070010U, 0x80000038U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00001616U);
+	Xil_Out32(0xFD070010U, 0x80000038U);
+	Xil_Out32(0xFD070010U, 0x80000030U);
+	Xil_Out32(0xFD0701B0U, 0x00000005U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0014FE01);
+
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x8000007E)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x010091C7U);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80008FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x810091C7U);
+	Xil_Out32(0xFD070180U, 0x010B0008U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD070020U, 0x00000001U, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x0000001FU, 0x0000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
+
+unsigned long psu_post_config_data(void)
+{
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c
new file mode 100644
index 000000000..6adbf5e23
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c
@@ -0,0 +1,966 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015900U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x80008E69U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015900U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x80008E69U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000600U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01013803U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0082808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11112412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060EU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x6F07010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02019707U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E2U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10028U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85610U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41980B06U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F09U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28210008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F09U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000830U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+	psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33800000U, 0x02800000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x5DB80000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
+	mask_delay(5);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD40CB00, 0x000000F0U, 0x000000F0U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U);
+	psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U);
+	psu_mask_write(0xFD480094, 0x00004200U, 0x00004200U);
+	psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED021U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000006U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD48013C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U);
+	psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	prog_reg(0xFD070010U, 0x00000008U, 0x00000003U, 0x00000001U);
+	prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD070010U, 0x00000030U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD070010U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD070010U, 0x0000F000U, 0x0000000CU, 0x00000006U);
+	prog_reg(0xFD070014U, 0x0003FFFFU, 0x00000000U, 0x00000819U);
+	prog_reg(0xFD070010U, 0x80000000U, 0x0000001FU, 0x00000001U);
+	while ((Xil_In32(0xFD070018) & 0x1) == 1)
+		;
+	prog_reg(0xFD070010U, 0x00000030U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD070010U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD070010U, 0x0000F000U, 0x0000000CU, 0x00000006U);
+	prog_reg(0xFD070014U, 0x0003FFFFU, 0x00000000U, 0x00000899U);
+	prog_reg(0xFD070010U, 0x80000000U, 0x0000001FU, 0x00000001U);
+	while ((Xil_In32(0xFD070018) & 0x1) == 1)
+		;
+	prog_reg(0xFD070010U, 0x00000030U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD070010U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD070010U, 0x0000F000U, 0x0000000CU, 0x00000006U);
+	prog_reg(0xFD070014U, 0x0003FFFFU, 0x00000000U, 0x00000819U);
+	prog_reg(0xFD070010U, 0x80000000U, 0x0000001FU, 0x00000001U);
+	while ((Xil_In32(0xFD070018) & 0x1) == 1)
+		;
+	prog_reg(0xFD070010U, 0x00000008U, 0x00000003U, 0x00000000U);
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EF2U);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F12302U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 8)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 8) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 8) | 0x40
+			    | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 8) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	unsigned int tmp_regval;
+
+	tmp_regval = Xil_In32(0xFD690040);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690040, tmp_regval);
+
+	tmp_regval = Xil_In32(0xFD690030);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690030, tmp_regval);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c
new file mode 100644
index 000000000..1f3f2e66b
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c
@@ -0,0 +1,1042 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014400U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015B00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010D00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010700U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010700U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02022600U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010D00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01011000U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01011000U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01011000U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01011000U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01011000U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000402U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000702U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000402U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01001002U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000702U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000402U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01011000U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011F02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01001000U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000300U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000300U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010E03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000300U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000200U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000300U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0080808AU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020103U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102311U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1107010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020192D5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000909U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000801U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FD78U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42021010U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCE401290U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06220F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01132B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x0000000CU);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000003EU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF010034, 0x000000FFU, 0x0000000CU);
+	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000003EU);
+	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x0597F128U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
+	mask_delay(5);
+	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U);
+	psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U);
+	psu_mask_write(0xFD480094, 0x00007E00U, 0x00004A00U);
+	psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED021U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000006U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD48013C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U);
+	psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x0000B000U, 0x00008000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xC] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
new file mode 100644
index 000000000..8ecd9ee90
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
@@ -0,0 +1,817 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E514C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00013900U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000820CU);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010402U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010302U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010303U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01012700U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011103U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0064, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0082808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11112412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060EU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x6F07010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02019707U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E2U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10028U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x5E001810U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x008005F0U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04121U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F09U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28220708U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00080200U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B08U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00340F09U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000830U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A2A58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080788, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0807C0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080888, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0808C0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080988, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0809C0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A88, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080AC0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B88, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080BC0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C88, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080CC0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D88, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080DC0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E88, 0xFFFFFFFFU, 0x0000000AU);
+	psu_mask_write(0xFD080EC0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F88, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080FC0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+	psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFF5E0238, 0x00100000U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33800000U, 0x00800000U);
+	psu_mask_write(0xFF18031C, 0x7F800000U, 0x63800000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0xC5ACCE55U);
+	psu_mask_write(0xFE980004, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD40CB00, 0x000000F0U, 0x000000F0U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00003FBFU, 0x00002417U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	int dpll_divisor;
+
+	dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U;
+	prog_reg(0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U);
+	prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
+	Xil_Out32(0xFD080004U, 0x00040003U);
+	while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U)
+		;
+	prog_reg(0xFD080684U, 0x06000000U, 0x00000019U, 0x00000001U);
+	prog_reg(0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U);
+	prog_reg(0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U);
+	prog_reg(0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U);
+	prog_reg(0xFD1A0080, 0x3F00, 0x8, dpll_divisor);
+	Xil_Out32(0xFD080004U, 0x40040071U);
+	while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U)
+		;
+	Xil_Out32(0xFD080004U, 0x40040001U);
+	while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U)
+		;
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EF2U);
+	Xil_Out32(0xFD08001CU, 0x55AA5498U);
+	Xil_Out32(0xFD08142CU, 0x00041830U);
+	Xil_Out32(0xFD08146CU, 0x00041830U);
+	Xil_Out32(0xFD0814ACU, 0x00041830U);
+	Xil_Out32(0xFD0814ECU, 0x00041830U);
+	Xil_Out32(0xFD08152CU, 0x00041830U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F12302U);
+	Xil_Out32(0xFD08001CU, 0x55AA5480U);
+	Xil_Out32(0xFD08142CU, 0x00041800U);
+	Xil_Out32(0xFD08146CU, 0x00041800U);
+	Xil_Out32(0xFD0814ACU, 0x00041800U);
+	Xil_Out32(0xFD0814ECU, 0x00041800U);
+	Xil_Out32(0xFD08152CU, 0x00041800U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int tmp_0_1, tmp_0_2, tmp_0_3, tmp_0_2_mod;
+
+	Xil_Out32(0xFD40EC4C, 0x00000020);
+
+	Xil_Out32(0xFD410010, 0x00000001);
+
+	maskstatus = mask_poll(0xFD40EF14, 0x2);
+
+	if (maskstatus == 0) {
+		/* xil_printf("SERDES initialization timed out\n\r"); */
+		return maskstatus;
+	}
+
+	tmp_0_1 = mask_read(0xFD400B0C, 0x3F);
+
+	tmp_0_2 = tmp_0_1 & (0x7);
+	tmp_0_3 = tmp_0_1 & (0x38);
+
+	Xil_Out32(0xFD410010, 0x00000000);
+	Xil_Out32(0xFD410014, 0x00000000);
+
+	tmp_0_2_mod = (tmp_0_2 << 1) | (0x1);
+	tmp_0_2_mod = (tmp_0_2_mod << 4);
+
+	tmp_0_3 = tmp_0_3 >> 3;
+	Xil_Out32(0xFD40EC4C, tmp_0_3);
+
+	Xil_Out32(0xFD40EC48, tmp_0_2_mod);
+	return maskstatus;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	unsigned int regvalue;
+	unsigned int tmp_regval;
+
+	Xil_Out32(((0xFF5E0000U) + 0x00000230U), 0x00000000);
+	Xil_Out32(((0xFF5E0000U) + 0x00000234U), 0x00000000);
+	Xil_Out32(((0xFF5E0000U) + 0x00000238U), 0x00000000);
+
+	regvalue = Xil_In32(((0xFF5E0000U) + 0x0000023CU));
+	regvalue &= 0x7;
+	Xil_Out32(((0xFF5E0000U) + 0x0000023CU), regvalue);
+
+	Xil_Out32(((0xFD1A0000U) + 0x00000100U), 0x00000000);
+
+	tmp_regval = Xil_In32(0xFD690040);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690040, tmp_regval);
+
+	tmp_regval = Xil_In32(0xFD690030);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690030, tmp_regval);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+
+	status &= init_serdes();
+	init_peripheral();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
new file mode 100644
index 000000000..383e3d0c7
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
@@ -0,0 +1,870 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0x7B3F007FU, 0x52240000U);
+	psu_mask_write(0xFF180208, 0xFFFFE000U, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33800000U, 0x00800000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EEFU);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revC b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revC
new file mode 120000
index 000000000..529e18f52
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revC
@@ -0,0 +1 @@
+zynqmp-zcu104-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
new file mode 100644
index 000000000..15f0be1a4
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
@@ -0,0 +1,793 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4E2C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015900U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x80008E69U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010502U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010A02U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010A02U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010A02U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0082808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11112412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060EU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x6F07010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02019707U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E2U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10028U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x5E001810U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41980B06U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F09U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28210008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F09U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000830U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+	psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFF5E0238, 0x00100000U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33800000U, 0x02800000U);
+	psu_mask_write(0xFF18031C, 0x7F800000U, 0x63800000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD40CB00, 0x000000F0U, 0x000000F0U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD405978, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD409978, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D978, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00003FFFU, 0x00002457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EF2U);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F12302U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int tmp_0_1, tmp_0_2, tmp_0_3, tmp_0_2_mod;
+
+	Xil_Out32(0xFD40EC4C, 0x00000020);
+
+	Xil_Out32(0xFD410010, 0x00000001);
+
+	maskstatus = mask_poll(0xFD40EF14, 0x2);
+
+	if (maskstatus == 0) {
+		xil_printf("SERDES initialization timed out\n\r");
+		return maskstatus;
+	}
+
+	tmp_0_1 = mask_read(0xFD400B0C, 0x3F);
+
+	tmp_0_2 = tmp_0_1 & (0x7);
+	tmp_0_3 = tmp_0_1 & (0x38);
+
+	Xil_Out32(0xFD410010, 0x00000000);
+	Xil_Out32(0xFD410014, 0x00000000);
+
+	tmp_0_2_mod = (tmp_0_2 << 1) | (0x1);
+	tmp_0_2_mod = (tmp_0_2_mod << 4);
+
+	tmp_0_3 = tmp_0_3 >> 3;
+	Xil_Out32(0xFD40EC4C, tmp_0_3);
+
+	Xil_Out32(0xFD40EC48, tmp_0_2_mod);
+	return maskstatus;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	unsigned int regvalue;
+	unsigned int tmp_regval;
+
+	Xil_Out32(((0xFF5E0000U) + 0x00000230U), 0x00000000);
+	Xil_Out32(((0xFF5E0000U) + 0x00000234U), 0x00000000);
+	Xil_Out32(((0xFF5E0000U) + 0x00000238U), 0x00000000);
+
+	regvalue = Xil_In32(((0xFF5E0000U) + 0x0000023CU));
+	regvalue &= 0x7;
+	Xil_Out32(((0xFF5E0000U) + 0x0000023CU), regvalue);
+
+	Xil_Out32(((0xFD1A0000U) + 0x00000100U), 0x00000000);
+
+	tmp_regval = Xil_In32(0xFD690040);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690040, tmp_regval);
+
+	tmp_regval = Xil_In32(0xFD690030);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690030, tmp_regval);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+
+	status &= init_serdes();
+	init_peripheral();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c
new file mode 100644
index 000000000..7c6664dc9
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c
@@ -0,0 +1,978 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00012D00U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010E03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x008180BBU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000909U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50040000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00018046U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xC] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu1275-revA b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu1275-revA
new file mode 120000
index 000000000..7abf1dc46
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu1275-revA
@@ -0,0 +1 @@
+zynqmp-zc1254-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c
new file mode 100644
index 000000000..2d93b2005
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c
@@ -0,0 +1,584 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0054, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF180308, 0x00000060U, 0x00000060U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x01240004U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280000U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x000D041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0507070BU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502008U);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x07020408U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030909U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80AB002BU);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E6U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048A8207U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000805U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000610U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05612C0U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08240E08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200404U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0200U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B1AU);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330E08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A0EU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000124U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AA858U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180204, 0x00000073U, 0x00000002U);
+	psu_mask_write(0xFF180208, 0xFFFFFF8CU, 0x00B03004U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00008044U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000140U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+	Xil_Out32(0xFD070180U, 0x00AB002BU);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c
new file mode 100644
index 000000000..f07e60abb
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c
@@ -0,0 +1,1880 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
+			   u32 lane2_protocol, u32 lane2_rate,
+			   u32 lane1_protocol, u32 lane1_rate,
+			   u32 lane0_protocol, u32 lane0_rate);
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+
+	serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+	psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+	int cur_R006_tREFPRD;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate,
+			  u32 lane2_protocol, u32 lane2_rate,
+			  u32 lane1_protocol, u32 lane1_rate,
+			  u32 lane0_protocol, u32 lane0_rate)
+{
+	Xil_Out32(0xFD410098, 0x00000000);
+	Xil_Out32(0xFD401010, 0x00000040);
+	Xil_Out32(0xFD405010, 0x00000040);
+	Xil_Out32(0xFD409010, 0x00000040);
+	Xil_Out32(0xFD40D010, 0x00000040);
+	Xil_Out32(0xFD402084, 0x00000080);
+	Xil_Out32(0xFD406084, 0x00000080);
+	Xil_Out32(0xFD40A084, 0x00000080);
+	Xil_Out32(0xFD40E084, 0x00000080);
+	Xil_Out32(0xFD410098, 0x00000004);
+	mask_delay(50);
+	if (lane0_rate == 1)
+		Xil_Out32(0xFD410098, 0x0000000E);
+	Xil_Out32(0xFD410098, 0x00000006);
+	if (lane0_rate == 1) {
+		Xil_Out32(0xFD40000C, 0x00000004);
+		Xil_Out32(0xFD40400C, 0x00000004);
+		Xil_Out32(0xFD40800C, 0x00000004);
+		Xil_Out32(0xFD40C00C, 0x00000004);
+		Xil_Out32(0xFD410098, 0x00000007);
+		mask_delay(400);
+		Xil_Out32(0xFD40000C, 0x0000000C);
+		Xil_Out32(0xFD40400C, 0x0000000C);
+		Xil_Out32(0xFD40800C, 0x0000000C);
+		Xil_Out32(0xFD40C00C, 0x0000000C);
+		mask_delay(15);
+		Xil_Out32(0xFD410098, 0x0000000F);
+		mask_delay(100);
+	}
+	if (lane0_protocol != 0)
+		mask_poll(0xFD4023E4, 0x00000010U);
+	if (lane1_protocol != 0)
+		mask_poll(0xFD4063E4, 0x00000010U);
+	if (lane2_protocol != 0)
+		mask_poll(0xFD40A3E4, 0x00000010U);
+	if (lane3_protocol != 0)
+		mask_poll(0xFD40E3E4, 0x00000010U);
+	mask_delay(50);
+	Xil_Out32(0xFD401010, 0x000000C0);
+	Xil_Out32(0xFD405010, 0x000000C0);
+	Xil_Out32(0xFD409010, 0x000000C0);
+	Xil_Out32(0xFD40D010, 0x000000C0);
+	Xil_Out32(0xFD401010, 0x00000080);
+	Xil_Out32(0xFD405010, 0x00000080);
+	Xil_Out32(0xFD409010, 0x00000080);
+	Xil_Out32(0xFD40D010, 0x00000080);
+
+	Xil_Out32(0xFD402084, 0x000000C0);
+	Xil_Out32(0xFD406084, 0x000000C0);
+	Xil_Out32(0xFD40A084, 0x000000C0);
+	Xil_Out32(0xFD40E084, 0x000000C0);
+	mask_delay(50);
+	Xil_Out32(0xFD402084, 0x00000080);
+	Xil_Out32(0xFD406084, 0x00000080);
+	Xil_Out32(0xFD40A084, 0x00000080);
+	Xil_Out32(0xFD40E084, 0x00000080);
+	mask_delay(50);
+	Xil_Out32(0xFD401010, 0x00000000);
+	Xil_Out32(0xFD405010, 0x00000000);
+	Xil_Out32(0xFD409010, 0x00000000);
+	Xil_Out32(0xFD40D010, 0x00000000);
+	Xil_Out32(0xFD402084, 0x00000000);
+	Xil_Out32(0xFD406084, 0x00000000);
+	Xil_Out32(0xFD40A084, 0x00000000);
+	Xil_Out32(0xFD40E084, 0x00000000);
+	mask_delay(500);
+	return 1;
+}
+
+static int serdes_bist_static_settings(u32 lane_active)
+{
+	if (lane_active == 0) {
+		Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD403068, 0x1);
+		Xil_Out32(0xFD40306C, 0x1);
+		Xil_Out32(0xFD4010AC, 0x0020);
+		Xil_Out32(0xFD403008, 0x0);
+		Xil_Out32(0xFD40300C, 0xF4);
+		Xil_Out32(0xFD403010, 0x0);
+		Xil_Out32(0xFD403014, 0x0);
+		Xil_Out32(0xFD403018, 0x00);
+		Xil_Out32(0xFD40301C, 0xFB);
+		Xil_Out32(0xFD403020, 0xFF);
+		Xil_Out32(0xFD403024, 0x0);
+		Xil_Out32(0xFD403028, 0x00);
+		Xil_Out32(0xFD40302C, 0x00);
+		Xil_Out32(0xFD403030, 0x4A);
+		Xil_Out32(0xFD403034, 0x4A);
+		Xil_Out32(0xFD403038, 0x4A);
+		Xil_Out32(0xFD40303C, 0x4A);
+		Xil_Out32(0xFD403040, 0x0);
+		Xil_Out32(0xFD403044, 0x14);
+		Xil_Out32(0xFD403048, 0x02);
+		Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
+	}
+	if (lane_active == 1) {
+		Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD407068, 0x1);
+		Xil_Out32(0xFD40706C, 0x1);
+		Xil_Out32(0xFD4050AC, 0x0020);
+		Xil_Out32(0xFD407008, 0x0);
+		Xil_Out32(0xFD40700C, 0xF4);
+		Xil_Out32(0xFD407010, 0x0);
+		Xil_Out32(0xFD407014, 0x0);
+		Xil_Out32(0xFD407018, 0x00);
+		Xil_Out32(0xFD40701C, 0xFB);
+		Xil_Out32(0xFD407020, 0xFF);
+		Xil_Out32(0xFD407024, 0x0);
+		Xil_Out32(0xFD407028, 0x00);
+		Xil_Out32(0xFD40702C, 0x00);
+		Xil_Out32(0xFD407030, 0x4A);
+		Xil_Out32(0xFD407034, 0x4A);
+		Xil_Out32(0xFD407038, 0x4A);
+		Xil_Out32(0xFD40703C, 0x4A);
+		Xil_Out32(0xFD407040, 0x0);
+		Xil_Out32(0xFD407044, 0x14);
+		Xil_Out32(0xFD407048, 0x02);
+		Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
+	}
+
+	if (lane_active == 2) {
+		Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD40B068, 0x1);
+		Xil_Out32(0xFD40B06C, 0x1);
+		Xil_Out32(0xFD4090AC, 0x0020);
+		Xil_Out32(0xFD40B008, 0x0);
+		Xil_Out32(0xFD40B00C, 0xF4);
+		Xil_Out32(0xFD40B010, 0x0);
+		Xil_Out32(0xFD40B014, 0x0);
+		Xil_Out32(0xFD40B018, 0x00);
+		Xil_Out32(0xFD40B01C, 0xFB);
+		Xil_Out32(0xFD40B020, 0xFF);
+		Xil_Out32(0xFD40B024, 0x0);
+		Xil_Out32(0xFD40B028, 0x00);
+		Xil_Out32(0xFD40B02C, 0x00);
+		Xil_Out32(0xFD40B030, 0x4A);
+		Xil_Out32(0xFD40B034, 0x4A);
+		Xil_Out32(0xFD40B038, 0x4A);
+		Xil_Out32(0xFD40B03C, 0x4A);
+		Xil_Out32(0xFD40B040, 0x0);
+		Xil_Out32(0xFD40B044, 0x14);
+		Xil_Out32(0xFD40B048, 0x02);
+		Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
+	}
+
+	if (lane_active == 3) {
+		Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD40F068, 0x1);
+		Xil_Out32(0xFD40F06C, 0x1);
+		Xil_Out32(0xFD40D0AC, 0x0020);
+		Xil_Out32(0xFD40F008, 0x0);
+		Xil_Out32(0xFD40F00C, 0xF4);
+		Xil_Out32(0xFD40F010, 0x0);
+		Xil_Out32(0xFD40F014, 0x0);
+		Xil_Out32(0xFD40F018, 0x00);
+		Xil_Out32(0xFD40F01C, 0xFB);
+		Xil_Out32(0xFD40F020, 0xFF);
+		Xil_Out32(0xFD40F024, 0x0);
+		Xil_Out32(0xFD40F028, 0x00);
+		Xil_Out32(0xFD40F02C, 0x00);
+		Xil_Out32(0xFD40F030, 0x4A);
+		Xil_Out32(0xFD40F034, 0x4A);
+		Xil_Out32(0xFD40F038, 0x4A);
+		Xil_Out32(0xFD40F03C, 0x4A);
+		Xil_Out32(0xFD40F040, 0x0);
+		Xil_Out32(0xFD40F044, 0x14);
+		Xil_Out32(0xFD40F048, 0x02);
+		Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
+	}
+	return 1;
+}
+
+static int serdes_bist_run(u32 lane_active)
+{
+	if (lane_active == 0) {
+		psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
+		psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
+		psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U);
+		Xil_Out32(0xFD4010AC, 0x0020);
+		Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1));
+	}
+	if (lane_active == 1) {
+		psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U);
+		psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U);
+		psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U);
+		Xil_Out32(0xFD4050AC, 0x0020);
+		Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1));
+	}
+	if (lane_active == 2) {
+		psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U);
+		psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U);
+		psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U);
+		Xil_Out32(0xFD4090AC, 0x0020);
+		Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1));
+	}
+	if (lane_active == 3) {
+		psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U);
+		psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U);
+		psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U);
+		Xil_Out32(0xFD40D0AC, 0x0020);
+		Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1));
+	}
+	mask_delay(100);
+	return 1;
+}
+
+static int serdes_bist_result(u32 lane_active)
+{
+	u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0;
+
+	if (lane_active == 0) {
+		pkt_cnt_l0 = Xil_In32(0xFD40304C);
+		pkt_cnt_h0 = Xil_In32(0xFD403050);
+		err_cnt_l0 = Xil_In32(0xFD403054);
+		err_cnt_h0 = Xil_In32(0xFD403058);
+	}
+	if (lane_active == 1) {
+		pkt_cnt_l0 = Xil_In32(0xFD40704C);
+		pkt_cnt_h0 = Xil_In32(0xFD407050);
+		err_cnt_l0 = Xil_In32(0xFD407054);
+		err_cnt_h0 = Xil_In32(0xFD407058);
+	}
+	if (lane_active == 2) {
+		pkt_cnt_l0 = Xil_In32(0xFD40B04C);
+		pkt_cnt_h0 = Xil_In32(0xFD40B050);
+		err_cnt_l0 = Xil_In32(0xFD40B054);
+		err_cnt_h0 = Xil_In32(0xFD40B058);
+	}
+	if (lane_active == 3) {
+		pkt_cnt_l0 = Xil_In32(0xFD40F04C);
+		pkt_cnt_h0 = Xil_In32(0xFD40F050);
+		err_cnt_l0 = Xil_In32(0xFD40F054);
+		err_cnt_h0 = Xil_In32(0xFD40F058);
+	}
+	if (lane_active == 0)
+		Xil_Out32(0xFD403004, 0x0);
+	if (lane_active == 1)
+		Xil_Out32(0xFD407004, 0x0);
+	if (lane_active == 2)
+		Xil_Out32(0xFD40B004, 0x0);
+	if (lane_active == 3)
+		Xil_Out32(0xFD40F004, 0x0);
+	if (err_cnt_l0 > 0 || err_cnt_h0 > 0 ||
+	    (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0))
+		return 0;
+	return 1;
+}
+
+static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate,
+				     u32 lane2_protocol, u32 lane2_rate,
+				     u32 lane1_protocol, u32 lane1_rate,
+				     u32 lane0_protocol, u32 lane0_rate,
+				     u32 gen2_calib)
+{
+	u64 tempbistresult;
+	u32 currbistresult[4];
+	u32 prevbistresult[4];
+	u32 itercount = 0;
+	u32 ill12_val[4], ill1_val[4];
+	u32 loop = 0;
+	u32 iterresult[8];
+	u32 meancount[4];
+	u32 bistpasscount[4];
+	u32 meancountalt[4];
+	u32 meancountalt_bistpasscount[4];
+	u32 lane0_active;
+	u32 lane1_active;
+	u32 lane2_active;
+	u32 lane3_active;
+
+	lane0_active = (lane0_protocol == 1);
+	lane1_active = (lane1_protocol == 1);
+	lane2_active = (lane2_protocol == 1);
+	lane3_active = (lane3_protocol == 1);
+	for (loop = 0; loop <= 3; loop++) {
+		iterresult[loop] = 0;
+		iterresult[loop + 4] = 0;
+		meancountalt[loop] = 0;
+		meancountalt_bistpasscount[loop] = 0;
+		meancount[loop] = 0;
+		prevbistresult[loop] = 0;
+		bistpasscount[loop] = 0;
+	}
+	itercount = 0;
+	if (lane0_active)
+		serdes_bist_static_settings(0);
+	if (lane1_active)
+		serdes_bist_static_settings(1);
+	if (lane2_active)
+		serdes_bist_static_settings(2);
+	if (lane3_active)
+		serdes_bist_static_settings(3);
+	do {
+		if (gen2_calib != 1) {
+			if (lane0_active == 1)
+				ill1_val[0] = ((0x04 + itercount * 8) % 0x100);
+			if (lane0_active == 1)
+				ill12_val[0] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+			if (lane1_active == 1)
+				ill1_val[1] = ((0x04 + itercount * 8) % 0x100);
+			if (lane1_active == 1)
+				ill12_val[1] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+			if (lane2_active == 1)
+				ill1_val[2] = ((0x04 + itercount * 8) % 0x100);
+			if (lane2_active == 1)
+				ill12_val[2] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+			if (lane3_active == 1)
+				ill1_val[3] = ((0x04 + itercount * 8) % 0x100);
+			if (lane3_active == 1)
+				ill12_val[3] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+
+			if (lane0_active == 1)
+				Xil_Out32(0xFD401924, ill1_val[0]);
+			if (lane0_active == 1)
+				psu_mask_write(0xFD401990, 0x000000F0U,
+					       ill12_val[0]);
+			if (lane1_active == 1)
+				Xil_Out32(0xFD405924, ill1_val[1]);
+			if (lane1_active == 1)
+				psu_mask_write(0xFD405990, 0x000000F0U,
+					       ill12_val[1]);
+			if (lane2_active == 1)
+				Xil_Out32(0xFD409924, ill1_val[2]);
+			if (lane2_active == 1)
+				psu_mask_write(0xFD409990, 0x000000F0U,
+					       ill12_val[2]);
+			if (lane3_active == 1)
+				Xil_Out32(0xFD40D924, ill1_val[3]);
+			if (lane3_active == 1)
+				psu_mask_write(0xFD40D990, 0x000000F0U,
+					       ill12_val[3]);
+		}
+		if (gen2_calib == 1) {
+			if (lane0_active == 1)
+				ill1_val[0] = ((0x104 + itercount * 8) % 0x100);
+			if (lane0_active == 1)
+				ill12_val[0] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+			if (lane1_active == 1)
+				ill1_val[1] = ((0x104 + itercount * 8) % 0x100);
+			if (lane1_active == 1)
+				ill12_val[1] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+			if (lane2_active == 1)
+				ill1_val[2] = ((0x104 + itercount * 8) % 0x100);
+			if (lane2_active == 1)
+				ill12_val[2] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+			if (lane3_active == 1)
+				ill1_val[3] = ((0x104 + itercount * 8) % 0x100);
+			if (lane3_active == 1)
+				ill12_val[3] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+
+			if (lane0_active == 1)
+				Xil_Out32(0xFD401928, ill1_val[0]);
+			if (lane0_active == 1)
+				psu_mask_write(0xFD401990, 0x0000000FU,
+					       ill12_val[0]);
+			if (lane1_active == 1)
+				Xil_Out32(0xFD405928, ill1_val[1]);
+			if (lane1_active == 1)
+				psu_mask_write(0xFD405990, 0x0000000FU,
+					       ill12_val[1]);
+			if (lane2_active == 1)
+				Xil_Out32(0xFD409928, ill1_val[2]);
+			if (lane2_active == 1)
+				psu_mask_write(0xFD409990, 0x0000000FU,
+					       ill12_val[2]);
+			if (lane3_active == 1)
+				Xil_Out32(0xFD40D928, ill1_val[3]);
+			if (lane3_active == 1)
+				psu_mask_write(0xFD40D990, 0x0000000FU,
+					       ill12_val[3]);
+		}
+
+		if (lane0_active == 1)
+			psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U);
+		if (lane1_active == 1)
+			psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U);
+		if (lane2_active == 1)
+			psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U);
+		if (lane3_active == 1)
+			psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U);
+		if (lane0_active == 1)
+			currbistresult[0] = 0;
+		if (lane1_active == 1)
+			currbistresult[1] = 0;
+		if (lane2_active == 1)
+			currbistresult[2] = 0;
+		if (lane3_active == 1)
+			currbistresult[3] = 0;
+		serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol,
+			       lane2_rate, lane1_protocol, lane1_rate,
+			       lane0_protocol, lane0_rate);
+		if (lane3_active == 1)
+			serdes_bist_run(3);
+		if (lane2_active == 1)
+			serdes_bist_run(2);
+		if (lane1_active == 1)
+			serdes_bist_run(1);
+		if (lane0_active == 1)
+			serdes_bist_run(0);
+		tempbistresult = 0;
+		if (lane3_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(3);
+		tempbistresult = tempbistresult << 1;
+		if (lane2_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(2);
+		tempbistresult = tempbistresult << 1;
+		if (lane1_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(1);
+		tempbistresult = tempbistresult << 1;
+		if (lane0_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(0);
+		Xil_Out32(0xFD410098, 0x0);
+		Xil_Out32(0xFD410098, 0x2);
+
+		if (itercount < 32) {
+			iterresult[0] =
+			    ((iterresult[0] << 1) |
+			     ((tempbistresult & 0x1) == 0x1));
+			iterresult[1] =
+			    ((iterresult[1] << 1) |
+			     ((tempbistresult & 0x2) == 0x2));
+			iterresult[2] =
+			    ((iterresult[2] << 1) |
+			     ((tempbistresult & 0x4) == 0x4));
+			iterresult[3] =
+			    ((iterresult[3] << 1) |
+			     ((tempbistresult & 0x8) == 0x8));
+		} else {
+			iterresult[4] =
+			    ((iterresult[4] << 1) |
+			     ((tempbistresult & 0x1) == 0x1));
+			iterresult[5] =
+			    ((iterresult[5] << 1) |
+			     ((tempbistresult & 0x2) == 0x2));
+			iterresult[6] =
+			    ((iterresult[6] << 1) |
+			     ((tempbistresult & 0x4) == 0x4));
+			iterresult[7] =
+			    ((iterresult[7] << 1) |
+			     ((tempbistresult & 0x8) == 0x8));
+		}
+		currbistresult[0] =
+		    currbistresult[0] | ((tempbistresult & 0x1) == 1);
+		currbistresult[1] =
+		    currbistresult[1] | ((tempbistresult & 0x2) == 0x2);
+		currbistresult[2] =
+		    currbistresult[2] | ((tempbistresult & 0x4) == 0x4);
+		currbistresult[3] =
+		    currbistresult[3] | ((tempbistresult & 0x8) == 0x8);
+
+		for (loop = 0; loop <= 3; loop++) {
+			if (currbistresult[loop] == 1 && prevbistresult[loop] == 1)
+				bistpasscount[loop] = bistpasscount[loop] + 1;
+			if (bistpasscount[loop] < 4 &&
+			    currbistresult[loop] == 0 && itercount > 2) {
+				if (meancountalt_bistpasscount[loop] <
+				    bistpasscount[loop]) {
+					meancountalt_bistpasscount[loop] =
+					    bistpasscount[loop];
+					meancountalt[loop] =
+					    ((itercount - 1) -
+					     ((bistpasscount[loop] + 1) / 2));
+				}
+				bistpasscount[loop] = 0;
+			}
+			if (meancount[loop] == 0 && bistpasscount[loop] >= 4 &&
+			    (currbistresult[loop] == 0 || itercount == 63) &&
+			    prevbistresult[loop] == 1)
+				meancount[loop] =
+				    (itercount - 1) -
+				    ((bistpasscount[loop] + 1) / 2);
+			prevbistresult[loop] = currbistresult[loop];
+		}
+	} while (++itercount < 64);
+
+	for (loop = 0; loop <= 3; loop++) {
+		if (lane0_active == 0 && loop == 0)
+			continue;
+		if (lane1_active == 0 && loop == 1)
+			continue;
+		if (lane2_active == 0 && loop == 2)
+			continue;
+		if (lane3_active == 0 && loop == 3)
+			continue;
+
+		if (meancount[loop] == 0)
+			meancount[loop] = meancountalt[loop];
+
+		if (gen2_calib != 1) {
+			ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100);
+			ill12_val[loop] =
+			    ((0x04 + meancount[loop] * 8) >=
+			     0x100) ? 0x10 : 0x00;
+			Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]);
+			Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]);
+			Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]);
+			Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]);
+		}
+		if (gen2_calib == 1) {
+			ill1_val[loop] =
+			    ((0x104 + meancount[loop] * 8) % 0x100);
+			ill12_val[loop] =
+			    ((0x104 + meancount[loop] * 8) >=
+			     0x200) ? 0x02 : 0x01;
+			Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]);
+			Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]);
+			Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]);
+			Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]);
+		}
+	}
+	if (gen2_calib != 1) {
+		if (lane0_active == 1)
+			Xil_Out32(0xFD401924, ill1_val[0]);
+		if (lane0_active == 1)
+			psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]);
+		if (lane1_active == 1)
+			Xil_Out32(0xFD405924, ill1_val[1]);
+		if (lane1_active == 1)
+			psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]);
+		if (lane2_active == 1)
+			Xil_Out32(0xFD409924, ill1_val[2]);
+		if (lane2_active == 1)
+			psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]);
+		if (lane3_active == 1)
+			Xil_Out32(0xFD40D924, ill1_val[3]);
+		if (lane3_active == 1)
+			psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]);
+	}
+	if (gen2_calib == 1) {
+		if (lane0_active == 1)
+			Xil_Out32(0xFD401928, ill1_val[0]);
+		if (lane0_active == 1)
+			psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]);
+		if (lane1_active == 1)
+			Xil_Out32(0xFD405928, ill1_val[1]);
+		if (lane1_active == 1)
+			psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]);
+		if (lane2_active == 1)
+			Xil_Out32(0xFD409928, ill1_val[2]);
+		if (lane2_active == 1)
+			psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]);
+		if (lane3_active == 1)
+			Xil_Out32(0xFD40D928, ill1_val[3]);
+		if (lane3_active == 1)
+			psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]);
+	}
+
+	if (lane0_active == 1)
+		psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U);
+	if (lane1_active == 1)
+		psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U);
+	if (lane2_active == 1)
+		psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U);
+	if (lane3_active == 1)
+		psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U);
+
+	Xil_Out32(0xFD410098, 0);
+	if (lane0_active == 1) {
+		Xil_Out32(0xFD403004, 0);
+		Xil_Out32(0xFD403008, 0);
+		Xil_Out32(0xFD40300C, 0);
+		Xil_Out32(0xFD403010, 0);
+		Xil_Out32(0xFD403014, 0);
+		Xil_Out32(0xFD403018, 0);
+		Xil_Out32(0xFD40301C, 0);
+		Xil_Out32(0xFD403020, 0);
+		Xil_Out32(0xFD403024, 0);
+		Xil_Out32(0xFD403028, 0);
+		Xil_Out32(0xFD40302C, 0);
+		Xil_Out32(0xFD403030, 0);
+		Xil_Out32(0xFD403034, 0);
+		Xil_Out32(0xFD403038, 0);
+		Xil_Out32(0xFD40303C, 0);
+		Xil_Out32(0xFD403040, 0);
+		Xil_Out32(0xFD403044, 0);
+		Xil_Out32(0xFD403048, 0);
+		Xil_Out32(0xFD40304C, 0);
+		Xil_Out32(0xFD403050, 0);
+		Xil_Out32(0xFD403054, 0);
+		Xil_Out32(0xFD403058, 0);
+		Xil_Out32(0xFD403068, 1);
+		Xil_Out32(0xFD40306C, 0);
+		Xil_Out32(0xFD4010AC, 0);
+		psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U);
+		psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U);
+		psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U);
+	}
+	if (lane1_active == 1) {
+		Xil_Out32(0xFD407004, 0);
+		Xil_Out32(0xFD407008, 0);
+		Xil_Out32(0xFD40700C, 0);
+		Xil_Out32(0xFD407010, 0);
+		Xil_Out32(0xFD407014, 0);
+		Xil_Out32(0xFD407018, 0);
+		Xil_Out32(0xFD40701C, 0);
+		Xil_Out32(0xFD407020, 0);
+		Xil_Out32(0xFD407024, 0);
+		Xil_Out32(0xFD407028, 0);
+		Xil_Out32(0xFD40702C, 0);
+		Xil_Out32(0xFD407030, 0);
+		Xil_Out32(0xFD407034, 0);
+		Xil_Out32(0xFD407038, 0);
+		Xil_Out32(0xFD40703C, 0);
+		Xil_Out32(0xFD407040, 0);
+		Xil_Out32(0xFD407044, 0);
+		Xil_Out32(0xFD407048, 0);
+		Xil_Out32(0xFD40704C, 0);
+		Xil_Out32(0xFD407050, 0);
+		Xil_Out32(0xFD407054, 0);
+		Xil_Out32(0xFD407058, 0);
+		Xil_Out32(0xFD407068, 1);
+		Xil_Out32(0xFD40706C, 0);
+		Xil_Out32(0xFD4050AC, 0);
+		psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U);
+		psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U);
+		psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U);
+	}
+	if (lane2_active == 1) {
+		Xil_Out32(0xFD40B004, 0);
+		Xil_Out32(0xFD40B008, 0);
+		Xil_Out32(0xFD40B00C, 0);
+		Xil_Out32(0xFD40B010, 0);
+		Xil_Out32(0xFD40B014, 0);
+		Xil_Out32(0xFD40B018, 0);
+		Xil_Out32(0xFD40B01C, 0);
+		Xil_Out32(0xFD40B020, 0);
+		Xil_Out32(0xFD40B024, 0);
+		Xil_Out32(0xFD40B028, 0);
+		Xil_Out32(0xFD40B02C, 0);
+		Xil_Out32(0xFD40B030, 0);
+		Xil_Out32(0xFD40B034, 0);
+		Xil_Out32(0xFD40B038, 0);
+		Xil_Out32(0xFD40B03C, 0);
+		Xil_Out32(0xFD40B040, 0);
+		Xil_Out32(0xFD40B044, 0);
+		Xil_Out32(0xFD40B048, 0);
+		Xil_Out32(0xFD40B04C, 0);
+		Xil_Out32(0xFD40B050, 0);
+		Xil_Out32(0xFD40B054, 0);
+		Xil_Out32(0xFD40B058, 0);
+		Xil_Out32(0xFD40B068, 1);
+		Xil_Out32(0xFD40B06C, 0);
+		Xil_Out32(0xFD4090AC, 0);
+		psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U);
+		psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U);
+		psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U);
+	}
+	if (lane3_active == 1) {
+		Xil_Out32(0xFD40F004, 0);
+		Xil_Out32(0xFD40F008, 0);
+		Xil_Out32(0xFD40F00C, 0);
+		Xil_Out32(0xFD40F010, 0);
+		Xil_Out32(0xFD40F014, 0);
+		Xil_Out32(0xFD40F018, 0);
+		Xil_Out32(0xFD40F01C, 0);
+		Xil_Out32(0xFD40F020, 0);
+		Xil_Out32(0xFD40F024, 0);
+		Xil_Out32(0xFD40F028, 0);
+		Xil_Out32(0xFD40F02C, 0);
+		Xil_Out32(0xFD40F030, 0);
+		Xil_Out32(0xFD40F034, 0);
+		Xil_Out32(0xFD40F038, 0);
+		Xil_Out32(0xFD40F03C, 0);
+		Xil_Out32(0xFD40F040, 0);
+		Xil_Out32(0xFD40F044, 0);
+		Xil_Out32(0xFD40F048, 0);
+		Xil_Out32(0xFD40F04C, 0);
+		Xil_Out32(0xFD40F050, 0);
+		Xil_Out32(0xFD40F054, 0);
+		Xil_Out32(0xFD40F058, 0);
+		Xil_Out32(0xFD40F068, 1);
+		Xil_Out32(0xFD40F06C, 0);
+		Xil_Out32(0xFD40D0AC, 0);
+		psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U);
+		psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U);
+		psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U);
+	}
+	return 1;
+}
+
+static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
+			   u32 lane2_protocol, u32 lane2_rate,
+			   u32 lane1_protocol, u32 lane1_rate,
+			   u32 lane0_protocol, u32 lane0_rate)
+{
+	unsigned int rdata = 0;
+	unsigned int sata_gen2 = 1;
+	unsigned int temp_ill12 = 0;
+	unsigned int temp_PLL_REF_SEL_OFFSET;
+	unsigned int temp_TM_IQ_ILL1;
+	unsigned int temp_TM_E_ILL1;
+	unsigned int temp_tx_dig_tm_61;
+	unsigned int temp_tm_dig_6;
+	unsigned int temp_pll_fbdiv_frac_3_msb_offset;
+
+	if (lane0_protocol == 2 || lane0_protocol == 1) {
+		Xil_Out32(0xFD401910, 0xF3);
+		Xil_Out32(0xFD40193C, 0xF3);
+		Xil_Out32(0xFD401914, 0xF3);
+		Xil_Out32(0xFD401940, 0xF3);
+	}
+	if (lane1_protocol == 2 || lane1_protocol == 1) {
+		Xil_Out32(0xFD405910, 0xF3);
+		Xil_Out32(0xFD40593C, 0xF3);
+		Xil_Out32(0xFD405914, 0xF3);
+		Xil_Out32(0xFD405940, 0xF3);
+	}
+	if (lane2_protocol == 2 || lane2_protocol == 1) {
+		Xil_Out32(0xFD409910, 0xF3);
+		Xil_Out32(0xFD40993C, 0xF3);
+		Xil_Out32(0xFD409914, 0xF3);
+		Xil_Out32(0xFD409940, 0xF3);
+	}
+	if (lane3_protocol == 2 || lane3_protocol == 1) {
+		Xil_Out32(0xFD40D910, 0xF3);
+		Xil_Out32(0xFD40D93C, 0xF3);
+		Xil_Out32(0xFD40D914, 0xF3);
+		Xil_Out32(0xFD40D940, 0xF3);
+	}
+
+	if (sata_gen2 == 1) {
+		if (lane0_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360);
+			Xil_Out32(0xFD402360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000);
+			psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD401924);
+			Xil_Out32(0xFD4018F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40106C);
+			psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD401990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0);
+
+			Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40106C, temp_tm_dig_6);
+			Xil_Out32(0xFD401928, Xil_In32(0xFD401924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF);
+			Xil_Out32(0xFD401990, temp_ill12);
+			Xil_Out32(0xFD401924, temp_TM_E_ILL1);
+		}
+		if (lane1_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360);
+			Xil_Out32(0xFD406360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004);
+			psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD405924);
+			Xil_Out32(0xFD4058F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40506C);
+			psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD405990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0);
+
+			Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40506C, temp_tm_dig_6);
+			Xil_Out32(0xFD405928, Xil_In32(0xFD405924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF);
+			Xil_Out32(0xFD405990, temp_ill12);
+			Xil_Out32(0xFD405924, temp_TM_E_ILL1);
+		}
+		if (lane2_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360);
+			Xil_Out32(0xFD40A360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008);
+			psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD409924);
+			Xil_Out32(0xFD4098F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40906C);
+			psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD409990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0);
+
+			Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40906C, temp_tm_dig_6);
+			Xil_Out32(0xFD409928, Xil_In32(0xFD409924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF);
+			Xil_Out32(0xFD409990, temp_ill12);
+			Xil_Out32(0xFD409924, temp_TM_E_ILL1);
+		}
+		if (lane3_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360);
+			Xil_Out32(0xFD40E360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C);
+			psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD40D924);
+			Xil_Out32(0xFD40D8F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40D06C);
+			psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD40D990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0);
+
+			Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40D06C, temp_tm_dig_6);
+			Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF);
+			Xil_Out32(0xFD40D990, temp_ill12);
+			Xil_Out32(0xFD40D924, temp_TM_E_ILL1);
+		}
+		rdata = Xil_In32(0xFD410098);
+		rdata = (rdata & 0xDF);
+		Xil_Out32(0xFD410098, rdata);
+	}
+
+	if (lane0_protocol == 2 && lane0_rate == 3) {
+		psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U);
+	}
+	if (lane1_protocol == 2 && lane1_rate == 3) {
+		psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U);
+	}
+	if (lane2_protocol == 2 && lane2_rate == 3) {
+		psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U);
+	}
+	if (lane3_protocol == 2 && lane3_rate == 3) {
+		psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U);
+	}
+
+	if (lane0_protocol == 1) {
+		if (lane0_rate == 0) {
+			serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
+						  lane2_protocol, lane2_rate,
+						  lane1_protocol, lane1_rate,
+						  lane0_protocol, 0, 0);
+		} else {
+			serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
+						  lane2_protocol, lane2_rate,
+						  lane1_protocol, lane1_rate,
+						  lane0_protocol, 0, 0);
+			serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
+						  lane2_protocol, lane2_rate,
+						  lane1_protocol, lane1_rate,
+						  lane0_protocol, lane0_rate,
+						  1);
+		}
+	}
+
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401914, 0xF3);
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401940, 0xF3);
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401990, 0x20);
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401924, 0x37);
+
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405914, 0xF3);
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405940, 0xF3);
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405990, 0x20);
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405924, 0x37);
+
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409914, 0xF3);
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409940, 0xF3);
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409990, 0x20);
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409924, 0x37);
+
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D914, 0xF3);
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D940, 0xF3);
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D990, 0x20);
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D924, 0x37);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xc] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c
new file mode 100644
index 000000000..fc3605d60
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c
@@ -0,0 +1,1882 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
+			   u32 lane2_protocol, u32 lane2_rate,
+			   u32 lane1_protocol, u32 lane1_rate,
+			   u32 lane0_protocol, u32 lane0_rate);
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+
+	serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+	psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+	int cur_R006_tREFPRD;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate,
+			  u32 lane2_protocol, u32 lane2_rate,
+			  u32 lane1_protocol, u32 lane1_rate,
+			  u32 lane0_protocol, u32 lane0_rate)
+{
+	Xil_Out32(0xFD410098, 0x00000000);
+	Xil_Out32(0xFD401010, 0x00000040);
+	Xil_Out32(0xFD405010, 0x00000040);
+	Xil_Out32(0xFD409010, 0x00000040);
+	Xil_Out32(0xFD40D010, 0x00000040);
+	Xil_Out32(0xFD402084, 0x00000080);
+	Xil_Out32(0xFD406084, 0x00000080);
+	Xil_Out32(0xFD40A084, 0x00000080);
+	Xil_Out32(0xFD40E084, 0x00000080);
+	Xil_Out32(0xFD410098, 0x00000004);
+	mask_delay(50);
+	if (lane0_rate == 1)
+		Xil_Out32(0xFD410098, 0x0000000E);
+	Xil_Out32(0xFD410098, 0x00000006);
+	if (lane0_rate == 1) {
+		Xil_Out32(0xFD40000C, 0x00000004);
+		Xil_Out32(0xFD40400C, 0x00000004);
+		Xil_Out32(0xFD40800C, 0x00000004);
+		Xil_Out32(0xFD40C00C, 0x00000004);
+		Xil_Out32(0xFD410098, 0x00000007);
+		mask_delay(400);
+		Xil_Out32(0xFD40000C, 0x0000000C);
+		Xil_Out32(0xFD40400C, 0x0000000C);
+		Xil_Out32(0xFD40800C, 0x0000000C);
+		Xil_Out32(0xFD40C00C, 0x0000000C);
+		mask_delay(15);
+		Xil_Out32(0xFD410098, 0x0000000F);
+		mask_delay(100);
+	}
+	if (lane0_protocol != 0)
+		mask_poll(0xFD4023E4, 0x00000010U);
+	if (lane1_protocol != 0)
+		mask_poll(0xFD4063E4, 0x00000010U);
+	if (lane2_protocol != 0)
+		mask_poll(0xFD40A3E4, 0x00000010U);
+	if (lane3_protocol != 0)
+		mask_poll(0xFD40E3E4, 0x00000010U);
+	mask_delay(50);
+	Xil_Out32(0xFD401010, 0x000000C0);
+	Xil_Out32(0xFD405010, 0x000000C0);
+	Xil_Out32(0xFD409010, 0x000000C0);
+	Xil_Out32(0xFD40D010, 0x000000C0);
+	Xil_Out32(0xFD401010, 0x00000080);
+	Xil_Out32(0xFD405010, 0x00000080);
+	Xil_Out32(0xFD409010, 0x00000080);
+	Xil_Out32(0xFD40D010, 0x00000080);
+
+	Xil_Out32(0xFD402084, 0x000000C0);
+	Xil_Out32(0xFD406084, 0x000000C0);
+	Xil_Out32(0xFD40A084, 0x000000C0);
+	Xil_Out32(0xFD40E084, 0x000000C0);
+	mask_delay(50);
+	Xil_Out32(0xFD402084, 0x00000080);
+	Xil_Out32(0xFD406084, 0x00000080);
+	Xil_Out32(0xFD40A084, 0x00000080);
+	Xil_Out32(0xFD40E084, 0x00000080);
+	mask_delay(50);
+	Xil_Out32(0xFD401010, 0x00000000);
+	Xil_Out32(0xFD405010, 0x00000000);
+	Xil_Out32(0xFD409010, 0x00000000);
+	Xil_Out32(0xFD40D010, 0x00000000);
+	Xil_Out32(0xFD402084, 0x00000000);
+	Xil_Out32(0xFD406084, 0x00000000);
+	Xil_Out32(0xFD40A084, 0x00000000);
+	Xil_Out32(0xFD40E084, 0x00000000);
+	mask_delay(500);
+	return 1;
+}
+
+static int serdes_bist_static_settings(u32 lane_active)
+{
+	if (lane_active == 0) {
+		Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD403068, 0x1);
+		Xil_Out32(0xFD40306C, 0x1);
+		Xil_Out32(0xFD4010AC, 0x0020);
+		Xil_Out32(0xFD403008, 0x0);
+		Xil_Out32(0xFD40300C, 0xF4);
+		Xil_Out32(0xFD403010, 0x0);
+		Xil_Out32(0xFD403014, 0x0);
+		Xil_Out32(0xFD403018, 0x00);
+		Xil_Out32(0xFD40301C, 0xFB);
+		Xil_Out32(0xFD403020, 0xFF);
+		Xil_Out32(0xFD403024, 0x0);
+		Xil_Out32(0xFD403028, 0x00);
+		Xil_Out32(0xFD40302C, 0x00);
+		Xil_Out32(0xFD403030, 0x4A);
+		Xil_Out32(0xFD403034, 0x4A);
+		Xil_Out32(0xFD403038, 0x4A);
+		Xil_Out32(0xFD40303C, 0x4A);
+		Xil_Out32(0xFD403040, 0x0);
+		Xil_Out32(0xFD403044, 0x14);
+		Xil_Out32(0xFD403048, 0x02);
+		Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
+	}
+	if (lane_active == 1) {
+		Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD407068, 0x1);
+		Xil_Out32(0xFD40706C, 0x1);
+		Xil_Out32(0xFD4050AC, 0x0020);
+		Xil_Out32(0xFD407008, 0x0);
+		Xil_Out32(0xFD40700C, 0xF4);
+		Xil_Out32(0xFD407010, 0x0);
+		Xil_Out32(0xFD407014, 0x0);
+		Xil_Out32(0xFD407018, 0x00);
+		Xil_Out32(0xFD40701C, 0xFB);
+		Xil_Out32(0xFD407020, 0xFF);
+		Xil_Out32(0xFD407024, 0x0);
+		Xil_Out32(0xFD407028, 0x00);
+		Xil_Out32(0xFD40702C, 0x00);
+		Xil_Out32(0xFD407030, 0x4A);
+		Xil_Out32(0xFD407034, 0x4A);
+		Xil_Out32(0xFD407038, 0x4A);
+		Xil_Out32(0xFD40703C, 0x4A);
+		Xil_Out32(0xFD407040, 0x0);
+		Xil_Out32(0xFD407044, 0x14);
+		Xil_Out32(0xFD407048, 0x02);
+		Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
+	}
+
+	if (lane_active == 2) {
+		Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD40B068, 0x1);
+		Xil_Out32(0xFD40B06C, 0x1);
+		Xil_Out32(0xFD4090AC, 0x0020);
+		Xil_Out32(0xFD40B008, 0x0);
+		Xil_Out32(0xFD40B00C, 0xF4);
+		Xil_Out32(0xFD40B010, 0x0);
+		Xil_Out32(0xFD40B014, 0x0);
+		Xil_Out32(0xFD40B018, 0x00);
+		Xil_Out32(0xFD40B01C, 0xFB);
+		Xil_Out32(0xFD40B020, 0xFF);
+		Xil_Out32(0xFD40B024, 0x0);
+		Xil_Out32(0xFD40B028, 0x00);
+		Xil_Out32(0xFD40B02C, 0x00);
+		Xil_Out32(0xFD40B030, 0x4A);
+		Xil_Out32(0xFD40B034, 0x4A);
+		Xil_Out32(0xFD40B038, 0x4A);
+		Xil_Out32(0xFD40B03C, 0x4A);
+		Xil_Out32(0xFD40B040, 0x0);
+		Xil_Out32(0xFD40B044, 0x14);
+		Xil_Out32(0xFD40B048, 0x02);
+		Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
+	}
+
+	if (lane_active == 3) {
+		Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD40F068, 0x1);
+		Xil_Out32(0xFD40F06C, 0x1);
+		Xil_Out32(0xFD40D0AC, 0x0020);
+		Xil_Out32(0xFD40F008, 0x0);
+		Xil_Out32(0xFD40F00C, 0xF4);
+		Xil_Out32(0xFD40F010, 0x0);
+		Xil_Out32(0xFD40F014, 0x0);
+		Xil_Out32(0xFD40F018, 0x00);
+		Xil_Out32(0xFD40F01C, 0xFB);
+		Xil_Out32(0xFD40F020, 0xFF);
+		Xil_Out32(0xFD40F024, 0x0);
+		Xil_Out32(0xFD40F028, 0x00);
+		Xil_Out32(0xFD40F02C, 0x00);
+		Xil_Out32(0xFD40F030, 0x4A);
+		Xil_Out32(0xFD40F034, 0x4A);
+		Xil_Out32(0xFD40F038, 0x4A);
+		Xil_Out32(0xFD40F03C, 0x4A);
+		Xil_Out32(0xFD40F040, 0x0);
+		Xil_Out32(0xFD40F044, 0x14);
+		Xil_Out32(0xFD40F048, 0x02);
+		Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
+	}
+	return 1;
+}
+
+static int serdes_bist_run(u32 lane_active)
+{
+	if (lane_active == 0) {
+		psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
+		psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
+		psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U);
+		Xil_Out32(0xFD4010AC, 0x0020);
+		Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1));
+	}
+	if (lane_active == 1) {
+		psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U);
+		psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U);
+		psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U);
+		Xil_Out32(0xFD4050AC, 0x0020);
+		Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1));
+	}
+	if (lane_active == 2) {
+		psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U);
+		psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U);
+		psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U);
+		Xil_Out32(0xFD4090AC, 0x0020);
+		Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1));
+	}
+	if (lane_active == 3) {
+		psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U);
+		psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U);
+		psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U);
+		Xil_Out32(0xFD40D0AC, 0x0020);
+		Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1));
+	}
+	mask_delay(100);
+	return 1;
+}
+
+static int serdes_bist_result(u32 lane_active)
+{
+	u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0;
+
+	if (lane_active == 0) {
+		pkt_cnt_l0 = Xil_In32(0xFD40304C);
+		pkt_cnt_h0 = Xil_In32(0xFD403050);
+		err_cnt_l0 = Xil_In32(0xFD403054);
+		err_cnt_h0 = Xil_In32(0xFD403058);
+	}
+	if (lane_active == 1) {
+		pkt_cnt_l0 = Xil_In32(0xFD40704C);
+		pkt_cnt_h0 = Xil_In32(0xFD407050);
+		err_cnt_l0 = Xil_In32(0xFD407054);
+		err_cnt_h0 = Xil_In32(0xFD407058);
+	}
+	if (lane_active == 2) {
+		pkt_cnt_l0 = Xil_In32(0xFD40B04C);
+		pkt_cnt_h0 = Xil_In32(0xFD40B050);
+		err_cnt_l0 = Xil_In32(0xFD40B054);
+		err_cnt_h0 = Xil_In32(0xFD40B058);
+	}
+	if (lane_active == 3) {
+		pkt_cnt_l0 = Xil_In32(0xFD40F04C);
+		pkt_cnt_h0 = Xil_In32(0xFD40F050);
+		err_cnt_l0 = Xil_In32(0xFD40F054);
+		err_cnt_h0 = Xil_In32(0xFD40F058);
+	}
+	if (lane_active == 0)
+		Xil_Out32(0xFD403004, 0x0);
+	if (lane_active == 1)
+		Xil_Out32(0xFD407004, 0x0);
+	if (lane_active == 2)
+		Xil_Out32(0xFD40B004, 0x0);
+	if (lane_active == 3)
+		Xil_Out32(0xFD40F004, 0x0);
+	if (err_cnt_l0 > 0 || err_cnt_h0 > 0 ||
+	    (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0))
+		return 0;
+	return 1;
+}
+
+static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate,
+				     u32 lane2_protocol, u32 lane2_rate,
+				     u32 lane1_protocol, u32 lane1_rate,
+				     u32 lane0_protocol, u32 lane0_rate,
+				     u32 gen2_calib)
+{
+	u64 tempbistresult;
+	u32 currbistresult[4];
+	u32 prevbistresult[4];
+	u32 itercount = 0;
+	u32 ill12_val[4], ill1_val[4];
+	u32 loop = 0;
+	u32 iterresult[8];
+	u32 meancount[4];
+	u32 bistpasscount[4];
+	u32 meancountalt[4];
+	u32 meancountalt_bistpasscount[4];
+	u32 lane0_active;
+	u32 lane1_active;
+	u32 lane2_active;
+	u32 lane3_active;
+
+	lane0_active = (lane0_protocol == 1);
+	lane1_active = (lane1_protocol == 1);
+	lane2_active = (lane2_protocol == 1);
+	lane3_active = (lane3_protocol == 1);
+	for (loop = 0; loop <= 3; loop++) {
+		iterresult[loop] = 0;
+		iterresult[loop + 4] = 0;
+		meancountalt[loop] = 0;
+		meancountalt_bistpasscount[loop] = 0;
+		meancount[loop] = 0;
+		prevbistresult[loop] = 0;
+		bistpasscount[loop] = 0;
+	}
+	itercount = 0;
+	if (lane0_active)
+		serdes_bist_static_settings(0);
+	if (lane1_active)
+		serdes_bist_static_settings(1);
+	if (lane2_active)
+		serdes_bist_static_settings(2);
+	if (lane3_active)
+		serdes_bist_static_settings(3);
+	do {
+		if (gen2_calib != 1) {
+			if (lane0_active == 1)
+				ill1_val[0] = ((0x04 + itercount * 8) % 0x100);
+			if (lane0_active == 1)
+				ill12_val[0] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+			if (lane1_active == 1)
+				ill1_val[1] = ((0x04 + itercount * 8) % 0x100);
+			if (lane1_active == 1)
+				ill12_val[1] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+			if (lane2_active == 1)
+				ill1_val[2] = ((0x04 + itercount * 8) % 0x100);
+			if (lane2_active == 1)
+				ill12_val[2] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+			if (lane3_active == 1)
+				ill1_val[3] = ((0x04 + itercount * 8) % 0x100);
+			if (lane3_active == 1)
+				ill12_val[3] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+
+			if (lane0_active == 1)
+				Xil_Out32(0xFD401924, ill1_val[0]);
+			if (lane0_active == 1)
+				psu_mask_write(0xFD401990, 0x000000F0U,
+					       ill12_val[0]);
+			if (lane1_active == 1)
+				Xil_Out32(0xFD405924, ill1_val[1]);
+			if (lane1_active == 1)
+				psu_mask_write(0xFD405990, 0x000000F0U,
+					       ill12_val[1]);
+			if (lane2_active == 1)
+				Xil_Out32(0xFD409924, ill1_val[2]);
+			if (lane2_active == 1)
+				psu_mask_write(0xFD409990, 0x000000F0U,
+					       ill12_val[2]);
+			if (lane3_active == 1)
+				Xil_Out32(0xFD40D924, ill1_val[3]);
+			if (lane3_active == 1)
+				psu_mask_write(0xFD40D990, 0x000000F0U,
+					       ill12_val[3]);
+		}
+		if (gen2_calib == 1) {
+			if (lane0_active == 1)
+				ill1_val[0] = ((0x104 + itercount * 8) % 0x100);
+			if (lane0_active == 1)
+				ill12_val[0] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+			if (lane1_active == 1)
+				ill1_val[1] = ((0x104 + itercount * 8) % 0x100);
+			if (lane1_active == 1)
+				ill12_val[1] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+			if (lane2_active == 1)
+				ill1_val[2] = ((0x104 + itercount * 8) % 0x100);
+			if (lane2_active == 1)
+				ill12_val[2] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+			if (lane3_active == 1)
+				ill1_val[3] = ((0x104 + itercount * 8) % 0x100);
+			if (lane3_active == 1)
+				ill12_val[3] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+
+			if (lane0_active == 1)
+				Xil_Out32(0xFD401928, ill1_val[0]);
+			if (lane0_active == 1)
+				psu_mask_write(0xFD401990, 0x0000000FU,
+					       ill12_val[0]);
+			if (lane1_active == 1)
+				Xil_Out32(0xFD405928, ill1_val[1]);
+			if (lane1_active == 1)
+				psu_mask_write(0xFD405990, 0x0000000FU,
+					       ill12_val[1]);
+			if (lane2_active == 1)
+				Xil_Out32(0xFD409928, ill1_val[2]);
+			if (lane2_active == 1)
+				psu_mask_write(0xFD409990, 0x0000000FU,
+					       ill12_val[2]);
+			if (lane3_active == 1)
+				Xil_Out32(0xFD40D928, ill1_val[3]);
+			if (lane3_active == 1)
+				psu_mask_write(0xFD40D990, 0x0000000FU,
+					       ill12_val[3]);
+		}
+
+		if (lane0_active == 1)
+			psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U);
+		if (lane1_active == 1)
+			psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U);
+		if (lane2_active == 1)
+			psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U);
+		if (lane3_active == 1)
+			psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U);
+		if (lane0_active == 1)
+			currbistresult[0] = 0;
+		if (lane1_active == 1)
+			currbistresult[1] = 0;
+		if (lane2_active == 1)
+			currbistresult[2] = 0;
+		if (lane3_active == 1)
+			currbistresult[3] = 0;
+		serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol,
+			       lane2_rate, lane1_protocol, lane1_rate,
+			       lane0_protocol, lane0_rate);
+		if (lane3_active == 1)
+			serdes_bist_run(3);
+		if (lane2_active == 1)
+			serdes_bist_run(2);
+		if (lane1_active == 1)
+			serdes_bist_run(1);
+		if (lane0_active == 1)
+			serdes_bist_run(0);
+		tempbistresult = 0;
+		if (lane3_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(3);
+		tempbistresult = tempbistresult << 1;
+		if (lane2_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(2);
+		tempbistresult = tempbistresult << 1;
+		if (lane1_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(1);
+		tempbistresult = tempbistresult << 1;
+		if (lane0_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(0);
+		Xil_Out32(0xFD410098, 0x0);
+		Xil_Out32(0xFD410098, 0x2);
+
+		if (itercount < 32) {
+			iterresult[0] =
+			    ((iterresult[0] << 1) |
+			     ((tempbistresult & 0x1) == 0x1));
+			iterresult[1] =
+			    ((iterresult[1] << 1) |
+			     ((tempbistresult & 0x2) == 0x2));
+			iterresult[2] =
+			    ((iterresult[2] << 1) |
+			     ((tempbistresult & 0x4) == 0x4));
+			iterresult[3] =
+			    ((iterresult[3] << 1) |
+			     ((tempbistresult & 0x8) == 0x8));
+		} else {
+			iterresult[4] =
+			    ((iterresult[4] << 1) |
+			     ((tempbistresult & 0x1) == 0x1));
+			iterresult[5] =
+			    ((iterresult[5] << 1) |
+			     ((tempbistresult & 0x2) == 0x2));
+			iterresult[6] =
+			    ((iterresult[6] << 1) |
+			     ((tempbistresult & 0x4) == 0x4));
+			iterresult[7] =
+			    ((iterresult[7] << 1) |
+			     ((tempbistresult & 0x8) == 0x8));
+		}
+		currbistresult[0] =
+		    currbistresult[0] | ((tempbistresult & 0x1) == 1);
+		currbistresult[1] =
+		    currbistresult[1] | ((tempbistresult & 0x2) == 0x2);
+		currbistresult[2] =
+		    currbistresult[2] | ((tempbistresult & 0x4) == 0x4);
+		currbistresult[3] =
+		    currbistresult[3] | ((tempbistresult & 0x8) == 0x8);
+
+		for (loop = 0; loop <= 3; loop++) {
+			if (currbistresult[loop] == 1 && prevbistresult[loop] == 1)
+				bistpasscount[loop] = bistpasscount[loop] + 1;
+			if (bistpasscount[loop] < 4 && currbistresult[loop] == 0 &&
+			    itercount > 2) {
+				if (meancountalt_bistpasscount[loop] <
+				    bistpasscount[loop]) {
+					meancountalt_bistpasscount[loop] =
+					    bistpasscount[loop];
+					meancountalt[loop] =
+					    ((itercount - 1) -
+					     ((bistpasscount[loop] + 1) / 2));
+				}
+				bistpasscount[loop] = 0;
+			}
+			if (meancount[loop] == 0 && bistpasscount[loop] >= 4 &&
+			    (currbistresult[loop] == 0 || itercount == 63) &&
+			    prevbistresult[loop] == 1)
+				meancount[loop] =
+				    (itercount - 1) -
+				    ((bistpasscount[loop] + 1) / 2);
+			prevbistresult[loop] = currbistresult[loop];
+		}
+	} while (++itercount < 64);
+
+	for (loop = 0; loop <= 3; loop++) {
+		if (lane0_active == 0 && loop == 0)
+			continue;
+		if (lane1_active == 0 && loop == 1)
+			continue;
+		if (lane2_active == 0 && loop == 2)
+			continue;
+		if (lane3_active == 0 && loop == 3)
+			continue;
+
+		if (meancount[loop] == 0)
+			meancount[loop] = meancountalt[loop];
+
+		if (gen2_calib != 1) {
+			ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100);
+			ill12_val[loop] =
+			    ((0x04 + meancount[loop] * 8) >=
+			     0x100) ? 0x10 : 0x00;
+			Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]);
+			Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]);
+			Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]);
+			Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]);
+		}
+		if (gen2_calib == 1) {
+			ill1_val[loop] =
+			    ((0x104 + meancount[loop] * 8) % 0x100);
+			ill12_val[loop] =
+			    ((0x104 + meancount[loop] * 8) >=
+			     0x200) ? 0x02 : 0x01;
+			Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]);
+			Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]);
+			Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]);
+			Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]);
+		}
+	}
+	if (gen2_calib != 1) {
+		if (lane0_active == 1)
+			Xil_Out32(0xFD401924, ill1_val[0]);
+		if (lane0_active == 1)
+			psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]);
+		if (lane1_active == 1)
+			Xil_Out32(0xFD405924, ill1_val[1]);
+		if (lane1_active == 1)
+			psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]);
+		if (lane2_active == 1)
+			Xil_Out32(0xFD409924, ill1_val[2]);
+		if (lane2_active == 1)
+			psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]);
+		if (lane3_active == 1)
+			Xil_Out32(0xFD40D924, ill1_val[3]);
+		if (lane3_active == 1)
+			psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]);
+	}
+	if (gen2_calib == 1) {
+		if (lane0_active == 1)
+			Xil_Out32(0xFD401928, ill1_val[0]);
+		if (lane0_active == 1)
+			psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]);
+		if (lane1_active == 1)
+			Xil_Out32(0xFD405928, ill1_val[1]);
+		if (lane1_active == 1)
+			psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]);
+		if (lane2_active == 1)
+			Xil_Out32(0xFD409928, ill1_val[2]);
+		if (lane2_active == 1)
+			psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]);
+		if (lane3_active == 1)
+			Xil_Out32(0xFD40D928, ill1_val[3]);
+		if (lane3_active == 1)
+			psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]);
+	}
+
+	if (lane0_active == 1)
+		psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U);
+	if (lane1_active == 1)
+		psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U);
+	if (lane2_active == 1)
+		psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U);
+	if (lane3_active == 1)
+		psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U);
+
+	Xil_Out32(0xFD410098, 0);
+	if (lane0_active == 1) {
+		Xil_Out32(0xFD403004, 0);
+		Xil_Out32(0xFD403008, 0);
+		Xil_Out32(0xFD40300C, 0);
+		Xil_Out32(0xFD403010, 0);
+		Xil_Out32(0xFD403014, 0);
+		Xil_Out32(0xFD403018, 0);
+		Xil_Out32(0xFD40301C, 0);
+		Xil_Out32(0xFD403020, 0);
+		Xil_Out32(0xFD403024, 0);
+		Xil_Out32(0xFD403028, 0);
+		Xil_Out32(0xFD40302C, 0);
+		Xil_Out32(0xFD403030, 0);
+		Xil_Out32(0xFD403034, 0);
+		Xil_Out32(0xFD403038, 0);
+		Xil_Out32(0xFD40303C, 0);
+		Xil_Out32(0xFD403040, 0);
+		Xil_Out32(0xFD403044, 0);
+		Xil_Out32(0xFD403048, 0);
+		Xil_Out32(0xFD40304C, 0);
+		Xil_Out32(0xFD403050, 0);
+		Xil_Out32(0xFD403054, 0);
+		Xil_Out32(0xFD403058, 0);
+		Xil_Out32(0xFD403068, 1);
+		Xil_Out32(0xFD40306C, 0);
+		Xil_Out32(0xFD4010AC, 0);
+		psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U);
+		psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U);
+		psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U);
+	}
+	if (lane1_active == 1) {
+		Xil_Out32(0xFD407004, 0);
+		Xil_Out32(0xFD407008, 0);
+		Xil_Out32(0xFD40700C, 0);
+		Xil_Out32(0xFD407010, 0);
+		Xil_Out32(0xFD407014, 0);
+		Xil_Out32(0xFD407018, 0);
+		Xil_Out32(0xFD40701C, 0);
+		Xil_Out32(0xFD407020, 0);
+		Xil_Out32(0xFD407024, 0);
+		Xil_Out32(0xFD407028, 0);
+		Xil_Out32(0xFD40702C, 0);
+		Xil_Out32(0xFD407030, 0);
+		Xil_Out32(0xFD407034, 0);
+		Xil_Out32(0xFD407038, 0);
+		Xil_Out32(0xFD40703C, 0);
+		Xil_Out32(0xFD407040, 0);
+		Xil_Out32(0xFD407044, 0);
+		Xil_Out32(0xFD407048, 0);
+		Xil_Out32(0xFD40704C, 0);
+		Xil_Out32(0xFD407050, 0);
+		Xil_Out32(0xFD407054, 0);
+		Xil_Out32(0xFD407058, 0);
+		Xil_Out32(0xFD407068, 1);
+		Xil_Out32(0xFD40706C, 0);
+		Xil_Out32(0xFD4050AC, 0);
+		psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U);
+		psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U);
+		psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U);
+	}
+	if (lane2_active == 1) {
+		Xil_Out32(0xFD40B004, 0);
+		Xil_Out32(0xFD40B008, 0);
+		Xil_Out32(0xFD40B00C, 0);
+		Xil_Out32(0xFD40B010, 0);
+		Xil_Out32(0xFD40B014, 0);
+		Xil_Out32(0xFD40B018, 0);
+		Xil_Out32(0xFD40B01C, 0);
+		Xil_Out32(0xFD40B020, 0);
+		Xil_Out32(0xFD40B024, 0);
+		Xil_Out32(0xFD40B028, 0);
+		Xil_Out32(0xFD40B02C, 0);
+		Xil_Out32(0xFD40B030, 0);
+		Xil_Out32(0xFD40B034, 0);
+		Xil_Out32(0xFD40B038, 0);
+		Xil_Out32(0xFD40B03C, 0);
+		Xil_Out32(0xFD40B040, 0);
+		Xil_Out32(0xFD40B044, 0);
+		Xil_Out32(0xFD40B048, 0);
+		Xil_Out32(0xFD40B04C, 0);
+		Xil_Out32(0xFD40B050, 0);
+		Xil_Out32(0xFD40B054, 0);
+		Xil_Out32(0xFD40B058, 0);
+		Xil_Out32(0xFD40B068, 1);
+		Xil_Out32(0xFD40B06C, 0);
+		Xil_Out32(0xFD4090AC, 0);
+		psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U);
+		psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U);
+		psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U);
+	}
+	if (lane3_active == 1) {
+		Xil_Out32(0xFD40F004, 0);
+		Xil_Out32(0xFD40F008, 0);
+		Xil_Out32(0xFD40F00C, 0);
+		Xil_Out32(0xFD40F010, 0);
+		Xil_Out32(0xFD40F014, 0);
+		Xil_Out32(0xFD40F018, 0);
+		Xil_Out32(0xFD40F01C, 0);
+		Xil_Out32(0xFD40F020, 0);
+		Xil_Out32(0xFD40F024, 0);
+		Xil_Out32(0xFD40F028, 0);
+		Xil_Out32(0xFD40F02C, 0);
+		Xil_Out32(0xFD40F030, 0);
+		Xil_Out32(0xFD40F034, 0);
+		Xil_Out32(0xFD40F038, 0);
+		Xil_Out32(0xFD40F03C, 0);
+		Xil_Out32(0xFD40F040, 0);
+		Xil_Out32(0xFD40F044, 0);
+		Xil_Out32(0xFD40F048, 0);
+		Xil_Out32(0xFD40F04C, 0);
+		Xil_Out32(0xFD40F050, 0);
+		Xil_Out32(0xFD40F054, 0);
+		Xil_Out32(0xFD40F058, 0);
+		Xil_Out32(0xFD40F068, 1);
+		Xil_Out32(0xFD40F06C, 0);
+		Xil_Out32(0xFD40D0AC, 0);
+		psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U);
+		psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U);
+		psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U);
+	}
+	return 1;
+}
+
+static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
+			   u32 lane2_protocol, u32 lane2_rate,
+			   u32 lane1_protocol, u32 lane1_rate,
+			   u32 lane0_protocol, u32 lane0_rate)
+{
+	unsigned int rdata = 0;
+	unsigned int sata_gen2 = 1;
+	unsigned int temp_ill12 = 0;
+	unsigned int temp_PLL_REF_SEL_OFFSET;
+	unsigned int temp_TM_IQ_ILL1;
+	unsigned int temp_TM_E_ILL1;
+	unsigned int temp_tx_dig_tm_61;
+	unsigned int temp_tm_dig_6;
+	unsigned int temp_pll_fbdiv_frac_3_msb_offset;
+
+	if (lane0_protocol == 2 || lane0_protocol == 1) {
+		Xil_Out32(0xFD401910, 0xF3);
+		Xil_Out32(0xFD40193C, 0xF3);
+		Xil_Out32(0xFD401914, 0xF3);
+		Xil_Out32(0xFD401940, 0xF3);
+	}
+	if (lane1_protocol == 2 || lane1_protocol == 1) {
+		Xil_Out32(0xFD405910, 0xF3);
+		Xil_Out32(0xFD40593C, 0xF3);
+		Xil_Out32(0xFD405914, 0xF3);
+		Xil_Out32(0xFD405940, 0xF3);
+	}
+	if (lane2_protocol == 2 || lane2_protocol == 1) {
+		Xil_Out32(0xFD409910, 0xF3);
+		Xil_Out32(0xFD40993C, 0xF3);
+		Xil_Out32(0xFD409914, 0xF3);
+		Xil_Out32(0xFD409940, 0xF3);
+	}
+	if (lane3_protocol == 2 || lane3_protocol == 1) {
+		Xil_Out32(0xFD40D910, 0xF3);
+		Xil_Out32(0xFD40D93C, 0xF3);
+		Xil_Out32(0xFD40D914, 0xF3);
+		Xil_Out32(0xFD40D940, 0xF3);
+	}
+
+	if (sata_gen2 == 1) {
+		if (lane0_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360);
+			Xil_Out32(0xFD402360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000);
+			psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD401924);
+			Xil_Out32(0xFD4018F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40106C);
+			psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD401990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0);
+
+			Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40106C, temp_tm_dig_6);
+			Xil_Out32(0xFD401928, Xil_In32(0xFD401924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF);
+			Xil_Out32(0xFD401990, temp_ill12);
+			Xil_Out32(0xFD401924, temp_TM_E_ILL1);
+		}
+		if (lane1_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360);
+			Xil_Out32(0xFD406360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004);
+			psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD405924);
+			Xil_Out32(0xFD4058F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40506C);
+			psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD405990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0);
+
+			Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40506C, temp_tm_dig_6);
+			Xil_Out32(0xFD405928, Xil_In32(0xFD405924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF);
+			Xil_Out32(0xFD405990, temp_ill12);
+			Xil_Out32(0xFD405924, temp_TM_E_ILL1);
+		}
+		if (lane2_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360);
+			Xil_Out32(0xFD40A360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008);
+			psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD409924);
+			Xil_Out32(0xFD4098F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40906C);
+			psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD409990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0);
+
+			Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40906C, temp_tm_dig_6);
+			Xil_Out32(0xFD409928, Xil_In32(0xFD409924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF);
+			Xil_Out32(0xFD409990, temp_ill12);
+			Xil_Out32(0xFD409924, temp_TM_E_ILL1);
+		}
+		if (lane3_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360);
+			Xil_Out32(0xFD40E360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C);
+			psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD40D924);
+			Xil_Out32(0xFD40D8F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40D06C);
+			psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD40D990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0);
+
+			Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40D06C, temp_tm_dig_6);
+			Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF);
+			Xil_Out32(0xFD40D990, temp_ill12);
+			Xil_Out32(0xFD40D924, temp_TM_E_ILL1);
+		}
+		rdata = Xil_In32(0xFD410098);
+		rdata = (rdata & 0xDF);
+		Xil_Out32(0xFD410098, rdata);
+	}
+
+	if (lane0_protocol == 2 && lane0_rate == 3) {
+		psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U);
+	}
+	if (lane1_protocol == 2 && lane1_rate == 3) {
+		psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U);
+	}
+	if (lane2_protocol == 2 && lane2_rate == 3) {
+		psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U);
+	}
+	if (lane3_protocol == 2 && lane3_rate == 3) {
+		psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U);
+	}
+
+	if (lane0_protocol == 1) {
+		if (lane0_rate == 0) {
+			serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
+						  lane2_protocol, lane2_rate,
+						  lane1_protocol, lane1_rate,
+						  lane0_protocol, 0, 0);
+		} else {
+			serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
+						  lane2_protocol, lane2_rate,
+						  lane1_protocol, lane1_rate,
+						  lane0_protocol, 0, 0);
+			serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
+						  lane2_protocol, lane2_rate,
+						  lane1_protocol, lane1_rate,
+						  lane0_protocol, lane0_rate,
+						  1);
+		}
+	}
+
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401914, 0xF3);
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401940, 0xF3);
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401990, 0x20);
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401924, 0x37);
+
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405914, 0xF3);
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405940, 0xF3);
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405990, 0x20);
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405924, 0x37);
+
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409914, 0xF3);
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409940, 0xF3);
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409990, 0x20);
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409924, 0x37);
+
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D914, 0xF3);
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D940, 0xF3);
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D990, 0x20);
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D924, 0x37);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xc] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp.c
new file mode 100644
index 000000000..ee4d0c85e
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp.c
@@ -0,0 +1,729 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <debug_uart.h>
+#include <env.h>
+#include <env_internal.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <sata.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <malloc.h>
+#include <wdt.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/psu_init_gpl.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/ptrace.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+#include <zynqmppl.h>
+#include <zynqmp_firmware.h>
+#include <g_dnl.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include "../common/board.h"
+
+#include "pm_cfg_obj.h"
+
+#define ZYNQMP_VERSION_SIZE	7
+#define EFUSE_VCU_DIS_MASK	0x100
+#define EFUSE_VCU_DIS_SHIFT	8
+#define EFUSE_GPU_DIS_MASK	0x20
+#define EFUSE_GPU_DIS_SHIFT	5
+#define IDCODE2_PL_INIT_MASK	0x200
+#define IDCODE2_PL_INIT_SHIFT	9
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
+static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
+
+enum {
+	ZYNQMP_VARIANT_EG = BIT(0U),
+	ZYNQMP_VARIANT_EV = BIT(1U),
+	ZYNQMP_VARIANT_CG = BIT(2U),
+	ZYNQMP_VARIANT_DR = BIT(3U),
+};
+
+static const struct {
+	u32 id;
+	u8 device;
+	u8 variants;
+} zynqmp_devices[] = {
+	{
+		.id = 0x04711093,
+		.device = 2,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+	},
+	{
+		.id = 0x04710093,
+		.device = 3,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+	},
+	{
+		.id = 0x04721093,
+		.device = 4,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
+	},
+	{
+		.id = 0x04720093,
+		.device = 5,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
+	},
+	{
+		.id = 0x04739093,
+		.device = 6,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+	},
+	{
+		.id = 0x04730093,
+		.device = 7,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
+	},
+	{
+		.id = 0x04738093,
+		.device = 9,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+	},
+	{
+		.id = 0x04740093,
+		.device = 11,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x04750093,
+		.device = 15,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x04759093,
+		.device = 17,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x04758093,
+		.device = 19,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x047E1093,
+		.device = 21,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E3093,
+		.device = 23,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E5093,
+		.device = 25,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E4093,
+		.device = 27,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E0093,
+		.device = 28,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E2093,
+		.device = 29,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E6093,
+		.device = 39,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047FD093,
+		.device = 43,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047F8093,
+		.device = 46,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047FF093,
+		.device = 47,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047FB093,
+		.device = 48,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047FE093,
+		.device = 49,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+};
+
+static char *zynqmp_get_silicon_idcode_name(void)
+{
+	u32 i;
+	u32 idcode, idcode2;
+	char name[ZYNQMP_VERSION_SIZE];
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
+	if (ret) {
+		debug("%s: Getting chipid failed\n", __func__);
+		return "unknown";
+	}
+
+	/*
+	 * Firmware returns:
+	 * payload[0][31:0]  = status of the operation
+	 * payload[1]] = IDCODE
+	 * payload[2][19:0]  = Version
+	 * payload[2][28:20] = EXTENDED_IDCODE
+	 * payload[2][29] = PL_INIT
+	 */
+
+	idcode  = ret_payload[1];
+	idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
+	debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
+	      idcode2);
+
+	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
+		if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
+			break;
+	}
+
+	if (i >= ARRAY_SIZE(zynqmp_devices))
+		return "unknown";
+
+	/* Add device prefix to the name */
+	ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
+		       zynqmp_devices[i].device);
+	if (ret < 0)
+		return "unknown";
+
+	if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
+		/* Devices with EV variant might be EG/CG/EV family */
+		if (idcode2 & IDCODE2_PL_INIT_MASK) {
+			u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
+				      EFUSE_VCU_DIS_SHIFT) << 1 |
+				     ((idcode2 & EFUSE_GPU_DIS_MASK) >>
+				      EFUSE_GPU_DIS_SHIFT);
+
+			/*
+			 * Get family name based on extended idcode values as
+			 * determined on UG1087, EXTENDED_IDCODE register
+			 * description
+			 */
+			switch (family) {
+			case 0x00:
+				strncat(name, "ev", 2);
+				break;
+			case 0x10:
+				strncat(name, "eg", 2);
+				break;
+			case 0x11:
+				strncat(name, "cg", 2);
+				break;
+			default:
+				/* Do not append family name*/
+				break;
+			}
+		} else {
+			/*
+			 * When PL powered down the VCU Disable efuse cannot be
+			 * read. So, ignore the bit and just findout if it is CG
+			 * or EG/EV variant.
+			 */
+			strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
+				"e", 2);
+		}
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
+		/* Devices with CG variant might be EG or CG family */
+		strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
+		strncat(name, "eg", 2);
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
+		strncat(name, "dr", 2);
+	} else {
+		debug("Variant not identified\n");
+	}
+
+	return strdup(name);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
+	int ret;
+
+	ret = psu_init();
+	if (ret)
+		return ret;
+
+	/*
+	 * PS_SYSMON_ANALOG_BUS register determines mapping between SysMon
+	 * supply sense channel to SysMon supply registers inside the IP.
+	 * This register must be programmed to complete SysMon IP
+	 * configuration. The default register configuration after
+	 * power-up is incorrect. Hence, fix this by writing the
+	 * correct value - 0x3210.
+	 */
+	writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
+	       ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
+
+	/* Delay is required for clocks to be propagated */
+	udelay(1000000);
+#endif
+
+#ifdef CONFIG_DEBUG_UART
+	/* Uart debug for sure */
+	debug_uart_init();
+	puts("Debug uart enabled\n"); /* or printch() */
+#endif
+
+	return 0;
+}
+
+static int multi_boot(void)
+{
+	u32 multiboot;
+
+	multiboot = readl(&csu_base->multi_boot);
+
+	printf("Multiboot:\t%d\n", multiboot);
+
+	return 0;
+}
+
+#define PS_SYSMON_ANALOG_BUS_VAL	0x3210
+#define PS_SYSMON_ANALOG_BUS_REG	0xFFA50914
+
+int board_init(void)
+{
+#if defined(CONFIG_ZYNQMP_FIRMWARE)
+	struct udevice *dev;
+
+	uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
+	if (!dev)
+		panic("PMU Firmware device not found - Enable it");
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+	/* Check *at build time* if the filename is an non-empty string */
+	if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
+		zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
+						zynqmp_pm_cfg_obj_size);
+	printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
+#else
+	if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
+		xilinx_read_eeprom();
+#endif
+
+	printf("EL Level:\tEL%d\n", current_el());
+
+	/* Bug in ROM sets wrong value in this register */
+	writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
+
+#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
+	zynqmppl.name = zynqmp_get_silicon_idcode_name();
+	printf("Chip ID:\t%s\n", zynqmppl.name);
+	fpga_init();
+	fpga_add(fpga_xilinx, &zynqmppl);
+#endif
+
+	if (current_el() == 3)
+		multi_boot();
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	u32 val;
+
+	if (current_el() != 3)
+		return 0;
+
+	val = readl(&crlapb_base->timestamp_ref_ctrl);
+	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+
+	if (!val) {
+		val = readl(&crlapb_base->timestamp_ref_ctrl);
+		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+		writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+		/* Program freq register in System counter */
+		writel(zynqmp_get_system_timer_freq(),
+		       &iou_scntr_secure->base_frequency_id_register);
+		/* And enable system counter */
+		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
+		       &iou_scntr_secure->counter_control_register);
+	}
+	return 0;
+}
+
+unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
+			 char *const argv[])
+{
+	int ret = 0;
+
+	if (current_el() > 1) {
+		smp_kick_all_cpus();
+		dcache_disable();
+		armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
+				    ES_TO_AARCH64);
+	} else {
+		printf("FAIL: current EL is not above EL1\n");
+		ret = EINVAL;
+	}
+	return ret;
+}
+
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+int dram_init_banksize(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_memory_banksize();
+	if (ret)
+		return ret;
+
+	mem_map_fill();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+#else
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = get_effective_memsize();
+
+	mem_map_fill();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
+#endif
+
+void reset_cpu(void)
+{
+}
+
+static u8 __maybe_unused zynqmp_get_bootmode(void)
+{
+	u8 bootmode;
+	u32 reg = 0;
+	int ret;
+
+	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
+	if (ret)
+		return -EINVAL;
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
+#if defined(CONFIG_BOARD_LATE_INIT)
+static const struct {
+	u32 bit;
+	const char *name;
+} reset_reasons[] = {
+	{ RESET_REASON_DEBUG_SYS, "DEBUG" },
+	{ RESET_REASON_SOFT, "SOFT" },
+	{ RESET_REASON_SRST, "SRST" },
+	{ RESET_REASON_PSONLY, "PS-ONLY" },
+	{ RESET_REASON_PMU, "PMU" },
+	{ RESET_REASON_INTERNAL, "INTERNAL" },
+	{ RESET_REASON_EXTERNAL, "EXTERNAL" },
+	{}
+};
+
+static int reset_reason(void)
+{
+	u32 reg;
+	int i, ret;
+	const char *reason = NULL;
+
+	ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
+	if (ret)
+		return -EINVAL;
+
+	puts("Reset reason:\t");
+
+	for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
+		if (reg & reset_reasons[i].bit) {
+			reason = reset_reasons[i].name;
+			printf("%s ", reset_reasons[i].name);
+			break;
+		}
+	}
+
+	puts("\n");
+
+	env_set("reset_reason", reason);
+
+	return 0;
+}
+
+static int set_fdtfile(void)
+{
+	char *compatible, *fdtfile;
+	const char *suffix = ".dtb";
+	const char *vendor = "xilinx/";
+	int fdt_compat_len;
+
+	if (env_get("fdtfile"))
+		return 0;
+
+	compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
+					 &fdt_compat_len);
+	if (compatible && fdt_compat_len) {
+		char *name;
+
+		debug("Compatible: %s\n", compatible);
+
+		name = strchr(compatible, ',');
+		if (!name)
+			return -EINVAL;
+
+		name++;
+
+		fdtfile = calloc(1, strlen(vendor) + strlen(name) +
+				 strlen(suffix) + 1);
+		if (!fdtfile)
+			return -ENOMEM;
+
+		sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
+
+		env_set("fdtfile", fdtfile);
+		free(fdtfile);
+	}
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	u8 bootmode;
+	struct udevice *dev;
+	int bootseq = -1;
+	int bootseq_len = 0;
+	int env_targets_len = 0;
+	const char *mode;
+	char *new_targets;
+	char *env_targets;
+	int ret;
+
+#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
+	usb_ether_init();
+#endif
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
+
+	if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
+		return 0;
+
+	ret = set_fdtfile();
+	if (ret)
+		return ret;
+
+	bootmode = zynqmp_get_bootmode();
+
+	puts("Bootmode: ");
+	switch (bootmode) {
+	case USB_MODE:
+		puts("USB_MODE\n");
+		mode = "usb_dfu0 usb_dfu1";
+		env_set("modeboot", "usb_dfu_spl");
+		break;
+	case JTAG_MODE:
+		puts("JTAG_MODE\n");
+		mode = "jtag pxe dhcp";
+		env_set("modeboot", "jtagboot");
+		break;
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		mode = "qspi0";
+		puts("QSPI_MODE\n");
+		env_set("modeboot", "qspiboot");
+		break;
+	case EMMC_MODE:
+		puts("EMMC_MODE\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "mmc@ff160000", &dev) &&
+		    uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@ff160000", &dev)) {
+			puts("Boot from EMMC but without SD0 enabled!\n");
+			return -1;
+		}
+		debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		break;
+	case SD_MODE:
+		puts("SD_MODE\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "mmc@ff160000", &dev) &&
+		    uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@ff160000", &dev)) {
+			puts("Boot from SD0 but without SD0 enabled!\n");
+			return -1;
+		}
+		debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		env_set("modeboot", "sdboot");
+		break;
+	case SD1_LSHFT_MODE:
+		puts("LVL_SHFT_");
+		/* fall through */
+	case SD_MODE1:
+		puts("SD_MODE1\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "mmc@ff170000", &dev) &&
+		    uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@ff170000", &dev)) {
+			puts("Boot from SD1 but without SD1 enabled!\n");
+			return -1;
+		}
+		debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		env_set("modeboot", "sdboot");
+		break;
+	case NAND_MODE:
+		puts("NAND_MODE\n");
+		mode = "nand0";
+		env_set("modeboot", "nandboot");
+		break;
+	default:
+		mode = "";
+		printf("Invalid Boot Mode:0x%x\n", bootmode);
+		break;
+	}
+
+	if (bootseq >= 0) {
+		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
+		debug("Bootseq len: %x\n", bootseq_len);
+		env_set_hex("bootseq", bootseq);
+	}
+
+	/*
+	 * One terminating char + one byte for space between mode
+	 * and default boot_targets
+	 */
+	env_targets = env_get("boot_targets");
+	if (env_targets)
+		env_targets_len = strlen(env_targets);
+
+	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
+			     bootseq_len);
+	if (!new_targets)
+		return -ENOMEM;
+
+	if (bootseq >= 0)
+		sprintf(new_targets, "%s%x %s", mode, bootseq,
+			env_targets ? env_targets : "");
+	else
+		sprintf(new_targets, "%s %s", mode,
+			env_targets ? env_targets : "");
+
+	env_set("boot_targets", new_targets);
+
+	reset_reason();
+
+	return board_late_init_xilinx();
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: Xilinx ZynqMP\n");
+	return 0;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	u32 bootmode = zynqmp_get_bootmode();
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	switch (bootmode) {
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD1_LSHFT_MODE:
+	case SD_MODE1:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+			return ENVL_FAT;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+			return ENVL_EXT4;
+		return ENVL_UNKNOWN;
+	case NAND_MODE:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
+			return ENVL_NAND;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
+			return ENVL_UBI;
+		return ENVL_UNKNOWN;
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		return ENVL_UNKNOWN;
+	case JTAG_MODE:
+	default:
+		return ENVL_NOWHERE;
+	}
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp_r5/MAINTAINERS b/roms/u-boot/board/xilinx/zynqmp_r5/MAINTAINERS
new file mode 100644
index 000000000..ac2676497
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp_r5/MAINTAINERS
@@ -0,0 +1,7 @@
+XILINX_ZYNQMP_R5 BOARDS
+M:	Michal Simek <michal.simek@xilinx.com>
+S:	Maintained
+F:	arch/arm/dts/zynqmp-r5*
+F:	board/xilinx/zynqmp_r5/
+F:	include/configs/xilinx_zynqmp_r5_*
+F:	configs/xilinx_zynqmp_r5_*
diff --git a/roms/u-boot/board/xilinx/zynqmp_r5/Makefile b/roms/u-boot/board/xilinx/zynqmp_r5/Makefile
new file mode 100644
index 000000000..c5a3e3d32
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp_r5/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
+#
+
+obj-y	:= board.o
diff --git a/roms/u-boot/board/xilinx/zynqmp_r5/board.c b/roms/u-boot/board/xilinx/zynqmp_r5/board.c
new file mode 100644
index 000000000..5c5a2e938
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp_r5/board.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/zyxel/nsa310s/Kconfig b/roms/u-boot/board/zyxel/nsa310s/Kconfig
new file mode 100644
index 000000000..801d6966e
--- /dev/null
+++ b/roms/u-boot/board/zyxel/nsa310s/Kconfig
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+
+if TARGET_NSA310S
+
+config SYS_BOARD
+	default "nsa310s"
+
+config SYS_VENDOR
+	default "zyxel"
+
+config SYS_CONFIG_NAME
+	default "nsa310s"
+
+endif
diff --git a/roms/u-boot/board/zyxel/nsa310s/MAINTAINERS b/roms/u-boot/board/zyxel/nsa310s/MAINTAINERS
new file mode 100644
index 000000000..d153758c2
--- /dev/null
+++ b/roms/u-boot/board/zyxel/nsa310s/MAINTAINERS
@@ -0,0 +1,8 @@
+NSA310S BOARD
+M:	Gerald Kerma <dreagle@doukki.net>
+M:	Tony Dinh <mibodhi@gmail.com>
+M:	Luka Perkov <luka.perkov@sartura.hr>
+S:	Maintained
+F:	board/zyxel/nsa310s/
+F:	include/configs/nsa310s.h
+F:	configs/nsa310s_defconfig
diff --git a/roms/u-boot/board/zyxel/nsa310s/Makefile b/roms/u-boot/board/zyxel/nsa310s/Makefile
new file mode 100644
index 000000000..2131e28db
--- /dev/null
+++ b/roms/u-boot/board/zyxel/nsa310s/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+
+obj-y	:= nsa310s.o
diff --git a/roms/u-boot/board/zyxel/nsa310s/kwbimage.cfg b/roms/u-boot/board/zyxel/nsa310s/kwbimage.cfg
new file mode 100644
index 000000000..9ebdeab94
--- /dev/null
+++ b/roms/u-boot/board/zyxel/nsa310s/kwbimage.cfg
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+# Refer to doc/README.kwbimage for more details about how-to
+# configure and create kirkwood boot images.
+#
+
+# Boot Media configurations
+BOOT_FROM       nand
+NAND_ECC_MODE   default
+NAND_PAGE_SIZE  0x0800
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+DATA 0xFFD01400 0x43010c30
+DATA 0xFFD01404 0x39543000
+DATA 0xFFD01408 0x22125451
+DATA 0xFFD0140C 0x00000833
+DATA 0xFFD01410 0x0000000C
+DATA 0xFFD01414 0x00000000
+DATA 0xFFD01418 0x00000000
+DATA 0xFFD0141C 0x00000652
+DATA 0xFFD01420 0x00000004
+DATA 0xFFD01424 0x0000F17F
+DATA 0xFFD01428 0x00085520
+DATA 0xFFD0147c 0x00008552
+DATA 0xFFD01504 0x0FFFFFF1
+DATA 0xFFD01508 0x10000000
+DATA 0xFFD0150C 0x00000000
+DATA 0xFFD01514 0x00000000
+DATA 0xFFD0151C 0x00000000
+DATA 0xFFD01494 0x00010000
+DATA 0xFFD01498 0x00000000
+DATA 0xFFD0149C 0x0000E403
+DATA 0xFFD01480 0x00000001
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x66666666
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/zyxel/nsa310s/nsa310s.c b/roms/u-boot/board/zyxel/nsa310s/nsa310s.c
new file mode 100644
index 000000000..cd4a7723b
--- /dev/null
+++ b/roms/u-boot/board/zyxel/nsa310s/nsa310s.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include "nsa310s.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
+			  NSA310S_OE_LOW, NSA310S_OE_HIGH);
+
+	/* (all LEDs & power off active high) */
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_GPO,
+		MPP13_GPIO,
+		MPP14_GPIO,
+		MPP15_GPIO,
+		MPP16_GPIO,
+		MPP17_GPIO,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GPIO,
+		MPP21_GPIO,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+	u16 reg;
+	u16 phyaddr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* read PHY dev address */
+	if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
+		printf("could not read PHY dev address\n");
+		return;
+	}
+
+	/* set RGMII delay */
+	miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
+	miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
+	miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
+	miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
+
+	/* reset PHY */
+	if (miiphy_reset(name, phyaddr))
+		return;
+
+	/*
+	 * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
+	 * and has an MCU attached to the LED[2] via tristate interrupt
+	 */
+
+	/* switch to LED register page */
+	miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
+	/* read out LED polarity register */
+	miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, &reg);
+	/* clear 4, set 5 - LED2 low, tri-state */
+	reg &= ~(MV88E1318_LED2_4);
+	reg |= (MV88E1318_LED2_5);
+	/* write back LED polarity register */
+	miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
+	/* jump back to page 0, per the PHY chip documenation. */
+	miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
+
+	/* set PHY back to auto-negotiation mode */
+	miiphy_write(name, phyaddr, 0x4, 0x1e1);
+	miiphy_write(name, phyaddr, 0x9, 0x300);
+	/* downshift */
+	miiphy_write(name, phyaddr, 0x10, 0x3860);
+	miiphy_write(name, phyaddr, 0x0, 0x9140);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/roms/u-boot/board/zyxel/nsa310s/nsa310s.h b/roms/u-boot/board/zyxel/nsa310s/nsa310s.h
new file mode 100644
index 000000000..d8bd9a586
--- /dev/null
+++ b/roms/u-boot/board/zyxel/nsa310s/nsa310s.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ */
+
+#ifndef __NSA310S_H
+#define __NSA310S_H
+
+/* low GPIO's */
+#define HDD1_GREEN_LED		(1 << 16)
+#define HDD1_RED_LED		(1 << 13)
+#define USB_GREEN_LED		(1 << 15)
+#define USB_POWER			(1 << 21)
+#define SYS_GREEN_LED		(1 << 28)
+#define SYS_ORANGE_LED		(1 << 29)
+
+#define COPY_GREEN_LED		(1 << 22)
+#define COPY_RED_LED		(1 << 23)
+
+#define PIN_USB_GREEN_LED	15
+#define PIN_USB_POWER		21
+
+#define NSA310S_OE_LOW		(~(0))
+#define NSA310S_VAL_LOW		(SYS_GREEN_LED | USB_POWER)
+
+/* high GPIO's */
+#define HDD2_GREEN_LED		(1 << 2)
+#define HDD2_POWER			(1 << 1)
+
+#define NSA310S_OE_HIGH		(~(0))
+#define NSA310S_VAL_HIGH	(HDD2_POWER)
+
+/* PHY related */
+#define MV88E1318_PGADR_REG		22
+#define MV88E1318_MAC_CTRL_PG	2
+#define MV88E1318_MAC_CTRL_REG	21
+#define MV88E1318_RGMII_TX_CTRL	(1 << 4)
+#define MV88E1318_RGMII_RX_CTRL	(1 << 5)
+#define MV88E1318_LED_PG		3
+#define MV88E1318_LED_POL_REG	17
+#define MV88E1318_LED2_4		(1 << 4)
+#define MV88E1318_LED2_5		(1 << 5)
+
+#endif /* __NSA310S_H */